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* Merge branch 'core-locking-for-linus' of ↵Linus Torvalds2010-05-182-8/+8
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'core-locking-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: lockdep: Reduce stack_trace usage lockdep: No need to disable preemption in debug atomic ops lockdep: Actually _dec_ in debug_atomic_dec lockdep: Provide off case for redundant_hardirqs_on increment lockdep: Simplify debug atomic ops lockdep: Fix redundant_hardirqs_on incremented with irqs enabled lockstat: Make lockstat counting per cpu i8253: Convert i8253_lock to raw_spinlock
| * Merge commit 'v2.6.34-rc6' into core/lockingIngo Molnar2010-05-0382-836/+1072
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| * | i8253: Convert i8253_lock to raw_spinlockThomas Gleixner2010-03-022-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i8253_lock needs to be a real spinlock in preempt-rt, i.e. it can not be converted to a sleeping lock. Convert it to raw_spinlock and fix up all users. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Acked-by: Takashi Iwai <tiwai@suse.de> Cc: Jens Axboe <jens.axboe@oracle.com> LKML-Reference: <20100217163751.030764372@linutronix.de>
* | | atomic_t: Cast to volatile when accessing atomic variablesAnton Blanchard2010-05-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | In preparation for removing volatile from the atomic_t definition, this patch adds a volatile cast to all the atomic read functions. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | MIPS: Oprofile: Fix Loongson irq handlerWu Zhangjin2010-05-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The interrupt enable bit for the performance counters is in the Control Register $24, not in the counter register. loongson2_perfcount_handler(), we need to use Reported-by: Xu Hengyang <hengyang@mail.ustc.edu.cn> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1198/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
* | | MIPS: N32: Use compat version for sys_ppoll.Chandrakala Chavva2010-05-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sys_ppoll() takes struct 'struct timespec'. This is different for the N32 and N64 ABIs. Use the compat version to do the proper conversions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1210/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
* | | MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1Shane McDonald2010-05-152-5/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the FPU emulator code of the MIPS, the Cause bits of the FCSR register are not currently writeable by the ctc1 instruction. In odd corner cases, this can cause problems. For example, a case existed where a divide-by-zero exception was generated by the FPU, and the signal handler attempted to restore the FPU registers to their state before the exception occurred. In this particular setup, writing the old value to the FCSR register would cause another divide-by-zero exception to occur immediately. The solution is to change the ctc1 instruction emulator code to allow the Cause bits of the FCSR register to be writeable. This is the behaviour of the hardware that the code is emulating. This problem was found by Shane McDonald, but the credit for the fix goes to Kevin Kissell. In Kevin's words: I submit that the bug is indeed in that ctc_op: case of the emulator. The Cause bits (17:12) are supposed to be writable by that instruction, but the CTC1 emulation won't let them be updated by the instruction. I think that actually if you just completely removed lines 387-388 [...] things would work a good deal better. At least, it would be a more accurate emulation of the architecturally defined FPU. If I wanted to be really, really pedantic (which I sometimes do), I'd also protect the reserved bits that aren't necessarily writable. Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com> To: anemo@mba.ocn.ne.jp To: kevink@paralogos.com To: sshtylyov@mvista.com Patchwork: http://patchwork.linux-mips.org/patch/1205/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
* | | MIPS: Loongson 2F: Fix of problems introduced by -mfix-loongson2f-jumpWu Zhangjin2010-04-301-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The -mfix-loongson2f-jump option provided by latest CVS binutils have fixed the out-of-order issue of Loongson-2F described in chapter 15 of the Loongson2F User Manual [1, 2], but introduced some problems. The option changes all of the jump target to "addr & 0xcfffffff" through the at($1) register, but for the reboot address of Loongson 2F 0xbfc00000 this is wrong. Avoids the problem via telling the assembler to not use the $at register. [1] Loongson2F User Manual (Chinese Version) http://www.loongson.cn/uploadfile/file/200808211 [2] English Version of Chapter 15: http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Reported-and-tested-by: Liu Shiwei <liushiwei@gmail.com> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1109/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Loongson-2F: Use CONFIG_CPU_JUMP_WORKAROUNDS to control workarounds.Wu Zhangjin2010-04-301-1/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1106/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Loongson 2F: Enable fixups of the latest binutilsWu Zhangjin2010-04-301-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the "Fixups of Loongson2F" patch [1] having been applied to binutils for binutils 2.20.1 we now can use it's time to enable the options provided by the patch to compile the kernel. Without these fixups, the system may hang if the erratum is triggered. For more information on these fixups please refer to the following references. [1] "Fixups of Loongson2F" patch for binutils(actually for gas) http://sourceware.org/ml/binutils/2009-11/msg00387.html [2] Chapter 15 of "Loongson2F User Manual"(Chinese Version) http://www.loongson.cn/uploadfile/file/200808211 [3] Chapter 15 of the English version Loongson 2F User Manual http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Signed-off-by: Zhang Le <r0bertz@gentoo.org> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: Zhang Le <r0bertz@gentoo.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1106/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Loongson: Add CPU_LOONGSON2F_WORKAROUNDSWu Zhangjin2010-04-301-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As documented in the Loongson 2F User Manual [2, 3], the old Loongson2F series (2F01 / 2F02) have the NOP & JUMP issues which requires workarounds in the kernel and binutils. This issue has been rectified in Loongson 2F series 2F03 so no workarounds needed. Now that the workarounds [1] adding the the -mfix-loongson2f-nop and -mfix-loongson2f-jump options have been comitted to the binutils the CVS repository), we can add the workarounds in the kernel. The workarounds have no significant side effect on the system but may decrease performance so we control them through a a new CPU_LOONGSON2F_WORKAROUNDS config option allowing the users to only enable it as necessary. [1] "Fixups of Loongson2F" patch for binutils(actually for gas) http://sourceware.org/ml/binutils/2009-11/msg00387.html [2] Chapter 15 of "Loongson2F User Manual"(Chinese Version) http://www.loongson.cn/uploadfile/file/200808211 [3] English Version of the above chapter 15 http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1105/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Kconfig: Make Broadcom SoC support naming consistentFlorian Fainelli2010-04-301-1/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Florian Fainelli <ffainelli@freebox.fr> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1082/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: BCM63xx: Update defconfigFlorian Fainelli2010-04-301-83/+335
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the defconfig was out-of-sync since 2.6.30-rc6, update it with the new symbols and enable BCM6338, 6345, wireless, b43 driver and LEDs support. Signed-off-by: Fainelli <ffainelli@freebox.fr> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1081/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: oprofile: Fix breakage when CONFIG_OPROFILE=mWu Zhangjin2010-04-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the oprofile is compiled as a module do_IRQ() is not called in arch/mips/loongson/lemote-2f/irq.c due to a wrong #ifdef there. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1143/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Loongson: Fix LOONGSON_ADDRWIN_CFG macro.Arnaud Patard2010-04-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's a typo in the LOONGSON_ADDRWIN_CFG macro. The cpu window mmap register address should contain the destination parameters not the source one. This has not been noticed because the code is only using source = destination. Signed-off-by: Arnaud Patard <apatard@mandriva.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1162/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Loongson: Fix phys_mem_access_prot() checkArnaud Patard2010-04-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The check used to determine if uncached accelerated should be used or not is wrong. The parenthesis are misplaced and making the test fail. Signed-off-by: Arnaud Patard <apatard@mandriva.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1161/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Loongson: Fix find_vga_mem_init()Richard LIU2010-04-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This allows to use all display device for instance DISPLAY_OTHER like SM501. Signed-off-by: Arnaud Patard <apatard@mandriva.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1160/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Loongson: Fix typo in gdium mach type string.Arnaud Patard2010-04-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | It's not "gidum" but "gdium". Signed-off-by: Arnaud Patard <apatard@mandriva.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1159/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Use CKSEG1ADDR for uncached handlerSebastian Andrzej Siewior2010-04-301-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "MIPS: Calculate proper ebase value for 64-bit kernels" 9af43ea080dd5d6c7b34f38261780e5dd43537bc (lmo) rsp. f6be75d03c8870be91e6e2a195648ece04b6bb16 (kernel.org) broke some 64-bit MIPS systems. Before this we were using XKPHYS/cached as ebase and computed the uncached xphsys/unchached address for that area. After that commit ebase became a 32-bit compat address and convert does not work anymore. We now should use CKSEG1 for this. CKSEG1ADDR does just that in 32-bit and 64-bit. Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> To: Ralf Baechle <ralf@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1149/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Check for accesses beyond the end of the PGD.David Daney2010-04-301-23/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some combinations of PAGE_SIZE and vmbits, it is possible to have userspace access that are beyond what is covered by the PGD, but within vmbits. Such an access would cause the TLB refill handler to load garbage values for PMD and PTE potentially giving userspace access to parts of the physical address space to which it is not entitled. In the TLB refill hot path, we add a single dsrl instruction so we can check if any bits outside of the range covered by the PGD are set. In the vmalloc side we then separate the bad case from the normal vmalloc case and call tlb_do_page_fault_0 if warranted. This slows us down a bit, but has the benefit of yielding deterministic behavior. [Ralf: Fixed build error for 32-bit kernels.] [Ralf: Folded lmo commit c8c0e22b2aa3982852b44279638ef37f9aa31b7d into this commit.] Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1152/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
* | | MIPS: Use uasm_i_ds{r,l}l_safe() instead of uasm_i_ds{r,l}l() in tlbex.cDavid Daney2010-04-301-16/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes the code somewhat cleaner while reducing the risk of shift amount overflows when various page table related options are changed. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Add uasm_i_dsrl_safe() and uasm_i_dsll_safe() to uasm.David Daney2010-04-301-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows us to clean up the code by not having to explicitly code checks for shift amounts greater than 32. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1153/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: die() does not call die notifier chainYury Polyanskiy2010-04-304-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS implementation of die() forgets to call notify_die() and thus notifiers registered via register_die_notifier() are not called. This results in kgdb not being activated on exceptions. The only subtlety is that notify_die declares its regs argument w/o const, so the const had to be removed from mips die() as well. [Ralf: Fixed build error for SGI IP22 and IP28 platforms.] Signed-off-by: Yury Polyanskiy <ypolyans@princeton.edu> Cc: linux-mips@linux-mips.org Patchworks: http://patchwork.linux-mips.org/patch/1142/ Acked-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
* | | MIPS: Swarm, Littlesur: Enable PATA platform driver.Sebastian Andrzej Siewior2010-04-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to include/asm/sibyte/swarm.h both systems provide a platform device for the ide controler. Until now the IDE subsystem was used which is deprecated by now. The same structure can be used with the PATA driver. Signed-off-by: Sebastian Andrzej Siewior <sebatian@breakpoint.cc> Cc: tbm@cyrius.com Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1127/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: DB1200: PCMCIA card detection must not be auto-enabled.Manuel Lauss2010-04-301-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Same issues as SD card detection: One of both is always triggering and the handlers take care to shut it up and enable the other. To avoid messages about "unbalanced interrupt enable/disable" they must not be automatically enabled when initally requested. This was not an issue with the db1200_defconfig due to fortunate timings; on a build without network chip support the warnings appear. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1133/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: SB1250: Include correct header and fix a warningSebastian Andrzej Siewior2010-04-301-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch/mips/pci/pci-sb1250.c: In function sb1250_pcibios_init: | arch/mips/pci/pci-sb1250.c:257: warning: assignment makes integer from pointer without a cast | arch/mips/pci/pci-sb1250.c:285: error: MAX_NR_CONSOLES undeclared (first use in this function) | arch/mips/pci/pci-sb1250.c:285: error: (Each undeclared identifier is reported only once | arch/mips/pci/pci-sb1250.c:285: error: for each function it appears in.) Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1136/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Fixup screen_info struct initializationsSebastian Andrzej Siewior2010-04-303-27/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | |arch/mips/sibyte/swarm/setup.c:153: | warning: large integer implicitly truncated to unsigned type The field was changed in d9b26352 aka ("x86, setup: Store the boot cursor state"). This patch changes the values back they way they were before this extra field got introduced. While here, the other two boards are also converted to C99 initializer. Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1137/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: cmpxchg.h: Fix excessive indentation.Ralf Baechle2010-04-301-1/+1
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Don't vmap things at address zero.David Daney2010-04-301-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the 64-bit kernel we use swapper_pg_dir for three different things. 1) xuseg mappings for kernel threads. 2) vmap mappings for all kernel-space accesses in xkseg. 3) vmap mappings for kernel modules in ksseg (kseg2). Due to how the TLB refill handlers work, any mapping established in xkseg or ksseg will also establish a xuseg mapping that should never be used by the kernel. In order to be able to use exceptions to trap NULL pointer dereferences, we need to ensure that nothing is mapped at address zero. Since vmap mappings in xkseg are reflected in xuseg, this means we need to ensure that there are no vmap mappings established at the start of xkseg. So we move back VMALLOC_START to avoid establishing vmap mappings at the start of xkseg. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1129/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: PNX8550: Fix build error, broken by:Ralf Baechle2010-04-301-0/+2
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 5a0e3ad6af8660be21ca98a971cd00f331318c05 Author: Tejun Heo <tj@kernel.org> Date: Wed Mar 24 17:04:11 2010 +0900 include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h Since a while the few headers included don't drag in <linux/kernel.h> anymore, thus no more prototype of printk() resulting in: CC arch/mips/nxp/pnx8550/common/reset.o /home/ralf/src/linux/upstream-linus/arch/mips/nxp/pnx8550/common/reset.c: In function 'pnx8550_machine_restart': /home/ralf/src/linux/upstream-linus/arch/mips/nxp/pnx8550/common/reset.c:31: error: implicit declaration of function 'printk' /home/ralf/src/linux/upstream-linus/arch/mips/nxp/pnx8550/common/reset.c:33: error: 'NULL' undeclared (first use in this function) /home/ralf/src/linux/upstream-linus/arch/mips/nxp/pnx8550/common/reset.c:33: error: (Each undeclared identifier is reported only once /home/ralf/src/linux/upstream-linus/arch/mips/nxp/pnx8550/common/reset.c:33: error: for each function it appears in.) make[3]: *** [arch/mips/nxp/pnx8550/common/reset.o] Error 1 Fixed by including <linux/kernel.h> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Calculate proper ebase value for 64-bit kernelsDavid Daney2010-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ebase is relative to CKSEG0 not CAC_BASE. On a 32-bit kernel they are the same thing, for a 64-bit kernel they are not. It happens to kind of work on a 64-bit kernel as they both reference the same physical memory. However since the CPU uses the CKSEG0 base, determining if a J instruction will reach always gives the wrong result unless we use the same number the CPU uses. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1093/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Alchemy: DB1200: Remove custom wait implementationManuel Lauss2010-04-121-40/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | While playing with the out-of-tree MAE driver module, the system would panic after a while in the db1200 custom wait code after wakeup due to a clobbered k0 register being used as target address of a store op. Remove the custom wait implementation and revert back to the Alchemy- recommended implementation already set as default. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1092/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Big Sur: Make defconfig more useful.Ralf Baechle2010-04-121-190/+490
| | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Fix __vmalloc() etc. on MIPS for non-GPL modulesAnton Altaparmakov2010-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit b3594a089f1c17ff919f8f78505c3f20e1f6f8ce (lmo) rsp. 351336929ccf222ae38ff0cb7a8dd5fd5c6236a0 (kernel.org) break non-GPL modules that use __vmalloc() or any of the vmap(), vm_map_ram(), etc functions on MIPS. All those functions are EXPORT_SYMBOL() so are meant to be allowed to be used by non-GPL kernel modules. These calls all take page protection as an argument which is normally a constant like PAGE_KERNEL. This commit causes all protection constants like PAGE_KERNEL to not be constants and instead to contain the GPL-only symbol _page_cachable_default. This means that all calls to __vmalloc(), vmap(), etc, cause non-GPL modules to fail to link with the complaint that they are trying to use the GPL-only symbol _page_cachable_default... Change EXPORT_SYMBOL_GPL(_page_cachable_default) to EXPORT_SYMBOL() for non-GPL modules that call __vmalloc(), vmap(), vm_map_ram() etc. Signed-off-by: Anton Altaparmakov <aia21@cantab.net> Cc: Chris Dearman <chris@mips.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: http://patchwork.linux-mips.org/patch/1084/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Sibyte: Fix M3 TLB exception handler workaround.Ralf Baechle2010-04-121-6/+16
| | | | | | | | | | | | The M3 workaround needs to cmpare the region and VPN2 fields only. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: BCM63xx: Fix build failure in board_bcm963xx.cFlorian Fainelli2010-04-121-70/+70
| | | | | | | | | | | | | | | | | | | | | | | | Since 2083e8327aeeaf818b0e4522a9d2539835c60423, the SPROM is now registered in the board_prom_init callback, but it references variables and functions which are declared below. Move the variables and functions above board_prom_init. Signed-off-by: Florian Fainelli <ffainelli@freebox.fr> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1077/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: uasm: Add OR instruction.Ralf Baechle2010-04-122-1/+4
| | | | | | | | | | | | This is needed for the fix of the M3 workaround. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.Ralf Baechle2010-04-122-1/+20
| | | | | | | | | | | | | | | | | | | | Previously it was unconditionally used on all Sibyte family SOCs. The M3 bug has to be handled in the TLB exception handler which is extremly performance sensitive, so this modification is expected to deliver around 2-3% performance improvment. This is important as required changes to the M3 workaround will make it more costly. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: BCM63xx: Initialize gpio_out_low & out_high to current value at boot.Maxime Bizon2010-04-121-0/+2
| | | | | | | | | | | | | | | | | | | | To avoid a glitch during GPIO initialisation read GPIO output register values left by the firmware. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/903/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: BCM63xx: Register SSB SPROM fallback in board's first stage callbackFlorian Fainelli2010-04-121-11/+11
| | | | | | | | | | | | | | | | Signed-off-by: Florian Fainelli <ffainelli@freebox.fr> To: Maxime Bizon <mbizon@freebox.fr> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1017/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: BCM63xx: Fix typo in cpu-feature-overrides file.Maxime Bizon2010-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | Fix typo: CONFIG_BCMCPU_IS_63xx does not exist; CONFIG_BCM63XX_CPU_63xx is the valid config option. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> To: linux-mips@linux-mips.org Cc: Maxime Bizon <mbizon@freebox.fr> Patchwork: http://patchwork.linux-mips.org/patch/901/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: BCM63xx: Add support for second uart.Maxime Bizon2010-04-126-19/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | The BCm63xx SOC has two uarts. Some boards use the second one for bluetooth. This patch changes platform device registration code to handle this. Changes to the UART driver were already merged in 6a2c7eabfd09ca7986bf96b8958a87ca041a19d8. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> To: linux-mips@linux-mips.org Cc: Maxime Bizon <mbizon@freebox.fr> Patchwork: http://patchwork.linux-mips.org/patch/900/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: BCM63xx: Fix double gpio registration.Maxime Bizon2010-04-121-2/+0
| | | | | | | | | | | | | | | | | | | | | | bcm63xx_gpio_init is already called from prom_init to allow board to use them early, so we can remove the unneeded arch_initcall. Signed-off-by: Maxime Bizon <mbizon@freebox.fr> To: linux-mips@linux-mips.org Cc: Maxime Bizon <mbizon@freebox.fr> Patchwork: http://patchwork.linux-mips.org/patch/899/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: BCM63xx: Add DWVS0 boardFlorian Fainelli2010-04-121-0/+22
| | | | | | | | | | | | | | | | | | The DWVS0 board is a BCM6358-based board with an on-board OHCI controler. Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1015/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: BCM63xx: Add the RTA1025W-16 BCM6348-based board to suppported boards.Florian Fainelli2010-04-121-0/+20
| | | | | | | | | | | | | | Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1014/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: BCM63xx: Fix BCM6338 and BCM6345 gpio countFlorian Fainelli2010-04-121-0/+4
| | | | | | | | | | | | | | | | | | | | The number of GPIOs on BCM6338 is 8, while BCM6345 has only 16 GPIOs available. Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1016/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: libgcc.h: Checkpatch cleanupAndrea Gelmini2010-04-121-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | arch/mips/lib/libgcc.h:21: ERROR: open brace '{' following union go on the same line Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> To: linux-kernel@vger.kernel.org Cc: Paul Mundt <lethal@linux-sh.org> Cc: linux-mips@linux-mips.org Cc: linux-sh@vger.kernel.org Patchwork: http://patchwork.linux-mips.org/patch/1007/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Loongson-2F: Flush the branch target history in BTB and RASWu Zhangjin2010-04-121-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per chapter 15 "Errata: Issue of Out-of-order in loongson"[1] to work around the Loongson 2F erratum we need to do: "When switching from user mode to kernel mode, you should flush the branch target history such as BTB and RAS." [1] Chinese version: http://www.loongson.cn/uploadfile/file/200808211 [2] English version of chapter 15: http://groups.google.com.hk/group/loongson-dev/msg/e0d2e220958f10a6?dmode=source Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: Shinya Kuribayashi <shinya.kuribayashi@necel.com> Patchwork: http://patchwork.linux-mips.org/patch/1066/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Move signal trampolines off of the stack.David Daney2010-04-125-135/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a follow on to the vdso patch. Since all processes now have signal trampolines permanently mapped, we can use those instead of putting the trampoline on the stack and invalidating the corresponding icache across all CPUs. We also get rid of a bunch of ICACHE_REFILLS_WORKAROUND_WAR code. [Ralf: GDB 7.1 which has the necessary modifications to allow backtracing over signal frames will supposedly be released tomorrow. The old signal frame format obsoleted by this patch exists in two variations, for sane processors and for those requiring ICACHE_REFILLS_WORKAROUND_WAR. So there was never a GDB which did support backtracing over signal frames on all MIPS systems. This convinved me this series should be applied and pushed upstream as soon as possible.] Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/974/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | MIPS: Preliminary VDSODavid Daney2010-04-128-6/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a preliminary patch to add a vdso to all user processes. Still missing are ELF headers and .eh_frame information. But it is enough to allow us to move signal trampolines off of the stack. Note that emulation of branch delay slots in the FPU emulator still requires the stack. We allocate a single page (the vdso) and write all possible signal trampolines into it. The stack is moved down by one page and the vdso is mapped into this space. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/975/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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