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* [SPARC64]: Negotiate hypervisor API for PCI services.David S. Miller2007-05-291-0/+18
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Don't be picky about virtual-dma values on sun4v.David S. Miller2007-05-291-26/+10
| | | | | | | | | Handle arbitrary base and length values as long as they are multiples of IO_PAGE_SIZE. Bug found by Arun Kumar Rao. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Spelling fixes.Simon Arlott2007-05-111-1/+1
| | | | | | | Spelling fixes in arch/sparc64/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64] PCI: Consolidate PCI access code into pci_common.cDavid S. Miller2007-05-091-84/+2
| | | | | | | | | | | | | All the sun4u controllers do the same thing to compute the physical I/O address to poke, and we can move the sun4v code into this common location too. This one needs a bit of testing, in particular the Sabre code had some funny stuff that would break up u16 and/or u32 accesses into pieces and I didn't think that was needed any more. If it is we need to find out why and add back code to do it again. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill asm-sparc64/pbm.hDavid S. Miller2007-05-081-1/+0
| | | | | | Everything it contains can be hidden in pci_impl.h Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Move index info pci_pbm_info.David S. Miller2007-05-081-2/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Move {setup,teardown}_msi_irq into pci_pbm_info.David S. Miller2007-05-081-113/+111
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Move pci_ops into pci_pbm_info.David S. Miller2007-05-081-1/+1
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64] PCI: Use root list of pbm's instead of pci_controller_info'sDavid S. Miller2007-05-081-34/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea is to move more and more things into the pbm, with the eventual goal of eliminating the pci_controller_info entirely as there really isn't any need for it. This stage of the transformations requires some reworking of the PCI error interrupt handling. It might be tricky to get rid of the pci_controller_info parenting for a few reasons: 1) When we get an uncorrectable or correctable error we want to interrogate the IOMMU and streaming cache of both PBMs for error status. These errors come from the UPA front-end which is shared between the two PBM PCI bus segments. Historically speaking this is why I choose the datastructure hierarchy of pci_controller_info-->pci_pbm_info 2) The probing does a portid/devhandle match to look for the 'other' pbm, but this is entirely an artifact and can be eliminated trivially. What we could do to solve #1 is to have a "buddy" pointer from one pbm to another. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64] PCI: Use common routine to fetch PBM properties.David S. Miller2007-05-081-15/+1
| | | | | | | | | | Namely bus-range and ino-bitmap. This allows us also to eliminate pci_controller_info's pci_{first,last}_busno fields as only the pbm ones are used now. Signed-off-by: David S. Miller <davem@davemloft.net>
* MSI: arch must connect the irq and the msi_descMichael Ellerman2007-05-021-2/+2
| | | | | | | | | | | | | | | | | | | | set_irq_msi() currently connects an irq_desc to an msi_desc. The archs call it at some point in their setup routine, and then the generic code sets up the reverse mapping from the msi_desc back to the irq. set_irq_msi() should do both connections, making it the one and only call required to connect an irq with it's MSI desc and vice versa. The arch code MUST call set_irq_msi(), and it must do so only once it's sure it's not going to fail the irq allocation. Given that there's no need for the arch to return the irq anymore, the return value from the arch setup routine just becomes 0 for success and anything else for failure. Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* [SPARC64]: Convert PCI over to generic struct iommu/strbuf.David S. Miller2007-04-261-17/+17
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Consolidate {sbus,pci}_iommu_arena.David S. Miller2007-04-261-3/+3
| | | | | | Move to asm-sparc64/iommu.h and rename to plain "iommu_arena". Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add dummy host controller to root of all PCI domains.David S. Miller2007-04-261-0/+6
| | | | | | | We fake up a dummy one in all cases because that is the simplest thing to do and it happens to be necessary for hypervisor systems. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Const'ify pci_iommu_ops.David S. Miller2007-04-261-1/+1
| | | | | | | Based upon a similar patch for x86_64 written by Stephen Hemminger. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill pbm->pci_first_slot.David S. Miller2007-04-261-1/+0
| | | | | | Set but never used. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill pci_controller->pbms_same_domainDavid S. Miller2007-04-261-1/+0
| | | | | | | | We don't do the "Simba APB is a PBM" bogosity for Sabre controllers any longer, so this pbms_same_domain thing is no longer necessary. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill pci_controller->base_address_update().David S. Miller2007-04-261-46/+0
| | | | | | Implemented but never actually used. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill pci_controller->resource_adjust()David S. Miller2007-04-261-9/+0
| | | | | | | All the implementations can be identical and generic, so no need for controller specific methods. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill PBM ranges software state.David S. Miller2007-04-261-13/+0
| | | | | | | It is only used in one spot and we can just fetch the OF property right there. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill PBM intmap software state.David S. Miller2007-04-261-8/+0
| | | | | | Set but never used. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Consolidate PCI mem/io resource determination.David S. Miller2007-04-261-69/+2
| | | | | | It can be done for every PCI configuration using OF properties. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Probe PCI bus using OF device tree.David S. Miller2007-04-261-175/+24
| | | | | | | | | Almost entirely taken from the 64-bit PowerPC PCI code. This allowed to eliminate a ton of cruft from the sparc64 PCI layer. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: constify of_get_property return: arch/sparc64Stephen Rothwell2007-04-261-4/+4
| | | | | Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add PCI MSI support on Niagara.David S. Miller2007-02-101-0/+444
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is kind of hokey, we could use the hardware provided facilities much better. MSIs are assosciated with MSI Queues. MSI Queues generate interrupts when any MSI assosciated with it is signalled. This suggests a two-tiered IRQ dispatch scheme: MSI Queue interrupt --> queue interrupt handler MSI dispatch --> driver interrupt handler But we just get one-level under Linux currently. What I'd like to do is possibly stick the IRQ actions into a per-MSI-Queue data structure, and dispatch them form there, but the generic IRQ layer doesn't provide a way to do that right now. So, the current kludge is to "ACK" the interrupt by processing the MSI Queue data structures and ACK'ing them, then we run the actual handler like normal. We are wasting a lot of useful information, for example the MSI data and address are provided with ever MSI, as well as a system tick if available. If we could pass this into the IRQ handler it could help with certain things, in particular for PCI-Express error messages. The MSI entries on sparc64 also tell you exactly which bus/device/fn sent the MSI, which would be great for error handling when no registered IRQ handler can service the interrupt. We override the disable/enable IRQ chip methods in sun4v_msi, so we have to call {mask,unmask}_msi_irq() directly from there. This is another ugly wart. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Replace kmalloc+memset with kzallocYan Burman2006-12-101-11/+5
| | | | | | | Replace kmalloc+memset with kzalloc Signed-off-by: Yan Burman <burman.yan@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: of_device layer IRQ resolutionDavid S. Miller2006-06-291-10/+0
| | | | | | | | | | | | | | | | | | Do IRQ determination generically by parsing the PROM properties, and using IRQ controller drivers for final resolution. One immediate positive effect is that all of the IRQ frobbing in the EBUS, ISA, and PCI controller layers has been eliminated. We just look up the of_device and use the properly computed value. The PCI controller irq_build() routines are gone and no longer used. Unfortunately sbus_build_irq() has to remain as there is a direct reference to this in the sunzilog driver. That can be killed off once the sparc32 side of this is written and the sunzilog driver is transformed into an "of" bus driver. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Convert sparc64 PCI layer to in-kernel device tree.David S. Miller2006-06-231-2/+1
| | | | | | | | One thing this change pointed out was that we really should pull the "get 'local-mac-address' property" logic into a helper function all the network drivers can call. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix for Niagara memory corruption.David S. Miller2006-06-231-5/+10
| | | | | | | | | | | | | | | | | | | On some sun4v systems, after netboot the ethernet controller and it's DMA mappings can be left active. The net result is that the kernel can end up using memory the ethernet controller will continue to DMA into, resulting in corruption. To deal with this, we are more careful about importing IOMMU translations which OBP has left in the IO-TLB. If the mapping maps into an area the firmware claimed was free and available memory for the kernel to use, we demap instead of import that IOMMU entry. This is going to cause the network chip to take a PCI master abort on the next DMA it attempts, if it has been left going like this. All tests show that this is handled properly by the PCI layer and the e1000 drivers. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Use in-kernel OBP device tree for PCI controller probing.David S. Miller2006-06-231-79/+65
| | | | | | It can be pushed even further down, but this is a first step. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Move over to GENERIC_HARDIRQS.David S. Miller2006-06-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This is the long overdue conversion of sparc64 over to the generic IRQ layer. The kernel image is slightly larger, but the BSS is ~60K smaller due to the reduced size of struct ino_bucket. A lot of IRQ implementation details, including ino_bucket, were moved out of asm-sparc64/irq.h and are now private to arch/sparc64/kernel/irq.c, and most of the code in irq.c totally disappeared. One thing that's different at the moment is IRQ distribution, we do it at enable_irq() time. If the cpu mask is ALL then we round-robin using a global rotating cpu counter, else we pick the first cpu in the mask to support single cpu targetting. This is similar to what powerpc's XICS IRQ support code does. This works fine on my UP SB1000, and the SMP build goes fine and runs on that machine, but lots of testing on different setups is needed. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill ino_bucket->pilDavid S. Miller2006-06-201-31/+1
| | | | | | | | | | | And reuse that struct member for virt_irq, which will be used in future changesets for the implementation of mapping between real and virtual IRQ numbers. This nicely kills off a ton of SBUS and PCI controller PIL assignment code which is no longer necessary. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Avoid JBUS errors on some Niagara systems.David S. Miller2006-06-101-6/+118
| | | | | | | | | | | | | | | | | | | Doing PCI config space accesses to non-present PCI slots can result in fatal JBUS errors if the PCI config access hypervisor call is performed on cpus other than the boot cpu. PCI config space accesses to present PCI slots works just fine. Recursively traverse the OBP device tree under the PCI controller node and record all present device IDs into a small hash table. Avoid the hypervisor call for any PCI config space access attempt for a device not recorded in the hash table. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Respect gfp_t argument to dma_alloc_coherent().David S. Miller2006-05-231-2/+2
| | | | | | | | | | | | | | | | Using asm-generic/dma-mapping.h does not work because pushing the call down to pci_alloc_coherent() causes the gfp_t argument of dma_alloc_coherent() to be ignored. Fix this by implementing things directly, and adding a gfp_t argument we can use in the internal call down to the PCI DMA implementation of pci_alloc_coherent(). This fixes massive memory corruption when using the sound driver layer, which passes things like __GFP_COMP down into these routines and (correctly) expects that to work. Signed-off-by: David S. Miller <davem@davemloft.net>
* [PATCH] for_each_possible_cpu: sparc64KAMEZAWA Hiroyuki2006-04-111-1/+1
| | | | | | | | | | | | | | | | | | for_each_cpu() actually iterates across all possible CPUs. We've had mistakes in the past where people were using for_each_cpu() where they should have been iterating across only online or present CPUs. This is inefficient and possibly buggy. We're renaming for_each_cpu() to for_each_possible_cpu() to avoid this in the future. This patch replaces for_each_cpu with for_each_possible_cpu. for sparc64. Signed-off-by: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com> Acked-by: "David S. Miller" <davem@davemloft.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [SPARC64]: Fix new context version SMP handling.David S. Miller2006-03-201-3/+3
| | | | | | | | | | | | | | | | Don't piggy back the SMP receive signal code to do the context version change handling. Instead allocate another fixed PIL number for this asynchronous cross-call. We can't use smp_call_function() because this thing is invoked with interrupts disabled and a few spinlocks held. Also, fix smp_call_function_mask() to count "cpus" correctly. There is no guarentee that the local cpu is in the mask yet that is exactly what this code was assuming. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Handle zero-length map requests in pci_sun4v.cDavid S. Miller2006-03-201-2/+2
| | | | | | | By simply changing the do-while loop into a plain while loop. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill stray PGLIST_NENTS check in pci_sun4v.cDavid S. Miller2006-03-201-2/+0
| | | | | | | I forgot to remove the one in pci_4v_map_sg() during the iommu batching commit. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Remove PGLIST_NENTS PCI IOMMU mapping limitation on SUN4V.David S. Miller2006-03-201-75/+158
| | | | | | | Use a batching queue system for IOMMU mapping setup, with a page sized batch. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64] PCI: Size TSB correctly on SUN4V.David S. Miller2006-03-201-6/+16
| | | | | | | | | Forgot to multiply by 8 * 1024, oops. Correct the size constant when the virtual-dma arena is 2GB in size, it should bet 256 not 128. Finally, log some info about the TSB at probe time. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Make lack of interrupt-map-* a fatal error on SUN4V.David S. Miller2006-03-201-13/+14
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Restrict PCI bus scanning on SUN4V.David S. Miller2006-03-201-20/+16
| | | | | | | | | | | | | On the PBM's first bus number, only allow device 0, function 0, to be poked at with PCI config space accesses. For some reason, this single device responds to all device numbers. Also, reduce the verbiage of the debugging log printk's for PCI cfg space accesses in the SUN4V PCI controller driver, so that it doesn't overwhelm the slow SUN4V hypervisor console. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix IOMMU mapping on sun4v.David S. Miller2006-03-201-30/+46
| | | | | | | | | | We should dynamically allocate the per-cpu pglist not use an in-kernel-image datum, since __pa() does not work on such addresses. Also, consistently use "u32" for devhandle. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill spurious semicolon in sun4v_pci_init().David S. Miller2006-03-201-1/+1
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Generic sun4v_build_irq().David S. Miller2006-03-201-28/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: More SUN4V PCI work.David S. Miller2006-03-201-14/+102
| | | | | | | | | | | Get bus range from child of PCI controller root nexus. This is actually a hack, but the PCI-E bridge sitting at the top of the PCI tree responds to PCI config cycles for every device number, so best to just ignore it for now. Preliminary PCI irq routing, needs lots of work. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Range check bus number in SUN4V PCI controller driver.David S. Miller2006-03-201-9/+24
| | | | | | | It has to be somewhere in the range from pbm->pci_first_busno to pbm->pci_last_busno, inclusive. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Missing 'return' statement in sun4v_pci_init().David S. Miller2006-03-201-4/+3
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Implement basic pci_sun4v_scan_bus().David S. Miller2006-03-201-3/+46
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: PCI-SUN4V fixes.David S. Miller2006-03-201-8/+33
| | | | | | | | | Clear top 8-bits of physical addresses in "ranges" property. This gives the actual physical address. Detect PBM-A vs. PBM-B by checking bit 0x40 of the devhandle. Signed-off-by: David S. Miller <davem@davemloft.net>
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