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* [SPARC64]: Bulletproof hypervisor TLB flushing.David S. Miller2006-03-201-0/+12
| | | | | | | | | | | Check TLB flush hypervisor calls for errors and report them. Pass HV_MMU_ALL always for now, we can add back the optimization to avoid the I-TLB flush later. Always explicitly page align the virtual address arguments. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Report mondo error correctly in hypervisor_xcall_deliver().David S. Miller2006-03-201-1/+1
| | | | | | It's in "arg0" not "func". Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Niagara optimized XOR functions for RAID.David S. Miller2006-03-201-0/+13
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix binfmt_aout32.c build.Andrew Morton2006-03-201-1/+1
| | | | | Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix TLB context allocation with SMT style shared TLBs.David S. Miller2006-03-201-11/+29
| | | | | | | | | | | | | | | The context allocation scheme we use depends upon there being a 1<-->1 mapping from cpu to physical TLB for correctness. Chips like Niagara break this assumption. So what we do is notify all cpus with a cross call when the context version number changes, and if necessary this makes them allocate a valid context for the address space they are running at the time. Stress tested with make -j1024, make -j2048, and make -j4096 kernel builds on a 32-strand, 8 core, T2000 with 16GB of ram. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Put syscall tables after trap table.David S. Miller2006-03-201-1/+2
| | | | | | | Otherwise with too much stuff enabled in the kernel config we can end up with an unaligned trap table. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Drop %gl to 0 before re-enabling PSTATE_IE in rtrapDavid S. Miller2006-03-201-1/+2
| | | | | | | | If we take a window fault, on SUN4V set %gl to zero before we turn PSTATE_IE back on in %pstate. Otherwise if we take an interrupt we'll end up with corrupt register state. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Create a seperate kernel TSB for 4MB/256MB mappings.David S. Miller2006-03-201-1/+14
| | | | | | | | | | It can map all of the linear kernel mappings with zero TSB hash conflicts for systems with 16GB or less ram. In such cases, on SUN4V, once we load up this TSB the first time with all the mappings, we never take a linear kernel mapping TLB miss ever again, the hypervisor handles them all. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Make use of Niagara 256MB PTEs for kernel mappings.David S. Miller2006-03-201-2/+27
| | | | | | | | | | | We use a bitmap, one bit for every 256MB of memory. If the bit is set we can use a 256MB PTE for linear mappings, else we have to use a 4MB PTE. SUN4V support is there, and we can very easily add support for Panther cpu 256MB PTEs in the future. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Use sun4v_cpu_idle() in cpu_idle() on SUN4V.David S. Miller2006-03-201-49/+32
| | | | | | | | | | | We have to turn off the "polling nrflag" bit when we sleep the cpu like this, so that we'll get a cross-cpu interrupt to wake the processor up from the yield. We also have to disable PSTATE_IE in %pstate around the yield call and recheck need_resched() in order to avoid any races. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add sun4v_cpu_yield().David S. Miller2006-03-201-0/+9
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill cpudata->idle_volume.David S. Miller2006-03-202-10/+2
| | | | | | | | | Set, but never used. We used to use this for dynamic IRQ retargetting, but that code died a long time ago. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Niagara optimized memset/bzero/clear_user.David S. Miller2006-03-201-0/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Pass multiple CPUs at once to hypervisor cross-call API.David S. Miller2006-03-201-54/+0
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Typo in sun4v_data_access_exception log message.David S. Miller2006-03-201-1/+1
| | | | | | Should be "Dax" not "Iax". Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Handle zero-length map requests in pci_sun4v.cDavid S. Miller2006-03-201-2/+2
| | | | | | | By simply changing the do-while loop into a plain while loop. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill stray PGLIST_NENTS check in pci_sun4v.cDavid S. Miller2006-03-201-2/+0
| | | | | | | I forgot to remove the one in pci_4v_map_sg() during the iommu batching commit. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix typo in dump_tl1_traplog()David S. Miller2006-03-201-1/+1
| | | | | | Actually make use of the 'limit' we compute. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Disable smp_report_regs() for now.David S. Miller2006-03-201-1/+2
| | | | | | | | | | It's extremely noisy and causes much grief on slow consoles with large numbers of cpus. We'll have to provide this some saner way in order to re-enable this. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Remove PGLIST_NENTS PCI IOMMU mapping limitation on SUN4V.David S. Miller2006-03-203-83/+171
| | | | | | | Use a batching queue system for IOMMU mapping setup, with a page sized batch. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Use KERN_EMERG in dump_tl1_traplog() and sun4v TLB errors.David S. Miller2006-03-201-7/+13
| | | | | | | We're about to seriously die in these cases so it is important that the messages make it to the console. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix unaligned access winfxup handling on SUN4V.David S. Miller2006-03-202-17/+34
| | | | | | | | | | | Another case where we have to force ourselves into global register level one. Also make sure the arguments passed to sun4v_do_mna() are correct. This area actually needs some more work, for example spill fixup is not necessarily going to do the right thing for this case. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Set %gl to 1 in kvmap_itlb_longpath on SUN4V.David S. Miller2006-03-201-1/+1
| | | | | | | | Just like kvmap_dtlb_longpath we have to force the global register level to one in order to mimick the PSTATE_MG --> PSTATE_AG trasition done on SUN4U. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: More TLB/TSB handling fixes.David S. Miller2006-03-205-37/+49
| | | | | | | | | | | | | | | The SUN4V convention with non-shared TSBs is that the context bit of the TAG is clear. So we have to choose an "invalid" bit and initialize new TSBs appropriately. Otherwise a zero TAG looks "valid". Make sure, for the window fixup cases, that we use the right global registers and that we don't potentially trample on the live global registers in etrap/rtrap handling (%g2 and %g6) and that we put the missing virtual address properly in %g5. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Don't do anything in flush_ptrace_access() on SUN4V.David S. Miller2006-03-201-0/+3
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix some SUN4V TLB handling bugs.David S. Miller2006-03-203-5/+92
| | | | | | | | | | | | | 1) Add error return checking for TLB load hypervisor calls. 2) Don't fallthru to dtlb tsb miss handler from itlb tsb miss handler, oops. 3) On window fixups, propagate fault information to fixup handler correctly. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Init boot cpu's trap_block[] before paging_init()David S. Miller2006-03-201-2/+2
| | | | | | It must be ready when we take over the trap table. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Define ARCH_HAS_READ_CURRENT_TIMER.David S. Miller2006-03-201-7/+1
| | | | | | | This gives more consistent bogomips and delay() semantics, especially on sun4v. It gives weird looking values though... Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: __bzero_noasi --> __clear_userDavid S. Miller2006-03-201-1/+1
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Put SUN4V ITSB miss into correct trap table entry.David S. Miller2006-03-201-6/+4
| | | | | | It's 0x9 not 0xb. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix uniprocessor IRQ targetting on SUN4V.David S. Miller2006-03-203-55/+53
| | | | | | | | | | | We need to use the real hardware processor ID when targetting interrupts, not the "define to 0" thing the uniprocessor build gives us. Also, fill in the Node-ID and Agent-ID fields properly on sun4u/Safari. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix PCI IRQ probing regression.David S. Miller2006-03-201-5/+5
| | | | | | | | If the top-level cnode had multi entries in it's "reg" property, we'd fail. The buffer wasn't large enough in such cases. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Get SUN4V SMP working.David S. Miller2006-03-205-50/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sibling cpu bringup is extremely fragile. We can only perform the most basic calls until we take over the trap table from the firmware/hypervisor on the new cpu. This means no accesses to %g4, %g5, %g6 since those can't be TLB translated without our trap handlers. In order to achieve this: 1) Change sun4v_init_mondo_queues() so that it can operate in several modes. It can allocate the queues, or install them in the current processor, or both. The boot cpu does both in it's call early on. Later, the boot cpu allocates the sibling cpu queue, starts the sibling cpu, then the sibling cpu loads them in. 2) init_cur_cpu_trap() is changed to take the current_thread_info() as an argument instead of reading %g6 directly on the current cpu. 3) Create a trampoline stack for the sibling cpus. We do our basic kernel calls using this stack, which is locked into the kernel image, then go to our proper thread stack after taking over the trap table. 4) While we are in this delicate startup state, we put 0xdeadbeef into %g4/%g5/%g6 in order to catch accidental accesses. 5) On the final prom_set_trap_table*() call, we put &init_thread_union into %g6. This is a hack to make prom_world(0) work. All that wants to do is restore the %asi register using get_thread_current_ds(). Longer term we should just do the OBP calls to set the trap table by hand just like we do for everything else. This would avoid that silly prom_world(0) issue, then we can remove the init_thread_union hack. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Disable smp_report_regs() for now.David S. Miller2006-03-201-0/+2
| | | | | | | For 32 cpus and a slow console, it just wedges the machine especially with DETECT_SOFTLOCKUP enabled. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Rewrite pci_intmap_match().David S. Miller2006-03-201-114/+155
| | | | | | | | | | | | | | | | | | | | The whole algorithm was wrong. What we need to do is: 1) Walk each PCI bus above this device on the path to the PCI controller nexus, and for each: a) If interrupt-map exists, apply it, record IRQ controller node b) Else, swivel interrupt number using PCI_SLOT(), use PCI bus parent OBP node as controller node c) Walk up to "controller node" until we hit the first PCI bus in this domain, or "controller node" is the PCI controller OBP node 2) If we walked to PCI controller OBP node, we're done. 3) Else, apply PCI controller interrupt-map to interrupt. There is some stuff that needs to be checked out for ebus and isa, but the PCI part is good to go. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Don't set interrupt state to IDLE in enable_irq().David S. Miller2006-03-201-4/+0
| | | | | | We'll lose events that way. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix return from trap on SUN4V.David S. Miller2006-03-201-1/+3
| | | | | | | | | | | | We need to set the global register set _AND_ disable PSTATE_IE in %pstate. The original patch sequence was leaving PSTATE_IE enabled when returning to kernel mode, oops. This fixes the random register corruption being seen on SUN4V. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Set dummy bucket->{imap,iclr} unique on SUN4V.David S. Miller2006-03-201-5/+10
| | | | | | So that free_irq() disable's the IRQ correctly. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add sun4v_cpu_qconf() hypervisor call.David S. Miller2006-03-202-19/+19
| | | | | | Call it from register_one_mondo(). Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: do_fptrap needs to load the thread reg into %g6.David S. Miller2006-03-201-0/+1
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix bogus call to sun4v_mna in winfixup code.David S. Miller2006-03-201-1/+1
| | | | | | The C function is named sun4v_do_mna not sun4v_mna. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix tl1 trap state capture/dump on SUN4V.David S. Miller2006-03-202-1/+9
| | | | | | No trap levels above 2 in privileged mode on SUN4V. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64] PCI: Size TSB correctly on SUN4V.David S. Miller2006-03-201-6/+16
| | | | | | | | | Forgot to multiply by 8 * 1024, oops. Correct the size constant when the virtual-dma arena is 2GB in size, it should bet 256 not 128. Finally, log some info about the TSB at probe time. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Don't use ASI_QUAD_LDD_PHYS on SUN4V.David S. Miller2006-03-201-2/+2
| | | | | | Need to use ASI_QUAD_LDD_PHYS_4V instead. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Do not write garbage into %pstate in tsb_context_switch().David S. Miller2006-03-201-1/+7
| | | | | | | | For SUN4V, we were clobbering %o5 to do the hypervisor call. This clobbers the saved %pstate value and we end up writing garbage into that register as a result. Oops. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Decode virtual-devices interrupts correctly.David S. Miller2006-03-201-12/+86
| | | | | | Need to translate through the interrupt-map{,-mask] properties. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add prom_{start,stop}cpu_cpuid().David S. Miller2006-03-201-3/+9
| | | | | | | | | Use prom_startcpu_cpuid() on SUN4V instead of prom_startcpu(). We should really test for "SUNW,start-cpu-by-cpuid" presence and use it if present even on SUN4U. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix pci_intmap_match().David S. Miller2006-03-201-3/+10
| | | | | | | | | | When crawling up the PCI bus chain, stop at the first node that has an interrupt-map property before we hit the root. Also, if we use a bus interrupt-{map,mask} do not forget to update the 'intmask' pointer as we do for the 'intmap' pointer. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Two IRQ handling fixes.David S. Miller2006-03-201-3/+8
| | | | | | | | | On SUN4V, force IRQ state to idle in enable_irq(). However, I'm still not sure this is %100 correct. Call add_interrupt_randomness() on SUN4V too. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Use different cache sizing defaults on SUN4V.David S. Miller2006-03-202-14/+48
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
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