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* [SPARC64]: Fix "mem=xxx" handling.David S. Miller2006-12-311-23/+124
| | | | | | | | We were not being careful enough. When we trim the physical memory areas, we have to make sure we don't remove the kernel image or initial ramdisk image ranges. Signed-off-by: David S. Miller <davem@davemloft.net>
* [PATCH] slab: remove kmem_cache_tChristoph Lameter2006-12-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace all uses of kmem_cache_t with struct kmem_cache. The patch was generated using the following script: #!/bin/sh # # Replace one string by another in all the kernel sources. # set -e for file in `find * -name "*.c" -o -name "*.h"|xargs grep -l $1`; do quilt add $file sed -e "1,\$s/$1/$2/g" $file >/tmp/$$ mv /tmp/$$ $file quilt refresh done The script was run like this sh replace kmem_cache_t "struct kmem_cache" Signed-off-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [SPARC64]: Kill bogus check from bootmem_init().David S. Miller2006-09-261-2/+1
| | | | | | | | | | | | | | | | | There is an ancient and totally incorrect sanity check being done on the ramdisk location. The check assumes that the kernel is always loaded to physical address zero, which is wrong. It was trying to validate the ramdisk value by saying that if it fell within the kernel image address range it must be wrong. Anyways, kill this because it actually creates problems. The 'ramdisk_image' should always be adjusted down by KERNBASE. SILO can easily put the ramdisk in a location which causes this test to trigger, breaking things. [ Based almost entirely upon a patch from Ben Collins. ] Signed-off-by: David S. Miller <davem@davemloft.net>
* Remove obsolete #include <linux/config.h>Jörn Engel2006-06-301-1/+0
| | | | | Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
* [PATCH] add poison.h and patch primary usersRandy Dunlap2006-06-271-1/+2
| | | | | | | | | | | | | | | | | Localize poison values into one header file for better documentation and easier/quicker debugging and so that the same values won't be used for multiple purposes. Use these constants in core arch., mm, driver, and fs code. Signed-off-by: Randy Dunlap <rdunlap@xenotime.net> Acked-by: Matt Mackall <mpm@selenic.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Andi Kleen <ak@muc.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [SPARC64]: Export _PAGE_IE to modules.David S. Miller2006-06-251-0/+1
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix for Niagara memory corruption.David S. Miller2006-06-231-1/+27
| | | | | | | | | | | | | | | | | | | On some sun4v systems, after netboot the ethernet controller and it's DMA mappings can be left active. The net result is that the kernel can end up using memory the ethernet controller will continue to DMA into, resulting in corruption. To deal with this, we are more careful about importing IOMMU translations which OBP has left in the IO-TLB. If the mapping maps into an area the firmware claimed was free and available memory for the kernel to use, we demap instead of import that IOMMU entry. This is going to cause the network chip to take a PCI master abort on the next DMA it attempts, if it has been left going like this. All tests show that this is handled properly by the PCI layer and the e1000 drivers. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Minor bug fix to obp_read_memory().David S. Miller2006-06-231-2/+19
| | | | | | | | | If we end up zero'ing out the size of one of the entries, pop it out of the array completely because some code that examines these things cannot handle a zero length element properly. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Import OBP device tree into kernel data structures.David S. Miller2006-06-231-0/+3
| | | | | | | | | The basic framework is based on the PowerPC OF code. This code even tries to get the device addressing components correct in the full path names. Signed-off-by: David S. Miller <davem@davemloft.net>
* [PATCH] sparc64: fix set_page_count merge clashNick Piggin2006-03-231-2/+2
| | | | | | | | | Merge clash will have broken sparc64. Synch up its online_page implementation with powerpc, which was identical until the set_page_count removal. Signed-off-by: Nick Piggin <npiggin@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6Linus Torvalds2006-03-221-2/+19
|\ | | | | | | | | | | * master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6: [SPARC64]: Add a secondary TSB for hugepage mappings. [SPARC]: Respect vm_page_prot in io_remap_page_range().
| * [SPARC64]: Add a secondary TSB for hugepage mappings.David S. Miller2006-03-221-2/+19
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* | [PATCH] remove set_page_count() outside mm/Nick Piggin2006-03-221-2/+2
|/ | | | | | | | | | | | | set_page_count usage outside mm/ is limited to setting the refcount to 1. Remove set_page_count from outside mm/, and replace those users with init_page_count() and set_page_refcounted(). This allows more debug checking, and tighter control on how code is allowed to play around with page->_count. Signed-off-by: Nick Piggin <npiggin@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* [SPARC64]: Allow CONFIG_MEMORY_HOTPLUG to build.David S. Miller2006-03-201-0/+18
| | | | | | | | | | online_page() is straightforward, and then add a dummy remove_memory() that returns -EINVAL just like i386. There is no point in implementing remove_memory() since __remove_pages() has no implementation either. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Use SLAB caches for TSB tables.David S. Miller2006-03-201-1/+4
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix and re-enable dynamic TSB sizing.David S. Miller2006-03-201-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is good for up to %50 performance improvement of some test cases. The problem has been the race conditions, and hopefully I've plugged them all up here. 1) There was a serious race in switch_mm() wrt. lazy TLB switching to and from kernel threads. We could erroneously skip a tsb_context_switch() and thus use a stale TSB across a TSB grow event. There is a big comment now in that function describing exactly how it can happen. 2) All code paths that do something with the TSB need to be guarded with the mm->context.lock spinlock. This makes page table flushing paths properly synchronize with both TSB growing and TLB context changes. 3) TSB growing events are moved to the end of successful fault processing. Previously it was in update_mmu_cache() but that is deadlock prone. At the end of do_sparc64_fault() we hold no spinlocks that could deadlock the TSB grow sequence. We also have dropped the address space semaphore. While we're here, add prefetching to the copy_tsb() routine and put it in assembler into the tsb.S file. This piece of code is quite time critical. There are some small negative side effects to this code which can be improved upon. In particular we grab the mm->context.lock even for the tsb insert done by update_mmu_cache() now and that's a bit excessive. We can get rid of that locking, and the same lock taking in flush_tsb_user(), by disabling PSTATE_IE around the whole operation including the capturing of the tsb pointer and tsb_nentries value. That would work because anyone growing the TSB won't free up the old TSB until all cpus respond to the TSB change cross call. I'm not quite so confident in that optimization to put it in right now, but eventually we might be able to and the description is here for reference. This code seems very solid now. It passes several parallel GCC bootstrap builds, and our favorite "nut cruncher" stress test which is a full "make -j8192" build of a "make allmodconfig" kernel. That puts about 256 processes on each cpu's run queue, makes lots of process cpu migrations occur, causes lots of page table and TLB flushing activity, incurs many context version number changes, and it swaps the machine real far out to disk even though there is 16GB of ram on this test system. :-) Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix 32-bit truncation which broke sparsemem.David S. Miller2006-03-201-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The page->flags manipulations done by the D-cache dirty state tracking was broken because the constants were not marked with "UL" to make them 64-bit, which means we were clobbering the upper 32-bits of page->flags all the time. This doesn't jive well with sparsemem which stores the section and indexing information in the top 32-bits of page->flags. This is yet another sparc64 bug which has been with us forever. While we're here, tidy up some things in bootmem_init() and paginig_init(): 1) Pass min_low_pfn to init_bootmem_node(), it's identical to (phys_base >> PAGE_SHIFT) but we should use consistent with the variable names we print in CONFIG_BOOTMEM_DEBUG 2) max_mapnr, although no longer used, was being set inaccurately, we shouldn't subtract pfn_base any more. 3) All the games with phys_base in the zones_*[] arrays we pass to free_area_init_node() are no longer necessary. Thanks to Josh Grebe and Fabbione for the bug reports and testing. Fix also verified locally on an SB2500 which had a memory layout that triggered the same problem. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Move over to sparsemem.David S. Miller2006-03-201-36/+98
| | | | | | | | This has been pending for a long time, and the fact that we waste a ton of ram on some configurations kind of pushed things over the edge. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Bulletproof MMU context locking.David S. Miller2006-03-201-2/+3
| | | | | | | | | | | 1) Always spin_lock_init() in init_context(). The caller essentially clears it out, or copies the mm info from the parent. In both cases we need to explicitly initialize the spinlock. 2) Always do explicit IRQ disabling while taking mm->context.lock and ctx_alloc_lock. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix loop termination in mark_kpte_bitmap()David S. Miller2006-03-201-1/+4
| | | | | | | | | If we were aligned, but didn't have at least 256MB left to process, we would loop forever. Thanks to fabbione for the report and testing the fix. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Simplify TSB insert checks.David S. Miller2006-03-201-9/+6
| | | | | | | | | | | | Don't try to avoid putting non-base page sized entries into the user TSB. It actually costs us more to check this than it helps. Eventually we'll have a multiple TSB scheme for user processes. Once a process starts using larger pages, we'll allocate and use such a TSB. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Avoid dcache-dirty page state management on sun4v.David S. Miller2006-03-201-22/+28
| | | | | | | It is totally wasted work, since we have no D-cache aliasing issues on sun4v. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix TLB context allocation with SMT style shared TLBs.David S. Miller2006-03-201-1/+8
| | | | | | | | | | | | | | | The context allocation scheme we use depends upon there being a 1<-->1 mapping from cpu to physical TLB for correctness. Chips like Niagara break this assumption. So what we do is notify all cpus with a cross call when the context version number changes, and if necessary this makes them allocate a valid context for the address space they are running at the time. Stress tested with make -j1024, make -j2048, and make -j4096 kernel builds on a 32-strand, 8 core, T2000 with 16GB of ram. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Export _PAGE_E and _PAGE_CACHE to modules.David S. Miller2006-03-201-0/+4
| | | | | | | | SBUS flash driver needs it. Noticed by Fabbione. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Create a seperate kernel TSB for 4MB/256MB mappings.David S. Miller2006-03-201-5/+19
| | | | | | | | | | It can map all of the linear kernel mappings with zero TSB hash conflicts for systems with 16GB or less ram. In such cases, on SUN4V, once we load up this TSB the first time with all the mappings, we never take a linear kernel mapping TLB miss ever again, the hypervisor handles them all. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Make use of Niagara 256MB PTEs for kernel mappings.David S. Miller2006-03-201-13/+69
| | | | | | | | | | | We use a bitmap, one bit for every 256MB of memory. If the bit is set we can use a 256MB PTE for linear mappings, else we have to use a 4MB PTE. SUN4V support is there, and we can very easily add support for Panther cpu 256MB PTEs in the future. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Export a PAGE_SHARED symbol.David S. Miller2006-03-201-0/+5
| | | | | | For drivers/media/*, noticed by Fabbione. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: More TLB/TSB handling fixes.David S. Miller2006-03-201-1/+3
| | | | | | | | | | | | | | | The SUN4V convention with non-shared TSBs is that the context bit of the TAG is clear. So we have to choose an "invalid" bit and initialize new TSBs appropriately. Otherwise a zero TAG looks "valid". Make sure, for the window fixup cases, that we use the right global registers and that we don't potentially trample on the live global registers in etrap/rtrap handling (%g2 and %g6) and that we put the missing virtual address properly in %g5. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Check for errors in hypervisor_tlb_lock().David S. Miller2006-03-201-0/+5
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Set associativity of kernel TSB descriptor correctly.David S. Miller2006-03-201-1/+1
| | | | | | It should be 1, not 0. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Use phys tsb address in tsb_insert() in SUN4V.David S. Miller2006-03-201-1/+1
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Use inline patching for critical PTE operations.David S. Miller2006-03-201-208/+3
| | | | | | | This handles the SUN4U vs SUN4V PTE layout differences with near zero performance cost. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Move PTE field definitions back into asm/pgtable.hDavid S. Miller2006-03-201-84/+0
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Deal with PTE layout differences in SUN4V.David S. Miller2006-03-201-94/+609
| | | | | | | | | | Yes, you heard it right, they changed the PTE layout for SUN4V. Ho hum... This is the simple and inefficient way to support this. It'll get optimized, don't worry. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Register kernel TSB with hypervisor.David S. Miller2006-03-201-1/+69
| | | | | | We do this right after we take over the trap table from OBP. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Use ASI_SCRATCHPAD address 0x0 properly.David S. Miller2006-03-201-21/+1
| | | | | | | | | | | | | This is where the virtual address of the fault status area belongs. To set it up we don't make a hypervisor call, instead we call OBP's SUNW,set-trap-table with the real address of the fault status area as the second argument. And right before that call we write the virtual address into ASI_SCRATCHPAD vaddr 0x0. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix hypervisor call arg passing.David S. Miller2006-03-201-10/+10
| | | | | | Function goes in %o5, args go in %o0 --> %o5. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Detect sun4v early in boot process.David S. Miller2006-03-201-12/+46
| | | | | | | | | | | | | We look for "SUNW,sun4v" in the 'compatible' property of the root OBP device tree node. Protect every %ver register access, to make sure it is not touched on sun4v, as %ver is hyperprivileged there. Lock kernel TLB entries using hypervisor calls instead of calls into OBP. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Patch up mmu context register writes for sun4v.David S. Miller2006-03-201-9/+0
| | | | | | sun4v uses ASI_MMU instead of ASI_DMMU Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Register per-cpu fault status area with sun4v hypervisor.David S. Miller2006-03-201-4/+25
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Initial sun4v TLB miss handling infrastructure.David S. Miller2006-03-201-1/+23
| | | | | | | | | | Things are a little tricky because, unlike sun4u, we have to: 1) do a hypervisor trap to do the TLB load. 2) do the TSB lookup calculations by hand Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add some hypervisor tlb_type checks.David S. Miller2006-03-201-2/+4
| | | | | | | And more consistently check cheetah{,_plus} instead of assuming anything not spitfire is cheetah{,_plus}. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Turn off TSB growing for now.David S. Miller2006-03-201-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | There are several tricky races involved with growing the TSB. So just use base-size TSBs for user contexts and we can revisit enabling this later. One part of the SMP problems is that tsb_context_switch() can see partially updated TSB configuration state if tsb_grow() is running in parallel. That's easily solved with a seqlock taken as a writer by tsb_grow() and taken as a reader to capture all the TSB config state in tsb_context_switch(). Then there is flush_tsb_user() running in parallel with a tsb_grow(). In theory we could take the seqlock as a reader there too, and just resample the TSB pointer and reflush but that looks really ugly. Lastly, I believe there is a case with threads that results in a TSB entry lock bit being set spuriously which will cause the next access to that TSB entry to wedge the cpu (since the TSB entry lock bit will never clear). It's either copy_tsb() or some bug elsewhere in the TSB assembly. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Access TSB with physical addresses when possible.David S. Miller2006-03-201-0/+32
| | | | | | | | | | | | | This way we don't need to lock the TSB into the TLB. The trick is that every TSB load/store is registered into a special instruction patch section. The default uses virtual addresses, and the patch instructions use physical address load/stores. We can't do this on all chips because only cheetah+ and later have the physical variant of the atomic quad load. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill swapper_pgd_zero, totally unused.David S. Miller2006-03-201-3/+0
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill sole argument passed to setup_tba().David S. Miller2006-03-201-9/+2
| | | | | | No longer used, and move extern declaration to a header file. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill PROM locked TLB entry preservation code.David S. Miller2006-03-201-285/+10
| | | | | | | It is totally unnecessary complexity. After we take over the trap table, we handle all PROM tlb misses fully. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Preload TSB entries from update_mmu_cache().David S. Miller2006-03-201-0/+10
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Dynamically grow TSB in response to RSS growth.David S. Miller2006-03-201-0/+7
| | | | | | | | | As the RSS grows, grow the TSB in order to reduce the likelyhood of hash collisions and thus poor hit rates in the TSB. This definitely needs some serious tuning. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill pgtable quicklists and use SLAB.David S. Miller2006-03-201-17/+15
| | | | | | | | | Taking a nod from the powerpc port. With the per-cpu caching of both the page allocator and SLAB, the pgtable quicklist scheme becomes relatively silly and primitive. Signed-off-by: David S. Miller <davem@davemloft.net>
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