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* x86: move apic declarations to mach_apic.hGlauber Costa2008-04-171-1/+1
| | | | | | | take them out of the x86_64-specific asm/mach_apic.h Signed-off-by: Glauber Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: pat cpu feature bit setting for known cpusYinghai Lu2008-04-171-0/+25
| | | | | Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: tom2 warning fixIngo Molnar2008-04-171-2/+4
| | | | Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: enable PAT for amd k8 and fam10hYinghai Lu2008-04-172-1/+18
| | | | | | | | | make known_pat_cpu to think amd k8 and fam10h is ok too. also make tom2 below to be WRBACK Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: PAT infrastructure patchvenkatesh.pallipadi@intel.com2008-04-171-0/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sets up pat_init() infrastructure. PAT MSR has following setting. PAT |PCD ||PWT ||| 000 WB _PAGE_CACHE_WB 001 WC _PAGE_CACHE_WC 010 UC- _PAGE_CACHE_UC_MINUS 011 UC _PAGE_CACHE_UC We are effectively changing WT from boot time setting to WC. UC_MINUS is used to provide backward compatibility to existing /dev/mem users(X). reserve_memtype and free_memtype are new interfaces for maintaining alias-free mapping. It is currently implemented in a simple way with a linked list and not optimized. reserve and free tracks the effective memory type, as a result of PAT and MTRR setting rather than what is actually requested in PAT. pat_init piggy backs on mtrr_init as the rules for setting both pat and mtrr are same. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: introduce initial apicidYinghai Lu2008-04-172-7/+9
| | | | | | | | | | store initial_apicid from early identify. it is could be different from phys_proc_id later. also print it out in /proc/cpuinfo. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: show apicid for cpu in procYinghai Lu2008-04-171-0/+1
| | | | | Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: arch/x86/kernel/cpu/feature_names.c - use angle brackets for includeJoe Perches2008-04-171-1/+1
| | | | | Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: switch to proc_create()Alexey Dobriyan2008-04-171-4/+3
| | | | | Signed-off-by: Alexey Dobriyan <adobriyan@sw.ru> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: clean up cpu capabilities accesses, transmeta.cIngo Molnar2008-04-171-1/+1
| | | | Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: clean up cpu capabilities in arch/x86/kernel/cpu/intel.cIngo Molnar2008-04-171-7/+7
| | | | Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: clean up cpu capabilities accesses, cyrix.cIngo Molnar2008-04-171-6/+6
| | | | Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: clean up cpu capabilities accesses, common.cIngo Molnar2008-04-171-1/+1
| | | | Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: clean up cpu capabilities accesses, centaur.cIngo Molnar2008-04-171-7/+7
| | | | Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: clean up cpu capabilities accesses, amd.cIngo Molnar2008-04-171-12/+12
| | | | Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: clean up cpu capabilities accesses, genericIngo Molnar2008-04-171-1/+1
| | | | Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: coding style fixes to arch/x86/kernel/cpu/common.cPaolo Ciarrocchi2008-04-171-49/+56
| | | | | | | | | | | | | | | | | | | | | | Before: total: 55 errors, 6 warnings, 727 lines checked After: total: 0 errors, 3 warnings, 734 lines checked No code changed: arch/x86/kernel/cpu/common.o: text data bss dec hex filename 3500 4611 44 8155 1fdb common.o.before 3500 4611 44 8155 1fdb common.o.after md5: e37091f11fbeb682c0db152ac3022a38 common.o.before.asm e37091f11fbeb682c0db152ac3022a38 common.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: coding style fixes to arch/x86/kernel/cpu/cyrix.cPaolo Ciarrocchi2008-04-171-57/+56
| | | | | | | | | | | | | | | | | | | | | | Before: total: 46 errors, 10 warnings, 450 lines checked After: total: 1 errors, 10 warnings, 449 lines checked No code changed: arch/x86/kernel/cpu/cyrix.o: text data bss dec hex filename 2048 908 4 2960 b90 cyrix.o.before 2048 908 4 2960 b90 cyrix.o.after md5: 9add5e69dbd788f91ff24eea8462dad7 cyrix.o.before.asm 9add5e69dbd788f91ff24eea8462dad7 cyrix.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: coding style fixes to arch/x86/kernel/cpu/mcheck/mce_32.cPaolo Ciarrocchi2008-04-171-25/+25
| | | | | | | | | | | | | | | | | | | | | | Before: total: 10 errors, 3 warnings, 90 lines checked After: total: 0 errors, 3 warnings, 90 lines checked No code changed: arch/x86/kernel/cpu/mcheck/mce_32.o: text data bss dec hex filename 287 42 12 341 155 mce_32.o.before 287 42 12 341 155 mce_32.o.after md5: fede5ff8e6bc3f62e8e691ca6c45eb39 mce_32.o.before.asm fede5ff8e6bc3f62e8e691ca6c45eb39 mce_32.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: coding style fixes to arch/x86/kernel/cpu/mcheck/winchip.cPaolo Ciarrocchi2008-04-171-4/+4
| | | | | | | | | | | | | | | | | | | | | | Before: total: 4 errors, 0 warnings, 36 lines checked After: total: 0 errors, 0 warnings, 36 lines checked No code changed: arch/x86/kernel/cpu/mcheck/winchip.o: text data bss dec hex filename 222 0 4 226 e2 winchip.o.before 222 0 4 226 e2 winchip.o.after md5: 9caefa12256c5f7d71ef324f6d01a2d5 winchip.o.before.asm 9caefa12256c5f7d71ef324f6d01a2d5 winchip.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: coding style fixes to arch/x86/kernel/cpu/mcheck/non-fatal.cPaolo Ciarrocchi2008-04-171-9/+12
| | | | | | | | | | | | | | | | | | | | | | Before: total: 5 errors, 5 warnings, 91 lines checked After: total: 0 errors, 0 warnings, 94 lines checked No code changed: arch/x86/kernel/cpu/mcheck/non-fatal.o: text data bss dec hex filename 441 80 4 525 20d non-fatal.o.before 441 80 4 525 20d non-fatal.o.after md5: 137bc114d2020ad331d5e76444a2c7d3 non-fatal.o.before.asm 137bc114d2020ad331d5e76444a2c7d3 non-fatal.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: coding style fixes to arch/x86/kernel/cpu/amd.cPaolo Ciarrocchi2008-04-171-46/+48
| | | | | | | | | | | | | | | | | | | | | | Before: total: 42 errors, 26 warnings, 350 lines checked After: total: 0 errors, 26 warnings, 352 lines checked No code changed: arch/x86/kernel/cpu/amd.o: text data bss dec hex filename 1936 328 0 2264 8d8 amd.o.before 1936 328 0 2264 8d8 amd.o.after md5: 873430a88faaf31bb4bbfe3a2a691e45 amd.o.before.asm 873430a88faaf31bb4bbfe3a2a691e45 amd.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: coding style fixes to arch/x86/kernel/cpu/transmeta.cPaolo Ciarrocchi2008-04-171-10/+12
| | | | | | | | | | | | | | | | | | | | | | Before: total: 13 errors, 3 warnings, 105 lines checked After: total: 0 errors, 3 warnings, 107 lines checked No code changed: arch/x86/kernel/cpu/transmeta.o: text data bss dec hex filename 713 324 0 1037 40d transmeta.o.before 713 324 0 1037 40d transmeta.o.after md5: 19abe2cafac617e1e2aadc4aa4e9923b transmeta.o.before.asm 19abe2cafac617e1e2aadc4aa4e9923b transmeta.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: coding style fixes to arch/x86/kernel/cpu/mtrr/state.cPaolo Ciarrocchi2008-04-171-6/+8
| | | | | | | | | | | | | | | | | | | | | | Before: total: 6 errors, 5 warnings, 80 lines checked After: total: 0 errors, 4 warnings, 82 lines checked No code changed: arch/x86/kernel/cpu/mtrr/state.o: text data bss dec hex filename 313 0 4 317 13d state.o.before 313 0 4 317 13d state.o.after md5: a0fbd61096205f9180f0bf45ed386d61 state.o.before.asm a0fbd61096205f9180f0bf45ed386d61 state.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: coding style fixes to arch/x86/kernel/cpu/intel.cPaolo Ciarrocchi2008-04-171-40/+43
| | | | | | | | | | | | | | | | | | | | | | Before: total: 37 errors, 16 warnings, 366 lines checked After: total: 0 errors, 15 warnings, 369 lines checked No code changed: arch/x86/kernel/cpu/intel.o: text data bss dec hex filename 1534 452 0 1986 7c2 intel.o.before 1534 452 0 1986 7c2 intel.o.after md5: 1ca348a06de6eb354c4b6ea715a57db5 intel.o.before.asm 1ca348a06de6eb354c4b6ea715a57db5 intel.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: coding style fixes to arch/x86/kernel/cpu/umc.cPaolo Ciarrocchi2008-04-171-5/+7
| | | | | | | | | | | | | | | | | | | | | | Before: total: 3 errors, 1 warnings, 23 lines checked After: total: 0 errors, 0 warnings, 25 lines checked No code changed: arch/x86/kernel/cpu/umc.o: text data bss dec hex filename 24 616 0 640 280 umc.o.before 24 616 0 640 280 umc.o.after md5: e8daa3eaed0963a0cdd2e83c2e1f9823 umc.o.before.asm e8daa3eaed0963a0cdd2e83c2e1f9823 umc.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: coding style fixes to arch/x86/kernel/cpu/mcheck/p6.cPaolo Ciarrocchi2008-04-171-24/+24
| | | | | | | | | | | | | | | | | | | | | | Before: total: 16 errors, 13 warnings, 122 lines checked After: total: 0 errors, 0 warnings, 122 lines checked No code changed: arch/x86/kernel/cpu/mcheck/p6.o: text data bss dec hex filename 1082 0 8 1090 442 p6.o.before 1082 0 8 1090 442 p6.o.after md5: 4e283fbc1b68240f1724d9725007d379 p6.o.before.asm 4e283fbc1b68240f1724d9725007d379 p6.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: unify cpu/proc|_64.cHiroshi Shimamoto2008-04-172-183/+2
| | | | | | | | Now cpu/proc.c and cpu/proc_64.c are same. So cpu/proc_64.c can be removed. Signed-off-by: Hiroshi Shimamoto <h-shimamoto@ct.jp.nec.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: cosmetic unification cpu/proc|_64.cHiroshi Shimamoto2008-04-172-2/+83
| | | | | | | make cpu/proc.c and cpu/proc_64.c same. Signed-off-by: Hiroshi Shimamoto <h-shimamoto@ct.jp.nec.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: add power management line in /proc/cpuinfoHiroshi Shimamoto2008-04-171-5/+9
| | | | | | | | | Change /proc/cpuinfo on 32-bit, it will look like on 64-bit. 'power management' line is added and power management information will be printed at the line. Signed-off-by: Hiroshi Shimamoto <h-shimamoto@ct.jp.nec.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: make cpu/proc|_64.c similarHiroshi Shimamoto2008-04-172-78/+105
| | | | | | | clean up for unification. Signed-off-by: Hiroshi Shimamoto <h-shimamoto@ct.jp.nec.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: split cpuinfo from setup_64.c into cpu/proc_64.cHiroshi Shimamoto2008-04-172-0/+127
| | | | | | | | x86 /proc/cpuinfo code can be unified. This is the first step of unification. Signed-off-by: Hiroshi Shimamoto <h-shimamoto@ct.jp.nec.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: coding style fixes to arch/x86/kernel/cpu/nexgen.cPaolo Ciarrocchi2008-04-171-8/+7
| | | | | | | | | | | | | arch/x86/kernel/cpu/nexgen.o: text data bss dec hex filename 111 316 0 427 1ab nexgen.o.before 111 316 0 427 1ab nexgen.o.after md5: e796efefea9ebc6644338bad226599ee nexgen.o.before.asm e796efefea9ebc6644338bad226599ee nexgen.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: coding style fixes to arch/x86/kernel/cpu/mcheck/p5.cPaolo Ciarrocchi2008-04-171-8/+8
| | | | | | | | | | | | | | | | The patch make the file errors free. Only 4 "WARNING: line over 80 characters" left. arch/x86/kernel/cpu/mcheck/p5.o: text data bss dec hex filename 452 0 4 456 1c8 p5.o.before 452 0 4 456 1c8 p5.o.after md5: 50c945ef150aa95bf0481cc3e1dc3315 p5.o.before.asm 50c945ef150aa95bf0481cc3e1dc3315 p5.o.after.asm Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: more coding style fixes in centaur.cIngo Molnar2008-04-171-195/+199
| | | | | | | | | | | | | | | | no code changed: arch/x86/kernel/cpu/centaur.o: text data bss dec hex filename 1031 324 0 1355 54b centaur.o.before 1031 324 0 1355 54b centaur.o.after md5: 4f306a7f980b58eb69c4bdcfcde565f1 centaur.o.before.asm 4f306a7f980b58eb69c4bdcfcde565f1 centaur.o.after.asm Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: coding style fixes for arch/x86/kernel/cpu/centaur.cPaolo Ciarrocchi2008-04-171-116/+114
| | | | | | | | Kills more than 150 errors/warnings Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: use ELF section to list CPU vendor specific codeThomas Petazzoni2008-04-178-69/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | Replace the hardcoded list of initialization functions for each CPU vendor by a list in an ELF section, which is read at initialization in arch/x86/kernel/cpu/cpu.c to fill the cpu_devs[] array. The ELF section, named .x86cpuvendor.init, is reclaimed after boot, and contains entries of type "struct cpu_vendor_dev" which associates a vendor number with a pointer to a "struct cpu_dev" structure. This first modification allows to remove all the VENDOR_init_cpu() functions. This patch also removes the hardcoded calls to early_init_amd() and early_init_intel(). Instead, we add a "c_early_init" member to the cpu_dev structure, which is then called if not NULL by the generic CPU initialization code. Unfortunately, in early_cpu_detect(), this_cpu is not yet set, so we have to use the cpu_devs[] array directly. This patch is part of the Linux Tiny project, and is needed for further patch that will allow to disable compilation of unused CPU support code. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* Fix booting pentium+ with dodgy TSCRusty Russell2008-04-061-8/+0
| | | | | | | | | | We handle a broken tsc these days, so no need to panic. We clear the TSC bit when tsc_init decides it's unreliable (eg. under lguest w/ bad host TSC), leading to bogus panic. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Acked-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* x86: print message if nmi_watchdog=2 cannot be enabledIngo Molnar2008-04-041-1/+3
| | | | | | | | | right now if there's no CPU support for nmi_watchdog=2 we'll just refuse it silently. print a useful warning. Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: fix nmi_watchdog=2 on Pentium-D CPUsIngo Molnar2008-04-041-3/+0
| | | | | | | | | | | | | implement nmi_watchdog=2 on this class of CPUs: cpu family : 15 model : 6 model name : Intel(R) Pentium(R) D CPU 3.00GHz the watchdog's ->setup() method is safe anyway, so if the CPU cannot support it we'll bail out safely. Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86, cpufreq: fix Speedfreq-SMI call that clobbers ECXStephan Diestelhorst2008-03-261-15/+24
| | | | | | | | | | | | | I have found that using SMI to change the cpu's frequency on my DELL Latitude L400 clobbers the ECX register in speedstep_set_state, causing unneccessary retries because the "state" variable has changed silently (GCC assumes it is still present in ECX). play safe and avoid gcc caching any register across IO port accesses that trigger SMIs. Signed-off by: <Stephan.Diestelhorst@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: convert mtrr/generic.c to kernel-docRandy Dunlap2008-03-261-19/+23
| | | | | | | | Convert function comment blocks to kernel-doc notation. Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: trim mtrr don't close gap for resource allocation.Yinghai Lu2008-03-211-1/+2
| | | | | | | | | | | | | | | | fix the bug reported here: http://bugzilla.kernel.org/show_bug.cgi?id=10232 use update_memory_range() instead of add_memory_range() directly to avoid closing the gap. ( the new code only affects and runs on systems where the MTRR workaround triggers. ) Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* [CPUFREQ] Remove debugging message from e_powersaverDave Jones2008-03-051-2/+6
| | | | | | | | | We don't need to printk a message every time we transition. Leave the code there, but ifdef'd out, as it's useful when adding support for new processors. Reported-by: Petr Titěra <P.Titera@century.cz> Signed-off-by: Dave Jones <davej@redhat.com>
* x86: fix boot failure on 486 due to TSC breakageMikael Pettersson2008-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | > Diffing dmesg between git7 and git8 doesn't sched any light since > git8 also removed the printouts of the x86 caps as they were being > initialised and updated. I'm currently adding those printouts back > in the hope of seeing where and when the caps get broken. That turned out to be very illuminating: --- dmesg-2.6.24-git7 2008-02-24 18:01:25.295851000 +0100 +++ dmesg-2.6.24-git8 2008-02-24 18:01:25.530358000 +0100 ... CPU: After generic identify, caps: 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 CPU: After all inits, caps: 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 +CPU: After applying cleared_cpu_caps, caps: 00000013 00000000 00000000 00000000 00000000 00000000 00000000 00000000 Notice how the TSC cap bit goes from Off to On. (The first two lines are printout loops from -git7 forward-ported to -git8, the third line is the same printout loop added just after the xor-with-cleared_cpu_caps[] loop.) Here's how the breakage occurs: 1. arch/x86/kernel/tsc_32.c:tsc_init() sees !cpu_has_tsc, so bails and calls setup_clear_cpu_cap(X86_FEATURE_TSC). 2. include/asm-x86/cpufeature.h:setup_clear_cpu_cap(bit) clears the bit in boot_cpu_data and sets it in cleared_cpu_caps 3. arch/x86/kernel/cpu/common.c:identify_cpu() XORs all caps in with cleared_cpu_caps HOWEVER, at this point c->x86_capability correctly has TSC Off, cleared_cpu_caps has TSC On, so the XOR incorrectly sets TSC to On in c->x86_capability, with disastrous results. The real bug is that clearing bits with XOR only works if the bits are known to be 1 prior to the XOR, and that's not true here. A simple fix is to convert the XOR to AND-NOT instead. The following patch does that, and allows my 486 to boot 2.6.25-rc kernels again. [ mingo@elte.hu: fixed a similar bug in setup_64.c as well. ] The breakage was introduced via commit 7d851c8d3db0. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: don't print a warning when MTRR are blank and running in KVMJoerg Roedel2008-02-261-2/+6
| | | | | | | | | Inside a KVM virtual machine the MTRRs are usually blank. This confuses Linux and causes a warning message at boot. This patch removes that warning message when running Linux as a KVM guest. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86/mtrr: fix kernel-doc missing notationRandy Dunlap2008-02-261-0/+1
| | | | | | | | Fix mtrr kernel-doc warning: Warning(linux-2.6.24-git12//arch/x86/kernel/cpu/mtrr/main.c:677): No description found for parameter 'end_pfn' Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* x86: do not promote TM3x00/TM5x00 to i686-classH. Peter Anvin2008-02-261-7/+0
| | | | | | | | | | | | | We have been promoting Transmeta TM3x00/TM5x00 chips to i686-class based on the notion that they contain all the user-space visible features of an i686-class chip. However, this is not actually true: they lack the EA-taking long NOPs (0F 1F /0). Since this is a userspace-visible incompatibility, downgrade these CPUs to the manufacturer-defined i586 level. Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* remove mca-pentiumAdrian Bunk2008-02-191-8/+0
| | | | | | | | | | | | | | | This patch removes the mca-pentium boot option that was a noop. besides the source code cleanup factor, this saves some text as well: arch/x86/kernel/cpu/bugs.o: text data bss dec hex filename 651 77 4 732 2dc bugs.o.before 631 53 4 688 2b0 bugs.o.after Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* x86: sparse warning in therm_throt.cHarvey Harrison2008-02-091-1/+1
| | | | | | | | arch/x86/kernel/cpu/mcheck/therm_throt.c:121:2: warning: returning void-valued expression Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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