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path: root/drivers/gpu/drm/nouveau/nv50_fifo.c
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* drm/nv50: fix RAMHT sizeBen Skeggs2010-07-131-1/+3
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: cleanup nv50_fifo.cBen Skeggs2010-07-131-67/+40
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: add instmem flush() hookBen Skeggs2010-07-131-12/+3
| | | | | | | | | | This removes the previous prepare_access() and finish_access() hooks, and replaces it with a much simpler flush() hook. All the chipset-specific code before nv50 has its use removed completely, as it's not required there at all. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: switch to indirect push buffer controlsBen Skeggs2010-02-251-4/+4
| | | | | | | | | | | | | | | PFIFO on G80 and up has a new mode where the main ring buffer is simply a ring of pointers to indirect buffers containing the actual command/data packets. In order to be able to implement index buffers in the 3D driver we need to be able to submit data-only push buffers right after the cmd packet header, which is only possible using the new command submission method. This commit doesn't make it possible to implement index buffers yet, some userspace interface changes will be required, but it does allow for testing/debugging of the hardware-side support in the meantime. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: protect channel create/destroy and irq handler with a spinlockMaarten Maathuis2010-02-251-0/+5
| | | | | | | | | The nv50 pgraph handler (for example) could reenable pgraph fifo access and that would be bad when pgraph context is being unloaded (we need the guarantee a ctxprog isn't running). Signed-off-by: Maarten Maathuis <madman2003@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: delete ramfc object after disabling fifo, not beforeMaarten Maathuis2010-02-101-3/+6
| | | | | | | | ramfc is zero'ed upon destruction, so it's safer to do things in the right order. Signed-off-by: Maarten Maathuis <madman2003@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: fix alignment of per-channel fifo cacheBen Skeggs2010-01-181-1/+1
| | | | | | | | GPU pointer to the structure is shifted right by 10 bits, so we need to align to 1024 bytes, not 256. Reported-by: Maarten Maathuis <madman2003@gmail.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: restore correct cache1 get/put address on fifoctx loadBen Skeggs2010-01-111-4/+2
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nv50: fix two potential suspend/resume oopsesBen Skeggs2009-12-161-1/+1
| | | | | | This avoids touching the dummy channel 0/127 we have on nv50. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: Add DRM driver for NVIDIA GPUsBen Skeggs2009-12-111-0/+494
This adds a drm/kms staging non-API stable driver for GPUs from NVIDIA. This driver is a KMS-based driver and requires a compatible nouveau userspace libdrm and nouveau X.org driver. This driver requires firmware files not available in this kernel tree, interested parties can find them via the nouveau project git archive. This driver is reverse engineered, and is in no way supported by nVidia. Support for nearly the complete range of nvidia hw from nv04->g80 (nv50) is available, and the kms driver should support driving nearly all output types (displayport is under development still) along with supporting suspend/resume. This work is all from the upstream nouveau project found at nouveau.freedesktop.org. The original authors list from nouveau git tree is: Anssi Hannula <anssi.hannula@iki.fi> Ben Skeggs <bskeggs@redhat.com> Francisco Jerez <currojerez@riseup.net> Maarten Maathuis <madman2003@gmail.com> Marcin Koƛcielnicki <koriakin@0x04.net> Matthew Garrett <mjg@redhat.com> Matt Parnell <mparnell@gmail.com> Patrice Mandin <patmandin@gmail.com> Pekka Paalanen <pq@iki.fi> Xavier Chantry <shiningxc@gmail.com> along with project founder Stephane Marchesin <marchesin@icps.u-strasbg.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>