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* Revert "Revert "mmc: Set suspend/resume bus operations if CONFIG_PM_RUNTIME ↵Todd Poynor2012-01-241-17/+7
| | | | | | | | | is used"" This reverts commit c96f99d7907853ffb7e29915954dfc38b912fa2c. Change-Id: I1953ba2fda5519023f3d173492b0ea6ce8e33c49 Signed-off-by: Todd Poynor <toddpoynor@google.com>
* Revert "mmc: Set suspend/resume bus operations if CONFIG_PM_RUNTIME is used"Ken Sumrall2012-01-181-7/+17
| | | | | | This reverts commit ea693bf7f87603b072f4ceea6684221fa0b8e863. We are reverting this change to see if it clears up some filesystem corruption we are seeing.
* mmc: Set suspend/resume bus operations if CONFIG_PM_RUNTIME is usedDmitry Shmidt2011-12-191-17/+7
| | | | Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
* Merge commit 'v3.0.8' into android-3.0Colin Cross2011-10-273-14/+41
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| * mmc: core: use non-reentrant workqueue for clock gatingMika Westerberg2011-10-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 50a50f9248497484c678631a9c1a719f1aaeab79 upstream. The default multithread workqueue can cause the same work to be executed concurrently on a different CPUs. This isn't really suitable for clock gating as it might already gated the clock and gating it twice results both host->clk_old and host->ios.clock to be set to 0. To prevent this from happening we use system_nrt_wq instead. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Chris Ball <cjb@laptop.org> Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * mmc: core: prevent aggressive clock gating racing with ios updatesMika Westerberg2011-10-031-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 778e277cb82411c9002ca28ccbd216c4d9eb9158 upstream. We have seen at least two different races when clock gating kicks in in a middle of ios structure update. First one happens when ios->clock is changed outside of aggressive clock gating framework, for example via mmc_set_clock(). The race might happen when we run following code: mmc_set_ios(): ... if (ios->clock > 0) mmc_set_ungated(host); Now if gating kicks in right after the condition check we end up setting host->clk_gated to false even though we have just gated the clock. Next time a request is started we try to ungate and restore the clock in mmc_host_clk_hold(). However since we have host->clk_gated set to false the original clock is not restored. This eventually will cause the host controller to hang since its clock is disabled while we are trying to issue a request. For example on Intel Medfield platform we see: [ 13.818610] mmc2: Timeout waiting for hardware interrupt. [ 13.818698] sdhci: =========== REGISTER DUMP (mmc2)=========== [ 13.818753] sdhci: Sys addr: 0x00000000 | Version: 0x00008901 [ 13.818804] sdhci: Blk size: 0x00000000 | Blk cnt: 0x00000000 [ 13.818853] sdhci: Argument: 0x00000000 | Trn mode: 0x00000000 [ 13.818903] sdhci: Present: 0x1fff0000 | Host ctl: 0x00000001 [ 13.818951] sdhci: Power: 0x0000000d | Blk gap: 0x00000000 [ 13.819000] sdhci: Wake-up: 0x00000000 | Clock: 0x00000000 [ 13.819049] sdhci: Timeout: 0x00000000 | Int stat: 0x00000000 [ 13.819098] sdhci: Int enab: 0x00ff00c3 | Sig enab: 0x00ff00c3 [ 13.819147] sdhci: AC12 err: 0x00000000 | Slot int: 0x00000000 [ 13.819196] sdhci: Caps: 0x6bee32b2 | Caps_1: 0x00000000 [ 13.819245] sdhci: Cmd: 0x00000000 | Max curr: 0x00000000 [ 13.819292] sdhci: Host ctl2: 0x00000000 [ 13.819331] sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x00000000 [ 13.819377] sdhci: =========================================== [ 13.919605] mmc2: Reset 0x2 never completed. and it never recovers. Second race might happen while running mmc_power_off(): static void mmc_power_off(struct mmc_host *host) { host->ios.clock = 0; host->ios.vdd = 0; [ clock gating kicks in here ] /* * Reset ocr mask to be the highest possible voltage supported for * this mmc host. This value will be used at next power up. */ host->ocr = 1 << (fls(host->ocr_avail) - 1); if (!mmc_host_is_spi(host)) { host->ios.bus_mode = MMC_BUSMODE_OPENDRAIN; host->ios.chip_select = MMC_CS_DONTCARE; } host->ios.power_mode = MMC_POWER_OFF; host->ios.bus_width = MMC_BUS_WIDTH_1; host->ios.timing = MMC_TIMING_LEGACY; mmc_set_ios(host); } If the clock gating worker kicks in while we are only partially updated the ios structure the host controller gets incomplete ios and might not work as supposed. Again on Intel Medfield platform we get: [ 4.185349] kernel BUG at drivers/mmc/host/sdhci.c:1155! [ 4.185422] invalid opcode: 0000 [#1] PREEMPT SMP [ 4.185509] Modules linked in: [ 4.185565] [ 4.185608] Pid: 4, comm: kworker/0:0 Not tainted 3.0.0+ #240 Intel Corporation Medfield/iCDKA [ 4.185742] EIP: 0060:[<c136364e>] EFLAGS: 00010083 CPU: 0 [ 4.185827] EIP is at sdhci_set_power+0x3e/0xd0 [ 4.185891] EAX: f5ff98e0 EBX: f5ff98e0 ECX: 00000000 EDX: 00000001 [ 4.185970] ESI: f5ff977c EDI: f5ff9904 EBP: f644fe98 ESP: f644fe94 [ 4.186049] DS: 007b ES: 007b FS: 00d8 GS: 0000 SS: 0068 [ 4.186125] Process kworker/0:0 (pid: 4, ti=f644e000 task=f644c0e0 task.ti=f644e000) [ 4.186219] Stack: [ 4.186257] f5ff98e0 f644feb0 c1365173 00000282 f5ff9460 f5ff96e0 f5ff96e0 f644feec [ 4.186418] c1355bd8 f644c0e0 c1499c3d f5ff96e0 f644fed4 00000006 f5ff96e0 00000286 [ 4.186579] f644fedc c107922b f644feec 00000286 f5ff9460 f5ff9700 f644ff10 c135839e [ 4.186739] Call Trace: [ 4.186802] [<c1365173>] sdhci_set_ios+0x1c3/0x340 [ 4.186883] [<c1355bd8>] mmc_gate_clock+0x68/0x120 [ 4.186963] [<c1499c3d>] ? _raw_spin_unlock_irqrestore+0x4d/0x60 [ 4.187052] [<c107922b>] ? trace_hardirqs_on+0xb/0x10 [ 4.187134] [<c135839e>] mmc_host_clk_gate_delayed+0xbe/0x130 [ 4.187219] [<c105ec09>] ? process_one_work+0xf9/0x5b0 [ 4.187300] [<c135841d>] mmc_host_clk_gate_work+0xd/0x10 [ 4.187379] [<c105ec82>] process_one_work+0x172/0x5b0 [ 4.187457] [<c105ec09>] ? process_one_work+0xf9/0x5b0 [ 4.187538] [<c1358410>] ? mmc_host_clk_gate_delayed+0x130/0x130 [ 4.187625] [<c105f3c8>] worker_thread+0x118/0x330 [ 4.187700] [<c1496cee>] ? preempt_schedule+0x2e/0x50 [ 4.187779] [<c105f2b0>] ? rescuer_thread+0x1f0/0x1f0 [ 4.187857] [<c1062cf4>] kthread+0x74/0x80 [ 4.187931] [<c1062c80>] ? __init_kthread_worker+0x60/0x60 [ 4.188015] [<c149acfa>] kernel_thread_helper+0x6/0xd [ 4.188079] Code: 81 fa 00 00 04 00 0f 84 a7 00 00 00 7f 21 81 fa 80 00 00 00 0f 84 92 00 00 00 81 fa 00 00 0 [ 4.188780] EIP: [<c136364e>] sdhci_set_power+0x3e/0xd0 SS:ESP 0068:f644fe94 [ 4.188898] ---[ end trace a7b23eecc71777e4 ]--- This BUG() comes from the fact that ios.power_mode was still in previous value (MMC_POWER_ON) and ios.vdd was set to zero. We prevent these by inhibiting the clock gating while we update the ios structure. Both problems can be reproduced by simply running the device in a reboot loop. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Chris Ball <cjb@laptop.org> Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * mmc: rename mmc_host_clk_{ungate|gate} to mmc_host_clk_{hold|release}Mika Westerberg2011-10-033-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 08c14071fda4e69abb9d5b1566651cd092b158d3 upstream. As per suggestion by Linus Walleij: > If you think the names of the functions are confusing then > you may rename them, say like this: > > mmc_host_clk_ungate() -> mmc_host_clk_hold() > mmc_host_clk_gate() -> mmc_host_clk_release() > > Which would make the usecases more clear (This is CC'd to stable@ because the next two patches, which fix observable races, depend on it.) Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* | mmc: core: host: only use wakelock for detect workColin Cross2011-09-072-17/+16
| | | | | | | | | | | | | | | | | | | | | | There is no need to take a wakelock for delayed lazy disable work, it will be cancelled in the suspend handler and force disabled. Only take the wakelock when the detect work is queued, and make sure to drop the wakelock if the work is cancelled. Change-Id: I1e507a5f98848954ea21d45e23b6192c3132a349 Signed-off-by: Colin Cross <ccross@android.com>
* | Merge commit 'v3.0' into android-3.0Colin Cross2011-08-101-27/+50
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| * mmc: core: Bus width testing needs to handle suspend/resumePhilip Rakity2011-07-131-27/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On reading the ext_csd for the first time (in 1 bit mode), save the ext_csd information needed for bus width compare. On every pass we make re-reading the ext_csd, compare the data against the saved ext_csd data. This fixes a regression introduced in 3.0-rc1 by 08ee80cc397ac1a3 ("mmc: core: eMMC bus width may not work on all platforms"), which incorrectly assumed we would be re-reading the ext_csd at resume- time. Signed-off-by: Philip Rakity <prakity@marvell.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* | Merge commit 'v3.0-rc5' into android-3.0Colin Cross2011-06-293-2/+41
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| * mmc: core: make erase timeout calculation allow for gated clockAdrian Hunter2011-06-251-1/+1
| | | | | | | | | | | | | | | | | | The erase timeout calculation may depend on clock rate which is zero if the clock is gated, so use mmc_host_clk_rate() which allows for that case. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdio: reset card during power_restoreDaniel Drake2011-06-251-0/+39
| | | | | | | | | | | | | | | | | | mmc_sdio_power_restore() skips some steps that are performed in other power-related codepaths which are necessary to fully reset the card. Without this, runtime PM fails for SD8686 SDIO wifi on OLPC XO-1.5. Signed-off-by: Daniel Drake <dsd@laptop.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdio: fix runtime PM path during driver removalOhad Ben-Cohen2011-06-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After commit e1866b3 "PM / Runtime: Rework runtime PM handling during driver removal" was introduced, the driver core stopped incrementing the runtime PM usage counter of the device during the invocation of the ->remove() callback. This indirectly broke SDIO's runtime PM path during driver removal, because no one calls _put_sync() anymore after ->remove() completes. This means that the power of runtime-PM-managed SDIO cards is kept high after their driver is removed (even if it was powered down beforehand). Fix that by directly calling _put_sync() when the last usage counter is downref'ed by the SDIO bus. Reported-and-tested-by: Daniel Drake <dsd@laptop.org> Signed-off-by: Ohad Ben-Cohen <ohad@wizery.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* | Revert "mmc: subtract boot sectors from disk size for eMMC 4.3+ devices"Colin Cross2011-06-141-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit f0b0e4bec1e89014f3dcef4da8bcf95428cc771c. The reverted commit incorrectly calculates the size of eMMC devices in some (all?) cases. This revert may cause problems in cases where the bootloader was bug-compatible and puts a GPT partition at the incorrect end of the eMMC device. Signed-off-by: Colin Cross <ccross@android.com>
* | mmc: Fix pm_notifier obeying deferred resumeDmitry Shmidt2011-06-141-1/+15
| | | | | | | | Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
* | mmc: Add "ignore mmc pm notify" functionalityDmitry Shmidt2011-06-141-2/+5
| | | | | | | | Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
* | mmc: sdio: Fix enable_hs and enable_wide in sdio_reset_comm()Dmitry Shmidt2011-06-141-15/+10
| | | | | | | | Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
* | mmc: subtract boot sectors from disk size for eMMC 4.3+ devicesGary King2011-06-141-1/+6
| | | | | | | | | | | | | | | | | | the csd sector count reported by eMMC 4.3+ cards includes the boot partition size; subtract this from the size reported to the disk since the boot partition is inaccessible Change-Id: I601b83aa0159b7aa446409ea8c945b256dd0b5b1 Signed-off-by: Gary King <gking@nvidia.com>
* | mmc: core: Release delayed mmc work wakelock after deep disableSan Mehat2011-06-141-1/+4
| | | | | | | | Signed-off-by: San Mehat <san@google.com>
* | mmc: sdio: Add high speed support to sdio_reset_comm()Daniel Chen2011-06-141-1/+22
| | | | | | | | Signed-off-by: San Mehat <san@google.com>
* | mmc: sdio: Claim host in sdio_reset_comm()Dmitry Shmidt2011-06-141-4/+5
| | | | | | | | Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
* | mmc: mmcblk: Add support for deferred SD bus resumeSan Mehat2011-06-141-0/+6
| | | | | | | | | | | | | | | | Signed-off-by: San Mehat <san@google.com> mmc: card: Add MMC_BLOCK_DEFERRED_RESUME option to Kconfig Signed-off-by: San Mehat <san@google.com>
* | mmc: core: Add deferred bus resume policy.San Mehat2011-06-141-0/+33
| | | | | | | | | | | | | | | | | | A card driver can now specify that the underlying bus should *not* auto-resume with the rest of the system. This is useful for reducing resume latency as well as saving power when the card driver is not using the bus. In the future, we'll add support for manual suspend Signed-off-by: San Mehat <san@google.com>
* | mmc: core: Hold a wake lock accross delayed work + mmc rescanSan Mehat2011-06-141-1/+16
| | | | | | | | | | | | | | | | Signed-off-by: San Mehat <san@android.com> mmc: core: Rework mmc_delayed_work wakelock so that the wakelock is only extended if a card is added or removed. Signed-off-by: San Mehat <san@google.com>
* | mmc: sd: Add retries in re-detectionSan Mehat2011-06-141-6/+45
| | | | | | | | | | | | | | | | Signed-off-by: San Mehat <san@android.com> mmc: sd: Remove debugging printk Signed-off-by: Dima Zavin <dima@android.com>
* | mmc: sd: When resuming, try a little harder to init the cardSan Mehat2011-06-141-0/+19
| | | | | | | | Signed-off-by: San Mehat <san@android.com>
* | mmc: Add new API call 'sdio_reset_comm' for resetting communication with an ↵San Mehat2011-06-141-0/+57
| | | | | | | | | | | | SDIO device Signed-off-by: San Mehat <san@android.com>
* | trout: Add functions for WiFiDmitry Shmidt2011-06-141-0/+33
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* | mmc: Add concept of an 'embedded' SDIO device.San Mehat2011-06-144-17/+95
| | | | | | | | | | | | | | | | | | | | | | This is required to support chips which use SDIO for signaling/ communication but do not implement the various card enumeration registers as required for full SD / SDIO cards. mmc: sdio: Fix bug where we're freeing the CIS tables we never allocated when using EMBEDDED_SDIO mmc: Add max_blksize to embedded SDIO data Signed-off-by: San Mehat <san@google.com>
* | mmc: sd: Add new CONFIG_MMC_PARANOID_SD_INIT for enabling retries during SD ↵San Mehat2011-06-142-0/+30
|/ | | | | | detection Signed-off-by: San Mehat <san@google.com>
* Merge branch 'for-linus' of ↵Linus Torvalds2011-05-2514-258/+764
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc: (75 commits) mmc: core: eMMC bus width may not work on all platforms mmc: sdhci: Auto-CMD23 fixes. mmc: sdhci: Auto-CMD23 support. mmc: core: Block CMD23 support for UHS104/SDXC cards. mmc: sdhci: Implement MMC_CAP_CMD23 for SDHCI. mmc: core: Use CMD23 for multiblock transfers when we can. mmc: quirks: Add/remove quirks conditional support. mmc: Add new VUB300 USB-to-SD/SDIO/MMC driver mmc: sdhci-pxa: Add quirks for DMA/ADMA to match h/w mmc: core: duplicated trial with same freq in mmc_rescan_try_freq() mmc: core: add support for eMMC Dual Data Rate mmc: core: eMMC signal voltage does not use CMD11 mmc: sdhci-pxa: add platform code for UHS signaling mmc: sdhci: add hooks for setting UHS in platform specific code mmc: core: clear MMC_PM_KEEP_POWER flag on resume mmc: dw_mmc: fixed wrong regulator_enable in suspend/resume mmc: sdhi: allow powering down controller with no card inserted mmc: tmio: runtime suspend the controller, where possible mmc: sdhi: support up to 3 interrupt sources mmc: sdhi: print physical base address and clock rate ...
| * mmc: core: eMMC bus width may not work on all platformsPhilip Rakity2011-05-251-10/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CMD19 -- The offical way to validate bus widths from the JEDEC spec does not work on all platforms. Some platforms that use PCI/PCIe to connect their SD controllers are known to fail. If the quirk MMC_BUS_WIDTH_TEST is not defined we try to figure out the bus width by reading the ext_csd at different bus widths and compare this against the ext_csd read in 1 bit mode. If no ext_csd is available we default to 1 bit operations. Code has been tested on mmp2 against 8 bit eMMC and Transcend 2GB card that is known to not work in 4 bit mode. The physical pins on the card are not present to support 4 bit operation. Signed-off-by: Philip Rakity <prakity@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: core: Block CMD23 support for UHS104/SDXC cards.Andrei Warkentin2011-05-251-0/+2
| | | | | | | | | | | | | | | | SD cards operating at UHS104 or better support SET_BLOCK_COUNT. Signed-off-by: Andrei Warkentin <andreiw@motorola.com> Reviewed-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: core: duplicated trial with same freq in mmc_rescan_try_freq()Jaehoon Chung2011-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mmc_rescan_try_freq() tries to init two times with the last frequency. For example, if host->f_min is 400KHz, we see the message below: mmc1: mmc_rescan_try_freq: trying to init card at 400000 Hz mmc1: mmc_rescan_try_freq: trying to init card at 400000 Hz Andy Ross says that he didn't try this code on a board with an f_min that exactly matches one of the table entries, which explains why the bug wasn't detected. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Cc: Andy Ross <andy.ross@windriver.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: core: add support for eMMC Dual Data RatePhilip Rakity2011-05-243-19/+32
| | | | | | | | | | | | | | | | | | eMMC voltage change not required for 1.8V. 3.3V and 1.8V vcc are capable of doing DDR. vccq of 1.8v is not required. Signed-off-by: Philip Rakity <prakity@marvell.com> Reviewed-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: core: eMMC signal voltage does not use CMD11Philip Rakity2011-05-243-5/+6
| | | | | | | | | | | | | | | | | | eMMC chips do not use CMD11 when changing voltage. Add extra argument to call to indicate if CMD11 needs to be sent. Signed-off-by: Philip Rakity <prakity@marvell.com> Reviewed-by: Arindam Nath <arindam.nath@amd.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: core: clear MMC_PM_KEEP_POWER flag on resumeEliad Peller2011-05-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | Since the MMC_PM_KEEP_POWER flag should be set on each suspend, it should also cleared on each resume. Upon resuming, we have to know if power was kept (for re-initialization, etc.), so clear it just after resuming. Signed-off-by: Eliad Peller <eliad@wizery.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdio: optimized SDIO IRQ handling for single irqStefan Nilsson XK2011-05-241-1/+32
| | | | | | | | | | | | | | | | | | | | | | If there is only 1 function interrupt registered it is possible to improve performance by directly calling the irq handler and avoiding the overhead of reading the CCCR registers. Signed-off-by: Per Forlin <per.forlin@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@stericsson.com> Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci: enable preset value after uhs initializationArindam Nath2011-05-241-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the Host Controller spec v3.00, setting Preset Value Enable in the Host Control2 register lets SDCLK Frequency Select, Clock Generator Select and Driver Strength Select to be set automatically by the Host Controller based on the UHS-I mode set. This patch enables this feature. Since Preset Value Enable makes sense only for UHS-I cards, we enable this feature after successfull UHS-I initialization. We also reset Preset Value Enable next time before initialization. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sd: add support for tuning during uhs initializationArindam Nath2011-05-241-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Host Controller needs tuning during initialization to operate SDR50 and SDR104 UHS-I cards. Whether SDR50 mode actually needs tuning is indicated by bit 45 of the Host Controller Capabilities register. A new command CMD19 has been defined in the Physical Layer spec v3.01 to request the card to send tuning pattern. We enable Buffer Read Ready interrupt at the very begining of tuning procedure, because that is the only interrupt generated by the Host Controller during tuning. We program the block size to 64 in the Block Size register. We make sure that DMA Enable and Multi Block Select in the Transfer Mode register are set to 0 before actually sending CMD19. The tuning block is sent by the card to the Host Controller using DAT lines, so we set Data Present Select (bit 5) in the Command register. The Host Controller is responsible for doing the verfication of tuning block sent by the card at the hardware level. After sending CMD19, we wait for Buffer Read Ready interrupt. In case we don't receive an interrupt after the specified timeout value, we fall back on fixed sampling clock by setting Execute Tuning (bit 6) and Sampling Clock Select (bit 7) of Host Control2 register to 0. Before exiting the tuning procedure, we disable Buffer Read Ready interrupt and re-enable other interrupts. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sd: report correct speed and capacity of uhs cardsArindam Nath2011-05-242-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since only UHS-I cards respond with S18A set in response to ACMD41, we set the card as ultra-high-speed after successfull initialization. We need to decide whether a card is SDXC based on the C_SIZE field of CSDv2.0 register. According to Physical Layer spec v3.01, the minimum value of C_SIZE for SDXC card is 00FFFFh. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sd: set current limit for uhs cardsArindam Nath2011-05-241-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We decide on the current limit to be set for the card based on the Capability of Host Controller to provide current at 1.8V signalling, and the maximum current limit of the card as indicated by CMD6 mode 0. We then set the current limit for the card using CMD6 mode 1. As per the Physical Layer Spec v3.01, the current limit switch is only applicable for SDR50, SDR104, and DDR50 bus speed modes. For other UHS-I modes, we set the default current limit of 200mA. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sd: add support for uhs bus speed mode selectionArindam Nath2011-05-241-0/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for setting UHS-I bus speed mode during UHS-I initialization procedure. Since both the host and card can support more than one bus speed, we select the highest speed based on both of their capabilities. First we set the bus speed mode for the card using CMD6 mode 1, and then we program the host controller to support the required speed mode. We also set High Speed Enable in case one of the UHS-I modes is selected. We take care to reset SD clock before setting UHS mode in the Host Control2 register, and then re-enable it as per the Host Controller spec v3.00. We then set the clock frequency for the UHS-I mode selected. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sd: add support for driver type selectionArindam Nath2011-05-245-29/+139
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for setting driver strength during UHS-I initialization procedure. Since UHS-I cards set S18A (bit 24) in response to ACMD41, we use this as a base for UHS-I initialization. We modify the parameter list of mmc_sd_get_cid() so that we can save the ROCR from ACMD41 to check whether bit 24 is set. We decide whether the Host Controller supports A, C, or D driver type depending on the Capabilities register. Driver type B is suported by default. We then set the appropriate driver type for the card using CMD6 mode 1. As per Host Controller spec v3.00, we set driver type for the host only if Preset Value Enable in the Host Control2 register is not set. SDHCI_HOST_CONTROL has been renamed to SDHCI_HOST_CONTROL1 to conform to the spec. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sd: query function modes for uhs cardsArindam Nath2011-05-241-10/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SD cards which conform to Physical Layer Spec v3.01 can support additional Bus Speed Modes, Driver Strength, and Current Limit other than the default values. We use CMD6 mode 0 to read these additional card functions. The values read here will be used during UHS-I initialization steps. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sd: add support for signal voltage switch procedureArindam Nath2011-05-243-2/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Host Controller v3.00 adds another Capabilities register. Apart from other things, this new register indicates whether the Host Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec doesn't mention about explicit support for SDR12 and SDR25 UHS-I modes, so the Host Controller v3.00 should support them by default. Also if the controller supports SDR104 mode, it will also support SDR50 mode as well. So depending on the host support, we set the corresponding MMC_CAP_* flags. One more new register. Host Control2 is added in v3.00, which is used during Signal Voltage Switch procedure described below. Since as per v3.00 spec, UHS-I supported hosts should set S18R to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also need to set XPC (bit 28) of OCR in case the host can supply >150mA. This support is indicated by the Maximum Current Capabilities register of the Host Controller. If the response of ACMD41 has both CCS and S18A set, we start the signal voltage switch procedure, which if successfull, will switch the card from 3.3V signalling to 1.8V signalling. Signal voltage switch procedure adds support for a new command CMD11 in the Physical Layer Spec v3.01. As part of this procedure, we need to set 1.8V Signalling Enable (bit 3) of Host Control2 register, which if remains set after 5ms, means the switch to 1.8V signalling is successfull. Otherwise, we clear bit 24 of OCR and retry the initialization sequence. When we remove the card, and insert the same or another card, we need to make sure that we start with 3.3V signalling voltage. So we call mmc_set_signal_voltage() with MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling voltage before we actually start initializing the card. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: core: Add mmc CMD+ACMD passthrough ioctlJohn Calixto2011-05-241-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allows appropriately-privileged applications to send CMD (normal) and ACMD (application-specific; preceded with CMD55) commands to cards/devices on the mmc bus. This is primarily useful for enabling the security functionality built in to every SD card. It can also be used as a generic passthrough (e.g. to enable virtual machines to control mmc bus devices directly). However, this use case has not been tested rigorously. Generic passthrough testing was only conducted for a few non-security opcodes to prove the feasibility of the passthrough. Since any opcode can be sent using this passthrough, it is very possible to render the card/device unusable. Applications that use this ioctl must have CAP_SYS_RAWIO. Security commands tested on TI PCIxx12 (SDHCI), Sigma Designs SMP8652 SoC, TI OMAP3621/OMAP3630 SoC, Samsung S5PC110 SoC, Qualcomm MSM7200A SoC. Signed-off-by: John Calixto <john.calixto@modsystems.com> Reviewed-by: Andrei Warkentin <andreiw@motorola.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: initialize struct mmc_request at declaration timeChris Ball2011-05-244-22/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Converts from: struct mmc_request mrq; memset(&mrq, 0, sizeof(struct mmc_request)); to: struct mmc_request mrq = {0}; because it's shorter, as performant, and easier to work out whether initialization has happened. Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: initialize struct mmc_data at declaration timeChris Ball2011-05-243-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Converts from: struct mmc_data data; memset(&data, 0, sizeof(struct mmc_data)); to: struct mmc_data data = {0}; because it's shorter, as performant, and easier to work out whether initialization has happened. Signed-off-by: Chris Ball <cjb@laptop.org>
generated by cgit v1.1 at 2025-08-07 07:50:58 +0000