From 5f873bae704cf8b7cbd64b5720912266286c9146 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 17 May 2011 16:12:37 -0600 Subject: tty/serial: Fix break handling for PORT_TEGRA When a break is received, Tegra's UART apparently fills the FIFO with 0 bytes. These must be drained so that they aren't interpreted as actual data received. This allows e.g. MAGIC_SYSRQ to work on Tegra's UARTs. v2: Added FIXME comment to clear_rx_fifo Originally-by: Laxman Dewangan Cc: Laxman Dewangan Signed-off-by: Stephen Warren Acked-by: Alan Cox Signed-off-by: Greg Kroah-Hartman --- include/linux/serial_reg.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux/serial_reg.h') diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h index 5f66e84..c75bda3 100644 --- a/include/linux/serial_reg.h +++ b/include/linux/serial_reg.h @@ -119,6 +119,7 @@ #define UART_MCR_DTR 0x01 /* DTR complement */ #define UART_LSR 5 /* In: Line Status Register */ +#define UART_LSR_FIFOE 0x80 /* Fifo error */ #define UART_LSR_TEMT 0x40 /* Transmitter empty */ #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ #define UART_LSR_BI 0x10 /* Break interrupt indicator */ -- cgit v1.1