diff options
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/Kconfig | 8 | ||||
| -rw-r--r-- | arch/arm/mm/abort-ev6.S | 2 | ||||
| -rw-r--r-- | arch/arm/mm/cache-v6.S | 23 | ||||
| -rw-r--r-- | arch/arm/mm/consistent.c | 54 | ||||
| -rw-r--r-- | arch/arm/mm/discontig.c | 4 | ||||
| -rw-r--r-- | arch/arm/mm/flush.c | 6 | ||||
| -rw-r--r-- | arch/arm/mm/ioremap.c | 49 | ||||
| -rw-r--r-- | arch/arm/mm/mm-armv.c | 7 | ||||
| -rw-r--r-- | arch/arm/mm/proc-xscale.S | 16 | ||||
| -rw-r--r-- | arch/arm/mm/tlb-v6.S | 1 |
10 files changed, 107 insertions, 63 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index e84fdde..3b79d0e 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -62,8 +62,8 @@ config CPU_ARM720T # ARM920T config CPU_ARM920T bool "Support ARM920T processor" if !ARCH_S3C2410 - depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000 - default y if ARCH_S3C2410 + depends on ARCH_INTEGRATOR || ARCH_S3C2410 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200 + default y if ARCH_S3C2410 || ARCH_AT91RM9200 select CPU_32v4 select CPU_ABRT_EV4T select CPU_CACHE_V4WT @@ -83,8 +83,8 @@ config CPU_ARM920T # ARM922T config CPU_ARM922T bool "Support ARM922T processor" if ARCH_INTEGRATOR - depends on ARCH_CAMELOT || ARCH_LH7A40X || ARCH_INTEGRATOR - default y if ARCH_CAMELOT || ARCH_LH7A40X + depends on ARCH_LH7A40X || ARCH_INTEGRATOR + default y if ARCH_LH7A40X select CPU_32v4 select CPU_ABRT_EV4T select CPU_CACHE_V4WT diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S index dbd3460..8a7f65b 100644 --- a/arch/arm/mm/abort-ev6.S +++ b/arch/arm/mm/abort-ev6.S @@ -20,7 +20,7 @@ */ .align 5 ENTRY(v6_early_abort) -#ifdef CONFIG_CPU_MPCORE +#ifdef CONFIG_CPU_32v6K clrex #else strex r0, r1, [sp] @ Clear the exclusive monitor diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S index 72966d9..2c6c2a7 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S @@ -92,25 +92,20 @@ ENTRY(v6_coherent_kern_range) * - the Icache does not read data from the write buffer */ ENTRY(v6_coherent_user_range) - bic r0, r0, #CACHE_LINE_SIZE - 1 -1: + #ifdef HARVARD_CACHE - mcr p15, 0, r0, c7, c10, 1 @ clean D line - mcr p15, 0, r0, c7, c5, 1 @ invalidate I line -#endif - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE - mcr p15, 0, r0, c7, c5, 7 @ invalidate BTB entry - add r0, r0, #BTB_FLUSH_SIZE + bic r0, r0, #CACHE_LINE_SIZE - 1 +1: mcr p15, 0, r0, c7, c10, 1 @ clean D line + add r0, r0, #CACHE_LINE_SIZE cmp r0, r1 blo 1b -#ifdef HARVARD_CACHE +#endif mov r0, #0 +#ifdef HARVARD_CACHE mcr p15, 0, r0, c7, c10, 4 @ drain write buffer + mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate +#else + mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB #endif mov pc, lr diff --git a/arch/arm/mm/consistent.c b/arch/arm/mm/consistent.c index dbfe9e8..c2ee18d 100644 --- a/arch/arm/mm/consistent.c +++ b/arch/arm/mm/consistent.c @@ -19,17 +19,26 @@ #include <linux/dma-mapping.h> #include <asm/cacheflush.h> -#include <asm/io.h> #include <asm/tlbflush.h> +#include <asm/sizes.h> + +/* Sanity check size */ +#if (CONSISTENT_DMA_SIZE % SZ_2M) +#error "CONSISTENT_DMA_SIZE must be multiple of 2MiB" +#endif -#define CONSISTENT_BASE (0xffc00000) #define CONSISTENT_END (0xffe00000) +#define CONSISTENT_BASE (CONSISTENT_END - CONSISTENT_DMA_SIZE) + #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT) +#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT) +#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT) + /* - * This is the page table (2MB) covering uncached, DMA consistent allocations + * These are the page tables (2MB each) covering uncached, DMA consistent allocations */ -static pte_t *consistent_pte; +static pte_t *consistent_pte[NUM_CONSISTENT_PTES]; static DEFINE_SPINLOCK(consistent_lock); /* @@ -143,7 +152,7 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, unsigned long order; u64 mask = ISA_DMA_THRESHOLD, limit; - if (!consistent_pte) { + if (!consistent_pte[0]) { printk(KERN_ERR "%s: not initialised\n", __func__); dump_stack(); return NULL; @@ -206,9 +215,12 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, c = vm_region_alloc(&consistent_head, size, gfp & ~(__GFP_DMA | __GFP_HIGHMEM)); if (c) { - pte_t *pte = consistent_pte + CONSISTENT_OFFSET(c->vm_start); + pte_t *pte; struct page *end = page + (1 << order); + int idx = CONSISTENT_PTE_INDEX(c->vm_start); + u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); + pte = consistent_pte[idx] + off; c->vm_pages = page; /* @@ -227,6 +239,11 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, set_pte(pte, mk_pte(page, prot)); page++; pte++; + off++; + if (off >= PTRS_PER_PTE) { + off = 0; + pte = consistent_pte[++idx]; + } } while (size -= PAGE_SIZE); /* @@ -328,6 +345,8 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr struct vm_region *c; unsigned long flags, addr; pte_t *ptep; + int idx; + u32 off; WARN_ON(irqs_disabled()); @@ -348,7 +367,9 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr size = c->vm_end - c->vm_start; } - ptep = consistent_pte + CONSISTENT_OFFSET(c->vm_start); + idx = CONSISTENT_PTE_INDEX(c->vm_start); + off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); + ptep = consistent_pte[idx] + off; addr = c->vm_start; do { pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep); @@ -356,6 +377,11 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr ptep++; addr += PAGE_SIZE; + off++; + if (off >= PTRS_PER_PTE) { + off = 0; + ptep = consistent_pte[++idx]; + } if (!pte_none(pte) && pte_present(pte)) { pfn = pte_pfn(pte); @@ -402,11 +428,12 @@ static int __init consistent_init(void) pgd_t *pgd; pmd_t *pmd; pte_t *pte; - int ret = 0; + int ret = 0, i = 0; + u32 base = CONSISTENT_BASE; do { - pgd = pgd_offset(&init_mm, CONSISTENT_BASE); - pmd = pmd_alloc(&init_mm, pgd, CONSISTENT_BASE); + pgd = pgd_offset(&init_mm, base); + pmd = pmd_alloc(&init_mm, pgd, base); if (!pmd) { printk(KERN_ERR "%s: no pmd tables\n", __func__); ret = -ENOMEM; @@ -414,15 +441,16 @@ static int __init consistent_init(void) } WARN_ON(!pmd_none(*pmd)); - pte = pte_alloc_kernel(pmd, CONSISTENT_BASE); + pte = pte_alloc_kernel(pmd, base); if (!pte) { printk(KERN_ERR "%s: no pte tables\n", __func__); ret = -ENOMEM; break; } - consistent_pte = pte; - } while (0); + consistent_pte[i++] = pte; + base += (1 << PGDIR_SHIFT); + } while (base < CONSISTENT_END); return ret; } diff --git a/arch/arm/mm/discontig.c b/arch/arm/mm/discontig.c index 0d097bb..1e56021 100644 --- a/arch/arm/mm/discontig.c +++ b/arch/arm/mm/discontig.c @@ -9,10 +9,8 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ - #include <linux/module.h> -#include <linux/mm.h> -#include <linux/init.h> +#include <linux/mmzone.h> #include <linux/bootmem.h> #if MAX_NUMNODES != 4 && MAX_NUMNODES != 16 diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 330695b..b103e56 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c @@ -24,14 +24,16 @@ static void flush_pfn_alias(unsigned long pfn, unsigned long vaddr) { unsigned long to = ALIAS_FLUSH_START + (CACHE_COLOUR(vaddr) << PAGE_SHIFT); + const int zero = 0; set_pte(TOP_PTE(to), pfn_pte(pfn, PAGE_KERNEL)); flush_tlb_kernel_page(to); asm( "mcrr p15, 0, %1, %0, c14\n" - " mcrr p15, 0, %1, %0, c5\n" + " mcr p15, 0, %2, c7, c10, 4\n" + " mcr p15, 0, %2, c7, c5, 0\n" : - : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES) + : "r" (to), "r" (to + PAGE_SIZE - L1_CACHE_BYTES), "r" (zero) : "cc"); } diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c index 1090139..da9b359 100644 --- a/arch/arm/mm/ioremap.c +++ b/arch/arm/mm/ioremap.c @@ -86,11 +86,12 @@ remap_area_pmd(pmd_t * pmd, unsigned long address, unsigned long size, } static int -remap_area_pages(unsigned long start, unsigned long phys_addr, +remap_area_pages(unsigned long start, unsigned long pfn, unsigned long size, unsigned long flags) { unsigned long address = start; unsigned long end = start + size; + unsigned long phys_addr = __pfn_to_phys(pfn); int err = 0; pgd_t * dir; @@ -130,36 +131,44 @@ remap_area_pages(unsigned long start, unsigned long phys_addr, * mapping. See include/asm-arm/proc-armv/pgtable.h for more information. */ void __iomem * +__ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size, + unsigned long flags) +{ + unsigned long addr; + struct vm_struct * area; + + area = get_vm_area(size, VM_IOREMAP); + if (!area) + return NULL; + addr = (unsigned long)area->addr; + if (remap_area_pages(addr, pfn, size, flags)) { + vfree((void *)addr); + return NULL; + } + return (void __iomem *) (offset + (char *)addr); +} +EXPORT_SYMBOL(__ioremap_pfn); + +void __iomem * __ioremap(unsigned long phys_addr, size_t size, unsigned long flags) { - void * addr; - struct vm_struct * area; - unsigned long offset, last_addr; + unsigned long last_addr; + unsigned long offset = phys_addr & ~PAGE_MASK; + unsigned long pfn = __phys_to_pfn(phys_addr); - /* Don't allow wraparound or zero size */ + /* + * Don't allow wraparound or zero size + */ last_addr = phys_addr + size - 1; if (!size || last_addr < phys_addr) return NULL; /* - * Mappings have to be page-aligned + * Page align the mapping size */ - offset = phys_addr & ~PAGE_MASK; - phys_addr &= PAGE_MASK; size = PAGE_ALIGN(last_addr + 1) - phys_addr; - /* - * Ok, go for it.. - */ - area = get_vm_area(size, VM_IOREMAP); - if (!area) - return NULL; - addr = area->addr; - if (remap_area_pages((unsigned long) addr, phys_addr, size, flags)) { - vfree(addr); - return NULL; - } - return (void __iomem *) (offset + (char *)addr); + return __ioremap_pfn(pfn, offset, size, flags); } EXPORT_SYMBOL(__ioremap); diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c index 9e50127..ef8d30a 100644 --- a/arch/arm/mm/mm-armv.c +++ b/arch/arm/mm/mm-armv.c @@ -19,7 +19,6 @@ #include <asm/pgalloc.h> #include <asm/page.h> -#include <asm/io.h> #include <asm/setup.h> #include <asm/tlbflush.h> @@ -344,6 +343,12 @@ static struct mem_types mem_types[] __initdata = { PMD_SECT_AP_WRITE | PMD_SECT_BUFFERABLE | PMD_SECT_TEX(1), .domain = DOMAIN_IO, + }, + [MT_NONSHARED_DEVICE] = { + .prot_l1 = PMD_TYPE_TABLE, + .prot_sect = PMD_TYPE_SECT | PMD_SECT_NONSHARED_DEV | + PMD_SECT_AP_WRITE, + .domain = DOMAIN_IO, } }; diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 861b359..2d3823e 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S @@ -241,7 +241,15 @@ ENTRY(xscale_flush_user_cache_range) * it also trashes the mini I-cache used by JTAG debuggers. */ ENTRY(xscale_coherent_kern_range) - /* FALLTHROUGH */ + bic r0, r0, #CACHELINESIZE - 1 +1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + add r0, r0, #CACHELINESIZE + cmp r0, r1 + blo 1b + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB + mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer + mov pc, lr /* * coherent_user_range(start, end) @@ -252,18 +260,16 @@ ENTRY(xscale_coherent_kern_range) * * - start - virtual start address * - end - virtual end address - * - * Note: single I-cache line invalidation isn't used here since - * it also trashes the mini I-cache used by JTAG debuggers. */ ENTRY(xscale_coherent_user_range) bic r0, r0, #CACHELINESIZE - 1 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry + mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry add r0, r0, #CACHELINESIZE cmp r0, r1 blo 1b mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB + mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer mov pc, lr diff --git a/arch/arm/mm/tlb-v6.S b/arch/arm/mm/tlb-v6.S index 6f76b89..fd6adde 100644 --- a/arch/arm/mm/tlb-v6.S +++ b/arch/arm/mm/tlb-v6.S @@ -80,6 +80,7 @@ ENTRY(v6wbi_flush_kern_tlb_range) add r0, r0, #PAGE_SZ cmp r0, r1 blo 1b + mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier mov pc, lr .section ".text.init", #alloc, #execinstr |