diff options
Diffstat (limited to 'arch/mips/sibyte/sb1250')
| -rw-r--r-- | arch/mips/sibyte/sb1250/prom.c | 3 | ||||
| -rw-r--r-- | arch/mips/sibyte/sb1250/setup.c | 36 | ||||
| -rw-r--r-- | arch/mips/sibyte/sb1250/time.c | 77 |
3 files changed, 84 insertions, 32 deletions
diff --git a/arch/mips/sibyte/sb1250/prom.c b/arch/mips/sibyte/sb1250/prom.c index de62ab0..742043f 100644 --- a/arch/mips/sibyte/sb1250/prom.c +++ b/arch/mips/sibyte/sb1250/prom.c @@ -24,6 +24,7 @@ #include <linux/bootmem.h> #include <linux/smp.h> #include <linux/initrd.h> +#include <linux/pm.h> #include <asm/bootinfo.h> #include <asm/reboot.h> @@ -79,7 +80,7 @@ void __init prom_init(void) { _machine_restart = (void (*)(char *))prom_linux_exit; _machine_halt = prom_linux_exit; - _machine_power_off = prom_linux_exit; + pm_power_off = prom_linux_exit; strcpy(arcs_cmdline, "root=/dev/ram0 "); diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c index df2e266..fde4751 100644 --- a/arch/mips/sibyte/sb1250/setup.c +++ b/arch/mips/sibyte/sb1250/setup.c @@ -16,6 +16,7 @@ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <linux/config.h> +#include <linux/init.h> #include <linux/kernel.h> #include <linux/reboot.h> #include <linux/string.h> @@ -42,7 +43,7 @@ static inline int setup_bcm112x(void); /* Setup code likely to be common to all SiByte platforms */ -static inline int sys_rev_decode(void) +static int __init sys_rev_decode(void) { int ret = 0; @@ -74,7 +75,7 @@ static inline int sys_rev_decode(void) return ret; } -static inline int setup_bcm1250(void) +static int __init setup_bcm1250(void) { int ret = 0; @@ -120,7 +121,7 @@ static inline int setup_bcm1250(void) return ret; } -static inline int setup_bcm112x(void) +static int __init setup_bcm112x(void) { int ret = 0; @@ -146,7 +147,7 @@ static inline int setup_bcm112x(void) return ret; } -void sb1250_setup(void) +void __init sb1250_setup(void) { uint64_t sys_rev; int plldiv; @@ -169,31 +170,42 @@ void sb1250_setup(void) soc_str, pass_str, zbbus_mhz * 2, sb1_pass); prom_printf("Board type: %s\n", get_system_type()); - switch(war_pass) { + switch (war_pass) { case K_SYS_REVISION_BCM1250_PASS1: #ifndef CONFIG_SB1_PASS_1_WORKAROUNDS - prom_printf("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n"); + prom_printf("@@@@ This is a BCM1250 A0-A2 (Pass 1) board, " + "and the kernel doesn't have the proper " + "workarounds compiled in. @@@@\n"); bad_config = 1; #endif break; case K_SYS_REVISION_BCM1250_PASS2: /* Pass 2 - easiest as default for now - so many numbers */ -#if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) - prom_printf("@@@@ This is a BCM1250 A3-A10 board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n"); +#if !defined(CONFIG_SB1_PASS_2_WORKAROUNDS) || \ + !defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) + prom_printf("@@@@ This is a BCM1250 A3-A10 board, and the " + "kernel doesn't have the proper workarounds " + "compiled in. @@@@\n"); bad_config = 1; #endif #ifdef CONFIG_CPU_HAS_PREFETCH - prom_printf("@@@@ Prefetches may be enabled in this kernel, but are buggy on this board. @@@@\n"); + prom_printf("@@@@ Prefetches may be enabled in this kernel, " + "but are buggy on this board. @@@@\n"); bad_config = 1; #endif break; case K_SYS_REVISION_BCM1250_PASS2_2: #ifndef CONFIG_SB1_PASS_2_WORKAROUNDS - prom_printf("@@@@ This is a BCM1250 B1/B2. board, and the kernel doesn't have the proper workarounds compiled in. @@@@\n"); + prom_printf("@@@@ This is a BCM1250 B1/B2. board, and the " + "kernel doesn't have the proper workarounds " + "compiled in. @@@@\n"); bad_config = 1; #endif -#if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || !defined(CONFIG_CPU_HAS_PREFETCH) - prom_printf("@@@@ This is a BCM1250 B1/B2, but the kernel is conservatively configured for an 'A' stepping. @@@@\n"); +#if defined(CONFIG_SB1_PASS_2_1_WORKAROUNDS) || \ + !defined(CONFIG_CPU_HAS_PREFETCH) + prom_printf("@@@@ This is a BCM1250 B1/B2, but the kernel is " + "conservatively configured for an 'A' stepping. " + "@@@@\n"); #endif break; default: diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c index 511c89d..1588f6d 100644 --- a/arch/mips/sibyte/sb1250/time.c +++ b/arch/mips/sibyte/sb1250/time.c @@ -47,23 +47,51 @@ #define IMR_IP3_VAL K_INT_MAP_I1 #define IMR_IP4_VAL K_INT_MAP_I2 +#define SB1250_HPT_NUM 3 +#define SB1250_HPT_VALUE M_SCD_TIMER_CNT /* max value */ +#define SB1250_HPT_SHIFT ((sizeof(unsigned int)*8)-V_SCD_TIMER_WIDTH) + + extern int sb1250_steal_irq(int irq); +static unsigned int sb1250_hpt_read(void); +static void sb1250_hpt_init(unsigned int); + +static unsigned int hpt_offset; + +void __init sb1250_hpt_setup(void) +{ + int cpu = smp_processor_id(); + + if (!cpu) { + /* Setup hpt using timer #3 but do not enable irq for it */ + __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); + __raw_writeq(SB1250_HPT_VALUE, + IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_INIT))); + __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, + IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CFG))); + + /* + * we need to fill 32 bits, so just use the upper 23 bits and pretend + * the timer is going 512Mhz instead of 1Mhz + */ + mips_hpt_frequency = V_SCD_TIMER_FREQ << SB1250_HPT_SHIFT; + mips_hpt_init = sb1250_hpt_init; + mips_hpt_read = sb1250_hpt_read; + } +} + + void sb1250_time_init(void) { int cpu = smp_processor_id(); int irq = K_INT_TIMER_0+cpu; - /* Only have 4 general purpose timers */ - if (cpu > 3) { + /* Only have 4 general purpose timers, and we use last one as hpt */ + if (cpu > 2) { BUG(); } - if (!cpu) { - /* Use our own gettimeoffset() routine */ - do_gettimeoffset = sb1250_gettimeoffset; - } - sb1250_mask_irq(cpu, irq); /* Map the timer interrupt to ip[4] of this cpu */ @@ -75,10 +103,10 @@ void sb1250_time_init(void) /* Disable the timer and set up the count */ __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); #ifdef CONFIG_SIMULATION - __raw_writeq(50000 / HZ, + __raw_writeq((50000 / HZ) - 1, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #else - __raw_writeq(1000000 / HZ, + __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #endif @@ -103,7 +131,7 @@ void sb1250_timer_interrupt(struct pt_regs *regs) int cpu = smp_processor_id(); int irq = K_INT_TIMER_0 + cpu; - /* Reset the timer */ + /* ACK interrupt */ ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); @@ -122,15 +150,26 @@ void sb1250_timer_interrupt(struct pt_regs *regs) } /* - * We use our own do_gettimeoffset() instead of the generic one, - * because the generic one does not work for SMP case. - * In addition, since we use general timer 0 for system time, - * we can get accurate intra-jiffy offset without calibration. + * The HPT is free running from SB1250_HPT_VALUE down to 0 then starts over + * again. There's no easy way to set to a specific value so store init value + * in hpt_offset and subtract each time. + * + * Note: Timer isn't full 32bits so shift it into the upper part making + * it appear to run at a higher frequency. */ -unsigned long sb1250_gettimeoffset(void) +static unsigned int sb1250_hpt_read(void) { - unsigned long count = - __raw_readq(IOADDR(A_SCD_TIMER_REGISTER(0, R_SCD_TIMER_CNT))); + unsigned int count; - return 1000000/HZ - count; - } + count = G_SCD_TIMER_CNT(__raw_readq(IOADDR(A_SCD_TIMER_REGISTER(SB1250_HPT_NUM, R_SCD_TIMER_CNT)))); + + count = (SB1250_HPT_VALUE - count) << SB1250_HPT_SHIFT; + + return count - hpt_offset; +} + +static void sb1250_hpt_init(unsigned int count) +{ + hpt_offset = count; + return; +} |