diff options
Diffstat (limited to 'arch/powerpc/boot')
| -rw-r--r-- | arch/powerpc/boot/Makefile | 30 | ||||
| -rw-r--r-- | arch/powerpc/boot/cuboot-83xx.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/boot/cuboot-85xx.c | 2 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/prpmc2800.dts | 315 | ||||
| -rw-r--r-- | arch/powerpc/boot/mpsc.c | 170 | ||||
| -rw-r--r-- | arch/powerpc/boot/mv64x60.c | 581 | ||||
| -rw-r--r-- | arch/powerpc/boot/mv64x60.h | 70 | ||||
| -rw-r--r-- | arch/powerpc/boot/mv64x60_i2c.c | 206 | ||||
| -rw-r--r-- | arch/powerpc/boot/ops.h | 1 | ||||
| -rw-r--r-- | arch/powerpc/boot/prpmc2800.c | 577 | ||||
| -rw-r--r-- | arch/powerpc/boot/serial.c | 2 |
11 files changed, 1951 insertions, 5 deletions
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index 5c384aa..d4f9fef 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -43,9 +43,9 @@ $(addprefix $(obj)/,$(zlib) gunzip_util.o main.o): \ src-wlib := string.S crt0.S stdio.c main.c flatdevtree.c flatdevtree_misc.c \ ns16550.c serial.c simple_alloc.c div64.S util.S \ gunzip_util.c elf_util.c $(zlib) devtree.c \ - 44x.c ebony.c + 44x.c ebony.c mv64x60.c mpsc.c mv64x60_i2c.c src-plat := of.c cuboot-83xx.c cuboot-85xx.c holly.c \ - cuboot-ebony.c treeboot-ebony.c + cuboot-ebony.c treeboot-ebony.c prpmc2800.c src-boot := $(src-wlib) $(src-plat) empty.c src-boot := $(addprefix $(obj)/, $(src-boot)) @@ -132,6 +132,7 @@ image-$(CONFIG_PPC_CHRP) += zImage.chrp image-$(CONFIG_PPC_EFIKA) += zImage.chrp image-$(CONFIG_PPC_PMAC) += zImage.pmac image-$(CONFIG_PPC_HOLLY) += zImage.holly-elf +image-$(CONFIG_PPC_PRPMC2800) += zImage.prpmc2800 image-$(CONFIG_DEFAULT_UIMAGE) += uImage ifneq ($(CONFIG_DEVICE_TREE),"") @@ -154,9 +155,27 @@ targets += $(image-y) $(initrd-y) $(addprefix $(obj)/, $(initrd-y)): $(obj)/ramdisk.image.gz +dts- := $(patsubst zImage%, zImage.dts%, $(image-n) $(image-)) +dts-y := $(patsubst zImage%, zImage.dts%, $(image-y)) +dts-y := $(filter-out $(image-y), $(dts-y)) +targets += $(image-y) $(dts-y) + +dts_initrd- := $(patsubst zImage%, zImage.dts_initrd%, $(image-n) $(image-)) +dts_initrd-y := $(patsubst zImage%, zImage.dts_initrd%, $(image-y)) +dts_initrd-y := $(filter-out $(image-y), $(dts_initrd-y)) +targets += $(image-y) $(dts_initrd-y) + +$(addprefix $(obj)/, $(dts_initrd-y)): $(obj)/ramdisk.image.gz + # Don't put the ramdisk on the pattern rule; when its missing make will try # the pattern rule with less dependencies that also matches (even with the # hard dependency listed). +$(obj)/zImage.dts_initrd.%: vmlinux $(wrapperbits) $(dts) $(obj)/ramdisk.image.gz + $(call if_changed,wrap,$*,$(dts),,$(obj)/ramdisk.image.gz) + +$(obj)/zImage.dts.%: vmlinux $(wrapperbits) $(dts) + $(call if_changed,wrap,$*,$(dts)) + $(obj)/zImage.initrd.%: vmlinux $(wrapperbits) $(call if_changed,wrap,$*,,,$(obj)/ramdisk.image.gz) @@ -195,13 +214,18 @@ $(obj)/zImage: $(addprefix $(obj)/, $(image-y)) @rm -f $@; ln $< $@ $(obj)/zImage.initrd: $(addprefix $(obj)/, $(initrd-y)) @rm -f $@; ln $< $@ +$(obj)/zImage.dts: $(addprefix $(obj)/, $(dts-y)) + @rm -f $@; ln $< $@ +$(obj)/zImage.dts_initrd: $(addprefix $(obj)/, $(dts_initrd-y)) + @rm -f $@; ln $< $@ + install: $(CONFIGURE) $(addprefix $(obj)/, $(image-y)) sh -x $(srctree)/$(src)/install.sh "$(KERNELRELEASE)" vmlinux System.map "$(INSTALL_PATH)" $< # anything not in $(targets) clean-files += $(image-) $(initrd-) zImage zImage.initrd cuImage.* \ - treeImage.* + treeImage.* zImage.dts zImage.dts_initrd # clean up files cached by wrapper clean-kernel := vmlinux.strip vmlinux.bin diff --git a/arch/powerpc/boot/cuboot-83xx.c b/arch/powerpc/boot/cuboot-83xx.c index 6cbc20a..9af554e 100644 --- a/arch/powerpc/boot/cuboot-83xx.c +++ b/arch/powerpc/boot/cuboot-83xx.c @@ -57,7 +57,7 @@ void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, memcpy(&bd, (bd_t *)r3, sizeof(bd)); loader_info.initrd_addr = r4; - loader_info.initrd_size = r4 ? r5 : 0; + loader_info.initrd_size = r4 ? r5 - r4 : 0; loader_info.cmdline = (char *)r6; loader_info.cmdline_len = r7 - r6; diff --git a/arch/powerpc/boot/cuboot-85xx.c b/arch/powerpc/boot/cuboot-85xx.c index f88ba00..e256031 100644 --- a/arch/powerpc/boot/cuboot-85xx.c +++ b/arch/powerpc/boot/cuboot-85xx.c @@ -58,7 +58,7 @@ void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, memcpy(&bd, (bd_t *)r3, sizeof(bd)); loader_info.initrd_addr = r4; - loader_info.initrd_size = r4 ? r5 : 0; + loader_info.initrd_size = r4 ? r5 - r4 : 0; loader_info.cmdline = (char *)r6; loader_info.cmdline_len = r7 - r6; diff --git a/arch/powerpc/boot/dts/prpmc2800.dts b/arch/powerpc/boot/dts/prpmc2800.dts new file mode 100644 index 0000000..568965a --- /dev/null +++ b/arch/powerpc/boot/dts/prpmc2800.dts @@ -0,0 +1,315 @@ +/* Device Tree Source for Motorola PrPMC2800 + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * 2007 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + * + * Property values that are labeled as "Default" will be updated by bootwrapper + * if it can determine the exact PrPMC type. + * + * To build: + * dtc -I dts -O asm -o prpmc2800.S -b 0 prpmc2800.dts + * dtc -I dts -O dtb -o prpmc2800.dtb -b 0 prpmc2800.dts + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "PrPMC280/PrPMC2800"; /* Default */ + compatible = "motorola,PrPMC2800"; + coherency-off; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,7447 { + device_type = "cpu"; + reg = <0>; + clock-frequency = <2bb0b140>; /* Default (733 MHz) */ + bus-frequency = <7f28155>; /* 133.333333 MHz */ + timebase-frequency = <1fca055>; /* 33.333333 MHz */ + i-cache-line-size = <20>; + d-cache-line-size = <20>; + i-cache-size = <8000>; + d-cache-size = <8000>; + }; + }; + + memory { + device_type = "memory"; + reg = <00000000 20000000>; /* Default (512MB) */ + }; + + mv64x60@f1000000 { /* Marvell Discovery */ + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + model = "mv64360"; /* Default */ + compatible = "marvell,mv64x60"; + clock-frequency = <7f28155>; /* 133.333333 MHz */ + reg = <f1000000 00010000>; + virtual-reg = <f1000000>; + ranges = <88000000 88000000 01000000 /* PCI 0 I/O Space */ + 80000000 80000000 08000000 /* PCI 0 MEM Space */ + a0000000 a0000000 04000000 /* User FLASH */ + 00000000 f1000000 00010000 /* Bridge's regs */ + f2000000 f2000000 00040000>; /* Integrated SRAM */ + + flash@a0000000 { + device_type = "rom"; + compatible = "direct-mapped"; + reg = <a0000000 4000000>; /* Default (64MB) */ + probe-type = "CFI"; + bank-width = <4>; + partitions = <00000000 00100000 /* RO */ + 00100000 00040001 /* RW */ + 00140000 00400000 /* RO */ + 00540000 039c0000 /* RO */ + 03f00000 00100000>; /* RO */ + partition-names = "FW Image A", "FW Config Data", "Kernel Image", "Filesystem", "FW Image B"; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + device_type = "mdio"; + compatible = "marvell,mv64x60-mdio"; + ethernet-phy@1 { + device_type = "ethernet-phy"; + compatible = "broadcom,bcm5421"; + interrupts = <4c>; /* GPP 12 */ + interrupt-parent = <&/mv64x60/pic>; + reg = <1>; + }; + ethernet-phy@3 { + device_type = "ethernet-phy"; + compatible = "broadcom,bcm5421"; + interrupts = <4c>; /* GPP 12 */ + interrupt-parent = <&/mv64x60/pic>; + reg = <3>; + }; + }; + + ethernet@2000 { + reg = <2000 2000>; + eth0 { + device_type = "network"; + compatible = "marvell,mv64x60-eth"; + block-index = <0>; + interrupts = <20>; + interrupt-parent = <&/mv64x60/pic>; + phy = <&/mv64x60/mdio/ethernet-phy@1>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + eth1 { + device_type = "network"; + compatible = "marvell,mv64x60-eth"; + block-index = <1>; + interrupts = <21>; + interrupt-parent = <&/mv64x60/pic>; + phy = <&/mv64x60/mdio/ethernet-phy@3>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; + + sdma@4000 { + device_type = "dma"; + compatible = "marvell,mv64x60-sdma"; + reg = <4000 c18>; + virtual-reg = <f1004000>; + interrupt-base = <0>; + interrupts = <24>; + interrupt-parent = <&/mv64x60/pic>; + }; + + sdma@6000 { + device_type = "dma"; + compatible = "marvell,mv64x60-sdma"; + reg = <6000 c18>; + virtual-reg = <f1006000>; + interrupt-base = <0>; + interrupts = <26>; + interrupt-parent = <&/mv64x60/pic>; + }; + + brg@b200 { + compatible = "marvell,mv64x60-brg"; + reg = <b200 8>; + clock-src = <8>; + clock-frequency = <7ed6b40>; + current-speed = <2580>; + bcr = <0>; + }; + + brg@b208 { + compatible = "marvell,mv64x60-brg"; + reg = <b208 8>; + clock-src = <8>; + clock-frequency = <7ed6b40>; + current-speed = <2580>; + bcr = <0>; + }; + + cunit@f200 { + reg = <f200 200>; + }; + + mpscrouting@b400 { + reg = <b400 c>; + }; + + mpscintr@b800 { + reg = <b800 100>; + virtual-reg = <f100b800>; + }; + + mpsc@8000 { + device_type = "serial"; + compatible = "marvell,mpsc"; + reg = <8000 38>; + virtual-reg = <f1008000>; + sdma = <&/mv64x60/sdma@4000>; + brg = <&/mv64x60/brg@b200>; + cunit = <&/mv64x60/cunit@f200>; + mpscrouting = <&/mv64x60/mpscrouting@b400>; + mpscintr = <&/mv64x60/mpscintr@b800>; + block-index = <0>; + max_idle = <28>; + chr_1 = <0>; + chr_2 = <0>; + chr_10 = <3>; + mpcr = <0>; + interrupts = <28>; + interrupt-parent = <&/mv64x60/pic>; + }; + + mpsc@9000 { + device_type = "serial"; + compatible = "marvell,mpsc"; + reg = <9000 38>; + virtual-reg = <f1009000>; + sdma = <&/mv64x60/sdma@6000>; + brg = <&/mv64x60/brg@b208>; + cunit = <&/mv64x60/cunit@f200>; + mpscrouting = <&/mv64x60/mpscrouting@b400>; + mpscintr = <&/mv64x60/mpscintr@b800>; + block-index = <1>; + max_idle = <28>; + chr_1 = <0>; + chr_2 = <0>; + chr_10 = <3>; + mpcr = <0>; + interrupts = <2a>; + interrupt-parent = <&/mv64x60/pic>; + }; + + i2c@c000 { + device_type = "i2c"; + compatible = "marvell,mv64x60-i2c"; + reg = <c000 20>; + virtual-reg = <f100c000>; + freq_m = <8>; + freq_n = <3>; + timeout = <3e8>; /* 1000 = 1 second */ + retries = <1>; + interrupts = <25>; + interrupt-parent = <&/mv64x60/pic>; + }; + + pic { + #interrupt-cells = <1>; + #address-cells = <0>; + compatible = "marvell,mv64x60-pic"; + reg = <0000 88>; + interrupt-controller; + }; + + mpp@f000 { + compatible = "marvell,mv64x60-mpp"; + reg = <f000 10>; + }; + + gpp@f100 { + compatible = "marvell,mv64x60-gpp"; + reg = <f100 20>; + }; + + pci@80000000 { + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + compatible = "marvell,mv64x60-pci"; + reg = <0cf8 8>; + ranges = <01000000 0 0 88000000 0 01000000 + 02000000 0 80000000 80000000 0 08000000>; + bus-range = <0 ff>; + clock-frequency = <3EF1480>; + interrupt-pci-iack = <0c34>; + interrupt-parent = <&/mv64x60/pic>; + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + /* IDSEL 0x0a */ + 5000 0 0 1 &/mv64x60/pic 50 + 5000 0 0 2 &/mv64x60/pic 51 + 5000 0 0 3 &/mv64x60/pic 5b + 5000 0 0 4 &/mv64x60/pic 5d + + /* IDSEL 0x0b */ + 5800 0 0 1 &/mv64x60/pic 5b + 5800 0 0 2 &/mv64x60/pic 5d + 5800 0 0 3 &/mv64x60/pic 50 + 5800 0 0 4 &/mv64x60/pic 51 + + /* IDSEL 0x0c */ + 6000 0 0 1 &/mv64x60/pic 5b + 6000 0 0 2 &/mv64x60/pic 5d + 6000 0 0 3 &/mv64x60/pic 50 + 6000 0 0 4 &/mv64x60/pic 51 + + /* IDSEL 0x0d */ + 6800 0 0 1 &/mv64x60/pic 5d + 6800 0 0 2 &/mv64x60/pic 50 + 6800 0 0 3 &/mv64x60/pic 51 + 6800 0 0 4 &/mv64x60/pic 5b + >; + }; + + cpu-error@0070 { + compatible = "marvell,mv64x60-cpu-error"; + reg = <0070 10 0128 28>; + interrupts = <03>; + interrupt-parent = <&/mv64x60/pic>; + }; + + sram-ctrl@0380 { + compatible = "marvell,mv64x60-sram-ctrl"; + reg = <0380 80>; + interrupts = <0d>; + interrupt-parent = <&/mv64x60/pic>; + }; + + pci-error@1d40 { + compatible = "marvell,mv64x60-pci-error"; + reg = <1d40 40 0c28 4>; + interrupts = <0c>; + interrupt-parent = <&/mv64x60/pic>; + }; + + mem-ctrl@1400 { + compatible = "marvell,mv64x60-mem-ctrl"; + reg = <1400 60>; + interrupts = <11>; + interrupt-parent = <&/mv64x60/pic>; + }; + }; + + chosen { + bootargs = "ip=on console=ttyMM0"; + linux,stdout-path = "/mv64x60@f1000000/mpsc@8000"; + }; +}; diff --git a/arch/powerpc/boot/mpsc.c b/arch/powerpc/boot/mpsc.c new file mode 100644 index 0000000..f1c0e96 --- /dev/null +++ b/arch/powerpc/boot/mpsc.c @@ -0,0 +1,170 @@ +/* + * MPSC/UART driver for the Marvell mv64360, mv64460, ... + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#include <stdarg.h> +#include <stddef.h> +#include "types.h" +#include "string.h" +#include "stdio.h" +#include "io.h" +#include "ops.h" + +extern void udelay(long delay); + +#define MPSC_CHR_1 0x000c + +#define MPSC_CHR_2 0x0010 +#define MPSC_CHR_2_TA (1<<7) +#define MPSC_CHR_2_TCS (1<<9) +#define MPSC_CHR_2_RA (1<<23) +#define MPSC_CHR_2_CRD (1<<25) +#define MPSC_CHR_2_EH (1<<31) + +#define MPSC_CHR_4 0x0018 +#define MPSC_CHR_4_Z (1<<29) + +#define MPSC_CHR_5 0x001c +#define MPSC_CHR_5_CTL1_INTR (1<<12) +#define MPSC_CHR_5_CTL1_VALID (1<<15) + +#define MPSC_CHR_10 0x0030 + +#define MPSC_INTR_CAUSE 0x0000 +#define MPSC_INTR_CAUSE_RCC (1<<6) +#define MPSC_INTR_MASK 0x0080 + +#define SDMA_SDCM 0x0008 +#define SDMA_SDCM_AR (1<<15) +#define SDMA_SDCM_AT (1<<31) + +static volatile char *mpsc_base; +static volatile char *mpscintr_base; +static u32 chr1, chr2; + +static int mpsc_open(void) +{ + chr1 = in_le32((u32 *)(mpsc_base + MPSC_CHR_1)) & 0x00ff0000; + chr2 = in_le32((u32 *)(mpsc_base + MPSC_CHR_2)) & ~(MPSC_CHR_2_TA + | MPSC_CHR_2_TCS | MPSC_CHR_2_RA | MPSC_CHR_2_CRD + | MPSC_CHR_2_EH); + out_le32((u32 *)(mpsc_base + MPSC_CHR_4), MPSC_CHR_4_Z); + out_le32((u32 *)(mpsc_base + MPSC_CHR_5), + MPSC_CHR_5_CTL1_INTR | MPSC_CHR_5_CTL1_VALID); + out_le32((u32 *)(mpsc_base + MPSC_CHR_2), chr2 | MPSC_CHR_2_EH); + return 0; +} + +static void mpsc_putc(unsigned char c) +{ + while (in_le32((u32 *)(mpsc_base + MPSC_CHR_2)) & MPSC_CHR_2_TCS); + + out_le32((u32 *)(mpsc_base + MPSC_CHR_1), chr1 | c); + out_le32((u32 *)(mpsc_base + MPSC_CHR_2), chr2 | MPSC_CHR_2_TCS); +} + +static unsigned char mpsc_getc(void) +{ + u32 cause = 0; + unsigned char c; + + while (!(cause & MPSC_INTR_CAUSE_RCC)) + cause = in_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE)); + + c = in_8((u8 *)(mpsc_base + MPSC_CHR_10 + 2)); + out_8((u8 *)(mpsc_base + MPSC_CHR_10 + 2), c); + out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), + cause & ~MPSC_INTR_CAUSE_RCC); + + return c; +} + +static u8 mpsc_tstc(void) +{ + return (u8)((in_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE)) + & MPSC_INTR_CAUSE_RCC) != 0); +} + +static void mpsc_stop_dma(volatile char *sdma_base) +{ + out_le32((u32 *)(mpsc_base + MPSC_CHR_2),MPSC_CHR_2_TA | MPSC_CHR_2_RA); + out_le32((u32 *)(sdma_base + SDMA_SDCM), SDMA_SDCM_AR | SDMA_SDCM_AT); + + while ((in_le32((u32 *)(sdma_base + SDMA_SDCM)) + & (SDMA_SDCM_AR | SDMA_SDCM_AT)) != 0) + udelay(100); +} + +static volatile char *mpsc_get_virtreg_of_phandle(void *devp, char *prop) +{ + void *v; + int n; + + n = getprop(devp, prop, &v, sizeof(v)); + if (n != sizeof(v)) + goto err_out; + + devp = find_node_by_linuxphandle((u32)v); + if (devp == NULL) + goto err_out; + + n = getprop(devp, "virtual-reg", &v, sizeof(v)); + if (n == sizeof(v)) + return v; + +err_out: + return NULL; +} + +int mpsc_console_init(void *devp, struct serial_console_data *scdp) +{ + void *v; + int n, reg_set; + volatile char *sdma_base; + + n = getprop(devp, "virtual-reg", &v, sizeof(v)); + if (n != sizeof(v)) + goto err_out; + mpsc_base = v; + + sdma_base = mpsc_get_virtreg_of_phandle(devp, "sdma"); + if (sdma_base == NULL) + goto err_out; + + mpscintr_base = mpsc_get_virtreg_of_phandle(devp, "mpscintr"); + if (mpscintr_base == NULL) + goto err_out; + + n = getprop(devp, "block-index", &v, sizeof(v)); + if (n != sizeof(v)) + goto err_out; + reg_set = (int)v; + + mpscintr_base += (reg_set == 0) ? 0x4 : 0xc; + + /* Make sure the mpsc ctlrs are shutdown */ + out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), 0); + out_le32((u32 *)(mpscintr_base + MPSC_INTR_CAUSE), 0); + out_le32((u32 *)(mpscintr_base + MPSC_INTR_MASK), 0); + out_le32((u32 *)(mpscintr_base + MPSC_INTR_MASK), 0); + + mpsc_stop_dma(sdma_base); + + scdp->open = mpsc_open; + scdp->putc = mpsc_putc; + scdp->getc = mpsc_getc; + scdp->tstc = mpsc_tstc; + scdp->close = NULL; + + return 0; + +err_out: + return -1; +} diff --git a/arch/powerpc/boot/mv64x60.c b/arch/powerpc/boot/mv64x60.c new file mode 100644 index 0000000..b432594 --- /dev/null +++ b/arch/powerpc/boot/mv64x60.c @@ -0,0 +1,581 @@ +/* + * Marvell hostbridge routines + * + * Author: Mark A. Greer <source@mvista.com> + * + * 2004, 2005, 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#include <stdarg.h> +#include <stddef.h> +#include "types.h" +#include "elf.h" +#include "page.h" +#include "string.h" +#include "stdio.h" +#include "io.h" +#include "ops.h" +#include "mv64x60.h" + +#define PCI_DEVFN(slot,func) ((((slot) & 0x1f) << 3) | ((func) & 0x07)) + +#define MV64x60_CPU2MEM_WINDOWS 4 +#define MV64x60_CPU2MEM_0_BASE 0x0008 +#define MV64x60_CPU2MEM_0_SIZE 0x0010 +#define MV64x60_CPU2MEM_1_BASE 0x0208 +#define MV64x60_CPU2MEM_1_SIZE 0x0210 +#define MV64x60_CPU2MEM_2_BASE 0x0018 +#define MV64x60_CPU2MEM_2_SIZE 0x0020 +#define MV64x60_CPU2MEM_3_BASE 0x0218 +#define MV64x60_CPU2MEM_3_SIZE 0x0220 + +#define MV64x60_ENET2MEM_BAR_ENABLE 0x2290 +#define MV64x60_ENET2MEM_0_BASE 0x2200 +#define MV64x60_ENET2MEM_0_SIZE 0x2204 +#define MV64x60_ENET2MEM_1_BASE 0x2208 +#define MV64x60_ENET2MEM_1_SIZE 0x220c +#define MV64x60_ENET2MEM_2_BASE 0x2210 +#define MV64x60_ENET2MEM_2_SIZE 0x2214 +#define MV64x60_ENET2MEM_3_BASE 0x2218 +#define MV64x60_ENET2MEM_3_SIZE 0x221c +#define MV64x60_ENET2MEM_4_BASE 0x2220 +#define MV64x60_ENET2MEM_4_SIZE 0x2224 +#define MV64x60_ENET2MEM_5_BASE 0x2228 +#define MV64x60_ENET2MEM_5_SIZE 0x222c +#define MV64x60_ENET2MEM_ACC_PROT_0 0x2294 +#define MV64x60_ENET2MEM_ACC_PROT_1 0x2298 +#define MV64x60_ENET2MEM_ACC_PROT_2 0x229c + +#define MV64x60_MPSC2MEM_BAR_ENABLE 0xf250 +#define MV64x60_MPSC2MEM_0_BASE 0xf200 +#define MV64x60_MPSC2MEM_0_SIZE 0xf204 +#define MV64x60_MPSC2MEM_1_BASE 0xf208 +#define MV64x60_MPSC2MEM_1_SIZE 0xf20c +#define MV64x60_MPSC2MEM_2_BASE 0xf210 +#define MV64x60_MPSC2MEM_2_SIZE 0xf214 +#define MV64x60_MPSC2MEM_3_BASE 0xf218 +#define MV64x60_MPSC2MEM_3_SIZE 0xf21c +#define MV64x60_MPSC_0_REMAP 0xf240 +#define MV64x60_MPSC_1_REMAP 0xf244 +#define MV64x60_MPSC2MEM_ACC_PROT_0 0xf254 +#define MV64x60_MPSC2MEM_ACC_PROT_1 0xf258 +#define MV64x60_MPSC2REGS_BASE 0xf25c + +#define MV64x60_IDMA2MEM_BAR_ENABLE 0x0a80 +#define MV64x60_IDMA2MEM_0_BASE 0x0a00 +#define MV64x60_IDMA2MEM_0_SIZE 0x0a04 +#define MV64x60_IDMA2MEM_1_BASE 0x0a08 +#define MV64x60_IDMA2MEM_1_SIZE 0x0a0c +#define MV64x60_IDMA2MEM_2_BASE 0x0a10 +#define MV64x60_IDMA2MEM_2_SIZE 0x0a14 +#define MV64x60_IDMA2MEM_3_BASE 0x0a18 +#define MV64x60_IDMA2MEM_3_SIZE 0x0a1c +#define MV64x60_IDMA2MEM_4_BASE 0x0a20 +#define MV64x60_IDMA2MEM_4_SIZE 0x0a24 +#define MV64x60_IDMA2MEM_5_BASE 0x0a28 +#define MV64x60_IDMA2MEM_5_SIZE 0x0a2c +#define MV64x60_IDMA2MEM_6_BASE 0x0a30 +#define MV64x60_IDMA2MEM_6_SIZE 0x0a34 +#define MV64x60_IDMA2MEM_7_BASE 0x0a38 +#define MV64x60_IDMA2MEM_7_SIZE 0x0a3c +#define MV64x60_IDMA2MEM_ACC_PROT_0 0x0a70 +#define MV64x60_IDMA2MEM_ACC_PROT_1 0x0a74 +#define MV64x60_IDMA2MEM_ACC_PROT_2 0x0a78 +#define MV64x60_IDMA2MEM_ACC_PROT_3 0x0a7c + +#define MV64x60_PCI_ACC_CNTL_WINDOWS 6 +#define MV64x60_PCI0_PCI_DECODE_CNTL 0x0d3c +#define MV64x60_PCI1_PCI_DECODE_CNTL 0x0dbc + +#define MV64x60_PCI0_BAR_ENABLE 0x0c3c +#define MV64x60_PCI02MEM_0_SIZE 0x0c08 +#define MV64x60_PCI0_ACC_CNTL_0_BASE_LO 0x1e00 +#define MV64x60_PCI0_ACC_CNTL_0_BASE_HI 0x1e04 +#define MV64x60_PCI0_ACC_CNTL_0_SIZE 0x1e08 +#define MV64x60_PCI0_ACC_CNTL_1_BASE_LO 0x1e10 +#define MV64x60_PCI0_ACC_CNTL_1_BASE_HI 0x1e14 +#define MV64x60_PCI0_ACC_CNTL_1_SIZE 0x1e18 +#define MV64x60_PCI0_ACC_CNTL_2_BASE_LO 0x1e20 +#define MV64x60_PCI0_ACC_CNTL_2_BASE_HI 0x1e24 +#define MV64x60_PCI0_ACC_CNTL_2_SIZE 0x1e28 +#define MV64x60_PCI0_ACC_CNTL_3_BASE_LO 0x1e30 +#define MV64x60_PCI0_ACC_CNTL_3_BASE_HI 0x1e34 +#define MV64x60_PCI0_ACC_CNTL_3_SIZE 0x1e38 +#define MV64x60_PCI0_ACC_CNTL_4_BASE_LO 0x1e40 +#define MV64x60_PCI0_ACC_CNTL_4_BASE_HI 0x1e44 +#define MV64x60_PCI0_ACC_CNTL_4_SIZE 0x1e48 +#define MV64x60_PCI0_ACC_CNTL_5_BASE_LO 0x1e50 +#define MV64x60_PCI0_ACC_CNTL_5_BASE_HI 0x1e54 +#define MV64x60_PCI0_ACC_CNTL_5_SIZE 0x1e58 + +#define MV64x60_PCI1_BAR_ENABLE 0x0cbc +#define MV64x60_PCI12MEM_0_SIZE 0x0c88 +#define MV64x60_PCI1_ACC_CNTL_0_BASE_LO 0x1e80 +#define MV64x60_PCI1_ACC_CNTL_0_BASE_HI 0x1e84 +#define MV64x60_PCI1_ACC_CNTL_0_SIZE 0x1e88 +#define MV64x60_PCI1_ACC_CNTL_1_BASE_LO 0x1e90 +#define MV64x60_PCI1_ACC_CNTL_1_BASE_HI 0x1e94 +#define MV64x60_PCI1_ACC_CNTL_1_SIZE 0x1e98 +#define MV64x60_PCI1_ACC_CNTL_2_BASE_LO 0x1ea0 +#define MV64x60_PCI1_ACC_CNTL_2_BASE_HI 0x1ea4 +#define MV64x60_PCI1_ACC_CNTL_2_SIZE 0x1ea8 +#define MV64x60_PCI1_ACC_CNTL_3_BASE_LO 0x1eb0 +#define MV64x60_PCI1_ACC_CNTL_3_BASE_HI 0x1eb4 +#define MV64x60_PCI1_ACC_CNTL_3_SIZE 0x1eb8 +#define MV64x60_PCI1_ACC_CNTL_4_BASE_LO 0x1ec0 +#define MV64x60_PCI1_ACC_CNTL_4_BASE_HI 0x1ec4 +#define MV64x60_PCI1_ACC_CNTL_4_SIZE 0x1ec8 +#define MV64x60_PCI1_ACC_CNTL_5_BASE_LO 0x1ed0 +#define MV64x60_PCI1_ACC_CNTL_5_BASE_HI 0x1ed4 +#define MV64x60_PCI1_ACC_CNTL_5_SIZE 0x1ed8 + +#define MV64x60_CPU2PCI_SWAP_NONE 0x01000000 + +#define MV64x60_CPU2PCI0_IO_BASE 0x0048 +#define MV64x60_CPU2PCI0_IO_SIZE 0x0050 +#define MV64x60_CPU2PCI0_IO_REMAP 0x00f0 +#define MV64x60_CPU2PCI0_MEM_0_BASE 0x0058 +#define MV64x60_CPU2PCI0_MEM_0_SIZE 0x0060 +#define MV64x60_CPU2PCI0_MEM_0_REMAP_LO 0x00f8 +#define MV64x60_CPU2PCI0_MEM_0_REMAP_HI 0x0320 + +#define MV64x60_CPU2PCI1_IO_BASE 0x0090 +#define MV64x60_CPU2PCI1_IO_SIZE 0x0098 +#define MV64x60_CPU2PCI1_IO_REMAP 0x0108 +#define MV64x60_CPU2PCI1_MEM_0_BASE 0x00a0 +#define MV64x60_CPU2PCI1_MEM_0_SIZE 0x00a8 +#define MV64x60_CPU2PCI1_MEM_0_REMAP_LO 0x0110 +#define MV64x60_CPU2PCI1_MEM_0_REMAP_HI 0x0340 + +struct mv64x60_mem_win { + u32 hi; + u32 lo; + u32 size; +}; + +struct mv64x60_pci_win { + u32 fcn; + u32 hi; + u32 lo; + u32 size; +}; + +/* PCI config access routines */ +struct { + u32 addr; + u32 data; +} static mv64x60_pci_cfgio[2] = { + { /* hose 0 */ + .addr = 0xcf8, + .data = 0xcfc, + }, + { /* hose 1 */ + .addr = 0xc78, + .data = 0xc7c, + } +}; + +u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset) +{ + out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr), + (1 << 31) | (bus << 16) | (devfn << 8) | offset); + return in_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data)); +} + +void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, u8 offset, + u32 val) +{ + out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].addr), + (1 << 31) | (bus << 16) | (devfn << 8) | offset); + out_le32((u32 *)(bridge_base + mv64x60_pci_cfgio[hose].data), val); +} + +/* I/O ctlr -> system memory setup */ +static struct mv64x60_mem_win mv64x60_cpu2mem[MV64x60_CPU2MEM_WINDOWS] = { + { + .lo = MV64x60_CPU2MEM_0_BASE, + .size = MV64x60_CPU2MEM_0_SIZE, + }, + { + .lo = MV64x60_CPU2MEM_1_BASE, + .size = MV64x60_CPU2MEM_1_SIZE, + }, + { + .lo = MV64x60_CPU2MEM_2_BASE, + .size = MV64x60_CPU2MEM_2_SIZE, + }, + { + .lo = MV64x60_CPU2MEM_3_BASE, + .size = MV64x60_CPU2MEM_3_SIZE, + }, +}; + +static struct mv64x60_mem_win mv64x60_enet2mem[MV64x60_CPU2MEM_WINDOWS] = { + { + .lo = MV64x60_ENET2MEM_0_BASE, + .size = MV64x60_ENET2MEM_0_SIZE, + }, + { + .lo = MV64x60_ENET2MEM_1_BASE, + .size = MV64x60_ENET2MEM_1_SIZE, + }, + { + .lo = MV64x60_ENET2MEM_2_BASE, + .size = MV64x60_ENET2MEM_2_SIZE, + }, + { + .lo = MV64x60_ENET2MEM_3_BASE, + .size = MV64x60_ENET2MEM_3_SIZE, + }, +}; + +static struct mv64x60_mem_win mv64x60_mpsc2mem[MV64x60_CPU2MEM_WINDOWS] = { + { + .lo = MV64x60_MPSC2MEM_0_BASE, + .size = MV64x60_MPSC2MEM_0_SIZE, + }, + { + .lo = MV64x60_MPSC2MEM_1_BASE, + .size = MV64x60_MPSC2MEM_1_SIZE, + }, + { + .lo = MV64x60_MPSC2MEM_2_BASE, + .size = MV64x60_MPSC2MEM_2_SIZE, + }, + { + .lo = MV64x60_MPSC2MEM_3_BASE, + .size = MV64x60_MPSC2MEM_3_SIZE, + }, +}; + +static struct mv64x60_mem_win mv64x60_idma2mem[MV64x60_CPU2MEM_WINDOWS] = { + { + .lo = MV64x60_IDMA2MEM_0_BASE, + .size = MV64x60_IDMA2MEM_0_SIZE, + }, + { + .lo = MV64x60_IDMA2MEM_1_BASE, + .size = MV64x60_IDMA2MEM_1_SIZE, + }, + { + .lo = MV64x60_IDMA2MEM_2_BASE, + .size = MV64x60_IDMA2MEM_2_SIZE, + }, + { + .lo = MV64x60_IDMA2MEM_3_BASE, + .size = MV64x60_IDMA2MEM_3_SIZE, + }, +}; + +static u32 mv64x60_dram_selects[MV64x60_CPU2MEM_WINDOWS] = {0xe,0xd,0xb,0x7}; + +/* + * ENET, MPSC, and IDMA ctlrs on the MV64x60 have separate windows that + * must be set up so that the respective ctlr can access system memory. + * Configure them to be same as cpu->memory windows. + */ +void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase, + u8 is_coherent) +{ + u32 i, base, size, enables, prot = 0, snoop_bits = 0; + + /* Disable ctlr->mem windows */ + out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0x3f); + out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), 0xf); + out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), 0xff); + + if (is_coherent) + snoop_bits = 0x2 << 12; /* Writeback */ + + enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf; + + for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) { + if (enables & (1 << i)) /* Set means disabled */ + continue; + + base = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].lo)) + << 16; + base |= snoop_bits | (mv64x60_dram_selects[i] << 8); + size = in_le32((u32 *)(bridge_base + mv64x60_cpu2mem[i].size)) + << 16; + prot |= (0x3 << (i << 1)); /* RW access */ + + out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].lo), base); + out_le32((u32 *)(bridge_base + mv64x60_enet2mem[i].size), size); + out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].lo), base); + out_le32((u32 *)(bridge_base + mv64x60_mpsc2mem[i].size), size); + out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].lo), base); + out_le32((u32 *)(bridge_base + mv64x60_idma2mem[i].size), size); + } + + out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_0), prot); + out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_1), prot); + out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_ACC_PROT_2), prot); + out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_0), prot); + out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_ACC_PROT_1), prot); + out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_0), prot); + out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_1), prot); + out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_2), prot); + out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_ACC_PROT_3), prot); + + /* Set mpsc->bridge's reg window to the bridge's internal registers. */ + out_le32((u32 *)(bridge_base + MV64x60_MPSC2REGS_BASE), + (u32)bridge_pbase); + + out_le32((u32 *)(bridge_base + MV64x60_ENET2MEM_BAR_ENABLE), enables); + out_le32((u32 *)(bridge_base + MV64x60_MPSC2MEM_BAR_ENABLE), enables); + out_le32((u32 *)(bridge_base + MV64x60_IDMA2MEM_BAR_ENABLE), enables); +} + +/* PCI MEM -> system memory, et. al. setup */ +static struct mv64x60_pci_win mv64x60_pci2mem[2] = { + { /* hose 0 */ + .fcn = 0, + .hi = 0x14, + .lo = 0x10, + .size = MV64x60_PCI02MEM_0_SIZE, + }, + { /* hose 1 */ + .fcn = 0, + .hi = 0x94, + .lo = 0x90, + .size = MV64x60_PCI12MEM_0_SIZE, + }, +}; + +static struct +mv64x60_mem_win mv64x60_pci_acc[2][MV64x60_PCI_ACC_CNTL_WINDOWS] = { + { /* hose 0 */ + { + .hi = MV64x60_PCI0_ACC_CNTL_0_BASE_HI, + .lo = MV64x60_PCI0_ACC_CNTL_0_BASE_LO, + .size = MV64x60_PCI0_ACC_CNTL_0_SIZE, + }, + { + .hi = MV64x60_PCI0_ACC_CNTL_1_BASE_HI, + .lo = MV64x60_PCI0_ACC_CNTL_1_BASE_LO, + .size = MV64x60_PCI0_ACC_CNTL_1_SIZE, + }, + { + .hi = MV64x60_PCI0_ACC_CNTL_2_BASE_HI, + .lo = MV64x60_PCI0_ACC_CNTL_2_BASE_LO, + .size = MV64x60_PCI0_ACC_CNTL_2_SIZE, + }, + { + .hi = MV64x60_PCI0_ACC_CNTL_3_BASE_HI, + .lo = MV64x60_PCI0_ACC_CNTL_3_BASE_LO, + .size = MV64x60_PCI0_ACC_CNTL_3_SIZE, + }, + }, + { /* hose 1 */ + { + .hi = MV64x60_PCI1_ACC_CNTL_0_BASE_HI, + .lo = MV64x60_PCI1_ACC_CNTL_0_BASE_LO, + .size = MV64x60_PCI1_ACC_CNTL_0_SIZE, + }, + { + .hi = MV64x60_PCI1_ACC_CNTL_1_BASE_HI, + .lo = MV64x60_PCI1_ACC_CNTL_1_BASE_LO, + .size = MV64x60_PCI1_ACC_CNTL_1_SIZE, + }, + { + .hi = MV64x60_PCI1_ACC_CNTL_2_BASE_HI, + .lo = MV64x60_PCI1_ACC_CNTL_2_BASE_LO, + .size = MV64x60_PCI1_ACC_CNTL_2_SIZE, + }, + { + .hi = MV64x60_PCI1_ACC_CNTL_3_BASE_HI, + .lo = MV64x60_PCI1_ACC_CNTL_3_BASE_LO, + .size = MV64x60_PCI1_ACC_CNTL_3_SIZE, + }, + }, +}; + +static struct mv64x60_mem_win mv64x60_pci2reg[2] = { + { + .hi = 0x24, + .lo = 0x20, + .size = 0, + }, + { + .hi = 0xa4, + .lo = 0xa0, + .size = 0, + }, +}; + +/* Only need to use 1 window (per hose) to get access to all of system memory */ +void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose, + u8 bus, u32 mem_size, u32 acc_bits) +{ + u32 i, offset, bar_enable, enables; + + /* Disable all windows but PCI MEM -> Bridge's regs window */ + enables = ~(1 << 9); + bar_enable = hose ? MV64x60_PCI1_BAR_ENABLE : MV64x60_PCI0_BAR_ENABLE; + out_le32((u32 *)(bridge_base + bar_enable), enables); + + for (i=0; i<MV64x60_PCI_ACC_CNTL_WINDOWS; i++) + out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][i].lo), 0); + + /* If mem_size is 0, leave windows disabled */ + if (mem_size == 0) + return; + + /* Cause automatic updates of PCI remap regs */ + offset = hose ? + MV64x60_PCI1_PCI_DECODE_CNTL : MV64x60_PCI0_PCI_DECODE_CNTL; + i = in_le32((u32 *)(bridge_base + offset)); + out_le32((u32 *)(bridge_base + offset), i & ~0x1); + + mem_size = (mem_size - 1) & 0xfffff000; + + /* Map PCI MEM addr 0 -> System Mem addr 0 */ + mv64x60_cfg_write(bridge_base, hose, bus, + PCI_DEVFN(0, mv64x60_pci2mem[hose].fcn), + mv64x60_pci2mem[hose].hi, 0); + mv64x60_cfg_write(bridge_base, hose, bus, + PCI_DEVFN(0, mv64x60_pci2mem[hose].fcn), + mv64x60_pci2mem[hose].lo, 0); + out_le32((u32 *)(bridge_base + mv64x60_pci2mem[hose].size),mem_size); + + acc_bits |= MV64x60_PCI_ACC_CNTL_ENABLE; + out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].hi), 0); + out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].lo), acc_bits); + out_le32((u32 *)(bridge_base + mv64x60_pci_acc[hose][0].size),mem_size); + + /* Set PCI MEM->bridge's reg window to where they are in CPU mem map */ + i = (u32)bridge_base; + i &= 0xffff0000; + i |= (0x2 << 1); + mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0), + mv64x60_pci2reg[hose].hi, 0); + mv64x60_cfg_write(bridge_base, hose, bus, PCI_DEVFN(0,0), + mv64x60_pci2reg[hose].lo, i); + + enables &= ~0x1; /* Enable PCI MEM -> System Mem window 0 */ + out_le32((u32 *)(bridge_base + bar_enable), enables); +} + +/* CPU -> PCI I/O & MEM setup */ +struct mv64x60_cpu2pci_win mv64x60_cpu2pci_io[2] = { + { /* hose 0 */ + .lo = MV64x60_CPU2PCI0_IO_BASE, + .size = MV64x60_CPU2PCI0_IO_SIZE, + .remap_hi = 0, + .remap_lo = MV64x60_CPU2PCI0_IO_REMAP, + }, + { /* hose 1 */ + .lo = MV64x60_CPU2PCI1_IO_BASE, + .size = MV64x60_CPU2PCI1_IO_SIZE, + .remap_hi = 0, + .remap_lo = MV64x60_CPU2PCI1_IO_REMAP, + }, +}; + +struct mv64x60_cpu2pci_win mv64x60_cpu2pci_mem[2] = { + { /* hose 0 */ + .lo = MV64x60_CPU2PCI0_MEM_0_BASE, + .size = MV64x60_CPU2PCI0_MEM_0_SIZE, + .remap_hi = MV64x60_CPU2PCI0_MEM_0_REMAP_HI, + .remap_lo = MV64x60_CPU2PCI0_MEM_0_REMAP_LO, + }, + { /* hose 1 */ + .lo = MV64x60_CPU2PCI1_MEM_0_BASE, + .size = MV64x60_CPU2PCI1_MEM_0_SIZE, + .remap_hi = MV64x60_CPU2PCI1_MEM_0_REMAP_HI, + .remap_lo = MV64x60_CPU2PCI1_MEM_0_REMAP_LO, + }, +}; + +/* Only need to set up 1 window to pci mem space */ +void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi, + u32 pci_base_lo, u32 cpu_base, u32 size, + struct mv64x60_cpu2pci_win *offset_tbl) +{ + cpu_base >>= 16; + cpu_base |= MV64x60_CPU2PCI_SWAP_NONE; + out_le32((u32 *)(bridge_base + offset_tbl[hose].lo), cpu_base); + + if (offset_tbl[hose].remap_hi != 0) + out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_hi), + pci_base_hi); + out_le32((u32 *)(bridge_base + offset_tbl[hose].remap_lo), + pci_base_lo >> 16); + + size = (size - 1) >> 16; + out_le32((u32 *)(bridge_base + offset_tbl[hose].size), size); +} + +/* Read mem ctlr to get the amount of mem in system */ +u32 mv64x60_get_mem_size(u8 *bridge_base) +{ + u32 enables, i, v; + u32 mem = 0; + + enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)) & 0xf; + + for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) + if (!(enables & (1<<i))) { + v = in_le32((u32*)(bridge_base + + mv64x60_cpu2mem[i].size)); + v = ((v & 0xffff) + 1) << 16; + mem += v; + } + + return mem; +} + +/* Get physical address of bridge's registers */ +u8 *mv64x60_get_bridge_pbase(void) +{ + u32 v[2]; + void *devp; + + devp = finddevice("/mv64x60"); + if (devp == NULL) + goto err_out; + if (getprop(devp, "reg", v, sizeof(v)) != sizeof(v)) + goto err_out; + + return (u8 *)v[0]; + +err_out: + return 0; +} + +/* Get virtual address of bridge's registers */ +u8 *mv64x60_get_bridge_base(void) +{ + u32 v; + void *devp; + + devp = finddevice("/mv64x60"); + if (devp == NULL) + goto err_out; + if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v)) + goto err_out; + + return (u8 *)v; + +err_out: + return 0; +} + +u8 mv64x60_is_coherent(void) +{ + u32 v; + void *devp; + + devp = finddevice("/"); + if (devp == NULL) + return 1; /* Assume coherency on */ + + if (getprop(devp, "coherency-off", &v, sizeof(v)) < 0) + return 1; /* Coherency on */ + else + return 0; +} diff --git a/arch/powerpc/boot/mv64x60.h b/arch/powerpc/boot/mv64x60.h new file mode 100644 index 0000000..b827105 --- /dev/null +++ b/arch/powerpc/boot/mv64x60.h @@ -0,0 +1,70 @@ +/* + * Author: Mark A. Greer <source@mvista.com> + * + * 2007 (c) MontaVista Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#ifndef _PPC_BOOT_MV64x60_H_ +#define _PPC_BOOT_MV64x60_H_ + +#define MV64x60_CPU_BAR_ENABLE 0x0278 + +#define MV64x60_PCI_ACC_CNTL_ENABLE (1<<0) +#define MV64x60_PCI_ACC_CNTL_REQ64 (1<<1) +#define MV64x60_PCI_ACC_CNTL_SNOOP_NONE 0x00000000 +#define MV64x60_PCI_ACC_CNTL_SNOOP_WT 0x00000004 +#define MV64x60_PCI_ACC_CNTL_SNOOP_WB 0x00000008 +#define MV64x60_PCI_ACC_CNTL_SNOOP_MASK 0x0000000c +#define MV64x60_PCI_ACC_CNTL_ACCPROT (1<<4) +#define MV64x60_PCI_ACC_CNTL_WRPROT (1<<5) +#define MV64x60_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 +#define MV64x60_PCI_ACC_CNTL_SWAP_NONE 0x00000040 +#define MV64x60_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x00000080 +#define MV64x60_PCI_ACC_CNTL_SWAP_WORD 0x000000c0 +#define MV64x60_PCI_ACC_CNTL_SWAP_MASK 0x000000c0 +#define MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES 0x00000000 +#define MV64x60_PCI_ACC_CNTL_MBURST_64_BYTES 0x00000100 +#define MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES 0x00000200 +#define MV64x60_PCI_ACC_CNTL_MBURST_MASK 0x00000300 +#define MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES 0x00000000 +#define MV64x60_PCI_ACC_CNTL_RDSIZE_64_BYTES 0x00000400 +#define MV64x60_PCI_ACC_CNTL_RDSIZE_128_BYTES 0x00000800 +#define MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES 0x00000c00 +#define MV64x60_PCI_ACC_CNTL_RDSIZE_MASK 0x00000c00 + +struct mv64x60_cpu2pci_win { + u32 lo; + u32 size; + u32 remap_hi; + u32 remap_lo; +}; + +extern struct mv64x60_cpu2pci_win mv64x60_cpu2pci_io[2]; +extern struct mv64x60_cpu2pci_win mv64x60_cpu2pci_mem[2]; + +u32 mv64x60_cfg_read(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, + u8 offset); +void mv64x60_cfg_write(u8 *bridge_base, u8 hose, u8 bus, u8 devfn, + u8 offset, u32 val); + +void mv64x60_config_ctlr_windows(u8 *bridge_base, u8 *bridge_pbase, + u8 is_coherent); +void mv64x60_config_pci_windows(u8 *bridge_base, u8 *bridge_pbase, u8 hose, + u8 bus, u32 mem_size, u32 acc_bits); +void mv64x60_config_cpu2pci_window(u8 *bridge_base, u8 hose, u32 pci_base_hi, + u32 pci_base_lo, u32 cpu_base, u32 size, + struct mv64x60_cpu2pci_win *offset_tbl); +u32 mv64x60_get_mem_size(u8 *bridge_base); +u8 *mv64x60_get_bridge_pbase(void); +u8 *mv64x60_get_bridge_base(void); +u8 mv64x60_is_coherent(void); + +int mv64x60_i2c_open(void); +int mv64x60_i2c_read(u32 devaddr, u8 *buf, u32 offset, u32 offset_size, + u32 count); +void mv64x60_i2c_close(void); + +#endif /* _PPC_BOOT_MV64x60_H_ */ diff --git a/arch/powerpc/boot/mv64x60_i2c.c b/arch/powerpc/boot/mv64x60_i2c.c new file mode 100644 index 0000000..435fe85 --- /dev/null +++ b/arch/powerpc/boot/mv64x60_i2c.c @@ -0,0 +1,206 @@ +/* + * Bootloader version of the i2c driver for the MV64x60. + * + * Author: Dale Farnsworth <dfarnsworth@mvista.com> + * Maintained by: Mark A. Greer <mgreer@mvista.com> + * + * 2003, 2007 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program is + * licensed "as is" without any warranty of any kind, whether express or + * implied. + */ + +#include <stdarg.h> +#include <stddef.h> +#include "types.h" +#include "elf.h" +#include "page.h" +#include "string.h" +#include "stdio.h" +#include "io.h" +#include "ops.h" +#include "mv64x60.h" + +extern void udelay(long); + +/* Register defines */ +#define MV64x60_I2C_REG_SLAVE_ADDR 0x00 +#define MV64x60_I2C_REG_DATA 0x04 +#define MV64x60_I2C_REG_CONTROL 0x08 +#define MV64x60_I2C_REG_STATUS 0x0c +#define MV64x60_I2C_REG_BAUD 0x0c +#define MV64x60_I2C_REG_EXT_SLAVE_ADDR 0x10 +#define MV64x60_I2C_REG_SOFT_RESET 0x1c + +#define MV64x60_I2C_CONTROL_ACK 0x04 +#define MV64x60_I2C_CONTROL_IFLG 0x08 +#define MV64x60_I2C_CONTROL_STOP 0x10 +#define MV64x60_I2C_CONTROL_START 0x20 +#define MV64x60_I2C_CONTROL_TWSIEN 0x40 +#define MV64x60_I2C_CONTROL_INTEN 0x80 + +#define MV64x60_I2C_STATUS_BUS_ERR 0x00 +#define MV64x60_I2C_STATUS_MAST_START 0x08 +#define MV64x60_I2C_STATUS_MAST_REPEAT_START 0x10 +#define MV64x60_I2C_STATUS_MAST_WR_ADDR_ACK 0x18 +#define MV64x60_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20 +#define MV64x60_I2C_STATUS_MAST_WR_ACK 0x28 +#define MV64x60_I2C_STATUS_MAST_WR_NO_ACK 0x30 +#define MV64x60_I2C_STATUS_MAST_LOST_ARB 0x38 +#define MV64x60_I2C_STATUS_MAST_RD_ADDR_ACK 0x40 +#define MV64x60_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48 +#define MV64x60_I2C_STATUS_MAST_RD_DATA_ACK 0x50 +#define MV64x60_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58 +#define MV64x60_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0 +#define MV64x60_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8 +#define MV64x60_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0 +#define MV64x60_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8 +#define MV64x60_I2C_STATUS_NO_STATUS 0xf8 + +static u8 *ctlr_base; + +static int mv64x60_i2c_wait_for_status(int wanted) +{ + int i; + int status; + + for (i=0; i<1000; i++) { + udelay(10); + status = in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_STATUS)) + & 0xff; + if (status == wanted) + return status; + } + return -status; +} + +static int mv64x60_i2c_control(int control, int status) +{ + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); + return mv64x60_i2c_wait_for_status(status); +} + +static int mv64x60_i2c_read_byte(int control, int status) +{ + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); + if (mv64x60_i2c_wait_for_status(status) < 0) + return -1; + return in_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA)) & 0xff; +} + +static int mv64x60_i2c_write_byte(int data, int control, int status) +{ + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_DATA), data & 0xff); + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_CONTROL), control & 0xff); + return mv64x60_i2c_wait_for_status(status); +} + +int mv64x60_i2c_read(u32 devaddr, u8 *buf, u32 offset, u32 offset_size, + u32 count) +{ + int i; + int data; + int control; + int status; + + if (ctlr_base == NULL) + return -1; + + /* send reset */ + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SOFT_RESET), 0); + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_SLAVE_ADDR), 0); + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_EXT_SLAVE_ADDR), 0); + out_le32((u32 *)(ctlr_base + MV64x60_I2C_REG_BAUD), (4 << 3) | 0x4); + + if (mv64x60_i2c_control(MV64x60_I2C_CONTROL_TWSIEN, + MV64x60_I2C_STATUS_NO_STATUS) < 0) + return -1; + + /* send start */ + control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN; + status = MV64x60_I2C_STATUS_MAST_START; + if (mv64x60_i2c_control(control, status) < 0) + return -1; + + /* select device for writing */ + data = devaddr & ~0x1; + control = MV64x60_I2C_CONTROL_TWSIEN; + status = MV64x60_I2C_STATUS_MAST_WR_ADDR_ACK; + if (mv64x60_i2c_write_byte(data, control, status) < 0) + return -1; + + /* send offset of data */ + control = MV64x60_I2C_CONTROL_TWSIEN; + status = MV64x60_I2C_STATUS_MAST_WR_ACK; + if (offset_size > 1) { + if (mv64x60_i2c_write_byte(offset >> 8, control, status) < 0) + return -1; + } + if (mv64x60_i2c_write_byte(offset, control, status) < 0) + return -1; + + /* resend start */ + control = MV64x60_I2C_CONTROL_START | MV64x60_I2C_CONTROL_TWSIEN; + status = MV64x60_I2C_STATUS_MAST_REPEAT_START; + if (mv64x60_i2c_control(control, status) < 0) + return -1; + + /* select device for reading */ + data = devaddr | 0x1; + control = MV64x60_I2C_CONTROL_TWSIEN; + status = MV64x60_I2C_STATUS_MAST_RD_ADDR_ACK; + if (mv64x60_i2c_write_byte(data, control, status) < 0) + return -1; + + /* read all but last byte of data */ + control = MV64x60_I2C_CONTROL_ACK | MV64x60_I2C_CONTROL_TWSIEN; + status = MV64x60_I2C_STATUS_MAST_RD_DATA_ACK; + + for (i=1; i<count; i++) { + data = mv64x60_i2c_read_byte(control, status); + if (data < 0) { + printf("errors on iteration %d\n", i); + return -1; + } + *buf++ = data; + } + + /* read last byte of data */ + control = MV64x60_I2C_CONTROL_TWSIEN; + status = MV64x60_I2C_STATUS_MAST_RD_DATA_NO_ACK; + data = mv64x60_i2c_read_byte(control, status); + if (data < 0) + return -1; + *buf++ = data; + + /* send stop */ + control = MV64x60_I2C_CONTROL_STOP | MV64x60_I2C_CONTROL_TWSIEN; + status = MV64x60_I2C_STATUS_NO_STATUS; + if (mv64x60_i2c_control(control, status) < 0) + return -1; + + return count; +} + +int mv64x60_i2c_open(void) +{ + u32 v; + void *devp; + + devp = finddevice("/mv64x60/i2c"); + if (devp == NULL) + goto err_out; + if (getprop(devp, "virtual-reg", &v, sizeof(v)) != sizeof(v)) + goto err_out; + + ctlr_base = (u8 *)v; + return 0; + +err_out: + return -1; +} + +void mv64x60_i2c_close(void) +{ + ctlr_base = NULL; +} diff --git a/arch/powerpc/boot/ops.h b/arch/powerpc/boot/ops.h index 73bd47a..959124f 100644 --- a/arch/powerpc/boot/ops.h +++ b/arch/powerpc/boot/ops.h @@ -79,6 +79,7 @@ void start(void); int ft_init(void *dt_blob, unsigned int max_size, unsigned int max_find_device); int serial_console_init(void); int ns16550_console_init(void *devp, struct serial_console_data *scdp); +int mpsc_console_init(void *devp, struct serial_console_data *scdp); void *simple_alloc_init(char *base, unsigned long heap_size, unsigned long granularity, unsigned long max_allocs); extern void flush_cache(void *, unsigned long); diff --git a/arch/powerpc/boot/prpmc2800.c b/arch/powerpc/boot/prpmc2800.c new file mode 100644 index 0000000..f428bac --- /dev/null +++ b/arch/powerpc/boot/prpmc2800.c @@ -0,0 +1,577 @@ +/* + * Motorola ECC prpmc280/f101 & prpmc2800/f101e platform code. + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * 2007 (c) MontaVista, Software, Inc. This file is licensed under + * the terms of the GNU General Public License version 2. This program + * is licensed "as is" without any warranty of any kind, whether express + * or implied. + */ + +#include <stdarg.h> +#include <stddef.h> +#include "types.h" +#include "elf.h" +#include "page.h" +#include "string.h" +#include "stdio.h" +#include "io.h" +#include "ops.h" +#include "gunzip_util.h" +#include "mv64x60.h" + +extern char _end[]; +extern char _vmlinux_start[], _vmlinux_end[]; +extern char _dtb_start[], _dtb_end[]; + +extern void udelay(long delay); + +#define KB 1024U +#define MB (KB*KB) +#define GB (KB*MB) +#define MHz (1000U*1000U) +#define GHz (1000U*MHz) + +#define BOARD_MODEL "PrPMC2800" +#define BOARD_MODEL_MAX 32 /* max strlen(BOARD_MODEL) + 1 */ + +#define EEPROM2_ADDR 0xa4 +#define EEPROM3_ADDR 0xa8 + +BSS_STACK(16*KB); + +static u8 *bridge_base; + +typedef enum { + BOARD_MODEL_PRPMC280, + BOARD_MODEL_PRPMC2800, +} prpmc2800_board_model; + +typedef enum { + BRIDGE_TYPE_MV64360, + BRIDGE_TYPE_MV64362, +} prpmc2800_bridge_type; + +struct prpmc2800_board_info { + prpmc2800_board_model model; + char variant; + prpmc2800_bridge_type bridge_type; + u8 subsys0; + u8 subsys1; + u8 vpd4; + u8 vpd4_mask; + u32 core_speed; + u32 mem_size; + u32 boot_flash; + u32 user_flash; +}; + +static struct prpmc2800_board_info prpmc2800_board_info[] = { + { + .model = BOARD_MODEL_PRPMC280, + .variant = 'a', + .bridge_type = BRIDGE_TYPE_MV64360, + .subsys0 = 0xff, + .subsys1 = 0xff, + .vpd4 = 0x00, + .vpd4_mask = 0x0f, + .core_speed = 1*GHz, + .mem_size = 512*MB, + .boot_flash = 1*MB, + .user_flash = 64*MB, + }, + { + .model = BOARD_MODEL_PRPMC280, + .variant = 'b', + .bridge_type = BRIDGE_TYPE_MV64362, + .subsys0 = 0xff, + .subsys1 = 0xff, + .vpd4 = 0x01, + .vpd4_mask = 0x0f, + .core_speed = 1*GHz, + .mem_size = 512*MB, + .boot_flash = 0, + .user_flash = 0, + }, + { + .model = BOARD_MODEL_PRPMC280, + .variant = 'c', + .bridge_type = BRIDGE_TYPE_MV64360, + .subsys0 = 0xff, + .subsys1 = 0xff, + .vpd4 = 0x02, + .vpd4_mask = 0x0f, + .core_speed = 733*MHz, + .mem_size = 512*MB, + .boot_flash = 1*MB, + .user_flash = 64*MB, + }, + { + .model = BOARD_MODEL_PRPMC280, + .variant = 'd', + .bridge_type = BRIDGE_TYPE_MV64360, + .subsys0 = 0xff, + .subsys1 = 0xff, + .vpd4 = 0x03, + .vpd4_mask = 0x0f, + .core_speed = 1*GHz, + .mem_size = 1*GB, + .boot_flash = 1*MB, + .user_flash = 64*MB, + }, + { + .model = BOARD_MODEL_PRPMC280, + .variant = 'e', + .bridge_type = BRIDGE_TYPE_MV64360, + .subsys0 = 0xff, + .subsys1 = 0xff, + .vpd4 = 0x04, + .vpd4_mask = 0x0f, + .core_speed = 1*GHz, + .mem_size = 512*MB, + .boot_flash = 1*MB, + .user_flash = 64*MB, + }, + { + .model = BOARD_MODEL_PRPMC280, + .variant = 'f', + .bridge_type = BRIDGE_TYPE_MV64362, + .subsys0 = 0xff, + .subsys1 = 0xff, + .vpd4 = 0x05, + .vpd4_mask = 0x0f, + .core_speed = 733*MHz, + .mem_size = 128*MB, + .boot_flash = 1*MB, + .user_flash = 0, + }, + { + .model = BOARD_MODEL_PRPMC280, + .variant = 'g', + .bridge_type = BRIDGE_TYPE_MV64360, + .subsys0 = 0xff, + .subsys1 = 0xff, + .vpd4 = 0x06, + .vpd4_mask = 0x0f, + .core_speed = 1*GHz, + .mem_size = 256*MB, + .boot_flash = 1*MB, + .user_flash = 0, + }, + { + .model = BOARD_MODEL_PRPMC280, + .variant = 'h', + .bridge_type = BRIDGE_TYPE_MV64360, + .subsys0 = 0xff, + .subsys1 = 0xff, + .vpd4 = 0x07, + .vpd4_mask = 0x0f, + .core_speed = 1*GHz, + .mem_size = 1*GB, + .boot_flash = 1*MB, + .user_flash = 64*MB, + }, + { + .model = BOARD_MODEL_PRPMC2800, + .variant = 'a', + .bridge_type = BRIDGE_TYPE_MV64360, + .subsys0 = 0xb2, + .subsys1 = 0x8c, + .vpd4 = 0x00, + .vpd4_mask = 0x00, + .core_speed = 1*GHz, + .mem_size = 512*MB, + .boot_flash = 2*MB, + .user_flash = 64*MB, + }, + { + .model = BOARD_MODEL_PRPMC2800, + .variant = 'b', + .bridge_type = BRIDGE_TYPE_MV64362, + .subsys0 = 0xb2, + .subsys1 = 0x8d, + .vpd4 = 0x00, + .vpd4_mask = 0x00, + .core_speed = 1*GHz, + .mem_size = 512*MB, + .boot_flash = 0, + .user_flash = 0, + }, + { + .model = BOARD_MODEL_PRPMC2800, + .variant = 'c', + .bridge_type = BRIDGE_TYPE_MV64360, + .subsys0 = 0xb2, + .subsys1 = 0x8e, + .vpd4 = 0x00, + .vpd4_mask = 0x00, + .core_speed = 733*MHz, + .mem_size = 512*MB, + .boot_flash = 2*MB, + .user_flash = 64*MB, + }, + { + .model = BOARD_MODEL_PRPMC2800, + .variant = 'd', + .bridge_type = BRIDGE_TYPE_MV64360, + .subsys0 = 0xb2, + .subsys1 = 0x8f, + .vpd4 = 0x00, + .vpd4_mask = 0x00, + .core_speed = 1*GHz, + .mem_size = 1*GB, + .boot_flash = 2*MB, + .user_flash = 64*MB, + }, + { + .model = BOARD_MODEL_PRPMC2800, + .variant = 'e', + .bridge_type = BRIDGE_TYPE_MV64360, + .subsys0 = 0xa2, + .subsys1 = 0x8a, + .vpd4 = 0x00, + .vpd4_mask = 0x00, + .core_speed = 1*GHz, + .mem_size = 512*MB, + .boot_flash = 2*MB, + .user_flash = 64*MB, + }, + { + .model = BOARD_MODEL_PRPMC2800, + .variant = 'f', + .bridge_type = BRIDGE_TYPE_MV64362, + .subsys0 = 0xa2, + .subsys1 = 0x8b, + .vpd4 = 0x00, + .vpd4_mask = 0x00, + .core_speed = 733*MHz, + .mem_size = 128*MB, + .boot_flash = 2*MB, + .user_flash = 0, + }, + { + .model = BOARD_MODEL_PRPMC2800, + .variant = 'g', + .bridge_type = BRIDGE_TYPE_MV64360, + .subsys0 = 0xa2, + .subsys1 = 0x8c, + .vpd4 = 0x00, + .vpd4_mask = 0x00, + .core_speed = 1*GHz, + .mem_size = 2*GB, + .boot_flash = 2*MB, + .user_flash = 64*MB, + }, + { + .model = BOARD_MODEL_PRPMC2800, + .variant = 'h', + .bridge_type = BRIDGE_TYPE_MV64360, + .subsys0 = 0xa2, + .subsys1 = 0x8d, + .vpd4 = 0x00, + .vpd4_mask = 0x00, + .core_speed = 733*MHz, + .mem_size = 1*GB, + .boot_flash = 2*MB, + .user_flash = 64*MB, + }, +}; + +static struct prpmc2800_board_info *prpmc2800_get_board_info(u8 *vpd) +{ + struct prpmc2800_board_info *bip; + int i; + + for (i=0,bip=prpmc2800_board_info; i<ARRAY_SIZE(prpmc2800_board_info); + i++,bip++) + if ((vpd[0] == bip->subsys0) && (vpd[1] == bip->subsys1) + && ((vpd[4] & bip->vpd4_mask) == bip->vpd4)) + return bip; + + return NULL; +} + +/* Get VPD from i2c eeprom 2, then match it to a board info entry */ +static struct prpmc2800_board_info *prpmc2800_get_bip(void) +{ + struct prpmc2800_board_info *bip; + u8 vpd[5]; + int rc; + + if (mv64x60_i2c_open()) + fatal("Error: Can't open i2c device\n\r"); + + /* Get VPD from i2c eeprom-2 */ + memset(vpd, 0, sizeof(vpd)); + rc = mv64x60_i2c_read(EEPROM2_ADDR, vpd, 0x1fde, 2, sizeof(vpd)); + if (rc < 0) + fatal("Error: Couldn't read eeprom2\n\r"); + mv64x60_i2c_close(); + + /* Get board type & related info */ + bip = prpmc2800_get_board_info(vpd); + if (bip == NULL) { + printf("Error: Unsupported board or corrupted VPD:\n\r"); + printf(" 0x%x 0x%x 0x%x 0x%x 0x%x\n\r", + vpd[0], vpd[1], vpd[2], vpd[3], vpd[4]); + printf("Using device tree defaults...\n\r"); + } + + return bip; +} + +static void prpmc2800_bridge_setup(u32 mem_size) +{ + u32 i, v[12], enables, acc_bits; + u32 pci_base_hi, pci_base_lo, size, buf[2]; + unsigned long cpu_base; + int rc; + void *devp; + u8 *bridge_pbase, is_coherent; + struct mv64x60_cpu2pci_win *tbl; + + bridge_pbase = mv64x60_get_bridge_pbase(); + is_coherent = mv64x60_is_coherent(); + + if (is_coherent) + acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_WB + | MV64x60_PCI_ACC_CNTL_SWAP_NONE + | MV64x60_PCI_ACC_CNTL_MBURST_32_BYTES + | MV64x60_PCI_ACC_CNTL_RDSIZE_32_BYTES; + else + acc_bits = MV64x60_PCI_ACC_CNTL_SNOOP_NONE + | MV64x60_PCI_ACC_CNTL_SWAP_NONE + | MV64x60_PCI_ACC_CNTL_MBURST_128_BYTES + | MV64x60_PCI_ACC_CNTL_RDSIZE_256_BYTES; + + mv64x60_config_ctlr_windows(bridge_base, bridge_pbase, is_coherent); + mv64x60_config_pci_windows(bridge_base, bridge_pbase, 0, 0, mem_size, + acc_bits); + + /* Get the cpu -> pci i/o & mem mappings from the device tree */ + devp = finddevice("/mv64x60/pci@80000000"); + if (devp == NULL) + fatal("Error: Missing /mv64x60/pci@80000000" + " device tree node\n\r"); + + rc = getprop(devp, "ranges", v, sizeof(v)); + if (rc != sizeof(v)) + fatal("Error: Can't find /mv64x60/pci@80000000/ranges" + " property\n\r"); + + /* Get the cpu -> pci i/o & mem mappings from the device tree */ + devp = finddevice("/mv64x60"); + if (devp == NULL) + fatal("Error: Missing /mv64x60 device tree node\n\r"); + + enables = in_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE)); + enables |= 0x0007fe00; /* Disable all cpu->pci windows */ + out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); + + for (i=0; i<12; i+=6) { + switch (v[i] & 0xff000000) { + case 0x01000000: /* PCI I/O Space */ + tbl = mv64x60_cpu2pci_io; + break; + case 0x02000000: /* PCI MEM Space */ + tbl = mv64x60_cpu2pci_mem; + break; + default: + continue; + } + + pci_base_hi = v[i+1]; + pci_base_lo = v[i+2]; + cpu_base = v[i+3]; + size = v[i+5]; + + buf[0] = cpu_base; + buf[1] = size; + + if (!dt_xlate_addr(devp, buf, sizeof(buf), &cpu_base)) + fatal("Error: Can't translate PCI address 0x%x\n\r", + (u32)cpu_base); + + mv64x60_config_cpu2pci_window(bridge_base, 0, pci_base_hi, + pci_base_lo, cpu_base, size, tbl); + } + + enables &= ~0x00000600; /* Enable cpu->pci0 i/o, cpu->pci0 mem0 */ + out_le32((u32 *)(bridge_base + MV64x60_CPU_BAR_ENABLE), enables); +} + +static void prpmc2800_fixups(void) +{ + u32 v[2], l, mem_size; + int rc; + void *devp; + char model[BOARD_MODEL_MAX]; + struct prpmc2800_board_info *bip; + + bip = prpmc2800_get_bip(); /* Get board info based on VPD */ + + mem_size = (bip) ? bip->mem_size : mv64x60_get_mem_size(bridge_base); + prpmc2800_bridge_setup(mem_size); /* Do necessary bridge setup */ + + /* If the VPD doesn't match what we know about, just use the + * defaults already in the device tree. + */ + if (!bip) + return; + + /* Know the board type so override device tree defaults */ + /* Set /model appropriately */ + devp = finddevice("/"); + if (devp == NULL) + fatal("Error: Missing '/' device tree node\n\r"); + memset(model, 0, BOARD_MODEL_MAX); + strncpy(model, BOARD_MODEL, BOARD_MODEL_MAX - 2); + l = strlen(model); + if (bip->model == BOARD_MODEL_PRPMC280) + l--; + model[l++] = bip->variant; + model[l++] = '\0'; + setprop(devp, "model", model, l); + + /* Set /cpus/PowerPC,7447/clock-frequency */ + devp = finddevice("/cpus/PowerPC,7447"); + if (devp == NULL) + fatal("Error: Missing proper /cpus device tree node\n\r"); + v[0] = bip->core_speed; + setprop(devp, "clock-frequency", &v[0], sizeof(v[0])); + + /* Set /memory/reg size */ + devp = finddevice("/memory"); + if (devp == NULL) + fatal("Error: Missing /memory device tree node\n\r"); + v[0] = 0; + v[1] = bip->mem_size; + setprop(devp, "reg", v, sizeof(v)); + + /* Update /mv64x60/model, if this is a mv64362 */ + if (bip->bridge_type == BRIDGE_TYPE_MV64362) { + devp = finddevice("/mv64x60"); + if (devp == NULL) + fatal("Error: Missing /mv64x60 device tree node\n\r"); + setprop(devp, "model", "mv64362", strlen("mv64362") + 1); + } + + /* Set User FLASH size */ + devp = finddevice("/mv64x60/flash@a0000000"); + if (devp == NULL) + fatal("Error: Missing User FLASH device tree node\n\r"); + rc = getprop(devp, "reg", v, sizeof(v)); + if (rc != sizeof(v)) + fatal("Error: Can't find User FLASH reg property\n\r"); + v[1] = bip->user_flash; + setprop(devp, "reg", v, sizeof(v)); +} + +#define MV64x60_MPP_CNTL_0 0xf000 +#define MV64x60_MPP_CNTL_2 0xf008 +#define MV64x60_GPP_IO_CNTL 0xf100 +#define MV64x60_GPP_LEVEL_CNTL 0xf110 +#define MV64x60_GPP_VALUE_SET 0xf118 + +static void prpmc2800_reset(void) +{ + u32 temp; + + udelay(5000000); + + if (bridge_base != 0) { + temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0)); + temp &= 0xFFFF0FFF; + out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_0), temp); + + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL)); + temp |= 0x00000004; + out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp); + + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL)); + temp |= 0x00000004; + out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp); + + temp = in_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2)); + temp &= 0xFFFF0FFF; + out_le32((u32 *)(bridge_base + MV64x60_MPP_CNTL_2), temp); + + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL)); + temp |= 0x00080000; + out_le32((u32 *)(bridge_base + MV64x60_GPP_LEVEL_CNTL), temp); + + temp = in_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL)); + temp |= 0x00080000; + out_le32((u32 *)(bridge_base + MV64x60_GPP_IO_CNTL), temp); + + out_le32((u32 *)(bridge_base + MV64x60_GPP_VALUE_SET), + 0x00080004); + } + + for (;;); +} + +#define HEAP_SIZE (16*MB) +static struct gunzip_state gzstate; + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + struct elf_info ei; + char *heap_start, *dtb; + int dt_size = _dtb_end - _dtb_start; + void *vmlinuz_addr = _vmlinux_start; + unsigned long vmlinuz_size = _vmlinux_end - _vmlinux_start; + char elfheader[256]; + + if (dt_size <= 0) /* No fdt */ + exit(); + + /* + * Start heap after end of the kernel (after decompressed to + * address 0) or the end of the zImage, whichever is higher. + * That's so things allocated by simple_alloc won't overwrite + * any part of the zImage and the kernel won't overwrite the dtb + * when decompressed & relocated. + */ + gunzip_start(&gzstate, vmlinuz_addr, vmlinuz_size); + gunzip_exactly(&gzstate, elfheader, sizeof(elfheader)); + + if (!parse_elf32(elfheader, &ei)) + exit(); + + heap_start = (char *)(ei.memsize + ei.elfoffset); /* end of kernel*/ + heap_start = max(heap_start, (char *)_end); /* end of zImage */ + + if ((unsigned)simple_alloc_init(heap_start, HEAP_SIZE, 2*KB, 16) + > (128*MB)) + exit(); + + /* Relocate dtb to safe area past end of zImage & kernel */ + dtb = malloc(dt_size); + if (!dtb) + exit(); + memmove(dtb, _dtb_start, dt_size); + if (ft_init(dtb, dt_size, 16)) + exit(); + + bridge_base = mv64x60_get_bridge_base(); + + platform_ops.fixups = prpmc2800_fixups; + platform_ops.exit = prpmc2800_reset; + + if (serial_console_init() < 0) + exit(); +} + +/* _zimage_start called very early--need to turn off external interrupts */ +asm (" .globl _zimage_start\n\ + _zimage_start:\n\ + mfmsr 10\n\ + rlwinm 10,10,0,~(1<<15) /* Clear MSR_EE */\n\ + sync\n\ + mtmsr 10\n\ + isync\n\ + b _zimage_start_lib\n\ +"); diff --git a/arch/powerpc/boot/serial.c b/arch/powerpc/boot/serial.c index e8de4cf..7fd3233 100644 --- a/arch/powerpc/boot/serial.c +++ b/arch/powerpc/boot/serial.c @@ -125,6 +125,8 @@ int serial_console_init(void) if (!strcmp(compat, "ns16550")) rc = ns16550_console_init(devp, &serial_cd); + else if (!strcmp(compat, "marvell,mpsc")) + rc = mpsc_console_init(devp, &serial_cd); /* Add other serial console driver calls here */ |