diff options
Diffstat (limited to 'include/asm-x86')
| -rw-r--r-- | include/asm-x86/cpufeature_64.h | 2 | ||||
| -rw-r--r-- | include/asm-x86/io_apic_32.h | 16 | ||||
| -rw-r--r-- | include/asm-x86/processor-flags.h | 2 | ||||
| -rw-r--r-- | include/asm-x86/system_32.h | 19 | ||||
| -rw-r--r-- | include/asm-x86/system_64.h | 10 |
5 files changed, 23 insertions, 26 deletions
diff --git a/include/asm-x86/cpufeature_64.h b/include/asm-x86/cpufeature_64.h index 2983501..e18496b 100644 --- a/include/asm-x86/cpufeature_64.h +++ b/include/asm-x86/cpufeature_64.h @@ -7,7 +7,7 @@ #ifndef __ASM_X8664_CPUFEATURE_H #define __ASM_X8664_CPUFEATURE_H -#include <asm/cpufeature_32.h> +#include "cpufeature_32.h" #undef cpu_has_vme #define cpu_has_vme 0 diff --git a/include/asm-x86/io_apic_32.h b/include/asm-x86/io_apic_32.h index dbe734d..3f08788 100644 --- a/include/asm-x86/io_apic_32.h +++ b/include/asm-x86/io_apic_32.h @@ -11,8 +11,6 @@ * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar */ -#ifdef CONFIG_X86_IO_APIC - /* * The structure of the IO-APIC: */ @@ -55,12 +53,6 @@ union IO_APIC_reg_03 { } __attribute__ ((packed)) bits; }; -/* - * # of IO-APICs and # of IRQ routing registers - */ -extern int nr_ioapics; -extern int nr_ioapic_registers[MAX_IO_APICS]; - enum ioapic_irq_destination_types { dest_Fixed = 0, dest_LowestPrio = 1, @@ -100,6 +92,14 @@ struct IO_APIC_route_entry { } __attribute__ ((packed)); +#ifdef CONFIG_X86_IO_APIC + +/* + * # of IO-APICs and # of IRQ routing registers + */ +extern int nr_ioapics; +extern int nr_ioapic_registers[MAX_IO_APICS]; + /* * MP-BIOS irq configuration table structures: */ diff --git a/include/asm-x86/processor-flags.h b/include/asm-x86/processor-flags.h index 5404e90..199cab1 100644 --- a/include/asm-x86/processor-flags.h +++ b/include/asm-x86/processor-flags.h @@ -63,7 +63,7 @@ /* * x86-64 Task Priority Register, CR8 */ -#define X86_CR8_TPR 0x00000007 /* task priority register */ +#define X86_CR8_TPR 0x0000000F /* task priority register */ /* * AMD and Transmeta use MSRs for configuration; see <asm/msr-index.h> diff --git a/include/asm-x86/system_32.h b/include/asm-x86/system_32.h index d69ba93..e7e5d42 100644 --- a/include/asm-x86/system_32.h +++ b/include/asm-x86/system_32.h @@ -216,6 +216,7 @@ static inline unsigned long get_limit(unsigned long segment) #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2) #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2) +#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM) /** * read_barrier_depends - Flush all pending reads that subsequents reads @@ -271,18 +272,18 @@ static inline unsigned long get_limit(unsigned long segment) #define read_barrier_depends() do { } while(0) +#ifdef CONFIG_SMP +#define smp_mb() mb() +#ifdef CONFIG_X86_PPRO_FENCE +# define smp_rmb() rmb() +#else +# define smp_rmb() barrier() +#endif #ifdef CONFIG_X86_OOSTORE -/* Actually there are no OOO store capable CPUs for now that do SSE, - but make it already an possibility. */ -#define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM) +# define smp_wmb() wmb() #else -#define wmb() __asm__ __volatile__ ("": : :"memory") +# define smp_wmb() barrier() #endif - -#ifdef CONFIG_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() #define smp_read_barrier_depends() read_barrier_depends() #define set_mb(var, value) do { (void) xchg(&var, value); } while (0) #else diff --git a/include/asm-x86/system_64.h b/include/asm-x86/system_64.h index 02175aa..5022aec 100644 --- a/include/asm-x86/system_64.h +++ b/include/asm-x86/system_64.h @@ -141,8 +141,8 @@ static inline void write_cr8(unsigned long val) #ifdef CONFIG_SMP #define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() +#define smp_rmb() barrier() +#define smp_wmb() barrier() #define smp_read_barrier_depends() do {} while(0) #else #define smp_mb() barrier() @@ -159,12 +159,8 @@ static inline void write_cr8(unsigned long val) */ #define mb() asm volatile("mfence":::"memory") #define rmb() asm volatile("lfence":::"memory") - -#ifdef CONFIG_UNORDERED_IO #define wmb() asm volatile("sfence" ::: "memory") -#else -#define wmb() asm volatile("" ::: "memory") -#endif + #define read_barrier_depends() do {} while(0) #define set_mb(var, value) do { (void) xchg(&var, value); } while (0) |