aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* ARM: mxs/mx23evk: add mmc deviceShawn Guo2011-03-252-0/+45
| | | | | | | | Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Marc Kleine-Budde <mkl@pengutronix.de> [sha: updated to Uwes v4 version] Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mxs: dynamically allocate mmc deviceShawn Guo2011-03-258-0/+131
| | | | | | | Signed-off-by: Shawn Guo <shawn.guo@freescale.com> [ukleinek: fix naming to include complete device name in functions] Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mx51_efika: update platform data for new mfd changesAndres Salomon2011-03-251-2/+4
| | | | | | | | | | | | | | | Note that this relies on stuff currently in mfd's next tree, but this is also a newer driver. I'm not sure which tree it should go through, as it's a problem that shows up in next. From: Andres Salomon <dilinger@queued.net> MFD changes in c738892f cause the mc13xxx_platform_data struct to change. This changes one more (new) user of it, fixing a build error. Signed-off-by: Andres Salomon <dilinger@queued.net> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* mx2/iomux: Set direction for CSPI2 pinsJulien Boibessot2011-03-251-6/+6
| | | | | Signed-off-by: Julien Boibessot <julien.boibessot@armadeus.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mx51: Implement code to allow mx51 to enter WFIDinh Nguyen2011-03-234-2/+99
| | | | | | | | | | Implement code for MX51 that allows the SoC to enter WFI when arch_idle is called. This patch is also necessary for correctly suspending the system. Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mx51: Add entry for gpc_dvfs_clkDinh Nguyen2011-03-231-0/+8
| | | | | | | | For MX51 SRPG, we need to turn on the GPC clock in order to set the SRPG registers. Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mx50: Add support to get the silicon revisionDinh Nguyen2011-03-232-0/+43
| | | | | | | | | | | | For MX50, the HW_ADADIG_DIGPROG register in the ANATOP module will have the correct silicon revision: Major Minor Description 0x50 0x0 TO1.0 0x50 0x1 TO1.1 Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mxs: configure and register the second FEC device on TX28/STK5-V4Lothar Waßmann2011-03-232-6/+36
| | | | | Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mxc: fix buggy '.end' of IORESOURCE_MEM in device codesShawn Guo2011-03-232-2/+2
| | | | | | | Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM i.MX: remove duplicated #includeHuang Weiyi2011-03-231-1/+0
| | | | | | | | Remove duplicated #include('s) in arch/arm/mach-mx5/mx51_efika.c Signed-off-by: Huang Weiyi <weiyi.huang@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: imx: let MACH_IMX27_VISSTRIM_M10 select IMX_HAVE_PLATFORM_IMX_SSIUwe Kleine-König2011-03-231-0/+1
| | | | | | | | | | | | mach-imx27_visstrim_m10.c uses imx27_add_imx_ssi() so it needs to select IMX_HAVE_PLATFORM_IMX_SSI to fix: arch/arm/mach-imx/built-in.o: In function `visstrim_m10_board_init': mach-imx27_visstrim_m10.c:(.init.text+0x308): undefined reference to `imx_add_imx_ssi' mach-imx27_visstrim_m10.c:(.init.text+0x394): undefined reference to `imx27_imx_ssi_data' Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* MX51: Add AUDMUX ports definitionsJulien Boibessot2011-03-231-1/+9
| | | | | Signed-off-by: Julien Boibessot <julien.boibessot@armadeus.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mxc: Add sched_clock to mxc platformJan Weitzel2011-03-232-0/+17
| | | | | | | | | Add sched_clock using cyc_to_sched_clock and update_sched_clock with HAVE_SCHED_CLOCK tested on iMX27 and iMX35 Signed-off-by: Jan Weitzel <j.weitzel@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mxc: Add dummy_get_cycles to avoid access before init is doneJan Weitzel2011-03-231-1/+8
| | | | | | | | this is needed to use get_cycles with sched_clock. Accessing timer without enabled clk will result in crash Signed-off-by: Jan Weitzel <j.weitzel@phytec.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mx5/mx53_evk: Make the reset pin name more meaningfulFabio Estevam2011-03-231-3/+3
| | | | | | | | | | | As there is a mx53_smd board in the kernel, using SMD_FEC_PHY_RST as the pin name can be misleading when used on a MX53_EVK board. Change the pin name to reflect the board name. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mx5/mx53_evk: Use gpio_request_one in mx53_evk_fec_resetFabio Estevam2011-03-231-3/+2
| | | | | | | | | | | Current code inside mx53_evk_fec_reset uses gpio_direction_output with initial value of the GPIO and also sets the GPIO value via gpio_set_value right after. This is not needed. By using gpio_request_one it is possible to set the direction and initial value in one shot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mx5/babbage: Use gpio_request_one in babbage_fec_resetFabio Estevam2011-03-231-3/+2
| | | | | | | | | | | Current code inside babbage_fec_reset uses gpio_direction_output with initial value of the GPIO and also sets the GPIO value via gpio_set_value to the same level right after. This is not needed. By using gpio_request_one it is possible to set the direction and initial value in one shot. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mx53_loco: Add GPIO Keypad supportFrank Li2011-03-232-0/+26
| | | | | Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* ARM: mx51: Print silicon revision on bootFabio Estevam2011-03-234-0/+36
| | | | | | | | | | | | | | | Having the silicon revision to appear on the boot log is a useful information. MX31 and MX35 already show the silicon revision on boot. Add support for displaying such information for MX51 as well. Tested on a MX51EVK, where it shows: CPU identified as i.MX51, silicon rev 3.0 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* Merge branch 'next' of ↵Linus Torvalds2011-03-2216-1262/+1989
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (66 commits) avr32: at32ap700x: fix typo in DMA master configuration dmaengine/dmatest: Pass timeout via module params dma: let IMX_DMA depend on IMX_HAVE_DMA_V1 instead of an explicit list of SoCs fsldma: make halt behave nicely on all supported controllers fsldma: reduce locking during descriptor cleanup fsldma: support async_tx dependencies and automatic unmapping fsldma: fix controller lockups fsldma: minor codingstyle and consistency fixes fsldma: improve link descriptor debugging fsldma: use channel name in printk output fsldma: move related helper functions near each other dmatest: fix automatic buffer unmap type drivers, pch_dma: Fix warning when CONFIG_PM=n. dmaengine/dw_dmac fix: use readl & writel instead of __raw_readl & __raw_writel avr32: at32ap700x: Specify DMA Flow Controller, Src and Dst msize dw_dmac: Setting Default Burst length for transfers as 16. dw_dmac: Allow src/dst msize & flow controller to be configured at runtime dw_dmac: Changing type of src_master and dest_master to u8. dw_dmac: Pass Channel Priority from platform_data dw_dmac: Pass Channel Allocation Order from platform_data ...
| * avr32: at32ap700x: fix typo in DMA master configurationJamie Iles2011-03-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4aa5f366431fe (avr32: at32ap700x: specify DMA src and dst masters) specified the masters for the ac97c playback device but incorrectly set them in the capture slave information rather than playback. Cc: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com> Reported-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Jamie Iles <jamie@jamieiles.com> Acked-by: Vinod Koul <vinod.koul@intel.com> [rebased on dmaengine for 2.6.39 (d42efe6b)] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dmaengine/dmatest: Pass timeout via module paramsViresh Kumar2011-03-221-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | When we try to test all channels present on our controller together, some channels of lower priority may be very slow as compared to others. If number of transfers is unlimited, some channels may timeout and will not finish within 3 seconds. Thus, while doing such regress testing we may need to have higher value of timeouts. This patch adds support for passing timeout value via module parameters. Default value is 3 msec, a negative value means max timeout possible. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dma: let IMX_DMA depend on IMX_HAVE_DMA_V1 instead of an explicit list of SoCsUwe Kleine-König2011-03-221-1/+1
| | | | | | | | | | | | | | | | As a side effect this makes IMX_DMA selectable on i.MX21 again, because the symbol ARCH_MX21 doesn't exist (MACH_MX21 would have been more correct). Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: make halt behave nicely on all supported controllersIra Snyder2011-03-111-3/+16
| | | | | | | | | | | | | | | | | | | | The original dma_halt() function set the CA (channel abort) bit on both the 83xx and 85xx controllers. This is incorrect on the 83xx, where this bit means TEM (transfer error mask) instead. The 83xx doesn't support channel abort, so we only do this operation on 85xx. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: reduce locking during descriptor cleanupIra Snyder2011-03-111-62/+46
| | | | | | | | | | | | | | | | | | | | | | This merges the fsl_chan_ld_cleanup() function into the dma_do_tasklet() function to reduce locking overhead. In the best case, we will be able to keep the DMA controller busy while we are freeing used descriptors. In all cases, the spinlock is grabbed two times fewer than before on each transaction. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: support async_tx dependencies and automatic unmappingIra Snyder2011-03-111-36/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Previous to this patch, the dma_run_dependencies() function has been called while holding desc_lock. This function can call tx_submit() for other descriptors, which may try to re-grab the lock. Avoid this by moving the descriptors to be cleaned up to a temporary list, and dropping the lock before cleanup. At the same time, add support for automatic unmapping of src and dst buffers, as offered by the DMAEngine API. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: fix controller lockupsIra Snyder2011-03-112-122/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enabling poisoning in the dmapool API quickly showed that the DMA controller was fetching descriptors that should not have been in use. This has caused intermittent controller lockups during testing. I have been unable to figure out the exact set of conditions which cause this to happen. However, I believe it is related to the driver using the hardware registers to track whether the controller is busy or not. The code can incorrectly decide that the hardware is idle due to lag between register writes and the hardware actually becoming busy. To fix this, the driver has been reworked to explicitly track the state of the hardware, rather than try to guess what it is doing based on the register values. This has passed dmatest with 10 threads per channel, 100000 iterations per thread several times without error. Previously, this would fail within a few seconds. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: minor codingstyle and consistency fixesIra Snyder2011-03-112-18/+15
| | | | | | | | | | | | | | | | | | This fixes some minor violations of the coding style. It also changes the style of the device_prep_dma_*() function definitions so they are identical. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: improve link descriptor debuggingIra Snyder2011-03-111-6/+15
| | | | | | | | | | | | | | | | This adds better tracking to link descriptor allocations, callbacks, and frees. This makes it much easier to track errors with link descriptors. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: use channel name in printk outputIra Snyder2011-03-112-34/+36
| | | | | | | | | | | | | | | | | | This makes debugging the driver much easier when multiple channels are running concurrently. In addition, you can see how much descriptor memory each channel has allocated via the dmapool API in sysfs. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: move related helper functions near each otherIra Snyder2011-03-111-52/+64
| | | | | | | | | | | | | | | | This is a purely cosmetic cleanup. It is nice to have related functions right next to each other in the code. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dmatest: fix automatic buffer unmap typeIra Snyder2011-03-111-1/+6
| | | | | | | | | | | | | | | | | | The dmatest code relies on the DMAEngine API to automatically call dma_unmap_single() on src buffers. The flags it passes are incorrect, fix them. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * Merge branch 'for_dan' of git://git.infradead.org/users/vkoul/slave-dma into ↵Dan Williams2011-03-119-50/+881
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dmaengine * 'for_dan' of git://git.infradead.org/users/vkoul/slave-dma: drivers, pch_dma: Fix warning when CONFIG_PM=n. dmaengine/dw_dmac fix: use readl & writel instead of __raw_readl & __raw_writel avr32: at32ap700x: Specify DMA Flow Controller, Src and Dst msize dw_dmac: Setting Default Burst length for transfers as 16. dw_dmac: Allow src/dst msize & flow controller to be configured at runtime dw_dmac: Changing type of src_master and dest_master to u8. dw_dmac: Pass Channel Priority from platform_data dw_dmac: Pass Channel Allocation Order from platform_data dw_dmac: Mark all tx_descriptors with DMA_CRTL_ACK after xfer finish dw_dmac: Change value of DWC_MAX_COUNT to 4095. dw_dmac: Adding support for 64 bit access width for memcpy xfers dw_dmac: Calling dwc_scan_descriptors from dwc_tx_status() after taking lock dw_dmac: Move single descriptor from dwc->queue to dwc->active_list in dwc_complete_all dw_dmac: Replace module_init() with subsys_initcall() dw_dmac: Remove compilation dependency from AVR32 and put on HAVE_CLK dmaengine: mxs-dma: add dma support for i.MX23/28 pch_dma: set the number of array correctly pch_dma: fix kernel error issue
| | * drivers, pch_dma: Fix warning when CONFIG_PM=n.Rakib Mullick2011-03-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_PM=n, we get the following warning: drivers/dma/pch_dma.c:741: warning: ‘pch_dma_suspend’ defined but not used drivers/dma/pch_dma.c:755: warning: ‘pch_dma_resume’ defined but not used To fix it, wrap pch_dma_{suspend,resume} and pch_dma_{save,restore}_regs functions with CONFIG_PM. Signed-off-by: Rakib Mullick <rakib.mullick@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dmaengine/dw_dmac fix: use readl & writel instead of __raw_readl & __raw_writelViresh Kumar2011-03-071-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARMv7 cores, device memory mapped as Normal Non-cacheable, may not guarantee ordered access causing failures in device drivers that do not use the mandatory memory barriers. readl & writel versions contain necessary memory barriers for this. commit 79f64dbf68c8a9779a7e9a25e0a9f0217a25b57a: "ARM: 6273/1: Add barriers to the I/O accessors if ARM_DMA_MEM_BUFFERABLE" can be referred for more information on this. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * avr32: at32ap700x: Specify DMA Flow Controller, Src and Dst msizeViresh Kumar2011-03-071-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the dw_dmac DMA driver supports configurable Flow Controller, source and destination burst or msize, we need to specify which ones to use. Msize or burst size was previously hardcoded to 1, Flow controller was DMA for both M2P & P2M transfers. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dw_dmac: Setting Default Burst length for transfers as 16.Viresh Kumar2011-03-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch sets default Burst length for all transfer to 16. This will enhance performance when user doesn't have any chan->private data. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dw_dmac: Allow src/dst msize & flow controller to be configured at runtimeViresh KUMAR2011-03-073-6/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Msize or Burst Size is peripheral dependent in case of prep_slave_sg and cyclic_prep transfers, and in case of memcpy transfers it is platform dependent. So msize configuration must come from platform data. Also some peripherals (ex: JPEG), need to be flow controller for dma transfers, so this information in case of slave_sg & cyclic_prep transfers must come from platform data. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dw_dmac: Changing type of src_master and dest_master to u8.Viresh Kumar2011-03-071-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | src_master & dest_master don't required u32 as they have values limited to u8 only. Also their description is missing from doc style comment. This patch fixes above mentioned issues. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dw_dmac: Pass Channel Priority from platform_dataViresh Kumar2011-03-073-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Synopsys designware, channel priority is programmable. This patch adds support for passing channel priority through platform data. By default Ascending channel priority will be followed, i.e. channel 0 will get highest priority and channel 7 will get lowest. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dw_dmac: Pass Channel Allocation Order from platform_dataViresh Kumar2011-03-072-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In SPEAr Platform channels 4-7 have more Fifo depth. So we must get better channel first. This patch introduces concept of channel allocation order in dw_dmac. If user doesn't pass anything or 0, than normal (ascending) channel allocation will follow, else channels will be allocated in descending order. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dw_dmac: Mark all tx_descriptors with DMA_CRTL_ACK after xfer finishViresh Kumar2011-03-071-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dwc_desc_get checks all descriptors for DMA_CTRL_ACK before allocating them for transfers. And descriptors are not marked with DMA_CRTL_ACK after transfer finishes. Thus descriptor once used is not usable again. This patch marks descriptors with DMA_CRTL_ACK after dma xfer finishes Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dw_dmac: Change value of DWC_MAX_COUNT to 4095.Viresh Kumar2011-03-071-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | Every descriptor can transfer a maximum count of 4095 (12 bits, in control reg), So we must have DWC_MAX_COUNT as 4095 instead of 2048. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dw_dmac: Adding support for 64 bit access width for memcpy xfersViresh Kumar2011-03-071-1/+3
| | | | | | | | | | | | | | | Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dw_dmac: Calling dwc_scan_descriptors from dwc_tx_status() after taking lockViresh Kumar2011-03-071-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lock must be taken before calling dwc_scan_descriptors, as this may access/modify shared data and queues. dwc_tx_status wasn't taking lock before calling this routine. This patch add code that takes lock before calling dwc_scan_descriptors. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dw_dmac: Move single descriptor from dwc->queue to dwc->active_list in ↵Viresh Kumar2011-03-071-12/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dwc_complete_all dwc_complete_all and other routines was removing all descriptors from dwc->queue and pushing them to dwc->active_list. Only one was required to be removed. Also we are calling dwc_dostart, once list is fixed. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dw_dmac: Replace module_init() with subsys_initcall()Viresh Kumar2011-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases users of dw_dmac are initialized before dw_dmac, and if they try to use dw_dmac, they simply fail. So its better we register init() routine of driver using subsys_initcall() instead of module_init(), so that dma driver is available at the earliest possible. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dw_dmac: Remove compilation dependency from AVR32 and put on HAVE_CLKViresh Kumar2011-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver will now be used in atleast two platforms AVR32 & ARM. And there is no actual hardware dependency of this driver over AVR32 or ARM. So this dependency can be removed altogether. Also dw_dmac driver uses clk framework and must have compilation dependency on HAVE_CLK Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * dmaengine: mxs-dma: add dma support for i.MX23/28Shawn Guo2011-03-024-0/+759
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds dma support for Freescale MXS-based SoC i.MX23/28, including apbh-dma and apbx-dma. * apbh-dma and apbx-dma are supported in the driver as two mxs-dma instances. * apbh-dma is different between mx23 and mx28, hardware version register is used to differentiate. * mxs-dma supports pio function besides data transfer. The driver uses dma_data_direction DMA_NONE to identify the pio mode, and steals sgl and sg_len to get pio words and numbers from clients. * mxs dmaengine has some very specific features, like sense function and the special NAND support (nand_lock, nand_wait4ready). These are too specific to implemented in generic dmaengine driver. * The driver refers to imx-sdma and only a single descriptor is statically assigned to each channel. Signed-off-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * pch_dma: set the number of array correctlyTomoya MORINAGA2011-02-261-2/+2
| | | | | | | | | | | | | | | | | | | | | set the number of array correctly. Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
generated by cgit v1.1 at 2024-12-28 10:39:39 +0000