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* Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into ↵Russell King2010-10-2827-50/+492
|\ | | | | | | devel-stable
| * ARM: imx: Add wake functionality to GPIODinh Nguyen2010-10-261-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | Add function definition for irq_chip.set_wake to enable GPIO to wake-up the system. This patch has been tested on a MX51 Babbage system that had suspend code implemented. The set_wake implementation is necessary for a GPIO to wake up a system from suspend. Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: mx5: Add gpio-keys to mx51 babbage boardDinh Nguyen2010-10-263-0/+27
| | | | | | | | | | | | | | Add functionality for the power button on MX51 Babbage board. Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: imx: Add gpio-keys to plat-mxcDinh Nguyen2010-10-265-0/+38
| | | | | | | | | | | | | | Add imx_add_gpio_keys function to add gpio-keys in plat-mxc Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mx31_3ds: Fix spi registrationRogerio Pimentel2010-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | Commit (06606ff13) "ARM: imx: dynamically register spi_imx devices (imx31)" registered the wrong SPI port for mx31_3ds board. mx31_3ds uses SPI2 to connect to the MC13783 PMIC. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Rogerio Pimentel <rogerio.pimentel@freescale.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mx31_3ds: Fix the logic for detecting the debug boardRogerio Pimentel2010-10-261-3/+3
| | | | | | | | | | | | | | | | | | | | The function mxc_expio_init returns 0 on success, so fix the logic for printing the error case. Also fixed the wording on the error message. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Rogerio Pimentel <rogerio.pimentel@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mx31_3ds: Remove unused debug board definitionsRogerio Pimentel2010-10-261-30/+0
| | | | | | | | | | | | | | | | | | | | | | In commit (c5d38f08): "mx31_3ds: revert 3ds debug board relate code" the debug board definitions are placed in a separate file. Remove the remaining debug board related define from mach-mx31_3ds.c. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Rogerio Pimentel <rogerio.pimentel@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * MX27 3ds: Add SDHC1 support to mx27 3dsRogerio Pimentel2010-10-221-0/+38
| | | | | | | | | | | | | | Add SDHC1 support to MX27 3ds Signed-off-by: Rogerio Pimentel <rpimentel.silva@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * imx: only select HAVE_CAN_FLEXCAN if CAN is enabledUwe Kleine-König2010-10-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes a warning warning: (IMX_HAVE_PLATFORM_FLEXCAN && ARCH_MXC) selects HAVE_CAN_FLEXCAN which has unmet direct dependencies (NET && CAN) (The warning in general exists since 246cf9c (kbuild: Warn on selecting symbols with unmet direct dependencies) which was reverted between 71ebc01 and b1f7d6e.) Reported-and-introduced-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mx35pdk: add debug board supportXiao Jiang2010-10-222-0/+9
| | | | | | | | | | | | | | | | Enable debug board support for mx35pdk. Signed-off-by: Xiao Jiang <jgq516@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * cpufreq for freescale mx51Yong Shen2010-10-2210-4/+295
| | | | | | | | | | | | | | | | Currently, only two operating points: 160Mhz and 800Mhz. the operating points are tested on babbage 3.0 Signed-off-by: Yong Shen <yong.shen@linaro.org> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mx25_3ds: add mmc supportShawn Guo2010-10-212-0/+11
| | | | | | | | | | | | | | | | Update mx25_3ds board support to register esdhc device Signed-off-by: Shawn Guo <shawn.gsc@gmail.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * mx35_3ds: add mmc supportShawn Guo2010-10-212-0/+9
| | | | | | | | | | | | | | | | Update mx35_3ds board support to register esdhc device Signed-off-by: Shawn Guo <shawn.gsc@gmail.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * babbage: esdhc device registrationShawn Guo2010-10-212-0/+20
| | | | | | | | | | | | | | Update babbage board support to register esdhc device Signed-off-by: Shawn Guo <shawn.gsc@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * ARM: mx3: fix build failure concerning MXC_INT_MMC_SDHC2Uwe Kleine-König2010-10-213-11/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit c074512 (imx-esdhc: update devices registration) renamed MX35_INT_MMC_SDHC2 to MX35_INT_ESDHC2 which broke expansion of the MXC_INT_MMC_SDHC2 macro. As (the only user of MXC_INT_MMC_SDHC2) is only used on mx31 use the MX31 prefixed symbol to define its resources. Moreover to reduce further confusion mxcsdhc_device0 is fixed accordingly and the MXC prefixed symbols are removed. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | fix braino in fs: do not assign default i_ino in new_inodeAl Viro2010-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | usbfs_get_inode() is something completely different... Bogosity introduced by commit 85fe4025c616 ("fs: do not assign default i_ino in new_inode"). Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Cc: Christoph Hellwig <hch@lst.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | Merge branch 'drm-core-next' of ↵Linus Torvalds2010-10-26212-11671/+18747
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6 * 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (476 commits) vmwgfx: Implement a proper GMR eviction mechanism drm/radeon/kms: fix r6xx/7xx 1D tiling CS checker v2 drm/radeon/kms: properly compute group_size on 6xx/7xx drm/radeon/kms: fix 2D tile height alignment in the r600 CS checker drm/radeon/kms/evergreen: set the clear state to the blit state drm/radeon/kms: don't poll dac load detect. gpu: Add Intel GMA500(Poulsbo) Stub Driver drm/radeon/kms: MC vram map needs to be >= pci aperture size drm/radeon/kms: implement display watermark support for evergreen drm/radeon/kms/evergreen: add some additional safe regs v2 drm/radeon/r600: fix tiling issues in CS checker. drm/i915: Move gpu_write_list to per-ring drm/i915: Invalidate the to-ring, flush the old-ring when updating domains drm/i915/ringbuffer: Write the value passed in to the tail register agp/intel: Restore valid PTE bit for Sandybridge after bdd3072 drm/i915: Fix flushing regression from 9af90d19f drm/i915/sdvo: Remove unused encoding member i915: enable AVI infoframe for intel_hdmi.c [v4] drm/i915: Fix current fb blocking for page flip drm/i915: IS_IRONLAKE is synonymous with gen == 5 ... Fix up conflicts in - drivers/gpu/drm/i915/{i915_gem.c, i915/intel_overlay.c}: due to the new simplified stack-based kmap_atomic() interface - drivers/gpu/drm/vmwgfx/vmwgfx_drv.c: added .llseek entry due to BKL removal cleanups.
| * | vmwgfx: Implement a proper GMR eviction mechanismThomas Hellstrom2010-10-279-160/+252
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use Ben's new range manager hooks to implement a manager for GMRs that manages ids rather than ranges. This means we can use the standard TTM code for binding, unbinding and eviction. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | drm/radeon/kms: fix r6xx/7xx 1D tiling CS checker v2Alex Deucher2010-10-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | broken by: drm/radeon/r600: fix tiling issues in CS checker. v2: only apply it to 1D tiling case. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | drm/radeon/kms: properly compute group_size on 6xx/7xxAlex Deucher2010-10-262-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | Needed for tiled surfaces. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | drm/radeon/kms: fix 2D tile height alignment in the r600 CS checkerAlex Deucher2010-10-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | macro tile heights are aligned to num channels, not num banks. Noticed by Dave Airlie. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | drm/radeon/kms/evergreen: set the clear state to the blit stateAlex Deucher2010-10-264-54/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hw stores a default clear state for registers in the context range that can be initialized when the CP is set up. Set the blit state as the default clear state and use the CLEAR_STATE packet to load the blit state rather than loading it from an IB. This reduces overhead when doing bo moves using the 3D engine. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | drm/radeon/kms: don't poll dac load detect.Dave Airlie2010-10-261-0/+10
| | | | | | | | | | | | | | | | | | This is slightly destructive, cpu intensive and can cause lockups. Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | gpu: Add Intel GMA500(Poulsbo) Stub DriverLee, Chun-Yi2010-10-265-1/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, there have no GMA500(Poulsbo) native video driver to support intel opregion. So, use this stub driver to enable the acpi backlight control sysfs entry files by requrest acpi_video_register. [airlied: fix warnings] Signed-off-by: Lee, Chun-Yi <jlee@novell.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | drm/radeon/kms: MC vram map needs to be >= pci aperture sizeAlex Deucher2010-10-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vram map in the radeon memory controller needs to be >= the pci aperture size. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=28402 The problematic cards in the above bug have 64 MB of vram, but the pci aperture is 128 MB and the MC vram map was only 64 MB. This can lead to hangs. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | drm/radeon/kms: implement display watermark support for evergreenAlex Deucher2010-10-262-1/+449
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improper display watermarks can result in underflow to the display controllers which can cause flickering or other artifacts. This patch implements display watermark support and line buffer allocation for evergreen asics. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | drm/radeon/kms/evergreen: add some additional safe regs v2Alex Deucher2010-10-262-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These are needed for enabling dynamic GPR allocation in the shaders in the userspace acceleration drivers. v2: fix typo in reg name Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | drm/radeon/r600: fix tiling issues in CS checker.Dave Airlie2010-10-262-10/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CS checker had some incorrect alignment requirements for 2D surfaces, this made rendering to mipmap levels that were 2D broken. Also the CB height was being worked out from the BO size, this doesn't work at all when rendering mipmap levels, instead we work out what height userspace wanted from slice max and use that to check it fits inside the BO, however the DDX send the wrong slice max for an unaligned buffer so we have to workaround for that even though its a userspace bug. Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
| * | Merge remote branch 'intel/drm-intel-next' of ../drm-next into drm-core-nextDave Airlie2010-10-2629-1366/+1979
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'intel/drm-intel-next' of ../drm-next: (63 commits) drm/i915: Move gpu_write_list to per-ring drm/i915: Invalidate the to-ring, flush the old-ring when updating domains drm/i915/ringbuffer: Write the value passed in to the tail register agp/intel: Restore valid PTE bit for Sandybridge after bdd3072 drm/i915: Fix flushing regression from 9af90d19f drm/i915/sdvo: Remove unused encoding member i915: enable AVI infoframe for intel_hdmi.c [v4] drm/i915: Fix current fb blocking for page flip drm/i915: IS_IRONLAKE is synonymous with gen == 5 drm/i915: Enable SandyBridge blitter ring drm/i915/ringbuffer: Remove broken intel_fill_struct() drm/i915/ringbuffer: Fix emit batch buffer regression from 8187a2b drm/i915: Copy the updated reloc->presumed_offset back to the user drm/i915: Track objects in global active list (as well as per-ring) drm/i915: Simplify most HAS_BSD() checks drm/i915: cache the last object lookup during pin_and_relocate() drm/i915: Do interrupible mutex lock first to avoid locking for unreference drivers: gpu: drm: i915: Fix a typo. agp/intel: Also add B43.1 to list of supported devices drm/i915: rearrange mutex acquisition for pread ...
| | * | drm/i915: Move gpu_write_list to per-ringChris Wilson2010-10-244-26/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... to prevent flush processing of an idle (or even absent) ring. This fixes a regression during suspend from 87acb0a5. Reported-and-tested-by: Alexey Fisher <bug-track@fisher-privat.net> Tested-by: Peter Clifton <pcjc2@cam.ac.uk> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: Invalidate the to-ring, flush the old-ring when updating domainsChris Wilson2010-10-231-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the object has been written to by the gpu it remains on the ring until its flush has been retired. However, when the object is moving to the ring and the associated cache needs to be invalidated, we need to perform the flush on the target ring, not the one it came from (which is NULL in the reported case and so the flush was entirely absent). Reported-by: Peter Clifton <pcjc2@cam.ac.uk> Reported-and-tested-by: Alexey Fisher <bug-track@fisher-privat.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/ringbuffer: Write the value passed in to the tail registerChris Wilson2010-10-222-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This should fix the error along the reset path were we tried to clear the tail register by setting it to 0, but were in fact setting it to the current value and complaining when it did not reset to 0. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | agp/intel: Restore valid PTE bit for Sandybridge after bdd3072Chris Wilson2010-10-221-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In cleaning up the mask functions in bdd3072, the setting of the PTE valid bit was dropped for Sandybridge. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: Fix flushing regression from 9af90d19fChris Wilson2010-10-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Whilst moving the code around in 9af90d19f, I dropped the or'ing in of new write domains which would zero out the write domain for a render target if later reused as a source later in the batch. This meant that we might drop a required flush before reading from the render target. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31043 Reported-by: xunx.fang@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/sdvo: Remove unused encoding memberChris Wilson2010-10-221-23/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This block is only used when detecting whether the connector is HDMI and never again, so scope the variable to the detection routine. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | i915: enable AVI infoframe for intel_hdmi.c [v4]David Härdeman2010-10-224-105/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the sending of AVI infoframes in drivers/gpu/drm/i915/intel_hdmi.c. My receiver currently loses sync when the HDMI output on my computer (DG45FC motherboard) is switched from 800x600 (the BIOS resolution) to 1920x1080 as part of the boot. Fixable by switching inputs on the receiver a couple of times. With this patch, my receiver has not lost sync yet (> 40 tries). Fourth version, now based on drm-intel-next from: git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel.git Two questions still remain: I'm assuming that the sdvo hardware also stores a header ECC byte in the MSB of the first dword - is this correct? Does the SDVOB and SDVOC handling in intel_hdmi_set_avi_infoframe() look correct? Signed-off-by: David Härdeman <david@hardeman.nu> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: Fix current fb blocking for page flipChia-I Wu2010-10-211-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Block execbuffer for the fb to be flipped away, not the one that is to be flipped in. [ickle: rewritten for -next] Signed-off-by: Chia-I Wu <olvaffe@gmail.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Acked-by: Kristian Høgsberg <krh@bitplanet.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: IS_IRONLAKE is synonymous with gen == 5Chris Wilson2010-10-218-22/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | So remove the redundant bit in the capabilities block and s/IS_IRONLAKE/IS_GEN5/. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: Enable SandyBridge blitter ringChris Wilson2010-10-2111-63/+175
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on an original patch by Zhenyu Wang, this initializes the BLT ring for SandyBridge and enables support for user execbuffers. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/ringbuffer: Remove broken intel_fill_struct()Chris Wilson2010-10-212-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... before someone tries to use it. The code both calls intel_ring_begin/advance() and open-codes the bookkeeping performed by those two functions. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/ringbuffer: Fix emit batch buffer regression from 8187a2bChris Wilson2010-10-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit 8187a2b, the number of dwords used in the ringbuffer for executing the batch buffer was erroneously changed from 2 to 4. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: Copy the updated reloc->presumed_offset back to the userChris Wilson2010-10-201-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the userspace driver is using a constant relocation array with a static buffer, they will pass the same relocation array back to the kernel. So we *do* need to update the presumed offset value in those relocations to reflect the current object so that they remain correct with future batchbuffers and we avoid the necessity of having to suspend execution and perform redundant relocations. Fixes the regression introduced by 12f889c for applications using absolute addressing on trees of buffer (i.e. the current consumers of libdrm_intel.so). Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30996 Reported-by: Wang, Jinjin <jinjin.wang@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: Track objects in global active list (as well as per-ring)Chris Wilson2010-10-205-96/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To handle retirements, we need per-ring tracking of active objects. To handle evictions, we need global tracking of active objects. As we enable more rings, rebuilding the global list from the individual per-ring lists quickly grows tiresome and overly complicated. Tracking the active objects in two lists is the lesser of two evils. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: Simplify most HAS_BSD() checksChris Wilson2010-10-203-37/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ... by always initialising the empty ringbuffer it is always then safe to check whether it is active. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: cache the last object lookup during pin_and_relocate()Chris Wilson2010-10-201-171/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The most frequent relocation within a batchbuffer is a contiguous sequence of vertex buffer relocations, for which we can virtually eliminate the drm_gem_object_lookup() overhead by caching the last handle to object translation. In doing so we refactor the pin and relocate retry loop out of do_execbuffer into its own helper function and so improve the error paths. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: Do interrupible mutex lock first to avoid locking for unreferenceChris Wilson2010-10-191-113/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One of the primarily consumers of the i915 driver is X, a large signal driven application. Frequently when writing into the buffers, there is a pending signal which causes us not to take the interruptible lock but then we need to take that same lock around the object unreference. By rearranging the code to do the interruptible lock as the first check, we can avoid the frequent additional locking around the unreference. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drivers: gpu: drm: i915: Fix a typo.Andrea Gelmini2010-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | "userpace" -> "userspace" Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | agp/intel: Also add B43.1 to list of supported devicesChris Wilson2010-10-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was a missing piece from 41a5142 that dropped recognition of the AGP module for the second B43 variant. Reported-by: Stefan Bader <stefan.bader@canonical.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
| | * | drm/i915: rearrange mutex acquisition for preadChris Wilson2010-10-191-56/+43
| | | | | | | | | | | | | | | | | | | | | | | | ... to avoid the double acquisition along fast[er] paths. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: Rearrange acquisition of mutex during pwriteChris Wilson2010-10-191-105/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... to avoid reacquiring it to drop the object reference count on exit. Note we have to make sure we now drop (and reacquire) the lock around acquiring the mm semaphore on the slow paths. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
generated by cgit v1.1 at 2025-02-07 23:35:43 +0000