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* Merge branch 'linux-omap-pm-3.0' into linux-omap-3.0Colin Cross2011-06-14113-2223/+10074
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| * omap4: control: Add apis to access wkup pad registers.sricharan2011-06-145-1/+63
| | | | | | | | | | | | | | | | | | | | | | The current omap4_ctrl_pad_writel/readl can be used to access only the core pad registers. In omap4 wakeup pad is seperate from the core group. So adding apis to access the wakeup pad registers. Also added apis for 8/16 bit access to the core pad registers. Signed-off-by: sricharan <r.sricharan@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| * Merge branch 'omap-pm-integration' of ↵Colin Cross2011-06-13141-2444/+10287
| |\ | | | | | | | | | git://github.com/nmenon/linux-omap-ti-pm into linux-omap-pm-3.0
| | * OMAP2+: defconfig: update for debugNishanth Menon2011-06-131-3/+34
| | | | | | | | | | | | | | | | | | | | | Update params for debugging Power management with lock, cpufreq,cpuidle and smartreflex enabled. Signed-off-by: Nishanth Menon <nm@ti.com>
| | *-. Merge branches 'omap-pm/devel/hotplug', 'omap-pm/devel/dvfs' and ↵Nishanth Menon2011-06-1392-1628/+8033
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'omap-pm/devel/cpuidle' into omap-pm-integration Conflicts: arch/arm/mach-omap2/Kconfig arch/arm/mach-omap2/powerdomains3xxx_data.c
| | | | * OMAP4: CPUidle: Change comment of C1 to CPU0 WFINishanth Menon2011-06-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To align with the technical jargon already prevelant, name the C1 state to state CPU0 WFI. Acked-by: Axel Haslam <axelhaslam@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
| | | | * OMAP4: CPUidle: Set MPU, CPU0 and core to INACTIVE for C2Axel Haslam2011-06-131-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently C1 and C2 states are the same. Define C2 state as INACTIVE for CPU0, MPU and core which will cut internal ARM clocks and save more power. Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Axel Haslam <axelhaslam@ti.com>
| | | | * I2C: OMAP: trigger pending runtime PM from system PMKevin Hilman2011-06-131-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Tested-by: Todd Poynor <toddpoynor@google.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| | | | * OMAP4: PM44: Handle 4460 clk name delta for mpuNishanth Menon2011-06-131-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DPLL for MPU should now be virt_dpll_mpu_ck instead of dpll_mpu_ck for OMAP4460. Fix this for idle changes Reported-by: Colin Cross <ccross@google.com> Signed-off-by: Nishanth Menon <nm@ti.com>
| | | | * OMAP4: CPUIDLE: correct cpuidle target_residencyAxel Haslam2011-06-131-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | exit_latency was defined twice in the table, second parameter is target_residency and not exit_latency. Acked-by: Ambresh K <ambresh@ti.com> Signed-off-by: Axel Haslam <axelhaslam@ti.com>
| | | | * OMAP4: PM: mpu_init: dont do sleepable dma_alloc_coherentAmbresh K2011-06-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | omap4_mpuss_init() calls dma_alloc_coherent() with GFP_KERNEL flags, need GFP_ATOMIC if called with interrupts off. Signed-off-by: Ambresh K <ambresh@ti.com>
| | | | * OMAP4: PM: clockdomain: workaround for l4_secure_clkdm HWSUPSantosh Shilimkar2011-06-131-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On HS/EMU devices the modules from l4_secure_clkdm are used. Few modules from L4_SEC clockdomain are not accessible without putting l4_secure_clkdm in force software wakeup. Follow the recommended sequence across secure API calls. Acked-by: Axel Haslam <axelhaslam@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | | * OMAP4: PM: Fix remaining static depdenciesSantosh Shilimkar2011-06-131-15/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 9399b0bf7f729e (OMAP4: PM: Set static dependency ...) misses MPUSS -> L3_2 and DUCATI -> L3* static dependencies to be set. Fix the same according to latest data. Acked-by: Axel Haslam <axelhaslam@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | | * OMAP4: serial: Avoid accidental overwrite of padsRajendra Nayak2011-06-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use 16bit read/write for programming pads for io wakeup. Using 32bit read/write's can overwrite other pad settings. Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
| | | | * OMAP4: control: Add omap4_ctrl_read/write apis for byte and word valuesRajendra Nayak2011-06-132-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add omap4_ctrl_read/write apis for byte and word values Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Rajendra NayaK <rnayak@ti.com>
| | | | * OMAP4: PM: give dummy omap4_enter_sleepVikram Pandita2011-06-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define a dummy omap4_enter_sleep if CONFIG_SUSPEND is not defined This fixes the linker break: LD .tmp_vmlinux1 arch/arm/mach-omap2/built-in.o: In function `omap4_enter_idle': /git/android39/arch/arm/mach-omap2/cpuidle44xx.c:158: undefined reference to `omap4_enter_sleep' make: *** [.tmp_vmlinux1] Error 1 Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
| | | | * OMAP: PM: NOOP: change prototype of omap_pm_get_dev_context_loss_countNishanth Menon2011-06-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | with CONFIG_OMAP_PM_NOOP=y build breaks with: arch/arm/plat-omap/omap-pm-noop.c:313: error: conflicting types for 'omap_pm_get_dev_context_loss_count' arch/arm/plat-omap/include/plat/omap-pm.h:361: note: previous declaration of 'omap_pm_get_dev_context_loss_count' was here Reported-by: Vikram Pandita <vikram.pandita@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
| | | | * OMAP4460: L2X0: Temporary work-around for stability.Santosh Shilimkar2011-06-132-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP4460 ES1.0 seems to suffer from stability with L2 cache enabled. The root-cause analysis is ongoing but in meantime this chabe is to enable a software WA with L2 cache enabled build. The WA consist of locking certain cache ways based on their positions on the physical memory layout. Downside of this WA is that effective L2 cache size will be 512 KB instead of 1 MB. Of course this is temporary WA and needs to removed once the root cause and the right fix is found. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | | * OMAP4: L2X0: Update PL310 register bits for OMAP4460Santosh Shilimkar2011-06-131-12/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP4460, L2 double line fill feature is available. Enable the same along with optimal POR offset. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | | * ARM: L2X0: Add the Prefetch Control Register bits to header.Santosh Shilimkar2011-06-131-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While at this, fix some indentation issues in cache-l2x0.h Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | | * OMAP4:PM: Adapt and fix compilation with constraint frmwkAxel Haslam2011-06-135-14/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes compilation issues seen when porting omap-pm constraint frmwk from 2.6.35. Also, new qos frmwk expects memory to be allocated by the caller. Signed-off-by: Axel Haslam <axelhaslam@ti.com>
| | | | * OMAP3: fix race condition of pm_qos_remove_requestkeun-o.park2011-06-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sometimes pm_qos_remove_request is called twice continuously, so list_del(&pm_qos_req->list) causes oops message. Signed-off-by: keun-o.park <sahara@ti.com>
| | | | * OMAP-PM: add API to set min mpu freq.Axel Haslam2011-06-132-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add the api omap_pm_set_min_mpu_freq which will restrict the mpu freq to a particular rate. Signed-off-by: Axel Haslam <axelhaslam@ti.com>
| | | | * omap4: oswr: fake context loss countVikram Pandita2011-06-131-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow omap_pm_get_dev_context_loss_count() to return a counter value so that driver logic can be written correctly for OSWR context restore The API needs to be enhanced to take care of the actual pm domain state, but till that is done, this can be a good substitute. Change-Id: Iec2592fbae689d6695558c69b85ce04ae183fe14 Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
| | | | * OMAP: PM: Fix bug while settting constraints.Avinash.H.M2011-06-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dummy-l3 device was created locally. So its address used to differ in both request and release context. The address was different even if same device used to request the throughput-set API. Now the dummy-l3 device is created static, so that it gets initialized only once and has a constant address. With this the clocks are released properly. Signed-off-by: Avinash.H.M.<avinashhm@ti.com>
| | | | * omap-pm: fix warning in omap_pm_set_min_bus_tput()Miguel Vadillo2011-06-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | target_level was being printed uninitialized in case of an error. moving the unlock label after printing target_level fix the warning and issue. Change-Id: Ie9ba4a03aae472aecf9d2f182854635e6a2a9959 Signed-off-by: Miguel Vadillo <vadillo@ti.com>
| | | | * OMAP PM: Fix for issue in throughput constraintVishwanath BS2011-06-131-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the function 'omap_pm_set_min_bus_tput' mutex is locked to protect code from race condition but in two if cases the function is returned without unlocking which can cause crash. This Patch fixes the Issue. Signed-off-by: Shweta Gulati <shweta.gulati@ti.com> Signed-off-by: Vishwanath Sripathy <vishwanath.bs@ti.com>
| | | | * OMAP4 PM: Interconnect Constraint FrameworkSripathy Vishwanath2011-06-133-23/+234
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This Patch adds support for interconnect constraint management, API 'omap_pm_set_min_bus_tput' which is called by device drivers to place or remove constraints on interconnects (L3/L4/DMM) throughput level. The resultant throughput is calculated by consolidating all the requests placed by different users and if same user places multiple requests then previous request is substituted by new requested level. To remove a constraint driver should call the API with argument, 'rate' (throughput level) as '-1'. This Patch is tested on OMAP 4430 SDP board. Signed-off-by: Sripathy Vishwanath <vishwanath.bs@ti.com> Signed-off-by: Shweta Gulati <shweta.gulati@ti.com>
| | | | * OMAP PM: Device wakeup latency constraint frameworkVibhore Vardhan2011-06-135-8/+383
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements device wakeup latency constraint framework. Using omap_pm_set_max_dev_wakeup_lat(), drivers can specify the maximum amount of time for a device to become accessible after its clocks are enabled. This is done by restricting the power states that the parent powerdomain of a device can be put into. Only power states with profiled wakeup latency value less than the requested constraint get selected while the constraint is active. Ported from 2.6.35 by Axel Haslam <axelhaslam@ti.com> Signed-off-by: Vibhore Vardhan <vvardhan@ti.com> Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
| | | | * OMAP PM: Fix for compilation issue in OMAP PM layerVishwanath BS2011-06-132-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As signature of some of the OMAP PM layer APIs are changed, this was breaking OMAP PM Layer. This patch has fix for the same. Also OMAP PM layer is enabled by default. Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
| | | | * OMAP PM: MPU/DMA Latency constraintsVishwanath BS2011-06-135-16/+335
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has implementation for OMAP MPU/DMA Latency constraints using PM QOS. Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com>
| | | | * ARM: smp: Skip non-boot CPU's calibration in hotplug pathSantosh Shilimkar2011-06-131-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current calibrate the lpj every time CPU hotplug path. This delays CPU online process. We can use msater CPU lpj and assign it to the onlined non-boot CPUs Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | | * OMAP4: PM: Make MPU and CORE next states as ON unless trying to sleepRajendra Nayak2011-06-132-13/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Leaving the next power states of MPU and CORE to sleep states have seen issues when secure software trying a wfi and accidentally hitting sleep states. Always keep MPU and CORE states programmed to ON unless attempting a sleep. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Reported-by: Patrick Titiano <p-titiano@ti.com> Rebased-by: Axel Haslam <axelhaslam@ti.com>
| | | | * OMAP4: PM: Set next power state as RET on suspendAxel Haslam2011-06-131-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On suspend, program next power state to retention domain except for cpu's that get set on further down the path. Signed-off-by: Axel Haslam <axelhaslam@ti.com>
| | | | * OMAP4:CPUIDLE: populate new cpuidle_params structureAxel Haslam2011-06-131-34/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To fix a compilation break, use the new cpu idle structure. The new structure was intrduced by: OMAP3: clean-up mach specific cpuidle data structures Signed-off-by: Axel Haslam <axelhaslam@ti.com>
| | | | * omap4: pm: De-assert PWRREQ signal in Device OFF stateSantosh Shilimkar2011-06-131-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PWRREQ is de-asserted if all voltage domain are in OFF state. Conversely, PWRREQ is asserted upon any voltage domain entering or staying in ON or SLEEP or RET state. This signal can be used to request the PMIC to shut down internal resources. Change-Id: I666ba98899229cba59c980506ae4e91d599eb038 Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Ported-by: Axel Haslam <axelhaslam@ti.com>
| | | | * OMAP4: PM: De-assert CLK-REQ in Device RET and OFF statesRajendra Nayak2011-06-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | De-assert CLK-REQ in Device RET and OFF states Change-Id: I5d0f772fda469da11d1cc4cde389a60142a945b0 Signed-off-by: Rajendra Nayak <rnayak@ti.com> Validated-by: Girish S G <girishsg@ti.com> Ported-by: Axel Haslam <axelhaslam@ti.com>
| | | | * OMAP4: PM: Errata i608: Disable unsupported RTA featureSantosh Shilimkar2011-06-131-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP4, Retention-Till-Access Memory feature is not working reliably and hardware recommondation is keep it disabled by default Impacted Silicon Rev: ES1.0,2.0,2.1,2.2 Change-Id: I24c628822c0909106759a4753a003c0bec3acc3c Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Reviewed-by: Praneeth Bajjuri <praneeth@ti.com>
| | | | * OMAP4: PRCM: Enable DPLL autoidle and autogating for post dividersRajendra Nayak2011-06-131-7/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Autoidle is enabled for all DPLL's and autogating for all post divider DPLL out is also kept enabled. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Axel Haslam <axelhaslam@ti.com>
| | | | * OMAP4:CPUIDLE: remove CPUIDLE_FLAG_CHECK_BM checkAxel Haslam2011-06-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bm check function pointer is set at init fora given C state, and the flag is overwriten when a hotplug operation happens. Since the bm_check function pointer is set, having the flag check is redundant, and prevents the check from happening after hotplug operation. Signed-off-by: Axel Haslam <axelhaslam@ti.com>
| | | | * OMAP4: CPUIDLE: update latency table with recomended valuesAxel Haslam2011-06-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update cpuidle_params_table, with the latency values that where recomended, and characterized. Signed-off-by: Axel Haslam <axelhaslam@ti.com>
| | | | * omap4: introduce config option to enable oswrVikram Pandita2011-06-132-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a config option in pm-defconfig to enable oswr This way we can merge driver oswr adaptations to mainline OSWR is currently supported on silicon versions ES2.1 and above This patch will be reverted when pm-defconfig is deleted Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
| | | | * OMAP4: CPUIDLE: Define C4 as OSWRAxel Haslam2011-06-131-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is not necessary to have C4 and C3 defined as equal states. C4 state will be OSWR for MPU and CORE, Define C4 states appropriately, and disable this state until supported. Signed-off-by: Axel Haslam <axelhaslam@ti.com>
| | | | * OMAP4: CPUIDLE: Rename omap4_idle_bm_checkAxel Haslam2011-06-131-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename omap4_idle_bm_check to omap4_idle_bm_busy to be more intuitive and adjust the return value appropriately. Signed-off-by: Axel Haslam <axelhaslam@ti.com>
| | | | * OMAP: UART: introduce is active function and enable idle timerAxel Haslam2011-06-133-2/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idle timer function set the can_sleep flag which will eventually decide if the clocks can be cut, and let the power domain to hit low states. Is active is needed to prevent us from cutting clocks when there is activity going on the uart. Signed-off-by: Axel Haslam <axelhaslam@ti.com>
| | | | * OMAP:PM: remove sleep_while_idle checkAxel Haslam2011-06-131-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On omap4 this flag is disabled, so checking for it will always return 0. Signed-off-by: Axel Haslam <axelhaslam@ti.com>
| | | | * OMAP: PM: Mark the PPI and SPI interrupts as non-secure only for GP.Axel Haslam2011-06-131-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For EMU these irq cannot be marked as non-secure. Signed-off-by: Axel Haslam <axelhaslam@ti.com>
| | | | * omap4: Add mpuss off support for HS/EMU deviceSantosh Shilimkar2011-06-132-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On HS/EMU devices the context save/restore is handled through secure APIs. Also one need to save the secure ram context to the external memory while attempting mpuss OFF state This patch adds support for the same to enable MPU OFF on omap4 HS/EMU devices Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | | * omap4: Add support for secure HAL APISantosh Shilimkar2011-06-133-0/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On HS/EMU devices for context save/restore needs secure APIs. This patch adds the common infrastructure so that low power code can use these APIs Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
| | | | * omap4: pm: Add HS device support towards CPUx OFFSantosh Shilimkar2011-06-133-2/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On High Secure(HS) devices, the SCU power status register needs to be accessed using the secure API. This patch adds the support for the same in the CPUx low power path to enable CPUx OFF on HS devices Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
generated by cgit v1.1 at 2025-02-10 20:36:27 +0000