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* Merge branch 'fixes' of ↵Linus Torvalds2011-01-031-1/+1
|\ | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx * 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: dmaengine: provide dummy functions for DMA_ENGINE=n mv_xor: fix race in tasklet function
| * mv_xor: fix race in tasklet functionSaeed Bishara2011-01-031-1/+1
| | | | | | | | | | | | | | | | | | use mv_xor_slot_cleanup() instead of __mv_xor_slot_cleanup() as the former function aquires the spin lock that needed to protect the drivers data. Cc: <stable@kernel.org> Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | Merge branch 'fixes' of ↵Linus Torvalds2010-12-1410-25/+32
|\ \ | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx * 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: dmaengine: at_hdmac: fix buffer transfer size specification fsldma: fix issue of slow dma dmaengine i.MX SDMA: initialize on module_init dma : EG20T PCH: Fix miss-setting DMA descriptor intel_mid_dma: fix section mismatch warnings dmaengine: imx-sdma: fix bug in buffer descriptor initialization drivers/dma/ppc4xx: Use printf extension %pR for struct resource drivers/dma/ioat: Use the ccflag-y instead of EXTRA_CFLAGS drivers/dma/: Use the ccflag-y instead of EXTRA_CFLAGS dma: intel_mid_dma: fix double free on mid_setup_dma error path dma: imx-dma: fix imxdma_probe error path
| * dmaengine: at_hdmac: fix buffer transfer size specificationNicolas Ferre2010-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | Buffer transfer size is the number of transfers to be performed in relation with the width of the _source_ interface. So in the DMA_FROM_DEVICE case, it should be the register width that should be taken into account. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * fsldma: fix issue of slow dmaForrest Shi2010-12-132-3/+12
| | | | | | | | | | | | | | | | | | | | Fixed fsl dma slow issue by initializing dma mode register with bandwidth control. It boosts dma performance and should works with 85xx board. Signed-off-by: Forrest Shi <b29237@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dmaengine i.MX SDMA: initialize on module_initSascha Hauer2010-12-071-1/+1
| | | | | | | | | | | | | | | | The firmware framework gets initialized during fs_initcall time, so we are not allowed to call request_firmware earlier. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dma : EG20T PCH: Fix miss-setting DMA descriptorTomoya MORINAGA2010-12-071-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, in case of using scatter/gather mode, head of data is not sent to destination. The cause is second descriptor address is set to NEXT. The NEXT must have head of descriptor address. This patch sets head of descriptor address to the NEXT. Acked-by: Yong Wang <youg.y.wang@intel.com> Signed-off-by: Tomoya MORINAGA <tomoya-linux@dsn.okisemi.com> [dan.j.williams@intel.com: fixed up usage of virt_to_phys()] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * intel_mid_dma: fix section mismatch warningsDan Williams2010-12-041-3/+3
| | | | | | | | | | | | | | | | Rename intel_mid_dma_pci to intel_mid_dma_pci_driver to pick up the applied annotations of that suffix. Reported-by: <major_Lee@wistron.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dmaengine: imx-sdma: fix bug in buffer descriptor initializationAnatolij Gustschin2010-12-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently while submitting scatterlists with more than one SG entry the DMA buffer address from the first SG entry is inserted into all initialized DMA buffer descriptors. This is due to the typo in the for_each_sg() loop where the scatterlist pointer is used for obtaining the DMA buffer address and _not_ the SG list iterator. As a result all received data will be written only into the first DMA buffer while reading. While writing the data from the first DMA buffer is send to the device multiple times. This caused the filesystem destruction on the MMC card when using DMA in mxcmmc driver. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * drivers/dma/ppc4xx: Use printf extension %pR for struct resourceJoe Perches2010-12-041-3/+2
| | | | | | | | | | | | | | Using %pR standardizes the struct resource output. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * drivers/dma/ioat: Use the ccflag-y instead of EXTRA_CFLAGSTracey Dent2010-12-041-1/+1
| | | | | | | | | | | | | | | | | | Changed Makefile to use <modules>-y instead of <modules>-objs. Following (documentation/kbuild/makefiles.txt). Signed-off-by: Tracey Dent <tdent48227@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * drivers/dma/: Use the ccflag-y instead of EXTRA_CFLAGSTracey Dent2010-12-031-2/+2
| | | | | | | | | | | | | | | | | | | | Use the ccflag-y flag instead of EXTRA_CFLAGS because EXTRA_CFLAGS is deprecated and should now be switched. According to (documentation/kbuild/makefiles.txt). Signed-off-by: Tracey Dent <tdent48227@gmail.com> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dma: intel_mid_dma: fix double free on mid_setup_dma error pathAxel Lin2010-12-031-2/+0
| | | | | | | | | | | | | | | | | | We should not call kfree(dma) in mid_setup_dma error path because the memory is allocated in intel_mid_dma_probe and will be freed in intel_mid_dma_probe error path if mid_setup_dma return error. Signed-off-by: Axel Lin <axel.lin@gmail.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dma: imx-dma: fix imxdma_probe error pathAxel Lin2010-12-031-1/+1
| | | | | | | | | | | | | | | | otherwise, i will be -1 inside the latest iteration of the while loop. Signed-off-by: Axel Lin <axel.lin@gmail.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | dma: shdma: add a MODULE_ALIAS() to allow module autoloadingGuennadi Liakhovetski2010-11-251-0/+1
|/ | | | | Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* drivers/dma/Kconfig: add part number for Topcliff.Valdis.Kletnieks@vt.edu2010-10-291-2/+2
| | | | | | | | | | Product codenames are OK, but once an actual product name is available, it should be referenced as well. http://ark.intel.com/chipset.aspx?familyID=52499 Signed-off-by: Valdis Kletnieks <valdis.kletnieks@vt.edu> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'next' of ↵Linus Torvalds2010-10-2714-899/+5276
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx * 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (48 commits) DMAENGINE: move COH901318 to arch_initcall dma: imx-dma: fix signedness bug dma/timberdale: simplify conditional ste_dma40: remove channel_type ste_dma40: remove enum for endianess ste_dma40: remove TIM_FOR_LINK option ste_dma40: move mode_opt to separate config ste_dma40: move channel mode to a separate field ste_dma40: move priority to separate field ste_dma40: add variable to indicate valid dma_cfg async_tx: make async_tx channel switching opt-in move async raid6 test to lib/Kconfig.debug dmaengine: Add Freescale i.MX1/21/27 DMA driver intel_mid_dma: change the slave interface intel_mid_dma: fix the WARN_ONs intel_mid_dma: Add sg list support to DMA driver intel_mid_dma: Allow DMAC2 to share interrupt intel_mid_dma: Allow IRQ sharing intel_mid_dma: Add runtime PM support DMAENGINE: define a dummy filter function for ste_dma40 ...
| * DMAENGINE: move COH901318 to arch_initcallLinus Walleij2010-10-221-1/+1
| | | | | | | | | | | | | | | | | | | | After moving the PL022 driver to subsys_initcall() due to the need of having stuff like regulators on the other end of the SPI link, I noticed that the COH901318 DMA engine will get probed before the DMA engine, so move it to an arch_initcall(). Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dma: imx-dma: fix signedness bugSascha Hauer2010-10-221-1/+3
| | | | | | | | | | | | | | | | | | | | | | mxdmac->channel was unsigned, so check (imxdmac->channel < 0) for failed imx_dma_request_by_prio() made no sence. Explicitly check signed values. Also, fix uninitialzed use of ret. Signed-off-by: Vasiliy Kulikov <segooon@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * Merge branch 'dma40' into dmaengineDan Williams2010-10-193-21/+50
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| | * ste_dma40: remove enum for endianessRabin Vincent2010-10-192-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | A bool will suffice. The default is little endian. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | * ste_dma40: move mode_opt to separate configRabin Vincent2010-10-192-2/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Defaults are "basic mode" for physical channels, and "logical source logical destination" for logical channels. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | * ste_dma40: move channel mode to a separate fieldRabin Vincent2010-10-191-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | And keep it logical by default. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | * ste_dma40: move priority to separate fieldRabin Vincent2010-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | And keep it low priority by default. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | * ste_dma40: add variable to indicate valid dma_cfgRabin Vincent2010-10-191-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we want to reduce the amount of required channel configuration and remove channel_type, don't depend on it to indicate whether the configuration is valid. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | dma/timberdale: simplify conditionalNicolas Kaiser2010-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Simplify: ((a && b) || (!a && !b)) => (a == b) Signed-off-by: Nicolas Kaiser <nikai@nikai.net> Acked-by: Jack Stone <jwjstone@fastmail.fm> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | async_tx: make async_tx channel switching opt-inDan Williams2010-10-072-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The majority of drivers in drivers/dma/ will never establish cross channel operation chains and do not need the extra overhead in struct dma_async_tx_descriptor. Make channel switching opt-in by default. Cc: Anatolij Gustschin <agust@denx.de> Cc: Ira Snyder <iws@ovro.caltech.edu> Cc: Linus Walleij <linus.walleij@stericsson.com> Cc: Saeed Bishara <saeed@marvell.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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| *-----. \ Merge branches 'dma40', 'pl08x', 'fsldma', 'imx' and 'intel-mid' into dmaengineDan Williams2010-10-0712-266/+4625
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| | | | | * intel_mid_dma: change the slave interfaceKoul, Vinod2010-10-072-25/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In 2.6.36 kernel, dma slave control command was introduced, this patch changes the intel-mid-dma driver to this new kernel slave interface Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | | | | * intel_mid_dma: fix the WARN_ONsKoul, Vinod2010-10-071-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved the WARN_ON to BUG_ON, as WARN_ON if hit, can cause null pointer derefrences Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | | | | * intel_mid_dma: Add sg list support to DMA driverRamesh Babu K V2010-10-072-50/+247
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For a very high speed DMA various periphral devices need scatter-gather list support. The DMA hardware support link list items. This list can be circular also (adding new flag DMA_PREP_CIRCULAR_LIST) Right now this flag is in driver header and should be moved to dmaengine header file eventually Signed-off-by: Ramesh Babu K V <ramesh.b.k.v@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | | | | * intel_mid_dma: Allow DMAC2 to share interruptYong Wang2010-10-071-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow DMAC2 to share interrupt since exclusive interrupt line for mrst DMAC2 is not provided on other platforms. Signed-off-by: Yong Wang <yong.y.wang@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | | | | * intel_mid_dma: Allow IRQ sharingYong Wang2010-10-071-11/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | intel_mid_dma driver allows interrupt sharing. Thus it needs to check whether IRQ source is the DMA controller and return the appropriate IRQ return. Signed-off-by: Yong Wang <yong.y.wang@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | | | | * intel_mid_dma: Add runtime PM supportKoul, Vinod2010-10-072-8/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds runtime PM support in this dma driver for 4 PCI Controllers Whenever the driver is idle (no channels grabbed), it can go to low power state It also adds the PCI suspend and resume support Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | | | * | dmaengine: Add Freescale i.MX1/21/27 DMA driverSascha Hauer2010-10-073-0/+431
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver is currently implemented as a user to the old i.MX DMA API. This allows us to convert each user of the old API to the dmaengine API one by one. Once this is done the old DMA driver can be merged into the i.MX dmaengine driver. V2: remove some debug leftovers and unused variables Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | | | * | dmaengine: Add Freescale i.MX SDMA supportSascha Hauer2010-10-053-0/+1401
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the Freescale i.MX SDMA engine. The SDMA engine is a scatter/gather DMA engine which is implemented as a seperate coprocessor. SDMA needs its own firmware which is requested using the standard request_firmware mechanism. The firmware has different entry points for each peripheral type, so drivers have to pass the peripheral type to the DMA engine which in turn picks the correct firmware entry point from a table contained in the firmware image itself. The original Freescale code also supports support for transfering data to the internal SRAM which needs different entry points to the firmware. Support for this is currently not implemented. Also, support for the ASRC (asymmetric sample rate converter) is skipped. I took a very simple approach to implement dmaengine support. Only a single descriptor is statically assigned to a each channel. This means that transfers can't be queued up but only a single transfer is in progress. This simplifies implementation a lot and is sufficient for the usual device/memory transfers. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Linus Walleij <linus.ml.walleij@gmail.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | | | * | dmaengine: add possibility for cyclic transfersSascha Hauer2010-10-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cyclic transfers are useful for audio where a single buffer divided in periods has to be transfered endlessly until stopped. After being prepared the transfer is started using the dma_async_descriptor->tx_submit function. dma_async_descriptor->callback is called after each period. The transfer is stopped using the DMA_TERMINATE_ALL callback. While being used for cyclic transfers the channel cannot be used for other transfer types. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | | * | | ste_dma40: implement support for scatterlist to scatterlist copyIra Snyder2010-10-071-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the DMAEngine API has support for scatterlist to scatterlist copy, implement support for the STE DMA40 DMA controller. Cc: Linus Walleij <linus.ml.walleij@gmail.com> Acked-by: Per Fridén <per.friden@stericsson.com> Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | | * | | fsldma: improved DMA_SLAVE supportIra Snyder2010-10-071-182/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the generic DMAEngine API has support for scatterlist to scatterlist copying, the device_prep_slave_sg() portion of the DMA_SLAVE API is no longer necessary and has been removed. However, the device_control() portion of the DMA_SLAVE API is still useful to control device specific parameters, such as externally controlled DMA transfers and maximum burst length. A special dma_ctrl_cmd has been added to enable externally controlled DMA transfers. This is currently specific to the Freescale DMA controller, but can easily be made generic when another user is found. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | | * | | fsldma: implement support for scatterlist to scatterlist copyIra Snyder2010-10-071-3/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the DMAEngine API has support for scatterlist to scatterlist copy, implement support for the Freescale DMA controller. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | | * | | dma: add support for scatterlist to scatterlist copyIra Snyder2010-10-071-0/+2
| | | | |/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for scatterlist to scatterlist DMA transfers. A similar interface is exposed by the fsldma driver (through the DMA_SLAVE API) and by the ste_dma40 driver (through an exported function). This patch paves the way for making this type of copy operation a part of the generic DMAEngine API. Futher patches will add support in individual drivers. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| | * | | dmaengine: driver for the ARM PL080/PL081 PrimeCells v5Linus Walleij2010-09-293-0/+2176
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This creates a DMAengine driver for the ARM PL080/PL081 PrimeCells based on the implementation earlier submitted by Peter Pearse. This is working like a charm for memcpy and slave DMA to the PL011 PrimeCell on the PB11MPCore. This DMA controller is used in mostly unmodified form in the ARM RealView and Versatile platforms, in the ST-Ericsson Nomadik, and in the ST SPEAr platform. It has been converted to use the header from the Samsung PL080 derivate instead of its own defintions. The Samsungs have a custom driver in their mach-* folders though, atleast we can share the register definitions. Cc: Peter Pearse <peter.pearse@arm.com> Cc: Ben Dooks <ben-linux@fluff.org> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Alessandro Rubini <rubini@unipv.it> Acked-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> [GFP_KERNEL to GFP_NOWAIT in pl08x_prep_dma_memcpy] Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | | DMAENGINE: Remove stedma40_set_psize and pre_transfer hook in ste_dma40Per Forlin2010-10-071-51/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove obsolete pre_transfer hook in stedma40_chan_cfg. The intent of this hook is merely to handle burst size compensation for ux500 variant MMCI. Remove obsolete stedma40_set_psize since it is only called from pre_transfer. DMAEngine device_control replaces the functionality of stedma40_set_psize. Signed-off-by: Per Forlin <per.forlin@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | | DMAENGINE: Set burst size for phy and log chans in ste_dma40 dev_controlPer Forlin2010-10-071-8/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set burst for physical or logical channels respectively. Convert the values in dma_cfg to dma reg bits for physical or logical channels. Signed-off-by: Per Forlin <per.forlin@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | | DMAENGINE: ste_dma40: fix resource leaks in error paths.Rabin Vincent2010-10-071-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix some leaks of allocated descriptors in error paths. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | | DMAENGINE: ste_dma40: fix desc_getRabin Vincent2010-10-071-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix desc_get to alloc a descriptor from the cache if the ones in the list are waiting for the ack. Also, memzero the descriptor when allocated from the list to ensure all fields are cleared. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | | DMAENGINE: ste_dma40: fix clk_get failure pathRabin Vincent2010-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk_get returns an ERR_PTR. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | | DMAENGINE: ste_dma40: fix disabled channels listRabin Vincent2010-10-071-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The value in the array, not the index, specifies the channel to be disabled. Acked-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | | DMAENGINE: ste_dma40: don't pause/resume non-executing channelsJonas Aaberg2010-09-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no point in pausing what isn't running. Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | | DMAENGINE: ste_dma40: rewrote LCLA entries allocation codeJonas Aaberg2010-09-223-309/+218
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LLI allocation is now done on job level instead of channel level. Previously the maximum length of a linked job in hw on a logical channel was 8, since the LLIs where evenly divided. Now only executing jobs have allocated LLIs which increase the length to a maximum of 64 links in HW. Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
generated by cgit v1.1 at 2024-09-09 11:13:33 +0000