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-rw-r--r--arch/avr32/mach-at32ap/Makefile2
-rw-r--r--arch/avr32/mach-at32ap/at32ap.c90
-rw-r--r--arch/avr32/mach-at32ap/at32ap7000.c866
-rw-r--r--arch/avr32/mach-at32ap/clock.c148
-rw-r--r--arch/avr32/mach-at32ap/clock.h30
-rw-r--r--arch/avr32/mach-at32ap/extint.c171
-rw-r--r--arch/avr32/mach-at32ap/intc.c133
-rw-r--r--arch/avr32/mach-at32ap/intc.h327
-rw-r--r--arch/avr32/mach-at32ap/pio.c118
-rw-r--r--arch/avr32/mach-at32ap/pio.h178
-rw-r--r--arch/avr32/mach-at32ap/sm.c289
-rw-r--r--arch/avr32/mach-at32ap/sm.h240
12 files changed, 2592 insertions, 0 deletions
diff --git a/arch/avr32/mach-at32ap/Makefile b/arch/avr32/mach-at32ap/Makefile
new file mode 100644
index 0000000..4b10853
--- /dev/null
+++ b/arch/avr32/mach-at32ap/Makefile
@@ -0,0 +1,2 @@
+obj-y += at32ap.o clock.o pio.o intc.o extint.o
+obj-$(CONFIG_CPU_AT32AP7000) += at32ap7000.o
diff --git a/arch/avr32/mach-at32ap/at32ap.c b/arch/avr32/mach-at32ap/at32ap.c
new file mode 100644
index 0000000..f7cedf5
--- /dev/null
+++ b/arch/avr32/mach-at32ap/at32ap.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/init.h>
+#include <asm/arch/sm.h>
+
+struct at32_sm system_manager;
+
+static int __init at32_sm_init(void)
+{
+ struct resource *regs;
+ struct at32_sm *sm = &system_manager;
+ int ret = -ENXIO;
+
+ regs = platform_get_resource(&at32_sm_device, IORESOURCE_MEM, 0);
+ if (!regs)
+ goto fail;
+
+ spin_lock_init(&sm->lock);
+ sm->pdev = &at32_sm_device;
+
+ ret = -ENOMEM;
+ sm->regs = ioremap(regs->start, regs->end - regs->start + 1);
+ if (!sm->regs)
+ goto fail;
+
+ return 0;
+
+fail:
+ printk(KERN_ERR "Failed to initialize System Manager: %d\n", ret);
+ return ret;
+}
+
+void __init setup_platform(void)
+{
+ at32_sm_init();
+ at32_clock_init();
+ at32_portmux_init();
+
+ /* FIXME: This doesn't belong here */
+ at32_setup_serial_console(1);
+}
+
+static int __init pdc_probe(struct platform_device *pdev)
+{
+ struct clk *pclk, *hclk;
+
+ pclk = clk_get(&pdev->dev, "pclk");
+ if (IS_ERR(pclk)) {
+ dev_err(&pdev->dev, "no pclk defined\n");
+ return PTR_ERR(pclk);
+ }
+ hclk = clk_get(&pdev->dev, "hclk");
+ if (IS_ERR(hclk)) {
+ dev_err(&pdev->dev, "no hclk defined\n");
+ clk_put(pclk);
+ return PTR_ERR(hclk);
+ }
+
+ clk_enable(pclk);
+ clk_enable(hclk);
+
+ dev_info(&pdev->dev, "Atmel Peripheral DMA Controller enabled\n");
+ return 0;
+}
+
+static struct platform_driver pdc_driver = {
+ .probe = pdc_probe,
+ .driver = {
+ .name = "pdc",
+ },
+};
+
+static int __init pdc_init(void)
+{
+ return platform_driver_register(&pdc_driver);
+}
+arch_initcall(pdc_init);
diff --git a/arch/avr32/mach-at32ap/at32ap7000.c b/arch/avr32/mach-at32ap/at32ap7000.c
new file mode 100644
index 0000000..e8c6893
--- /dev/null
+++ b/arch/avr32/mach-at32ap/at32ap7000.c
@@ -0,0 +1,866 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/clk.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/board.h>
+#include <asm/arch/portmux.h>
+#include <asm/arch/sm.h>
+
+#include "clock.h"
+#include "pio.h"
+#include "sm.h"
+
+#define PBMEM(base) \
+ { \
+ .start = base, \
+ .end = base + 0x3ff, \
+ .flags = IORESOURCE_MEM, \
+ }
+#define IRQ(num) \
+ { \
+ .start = num, \
+ .end = num, \
+ .flags = IORESOURCE_IRQ, \
+ }
+#define NAMED_IRQ(num, _name) \
+ { \
+ .start = num, \
+ .end = num, \
+ .name = _name, \
+ .flags = IORESOURCE_IRQ, \
+ }
+
+#define DEFINE_DEV(_name, _id) \
+static struct platform_device _name##_id##_device = { \
+ .name = #_name, \
+ .id = _id, \
+ .resource = _name##_id##_resource, \
+ .num_resources = ARRAY_SIZE(_name##_id##_resource), \
+}
+#define DEFINE_DEV_DATA(_name, _id) \
+static struct platform_device _name##_id##_device = { \
+ .name = #_name, \
+ .id = _id, \
+ .dev = { \
+ .platform_data = &_name##_id##_data, \
+ }, \
+ .resource = _name##_id##_resource, \
+ .num_resources = ARRAY_SIZE(_name##_id##_resource), \
+}
+
+#define DEV_CLK(_name, devname, bus, _index) \
+static struct clk devname##_##_name = { \
+ .name = #_name, \
+ .dev = &devname##_device.dev, \
+ .parent = &bus##_clk, \
+ .mode = bus##_clk_mode, \
+ .get_rate = bus##_clk_get_rate, \
+ .index = _index, \
+}
+
+enum {
+ PIOA,
+ PIOB,
+ PIOC,
+ PIOD,
+};
+
+enum {
+ FUNC_A,
+ FUNC_B,
+};
+
+unsigned long at32ap7000_osc_rates[3] = {
+ [0] = 32768,
+ /* FIXME: these are ATSTK1002-specific */
+ [1] = 20000000,
+ [2] = 12000000,
+};
+
+static unsigned long osc_get_rate(struct clk *clk)
+{
+ return at32ap7000_osc_rates[clk->index];
+}
+
+static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
+{
+ unsigned long div, mul, rate;
+
+ if (!(control & SM_BIT(PLLEN)))
+ return 0;
+
+ div = SM_BFEXT(PLLDIV, control) + 1;
+ mul = SM_BFEXT(PLLMUL, control) + 1;
+
+ rate = clk->parent->get_rate(clk->parent);
+ rate = (rate + div / 2) / div;
+ rate *= mul;
+
+ return rate;
+}
+
+static unsigned long pll0_get_rate(struct clk *clk)
+{
+ u32 control;
+
+ control = sm_readl(&system_manager, PM_PLL0);
+
+ return pll_get_rate(clk, control);
+}
+
+static unsigned long pll1_get_rate(struct clk *clk)
+{
+ u32 control;
+
+ control = sm_readl(&system_manager, PM_PLL1);
+
+ return pll_get_rate(clk, control);
+}
+
+/*
+ * The AT32AP7000 has five primary clock sources: One 32kHz
+ * oscillator, two crystal oscillators and two PLLs.
+ */
+static struct clk osc32k = {
+ .name = "osc32k",
+ .get_rate = osc_get_rate,
+ .users = 1,
+ .index = 0,
+};
+static struct clk osc0 = {
+ .name = "osc0",
+ .get_rate = osc_get_rate,
+ .users = 1,
+ .index = 1,
+};
+static struct clk osc1 = {
+ .name = "osc1",
+ .get_rate = osc_get_rate,
+ .index = 2,
+};
+static struct clk pll0 = {
+ .name = "pll0",
+ .get_rate = pll0_get_rate,
+ .parent = &osc0,
+};
+static struct clk pll1 = {
+ .name = "pll1",
+ .get_rate = pll1_get_rate,
+ .parent = &osc0,
+};
+
+/*
+ * The main clock can be either osc0 or pll0. The boot loader may
+ * have chosen one for us, so we don't really know which one until we
+ * have a look at the SM.
+ */
+static struct clk *main_clock;
+
+/*
+ * Synchronous clocks are generated from the main clock. The clocks
+ * must satisfy the constraint
+ * fCPU >= fHSB >= fPB
+ * i.e. each clock must not be faster than its parent.
+ */
+static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
+{
+ return main_clock->get_rate(main_clock) >> shift;
+};
+
+static void cpu_clk_mode(struct clk *clk, int enabled)
+{
+ struct at32_sm *sm = &system_manager;
+ unsigned long flags;
+ u32 mask;
+
+ spin_lock_irqsave(&sm->lock, flags);
+ mask = sm_readl(sm, PM_CPU_MASK);
+ if (enabled)
+ mask |= 1 << clk->index;
+ else
+ mask &= ~(1 << clk->index);
+ sm_writel(sm, PM_CPU_MASK, mask);
+ spin_unlock_irqrestore(&sm->lock, flags);
+}
+
+static unsigned long cpu_clk_get_rate(struct clk *clk)
+{
+ unsigned long cksel, shift = 0;
+
+ cksel = sm_readl(&system_manager, PM_CKSEL);
+ if (cksel & SM_BIT(CPUDIV))
+ shift = SM_BFEXT(CPUSEL, cksel) + 1;
+
+ return bus_clk_get_rate(clk, shift);
+}
+
+static void hsb_clk_mode(struct clk *clk, int enabled)
+{
+ struct at32_sm *sm = &system_manager;
+ unsigned long flags;
+ u32 mask;
+
+ spin_lock_irqsave(&sm->lock, flags);
+ mask = sm_readl(sm, PM_HSB_MASK);
+ if (enabled)
+ mask |= 1 << clk->index;
+ else
+ mask &= ~(1 << clk->index);
+ sm_writel(sm, PM_HSB_MASK, mask);
+ spin_unlock_irqrestore(&sm->lock, flags);
+}
+
+static unsigned long hsb_clk_get_rate(struct clk *clk)
+{
+ unsigned long cksel, shift = 0;
+
+ cksel = sm_readl(&system_manager, PM_CKSEL);
+ if (cksel & SM_BIT(HSBDIV))
+ shift = SM_BFEXT(HSBSEL, cksel) + 1;
+
+ return bus_clk_get_rate(clk, shift);
+}
+
+static void pba_clk_mode(struct clk *clk, int enabled)
+{
+ struct at32_sm *sm = &system_manager;
+ unsigned long flags;
+ u32 mask;
+
+ spin_lock_irqsave(&sm->lock, flags);
+ mask = sm_readl(sm, PM_PBA_MASK);
+ if (enabled)
+ mask |= 1 << clk->index;
+ else
+ mask &= ~(1 << clk->index);
+ sm_writel(sm, PM_PBA_MASK, mask);
+ spin_unlock_irqrestore(&sm->lock, flags);
+}
+
+static unsigned long pba_clk_get_rate(struct clk *clk)
+{
+ unsigned long cksel, shift = 0;
+
+ cksel = sm_readl(&system_manager, PM_CKSEL);
+ if (cksel & SM_BIT(PBADIV))
+ shift = SM_BFEXT(PBASEL, cksel) + 1;
+
+ return bus_clk_get_rate(clk, shift);
+}
+
+static void pbb_clk_mode(struct clk *clk, int enabled)
+{
+ struct at32_sm *sm = &system_manager;
+ unsigned long flags;
+ u32 mask;
+
+ spin_lock_irqsave(&sm->lock, flags);
+ mask = sm_readl(sm, PM_PBB_MASK);
+ if (enabled)
+ mask |= 1 << clk->index;
+ else
+ mask &= ~(1 << clk->index);
+ sm_writel(sm, PM_PBB_MASK, mask);
+ spin_unlock_irqrestore(&sm->lock, flags);
+}
+
+static unsigned long pbb_clk_get_rate(struct clk *clk)
+{
+ unsigned long cksel, shift = 0;
+
+ cksel = sm_readl(&system_manager, PM_CKSEL);
+ if (cksel & SM_BIT(PBBDIV))
+ shift = SM_BFEXT(PBBSEL, cksel) + 1;
+
+ return bus_clk_get_rate(clk, shift);
+}
+
+static struct clk cpu_clk = {
+ .name = "cpu",
+ .get_rate = cpu_clk_get_rate,
+ .users = 1,
+};
+static struct clk hsb_clk = {
+ .name = "hsb",
+ .parent = &cpu_clk,
+ .get_rate = hsb_clk_get_rate,
+};
+static struct clk pba_clk = {
+ .name = "pba",
+ .parent = &hsb_clk,
+ .mode = hsb_clk_mode,
+ .get_rate = pba_clk_get_rate,
+ .index = 1,
+};
+static struct clk pbb_clk = {
+ .name = "pbb",
+ .parent = &hsb_clk,
+ .mode = hsb_clk_mode,
+ .get_rate = pbb_clk_get_rate,
+ .users = 1,
+ .index = 2,
+};
+
+/* --------------------------------------------------------------------
+ * Generic Clock operations
+ * -------------------------------------------------------------------- */
+
+static void genclk_mode(struct clk *clk, int enabled)
+{
+ u32 control;
+
+ BUG_ON(clk->index > 7);
+
+ control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
+ if (enabled)
+ control |= SM_BIT(CEN);
+ else
+ control &= ~SM_BIT(CEN);
+ sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
+}
+
+static unsigned long genclk_get_rate(struct clk *clk)
+{
+ u32 control;
+ unsigned long div = 1;
+
+ BUG_ON(clk->index > 7);
+
+ if (!clk->parent)
+ return 0;
+
+ control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
+ if (control & SM_BIT(DIVEN))
+ div = 2 * (SM_BFEXT(DIV, control) + 1);
+
+ return clk->parent->get_rate(clk->parent) / div;
+}
+
+static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
+{
+ u32 control;
+ unsigned long parent_rate, actual_rate, div;
+
+ BUG_ON(clk->index > 7);
+
+ if (!clk->parent)
+ return 0;
+
+ parent_rate = clk->parent->get_rate(clk->parent);
+ control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
+
+ if (rate > 3 * parent_rate / 4) {
+ actual_rate = parent_rate;
+ control &= ~SM_BIT(DIVEN);
+ } else {
+ div = (parent_rate + rate) / (2 * rate) - 1;
+ control = SM_BFINS(DIV, div, control) | SM_BIT(DIVEN);
+ actual_rate = parent_rate / (2 * (div + 1));
+ }
+
+ printk("clk %s: new rate %lu (actual rate %lu)\n",
+ clk->name, rate, actual_rate);
+
+ if (apply)
+ sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index,
+ control);
+
+ return actual_rate;
+}
+
+int genclk_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 control;
+
+ BUG_ON(clk->index > 7);
+
+ printk("clk %s: new parent %s (was %s)\n",
+ clk->name, parent->name,
+ clk->parent ? clk->parent->name : "(null)");
+
+ control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
+
+ if (parent == &osc1 || parent == &pll1)
+ control |= SM_BIT(OSCSEL);
+ else if (parent == &osc0 || parent == &pll0)
+ control &= ~SM_BIT(OSCSEL);
+ else
+ return -EINVAL;
+
+ if (parent == &pll0 || parent == &pll1)
+ control |= SM_BIT(PLLSEL);
+ else
+ control &= ~SM_BIT(PLLSEL);
+
+ sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
+ clk->parent = parent;
+
+ return 0;
+}
+
+/* --------------------------------------------------------------------
+ * System peripherals
+ * -------------------------------------------------------------------- */
+static struct resource sm_resource[] = {
+ PBMEM(0xfff00000),
+ NAMED_IRQ(19, "eim"),
+ NAMED_IRQ(20, "pm"),
+ NAMED_IRQ(21, "rtc"),
+};
+struct platform_device at32_sm_device = {
+ .name = "sm",
+ .id = 0,
+ .resource = sm_resource,
+ .num_resources = ARRAY_SIZE(sm_resource),
+};
+DEV_CLK(pclk, at32_sm, pbb, 0);
+
+static struct resource intc0_resource[] = {
+ PBMEM(0xfff00400),
+};
+struct platform_device at32_intc0_device = {
+ .name = "intc",
+ .id = 0,
+ .resource = intc0_resource,
+ .num_resources = ARRAY_SIZE(intc0_resource),
+};
+DEV_CLK(pclk, at32_intc0, pbb, 1);
+
+static struct clk ebi_clk = {
+ .name = "ebi",
+ .parent = &hsb_clk,
+ .mode = hsb_clk_mode,
+ .get_rate = hsb_clk_get_rate,
+ .users = 1,
+};
+static struct clk hramc_clk = {
+ .name = "hramc",
+ .parent = &hsb_clk,
+ .mode = hsb_clk_mode,
+ .get_rate = hsb_clk_get_rate,
+ .users = 1,
+};
+
+static struct platform_device pdc_device = {
+ .name = "pdc",
+ .id = 0,
+};
+DEV_CLK(hclk, pdc, hsb, 4);
+DEV_CLK(pclk, pdc, pba, 16);
+
+static struct clk pico_clk = {
+ .name = "pico",
+ .parent = &cpu_clk,
+ .mode = cpu_clk_mode,
+ .get_rate = cpu_clk_get_rate,
+ .users = 1,
+};
+
+/* --------------------------------------------------------------------
+ * PIO
+ * -------------------------------------------------------------------- */
+
+static struct resource pio0_resource[] = {
+ PBMEM(0xffe02800),
+ IRQ(13),
+};
+DEFINE_DEV(pio, 0);
+DEV_CLK(mck, pio0, pba, 10);
+
+static struct resource pio1_resource[] = {
+ PBMEM(0xffe02c00),
+ IRQ(14),
+};
+DEFINE_DEV(pio, 1);
+DEV_CLK(mck, pio1, pba, 11);
+
+static struct resource pio2_resource[] = {
+ PBMEM(0xffe03000),
+ IRQ(15),
+};
+DEFINE_DEV(pio, 2);
+DEV_CLK(mck, pio2, pba, 12);
+
+static struct resource pio3_resource[] = {
+ PBMEM(0xffe03400),
+ IRQ(16),
+};
+DEFINE_DEV(pio, 3);
+DEV_CLK(mck, pio3, pba, 13);
+
+void __init at32_add_system_devices(void)
+{
+ system_manager.eim_first_irq = NR_INTERNAL_IRQS;
+
+ platform_device_register(&at32_sm_device);
+ platform_device_register(&at32_intc0_device);
+ platform_device_register(&pdc_device);
+
+ platform_device_register(&pio0_device);
+ platform_device_register(&pio1_device);
+ platform_device_register(&pio2_device);
+ platform_device_register(&pio3_device);
+}
+
+/* --------------------------------------------------------------------
+ * USART
+ * -------------------------------------------------------------------- */
+
+static struct resource usart0_resource[] = {
+ PBMEM(0xffe00c00),
+ IRQ(7),
+};
+DEFINE_DEV(usart, 0);
+DEV_CLK(usart, usart0, pba, 4);
+
+static struct resource usart1_resource[] = {
+ PBMEM(0xffe01000),
+ IRQ(7),
+};
+DEFINE_DEV(usart, 1);
+DEV_CLK(usart, usart1, pba, 4);
+
+static struct resource usart2_resource[] = {
+ PBMEM(0xffe01400),
+ IRQ(8),
+};
+DEFINE_DEV(usart, 2);
+DEV_CLK(usart, usart2, pba, 5);
+
+static struct resource usart3_resource[] = {
+ PBMEM(0xffe01800),
+ IRQ(9),
+};
+DEFINE_DEV(usart, 3);
+DEV_CLK(usart, usart3, pba, 6);
+
+static inline void configure_usart0_pins(void)
+{
+ portmux_set_func(PIOA, 8, FUNC_B); /* RXD */
+ portmux_set_func(PIOA, 9, FUNC_B); /* TXD */
+}
+
+static inline void configure_usart1_pins(void)
+{
+ portmux_set_func(PIOA, 17, FUNC_A); /* RXD */
+ portmux_set_func(PIOA, 18, FUNC_A); /* TXD */
+}
+
+static inline void configure_usart2_pins(void)
+{
+ portmux_set_func(PIOB, 26, FUNC_B); /* RXD */
+ portmux_set_func(PIOB, 27, FUNC_B); /* TXD */
+}
+
+static inline void configure_usart3_pins(void)
+{
+ portmux_set_func(PIOB, 18, FUNC_B); /* RXD */
+ portmux_set_func(PIOB, 17, FUNC_B); /* TXD */
+}
+
+static struct platform_device *setup_usart(unsigned int id)
+{
+ struct platform_device *pdev;
+
+ switch (id) {
+ case 0:
+ pdev = &usart0_device;
+ configure_usart0_pins();
+ break;
+ case 1:
+ pdev = &usart1_device;
+ configure_usart1_pins();
+ break;
+ case 2:
+ pdev = &usart2_device;
+ configure_usart2_pins();
+ break;
+ case 3:
+ pdev = &usart3_device;
+ configure_usart3_pins();
+ break;
+ default:
+ pdev = NULL;
+ break;
+ }
+
+ return pdev;
+}
+
+struct platform_device *__init at32_add_device_usart(unsigned int id)
+{
+ struct platform_device *pdev;
+
+ pdev = setup_usart(id);
+ if (pdev)
+ platform_device_register(pdev);
+
+ return pdev;
+}
+
+struct platform_device *at91_default_console_device;
+
+void __init at32_setup_serial_console(unsigned int usart_id)
+{
+ at91_default_console_device = setup_usart(usart_id);
+}
+
+/* --------------------------------------------------------------------
+ * Ethernet
+ * -------------------------------------------------------------------- */
+
+static struct eth_platform_data macb0_data;
+static struct resource macb0_resource[] = {
+ PBMEM(0xfff01800),
+ IRQ(25),
+};
+DEFINE_DEV_DATA(macb, 0);
+DEV_CLK(hclk, macb0, hsb, 8);
+DEV_CLK(pclk, macb0, pbb, 6);
+
+struct platform_device *__init
+at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
+{
+ struct platform_device *pdev;
+
+ switch (id) {
+ case 0:
+ pdev = &macb0_device;
+
+ portmux_set_func(PIOC, 3, FUNC_A); /* TXD0 */
+ portmux_set_func(PIOC, 4, FUNC_A); /* TXD1 */
+ portmux_set_func(PIOC, 7, FUNC_A); /* TXEN */
+ portmux_set_func(PIOC, 8, FUNC_A); /* TXCK */
+ portmux_set_func(PIOC, 9, FUNC_A); /* RXD0 */
+ portmux_set_func(PIOC, 10, FUNC_A); /* RXD1 */
+ portmux_set_func(PIOC, 13, FUNC_A); /* RXER */
+ portmux_set_func(PIOC, 15, FUNC_A); /* RXDV */
+ portmux_set_func(PIOC, 16, FUNC_A); /* MDC */
+ portmux_set_func(PIOC, 17, FUNC_A); /* MDIO */
+
+ if (!data->is_rmii) {
+ portmux_set_func(PIOC, 0, FUNC_A); /* COL */
+ portmux_set_func(PIOC, 1, FUNC_A); /* CRS */
+ portmux_set_func(PIOC, 2, FUNC_A); /* TXER */
+ portmux_set_func(PIOC, 5, FUNC_A); /* TXD2 */
+ portmux_set_func(PIOC, 6, FUNC_A); /* TXD3 */
+ portmux_set_func(PIOC, 11, FUNC_A); /* RXD2 */
+ portmux_set_func(PIOC, 12, FUNC_A); /* RXD3 */
+ portmux_set_func(PIOC, 14, FUNC_A); /* RXCK */
+ portmux_set_func(PIOC, 18, FUNC_A); /* SPD */
+ }
+ break;
+
+ default:
+ return NULL;
+ }
+
+ memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
+ platform_device_register(pdev);
+
+ return pdev;
+}
+
+/* --------------------------------------------------------------------
+ * SPI
+ * -------------------------------------------------------------------- */
+static struct resource spi0_resource[] = {
+ PBMEM(0xffe00000),
+ IRQ(3),
+};
+DEFINE_DEV(spi, 0);
+DEV_CLK(mck, spi0, pba, 0);
+
+struct platform_device *__init at32_add_device_spi(unsigned int id)
+{
+ struct platform_device *pdev;
+
+ switch (id) {
+ case 0:
+ pdev = &spi0_device;
+ portmux_set_func(PIOA, 0, FUNC_A); /* MISO */
+ portmux_set_func(PIOA, 1, FUNC_A); /* MOSI */
+ portmux_set_func(PIOA, 2, FUNC_A); /* SCK */
+ portmux_set_func(PIOA, 3, FUNC_A); /* NPCS0 */
+ portmux_set_func(PIOA, 4, FUNC_A); /* NPCS1 */
+ portmux_set_func(PIOA, 5, FUNC_A); /* NPCS2 */
+ break;
+
+ default:
+ return NULL;
+ }
+
+ platform_device_register(pdev);
+ return pdev;
+}
+
+/* --------------------------------------------------------------------
+ * LCDC
+ * -------------------------------------------------------------------- */
+static struct lcdc_platform_data lcdc0_data;
+static struct resource lcdc0_resource[] = {
+ {
+ .start = 0xff000000,
+ .end = 0xff000fff,
+ .flags = IORESOURCE_MEM,
+ },
+ IRQ(1),
+};
+DEFINE_DEV_DATA(lcdc, 0);
+DEV_CLK(hclk, lcdc0, hsb, 7);
+static struct clk lcdc0_pixclk = {
+ .name = "pixclk",
+ .dev = &lcdc0_device.dev,
+ .mode = genclk_mode,
+ .get_rate = genclk_get_rate,
+ .set_rate = genclk_set_rate,
+ .set_parent = genclk_set_parent,
+ .index = 7,
+};
+
+struct platform_device *__init
+at32_add_device_lcdc(unsigned int id, struct lcdc_platform_data *data)
+{
+ struct platform_device *pdev;
+
+ switch (id) {
+ case 0:
+ pdev = &lcdc0_device;
+ portmux_set_func(PIOC, 19, FUNC_A); /* CC */
+ portmux_set_func(PIOC, 20, FUNC_A); /* HSYNC */
+ portmux_set_func(PIOC, 21, FUNC_A); /* PCLK */
+ portmux_set_func(PIOC, 22, FUNC_A); /* VSYNC */
+ portmux_set_func(PIOC, 23, FUNC_A); /* DVAL */
+ portmux_set_func(PIOC, 24, FUNC_A); /* MODE */
+ portmux_set_func(PIOC, 25, FUNC_A); /* PWR */
+ portmux_set_func(PIOC, 26, FUNC_A); /* DATA0 */
+ portmux_set_func(PIOC, 27, FUNC_A); /* DATA1 */
+ portmux_set_func(PIOC, 28, FUNC_A); /* DATA2 */
+ portmux_set_func(PIOC, 29, FUNC_A); /* DATA3 */
+ portmux_set_func(PIOC, 30, FUNC_A); /* DATA4 */
+ portmux_set_func(PIOC, 31, FUNC_A); /* DATA5 */
+ portmux_set_func(PIOD, 0, FUNC_A); /* DATA6 */
+ portmux_set_func(PIOD, 1, FUNC_A); /* DATA7 */
+ portmux_set_func(PIOD, 2, FUNC_A); /* DATA8 */
+ portmux_set_func(PIOD, 3, FUNC_A); /* DATA9 */
+ portmux_set_func(PIOD, 4, FUNC_A); /* DATA10 */
+ portmux_set_func(PIOD, 5, FUNC_A); /* DATA11 */
+ portmux_set_func(PIOD, 6, FUNC_A); /* DATA12 */
+ portmux_set_func(PIOD, 7, FUNC_A); /* DATA13 */
+ portmux_set_func(PIOD, 8, FUNC_A); /* DATA14 */
+ portmux_set_func(PIOD, 9, FUNC_A); /* DATA15 */
+ portmux_set_func(PIOD, 10, FUNC_A); /* DATA16 */
+ portmux_set_func(PIOD, 11, FUNC_A); /* DATA17 */
+ portmux_set_func(PIOD, 12, FUNC_A); /* DATA18 */
+ portmux_set_func(PIOD, 13, FUNC_A); /* DATA19 */
+ portmux_set_func(PIOD, 14, FUNC_A); /* DATA20 */
+ portmux_set_func(PIOD, 15, FUNC_A); /* DATA21 */
+ portmux_set_func(PIOD, 16, FUNC_A); /* DATA22 */
+ portmux_set_func(PIOD, 17, FUNC_A); /* DATA23 */
+
+ clk_set_parent(&lcdc0_pixclk, &pll0);
+ clk_set_rate(&lcdc0_pixclk, clk_get_rate(&pll0));
+ break;
+
+ default:
+ return NULL;
+ }
+
+ memcpy(pdev->dev.platform_data, data,
+ sizeof(struct lcdc_platform_data));
+
+ platform_device_register(pdev);
+ return pdev;
+}
+
+struct clk *at32_clock_list[] = {
+ &osc32k,
+ &osc0,
+ &osc1,
+ &pll0,
+ &pll1,
+ &cpu_clk,
+ &hsb_clk,
+ &pba_clk,
+ &pbb_clk,
+ &at32_sm_pclk,
+ &at32_intc0_pclk,
+ &ebi_clk,
+ &hramc_clk,
+ &pdc_hclk,
+ &pdc_pclk,
+ &pico_clk,
+ &pio0_mck,
+ &pio1_mck,
+ &pio2_mck,
+ &pio3_mck,
+ &usart0_usart,
+ &usart1_usart,
+ &usart2_usart,
+ &usart3_usart,
+ &macb0_hclk,
+ &macb0_pclk,
+ &spi0_mck,
+ &lcdc0_hclk,
+ &lcdc0_pixclk,
+};
+unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
+
+void __init at32_portmux_init(void)
+{
+ at32_init_pio(&pio0_device);
+ at32_init_pio(&pio1_device);
+ at32_init_pio(&pio2_device);
+ at32_init_pio(&pio3_device);
+}
+
+void __init at32_clock_init(void)
+{
+ struct at32_sm *sm = &system_manager;
+ u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
+ int i;
+
+ if (sm_readl(sm, PM_MCCTRL) & SM_BIT(PLLSEL))
+ main_clock = &pll0;
+ else
+ main_clock = &osc0;
+
+ if (sm_readl(sm, PM_PLL0) & SM_BIT(PLLOSC))
+ pll0.parent = &osc1;
+ if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC))
+ pll1.parent = &osc1;
+
+ /*
+ * Turn on all clocks that have at least one user already, and
+ * turn off everything else. We only do this for module
+ * clocks, and even though it isn't particularly pretty to
+ * check the address of the mode function, it should do the
+ * trick...
+ */
+ for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
+ struct clk *clk = at32_clock_list[i];
+
+ if (clk->mode == &cpu_clk_mode)
+ cpu_mask |= 1 << clk->index;
+ else if (clk->mode == &hsb_clk_mode)
+ hsb_mask |= 1 << clk->index;
+ else if (clk->mode == &pba_clk_mode)
+ pba_mask |= 1 << clk->index;
+ else if (clk->mode == &pbb_clk_mode)
+ pbb_mask |= 1 << clk->index;
+ }
+
+ sm_writel(sm, PM_CPU_MASK, cpu_mask);
+ sm_writel(sm, PM_HSB_MASK, hsb_mask);
+ sm_writel(sm, PM_PBA_MASK, pba_mask);
+ sm_writel(sm, PM_PBB_MASK, pbb_mask);
+}
diff --git a/arch/avr32/mach-at32ap/clock.c b/arch/avr32/mach-at32ap/clock.c
new file mode 100644
index 0000000..3d0d109
--- /dev/null
+++ b/arch/avr32/mach-at32ap/clock.c
@@ -0,0 +1,148 @@
+/*
+ * Clock management for AT32AP CPUs
+ *
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * Based on arch/arm/mach-at91rm9200/clock.c
+ * Copyright (C) 2005 David Brownell
+ * Copyright (C) 2005 Ivan Kokshaysky
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/device.h>
+#include <linux/string.h>
+
+#include "clock.h"
+
+static spinlock_t clk_lock = SPIN_LOCK_UNLOCKED;
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+ int i;
+
+ for (i = 0; i < at32_nr_clocks; i++) {
+ struct clk *clk = at32_clock_list[i];
+
+ if (clk->dev == dev && strcmp(id, clk->name) == 0)
+ return clk;
+ }
+
+ return ERR_PTR(-ENOENT);
+}
+EXPORT_SYMBOL(clk_get);
+
+void clk_put(struct clk *clk)
+{
+ /* clocks are static for now, we can't free them */
+}
+EXPORT_SYMBOL(clk_put);
+
+static void __clk_enable(struct clk *clk)
+{
+ if (clk->parent)
+ __clk_enable(clk->parent);
+ if (clk->users++ == 0 && clk->mode)
+ clk->mode(clk, 1);
+}
+
+int clk_enable(struct clk *clk)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&clk_lock, flags);
+ __clk_enable(clk);
+ spin_unlock_irqrestore(&clk_lock, flags);
+
+ return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+static void __clk_disable(struct clk *clk)
+{
+ BUG_ON(clk->users == 0);
+
+ if (--clk->users == 0 && clk->mode)
+ clk->mode(clk, 0);
+ if (clk->parent)
+ __clk_disable(clk->parent);
+}
+
+void clk_disable(struct clk *clk)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&clk_lock, flags);
+ __clk_disable(clk);
+ spin_unlock_irqrestore(&clk_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ unsigned long flags;
+ unsigned long rate;
+
+ spin_lock_irqsave(&clk_lock, flags);
+ rate = clk->get_rate(clk);
+ spin_unlock_irqrestore(&clk_lock, flags);
+
+ return rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long flags, actual_rate;
+
+ if (!clk->set_rate)
+ return -ENOSYS;
+
+ spin_lock_irqsave(&clk_lock, flags);
+ actual_rate = clk->set_rate(clk, rate, 0);
+ spin_unlock_irqrestore(&clk_lock, flags);
+
+ return actual_rate;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long flags;
+ long ret;
+
+ if (!clk->set_rate)
+ return -ENOSYS;
+
+ spin_lock_irqsave(&clk_lock, flags);
+ ret = clk->set_rate(clk, rate, 1);
+ spin_unlock_irqrestore(&clk_lock, flags);
+
+ return (ret < 0) ? ret : 0;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ unsigned long flags;
+ int ret;
+
+ if (!clk->set_parent)
+ return -ENOSYS;
+
+ spin_lock_irqsave(&clk_lock, flags);
+ ret = clk->set_parent(clk, parent);
+ spin_unlock_irqrestore(&clk_lock, flags);
+
+ return ret;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+ return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
diff --git a/arch/avr32/mach-at32ap/clock.h b/arch/avr32/mach-at32ap/clock.h
new file mode 100644
index 0000000..f953f04
--- /dev/null
+++ b/arch/avr32/mach-at32ap/clock.h
@@ -0,0 +1,30 @@
+/*
+ * Clock management for AT32AP CPUs
+ *
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * Based on arch/arm/mach-at91rm9200/clock.c
+ * Copyright (C) 2005 David Brownell
+ * Copyright (C) 2005 Ivan Kokshaysky
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/clk.h>
+
+struct clk {
+ const char *name; /* Clock name/function */
+ struct device *dev; /* Device the clock is used by */
+ struct clk *parent; /* Parent clock, if any */
+ void (*mode)(struct clk *clk, int enabled);
+ unsigned long (*get_rate)(struct clk *clk);
+ long (*set_rate)(struct clk *clk, unsigned long rate,
+ int apply);
+ int (*set_parent)(struct clk *clk, struct clk *parent);
+ u16 users; /* Enabled if non-zero */
+ u16 index; /* Sibling index */
+};
+
+extern struct clk *at32_clock_list[];
+extern unsigned int at32_nr_clocks;
diff --git a/arch/avr32/mach-at32ap/extint.c b/arch/avr32/mach-at32ap/extint.c
new file mode 100644
index 0000000..7da9c5f
--- /dev/null
+++ b/arch/avr32/mach-at32ap/extint.c
@@ -0,0 +1,171 @@
+/*
+ * External interrupt handling for AT32AP CPUs
+ *
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/random.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/sm.h>
+
+#include "sm.h"
+
+static void eim_ack_irq(unsigned int irq)
+{
+ struct at32_sm *sm = get_irq_chip_data(irq);
+ sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
+}
+
+static void eim_mask_irq(unsigned int irq)
+{
+ struct at32_sm *sm = get_irq_chip_data(irq);
+ sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
+}
+
+static void eim_mask_ack_irq(unsigned int irq)
+{
+ struct at32_sm *sm = get_irq_chip_data(irq);
+ sm_writel(sm, EIM_ICR, 1 << (irq - sm->eim_first_irq));
+ sm_writel(sm, EIM_IDR, 1 << (irq - sm->eim_first_irq));
+}
+
+static void eim_unmask_irq(unsigned int irq)
+{
+ struct at32_sm *sm = get_irq_chip_data(irq);
+ sm_writel(sm, EIM_IER, 1 << (irq - sm->eim_first_irq));
+}
+
+static int eim_set_irq_type(unsigned int irq, unsigned int flow_type)
+{
+ struct at32_sm *sm = get_irq_chip_data(irq);
+ unsigned int i = irq - sm->eim_first_irq;
+ u32 mode, edge, level;
+ unsigned long flags;
+ int ret = 0;
+
+ flow_type &= IRQ_TYPE_SENSE_MASK;
+
+ spin_lock_irqsave(&sm->lock, flags);
+
+ mode = sm_readl(sm, EIM_MODE);
+ edge = sm_readl(sm, EIM_EDGE);
+ level = sm_readl(sm, EIM_LEVEL);
+
+ switch (flow_type) {
+ case IRQ_TYPE_LEVEL_LOW:
+ mode |= 1 << i;
+ level &= ~(1 << i);
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ mode |= 1 << i;
+ level |= 1 << i;
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ mode &= ~(1 << i);
+ edge |= 1 << i;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ mode &= ~(1 << i);
+ edge &= ~(1 << i);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ sm_writel(sm, EIM_MODE, mode);
+ sm_writel(sm, EIM_EDGE, edge);
+ sm_writel(sm, EIM_LEVEL, level);
+
+ spin_unlock_irqrestore(&sm->lock, flags);
+
+ return ret;
+}
+
+struct irq_chip eim_chip = {
+ .name = "eim",
+ .ack = eim_ack_irq,
+ .mask = eim_mask_irq,
+ .mask_ack = eim_mask_ack_irq,
+ .unmask = eim_unmask_irq,
+ .set_type = eim_set_irq_type,
+};
+
+static void demux_eim_irq(unsigned int irq, struct irq_desc *desc,
+ struct pt_regs *regs)
+{
+ struct at32_sm *sm = desc->handler_data;
+ struct irq_desc *ext_desc;
+ unsigned long status, pending;
+ unsigned int i, ext_irq;
+
+ spin_lock(&sm->lock);
+
+ status = sm_readl(sm, EIM_ISR);
+ pending = status & sm_readl(sm, EIM_IMR);
+
+ while (pending) {
+ i = fls(pending) - 1;
+ pending &= ~(1 << i);
+
+ ext_irq = i + sm->eim_first_irq;
+ ext_desc = irq_desc + ext_irq;
+ ext_desc->handle_irq(ext_irq, ext_desc, regs);
+ }
+
+ spin_unlock(&sm->lock);
+}
+
+static int __init eim_init(void)
+{
+ struct at32_sm *sm = &system_manager;
+ unsigned int i;
+ unsigned int nr_irqs;
+ unsigned int int_irq;
+ u32 pattern;
+
+ /*
+ * The EIM is really the same module as SM, so register
+ * mapping, etc. has been taken care of already.
+ */
+
+ /*
+ * Find out how many interrupt lines that are actually
+ * implemented in hardware.
+ */
+ sm_writel(sm, EIM_IDR, ~0UL);
+ sm_writel(sm, EIM_MODE, ~0UL);
+ pattern = sm_readl(sm, EIM_MODE);
+ nr_irqs = fls(pattern);
+
+ sm->eim_chip = &eim_chip;
+
+ for (i = 0; i < nr_irqs; i++) {
+ set_irq_chip(sm->eim_first_irq + i, &eim_chip);
+ set_irq_chip_data(sm->eim_first_irq + i, sm);
+ }
+
+ int_irq = platform_get_irq_byname(sm->pdev, "eim");
+
+ set_irq_chained_handler(int_irq, demux_eim_irq);
+ set_irq_data(int_irq, sm);
+
+ printk("EIM: External Interrupt Module at 0x%p, IRQ %u\n",
+ sm->regs, int_irq);
+ printk("EIM: Handling %u external IRQs, starting with IRQ %u\n",
+ nr_irqs, sm->eim_first_irq);
+
+ return 0;
+}
+arch_initcall(eim_init);
diff --git a/arch/avr32/mach-at32ap/intc.c b/arch/avr32/mach-at32ap/intc.c
new file mode 100644
index 0000000..74f8c9f
--- /dev/null
+++ b/arch/avr32/mach-at32ap/intc.c
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+
+#include <asm/io.h>
+
+#include "intc.h"
+
+struct intc {
+ void __iomem *regs;
+ struct irq_chip chip;
+};
+
+extern struct platform_device at32_intc0_device;
+
+/*
+ * TODO: We may be able to implement mask/unmask by setting IxM flags
+ * in the status register.
+ */
+static void intc_mask_irq(unsigned int irq)
+{
+
+}
+
+static void intc_unmask_irq(unsigned int irq)
+{
+
+}
+
+static struct intc intc0 = {
+ .chip = {
+ .name = "intc",
+ .mask = intc_mask_irq,
+ .unmask = intc_unmask_irq,
+ },
+};
+
+/*
+ * All interrupts go via intc at some point.
+ */
+asmlinkage void do_IRQ(int level, struct pt_regs *regs)
+{
+ struct irq_desc *desc;
+ unsigned int irq;
+ unsigned long status_reg;
+
+ local_irq_disable();
+
+ irq_enter();
+
+ irq = intc_readl(&intc0, INTCAUSE0 - 4 * level);
+ desc = irq_desc + irq;
+ desc->handle_irq(irq, desc, regs);
+
+ /*
+ * Clear all interrupt level masks so that we may handle
+ * interrupts during softirq processing. If this is a nested
+ * interrupt, interrupts must stay globally disabled until we
+ * return.
+ */
+ status_reg = sysreg_read(SR);
+ status_reg &= ~(SYSREG_BIT(I0M) | SYSREG_BIT(I1M)
+ | SYSREG_BIT(I2M) | SYSREG_BIT(I3M));
+ sysreg_write(SR, status_reg);
+
+ irq_exit();
+}
+
+void __init init_IRQ(void)
+{
+ extern void _evba(void);
+ extern void irq_level0(void);
+ struct resource *regs;
+ struct clk *pclk;
+ unsigned int i;
+ u32 offset, readback;
+
+ regs = platform_get_resource(&at32_intc0_device, IORESOURCE_MEM, 0);
+ if (!regs) {
+ printk(KERN_EMERG "intc: no mmio resource defined\n");
+ goto fail;
+ }
+ pclk = clk_get(&at32_intc0_device.dev, "pclk");
+ if (IS_ERR(pclk)) {
+ printk(KERN_EMERG "intc: no clock defined\n");
+ goto fail;
+ }
+
+ clk_enable(pclk);
+
+ intc0.regs = ioremap(regs->start, regs->end - regs->start + 1);
+ if (!intc0.regs) {
+ printk(KERN_EMERG "intc: failed to map registers (0x%08lx)\n",
+ (unsigned long)regs->start);
+ goto fail;
+ }
+
+ /*
+ * Initialize all interrupts to level 0 (lowest priority). The
+ * priority level may be changed by calling
+ * irq_set_priority().
+ *
+ */
+ offset = (unsigned long)&irq_level0 - (unsigned long)&_evba;
+ for (i = 0; i < NR_INTERNAL_IRQS; i++) {
+ intc_writel(&intc0, INTPR0 + 4 * i, offset);
+ readback = intc_readl(&intc0, INTPR0 + 4 * i);
+ if (readback == offset)
+ set_irq_chip_and_handler(i, &intc0.chip,
+ handle_simple_irq);
+ }
+
+ /* Unmask all interrupt levels */
+ sysreg_write(SR, (sysreg_read(SR)
+ & ~(SR_I3M | SR_I2M | SR_I1M | SR_I0M)));
+
+ return;
+
+fail:
+ panic("Interrupt controller initialization failed!\n");
+}
+
diff --git a/arch/avr32/mach-at32ap/intc.h b/arch/avr32/mach-at32ap/intc.h
new file mode 100644
index 0000000..d289ca2
--- /dev/null
+++ b/arch/avr32/mach-at32ap/intc.h
@@ -0,0 +1,327 @@
+/*
+ * Automatically generated by gen-header.xsl
+ */
+#ifndef __ASM_AVR32_PERIHP_INTC_H__
+#define __ASM_AVR32_PERIHP_INTC_H__
+
+#define INTC_NUM_INT_GRPS 33
+
+#define INTC_INTPR0 0x0
+# define INTC_INTPR0_INTLEV_OFFSET 30
+# define INTC_INTPR0_INTLEV_SIZE 2
+# define INTC_INTPR0_OFFSET_OFFSET 0
+# define INTC_INTPR0_OFFSET_SIZE 24
+#define INTC_INTREQ0 0x100
+# define INTC_INTREQ0_IREQUEST0_OFFSET 0
+# define INTC_INTREQ0_IREQUEST0_SIZE 1
+# define INTC_INTREQ0_IREQUEST1_OFFSET 1
+# define INTC_INTREQ0_IREQUEST1_SIZE 1
+#define INTC_INTPR1 0x4
+# define INTC_INTPR1_INTLEV_OFFSET 30
+# define INTC_INTPR1_INTLEV_SIZE 2
+# define INTC_INTPR1_OFFSET_OFFSET 0
+# define INTC_INTPR1_OFFSET_SIZE 24
+#define INTC_INTREQ1 0x104
+# define INTC_INTREQ1_IREQUEST32_OFFSET 0
+# define INTC_INTREQ1_IREQUEST32_SIZE 1
+# define INTC_INTREQ1_IREQUEST33_OFFSET 1
+# define INTC_INTREQ1_IREQUEST33_SIZE 1
+# define INTC_INTREQ1_IREQUEST34_OFFSET 2
+# define INTC_INTREQ1_IREQUEST34_SIZE 1
+# define INTC_INTREQ1_IREQUEST35_OFFSET 3
+# define INTC_INTREQ1_IREQUEST35_SIZE 1
+# define INTC_INTREQ1_IREQUEST36_OFFSET 4
+# define INTC_INTREQ1_IREQUEST36_SIZE 1
+# define INTC_INTREQ1_IREQUEST37_OFFSET 5
+# define INTC_INTREQ1_IREQUEST37_SIZE 1
+#define INTC_INTPR2 0x8
+# define INTC_INTPR2_INTLEV_OFFSET 30
+# define INTC_INTPR2_INTLEV_SIZE 2
+# define INTC_INTPR2_OFFSET_OFFSET 0
+# define INTC_INTPR2_OFFSET_SIZE 24
+#define INTC_INTREQ2 0x108
+# define INTC_INTREQ2_IREQUEST64_OFFSET 0
+# define INTC_INTREQ2_IREQUEST64_SIZE 1
+# define INTC_INTREQ2_IREQUEST65_OFFSET 1
+# define INTC_INTREQ2_IREQUEST65_SIZE 1
+# define INTC_INTREQ2_IREQUEST66_OFFSET 2
+# define INTC_INTREQ2_IREQUEST66_SIZE 1
+# define INTC_INTREQ2_IREQUEST67_OFFSET 3
+# define INTC_INTREQ2_IREQUEST67_SIZE 1
+# define INTC_INTREQ2_IREQUEST68_OFFSET 4
+# define INTC_INTREQ2_IREQUEST68_SIZE 1
+#define INTC_INTPR3 0xc
+# define INTC_INTPR3_INTLEV_OFFSET 30
+# define INTC_INTPR3_INTLEV_SIZE 2
+# define INTC_INTPR3_OFFSET_OFFSET 0
+# define INTC_INTPR3_OFFSET_SIZE 24
+#define INTC_INTREQ3 0x10c
+# define INTC_INTREQ3_IREQUEST96_OFFSET 0
+# define INTC_INTREQ3_IREQUEST96_SIZE 1
+#define INTC_INTPR4 0x10
+# define INTC_INTPR4_INTLEV_OFFSET 30
+# define INTC_INTPR4_INTLEV_SIZE 2
+# define INTC_INTPR4_OFFSET_OFFSET 0
+# define INTC_INTPR4_OFFSET_SIZE 24
+#define INTC_INTREQ4 0x110
+# define INTC_INTREQ4_IREQUEST128_OFFSET 0
+# define INTC_INTREQ4_IREQUEST128_SIZE 1
+#define INTC_INTPR5 0x14
+# define INTC_INTPR5_INTLEV_OFFSET 30
+# define INTC_INTPR5_INTLEV_SIZE 2
+# define INTC_INTPR5_OFFSET_OFFSET 0
+# define INTC_INTPR5_OFFSET_SIZE 24
+#define INTC_INTREQ5 0x114
+# define INTC_INTREQ5_IREQUEST160_OFFSET 0
+# define INTC_INTREQ5_IREQUEST160_SIZE 1
+#define INTC_INTPR6 0x18
+# define INTC_INTPR6_INTLEV_OFFSET 30
+# define INTC_INTPR6_INTLEV_SIZE 2
+# define INTC_INTPR6_OFFSET_OFFSET 0
+# define INTC_INTPR6_OFFSET_SIZE 24
+#define INTC_INTREQ6 0x118
+# define INTC_INTREQ6_IREQUEST192_OFFSET 0
+# define INTC_INTREQ6_IREQUEST192_SIZE 1
+#define INTC_INTPR7 0x1c
+# define INTC_INTPR7_INTLEV_OFFSET 30
+# define INTC_INTPR7_INTLEV_SIZE 2
+# define INTC_INTPR7_OFFSET_OFFSET 0
+# define INTC_INTPR7_OFFSET_SIZE 24
+#define INTC_INTREQ7 0x11c
+# define INTC_INTREQ7_IREQUEST224_OFFSET 0
+# define INTC_INTREQ7_IREQUEST224_SIZE 1
+#define INTC_INTPR8 0x20
+# define INTC_INTPR8_INTLEV_OFFSET 30
+# define INTC_INTPR8_INTLEV_SIZE 2
+# define INTC_INTPR8_OFFSET_OFFSET 0
+# define INTC_INTPR8_OFFSET_SIZE 24
+#define INTC_INTREQ8 0x120
+# define INTC_INTREQ8_IREQUEST256_OFFSET 0
+# define INTC_INTREQ8_IREQUEST256_SIZE 1
+#define INTC_INTPR9 0x24
+# define INTC_INTPR9_INTLEV_OFFSET 30
+# define INTC_INTPR9_INTLEV_SIZE 2
+# define INTC_INTPR9_OFFSET_OFFSET 0
+# define INTC_INTPR9_OFFSET_SIZE 24
+#define INTC_INTREQ9 0x124
+# define INTC_INTREQ9_IREQUEST288_OFFSET 0
+# define INTC_INTREQ9_IREQUEST288_SIZE 1
+#define INTC_INTPR10 0x28
+# define INTC_INTPR10_INTLEV_OFFSET 30
+# define INTC_INTPR10_INTLEV_SIZE 2
+# define INTC_INTPR10_OFFSET_OFFSET 0
+# define INTC_INTPR10_OFFSET_SIZE 24
+#define INTC_INTREQ10 0x128
+# define INTC_INTREQ10_IREQUEST320_OFFSET 0
+# define INTC_INTREQ10_IREQUEST320_SIZE 1
+#define INTC_INTPR11 0x2c
+# define INTC_INTPR11_INTLEV_OFFSET 30
+# define INTC_INTPR11_INTLEV_SIZE 2
+# define INTC_INTPR11_OFFSET_OFFSET 0
+# define INTC_INTPR11_OFFSET_SIZE 24
+#define INTC_INTREQ11 0x12c
+# define INTC_INTREQ11_IREQUEST352_OFFSET 0
+# define INTC_INTREQ11_IREQUEST352_SIZE 1
+#define INTC_INTPR12 0x30
+# define INTC_INTPR12_INTLEV_OFFSET 30
+# define INTC_INTPR12_INTLEV_SIZE 2
+# define INTC_INTPR12_OFFSET_OFFSET 0
+# define INTC_INTPR12_OFFSET_SIZE 24
+#define INTC_INTREQ12 0x130
+# define INTC_INTREQ12_IREQUEST384_OFFSET 0
+# define INTC_INTREQ12_IREQUEST384_SIZE 1
+#define INTC_INTPR13 0x34
+# define INTC_INTPR13_INTLEV_OFFSET 30
+# define INTC_INTPR13_INTLEV_SIZE 2
+# define INTC_INTPR13_OFFSET_OFFSET 0
+# define INTC_INTPR13_OFFSET_SIZE 24
+#define INTC_INTREQ13 0x134
+# define INTC_INTREQ13_IREQUEST416_OFFSET 0
+# define INTC_INTREQ13_IREQUEST416_SIZE 1
+#define INTC_INTPR14 0x38
+# define INTC_INTPR14_INTLEV_OFFSET 30
+# define INTC_INTPR14_INTLEV_SIZE 2
+# define INTC_INTPR14_OFFSET_OFFSET 0
+# define INTC_INTPR14_OFFSET_SIZE 24
+#define INTC_INTREQ14 0x138
+# define INTC_INTREQ14_IREQUEST448_OFFSET 0
+# define INTC_INTREQ14_IREQUEST448_SIZE 1
+#define INTC_INTPR15 0x3c
+# define INTC_INTPR15_INTLEV_OFFSET 30
+# define INTC_INTPR15_INTLEV_SIZE 2
+# define INTC_INTPR15_OFFSET_OFFSET 0
+# define INTC_INTPR15_OFFSET_SIZE 24
+#define INTC_INTREQ15 0x13c
+# define INTC_INTREQ15_IREQUEST480_OFFSET 0
+# define INTC_INTREQ15_IREQUEST480_SIZE 1
+#define INTC_INTPR16 0x40
+# define INTC_INTPR16_INTLEV_OFFSET 30
+# define INTC_INTPR16_INTLEV_SIZE 2
+# define INTC_INTPR16_OFFSET_OFFSET 0
+# define INTC_INTPR16_OFFSET_SIZE 24
+#define INTC_INTREQ16 0x140
+# define INTC_INTREQ16_IREQUEST512_OFFSET 0
+# define INTC_INTREQ16_IREQUEST512_SIZE 1
+#define INTC_INTPR17 0x44
+# define INTC_INTPR17_INTLEV_OFFSET 30
+# define INTC_INTPR17_INTLEV_SIZE 2
+# define INTC_INTPR17_OFFSET_OFFSET 0
+# define INTC_INTPR17_OFFSET_SIZE 24
+#define INTC_INTREQ17 0x144
+# define INTC_INTREQ17_IREQUEST544_OFFSET 0
+# define INTC_INTREQ17_IREQUEST544_SIZE 1
+#define INTC_INTPR18 0x48
+# define INTC_INTPR18_INTLEV_OFFSET 30
+# define INTC_INTPR18_INTLEV_SIZE 2
+# define INTC_INTPR18_OFFSET_OFFSET 0
+# define INTC_INTPR18_OFFSET_SIZE 24
+#define INTC_INTREQ18 0x148
+# define INTC_INTREQ18_IREQUEST576_OFFSET 0
+# define INTC_INTREQ18_IREQUEST576_SIZE 1
+#define INTC_INTPR19 0x4c
+# define INTC_INTPR19_INTLEV_OFFSET 30
+# define INTC_INTPR19_INTLEV_SIZE 2
+# define INTC_INTPR19_OFFSET_OFFSET 0
+# define INTC_INTPR19_OFFSET_SIZE 24
+#define INTC_INTREQ19 0x14c
+# define INTC_INTREQ19_IREQUEST608_OFFSET 0
+# define INTC_INTREQ19_IREQUEST608_SIZE 1
+# define INTC_INTREQ19_IREQUEST609_OFFSET 1
+# define INTC_INTREQ19_IREQUEST609_SIZE 1
+# define INTC_INTREQ19_IREQUEST610_OFFSET 2
+# define INTC_INTREQ19_IREQUEST610_SIZE 1
+# define INTC_INTREQ19_IREQUEST611_OFFSET 3
+# define INTC_INTREQ19_IREQUEST611_SIZE 1
+#define INTC_INTPR20 0x50
+# define INTC_INTPR20_INTLEV_OFFSET 30
+# define INTC_INTPR20_INTLEV_SIZE 2
+# define INTC_INTPR20_OFFSET_OFFSET 0
+# define INTC_INTPR20_OFFSET_SIZE 24
+#define INTC_INTREQ20 0x150
+# define INTC_INTREQ20_IREQUEST640_OFFSET 0
+# define INTC_INTREQ20_IREQUEST640_SIZE 1
+#define INTC_INTPR21 0x54
+# define INTC_INTPR21_INTLEV_OFFSET 30
+# define INTC_INTPR21_INTLEV_SIZE 2
+# define INTC_INTPR21_OFFSET_OFFSET 0
+# define INTC_INTPR21_OFFSET_SIZE 24
+#define INTC_INTREQ21 0x154
+# define INTC_INTREQ21_IREQUEST672_OFFSET 0
+# define INTC_INTREQ21_IREQUEST672_SIZE 1
+#define INTC_INTPR22 0x58
+# define INTC_INTPR22_INTLEV_OFFSET 30
+# define INTC_INTPR22_INTLEV_SIZE 2
+# define INTC_INTPR22_OFFSET_OFFSET 0
+# define INTC_INTPR22_OFFSET_SIZE 24
+#define INTC_INTREQ22 0x158
+# define INTC_INTREQ22_IREQUEST704_OFFSET 0
+# define INTC_INTREQ22_IREQUEST704_SIZE 1
+# define INTC_INTREQ22_IREQUEST705_OFFSET 1
+# define INTC_INTREQ22_IREQUEST705_SIZE 1
+# define INTC_INTREQ22_IREQUEST706_OFFSET 2
+# define INTC_INTREQ22_IREQUEST706_SIZE 1
+#define INTC_INTPR23 0x5c
+# define INTC_INTPR23_INTLEV_OFFSET 30
+# define INTC_INTPR23_INTLEV_SIZE 2
+# define INTC_INTPR23_OFFSET_OFFSET 0
+# define INTC_INTPR23_OFFSET_SIZE 24
+#define INTC_INTREQ23 0x15c
+# define INTC_INTREQ23_IREQUEST736_OFFSET 0
+# define INTC_INTREQ23_IREQUEST736_SIZE 1
+# define INTC_INTREQ23_IREQUEST737_OFFSET 1
+# define INTC_INTREQ23_IREQUEST737_SIZE 1
+# define INTC_INTREQ23_IREQUEST738_OFFSET 2
+# define INTC_INTREQ23_IREQUEST738_SIZE 1
+#define INTC_INTPR24 0x60
+# define INTC_INTPR24_INTLEV_OFFSET 30
+# define INTC_INTPR24_INTLEV_SIZE 2
+# define INTC_INTPR24_OFFSET_OFFSET 0
+# define INTC_INTPR24_OFFSET_SIZE 24
+#define INTC_INTREQ24 0x160
+# define INTC_INTREQ24_IREQUEST768_OFFSET 0
+# define INTC_INTREQ24_IREQUEST768_SIZE 1
+#define INTC_INTPR25 0x64
+# define INTC_INTPR25_INTLEV_OFFSET 30
+# define INTC_INTPR25_INTLEV_SIZE 2
+# define INTC_INTPR25_OFFSET_OFFSET 0
+# define INTC_INTPR25_OFFSET_SIZE 24
+#define INTC_INTREQ25 0x164
+# define INTC_INTREQ25_IREQUEST800_OFFSET 0
+# define INTC_INTREQ25_IREQUEST800_SIZE 1
+#define INTC_INTPR26 0x68
+# define INTC_INTPR26_INTLEV_OFFSET 30
+# define INTC_INTPR26_INTLEV_SIZE 2
+# define INTC_INTPR26_OFFSET_OFFSET 0
+# define INTC_INTPR26_OFFSET_SIZE 24
+#define INTC_INTREQ26 0x168
+# define INTC_INTREQ26_IREQUEST832_OFFSET 0
+# define INTC_INTREQ26_IREQUEST832_SIZE 1
+#define INTC_INTPR27 0x6c
+# define INTC_INTPR27_INTLEV_OFFSET 30
+# define INTC_INTPR27_INTLEV_SIZE 2
+# define INTC_INTPR27_OFFSET_OFFSET 0
+# define INTC_INTPR27_OFFSET_SIZE 24
+#define INTC_INTREQ27 0x16c
+# define INTC_INTREQ27_IREQUEST864_OFFSET 0
+# define INTC_INTREQ27_IREQUEST864_SIZE 1
+#define INTC_INTPR28 0x70
+# define INTC_INTPR28_INTLEV_OFFSET 30
+# define INTC_INTPR28_INTLEV_SIZE 2
+# define INTC_INTPR28_OFFSET_OFFSET 0
+# define INTC_INTPR28_OFFSET_SIZE 24
+#define INTC_INTREQ28 0x170
+# define INTC_INTREQ28_IREQUEST896_OFFSET 0
+# define INTC_INTREQ28_IREQUEST896_SIZE 1
+#define INTC_INTPR29 0x74
+# define INTC_INTPR29_INTLEV_OFFSET 30
+# define INTC_INTPR29_INTLEV_SIZE 2
+# define INTC_INTPR29_OFFSET_OFFSET 0
+# define INTC_INTPR29_OFFSET_SIZE 24
+#define INTC_INTREQ29 0x174
+# define INTC_INTREQ29_IREQUEST928_OFFSET 0
+# define INTC_INTREQ29_IREQUEST928_SIZE 1
+#define INTC_INTPR30 0x78
+# define INTC_INTPR30_INTLEV_OFFSET 30
+# define INTC_INTPR30_INTLEV_SIZE 2
+# define INTC_INTPR30_OFFSET_OFFSET 0
+# define INTC_INTPR30_OFFSET_SIZE 24
+#define INTC_INTREQ30 0x178
+# define INTC_INTREQ30_IREQUEST960_OFFSET 0
+# define INTC_INTREQ30_IREQUEST960_SIZE 1
+#define INTC_INTPR31 0x7c
+# define INTC_INTPR31_INTLEV_OFFSET 30
+# define INTC_INTPR31_INTLEV_SIZE 2
+# define INTC_INTPR31_OFFSET_OFFSET 0
+# define INTC_INTPR31_OFFSET_SIZE 24
+#define INTC_INTREQ31 0x17c
+# define INTC_INTREQ31_IREQUEST992_OFFSET 0
+# define INTC_INTREQ31_IREQUEST992_SIZE 1
+#define INTC_INTPR32 0x80
+# define INTC_INTPR32_INTLEV_OFFSET 30
+# define INTC_INTPR32_INTLEV_SIZE 2
+# define INTC_INTPR32_OFFSET_OFFSET 0
+# define INTC_INTPR32_OFFSET_SIZE 24
+#define INTC_INTREQ32 0x180
+# define INTC_INTREQ32_IREQUEST1024_OFFSET 0
+# define INTC_INTREQ32_IREQUEST1024_SIZE 1
+#define INTC_INTCAUSE0 0x20c
+# define INTC_INTCAUSE0_CAUSEGRP_OFFSET 0
+# define INTC_INTCAUSE0_CAUSEGRP_SIZE 6
+#define INTC_INTCAUSE1 0x208
+# define INTC_INTCAUSE1_CAUSEGRP_OFFSET 0
+# define INTC_INTCAUSE1_CAUSEGRP_SIZE 6
+#define INTC_INTCAUSE2 0x204
+# define INTC_INTCAUSE2_CAUSEGRP_OFFSET 0
+# define INTC_INTCAUSE2_CAUSEGRP_SIZE 6
+#define INTC_INTCAUSE3 0x200
+# define INTC_INTCAUSE3_CAUSEGRP_OFFSET 0
+# define INTC_INTCAUSE3_CAUSEGRP_SIZE 6
+
+#define INTC_BIT(name) (1 << INTC_##name##_OFFSET)
+#define INTC_MKBF(name, value) (((value) & ((1 << INTC_##name##_SIZE) - 1)) << INTC_##name##_OFFSET)
+#define INTC_GETBF(name, value) (((value) >> INTC_##name##_OFFSET) & ((1 << INTC_##name##_SIZE) - 1))
+
+#define intc_readl(port,reg) readl((port)->regs + INTC_##reg)
+#define intc_writel(port,reg,value) writel((value), (port)->regs + INTC_##reg)
+
+#endif /* __ASM_AVR32_PERIHP_INTC_H__ */
diff --git a/arch/avr32/mach-at32ap/pio.c b/arch/avr32/mach-at32ap/pio.c
new file mode 100644
index 0000000..d3aabfc
--- /dev/null
+++ b/arch/avr32/mach-at32ap/pio.c
@@ -0,0 +1,118 @@
+/*
+ * Atmel PIO2 Port Multiplexer support
+ *
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/fs.h>
+#include <linux/platform_device.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/portmux.h>
+
+#include "pio.h"
+
+#define MAX_NR_PIO_DEVICES 8
+
+struct pio_device {
+ void __iomem *regs;
+ const struct platform_device *pdev;
+ struct clk *clk;
+ u32 alloc_mask;
+ char name[32];
+};
+
+static struct pio_device pio_dev[MAX_NR_PIO_DEVICES];
+
+void portmux_set_func(unsigned int portmux_id, unsigned int pin_id,
+ unsigned int function_id)
+{
+ struct pio_device *pio;
+ u32 mask = 1 << pin_id;
+
+ BUG_ON(portmux_id >= MAX_NR_PIO_DEVICES);
+
+ pio = &pio_dev[portmux_id];
+
+ if (function_id)
+ pio_writel(pio, BSR, mask);
+ else
+ pio_writel(pio, ASR, mask);
+ pio_writel(pio, PDR, mask);
+}
+
+static int __init pio_probe(struct platform_device *pdev)
+{
+ struct pio_device *pio = NULL;
+
+ BUG_ON(pdev->id >= MAX_NR_PIO_DEVICES);
+ pio = &pio_dev[pdev->id];
+ BUG_ON(!pio->regs);
+
+ /* TODO: Interrupts */
+
+ platform_set_drvdata(pdev, pio);
+
+ printk(KERN_INFO "%s: Atmel Port Multiplexer at 0x%p (irq %d)\n",
+ pio->name, pio->regs, platform_get_irq(pdev, 0));
+
+ return 0;
+}
+
+static struct platform_driver pio_driver = {
+ .probe = pio_probe,
+ .driver = {
+ .name = "pio",
+ },
+};
+
+static int __init pio_init(void)
+{
+ return platform_driver_register(&pio_driver);
+}
+subsys_initcall(pio_init);
+
+void __init at32_init_pio(struct platform_device *pdev)
+{
+ struct resource *regs;
+ struct pio_device *pio;
+
+ if (pdev->id > MAX_NR_PIO_DEVICES) {
+ dev_err(&pdev->dev, "only %d PIO devices supported\n",
+ MAX_NR_PIO_DEVICES);
+ return;
+ }
+
+ pio = &pio_dev[pdev->id];
+ snprintf(pio->name, sizeof(pio->name), "pio%d", pdev->id);
+
+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!regs) {
+ dev_err(&pdev->dev, "no mmio resource defined\n");
+ return;
+ }
+
+ pio->clk = clk_get(&pdev->dev, "mck");
+ if (IS_ERR(pio->clk))
+ /*
+ * This is a fatal error, but if we continue we might
+ * be so lucky that we manage to initialize the
+ * console and display this message...
+ */
+ dev_err(&pdev->dev, "no mck clock defined\n");
+ else
+ clk_enable(pio->clk);
+
+ pio->pdev = pdev;
+ pio->regs = ioremap(regs->start, regs->end - regs->start + 1);
+
+ pio_writel(pio, ODR, ~0UL);
+ pio_writel(pio, PER, ~0UL);
+}
diff --git a/arch/avr32/mach-at32ap/pio.h b/arch/avr32/mach-at32ap/pio.h
new file mode 100644
index 0000000..cfea123
--- /dev/null
+++ b/arch/avr32/mach-at32ap/pio.h
@@ -0,0 +1,178 @@
+/*
+ * Atmel PIO2 Port Multiplexer support
+ *
+ * Copyright (C) 2004-2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ARCH_AVR32_AT32AP_PIO_H__
+#define __ARCH_AVR32_AT32AP_PIO_H__
+
+/* PIO register offsets */
+#define PIO_PER 0x0000
+#define PIO_PDR 0x0004
+#define PIO_PSR 0x0008
+#define PIO_OER 0x0010
+#define PIO_ODR 0x0014
+#define PIO_OSR 0x0018
+#define PIO_IFER 0x0020
+#define PIO_IFDR 0x0024
+#define PIO_ISFR 0x0028
+#define PIO_SODR 0x0030
+#define PIO_CODR 0x0034
+#define PIO_ODSR 0x0038
+#define PIO_PDSR 0x003c
+#define PIO_IER 0x0040
+#define PIO_IDR 0x0044
+#define PIO_IMR 0x0048
+#define PIO_ISR 0x004c
+#define PIO_MDER 0x0050
+#define PIO_MDDR 0x0054
+#define PIO_MDSR 0x0058
+#define PIO_PUDR 0x0060
+#define PIO_PUER 0x0064
+#define PIO_PUSR 0x0068
+#define PIO_ASR 0x0070
+#define PIO_BSR 0x0074
+#define PIO_ABSR 0x0078
+#define PIO_OWER 0x00a0
+#define PIO_OWDR 0x00a4
+#define PIO_OWSR 0x00a8
+
+/* Bitfields in PER */
+
+/* Bitfields in PDR */
+
+/* Bitfields in PSR */
+
+/* Bitfields in OER */
+
+/* Bitfields in ODR */
+
+/* Bitfields in OSR */
+
+/* Bitfields in IFER */
+
+/* Bitfields in IFDR */
+
+/* Bitfields in ISFR */
+
+/* Bitfields in SODR */
+
+/* Bitfields in CODR */
+
+/* Bitfields in ODSR */
+
+/* Bitfields in PDSR */
+
+/* Bitfields in IER */
+
+/* Bitfields in IDR */
+
+/* Bitfields in IMR */
+
+/* Bitfields in ISR */
+
+/* Bitfields in MDER */
+
+/* Bitfields in MDDR */
+
+/* Bitfields in MDSR */
+
+/* Bitfields in PUDR */
+
+/* Bitfields in PUER */
+
+/* Bitfields in PUSR */
+
+/* Bitfields in ASR */
+
+/* Bitfields in BSR */
+
+/* Bitfields in ABSR */
+#define PIO_P0_OFFSET 0
+#define PIO_P0_SIZE 1
+#define PIO_P1_OFFSET 1
+#define PIO_P1_SIZE 1
+#define PIO_P2_OFFSET 2
+#define PIO_P2_SIZE 1
+#define PIO_P3_OFFSET 3
+#define PIO_P3_SIZE 1
+#define PIO_P4_OFFSET 4
+#define PIO_P4_SIZE 1
+#define PIO_P5_OFFSET 5
+#define PIO_P5_SIZE 1
+#define PIO_P6_OFFSET 6
+#define PIO_P6_SIZE 1
+#define PIO_P7_OFFSET 7
+#define PIO_P7_SIZE 1
+#define PIO_P8_OFFSET 8
+#define PIO_P8_SIZE 1
+#define PIO_P9_OFFSET 9
+#define PIO_P9_SIZE 1
+#define PIO_P10_OFFSET 10
+#define PIO_P10_SIZE 1
+#define PIO_P11_OFFSET 11
+#define PIO_P11_SIZE 1
+#define PIO_P12_OFFSET 12
+#define PIO_P12_SIZE 1
+#define PIO_P13_OFFSET 13
+#define PIO_P13_SIZE 1
+#define PIO_P14_OFFSET 14
+#define PIO_P14_SIZE 1
+#define PIO_P15_OFFSET 15
+#define PIO_P15_SIZE 1
+#define PIO_P16_OFFSET 16
+#define PIO_P16_SIZE 1
+#define PIO_P17_OFFSET 17
+#define PIO_P17_SIZE 1
+#define PIO_P18_OFFSET 18
+#define PIO_P18_SIZE 1
+#define PIO_P19_OFFSET 19
+#define PIO_P19_SIZE 1
+#define PIO_P20_OFFSET 20
+#define PIO_P20_SIZE 1
+#define PIO_P21_OFFSET 21
+#define PIO_P21_SIZE 1
+#define PIO_P22_OFFSET 22
+#define PIO_P22_SIZE 1
+#define PIO_P23_OFFSET 23
+#define PIO_P23_SIZE 1
+#define PIO_P24_OFFSET 24
+#define PIO_P24_SIZE 1
+#define PIO_P25_OFFSET 25
+#define PIO_P25_SIZE 1
+#define PIO_P26_OFFSET 26
+#define PIO_P26_SIZE 1
+#define PIO_P27_OFFSET 27
+#define PIO_P27_SIZE 1
+#define PIO_P28_OFFSET 28
+#define PIO_P28_SIZE 1
+#define PIO_P29_OFFSET 29
+#define PIO_P29_SIZE 1
+#define PIO_P30_OFFSET 30
+#define PIO_P30_SIZE 1
+#define PIO_P31_OFFSET 31
+#define PIO_P31_SIZE 1
+
+/* Bitfields in OWER */
+
+/* Bitfields in OWDR */
+
+/* Bitfields in OWSR */
+
+/* Bit manipulation macros */
+#define PIO_BIT(name) (1 << PIO_##name##_OFFSET)
+#define PIO_BF(name,value) (((value) & ((1 << PIO_##name##_SIZE) - 1)) << PIO_##name##_OFFSET)
+#define PIO_BFEXT(name,value) (((value) >> PIO_##name##_OFFSET) & ((1 << PIO_##name##_SIZE) - 1))
+#define PIO_BFINS(name,value,old) (((old) & ~(((1 << PIO_##name##_SIZE) - 1) << PIO_##name##_OFFSET)) | PIO_BF(name,value))
+
+/* Register access macros */
+#define pio_readl(port,reg) readl((port)->regs + PIO_##reg)
+#define pio_writel(port,reg,value) writel((value), (port)->regs + PIO_##reg)
+
+void at32_init_pio(struct platform_device *pdev);
+
+#endif /* __ARCH_AVR32_AT32AP_PIO_H__ */
diff --git a/arch/avr32/mach-at32ap/sm.c b/arch/avr32/mach-at32ap/sm.c
new file mode 100644
index 0000000..03306eb
--- /dev/null
+++ b/arch/avr32/mach-at32ap/sm.c
@@ -0,0 +1,289 @@
+/*
+ * System Manager driver for AT32AP CPUs
+ *
+ * Copyright (C) 2006 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/random.h>
+#include <linux/spinlock.h>
+
+#include <asm/intc.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include <asm/arch/sm.h>
+
+#include "sm.h"
+
+#define SM_EIM_IRQ_RESOURCE 1
+#define SM_PM_IRQ_RESOURCE 2
+#define SM_RTC_IRQ_RESOURCE 3
+
+#define to_eim(irqc) container_of(irqc, struct at32_sm, irqc)
+
+struct at32_sm system_manager;
+
+int __init at32_sm_init(void)
+{
+ struct resource *regs;
+ struct at32_sm *sm = &system_manager;
+ int ret = -ENXIO;
+
+ regs = platform_get_resource(&at32_sm_device, IORESOURCE_MEM, 0);
+ if (!regs)
+ goto fail;
+
+ spin_lock_init(&sm->lock);
+ sm->pdev = &at32_sm_device;
+
+ ret = -ENOMEM;
+ sm->regs = ioremap(regs->start, regs->end - regs->start + 1);
+ if (!sm->regs)
+ goto fail;
+
+ return 0;
+
+fail:
+ printk(KERN_ERR "Failed to initialize System Manager: %d\n", ret);
+ return ret;
+}
+
+/*
+ * External Interrupt Module (EIM).
+ *
+ * EIM gets level- or edge-triggered interrupts of either polarity
+ * from the outside and converts it to active-high level-triggered
+ * interrupts that the internal interrupt controller can handle. EIM
+ * also provides masking/unmasking of interrupts, as well as
+ * acknowledging of edge-triggered interrupts.
+ */
+
+static irqreturn_t spurious_eim_interrupt(int irq, void *dev_id,
+ struct pt_regs *regs)
+{
+ printk(KERN_WARNING "Spurious EIM interrupt %d\n", irq);
+ disable_irq(irq);
+ return IRQ_NONE;
+}
+
+static struct irqaction eim_spurious_action = {
+ .handler = spurious_eim_interrupt,
+};
+
+static irqreturn_t eim_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct irq_controller * irqc = dev_id;
+ struct at32_sm *sm = to_eim(irqc);
+ unsigned long pending;
+
+ /*
+ * No need to disable interrupts globally. The interrupt
+ * level relevant to this group must be masked all the time,
+ * so we know that this particular EIM instance will not be
+ * re-entered.
+ */
+ spin_lock(&sm->lock);
+
+ pending = intc_get_pending(sm->irqc.irq_group);
+ if (unlikely(!pending)) {
+ printk(KERN_ERR "EIM (group %u): No interrupts pending!\n",
+ sm->irqc.irq_group);
+ goto unlock;
+ }
+
+ do {
+ struct irqaction *action;
+ unsigned int i;
+
+ i = fls(pending) - 1;
+ pending &= ~(1 << i);
+ action = sm->action[i];
+
+ /* Acknowledge the interrupt */
+ sm_writel(sm, EIM_ICR, 1 << i);
+
+ spin_unlock(&sm->lock);
+
+ if (action->flags & SA_INTERRUPT)
+ local_irq_disable();
+ action->handler(sm->irqc.first_irq + i, action->dev_id, regs);
+ local_irq_enable();
+ spin_lock(&sm->lock);
+ if (action->flags & SA_SAMPLE_RANDOM)
+ add_interrupt_randomness(sm->irqc.first_irq + i);
+ } while (pending);
+
+unlock:
+ spin_unlock(&sm->lock);
+ return IRQ_HANDLED;
+}
+
+static void eim_mask(struct irq_controller *irqc, unsigned int irq)
+{
+ struct at32_sm *sm = to_eim(irqc);
+ unsigned int i;
+
+ i = irq - sm->irqc.first_irq;
+ sm_writel(sm, EIM_IDR, 1 << i);
+}
+
+static void eim_unmask(struct irq_controller *irqc, unsigned int irq)
+{
+ struct at32_sm *sm = to_eim(irqc);
+ unsigned int i;
+
+ i = irq - sm->irqc.first_irq;
+ sm_writel(sm, EIM_IER, 1 << i);
+}
+
+static int eim_setup(struct irq_controller *irqc, unsigned int irq,
+ struct irqaction *action)
+{
+ struct at32_sm *sm = to_eim(irqc);
+ sm->action[irq - sm->irqc.first_irq] = action;
+ /* Acknowledge earlier interrupts */
+ sm_writel(sm, EIM_ICR, (1<<(irq - sm->irqc.first_irq)));
+ eim_unmask(irqc, irq);
+ return 0;
+}
+
+static void eim_free(struct irq_controller *irqc, unsigned int irq,
+ void *dev)
+{
+ struct at32_sm *sm = to_eim(irqc);
+ eim_mask(irqc, irq);
+ sm->action[irq - sm->irqc.first_irq] = &eim_spurious_action;
+}
+
+static int eim_set_type(struct irq_controller *irqc, unsigned int irq,
+ unsigned int type)
+{
+ struct at32_sm *sm = to_eim(irqc);
+ unsigned long flags;
+ u32 value, pattern;
+
+ spin_lock_irqsave(&sm->lock, flags);
+
+ pattern = 1 << (irq - sm->irqc.first_irq);
+
+ value = sm_readl(sm, EIM_MODE);
+ if (type & IRQ_TYPE_LEVEL)
+ value |= pattern;
+ else
+ value &= ~pattern;
+ sm_writel(sm, EIM_MODE, value);
+ value = sm_readl(sm, EIM_EDGE);
+ if (type & IRQ_EDGE_RISING)
+ value |= pattern;
+ else
+ value &= ~pattern;
+ sm_writel(sm, EIM_EDGE, value);
+ value = sm_readl(sm, EIM_LEVEL);
+ if (type & IRQ_LEVEL_HIGH)
+ value |= pattern;
+ else
+ value &= ~pattern;
+ sm_writel(sm, EIM_LEVEL, value);
+
+ spin_unlock_irqrestore(&sm->lock, flags);
+
+ return 0;
+}
+
+static unsigned int eim_get_type(struct irq_controller *irqc,
+ unsigned int irq)
+{
+ struct at32_sm *sm = to_eim(irqc);
+ unsigned long flags;
+ unsigned int type = 0;
+ u32 mode, edge, level, pattern;
+
+ pattern = 1 << (irq - sm->irqc.first_irq);
+
+ spin_lock_irqsave(&sm->lock, flags);
+ mode = sm_readl(sm, EIM_MODE);
+ edge = sm_readl(sm, EIM_EDGE);
+ level = sm_readl(sm, EIM_LEVEL);
+ spin_unlock_irqrestore(&sm->lock, flags);
+
+ if (mode & pattern)
+ type |= IRQ_TYPE_LEVEL;
+ if (edge & pattern)
+ type |= IRQ_EDGE_RISING;
+ if (level & pattern)
+ type |= IRQ_LEVEL_HIGH;
+
+ return type;
+}
+
+static struct irq_controller_class eim_irq_class = {
+ .typename = "EIM",
+ .handle = eim_handle_irq,
+ .setup = eim_setup,
+ .free = eim_free,
+ .mask = eim_mask,
+ .unmask = eim_unmask,
+ .set_type = eim_set_type,
+ .get_type = eim_get_type,
+};
+
+static int __init eim_init(void)
+{
+ struct at32_sm *sm = &system_manager;
+ unsigned int i;
+ u32 pattern;
+ int ret;
+
+ /*
+ * The EIM is really the same module as SM, so register
+ * mapping, etc. has been taken care of already.
+ */
+
+ /*
+ * Find out how many interrupt lines that are actually
+ * implemented in hardware.
+ */
+ sm_writel(sm, EIM_IDR, ~0UL);
+ sm_writel(sm, EIM_MODE, ~0UL);
+ pattern = sm_readl(sm, EIM_MODE);
+ sm->irqc.nr_irqs = fls(pattern);
+
+ ret = -ENOMEM;
+ sm->action = kmalloc(sizeof(*sm->action) * sm->irqc.nr_irqs,
+ GFP_KERNEL);
+ if (!sm->action)
+ goto out;
+
+ for (i = 0; i < sm->irqc.nr_irqs; i++)
+ sm->action[i] = &eim_spurious_action;
+
+ spin_lock_init(&sm->lock);
+ sm->irqc.irq_group = sm->pdev->resource[SM_EIM_IRQ_RESOURCE].start;
+ sm->irqc.class = &eim_irq_class;
+
+ ret = intc_register_controller(&sm->irqc);
+ if (ret < 0)
+ goto out_free_actions;
+
+ printk("EIM: External Interrupt Module at 0x%p, IRQ group %u\n",
+ sm->regs, sm->irqc.irq_group);
+ printk("EIM: Handling %u external IRQs, starting with IRQ%u\n",
+ sm->irqc.nr_irqs, sm->irqc.first_irq);
+
+ return 0;
+
+out_free_actions:
+ kfree(sm->action);
+out:
+ return ret;
+}
+arch_initcall(eim_init);
diff --git a/arch/avr32/mach-at32ap/sm.h b/arch/avr32/mach-at32ap/sm.h
new file mode 100644
index 0000000..2756582
--- /dev/null
+++ b/arch/avr32/mach-at32ap/sm.h
@@ -0,0 +1,240 @@
+/*
+ * Register definitions for SM
+ *
+ * System Manager
+ */
+#ifndef __ASM_AVR32_SM_H__
+#define __ASM_AVR32_SM_H__
+
+/* SM register offsets */
+#define SM_PM_MCCTRL 0x0000
+#define SM_PM_CKSEL 0x0004
+#define SM_PM_CPU_MASK 0x0008
+#define SM_PM_HSB_MASK 0x000c
+#define SM_PM_PBA_MASK 0x0010
+#define SM_PM_PBB_MASK 0x0014
+#define SM_PM_PLL0 0x0020
+#define SM_PM_PLL1 0x0024
+#define SM_PM_VCTRL 0x0030
+#define SM_PM_VMREF 0x0034
+#define SM_PM_VMV 0x0038
+#define SM_PM_IER 0x0040
+#define SM_PM_IDR 0x0044
+#define SM_PM_IMR 0x0048
+#define SM_PM_ISR 0x004c
+#define SM_PM_ICR 0x0050
+#define SM_PM_GCCTRL 0x0060
+#define SM_RTC_CTRL 0x0080
+#define SM_RTC_VAL 0x0084
+#define SM_RTC_TOP 0x0088
+#define SM_RTC_IER 0x0090
+#define SM_RTC_IDR 0x0094
+#define SM_RTC_IMR 0x0098
+#define SM_RTC_ISR 0x009c
+#define SM_RTC_ICR 0x00a0
+#define SM_WDT_CTRL 0x00b0
+#define SM_WDT_CLR 0x00b4
+#define SM_WDT_EXT 0x00b8
+#define SM_RC_RCAUSE 0x00c0
+#define SM_EIM_IER 0x0100
+#define SM_EIM_IDR 0x0104
+#define SM_EIM_IMR 0x0108
+#define SM_EIM_ISR 0x010c
+#define SM_EIM_ICR 0x0110
+#define SM_EIM_MODE 0x0114
+#define SM_EIM_EDGE 0x0118
+#define SM_EIM_LEVEL 0x011c
+#define SM_EIM_TEST 0x0120
+#define SM_EIM_NMIC 0x0124
+
+/* Bitfields in PM_MCCTRL */
+
+/* Bitfields in PM_CKSEL */
+#define SM_CPUSEL_OFFSET 0
+#define SM_CPUSEL_SIZE 3
+#define SM_CPUDIV_OFFSET 7
+#define SM_CPUDIV_SIZE 1
+#define SM_HSBSEL_OFFSET 8
+#define SM_HSBSEL_SIZE 3
+#define SM_HSBDIV_OFFSET 15
+#define SM_HSBDIV_SIZE 1
+#define SM_PBASEL_OFFSET 16
+#define SM_PBASEL_SIZE 3
+#define SM_PBADIV_OFFSET 23
+#define SM_PBADIV_SIZE 1
+#define SM_PBBSEL_OFFSET 24
+#define SM_PBBSEL_SIZE 3
+#define SM_PBBDIV_OFFSET 31
+#define SM_PBBDIV_SIZE 1
+
+/* Bitfields in PM_CPU_MASK */
+
+/* Bitfields in PM_HSB_MASK */
+
+/* Bitfields in PM_PBA_MASK */
+
+/* Bitfields in PM_PBB_MASK */
+
+/* Bitfields in PM_PLL0 */
+#define SM_PLLEN_OFFSET 0
+#define SM_PLLEN_SIZE 1
+#define SM_PLLOSC_OFFSET 1
+#define SM_PLLOSC_SIZE 1
+#define SM_PLLOPT_OFFSET 2
+#define SM_PLLOPT_SIZE 3
+#define SM_PLLDIV_OFFSET 8
+#define SM_PLLDIV_SIZE 8
+#define SM_PLLMUL_OFFSET 16
+#define SM_PLLMUL_SIZE 8
+#define SM_PLLCOUNT_OFFSET 24
+#define SM_PLLCOUNT_SIZE 6
+#define SM_PLLTEST_OFFSET 31
+#define SM_PLLTEST_SIZE 1
+
+/* Bitfields in PM_PLL1 */
+
+/* Bitfields in PM_VCTRL */
+#define SM_VAUTO_OFFSET 0
+#define SM_VAUTO_SIZE 1
+#define SM_PM_VCTRL_VAL_OFFSET 8
+#define SM_PM_VCTRL_VAL_SIZE 7
+
+/* Bitfields in PM_VMREF */
+#define SM_REFSEL_OFFSET 0
+#define SM_REFSEL_SIZE 4
+
+/* Bitfields in PM_VMV */
+#define SM_PM_VMV_VAL_OFFSET 0
+#define SM_PM_VMV_VAL_SIZE 8
+
+/* Bitfields in PM_IER */
+
+/* Bitfields in PM_IDR */
+
+/* Bitfields in PM_IMR */
+
+/* Bitfields in PM_ISR */
+
+/* Bitfields in PM_ICR */
+#define SM_LOCK0_OFFSET 0
+#define SM_LOCK0_SIZE 1
+#define SM_LOCK1_OFFSET 1
+#define SM_LOCK1_SIZE 1
+#define SM_WAKE_OFFSET 2
+#define SM_WAKE_SIZE 1
+#define SM_VOK_OFFSET 3
+#define SM_VOK_SIZE 1
+#define SM_VMRDY_OFFSET 4
+#define SM_VMRDY_SIZE 1
+#define SM_CKRDY_OFFSET 5
+#define SM_CKRDY_SIZE 1
+
+/* Bitfields in PM_GCCTRL */
+#define SM_OSCSEL_OFFSET 0
+#define SM_OSCSEL_SIZE 1
+#define SM_PLLSEL_OFFSET 1
+#define SM_PLLSEL_SIZE 1
+#define SM_CEN_OFFSET 2
+#define SM_CEN_SIZE 1
+#define SM_CPC_OFFSET 3
+#define SM_CPC_SIZE 1
+#define SM_DIVEN_OFFSET 4
+#define SM_DIVEN_SIZE 1
+#define SM_DIV_OFFSET 8
+#define SM_DIV_SIZE 8
+
+/* Bitfields in RTC_CTRL */
+#define SM_PCLR_OFFSET 1
+#define SM_PCLR_SIZE 1
+#define SM_TOPEN_OFFSET 2
+#define SM_TOPEN_SIZE 1
+#define SM_CLKEN_OFFSET 3
+#define SM_CLKEN_SIZE 1
+#define SM_PSEL_OFFSET 8
+#define SM_PSEL_SIZE 16
+
+/* Bitfields in RTC_VAL */
+#define SM_RTC_VAL_VAL_OFFSET 0
+#define SM_RTC_VAL_VAL_SIZE 31
+
+/* Bitfields in RTC_TOP */
+#define SM_RTC_TOP_VAL_OFFSET 0
+#define SM_RTC_TOP_VAL_SIZE 32
+
+/* Bitfields in RTC_IER */
+
+/* Bitfields in RTC_IDR */
+
+/* Bitfields in RTC_IMR */
+
+/* Bitfields in RTC_ISR */
+
+/* Bitfields in RTC_ICR */
+#define SM_TOPI_OFFSET 0
+#define SM_TOPI_SIZE 1
+
+/* Bitfields in WDT_CTRL */
+#define SM_KEY_OFFSET 24
+#define SM_KEY_SIZE 8
+
+/* Bitfields in WDT_CLR */
+
+/* Bitfields in WDT_EXT */
+
+/* Bitfields in RC_RCAUSE */
+#define SM_POR_OFFSET 0
+#define SM_POR_SIZE 1
+#define SM_BOD_OFFSET 1
+#define SM_BOD_SIZE 1
+#define SM_EXT_OFFSET 2
+#define SM_EXT_SIZE 1
+#define SM_WDT_OFFSET 3
+#define SM_WDT_SIZE 1
+#define SM_NTAE_OFFSET 4
+#define SM_NTAE_SIZE 1
+#define SM_SERP_OFFSET 5
+#define SM_SERP_SIZE 1
+
+/* Bitfields in EIM_IER */
+
+/* Bitfields in EIM_IDR */
+
+/* Bitfields in EIM_IMR */
+
+/* Bitfields in EIM_ISR */
+
+/* Bitfields in EIM_ICR */
+
+/* Bitfields in EIM_MODE */
+
+/* Bitfields in EIM_EDGE */
+#define SM_INT0_OFFSET 0
+#define SM_INT0_SIZE 1
+#define SM_INT1_OFFSET 1
+#define SM_INT1_SIZE 1
+#define SM_INT2_OFFSET 2
+#define SM_INT2_SIZE 1
+#define SM_INT3_OFFSET 3
+#define SM_INT3_SIZE 1
+
+/* Bitfields in EIM_LEVEL */
+
+/* Bitfields in EIM_TEST */
+#define SM_TESTEN_OFFSET 31
+#define SM_TESTEN_SIZE 1
+
+/* Bitfields in EIM_NMIC */
+#define SM_EN_OFFSET 0
+#define SM_EN_SIZE 1
+
+/* Bit manipulation macros */
+#define SM_BIT(name) (1 << SM_##name##_OFFSET)
+#define SM_BF(name,value) (((value) & ((1 << SM_##name##_SIZE) - 1)) << SM_##name##_OFFSET)
+#define SM_BFEXT(name,value) (((value) >> SM_##name##_OFFSET) & ((1 << SM_##name##_SIZE) - 1))
+#define SM_BFINS(name,value,old) (((old) & ~(((1 << SM_##name##_SIZE) - 1) << SM_##name##_OFFSET)) | SM_BF(name,value))
+
+/* Register access macros */
+#define sm_readl(port,reg) readl((port)->regs + SM_##reg)
+#define sm_writel(port,reg,value) writel((value), (port)->regs + SM_##reg)
+
+#endif /* __ASM_AVR32_SM_H__ */
generated by cgit v1.1 at 2024-12-28 07:10:05 +0000