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| * [SPARC64]: Export _PAGE_E and _PAGE_CACHE to modules.David S. Miller2006-03-201-0/+4
| | | | | | | | | | | | | | | | SBUS flash driver needs it. Noticed by Fabbione. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix %tstate ASI handling in start_thread{,32}()David S. Miller2006-03-201-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Niagara helps us find a ancient bug in the sparc64 port :-) The ASI_* values are plain constant defines, thus signed 32-bit on sparc64. To put shift this into the regs->tstate value we were doing or'ing "(ASI_PNF << 24)" into there. ASI_PNF is 0x82 and shifted left by 24 makes that topmost bit the sign bit in a 32-bit value. This would get sign extended to 64-bits and thus corrupt the top-half of the reg->tstate value. This never caused problems in pre-Niagara cpus because the only thing up there were the condition code values. But Niagara has the global register level field, and this all 1's value is illegal there so Niagara gives an illegal instruction trap due to this bug. I'm pretty sure this bug is about as old as the sparc64 port itself. This also points out that we weren't setting ASI_PNF for 32-bit tasks. We should, so fix that while we're here. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Drop %gl to 0 before re-enabling PSTATE_IE in rtrapDavid S. Miller2006-03-201-1/+2
| | | | | | | | | | | | | | | | If we take a window fault, on SUN4V set %gl to zero before we turn PSTATE_IE back on in %pstate. Otherwise if we take an interrupt we'll end up with corrupt register state. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Create a seperate kernel TSB for 4MB/256MB mappings.David S. Miller2006-03-203-6/+48
| | | | | | | | | | | | | | | | | | | | It can map all of the linear kernel mappings with zero TSB hash conflicts for systems with 16GB or less ram. In such cases, on SUN4V, once we load up this TSB the first time with all the mappings, we never take a linear kernel mapping TLB miss ever again, the hypervisor handles them all. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Make use of Niagara 256MB PTEs for kernel mappings.David S. Miller2006-03-202-15/+96
| | | | | | | | | | | | | | | | | | | | | | We use a bitmap, one bit for every 256MB of memory. If the bit is set we can use a 256MB PTE for linear mappings, else we have to use a 4MB PTE. SUN4V support is there, and we can very easily add support for Panther cpu 256MB PTEs in the future. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Use sun4v_cpu_idle() in cpu_idle() on SUN4V.David S. Miller2006-03-201-49/+32
| | | | | | | | | | | | | | | | | | | | | | We have to turn off the "polling nrflag" bit when we sleep the cpu like this, so that we'll get a cross-cpu interrupt to wake the processor up from the yield. We also have to disable PSTATE_IE in %pstate around the yield call and recheck need_resched() in order to avoid any races. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64] math-emu: Delete debugging printk left by previous commit.David S. Miller2006-03-201-1/+0
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Add sun4v_cpu_yield().David S. Miller2006-03-202-0/+12
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Kill cpudata->idle_volume.David S. Miller2006-03-203-11/+3
| | | | | | | | | | | | | | | | | | Set, but never used. We used to use this for dynamic IRQ retargetting, but that code died a long time ago. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Niagara optimized memset/bzero/clear_user.David S. Miller2006-03-203-1/+165
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Pass multiple CPUs at once to hypervisor cross-call API.David S. Miller2006-03-201-54/+0
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Args to SUNW,set-trap-table are 64-bit.David S. Miller2006-03-201-2/+7
| | | | | | | | | | | | | | | | They were getting truncated to 32-bit and this is very bad when your MMU fault status area is in physical memory above 4GB on SUN4V. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Handle unimplemented FPU square-root on Niagara.David S. Miller2006-03-201-2/+23
| | | | | | | | | | | | | | | | The math-emu code only expects unfinished fpop traps when emulating FPU sqrt instructions on pre-Niagara chips. On Niagara we can get unimplemented fpop, so handle that. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC] serial: Make sure sysfs nodes get named correctly.David S. Miller2006-03-204-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Because we play this trick where we use ttyS? in increasing minor numbers for different sunfoo.c drivers, we have to inform the TTY layer of this. Do so by setting the tty->name_base appropriately. Probably there should be a generic way to do this in the serial core, but for now... Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Typo in sun4v_data_access_exception log message.David S. Miller2006-03-201-1/+1
| | | | | | | | | | | | Should be "Dax" not "Iax". Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Handle zero-length map requests in pci_sun4v.cDavid S. Miller2006-03-201-2/+2
| | | | | | | | | | | | | | By simply changing the do-while loop into a plain while loop. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Kill stray PGLIST_NENTS check in pci_sun4v.cDavid S. Miller2006-03-201-2/+0
| | | | | | | | | | | | | | I forgot to remove the one in pci_4v_map_sg() during the iommu batching commit. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix typo in dump_tl1_traplog()David S. Miller2006-03-201-1/+1
| | | | | | | | | | | | Actually make use of the 'limit' we compute. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Disable smp_report_regs() for now.David S. Miller2006-03-201-1/+2
| | | | | | | | | | | | | | | | | | | | It's extremely noisy and causes much grief on slow consoles with large numbers of cpus. We'll have to provide this some saner way in order to re-enable this. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Remove PGLIST_NENTS PCI IOMMU mapping limitation on SUN4V.David S. Miller2006-03-203-83/+171
| | | | | | | | | | | | | | Use a batching queue system for IOMMU mapping setup, with a page sized batch. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Use KERN_EMERG in dump_tl1_traplog() and sun4v TLB errors.David S. Miller2006-03-201-7/+13
| | | | | | | | | | | | | | We're about to seriously die in these cases so it is important that the messages make it to the console. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix unaligned access winfxup handling on SUN4V.David S. Miller2006-03-202-17/+34
| | | | | | | | | | | | | | | | | | | | | | Another case where we have to force ourselves into global register level one. Also make sure the arguments passed to sun4v_do_mna() are correct. This area actually needs some more work, for example spill fixup is not necessarily going to do the right thing for this case. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Set %gl to 1 in kvmap_itlb_longpath on SUN4V.David S. Miller2006-03-201-1/+1
| | | | | | | | | | | | | | | | Just like kvmap_dtlb_longpath we have to force the global register level to one in order to mimick the PSTATE_MG --> PSTATE_AG trasition done on SUN4U. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64] sunhv: Fix locking in sunhv_start_tx()David S. Miller2006-03-201-6/+2
| | | | | | | | | | | | | | | | | | | | Caller takes the lock already. Also, fixup the poll loop in sunhv_break_ctl(). Just like in console write, we udelay(2) and use a loop limit of 1000000 iterations. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Put sunhv.o earliest in the list of sparc serial drivers.David S. Miller2006-03-201-1/+1
| | | | | | | | | | | | | | | | So that it will show up as /dev/ttyS0. Otherwise things like installers will try to run on whatever serial port gets probed first. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Export a PAGE_SHARED symbol.David S. Miller2006-03-202-0/+6
| | | | | | | | | | | | For drivers/media/*, noticed by Fabbione. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64] Fix build if CONFIG_HUGETLB_PAGE is not setFabio M. Di Nitto2006-03-201-0/+2
| | | | | | | | | | Signed-off-by: Fabio M. Di Nitto <fabbione@ubuntu.com> Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: More TLB/TSB handling fixes.David S. Miller2006-03-209-57/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SUN4V convention with non-shared TSBs is that the context bit of the TAG is clear. So we have to choose an "invalid" bit and initialize new TSBs appropriately. Otherwise a zero TAG looks "valid". Make sure, for the window fixup cases, that we use the right global registers and that we don't potentially trample on the live global registers in etrap/rtrap handling (%g2 and %g6) and that we put the missing virtual address properly in %g5. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Don't do anything in flush_ptrace_access() on SUN4V.David S. Miller2006-03-201-0/+3
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix some SUN4V TLB handling bugs.David S. Miller2006-03-203-5/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | 1) Add error return checking for TLB load hypervisor calls. 2) Don't fallthru to dtlb tsb miss handler from itlb tsb miss handler, oops. 3) On window fixups, propagate fault information to fixup handler correctly. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Check for errors in hypervisor_tlb_lock().David S. Miller2006-03-201-0/+5
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Init boot cpu's trap_block[] before paging_init()David S. Miller2006-03-201-2/+2
| | | | | | | | | | | | It must be ready when we take over the trap table. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Define ARCH_HAS_READ_CURRENT_TIMER.David S. Miller2006-03-203-18/+15
| | | | | | | | | | | | | | This gives more consistent bogomips and delay() semantics, especially on sun4v. It gives weird looking values though... Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Set associativity of kernel TSB descriptor correctly.David S. Miller2006-03-201-1/+1
| | | | | | | | | | | | It should be 1, not 0. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: __bzero_noasi --> __clear_userDavid S. Miller2006-03-203-18/+11
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Put SUN4V ITSB miss into correct trap table entry.David S. Miller2006-03-201-6/+4
| | | | | | | | | | | | It's 0x9 not 0xb. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Add HWCAP_SPARC_BLKINIT elf capability flag for Niagara.David S. Miller2006-03-201-5/+17
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Use phys tsb address in tsb_insert() in SUN4V.David S. Miller2006-03-201-1/+1
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix uniprocessor IRQ targetting on SUN4V.David S. Miller2006-03-205-59/+58
| | | | | | | | | | | | | | | | | | | | | | We need to use the real hardware processor ID when targetting interrupts, not the "define to 0" thing the uniprocessor build gives us. Also, fill in the Node-ID and Agent-ID fields properly on sun4u/Safari. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix PCI IRQ probing regression.David S. Miller2006-03-201-5/+5
| | | | | | | | | | | | | | | | If the top-level cnode had multi entries in it's "reg" property, we'd fail. The buffer wasn't large enough in such cases. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Get SUN4V SMP working.David S. Miller2006-03-206-51/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sibling cpu bringup is extremely fragile. We can only perform the most basic calls until we take over the trap table from the firmware/hypervisor on the new cpu. This means no accesses to %g4, %g5, %g6 since those can't be TLB translated without our trap handlers. In order to achieve this: 1) Change sun4v_init_mondo_queues() so that it can operate in several modes. It can allocate the queues, or install them in the current processor, or both. The boot cpu does both in it's call early on. Later, the boot cpu allocates the sibling cpu queue, starts the sibling cpu, then the sibling cpu loads them in. 2) init_cur_cpu_trap() is changed to take the current_thread_info() as an argument instead of reading %g6 directly on the current cpu. 3) Create a trampoline stack for the sibling cpus. We do our basic kernel calls using this stack, which is locked into the kernel image, then go to our proper thread stack after taking over the trap table. 4) While we are in this delicate startup state, we put 0xdeadbeef into %g4/%g5/%g6 in order to catch accidental accesses. 5) On the final prom_set_trap_table*() call, we put &init_thread_union into %g6. This is a hack to make prom_world(0) work. All that wants to do is restore the %asi register using get_thread_current_ds(). Longer term we should just do the OBP calls to set the trap table by hand just like we do for everything else. This would avoid that silly prom_world(0) issue, then we can remove the init_thread_union hack. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Disable smp_report_regs() for now.David S. Miller2006-03-201-0/+2
| | | | | | | | | | | | | | For 32 cpus and a slow console, it just wedges the machine especially with DETECT_SOFTLOCKUP enabled. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Rewrite pci_intmap_match().David S. Miller2006-03-201-114/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The whole algorithm was wrong. What we need to do is: 1) Walk each PCI bus above this device on the path to the PCI controller nexus, and for each: a) If interrupt-map exists, apply it, record IRQ controller node b) Else, swivel interrupt number using PCI_SLOT(), use PCI bus parent OBP node as controller node c) Walk up to "controller node" until we hit the first PCI bus in this domain, or "controller node" is the PCI controller OBP node 2) If we walked to PCI controller OBP node, we're done. 3) Else, apply PCI controller interrupt-map to interrupt. There is some stuff that needs to be checked out for ebus and isa, but the PCI part is good to go. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Don't set interrupt state to IDLE in enable_irq().David S. Miller2006-03-201-4/+0
| | | | | | | | | | | | We'll lose events that way. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix return from trap on SUN4V.David S. Miller2006-03-201-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | We need to set the global register set _AND_ disable PSTATE_IE in %pstate. The original patch sequence was leaving PSTATE_IE enabled when returning to kernel mode, oops. This fixes the random register corruption being seen on SUN4V. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Add GET_GL_GLOBAL() macro for SUN4V.David S. Miller2006-03-201-0/+4
| | | | | | | | | | | | So we can read the %gl register for debugging. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Set dummy bucket->{imap,iclr} unique on SUN4V.David S. Miller2006-03-201-5/+10
| | | | | | | | | | | | So that free_irq() disable's the IRQ correctly. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Add sun4v_cpu_qconf() hypervisor call.David S. Miller2006-03-203-19/+25
| | | | | | | | | | | | Call it from register_one_mondo(). Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC]: Kill off these __put_user_ret things.David S. Miller2006-03-202-84/+0
| | | | | | | | | | | | They are bogus and haven't been referenced in years. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: do_fptrap needs to load the thread reg into %g6.David S. Miller2006-03-201-0/+1
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
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