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* OMAP: PM: Hook into PM countersPeter 'p2' De Schrijver2009-09-021-0/+2
| | | | | | | | | This patch modifies the clock, clockdomain and OMAP3 specific powerdomain code to call the PM counter infrastructure whenever one or more powerdomains might have changed state. Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* OMAP2/3 clock: split, rename omap2_wait_clock_ready()Paul Walmsley2009-07-241-77/+79
| | | | | | | | | | | | | | | | | | | | | | Some OMAP2/3 hardware modules have CM_IDLEST attributes that are not handled by the current omap2_wait_clock_ready() code. In preparation for patches that fix the unusual devices, rename the function omap2_wait_clock_ready() to omap2_wait_module_ready() and split it into three parts: 1. A clkops-specific companion clock return function (by default, omap2_clk_dflt_find_companion()) 2. A clkops-specific CM_IDLEST register address and bit shift return function (by default, omap2_clk_dflt_find_idlest()) 3. Code to wait for the CM to indicate that the module is ready (omap2_cm_wait_idlest()) Clocks can now specify their own custom find_companion() and find_idlest() functions; used in subsequent patches. Signed-off-by: Paul Walmsley <paul@pwsan.com>
* OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisonsRoel Kluin2009-06-191-1/+1
| | | | | | | | with while (i++ < MAX_CLOCK_ENABLE_WAIT); i can reach MAX_CLOCK_ENABLE_WAIT + 1 after the loop, so if (i == MAX_CLOCK_ENABLE_WAIT) that's still success. Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* Merge branch 'omap-clock-upstream' of git://git.pwsan.com/linux-2.6 into ↵Tony Lindgren2009-05-261-7/+7
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| * OMAP3 clock: lessen amount of noisy messagesArtem Bityutskiy2009-05-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On our system we see the following messages: Disabling unused clock "gpt2_ick" Disabling unused clock "gpt3_ick" Disabling unused clock "gpt4_ick" Disabling unused clock "gpt5_ick" ... The messages have KERN_INFO level and if you have serial console, they normally go there. I do not think it is good idea to print that much stuff there. Moreover, messages are not properly prefixed and for mortals it is not immeadietly clear where they come from. Let's give them debugging level instead. Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: trimmed debugging output in patch description]
| * OMAP3 clock: use pr_debug() rather than pr_info() in some clock change codePaul Walmsley2009-05-121-6/+6
| | | | | | | | | | | | | | | | | | The CORE DPLL M2 frequency change code should use pr_debug(), not pr_info(), for its debug messages. Same with omap2_clksel_round_rate_div(). While here, convert a few printk(KERN_ERR .. into pr_err(). Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | ARM: OMAP2/3: Remove OMAP_PRM_REGADDR and OMAP2_PRM_BASETony Lindgren2009-05-251-2/+2
|/ | | | | | | | | | | | | Remove OMAP_PRM_REGADDR and use processor specific defines instead. Also fold in a patch from Kevin Hilman to add _OFFSET #defines for the PRCM registers to be used with the prm_[read|write]_* macros. These are used extensively in the forthcoming OMAP PM support. Also remove now unused OMAP2_PRM_BASE. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge branch 'omap-clks3' into develRussell King2009-03-191-216/+283
|\ | | | | | | | | | | Conflicts: arch/arm/mach-omap2/clock.c
| * [ARM] omap: clk_set_parent: deny changing parent if clock is enabledRussell King2009-03-031-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Richard Woodruff writes: | The historic usage of this has been against single use leaf clocks | (1st instance of gptimer). When it was used it did: | clk_get() | clk_set_parent() | clk_enable() | | This usage was ok for that. Use on a disabled clock is needed. | | If there are multiple users on the clock or it is enabled there are | problems. | | The call can still be unfriendly if 2 different drivers are using the | clock with their own clock get/enable. It might be the function should | return an error if usecount != 0 to stop surprises. It is all around | better if the parenting is done when the clock is off. This is a good reason to ensure that the clock is not enabled when clk_set_parent() is called. Acked-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] omap: add support for bypassing DPLLsRussell King2009-02-191-10/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This roughly corresponds with OMAP commits: 7d06c48, 3241b19, 88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8. For both OMAP2 and OMAP3, we note the reference and bypass clocks in the DPLL data structure. Whenever we modify the DPLL rate, we first ensure that both the reference and bypass clocks are enabled. Then, we decide whether to use the reference and DPLL, or the bypass clock if the desired rate is identical to the bypass rate, and program the DPLL appropriately. Finally, we update the clock's parent, and then disable the unused clocks. This keeps the parents correctly balanced, and more importantly ensures that the bypass clock is running whenever we reprogram the DPLL. This is especially important because the procedure for reprogramming the DPLL involves switching to the bypass clock. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] omap: arrange for clock recalc methods to return the rateRussell King2009-02-141-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | linux-omap source commit 33d000c99ee393fe2042f93e8422f94976d276ce introduces a way to "dry run" clock changes before they're committed. However, this involves putting logic to handle this into each and every recalc function, and unfortunately due to the caching, led to some bugs. Solve both of issues by making the recalc methods always return the clock rate for the clock, which the caller decides what to do with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] omap: fix clockdomain enable/disable orderingRussell King2009-02-081-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Based on a patch from Paul Walmsley <paul@pwsan.com>: omap2_clk_enable() should enable a clock's clockdomain before attempting to enable its parent clock's clockdomain. Similarly, in the unlikely event that the parent clock enable fails, the clockdomain should be disabled. linux-omap source commit is 6d6e285e5a7912b1ea68fadac387304c914aaba8. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] omap: fix usecount decrement bugRussell King2009-02-081-10/+10
| | | | | | | | | | | | | | | | | | | | | | Based upon a patch from Paul Walmsley <paul@pwsan.com>: If _omap2_clk_enable() fails, the clock's usecount must be decremented by one no matter whether the clock has a parent or not. but reorganised a bit. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] OMAP2/3 clock: convert remaining MPU barriers into OCP barriersPaul Walmsley2009-02-081-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several parts of the OMAP2/3 clock code use wmb() to try to ensure that the hardware write completes before continuing. This approach is problematic: wmb() only ensures that the write leaves the ARM. It does not ensure that the write actually reaches the endpoint device. The endpoint device in this case - either the PRM, CM, or SCM - is three interconnects away from the ARM - and the final interconnect is low-speed. And the OCP interconnects will post the write, and who knows how long that will take to complete. So the wmb() is not what we want. Worse, the wmb() is indiscriminate; it causes the ARM to flush any other unrelated buffered writes and wait for the local interconnect to acknowledge them - potentially very expensive. Fix this by converting the wmb()s into readbacks of the same PRM/CM/SCM register. Since the PRM/CM/SCM devices use a single OCP thread, this will cause the MPU to block while waiting for posted writes to that device to complete. linux-omap source commit is 260f5487848681b4d8ea7430a709a601bbcb21d1. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] OMAP2xxx clock: consolidate DELAYED_APP clock commits; fix barrierPaul Walmsley2009-02-081-9/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | Consolidate the commit code for DELAYED_APP clocks into a subroutine, _omap2xxx_clk_commit(). Also convert the MPU barrier wmb() into an OCP barrier, since with an MPU barrier, we have no guarantee that the write actually reached the endpoint device. linux-omap source commit is 0f5bdb736515801b296125d16937a21ff7b3cfdc. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] OMAP2/3 clock: don't use a barrier after clk_disable()Paul Walmsley2009-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk_disable() previously used an ARM barrier, wmb(), to try to ensure that the hardware write completed before continuing. There are some problems with this approach. The first problem is that wmb() only ensures that the write leaves the ARM -- not that it actually reaches the endpoint device. In this case, the endpoint device - either the PRM, CM, or SCM - is three interconnects away from the ARM, and the final interconnect is low-speed. And the OCP interconnects will post the write, who knows how long that will take to complete. So the wmb() is not really what we want. Worse, the wmb() is indiscriminate; it will cause the ARM to flush any other unrelated buffered writes and wait for the local interconnect to acknowledge them - potentially very expensive. This first problem could be fixed by doing a readback of the same PRM/CM/SCM register. Since these devices use a single OCP thread, this will cause the MPU to wait for the write to complete. But the primary problem is a conceptual one: clk_disable() should not need any kind of barrier. clk_enable() needs one since device driver code must not access a device until its clocks are known to be enabled. But clk_disable() has no such restriction. Since blocking the MPU on a PRM/CM/SCM write can be a very high-latency operation - several hundred MPU cycles - it's worth avoiding this barrier if possible. linux-omap source commit is f4aacad2c0ed1055622d5c1e910befece24ef0e2. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] omap: create a proper tree of clocksRussell King2009-02-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | Traditionally, we've tracked the parent/child relationships between clk structures by setting the child's parent member to point at the upstream clock. As a result, when decending the tree, we have had to scan all clocks to find the children. Avoid this wasteful scanning by keeping a list of the clock's children. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] OMAP3: PM: Make sure clk_disable_unused() order is correctTero Kristo2009-02-081-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Current implementation will disable clocks in the order defined in clock34xx.h, at least DPLL4_M2X2 will hang in certain cases (and prevent retention / off) if clocks are not disabled in correct order. This patch makes sure the parent clocks will be active when disabling a clock. linux-omap source commit is 672680063420ef8c8c4e7271984bb9cc08171d29. Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] OMAP2 SDRC: move mach-omap2/memory.h into mach/sdrc.hPaul Walmsley2009-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Move the contents of the arch/arm/mach-omap2/memory.h file to the existing mach/sdrc.h file, and remove memory.h. Modify files which include memory.h to include asm/arch/sdrc.h instead. linux-omap source commit is e7ae2d89921372fc4b9712a32cc401d645597807. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] OMAP2/3 clock: clean up mach-omap2/clock.cPaul Walmsley2009-02-081-63/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch rolls up several cleanup patches. 1. Some unnecessarily verbose variable names are used in several clock.c functions; clean these up per CodingStyle. 2. Remove omap2_get_clksel() and just use clk->clksel_reg and clk->clksel_mask directly. 3. Get rid of void __iomem * usage in omap2_clksel_get_src_field. Prepend the function name with an underscore to highlight that it is a static function. linux-omap source commits are 7fa95e007ea2f3c4d0ecd2779d809756e7775894, af0ea23f1ee4a5bea3b026e38761b47089f9048a, and 91c0c979b47c44b08f80e4f8d4c990fb158d82c4. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] OMAP3 clock: avoid invalid FREQSEL values during DPLL rate roundingPaul Walmsley2009-02-081-2/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DPLL FREQSEL jitter correction bits are set based on a table in the 34xx TRM, Table 4-38, according to the DPLL's internal clock frequency "Fint." Several Fint frequency ranges are missing from this table. Previously, we allowed these Fint frequency ranges to be selected in the rate rounding code, but did not change the FREQSEL bits. Correspondence with the OMAP hardware team indicates that Fint values not in the table should not be used. So, prevent them from being selected during DPLL rate rounding. This removes warnings and also can prevent the chip from locking up. The first pass through the rate rounding code will update the DPLL max and min dividers appropriately, so later rate rounding passes will run faster than the first. Peter de Schrijver <peter.de-schrijver@nokia.com> put up with several test cycles of this patch - thanks Peter. linux-omap source commit is f9c1b82f55b60fc39eaa6e7aa1fbe380c0ffe2e9. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Peter de Schrijver <peter.de-schrijver@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] OMAP3 clock: optimize DPLL rate rounding algorithmPaul Walmsley2009-02-081-17/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous DPLL rate rounding algorithm counted the divider (N) down from the maximum to 1. Since we currently use a broad DPLL rate tolerance, and lower N values are more power-efficient, we can often bypass several iterations through the loop by counting N upwards from 1. Peter de Schrijver <peter.de-schrijver@nokia.com> put up with several test cycles of this patch - thanks Peter. linux-omap source commit is 6f6d82bb2f80fa20a841ac3e95a6f44a5a156188. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Peter de Schrijver <peter.de-schrijver@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] OMAP3 clock: remove unnecessary dpll_data dereferencesPaul Walmsley2009-02-081-10/+13
| | | | | | | | | | | | | | | | | | | | Remove some clutter from omap2_dpll_round_rate(). linux-omap source commit is 4625dceb8583c02a6d67ededc9f6a8347b6b8cb7. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] OMAP: Fix sparse, checkpatch warnings in OMAP2/3 PRCM/PM codePaul Walmsley2009-02-081-26/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix sparse & checkpatch warnings in OMAP2/3 PRCM & PM code. This mostly consists of: - converting pointer comparisons to integers in form similar to (ptr == 0) to the standard idiom (!ptr) - labeling a few non-static private functions as static - adding prototypes for *_init() functions in the appropriate header files, and getting rid of the corresponding open-coded extern prototypes in other C files - renaming the variable 'sclk' in mach-omap2/clock.c:omap2_get_apll_clkin to avoid shadowing an earlier declaration Clean up checkpatch issues. This mostly involves: - converting some asm/ includes to linux/ includes - cleaning up some whitespace - getting rid of braces for conditionals with single following statements Also take care of a few odds and ends, including: - getting rid of unlikely() and likely() - none of this code is particularly fast-path code, so the performance impact seems slim; and some of those likely() and unlikely() indicators are probably not as accurate as the ARM's branch predictor - removing some superfluous casts linux-omap source commit is 347df59f5d20fdf905afbc26b1328b0e28a8a01b. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] omap: move propagate_rate() calls into generic omap clock codeRussell King2009-02-081-6/+0
| | | | | | | | | | | | | | | | | | propagate_rate() is recursive, so it makes sense to minimise the amount of stack which is used for each recursion. So, rather than recursing back into it from the ->recalc functions if RATE_PROPAGATES is set, do that test at the higher level. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] omap: move clock propagation into core omap clock codeRussell King2009-02-081-6/+0
| | | | | | | | | | | | | | | | Move the clock propagation calls for set_parent and set_rate into the core omap clock code, rather than having these calls scattered throughout the OMAP1 and OMAP2 implementations. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] omap: don't use clkops_omap2_dflt_wait for non-ICLK/FCLK clocksRussell King2009-02-081-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original code in omap2_clk_wait_ready() used to check the low 8 bits to determine whether they were within the FCLKEN or ICLKEN registers. Specifically, the test is satisfied when these offsets are used: CM_FCLKEN, CM_FCLKEN1, CM_CLKEN, OMAP24XX_CM_FCLKEN2, CM_ICLKEN, CM_ICLKEN1, CM_ICLKEN2, CM_ICLKEN3, OMAP24XX_CM_ICLKEN4 OMAP3430_CM_CLKEN_PLL, OMAP3430ES2_CM_CLKEN2 If one of these offsets isn't used, omap2_clk_wait_ready() merely returns without doing anything. So we should use the non-wait clkops version instead and eliminate that conditional. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] omap: eliminate unnecessary conditionals in omap2_clk_wait_readyRussell King2009-02-081-20/+22
| | | | | | | | | | | | | | | | | | | | Rather than employing run-time tests in omap2_clk_wait_ready() to decide whether we need to wait for the clock to become ready, we can set the .ops appropriately. This change deals with the OMAP24xx and OMAP34xx conditionals only. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] omap: add default .ops to all remaining OMAP2 clocksRussell King2009-02-081-14/+21
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] omap: kill PARENT_CONTROLS_CLOCKRussell King2009-02-081-6/+0
| | | | | | | | | | | | | | | | PARENT_CONTROLS_CLOCK just makes enable/disable no-op, and is functionally an alias for ALWAYS_ENABLED. This can be handled in the same way, using clkops_null. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] omap: provide a NULL clock operations structureRussell King2009-02-081-2/+2
| | | | | | | | | | | | | | | | ... and use it for clocks which are ALWAYS_ENABLED. These clocks use a non-NULL enable_reg pointer for other purposes (such as selecting clock rates.) Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * [ARM] omap: introduce clock operations structureRussell King2009-02-021-4/+4
| | | | | | | | | | | | | | Collect up all the common enable/disable clock operation functions into a separate operations structure. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] omap: fix clock reparenting in omap2_clk_set_parent()Russell King2009-02-191-4/+4
| | | | | | | | | | | | | | | | | | When changing the parent of a clock, it is necessary to keep the clock use counts balanced otherwise things the parent state will get corrupted. Since we already disable and re-enable the clock, we might as well use the recursive versions instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] omap: fix _omap2_clksel_get_src_field()Russell King2009-02-141-1/+1
| | | | | | | | | | | | | | | | _omap2_clksel_get_src_field() was returning the first entry which was either the default _or_ applicable to the SoC. This is wrong - we should be returning the first default which is applicable to the SoC. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] omap: fix omap2_divisor_to_clksel() error return valueRussell King2009-02-141-3/+3
|/ | | | | | | | The error checks for omap2_divisor_to_clksel() and comment disagree with the actual value returned on error. Fix this to return the correct error value. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'omap-all' into develRussell King2008-10-141-13/+51
|\ | | | | | | | | | | | | Conflicts: arch/arm/mach-omap2/gpmc.c arch/arm/mach-omap2/irq.c
| * Merge unstable branch 'omap-rmk'Russell King2008-10-031-9/+9
| |\ | | | | | | | | | Merge branch 'omap-rmk' into omap-all
| | * [ARM] omap: fix lots of 'Using plain integer as NULL pointer'Russell King2008-09-051-9/+9
| | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: OMAP2: Clockdomain: Integrate OMAP3 clocks with clockdomain codePaul Walmsley2008-08-191-4/+42
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch integrates the OMAP3 clock tree with the clockdomain code. This patch: - marks OMAP34xx clocks with their corresponding clockdomain. - adds code to convert the clockdomain name to a clockdomain pointer in the struct clk during clk_register(). - modifies OMAP2 clock usecounting to call into the clockdomain code when clocks are enabled or disabled. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* | [ARM] Convert asm/bitops.h to linux/bitops.hRussell King2008-09-061-1/+1
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | [ARM] Convert asm/io.h to linux/io.hRussell King2008-09-061-2/+1
|/ | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Move include/asm-arm/arch-* to arch/arm/*/include/machRussell King2008-08-071-3/+3
| | | | | | This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithmPaul Walmsley2008-07-031-1/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a new rate rounding algorithm for DPLL clocks on the OMAP2/3 architecture. For a desired DPLL target rate, there may be several multiplier/divider (M, N) values which will generate a sufficiently close rate. Lower N values result in greater power economy. However, lower N values can cause the difference between the rounded rate and the target rate ("rate error") to be larger than it would be with a higher N. This can cause downstream devices to run more slowly than they otherwise would. This DPLL rate rounding algorithm: - attempts to find the lowest possible N (DPLL divider) to reach the target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>, lower N values save more power than higher N values). - allows developers to set an upper bound on the error between the rounded rate and the desired target rate ("rate tolerance"), so an appropriate balance between rate fidelity and power savings can be set. This maximum rate error tolerance is set via omap2_set_dpll_rate_tolerance(). - never returns a rounded rate higher than the target rate. The rate rounding algorithm caches the last rounded M, N, and rate computation to avoid rounding the rate twice for each clk_set_rate() call. (This patch does not yet implement set_rate for DPLLs; that follows in a future patch.) The algorithm trades execution speed for rate accuracy. It will find the (M, N) set that results in the least rate error, within a specified rate tolerance. It does this by evaluating each divider setting - on OMAP3, this involves 128 steps. Another approach to DPLL rate rounding would be to bail out as soon as a valid rate is found within the rate tolerance, which would trade rate accuracy for execution speed. Alternate implementations welcome. This code is not yet used by the OMAP24XX DPLL clock, since it is currently defined as a composite clock, fusing the DPLL M,N and the M2 output divider. This patch also renames the existing OMAP24xx DPLL programming functions to highlight that they program both the DPLL and the DPLL's output multiplier. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP: SRAM: Split sram24xx.S into sram242x.S and sram243x.STony Lindgren2008-07-031-1/+2
| | | | | | | Split sram24xx.S into sram242x.S and sram243x.S Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP: PRCM fixes to ssi clock handlingJouni Högander2008-05-091-1/+3
| | | | | | | | ssi_l4_ick should have PARENT_CONTROLS_CLOCK flag. ST_SSI_STDBY bit in idlest register cannot be used in omap2_clk_wait_ready Signed-off-by: Jouni Högander <jouni.hogander@nokia.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: New DPLL clock frameworkRoman Tereshonkov2008-04-141-8/+0
| | | | | | | | | | | | | | | | | | | These changes is the result of the discussion with Paul Walmsley. His ideas are included into this patch. Remove DPLL output divider handling from DPLLs and CLKOUTX2 clocks, and place it into specific DPLL output divider clocks (e.g., dpll3_m2_clk). omap2_get_dpll_rate() now returns the correct DPLL rate, as represented by the DPLL's CLKOUT output. Also add MPU and IVA2 subsystem clocks, along with high-frequency bypass support. Add support for DPLLs function in locked and bypass clock modes. Signed-off-by: Roman Tereshonkov <roman.tereshonkov@nokia.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Clean up 24xx clock codeTony Lindgren2008-04-141-11/+4
| | | | | | | | Clean up 24xx clock code to sync it with linux-omap tree. Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Change 24xx to use shared clock code and new reg accessPaul Walmsley2008-04-141-1/+1
| | | | | | | | | | | | | | | | | This patch changes 24xx to use shared clock code and new register access. Note that patch adds some temporary OLD_CK defines to keep patch more readable. These temporary defines will be removed in the next patch. Also not all clocks are changed in this patch to limit the size. Also, the patch fixes few incorrect clock defines in clock24xx.h. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Add common clock framework for 24xx and 34xxPaul Walmsley2008-04-141-0/+757
| | | | | | | | | | This patch adds a common clock framework for 24xx and 34xx. Note that this patch does not add it to Makefile until in next patch. Some functions are modified from earlier 24xx clock framework code. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Move clock.c to clock24xx.cPaul Walmsley2008-04-141-1176/+0
| | | | | | | | | | | This patch moves clock.h to clock24xx.c to make room for adding common clock code for 24xx and 34xx. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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