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* [ARM] Kirkwood: add support for rev A1 of the 88f6192 and 88f6180 chips.Saeed Bishara2010-07-162-0/+6
| | | | | Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* [ARM] Kirkwood: configure NAND mpp's for db88f6281Saeed Bishara2010-07-161-0/+8
| | | | | | | | | In case the board is configured to boot from spi flash, the mpps will not be configured to select the NAND I/Os. This patch makes sure to select the NAND I/O's regardless to the boot device type. Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* [ARM] orion5x: Fix soft-reset for some platformsBenjamin Herrenschmidt2010-07-161-0/+2
| | | | | | | | | | | | Some platforms, such as the DNS-323 rev C requires the soft reset line to be toggled on and back off for the reset to work. Note: The choice of 200ms delay comes from the 2.6.12 based vendor kernel. It seems to be a -lot- though and I had my device working fine with much smaller delays but better safe... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* [ARM] orion5x: Base support for DNS-323 rev C1Benjamin Herrenschmidt2010-07-161-62/+305
| | | | | | | | | | This patch adds the base support for this new HW revision to the existing dns323-setup.c file. The SoC seems to be the same as rev B1, the GPIOs are all wired differently though and the fan control isn't i2c based anymore. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* [ARM] Marvell OpenRD-Ultimate machine supportDmytro Milinevskyy2010-07-162-3/+31
| | | | | | | | | This patch adds support for the OpenRD Ultimate machine (could be found at http://www.arm.linux.org.uk/developer/machines/list.php?id=2884) Signed-off-by: Dmytro Milinevskyy <milinevskyy@gmail.com> Acked-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* [ARM] orion/kirkwood: reset PCIe unit on bootOlaf Rempel2010-07-161-0/+34
| | | | | | | | | | | | | | | | | | | | Patch found in QNAPs vendor source package, with some cleanups (proper defines, shortened max. timeout from 1s to 200ms). Without this patch the PCIe SATA controller (Marvell 88sx7042/sata_mv) in my QNAP TS-419P (Marvell 88f6281/Kirkwood) stops working after a few minutes. The symptomes are described in this thread: http://marc.info/?l=linux-ide&m=124822863706181&w=2 [ Note: this is a workaround in need of a better analysis/solution -- NP ] Acked-by: Saeed Bishara <saeed@marvell.com> Tested-by: Bernhard R. Link <brl@pcpool00.mathematik.uni-freiburg.de> Seconded-by: Martin Michlmayr <tbm@cyrius.com> I'm_not_very_happy_with_it-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* [ARM] Kirkwood: fix HP t5325 after commit 6605742f2aNicolas Pitre2010-07-161-7/+7
| | | | Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* [ARM] Kirkwood: Add support for HP t5325 Thin ClientMartin Michlmayr2010-07-163-0/+201
| | | | | | | | | Add support for the HP t5325 Thin Client. This thin client is based on a Marvell Kirkwood chip at 1.2 GHz and features 512 MB RAM, 512 MB SATA-attached flash and an XGI Volari Z11 GPU. Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* [ARM] Kirkwood: Add MPP44 (board ID) on TS-219Martin Michlmayr2010-07-161-0/+1
| | | | | | | | | | | | MPP44 can be used to differentiate between one-bay (TS-11x) and two-bay (TS-21x) devices. According to an engineer from QNAP, the setting of MPP44 depends on the firmware rather than hardware. Presumably, this means that you could fake the MPP44 value by changing the boot loader. Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* [ARM] Kirkwood: update MPP definition.Benjamin Zores2010-07-165-307/+357
| | | | | | | | Add MPP definitions for Marvell Kirkwood 88F6282 revision. Update some defines to reflect datasheet's MPP names. Signed-off-by: Benjamin Zores <benjamin.zores@alcatel-lucent.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* [ARM] orion5x: Set links to solid on D-Link DNS-323Martin Michlmayr2010-07-161-2/+1
| | | | | | | | | | | | | | | Among other changes, commit b2a731aa ("D-link DNS-323 revision A1 power LED") changed the default behaviour of the power LED from solid to blinking. This was done to match the original DNS-323 firmware which blinks during the boot process and sets the LED to solid when booting has completed. However, the downside of this behaviour is that it requires userland code to change the LED, even for those who don't care about the behaviour of the original firmware. Therefore, change it to solid again and let those who care about the original behaviour change the behaviour from userland. Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* [ARM] Kirkwood: Fix explanation of MPP45 for QNAP TS41xMartin Michlmayr2010-07-161-1/+1
| | | | | | | | On the QNAP TS-41x, MPP45 is used to show the setting of jumper JP1. Fix the documentation to explain what the settings really indicate. Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* [ARM] Kirkwood: Export GPIO indicating jumper setting of JP1Martin Michlmayr2010-07-161-1/+6
| | | | | | | | | Export GPIO 45 which is used to indicate the setting of the JP1 jumper. This is useful for userland tools, such as qcontrol, to see whether the LCD or a serial console is connected. Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* [ARM] qnap tsx1x: fix section mismatchArnaud Patard2010-07-161-1/+1
| | | | | | | | | | | | | | Fix the following warning : WARNING: vmlinux.o(.text+0x95a0): Section mismatch in reference from the function qnap_tsx1x_register_flash() to the (unknown reference) .init.data:(unknown) The function qnap_tsx1x_register_flash() references the (unknown reference) __initdata (unknown). This is often because qnap_tsx1x_register_flash lacks a __initdata annotation or the annotation of (unknown) is wrong. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Signed-off-by: Martin Michlmayr <tbm@cyrius.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
* Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2010-07-148-93/+243
|\ | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 6226/1: fix kprobe bug in ldr instruction emulation ARM: Update mach-types ARM: lockdep: fix unannotated irqs-on ARM: 6184/2: ux500: use neutral PRCMU base ARM: 6212/1: atomic ops: add memory constraints to inline asm ARM: 6211/1: atomic ops: fix register constraints for atomic64_add_unless ARM: 6210/1: Do not rely on reset defaults of L2X0_AUX_CTRL
| * ARM: 6226/1: fix kprobe bug in ldr instruction emulationNicolas Pitre2010-07-141-2/+3
| | | | | | | | | | | | | | | | | | From: Bin Yang <bin.yang@marvell.com> Cc: stable@kernel.org Signed-off-by: Bin Yang <bin.yang@marvell.com> Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: Update mach-typesRussell King2010-07-121-3/+149
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: lockdep: fix unannotated irqs-onRussell King2010-07-102-19/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPU: Testing write buffer coherency: ok ------------[ cut here ]------------ WARNING: at kernel/lockdep.c:3145 check_flags+0xcc/0x1dc() Modules linked in: [<c0035120>] (unwind_backtrace+0x0/0xf8) from [<c0355374>] (dump_stack+0x20/0x24) [<c0355374>] (dump_stack+0x20/0x24) from [<c0060c04>] (warn_slowpath_common+0x58/0x70) [<c0060c04>] (warn_slowpath_common+0x58/0x70) from [<c0060c3c>] (warn_slowpath_null+0x20/0x24) [<c0060c3c>] (warn_slowpath_null+0x20/0x24) from [<c008f224>] (check_flags+0xcc/0x1dc) [<c008f224>] (check_flags+0xcc/0x1dc) from [<c00945dc>] (lock_acquire+0x50/0x140) [<c00945dc>] (lock_acquire+0x50/0x140) from [<c0358434>] (_raw_spin_lock+0x50/0x88) [<c0358434>] (_raw_spin_lock+0x50/0x88) from [<c00fd114>] (set_task_comm+0x2c/0x60) [<c00fd114>] (set_task_comm+0x2c/0x60) from [<c007e184>] (kthreadd+0x30/0x108) [<c007e184>] (kthreadd+0x30/0x108) from [<c0030104>] (kernel_thread_exit+0x0/0x8) ---[ end trace 1b75b31a2719ed1c ]--- possible reason: unannotated irqs-on. irq event stamp: 3 hardirqs last enabled at (2): [<c0059bb0>] finish_task_switch+0x48/0xb0 hardirqs last disabled at (3): [<c002f0b0>] ret_slow_syscall+0xc/0x1c softirqs last enabled at (0): [<c005f3e0>] copy_process+0x394/0xe5c softirqs last disabled at (0): [<(null)>] (null) Fix this by ensuring that the lockdep interrupt state is manipulated in the appropriate places. We essentially treat userspace as an entirely separate environment which isn't relevant to lockdep (lockdep doesn't monitor userspace.) We don't tell lockdep that IRQs will be enabled in that environment. Instead, when creating kernel threads (which is a rare event compared to entering/leaving userspace) we have to update the lockdep state. Do this by starting threads with IRQs disabled, and in the kthread helper, tell lockdep that IRQs are enabled, and enable them. This provides lockdep with a consistent view of the current IRQ state in kernel space. This also revert portions of 0d928b0b616d1c5c5fe76019a87cba171ca91633 which didn't fix the problem. Tested-by: Ming Lei <tom.leiming@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 6184/2: ux500: use neutral PRCMU baseLinus Walleij2010-07-092-1/+2
| | | | | | | | | | | | | | | | The MTU wallclock timing fix-up patch was hardwired to the DB8500 causing a regression. This makes it work on the DB5500 as well. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 6212/1: atomic ops: add memory constraints to inline asmWill Deacon2010-07-091-66/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the 32-bit and 64-bit atomic operations on ARM do not include memory constraints in the inline assembly blocks. In the case of barrier-less operations [for example, atomic_add], this means that the compiler may constant fold values which have actually been modified by a call to an atomic operation. This issue can be observed in the atomic64_test routine in <kernel root>/lib/atomic64_test.c: 00000000 <test_atomic64>: 0: e1a0c00d mov ip, sp 4: e92dd830 push {r4, r5, fp, ip, lr, pc} 8: e24cb004 sub fp, ip, #4 c: e24dd008 sub sp, sp, #8 10: e24b3014 sub r3, fp, #20 14: e30d000d movw r0, #53261 ; 0xd00d 18: e3011337 movw r1, #4919 ; 0x1337 1c: e34c0001 movt r0, #49153 ; 0xc001 20: e34a1aa3 movt r1, #43683 ; 0xaaa3 24: e16300f8 strd r0, [r3, #-8]! 28: e30c0afe movw r0, #51966 ; 0xcafe 2c: e30b1eef movw r1, #48879 ; 0xbeef 30: e34d0eaf movt r0, #57007 ; 0xdeaf 34: e34d1ead movt r1, #57005 ; 0xdead 38: e1b34f9f ldrexd r4, [r3] 3c: e1a34f90 strexd r4, r0, [r3] 40: e3340000 teq r4, #0 44: 1afffffb bne 38 <test_atomic64+0x38> 48: e59f0004 ldr r0, [pc, #4] ; 54 <test_atomic64+0x54> 4c: e3a0101e mov r1, #30 50: ebfffffe bl 0 <__bug> 54: 00000000 .word 0x00000000 The atomic64_set (0x38-0x44) writes to the atomic64_t, but the compiler doesn't see this, assumes the test condition is always false and generates an unconditional branch to __bug. The rest of the test is optimised away. This patch adds suitable memory constraints to the atomic operations on ARM to ensure that the compiler is informed of the correct data hazards. We have to use the "Qo" constraints to avoid hitting the GCC anomaly described at http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44492 , where the compiler makes assumptions about the writeback in the addressing mode used by the inline assembly. These constraints forbid the use of auto{inc,dec} addressing modes, so it doesn't matter if we don't use the operand exactly once. Cc: stable@kernel.org Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 6211/1: atomic ops: fix register constraints for atomic64_add_unlessWill Deacon2010-07-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The atomic64_add_unless function compares an atomic variable with a given value and, if they are not equal, adds another given value to the atomic variable. The function returns zero if the addition did not occur and non-zero otherwise. On ARM, the return value is initialised to 1 in C code. Inline assembly code then performs the atomic64_add_unless operation, setting the return value to 0 iff the addition does not occur. This means that when the addition *does* occur, the value of ret must be preserved across the inline assembly and therefore requires a "+r" constraint rather than the current one of "=&r". Thanks to Nicolas Pitre for helping to spot this. Cc: stable@kernel.org Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 6210/1: Do not rely on reset defaults of L2X0_AUX_CTRLSascha Hauer2010-07-091-2/+3
| | | | | | | | | | | | | | | | | | | | On i.MX35 the L2X0_AUX_CTRL register does not have sensible reset default values. Allow them to be overwritten with the aux_val/aux_mask arguments passed to l2x0_init(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge branch 'arm/defconfig/reduced-v2.6.35-rc1' of ↵Linus Torvalds2010-07-12177-194157/+652
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.pengutronix.de/git/ukl/linux-2.6 * 'arm/defconfig/reduced-v2.6.35-rc1' of git://git.pengutronix.de/git/ukl/linux-2.6: ARM: reduce defconfigs This is a big change, but results in no loss of information, despite us losing almost 200k lines: 177 files changed, 652 insertions(+), 194157 deletions(-) and Grant Likely thinks powerpc can also use the same reduction technique. The python script that did the reduction looks like this: #! /usr/bin/env python # vim: set fileencoding=utf-8 : # Copyright (C) 2010 by Uwe Kleine-König <u.kleine-koenig@pengutronix.de> import re import subprocess import os import sys # This prevents including a timestamp in the .config which makes comparing a # bit easier. os.environ['KCONFIG_NOTIMESTAMP'] = 'Yes, please' # XXX: get these using getopt kernel_tree = '' # os.path.join(os.environ['HOME'], 'gsrc', 'linux-2.6') arch = 'arm' target = sys.argv[1] defconfig_src = os.path.join(kernel_tree, 'arch/%s/configs/%s' % (arch, target)) subprocess.check_call(['make', '-s', 'ARCH=%s' % arch, target]) origconfig = list(open('.config')) config = list(origconfig) config_size = os.stat('.config').st_size i = 0 while i < len(config): print 'test for %r' % config[i] defconfig = open(defconfig_src, 'w') defconfig.writelines(config[:i]) defconfig.writelines(config[i + 1:]) defconfig.close() subprocess.check_call(['make', '-s', 'ARCH=%s' % arch, target]) if os.stat('.config').st_size == config_size and list(open('.config')) == origconfig: del config[i] else: i += 1 defconfig = open(defconfig_src, 'w') defconfig.writelines(config) defconfig.close() which is pretty self-explanatory. Acked-by: Nicolas Pitre <nico@fluxnic.net> Acked-by: Russell King <linux@arm.linux.org.uk> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * ARM: reduce defconfigsUwe Kleine-König2010-06-10177-194157/+652
| | | | | | | | Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
* | ARM: SAMSUNG: Fix on wrong function name for S5PV210 sdhci0Hyuk Lee2010-07-051-1/+1
| | | | | | | | | | | | | | | | | | This patch fixes on wrong function name in include/plat/sdhci.h for Samsung. The 's5pc100_default_sdhci0()' function should be chnaged to 's5pv210_default_sdhci0()'. Because 's5pv210_default_sdhci0()' must be pair. Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | ARM: S5P6442: Fix PLL setting announce message.Thomas Abraham2010-07-051-1/+1
| | | | | | | | | | | | | | | | The S5P6442 PLL setting announce message incorrectly displays S5P6440 as the SoC. Change it to S5P6442. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | ARM: SAMSUNG: Fix build without SDHCI controllers for S3C64XXMarek Szyprowski2010-07-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the following compilation problem if only NCP machine is selected: arch/arm/mach-s3c64xx/s3c6410.c: In function 's3c6410_map_io': arch/arm/mach-s3c64xx/s3c6410.c:51: error: implicit declaration of function 's3c6410_default_sdhci2' And also adds missed 's3c6400_default_sdhci2'. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: minor title fix and added comments] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | ARM: S5PV210: Correct clock register propertiesMyungJoo Ham2010-07-051-53/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which were defined incorrectly. 2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc, sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their twins defined in struct clk init_clocks_disable[] and struct clk init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK register to avoid the duplicated clock problem described below. NOTE: Duplicated Clock Problem Please note that each clock definition should access different control register; otherwise, the system may suffer lockups. For example, if we have two clock definitions "a" and "b" which access the same register (and the shift value). Then, when we do: module A clk = clk_get("a"); clk->clk_enable(clk); module B (context switch) clk = clk_get("b"); clk->clk_enable(clk); do something with clk. clk->clk_disable(clk); module A (context switch) do something with clk * At this point, the system may hang. Therefore, there should be no clock definitions with the same contol register/shift. If we need to create "aliases", then, creating child clocks sharing the clock should be fine. 3. Corrected other sclk_* shift values and access registers. Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: minor title and message fix] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | ARM: S5P: Bug fix on external interrupt for S5P SoCsBoojin Kim2010-07-051-1/+1
| | | | | | | | | | | | | | | | | | This patch fixes bug on eint type set function, s5p_irq_eint_set_type(). In the IRQ_TYPE_EDGE_FALLING case, S5P_EXTINT_FALLEDGE is right instead of S5P_EXTINT_RISEEDGE Signed-off-by: Boojin Kim <boojin.kim@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | ARM: 6205/1: perf: ensure counter delta is treated as unsignedWill Deacon2010-07-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hardware performance counters on ARM are 32-bits wide but atomic64_t variables are used to represent counter data in the hw_perf_event structure. The armpmu_event_update function right-shifts a signed 64-bit delta variable and adds the result to the event count. This can lead to shifting in sign-bits if the MSB of the 32-bit counter value is set. This results in perf output such as: Performance counter stats for 'sleep 20': 18446744073460670464 cycles <-- 0xFFFFFFFFF12A6000 7783773 instructions # 0.000 IPC 465 context-switches 161 page-faults 1172393 branches 20.154242147 seconds time elapsed This patch ensures that the delta value is treated as unsigned so that the right shift sets the upper bits to zero. Cc: <stable@kernel.org> Acked-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6202/1: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards with L210/L220Catalin Marinas2010-07-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | RealView boards with certain revisions of the L210/L220 cache controller may have issues (hardware deadlock) with the mandatory barriers (DSB followed by an L2 cache sync) when ARM_DMA_MEM_BUFFERABLE is enabled. The patch disables ARM_DMA_MEM_BUFFERABLE for these boards. Tested-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | ARM: 6201/1: RealView: Do not use outer_sync() on ARM11MPCore boards with L220Catalin Marinas2010-07-022-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | RealView boards with certain revisions of the L220 cache controller (ARM11* processors only) may have issues (hardware deadlock) with the recent changes to the mb() barrier implementation (DSB followed by an L2 cache sync). The patch redefines the RealView ARM11MPCore mandatory barriers without the outer_sync() call. Cc: <stable@kernel.org> Tested-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge branch 'imx-for-2.6.35' of git://git.pengutronix.de/git/imx/linux-2.6Russell King2010-07-011-11/+22
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| * | ARM: mx3: mx31lilly: fix build error for !CONFIG_USB_ULPIDaniel Mack2010-07-011-11/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch/arm/mach-mx3/built-in.o: In function `mx31lilly_board_init': mach-kzm_arm11_01.c:(.init.text+0x674): undefined reference to `otg_ulpi_create' mach-kzm_arm11_01.c:(.init.text+0x68c): undefined reference to `otg_ulpi_create' mach-kzm_arm11_01.c:(.init.text+0x744): undefined reference to `mxc_ulpi_access_ops' make: *** [.tmp_vmlinux1] Error 1 Signed-off-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
* | | Merge branch 'fix' of ↵Russell King2010-07-014-20/+15
|\ \ \ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
| * | | [ARM] mmp: fix build failure due to IRQ_PMU depends on ARCH_PXAJonathan Cameron2010-06-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PMU is not tested and enabled on MMP architecture at this moment, the device IRQ number, IRQ_PMU depends on ARCH_PXA. Build PMU only for ARCH_PXA. Signed-off-by: Jonathan Cameron <jic23@cam.ac.uk> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * | | [ARM] pxa/mioa701: fix camera regressionRobert Jarzmik2010-06-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit a48c24a696f0d93c49f913b7818e9819612b1f4e, the camera is not working anymore. After the v4l2 migration, the mt9m111 camera board information was not passed to the i2c layer anymore, but stored for future use of v4l2 (through soc_camera). Because mioa701_i2c_devices[] was tagged as "__initdata", and because after the v4l2 migration, the new structure "iclink" references it, the mt9m111 driver is not probed anymore, as part of "iclink" is not valid (discarded after kernel init). Although there is not compilation error, nor runtime oops, this patch restores a working camera on the mioa701 board. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * | | [ARM] pxa/z2: fix flash layout to final versionMarek Vasut2010-06-131-16/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes flash layout to it's final version. Also, I fixed the authorship information of this file as it's been totally reworked since Ken released his last version. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * | | [ARM] pxa: fix incorrect gpio type in udc_pxa2xx.hSteve Bennett2010-06-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gpio must be int, not u16, otherwise -1 isn't recognised by gpio_is_valid(). Signed-off-by: Steve Bennett <steveb@workware.net.au> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* | | | ARM: 6195/1: OMAP3: pmu: make CPU_HAS_PMU dependent on OMAP3_EMUWill Deacon2010-07-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPU performance event counters on v7 cores will only operate if either the NIDEN or DBGEN signals are driven high. For the OMAP3 platform, these signals are driven low by default but DBGEN can be asserted by selecting the OMAP3_EMU Kconfig option, which enables the virtual clock for hardware debugging peripherals. Acked-by: Jean Pihet <jpihet@mvista.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 6194/1: change definition of cpu_relax() for ARM11MPCoreWill Deacon2010-07-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux expects that if a CPU modifies a memory location, then that modification will eventually become visible to other CPUs in the system. On an ARM11MPCore processor, loads are prioritised over stores so it is possible for a store operation to be postponed if a polling loop immediately follows it. If the variable being polled indirectly depends on the outstanding store [for example, another CPU may be polling the variable that is pending modification] then there is the potential for deadlock if interrupts are disabled. This deadlock occurs in the KGDB testsuire when executing on an SMP ARM11MPCore configuration. This patch changes the definition of cpu_relax() to smp_mb() for ARMv6 cores, forcing a flushing of the write buffer on SMP systems before the next load takes place. If the Kernel is not compiled for SMP support, this will expand to a barrier() as before. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 6193/1: RealView: Align the machine_desc.phys_io to 1MB sectionCatalin Marinas2010-07-015-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When not aligned, random bits could be written in the initial page table by the __create_page_tables() function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 6192/1: VExpress: Align the machine_desc.phys_io to 1MB sectionCatalin Marinas2010-07-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When not aligned, random bits could be written in the initial page table by the __create_page_tables() function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 6188/1: Add a config option for the ARM11MPCore DMA cache maintenance ↵Catalin Marinas2010-07-012-3/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | workaround Commit f4d6477f introduced a workaround for the lack of hardware broadcasting of the cache maintenance operations on ARM11MPCore. However, the workaround is only valid on CPUs that do not do speculative loads into the D-cache. This patch adds a Kconfig option with the corresponding help to make the above clear. When the DMA_CACHE_RWFO option is disabled, the kernel behaviour is that prior to the f4d6477f commit. This also allows ARMv6 UP processors with speculative loads to work correctly. For other processors, a different workaround may be needed. Cc: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 6187/1: The v6_dma_inv_range() function must preserve data on SMPCatalin Marinas2010-07-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent patch for DMA cache maintenance on ARM11MPCore added a write for ownership trick to the v6_dma_inv_range() function. Such operation destroys data already present in the buffer. However, this function is used with with dma_sync_single_for_device() which is supposed to preserve the existing data transfered into the buffer. This patch adds a combination of read/write for ownership to preserve the original data. Reported-by: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | ARM: 6186/1: Avoid the CONSISTENT_DMA_SIZE warning on noMMU buildsCatalin Marinas2010-07-011-9/+9
| |/ / |/| | | | | | | | | | | | | | | | | | | | This macro is not defined when !CONFIG_MMU so this patch moves the CONSISTENT_* definitions to the CONFIG_MMU section. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge branch 'omap-fixes-for-linus' of ↵Linus Torvalds2010-06-308-12/+20
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: OMAP: hwmod: Fix the missing braces OMAP4: clock: Fix multi-omap boot with reset un-used clocks OMAP3: PM: fix IO daisy chain enable to use PM_WKEN reg omap: GPIO: fix auto-disable of debounce clock omap: DMTIMER: Ack pending interrupt always when stopping a timer omap: Stalker board: switch over to gpio_set_debounce omap: fix build failure due to missing include dma-mapping.h omap iommu: Fix Memory leak
| * \ \ Merge branch 'for_2.6.35rc' of git://git.pwsan.com/linux-2.6 into ↵Tony Lindgren2010-06-2821-33/+213
| |\ \ \ | | | | | | | | | | | | | | | omap-fixes-for-linus
| | * | | OMAP: hwmod: Fix the missing bracesBenoit Cousson2010-06-231-3/+6
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As reported by Sergei, a couple of braces were missing after the WARN removal patch. [07/22] OMAP: hwmod: Replace WARN by pr_warning if clock lookup failed https://patchwork.kernel.org/patch/100756/ Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: fixed patch description per Anand's E-mail] Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Sergei Shtylyov <sshtylyov@mvista.com> Cc: Anand Gadiyar <gadiyar@ti.com>
| * | | OMAP4: clock: Fix multi-omap boot with reset un-used clocksSantosh Shilimkar2010-06-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses "ENABLE_ON_INIT" flag on the emif clock nodes to avoid the emif clk getting cut as part of reset un-used clock routine which prevents boot. Since "omap4xxx_clk_init()" calls "clk_enable_init_clocks()" which increases the usecount on all ENABLE_ON_INIT clocks, it prevents "omap2_clk_disable_unused()" from disabling the clock. The real fix is to have driver for EMIF and do clock get/enable as part of it. The EMIF driver is planned to be done HWMOD way so till that available to keep omap3_defconfig booting on OMAP4430, this patch is necessary. (Will updated the auto-gen script for 44xx accordingly) The fix was suggested by Paul Walmsley Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
generated by cgit v1.1 at 2024-12-26 17:44:33 +0000