aboutsummaryrefslogtreecommitdiffstats
path: root/arch/sh/include/cpu-sh4/cpu
Commit message (Collapse)AuthorAgeFilesLines
* sh: Support for extended ASIDs on PTEAEX-capable SH-X3 cores.Paul Mundt2009-03-171-19/+16
| | | | | | | | | | | | | | | | | | | | This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores that implement the PTAEX register and respective functionality. Presently only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs). The main change is in how the PTE is written out when loading the entry in to the TLB, as well as in how the TLB entry is selectively flushed. While SH-X2 extended mode splits out the memory-mapped U and I-TLB data arrays for extra bits, extended ASID mode splits out the address arrays. While we don't use the memory-mapped data array access, the address array accesses are necessary for selective TLB flushes, so these are implemented newly and replace the generic SH-4 implementation. With this, TLB flushes in switch_mm() are almost non-existent on newer parts. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: dma-sh updates for multi IRQ and new SH-4A CPUs.Nobuhiro Iwamatsu2009-03-103-55/+108
| | | | | | | | | | | This adds DMA support for newer SH-4A CPUs, particularly SH7763/64/80/85. This also enables multi IRQ support for platforms that have multiple vectors bound to the same IRQ source. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add support for SH7786 CPU subtype.Kuninori Morimoto2009-03-032-0/+196
| | | | | | | | | | | | | | This adds preliminary support for the SH7786 CPU subtype. While this is a dual-core CPU, only UP is supported for now. L2 cache support is likewise not yet implemented. More information on this particular CPU subtype is available at: http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/ Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Add on-chip RTC support for SH7722.Paul Mundt2008-10-281-1/+1
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: sh7785 pinmux supportMagnus Damm2008-10-231-0/+234
| | | | | | | This patch implements pinmux tables for the sh7785 processor. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Move SH-4 CPU headers down one more level.Paul Mundt2008-10-202-0/+464
| | | | | | | These accidentally got placed in to cpu-sh4 instead of cpu-sh4/cpu, push them down one more level. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: migrate to arch/sh/include/Paul Mundt2008-07-2914-0/+584
This follows the sparc changes a439fe51a1f8eb087c22dd24d69cebae4a3addac. Most of the moving about was done with Sam's directions at: http://marc.info/?l=linux-sh&m=121724823706062&w=2 with subsequent hacking and fixups entirely my fault. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
generated by cgit v1.1 at 2024-09-17 04:21:58 +0000