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* [ARM] 4057/1: ixp23xx: unconditionally enable hardware coherencyLennert Buytenhek2006-12-181-15/+1
| | | | | | | | | | | | | On ixp23xx, it was thought to be necessary to disable coherency to work around certain silicon errata. This turns out not to be the case -- none of the documented errata workarounds require disabling coherency, and disabling coherency does not work around any existing errata. Furthermore, all ixp23xx models do support coherency, so we should just unconditionally enable coherency for all ixp23xx. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4055/1: iop13xx: fix phys_io/io_pg_offst for iq81340mc/scLennert Buytenhek2006-12-181-4/+1
| | | | | | | | The phys_io/io_pg_offst machine record variables were being set to bogus values, causing problems when enabling DEBUG_LL. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4054/1: ep93xx: add HWCAP_CRUNCHLennert Buytenhek2006-12-181-0/+1
| | | | | | | | Add HWCAP_CRUNCH so that the dynamic linker knows whether it can use Crunch-optimised libraries or not. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Fix warnings from asm/system.hRussell King2006-12-181-25/+8
| | | | | | | Move adjust_cr() into arch/arm/mm/mmu.c, and move irqflags.h to a more appropriate place in the header file. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4049/1: S3C24XX: fix sparse warning due to upf_t in regs-serial.hBen Dooks2006-12-172-1/+2
| | | | | | | | | | | | | | | | | Change the include/asm-arm/arch-s3c2410/regs-serial.h platform data to use the prorper type (upf_t) for the uart_flags. Fix all the other parts of arch/arm/mach-s3c2410 to include <linux/serial_core.h> and all other uses of the include file. mach-rx3715.c:101:18: warning: incorrect type in initializer (different base types) mach-rx3715.c:101:18: expected unsigned long [unsigned] uart_flags mach-rx3715.c:101:18: got restricted unsigned int [usertype] [force] <noident> Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4045/1: S3C24XX: remove old VA for non-shared areasBen Dooks2006-12-171-18/+6
| | | | | | | | | Remove old (and non-shared) VA addresses from the mappings in arch/arm/mach-s3c2410/map.h and anywhere they are being mapped in arch/arm/mach-s3c2410 Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4042/1: H1940: Fix sparse errors from VA addressesBen Dooks2006-12-171-1/+1
| | | | | | | | | | Fix address-space conversion errors from passing addresses generated from include/asm-arm/arch-s3c2410/map.h by adding an __force argument to the `void __iomem *` for all the virtual addresses. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4041/1: S3C24XX: Fix sparse errors from VA addressesBen Dooks2006-12-171-1/+1
| | | | | | | | | | Fix address-space conversion errors from passing addresses generated from include/asm-arm/arch-s3c2410/map.h by adding an __force argument to the `void __iomem *` for all the virtual addresses. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4039/1: S3C24XX: Fix copyrights in include/asm-arm/arch-s3c2410 (mach)Ben Dooks2006-12-1712-18/+18
| | | | | | | | | Fix copyright notices in include/asm-arm/arch-s3c2410 to actually have `Copyright` in the line. This patch deals with all the core files. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] 4038/1: S3C24XX: Fix copyrights in include/asm-arm/arch-s3c2410 (core)Ben Dooks2006-12-1710-17/+17
| | | | | | | | | Fix copyright notices in include/asm-arm/arch-s3c2410 to actually have `Copyright` in the line. This patch deals with all the core files. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] Add more syscallsRussell King2006-12-171-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add: sys_unshare sys_set_robust_list sys_get_robust_list sys_splice sys_arm_sync_file_range sys_tee sys_vmsplice sys_move_pages sys_getcpu Special note about sys_arm_sync_file_range(), which is implemented as: asmlinkage long sys_arm_sync_file_range(int fd, unsigned int flags, loff_t offset, loff_t nbytes) { return sys_sync_file_range(fd, offset, nbytes, flags); } We can't export sys_sync_file_range() directly on ARM because the argument list someone picked does not fit in the available registers. Would be nice if... there was an arch maintainer review mechanism for new syscalls before they hit the kernel. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2006-12-138-37/+94
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: [ARM] 4017/1: [Jornada7xx] - Updating Jornada720.c [ARM] 3992/1: i.MX/MX1 CPU Frequency scaling support [ARM] Provide a method to alter the control register [ARM] 4016/1: prefetch macro is wrong wrt gcc's "delete-null-pointer-checks" [ARM] Remove empty fixup function [ARM] 4014/1: include drivers/hid/Kconfig [ARM] 4013/1: clocksource driver for netx [ARM] 4012/1: Clocksource for pxa [ARM] Clean up ioremap code [ARM] Unuse another Linux PTE bit [ARM] Clean up KERNEL_RAM_ADDR [ARM] Add sys_*at syscalls [ARM] 4004/1: S3C24XX: UDC remove implict addition of VA to regs [ARM] Formalise the ARMv6 processor name string [ARM] Handle HWCAP_VFP in VFP support code [ARM] 4011/1: AT91SAM9260: Fix compilation with NAND driver [ARM] 4010/1: AT91SAM9260-EK board: Prepare for MACB Ethernet support
| *-. [ARM] Merge AT91 and devel branchesRussell King2006-12-138-37/+94
| |\ \ | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 3992/1: i.MX/MX1 CPU Frequency scaling supportPavel Pisa2006-12-131-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support to change MX1 CPU frequency at runtime. Tested on PiKRON's PiMX1 board and seems to be fully stable up to 200 MHz end even as low as 8 MHz. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] Provide a method to alter the control registerRussell King2006-12-131-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX needs to tweak the control register to support CPU frequency scaling. Rather than have folk blindly try and change the control register by writing to it and then wondering why it doesn't work, provide a method (which is safe for UP only, and therefore only available for UP) to achieve this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 4016/1: prefetch macro is wrong wrt gcc's "delete-null-pointer-checks"Nicolas Pitre2006-12-131-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | optimization The gcc manual says: |`-fdelete-null-pointer-checks' | Use global dataflow analysis to identify and eliminate useless | checks for null pointers. The compiler assumes that dereferencing | a null pointer would have halted the program. If a pointer is | checked after it has already been dereferenced, it cannot be null. | Enabled at levels `-O2', `-O3', `-Os'. Now the problem can be seen with this test case: #include <linux/prefetch.h> extern void bar(char *x); void foo(char *x) { prefetch(x); if (x) bar(x); } Because the constraint to the inline asm used in the prefetch() macro is a memory operand, gcc assumes that the asm code does dereference the pointer and the delete-null-pointer-checks optimization kicks in. Inspection of generated assembly for the above example shows that bar() is indeed called unconditionally without any test on the value of x. Of course in the prefetch case there is no real dereference and it cannot be assumed that a null pointer would have been caught at that point. This causes kernel oopses with constructs like hlist_for_each_entry() where the list's 'next' content is prefetched before the pointer is tested against NULL, and only when gcc feels like applying this optimization which doesn't happen all the time with more complex code. It appears that the way to prevent delete-null-pointer-checks optimization to occur in this case is to make prefetch() into a static inline function instead of a macro. At least this is what is done on x86_64 where a similar inline asm memory operand is used (I presume they would have seen the same problem if it didn't work) and resulting code for the above example confirms that. An alternative would consist of replacing the memory operand by a register operand containing the pointer, and use the addressing mode explicitly in the asm template. But that would be less optimal than an offsettable memory reference. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] Unuse another Linux PTE bitRussell King2006-12-133-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | L_PTE_ASID is not really required to be stored in every PTE, since we can identify it via the address passed to set_pte_at(). So, create set_pte_ext() which takes the address of the PTE to set, the Linux PTE value, and the additional CPU PTE bits which aren't encoded in the Linux PTE value. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] Add sys_*at syscallsRussell King2006-12-091-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | Later glibc requires the *at syscalls. Add them. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 4004/1: S3C24XX: UDC remove implict addition of VA to regsBen Dooks2006-12-081-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the implicit addition of a virtual address to the UDC registers. This should have been done by ioremap() in the driver, not by a static map. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] Handle HWCAP_VFP in VFP support codeRussell King2006-12-081-13/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't set HWCAP_VFP in the processor support file; not only does it depend on the processor features, but it also depends on the support code being present. Therefore, only set it if the support code detects that we have a VFP coprocessor attached. Also, move the VFP handling of the coprocessor access register into the VFP support code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | [PATCH] Optimize D-cache alias handling on forkRalf Baechle2006-12-131-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Virtually index, physically tagged cache architectures can get away without cache flushing when forking. This patch adds a new cache flushing function flush_cache_dup_mm(struct mm_struct *) which for the moment I've implemented to do the same thing on all architectures except on MIPS where it's a no-op. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | | | [PATCH] PM: Fix SMP races in the freezerRafael J. Wysocki2006-12-131-0/+2
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, to tell a task that it should go to the refrigerator, we set the PF_FREEZE flag for it and send a fake signal to it. Unfortunately there are two SMP-related problems with this approach. First, a task running on another CPU may be updating its flags while the freezer attempts to set PF_FREEZE for it and this may leave the task's flags in an inconsistent state. Second, there is a potential race between freeze_process() and refrigerator() in which freeze_process() running on one CPU is reading a task's PF_FREEZE flag while refrigerator() running on another CPU has just set PF_FROZEN for the same task and attempts to reset PF_FREEZE for it. If the refrigerator wins the race, freeze_process() will state that PF_FREEZE hasn't been set for the task and will set it unnecessarily, so the task will go to the refrigerator once again after it's been thawed. To solve first of these problems we need to stop using PF_FREEZE to tell tasks that they should go to the refrigerator. Instead, we can introduce a special TIF_*** flag and use it for this purpose, since it is allowed to change the other tasks' TIF_*** flags and there are special calls for it. To avoid the freeze_process()-refrigerator() race we can make freeze_process() to always check the task's PF_FROZEN flag after it's read its "freeze" flag. We should also make sure that refrigerator() will always reset the task's "freeze" flag after it's set PF_FROZEN for it. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Acked-by: Pavel Machek <pavel@ucw.cz> Cc: Russell King <rmk@arm.linux.org.uk> Cc: David Howells <dhowells@redhat.com> Cc: Andi Kleen <ak@muc.de> Cc: "Luck, Tony" <tony.luck@intel.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | | Merge branch 'i2c-for-linus' of git://jdelvare.pck.nerim.net/jdelvare-2.6Linus Torvalds2006-12-121-0/+67
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'i2c-for-linus' of git://jdelvare.pck.nerim.net/jdelvare-2.6: i2c: Fix OMAP clock prescaler to match the comment i2c: Refactor a kfree in i2c-dev i2c: Fix return value check in i2c-dev i2c: Enable PEC on more i2c-i801 devices i2c: Discard the i2c algo del_bus wrappers i2c: New ARM Versatile/Realview bus driver i2c: fix broken ds1337 initialization i2c: i2c-i801 documentation update i2c: Use the __ATTR macro where possible i2c: Whitespace cleanups i2c: Use put_user instead of copy_to_user where possible i2c: New Atmel AT91 bus driver i2c: Add support for nested i2c bus locking i2c: Cleanups to the i2c-nforce2 bus driver i2c: Add request/release_mem_region to i2c-ibm_iic bus driver i2c: New Philips PNX bus driver i2c: Delete the broken i2c-ite bus driver i2c: Update the list of driver IDs i2c: Fix documentation typos
| * | | i2c: New Philips PNX bus driverVitaly Wool2006-12-101-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New I2C bus driver for Philips ARM boards (Philips IP3204 I2C IP block). This I2C controller can be found on (at least) PNX010x, PNX52xx and PNX4008 Philips boards. Signed-off-by: Vitaly Wool <vitalywool@gmail.com> Signed-off-by: Jean Delvare <khali@linux-fr.org>
* | | | [PATCH] spi: stabilize PIO mode transfers on PXA2xx systemsStephen Street2006-12-101-4/+1
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stabilize PIO mode transfers against a range of word sizes and FIFO thresholds and fixes word size setup/override issues. 1) 16 and 32 bit DMA/PIO transfers broken due to timing differences. 2) Potential for bad transfer counts due to transfer size assumptions. 3) Setup function broken is multiple ways. 4) Per transfer bit_per_word changes break DMA setup in pump_tranfers. 5) False positive timeout are not errors. 6) Changes in pxa2xx_spi_chip not effective in calls to setup. 7) Timeout scaling wrong for PXA255 NSSP. 8) Driver leaks memory while busy during unloading. Known issues: SPI_CS_HIGH and SPI_LSB_FIRST settings in struct spi_device are not handled. Testing: This patch has been test against the "random length, random bits/word, random data (verified on loopback) and stepped baud rate by octaves (3.6MHz to 115kHz)" test. It is robust in PIO mode, using any combination of tx and rx thresholds, and also in DMA mode (which internally computes the thresholds). Much thanks to Ned Forrester for exhaustive reviews, fixes and testing. The driver is substantially better for his efforts. Signed-off-by: Stephen Street <stephen@streetfiresound.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | | [PATCH] s3c2410fb: Add support for STN displaysArnaud Patard (Rtp2006-12-081-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for stn displays on the s3c2410 arm SoC. The LCD type is choosen by a new field in the s3c2410fb_mach_info structure and its value is the value of the PNRMODE bits. This worth to be noted as a value of 0 means that you configure a 4 bit dual scan stn display. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Ben Dooks <ben-linux@fluff.org> Acked-by: James Simmons <jsimmons@infradead.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | | [PATCH] tty: preparatory structures for termios revampAlan Cox2006-12-081-0/+12
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to sort out our struct termios and add proper speed control we need to separate the kernel and user termios structures. Glibc is fine but the other libraries rely on the kernel exported struct termios and we need to extend this without breaking the ABI/API To do so we add a struct ktermios which is the kernel view of a termios structure and overlaps the struct termios with extra fields on the end for now. (That limitation will go away in later patches). Some platforms (eg alpha) planned ahead and thus use the same struct for both, others did not. This just adds the structures but does not use them, it seems a sensible splitting point for bisect if there are compile failures (not that I expect them) Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
* | Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2006-12-0777-964/+3252
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (76 commits) [ARM] 4002/1: S3C24XX: leave parent IRQs unmasked [ARM] 4001/1: S3C24XX: shorten reboot time [ARM] 3983/2: remove unused argument to __bug() [ARM] 4000/1: Osiris: add third serial port in [ARM] 3999/1: RX3715: suspend to RAM support [ARM] 3998/1: VR1000: LED platform devices [ARM] 3995/1: iop13xx: add iop13xx support [ARM] 3968/1: iop13xx: add iop13xx_defconfig [ARM] Update mach-types [ARM] Allow gcc to optimise arm_add_memory a little more [ARM] 3991/1: i.MX/MX1 high resolution time source [ARM] 3990/1: i.MX/MX1 more precise PLL decode [ARM] 3986/1: H1940: suspend to RAM support [ARM] 3985/1: ixp4xx clocksource cleanup [ARM] 3984/1: ixp4xx/nslu2: Fix disk LED numbering (take 2) [ARM] 3994/1: ixp23xx: fix handling of pci master aborts [ARM] 3981/1: sched_clock for PXA2xx [ARM] 3980/1: extend the ARM Versatile sched_clock implementation from 32 to 63 bit [ARM] 3979/1: extend the SA11x0 sched_clock implementation from 32 to 63 bit period [ARM] 3978/1: macro to provide a 63-bit value from a 32-bit hardware counter ...
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| *-------. \ [ARM] Merge individual ARM sub-treesRussell King2006-12-0777-964/+3252
| |\ \ \ \ \ \ | | | |_|_|_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge: Atmel AT91RM9200 and AT91SAM9260 changes General ARM developments Disconfiguous memory cleanups 64-bit/32-bit division and sched_clock extension patches EP93xx support changes IOP support changes Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | * [ARM] 3995/1: iop13xx: add iop13xx supportDan Williams2006-12-0714-0/+1078
| | |_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * [ARM] 3978/1: macro to provide a 63-bit value from a 32-bit hardware counterNicolas Pitre2006-12-071-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is done in a completely lockless fashion. Bits 0 to 31 of the count are provided by the hardware while bits 32 to 62 are stored in memory. The top bit in memory is used to synchronize with the hardware count half-period. When the top bit of both counters (hardware and in memory) differ then the memory is updated with a new value, incrementing it when the hardware counter wraps around. Because a word store in memory is atomic then the incremented value will always be in synch with the top bit indicating to any potential concurrent reader if the value in memory is up to date or not wrt the needed increment. And any race in updating the value in memory is harmless as the same value would be stored more than once. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | * [ARM] 3611/4: optimize do_div() when divisor is constantNicolas Pitre2006-12-071-1/+179
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On ARM all divisions have to be performed "manually". For 64-bit divisions that may take more than a hundred cycles in many cases. With 32-bit divisions gcc already use the recyprocal of constant divisors to perform a multiplication, but not with 64-bit divisions. Since the kernel is increasingly relying upon 64-bit divisions it is worth optimizing at least those cases where the divisor is a constant. This is what this patch does using plain C code that gets optimized away at compile time. For example, despite the amount of added C code, do_div(x, 10000) now produces the following assembly code (where x is assigned to r0-r1): adr r4, .L0 ldmia r4, {r4-r5} umull r2, r3, r4, r0 mov r2, #0 umlal r3, r2, r5, r0 umlal r3, r2, r4, r1 mov r3, #0 umlal r2, r3, r5, r1 mov r0, r2, lsr #11 orr r0, r0, r3, lsl #21 mov r1, r3, lsr #11 ... .L0: .word 948328779 .word 879609302 which is the fastest that can be done for any value of x in that case, many times faster than the __do_div64 code (except for the small x value space for which the result ends up being zero or a single bit). The fact that this code is generated inline produces a tiny increase in .text size, but not significant compared to the needed code around each __do_div64 call site this code is replacing. The algorithm used has been validated on a 16-bit scale for all possible values, and then recodified for 64-bit values. Furthermore I've been running it with the final BUG_ON() uncommented for over two months now with no problem. Note that this new code is compiled with gcc versions 4.0 or later. Earlier gcc versions proved themselves too problematic and only the original code is used with them. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | * [ARM] Clean up discontigmem supportRussell King2006-11-306-160/+54
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most architectures have fairly simple discontiguous memory - a simple set of successive regions each containing some memory. These can be described simply as a log2 of their maximum size, along with the base address of the first region and the number of regions. The base address is already described by PHYS_PFN_OFFSET, and the number of regions via the MAX_NUMNODES and the number of online nodes. If we then supply the log2 of their maximum size, all the other discontigmem macros can move into generic code. There is one exception: lh7a40x seems to have a more complicated setup; this is left alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 4001/1: S3C24XX: shorten reboot timeBen Dooks2006-12-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cut down the time between requesting a reboot and actually getting the reboot to happen by a quarter. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 3983/2: remove unused argument to __bug()Nicolas Pitre2006-12-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It appears that include/asm-arm/bug.h requires include/linux/stddef.h for the definition of NULL. It seems that stddef.h was always included indirectly in most cases, and that issue was properly fixed a while ago. Then commit 5047f09b56d0bc3c21aec9cb16de60283da645c6 incorrectly reverted change from commit ff10952a547dad934d9ed9afc5cf579ed1ccb53a (bad dwmw2) and the problem recently resurfaced. Because the third argument to __bug() is never used anyway, RMK suggested getting rid of it entirely instead of readding #include <linux/stddef.h> which this patch does. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 3991/1: i.MX/MX1 high resolution time sourcePavel Pisa2006-12-071-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enhanced resolution for time measurement functions. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 3986/1: H1940: suspend to RAM supportBen Dooks2006-12-071-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support to suspend and resume, using the H1940's bootloader Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 3984/1: ixp4xx/nslu2: Fix disk LED numbering (take 2)Rod Whitby2006-12-071-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes an error in the numbering of the disk LEDs on the Linksys NSLU2. The error crept in because the physical location of the LEDs has the Disk 2 LED *above* the Disk 1 LED. Thanks to Gordon Farquharson for reporting this. Signed-off-by: Rod Whitby <rod@whitby.id.au> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 3881/4: xscale: clean up cp0/cp1 handlingLennert Buytenhek2006-12-031-32/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XScale cores either have a DSP coprocessor (which contains a single 40 bit accumulator register), or an iWMMXt coprocessor (which contains eight 64 bit registers.) Because of the small amount of state in the DSP coprocessor, access to the DSP coprocessor (CP0) is always enabled, and DSP context switching is done unconditionally on every task switch. Access to the iWMMXt coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is first issued, and iWMMXt context switching is done lazily. CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will have iWMMXt support', but boards are supposed to select this config symbol by hand, and at least one pxa27x board doesn't get this right, so on that board, proc-xscale.S will incorrectly assume that we have a DSP coprocessor, enable CP0 on boot, and we will then only save the first iWMMXt register (wR0) on context switches, which is Bad. This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on might have iWMMXt support, and we will enable iWMMXt context switching if it does.' This means that with this patch, running a CONFIG_IWMMXT=n kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt state over context switches, and running a CONFIG_IWMMXT=y kernel on a non-iWMMXt capable CPU will still do DSP context save/restore. These changes should make iWMMXt work on PXA3xx, and as a side effect, enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined), as well as setting and using HWCAP_IWMMXT properly. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Acked-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 3971/1: xsc3: get rid of L_PTE_COHERENTLennert Buytenhek2006-12-011-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge L_PTE_COHERENT with L_PTE_SHARED and free up a L_PTE_* bit. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 3958/1: add platform device (pxa2xx-udc)to ixp4xxMilan Svoboda2006-12-011-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create include/asm-arm/arch-ixp4xx/udc.h and add platfrom device ixp4xx_udc_device into arch/arm/mach-ixp4xx/common.c. This allows us to use pxa2xx-udc on the ixp4xx platfrom. Both pxa2xx and ixp4xx use the same device controller. Signed-off-by:Milan Svoboda <msvoboda@ra.rockwell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 3911/2: Simplify alloc_thread_info on ARMPaul Gortmaker2006-11-301-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove ARM local cache of 4 struct thread_info. Can cause oops under certain circumstances. Russell indicated the original optimization was required on older kernels to avoid thread starvation on memory fragmentation, but may no longer be required. I've updated the patch to 19rc4 and ensured no <config.h> dain-bramage slipped in this time (sorry about that). Original description follows: I was given some test results which pointed to an Oops in alloc_thread_info (happened 2x), and after looking at the code, I see that ARM has its own local cache of 4 struct thread_info. There wasn't any clear (to me) synchronization between the alloc_thread_info and the free_thread_info. I looked over the other arch, and they all simply allocate them on an as needed basis, so I simplified the ARM to do the same, based on the other arch (e.g. PPC) and the folks doing the testing have indicated that this fixed the oops. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] Remove "translated" io macrosRussell King2006-11-301-26/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "translated" io macros were never really used. Remove them. Preserve the L7200 inb() and friends by defining the __io() macro, so that the generic versions can be used instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] Remove warnings for __io_pci and __arch_(get|put)*Russell King2006-11-301-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the last definitions of this macros have been removed, we can remove the warnings in asm/io.h. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] L7200: Remove deprecated __io_pci and __arch_(get|put)*Russell King2006-11-301-27/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These functions have been deprecated for quite some time, and in fact are no longer used. They just add to clutter. Remove them. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] Fix nommu buildRussell King2006-11-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix warnings and errors in arch/arm/mm for nommu build. Remove commented out function prototype in pgtable-nommu.h Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 3936/1: [Jornada7xx] - No use for jornada720.hKristoffer Ericson2006-11-301-42/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * We don't need this header anymore - there is no data we need to share this way. FB driver gets this data through a resources structure. MCU Driver api will go to a jornada720_mcu.h file. Signed-off-by: Filip Zyzniewski <filip.zyzniewski@tefnet.pl> Signed-off-by: Kristoffer Ericson <Kristoffer_e1@hotmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] Remove compatibility layer for ARM irqsRussell King2006-11-301-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | set_irq_chipdata -> set_irq_chip_data get_irq_chipdata -> get_irq_chip_data do_level_IRQ -> handle_level_irq do_edge_IRQ -> handle_edge_irq do_simple_IRQ -> handle_simple_irq irqdesc -> irq_desc irqchip -> irq_chip Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 3894/1: pxa27x: Update DCSR_EORINTR bit definition in DCSRstanley cai2006-11-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates a bit definition name to align with the PXA27x spec.EORINTR(End-Of-Receive Intr) bit in DCSR register (DMA Channel Control/Status Register) Signed-off-by: Stanley Cai <stanley.w.cai@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * [ARM] 3893/1: pxa27x: Update UDCISR1 bit definitionsstanley cai2006-11-301-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates several bit definitions name in UDCISR1 register. Signed-off-by: Stanley Cai <stanley.w.cai@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
generated by cgit v1.1 at 2024-12-26 01:37:03 +0000