From 167879ae8924540660b187d759956f316dd6e8fe Mon Sep 17 00:00:00 2001 From: viresh kumar Date: Wed, 16 Feb 2011 07:40:41 +0100 Subject: ARM: 6700/1: SPEAr: Correct SOC config base address for spear320 SPEAR320_SOC_CONFIG_BASE was wrong, causing the wrong registers to be accessed. Reviewed-by: Stanley Miao Signed-off-by: Viresh Kumar Signed-off-by: Russell King --- arch/arm/mach-spear3xx/include/mach/spear320.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm/mach-spear3xx/include') diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h index cacf17a..53677e4 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear320.h +++ b/arch/arm/mach-spear3xx/include/mach/spear320.h @@ -62,7 +62,7 @@ #define SPEAR320_SMII1_BASE 0xAB000000 #define SPEAR320_SMII1_SIZE 0x01000000 -#define SPEAR320_SOC_CONFIG_BASE 0xB4000000 +#define SPEAR320_SOC_CONFIG_BASE 0xB3000000 #define SPEAR320_SOC_CONFIG_SIZE 0x00000070 /* Interrupt registers offsets and masks */ #define INT_STS_MASK_REG 0x04 -- cgit v1.1 From f9324a85c10ee109022672ec72db9e2eb37050ee Mon Sep 17 00:00:00 2001 From: viresh kumar Date: Wed, 16 Feb 2011 07:40:28 +0100 Subject: ARM: 6677/1: SPEAr: add IOMEM(x) definition and update declaration of MISC_BASE Add IOMEM(x) definition, and use it with MISC_BASE for SPEAr platform. With this there is no need to typecast misc macros to (unsigned int *). Reviewed-by: Stanley Miao Signed-off-by: Viresh Kumar Signed-off-by: Russell King --- arch/arm/mach-spear3xx/include/mach/hardware.h | 2 + arch/arm/mach-spear3xx/include/mach/misc_regs.h | 136 ++++++++++++------------ 2 files changed, 70 insertions(+), 68 deletions(-) (limited to 'arch/arm/mach-spear3xx/include') diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h index 4a86e6a..490e86a 100644 --- a/arch/arm/mach-spear3xx/include/mach/hardware.h +++ b/arch/arm/mach-spear3xx/include/mach/hardware.h @@ -14,6 +14,8 @@ #ifndef __MACH_HARDWARE_H #define __MACH_HARDWARE_H +#include + /* Vitual to physical translation of statically mapped space */ #define IO_ADDRESS(x) (x | 0xF0000000) diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h index 38d767a..6c919e1 100644 --- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h +++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h @@ -16,14 +16,14 @@ #include -#define MISC_BASE VA_SPEAR3XX_ICM3_MISC_REG_BASE +#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) -#define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000)) -#define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004)) -#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008)) -#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C)) -#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010)) -#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014)) +#define SOC_CFG_CTR (MISC_BASE + 0x000) +#define DIAG_CFG_CTR (MISC_BASE + 0x004) +#define PLL1_CTR (MISC_BASE + 0x008) +#define PLL1_FRQ (MISC_BASE + 0x00C) +#define PLL1_MOD (MISC_BASE + 0x010) +#define PLL2_CTR (MISC_BASE + 0x014) /* PLL_CTR register masks */ #define PLL_ENABLE 2 #define PLL_MODE_SHIFT 4 @@ -33,7 +33,7 @@ #define PLL_MODE_DITH_DSB 2 #define PLL_MODE_DITH_SSB 3 -#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018)) +#define PLL2_FRQ (MISC_BASE + 0x018) /* PLL FRQ register masks */ #define PLL_DIV_N_SHIFT 0 #define PLL_DIV_N_MASK 0xFF @@ -44,16 +44,16 @@ #define PLL_DITH_FDBK_M_SHIFT 16 #define PLL_DITH_FDBK_M_MASK 0xFFFF -#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C)) -#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020)) -#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024)) +#define PLL2_MOD (MISC_BASE + 0x01C) +#define PLL_CLK_CFG (MISC_BASE + 0x020) +#define CORE_CLK_CFG (MISC_BASE + 0x024) /* CORE CLK CFG register masks */ #define PLL_HCLK_RATIO_SHIFT 10 #define PLL_HCLK_RATIO_MASK 0x3 #define HCLK_PCLK_RATIO_SHIFT 8 #define HCLK_PCLK_RATIO_MASK 0x3 -#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028)) +#define PERIP_CLK_CFG (MISC_BASE + 0x028) /* PERIP_CLK_CFG register masks */ #define UART_CLK_SHIFT 4 #define UART_CLK_MASK 0x1 @@ -66,7 +66,7 @@ #define AUX_CLK_PLL3_MASK 0 #define AUX_CLK_PLL1_MASK 1 -#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C)) +#define PERIP1_CLK_ENB (MISC_BASE + 0x02C) /* PERIP1_CLK_ENB register masks */ #define UART_CLK_ENB 3 #define SSP_CLK_ENB 5 @@ -85,33 +85,33 @@ #define USBH_CLK_ENB 25 #define C3_CLK_ENB 31 -#define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030)) -#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034)) -#define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038)) +#define SOC_CORE_ID (MISC_BASE + 0x030) +#define RAS_CLK_ENB (MISC_BASE + 0x034) +#define PERIP1_SOF_RST (MISC_BASE + 0x038) /* PERIP1_SOF_RST register masks */ #define JPEG_SOF_RST 8 -#define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C)) -#define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040)) -#define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044)) -#define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048)) -#define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C)) +#define SOC_USER_ID (MISC_BASE + 0x03C) +#define RAS_SOF_RST (MISC_BASE + 0x040) +#define PRSC1_CLK_CFG (MISC_BASE + 0x044) +#define PRSC2_CLK_CFG (MISC_BASE + 0x048) +#define PRSC3_CLK_CFG (MISC_BASE + 0x04C) /* gpt synthesizer register masks */ #define GPT_MSCALE_SHIFT 0 #define GPT_MSCALE_MASK 0xFFF #define GPT_NSCALE_SHIFT 12 #define GPT_NSCALE_MASK 0xF -#define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050)) -#define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054)) -#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C)) -#define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060)) -#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064)) -#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068)) -#define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C)) -#define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070)) -#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074)) -#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078)) +#define AMEM_CLK_CFG (MISC_BASE + 0x050) +#define EXPI_CLK_CFG (MISC_BASE + 0x054) +#define CLCD_CLK_SYNT (MISC_BASE + 0x05C) +#define FIRDA_CLK_SYNT (MISC_BASE + 0x060) +#define UART_CLK_SYNT (MISC_BASE + 0x064) +#define GMAC_CLK_SYNT (MISC_BASE + 0x068) +#define RAS1_CLK_SYNT (MISC_BASE + 0x06C) +#define RAS2_CLK_SYNT (MISC_BASE + 0x070) +#define RAS3_CLK_SYNT (MISC_BASE + 0x074) +#define RAS4_CLK_SYNT (MISC_BASE + 0x078) /* aux clk synthesiser register masks for irda to ras4 */ #define AUX_EQ_SEL_SHIFT 30 #define AUX_EQ_SEL_MASK 1 @@ -122,42 +122,42 @@ #define AUX_YSCALE_SHIFT 0 #define AUX_YSCALE_MASK 0xFFF -#define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C)) -#define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080)) -#define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084)) -#define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088)) -#define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C)) -#define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090)) -#define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094)) -#define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098)) -#define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C)) -#define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0)) -#define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4)) -#define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8)) -#define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC)) -#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0)) -#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4)) -#define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8)) -#define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC)) -#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0)) -#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4)) -#define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8)) -#define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC)) -#define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0)) -#define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4)) -#define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8)) -#define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC)) -#define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0)) -#define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4)) -#define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8)) -#define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC)) -#define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100)) -#define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104)) -#define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108)) -#define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C)) -#define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110)) -#define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114)) -#define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118)) -#define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C)) +#define ICM1_ARB_CFG (MISC_BASE + 0x07C) +#define ICM2_ARB_CFG (MISC_BASE + 0x080) +#define ICM3_ARB_CFG (MISC_BASE + 0x084) +#define ICM4_ARB_CFG (MISC_BASE + 0x088) +#define ICM5_ARB_CFG (MISC_BASE + 0x08C) +#define ICM6_ARB_CFG (MISC_BASE + 0x090) +#define ICM7_ARB_CFG (MISC_BASE + 0x094) +#define ICM8_ARB_CFG (MISC_BASE + 0x098) +#define ICM9_ARB_CFG (MISC_BASE + 0x09C) +#define DMA_CHN_CFG (MISC_BASE + 0x0A0) +#define USB2_PHY_CFG (MISC_BASE + 0x0A4) +#define GMAC_CFG_CTR (MISC_BASE + 0x0A8) +#define EXPI_CFG_CTR (MISC_BASE + 0x0AC) +#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0) +#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4) +#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8) +#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC) +#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0) +#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4) +#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8) +#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC) +#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0) +#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4) +#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8) +#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC) +#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0) +#define BIST1_CFG_CTR (MISC_BASE + 0x0F4) +#define BIST2_CFG_CTR (MISC_BASE + 0x0F8) +#define BIST3_CFG_CTR (MISC_BASE + 0x0FC) +#define BIST4_CFG_CTR (MISC_BASE + 0x100) +#define BIST5_CFG_CTR (MISC_BASE + 0x104) +#define BIST1_STS_RES (MISC_BASE + 0x108) +#define BIST2_STS_RES (MISC_BASE + 0x10C) +#define BIST3_STS_RES (MISC_BASE + 0x110) +#define BIST4_STS_RES (MISC_BASE + 0x114) +#define BIST5_STS_RES (MISC_BASE + 0x118) +#define SYSERR_CFG_CTR (MISC_BASE + 0x11C) #endif /* __MACH_MISC_REGS_H */ -- cgit v1.1 From 53688c51e412b7fd642e5c8eb8ba8ee19744c4ea Mon Sep 17 00:00:00 2001 From: viresh kumar Date: Wed, 16 Feb 2011 07:40:30 +0100 Subject: ARM: 6678/1: SPEAr: update padmux code - compile padmux only for spear3xx - padmux initialization code rearranged in evaluation board and machine files. Reviewed-by: Stanley Miao Signed-off-by: Viresh Kumar Signed-off-by: Russell King --- arch/arm/mach-spear3xx/include/mach/generic.h | 7 ------- 1 file changed, 7 deletions(-) (limited to 'arch/arm/mach-spear3xx/include') diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h index af7e02c..c16d2f8 100644 --- a/arch/arm/mach-spear3xx/include/mach/generic.h +++ b/arch/arm/mach-spear3xx/include/mach/generic.h @@ -40,7 +40,6 @@ void __init clk_init(void); void __init spear3xx_map_io(void); void __init spear3xx_init_irq(void); void __init spear3xx_init(void); -void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size); /* pad mux declarations */ #define PMX_FIRDA_MASK (1 << 14) @@ -133,8 +132,6 @@ extern struct pmx_dev pmx_telecom_sdio_4bit; extern struct pmx_dev pmx_telecom_sdio_8bit; extern struct pmx_dev pmx_gpio1; -void spear300_pmx_init(void); - /* Add spear300 machine function declarations here */ void __init spear300_init(void); @@ -154,8 +151,6 @@ extern struct pmx_dev pmx_fsmc; extern struct pmx_dev pmx_rs485_0_1; extern struct pmx_dev pmx_tdm0; -void spear310_pmx_init(void); - /* Add spear310 machine function declarations here */ void __init spear310_init(void); @@ -195,8 +190,6 @@ extern struct pmx_dev pmx_smii0; extern struct pmx_dev pmx_smii1; extern struct pmx_dev pmx_i2c1; -void spear320_pmx_init(void); - /* Add spear320 machine function declarations here */ void __init spear320_init(void); -- cgit v1.1 From 5c881d9ae9480171f01921585e1893863d7ab421 Mon Sep 17 00:00:00 2001 From: Shiraz Hashim Date: Wed, 16 Feb 2011 07:40:32 +0100 Subject: ARM: 6737/1: SPEAr: formalized timer support Move platform specific timer initialization code is moved into platform specific files. Reviewed-by: Jamie Iles Reviewed-by: Stanley Miao Signed-off-by: Shiraz Hashim Signed-off-by: Rajeev Kumar Signed-off-by: Viresh Kumar Signed-off-by: Russell King --- arch/arm/mach-spear3xx/include/mach/generic.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-spear3xx/include') diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h index c16d2f8..e7d2de8 100644 --- a/arch/arm/mach-spear3xx/include/mach/generic.h +++ b/arch/arm/mach-spear3xx/include/mach/generic.h @@ -33,10 +33,11 @@ /* Add spear3xx family device structure declarations here */ extern struct amba_device gpio_device; extern struct amba_device uart_device; -extern struct sys_timer spear_sys_timer; +extern struct sys_timer spear3xx_timer; /* Add spear3xx family function declarations here */ void __init clk_init(void); +void __init spear_setup_timer(void); void __init spear3xx_map_io(void); void __init spear3xx_init_irq(void); void __init spear3xx_init(void); -- cgit v1.1 From af89fd812b00a52c54a3b9b2290fae4d31c7be9a Mon Sep 17 00:00:00 2001 From: viresh kumar Date: Wed, 16 Feb 2011 07:40:39 +0100 Subject: ARM: 6703/1: SPEAr: update clk API support - Add support for divisor per parent clock - Add ENABLED_ON_INIT feature in clk - Add clk_set_rate(), round_rate_index & clk_round_rate() - Simplify clk_recalc functions - Add/update clock definitions Reviewed-by: Stanley Miao Signed-off-by: Viresh Kumar Signed-off-by: shiraz hashim Signed-off-by: Rajeev Kumar Signed-off-by: Russell King --- arch/arm/mach-spear3xx/include/mach/misc_regs.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-spear3xx/include') diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h index 6c919e1..0b93347 100644 --- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h +++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h @@ -63,8 +63,8 @@ #define GPT1_CLK_SHIFT 11 #define GPT2_CLK_SHIFT 12 #define GPT_CLK_MASK 0x1 -#define AUX_CLK_PLL3_MASK 0 -#define AUX_CLK_PLL1_MASK 1 +#define AUX_CLK_PLL3_VAL 0 +#define AUX_CLK_PLL1_VAL 1 #define PERIP1_CLK_ENB (MISC_BASE + 0x02C) /* PERIP1_CLK_ENB register masks */ @@ -113,6 +113,7 @@ #define RAS3_CLK_SYNT (MISC_BASE + 0x074) #define RAS4_CLK_SYNT (MISC_BASE + 0x078) /* aux clk synthesiser register masks for irda to ras4 */ +#define AUX_SYNT_ENB 31 #define AUX_EQ_SEL_SHIFT 30 #define AUX_EQ_SEL_MASK 1 #define AUX_EQ1_SEL 0 -- cgit v1.1 From 410782beba6aa75744881810ec0cdff4c66ca777 Mon Sep 17 00:00:00 2001 From: viresh kumar Date: Mon, 7 Mar 2011 05:57:01 +0100 Subject: ARM: 6787/1: SPEAr: Reorder #includes in .h & .c files. Order of inclusion of .h files must be: , , , . This patch corrects this ordering whereever it is not followed. Signed-off-by: Viresh Kumar Signed-off-by: Russell King --- arch/arm/mach-spear3xx/include/mach/entry-macro.S | 2 +- arch/arm/mach-spear3xx/include/mach/generic.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-spear3xx/include') diff --git a/arch/arm/mach-spear3xx/include/mach/entry-macro.S b/arch/arm/mach-spear3xx/include/mach/entry-macro.S index 947625d..e8e7dc0 100644 --- a/arch/arm/mach-spear3xx/include/mach/entry-macro.S +++ b/arch/arm/mach-spear3xx/include/mach/entry-macro.S @@ -11,9 +11,9 @@ * warranty of any kind, whether express or implied. */ +#include #include #include -#include .macro disable_fiq .endm diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h index e7d2de8..aaaa046 100644 --- a/arch/arm/mach-spear3xx/include/mach/generic.h +++ b/arch/arm/mach-spear3xx/include/mach/generic.h @@ -14,11 +14,11 @@ #ifndef __MACH_GENERIC_H #define __MACH_GENERIC_H -#include -#include #include #include #include +#include +#include #include /* spear3xx declarations */ -- cgit v1.1 From 02aa06bc49fdb1749f350649c46b74da50290414 Mon Sep 17 00:00:00 2001 From: viresh kumar Date: Mon, 7 Mar 2011 05:57:02 +0100 Subject: ARM: 6788/1: SPEAr: Include mach/hardware.h instead of mach/spear.h This patch makes inclusion of hardware.h and spear.h consistent over all spear variants. Now we will include hardware.h, wherever we need to use hardware macros. spear.h will be automatically included by hardware.h Signed-off-by: Viresh Kumar Signed-off-by: Russell King --- arch/arm/mach-spear3xx/include/mach/entry-macro.S | 1 - arch/arm/mach-spear3xx/include/mach/hardware.h | 1 + arch/arm/mach-spear3xx/include/mach/misc_regs.h | 2 +- arch/arm/mach-spear3xx/include/mach/spear.h | 1 - 4 files changed, 2 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-spear3xx/include') diff --git a/arch/arm/mach-spear3xx/include/mach/entry-macro.S b/arch/arm/mach-spear3xx/include/mach/entry-macro.S index e8e7dc0..53da422 100644 --- a/arch/arm/mach-spear3xx/include/mach/entry-macro.S +++ b/arch/arm/mach-spear3xx/include/mach/entry-macro.S @@ -13,7 +13,6 @@ #include #include -#include .macro disable_fiq .endm diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h index 490e86a..4660c0d 100644 --- a/arch/arm/mach-spear3xx/include/mach/hardware.h +++ b/arch/arm/mach-spear3xx/include/mach/hardware.h @@ -15,6 +15,7 @@ #define __MACH_HARDWARE_H #include +#include /* Vitual to physical translation of statically mapped space */ #define IO_ADDRESS(x) (x | 0xF0000000) diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h index 0b93347..5bd8cd8 100644 --- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h +++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h @@ -14,7 +14,7 @@ #ifndef __MACH_MISC_REGS_H #define __MACH_MISC_REGS_H -#include +#include #define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h index dcca856..8745802 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear.h +++ b/arch/arm/mach-spear3xx/include/mach/spear.h @@ -14,7 +14,6 @@ #ifndef __MACH_SPEAR3XX_H #define __MACH_SPEAR3XX_H -#include #include #include #include -- cgit v1.1 From 069580b831dba8da8a0751770ee2b2d7a43faf33 Mon Sep 17 00:00:00 2001 From: viresh kumar Date: Mon, 7 Mar 2011 05:57:03 +0100 Subject: ARM: 6789/1: SPEAr3xx: Rename sdio to sdhci Device name of SD/MMC/SDIO controller in linux is sdhci. To maintain consistency across all spear code, rename sdio to sdhci. Signed-off-by: Viresh Kumar Signed-off-by: Russell King --- arch/arm/mach-spear3xx/include/mach/generic.h | 8 ++++---- arch/arm/mach-spear3xx/include/mach/irqs.h | 4 ++-- arch/arm/mach-spear3xx/include/mach/spear300.h | 4 ++-- arch/arm/mach-spear3xx/include/mach/spear320.h | 6 +++--- 4 files changed, 11 insertions(+), 11 deletions(-) (limited to 'arch/arm/mach-spear3xx/include') diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h index aaaa046..8e30636 100644 --- a/arch/arm/mach-spear3xx/include/mach/generic.h +++ b/arch/arm/mach-spear3xx/include/mach/generic.h @@ -129,8 +129,8 @@ extern struct pmx_dev pmx_telecom_camera; extern struct pmx_dev pmx_telecom_dac; extern struct pmx_dev pmx_telecom_i2s; extern struct pmx_dev pmx_telecom_boot_pins; -extern struct pmx_dev pmx_telecom_sdio_4bit; -extern struct pmx_dev pmx_telecom_sdio_8bit; +extern struct pmx_dev pmx_telecom_sdhci_4bit; +extern struct pmx_dev pmx_telecom_sdhci_8bit; extern struct pmx_dev pmx_gpio1; /* Add spear300 machine function declarations here */ @@ -172,14 +172,14 @@ extern struct pmx_dev pmx_clcd; extern struct pmx_dev pmx_emi; extern struct pmx_dev pmx_fsmc; extern struct pmx_dev pmx_spp; -extern struct pmx_dev pmx_sdio; +extern struct pmx_dev pmx_sdhci; extern struct pmx_dev pmx_i2s; extern struct pmx_dev pmx_uart1; extern struct pmx_dev pmx_uart1_modem; extern struct pmx_dev pmx_uart2; extern struct pmx_dev pmx_touchscreen; extern struct pmx_dev pmx_can; -extern struct pmx_dev pmx_sdio_led; +extern struct pmx_dev pmx_sdhci_led; extern struct pmx_dev pmx_pwm0; extern struct pmx_dev pmx_pwm1; extern struct pmx_dev pmx_pwm2; diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h index 7f940b8..a1a7f48 100644 --- a/arch/arm/mach-spear3xx/include/mach/irqs.h +++ b/arch/arm/mach-spear3xx/include/mach/irqs.h @@ -69,7 +69,7 @@ #define IRQ_CLCD IRQ_GEN_RAS_3 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */ -#define IRQ_SDIO IRQ_INTRCOMM_RAS_ARM +#define IRQ_SDHCI IRQ_INTRCOMM_RAS_ARM /* GPIO pins virtual irqs */ #define SPEAR_GPIO_INT_BASE (VIRQ_START + 9) @@ -115,7 +115,7 @@ #define VIRQ_SPP (VIRQ_START + 2) /* IRQs sharing IRQ_GEN_RAS_2 */ -#define IRQ_SDIO IRQ_GEN_RAS_2 +#define IRQ_SDHCI IRQ_GEN_RAS_2 /* IRQs sharing IRQ_GEN_RAS_3 */ #define VIRQ_PLGPIO (VIRQ_START + 3) diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h index ccaa765..1059d5a 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear300.h +++ b/arch/arm/mach-spear3xx/include/mach/spear300.h @@ -39,8 +39,8 @@ #define SPEAR300_CLCD_BASE 0x60000000 #define SPEAR300_CLCD_SIZE 0x10000000 -#define SPEAR300_SDIO_BASE 0x70000000 -#define SPEAR300_SDIO_SIZE 0x10000000 +#define SPEAR300_SDHCI_BASE 0x70000000 +#define SPEAR300_SDHCI_SIZE 0x10000000 #define SPEAR300_NAND_0_BASE 0x80000000 #define SPEAR300_NAND_0_SIZE 0x04000000 diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h index 53677e4..1c9d310 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear320.h +++ b/arch/arm/mach-spear3xx/include/mach/spear320.h @@ -25,8 +25,8 @@ #define SPEAR320_I2S_BASE 0x60000000 #define SPEAR320_I2S_SIZE 0x10000000 -#define SPEAR320_SDIO_BASE 0x70000000 -#define SPEAR320_SDIO_SIZE 0x10000000 +#define SPEAR320_SDHCI_BASE 0x70000000 +#define SPEAR320_SDHCI_SIZE 0x10000000 #define SPEAR320_CLCD_BASE 0x90000000 #define SPEAR320_CLCD_SIZE 0x10000000 @@ -74,7 +74,7 @@ #define EMI_IRQ_MASK (1 << 7) #define CLCD_IRQ_MASK (1 << 8) #define SPP_IRQ_MASK (1 << 9) -#define SDIO_IRQ_MASK (1 << 10) +#define SDHCI_IRQ_MASK (1 << 10) #define CAN_U_IRQ_MASK (1 << 11) #define CAN_L_IRQ_MASK (1 << 12) #define UART1_IRQ_MASK (1 << 13) -- cgit v1.1 From 8fc4ef451eebc72d10c6987b59ec3316da62f02b Mon Sep 17 00:00:00 2001 From: viresh kumar Date: Mon, 7 Mar 2011 05:57:07 +0100 Subject: ARM: 6793/1: SPEAr: Remove unused *_SIZE macros from spear*.h files Now we used standard SZ_* macros instead of self defined *_SIZE macros. This patch removes all such unused *_SIZE macros for spear3xx & 6xx. Signed-off-by: Viresh Kumar Signed-off-by: Russell King --- arch/arm/mach-spear3xx/include/mach/spear.h | 63 -------------------------- arch/arm/mach-spear3xx/include/mach/spear300.h | 29 ------------ arch/arm/mach-spear3xx/include/mach/spear310.h | 14 +----- arch/arm/mach-spear3xx/include/mach/spear320.h | 32 +------------ 4 files changed, 2 insertions(+), 136 deletions(-) (limited to 'arch/arm/mach-spear3xx/include') diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h index 8745802..df60e30 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear.h +++ b/arch/arm/mach-spear3xx/include/mach/spear.h @@ -19,118 +19,55 @@ #include #define SPEAR3XX_ML_SDRAM_BASE 0x00000000 -#define SPEAR3XX_ML_SDRAM_SIZE 0x40000000 #define SPEAR3XX_ICM9_BASE 0xC0000000 -#define SPEAR3XX_ICM9_SIZE 0x10000000 /* ICM1 - Low speed connection */ #define SPEAR3XX_ICM1_2_BASE 0xD0000000 -#define SPEAR3XX_ICM1_2_SIZE 0x10000000 - #define SPEAR3XX_ICM1_UART_BASE 0xD0000000 #define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE) -#define SPEAR3XX_ICM1_UART_SIZE 0x00080000 - #define SPEAR3XX_ICM1_ADC_BASE 0xD0080000 -#define SPEAR3XX_ICM1_ADC_SIZE 0x00080000 - #define SPEAR3XX_ICM1_SSP_BASE 0xD0100000 -#define SPEAR3XX_ICM1_SSP_SIZE 0x00080000 - #define SPEAR3XX_ICM1_I2C_BASE 0xD0180000 -#define SPEAR3XX_ICM1_I2C_SIZE 0x00080000 - #define SPEAR3XX_ICM1_JPEG_BASE 0xD0800000 -#define SPEAR3XX_ICM1_JPEG_SIZE 0x00800000 - #define SPEAR3XX_ICM1_IRDA_BASE 0xD1000000 -#define SPEAR3XX_ICM1_IRDA_SIZE 0x00080000 - #define SPEAR3XX_ICM1_SRAM_BASE 0xD2800000 -#define SPEAR3XX_ICM1_SRAM_SIZE 0x05800000 /* ICM2 - Application Subsystem */ #define SPEAR3XX_ICM2_HWACCEL0_BASE 0xD8800000 -#define SPEAR3XX_ICM2_HWACCEL0_SIZE 0x00800000 - #define SPEAR3XX_ICM2_HWACCEL1_BASE 0xD9000000 -#define SPEAR3XX_ICM2_HWACCEL1_SIZE 0x00800000 /* ICM4 - High Speed Connection */ #define SPEAR3XX_ICM4_BASE 0xE0000000 -#define SPEAR3XX_ICM4_SIZE 0x08000000 - #define SPEAR3XX_ICM4_MII_BASE 0xE0800000 -#define SPEAR3XX_ICM4_MII_SIZE 0x00800000 - #define SPEAR3XX_ICM4_USBD_FIFO_BASE 0xE1000000 -#define SPEAR3XX_ICM4_USBD_FIFO_SIZE 0x00100000 - #define SPEAR3XX_ICM4_USBD_CSR_BASE 0xE1100000 -#define SPEAR3XX_ICM4_USBD_CSR_SIZE 0x00100000 - #define SPEAR3XX_ICM4_USBD_PLDT_BASE 0xE1200000 -#define SPEAR3XX_ICM4_USBD_PLDT_SIZE 0x00100000 - #define SPEAR3XX_ICM4_USB_EHCI0_1_BASE 0xE1800000 -#define SPEAR3XX_ICM4_USB_EHCI0_1_SIZE 0x00100000 - #define SPEAR3XX_ICM4_USB_OHCI0_BASE 0xE1900000 -#define SPEAR3XX_ICM4_USB_OHCI0_SIZE 0x00100000 - #define SPEAR3XX_ICM4_USB_OHCI1_BASE 0xE2100000 -#define SPEAR3XX_ICM4_USB_OHCI1_SIZE 0x00100000 - #define SPEAR3XX_ICM4_USB_ARB_BASE 0xE2800000 -#define SPEAR3XX_ICM4_USB_ARB_SIZE 0x00010000 /* ML1 - Multi Layer CPU Subsystem */ #define SPEAR3XX_ICM3_ML1_2_BASE 0xF0000000 -#define SPEAR3XX_ICM3_ML1_2_SIZE 0x0F000000 - #define SPEAR3XX_ML1_TMR_BASE 0xF0000000 -#define SPEAR3XX_ML1_TMR_SIZE 0x00100000 - #define SPEAR3XX_ML1_VIC_BASE 0xF1100000 #define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE) -#define SPEAR3XX_ML1_VIC_SIZE 0x00100000 /* ICM3 - Basic Subsystem */ #define SPEAR3XX_ICM3_SMEM_BASE 0xF8000000 -#define SPEAR3XX_ICM3_SMEM_SIZE 0x04000000 - #define SPEAR3XX_ICM3_SMI_CTRL_BASE 0xFC000000 -#define SPEAR3XX_ICM3_SMI_CTRL_SIZE 0x00200000 - #define SPEAR3XX_ICM3_DMA_BASE 0xFC400000 -#define SPEAR3XX_ICM3_DMA_SIZE 0x00200000 - #define SPEAR3XX_ICM3_SDRAM_CTRL_BASE 0xFC600000 -#define SPEAR3XX_ICM3_SDRAM_CTRL_SIZE 0x00200000 - #define SPEAR3XX_ICM3_TMR0_BASE 0xFC800000 -#define SPEAR3XX_ICM3_TMR0_SIZE 0x00080000 - #define SPEAR3XX_ICM3_WDT_BASE 0xFC880000 -#define SPEAR3XX_ICM3_WDT_SIZE 0x00080000 - #define SPEAR3XX_ICM3_RTC_BASE 0xFC900000 -#define SPEAR3XX_ICM3_RTC_SIZE 0x00080000 - #define SPEAR3XX_ICM3_GPIO_BASE 0xFC980000 -#define SPEAR3XX_ICM3_GPIO_SIZE 0x00080000 - #define SPEAR3XX_ICM3_SYS_CTRL_BASE 0xFCA00000 #define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE) -#define SPEAR3XX_ICM3_SYS_CTRL_SIZE 0x00080000 - #define SPEAR3XX_ICM3_MISC_REG_BASE 0xFCA80000 #define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE) -#define SPEAR3XX_ICM3_MISC_REG_SIZE 0x00080000 - #define SPEAR3XX_ICM3_TMR1_BASE 0xFCB00000 -#define SPEAR3XX_ICM3_TMR1_SIZE 0x00080000 /* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h index 1059d5a..8f96cc5 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear300.h +++ b/arch/arm/mach-spear3xx/include/mach/spear300.h @@ -18,10 +18,8 @@ /* Base address of various IPs */ #define SPEAR300_TELECOM_BASE 0x50000000 -#define SPEAR300_TELECOM_SIZE 0x10000000 /* Interrupt registers offsets and masks */ -#define SPEAR300_TELECOM_REG_SIZE 0x00010000 #define INT_ENB_MASK_REG 0x54 #define INT_STS_MASK_REG 0x58 #define IT_PERS_S_IRQ_MASK (1 << 0) @@ -37,46 +35,19 @@ #define SHIRQ_RAS1_MASK 0x1FF #define SPEAR300_CLCD_BASE 0x60000000 -#define SPEAR300_CLCD_SIZE 0x10000000 - #define SPEAR300_SDHCI_BASE 0x70000000 -#define SPEAR300_SDHCI_SIZE 0x10000000 - #define SPEAR300_NAND_0_BASE 0x80000000 -#define SPEAR300_NAND_0_SIZE 0x04000000 - #define SPEAR300_NAND_1_BASE 0x84000000 -#define SPEAR300_NAND_1_SIZE 0x04000000 - #define SPEAR300_NAND_2_BASE 0x88000000 -#define SPEAR300_NAND_2_SIZE 0x04000000 - #define SPEAR300_NAND_3_BASE 0x8c000000 -#define SPEAR300_NAND_3_SIZE 0x04000000 - #define SPEAR300_NOR_0_BASE 0x90000000 -#define SPEAR300_NOR_0_SIZE 0x01000000 - #define SPEAR300_NOR_1_BASE 0x91000000 -#define SPEAR300_NOR_1_SIZE 0x01000000 - #define SPEAR300_NOR_2_BASE 0x92000000 -#define SPEAR300_NOR_2_SIZE 0x01000000 - #define SPEAR300_NOR_3_BASE 0x93000000 -#define SPEAR300_NOR_3_SIZE 0x01000000 - #define SPEAR300_FSMC_BASE 0x94000000 -#define SPEAR300_FSMC_SIZE 0x05000000 - #define SPEAR300_SOC_CONFIG_BASE 0x99000000 -#define SPEAR300_SOC_CONFIG_SIZE 0x00000008 - #define SPEAR300_KEYBOARD_BASE 0xA0000000 -#define SPEAR300_KEYBOARD_SIZE 0x09000000 - #define SPEAR300_GPIO_BASE 0xA9000000 -#define SPEAR300_GPIO_SIZE 0x07000000 #endif /* __MACH_SPEAR300_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h index b27bb8a..4f58eb1 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear310.h +++ b/arch/arm/mach-spear3xx/include/mach/spear310.h @@ -17,29 +17,17 @@ #define __MACH_SPEAR310_H #define SPEAR310_NAND_BASE 0x40000000 -#define SPEAR310_NAND_SIZE 0x04000000 - #define SPEAR310_FSMC_BASE 0x44000000 -#define SPEAR310_FSMC_SIZE 0x01000000 - #define SPEAR310_UART1_BASE 0xB2000000 #define SPEAR310_UART2_BASE 0xB2080000 #define SPEAR310_UART3_BASE 0xB2100000 #define SPEAR310_UART4_BASE 0xB2180000 #define SPEAR310_UART5_BASE 0xB2200000 -#define SPEAR310_UART_SIZE 0x00080000 - #define SPEAR310_HDLC_BASE 0xB2800000 -#define SPEAR310_HDLC_SIZE 0x00800000 - #define SPEAR310_RS485_0_BASE 0xB3000000 -#define SPEAR310_RS485_0_SIZE 0x00800000 - #define SPEAR310_RS485_1_BASE 0xB3800000 -#define SPEAR310_RS485_1_SIZE 0x00800000 - #define SPEAR310_SOC_CONFIG_BASE 0xB4000000 -#define SPEAR310_SOC_CONFIG_SIZE 0x00000070 + /* Interrupt registers offsets and masks */ #define INT_STS_MASK_REG 0x04 #define SMII0_IRQ_MASK (1 << 0) diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h index 1c9d310..95bdb2e 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear320.h +++ b/arch/arm/mach-spear3xx/include/mach/spear320.h @@ -17,53 +17,23 @@ #define __MACH_SPEAR320_H #define SPEAR320_EMI_CTRL_BASE 0x40000000 -#define SPEAR320_EMI_CTRL_SIZE 0x08000000 - #define SPEAR320_FSMC_BASE 0x4C000000 -#define SPEAR320_FSMC_SIZE 0x01000000 - #define SPEAR320_I2S_BASE 0x60000000 -#define SPEAR320_I2S_SIZE 0x10000000 - #define SPEAR320_SDHCI_BASE 0x70000000 -#define SPEAR320_SDHCI_SIZE 0x10000000 - #define SPEAR320_CLCD_BASE 0x90000000 -#define SPEAR320_CLCD_SIZE 0x10000000 - #define SPEAR320_PAR_PORT_BASE 0xA0000000 -#define SPEAR320_PAR_PORT_SIZE 0x01000000 - #define SPEAR320_CAN0_BASE 0xA1000000 -#define SPEAR320_CAN0_SIZE 0x01000000 - #define SPEAR320_CAN1_BASE 0xA2000000 -#define SPEAR320_CAN1_SIZE 0x01000000 - #define SPEAR320_UART1_BASE 0xA3000000 #define SPEAR320_UART2_BASE 0xA4000000 -#define SPEAR320_UART_SIZE 0x01000000 - #define SPEAR320_SSP0_BASE 0xA5000000 -#define SPEAR320_SSP0_SIZE 0x01000000 - #define SPEAR320_SSP1_BASE 0xA6000000 -#define SPEAR320_SSP1_SIZE 0x01000000 - #define SPEAR320_I2C_BASE 0xA7000000 -#define SPEAR320_I2C_SIZE 0x01000000 - #define SPEAR320_PWM_BASE 0xA8000000 -#define SPEAR320_PWM_SIZE 0x01000000 - #define SPEAR320_SMII0_BASE 0xAA000000 -#define SPEAR320_SMII0_SIZE 0x01000000 - #define SPEAR320_SMII1_BASE 0xAB000000 -#define SPEAR320_SMII1_SIZE 0x01000000 - #define SPEAR320_SOC_CONFIG_BASE 0xB3000000 -#define SPEAR320_SOC_CONFIG_SIZE 0x00000070 + /* Interrupt registers offsets and masks */ #define INT_STS_MASK_REG 0x04 #define INT_CLR_MASK_REG 0x04 -- cgit v1.1 From 981a95d37126cdf09e1dba3884305c2e25375bfb Mon Sep 17 00:00:00 2001 From: Shiraz Hashim Date: Mon, 7 Mar 2011 05:57:08 +0100 Subject: ARM: 6794/1: SPEAr: Append UL to device address macros. Reviewed-by: Stanley Miao Signed-off-by: Shiraz Hashim Signed-off-by: Rajeev Kumar Signed-off-by: Viresh Kumar Signed-off-by: Russell King --- arch/arm/mach-spear3xx/include/mach/spear.h | 71 +++++++++++++------------- arch/arm/mach-spear3xx/include/mach/spear300.h | 30 +++++------ arch/arm/mach-spear3xx/include/mach/spear310.h | 22 ++++---- arch/arm/mach-spear3xx/include/mach/spear320.h | 35 +++++++------ 4 files changed, 80 insertions(+), 78 deletions(-) (limited to 'arch/arm/mach-spear3xx/include') diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h index df60e30..63fd983 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear.h +++ b/arch/arm/mach-spear3xx/include/mach/spear.h @@ -14,60 +14,61 @@ #ifndef __MACH_SPEAR3XX_H #define __MACH_SPEAR3XX_H +#include #include #include #include -#define SPEAR3XX_ML_SDRAM_BASE 0x00000000 +#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000) -#define SPEAR3XX_ICM9_BASE 0xC0000000 +#define SPEAR3XX_ICM9_BASE UL(0xC0000000) /* ICM1 - Low speed connection */ -#define SPEAR3XX_ICM1_2_BASE 0xD0000000 -#define SPEAR3XX_ICM1_UART_BASE 0xD0000000 +#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) +#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) #define VA_SPEAR3XX_ICM1_UART_BASE IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE) -#define SPEAR3XX_ICM1_ADC_BASE 0xD0080000 -#define SPEAR3XX_ICM1_SSP_BASE 0xD0100000 -#define SPEAR3XX_ICM1_I2C_BASE 0xD0180000 -#define SPEAR3XX_ICM1_JPEG_BASE 0xD0800000 -#define SPEAR3XX_ICM1_IRDA_BASE 0xD1000000 -#define SPEAR3XX_ICM1_SRAM_BASE 0xD2800000 +#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000) +#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) +#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000) +#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000) +#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000) +#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000) /* ICM2 - Application Subsystem */ -#define SPEAR3XX_ICM2_HWACCEL0_BASE 0xD8800000 -#define SPEAR3XX_ICM2_HWACCEL1_BASE 0xD9000000 +#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000) +#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000) /* ICM4 - High Speed Connection */ -#define SPEAR3XX_ICM4_BASE 0xE0000000 -#define SPEAR3XX_ICM4_MII_BASE 0xE0800000 -#define SPEAR3XX_ICM4_USBD_FIFO_BASE 0xE1000000 -#define SPEAR3XX_ICM4_USBD_CSR_BASE 0xE1100000 -#define SPEAR3XX_ICM4_USBD_PLDT_BASE 0xE1200000 -#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE 0xE1800000 -#define SPEAR3XX_ICM4_USB_OHCI0_BASE 0xE1900000 -#define SPEAR3XX_ICM4_USB_OHCI1_BASE 0xE2100000 -#define SPEAR3XX_ICM4_USB_ARB_BASE 0xE2800000 +#define SPEAR3XX_ICM4_BASE UL(0xE0000000) +#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000) +#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000) +#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000) +#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000) +#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000) +#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000) +#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000) +#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000) /* ML1 - Multi Layer CPU Subsystem */ -#define SPEAR3XX_ICM3_ML1_2_BASE 0xF0000000 -#define SPEAR3XX_ML1_TMR_BASE 0xF0000000 -#define SPEAR3XX_ML1_VIC_BASE 0xF1100000 +#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) +#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) +#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000) #define VA_SPEAR3XX_ML1_VIC_BASE IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE) /* ICM3 - Basic Subsystem */ -#define SPEAR3XX_ICM3_SMEM_BASE 0xF8000000 -#define SPEAR3XX_ICM3_SMI_CTRL_BASE 0xFC000000 -#define SPEAR3XX_ICM3_DMA_BASE 0xFC400000 -#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE 0xFC600000 -#define SPEAR3XX_ICM3_TMR0_BASE 0xFC800000 -#define SPEAR3XX_ICM3_WDT_BASE 0xFC880000 -#define SPEAR3XX_ICM3_RTC_BASE 0xFC900000 -#define SPEAR3XX_ICM3_GPIO_BASE 0xFC980000 -#define SPEAR3XX_ICM3_SYS_CTRL_BASE 0xFCA00000 +#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000) +#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) +#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) +#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000) +#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000) +#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000) +#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000) +#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000) +#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) #define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE) -#define SPEAR3XX_ICM3_MISC_REG_BASE 0xFCA80000 +#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) #define VA_SPEAR3XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE) -#define SPEAR3XX_ICM3_TMR1_BASE 0xFCB00000 +#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000) /* Debug uart for linux, will be used for debug and uncompress messages */ #define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h index 8f96cc5..c723515 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear300.h +++ b/arch/arm/mach-spear3xx/include/mach/spear300.h @@ -17,7 +17,7 @@ #define __MACH_SPEAR300_H /* Base address of various IPs */ -#define SPEAR300_TELECOM_BASE 0x50000000 +#define SPEAR300_TELECOM_BASE UL(0x50000000) /* Interrupt registers offsets and masks */ #define INT_ENB_MASK_REG 0x54 @@ -34,20 +34,20 @@ #define SHIRQ_RAS1_MASK 0x1FF -#define SPEAR300_CLCD_BASE 0x60000000 -#define SPEAR300_SDHCI_BASE 0x70000000 -#define SPEAR300_NAND_0_BASE 0x80000000 -#define SPEAR300_NAND_1_BASE 0x84000000 -#define SPEAR300_NAND_2_BASE 0x88000000 -#define SPEAR300_NAND_3_BASE 0x8c000000 -#define SPEAR300_NOR_0_BASE 0x90000000 -#define SPEAR300_NOR_1_BASE 0x91000000 -#define SPEAR300_NOR_2_BASE 0x92000000 -#define SPEAR300_NOR_3_BASE 0x93000000 -#define SPEAR300_FSMC_BASE 0x94000000 -#define SPEAR300_SOC_CONFIG_BASE 0x99000000 -#define SPEAR300_KEYBOARD_BASE 0xA0000000 -#define SPEAR300_GPIO_BASE 0xA9000000 +#define SPEAR300_CLCD_BASE UL(0x60000000) +#define SPEAR300_SDHCI_BASE UL(0x70000000) +#define SPEAR300_NAND_0_BASE UL(0x80000000) +#define SPEAR300_NAND_1_BASE UL(0x84000000) +#define SPEAR300_NAND_2_BASE UL(0x88000000) +#define SPEAR300_NAND_3_BASE UL(0x8c000000) +#define SPEAR300_NOR_0_BASE UL(0x90000000) +#define SPEAR300_NOR_1_BASE UL(0x91000000) +#define SPEAR300_NOR_2_BASE UL(0x92000000) +#define SPEAR300_NOR_3_BASE UL(0x93000000) +#define SPEAR300_FSMC_BASE UL(0x94000000) +#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000) +#define SPEAR300_KEYBOARD_BASE UL(0xA0000000) +#define SPEAR300_GPIO_BASE UL(0xA9000000) #endif /* __MACH_SPEAR300_H */ diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h index 4f58eb1..1e85347 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear310.h +++ b/arch/arm/mach-spear3xx/include/mach/spear310.h @@ -16,17 +16,17 @@ #ifndef __MACH_SPEAR310_H #define __MACH_SPEAR310_H -#define SPEAR310_NAND_BASE 0x40000000 -#define SPEAR310_FSMC_BASE 0x44000000 -#define SPEAR310_UART1_BASE 0xB2000000 -#define SPEAR310_UART2_BASE 0xB2080000 -#define SPEAR310_UART3_BASE 0xB2100000 -#define SPEAR310_UART4_BASE 0xB2180000 -#define SPEAR310_UART5_BASE 0xB2200000 -#define SPEAR310_HDLC_BASE 0xB2800000 -#define SPEAR310_RS485_0_BASE 0xB3000000 -#define SPEAR310_RS485_1_BASE 0xB3800000 -#define SPEAR310_SOC_CONFIG_BASE 0xB4000000 +#define SPEAR310_NAND_BASE UL(0x40000000) +#define SPEAR310_FSMC_BASE UL(0x44000000) +#define SPEAR310_UART1_BASE UL(0xB2000000) +#define SPEAR310_UART2_BASE UL(0xB2080000) +#define SPEAR310_UART3_BASE UL(0xB2100000) +#define SPEAR310_UART4_BASE UL(0xB2180000) +#define SPEAR310_UART5_BASE UL(0xB2200000) +#define SPEAR310_HDLC_BASE UL(0xB2800000) +#define SPEAR310_RS485_0_BASE UL(0xB3000000) +#define SPEAR310_RS485_1_BASE UL(0xB3800000) +#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000) /* Interrupt registers offsets and masks */ #define INT_STS_MASK_REG 0x04 diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h index 95bdb2e..940f0d8 100644 --- a/arch/arm/mach-spear3xx/include/mach/spear320.h +++ b/arch/arm/mach-spear3xx/include/mach/spear320.h @@ -16,23 +16,24 @@ #ifndef __MACH_SPEAR320_H #define __MACH_SPEAR320_H -#define SPEAR320_EMI_CTRL_BASE 0x40000000 -#define SPEAR320_FSMC_BASE 0x4C000000 -#define SPEAR320_I2S_BASE 0x60000000 -#define SPEAR320_SDHCI_BASE 0x70000000 -#define SPEAR320_CLCD_BASE 0x90000000 -#define SPEAR320_PAR_PORT_BASE 0xA0000000 -#define SPEAR320_CAN0_BASE 0xA1000000 -#define SPEAR320_CAN1_BASE 0xA2000000 -#define SPEAR320_UART1_BASE 0xA3000000 -#define SPEAR320_UART2_BASE 0xA4000000 -#define SPEAR320_SSP0_BASE 0xA5000000 -#define SPEAR320_SSP1_BASE 0xA6000000 -#define SPEAR320_I2C_BASE 0xA7000000 -#define SPEAR320_PWM_BASE 0xA8000000 -#define SPEAR320_SMII0_BASE 0xAA000000 -#define SPEAR320_SMII1_BASE 0xAB000000 -#define SPEAR320_SOC_CONFIG_BASE 0xB3000000 +#define SPEAR320_EMI_CTRL_BASE UL(0x40000000) +#define SPEAR320_FSMC_BASE UL(0x4C000000) +#define SPEAR320_NAND_BASE UL(0x50000000) +#define SPEAR320_I2S_BASE UL(0x60000000) +#define SPEAR320_SDHCI_BASE UL(0x70000000) +#define SPEAR320_CLCD_BASE UL(0x90000000) +#define SPEAR320_PAR_PORT_BASE UL(0xA0000000) +#define SPEAR320_CAN0_BASE UL(0xA1000000) +#define SPEAR320_CAN1_BASE UL(0xA2000000) +#define SPEAR320_UART1_BASE UL(0xA3000000) +#define SPEAR320_UART2_BASE UL(0xA4000000) +#define SPEAR320_SSP0_BASE UL(0xA5000000) +#define SPEAR320_SSP1_BASE UL(0xA6000000) +#define SPEAR320_I2C_BASE UL(0xA7000000) +#define SPEAR320_PWM_BASE UL(0xA8000000) +#define SPEAR320_SMII0_BASE UL(0xAA000000) +#define SPEAR320_SMII1_BASE UL(0xAB000000) +#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000) /* Interrupt registers offsets and masks */ #define INT_STS_MASK_REG 0x04 -- cgit v1.1