diff options
Diffstat (limited to 'arch/arm/mach-omap2/include/mach')
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/barriers.h | 48 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h | 57 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h | 8 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/dmm-44xx.h | 363 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/dmm.h | 164 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/emif-44xx.h | 526 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/emif.h | 268 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/id.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/lpddr2-elpida.h | 23 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/lpddr2-jedec.h | 149 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/omap-wakeupgen.h | 41 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/omap4-common.h | 141 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/omap_fiq_debugger.h | 36 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/include/mach/tiler.h | 513 |
14 files changed, 2315 insertions, 23 deletions
diff --git a/arch/arm/mach-omap2/include/mach/barriers.h b/arch/arm/mach-omap2/include/mach/barriers.h new file mode 100644 index 0000000..aa72a33 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/barriers.h @@ -0,0 +1,48 @@ +/* + * OMAP memory barrier header. + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __MACH_BARRIERS_H +#define __MACH_BARRIERS_H + +#include <linux/types.h> + +/* provide func ptr so to allow safe calling at any point */ +struct omap_bus_post_fns { + void (*sync)(void); +}; + +extern struct omap_bus_post_fns omap_bus_post; + +#ifdef CONFIG_ARCH_OMAP4 +static inline void bus_sync(void) +{ + omap_bus_post.sync(); +} +#else +static inline void bus_sync(void) +{ } +#endif + +#define rmb() dsb() +#define wmb() do { dsb(); outer_sync(); bus_sync(); } while (0) +#define mb() wmb() + +#endif /* __MACH_BARRIERS_H */ diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h index 2f7ac70..58983a1 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h @@ -163,6 +163,7 @@ /* STD_FUSE_OPP_BGAP */ #define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0 #define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0) +#define OMAP4_STD_FUSE_OPP_BGAP_MASK_LSB (0xffff << 16) /* STD_FUSE_OPP_DPLL_0 */ #define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0 @@ -257,18 +258,50 @@ #define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0) /* TEMP_SENSOR */ -#define OMAP4_BGAP_TEMPSOFF_SHIFT 12 -#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12) -#define OMAP4_BGAP_TSHUT_SHIFT 11 -#define OMAP4_BGAP_TSHUT_MASK (1 << 11) -#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10 -#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10) -#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9 -#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9) -#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8 -#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8) -#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0 -#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0) +#define OMAP4_BGAP_TEMPSOFF_SHIFT 13 +#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 13) +#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 12 +#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 12) +#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 11 +#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 11) +#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 10 +#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 10) +#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0 +#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0) + +/* BANDGAP_CTRL */ +#define OMAP4_SINGLE_MODE_SHIFT 31 +#define OMAP4_SINGLE_MODE_MASK (1 << 31) +#define OMAP4_MASK_HOT_SHIFT 1 +#define OMAP4_MASK_HOT_MASK (1 << 1) +#define OMAP4_MASK_COLD_SHIFT 0 +#define OMAP4_MASK_COLD_MASK (1 << 0) + +/* BANDGAP_COUNTER */ +#define OMAP4_COUNTER_SHIFT 0 +#define OMAP4_COUNTER_MASK (0xffffff << 0) + +/* BANDGAP_THRESHOLD */ +#define OMAP4_T_HOT_SHIFT 16 +#define OMAP4_T_HOT_MASK (0x3ff << 16) +#define OMAP4_T_COLD_SHIFT 0 +#define OMAP4_T_COLD_MASK (0x3ff << 0) + +/* TSHUT_THRESHOLD */ +#define OMAP4_TSHUT_HOT_SHIFT 16 +#define OMAP4_TSHUT_HOT_MASK (0x3ff << 16) +#define OMAP4_TSHUT_COLD_SHIFT 0 +#define OMAP4_TSHUT_COLD_MASK (0x3ff << 0) + +/* BANDGAP_STATUS */ +#define OMAP4_CLEAN_STOP_SHIFT 3 +#define OMAP4_CLEAN_STOP_MASK (1 << 3) +#define OMAP4_BGAP_ALERT_SHIFT 2 +#define OMAP4_BGAP_ALERT_MASK (1 << 2) +#define OMAP4_HOT_FLAG_SHIFT 1 +#define OMAP4_HOT_FLAG_MASK (1 << 1) +#define OMAP4_COLD_FLAG_SHIFT 0 +#define OMAP4_COLD_FLAG_MASK (1 << 0) /* DPLL_NWELL_TRIM_0 */ #define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29 diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h index c88420d..852a3a9 100644 --- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h +++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h @@ -1185,6 +1185,14 @@ #define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13) #define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12 #define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12) +#define OMAP4_LPDDR21_VREF_EN_CA_SHIFT 3 +#define OMAP4_LPDDR21_VREF_EN_CA_MASK (1 << 3) +#define OMAP4_LPDDR21_VREF_EN_DQ_SHIFT 2 +#define OMAP4_LPDDR21_VREF_EN_DQ_MASK (1 << 2) +#define OMAP4_LPDDR21_VREF_AUTO_EN_CA_SHIFT 1 +#define OMAP4_LPDDR21_VREF_AUTO_EN_CA_MASK (1 << 1) +#define OMAP4_LPDDR21_VREF_AUTO_EN_DQ_SHIFT 0 +#define OMAP4_LPDDR21_VREF_AUTO_EN_DQ_MASK (1 << 0) /* CONTROL_LPDDR2IO2_0 */ #define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30 diff --git a/arch/arm/mach-omap2/include/mach/dmm-44xx.h b/arch/arm/mach-omap2/include/mach/dmm-44xx.h new file mode 100644 index 0000000..c25dda5 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/dmm-44xx.h @@ -0,0 +1,363 @@ +/* + * OMAP44xx DMM_CORE registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * Santosh Shilimkar (santosh.shilimkar@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_DMM_CORE_44XX_H +#define __ARCH_ARM_MACH_OMAP2_DMM_CORE_44XX_H + + +/* Base address */ +#define OMAP44XX_DMM__DMM 0x4e000000 + +/* Registers offset */ +#define OMAP44XX_DMM_REVISION 0x0000 +#define OMAP44XX_DMM_HWINFO 0x0004 +#define OMAP44XX_DMM_LISA_HWINFO 0x0008 +#define OMAP44XX_DMM_SYSCONFIG 0x0010 +#define OMAP44XX_DMM_LISA_LOCK 0x001c +#define OMAP44XX_DMM_LISA_MAP 0x0040 +#define OMAP44XX_DMM_TILER_HWINFO 0x0208 +#define OMAP44XX_DMM_TILER_OR 0x0220 +#define OMAP44XX_DMM_PAT_HWINFO 0x0408 +#define OMAP44XX_DMM_PAT_GEOMETRY 0x040c +#define OMAP44XX_DMM_PAT_CONFIG 0x0410 +#define OMAP44XX_DMM_PAT_VIEW 0x0420 +#define OMAP44XX_DMM_PAT_VIEW_MAP 0x0440 +#define OMAP44XX_DMM_PAT_VIEW_MAP_BASE 0x0460 +#define OMAP44XX_DMM_PAT_IRQ_EOI 0x0478 +#define OMAP44XX_DMM_PAT_IRQSTATUS_RAW 0x0480 +#define OMAP44XX_DMM_PAT_IRQSTATUS 0x0490 +#define OMAP44XX_DMM_PAT_IRQENABLE_SET 0x04a0 +#define OMAP44XX_DMM_PAT_IRQENABLE_CLR 0x04b0 +#define OMAP44XX_DMM_PAT_STATUS 0x04c0 +#define OMAP44XX_DMM_PAT_DESCR 0x0500 +#define OMAP44XX_DMM_PAT_AREA 0x0504 +#define OMAP44XX_DMM_PAT_CTRL 0x0508 +#define OMAP44XX_DMM_PAT_DATA 0x050c +#define OMAP44XX_DMM_PEG_HWINFO 0x0608 +#define OMAP44XX_DMM_PEG_PRIO 0x0620 +#define OMAP44XX_DMM_PEG_PRIO_PAT 0x0640 + +/* Registers shifts and masks */ + +/* DMM_REVISION */ +#define OMAP44XX_SCHEME_SHIFT 30 +#define OMAP44XX_SCHEME_MASK (0x3 << 30) +#define OMAP44XX_FUNC_SHIFT 16 +#define OMAP44XX_FUNC_MASK (0xfff << 16) +#define OMAP44XX_R_RTL_SHIFT 11 +#define OMAP44XX_R_RTL_MASK (0x1f << 11) +#define OMAP44XX_X_MAJOR_SHIFT 8 +#define OMAP44XX_X_MAJOR_MASK (0x7 << 8) +#define OMAP44XX_CUSTOM_SHIFT 6 +#define OMAP44XX_CUSTOM_MASK (0x3 << 6) +#define OMAP44XX_Y_MINOR_SHIFT 0 +#define OMAP44XX_Y_MINOR_MASK (0x3f << 0) + +/* DMM_HWINFO */ +#define OMAP44XX_ROBIN_CNT_SHIFT 16 +#define OMAP44XX_ROBIN_CNT_MASK (0xf << 16) +#define OMAP44XX_ELLA_CNT_SHIFT 8 +#define OMAP44XX_ELLA_CNT_MASK (0xf << 8) +#define OMAP44XX_TILER_CNT_SHIFT 0 +#define OMAP44XX_TILER_CNT_MASK (0xf << 0) + +/* DMM_LISA_HWINFO */ +#define OMAP44XX_SDRC_CNT_SHIFT 8 +#define OMAP44XX_SDRC_CNT_MASK (0xf << 8) +#define OMAP44XX_SECTION_CNT_SHIFT 0 +#define OMAP44XX_SECTION_CNT_MASK (0x1f << 0) + +/* DMM_SYSCONFIG */ +#define OMAP44XX_IDLE_MODE_SHIFT 2 +#define OMAP44XX_IDLE_MODE_MASK (0x3 << 2) + +/* DMM_LISA_LOCK */ +#define OMAP44XX_LOCK_SHIFT 0 +#define OMAP44XX_LOCK_MASK (1 << 0) + +/* DMM_LISA_MAP */ +#define OMAP44XX_SYS_ADDR_SHIFT 24 +#define OMAP44XX_SYS_ADDR_MASK (0xff << 24) +#define OMAP44XX_SYS_SIZE_SHIFT 20 +#define OMAP44XX_SYS_SIZE_MASK (0x7 << 20) +#define OMAP44XX_SDRC_INTL_SHIFT 18 +#define OMAP44XX_SDRC_INTL_MASK (0x3 << 18) +#define OMAP44XX_SDRC_ADDRSPC_SHIFT 16 +#define OMAP44XX_SDRC_ADDRSPC_MASK (0x3 << 16) +#define OMAP44XX_SDRC_MAP_SHIFT 8 +#define OMAP44XX_SDRC_MAP_MASK (0x3 << 8) +#define OMAP44XX_SDRC_ADDR_SHIFT 0 +#define OMAP44XX_SDRC_ADDR_MASK (0xff << 0) + +/* DMM_TILER_HWINFO */ +#define OMAP44XX_OR_CNT_SHIFT 0 +#define OMAP44XX_OR_CNT_MASK (0x7f << 0) + +/* DMM_TILER_OR */ +#define OMAP44XX_W7_SHIFT 31 +#define OMAP44XX_W7_MASK (1 << 31) +#define OMAP44XX_OR7_SHIFT 28 +#define OMAP44XX_OR7_MASK (0x7 << 28) +#define OMAP44XX_W6_SHIFT 27 +#define OMAP44XX_W6_MASK (1 << 27) +#define OMAP44XX_OR6_SHIFT 24 +#define OMAP44XX_OR6_MASK (0x7 << 24) +#define OMAP44XX_W5_SHIFT 23 +#define OMAP44XX_W5_MASK (1 << 23) +#define OMAP44XX_OR5_SHIFT 20 +#define OMAP44XX_OR5_MASK (0x7 << 20) +#define OMAP44XX_W4_SHIFT 19 +#define OMAP44XX_W4_MASK (1 << 19) +#define OMAP44XX_OR4_SHIFT 16 +#define OMAP44XX_OR4_MASK (0x7 << 16) +#define OMAP44XX_W3_SHIFT 15 +#define OMAP44XX_W3_MASK (1 << 15) +#define OMAP44XX_OR3_SHIFT 12 +#define OMAP44XX_OR3_MASK (0x7 << 12) +#define OMAP44XX_W2_SHIFT 11 +#define OMAP44XX_W2_MASK (1 << 11) +#define OMAP44XX_OR2_SHIFT 8 +#define OMAP44XX_OR2_MASK (0x7 << 8) +#define OMAP44XX_W1_SHIFT 7 +#define OMAP44XX_W1_MASK (1 << 7) +#define OMAP44XX_OR1_SHIFT 4 +#define OMAP44XX_OR1_MASK (0x7 << 4) +#define OMAP44XX_W0_SHIFT 3 +#define OMAP44XX_W0_MASK (1 << 3) +#define OMAP44XX_OR0_SHIFT 0 +#define OMAP44XX_OR0_MASK (0x7 << 0) + +/* DMM_PAT_HWINFO */ +#define OMAP44XX_ENGINE_CNT_SHIFT 24 +#define OMAP44XX_ENGINE_CNT_MASK (0x1f << 24) +#define OMAP44XX_LUT_CNT_SHIFT 16 +#define OMAP44XX_LUT_CNT_MASK (0x1f << 16) +#define OMAP44XX_VIEW_MAP_CNT_SHIFT 8 +#define OMAP44XX_VIEW_MAP_CNT_MASK (0xf << 8) +#define OMAP44XX_VIEW_CNT_SHIFT 0 +#define OMAP44XX_VIEW_CNT_MASK (0x7f << 0) + +/* DMM_PAT_GEOMETRY */ +#define OMAP44XX_CONT_HGHT_SHIFT 24 +#define OMAP44XX_CONT_HGHT_MASK (0x7 << 24) +#define OMAP44XX_CONT_WDTH_SHIFT 16 +#define OMAP44XX_CONT_WDTH_MASK (0xf << 16) +#define OMAP44XX_ADDR_RANGE_SHIFT 8 +#define OMAP44XX_ADDR_RANGE_MASK (0x3f << 8) +#define OMAP44XX_PAGE_SZ_SHIFT 0 +#define OMAP44XX_PAGE_SZ_MASK (0x1f << 0) + +/* DMM_PAT_CONFIG */ +#define OMAP44XX_MODE3_SHIFT 3 +#define OMAP44XX_MODE3_MASK (1 << 3) +#define OMAP44XX_MODE2_SHIFT 2 +#define OMAP44XX_MODE2_MASK (1 << 2) +#define OMAP44XX_MODE1_SHIFT 1 +#define OMAP44XX_MODE1_MASK (1 << 1) +#define OMAP44XX_MODE0_SHIFT 0 +#define OMAP44XX_MODE0_MASK (1 << 0) + +/* DMM_PAT_VIEW */ +#define OMAP44XX_V7_SHIFT 28 +#define OMAP44XX_V7_MASK (0x3 << 28) +#define OMAP44XX_V6_SHIFT 24 +#define OMAP44XX_V6_MASK (0x3 << 24) +#define OMAP44XX_V5_SHIFT 20 +#define OMAP44XX_V5_MASK (0x3 << 20) +#define OMAP44XX_V4_SHIFT 16 +#define OMAP44XX_V4_MASK (0x3 << 16) +#define OMAP44XX_V3_SHIFT 12 +#define OMAP44XX_V3_MASK (0x3 << 12) +#define OMAP44XX_V2_SHIFT 8 +#define OMAP44XX_V2_MASK (0x3 << 8) +#define OMAP44XX_V1_SHIFT 4 +#define OMAP44XX_V1_MASK (0x3 << 4) +#define OMAP44XX_V0_SHIFT 0 +#define OMAP44XX_V0_MASK (0x3 << 0) + +/* DMM_PAT_VIEW_MAP */ +#define OMAP44XX_ACCESS_PAGE_SHIFT 31 +#define OMAP44XX_ACCESS_PAGE_MASK (1 << 31) +#define OMAP44XX_CONT_PAGE_SHIFT 24 +#define OMAP44XX_CONT_PAGE_MASK (0xf << 24) +#define OMAP44XX_ACCESS_32_SHIFT 23 +#define OMAP44XX_ACCESS_32_MASK (1 << 23) +#define OMAP44XX_CONT_32_SHIFT 16 +#define OMAP44XX_CONT_32_MASK (0xf << 16) +#define OMAP44XX_ACCESS_16_SHIFT 15 +#define OMAP44XX_ACCESS_16_MASK (1 << 15) +#define OMAP44XX_CONT_16_SHIFT 8 +#define OMAP44XX_CONT_16_MASK (0xf << 8) +#define OMAP44XX_ACCESS_8_SHIFT 7 +#define OMAP44XX_ACCESS_8_MASK (1 << 7) +#define OMAP44XX_CONT_8_SHIFT 0 +#define OMAP44XX_CONT_8_MASK (0xf << 0) + +/* DMM_PAT_VIEW_MAP_BASE */ +#define OMAP44XX_BASE_ADDR_SHIFT 31 +#define OMAP44XX_BASE_ADDR_MASK (1 << 31) + +/* DMM_PAT_IRQ_EOI */ +#define OMAP44XX_EOI_SHIFT 0 +#define OMAP44XX_EOI_MASK (1 << 0) + +/* DMM_PAT_IRQSTATUS_RAW */ +#define OMAP44XX_ERR_LUT_MISS3_SHIFT 31 +#define OMAP44XX_ERR_LUT_MISS3_MASK (1 << 31) +#define OMAP44XX_ERR_UPD_DATA3_SHIFT 30 +#define OMAP44XX_ERR_UPD_DATA3_MASK (1 << 30) +#define OMAP44XX_ERR_UPD_CTRL3_SHIFT 29 +#define OMAP44XX_ERR_UPD_CTRL3_MASK (1 << 29) +#define OMAP44XX_ERR_UPD_AREA3_SHIFT 28 +#define OMAP44XX_ERR_UPD_AREA3_MASK (1 << 28) +#define OMAP44XX_ERR_INV_DATA3_SHIFT 27 +#define OMAP44XX_ERR_INV_DATA3_MASK (1 << 27) +#define OMAP44XX_ERR_INV_DSC3_SHIFT 26 +#define OMAP44XX_ERR_INV_DSC3_MASK (1 << 26) +#define OMAP44XX_FILL_LST3_SHIFT 25 +#define OMAP44XX_FILL_LST3_MASK (1 << 25) +#define OMAP44XX_FILL_DSC3_SHIFT 24 +#define OMAP44XX_FILL_DSC3_MASK (1 << 24) +#define OMAP44XX_ERR_LUT_MISS2_SHIFT 23 +#define OMAP44XX_ERR_LUT_MISS2_MASK (1 << 23) +#define OMAP44XX_ERR_UPD_DATA2_SHIFT 22 +#define OMAP44XX_ERR_UPD_DATA2_MASK (1 << 22) +#define OMAP44XX_ERR_UPD_CTRL2_SHIFT 21 +#define OMAP44XX_ERR_UPD_CTRL2_MASK (1 << 21) +#define OMAP44XX_ERR_UPD_AREA2_SHIFT 20 +#define OMAP44XX_ERR_UPD_AREA2_MASK (1 << 20) +#define OMAP44XX_ERR_INV_DATA2_SHIFT 19 +#define OMAP44XX_ERR_INV_DATA2_MASK (1 << 19) +#define OMAP44XX_ERR_INV_DSC2_SHIFT 18 +#define OMAP44XX_ERR_INV_DSC2_MASK (1 << 18) +#define OMAP44XX_FILL_LST2_SHIFT 17 +#define OMAP44XX_FILL_LST2_MASK (1 << 17) +#define OMAP44XX_FILL_DSC2_SHIFT 16 +#define OMAP44XX_FILL_DSC2_MASK (1 << 16) +#define OMAP44XX_ERR_LUT_MISS1_SHIFT 15 +#define OMAP44XX_ERR_LUT_MISS1_MASK (1 << 15) +#define OMAP44XX_ERR_UPD_DATA1_SHIFT 14 +#define OMAP44XX_ERR_UPD_DATA1_MASK (1 << 14) +#define OMAP44XX_ERR_UPD_CTRL1_SHIFT 13 +#define OMAP44XX_ERR_UPD_CTRL1_MASK (1 << 13) +#define OMAP44XX_ERR_UPD_AREA1_SHIFT 12 +#define OMAP44XX_ERR_UPD_AREA1_MASK (1 << 12) +#define OMAP44XX_ERR_INV_DATA1_SHIFT 11 +#define OMAP44XX_ERR_INV_DATA1_MASK (1 << 11) +#define OMAP44XX_ERR_INV_DSC1_SHIFT 10 +#define OMAP44XX_ERR_INV_DSC1_MASK (1 << 10) +#define OMAP44XX_FILL_LST1_SHIFT 9 +#define OMAP44XX_FILL_LST1_MASK (1 << 9) +#define OMAP44XX_FILL_DSC1_SHIFT 8 +#define OMAP44XX_FILL_DSC1_MASK (1 << 8) +#define OMAP44XX_ERR_LUT_MISS0_SHIFT 7 +#define OMAP44XX_ERR_LUT_MISS0_MASK (1 << 7) +#define OMAP44XX_ERR_UPD_DATA0_SHIFT 6 +#define OMAP44XX_ERR_UPD_DATA0_MASK (1 << 6) +#define OMAP44XX_ERR_UPD_CTRL0_SHIFT 5 +#define OMAP44XX_ERR_UPD_CTRL0_MASK (1 << 5) +#define OMAP44XX_ERR_UPD_AREA0_SHIFT 4 +#define OMAP44XX_ERR_UPD_AREA0_MASK (1 << 4) +#define OMAP44XX_ERR_INV_DATA0_SHIFT 3 +#define OMAP44XX_ERR_INV_DATA0_MASK (1 << 3) +#define OMAP44XX_ERR_INV_DSC0_SHIFT 2 +#define OMAP44XX_ERR_INV_DSC0_MASK (1 << 2) +#define OMAP44XX_FILL_LST0_SHIFT 1 +#define OMAP44XX_FILL_LST0_MASK (1 << 1) +#define OMAP44XX_FILL_DSC0_SHIFT 0 +#define OMAP44XX_FILL_DSC0_MASK (1 << 0) + +/* DMM_PAT_IRQSTATUS */ + +/* DMM_PAT_IRQENABLE_SET */ + +/* DMM_PAT_IRQENABLE_CLR */ + +/* DMM_PAT_STATUS */ +#define OMAP44XX_CNT_SHIFT 16 +#define OMAP44XX_CNT_MASK (0x1ff << 16) +#define OMAP44XX_ERROR_SHIFT 10 +#define OMAP44XX_ERROR_MASK (0x3f << 10) +#define OMAP44XX_BYPASSED_SHIFT 7 +#define OMAP44XX_BYPASSED_MASK (1 << 7) +#define OMAP44XX_LINKED_SHIFT 4 +#define OMAP44XX_LINKED_MASK (1 << 4) +#define OMAP44XX_DONE_SHIFT 3 +#define OMAP44XX_DONE_MASK (1 << 3) +#define OMAP44XX_RUN_SHIFT 2 +#define OMAP44XX_RUN_MASK (1 << 2) +#define OMAP44XX_VALID_SHIFT 1 +#define OMAP44XX_VALID_MASK (1 << 1) +#define OMAP44XX_READY_SHIFT 0 +#define OMAP44XX_READY_MASK (1 << 0) + +/* DMM_PAT_DESCR */ +#define OMAP44XX_ADDR_SHIFT 4 +#define OMAP44XX_ADDR_MASK (0xfffffff << 4) + +/* DMM_PAT_AREA */ +#define OMAP44XX_Y1_SHIFT 24 +#define OMAP44XX_Y1_MASK (0x7f << 24) +#define OMAP44XX_X1_SHIFT 16 +#define OMAP44XX_X1_MASK (0xff << 16) +#define OMAP44XX_Y0_SHIFT 8 +#define OMAP44XX_Y0_MASK (0x7f << 8) +#define OMAP44XX_X0_SHIFT 0 +#define OMAP44XX_X0_MASK (0xff << 0) + +/* DMM_PAT_CTRL */ +#define OMAP44XX_INITIATOR_SHIFT 28 +#define OMAP44XX_INITIATOR_MASK (0xf << 28) +#define OMAP44XX_SYNC_SHIFT 16 +#define OMAP44XX_SYNC_MASK (1 << 16) +#define OMAP44XX_DIRECTION_SHIFT 4 +#define OMAP44XX_DIRECTION_MASK (0x7 << 4) +#define OMAP44XX_START_SHIFT 0 +#define OMAP44XX_START_MASK (1 << 0) + +/* DMM_PAT_DATA */ + +/* DMM_PEG_HWINFO */ +#define OMAP44XX_PRIO_CNT_SHIFT 0 +#define OMAP44XX_PRIO_CNT_MASK (0x7f << 0) + +/* DMM_PEG_PRIO */ +#define OMAP44XX_P7_SHIFT 28 +#define OMAP44XX_P7_MASK (0x7 << 28) +#define OMAP44XX_P6_SHIFT 24 +#define OMAP44XX_P6_MASK (0x7 << 24) +#define OMAP44XX_P5_SHIFT 20 +#define OMAP44XX_P5_MASK (0x7 << 20) +#define OMAP44XX_P4_SHIFT 16 +#define OMAP44XX_P4_MASK (0x7 << 16) +#define OMAP44XX_P3_SHIFT 12 +#define OMAP44XX_P3_MASK (0x7 << 12) +#define OMAP44XX_P2_SHIFT 8 +#define OMAP44XX_P2_MASK (0x7 << 8) +#define OMAP44XX_P1_SHIFT 4 +#define OMAP44XX_P1_MASK (0x7 << 4) +#define OMAP44XX_P0_SHIFT 0 +#define OMAP44XX_P0_MASK (0x7 << 0) + +/* DMM_PEG_PRIO_PAT */ +#define OMAP44XX_W_PAT_SHIFT 3 +#define OMAP44XX_W_PAT_MASK (1 << 3) +#define OMAP44XX_P_PAT_SHIFT 0 +#define OMAP44XX_P_PAT_MASK (0x7 << 0) +#endif diff --git a/arch/arm/mach-omap2/include/mach/dmm.h b/arch/arm/mach-omap2/include/mach/dmm.h new file mode 100644 index 0000000..3567b6f9 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/dmm.h @@ -0,0 +1,164 @@ +/* + * dmm.h + * + * DMM driver support functions for TI DMM-TILER hardware block. + * + * Author: David Sin <davidsin@ti.com> + * + * Copyright (C) 2009-2011 Texas Instruments, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef DMM_H +#define DMM_H + +#define DMM_BASE 0x4E000000 +#define DMM_SIZE 0x800 + +#define DMM_REVISION 0x000 +#define DMM_HWINFO 0x004 +#define DMM_LISA_HWINFO 0x008 +#define DMM_DMM_SYSCONFIG 0x010 +#define DMM_LISA_LOCK 0x01C +#define DMM_LISA_MAP__0 0x040 +#define DMM_LISA_MAP__1 0x044 +#define DMM_TILER_HWINFO 0x208 +#define DMM_TILER_OR__0 0x220 +#define DMM_TILER_OR__1 0x224 +#define DMM_PAT_HWINFO 0x408 +#define DMM_PAT_GEOMETRY 0x40C +#define DMM_PAT_CONFIG 0x410 +#define DMM_PAT_VIEW__0 0x420 +#define DMM_PAT_VIEW__1 0x424 +#define DMM_PAT_VIEW_MAP__0 0x440 +#define DMM_PAT_VIEW_MAP_BASE 0x460 +#define DMM_PAT_IRQ_EOI 0x478 +#define DMM_PAT_IRQSTATUS_RAW 0x480 +#define DMM_PAT_IRQSTATUS 0x490 +#define DMM_PAT_IRQENABLE_SET 0x4A0 +#define DMM_PAT_IRQENABLE_CLR 0x4B0 +#define DMM_PAT_STATUS__0 0x4C0 +#define DMM_PAT_STATUS__1 0x4C4 +#define DMM_PAT_STATUS__2 0x4C8 +#define DMM_PAT_STATUS__3 0x4CC +#define DMM_PAT_DESCR__0 0x500 +#define DMM_PAT_AREA__0 0x504 +#define DMM_PAT_CTRL__0 0x508 +#define DMM_PAT_DATA__0 0x50C +#define DMM_PEG_HWINFO 0x608 +#define DMM_PEG_PRIO 0x620 +#define DMM_PEG_PRIO_PAT 0x640 + +/** + * PAT refill programming mode. + */ +enum pat_mode { + MANUAL, + AUTO +}; + +/** + * Area definition for DMM physical address translator. + */ +struct pat_area { + s32 x0:8; + s32 y0:8; + s32 x1:8; + s32 y1:8; +}; + +/** + * DMM physical address translator control. + */ +struct pat_ctrl { + s32 start:4; + s32 dir:4; + s32 lut_id:8; + s32 sync:12; + s32 ini:4; +}; + +/** + * PAT descriptor. + */ +struct pat { + struct pat *next; + struct pat_area area; + struct pat_ctrl ctrl; + u32 data; +}; + +/** + * DMM device data + */ +struct dmm { + void __iomem *base; +}; + +/** + * Create and initialize the physical address translator. + * @param id PAT id + * @return pointer to device data + */ +struct dmm *dmm_pat_init(u32 id); + +/** + * Program the physical address translator. + * @param dmm Device data + * @param desc PAT descriptor + * @param mode programming mode + * @return an error status. + */ +s32 dmm_pat_refill(struct dmm *dmm, struct pat *desc, enum pat_mode mode); + +/** + * Clean up the physical address translator. + * @param dmm Device data + * @return an error status. + */ +void dmm_pat_release(struct dmm *dmm); + +/** + * DMM Platform Device Data structure + * + */ +struct omap_dmm_platform_data { + const char *oh_name; + void __iomem *base; + int irq; +}; + +/** + * Init function for use in board init file + * + */ +void omap_dmm_init(void); + +#endif diff --git a/arch/arm/mach-omap2/include/mach/emif-44xx.h b/arch/arm/mach-omap2/include/mach/emif-44xx.h new file mode 100644 index 0000000..58a80f2 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/emif-44xx.h @@ -0,0 +1,526 @@ +/* + * OMAP44xx EMIF registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * Santosh Shilimkar (santosh.shilimkar@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_EMIF_44XX_H +#define __ARCH_ARM_MACH_OMAP2_EMIF_44XX_H + + +/* Base address */ +#define OMAP44XX_EMIF1 0x4c000000 +#define OMAP44XX_EMIF2 0x4d000000 + +/* Registers offset */ +#define OMAP44XX_EMIF_MOD_ID_REV 0x0000 +#define OMAP44XX_EMIF_STATUS 0x0004 +#define OMAP44XX_EMIF_SDRAM_CONFIG 0x0008 +#define OMAP44XX_EMIF_SDRAM_CONFIG_2 0x000c +#define OMAP44XX_EMIF_SDRAM_REF_CTRL 0x0010 +#define OMAP44XX_EMIF_SDRAM_REF_CTRL_SHDW 0x0014 +#define OMAP44XX_EMIF_SDRAM_TIM_1 0x0018 +#define OMAP44XX_EMIF_SDRAM_TIM_1_SHDW 0x001c +#define OMAP44XX_EMIF_SDRAM_TIM_2 0x0020 +#define OMAP44XX_EMIF_SDRAM_TIM_2_SHDW 0x0024 +#define OMAP44XX_EMIF_SDRAM_TIM_3 0x0028 +#define OMAP44XX_EMIF_SDRAM_TIM_3_SHDW 0x002c +#define OMAP44XX_EMIF_LPDDR2_NVM_TIM 0x0030 +#define OMAP44XX_EMIF_LPDDR2_NVM_TIM_SHDW 0x0034 +#define OMAP44XX_EMIF_PWR_MGMT_CTRL 0x0038 +#define OMAP44XX_EMIF_PWR_MGMT_CTRL_SHDW 0x003c +#define OMAP44XX_EMIF_LPDDR2_MODE_REG_DATA 0x0040 +#define OMAP44XX_EMIF_LPDDR2_MODE_REG_CFG 0x0050 +#define OMAP44XX_EMIF_OCP_CONFIG 0x0054 +#define OMAP44XX_EMIF_OCP_CFG_VAL_1 0x0058 +#define OMAP44XX_EMIF_OCP_CFG_VAL_2 0x005c +#define OMAP44XX_EMIF_IODFT_TLGC 0x0060 +#define OMAP44XX_EMIF_IODFT_CTRL_MISR_RSLT 0x0064 +#define OMAP44XX_EMIF_IODFT_ADDR_MISR_RSLT 0x0068 +#define OMAP44XX_EMIF_IODFT_DATA_MISR_RSLT_1 0x006c +#define OMAP44XX_EMIF_IODFT_DATA_MISR_RSLT_2 0x0070 +#define OMAP44XX_EMIF_IODFT_DATA_MISR_RSLT_3 0x0074 +#define OMAP44XX_EMIF_PERF_CNT_1 0x0080 +#define OMAP44XX_EMIF_PERF_CNT_2 0x0084 +#define OMAP44XX_EMIF_PERF_CNT_CFG 0x0088 +#define OMAP44XX_EMIF_PERF_CNT_SEL 0x008c +#define OMAP44XX_EMIF_PERF_CNT_TIM 0x0090 +#define OMAP44XX_EMIF_READ_IDLE_CTRL 0x0098 +#define OMAP44XX_EMIF_READ_IDLE_CTRL_SHDW 0x009c +#define OMAP44XX_EMIF_IRQ_EOI 0x00a0 +#define OMAP44XX_EMIF_IRQSTATUS_RAW_SYS 0x00a4 +#define OMAP44XX_EMIF_IRQSTATUS_RAW_LL 0x00a8 +#define OMAP44XX_EMIF_IRQSTATUS_SYS 0x00ac +#define OMAP44XX_EMIF_IRQSTATUS_LL 0x00b0 +#define OMAP44XX_EMIF_IRQENABLE_SET_SYS 0x00b4 +#define OMAP44XX_EMIF_IRQENABLE_SET_LL 0x00b8 +#define OMAP44XX_EMIF_IRQENABLE_CLR_SYS 0x00bc +#define OMAP44XX_EMIF_IRQENABLE_CLR_LL 0x00c0 +#define OMAP44XX_EMIF_ZQ_CONFIG 0x00c8 +#define OMAP44XX_EMIF_TEMP_ALERT_CONFIG 0x00cc +#define OMAP44XX_EMIF_OCP_ERR_LOG 0x00d0 +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1 0x00e4 +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_SHDW 0x00e8 +#define OMAP44XX_EMIF_DDR_PHY_CTRL_2 0x00ec + +/* Registers shifts and masks */ + +/* EMIF_MOD_ID_REV */ +#define OMAP44XX_REG_SCHEME_SHIFT 30 +#define OMAP44XX_REG_SCHEME_MASK (0x3 << 30) +#define OMAP44XX_REG_MODULE_ID_SHIFT 16 +#define OMAP44XX_REG_MODULE_ID_MASK (0xfff << 16) +#define OMAP44XX_REG_RTL_VERSION_SHIFT 11 +#define OMAP44XX_REG_RTL_VERSION_MASK (0x1f << 11) +#define OMAP44XX_REG_MAJOR_REVISION_SHIFT 8 +#define OMAP44XX_REG_MAJOR_REVISION_MASK (0x7 << 8) +#define OMAP44XX_REG_MINOR_REVISION_SHIFT 0 +#define OMAP44XX_REG_MINOR_REVISION_MASK (0x3f << 0) + +/* STATUS */ +#define OMAP44XX_REG_BE_SHIFT 31 +#define OMAP44XX_REG_BE_MASK (1 << 31) +#define OMAP44XX_REG_DUAL_CLK_MODE_SHIFT 30 +#define OMAP44XX_REG_DUAL_CLK_MODE_MASK (1 << 30) +#define OMAP44XX_REG_FAST_INIT_SHIFT 29 +#define OMAP44XX_REG_FAST_INIT_MASK (1 << 29) +#define OMAP44XX_REG_PHY_DLL_READY_SHIFT 2 +#define OMAP44XX_REG_PHY_DLL_READY_MASK (1 << 2) + +/* SDRAM_CONFIG */ +#define OMAP44XX_REG_SDRAM_TYPE_SHIFT 29 +#define OMAP44XX_REG_SDRAM_TYPE_MASK (0x7 << 29) +#define OMAP44XX_REG_IBANK_POS_SHIFT 27 +#define OMAP44XX_REG_IBANK_POS_MASK (0x3 << 27) +#define OMAP44XX_REG_DDR_TERM_SHIFT 24 +#define OMAP44XX_REG_DDR_TERM_MASK (0x7 << 24) +#define OMAP44XX_REG_DDR2_DDQS_SHIFT 23 +#define OMAP44XX_REG_DDR2_DDQS_MASK (1 << 23) +#define OMAP44XX_REG_DYN_ODT_SHIFT 21 +#define OMAP44XX_REG_DYN_ODT_MASK (0x3 << 21) +#define OMAP44XX_REG_DDR_DISABLE_DLL_SHIFT 20 +#define OMAP44XX_REG_DDR_DISABLE_DLL_MASK (1 << 20) +#define OMAP44XX_REG_SDRAM_DRIVE_SHIFT 18 +#define OMAP44XX_REG_SDRAM_DRIVE_MASK (0x3 << 18) +#define OMAP44XX_REG_CWL_SHIFT 16 +#define OMAP44XX_REG_CWL_MASK (0x3 << 16) +#define OMAP44XX_REG_NARROW_MODE_SHIFT 14 +#define OMAP44XX_REG_NARROW_MODE_MASK (0x3 << 14) +#define OMAP44XX_REG_CL_SHIFT 10 +#define OMAP44XX_REG_CL_MASK (0xf << 10) +#define OMAP44XX_REG_ROWSIZE_SHIFT 7 +#define OMAP44XX_REG_ROWSIZE_MASK (0x7 << 7) +#define OMAP44XX_REG_IBANK_SHIFT 4 +#define OMAP44XX_REG_IBANK_MASK (0x7 << 4) +#define OMAP44XX_REG_EBANK_SHIFT 3 +#define OMAP44XX_REG_EBANK_MASK (1 << 3) +#define OMAP44XX_REG_PAGESIZE_SHIFT 0 +#define OMAP44XX_REG_PAGESIZE_MASK (0x7 << 0) + +/* SDRAM_CONFIG_2 */ +#define OMAP44XX_REG_CS1NVMEN_SHIFT 30 +#define OMAP44XX_REG_CS1NVMEN_MASK (1 << 30) +#define OMAP44XX_REG_EBANK_POS_SHIFT 27 +#define OMAP44XX_REG_EBANK_POS_MASK (1 << 27) +#define OMAP44XX_REG_RDBNUM_SHIFT 4 +#define OMAP44XX_REG_RDBNUM_MASK (0x3 << 4) +#define OMAP44XX_REG_RDBSIZE_SHIFT 0 +#define OMAP44XX_REG_RDBSIZE_MASK (0x7 << 0) + +/* SDRAM_REF_CTRL */ +#define OMAP44XX_REG_INITREF_DIS_SHIFT 31 +#define OMAP44XX_REG_INITREF_DIS_MASK (1 << 31) +#define OMAP44XX_REG_SRT_SHIFT 29 +#define OMAP44XX_REG_SRT_MASK (1 << 29) +#define OMAP44XX_REG_ASR_SHIFT 28 +#define OMAP44XX_REG_ASR_MASK (1 << 28) +#define OMAP44XX_REG_PASR_SHIFT 24 +#define OMAP44XX_REG_PASR_MASK (0x7 << 24) +#define OMAP44XX_REG_REFRESH_RATE_SHIFT 0 +#define OMAP44XX_REG_REFRESH_RATE_MASK (0xffff << 0) + +/* SDRAM_REF_CTRL_SHDW */ +#define OMAP44XX_REG_REFRESH_RATE_SHDW_SHIFT 0 +#define OMAP44XX_REG_REFRESH_RATE_SHDW_MASK (0xffff << 0) + +/* SDRAM_TIM_1 */ +#define OMAP44XX_REG_T_RP_SHIFT 25 +#define OMAP44XX_REG_T_RP_MASK (0xf << 25) +#define OMAP44XX_REG_T_RCD_SHIFT 21 +#define OMAP44XX_REG_T_RCD_MASK (0xf << 21) +#define OMAP44XX_REG_T_WR_SHIFT 17 +#define OMAP44XX_REG_T_WR_MASK (0xf << 17) +#define OMAP44XX_REG_T_RAS_SHIFT 12 +#define OMAP44XX_REG_T_RAS_MASK (0x1f << 12) +#define OMAP44XX_REG_T_RC_SHIFT 6 +#define OMAP44XX_REG_T_RC_MASK (0x3f << 6) +#define OMAP44XX_REG_T_RRD_SHIFT 3 +#define OMAP44XX_REG_T_RRD_MASK (0x7 << 3) +#define OMAP44XX_REG_T_WTR_SHIFT 0 +#define OMAP44XX_REG_T_WTR_MASK (0x7 << 0) + +/* SDRAM_TIM_1_SHDW */ +#define OMAP44XX_REG_T_RP_SHDW_SHIFT 25 +#define OMAP44XX_REG_T_RP_SHDW_MASK (0xf << 25) +#define OMAP44XX_REG_T_RCD_SHDW_SHIFT 21 +#define OMAP44XX_REG_T_RCD_SHDW_MASK (0xf << 21) +#define OMAP44XX_REG_T_WR_SHDW_SHIFT 17 +#define OMAP44XX_REG_T_WR_SHDW_MASK (0xf << 17) +#define OMAP44XX_REG_T_RAS_SHDW_SHIFT 12 +#define OMAP44XX_REG_T_RAS_SHDW_MASK (0x1f << 12) +#define OMAP44XX_REG_T_RC_SHDW_SHIFT 6 +#define OMAP44XX_REG_T_RC_SHDW_MASK (0x3f << 6) +#define OMAP44XX_REG_T_RRD_SHDW_SHIFT 3 +#define OMAP44XX_REG_T_RRD_SHDW_MASK (0x7 << 3) +#define OMAP44XX_REG_T_WTR_SHDW_SHIFT 0 +#define OMAP44XX_REG_T_WTR_SHDW_MASK (0x7 << 0) + +/* SDRAM_TIM_2 */ +#define OMAP44XX_REG_T_XP_SHIFT 28 +#define OMAP44XX_REG_T_XP_MASK (0x7 << 28) +#define OMAP44XX_REG_T_ODT_SHIFT 25 +#define OMAP44XX_REG_T_ODT_MASK (0x7 << 25) +#define OMAP44XX_REG_T_XSNR_SHIFT 16 +#define OMAP44XX_REG_T_XSNR_MASK (0x1ff << 16) +#define OMAP44XX_REG_T_XSRD_SHIFT 6 +#define OMAP44XX_REG_T_XSRD_MASK (0x3ff << 6) +#define OMAP44XX_REG_T_RTP_SHIFT 3 +#define OMAP44XX_REG_T_RTP_MASK (0x7 << 3) +#define OMAP44XX_REG_T_CKE_SHIFT 0 +#define OMAP44XX_REG_T_CKE_MASK (0x7 << 0) + +/* SDRAM_TIM_2_SHDW */ +#define OMAP44XX_REG_T_XP_SHDW_SHIFT 28 +#define OMAP44XX_REG_T_XP_SHDW_MASK (0x7 << 28) +#define OMAP44XX_REG_T_ODT_SHDW_SHIFT 25 +#define OMAP44XX_REG_T_ODT_SHDW_MASK (0x7 << 25) +#define OMAP44XX_REG_T_XSNR_SHDW_SHIFT 16 +#define OMAP44XX_REG_T_XSNR_SHDW_MASK (0x1ff << 16) +#define OMAP44XX_REG_T_XSRD_SHDW_SHIFT 6 +#define OMAP44XX_REG_T_XSRD_SHDW_MASK (0x3ff << 6) +#define OMAP44XX_REG_T_RTP_SHDW_SHIFT 3 +#define OMAP44XX_REG_T_RTP_SHDW_MASK (0x7 << 3) +#define OMAP44XX_REG_T_CKE_SHDW_SHIFT 0 +#define OMAP44XX_REG_T_CKE_SHDW_MASK (0x7 << 0) + +/* SDRAM_TIM_3 */ +#define OMAP44XX_REG_T_CKESR_SHIFT 21 +#define OMAP44XX_REG_T_CKESR_MASK (0x7 << 21) +#define OMAP44XX_REG_ZQ_ZQCS_SHIFT 15 +#define OMAP44XX_REG_ZQ_ZQCS_MASK (0x3f << 15) +#define OMAP44XX_REG_T_TDQSCKMAX_SHIFT 13 +#define OMAP44XX_REG_T_TDQSCKMAX_MASK (0x3 << 13) +#define OMAP44XX_REG_T_RFC_SHIFT 4 +#define OMAP44XX_REG_T_RFC_MASK (0x1ff << 4) +#define OMAP44XX_REG_T_RAS_MAX_SHIFT 0 +#define OMAP44XX_REG_T_RAS_MAX_MASK (0xf << 0) + +/* SDRAM_TIM_3_SHDW */ +#define OMAP44XX_REG_T_CKESR_SHDW_SHIFT 21 +#define OMAP44XX_REG_T_CKESR_SHDW_MASK (0x7 << 21) +#define OMAP44XX_REG_ZQ_ZQCS_SHDW_SHIFT 15 +#define OMAP44XX_REG_ZQ_ZQCS_SHDW_MASK (0x3f << 15) +#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_SHIFT 13 +#define OMAP44XX_REG_T_TDQSCKMAX_SHDW_MASK (0x3 << 13) +#define OMAP44XX_REG_T_RFC_SHDW_SHIFT 4 +#define OMAP44XX_REG_T_RFC_SHDW_MASK (0x1ff << 4) +#define OMAP44XX_REG_T_RAS_MAX_SHDW_SHIFT 0 +#define OMAP44XX_REG_T_RAS_MAX_SHDW_MASK (0xf << 0) + +/* LPDDR2_NVM_TIM */ +#define OMAP44XX_REG_NVM_T_XP_SHIFT 28 +#define OMAP44XX_REG_NVM_T_XP_MASK (0x7 << 28) +#define OMAP44XX_REG_NVM_T_WTR_SHIFT 24 +#define OMAP44XX_REG_NVM_T_WTR_MASK (0x7 << 24) +#define OMAP44XX_REG_NVM_T_RP_SHIFT 20 +#define OMAP44XX_REG_NVM_T_RP_MASK (0xf << 20) +#define OMAP44XX_REG_NVM_T_WRA_SHIFT 16 +#define OMAP44XX_REG_NVM_T_WRA_MASK (0xf << 16) +#define OMAP44XX_REG_NVM_T_RRD_SHIFT 8 +#define OMAP44XX_REG_NVM_T_RRD_MASK (0xff << 8) +#define OMAP44XX_REG_NVM_T_RCDMIN_SHIFT 0 +#define OMAP44XX_REG_NVM_T_RCDMIN_MASK (0xff << 0) + +/* LPDDR2_NVM_TIM_SHDW */ +#define OMAP44XX_REG_NVM_T_XP_SHDW_SHIFT 28 +#define OMAP44XX_REG_NVM_T_XP_SHDW_MASK (0x7 << 28) +#define OMAP44XX_REG_NVM_T_WTR_SHDW_SHIFT 24 +#define OMAP44XX_REG_NVM_T_WTR_SHDW_MASK (0x7 << 24) +#define OMAP44XX_REG_NVM_T_RP_SHDW_SHIFT 20 +#define OMAP44XX_REG_NVM_T_RP_SHDW_MASK (0xf << 20) +#define OMAP44XX_REG_NVM_T_WRA_SHDW_SHIFT 16 +#define OMAP44XX_REG_NVM_T_WRA_SHDW_MASK (0xf << 16) +#define OMAP44XX_REG_NVM_T_RRD_SHDW_SHIFT 8 +#define OMAP44XX_REG_NVM_T_RRD_SHDW_MASK (0xff << 8) +#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_SHIFT 0 +#define OMAP44XX_REG_NVM_T_RCDMIN_SHDW_MASK (0xff << 0) + +/* PWR_MGMT_CTRL */ +#define OMAP44XX_REG_PD_TIM_SHIFT 12 +#define OMAP44XX_REG_PD_TIM_MASK (0xf << 12) +#define OMAP44XX_REG_DPD_EN_SHIFT 11 +#define OMAP44XX_REG_DPD_EN_MASK (1 << 11) +#define OMAP44XX_REG_LP_MODE_SHIFT 8 +#define OMAP44XX_REG_LP_MODE_MASK (0x7 << 8) +#define OMAP44XX_REG_SR_TIM_SHIFT 4 +#define OMAP44XX_REG_SR_TIM_MASK (0xf << 4) +#define OMAP44XX_REG_CS_TIM_SHIFT 0 +#define OMAP44XX_REG_CS_TIM_MASK (0xf << 0) + +/* PWR_MGMT_CTRL_SHDW */ +#define OMAP44XX_REG_PD_TIM_SHDW_SHIFT 12 +#define OMAP44XX_REG_PD_TIM_SHDW_MASK (0xf << 12) +#define OMAP44XX_REG_SR_TIM_SHDW_SHIFT 4 +#define OMAP44XX_REG_SR_TIM_SHDW_MASK (0xf << 4) +#define OMAP44XX_REG_CS_TIM_SHDW_SHIFT 0 +#define OMAP44XX_REG_CS_TIM_SHDW_MASK (0xf << 0) + +/* LPDDR2_MODE_REG_DATA */ +#define OMAP44XX_REG_VALUE_0_SHIFT 0 +#define OMAP44XX_REG_VALUE_0_MASK (0x7f << 0) + +/* LPDDR2_MODE_REG_CFG */ +#define OMAP44XX_REG_CS_SHIFT 31 +#define OMAP44XX_REG_CS_MASK (1 << 31) +#define OMAP44XX_REG_REFRESH_EN_SHIFT 30 +#define OMAP44XX_REG_REFRESH_EN_MASK (1 << 30) +#define OMAP44XX_REG_ADDRESS_SHIFT 0 +#define OMAP44XX_REG_ADDRESS_MASK (0xff << 0) + +/* OCP_CONFIG */ +#define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT 24 +#define OMAP44XX_REG_SYS_THRESH_MAX_MASK (0xf << 24) +#define OMAP44XX_REG_LL_THRESH_MAX_SHIFT 16 +#define OMAP44XX_REG_LL_THRESH_MAX_MASK (0xf << 16) +#define OMAP44XX_REG_PR_OLD_COUNT_SHIFT 0 +#define OMAP44XX_REG_PR_OLD_COUNT_MASK (0xff << 0) + +/* OCP_CFG_VAL_1 */ +#define OMAP44XX_REG_SYS_BUS_WIDTH_SHIFT 30 +#define OMAP44XX_REG_SYS_BUS_WIDTH_MASK (0x3 << 30) +#define OMAP44XX_REG_LL_BUS_WIDTH_SHIFT 28 +#define OMAP44XX_REG_LL_BUS_WIDTH_MASK (0x3 << 28) +#define OMAP44XX_REG_WR_FIFO_DEPTH_SHIFT 8 +#define OMAP44XX_REG_WR_FIFO_DEPTH_MASK (0xff << 8) +#define OMAP44XX_REG_CMD_FIFO_DEPTH_SHIFT 0 +#define OMAP44XX_REG_CMD_FIFO_DEPTH_MASK (0xff << 0) + +/* OCP_CFG_VAL_2 */ +#define OMAP44XX_REG_RREG_FIFO_DEPTH_SHIFT 16 +#define OMAP44XX_REG_RREG_FIFO_DEPTH_MASK (0xff << 16) +#define OMAP44XX_REG_RSD_FIFO_DEPTH_SHIFT 8 +#define OMAP44XX_REG_RSD_FIFO_DEPTH_MASK (0xff << 8) +#define OMAP44XX_REG_RCMD_FIFO_DEPTH_SHIFT 0 +#define OMAP44XX_REG_RCMD_FIFO_DEPTH_MASK (0xff << 0) + +/* IODFT_TLGC */ +#define OMAP44XX_REG_TLEC_SHIFT 16 +#define OMAP44XX_REG_TLEC_MASK (0xffff << 16) +#define OMAP44XX_REG_MT_SHIFT 14 +#define OMAP44XX_REG_MT_MASK (1 << 14) +#define OMAP44XX_REG_ACT_CAP_EN_SHIFT 13 +#define OMAP44XX_REG_ACT_CAP_EN_MASK (1 << 13) +#define OMAP44XX_REG_OPG_LD_SHIFT 12 +#define OMAP44XX_REG_OPG_LD_MASK (1 << 12) +#define OMAP44XX_REG_RESET_PHY_SHIFT 10 +#define OMAP44XX_REG_RESET_PHY_MASK (1 << 10) +#define OMAP44XX_REG_MMS_SHIFT 8 +#define OMAP44XX_REG_MMS_MASK (1 << 8) +#define OMAP44XX_REG_MC_SHIFT 4 +#define OMAP44XX_REG_MC_MASK (0x3 << 4) +#define OMAP44XX_REG_PC_SHIFT 1 +#define OMAP44XX_REG_PC_MASK (0x7 << 1) +#define OMAP44XX_REG_TM_SHIFT 0 +#define OMAP44XX_REG_TM_MASK (1 << 0) + +/* IODFT_CTRL_MISR_RSLT */ +#define OMAP44XX_REG_DQM_TLMR_SHIFT 16 +#define OMAP44XX_REG_DQM_TLMR_MASK (0x3ff << 16) +#define OMAP44XX_REG_CTL_TLMR_SHIFT 0 +#define OMAP44XX_REG_CTL_TLMR_MASK (0x7ff << 0) + +/* IODFT_ADDR_MISR_RSLT */ +#define OMAP44XX_REG_ADDR_TLMR_SHIFT 0 +#define OMAP44XX_REG_ADDR_TLMR_MASK (0x1fffff << 0) + +/* IODFT_DATA_MISR_RSLT_1 */ +#define OMAP44XX_REG_DATA_TLMR_31_0_SHIFT 0 +#define OMAP44XX_REG_DATA_TLMR_31_0_MASK (0xffffffff << 0) + +/* IODFT_DATA_MISR_RSLT_2 */ +#define OMAP44XX_REG_DATA_TLMR_63_32_SHIFT 0 +#define OMAP44XX_REG_DATA_TLMR_63_32_MASK (0xffffffff << 0) + +/* IODFT_DATA_MISR_RSLT_3 */ +#define OMAP44XX_REG_DATA_TLMR_66_64_SHIFT 0 +#define OMAP44XX_REG_DATA_TLMR_66_64_MASK (0x7 << 0) + +/* PERF_CNT_1 */ +#define OMAP44XX_REG_COUNTER1_SHIFT 0 +#define OMAP44XX_REG_COUNTER1_MASK (0xffffffff << 0) + +/* PERF_CNT_2 */ +#define OMAP44XX_REG_COUNTER2_SHIFT 0 +#define OMAP44XX_REG_COUNTER2_MASK (0xffffffff << 0) + +/* PERF_CNT_CFG */ +#define OMAP44XX_REG_CNTR2_MCONNID_EN_SHIFT 31 +#define OMAP44XX_REG_CNTR2_MCONNID_EN_MASK (1 << 31) +#define OMAP44XX_REG_CNTR2_REGION_EN_SHIFT 30 +#define OMAP44XX_REG_CNTR2_REGION_EN_MASK (1 << 30) +#define OMAP44XX_REG_CNTR2_CFG_SHIFT 16 +#define OMAP44XX_REG_CNTR2_CFG_MASK (0xf << 16) +#define OMAP44XX_REG_CNTR1_MCONNID_EN_SHIFT 15 +#define OMAP44XX_REG_CNTR1_MCONNID_EN_MASK (1 << 15) +#define OMAP44XX_REG_CNTR1_REGION_EN_SHIFT 14 +#define OMAP44XX_REG_CNTR1_REGION_EN_MASK (1 << 14) +#define OMAP44XX_REG_CNTR1_CFG_SHIFT 0 +#define OMAP44XX_REG_CNTR1_CFG_MASK (0xf << 0) + +/* PERF_CNT_SEL */ +#define OMAP44XX_REG_MCONNID2_SHIFT 24 +#define OMAP44XX_REG_MCONNID2_MASK (0xff << 24) +#define OMAP44XX_REG_REGION_SEL2_SHIFT 16 +#define OMAP44XX_REG_REGION_SEL2_MASK (0x3 << 16) +#define OMAP44XX_REG_MCONNID1_SHIFT 8 +#define OMAP44XX_REG_MCONNID1_MASK (0xff << 8) +#define OMAP44XX_REG_REGION_SEL1_SHIFT 0 +#define OMAP44XX_REG_REGION_SEL1_MASK (0x3 << 0) + +/* PERF_CNT_TIM */ +#define OMAP44XX_REG_TOTAL_TIME_SHIFT 0 +#define OMAP44XX_REG_TOTAL_TIME_MASK (0xffffffff << 0) + +/* READ_IDLE_CTRL */ +#define OMAP44XX_REG_READ_IDLE_LEN_SHIFT 16 +#define OMAP44XX_REG_READ_IDLE_LEN_MASK (0xf << 16) +#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHIFT 0 +#define OMAP44XX_REG_READ_IDLE_INTERVAL_MASK (0x1ff << 0) + +/* READ_IDLE_CTRL_SHDW */ +#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_SHIFT 16 +#define OMAP44XX_REG_READ_IDLE_LEN_SHDW_MASK (0xf << 16) +#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_SHIFT 0 +#define OMAP44XX_REG_READ_IDLE_INTERVAL_SHDW_MASK (0x1ff << 0) + +/* IRQ_EOI */ +#define OMAP44XX_REG_EOI_SHIFT 0 +#define OMAP44XX_REG_EOI_MASK (1 << 0) + +/* IRQSTATUS_RAW_SYS */ +#define OMAP44XX_REG_DNV_SYS_SHIFT 2 +#define OMAP44XX_REG_DNV_SYS_MASK (1 << 2) +#define OMAP44XX_REG_TA_SYS_SHIFT 1 +#define OMAP44XX_REG_TA_SYS_MASK (1 << 1) +#define OMAP44XX_REG_ERR_SYS_SHIFT 0 +#define OMAP44XX_REG_ERR_SYS_MASK (1 << 0) + +/* IRQSTATUS_RAW_LL */ +#define OMAP44XX_REG_DNV_LL_SHIFT 2 +#define OMAP44XX_REG_DNV_LL_MASK (1 << 2) +#define OMAP44XX_REG_TA_LL_SHIFT 1 +#define OMAP44XX_REG_TA_LL_MASK (1 << 1) +#define OMAP44XX_REG_ERR_LL_SHIFT 0 +#define OMAP44XX_REG_ERR_LL_MASK (1 << 0) + +/* IRQSTATUS_SYS */ + +/* IRQSTATUS_LL */ + +/* IRQENABLE_SET_SYS */ +#define OMAP44XX_REG_EN_DNV_SYS_SHIFT 2 +#define OMAP44XX_REG_EN_DNV_SYS_MASK (1 << 2) +#define OMAP44XX_REG_EN_TA_SYS_SHIFT 1 +#define OMAP44XX_REG_EN_TA_SYS_MASK (1 << 1) +#define OMAP44XX_REG_EN_ERR_SYS_SHIFT 0 +#define OMAP44XX_REG_EN_ERR_SYS_MASK (1 << 0) + +/* IRQENABLE_SET_LL */ +#define OMAP44XX_REG_EN_DNV_LL_SHIFT 2 +#define OMAP44XX_REG_EN_DNV_LL_MASK (1 << 2) +#define OMAP44XX_REG_EN_TA_LL_SHIFT 1 +#define OMAP44XX_REG_EN_TA_LL_MASK (1 << 1) +#define OMAP44XX_REG_EN_ERR_LL_SHIFT 0 +#define OMAP44XX_REG_EN_ERR_LL_MASK (1 << 0) + +/* IRQENABLE_CLR_SYS */ + +/* IRQENABLE_CLR_LL */ + +/* ZQ_CONFIG */ +#define OMAP44XX_REG_ZQ_CS1EN_SHIFT 31 +#define OMAP44XX_REG_ZQ_CS1EN_MASK (1 << 31) +#define OMAP44XX_REG_ZQ_CS0EN_SHIFT 30 +#define OMAP44XX_REG_ZQ_CS0EN_MASK (1 << 30) +#define OMAP44XX_REG_ZQ_DUALCALEN_SHIFT 29 +#define OMAP44XX_REG_ZQ_DUALCALEN_MASK (1 << 29) +#define OMAP44XX_REG_ZQ_SFEXITEN_SHIFT 28 +#define OMAP44XX_REG_ZQ_SFEXITEN_MASK (1 << 28) +#define OMAP44XX_REG_ZQ_ZQINIT_MULT_SHIFT 18 +#define OMAP44XX_REG_ZQ_ZQINIT_MULT_MASK (0x3 << 18) +#define OMAP44XX_REG_ZQ_ZQCL_MULT_SHIFT 16 +#define OMAP44XX_REG_ZQ_ZQCL_MULT_MASK (0x3 << 16) +#define OMAP44XX_REG_ZQ_REFINTERVAL_SHIFT 0 +#define OMAP44XX_REG_ZQ_REFINTERVAL_MASK (0xffff << 0) + +/* TEMP_ALERT_CONFIG */ +#define OMAP44XX_REG_TA_CS1EN_SHIFT 31 +#define OMAP44XX_REG_TA_CS1EN_MASK (1 << 31) +#define OMAP44XX_REG_TA_CS0EN_SHIFT 30 +#define OMAP44XX_REG_TA_CS0EN_MASK (1 << 30) +#define OMAP44XX_REG_TA_SFEXITEN_SHIFT 28 +#define OMAP44XX_REG_TA_SFEXITEN_MASK (1 << 28) +#define OMAP44XX_REG_TA_DEVWDT_SHIFT 26 +#define OMAP44XX_REG_TA_DEVWDT_MASK (0x3 << 26) +#define OMAP44XX_REG_TA_DEVCNT_SHIFT 24 +#define OMAP44XX_REG_TA_DEVCNT_MASK (0x3 << 24) +#define OMAP44XX_REG_TA_REFINTERVAL_SHIFT 0 +#define OMAP44XX_REG_TA_REFINTERVAL_MASK (0x3fffff << 0) + +/* OCP_ERR_LOG */ +#define OMAP44XX_REG_MADDRSPACE_SHIFT 14 +#define OMAP44XX_REG_MADDRSPACE_MASK (0x3 << 14) +#define OMAP44XX_REG_MBURSTSEQ_SHIFT 11 +#define OMAP44XX_REG_MBURSTSEQ_MASK (0x7 << 11) +#define OMAP44XX_REG_MCMD_SHIFT 8 +#define OMAP44XX_REG_MCMD_MASK (0x7 << 8) +#define OMAP44XX_REG_MCONNID_SHIFT 0 +#define OMAP44XX_REG_MCONNID_MASK (0xff << 0) + +/* DDR_PHY_CTRL_1 */ +#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHIFT 4 +#define OMAP44XX_REG_DDR_PHY_CTRL_1_MASK (0xfffffff << 4) +#define OMAP44XX_REG_READ_LATENCY_SHIFT 0 +#define OMAP44XX_REG_READ_LATENCY_MASK (0xf << 0) +#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHIFT 4 +#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_MASK (0xFF << 4) +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT 12 +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_MASK (0xFFFFF << 12) + +/* DDR_PHY_CTRL_1_SHDW */ +#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_SHIFT 4 +#define OMAP44XX_REG_DDR_PHY_CTRL_1_SHDW_MASK (0xfffffff << 4) +#define OMAP44XX_REG_READ_LATENCY_SHDW_SHIFT 0 +#define OMAP44XX_REG_READ_LATENCY_SHDW_MASK (0xf << 0) +#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_SHIFT 4 +#define OMAP44XX_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK (0xFF << 4) +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12 +#define OMAP44XX_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK (0xFFFFF << 12) + +/* DDR_PHY_CTRL_2 */ +#define OMAP44XX_REG_DDR_PHY_CTRL_2_SHIFT 0 +#define OMAP44XX_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0) +#endif diff --git a/arch/arm/mach-omap2/include/mach/emif.h b/arch/arm/mach-omap2/include/mach/emif.h new file mode 100644 index 0000000..8a3ea34 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/emif.h @@ -0,0 +1,268 @@ +/* + * OMAP44xx EMIF header + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Aneesh V <aneesh@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _EMIF_H +#define _EMIF_H + +#include <mach/emif-44xx.h> +#include <mach/lpddr2-jedec.h> + +#define EMIF_NUM_INSTANCES 2 +#define EMIF1 0 +#define EMIF2 1 + +/* The maximum frequency at which the LPDDR2 interface can operate in Hz*/ +#define MAX_LPDDR2_FREQ 400000000 /* 400 MHz */ + +/* 19.2 MHz to be used for finding initialization values */ +#define EMIF_FREQ_19_2_MHZ 19200000 /* 19.2 MHz */ +/* + * The period of DDR clk is represented as numerator and denominator for + * better accuracy in integer based calculations. However, if the numerator + * and denominator are very huge there may be chances of overflow in + * calculations. So, as a trade-off keep denominator(and consequently + * numerator) within a limit sacrificing some accuracy - but not much + * If denominator and numerator are already small (such as at 400 MHz) + * no adjustment is needed + */ +#define EMIF_PERIOD_DEN_LIMIT 1000 +/* + * Maximum number of different frequencies supported by EMIF driver + * Determines the number of entries in the pointer array for register + * cache + */ +#define EMIF_MAX_NUM_FREQUENCIES 6 +/* + * Indices into the Addressing Table array. + * One entry each for all the different types of devices with different + * addressing schemes + */ +#define ADDR_TABLE_INDEX64M 0 +#define ADDR_TABLE_INDEX128M 1 +#define ADDR_TABLE_INDEX256M 2 +#define ADDR_TABLE_INDEX512M 3 +#define ADDR_TABLE_INDEX1GS4 4 +#define ADDR_TABLE_INDEX2GS4 5 +#define ADDR_TABLE_INDEX4G 6 +#define ADDR_TABLE_INDEX8G 7 +#define ADDR_TABLE_INDEX1GS2 8 +#define ADDR_TABLE_INDEX2GS2 9 +#define ADDR_TABLE_INDEXMAX 10 + +/* Number of Row bits */ +#define ROW_9 0 +#define ROW_10 1 +#define ROW_11 2 +#define ROW_12 3 +#define ROW_13 4 +#define ROW_14 5 +#define ROW_15 6 +#define ROW_16 7 + +/* Number of Column bits */ +#define COL_8 0 +#define COL_9 1 +#define COL_10 2 +#define COL_11 3 +#define COL_7 4 /*Not supported by OMAP included for completeness */ + +/* Number of Banks*/ +#define BANKS1 0 +#define BANKS2 1 +#define BANKS4 2 +#define BANKS8 3 + +/* Refresh rate in micro seconds x 10 */ +#define T_REFI_15_6 156 +#define T_REFI_7_8 78 +#define T_REFI_3_9 39 + +#define EBANK_CS1_DIS 0 +#define EBANK_CS1_EN 1 + +/* Read Latency at the base frequency - 19.2 MHz on bootup */ +#define RL_19_2_MHZ 3 +/* Interleaving policies at EMIF level- between banks and Chip Selects */ +#define EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING 0 +#define EMIF_INTERLEAVING_POLICY_NO_BANK_INTERLEAVING 3 + +/* + * Interleaving policy to be used + * Currently set to MAX interleaving for better performance + */ +#define EMIF_INTERLEAVING_POLICY EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING + +/* State of the core voltage: + * This is important for some parameters such as read idle control and + * ZQ calibration timings. Timings are much stricter when voltage ramp + * is happening compared to when the voltage is stable. + * We need to calculate two sets of values for these parameters and use + * them accordingly + */ +#define LPDDR2_VOLTAGE_STABLE 0 +#define LPDDR2_VOLTAGE_RAMPING 1 + +/* Length of the forced read idle period in terms of cycles */ +#define EMIF_REG_READ_IDLE_LEN_VAL 5 + +/* Interval between forced 'read idles' */ +/* To be used when voltage is changed for DPS/DVFS - 1us */ +#define READ_IDLE_INTERVAL_DVFS (1*1000) +/* + * To be used when voltage is not scaled except by Smart Reflex + * 50us - or maximum value will do + */ +#define READ_IDLE_INTERVAL_NORMAL (50*1000) + + +/* + * Unless voltage is changing due to DVFS one ZQCS command every 50ms should + * be enough. This shoule be enough also in the case when voltage is changing + * due to smart-reflex. + */ +#define EMIF_ZQCS_INTERVAL_NORMAL_IN_US (50*1000) +/* + * If voltage is changing due to DVFS ZQCS should be performed more + * often(every 50us) + */ +#define EMIF_ZQCS_INTERVAL_DVFS_IN_US 50 + +/* The interval between ZQCL commands as a multiple of ZQCS interval */ +#define REG_ZQ_ZQCL_MULT 4 +/* The interval between ZQINIT commands as a multiple of ZQCL interval */ +#define REG_ZQ_ZQINIT_MULT 3 +/* Enable ZQ Calibration on exiting Self-refresh */ +#define REG_ZQ_SFEXITEN_ENABLE 1 +/* + * ZQ Calibration simultaneously on both chip-selects: + * Needs one calibration resistor per CS + * None of the boards that we know of have this capability + * So disabled by default + */ +#define REG_ZQ_DUALCALEN_DISABLE 0 +/* + * Enable ZQ Calibration by default on CS0. If we are asked to program + * the EMIF there will be something connected to CS0 for sure + */ +#define REG_ZQ_CS0EN_ENABLE 1 + +/* EMIF_PWR_MGMT_CTRL register */ +/* Low power modes */ +#define LP_MODE_DISABLE 0 +#define LP_MODE_CLOCK_STOP 1 +#define LP_MODE_SELF_REFRESH 2 +#define LP_MODE_PWR_DN 3 + +/* REG_DPD_EN */ +#define DPD_DISABLE 0 +#define DPD_ENABLE 1 + +/* + * Value of bits 12:31 of DDR_PHY_CTRL_1 register: + * All these fields have magic values dependent on frequency and + * determined by PHY and DLL integration with EMIF. Setting the magic + * values suggested by hw team. + */ +#define EMIF_DDR_PHY_CTRL_1_BASE_VAL 0x049FF +#define EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ 0x41 +#define EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ 0x80 +#define EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS 0xFF + +/* +* MR1 value: +* Burst length : 8 +* Burst type : sequential +* Wrap : enabled +* nWR : 3(default). EMIF does not do pre-charge. +* : So nWR is don't care +*/ +#define MR1_VAL 0x23 + +/* MR10: ZQ calibration codes */ +#define MR10_ZQ_ZQCS 0x56 +#define MR10_ZQ_ZQCL 0xAB +#define MR10_ZQ_ZQINIT 0xFF +#define MR10_ZQ_ZQRESET 0xC3 + +/* TEMP_ALERT_CONFIG */ +#define TEMP_ALERT_POLL_INTERVAL_MS 360 /* for temp gradient - 5 C/s */ +#define TEMP_ALERT_CONFIG_DEVCT_1 0 +#define TEMP_ALERT_CONFIG_DEVWDT_32 2 + +/* MR16 value: refresh full array(no partial array self refresh) */ +#define MR16_VAL 0 + +#if defined(DEBUG) +#define emif_assert(c) BUG_ON(!(c)) +#else +#define emif_assert(c) ({ if (0) BUG_ON(!(c)); 0; }) +#endif + +/* Details of the devices connected to each chip-select of an EMIF instance */ +struct emif_device_details { + const struct lpddr2_device_info *cs0_device; + const struct lpddr2_device_info *cs1_device; +}; + +/* + * LPDDR2 interface clock frequency: + * Period (represented as numerator and denominator for better accuracy in + * calculations) should be <= the real value. Period is used for calculating + * all timings except refresh rate. + * freq_mhz_floor - freq in mhz truncated to the lower integer is used for + * calculating refresh rate + * freq_mhz_ceil - frequency in mhz rounded up is used for identifying the + * right speed bin and the corresponding timings table for the LPDDR2 device + */ +struct freq_info { + u16 period_num; + u16 period_den; + u16 freq_mhz_floor; + u16 freq_mhz_ceil; +}; + +/* + * Structure containing shadow of important registers in EMIF + * The calculation function fills in this structure to be later used for + * initialization and DVFS + */ +struct emif_regs { + u32 freq; + u8 RL_final; + u32 sdram_config_init; + u32 sdram_config_final; + u32 ref_ctrl; + u32 ref_ctrl_derated; + u32 sdram_tim1; + u32 sdram_tim1_derated; + u32 sdram_tim2; + u32 sdram_tim3; + u32 read_idle_ctrl_normal; + u32 read_idle_ctrl_volt_ramp; + u32 zq_config_normal; + u32 zq_config_volt_ramp; + u32 temp_alert_config; + u32 temp_alert_config_derated; + u32 emif_ddr_phy_ctlr_1_init; + u32 emif_ddr_phy_ctlr_1_final; +}; + +int omap_emif_setup_registers(u32 freq, + u32 volt_state); +void omap_emif_frequency_pre_notify(void); +void omap_emif_frequency_post_notify(void); +int omap_emif_setup_device_details( + const struct emif_device_details *emif1_devices, + const struct emif_device_details *emif2_devices); + +void emif_clear_irq(int emif_id); +#endif diff --git a/arch/arm/mach-omap2/include/mach/id.h b/arch/arm/mach-omap2/include/mach/id.h index 02ed3aa..096c02b 100644 --- a/arch/arm/mach-omap2/include/mach/id.h +++ b/arch/arm/mach-omap2/include/mach/id.h @@ -18,5 +18,6 @@ struct omap_die_id { }; void omap_get_die_id(struct omap_die_id *odi); +void omap_get_production_id(struct omap_die_id *odi); #endif diff --git a/arch/arm/mach-omap2/include/mach/lpddr2-elpida.h b/arch/arm/mach-omap2/include/mach/lpddr2-elpida.h new file mode 100644 index 0000000..b1accb8 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/lpddr2-elpida.h @@ -0,0 +1,23 @@ +/* + * ELPIDA LPDDR2 timings. + * + * Copyright (C) 2010 Texas Instruments + * + * Aneesh V <aneesh@ti.com> + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _LPDDR2_ELPIDA_H +#define _LPDDR2_ELPIDA_H + +extern const struct lpddr2_timings lpddr2_elpida_timings_200_mhz; +extern const struct lpddr2_timings lpddr2_elpida_timings_333_mhz; +extern const struct lpddr2_timings lpddr2_elpida_timings_400_mhz; +extern const struct lpddr2_min_tck lpddr2_elpida_min_tck; +extern struct lpddr2_device_info lpddr2_elpida_2G_S4_dev; + +#endif diff --git a/arch/arm/mach-omap2/include/mach/lpddr2-jedec.h b/arch/arm/mach-omap2/include/mach/lpddr2-jedec.h new file mode 100644 index 0000000..4545c29 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/lpddr2-jedec.h @@ -0,0 +1,149 @@ +/* + * LPDDR2 header based on JESD209-2 + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * Aneesh V <aneesh@ti.com> + * Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _LPDDR2_JDEC_H +#define _LPDDR2_JDEC_H + +#include <linux/types.h> + +/* + * Maximum number of entries we keep in our array of timing tables + * We need not keep all the speed bins supported by the device + * We need to keep timing tables for only the speed bins that we + * are interested in + */ +#define MAX_NUM_SPEEDBINS 4 + +/* LPDDR2 Densities */ +#define LPDDR2_DENSITY_64Mb 0 +#define LPDDR2_DENSITY_128Mb 1 +#define LPDDR2_DENSITY_256Mb 2 +#define LPDDR2_DENSITY_512Mb 3 +#define LPDDR2_DENSITY_1Gb 4 +#define LPDDR2_DENSITY_2Gb 5 +#define LPDDR2_DENSITY_4Gb 6 +#define LPDDR2_DENSITY_8Gb 7 +#define LPDDR2_DENSITY_16Gb 8 +#define LPDDR2_DENSITY_32Gb 9 + +/* LPDDR2 type */ +#define LPDDR2_TYPE_S4 0 +#define LPDDR2_TYPE_S2 1 +#define LPDDR2_TYPE_NVM 2 + +/* LPDDR2 IO width */ +#define LPDDR2_IO_WIDTH_32 0 +#define LPDDR2_IO_WIDTH_16 1 +#define LPDDR2_IO_WIDTH_8 2 + +/* Mode register numbers */ +#define LPDDR2_MR0 0 +#define LPDDR2_MR1 1 +#define LPDDR2_MR2 2 +#define LPDDR2_MR3 3 +#define LPDDR2_MR4 4 +#define LPDDR2_MR5 5 +#define LPDDR2_MR6 6 +#define LPDDR2_MR7 7 +#define LPDDR2_MR8 8 +#define LPDDR2_MR9 9 +#define LPDDR2_MR10 10 +#define LPDDR2_MR11 11 +#define LPDDR2_MR16 16 +#define LPDDR2_MR17 17 +#define LPDDR2_MR18 18 + +/* MR4 register fields */ +#define MR4_SDRAM_REF_RATE_SHIFT 0 +#define MR4_SDRAM_REF_RATE_MASK 7 +#define MR4_TUF_SHIFT 7 +#define MR4_TUF_MASK (1 << 7) + +/* MR4 SDRAM Refresh Rate field values */ +#define SDRAM_TEMP_NOMINAL 0x3 +#define SDRAM_TEMP_RESERVED_4 0x4 +#define SDRAM_TEMP_HIGH_DERATE_REFRESH 0x5 +#define SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS 0x6 +#define SDRAM_TEMP_VERY_HIGH_SHUTDOWN 0x7 + +struct lpddr2_addressing { + u8 num_banks; + u8 t_REFI_us_x10; + u8 row_sz[2]; /* One entry each for x32 and x16 */ + u8 col_sz[2]; /* One entry each for x32 and x16 */ +}; + +/* Structure for timings from the DDR datasheet */ +struct lpddr2_timings { + u32 max_freq; + u8 RL; + u8 tRPab; + u8 tRCD; + u8 tWR; + u8 tRASmin; + u8 tRRD; + u8 tWTRx2; + u8 tXSR; + u8 tXPx2; + u8 tRFCab; + u8 tRTPx2; + u8 tCKE; + u8 tCKESR; + u8 tZQCS; + u32 tZQCL; + u32 tZQINIT; + u8 tDQSCKMAXx2; + u8 tRASmax; + u8 tFAW; +}; + +/* + * Min tCK values for some of the parameters: + * If the calculated clock cycles for the respective parameter is + * less than the corresponding min tCK value, we need to set the min + * tCK value. This may happen at lower frequencies. + */ +struct lpddr2_min_tck { + u32 tRL; + u32 tRP_AB; + u32 tRCD; + u32 tWR; + u32 tRAS_MIN; + u32 tRRD; + u32 tWTR; + u32 tXP; + u32 tRTP; + u8 tCKE; + u32 tCKESR; + u32 tFAW; +}; + +struct lpddr2_device_info { + const struct lpddr2_timings *device_timings[MAX_NUM_SPEEDBINS]; + const struct lpddr2_min_tck *min_tck; + u8 type; + u8 density; + u8 io_width; + + /* Idle time in cycles to wait before putting the memory in self refresh */ + s32 emif_ddr_selfrefresh_cycles; +}; + +/* The following are exported for devices which use JDEC specifications */ +extern const struct lpddr2_addressing lpddr2_jedec_addressing_table[]; +extern const struct lpddr2_timings lpddr2_jedec_timings_400_mhz; +extern const struct lpddr2_timings lpddr2_jedec_timings_333_mhz; +extern const struct lpddr2_timings lpddr2_jedec_timings_200_mhz; +extern const struct lpddr2_min_tck lpddr2_jedec_min_tck; + +#endif diff --git a/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h new file mode 100644 index 0000000..66f31c3 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/omap-wakeupgen.h @@ -0,0 +1,41 @@ +/* + * OMAP WakeupGen header file + * + * Copyright (C) 2011 Texas Instruments, Inc. + * Written by Santosh Shilimkar <santosh.shilimkar@ti.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef OMAP_ARCH_WAKEUPGEN_H +#define OMAP_ARCH_WAKEUPGEN_H + +#define OMAP_WKG_CONTROL_0 0x00 +#define OMAP_WKG_ENB_A_0 0x10 +#define OMAP_WKG_ENB_B_0 0x14 +#define OMAP_WKG_ENB_C_0 0x18 +#define OMAP_WKG_ENB_D_0 0x1c +#define OMAP_WKG_ENB_SECURE_A_0 0x20 +#define OMAP_WKG_ENB_SECURE_B_0 0x24 +#define OMAP_WKG_ENB_SECURE_C_0 0x28 +#define OMAP_WKG_ENB_SECURE_D_0 0x2c +#define OMAP_WKG_ENB_A_1 0x410 +#define OMAP_WKG_ENB_B_1 0x414 +#define OMAP_WKG_ENB_C_1 0x418 +#define OMAP_WKG_ENB_D_1 0x41c +#define OMAP_WKG_ENB_SECURE_A_1 0x420 +#define OMAP_WKG_ENB_SECURE_B_1 0x424 +#define OMAP_WKG_ENB_SECURE_C_1 0x428 +#define OMAP_WKG_ENB_SECURE_D_1 0x42c +#define OMAP_AUX_CORE_BOOT_0 0x800 +#define OMAP_AUX_CORE_BOOT_1 0x804 +#define OMAP_PTMSYNCREQ_MASK 0xc00 +#define OMAP_PTMSYNCREQ_EN 0xc04 +#define OMAP_TIMESTAMPCYCLELO 0xc08 +#define OMAP_TIMESTAMPCYCLEHI 0xc0c + +extern int __init omap_wakeupgen_init(void); +extern void omap_wakeupgen_irqmask_all(unsigned int cpu, unsigned int set); +extern void omap_wakeupgen_save(void); +#endif diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h index e4bd87619..f37cf4e 100644 --- a/arch/arm/mach-omap2/include/mach/omap4-common.h +++ b/arch/arm/mach-omap2/include/mach/omap4-common.h @@ -13,25 +13,84 @@ #ifndef OMAP_ARCH_OMAP4_COMMON_H #define OMAP_ARCH_OMAP4_COMMON_H +#include <asm/proc-fns.h> /* - * wfi used in low power code. Directly opcode is used instead - * of instruction to avoid mulit-omap build break + * Secure low power context save/restore API index */ -#ifdef CONFIG_THUMB2_KERNEL -#define do_wfi() __asm__ __volatile__ ("wfi" : : : "memory") -#else -#define do_wfi() \ - __asm__ __volatile__ (".word 0xe320f003" : : : "memory") -#endif +#define HAL_SAVESECURERAM_INDEX 0x1a +#define HAL_SAVEHW_INDEX 0x1b +#define HAL_SAVEALL_INDEX 0x1c +#define HAL_SAVEGIC_INDEX 0x1d + +/* + * Secure HAL, PPA services available + */ +#define PPA_SERVICE_0 0x21 +#define PPA_SERVICE_PL310_POR 0x23 +#define PPA_SERVICE_DEFAULT_POR_NS_SMP 0x25 +/* + * Secure HAL API flags + */ +#define FLAG_START_CRITICAL 0x4 +#define FLAG_IRQFIQ_MASK 0x3 +#define FLAG_IRQ_ENABLE 0x2 +#define FLAG_FIQ_ENABLE 0x1 +#define NO_FLAG 0x0 + +/* + * SAR restore phase USB HOST static port + * configuration + */ +#define OMAP4_USBHOST_CLKSEL_UTMI_P2_INT_P1_INT 0x0 +#define OMAP4_USBHOST_CLKSEL_UTMI_P2_INT_P1_EXT 0x1 +#define OMAP4_USBHOST_CLKSEL_UTMI_P2_EXT_P1_INT 0x2 +#define OMAP4_USBHOST_CLKSEL_UTMI_P2_EXT_P1_EXT 0x3 + +#ifndef __ASSEMBLER__ #ifdef CONFIG_CACHE_L2X0 -extern void __iomem *l2cache_base; +extern void __iomem *omap4_get_l2cache_base(void); #endif -extern void __iomem *gic_dist_base_addr; +#ifdef CONFIG_SMP +extern void __iomem *omap4_get_scu_base(void); +#else +static inline void __iomem *omap4_get_scu_base(void) +{ + return NULL; +} +#endif +extern void __iomem *omap4_get_gic_dist_base(void); +extern void __iomem *omap4_get_gic_cpu_base(void); +extern void __iomem *omap4_get_sar_ram_base(void); +extern void *omap_get_dram_barrier_base(void); +extern dma_addr_t omap4_secure_ram_phys; extern void __init gic_init_irq(void); +extern void gic_cpu_enable(void); +extern void gic_cpu_disable(void); +extern void gic_dist_enable(void); +extern void gic_dist_disable(void); +extern u32 gic_cpu_read(u32 reg); extern void omap_smc1(u32 fn, u32 arg); +extern void omap_bus_sync(void); +extern void omap_do_wfi(void); + +extern bool gic_dist_disabled(void); +extern void gic_timer_retrigger(void); + +/* + * Read MPIDR: Multiprocessor affinity register + */ +static inline unsigned int hard_smp_processor_id(void) +{ + unsigned int cpunum; + + asm volatile ( + "mrc p15, 0, %0, c0, c0, 5\n" + : "=r" (cpunum)); + return cpunum &= 0x0f; +} #ifdef CONFIG_SMP /* Needed for secondary core boot */ @@ -39,5 +98,65 @@ extern void omap_secondary_startup(void); extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); extern void omap_auxcoreboot_addr(u32 cpu_addr); extern u32 omap_read_auxcoreboot0(void); + +#ifdef CONFIG_PM +extern int omap4_mpuss_init(void); +extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state); +extern void omap4_cpu_suspend(unsigned int cpu, unsigned int save_state); +extern void omap4_cpu_resume(void); +extern u32 omap_smc2(u32 id, u32 falg, u32 pargs); +extern u32 omap4_secure_dispatcher(u32 idx, u32 flag, u32 nargs, + u32 arg1, u32 arg2, u32 arg3, u32 arg4); +#else +static inline int omap4_enter_lowpower(unsigned int cpu, + unsigned int power_state) +{ + cpu_do_idle(); + return 0; +} + +static inline int omap4_mpuss_init(void) +{ + return 0; +} + +static inline void omap4_cpu_suspend(unsigned int cpu, unsigned int save_state) +{ +} + +static inline void omap4_cpu_resume(void) +{ +} + +static inline u32 omap_smc2(u32 id, u32 falg, u32 pargs) +{ + return 0; +} +static inline u32 omap4_secure_dispatcher(u32 idx, u32 flag, u32 nargs, + u32 arg1, u32 arg2, u32 arg3, u32 arg4) +{ + return 0; +} +#endif /* CONFIG_PM */ +#endif /* CONFIG_SMP */ + +extern int omap4_prcm_freq_update(void); + +#ifdef CONFIG_PM +extern int omap4_sar_save(void); +extern void omap4_sar_overwrite(void); +extern void omap4_sar_usbhost_init(u32 fck_source); +#else +void omap4_sar_save(void) +{ +} +void omap4_sar_overwrite(void) +{ +} +void omap4_sar_usbhost_init(u32 fck_source) +{ +} #endif -#endif + +#endif /* __ASSEMBLER__ */ +#endif /* OMAP_ARCH_OMAP4_COMMON_H */ diff --git a/arch/arm/mach-omap2/include/mach/omap_fiq_debugger.h b/arch/arm/mach-omap2/include/mach/omap_fiq_debugger.h new file mode 100644 index 0000000..4378a77 --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/omap_fiq_debugger.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2011 Google, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __MACH_OMAP_FIQ_DEBUGGER_H +#define __MACH_OMAP_FIQ_DEBUGGER_H + +#ifdef CONFIG_OMAP_FIQ_DEBUGGER +int __init omap_serial_debug_init(int id, bool is_fiq, bool is_high_prio_irq, + struct omap_device_pad *pads, int num_pads); +u32 omap_debug_uart_resume_idle(void); + +#else +static inline int __init omap_serial_debug_init(int id, bool is_fiq, bool is_high_prio_irq, + struct omap_device_pad *pads, int num_pads) +{ + return 0; +} + +static inline u32 omap_debug_uart_resume_idle(void) +{ + return 0; +} +#endif + +#endif diff --git a/arch/arm/mach-omap2/include/mach/tiler.h b/arch/arm/mach-omap2/include/mach/tiler.h new file mode 100644 index 0000000..0fdb6eb --- /dev/null +++ b/arch/arm/mach-omap2/include/mach/tiler.h @@ -0,0 +1,513 @@ +/* + * tiler.h + * + * TILER driver support functions for TI TILER hardware block. + * + * Authors: Lajos Molnar <molnar@ti.com> + * David Sin <davidsin@ti.com> + * + * Copyright (C) 2009-2011 Texas Instruments, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * * Neither the name of Texas Instruments Incorporated nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; + * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef TILER_H +#define TILER_H + +#include <linux/mm.h> + +/* + * ----------------------------- API Definitions ----------------------------- + */ + +/* return true if physical address is in the tiler container */ +bool is_tiler_addr(u32 phys); + +enum tiler_fmt { + TILFMT_MIN = -2, + TILFMT_INVALID = -2, + TILFMT_NONE = -1, + TILFMT_8BIT = 0, + TILFMT_16BIT = 1, + TILFMT_32BIT = 2, + TILFMT_PAGE = 3, + TILFMT_MAX = 3, + TILFMT_8AND16 = 4, /* used to mark NV12 reserve block */ +}; + +/* tiler block info */ +struct tiler_block_t { + u32 phys; /* system space (L3) tiler addr */ + u32 width; /* width */ + u32 height; /* height */ + u32 key; /* secret key */ + u32 id; /* unique block ID */ +}; + +/* tiler (image/video frame) view */ +struct tiler_view_t { + u32 tsptr; /* tiler space addr */ + u32 width; /* width */ + u32 height; /* height */ + u32 bpp; /* bytes per pixel */ + s32 h_inc; /* horizontal increment */ + s32 v_inc; /* vertical increment */ +}; + +/* get the tiler format for a physical address or TILFMT_INVALID */ +enum tiler_fmt tiler_fmt(u32 phys); + +/* get the modified (1 for page mode) bytes-per-pixel for a tiler block */ +u32 tiler_bpp(const struct tiler_block_t *b); + +/* get tiler block physical stride */ +u32 tiler_pstride(const struct tiler_block_t *b); + +/* get tiler block virtual stride */ +static inline u32 tiler_vstride(const struct tiler_block_t *b) +{ + return PAGE_ALIGN((b->phys & ~PAGE_MASK) + tiler_bpp(b) * b->width); +} + +/* returns the virtual size of the block (for mmap) */ +static inline u32 tiler_size(const struct tiler_block_t *b) +{ + return b->height * tiler_vstride(b); +} + +/* Event types */ +#define TILER_DEVICE_CLOSE 0 + +/** + * Registers a notifier block with TILER driver. + * + * @param nb notifier_block + * + * @return error status + */ +s32 tiler_reg_notifier(struct notifier_block *nb); + +/** + * Un-registers a notifier block with TILER driver. + * + * @param nb notifier_block + * + * @return error status + */ +s32 tiler_unreg_notifier(struct notifier_block *nb); + +/** + * Get the physical address for a given user va. + * + * @param usr user virtual address + * + * @return valid pa or 0 for error + */ +u32 tiler_virt2phys(u32 usr); + +/** + * Reserves a 1D or 2D TILER block area and memory for the + * current process with group ID 0. + * + * @param blk pointer to tiler block data. This must be set up ('phys' member + * must be 0) with the tiler block information. 'height' must be 1 + * for 1D block. + * @param fmt TILER block format + * + * @return error status + */ +s32 tiler_alloc(struct tiler_block_t *blk, enum tiler_fmt fmt); + +/** + * Reserves a 1D or 2D TILER block area and memory for a set process and group + * ID. + * + * @param blk pointer to tiler block data. This must be set up ('phys' member + * must be 0) with the tiler block information. 'height' must be 1 + * for 1D block. + * @param fmt TILER block format + * @param gid group ID + * @param pid process ID + * + * @return error status + */ +s32 tiler_allocx(struct tiler_block_t *blk, enum tiler_fmt fmt, + u32 gid, pid_t pid); + +/** + * Mmaps a portion of a tiler block to a virtual address. Use this method in + * your driver's mmap function to potentially combine multiple tiler blocks as + * one virtual buffer. + * + * @param blk pointer to tiler block data + * @param offs offset from where to map (must be page aligned) + * @param size size of area to map (must be page aligned) + * @param vma VMM memory area to map to + * @param voffs offset (from vm_start) in the VMM memory area to start + * mapping at + * + * @return error status + */ +s32 tiler_mmap_blk(struct tiler_block_t *blk, u32 offs, u32 size, + struct vm_area_struct *vma, u32 voffs); + +/** + * Ioremaps a portion of a tiler block. Use this method in your driver instead + * of ioremap to potentially combine multiple tiler blocks as one virtual + * buffer. + * + * @param blk pointer to tiler block data + * @param offs offset from where to map (must be page aligned) + * @param size size of area to map (must be page aligned) + * @param addr virtual address + * @param mtype ioremap memory type (e.g. MT_DEVICE) + * + * @return error status + */ +s32 tiler_ioremap_blk(struct tiler_block_t *blk, u32 offs, u32 size, u32 addr, + u32 mtype); + +/** + * Maps an existing buffer to a 1D or 2D TILER area for the + * current process with group ID 0. + * + * Currently, only 1D area mapping is supported. + * + * NOTE: alignment is always PAGE_SIZE and offset is 0 as full pages are mapped + * into tiler container. + * + * @param blk pointer to tiler block data. This must be set up + * ('phys' member must be 0) with the tiler block + * information. 'height' must be 1 for 1D block. + * @param fmt TILER format + * @param usr_addr user space address of existing buffer. + * + * @return error status + */ +s32 tiler_map(struct tiler_block_t *blk, enum tiler_fmt fmt, u32 usr_addr); + +/** + * Maps an existing buffer to a 1D or 2D TILER area for a set process and group + * ID. + * + * Currently, only 1D area mapping is supported. + * + * NOTE: alignment is always PAGE_SIZE and offset is 0 as full pages are mapped + * into tiler container. + * + * @param blk pointer to tiler block data. This must be set up + * ('phys' member must be 0) with the tiler block + * information. 'height' must be 1 for 1D block. + * @param fmt TILER format + * @param gid group ID + * @param pid process ID + * @param usr_addr user space address of existing buffer. + * + * @return error status + */ +s32 tiler_mapx(struct tiler_block_t *blk, enum tiler_fmt fmt, + u32 gid, pid_t pid, u32 usr_addr); + +/** + * Frees TILER memory. Since there may be multiple references for the same area + * if duplicated by tiler_dup, the area is only actually freed if all references + * have been freed. + * + * @param blk pointer to a tiler block data as filled by tiler_alloc, + * tiler_map or tiler_dup. 'phys' and 'id' members will be set to + * 0 on success. + */ +void tiler_free(struct tiler_block_t *blk); + +/** + * Reserves tiler area for n identical blocks for the current process. Use this + * method to get optimal placement of multiple identical tiler blocks; however, + * it may not reserve area if tiler_alloc is equally efficient. + * + * @param n number of identical set of blocks + * @param fmt TILER format + * @param width block width + * @param height block height (must be 1 for 1D) + */ +void tiler_reserve(u32 n, enum tiler_fmt fmt, u32 width, u32 height); + +/** + * Reserves tiler area for n identical blocks. Use this method to get optimal + * placement of multiple identical tiler blocks; however, it may not reserve + * area if tiler_alloc is equally efficient. + * + * @param n number of identical set of blocks + * @param fmt TILER bit mode + * @param width block width + * @param height block height (must be 1 for 1D) + * @param gid group ID + * @param pid process ID + */ +void tiler_reservex(u32 n, enum tiler_fmt fmt, u32 width, u32 height, + u32 gid, pid_t pid); + +/** + * Reserves tiler area for n identical NV12 blocks for the current process. Use + * this method to get optimal placement of multiple identical NV12 tiler blocks; + * however, it may not reserve area if tiler_alloc is equally efficient. + * + * @param n number of identical set of blocks + * @param width block width (Y) + * @param height block height (Y) + */ +void tiler_reserve_nv12(u32 n, u32 width, u32 height); + +/** + * Reserves tiler area for n identical NV12 blocks. Use this method to get + * optimal placement of multiple identical NV12 tiler blocks; however, it may + * not reserve area if tiler_alloc is equally efficient. + * + * @param n number of identical set of blocks + * @param width block width (Y) + * @param height block height (Y) + * @param gid group ID + * @param pid process ID + */ +void tiler_reservex_nv12(u32 n, u32 width, u32 height, u32 gid, pid_t pid); + +/** + * Create a view based on a tiler address and width and height + * + * This method should only be used as a last resort, e.g. if tilview object + * cannot be passed because of incoherence with other view 2D objects that must + * be supported. + * + * @param view Pointer to a view where the information will be stored + * @param ssptr MUST BE a tiler address + * @param width view width + * @param height view height + */ +void tilview_create(struct tiler_view_t *view, u32 phys, u32 width, u32 height); + +/** + * Obtains the view information for a tiler block + * + * @param view Pointer to a view where the information will be stored + * @param blk Pointer to an existing allocated tiler block + */ +void tilview_get(struct tiler_view_t *view, struct tiler_block_t *blk); + +/** + * Crops a tiler view to a rectangular portion. Crop area must be fully within + * the orginal tiler view: 0 <= left <= left + width <= view->width, also: + * 0 <= top <= top + height <= view->height. + * + * @param view Pointer to tiler view to be cropped + * @param left x of top-left corner + * @param top y of top-left corner + * @param width crop width + * @param height crop height + * + * @return error status. The view will be reduced to the crop region if the + * crop region is correct. Otherwise, no modifications are made. + */ +s32 tilview_crop(struct tiler_view_t *view, u32 left, u32 top, u32 width, + u32 height); + +/** + * Rotates a tiler view clockwise by a specified degree. + * + * @param view Pointer to tiler view to be cropped + * @param rotate Degree of rotation (clockwise). Must be a multiple of + * 90. + * @return error status. View is not modified on error; otherwise, it is + * updated in place. + */ +s32 tilview_rotate(struct tiler_view_t *view, s32 rotation); + +/** + * Mirrors a tiler view horizontally and/or vertically. + * + * @param view Pointer to tiler view to be cropped + * @param flip_x Mirror horizontally (left-to-right) + * @param flip_y Mirror vertically (top-to-bottom) + * + * @return error status. View is not modified on error; otherwise, it is + * updated in place. + */ +s32 tilview_flip(struct tiler_view_t *view, bool flip_x, bool flip_y); + +/* + * -------------------- TILER hooks for ION/HWC migration -------------------- + */ + +/* type of tiler memory */ +enum tiler_memtype { + TILER_MEM_ALLOCED, /* tiler allocated the memory */ + TILER_MEM_GOT_PAGES, /* tiler used get_user_pages */ + TILER_MEM_USING, /* tiler is using the pages */ +}; + +/* physical pages to pin - mem must be kmalloced */ +struct tiler_pa_info { + u32 num_pg; /* number of pages in page-list */ + u32 *mem; /* list of phys page addresses */ + enum tiler_memtype memtype; /* how we got physical pages */ +}; + +typedef struct mem_info *tiler_blk_handle; + +/** + * Allocate a 1D area of container space in the Tiler + * + * @param pa ptr to tiler_pa_info structure + * + * @return handle Handle to tiler block information. NULL on error. + * + * NOTE: this will take ownership pa->mem (will free it) + * + */ +tiler_blk_handle tiler_map_1d_block(struct tiler_pa_info *pa); + +/** + * Allocate an area of container space in the Tiler + * + * @param fmt Tiler bpp mode + * @param width Width in pixels + * @param height Height in pixels + * @param ssptr Value of tiler physical address of allocation + * @param virt_array Array of physical address for the start of each virtual + page + * + * @return handle Handle to tiler block information. NULL on error. + * + * NOTE: For 1D allocations, specify the full size in the width field, and + * specify a height of 1. + */ +tiler_blk_handle tiler_alloc_block_area(enum tiler_fmt fmt, u32 width, + u32 height, u32 *ssptr, + u32 *virt_array); + +/** + * Free a reserved area in the Tiler + * + * @param handle Handle to tiler block information + * + */ +void tiler_free_block_area(tiler_blk_handle block); + +/** + * Pins a set of physical pages into the Tiler using the area defined in a + * handle + * + * @param handle Handle to tiler block information + * @param addr_array Array of addresses + * @param nents Number of addresses in array + * + * @return error status. + */ +s32 tiler_pin_block(tiler_blk_handle handle, u32 *addr_array, u32 nents); + +/** + * Unpins a set of physical pages from the Tiler + * + * @param handle Handle to tiler block information + * + */ +void tiler_unpin_block(tiler_blk_handle handle); + +/** + * Gives memory requirements for a given container allocation + * + * @param fmt Tiler bpp mode + * @param width Width in pixels + * @param height Height in pixels + * @param alloc_pages Number of pages required to back tiler container + * @param virt_pages Number of pages required to back the virtual address space + * + * @return 0 for success. Non zero for error + */ +s32 tiler_memsize(enum tiler_fmt fmt, u32 width, u32 height, u32 *alloc_pages, + u32 *virt_pages); + +/** + * Returns virtual stride of a tiler block + * + * @param handle Handle to tiler block allocation + * + * @return Size of virtual stride + */ +u32 tiler_block_vstride(tiler_blk_handle handle); + +struct tiler_pa_info *user_block_to_pa(u32 usr_addr, u32 num_pg); +void tiler_pa_free(struct tiler_pa_info *pa); + +/* + * ---------------------------- IOCTL Definitions ---------------------------- + */ + +/* ioctls */ +#define TILIOC_GBLK _IOWR('z', 100, struct tiler_block_info) +#define TILIOC_FBLK _IOW('z', 101, struct tiler_block_info) +#define TILIOC_GSSP _IOWR('z', 102, u32) +#define TILIOC_MBLK _IOWR('z', 103, struct tiler_block_info) +#define TILIOC_UMBLK _IOW('z', 104, struct tiler_block_info) +#define TILIOC_QBUF _IOWR('z', 105, struct tiler_buf_info) +#define TILIOC_RBUF _IOWR('z', 106, struct tiler_buf_info) +#define TILIOC_URBUF _IOWR('z', 107, struct tiler_buf_info) +#define TILIOC_QBLK _IOWR('z', 108, struct tiler_block_info) +#define TILIOC_PRBLK _IOW('z', 109, struct tiler_block_info) +#define TILIOC_URBLK _IOW('z', 110, u32) + +struct area { + u16 width; + u16 height; +}; + +/* userspace tiler block info */ +struct tiler_block_info { + enum tiler_fmt fmt; + union { + struct area area; + u32 len; + } dim; + u32 stride; /* stride is not maintained for 1D blocks */ + void *ptr; /* userspace address for mapping existing buffer */ + u32 id; + u32 key; + u32 group_id; + u32 ssptr; /* physical address, may not exposed by default */ +}; + +#define TILER_MAX_NUM_BLOCKS 16 + +/* userspace tiler buffer info */ +struct tiler_buf_info { + u32 num_blocks; + struct tiler_block_info blocks[TILER_MAX_NUM_BLOCKS]; + u32 offset; + u32 length; /* also used as number of buffers for reservation */ +}; + +#endif |