diff options
Diffstat (limited to 'arch/powerpc/boot')
24 files changed, 2657 insertions, 218 deletions
diff --git a/arch/powerpc/boot/4xx.c b/arch/powerpc/boot/4xx.c index 3d0e4f9..33f25b6 100644 --- a/arch/powerpc/boot/4xx.c +++ b/arch/powerpc/boot/4xx.c @@ -22,16 +22,14 @@ #include "dcr.h" /* Read the 4xx SDRAM controller to get size of system memory. */ -void ibm4xx_fixup_memsize(void) +void ibm4xx_sdram_fixup_memsize(void) { int i; unsigned long memsize, bank_config; memsize = 0; for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) { - mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]); - bank_config = mfdcr(DCRN_SDRAM0_CFGDATA); - + bank_config = SDRAM0_READ(sdram_bxcr[i]); if (bank_config & SDRAM_CONFIG_BANK_ENABLE) memsize += SDRAM_CONFIG_BANK_SIZE(bank_config); } @@ -39,6 +37,69 @@ void ibm4xx_fixup_memsize(void) dt_fixup_memory(0, memsize); } +/* Read the 440SPe MQ controller to get size of system memory. */ +#define DCRN_MQ0_B0BAS 0x40 +#define DCRN_MQ0_B1BAS 0x41 +#define DCRN_MQ0_B2BAS 0x42 +#define DCRN_MQ0_B3BAS 0x43 + +static u64 ibm440spe_decode_bas(u32 bas) +{ + u64 base = ((u64)(bas & 0xFFE00000u)) << 2; + + /* open coded because I'm paranoid about invalid values */ + switch ((bas >> 4) & 0xFFF) { + case 0: + return 0; + case 0xffc: + return base + 0x000800000ull; + case 0xff8: + return base + 0x001000000ull; + case 0xff0: + return base + 0x002000000ull; + case 0xfe0: + return base + 0x004000000ull; + case 0xfc0: + return base + 0x008000000ull; + case 0xf80: + return base + 0x010000000ull; + case 0xf00: + return base + 0x020000000ull; + case 0xe00: + return base + 0x040000000ull; + case 0xc00: + return base + 0x080000000ull; + case 0x800: + return base + 0x100000000ull; + } + printf("Memory BAS value 0x%08x unsupported !\n", bas); + return 0; +} + +void ibm440spe_fixup_memsize(void) +{ + u64 banktop, memsize = 0; + + /* Ultimately, we should directly construct the memory node + * so we are able to handle holes in the memory address space + */ + banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS)); + if (banktop > memsize) + memsize = banktop; + banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS)); + if (banktop > memsize) + memsize = banktop; + banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS)); + if (banktop > memsize) + memsize = banktop; + banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS)); + if (banktop > memsize) + memsize = banktop; + + dt_fixup_memory(0, memsize); +} + + /* 4xx DDR1/2 Denali memory controller support */ /* DDR0 registers */ #define DDR0_02 2 @@ -77,19 +138,13 @@ void ibm4xx_fixup_memsize(void) #define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask)) -static inline u32 mfdcr_sdram0(u32 reg) -{ - mtdcr(DCRN_SDRAM0_CFGADDR, reg); - return mfdcr(DCRN_SDRAM0_CFGDATA); -} - void ibm4xx_denali_fixup_memsize(void) { u32 val, max_cs, max_col, max_row; u32 cs, col, row, bank, dpath; unsigned long memsize; - val = mfdcr_sdram0(DDR0_02); + val = SDRAM0_READ(DDR0_02); if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT)) fatal("DDR controller is not initialized\n"); @@ -99,7 +154,7 @@ void ibm4xx_denali_fixup_memsize(void) max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT); /* get CS value */ - val = mfdcr_sdram0(DDR0_10); + val = SDRAM0_READ(DDR0_10); val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT); cs = 0; @@ -115,7 +170,7 @@ void ibm4xx_denali_fixup_memsize(void) fatal("DDR wrong CS configuration\n"); /* get data path bytes */ - val = mfdcr_sdram0(DDR0_14); + val = SDRAM0_READ(DDR0_14); if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT)) dpath = 8; /* 64 bits */ @@ -123,7 +178,7 @@ void ibm4xx_denali_fixup_memsize(void) dpath = 4; /* 32 bits */ /* get address pins (rows) */ - val = mfdcr_sdram0(DDR0_42); + val = SDRAM0_READ(DDR0_42); row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT); if (row > max_row) @@ -131,7 +186,7 @@ void ibm4xx_denali_fixup_memsize(void) row = max_row - row; /* get collomn size and banks */ - val = mfdcr_sdram0(DDR0_43); + val = SDRAM0_READ(DDR0_43); col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT); if (col > max_col) @@ -179,13 +234,17 @@ void ibm40x_dbcr_reset(void) #define EMAC_RESET 0x20000000 void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1) { - /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't do this for us */ + /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't + * do this for us + */ if (emac0) *emac0 = EMAC_RESET; if (emac1) *emac1 = EMAC_RESET; mtdcr(DCRN_MAL0_CFG, MAL_RESET); + while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET) + ; /* loop until reset takes effect */ } /* Read 4xx EBC bus bridge registers to get mappings of the peripheral @@ -217,84 +276,268 @@ void ibm4xx_fixup_ebc_ranges(const char *ebc) setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32)); } -#define SPRN_CCR1 0x378 -void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk) +/* Calculate 440GP clocks */ +void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk) { - u32 cpu, plb, opb, ebc, tb, uart0, m, vco; - u32 reg; - u32 fwdva, fwdvb, fbdv, lfbdv, opbdv0, perdv0, spcid0, prbdv0, tmp; - - mtdcr(DCRN_CPR0_ADDR, CPR0_PLLD0); - reg = mfdcr(DCRN_CPR0_DATA); - tmp = (reg & 0x000F0000) >> 16; - fwdva = tmp ? tmp : 16; - tmp = (reg & 0x00000700) >> 8; - fwdvb = tmp ? tmp : 8; - tmp = (reg & 0x1F000000) >> 24; - fbdv = tmp ? tmp : 32; - lfbdv = (reg & 0x0000007F); - - mtdcr(DCRN_CPR0_ADDR, CPR0_OPBD0); - reg = mfdcr(DCRN_CPR0_DATA); - tmp = (reg & 0x03000000) >> 24; - opbdv0 = tmp ? tmp : 4; - - mtdcr(DCRN_CPR0_ADDR, CPR0_PERD0); - reg = mfdcr(DCRN_CPR0_DATA); - tmp = (reg & 0x07000000) >> 24; - perdv0 = tmp ? tmp : 8; - - mtdcr(DCRN_CPR0_ADDR, CPR0_PRIMBD0); - reg = mfdcr(DCRN_CPR0_DATA); - tmp = (reg & 0x07000000) >> 24; - prbdv0 = tmp ? tmp : 8; - - mtdcr(DCRN_CPR0_ADDR, CPR0_SCPID); - reg = mfdcr(DCRN_CPR0_DATA); - tmp = (reg & 0x03000000) >> 24; - spcid0 = tmp ? tmp : 4; - - /* Calculate M */ - mtdcr(DCRN_CPR0_ADDR, CPR0_PLLC0); - reg = mfdcr(DCRN_CPR0_DATA); - tmp = (reg & 0x03000000) >> 24; - if (tmp == 0) { /* PLL output */ - tmp = (reg & 0x20000000) >> 29; - if (!tmp) /* PLLOUTA */ - m = fbdv * lfbdv * fwdva; + u32 sys0 = mfdcr(DCRN_CPC0_SYS0); + u32 cr0 = mfdcr(DCRN_CPC0_CR0); + u32 cpu, plb, opb, ebc, tb, uart0, uart1, m; + u32 opdv = CPC0_SYS0_OPDV(sys0); + u32 epdv = CPC0_SYS0_EPDV(sys0); + + if (sys0 & CPC0_SYS0_BYPASS) { + /* Bypass system PLL */ + cpu = plb = sys_clk; + } else { + if (sys0 & CPC0_SYS0_EXTSL) + /* PerClk */ + m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv; else - m = fbdv * lfbdv * fwdvb; + /* CPU clock */ + m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0); + cpu = sys_clk * m / CPC0_SYS0_FWDVA(sys0); + plb = sys_clk * m / CPC0_SYS0_FWDVB(sys0); } - else if (tmp == 1) /* CPU output */ - m = fbdv * fwdva; + + opb = plb / opdv; + ebc = opb / epdv; + + /* FIXME: Check if this is for all 440GP, or just Ebony */ + if ((mfpvr() & 0xf0000fff) == 0x40000440) + /* Rev. B 440GP, use external system clock */ + tb = sys_clk; else - m = perdv0 * opbdv0 * fwdvb; + /* Rev. C 440GP, errata force us to use internal clock */ + tb = cpu; - vco = (m * sysclk) + (m >> 1); - cpu = vco / fwdva; - plb = vco / fwdvb / prbdv0; - opb = plb / opbdv0; - ebc = plb / perdv0; + if (cr0 & CPC0_CR0_U0EC) + /* External UART clock */ + uart0 = ser_clk; + else + /* Internal UART clock */ + uart0 = plb / CPC0_CR0_UDIV(cr0); + + if (cr0 & CPC0_CR0_U1EC) + /* External UART clock */ + uart1 = ser_clk; + else + /* Internal UART clock */ + uart1 = plb / CPC0_CR0_UDIV(cr0); + + printf("PPC440GP: SysClk = %dMHz (%x)\n\r", + (sys_clk + 500000) / 1000000, sys_clk); + + dt_fixup_cpu_clocks(cpu, tb, 0); - /* FIXME */ - uart0 = ser_clk; + dt_fixup_clock("/plb", plb); + dt_fixup_clock("/plb/opb", opb); + dt_fixup_clock("/plb/opb/ebc", ebc); + dt_fixup_clock("/plb/opb/serial@40000200", uart0); + dt_fixup_clock("/plb/opb/serial@40000300", uart1); +} + +#define SPRN_CCR1 0x378 + +static inline u32 __fix_zero(u32 v, u32 def) +{ + return v ? v : def; +} + +static unsigned int __ibm440eplike_fixup_clocks(unsigned int sys_clk, + unsigned int tmr_clk, + int per_clk_from_opb) +{ + /* PLL config */ + u32 pllc = CPR0_READ(DCRN_CPR0_PLLC); + u32 plld = CPR0_READ(DCRN_CPR0_PLLD); + + /* Dividers */ + u32 fbdv = __fix_zero((plld >> 24) & 0x1f, 32); + u32 fwdva = __fix_zero((plld >> 16) & 0xf, 16); + u32 fwdvb = __fix_zero((plld >> 8) & 7, 8); + u32 lfbdv = __fix_zero(plld & 0x3f, 64); + u32 pradv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMAD) >> 24) & 7, 8); + u32 prbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMBD) >> 24) & 7, 8); + u32 opbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_OPBD) >> 24) & 3, 4); + u32 perdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PERD) >> 24) & 3, 4); + + /* Input clocks for primary dividers */ + u32 clk_a, clk_b; + + /* Resulting clocks */ + u32 cpu, plb, opb, ebc, vco; + + /* Timebase */ + u32 ccr1, tb = tmr_clk; + + if (pllc & 0x40000000) { + u32 m; + + /* Feedback path */ + switch ((pllc >> 24) & 7) { + case 0: + /* PLLOUTx */ + m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv; + break; + case 1: + /* CPU */ + m = fwdva * pradv0; + break; + case 5: + /* PERClk */ + m = fwdvb * prbdv0 * opbdv0 * perdv0; + break; + default: + printf("WARNING ! Invalid PLL feedback source !\n"); + goto bypass; + } + m *= fbdv; + vco = sys_clk * m; + clk_a = vco / fwdva; + clk_b = vco / fwdvb; + } else { +bypass: + /* Bypass system PLL */ + vco = 0; + clk_a = clk_b = sys_clk; + } + + cpu = clk_a / pradv0; + plb = clk_b / prbdv0; + opb = plb / opbdv0; + ebc = (per_clk_from_opb ? opb : plb) / perdv0; /* Figure out timebase. Either CPU or default TmrClk */ - asm volatile ( - "mfspr %0,%1\n" - : - "=&r"(reg) : "i"(SPRN_CCR1)); - if (reg & 0x0080) - tb = 25000000; /* TmrClk is 25MHz */ - else + ccr1 = mfspr(SPRN_CCR1); + + /* If passed a 0 tmr_clk, force CPU clock */ + if (tb == 0) { + ccr1 &= ~0x80u; + mtspr(SPRN_CCR1, ccr1); + } + if ((ccr1 & 0x0080) == 0) tb = cpu; dt_fixup_cpu_clocks(cpu, tb, 0); dt_fixup_clock("/plb", plb); dt_fixup_clock("/plb/opb", opb); dt_fixup_clock("/plb/opb/ebc", ebc); + + return plb; +} + +static void eplike_fixup_uart_clk(int index, const char *path, + unsigned int ser_clk, + unsigned int plb_clk) +{ + unsigned int sdr; + unsigned int clock; + + switch (index) { + case 0: + sdr = SDR0_READ(DCRN_SDR0_UART0); + break; + case 1: + sdr = SDR0_READ(DCRN_SDR0_UART1); + break; + case 2: + sdr = SDR0_READ(DCRN_SDR0_UART2); + break; + case 3: + sdr = SDR0_READ(DCRN_SDR0_UART3); + break; + default: + return; + } + + if (sdr & 0x00800000u) + clock = ser_clk; + else + clock = plb_clk / __fix_zero(sdr & 0xff, 256); + + dt_fixup_clock(path, clock); +} + +void ibm440ep_fixup_clocks(unsigned int sys_clk, + unsigned int ser_clk, + unsigned int tmr_clk) +{ + unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0); + + /* serial clocks beed fixup based on int/ext */ + eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk); + eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk); + eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk); + eplike_fixup_uart_clk(3, "/plb/opb/serial@ef600600", ser_clk, plb_clk); +} + +void ibm440gx_fixup_clocks(unsigned int sys_clk, + unsigned int ser_clk, + unsigned int tmr_clk) +{ + unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1); + + /* serial clocks beed fixup based on int/ext */ + eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk); + eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk); +} + +void ibm440spe_fixup_clocks(unsigned int sys_clk, + unsigned int ser_clk, + unsigned int tmr_clk) +{ + unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1); + + /* serial clocks beed fixup based on int/ext */ + eplike_fixup_uart_clk(0, "/plb/opb/serial@10000200", ser_clk, plb_clk); + eplike_fixup_uart_clk(1, "/plb/opb/serial@10000300", ser_clk, plb_clk); + eplike_fixup_uart_clk(2, "/plb/opb/serial@10000600", ser_clk, plb_clk); +} + +void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk) +{ + u32 pllmr = mfdcr(DCRN_CPC0_PLLMR); + u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0); + u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1); + u32 cpu, plb, opb, ebc, tb, uart0, uart1, m; + u32 fwdv, fbdv, cbdv, opdv, epdv, udiv; + + fwdv = (8 - ((pllmr & 0xe0000000) >> 29)); + fbdv = (pllmr & 0x1e000000) >> 25; + cbdv = ((pllmr & 0x00060000) >> 17) + 1; + opdv = ((pllmr & 0x00018000) >> 15) + 1; + epdv = ((pllmr & 0x00001800) >> 13) + 2; + udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1; + + m = fwdv * fbdv * cbdv; + + cpu = sys_clk * m / fwdv; + plb = cpu / cbdv; + opb = plb / opdv; + ebc = plb / epdv; + + if (cpc0_cr0 & 0x80) + /* uart0 uses the external clock */ + uart0 = ser_clk; + else + uart0 = cpu / udiv; + + if (cpc0_cr0 & 0x40) + /* uart1 uses the external clock */ + uart1 = ser_clk; + else + uart1 = cpu / udiv; + + /* setup the timebase clock to tick at the cpu frequency */ + cpc0_cr1 = cpc0_cr1 & ~0x00800000; + mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1); + tb = cpu; + + dt_fixup_cpu_clocks(cpu, tb, 0); + dt_fixup_clock("/plb", plb); + dt_fixup_clock("/plb/opb", opb); + dt_fixup_clock("/plb/ebc", ebc); dt_fixup_clock("/plb/opb/serial@ef600300", uart0); - dt_fixup_clock("/plb/opb/serial@ef600400", uart0); - dt_fixup_clock("/plb/opb/serial@ef600500", uart0); - dt_fixup_clock("/plb/opb/serial@ef600600", uart0); + dt_fixup_clock("/plb/opb/serial@ef600400", uart1); } + diff --git a/arch/powerpc/boot/4xx.h b/arch/powerpc/boot/4xx.h index adba6a5..fbe0632 100644 --- a/arch/powerpc/boot/4xx.h +++ b/arch/powerpc/boot/4xx.h @@ -11,12 +11,21 @@ #ifndef _POWERPC_BOOT_4XX_H_ #define _POWERPC_BOOT_4XX_H_ -void ibm4xx_fixup_memsize(void); +void ibm4xx_sdram_fixup_memsize(void); +void ibm440spe_fixup_memsize(void); void ibm4xx_denali_fixup_memsize(void); void ibm44x_dbcr_reset(void); void ibm40x_dbcr_reset(void); void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1); void ibm4xx_fixup_ebc_ranges(const char *ebc); -void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk); + +void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk); +void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk); +void ibm440ep_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk, + unsigned int tmr_clk); +void ibm440gx_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk, + unsigned int tmr_clk); +void ibm440spe_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk, + unsigned int tmr_clk); #endif /* _POWERPC_BOOT_4XX_H_ */ diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile index 9149bb8..d1e625c 100644 --- a/arch/powerpc/boot/Makefile +++ b/arch/powerpc/boot/Makefile @@ -37,8 +37,11 @@ BOOTCFLAGS += -I$(obj) -I$(srctree)/$(obj) -I$(srctree)/$(src)/libfdt $(obj)/4xx.o: BOOTCFLAGS += -mcpu=440 $(obj)/ebony.o: BOOTCFLAGS += -mcpu=440 +$(obj)/cuboot-taishan.o: BOOTCFLAGS += -mcpu=440 +$(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=440 $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405 + zlib := inffast.c inflate.c inftrees.c zlibheader := inffast.h inffixed.h inflate.h inftrees.h infutil.h zliblinuxheader := zlib.h zconf.h zutil.h @@ -58,7 +61,8 @@ src-plat := of.c cuboot-52xx.c cuboot-83xx.c cuboot-85xx.c holly.c \ cuboot-ebony.c treeboot-ebony.c prpmc2800.c \ ps3-head.S ps3-hvcall.S ps3.c treeboot-bamboo.c cuboot-8xx.c \ cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c cuboot-bamboo.c \ - fixed-head.S ep88xc.c cuboot-hpc2.c + fixed-head.S ep88xc.c cuboot-hpc2.c ep405.c cuboot-taishan.c \ + cuboot-katmai.c cuboot-rainier.c src-boot := $(src-wlib) $(src-plat) empty.c src-boot := $(addprefix $(obj)/, $(src-boot)) @@ -189,6 +193,7 @@ image-$(CONFIG_DEFAULT_UIMAGE) += uImage ifneq ($(CONFIG_DEVICE_TREE),"") image-$(CONFIG_PPC_8xx) += cuImage.8xx image-$(CONFIG_PPC_EP88XC) += zImage.ep88xc +image-$(CONFIG_EP405) += zImage.ep405 image-$(CONFIG_8260) += cuImage.pq2 image-$(CONFIG_PPC_MPC52xx) += cuImage.52xx image-$(CONFIG_PPC_83xx) += cuImage.83xx @@ -197,7 +202,10 @@ image-$(CONFIG_MPC7448HPC2) += cuImage.hpc2 image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony image-$(CONFIG_BAMBOO) += treeImage.bamboo cuImage.bamboo image-$(CONFIG_SEQUOIA) += cuImage.sequoia +image-$(CONFIG_RAINIER) += cuImage.rainier image-$(CONFIG_WALNUT) += treeImage.walnut +image-$(CONFIG_TAISHAN) += cuImage.taishan +image-$(CONFIG_KATMAI) += cuImage.katmai endif # For 32-bit powermacs, build the COFF and miboot images diff --git a/arch/powerpc/boot/bamboo.c b/arch/powerpc/boot/bamboo.c index e634359..54b33f1 100644 --- a/arch/powerpc/boot/bamboo.c +++ b/arch/powerpc/boot/bamboo.c @@ -30,8 +30,8 @@ static void bamboo_fixups(void) { unsigned long sysclk = 33333333; - ibm440ep_fixup_clocks(sysclk, 11059200); - ibm4xx_fixup_memsize(); + ibm440ep_fixup_clocks(sysclk, 11059200, 25000000); + ibm4xx_sdram_fixup_memsize(); ibm4xx_quiesce_eth((u32 *)0xef600e00, (u32 *)0xef600f00); dt_fixup_mac_addresses(bamboo_mac0, bamboo_mac1); } diff --git a/arch/powerpc/boot/cuboot-katmai.c b/arch/powerpc/boot/cuboot-katmai.c new file mode 100644 index 0000000..c021167 --- /dev/null +++ b/arch/powerpc/boot/cuboot-katmai.c @@ -0,0 +1,56 @@ +/* + * Old U-boot compatibility for Katmai + * + * Author: Hugh Blemings <hugh@au.ibm.com> + * + * Copyright 2007 Hugh Blemings, IBM Corporation. + * Based on cuboot-ebony.c which is: + * Copyright 2007 David Gibson, IBM Corporation. + * Based on cuboot-83xx.c, which is: + * Copyright (c) 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ops.h" +#include "stdio.h" +#include "reg.h" +#include "dcr.h" +#include "4xx.h" +#include "44x.h" +#include "cuboot.h" + +#define TARGET_44x +#include "ppcboot.h" + +static bd_t bd; + +BSS_STACK(4096); + +static void katmai_fixups(void) +{ + unsigned long sysclk = 33333000; + + /* 440SP Clock logic is all but identical to 440GX + * so we just use that code for now at least + */ + ibm440spe_fixup_clocks(sysclk, 6 * 1843200, 0); + + ibm440spe_fixup_memsize(); + + dt_fixup_mac_address(0, bd.bi_enetaddr); + + ibm4xx_fixup_ebc_ranges("/plb/opb/ebc"); +} + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + CUBOOT_INIT(); + + platform_ops.fixups = katmai_fixups; + fdt_init(_dtb_start); + serial_console_init(); +} diff --git a/arch/powerpc/boot/cuboot-rainier.c b/arch/powerpc/boot/cuboot-rainier.c new file mode 100644 index 0000000..cf452b6 --- /dev/null +++ b/arch/powerpc/boot/cuboot-rainier.c @@ -0,0 +1,56 @@ +/* + * Old U-boot compatibility for Rainier + * + * Valentine Barshak <vbarshak@ru.mvista.com> + * Copyright 2007 MontaVista Software, Inc + * + * Based on Ebony code by David Gibson <david@gibson.dropbear.id.au> + * Copyright IBM Corporation, 2007 + * + * Based on Bamboo code by Josh Boyer <jwboyer@linux.vnet.ibm.com> + * Copyright IBM Corporation, 2007 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; version 2 of the License + */ + +#include <stdarg.h> +#include <stddef.h> +#include "types.h" +#include "elf.h" +#include "string.h" +#include "stdio.h" +#include "page.h" +#include "ops.h" +#include "dcr.h" +#include "4xx.h" +#include "44x.h" +#include "cuboot.h" + +#define TARGET_4xx +#define TARGET_44x +#include "ppcboot.h" + +static bd_t bd; + + +static void rainier_fixups(void) +{ + unsigned long sysclk = 33333333; + + ibm440ep_fixup_clocks(sysclk, 11059200, 50000000); + ibm4xx_fixup_ebc_ranges("/plb/opb/ebc"); + ibm4xx_denali_fixup_memsize(); + dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr); +} + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + CUBOOT_INIT(); + platform_ops.fixups = rainier_fixups; + platform_ops.exit = ibm44x_dbcr_reset; + fdt_init(_dtb_start); + serial_console_init(); +} diff --git a/arch/powerpc/boot/cuboot-sequoia.c b/arch/powerpc/boot/cuboot-sequoia.c index cf78260..f555575 100644 --- a/arch/powerpc/boot/cuboot-sequoia.c +++ b/arch/powerpc/boot/cuboot-sequoia.c @@ -39,7 +39,7 @@ static void sequoia_fixups(void) { unsigned long sysclk = 33333333; - ibm440ep_fixup_clocks(sysclk, 11059200); + ibm440ep_fixup_clocks(sysclk, 11059200, 50000000); ibm4xx_fixup_ebc_ranges("/plb/opb/ebc"); ibm4xx_denali_fixup_memsize(); dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr); diff --git a/arch/powerpc/boot/cuboot-taishan.c b/arch/powerpc/boot/cuboot-taishan.c new file mode 100644 index 0000000..f66455a --- /dev/null +++ b/arch/powerpc/boot/cuboot-taishan.c @@ -0,0 +1,54 @@ +/* + * Old U-boot compatibility for Taishan + * + * Author: Hugh Blemings <hugh@au.ibm.com> + * + * Copyright 2007 Hugh Blemings, IBM Corporation. + * Based on cuboot-ebony.c which is: + * Copyright 2007 David Gibson, IBM Corporation. + * Based on cuboot-83xx.c, which is: + * Copyright (c) 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ops.h" +#include "stdio.h" +#include "cuboot.h" +#include "reg.h" +#include "dcr.h" +#include "4xx.h" + +#define TARGET_44x +#include "ppcboot.h" + +static bd_t bd; + +BSS_STACK(4096); + +static void taishan_fixups(void) +{ + /* FIXME: sysclk should be derived by reading the FPGA + registers */ + unsigned long sysclk = 33000000; + + ibm440gx_fixup_clocks(sysclk, 6 * 1843200, 25000000); + + ibm4xx_sdram_fixup_memsize(); + + dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr); + + ibm4xx_fixup_ebc_ranges("/plb/opb/ebc"); +} + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + CUBOOT_INIT(); + + platform_ops.fixups = taishan_fixups; + fdt_init(_dtb_start); + serial_console_init(); +} diff --git a/arch/powerpc/boot/dcr.h b/arch/powerpc/boot/dcr.h index 83b88aa..55655f7 100644 --- a/arch/powerpc/boot/dcr.h +++ b/arch/powerpc/boot/dcr.h @@ -14,12 +14,20 @@ #define DCRN_SDRAM0_CFGADDR 0x010 #define DCRN_SDRAM0_CFGDATA 0x011 +#define SDRAM0_READ(offset) ({\ + mtdcr(DCRN_SDRAM0_CFGADDR, offset); \ + mfdcr(DCRN_SDRAM0_CFGDATA); }) +#define SDRAM0_WRITE(offset, data) ({\ + mtdcr(DCRN_SDRAM0_CFGADDR, offset); \ + mtdcr(DCRN_SDRAM0_CFGDATA, data); }) + #define SDRAM0_B0CR 0x40 #define SDRAM0_B1CR 0x44 #define SDRAM0_B2CR 0x48 #define SDRAM0_B3CR 0x4c -static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2CR, SDRAM0_B3CR }; +static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, + SDRAM0_B2CR, SDRAM0_B3CR }; #define SDRAM_CONFIG_BANK_ENABLE 0x00000001 #define SDRAM_CONFIG_SIZE_MASK 0x000e0000 @@ -139,4 +147,48 @@ static const unsigned long sdram_bxcr[] = { SDRAM0_B0CR, SDRAM0_B1CR, SDRAM0_B2C #define DCRN_405_CPC0_CR0 0xb1 #define DCRN_405_CPC0_CR1 0xb2 + +/* 440GX Clock control etc */ + + +#define DCRN_CPR0_CLKUPD 0x020 +#define DCRN_CPR0_PLLC 0x040 +#define DCRN_CPR0_PLLD 0x060 +#define DCRN_CPR0_PRIMAD 0x080 +#define DCRN_CPR0_PRIMBD 0x0a0 +#define DCRN_CPR0_OPBD 0x0c0 +#define DCRN_CPR0_PERD 0x0e0 +#define DCRN_CPR0_MALD 0x100 + +#define DCRN_SDR0_CONFIG_ADDR 0xe +#define DCRN_SDR0_CONFIG_DATA 0xf + +/* SDR read/write helper macros */ +#define SDR0_READ(offset) ({\ + mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \ + mfdcr(DCRN_SDR0_CONFIG_DATA); }) +#define SDR0_WRITE(offset, data) ({\ + mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \ + mtdcr(DCRN_SDR0_CONFIG_DATA, data); }) + +#define DCRN_SDR0_UART0 0x0120 +#define DCRN_SDR0_UART1 0x0121 +#define DCRN_SDR0_UART2 0x0122 +#define DCRN_SDR0_UART3 0x0123 + + +/* CPRs read/write helper macros - based off include/asm-ppc/ibm44x.h */ + +#define DCRN_CPR0_CFGADDR 0xc +#define DCRN_CPR0_CFGDATA 0xd + +#define CPR0_READ(offset) ({\ + mtdcr(DCRN_CPR0_CFGADDR, offset); \ + mfdcr(DCRN_CPR0_CFGDATA); }) +#define CPR0_WRITE(offset, data) ({\ + mtdcr(DCRN_CPR0_CFGADDR, offset); \ + mtdcr(DCRN_CPR0_CFGDATA, data); }) + + + #endif /* _PPC_BOOT_DCR_H_ */ diff --git a/arch/powerpc/boot/dts/bamboo.dts b/arch/powerpc/boot/dts/bamboo.dts index cb2fb50..29f1a6f 100644 --- a/arch/powerpc/boot/dts/bamboo.dts +++ b/arch/powerpc/boot/dts/bamboo.dts @@ -16,14 +16,24 @@ #size-cells = <1>; model = "amcc,bamboo"; compatible = "amcc,bamboo"; - dcr-parent = <&/cpus/PowerPC,440EP@0>; + dcr-parent = <&/cpus/cpu@0>; + + aliases { + ethernet0 = &EMAC0; + ethernet1 = &EMAC1; + serial0 = &UART0; + serial1 = &UART1; + serial2 = &UART2; + serial3 = &UART3; + }; cpus { #address-cells = <1>; #size-cells = <0>; - PowerPC,440EP@0 { + cpu@0 { device_type = "cpu"; + model = "PowerPC,440EP"; reg = <0>; clock-frequency = <0>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ @@ -126,7 +136,6 @@ #address-cells = <2>; #size-cells = <1>; clock-frequency = <0>; /* Filled in by zImage */ - ranges; interrupts = <5 1>; interrupt-parent = <&UIC1>; }; @@ -238,11 +247,56 @@ zmii-device = <&ZMII0>; zmii-channel = <1>; }; + + usb@ef601000 { + compatible = "ohci-be"; + reg = <ef601000 80>; + interrupts = <8 1 9 1>; + interrupt-parent = < &UIC1 >; + }; + }; + + PCI0: pci@ec000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb440ep-pci", "ibm,plb-pci"; + primary; + reg = <0 eec00000 8 /* Config space access */ + 0 eed00000 4 /* IACK */ + 0 eed00000 4 /* Special cycle */ + 0 ef400000 40>; /* Internal registers */ + + /* Outbound ranges, one memory and one IO, + * later cannot be changed. Chip supports a second + * IO range but we don't use it for now + */ + ranges = <02000000 0 a0000000 0 a0000000 0 20000000 + 01000000 0 00000000 0 e8000000 0 00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 0 80000000>; + + /* Bamboo has all 4 IRQ pins tied together per slot */ + interrupt-map-mask = <f800 0 0 0>; + interrupt-map = < + /* IDSEL 1 */ + 0800 0 0 0 &UIC0 1c 8 + + /* IDSEL 2 */ + 1000 0 0 0 &UIC0 1b 8 + + /* IDSEL 3 */ + 1800 0 0 0 &UIC0 1a 8 + + /* IDSEL 4 */ + 2000 0 0 0 &UIC0 19 8 + >; }; }; chosen { linux,stdout-path = "/plb/opb/serial@ef600300"; - bootargs = "console=ttyS0,115200"; }; }; diff --git a/arch/powerpc/boot/dts/ebony.dts b/arch/powerpc/boot/dts/ebony.dts index bc25997..f8790c4 100644 --- a/arch/powerpc/boot/dts/ebony.dts +++ b/arch/powerpc/boot/dts/ebony.dts @@ -16,14 +16,22 @@ #size-cells = <1>; model = "ibm,ebony"; compatible = "ibm,ebony"; - dcr-parent = <&/cpus/PowerPC,440GP@0>; + dcr-parent = <&/cpus/cpu@0>; + + aliases { + ethernet0 = &EMAC0; + ethernet1 = &EMAC1; + serial0 = &UART0; + serial1 = &UART1; + }; cpus { #address-cells = <1>; #size-cells = <0>; - PowerPC,440GP@0 { + cpu@0 { device_type = "cpu"; + model = "PowerPC,440GP"; reg = <0>; clock-frequency = <0>; // Filled in by zImage timebase-frequency = <0>; // Filled in by zImage @@ -284,12 +292,43 @@ }; - PCIX0: pci@1234 { + PCIX0: pci@20ec00000 { device_type = "pci"; - /* FIXME */ - reg = <2 0ec00000 8 - 2 0ec80000 f0 - 2 0ec80100 fc>; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix"; + primary; + reg = <2 0ec00000 8 /* Config space access */ + 0 0 0 /* no IACK cycles */ + 2 0ed00000 4 /* Special cycles */ + 2 0ec80000 f0 /* Internal registers */ + 2 0ec80100 fc>; /* Internal messaging registers */ + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <02000000 0 80000000 00000003 80000000 0 80000000 + 01000000 0 00000000 00000002 08000000 0 00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 0 80000000>; + + /* Ebony has all 4 IRQ pins tied together per slot */ + interrupt-map-mask = <f800 0 0 0>; + interrupt-map = < + /* IDSEL 1 */ + 0800 0 0 0 &UIC0 17 8 + + /* IDSEL 2 */ + 1000 0 0 0 &UIC0 18 8 + + /* IDSEL 3 */ + 1800 0 0 0 &UIC0 19 8 + + /* IDSEL 4 */ + 2000 0 0 0 &UIC0 1a 8 + >; }; }; diff --git a/arch/powerpc/boot/dts/ep405.dts b/arch/powerpc/boot/dts/ep405.dts new file mode 100644 index 0000000..9293855 --- /dev/null +++ b/arch/powerpc/boot/dts/ep405.dts @@ -0,0 +1,228 @@ +/* + * Device Tree Source for EP405 + * + * Copyright 2007 IBM Corp. + * Benjamin Herrenschmidt <benh@kernel.crashing.org> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "ep405"; + compatible = "ep405"; + dcr-parent = <&/cpus/cpu@0>; + + aliases { + ethernet0 = &EMAC; + serial0 = &UART0; + serial1 = &UART1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,405GP"; + reg = <0>; + clock-frequency = <bebc200>; /* Filled in by zImage */ + timebase-frequency = <0>; /* Filled in by zImage */ + i-cache-line-size = <20>; + d-cache-line-size = <20>; + i-cache-size = <4000>; + d-cache-size = <4000>; + dcr-controller; + dcr-access-method = "native"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0>; /* Filled in by zImage */ + }; + + UIC0: interrupt-controller { + compatible = "ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0c0 9>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + plb { + compatible = "ibm,plb3"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; /* Filled in by zImage */ + + SDRAM0: memory-controller { + compatible = "ibm,sdram-405gp"; + dcr-reg = <010 2>; + }; + + MAL: mcmal { + compatible = "ibm,mcmal-405gp", "ibm,mcmal"; + dcr-reg = <180 62>; + num-tx-chans = <1>; + num-rx-chans = <1>; + interrupt-parent = <&UIC0>; + interrupts = < + b 4 /* TXEOB */ + c 4 /* RXEOB */ + a 4 /* SERR */ + d 4 /* TXDE */ + e 4 /* RXDE */>; + }; + + POB0: opb { + compatible = "ibm,opb-405gp", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <ef600000 ef600000 a00000>; + dcr-reg = <0a0 5>; + clock-frequency = <0>; /* Filled in by zImage */ + + UART0: serial@ef600300 { + device_type = "serial"; + compatible = "ns16550"; + reg = <ef600300 8>; + virtual-reg = <ef600300>; + clock-frequency = <0>; /* Filled in by zImage */ + current-speed = <2580>; + interrupt-parent = <&UIC0>; + interrupts = <0 4>; + }; + + UART1: serial@ef600400 { + device_type = "serial"; + compatible = "ns16550"; + reg = <ef600400 8>; + virtual-reg = <ef600400>; + clock-frequency = <0>; /* Filled in by zImage */ + current-speed = <2580>; + interrupt-parent = <&UIC0>; + interrupts = <1 4>; + }; + + IIC: i2c@ef600500 { + compatible = "ibm,iic-405gp", "ibm,iic"; + reg = <ef600500 11>; + interrupt-parent = <&UIC0>; + interrupts = <2 4>; + }; + + GPIO: gpio@ef600700 { + compatible = "ibm,gpio-405gp"; + reg = <ef600700 20>; + }; + + EMAC: ethernet@ef600800 { + linux,network-index = <0>; + device_type = "network"; + compatible = "ibm,emac-405gp", "ibm,emac"; + interrupt-parent = <&UIC0>; + interrupts = < + f 4 /* Ethernet */ + 9 4 /* Ethernet Wake Up */>; + local-mac-address = [000000000000]; /* Filled in by zImage */ + reg = <ef600800 70>; + mal-device = <&MAL>; + mal-tx-channel = <0>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rmii"; + phy-map = <00000000>; + }; + + }; + + EBC0: ebc { + compatible = "ibm,ebc-405gp", "ibm,ebc"; + dcr-reg = <012 2>; + #address-cells = <2>; + #size-cells = <1>; + + + /* The ranges property is supplied by the bootwrapper + * and is based on the firmware's configuration of the + * EBC bridge + */ + clock-frequency = <0>; /* Filled in by zImage */ + + /* NVRAM and RTC */ + nvrtc@4,200000 { + compatible = "ds1742"; + reg = <4 200000 0>; /* size fixed up by zImage */ + }; + + /* "BCSR" CPLD contains a PCI irq controller */ + bcsr@4,0 { + compatible = "ep405-bcsr"; + reg = <4 0 10>; + interrupt-controller; + /* Routing table */ + irq-routing = [ 00 /* SYSERR */ + 01 /* STTM */ + 01 /* RTC */ + 01 /* FENET */ + 02 /* NB PCIIRQ mux ? */ + 03 /* SB Winbond 8259 ? */ + 04 /* Serial Ring */ + 05 /* USB (ep405pc) */ + 06 /* XIRQ 0 */ + 06 /* XIRQ 1 */ + 06 /* XIRQ 2 */ + 06 /* XIRQ 3 */ + 06 /* XIRQ 4 */ + 06 /* XIRQ 5 */ + 06 /* XIRQ 6 */ + 07]; /* Reserved */ + }; + }; + + PCI0: pci@ec000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb405gp-pci", "ibm,plb-pci"; + primary; + reg = <eec00000 8 /* Config space access */ + eed80000 4 /* IACK */ + eed80000 4 /* Special cycle */ + ef480000 40>; /* Internal registers */ + + /* Outbound ranges, one memory and one IO, + * later cannot be changed. Chip supports a second + * IO range but we don't use it for now + */ + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e8000000 0 00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 80000000>; + + /* That's all I know about IRQs on that thing ... */ + interrupt-map-mask = <f800 0 0 0>; + interrupt-map = < + /* USB */ + 7000 0 0 0 &UIC0 1e 8 /* IRQ5 */ + >; + }; + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@ef600300"; + }; +}; diff --git a/arch/powerpc/boot/dts/katmai.dts b/arch/powerpc/boot/dts/katmai.dts new file mode 100644 index 0000000..9bdfc0f --- /dev/null +++ b/arch/powerpc/boot/dts/katmai.dts @@ -0,0 +1,400 @@ +/* + * Device Tree Source for AMCC Katmai eval board + * + * Copyright (c) 2006, 2007 IBM Corp. + * Benjamin Herrenschmidt <benh@kernel.crashing.org> + * + * Copyright (c) 2006, 2007 IBM Corp. + * Josh Boyer <jwboyer@linux.vnet.ibm.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "amcc,katmai"; + compatible = "amcc,katmai"; + dcr-parent = <&/cpus/cpu@0>; + + aliases { + ethernet0 = &EMAC0; + serial0 = &UART0; + serial1 = &UART1; + serial2 = &UART2; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,440SPe"; + reg = <0>; + clock-frequency = <0>; /* Filled in by zImage */ + timebase-frequency = <0>; /* Filled in by zImage */ + i-cache-line-size = <20>; + d-cache-line-size = <20>; + i-cache-size = <20000>; + d-cache-size = <20000>; + dcr-controller; + dcr-access-method = "native"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0 0>; /* Filled in by zImage */ + }; + + UIC0: interrupt-controller0 { + compatible = "ibm,uic-440spe","ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0c0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + UIC1: interrupt-controller1 { + compatible = "ibm,uic-440spe","ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0d0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <1e 4 1f 4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC2: interrupt-controller2 { + compatible = "ibm,uic-440spe","ibm,uic"; + interrupt-controller; + cell-index = <2>; + dcr-reg = <0e0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <a 4 b 4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC3: interrupt-controller3 { + compatible = "ibm,uic-440spe","ibm,uic"; + interrupt-controller; + cell-index = <3>; + dcr-reg = <0f0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <10 4 11 4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + SDR0: sdr { + compatible = "ibm,sdr-440spe"; + dcr-reg = <00e 002>; + }; + + CPR0: cpr { + compatible = "ibm,cpr-440spe"; + dcr-reg = <00c 002>; + }; + + plb { + compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; /* Filled in by zImage */ + + SDRAM0: sdram { + compatible = "ibm,sdram-440spe", "ibm,sdram-405gp"; + dcr-reg = <010 2>; + }; + + MAL0: mcmal { + compatible = "ibm,mcmal-440spe", "ibm,mcmal2"; + dcr-reg = <180 62>; + num-tx-chans = <2>; + num-rx-chans = <1>; + interrupt-parent = <&MAL0>; + interrupts = <0 1 2 3 4>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*TXEOB*/ 0 &UIC1 6 4 + /*RXEOB*/ 1 &UIC1 7 4 + /*SERR*/ 2 &UIC1 1 4 + /*TXDE*/ 3 &UIC1 2 4 + /*RXDE*/ 4 &UIC1 3 4>; + }; + + POB0: opb { + compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <00000000 4 e0000000 20000000>; + clock-frequency = <0>; /* Filled in by zImage */ + + EBC0: ebc { + compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc"; + dcr-reg = <012 2>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <0>; /* Filled in by zImage */ + interrupts = <5 1>; + interrupt-parent = <&UIC1>; + }; + + UART0: serial@10000200 { + device_type = "serial"; + compatible = "ns16550"; + reg = <10000200 8>; + virtual-reg = <a0000200>; + clock-frequency = <0>; /* Filled in by zImage */ + current-speed = <1c200>; + interrupt-parent = <&UIC0>; + interrupts = <0 4>; + }; + + UART1: serial@10000300 { + device_type = "serial"; + compatible = "ns16550"; + reg = <10000300 8>; + virtual-reg = <a0000300>; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC0>; + interrupts = <1 4>; + }; + + + UART2: serial@10000600 { + device_type = "serial"; + compatible = "ns16550"; + reg = <10000600 8>; + virtual-reg = <a0000600>; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC1>; + interrupts = <5 4>; + }; + + IIC0: i2c@10000400 { + device_type = "i2c"; + compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; + reg = <10000400 14>; + interrupt-parent = <&UIC0>; + interrupts = <2 4>; + }; + + IIC1: i2c@10000500 { + device_type = "i2c"; + compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic"; + reg = <10000500 14>; + interrupt-parent = <&UIC0>; + interrupts = <3 4>; + }; + + EMAC0: ethernet@10000800 { + linux,network-index = <0>; + device_type = "network"; + compatible = "ibm,emac-440spe", "ibm,emac4"; + interrupt-parent = <&UIC1>; + interrupts = <1c 4 1d 4>; + reg = <10000800 70>; + local-mac-address = [000000000000]; + mal-device = <&MAL0>; + mal-tx-channel = <0>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "gmii"; + phy-map = <00000000>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + }; + }; + + PCIX0: pci@c0ec00000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix"; + primary; + large-inbound-windows; + enable-msi-hole; + reg = <c 0ec00000 8 /* Config space access */ + 0 0 0 /* no IACK cycles */ + c 0ed00000 4 /* Special cycles */ + c 0ec80000 100 /* Internal registers */ + c 0ec80100 fc>; /* Internal messaging registers */ + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <02000000 0 80000000 0000000d 80000000 0 80000000 + 01000000 0 00000000 0000000c 08000000 0 00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 0 80000000>; + + /* This drives busses 0 to 0xf */ + bus-range = <0 f>; + + /* + * On Katmai, the following PCI-X interrupts signals + * have to be enabled via jumpers (only INTA is + * enabled per default): + * + * INTB: J3: 1-2 + * INTC: J2: 1-2 + * INTD: J1: 1-2 + */ + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + /* IDSEL 1 */ + 0800 0 0 1 &UIC1 14 8 + 0800 0 0 2 &UIC1 13 8 + 0800 0 0 3 &UIC1 12 8 + 0800 0 0 4 &UIC1 11 8 + >; + }; + + PCIE0: pciex@d00000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; + primary; + port = <0>; /* port number */ + reg = <d 00000000 20000000 /* Config space access */ + c 10000000 00001000>; /* Registers */ + dcr-reg = <100 020>; + sdr-base = <300>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <02000000 0 80000000 0000000e 00000000 0 80000000 + 01000000 0 00000000 0000000f 80000000 0 00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 0 80000000>; + + /* This drives busses 10 to 0x1f */ + bus-range = <10 1f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0000 0 0 7>; + interrupt-map = < + 0000 0 0 1 &UIC3 0 4 /* swizzled int A */ + 0000 0 0 2 &UIC3 1 4 /* swizzled int B */ + 0000 0 0 3 &UIC3 2 4 /* swizzled int C */ + 0000 0 0 4 &UIC3 3 4 /* swizzled int D */>; + }; + + PCIE1: pciex@d20000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; + primary; + port = <1>; /* port number */ + reg = <d 20000000 20000000 /* Config space access */ + c 10001000 00001000>; /* Registers */ + dcr-reg = <120 020>; + sdr-base = <340>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <02000000 0 80000000 0000000e 80000000 0 80000000 + 01000000 0 00000000 0000000f 80010000 0 00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 0 80000000>; + + /* This drives busses 10 to 0x1f */ + bus-range = <20 2f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0000 0 0 7>; + interrupt-map = < + 0000 0 0 1 &UIC3 4 4 /* swizzled int A */ + 0000 0 0 2 &UIC3 5 4 /* swizzled int B */ + 0000 0 0 3 &UIC3 6 4 /* swizzled int C */ + 0000 0 0 4 &UIC3 7 4 /* swizzled int D */>; + }; + + PCIE2: pciex@d40000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex"; + primary; + port = <2>; /* port number */ + reg = <d 40000000 20000000 /* Config space access */ + c 10002000 00001000>; /* Registers */ + dcr-reg = <140 020>; + sdr-base = <370>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <02000000 0 80000000 0000000f 00000000 0 80000000 + 01000000 0 00000000 0000000f 80020000 0 00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 0 80000000>; + + /* This drives busses 10 to 0x1f */ + bus-range = <30 3f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0000 0 0 7>; + interrupt-map = < + 0000 0 0 1 &UIC3 8 4 /* swizzled int A */ + 0000 0 0 2 &UIC3 9 4 /* swizzled int B */ + 0000 0 0 3 &UIC3 a 4 /* swizzled int C */ + 0000 0 0 4 &UIC3 b 4 /* swizzled int D */>; + }; + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@10000200"; + }; +}; diff --git a/arch/powerpc/boot/dts/kilauea.dts b/arch/powerpc/boot/dts/kilauea.dts index c824e8f..67c7ea1 100644 --- a/arch/powerpc/boot/dts/kilauea.dts +++ b/arch/powerpc/boot/dts/kilauea.dts @@ -13,14 +13,22 @@ #size-cells = <1>; model = "amcc,kilauea"; compatible = "amcc,kilauea"; - dcr-parent = <&/cpus/PowerPC,405EX@0>; + dcr-parent = <&/cpus/cpu@0>; + + aliases { + ethernet0 = &EMAC0; + ethernet1 = &EMAC1; + serial0 = &UART0; + serial1 = &UART1; + }; cpus { #address-cells = <1>; #size-cells = <0>; - PowerPC,405EX@0 { + cpu@0 { device_type = "cpu"; + model = "PowerPC,405EX"; reg = <0>; clock-frequency = <0>; /* Filled in by U-Boot */ timebase-frequency = <0>; /* Filled in by U-Boot */ @@ -194,6 +202,7 @@ device_type = "rgmii-interface"; compatible = "ibm,rgmii-405ex", "ibm,rgmii"; reg = <ef600b00 104>; + has-mdio; }; EMAC0: ethernet@ef600900 { @@ -220,6 +229,8 @@ phy-map = <00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <0>; + has-inverted-stacr-oc; + has-new-stacr-staopc; }; EMAC1: ethernet@ef600a00 { @@ -246,7 +257,91 @@ phy-map = <00000000>; rgmii-device = <&RGMII0>; rgmii-channel = <1>; + has-inverted-stacr-oc; + has-new-stacr-staopc; }; }; + + PCIE0: pciex@0a0000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; + primary; + port = <0>; /* port number */ + reg = <a0000000 20000000 /* Config space access */ + ef000000 00001000>; /* Registers */ + dcr-reg = <040 020>; + sdr-base = <400>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <02000000 0 80000000 90000000 0 08000000 + 01000000 0 00000000 e0000000 0 00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 80000000>; + + /* This drives busses 0x00 to 0x3f */ + bus-range = <00 3f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0000 0 0 7>; + interrupt-map = < + 0000 0 0 1 &UIC2 0 4 /* swizzled int A */ + 0000 0 0 2 &UIC2 1 4 /* swizzled int B */ + 0000 0 0 3 &UIC2 2 4 /* swizzled int C */ + 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>; + }; + + PCIE1: pciex@0c0000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; + primary; + port = <1>; /* port number */ + reg = <c0000000 20000000 /* Config space access */ + ef001000 00001000>; /* Registers */ + dcr-reg = <060 020>; + sdr-base = <440>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <02000000 0 80000000 98000000 0 08000000 + 01000000 0 00000000 e0010000 0 00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 80000000>; + + /* This drives busses 0x40 to 0x7f */ + bus-range = <40 7f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0000 0 0 7>; + interrupt-map = < + 0000 0 0 1 &UIC2 b 4 /* swizzled int A */ + 0000 0 0 2 &UIC2 c 4 /* swizzled int B */ + 0000 0 0 3 &UIC2 d 4 /* swizzled int C */ + 0000 0 0 4 &UIC2 e 4 /* swizzled int D */>; + }; }; }; diff --git a/arch/powerpc/boot/dts/makalu.dts b/arch/powerpc/boot/dts/makalu.dts new file mode 100644 index 0000000..bdd70e4 --- /dev/null +++ b/arch/powerpc/boot/dts/makalu.dts @@ -0,0 +1,347 @@ +/* + * Device Tree Source for AMCC Makalu (405EX) + * + * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + */ + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "amcc,makalu"; + compatible = "amcc,makalu"; + dcr-parent = <&/cpus/cpu@0>; + + aliases { + ethernet0 = &EMAC0; + ethernet1 = &EMAC1; + serial0 = &UART0; + serial1 = &UART1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,405EX"; + reg = <0>; + clock-frequency = <0>; /* Filled in by U-Boot */ + timebase-frequency = <0>; /* Filled in by U-Boot */ + i-cache-line-size = <20>; + d-cache-line-size = <20>; + i-cache-size = <4000>; /* 16 kB */ + d-cache-size = <4000>; /* 16 kB */ + dcr-controller; + dcr-access-method = "native"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0>; /* Filled in by U-Boot */ + }; + + UIC0: interrupt-controller { + compatible = "ibm,uic-405ex", "ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0c0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + UIC1: interrupt-controller1 { + compatible = "ibm,uic-405ex","ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0d0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <1e 4 1f 4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC2: interrupt-controller2 { + compatible = "ibm,uic-405ex","ibm,uic"; + interrupt-controller; + cell-index = <2>; + dcr-reg = <0e0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <1c 4 1d 4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + plb { + compatible = "ibm,plb-405ex", "ibm,plb4"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; /* Filled in by U-Boot */ + + SDRAM0: memory-controller { + compatible = "ibm,sdram-405ex"; + dcr-reg = <010 2>; + }; + + MAL0: mcmal { + compatible = "ibm,mcmal-405ex", "ibm,mcmal2"; + dcr-reg = <180 62>; + num-tx-chans = <2>; + num-rx-chans = <2>; + interrupt-parent = <&MAL0>; + interrupts = <0 1 2 3 4>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 + /*RXEOB*/ 1 &UIC0 b 4 + /*SERR*/ 2 &UIC1 0 4 + /*TXDE*/ 3 &UIC1 1 4 + /*RXDE*/ 4 &UIC1 2 4>; + interrupt-map-mask = <ffffffff>; + }; + + POB0: opb { + compatible = "ibm,opb-405ex", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <80000000 80000000 10000000 + ef600000 ef600000 a00000 + f0000000 f0000000 10000000>; + dcr-reg = <0a0 5>; + clock-frequency = <0>; /* Filled in by U-Boot */ + + EBC0: ebc { + compatible = "ibm,ebc-405ex", "ibm,ebc"; + dcr-reg = <012 2>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <0>; /* Filled in by U-Boot */ + /* ranges property is supplied by U-Boot */ + interrupts = <5 1>; + interrupt-parent = <&UIC1>; + + nor_flash@0,0 { + compatible = "amd,s29gl512n", "cfi-flash"; + bank-width = <2>; + reg = <0 000000 4000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "kernel"; + reg = <0 200000>; + }; + partition@200000 { + label = "root"; + reg = <200000 200000>; + }; + partition@400000 { + label = "user"; + reg = <400000 3b60000>; + }; + partition@3f60000 { + label = "env"; + reg = <3f60000 40000>; + }; + partition@3fa0000 { + label = "u-boot"; + reg = <3fa0000 60000>; + }; + }; + }; + + UART0: serial@ef600200 { + device_type = "serial"; + compatible = "ns16550"; + reg = <ef600200 8>; + virtual-reg = <ef600200>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; + interrupt-parent = <&UIC0>; + interrupts = <1a 4>; + }; + + UART1: serial@ef600300 { + device_type = "serial"; + compatible = "ns16550"; + reg = <ef600300 8>; + virtual-reg = <ef600300>; + clock-frequency = <0>; /* Filled in by U-Boot */ + current-speed = <0>; + interrupt-parent = <&UIC0>; + interrupts = <1 4>; + }; + + IIC0: i2c@ef600400 { + device_type = "i2c"; + compatible = "ibm,iic-405ex", "ibm,iic"; + reg = <ef600400 14>; + interrupt-parent = <&UIC0>; + interrupts = <2 4>; + }; + + IIC1: i2c@ef600500 { + device_type = "i2c"; + compatible = "ibm,iic-405ex", "ibm,iic"; + reg = <ef600500 14>; + interrupt-parent = <&UIC0>; + interrupts = <7 4>; + }; + + + RGMII0: emac-rgmii@ef600b00 { + device_type = "rgmii-interface"; + compatible = "ibm,rgmii-405ex", "ibm,rgmii"; + reg = <ef600b00 104>; + has-mdio; + }; + + EMAC0: ethernet@ef600900 { + linux,network-index = <0>; + device_type = "network"; + compatible = "ibm,emac-405ex", "ibm,emac4"; + interrupt-parent = <&EMAC0>; + interrupts = <0 1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0 &UIC0 18 4 + /*Wake*/ 1 &UIC1 1d 4>; + reg = <ef600900 70>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <0>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rgmii"; + phy-map = <0000003f>; /* Start at 6 */ + rgmii-device = <&RGMII0>; + rgmii-channel = <0>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + }; + + EMAC1: ethernet@ef600a00 { + linux,network-index = <1>; + device_type = "network"; + compatible = "ibm,emac-405ex", "ibm,emac4"; + interrupt-parent = <&EMAC1>; + interrupts = <0 1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0 &UIC0 19 4 + /*Wake*/ 1 &UIC1 1f 4>; + reg = <ef600a00 70>; + local-mac-address = [000000000000]; /* Filled in by U-Boot */ + mal-device = <&MAL0>; + mal-tx-channel = <1>; + mal-rx-channel = <1>; + cell-index = <1>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rgmii"; + phy-map = <00000000>; + rgmii-device = <&RGMII0>; + rgmii-channel = <1>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + }; + }; + + PCIE0: pciex@0a0000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; + primary; + port = <0>; /* port number */ + reg = <a0000000 20000000 /* Config space access */ + ef000000 00001000>; /* Registers */ + dcr-reg = <040 020>; + sdr-base = <400>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <02000000 0 80000000 90000000 0 08000000 + 01000000 0 00000000 e0000000 0 00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 80000000>; + + /* This drives busses 0x00 to 0x3f */ + bus-range = <00 3f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0000 0 0 7>; + interrupt-map = < + 0000 0 0 1 &UIC2 0 4 /* swizzled int A */ + 0000 0 0 2 &UIC2 1 4 /* swizzled int B */ + 0000 0 0 3 &UIC2 2 4 /* swizzled int C */ + 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>; + }; + + PCIE1: pciex@0c0000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex"; + primary; + port = <1>; /* port number */ + reg = <c0000000 20000000 /* Config space access */ + ef001000 00001000>; /* Registers */ + dcr-reg = <060 020>; + sdr-base = <440>; + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <02000000 0 80000000 98000000 0 08000000 + 01000000 0 00000000 e0010000 0 00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 80000000>; + + /* This drives busses 0x40 to 0x7f */ + bus-range = <40 7f>; + + /* Legacy interrupts (note the weird polarity, the bridge seems + * to invert PCIe legacy interrupts). + * We are de-swizzling here because the numbers are actually for + * port of the root complex virtual P2P bridge. But I want + * to avoid putting a node for it in the tree, so the numbers + * below are basically de-swizzled numbers. + * The real slot is on idsel 0, so the swizzling is 1:1 + */ + interrupt-map-mask = <0000 0 0 7>; + interrupt-map = < + 0000 0 0 1 &UIC2 b 4 /* swizzled int A */ + 0000 0 0 2 &UIC2 c 4 /* swizzled int B */ + 0000 0 0 3 &UIC2 d 4 /* swizzled int C */ + 0000 0 0 4 &UIC2 e 4 /* swizzled int D */>; + }; + }; +}; diff --git a/arch/powerpc/boot/dts/rainier.dts b/arch/powerpc/boot/dts/rainier.dts new file mode 100644 index 0000000..d3c2ac3 --- /dev/null +++ b/arch/powerpc/boot/dts/rainier.dts @@ -0,0 +1,353 @@ +/* + * Device Tree Source for AMCC Rainier + * + * Based on Sequoia code + * Copyright (c) 2007 MontaVista Software, Inc. + * + * FIXME: Draft only! + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "amcc,rainier"; + compatible = "amcc,rainier"; + dcr-parent = <&/cpus/cpu@0>; + + aliases { + ethernet0 = &EMAC0; + ethernet1 = &EMAC1; + serial0 = &UART0; + serial1 = &UART1; + serial2 = &UART2; + serial3 = &UART3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,440GRx"; + reg = <0>; + clock-frequency = <0>; /* Filled in by zImage */ + timebase-frequency = <0>; /* Filled in by zImage */ + i-cache-line-size = <20>; + d-cache-line-size = <20>; + i-cache-size = <8000>; + d-cache-size = <8000>; + dcr-controller; + dcr-access-method = "native"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0 0>; /* Filled in by zImage */ + }; + + UIC0: interrupt-controller0 { + compatible = "ibm,uic-440grx","ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0c0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + UIC1: interrupt-controller1 { + compatible = "ibm,uic-440grx","ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0d0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <1e 4 1f 4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + UIC2: interrupt-controller2 { + compatible = "ibm,uic-440grx","ibm,uic"; + interrupt-controller; + cell-index = <2>; + dcr-reg = <0e0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <1c 4 1d 4>; /* cascade */ + interrupt-parent = <&UIC0>; + }; + + SDR0: sdr { + compatible = "ibm,sdr-440grx", "ibm,sdr-440ep"; + dcr-reg = <00e 002>; + }; + + CPR0: cpr { + compatible = "ibm,cpr-440grx", "ibm,cpr-440ep"; + dcr-reg = <00c 002>; + }; + + plb { + compatible = "ibm,plb-440grx", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <0>; /* Filled in by zImage */ + + SDRAM0: sdram { + compatible = "ibm,sdram-440grx", "ibm,sdram-44x-ddr2denali"; + dcr-reg = <010 2>; + }; + + DMA0: dma { + compatible = "ibm,dma-440grx", "ibm,dma-4xx"; + dcr-reg = <100 027>; + }; + + MAL0: mcmal { + compatible = "ibm,mcmal-440grx", "ibm,mcmal2"; + dcr-reg = <180 62>; + num-tx-chans = <2>; + num-rx-chans = <2>; + interrupt-parent = <&MAL0>; + interrupts = <0 1 2 3 4>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 + /*RXEOB*/ 1 &UIC0 b 4 + /*SERR*/ 2 &UIC1 0 4 + /*TXDE*/ 3 &UIC1 1 4 + /*RXDE*/ 4 &UIC1 2 4>; + interrupt-map-mask = <ffffffff>; + }; + + POB0: opb { + compatible = "ibm,opb-440grx", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <00000000 1 00000000 80000000 + 80000000 1 80000000 80000000>; + interrupt-parent = <&UIC1>; + interrupts = <7 4>; + clock-frequency = <0>; /* Filled in by zImage */ + + EBC0: ebc { + compatible = "ibm,ebc-440grx", "ibm,ebc"; + dcr-reg = <012 2>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <0>; /* Filled in by zImage */ + interrupts = <5 1>; + interrupt-parent = <&UIC1>; + + nor_flash@0,0 { + compatible = "amd,s29gl256n", "cfi-flash"; + bank-width = <2>; + reg = <0 000000 4000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "Kernel"; + reg = <0 180000>; + }; + partition@180000 { + label = "ramdisk"; + reg = <180000 200000>; + }; + partition@380000 { + label = "file system"; + reg = <380000 3aa0000>; + }; + partition@3e20000 { + label = "kozio"; + reg = <3e20000 140000>; + }; + partition@3f60000 { + label = "env"; + reg = <3f60000 40000>; + }; + partition@3fa0000 { + label = "u-boot"; + reg = <3fa0000 60000>; + }; + }; + + }; + + UART0: serial@ef600300 { + device_type = "serial"; + compatible = "ns16550"; + reg = <ef600300 8>; + virtual-reg = <ef600300>; + clock-frequency = <0>; /* Filled in by zImage */ + current-speed = <1c200>; + interrupt-parent = <&UIC0>; + interrupts = <0 4>; + }; + + UART1: serial@ef600400 { + device_type = "serial"; + compatible = "ns16550"; + reg = <ef600400 8>; + virtual-reg = <ef600400>; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC0>; + interrupts = <1 4>; + }; + + UART2: serial@ef600500 { + device_type = "serial"; + compatible = "ns16550"; + reg = <ef600500 8>; + virtual-reg = <ef600500>; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC1>; + interrupts = <3 4>; + }; + + UART3: serial@ef600600 { + device_type = "serial"; + compatible = "ns16550"; + reg = <ef600600 8>; + virtual-reg = <ef600600>; + clock-frequency = <0>; + current-speed = <0>; + interrupt-parent = <&UIC1>; + interrupts = <4 4>; + }; + + IIC0: i2c@ef600700 { + device_type = "i2c"; + compatible = "ibm,iic-440grx", "ibm,iic"; + reg = <ef600700 14>; + interrupt-parent = <&UIC0>; + interrupts = <2 4>; + }; + + IIC1: i2c@ef600800 { + device_type = "i2c"; + compatible = "ibm,iic-440grx", "ibm,iic"; + reg = <ef600800 14>; + interrupt-parent = <&UIC0>; + interrupts = <7 4>; + }; + + ZMII0: emac-zmii@ef600d00 { + device_type = "zmii-interface"; + compatible = "ibm,zmii-440grx", "ibm,zmii"; + reg = <ef600d00 c>; + }; + + RGMII0: emac-rgmii@ef601000 { + device_type = "rgmii-interface"; + compatible = "ibm,rgmii-440grx", "ibm,rgmii"; + reg = <ef601000 8>; + has-mdio; + }; + + EMAC0: ethernet@ef600e00 { + linux,network-index = <0>; + device_type = "network"; + compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4"; + interrupt-parent = <&EMAC0>; + interrupts = <0 1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0 &UIC0 18 4 + /*Wake*/ 1 &UIC1 1d 4>; + reg = <ef600e00 70>; + local-mac-address = [000000000000]; + mal-device = <&MAL0>; + mal-tx-channel = <0>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rgmii"; + phy-map = <00000000>; + zmii-device = <&ZMII0>; + zmii-channel = <0>; + rgmii-device = <&RGMII0>; + rgmii-channel = <0>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + }; + + EMAC1: ethernet@ef600f00 { + linux,network-index = <1>; + device_type = "network"; + compatible = "ibm,emac-440grx", "ibm,emac-440epx", "ibm,emac4"; + interrupt-parent = <&EMAC1>; + interrupts = <0 1>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*Status*/ 0 &UIC0 19 4 + /*Wake*/ 1 &UIC1 1f 4>; + reg = <ef600f00 70>; + local-mac-address = [000000000000]; + mal-device = <&MAL0>; + mal-tx-channel = <1>; + mal-rx-channel = <1>; + cell-index = <1>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rgmii"; + phy-map = <00000000>; + zmii-device = <&ZMII0>; + zmii-channel = <1>; + rgmii-device = <&RGMII0>; + rgmii-channel = <1>; + has-inverted-stacr-oc; + has-new-stacr-staopc; + }; + }; + + PCI0: pci@1ec000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb440grx-pci", "ibm,plb-pci"; + primary; + reg = <1 eec00000 8 /* Config space access */ + 1 eed00000 4 /* IACK */ + 1 eed00000 4 /* Special cycle */ + 1 ef400000 40>; /* Internal registers */ + + /* Outbound ranges, one memory and one IO, + * later cannot be changed. Chip supports a second + * IO range but we don't use it for now + */ + ranges = <02000000 0 80000000 1 80000000 0 10000000 + 01000000 0 00000000 1 e8000000 0 00100000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 0 80000000>; + + /* All PCI interrupts are routed to IRQ 67 */ + interrupt-map-mask = <0000 0 0 0>; + interrupt-map = < 0000 0 0 0 &UIC2 3 8 >; + }; + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@ef600300"; + bootargs = "console=ttyS0,115200"; + }; +}; diff --git a/arch/powerpc/boot/dts/sequoia.dts b/arch/powerpc/boot/dts/sequoia.dts index 10784ff..d9046c1 100644 --- a/arch/powerpc/boot/dts/sequoia.dts +++ b/arch/powerpc/boot/dts/sequoia.dts @@ -17,14 +17,24 @@ #size-cells = <1>; model = "amcc,sequoia"; compatible = "amcc,sequoia"; - dcr-parent = <&/cpus/PowerPC,440EPx@0>; + dcr-parent = <&/cpus/cpu@0>; + + aliases { + ethernet0 = &EMAC0; + ethernet1 = &EMAC1; + serial0 = &UART0; + serial1 = &UART1; + serial2 = &UART2; + serial3 = &UART3; + }; cpus { #address-cells = <1>; #size-cells = <0>; - PowerPC,440EPx@0 { + cpu@0 { device_type = "cpu"; + model = "PowerPC,440EPx"; reg = <0>; clock-frequency = <0>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ @@ -94,7 +104,6 @@ clock-frequency = <0>; /* Filled in by zImage */ SDRAM0: sdram { - device_type = "memory-controller"; compatible = "ibm,sdram-440epx", "ibm,sdram-44x-ddr2denali"; dcr-reg = <010 2>; }; @@ -122,6 +131,13 @@ interrupt-map-mask = <ffffffff>; }; + USB1: usb@e0000400 { + compatible = "ohci-be"; + reg = <0 e0000400 60>; + interrupt-parent = <&UIC0>; + interrupts = <15 8>; + }; + POB0: opb { compatible = "ibm,opb-440epx", "ibm,opb"; #address-cells = <1>; @@ -308,6 +324,33 @@ has-new-stacr-staopc; }; }; + + PCI0: pci@1ec000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb440epx-pci", "ibm,plb-pci"; + primary; + reg = <1 eec00000 8 /* Config space access */ + 1 eed00000 4 /* IACK */ + 1 eed00000 4 /* Special cycle */ + 1 ef400000 40>; /* Internal registers */ + + /* Outbound ranges, one memory and one IO, + * later cannot be changed. Chip supports a second + * IO range but we don't use it for now + */ + ranges = <02000000 0 80000000 1 80000000 0 10000000 + 01000000 0 00000000 1 e8000000 0 00100000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 0 80000000>; + + /* All PCI interrupts are routed to IRQ 67 */ + interrupt-map-mask = <0000 0 0 0>; + interrupt-map = < 0000 0 0 0 &UIC2 3 8 >; + }; }; chosen { diff --git a/arch/powerpc/boot/dts/taishan.dts b/arch/powerpc/boot/dts/taishan.dts new file mode 100644 index 0000000..0706a4a --- /dev/null +++ b/arch/powerpc/boot/dts/taishan.dts @@ -0,0 +1,383 @@ +/* + * Device Tree Source for IBM/AMCC Taishan + * + * Copyright 2007 IBM Corp. + * Hugh Blemings <hugh@au.ibm.com> based off code by + * Josh Boyer <jwboyer@linux.vnet.ibm.com>, David Gibson <dwg@au1.ibm.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + */ + +/ { + #address-cells = <2>; + #size-cells = <1>; + model = "amcc,taishan"; + compatible = "amcc,taishan"; + dcr-parent = <&/cpus/cpu@0>; + + aliases { + ethernet0 = &EMAC2; + ethernet1 = &EMAC3; + serial0 = &UART0; + serial1 = &UART1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + model = "PowerPC,440GX"; + reg = <0>; + clock-frequency = <2FAF0800>; // 800MHz + timebase-frequency = <0>; // Filled in by zImage + i-cache-line-size = <32>; + d-cache-line-size = <32>; + i-cache-size = <8000>; /* 32 kB */ + d-cache-size = <8000>; /* 32 kB */ + dcr-controller; + dcr-access-method = "native"; + }; + }; + + memory { + device_type = "memory"; + reg = <0 0 0>; // Filled in by zImage + }; + + + UICB0: interrupt-controller-base { + compatible = "ibm,uic-440gx", "ibm,uic"; + interrupt-controller; + cell-index = <3>; + dcr-reg = <200 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + }; + + + UIC0: interrupt-controller0 { + compatible = "ibm,uic-440gx", "ibm,uic"; + interrupt-controller; + cell-index = <0>; + dcr-reg = <0c0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <01 4 00 4>; /* cascade - first non-critical */ + interrupt-parent = <&UICB0>; + + }; + + UIC1: interrupt-controller1 { + compatible = "ibm,uic-440gx", "ibm,uic"; + interrupt-controller; + cell-index = <1>; + dcr-reg = <0d0 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <03 4 02 4>; /* cascade */ + interrupt-parent = <&UICB0>; + }; + + UIC2: interrupt-controller2 { + compatible = "ibm,uic-440gx", "ibm,uic"; + interrupt-controller; + cell-index = <2>; /* was 1 */ + dcr-reg = <210 009>; + #address-cells = <0>; + #size-cells = <0>; + #interrupt-cells = <2>; + interrupts = <05 4 04 4>; /* cascade */ + interrupt-parent = <&UICB0>; + }; + + + CPC0: cpc { + compatible = "ibm,cpc-440gp"; + dcr-reg = <0b0 003 0e0 010>; + // FIXME: anything else? + }; + + plb { + compatible = "ibm,plb-440gx", "ibm,plb4"; + #address-cells = <2>; + #size-cells = <1>; + ranges; + clock-frequency = <9896800>; // 160MHz + + SDRAM0: memory-controller { + compatible = "ibm,sdram-440gp"; + dcr-reg = <010 2>; + // FIXME: anything else? + }; + + SRAM0: sram { + compatible = "ibm,sram-440gp"; + dcr-reg = <020 8 00a 1>; + }; + + DMA0: dma { + // FIXME: ??? + compatible = "ibm,dma-440gp"; + dcr-reg = <100 027>; + }; + + MAL0: mcmal { + compatible = "ibm,mcmal-440gx", "ibm,mcmal2"; + dcr-reg = <180 62>; + num-tx-chans = <4>; + num-rx-chans = <4>; + interrupt-parent = <&MAL0>; + interrupts = <0 1 2 3 4>; + #interrupt-cells = <1>; + #address-cells = <0>; + #size-cells = <0>; + interrupt-map = </*TXEOB*/ 0 &UIC0 a 4 + /*RXEOB*/ 1 &UIC0 b 4 + /*SERR*/ 2 &UIC1 0 4 + /*TXDE*/ 3 &UIC1 1 4 + /*RXDE*/ 4 &UIC1 2 4>; + interrupt-map-mask = <ffffffff>; + }; + + POB0: opb { + compatible = "ibm,opb-440gx", "ibm,opb"; + #address-cells = <1>; + #size-cells = <1>; + /* Wish there was a nicer way of specifying a full 32-bit + range */ + ranges = <00000000 1 00000000 80000000 + 80000000 1 80000000 80000000>; + dcr-reg = <090 00b>; + interrupt-parent = <&UIC1>; + interrupts = <7 4>; + clock-frequency = <4C4B400>; // 80MHz + + + EBC0: ebc { + compatible = "ibm,ebc-440gx", "ibm,ebc"; + dcr-reg = <012 2>; + #address-cells = <2>; + #size-cells = <1>; + clock-frequency = <4C4B400>; // 80MHz + + /* ranges property is supplied by zImage + * based on firmware's configuration of the + * EBC bridge */ + + interrupts = <5 4>; + interrupt-parent = <&UIC1>; + + /* TODO: Add other EBC devices */ + }; + + + + UART0: serial@40000200 { + device_type = "serial"; + compatible = "ns16550"; + reg = <40000200 8>; + virtual-reg = <e0000200>; + clock-frequency = <A8C000>; + current-speed = <1C200>; /* 115200 */ + interrupt-parent = <&UIC0>; + interrupts = <0 4>; + }; + + UART1: serial@40000300 { + device_type = "serial"; + compatible = "ns16550"; + reg = <40000300 8>; + virtual-reg = <e0000300>; + clock-frequency = <A8C000>; + current-speed = <1C200>; /* 115200 */ + interrupt-parent = <&UIC0>; + interrupts = <1 4>; + }; + + IIC0: i2c@40000400 { + /* FIXME */ + device_type = "i2c"; + compatible = "ibm,iic-440gp", "ibm,iic"; + reg = <40000400 14>; + interrupt-parent = <&UIC0>; + interrupts = <2 4>; + }; + IIC1: i2c@40000500 { + /* FIXME */ + device_type = "i2c"; + compatible = "ibm,iic-440gp", "ibm,iic"; + reg = <40000500 14>; + interrupt-parent = <&UIC0>; + interrupts = <3 4>; + }; + + GPIO0: gpio@40000700 { + /* FIXME */ + compatible = "ibm,gpio-440gp"; + reg = <40000700 20>; + }; + + ZMII0: emac-zmii@40000780 { + device_type = "zgmii-interface"; + compatible = "ibm,zmii-440gx", "ibm,zmii"; + reg = <40000780 c>; + }; + + RGMII0: emac-rgmii@40000790 { + device_type = "rgmii-interface"; + compatible = "ibm,rgmii"; + reg = <40000790 8>; + }; + + + EMAC0: ethernet@40000800 { + unused = <1>; + linux,network-index = <2>; + device_type = "network"; + compatible = "ibm,emac-440gx", "ibm,emac4"; + interrupt-parent = <&UIC1>; + interrupts = <1c 4 1d 4>; + reg = <40000800 70>; + local-mac-address = [000000000000]; // Filled in by zImage + mal-device = <&MAL0>; + mal-tx-channel = <0>; + mal-rx-channel = <0>; + cell-index = <0>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rmii"; + phy-map = <00000001>; + zmii-device = <&ZMII0>; + zmii-channel = <0>; + }; + EMAC1: ethernet@40000900 { + unused = <1>; + linux,network-index = <3>; + device_type = "network"; + compatible = "ibm,emac-440gx", "ibm,emac4"; + interrupt-parent = <&UIC1>; + interrupts = <1e 4 1f 4>; + reg = <40000900 70>; + local-mac-address = [000000000000]; // Filled in by zImage + mal-device = <&MAL0>; + mal-tx-channel = <1>; + mal-rx-channel = <1>; + cell-index = <1>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rmii"; + phy-map = <00000001>; + zmii-device = <&ZMII0>; + zmii-channel = <1>; + }; + + EMAC2: ethernet@40000c00 { + linux,network-index = <0>; + device_type = "network"; + compatible = "ibm,emac-440gx", "ibm,emac4"; + interrupt-parent = <&UIC2>; + interrupts = <0 4 1 4>; + reg = <40000c00 70>; + local-mac-address = [000000000000]; // Filled in by zImage + mal-device = <&MAL0>; + mal-tx-channel = <2>; + mal-rx-channel = <2>; + cell-index = <2>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rgmii"; + phy-map = <00000001>; + rgmii-device = <&RGMII0>; + rgmii-channel = <0>; + zmii-device = <&ZMII0>; + zmii-channel = <2>; + }; + + EMAC3: ethernet@40000e00 { + linux,network-index = <1>; + device_type = "network"; + compatible = "ibm,emac-440gx", "ibm,emac4"; + interrupt-parent = <&UIC2>; + interrupts = <2 4 3 4>; + reg = <40000e00 70>; + local-mac-address = [000000000000]; // Filled in by zImage + mal-device = <&MAL0>; + mal-tx-channel = <3>; + mal-rx-channel = <3>; + cell-index = <3>; + max-frame-size = <5dc>; + rx-fifo-size = <1000>; + tx-fifo-size = <800>; + phy-mode = "rgmii"; + phy-map = <00000003>; + rgmii-device = <&RGMII0>; + rgmii-channel = <1>; + zmii-device = <&ZMII0>; + zmii-channel = <3>; + }; + + + GPT0: gpt@40000a00 { + /* FIXME */ + reg = <40000a00 d4>; + interrupt-parent = <&UIC0>; + interrupts = <12 4 13 4 14 4 15 4 16 4>; + }; + + }; + + PCIX0: pci@20ec00000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb440gp-pcix", "ibm,plb-pcix"; + primary; + large-inbound-windows; + enable-msi-hole; + reg = <2 0ec00000 8 /* Config space access */ + 0 0 0 /* no IACK cycles */ + 2 0ed00000 4 /* Special cycles */ + 2 0ec80000 100 /* Internal registers */ + 2 0ec80100 fc>; /* Internal messaging registers */ + + /* Outbound ranges, one memory and one IO, + * later cannot be changed + */ + ranges = <02000000 0 80000000 00000003 80000000 0 80000000 + 01000000 0 00000000 00000002 08000000 0 00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 0 80000000>; + + interrupt-map-mask = <f800 0 0 7>; + interrupt-map = < + /* IDSEL 1 */ + 0800 0 0 1 &UIC0 17 8 + 0800 0 0 2 &UIC0 18 8 + 0800 0 0 3 &UIC0 19 8 + 0800 0 0 4 &UIC0 1a 8 + + /* IDSEL 2 */ + 1000 0 0 1 &UIC0 18 8 + 1000 0 0 2 &UIC0 19 8 + 1000 0 0 3 &UIC0 1a 8 + 1000 0 0 4 &UIC0 17 8 + >; + }; + }; + + chosen { + linux,stdout-path = "/plb/opb/serial@40000300"; + }; +}; diff --git a/arch/powerpc/boot/dts/walnut.dts b/arch/powerpc/boot/dts/walnut.dts index 754fa39..0e3825e 100644 --- a/arch/powerpc/boot/dts/walnut.dts +++ b/arch/powerpc/boot/dts/walnut.dts @@ -14,14 +14,21 @@ #size-cells = <1>; model = "ibm,walnut"; compatible = "ibm,walnut"; - dcr-parent = <&/cpus/PowerPC,405GP@0>; + dcr-parent = <&/cpus/cpu@0>; + + aliases { + ethernet0 = &EMAC; + serial0 = &UART0; + serial1 = &UART1; + }; cpus { #address-cells = <1>; #size-cells = <0>; - PowerPC,405GP@0 { + cpu@0 { device_type = "cpu"; + model = "PowerPC,405GP"; reg = <0>; clock-frequency = <bebc200>; /* Filled in by zImage */ timebase-frequency = <0>; /* Filled in by zImage */ @@ -190,6 +197,45 @@ virtual-reg = <f0300005>; }; }; + + PCI0: pci@ec000000 { + device_type = "pci"; + #interrupt-cells = <1>; + #size-cells = <2>; + #address-cells = <3>; + compatible = "ibm,plb405gp-pci", "ibm,plb-pci"; + primary; + reg = <eec00000 8 /* Config space access */ + eed80000 4 /* IACK */ + eed80000 4 /* Special cycle */ + ef480000 40>; /* Internal registers */ + + /* Outbound ranges, one memory and one IO, + * later cannot be changed. Chip supports a second + * IO range but we don't use it for now + */ + ranges = <02000000 0 80000000 80000000 0 20000000 + 01000000 0 00000000 e8000000 0 00010000>; + + /* Inbound 2GB range starting at 0 */ + dma-ranges = <42000000 0 0 0 0 80000000>; + + /* Walnut has all 4 IRQ pins tied together per slot */ + interrupt-map-mask = <f800 0 0 0>; + interrupt-map = < + /* IDSEL 1 */ + 0800 0 0 0 &UIC0 1c 8 + + /* IDSEL 2 */ + 1000 0 0 0 &UIC0 1d 8 + + /* IDSEL 3 */ + 1800 0 0 0 &UIC0 1e 8 + + /* IDSEL 4 */ + 2000 0 0 0 &UIC0 1f 8 + >; + }; }; chosen { diff --git a/arch/powerpc/boot/ebony.c b/arch/powerpc/boot/ebony.c index ee31be5..f61364c 100644 --- a/arch/powerpc/boot/ebony.c +++ b/arch/powerpc/boot/ebony.c @@ -31,66 +31,6 @@ static u8 *ebony_mac0, *ebony_mac1; -/* Calculate 440GP clocks */ -void ibm440gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk) -{ - u32 sys0 = mfdcr(DCRN_CPC0_SYS0); - u32 cr0 = mfdcr(DCRN_CPC0_CR0); - u32 cpu, plb, opb, ebc, tb, uart0, uart1, m; - u32 opdv = CPC0_SYS0_OPDV(sys0); - u32 epdv = CPC0_SYS0_EPDV(sys0); - - if (sys0 & CPC0_SYS0_BYPASS) { - /* Bypass system PLL */ - cpu = plb = sysclk; - } else { - if (sys0 & CPC0_SYS0_EXTSL) - /* PerClk */ - m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv; - else - /* CPU clock */ - m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0); - cpu = sysclk * m / CPC0_SYS0_FWDVA(sys0); - plb = sysclk * m / CPC0_SYS0_FWDVB(sys0); - } - - opb = plb / opdv; - ebc = opb / epdv; - - /* FIXME: Check if this is for all 440GP, or just Ebony */ - if ((mfpvr() & 0xf0000fff) == 0x40000440) - /* Rev. B 440GP, use external system clock */ - tb = sysclk; - else - /* Rev. C 440GP, errata force us to use internal clock */ - tb = cpu; - - if (cr0 & CPC0_CR0_U0EC) - /* External UART clock */ - uart0 = ser_clk; - else - /* Internal UART clock */ - uart0 = plb / CPC0_CR0_UDIV(cr0); - - if (cr0 & CPC0_CR0_U1EC) - /* External UART clock */ - uart1 = ser_clk; - else - /* Internal UART clock */ - uart1 = plb / CPC0_CR0_UDIV(cr0); - - printf("PPC440GP: SysClk = %dMHz (%x)\n\r", - (sysclk + 500000) / 1000000, sysclk); - - dt_fixup_cpu_clocks(cpu, tb, 0); - - dt_fixup_clock("/plb", plb); - dt_fixup_clock("/plb/opb", opb); - dt_fixup_clock("/plb/opb/ebc", ebc); - dt_fixup_clock("/plb/opb/serial@40000200", uart0); - dt_fixup_clock("/plb/opb/serial@40000300", uart1); -} - #define EBONY_FPGA_PATH "/plb/opb/ebc/fpga" #define EBONY_FPGA_FLASH_SEL 0x01 #define EBONY_SMALL_FLASH_PATH "/plb/opb/ebc/small-flash" @@ -134,7 +74,7 @@ static void ebony_fixups(void) unsigned long sysclk = 33000000; ibm440gp_fixup_clocks(sysclk, 6 * 1843200); - ibm4xx_fixup_memsize(); + ibm4xx_sdram_fixup_memsize(); dt_fixup_mac_addresses(ebony_mac0, ebony_mac1); ibm4xx_fixup_ebc_ranges("/plb/opb/ebc"); ebony_flashsel_fixup(); diff --git a/arch/powerpc/boot/ep405.c b/arch/powerpc/boot/ep405.c new file mode 100644 index 0000000..2d08a86 --- /dev/null +++ b/arch/powerpc/boot/ep405.c @@ -0,0 +1,74 @@ +/* + * Embedded Planet EP405 with PlanetCore firmware + * + * (c) Benjamin Herrenschmidt <benh@kernel.crashing.org>, IBM Corp,\ + * + * Based on ep88xc.c by + * + * Scott Wood <scottwood@freescale.com> + * + * Copyright (c) 2007 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include "ops.h" +#include "stdio.h" +#include "planetcore.h" +#include "dcr.h" +#include "4xx.h" +#include "io.h" + +static char *table; +static u64 mem_size; + +static void platform_fixups(void) +{ + u64 val; + void *nvrtc; + + dt_fixup_memory(0, mem_size); + planetcore_set_mac_addrs(table); + + if (!planetcore_get_decimal(table, PLANETCORE_KEY_CRYSTAL_HZ, &val)) { + printf("No PlanetCore crystal frequency key.\r\n"); + return; + } + ibm405gp_fixup_clocks(val, 0xa8c000); + ibm4xx_quiesce_eth((u32 *)0xef600800, NULL); + ibm4xx_fixup_ebc_ranges("/plb/ebc"); + + if (!planetcore_get_decimal(table, PLANETCORE_KEY_KB_NVRAM, &val)) { + printf("No PlanetCore NVRAM size key.\r\n"); + return; + } + nvrtc = finddevice("/plb/ebc/nvrtc@4,200000"); + if (nvrtc != NULL) { + u32 reg[3] = { 4, 0x200000, 0}; + getprop(nvrtc, "reg", reg, 3); + reg[2] = (val << 10) & 0xffffffff; + setprop(nvrtc, "reg", reg, 3); + } +} + +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7) +{ + table = (char *)r3; + planetcore_prepare_table(table); + + if (!planetcore_get_decimal(table, PLANETCORE_KEY_MB_RAM, &mem_size)) + return; + + mem_size *= 1024 * 1024; + simple_alloc_init(_end, mem_size - (unsigned long)_end, 32, 64); + + fdt_init(_dtb_start); + + planetcore_set_stdout_path(table); + + serial_console_init(); + platform_ops.fixups = platform_fixups; +} diff --git a/arch/powerpc/boot/reg.h b/arch/powerpc/boot/reg.h index d3cd9ee..9c2c997 100644 --- a/arch/powerpc/boot/reg.h +++ b/arch/powerpc/boot/reg.h @@ -16,6 +16,14 @@ static inline u32 mfpvr(void) return pvr; } +#define __stringify_1(x) #x +#define __stringify(x) __stringify_1(x) + +#define mfspr(rn) ({unsigned long rval; \ + asm volatile("mfspr %0," __stringify(rn) \ + : "=r" (rval)); rval; }) +#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v)) + register void *__stack_pointer asm("r1"); #define get_sp() (__stack_pointer) diff --git a/arch/powerpc/boot/treeboot-walnut.c b/arch/powerpc/boot/treeboot-walnut.c index 70ffce3..472e366 100644 --- a/arch/powerpc/boot/treeboot-walnut.c +++ b/arch/powerpc/boot/treeboot-walnut.c @@ -20,55 +20,6 @@ BSS_STACK(4096); -void ibm405gp_fixup_clocks(unsigned int sysclk, unsigned int ser_clk) -{ - u32 pllmr = mfdcr(DCRN_CPC0_PLLMR); - u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0); - u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1); - u32 cpu, plb, opb, ebc, tb, uart0, uart1, m; - u32 fwdv, fbdv, cbdv, opdv, epdv, udiv; - - fwdv = (8 - ((pllmr & 0xe0000000) >> 29)); - fbdv = (pllmr & 0x1e000000) >> 25; - cbdv = ((pllmr & 0x00060000) >> 17) + 1; - opdv = ((pllmr & 0x00018000) >> 15) + 1; - epdv = ((pllmr & 0x00001800) >> 13) + 2; - udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1; - - m = fwdv * fbdv * cbdv; - - cpu = sysclk * m / fwdv; - plb = cpu / cbdv; - opb = plb / opdv; - ebc = plb / epdv; - - if (cpc0_cr0 & 0x80) { - /* uart0 uses the external clock */ - uart0 = ser_clk; - } else { - uart0 = cpu / udiv; - } - - if (cpc0_cr0 & 0x40) { - /* uart1 uses the external clock */ - uart1 = ser_clk; - } else { - uart1 = cpu / udiv; - } - - /* setup the timebase clock to tick at the cpu frequency */ - cpc0_cr1 = cpc0_cr1 & ~0x00800000; - mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1); - tb = cpu; - - dt_fixup_cpu_clocks(cpu, tb, 0); - dt_fixup_clock("/plb", plb); - dt_fixup_clock("/plb/opb", opb); - dt_fixup_clock("/plb/ebc", ebc); - dt_fixup_clock("/plb/opb/serial@ef600300", uart0); - dt_fixup_clock("/plb/opb/serial@ef600400", uart1); -} - static void walnut_flashsel_fixup(void) { void *devp, *sram; @@ -112,7 +63,7 @@ static void walnut_flashsel_fixup(void) #define WALNUT_OPENBIOS_MAC_OFF 0xfffffe0b static void walnut_fixups(void) { - ibm4xx_fixup_memsize(); + ibm4xx_sdram_fixup_memsize(); ibm405gp_fixup_clocks(33330000, 0xa8c000); ibm4xx_quiesce_eth((u32 *)0xef600800, NULL); ibm4xx_fixup_ebc_ranges("/plb/ebc"); diff --git a/arch/powerpc/boot/wrapper b/arch/powerpc/boot/wrapper index f961cde..154df05 100755 --- a/arch/powerpc/boot/wrapper +++ b/arch/powerpc/boot/wrapper @@ -168,7 +168,7 @@ ps3) ksection=.kernel:vmlinux.bin isection=.kernel:initrd ;; -ep88xc) +ep88xc|ep405) platformo="$object/fixed-head.o $object/$platform.o" binary=y ;; |