diff options
Diffstat (limited to 'drivers/gpu/drm')
24 files changed, 389 insertions, 188 deletions
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index a245d17..af60d9b 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -449,12 +449,11 @@ static void edid_fixup_preferred(struct drm_connector *connector, struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, int hsize, int vsize, int fresh) { + struct drm_display_mode *mode = NULL; int i; - struct drm_display_mode *ptr, *mode; - mode = NULL; for (i = 0; i < drm_num_dmt_modes; i++) { - ptr = &drm_dmt_modes[i]; + const struct drm_display_mode *ptr = &drm_dmt_modes[i]; if (hsize == ptr->hdisplay && vsize == ptr->vdisplay && fresh == drm_mode_vrefresh(ptr)) { @@ -885,7 +884,7 @@ static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, } static bool -mode_is_rb(struct drm_display_mode *mode) +mode_is_rb(const struct drm_display_mode *mode) { return (mode->htotal - mode->hdisplay == 160) && (mode->hsync_end - mode->hdisplay == 80) && @@ -894,7 +893,8 @@ mode_is_rb(struct drm_display_mode *mode) } static bool -mode_in_hsync_range(struct drm_display_mode *mode, struct edid *edid, u8 *t) +mode_in_hsync_range(const struct drm_display_mode *mode, + struct edid *edid, u8 *t) { int hsync, hmin, hmax; @@ -910,7 +910,8 @@ mode_in_hsync_range(struct drm_display_mode *mode, struct edid *edid, u8 *t) } static bool -mode_in_vsync_range(struct drm_display_mode *mode, struct edid *edid, u8 *t) +mode_in_vsync_range(const struct drm_display_mode *mode, + struct edid *edid, u8 *t) { int vsync, vmin, vmax; @@ -941,7 +942,7 @@ range_pixel_clock(struct edid *edid, u8 *t) } static bool -mode_in_range(struct drm_display_mode *mode, struct edid *edid, +mode_in_range(const struct drm_display_mode *mode, struct edid *edid, struct detailed_timing *timing) { u32 max_clock; @@ -1472,7 +1473,7 @@ int drm_add_modes_noedid(struct drm_connector *connector, int hdisplay, int vdisplay) { int i, count, num_modes = 0; - struct drm_display_mode *mode, *ptr; + struct drm_display_mode *mode; struct drm_device *dev = connector->dev; count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); @@ -1482,7 +1483,7 @@ int drm_add_modes_noedid(struct drm_connector *connector, vdisplay = 0; for (i = 0; i < count; i++) { - ptr = &drm_dmt_modes[i]; + const struct drm_display_mode *ptr = &drm_dmt_modes[i]; if (hdisplay && vdisplay) { /* * Only when two are valid, they will be used to check diff --git a/drivers/gpu/drm/drm_edid_modes.h b/drivers/gpu/drm/drm_edid_modes.h index 6eb7592..5f20644 100644 --- a/drivers/gpu/drm/drm_edid_modes.h +++ b/drivers/gpu/drm/drm_edid_modes.h @@ -32,7 +32,7 @@ * This table is copied from xfree86/modes/xf86EdidModes.c. * But the mode with Reduced blank feature is deleted. */ -static struct drm_display_mode drm_dmt_modes[] = { +static const struct drm_display_mode drm_dmt_modes[] = { /* 640x350@85Hz */ { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 736, 832, 0, 350, 382, 385, 445, 0, @@ -266,7 +266,7 @@ static struct drm_display_mode drm_dmt_modes[] = { static const int drm_num_dmt_modes = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); -static struct drm_display_mode edid_est_modes[] = { +static const struct drm_display_mode edid_est_modes[] = { { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 968, 1056, 0, 600, 601, 605, 628, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index 6977a1c..d421f9d 100644 --- a/drivers/gpu/drm/drm_fb_helper.c +++ b/drivers/gpu/drm/drm_fb_helper.c @@ -627,6 +627,11 @@ static int setcolreg(struct drm_crtc *crtc, u16 red, u16 green, value = (red << info->var.red.offset) | (green << info->var.green.offset) | (blue << info->var.blue.offset); + if (info->var.transp.length > 0) { + u32 mask = (1 << info->var.transp.length) - 1; + mask <<= info->var.transp.offset; + value |= mask; + } palette[regno] = value; return 0; } diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c index aa8df25..57ce27c 100644 --- a/drivers/gpu/drm/drm_gem.c +++ b/drivers/gpu/drm/drm_gem.c @@ -101,7 +101,7 @@ drm_gem_init(struct drm_device *dev) dev->mm_private = mm; - if (drm_ht_create(&mm->offset_hash, 19)) { + if (drm_ht_create(&mm->offset_hash, 12)) { kfree(mm); return -ENOMEM; } diff --git a/drivers/gpu/drm/drm_hashtab.c b/drivers/gpu/drm/drm_hashtab.c index a93d7b4..e3a7568 100644 --- a/drivers/gpu/drm/drm_hashtab.c +++ b/drivers/gpu/drm/drm_hashtab.c @@ -39,27 +39,18 @@ int drm_ht_create(struct drm_open_hash *ht, unsigned int order) { - unsigned int i; + unsigned int size = 1 << order; - ht->size = 1 << order; ht->order = order; - ht->fill = 0; ht->table = NULL; - ht->use_vmalloc = ((ht->size * sizeof(*ht->table)) > PAGE_SIZE); - if (!ht->use_vmalloc) { - ht->table = kcalloc(ht->size, sizeof(*ht->table), GFP_KERNEL); - } - if (!ht->table) { - ht->use_vmalloc = 1; - ht->table = vmalloc(ht->size*sizeof(*ht->table)); - } + if (size <= PAGE_SIZE / sizeof(*ht->table)) + ht->table = kcalloc(size, sizeof(*ht->table), GFP_KERNEL); + else + ht->table = vzalloc(size*sizeof(*ht->table)); if (!ht->table) { DRM_ERROR("Out of memory for hash table\n"); return -ENOMEM; } - for (i=0; i< ht->size; ++i) { - INIT_HLIST_HEAD(&ht->table[i]); - } return 0; } EXPORT_SYMBOL(drm_ht_create); @@ -180,7 +171,6 @@ int drm_ht_remove_key(struct drm_open_hash *ht, unsigned long key) list = drm_ht_find_key(ht, key); if (list) { hlist_del_init(list); - ht->fill--; return 0; } return -EINVAL; @@ -189,7 +179,6 @@ int drm_ht_remove_key(struct drm_open_hash *ht, unsigned long key) int drm_ht_remove_item(struct drm_open_hash *ht, struct drm_hash_item *item) { hlist_del_init(&item->head); - ht->fill--; return 0; } EXPORT_SYMBOL(drm_ht_remove_item); @@ -197,10 +186,10 @@ EXPORT_SYMBOL(drm_ht_remove_item); void drm_ht_remove(struct drm_open_hash *ht) { if (ht->table) { - if (ht->use_vmalloc) - vfree(ht->table); - else + if ((PAGE_SIZE / sizeof(*ht->table)) >> ht->order) kfree(ht->table); + else + vfree(ht->table); ht->table = NULL; } } diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index 58e65f9..25bf873 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -593,7 +593,7 @@ EXPORT_SYMBOL(drm_mode_height); * * Return @modes's hsync rate in kHz, rounded to the nearest int. */ -int drm_mode_hsync(struct drm_display_mode *mode) +int drm_mode_hsync(const struct drm_display_mode *mode) { unsigned int calc_val; @@ -627,7 +627,7 @@ EXPORT_SYMBOL(drm_mode_hsync); * If it is 70.288, it will return 70Hz. * If it is 59.6, it will return 60Hz. */ -int drm_mode_vrefresh(struct drm_display_mode *mode) +int drm_mode_vrefresh(const struct drm_display_mode *mode) { int refresh = 0; unsigned int calc_val; @@ -725,7 +725,7 @@ EXPORT_SYMBOL(drm_mode_set_crtcinfo); * a pointer to it. Used to create new instances of established modes. */ struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev, - struct drm_display_mode *mode) + const struct drm_display_mode *mode) { struct drm_display_mode *nmode; int new_id; diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 6a09c14..318f398 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1460,7 +1460,7 @@ static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) * Note! This is in reply order (see loop in get_tv_modes). * XXX: all 60Hz refresh? */ -struct drm_display_mode sdvo_tv_modes[] = { +static const struct drm_display_mode sdvo_tv_modes[] = { { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, 416, 0, 200, 201, 232, 233, 0, DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c index 123969d..2b4e5e9 100644 --- a/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/drivers/gpu/drm/nouveau/nouveau_mem.c @@ -409,6 +409,7 @@ nouveau_mem_vram_init(struct drm_device *dev) if (ret) return ret; + dev_priv->ttm.bdev.dev = dev->dev; ret = ttm_bo_device_init(&dev_priv->ttm.bdev, dev_priv->ttm.bo_global_ref.ref.object, &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET, diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c index 9a250eb..07b1151 100644 --- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c +++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c @@ -12,6 +12,7 @@ struct nouveau_sgdma_be { struct drm_device *dev; dma_addr_t *pages; + bool *ttm_alloced; unsigned nr_pages; u64 offset; @@ -20,7 +21,8 @@ struct nouveau_sgdma_be { static int nouveau_sgdma_populate(struct ttm_backend *be, unsigned long num_pages, - struct page **pages, struct page *dummy_read_page) + struct page **pages, struct page *dummy_read_page, + dma_addr_t *dma_addrs) { struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be; struct drm_device *dev = nvbe->dev; @@ -34,15 +36,25 @@ nouveau_sgdma_populate(struct ttm_backend *be, unsigned long num_pages, if (!nvbe->pages) return -ENOMEM; + nvbe->ttm_alloced = kmalloc(sizeof(bool) * num_pages, GFP_KERNEL); + if (!nvbe->ttm_alloced) + return -ENOMEM; + nvbe->nr_pages = 0; while (num_pages--) { - nvbe->pages[nvbe->nr_pages] = - pci_map_page(dev->pdev, pages[nvbe->nr_pages], 0, + if (dma_addrs[nvbe->nr_pages] != DMA_ERROR_CODE) { + nvbe->pages[nvbe->nr_pages] = + dma_addrs[nvbe->nr_pages]; + nvbe->ttm_alloced[nvbe->nr_pages] = true; + } else { + nvbe->pages[nvbe->nr_pages] = + pci_map_page(dev->pdev, pages[nvbe->nr_pages], 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); - if (pci_dma_mapping_error(dev->pdev, - nvbe->pages[nvbe->nr_pages])) { - be->func->clear(be); - return -EFAULT; + if (pci_dma_mapping_error(dev->pdev, + nvbe->pages[nvbe->nr_pages])) { + be->func->clear(be); + return -EFAULT; + } } nvbe->nr_pages++; @@ -65,11 +77,14 @@ nouveau_sgdma_clear(struct ttm_backend *be) be->func->unbind(be); while (nvbe->nr_pages--) { - pci_unmap_page(dev->pdev, nvbe->pages[nvbe->nr_pages], + if (!nvbe->ttm_alloced[nvbe->nr_pages]) + pci_unmap_page(dev->pdev, nvbe->pages[nvbe->nr_pages], PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); } kfree(nvbe->pages); + kfree(nvbe->ttm_alloced); nvbe->pages = NULL; + nvbe->ttm_alloced = NULL; nvbe->nr_pages = 0; } } diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c index 28119fd..3900ceb 100644 --- a/drivers/gpu/drm/nouveau/nv17_tv.c +++ b/drivers/gpu/drm/nouveau/nv17_tv.c @@ -197,10 +197,12 @@ static int nv17_tv_get_ld_modes(struct drm_encoder *encoder, struct drm_connector *connector) { struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); - struct drm_display_mode *mode, *tv_mode; + const struct drm_display_mode *tv_mode; int n = 0; for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) { + struct drm_display_mode *mode; + mode = drm_mode_duplicate(encoder->dev, tv_mode); mode->clock = tv_norm->tv_enc_mode.vrefresh * diff --git a/drivers/gpu/drm/nouveau/nv17_tv.h b/drivers/gpu/drm/nouveau/nv17_tv.h index 6bf0384..622e722 100644 --- a/drivers/gpu/drm/nouveau/nv17_tv.h +++ b/drivers/gpu/drm/nouveau/nv17_tv.h @@ -112,7 +112,7 @@ extern struct nv17_tv_norm_params { } nv17_tv_norms[NUM_TV_NORMS]; #define get_tv_norm(enc) (&nv17_tv_norms[to_tv_enc(enc)->tv_norm]) -extern struct drm_display_mode nv17_tv_modes[]; +extern const struct drm_display_mode nv17_tv_modes[]; static inline int interpolate(int y0, int y1, int y2, int x) { diff --git a/drivers/gpu/drm/nouveau/nv17_tv_modes.c b/drivers/gpu/drm/nouveau/nv17_tv_modes.c index 9d3893c..4d1d29f 100644 --- a/drivers/gpu/drm/nouveau/nv17_tv_modes.c +++ b/drivers/gpu/drm/nouveau/nv17_tv_modes.c @@ -438,7 +438,7 @@ void nv17_tv_state_load(struct drm_device *dev, struct nv17_tv_state *state) /* Timings similar to the ones the blob sets */ -struct drm_display_mode nv17_tv_modes[] = { +const struct drm_display_mode nv17_tv_modes[] = { { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 0, 320, 344, 392, 560, 0, 200, 200, 202, 220, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 7831e08..4706294 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c @@ -71,75 +71,164 @@ struct r600_cs_track { u64 db_bo_mc; }; +#define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc } +#define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc } +#define FMT_24_BIT(fmt) [fmt] = { 1, 1, 3, 0 } +#define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc } +#define FMT_48_BIT(fmt) [fmt] = { 1, 1, 6, 0 } +#define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc } +#define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0 } +#define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16, vc } + +struct gpu_formats { + unsigned blockwidth; + unsigned blockheight; + unsigned blocksize; + unsigned valid_color; +}; + +static const struct gpu_formats color_formats_table[] = { + /* 8 bit */ + FMT_8_BIT(V_038004_COLOR_8, 1), + FMT_8_BIT(V_038004_COLOR_4_4, 1), + FMT_8_BIT(V_038004_COLOR_3_3_2, 1), + FMT_8_BIT(V_038004_FMT_1, 0), + + /* 16-bit */ + FMT_16_BIT(V_038004_COLOR_16, 1), + FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1), + FMT_16_BIT(V_038004_COLOR_8_8, 1), + FMT_16_BIT(V_038004_COLOR_5_6_5, 1), + FMT_16_BIT(V_038004_COLOR_6_5_5, 1), + FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1), + FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1), + FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1), + + /* 24-bit */ + FMT_24_BIT(V_038004_FMT_8_8_8), + + /* 32-bit */ + FMT_32_BIT(V_038004_COLOR_32, 1), + FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1), + FMT_32_BIT(V_038004_COLOR_16_16, 1), + FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1), + FMT_32_BIT(V_038004_COLOR_8_24, 1), + FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1), + FMT_32_BIT(V_038004_COLOR_24_8, 1), + FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1), + FMT_32_BIT(V_038004_COLOR_10_11_11, 1), + FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1), + FMT_32_BIT(V_038004_COLOR_11_11_10, 1), + FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1), + FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1), + FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1), + FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1), + FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0), + FMT_32_BIT(V_038004_FMT_32_AS_8, 0), + FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0), + + /* 48-bit */ + FMT_48_BIT(V_038004_FMT_16_16_16), + FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT), + + /* 64-bit */ + FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1), + FMT_64_BIT(V_038004_COLOR_32_32, 1), + FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1), + FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1), + FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1), + + FMT_96_BIT(V_038004_FMT_32_32_32), + FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT), + + /* 128-bit */ + FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1), + FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1), + + [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 }, + [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 }, + + /* block compressed formats */ + [V_038004_FMT_BC1] = { 4, 4, 8, 0 }, + [V_038004_FMT_BC2] = { 4, 4, 16, 0 }, + [V_038004_FMT_BC3] = { 4, 4, 16, 0 }, + [V_038004_FMT_BC4] = { 4, 4, 8, 0 }, + [V_038004_FMT_BC5] = { 4, 4, 16, 0}, + +}; + +static inline bool fmt_is_valid_color(u32 format) +{ + if (format > ARRAY_SIZE(color_formats_table)) + return false; + + if (color_formats_table[format].valid_color) + return true; + + return false; +} + +static inline bool fmt_is_valid_texture(u32 format) +{ + if (format > ARRAY_SIZE(color_formats_table)) + return false; + + if (color_formats_table[format].blockwidth > 0) + return true; + + return false; +} + +static inline int fmt_get_blocksize(u32 format) +{ + if (format > ARRAY_SIZE(color_formats_table)) + return 0; + + return color_formats_table[format].blocksize; +} + +static inline int fmt_get_nblocksx(u32 format, u32 w) +{ + unsigned bw; + if (format > ARRAY_SIZE(color_formats_table)) + return 0; + + bw = color_formats_table[format].blockwidth; + if (bw == 0) + return 0; + + return (w + bw - 1) / bw; +} + +static inline int fmt_get_nblocksy(u32 format, u32 h) +{ + unsigned bh; + if (format > ARRAY_SIZE(color_formats_table)) + return 0; + + bh = color_formats_table[format].blockheight; + if (bh == 0) + return 0; + + return (h + bh - 1) / bh; +} + static inline int r600_bpe_from_format(u32 *bpe, u32 format) { - switch (format) { - case V_038004_COLOR_8: - case V_038004_COLOR_4_4: - case V_038004_COLOR_3_3_2: - case V_038004_FMT_1: - *bpe = 1; - break; - case V_038004_COLOR_16: - case V_038004_COLOR_16_FLOAT: - case V_038004_COLOR_8_8: - case V_038004_COLOR_5_6_5: - case V_038004_COLOR_6_5_5: - case V_038004_COLOR_1_5_5_5: - case V_038004_COLOR_4_4_4_4: - case V_038004_COLOR_5_5_5_1: - *bpe = 2; - break; - case V_038004_FMT_8_8_8: - *bpe = 3; - break; - case V_038004_COLOR_32: - case V_038004_COLOR_32_FLOAT: - case V_038004_COLOR_16_16: - case V_038004_COLOR_16_16_FLOAT: - case V_038004_COLOR_8_24: - case V_038004_COLOR_8_24_FLOAT: - case V_038004_COLOR_24_8: - case V_038004_COLOR_24_8_FLOAT: - case V_038004_COLOR_10_11_11: - case V_038004_COLOR_10_11_11_FLOAT: - case V_038004_COLOR_11_11_10: - case V_038004_COLOR_11_11_10_FLOAT: - case V_038004_COLOR_2_10_10_10: - case V_038004_COLOR_8_8_8_8: - case V_038004_COLOR_10_10_10_2: - case V_038004_FMT_5_9_9_9_SHAREDEXP: - case V_038004_FMT_32_AS_8: - case V_038004_FMT_32_AS_8_8: - *bpe = 4; - break; - case V_038004_COLOR_X24_8_32_FLOAT: - case V_038004_COLOR_32_32: - case V_038004_COLOR_32_32_FLOAT: - case V_038004_COLOR_16_16_16_16: - case V_038004_COLOR_16_16_16_16_FLOAT: - *bpe = 8; - break; - case V_038004_FMT_16_16_16: - case V_038004_FMT_16_16_16_FLOAT: - *bpe = 6; - break; - case V_038004_FMT_32_32_32: - case V_038004_FMT_32_32_32_FLOAT: - *bpe = 12; - break; - case V_038004_COLOR_32_32_32_32: - case V_038004_COLOR_32_32_32_32_FLOAT: - *bpe = 16; - break; - case V_038004_FMT_GB_GR: - case V_038004_FMT_BG_RG: - case V_038004_COLOR_INVALID: - default: - *bpe = 16; - return -EINVAL; - } + unsigned res; + if (format > ARRAY_SIZE(color_formats_table)) + goto fail; + + res = color_formats_table[format].blocksize; + if (res == 0) + goto fail; + + *bpe = res; return 0; + +fail: + *bpe = 16; + return -EINVAL; } struct array_mode_checker { @@ -148,7 +237,7 @@ struct array_mode_checker { u32 nbanks; u32 npipes; u32 nsamples; - u32 bpe; + u32 blocksize; }; /* returns alignment in pixels for pitch/height/depth and bytes for base */ @@ -162,7 +251,7 @@ static inline int r600_get_array_mode_alignment(struct array_mode_checker *value u32 tile_height = 8; u32 macro_tile_width = values->nbanks; u32 macro_tile_height = values->npipes; - u32 tile_bytes = tile_width * tile_height * values->bpe * values->nsamples; + u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples; u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes; switch (values->array_mode) { @@ -174,7 +263,7 @@ static inline int r600_get_array_mode_alignment(struct array_mode_checker *value *base_align = 1; break; case ARRAY_LINEAR_ALIGNED: - *pitch_align = max((u32)64, (u32)(values->group_size / values->bpe)); + *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize)); *height_align = tile_height; *depth_align = 1; *base_align = values->group_size; @@ -182,7 +271,7 @@ static inline int r600_get_array_mode_alignment(struct array_mode_checker *value case ARRAY_1D_TILED_THIN1: *pitch_align = max((u32)tile_width, (u32)(values->group_size / - (tile_height * values->bpe * values->nsamples))); + (tile_height * values->blocksize * values->nsamples))); *height_align = tile_height; *depth_align = 1; *base_align = values->group_size; @@ -190,12 +279,12 @@ static inline int r600_get_array_mode_alignment(struct array_mode_checker *value case ARRAY_2D_TILED_THIN1: *pitch_align = max((u32)macro_tile_width, (u32)(((values->group_size / tile_height) / - (values->bpe * values->nsamples)) * + (values->blocksize * values->nsamples)) * values->nbanks)) * tile_width; *height_align = macro_tile_height * tile_height; *depth_align = 1; *base_align = max(macro_tile_bytes, - (*pitch_align) * values->bpe * (*height_align) * values->nsamples); + (*pitch_align) * values->blocksize * (*height_align) * values->nsamples); break; default: return -EINVAL; @@ -234,21 +323,22 @@ static void r600_cs_track_init(struct r600_cs_track *track) static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) { struct r600_cs_track *track = p->track; - u32 bpe = 0, slice_tile_max, size, tmp; + u32 slice_tile_max, size, tmp; u32 height, height_align, pitch, pitch_align, depth_align; u64 base_offset, base_align; struct array_mode_checker array_check; volatile u32 *ib = p->ib->ptr; unsigned array_mode; - + u32 format; if (G_0280A0_TILE_MODE(track->cb_color_info[i])) { dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n"); return -EINVAL; } size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i]; - if (r600_bpe_from_format(&bpe, G_0280A0_FORMAT(track->cb_color_info[i]))) { + format = G_0280A0_FORMAT(track->cb_color_info[i]); + if (!fmt_is_valid_color(format)) { dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", - __func__, __LINE__, G_0280A0_FORMAT(track->cb_color_info[i]), + __func__, __LINE__, format, i, track->cb_color_info[i]); return -EINVAL; } @@ -267,7 +357,7 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) array_check.nbanks = track->nbanks; array_check.npipes = track->npipes; array_check.nsamples = track->nsamples; - array_check.bpe = bpe; + array_check.blocksize = fmt_get_blocksize(format); if (r600_get_array_mode_alignment(&array_check, &pitch_align, &height_align, &depth_align, &base_align)) { dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, @@ -310,7 +400,7 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) } /* check offset */ - tmp = height * pitch * bpe; + tmp = fmt_get_nblocksy(format, height) * fmt_get_nblocksx(format, pitch) * fmt_get_blocksize(format); if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) { /* the initial DDX does bad things with the CB size occasionally */ @@ -432,7 +522,7 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) array_check.nbanks = track->nbanks; array_check.npipes = track->npipes; array_check.nsamples = track->nsamples; - array_check.bpe = bpe; + array_check.blocksize = bpe; if (r600_get_array_mode_alignment(&array_check, &pitch_align, &height_align, &depth_align, &base_align)) { dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, @@ -1107,39 +1197,61 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx return 0; } -static inline unsigned minify(unsigned size, unsigned levels) +static inline unsigned mip_minify(unsigned size, unsigned level) { - size = size >> levels; - if (size < 1) - size = 1; - return size; + unsigned val; + + val = max(1U, size >> level); + if (level > 0) + val = roundup_pow_of_two(val); + return val; } -static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned nlevels, - unsigned w0, unsigned h0, unsigned d0, unsigned bpe, - unsigned pitch_align, +static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel, + unsigned w0, unsigned h0, unsigned d0, unsigned format, + unsigned block_align, unsigned height_align, unsigned base_align, unsigned *l0_size, unsigned *mipmap_size) { - unsigned offset, i, level, face; - unsigned width, height, depth, rowstride, size; - - w0 = minify(w0, 0); - h0 = minify(h0, 0); - d0 = minify(d0, 0); + unsigned offset, i, level; + unsigned width, height, depth, size; + unsigned blocksize; + unsigned nbx, nby; + unsigned nlevels = llevel - blevel + 1; + + *l0_size = -1; + blocksize = fmt_get_blocksize(format); + + w0 = mip_minify(w0, 0); + h0 = mip_minify(h0, 0); + d0 = mip_minify(d0, 0); for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) { - width = minify(w0, i); - height = minify(h0, i); - depth = minify(d0, i); - for(face = 0; face < nfaces; face++) { - rowstride = ALIGN((width * bpe), pitch_align); - size = height * rowstride * depth; - offset += size; - offset = (offset + 0x1f) & ~0x1f; - } + width = mip_minify(w0, i); + nbx = fmt_get_nblocksx(format, width); + + nbx = round_up(nbx, block_align); + + height = mip_minify(h0, i); + nby = fmt_get_nblocksy(format, height); + nby = round_up(nby, height_align); + + depth = mip_minify(d0, i); + + size = nbx * nby * blocksize; + if (nfaces) + size *= nfaces; + else + size *= depth; + + if (i == 0) + *l0_size = size; + + if (i == 0 || i == 1) + offset = round_up(offset, base_align); + + offset += size; } - *l0_size = ALIGN((w0 * bpe), pitch_align) * h0 * d0; *mipmap_size = offset; - if (!nlevels) + if (llevel == 0) *mipmap_size = *l0_size; if (!blevel) *mipmap_size -= *l0_size; @@ -1163,11 +1275,13 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i u32 tiling_flags) { struct r600_cs_track *track = p->track; - u32 nfaces, nlevels, blevel, w0, h0, d0, bpe = 0; + u32 nfaces, llevel, blevel, w0, h0, d0; u32 word0, word1, l0_size, mipmap_size; u32 height_align, pitch, pitch_align, depth_align; + u32 array, barray, larray; u64 base_align; struct array_mode_checker array_check; + u32 format; /* on legacy kernel we don't perform advanced check */ if (p->rdev == NULL) @@ -1193,19 +1307,25 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i case V_038000_SQ_TEX_DIM_3D: break; case V_038000_SQ_TEX_DIM_CUBEMAP: - nfaces = 6; + if (p->family >= CHIP_RV770) + nfaces = 8; + else + nfaces = 6; break; case V_038000_SQ_TEX_DIM_1D_ARRAY: case V_038000_SQ_TEX_DIM_2D_ARRAY: + array = 1; + break; case V_038000_SQ_TEX_DIM_2D_MSAA: case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA: default: dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0)); return -EINVAL; } - if (r600_bpe_from_format(&bpe, G_038004_DATA_FORMAT(word1))) { + format = G_038004_DATA_FORMAT(word1); + if (!fmt_is_valid_texture(format)) { dev_warn(p->dev, "%s:%d texture invalid format %d\n", - __func__, __LINE__, G_038004_DATA_FORMAT(word1)); + __func__, __LINE__, format); return -EINVAL; } @@ -1216,7 +1336,7 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i array_check.nbanks = track->nbanks; array_check.npipes = track->npipes; array_check.nsamples = 1; - array_check.bpe = bpe; + array_check.blocksize = fmt_get_blocksize(format); if (r600_get_array_mode_alignment(&array_check, &pitch_align, &height_align, &depth_align, &base_align)) { dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n", @@ -1245,22 +1365,29 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i word0 = radeon_get_ib_value(p, idx + 4); word1 = radeon_get_ib_value(p, idx + 5); blevel = G_038010_BASE_LEVEL(word0); - nlevels = G_038014_LAST_LEVEL(word1); - r600_texture_size(nfaces, blevel, nlevels, w0, h0, d0, bpe, - (pitch_align * bpe), + llevel = G_038014_LAST_LEVEL(word1); + if (array == 1) { + barray = G_038014_BASE_ARRAY(word1); + larray = G_038014_LAST_ARRAY(word1); + + nfaces = larray - barray + 1; + } + r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, format, + pitch_align, height_align, base_align, &l0_size, &mipmap_size); /* using get ib will give us the offset into the texture bo */ word0 = radeon_get_ib_value(p, idx + 2) << 8; if ((l0_size + word0) > radeon_bo_size(texture)) { dev_warn(p->dev, "texture bo too small (%d %d %d %d -> %d have %ld)\n", - w0, h0, bpe, word0, l0_size, radeon_bo_size(texture)); + w0, h0, format, word0, l0_size, radeon_bo_size(texture)); + dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align); return -EINVAL; } /* using get ib will give us the offset into the mipmap bo */ word0 = radeon_get_ib_value(p, idx + 3) << 8; if ((mipmap_size + word0) > radeon_bo_size(mipmap)) { /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n", - w0, h0, bpe, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));*/ + w0, h0, format, blevel, nlevels, word0, mipmap_size, radeon_bo_size(texture));*/ } return 0; } diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h index a5d898b..d1f5986 100644 --- a/drivers/gpu/drm/radeon/r600d.h +++ b/drivers/gpu/drm/radeon/r600d.h @@ -1303,6 +1303,11 @@ #define V_038004_FMT_16_16_16_FLOAT 0x0000002E #define V_038004_FMT_32_32_32 0x0000002F #define V_038004_FMT_32_32_32_FLOAT 0x00000030 +#define V_038004_FMT_BC1 0x00000031 +#define V_038004_FMT_BC2 0x00000032 +#define V_038004_FMT_BC3 0x00000033 +#define V_038004_FMT_BC4 0x00000034 +#define V_038004_FMT_BC5 0x00000035 #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 15e86b4..55fefe7 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -329,6 +329,7 @@ struct radeon_gart { union radeon_gart_table table; struct page **pages; dma_addr_t *pages_addr; + bool *ttm_alloced; bool ready; }; @@ -341,7 +342,8 @@ void radeon_gart_fini(struct radeon_device *rdev); void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, int pages); int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, - int pages, struct page **pagelist); + int pages, struct page **pagelist, + dma_addr_t *dma_addr); /* diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c index 9ac1bf0..f0534ef 100644 --- a/drivers/gpu/drm/radeon/radeon_gart.c +++ b/drivers/gpu/drm/radeon/radeon_gart.c @@ -149,8 +149,9 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); for (i = 0; i < pages; i++, p++) { if (rdev->gart.pages[p]) { - pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p], - PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); + if (!rdev->gart.ttm_alloced[p]) + pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p], + PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); rdev->gart.pages[p] = NULL; rdev->gart.pages_addr[p] = rdev->dummy_page.addr; page_base = rdev->gart.pages_addr[p]; @@ -165,7 +166,7 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, } int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, - int pages, struct page **pagelist) + int pages, struct page **pagelist, dma_addr_t *dma_addr) { unsigned t; unsigned p; @@ -180,15 +181,22 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); for (i = 0; i < pages; i++, p++) { - /* we need to support large memory configurations */ - /* assume that unbind have already been call on the range */ - rdev->gart.pages_addr[p] = pci_map_page(rdev->pdev, pagelist[i], + /* On TTM path, we only use the DMA API if TTM_PAGE_FLAG_DMA32 + * is requested. */ + if (dma_addr[i] != DMA_ERROR_CODE) { + rdev->gart.ttm_alloced[p] = true; + rdev->gart.pages_addr[p] = dma_addr[i]; + } else { + /* we need to support large memory configurations */ + /* assume that unbind have already been call on the range */ + rdev->gart.pages_addr[p] = pci_map_page(rdev->pdev, pagelist[i], 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); - if (pci_dma_mapping_error(rdev->pdev, rdev->gart.pages_addr[p])) { - /* FIXME: failed to map page (return -ENOMEM?) */ - radeon_gart_unbind(rdev, offset, pages); - return -ENOMEM; + if (pci_dma_mapping_error(rdev->pdev, rdev->gart.pages_addr[p])) { + /* FIXME: failed to map page (return -ENOMEM?) */ + radeon_gart_unbind(rdev, offset, pages); + return -ENOMEM; + } } rdev->gart.pages[p] = pagelist[i]; page_base = rdev->gart.pages_addr[p]; @@ -251,6 +259,12 @@ int radeon_gart_init(struct radeon_device *rdev) radeon_gart_fini(rdev); return -ENOMEM; } + rdev->gart.ttm_alloced = kzalloc(sizeof(bool) * + rdev->gart.num_cpu_pages, GFP_KERNEL); + if (rdev->gart.ttm_alloced == NULL) { + radeon_gart_fini(rdev); + return -ENOMEM; + } /* set GART entry to point to the dummy page by default */ for (i = 0; i < rdev->gart.num_cpu_pages; i++) { rdev->gart.pages_addr[i] = rdev->dummy_page.addr; @@ -267,6 +281,8 @@ void radeon_gart_fini(struct radeon_device *rdev) rdev->gart.ready = false; kfree(rdev->gart.pages); kfree(rdev->gart.pages_addr); + kfree(rdev->gart.ttm_alloced); rdev->gart.pages = NULL; rdev->gart.pages_addr = NULL; + rdev->gart.ttm_alloced = NULL; } diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c index e17e595..177adc8 100644 --- a/drivers/gpu/drm/radeon/radeon_ttm.c +++ b/drivers/gpu/drm/radeon/radeon_ttm.c @@ -513,6 +513,7 @@ int radeon_ttm_init(struct radeon_device *rdev) if (r) { return r; } + rdev->mman.bdev.dev = rdev->dev; /* No others user of address space so set it to 0 */ r = ttm_bo_device_init(&rdev->mman.bdev, rdev->mman.bo_global_ref.ref.object, @@ -647,6 +648,7 @@ struct radeon_ttm_backend { unsigned long num_pages; struct page **pages; struct page *dummy_read_page; + dma_addr_t *dma_addrs; bool populated; bool bound; unsigned offset; @@ -655,12 +657,14 @@ struct radeon_ttm_backend { static int radeon_ttm_backend_populate(struct ttm_backend *backend, unsigned long num_pages, struct page **pages, - struct page *dummy_read_page) + struct page *dummy_read_page, + dma_addr_t *dma_addrs) { struct radeon_ttm_backend *gtt; gtt = container_of(backend, struct radeon_ttm_backend, backend); gtt->pages = pages; + gtt->dma_addrs = dma_addrs; gtt->num_pages = num_pages; gtt->dummy_read_page = dummy_read_page; gtt->populated = true; @@ -673,6 +677,7 @@ static void radeon_ttm_backend_clear(struct ttm_backend *backend) gtt = container_of(backend, struct radeon_ttm_backend, backend); gtt->pages = NULL; + gtt->dma_addrs = NULL; gtt->num_pages = 0; gtt->dummy_read_page = NULL; gtt->populated = false; @@ -693,7 +698,7 @@ static int radeon_ttm_backend_bind(struct ttm_backend *backend, gtt->num_pages, bo_mem, backend); } r = radeon_gart_bind(gtt->rdev, gtt->offset, - gtt->num_pages, gtt->pages); + gtt->num_pages, gtt->pages, gtt->dma_addrs); if (r) { DRM_ERROR("failed to bind %lu pages at 0x%08X\n", gtt->num_pages, gtt->offset); diff --git a/drivers/gpu/drm/ttm/ttm_agp_backend.c b/drivers/gpu/drm/ttm/ttm_agp_backend.c index f999e36..1c4a72f 100644 --- a/drivers/gpu/drm/ttm/ttm_agp_backend.c +++ b/drivers/gpu/drm/ttm/ttm_agp_backend.c @@ -47,7 +47,8 @@ struct ttm_agp_backend { static int ttm_agp_populate(struct ttm_backend *backend, unsigned long num_pages, struct page **pages, - struct page *dummy_read_page) + struct page *dummy_read_page, + dma_addr_t *dma_addrs) { struct ttm_agp_backend *agp_be = container_of(backend, struct ttm_agp_backend, backend); diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index af61fc2..0b6a55a 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -406,11 +406,12 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, } if (bo->mem.mem_type == TTM_PL_SYSTEM) { + if (bdev->driver->move_notify) + bdev->driver->move_notify(bo, mem); bo->mem = *mem; mem->mm_node = NULL; goto moved; } - } if (bdev->driver->move_notify) diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c index b1e02ff..35849db 100644 --- a/drivers/gpu/drm/ttm/ttm_page_alloc.c +++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c @@ -38,6 +38,7 @@ #include <linux/mm.h> #include <linux/seq_file.h> /* for seq_printf */ #include <linux/slab.h> +#include <linux/dma-mapping.h> #include <asm/atomic.h> @@ -662,7 +663,8 @@ out: * cached pages. */ int ttm_get_pages(struct list_head *pages, int flags, - enum ttm_caching_state cstate, unsigned count) + enum ttm_caching_state cstate, unsigned count, + dma_addr_t *dma_address, struct device *dev) { struct ttm_page_pool *pool = ttm_get_pool(flags, cstate); struct page *p = NULL; @@ -681,14 +683,22 @@ int ttm_get_pages(struct list_head *pages, int flags, gfp_flags |= GFP_HIGHUSER; for (r = 0; r < count; ++r) { - p = alloc_page(gfp_flags); + if ((flags & TTM_PAGE_FLAG_DMA32) && dma_address) { + void *addr; + addr = dma_alloc_coherent(dev, PAGE_SIZE, + &dma_address[r], + gfp_flags); + if (addr == NULL) + return -ENOMEM; + p = virt_to_page(addr); + } else + p = alloc_page(gfp_flags); if (!p) { printk(KERN_ERR TTM_PFX "Unable to allocate page."); return -ENOMEM; } - list_add(&p->lru, pages); } return 0; @@ -720,7 +730,7 @@ int ttm_get_pages(struct list_head *pages, int flags, printk(KERN_ERR TTM_PFX "Failed to allocate extra pages " "for large request."); - ttm_put_pages(pages, 0, flags, cstate); + ttm_put_pages(pages, 0, flags, cstate, NULL, NULL); return r; } } @@ -731,17 +741,30 @@ int ttm_get_pages(struct list_head *pages, int flags, /* Put all pages in pages list to correct pool to wait for reuse */ void ttm_put_pages(struct list_head *pages, unsigned page_count, int flags, - enum ttm_caching_state cstate) + enum ttm_caching_state cstate, dma_addr_t *dma_address, + struct device *dev) { unsigned long irq_flags; struct ttm_page_pool *pool = ttm_get_pool(flags, cstate); struct page *p, *tmp; + unsigned r; if (pool == NULL) { /* No pool for this memory type so free the pages */ + r = page_count-1; list_for_each_entry_safe(p, tmp, pages, lru) { - __free_page(p); + if ((flags & TTM_PAGE_FLAG_DMA32) && dma_address) { + void *addr = page_address(p); + WARN_ON(!addr || !dma_address[r]); + if (addr) + dma_free_coherent(dev, PAGE_SIZE, + addr, + dma_address[r]); + dma_address[r] = 0; + } else + __free_page(p); + r--; } /* Make the pages list empty */ INIT_LIST_HEAD(pages); diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index af789dc..0f8fc9f 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -49,12 +49,16 @@ static int ttm_tt_swapin(struct ttm_tt *ttm); static void ttm_tt_alloc_page_directory(struct ttm_tt *ttm) { ttm->pages = drm_calloc_large(ttm->num_pages, sizeof(*ttm->pages)); + ttm->dma_address = drm_calloc_large(ttm->num_pages, + sizeof(*ttm->dma_address)); } static void ttm_tt_free_page_directory(struct ttm_tt *ttm) { drm_free_large(ttm->pages); ttm->pages = NULL; + drm_free_large(ttm->dma_address); + ttm->dma_address = NULL; } static void ttm_tt_free_user_pages(struct ttm_tt *ttm) @@ -105,7 +109,8 @@ static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int index) INIT_LIST_HEAD(&h); - ret = ttm_get_pages(&h, ttm->page_flags, ttm->caching_state, 1); + ret = ttm_get_pages(&h, ttm->page_flags, ttm->caching_state, 1, + &ttm->dma_address[index], ttm->be->bdev->dev); if (ret != 0) return NULL; @@ -164,7 +169,7 @@ int ttm_tt_populate(struct ttm_tt *ttm) } be->func->populate(be, ttm->num_pages, ttm->pages, - ttm->dummy_read_page); + ttm->dummy_read_page, ttm->dma_address); ttm->state = tt_unbound; return 0; } @@ -298,7 +303,8 @@ static void ttm_tt_free_alloced_pages(struct ttm_tt *ttm) count++; } } - ttm_put_pages(&h, count, ttm->page_flags, ttm->caching_state); + ttm_put_pages(&h, count, ttm->page_flags, ttm->caching_state, + ttm->dma_address, ttm->be->bdev->dev); ttm->state = tt_unpopulated; ttm->first_himem_page = ttm->num_pages; ttm->last_lomem_page = -1; diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c b/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c index 80bc37b..87e43e0 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c @@ -102,7 +102,8 @@ struct vmw_ttm_backend { static int vmw_ttm_populate(struct ttm_backend *backend, unsigned long num_pages, struct page **pages, - struct page *dummy_read_page) + struct page *dummy_read_page, + dma_addr_t *dma_addrs) { struct vmw_ttm_backend *vmw_be = container_of(backend, struct vmw_ttm_backend, backend); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c index 96949b9..df04661 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c @@ -322,7 +322,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); dev_priv->active_master = &dev_priv->fbdev_master; - + dev_priv->bdev.dev = dev->dev; ret = ttm_bo_device_init(&dev_priv->bdev, dev_priv->bo_global_ref.ref.object, &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET, diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c index 29113c9..b3a2cd5 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c @@ -345,7 +345,7 @@ static enum drm_connector_status return connector_status_disconnected; } -static struct drm_display_mode vmw_ldu_connector_builtin[] = { +static const struct drm_display_mode vmw_ldu_connector_builtin[] = { /* 640x480@60Hz */ { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 752, 800, 0, 480, 489, 492, 525, 0, @@ -429,7 +429,6 @@ static int vmw_ldu_connector_fill_modes(struct drm_connector *connector, struct drm_device *dev = connector->dev; struct vmw_private *dev_priv = vmw_priv(dev); struct drm_display_mode *mode = NULL; - struct drm_display_mode *bmode; struct drm_display_mode prefmode = { DRM_MODE("preferred", DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -459,6 +458,8 @@ static int vmw_ldu_connector_fill_modes(struct drm_connector *connector, } for (i = 0; vmw_ldu_connector_builtin[i].type != 0; i++) { + const struct drm_display_mode *bmode; + bmode = &vmw_ldu_connector_builtin[i]; if (bmode->hdisplay > max_width || bmode->vdisplay > max_height) |