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* OMAP4: cpuidle: don't touch mpu and core state until CPU1 is offlianwei.wang2014-10-011-10/+10
| | | | | | | | | | MPU/Core logic and PD states shouldn't be changed until CPU1 is completely off Change-Id: Ia90126776e7bd7108c7b885c622df36323982cb0 Signed-off-by: Lianwei Wang <lian-wei.wang@motorola.com> Signed-off-by: suilunlam <a0868997@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
* ARM: OMAP4: cpuidle: Configure MPU C4 state to OSWRMadhusudan Chittim2014-10-011-4/+4
| | | | | | | | | | | Due to MPU_EMIF_NO_DYNDEP_IDLE_iXXX, MPU->EMIF dynamic dependency is disabled when going to LP mode. This allows us to enable deeper power state for MPU as MPU can transition to lower power state independent of core power domain. We have observed 1.5mA saving in OS Idle Screen on use case. Change-Id: If4ec4426626dabf810b1f21ed33cdabafa386d5f Signed-off-by: Madhusudan Chittim <c-madhu@ti.com>
* ARM: OMAP4: cpuidle: prevent CPU1 from locking CPU0 in idle entryYuan Jiangli2012-02-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | We can have a lockup scenario when two cpu are spin waiting for each other: CPU0: omap4_enter_idle() |---omap4_enter_idle_primary() |---------while (omap4_idle_requested_cx[1]) cpu_relax(); CPU1: omap4_enter_idle() |---- while ((omap4_idle_ready_count == 0) && omap4_all_cpus_idle()) { spin_unlock(&omap4_idle_lock); cpu_relax(); spin_lock(&omap4_idle_lock); } Depend on idle ready count to let CPU0 to progress forward. Change-Id: Ida6b60f618e8078701fcad8d976c3f1620cc71e6 Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Yuan Jiangli <jlyuan@motorola.com>
* ARM: omap4: cpuidle: configure MPU C4 state to CSWRColin Cross2011-10-251-11/+6
| | | | | | | | | | For enabling dynamic dependency btn MPUSS <-> EMIF, device is unstable at with MPUSS configured to OSWR. By disabling static dep btn MPUSS <->EMIF, there is significant power saving seen on during active use-cases. So hence preventing MPUSS power domain to CSWR. Change-Id: I63902a501997e2e9f8b7539f2f17067af0b417f1 Signed-off-by: Ambresh K <ambresh@ti.com>
* ARM: omap4: cpuidle: prevent OSWR during idleColin Cross2011-10-191-1/+6
| | | | | | | | | | | Prevent OSWR on mpuss during idle to allow the static dependency between the mpuss and emif clock domains to be disabled. A HW bug prevents using OSWR if the static dependency is not enabled, but the power savings of dropping the static dependency is higher than the savings in OSWR vs. CSWR. Change-Id: I7da24d2d29cb87c314bcf2db37ca668684383c7b Signed-off-by: Colin Cross <ccross@android.com>
* ARM: omap4: cpuidle: fix typos in cpuidle target residenciesColin Cross2011-10-191-2/+2
| | | | | | | | | | | Increase the target residencies of C3 and C4 to match the exit latencies. Should have no effect, at least when using the menu cpuidle governor, because the menu governor will only use a state where the predicted sleep is greater than the exit latency and the target residency. Change-Id: I33453aecd925dea0bf445137c5ef3ba68d4c3cd5 Signed-off-by: Colin Cross <ccross@android.com>
* ARM: omap4: idle: check for ipi before going to idleColin Cross2011-09-271-3/+21
| | | | | | | | | If an ipi is received while waiting in wfi, it could be lost when we turn off the gic. After both cpus have agreed to go idle, check for pending interrupts on both cpus. Change-Id: I941c7248c76f6bb2835dd633d141fb115c8ed079 Signed-off-by: Colin Cross <ccross@android.com>
* ARM: omap4: cpuidle: use cpu_pm to save VFP registersColin Cross2011-09-261-0/+9
| | | | | | | | VFP registers are not being saved by sleep44xx.S, use cpu_pm notifiers to trigger the VFP code to save them. Change-Id: Ic59621568ca4caa10877e077be87094cf21d0473 Signed-off-by: Colin Cross <ccross@android.com>
* ARM: omap4: cpuidle: update exit latenciesColin Cross2011-09-191-7/+7
| | | | | | | Update exit latencies based on latest measurements. Change-Id: Ieb90fbc4c32925915d5baf3b7c42d3b001f2c49f Signed-off-by: Colin Cross <ccross@android.com>
* ARM: omap4: cpuidle: don't leave wfi until an interrupt is pendingColin Cross2011-09-191-3/+23
| | | | | | | | | | Sometimes wfi is exited with no interrupt pending. If this happens, go back into wfi. If we just return, the cpuidle governor will see short idle times, and start avoiding longer idle states, increasing power usage. Change-Id: I756bebde974c5068dec819641797347c79bbf584 Signed-off-by: Colin Cross <ccross@android.com>
* ARM: omap4: cpuidle: wait for cpu1 to boot before releasing cpu0Colin Cross2011-09-071-0/+7
| | | | | | | | cpu1 mucks with page tables while it is starting, prevent cpu0 executing any processes until cpu1 is up. Change-Id: Ic6e24b6cd039f180cd420cba3919398c28ea1332 Signed-off-by: Colin Cross <ccross@android.com>
* ARM: omap4: cpuidle: allow all states when both cpus are activeColin Cross2011-09-021-143/+484
| | | | | | | | | | | | | | | | | | Add a power sequencing step to omap4_enter_idle that waits for the other cpu to be ready, and then go to the higher of the two requested idle states. When both cpus are ready, sequence the power off so that it follows the same order as when hotplug is used: cpu1 off, then cpu0 off, and when powering on, cpu0 on, then cpu1 on. In order to minimize power when waiting for the other cpu, the waiting cpu should be in wfi. omap4_idle_wait waits in wfi for either an interrupt to abort suspend, or an event from the other cpu (emulated with an unused interrupt triggered directly into the GIC). Change-Id: I8a8e49529c674aeda1584e851fe9eb11cde8fc09 Signed-off-by: Colin Cross <ccross@android.com>
* OMAP4: PM: allow sleep to know if called inline of suspendAxel Haslam2011-07-231-1/+1
| | | | | | | | | | omap4_enter_sleep has no differentiation between idle and suspend at the moment. by introducing suspend differentiation, we can now selectively do operations in subsequent patches such as selective disable/enable of SmartReflex etc. Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Axel Haslam <axelhaslam@ti.com>
* OMAP4: PM: remove hacks that were needed for serialNishanth Menon2011-07-141-36/+3
| | | | | | | Since runtime PM is active for serial, we dont need the hacks we added in PM layer for handling runtime PM. Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP4: CPUIDLE: If OSWR is enabled, allow C4 state.Axel Haslam2011-07-101-1/+5
| | | | | | | | C4 is defined as OSWR for MPU and CORE powerdomains If OSWR is enabled as a config option, enable C4 state for idle path. Signed-off-by: Axel Haslam <axelhaslam@ti.com>
* OMAP4: CPUidle: Change comment of C1 to CPU0 WFINishanth Menon2011-06-131-3/+3
| | | | | | | | To align with the technical jargon already prevelant, name the C1 state to state CPU0 WFI. Acked-by: Axel Haslam <axelhaslam@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP4: CPUidle: Set MPU, CPU0 and core to INACTIVE for C2Axel Haslam2011-06-131-7/+7
| | | | | | | | Currently C1 and C2 states are the same. Define C2 state as INACTIVE for CPU0, MPU and core which will cut internal ARM clocks and save more power. Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Axel Haslam <axelhaslam@ti.com>
* OMAP4: CPUIDLE: correct cpuidle target_residencyAxel Haslam2011-06-131-4/+4
| | | | | | | | | exit_latency was defined twice in the table, second parameter is target_residency and not exit_latency. Acked-by: Ambresh K <ambresh@ti.com> Signed-off-by: Axel Haslam <axelhaslam@ti.com>
* OMAP4: PM: Make MPU and CORE next states as ON unless trying to sleepRajendra Nayak2011-06-131-0/+3
| | | | | | | | | | | | | Leaving the next power states of MPU and CORE to sleep states have seen issues when secure software trying a wfi and accidentally hitting sleep states. Always keep MPU and CORE states programmed to ON unless attempting a sleep. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Reported-by: Patrick Titiano <p-titiano@ti.com> Rebased-by: Axel Haslam <axelhaslam@ti.com>
* OMAP4:CPUIDLE: populate new cpuidle_params structureAxel Haslam2011-06-131-34/+24
| | | | | | | | | | To fix a compilation break, use the new cpu idle structure. The new structure was intrduced by: OMAP3: clean-up mach specific cpuidle data structures Signed-off-by: Axel Haslam <axelhaslam@ti.com>
* OMAP4:CPUIDLE: remove CPUIDLE_FLAG_CHECK_BM checkAxel Haslam2011-06-131-1/+1
| | | | | | | | | | | Bm check function pointer is set at init fora given C state, and the flag is overwriten when a hotplug operation happens. Since the bm_check function pointer is set, having the flag check is redundant, and prevents the check from happening after hotplug operation. Signed-off-by: Axel Haslam <axelhaslam@ti.com>
* OMAP4: CPUIDLE: update latency table with recomended valuesAxel Haslam2011-06-131-3/+3
| | | | | | | Update cpuidle_params_table, with the latency values that where recomended, and characterized. Signed-off-by: Axel Haslam <axelhaslam@ti.com>
* OMAP4: CPUIDLE: Define C4 as OSWRAxel Haslam2011-06-131-5/+6
| | | | | | | | | | | It is not necessary to have C4 and C3 defined as equal states. C4 state will be OSWR for MPU and CORE, Define C4 states appropriately, and disable this state until supported. Signed-off-by: Axel Haslam <axelhaslam@ti.com>
* OMAP4: CPUIDLE: Rename omap4_idle_bm_checkAxel Haslam2011-06-131-5/+5
| | | | | | | | Rename omap4_idle_bm_check to omap4_idle_bm_busy to be more intuitive and adjust the return value appropriately. Signed-off-by: Axel Haslam <axelhaslam@ti.com>
* Restrict mpu PD to retAvinash.H.M2011-06-131-5/+5
| | | | | | | | MPU OFF isn't supported in 4460. So restrict MPUOFF to MPURET in both cpuidle and suspend-resume path. C4 definition is changed from MPUOFF,CORERET to MPURET,CORERET. Signed-off-by: Avinash.H.M <avinashhm@ti.com>
* omap4: enable cpuidle support for CORE RET.Avinash.H.M2011-06-131-17/+52
| | | | | | | | | Add the cpuidle initialization routines for omap4. Define the C states and attempt CORE RET. The low level code is shared between suspend resume and cpuidle. Signed-off-by: Avinash.H.M <avinashhm@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com>
* OMAP4: cpuidle: Add CPU hotplug notifier and prepare() hook.Santosh Shilimkar2011-06-131-0/+64
| | | | | | | | | | | | | | | | On OMAP4 CPUidle, the low power states are triggered when CPU1 is offlined to OFF power state. When the CPU1 is online, no low power states are supported. The patch adds CPU hotplug notifier to manage the C-state states using CPUidle prepare() hook and CPUIDLE_FLAG_IGNORE c-state flag. This was suggested by Kevin Hilman <khilman@ti.com> during OMAP4 PM code review. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Kevin Hilman <khilman@ti.com>
* OMAP4: cpuidle: Switch to gptimer from twd in deeper C-states.Santosh Shilimkar2011-06-131-0/+8
| | | | | | | | | | | | | | | CPU local timer(TWD) stops when the CPU is transitioning into deeper C-States. Since these timers are not wakeup capable, we need the wakeup capable global timer to program the wakeup time depending on the next timer expiry. It can be handled by registering a global wakeup capable timer along with local timers marked with (mis)feature flag CLOCK_EVT_FEAT_C3STOP. Then notify the clock events layer from idle code using CLOCK_EVT_NOTIFY_BROADCAST_ENTER/EXIT). Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Kevin Hilman <khilman@ti.com>
* OMAP4: cpuidle: Add MPUSS RET OFF statesSantosh Shilimkar2011-06-131-5/+124
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds MPUSS low power states in cpuidle. C1 - CPU0 ON + CPU1 ON + MPU ON C2 - CPU0 ON + CPU1 OFF + MPU ON C3 - CPU0 OFF + CPU1 OFF + MPU CSWR C4 - CPU0 OFF + CPU1 OFF + MPU OFF MPU OSWR isn't supported yet. To support OSWR, power domain context registers needs to be managed which are not supported yet. A patch to address this was submitted but it's not ready for merge yet because it was not addressing all OMAP4 power domain context registers. More info on this issue: http://www.mail-archive.com/linux-omap@vger.kernel.org/msg38667.html OMAP4 powerdomain INACTIVE support is also dropped because of inconsistency of it with OMAP3. More information on this thread. http://www.spinics.net/lists/linux-omap/msg45370.html CORE low power states and associated latencies will be updated as part along with chip retention support. On OMAP4 because of hardware constraints, no low power states are targeted when both CPUs are online and in SMP mode. The low power states are attempted only when secondary CPU gets offline to OFF through hotplug infrastructure. Thanks to Nicole Chalhoub <n-chalhoub@ti.com> for doing exhaustive C-state latency profiling. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Kevin Hilman <khilman@ti.com>
* OMAP4: cpuidle: Basic CPUidle supportRajendra Nayak2011-06-131-0/+161
The patch adds a basic CPUidle driver for OMAP4. Just one C state is registered for CPU0 which does a WFI. CPU1 is left with defualt idle and the low power state for it is managed via cpu-hotplug. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Kevin Hilman <khilman@ti.com>
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