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* OMAP4470: OPP: Change IVA OPP100 to CORE OPP dependencyOleksandr_Tyshchenko2014-10-011-1/+1
| | | | | | | | | | From timing closure point only VDD_CORE should be scaled to OPP100 level for IVA to be able to work at OPP100. L3 frequency can stay at 116MHz. So CORE OPP100H can be used as dependent OPP for IVA OPP100. Change-Id: I2493a4c45d81ebfbfd24600a90bd4ea2d3782c24 Signed-off-by: Oleksandr_Tyshchenko <oleksandr.tyshchenko@ti.com>
* OMAP4: OPP: Add DSS OPPsTaras Kondratiuk2014-10-011-0/+16
| | | | | | | | | | | To generate pixel clock rate higher than 93MHz DSS has to scale VDD_CORE to at least OPP100 level. This patch adds two DSS OPPs, for DSS to be able to control minimum VDD_CORE level. Change-Id: I98eab1c3b56fcf41026b742cb43c8155b68dd5c4 Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAP4470: OPP/voltage: Add CORE OPP100 to High Perf CORE OPP setTaras Kondratiuk2014-10-011-5/+19
| | | | | | | | | | | | | | | | Initially 4470 High Performance CORE OPP set didn't have OPP100 defined. That's why when some devices need OPP100 VDD_CORE voltage level to work at higher frequency they have to scale L3 to OPP-OV. To fill a gap between OPP50 and OPP-OV a new OPP100 have been added. It has OPP100 voltage level but keeps L3 frequency at 116MHz. Both 4470's OPP sets share same OPP depencensies tables, so a new OPP100H is defined to maintain correct depencencies in both OPP sets. Change-Id: Iab44165a4f0a8fecf6888e52a307425bd264e5cd Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAP4470: OPP: Enable SGX OPP-OV for Low Power OPP setTaras Kondratiuk2014-10-011-1/+1
| | | | | | | | | | | Initial 4470 Low Power OPP set was copied from 4460 OPP set. 4460 OPP set had SGX OPP-OV disabled by commit 919cf0ce816b626f1d836d050a31463650f54526. This commit is reverted and 4460 SGX OPP-OV is enabled. Same should be done for 4470. Change-Id: I7483a8669da79479303453495c0d41f959daa9ad Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAP4470: OPP: Add initial BB2D OPP definitionsEugen Mandrenko2014-10-011-0/+10
| | | | | | | | Add new 4470 OPP definitions for 2D graphics accelerator subsystem Change-Id: I8e41b788df4769ed2ffab496f8a2ea4fc8cb5b1f Signed-off-by: Taras Kondratiuk <taras@ti.com> Signed-off-by: Eugen Mandrenko <ievgen.mandrenko@ti.com>
* OMAP4470: OPP: Update ABB type according to trim bitsTaras Kondratiuk2014-10-011-21/+46
| | | | | | | | | | | | | | | | | Depending on a trim bits blown into eFuse register CONTROL_STD_FUSE_OPP_DPLL_1 RBB should be enabled at some MPU/IVA OPPs to reduce a leakage on OMAP4470. Bit #| Name | Description ------+-----------------+--------------------------------------- 20 | MPU_RBB_TURBO | 0 - RBB is trimmed and should be used. 21 | IVA_RBB_TURBO | 1 - RBB is not trimmed 22 | MPU_RBB_NITRO | 23 | MPU_RBB_NITROSB | 24 | IVA_RBB_NITRO | 25 | IVA_RBB_NITROSB | Change-Id: Idd76e8dd2f5e55573f6dd6f7515ab57d87b14125 Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAP4: OPP: Make ABB type trim update more genericTaras Kondratiuk2014-10-011-69/+61
| | | | | | | | Change omap4460_abb_update() with generic omap4_abb_trim_update() So it can be used for other devices and OPPs. Change-Id: I2390bedc439b3388eda9efbaaecf1d66f7436ab8 Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAP4460: OPP: update ABB for IVA OPP turboNishanth Menon2014-10-011-0/+18
| | | | | | | | | | | | | | | On 4460 all OPPs have pre-determined states for VDD_IVA's ABB LDO, except for OPP_TURBO. OPP_TURBO may require bypass or RBB. depending on a characterisation data blown into eFuse register CONTROL_STD_FUSE_OPP_DPLL_1. Bit 21 of that register signify DPLL_IVA trim OPP_TURBO might put IVA's ABB LDO into bypass or RBB based on this value. This patch introduces ABB type detection into the OPP init code. Change-Id: Ie2f49652fda667943a7a9ac76d529c6a594b8755 Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP4460: OPP: Move ABB update for MPU OPP turbo to OPP init codeMike Turquette2014-10-011-0/+94
| | | | | | | | | | | | | | Initially ABB type update was implemented in ABB init code. This leads to a voltage values duplication. This patch moves ABB type detection into the OPP init code. Change-Id: I6140dff1be0f2b9e667160da957c8e1dbabf3e8f [taras@ti.com: remove previous implementation] Signed-off-by: Taras Kondratiuk <taras@ti.com> [nm@ti.com: movement of code to central opp update] Signed-off-by: Nishanth Menon <nm@ti.com> [mturquette@ti.com: original author] Signed-off-by: Mike Turquette <mturquette@ti.com>
* OMAP4: OPP: Correct default ABB type for MPU OPP TurboTaras Kondratiuk2014-10-011-1/+1
| | | | | | | | | | | | | | | | | Default MPU ABB type for OMAP4460/70 is following: OPP | ABB type ---------+---------- OPP50 | Bypass OPP100 | Bypass OPPTB | Bypass OPPNT | FBB OPPNTSB | FBB This patch corrects default ABB type for MPU OPP Turbo for OMAP4460/70. Change-Id: Ifc424be0b3d103f8923d2633f1a1830f2de9651f Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAP4470: OPP: Fix voltages of FDIF and HSI OPP100Taras Kondratiuk2014-10-011-2/+2
| | | | | | | | High Power CORE OPP set of OMAP4470 doesn't have OPP100. So FDIF@OPP100 and HSI@OPP100 should request CORE OPP-OV voltages. Change-Id: I768916b6a0d82132886157add37d918f87c7ebd7 Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAP4: OPP: enable all higher OPPs for VDD_IVANishanth Menon2014-10-011-34/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The standard PMICs used with OMAP44xx are TWL603x. OMAP hooks its VDD_IVA net to one of TWL's regulators. OMAP | PMIC / REG | Max REG current | Max VDD_IVA current ----------+------------------+-----------------+--------------------- OMAP4430 | TWL6030 / VCORE2 | 1000mA [1] | 700mA [3] OMAP4460 | TWL6030 / VCORE2 | 1000mA [1] | 1000mA [4] OMAP4470 | TWL6032 / SMPS5 | 1100mA [2] | 1100mA [5] Max regulator's current, definitely allows us to enable higher OPPs on VDD_IVA. This enables the possibility of doing better performing DVFS on IVA intensive usecases. VDD_IVA has DSP and IVA devices connected. This allows the OPP Turbo to be enabled for all OMAP44xx devices. On OMAP4460/70 OPP Nitro can be enabled for Standard silicon while OPP NitroSB can be enabled for Performance silicon. Footnotes: [1] TWL6030 datasheet SWCS045B (June 2011) [2] TWL6032 datasheet SWCS075C (Nov 2011) [3] OMAP4470 Data Manual SWPS045B (Oct 2011) [4] OMAP4460 Data Manual SWPS042J (Nov 2011) [5] OMAP4430 Data Manual SWPS040P (Oct 2011) Change-Id: I2a812bb1b65ec5d0c2321d65695d844b6c01792d [nm@ti.com: original patch author] Signed-off-by: Nishanth Menon <nm@ti.com> [taras@ti.com: added OMAP4470 part] Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAP4: OPP: make omap4_mpu_opp_enable genericNishanth Menon2014-10-011-11/+12
| | | | | | | | | Make omap4_mpu_opp_enable generic using the omap_hwmod_name_get_dev api so that we can reuse it for other devices as well. As part of this, rename it to omap4_opp_enable. Change-Id: I87e76b446fb4e57200edd0ae00f5ff9b70021fa5 Signed-off-by: Nishanth Menon <nm@ti.com>
* OMAP4: OPP/voltage: Add voltage for IVA OPP NitroSBTaras Kondratiuk2014-10-011-3/+9
| | | | | | | | | On OMAP4460/70 IVA OPP Nitro and OPP NitroSB voltages are the same, but they should have different nTargets for SmartReflex. Wrong nTargets lead to lower voltage and possible instability at OPPSB. Change-Id: I92558908b4e91eb64680e47e01ff82dedf93aad3 Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAP4: PM: OPP/Clock: Add virtual clocks for high IVA OPPs supportTaras Kondratiuk2014-10-011-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | To get correct frequencies for IVA OPP higher than OPP100 IVA DPLL should be reconfigured. Tesla is also supplied from the same IVA DPLL, so frequency on DSP should be reconfigured together with IVAHD frequency. This is achieved by adding virtual clocks for IVA and DSP. Main logic is implemented in IVA virtual clock which sets frequency for both IVAHD and DSP. DSP virtual clock is just a dummy clock and it do nothing. Necessary DSP OPP is set via IVA virtual clock by using DVFS framework feature: if device on which OPP is set is not the primary device in voltage domain, then constraint to the same OPP is set for primary device. In case of DSP the primary device is IVAHD. If switching to the lower OPP will cause IVA DPLL scaling up, then frequency of IVA and DSP should be scaled down before DPLL. Change-Id: I1b229f1d52f0f8bfa4f65f08221df1e1ba6194bc [jagadeeshwar.reddy@ti.com: original patch author for 4430] Signed-off-by: Jagadeeshwar Reddy <jagadeeshwar.reddy@ti.com> [taras@ti.com: modified and extended for all OMAP44xx] Signed-off-by: Taras Kondratiuk <taras@ti.com>
* ARM: OMAP4460: Fixed missing dependency map of OPP for ivaVitaly Chernooky2014-10-011-0/+1
| | | | | | | | | | | Added missing dependency map of OPP-Nitro and OPP-SpeedBin for iva. Without this line setting IVA into high OPP fail with errors: rpres iva.0: _dep_scan_table: 1375000 volt map missing in vdd_core rpres iva.0: omap_device_scale: Error in scan domains for vdd_iva Change-Id: I73df4897e886a2d4c9fa22abcbc8a6f34c2a8503 Signed-off-by: Vitaly Chernooky <vitaly.chernooky@ti.com>
* OMAP4: OPP: correct hwmod name for dsp in opp_def_listJuan Gutierrez2014-10-011-12/+12
| | | | | | | | | | | | | | Replace "dsp" with "dsp_c0" in the opp definition list. The "dsp" name refers to the dsp's iommu hwmod, and not to the dsp core itself (iommu is not opp-scalable). "dsp_c0" is the correct hwmod name that should be used in the OPP definitions list. Change-Id: I69e89e86de32b2c0f0afdb17533548fab91cee53 Signed-off-by: Juan Gutierrez <jgutierrez@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com>
* OMAP4470: OPP: Changed HSI Fclk to 192Mhz for OPP100Taras Kondratiuk2014-10-011-2/+2
| | | | | | | | | | | | HSI RX and TX bit rates depend on HSI Functional clock and cannot be higher than Fclk. Allowed higher HSI throughputs by enabling 192MHz@OPP100. Extend 3a88a5737a188df5d0a415426375bed977262530 to cover OMAP4470. Change-Id: I8653f217d6d7378f6fe4e01a58f049842dde1831 Signed-off-by: Djamil Elaidi <d-elaidi@ti.com> Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAP4470: OPP: Set SmartReflex voltage margins to zeroEugen Mandrenko2014-10-011-7/+7
| | | | | | | | | | | SmartReflex voltage margins were added for OMAP4460, because it has nTarget optimized for SR 3.0. OMAP4470 has nTarget optimized for SR 1.5 so these margins can be removed. Change-Id: I7213fad18ecffe939b522c5ee1858a1ceb77ad5a Signed-off-by: Taras Kondratiuk <taras@ti.com> Signed-off-by: Eugen Mandrenko <ievgen.mandrenko@ti.com>
* OMAP4430: OPP/voltage: 1.2GHz needs different SR ntargetEugen Mandrenko2014-10-011-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | nTarget value for 1.2GHz uses the nTarget efuse offset meant for 1GHz. This can cause instabilities since the voltage levels are lower than required for operating at 1.2GHz. Since SR nTarget values are hooked to omap_volt_data structure and Vnom for 1.2GHz is same as 1GHz, we need to ensure a uniquely identifiable voltage for 1.2GHz to supply the right offset. We do this by adding a 10mV step on top of 1GHz Vnom. This additional step should have no impact as SmartReflex AVS will adjust this to optimal voltage on enabling SR from Vnom in operation. With the unique voltage entry in omap_volt_data for 1.2GHz, we provide the right efuse offset for 1.2GHz and map the OPP entry for 1.2GHz to use this "OPPNITROSB" voltage. This will allow voltage and SmartReflex AVS mapping back to the right nTarget offsets + adjust voltage to the correct optimal voltage levels for 1.2GHz. Change-Id: I1e8d0efa46cfb5d6db1b54ef5fc323d0b7877fef Signed-off-by: Taras Kondratiuk <taras@ti.com> Signed-off-by: Eugen Mandrenko <ievgen.mandrenko@ti.com>
* [4470] Fix 4470 OPP table merge error.Dan Murphy2014-10-011-9/+9
| | | | | | | | One variable did not make it when the merge was done. This adds the base code back in for 4470 Change-Id: Ia104670e00f44e551840cd5ac15365f37d4736f4 Signed-off-by: Dan Murphy <dmurphy@ti.com>
* ARM: OMAP4470: DSS: AVDAC removedKonstantin Shlyakhovoy2014-10-011-1/+1
| | | | | | | | | | The access to AVDAC registes was removed for OMAP4470. Signed-off-by: K.Shlyakhovoy <x0155534@ti.com> Change-Id: I4c3aa87cae8b2775f7ff2043679fd2f054754c0d Conflicts: arch/arm/mach-omap2/omap4_trim_quirks.c
* OMAP4: HACK: disable OPP 1.5 GHz on untrimmed units.Oleksandr Kozaruk2014-10-011-1/+3
| | | | | | | | | Noticed device reboots with untrimmed 1.5 GHz units. Temporary workaround to restrict the max OPP to 1.2 GHz to make it functional. Change-Id: Ia254e34893e008b4a966e5987bdb7b0099793ebc Signed-off-by: Oleksandr Kozaruk <oleksandr.kozaruk@ti.com>
* OMAP4460: OPP/voltage: 1.5GHz needs different SR ntargetNishanth Menon2014-10-011-1/+4
| | | | | | | | | | | | | | | nTarget value for 1.5GHz uses the wrong nTarget which was meant for 1.2GHz. this can cause instabilities all over the place. add a 10mV to Vnom of 1.2GHz as the start voltage for 1.5GHz and use the proper nTarget values meant for 1.5GHz. Change-Id: Ib0a669a75675149c98a7da208e662a91a9de0b84 Reported-by: Jean-Yves Caron <j-caron@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Oleksandr Kozaruk <oleksandr.kozaruk@ti.com> Conflicts: arch/arm/mach-omap2/opp4xxx_data.c
* Revert "HACK: ARM: omap4: opp: disable MPU 1.5 GHz OPP"Ziyann2014-10-011-3/+2
| | | | This reverts commit bca4426f9b44aad21802caa7c6e29ed48de7ea57.
* HACK: OMAP4470: OPP: Set MPU OPP50 to 396.8MHzLeonid Iziumtsev2014-10-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to current clock framework implementation we shall prevent unnecessary matching of DPLL target rate with bypass clock rate. Otherwise DPLL will be set to bypass mode, that can give unexpected result. Example: OPP100 -> 0PP50 (assuming that IVA is not holding CORE) .---------------------------------------------------------------. . _______ _____800MHz_____ . . | | \ . . | MPU | \______400MHz____ . . | | \_____200MHz_____ . . |-----+----------------------------------------------------- . . |mode | MPU dpll locked | MPU dpll bypass | MPU dpll bypass | . . |-----+----------------------------------------------------- . . | | . . |CORE | _______________400MHz_____________ . . |_____| \_____200MHz_____ . --------------------------------------------------------------- Result: OPP50 working on 200MHz To avoid similar situations OPP50 rate will be moved from 400 to 396.8MHz. Change-Id: I33352aa19506bbdad3cb402c167196471bbf7253 Signed-off-by: Leonid Iziumtsev <x0153368@ti.com>
* OMAP4: OPP: Add High Performance CORE OPP setTaras Kondratiuk2014-10-011-4/+80
| | | | | | | | | | | | | | | | | OMAP4470 specification defines two sets of CORE OPPs: OPP | Low Power | High Performance | | Volt | L3 | SGX | Volt | L3 | SGX | --------+------+-----+-----+------+-----+-----+ OPP50 | 0.96 | 100 | 154 | 0.96 | 117 | 191 | OPP100 | 1.13 | 200 | 307 | N/A | N/A | N/A | OPP-OV | 1.23 | 200 | 384 | 1.23 | 233 | 384 | High Performance set is enabled if CORE DPLL frequency is higher than 1600MHz. OPP100 is absent in High Performance set. Change-Id: Ief4c6617940365e18a0f5a22adf94a3c6f3b7192 Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAP4470: OPP/voltage: Add voltage for OPPSBTaras Kondratiuk2014-10-011-6/+9
| | | | | | | | OPPNT and OPPSB have the same voltage, but they should have different nTargets. Wrong nTargets leads to instability at 1.5GHz, because voltage goes too low. Change-Id: I698920118860cce47e76c5c03fa9c829c06454a2 Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAP4: OPP: Add 4470 OPP definitionsTaras Kondratiuk2014-10-011-1/+64
| | | | | | | | Add initial OPP definitions for OMAP4470. Based on Data Manual Operating Condition Addendum v0.2 for 4470. Change-Id: Ib3c1b3f4b69560e501b97a18cb72bd0aa0e4292f Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAP4: DPLL: override for untrimmed unitOleksandr Kozaruk2014-10-011-1/+7
| | | | | | | | | Read the value of DPLL TRIM register to check if unit is trimmed. If it is not trimmed override OMAP4_DPLL_NWELL_TRIM_0 register with value 0x29. Change-Id: I5a1678860a9b663b4ce9f1f53694de9930593147 Signed-off-by: Oleksandr Kozaruk <oleksandr.kozaruk@ti.com>
* OMAP4: voltage: Add 4470 voltage definitionsTaras Kondratiuk2014-10-011-0/+74
| | | | | | | | | | Add structures containing OMAP4470 voltage supported and various voltage dependent data for each VDD. Data is based on Data Manual Operating Condition Addendum v0.2 for 4470. Change-Id: I8baa6ccf26786b4ee1764fe96f312ae7fb65ccbf Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAP4: Add 1.2G OPP for 443x OPP tableGirish S Ghongdemath2014-10-011-1/+3
| | | | | | | | | 1.2G OPP can be dynamically enabled for 443x now based on si type. Adding it in OPP table. Change-Id: Id1e32a86b0afaa83c7863afdeaa902cd73a9a89c Signed-off-by: Girish S G <girishsg@ti.com> Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
* Revert "ARM: omap4: opp: disable OPP100_OV for gpu"Chittim, Madhusudan2014-10-011-1/+1
| | | | | | | | | | This reverts commit 919cf0ce816b626f1d836d050a31463650f54526. Enables SGX to run at 384MHz, SGX idling is more aggressive with APM timer set to 2ms with minimal impact to power. Change-Id: I92f45e40bb64279e2561e8b84771cd05d517d26e Signed-off-by: Chittim, Madhusudan <c-madhu@ti.com>
* OMAP4: HSI: changed Fclk to 192Mhz for OPP100Djamil Elaidi2014-10-011-2/+2
| | | | | | | | | HSI RX and TX bit rates depend on HSI Functional clock and cannot be higher than Fclk. Allowed higher HSI throughputs by enabling 192MHz@OPP100. Change-Id: I274f0860d48ec79a1331366b8866f883ae372d2f Signed-off-by: Djamil Elaidi <d-elaidi@ti.com>
* Merge branch 'android-omap-3.0' into android-omap-tuna-3.0Benoit Goby2012-04-131-26/+26
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| * OMAP4460: OPP: SR1.5: update margin to spec rev 0.4Nishanth Menon2012-04-131-10/+10
| | | | | | | | | | | | | | | | Update SR1.5 voltage margin from Operating Conditions Data Manual Addendum Revision 0.4 (December 2011) for OMAP4460. Change-Id: I4a53f39fd2eab25912f50b2e9cfdea5b8f071941 Signed-off-by: Nishanth Menon <nm@ti.com>
| * OMAP2+: PM: Voltage: allow software margin per OPPNishanth Menon2012-04-131-26/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | Allow per OPP software margin to be defined in OPP table for the voltage definitions. Note: OMAP4460 has currently recommended 10mV margin to be added. This also introduces /sys/kernel/debug/voltage/*/curr_margin_volt to show the current voltage margin used. Change-Id: Id49185ffb224d03ac05a41780ad35b1c7a20f4a0 Signed-off-by: Nishanth Menon <nm@ti.com>
* | Merge branch 'android-omap-3.0' into android-omap-tuna-3.0Colin Cross2011-09-151-1/+1
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| * ARM: omap4: opp: disable OPP100_OV for gpuColin Cross2011-09-151-1/+1
| | | | | | | | | | | | | | | | | | The gpu is the only thing that uses OPP100_OV, which has a very high power impact on the rest of the system. Disable this OPP for now, reducing the gpu clock from 384MHz to 307MHz. Change-Id: I2980aa843924b5f5f47c0e790a8d13b06494d26a Signed-off-by: Colin Cross <ccross@android.com>
* | Merge branch 'android-omap-3.0' into android-omap-tuna-3.0Colin Cross2011-08-301-0/+1
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| * OMAP4: PM: Add OPP to support Overdrive Voltage (OV) for COREGirish S Ghongdemath2011-08-301-0/+1
| | | | | | | | | | | | | | | | Add OPP to support OV for VDD CORE rail. SGX has a overdrive OPP which requres CORE to be at OV. Change-Id: I7258f282b3e9a1a5e161f051be3de1c3ade561ee Signed-off-by: Girish S G <girishsg@ti.com>
* | Merge branch 'android-omap-3.0' into android-omap-tuna-3.0Colin Cross2011-08-101-1/+1
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| * ARM: omap4: correct dsp opp data againColin Cross2011-08-101-1/+1
| | | | | | | | | | | | | | | | | | | | A bad merge from the linux-omap-3.0 tree caused one line of commit 967f02c462598eeb7d38a7be7c09323535baa642 "OMAP4460: OPP data: correct core voltage typo for fdif and dsp" to be dropped. Change-Id: I9c92472c2f568d742595c6dfc2dd288f04b96369 Signed-off-by: Colin Cross <ccross@android.com>
* | HACK: ARM: omap4: opp: disable MPU 1.5 GHz OPPColin Cross2011-08-041-2/+3
|/ | | | | | | | | | The tuna PCB does not support 1.5 GHz, but the omap 4460 might. There is no chance to disable 1.5 GHz between omap4_opp_init at device_initcall time and omap_cpufreq_init at late_initcall time, so just disable 1.5 GHz in omap4_opp_init for now. Change-Id: I1e8743a43370bf9a74c5366884f842e8bb45ab53 Signed-off-by: Colin Cross <ccross@android.com>
* OMAP4: OPP: Enable higher frequencyVishwanath BS2011-08-041-6/+33
| | | | | | | | | | | | | | | | With ABB, SmartReflex, and thermal management support in place, we can now safely enable the higher frequencies on OMAP4. Standard OMAP4460 devices have support up to 1.2GHz while high performance versions have 1.5GHz support. Since there is an efuse to detect the high performance devices, we automatically enable that frequency on detection. [nm@ti.com: cleanups] Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Colin Cross <ccross@android.com> Change-Id: I488d149ee57d1584ebe76aca266740d699a78762
* Merge branch 'linux-omap-pm-3.0' into linux-omap-3.0Colin Cross2011-08-021-24/+29
|\ | | | | | | | | | | | | Conflicts: arch/arm/mach-omap2/opp4xxx_data.c Change-Id: I240eb77af6bf12b7cded89e7fc225d9cc1ea046b
| * OMAP4-SGX: Correct SGX OPP2 entry in omap443x OPP list.Jeff McGee2011-08-021-1/+1
| | | | | | | | Signed-off-by: Jeff McGee <j-mcgee@ti.com>
| * OMAP4430: OPP data: update voltages to spec rev 0.5Nishanth Menon2011-08-021-7/+7
| | | | | | | | | | | | | | Update voltages from Operating Conditions Data Manual Addendum Revison 0.5 (July 2011). Signed-off-by: Nishanth Menon <nm@ti.com>
| * OMAP4460: OPP data: update voltages to spec rev 0.2Nishanth Menon2011-08-021-8/+8
| | | | | | | | | | | | | | Update voltages from Operating Conditions Data Manual Addendum Revison 0.2 (July 2011). Signed-off-by: Nishanth Menon <nm@ti.com>
| * OMAP4: OPP: Add OPPs for AESSMisael Lopez Cruz2011-08-021-2/+8
| | | | | | | | | | | | | | Add OPPs for Audio Engine Subsystem. Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
generated by cgit v1.1 at 2025-02-03 08:57:55 +0000