| Commit message (Collapse) | Author | Age | Files | Lines |
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commit 8404663f81d212918ff85f493649a7991209fa04 upstream.
The {get,put}_user macros don't perform range checking on the provided
__user address when !CPU_HAS_DOMAINS.
This patch reworks the out-of-line assembly accessors to check the user
address against a specified limit, returning -EFAULT if is is out of
range.
[will: changed get_user register allocation to match put_user]
[rmk: fixed building on older ARM architectures]
Change-Id: I9bfb98408bd76da6a342258dd50e72aa283f5416
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Declaring strings in assembler source involves a certain amount of
tedious boilerplate code in order to annotate the resulting symbol
correctly.
Encapsulating this boilerplate in a macro should help to avoid some
duplication and the occasional mistake.
Change-Id: I0238dfb0bc97285d9a32b55289b4949cda13fbde
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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This macro is used to generate unprivileged accesses (LDRT/STRT) to user
space.
Change-Id: Iede5f5f8454abafd3b7d4519b7aa77b85fe474b6
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Change-Id: Ic3ba8d94c0c83c832054eda8799d9e1251d70b18
Signed-off-by: Kyle Repinski <repinski23@gmail.com>
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(cherry pick from commit 7f1b5a9966b176e10d6cd322324a82be2379a51b)
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Bug: 9674955
Bug: 25773781
Change-Id: I0bed5e1b77e1309747a963719a12f20b47cd2703
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(cherry picked from commit https://lkml.org/lkml/2016/2/4/833)
Replace calls to get_random_int() followed by a cast to (unsigned long)
with calls to get_random_long(). Also address shifting bug which, in case
of x86 removed entropy mask for mmap_rnd_bits values > 31 bits.
Bug: 26963541
Signed-off-by: Daniel Cashman <dcashman@android.com>
Signed-off-by: Daniel Cashman <dcashman@google.com>
Change-Id: Iac34b63294ec120edcbf8760186667a84a5cf556
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(cherry picked from commit https://lkml.org/lkml/2015/12/21/341)
arm: arch_mmap_rnd() uses a hard-code value of 8 to generate the
random offset for the mmap base address. This value represents a
compromise between increased ASLR effectiveness and avoiding
address-space fragmentation. Replace it with a Kconfig option, which
is sensibly bounded, so that platform developers may choose where to
place this compromise. Keep 8 as the minimum acceptable value.
Bug: 24047224
Signed-off-by: Daniel Cashman <dcashman@android.com>
Signed-off-by: Daniel Cashman <dcashman@google.com>
Change-Id: I2f6c18a0060e1c21b53200ecdcfde9a8c2e3db98
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Similar to other architectures, this adds topdown mmap support in user
process address space allocation policy. This allows mmap sizes greater
than 2GB. This support is largely copied from MIPS and the generic
implementations.
The address space randomization is moved into arch_pick_mmap_layout.
Tested on V-Express with ubuntu and a mmap test from here:
https://bugs.launchpad.net/bugs/861296
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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There are already cache type decoding functions, so use those instead
of custom decode code which only works for ARMv6.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Re-enable SCSI support (for USB storage).
Align with updated BCMD driver.
Remove some deprecated options.
Change-Id: I6a7f80c35788ce814ac34585bca590e27d2c6674
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Change-Id: Ibd1164e6fa56d4a1bd8439fa18b23935171a9420
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This setting can be used both to adjust the timeout and to disable
autosuspension completely.
Change-Id: Idff82013d36ee824772994c708af502a62a232ec
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This commit implements the work-around for the power usage bug in tuna SMC
PA and enables SMC-related kernel options. Note that in order to take
advantage of this code there are also some userspace changes that are
required, e.g. enabling SMC PA loading and using tuna keymaster version
that is ported to Keymaster HAL 0.
Change-Id: I0e4705c6959e73fbeaec9bfb62d5e82e1dfa62a4
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Change-Id: I76aabb05867233b6e7b84b512bae5f5a640ab589
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So far I wasn't able to find the use case when IOBUFS goes above
~8.3MB, so lowering the threshold from 90MB to 9MB seems to be safe.
Change-Id: I0dc0874c46a2484cf28dbd2420319f9661d7f3a9
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Note that omap4_ion_heap_secure_input_addr needs a fixed value instead of
a dynamically calculated one, which would change after overriding this
carveout size, causing problems as that address is hardcoded in out Ducati.
Change-Id: I5018d88c0ecf7444b133f545f963363acaf99198
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Change-Id: I357fe0a0f36396fef89faae5429b9ac1b4aa8952
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Change-Id: I35aa150bdeda21b063591cd18ef55f01a6171e8c
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Allows newer blobs to run
Change-Id: Ib7ae1f21b681e5b85301013f8f79545e9369f88f
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Change-Id: Ie60d2124d7835e85f03008d3dfe259b70490b4f2
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The Virtualization Extensions introduce the requirement for an ARMv7-A
implementation to include SDIV and UDIV. Any implementation of the
Virtualization Extensions must include the SDIV and UDIV instructions
in the Thumb and ARM instruction sets.
In an ARMv7-A implementation that does not include the Virtualization
Extensions, it is IMPLEMENTATION DEFINED whether:
* SDIV and UDIV are not implemented
* SDIV and UDIV are implemented only in the Thumb instruction set
* SDIV and UDIV are implemented in the Thumb and ARM instruction sets.
This patch adds a handler to trap and emulate unimplemented SDIV and
UDIV instructions in ARM and Thumb modes. Also some basic statistic is
exported via /proc/cpu/idiv_emulation
Change-Id: I8e721ecac62a05fab42ed7db7951b4c837a59bc7
Signed-off-by: Vladimir Murzin <murzin.v@gmail.com>
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This patch breaks the ARM condition checking code out of nwfpe/fpopcode.{ch}
into a standalone file for opcode operations. It also modifies the code
somewhat for coding style adherence, and adds some temporary variables for
increased readability.
Change-Id: I9935fbdebff9ddd263007412edd6a2b3eb06ae69
Signed-off-by: Leif Lindholm <leif.lindholm@arm.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Change-Id: I0b793c06bb6a68ed3045d76cfc5239d0eaa71d60
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Makes Netd happier on M:
E/Netd(163): cannot find interface dummy0
See system/netd commit 3667936aadcabddc708797ac38ce1ffb2f992cb3.
Change-Id: I8b0e7f99b70a1f07c2f886ce8b0632f087223f77
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Mainly debugging ones.
Change-Id: I74e154e7774b59e30fcaaa5391ac1f16d70ed3fd
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Change-Id: Ida98ff1bce9d2b1c17e10734e872dff67c635dca
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Change-Id: I4aa6da2d40301f93af99e29b0462749046999ef7
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Change-Id: I7e20165ded78349d79e4ea75fcb409f0f8aae7b2
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This allows us to disable the unused nonsecure tiler2d carveout (10 mb).
Since the freed carveout memory will be added to tiler2d, we can lower its carveout size by this amount.
Change-Id: I12b0eb55a4bbb2f6dc251697d93c96fc574cc472
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Change-Id: Ibab8e1b343555e9d359eff6eccbadfd07687a3da
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Change-Id: I65bf354322fff214b72ca2950ada8c15a625e202
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...to avoid errors. Got a report via PM that the sharper values
may cause instabilities. I guess these settings are final now.
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Samsung K3PE7E700M RAM chips are CL5. Set it accordingly.
Also, set tRCD and tRP to what's still stable.
Adjust tWR, tCAS and tRAS to reflect sane values. Lower does
not necessarily mean better in these cases.
Information sources:
http://en.wikipedia.org/wiki/SDRAM_latency
http://forums.legitreviews.com/about20065.html
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Change-Id: Ia14955d0824e0ef4be802f27b8b14c2addb8e1c6
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- don't log sysfs reads
- make pwm value change log message clearer
- only log vibrator events in dynamic debug mode
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Change-Id: Ifbd5bb5e617e6ba3b27f1192545802f0ea7c0e82
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In less than a day's time I had quite a few minutes of nfc wakelock...
Unsure if we should bail if enable/disable of wakelock fails, will revist.
Signed-off-by: Kyle Repinski <repinski23@gmail.com>
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This reverts commit b01a056a0b676685942d80886c069499e86058e0.
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Before enabling pixel clock DSS should set its OPP
for OPP framework to set correct VDD_CORE voltage level.
When pixel clock is disabled DSS can set the lowest OPP.
Change-Id: Ia1459614ae306dba9b048b149e474442e2880bba
Signed-off-by: Taras Kondratiuk <taras@ti.com>
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- enable SLUB_DEBUG
SLUB_DEBUG is very cheap by default, and allows more expensive
poisoning to be turned on at runtime. It also makes /proc/slabinfo
available, which is critical for debugging memory issues.
- enable CONFIG_CRYPTO_AES_ARM
- enable DHD_USE_SCHED_SCAN
- normalize
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FB ram size should not be specified since it is being calculated.
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It causes more harm than good.
http://lwn.net/Articles/516533/
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