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* Merge branch 'x86-mm-for-linus' of ↵Linus Torvalds2010-02-281-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-mm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, mm: Unify kernel_physical_mapping_init() API x86, mm: Allow highmem user page tables to be disabled at boot time x86: Do not reserve brk for DMI if it's not going to be used x86: Convert tlbstate_lock to raw_spinlock x86: Use the generic page_is_ram() x86: Remove BIOS data range from e820 Move page_is_ram() declaration to mm.h Generic page_is_ram: use __weak resources: introduce generic page_is_ram()
| * Merge branch 'linus' into x86/mmThomas Gleixner2010-02-17319-5101/+18434
| |\ | | | | | | | | | | | | | | | | | | x86/mm is on 32-rc4 and missing the spinlock namespace changes which are needed for further commits into this topic. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | resources: introduce generic page_is_ram()Wu Fengguang2010-02-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's based on walk_system_ram_range(), for archs that don't have their own page_is_ram(). The static verions in MIPS and SCORE are also made global. v4: prefer plain 1 instead of PAGE_IS_RAM (H. Peter Anvin) v3: add comment (KAMEZAWA Hiroyuki) "AFAIK, this "System RAM" information has been used for kdump to grab valid memory area and seems good for the kernel itself." v2: add PAGE_IS_RAM macro (Américo Wang) Cc: Chen Liqin <liqin.chen@sunplusct.com> Cc: Lennox Wu <lennox.wu@gmail.com> Cc: Américo Wang <xiyou.wangcong@gmail.com> Cc: linux-mips@linux-mips.org Cc: Yinghai Lu <yinghai@kernel.org> Acked-by: Ralf Baechle <ralf@linux-mips.org> Reviewed-by: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com> Signed-off-by: Wu Fengguang <fengguang.wu@intel.com> LKML-Reference: <20100122081619.GA6431@localhost> Cc: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* | | MIPS: Alchemy: defconfig updatesManuel Lauss2010-02-279-4283/+6340
| | | | | | | | | | | | | | | | | | | | | | | | | | | Updated, leaner defconfig for the alchemy development boards. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1005/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Alchemy: Fix Au1100 ethernet build failureManuel Lauss2010-02-271-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't define platform info for second mac on au1100 (which only has a single mac). Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1004/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Alchemy: Repair db1500/bosporus buildsManuel Lauss2010-02-271-24/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few hunks somehow ended up outside their #ifdef/endif blocks, leading to -Werror-induces build failures. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1003/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: ARC: Cleanup unused definitions from sgialib.hYoichi Yuasa2010-02-271-45/+0
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/979/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Cobalt: convert legacy port addresses to GT-64111 bus addressesBjorn Helgaas2010-02-272-2/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GT-64111 PCI host bridge has no address translation mechanism, so it can't generate legacy port accesses. This quirk fixes legacy device port resources to contain the bus addresses actually generated by the GT-64111. I think this is the approach Ben Herrenschmidt suggested long ago: http://marc.info/?l=linux-kernel&m=119733290624544&w=2 This allows us to remove the IORESOURCE_PCI_FIXED hack from pcibios_fixup_device_resources(), which converts bus addresses to CPU addresses. IORESOURCE_PCI_FIXED denotes resources that can't be moved; it has nothing to do with converting bus to CPU addresses. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: Yoichi Yuasa <yuasa@linux-mips.org> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: linux-mips@linux-mips.org Tested-by: Yoichi Yuasa <yuasa@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/998/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Alchemy: use 36bit addresses for PCMCIA resources.Manuel Lauss2010-02-2712-132/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Alchemy the PCMCIA area lies at the end of the chips 36bit system bus area. Currently, addresses at the far end of the 32bit area are assumed to belong to the PCMCIA area and fixed up to the real 36bit address before being passed to ioremap(). A previous commit enabled 64 bit physical size for the resource datatype on Alchemy and this allows to use the correct 36bit addresses when registering the PCMCIA sockets. This patch removes the 32-to-36bit address fixup and registers the Alchemy demo board pcmcia socket with the correct 36bit physical addresses. Tested on DB1200, with a CF card (ide-cs driver) and a 3c589 PCMCIA ethernet card. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Cc: Manuel Lauss <manuel.lauss@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/994/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Cobalt: Fix theoretical port aliasing issueRalf Baechle2010-02-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because the VIA SuperIO chip only decodes 24 bits of address space but port address space currently being configured as 32MB there is the theoretical possibility of aliases within the I/O port address range. The complicated solution is to reserve all address range that potencially could cause such aliases. But with the PCI spec limiting port allocations for devices to a maximum of 256 bytes 16MB of port address space already is way more than one would ever expect to be used so we just reduce the port space to 16MB. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> To: Yoichi Yuasa <yuasa@linux-mips.org> Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: linux-mips@linux-mips.org Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Patchwork: http://patchwork.linux-mips.org/patch/995/
* | | MIPS: Use ALIGN(x, bytes) instead of __ALIGN_MASK(x, bytes - 1)Matt Turner2010-02-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ALIGN(x, bytes) expands to __ALIGN_MASK(x, bytes - 1), so use the one that is most clear. Signed-off-by: Matt Turner <mattst88@gmail.com> To: linux-mips@linux-mips.org Cc: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/999/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Crazy spinlock speed test.David Daney2010-02-273-0/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is just a test program for raw_spinlocks. The main reason I wrote it is to validate my spinlock changes that I sent in a previous patch. To use it enable CONFIG_DEBUG_FS and CONFIG_SPINLOCK_TEST then at run time do: # mount -t debugfs none /sys/kernel/debug/ # cat /sys/kernel/debug/mips/spin_single # cat /sys/kernel/debug/mips/spin_multi On my 600MHz octeon cn5860 (16 CPUs) I get spin_single spin_multi base 106885 247941 spinlock_patch 75194 219465 This shows that for uncontended locks the spinlock patch gives 41% improvement and for contended locks 12% improvement (1/time). Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/969/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Optimize spinlocks.David Daney2010-02-273-81/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current locking mechanism uses a ll/sc sequence to release a spinlock. This is slower than a wmb() followed by a store to unlock. The branching forward to .subsection 2 on sc failure slows down the contended case. So we get rid of that part too. Since we are now working on naturally aligned u16 values, we can get rid of a masking operation as the LHU already does the right thing. The ANDI are reversed for better scheduling on multi-issue CPUs On a 12 CPU 750MHz Octeon cn5750 this patch improves ipv4 UDP packet forwarding rates from 3.58*10^6 PPS to 3.99*10^6 PPS, or about 11%. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/937/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Alchemy: devboard PM needs to save CPLD registers.Manuel Lauss2010-02-271-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Save/restore CPLD registers when doing suspend-to-ram; this fixes issues with harddisk and ethernet not working correctly when resuming on DB1200. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/986/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: PowerTV: Eliminate duplicate opcode definition macrosDavid VomLehn2010-02-271-53/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change to different macros for assembler macros since the old names in powertv_setup.c were co-opted for use in asm/asm.h. This broken the build for the powertv platform. This patch introduces new macros based on the new macros in asm.h to take the place of the old macro values. Signed-off-by: David VomLehn <dvomlehn@cisco.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/985/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Lemote 2F: Move printks out of port_access_lock.Ralf Baechle2010-02-271-2/+2
| | | | | | | | | | | | | | | | | | No point in protecting them and printks are sloow. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: PNX833x: Convert IRQ controller locks to raw spinlocks.Ralf Baechle2010-02-271-18/+18
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Octeon: Replace spinlock with raw_spinlocks in dma-octeon.c.David Daney2010-02-271-5/+5
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/973/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Octeon: Replace rwlocks in irq_chip handlers with raw_spinlocks.David Daney2010-02-271-28/+14
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/972/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Octeon: Convert octeon_irq_msi_lock to raw spinlock.Ralf Baechle2010-02-271-5/+5
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Loongson: Remove pointless sample_lock from oprofile code.Ralf Baechle2010-02-271-7/+0
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: SNI: Convert sni_rm200_i8259A_lock to raw spinlock.Ralf Baechle2010-02-271-11/+11
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: i8259: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-273-16/+16
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: IP27: Convert nmi_lock lock to arch spinlock;Ralf Baechle2010-02-271-2/+2
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: IP27: Remove code obfuscation by enter_panic_mode().Ralf Baechle2010-02-271-3/+2
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: GT641xx: Convert timer lock to raw spinlock.Ralf Baechle2010-02-271-5/+5
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Alchemy: Simplify DMA channel allocation code.Ralf Baechle2010-02-271-55/+56
| | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Manuel Lauss <manuel.lauss@googlemail.com>
* | | MIPS: Yosemite: Convert SMP startup lock to arch spinlock.Ralf Baechle2010-02-271-4/+4
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Alchemy: Remove time_lock.Ralf Baechle2010-02-271-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | The sole user is au1xxx_calc_clock() which is only used in early bootup where the is no paralellism thus no race condition to protect against. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: Manuel Lauss <manuel.lauss@googlemail.com>
* | | MIPS: DEC: Convert KN01 lock to raw spinlock.Ralf Baechle2010-02-271-5/+5
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: BCM63xx: Convert timer locks to raw spinlocks.Ralf Baechle2010-02-271-17/+17
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: PowerTV: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-271-3/+3
| | | | | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Cc: David VomLehn <dvomlehn@cisco.com>
* | | MIPS: Malta: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-271-3/+3
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: SB1480: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-271-7/+7
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: SB1250: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-271-7/+7
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: GT641xx: Convert IRQ controller lock to raw spinlock.Ralf Baechle2010-02-271-9/+9
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Jazz: Convert irq controller lock to raw spinlock.Ralf Baechle2010-02-271-5/+5
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Make various locks static.Ralf Baechle2010-02-279-9/+9
| | | | | | | | | | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Octeon: Do proper acknowledgment of CIU timer interrupts.David Daney2010-02-271-4/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: netdev@vger.kernel.org To: gregkh@suse.de Patchwork: http://patchwork.linux-mips.org/patch/967/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Use generic ucontext.hYoichi Yuasa2010-02-271-21/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/959/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Use generic serial.hYoichi Yuasa2010-02-271-22/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/960/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Use generic parport.hYoichi Yuasa2010-02-271-15/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/958/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Use generic current.hYoichi Yuasa2010-02-271-23/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/957/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUsDavid Daney2010-02-271-0/+3
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/955/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Give Octeon+ CPUs their own cputype.David Daney2010-02-273-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows us to treat them differently at runtime. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/951/ Patchwork: http://patchwork.linux-mips.org/patch/987/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Implement Read Inhibit/eXecute InhibitDavid Daney2010-02-2710-79/+348
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit (XI) bits in the page tables work. The upper two bits of EntryLo{0,1} are RI and XI when the feature is enabled in the PageGrain register. SmartMIPS only covers 32-bit systems. Cavium Octeon+ extends this to 64-bit systems by continuing to place the RI and XI bits in the top of EntryLo even when EntryLo is 64-bits wide. Because we need to carry the RI and XI bits in the PTE, the layout of the PTE is changed. There is a two instruction overhead in the TLB refill hot path to get the EntryLo bits into the proper position. Also the TLB load exception has to probe the TLB to check if RI or XI caused the exception. Also of note is that the layout of the PTE bits is done at compile and runtime rather than statically. In the 32-bit case this allows for the same number of PFN bits as before the patch as the _PAGE_HUGE is not supported in 32-bit kernels (we have _PAGE_NO_EXEC and _PAGE_NO_READ instead of _PAGE_READ and _PAGE_HUGE). The patch is tested on Cavium Octeon+, but should also work on 32-bit systems with the Smart-MIPS ASE. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/952/ Patchwork: http://patchwork.linux-mips.org/patch/956/ Patchwork: http://patchwork.linux-mips.org/patch/962/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Add TLBR and ROTR to uasm.David Daney2010-02-272-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and ROTR support in uasm. We also add a UASM_i_ROTR macro. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/953/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Add accessor functions and bit definitions for c0_PageGrainDavid Daney2010-02-271-0/+11
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/950/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels.David Daney2010-02-271-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 64-bit CPUs have 64-bit c0_entrylo{0,1} registers. We should use the 64-bit dmtc0 instruction to set them. This becomes important if we want to set the RI and XI bits present in some processors. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/954/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | MIPS: Remove trailing space in messagesFrans Pop2010-02-273-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Frans Pop <elendil@planet.nl> To: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/946/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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