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* powerpc/pci: Clean up direct access to sysdata by 4xx platformsKumar Gala2009-05-211-2/+2
| | | | | | | | | | We shouldn't directly access sysdata to get the pci_controller. Instead use pci_bus_to_host() for this purpose. In the future we might have sysdata be a device_node to match ppc64 and unify the code between ppc32 & ppc64. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
* Merge commit 'origin/master' into nextBenjamin Herrenschmidt2009-03-111-0/+17
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| * powerpc/44x: Fix address decoding setup of PCI 2.x cellsBenjamin Herrenschmidt2009-02-271-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PCI 2.x cells used on some 44x SoCs only let us configure the decode for the low 32-bit of the incoming PLB addresses. The top 4 bits (this is a 36-bit bus) are hard wired to different values depending on the specific SoC in use. Our code used to work "by accident" until I added support for the ISA memory holes and while at it added more validity checking of the addresses. This patch should bring it back to working condition. It still relies on the device-tree being correct but that's somewhat a pre-requisite for anything to work anyway. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | powerpc/4xx: Enable PCI domains on 4xxBenjamin Herrenschmidt2009-02-141-0/+2
|/ | | | | | | | | | 4xx chips commonly now have multiple PHBs, there is no reason to not enable PCI domains on them. The main issue with PCI domains is X but currently its already somewhat busted for other reasons such as the 36-bit physical address space, which I'm fixing separately. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/4xx: Add support for ISA holes on 4xx PCI/X/EBenjamin Herrenschmidt2008-12-041-98/+208
| | | | | | | | | | | | | | | | | This adds support for ISA memory holes on the PCI, PCI-X and PCI-E busses of the 4xx platforms. The patch includes changes to the Bamboo and Canyonlands device-trees to add such a hole, others can be updated separately. The ISA memory hole is an additional outbound window configured in the bridge to generate PCI cycles in the low memory addresses, thus allowing to access things such as the hard-decoded VGA aperture at 0xa0000..0xbffff or other similar things. It's made accessible to userspace via the new legacy_mem file in sysfs for which support was added by a previous patch. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* Merge branch 'core-v28-for-linus' of ↵Linus Torvalds2008-10-161-10/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'core-v28-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: do_generic_file_read: s/EINTR/EIO/ if lock_page_killable() fails softirq, warning fix: correct a format to avoid a warning softirqs, debug: preemption check x86, pci-hotplug, calgary / rio: fix EBDA ioremap() IO resources, x86: ioremap sanity check to catch mapping requests exceeding, fix IO resources, x86: ioremap sanity check to catch mapping requests exceeding the BAR sizes softlockup: Documentation/sysctl/kernel.txt: fix softlockup_thresh description dmi scan: warn about too early calls to dmi_check_system() generic: redefine resource_size_t as phys_addr_t generic: make PFN_PHYS explicitly return phys_addr_t generic: add phys_addr_t for holding physical addresses softirq: allocate less vectors IO resources: fix/remove printk printk: robustify printk, update comment printk: robustify printk, fix #2 printk: robustify printk, fix printk: robustify printk Fixed up conflicts in: arch/powerpc/include/asm/types.h arch/powerpc/platforms/Kconfig.cputype manually.
| * generic: redefine resource_size_t as phys_addr_tJeremy Fitzhardinge2008-09-141-10/+6
| | | | | | | | | | | | | | | | There's no good reason why a resource_size_t shouldn't just be a physical address, so simply redefine it in terms of phys_addr_t. Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | powerpc/4xx: Allow 4xx PCI bridge to be disabled via device treeMatthias Fuchs2008-10-021-1/+8
| | | | | | | | | | | | | | | | | | | | | | This patch allows the 4xx (conventional) PCI bridge to be disabled via the device tree. This is needed for 4xx PCI adapter hardware. Use the PCI node's status property to disable the PCI bridge. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | powerpc/4xx: Necessary fixes to PCI for 4GB RAM sizeIlya Yanok2008-09-021-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The declaration of total_memory removed. Now including <mm/mmu_decl.h> instead. Since total_memory is a phys_addr_t which is 64-bit on 44x and is_power_of_2() works with u32 so I just inlined (size & (size-1)) != 0 instead. Also this patch fixes default initialization: res->end should be 0x7fffffff not 0x80000000. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* | powerpc/44x: AMCC PPC460GT/EX PCI-E de-emphasis adjustment fixTirumala R Marri2008-08-281-5/+5
|/ | | | | | | | | | | During recent tests with PCI-E , it has been found the DRV + De-Emphasis values are not optimum. These new values are tested thouroughly. Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Feng Kan fkan@amcc.com Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/4xx: Workaround for PPC440EPx/GRx PCI_28 ErrataJosh Boyer2008-06-171-0/+5
| | | | | | | | | | | | | | | | | | | | | | | The 440EPx/GRx chips don't support PCI MRM commands. Drivers determine this by looking for a zero value in the PCI cache line size register. However, some drivers write to this register upon initialization. This can cause MRMs to be used on these chips, which may cause deadlocks on PLB4. The workaround implemented here introduces a new indirect_type flag, called PPC_INDIRECT_TYPE_BROKEN_MRM. This is set in the pci_controller structure in the pci fixup function for 4xx PCI bridges by determining if the bridge is compatible with 440EPx/GRx. The flag is checked in the indirect_write_config function, and forces any writes to the PCI_CACHE_LINE_SIZE register to be zero, which will disable MRMs for these chips. A similar workaround has been tested by AMCC on various PCI cards, such as the Silicon Image ATA card and Intel E1000 GIGE card. Hangs were seen with the Silicon Image card, and MRMs were seen on the bus with a PCI analyzer. With the workaround in place, the card functioned properly and only Memory Reads were seen on the bus with the analyzer. Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* powerpc/4xx: PCIe driver now detects if a port is disabled via the dev-treeStefan Roese2008-06-111-0/+9
| | | | | | | | | | | | This patch add a check to the PPC4xx PCIe driver to detect if the port is disabled via the device-tree. This is needed for the AMCC Canyonlands board which has an option to either select 2 PCIe ports or 1 PCIe port and one SATA port. The SATA port and the 1st PCIe port pins are multiplexed so we can't start both drivers. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Add endpoint support to 4xx PCIe driverStefan Roese2008-05-061-49/+131
| | | | | | | | | | | | | | | This patch adds basic endpoint support to the 4xx PCIe driver. This is done by checking the device_type property of the PCIe device node ("pci" for root-complex and "pci-endpoint" for endpoint configuration). Note: Currently we map a fixed 64MByte window to PLB address 0 (SDRAM). This should probably be configurable via a dts property. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Fix PESDRn_UTLSET1 register setup on 460EX/GTStefan Roese2008-04-021-6/+4
| | | | | | | | | The patch fixes a bug, where the PESDRn_UTLSET1 register was setup wrongly resulting in a non working PCIe port 1. With this fix both PCIe ports work fine again. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Only reset PCIe PHY on 405EX systems when no link is detectedStefan Roese2008-04-021-8/+0
| | | | | | | | | | | Since the arch/powerpc PCI subsystem now does a complete re-assignment of the resources, we can move from the unconditional PCIe PHY reset to the conditional version. Now the PHY is only reset, if no link is established yet. An additional PHY reset (one is already done in U-Boot) leads to problems with some Atheros PCIe boards and some HP FPGA PCIe designs. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Use dcri_clrset() for PCIe indirect dcr read/modify/write accessValentine Barshak2008-03-261-8/+5
| | | | | | | Use dcri_clrset() for PCIe SDR0 read/modify/write access. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Add 460EX PCIe support to 4xx pci driverStefan Roese2008-03-261-0/+114
| | | | | | | | | | | | | | | | All this code is needed to properly initialize the 460EX PCIe host bridge(s). We re-initialize all ports again, even though this has been done in the bootloader (U-Boot) before. This way we make sure, that we always run the latest init code in Linux and don't depend on code versions from U-Boot. Unfortunately all IBM/AMCC chips currently supported in this PCIe driver need a different reset-/init-sequence. Tested on AMCC Canyonlands eval board. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: PCIe: Increase max busses per port to 64Stefan Roese2008-01-081-1/+1
| | | | | | | | | | | Because of how big mapping the config space is (1M per bus), we limit how many busses we support for now. In the long run, we could replace that with something akin to kmap_atomic instead. This patch changes the limit from currently 16 to 64. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Set ibpre for 405EX in 4xx PCIe driverStefan Roese2007-12-231-0/+2
| | | | | | | | This patch sets the ibpre flag (Inbound Presence) for the 405EX in the 4xx PCIe driver. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: Add 440SPe revA runtime detection to PCIeStefan Roese2007-12-231-8/+17
| | | | | | | | | | | | This patch adds runtime detection of the 440SPe revision A chips. These chips are equipped with a slighly different PCIe core and need special/ different initialization. The compatible node is changed to "plb-pciex-440spe" ("A" and "B" dropped). This is needed for boards that can be equipped with both PPC revisions like the AMCC Yucca. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: PCI-E Link setup improvementsBenjamin Herrenschmidt2007-12-231-89/+131
| | | | | | | | | | | | | | This improves the way the 4xx PCI-E code handles checking for a link and adds explicit testing of CRS result codes on config space accesses. This should make it more reliable. Also, bridges with no link are now still created, though config space accesses beyond the root complex are filtered. This is one step toward eventually supporting hotplug. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: PLB to PCI Express supportBenjamin Herrenschmidt2007-12-231-18/+976
| | | | | | | | | | | | | | | | | | | | | | | | | This adds to the previous 2 patches the support for the 4xx PCI Express cells as found in the 440SPe revA, revB and 405EX. Unfortunately, due to significant differences between these, and other interesting "features" of those pieces of HW, the code isn't as simple as it is for PCI and PCI-X and some of the functions differ significantly between the 3 implementations. Thus, not only this code can only support those 3 implementations for now and will refuse to operate on any other, but there are added ifdef's to avoid the bloat of building a fairly large amount of code on platforms that don't need it. Also, this code currently only supports fully initializing root complex nodes, not endpoint. Some more code will have to be lifted from the arch/ppc implementation to add the endpoint support, though it's mostly differences in memory mapping, and the question on how to represent endpoint mode PCI in the device-tree is thus open. Many thanks to Stefan Roese for testing & fixing up the 405EX bits ! Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: PLB to PCI 2.x supportBenjamin Herrenschmidt2007-12-231-1/+179
| | | | | | | | This adds to the previous patch the support for the 4xx PCI 2.x bridges. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* [POWERPC] 4xx: PLB to PCI-X supportBenjamin Herrenschmidt2007-12-231-0/+339
This adds base support code for the 4xx PCI-X bridge. It also provides placeholders for the PCI and PCI-E version but they aren't supported with this patch. The bridges are configured based on device-tree properties. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>