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* sched: zap the migration init / cache-hot balancing codeIngo Molnar2007-07-091-27/+0
| | | | | | | | | | | | | | | | | | | | | | the SMP load-balancer uses the boot-time migration-cost estimation code to attempt to improve the quality of balancing. The reason for this code is that the discrete priority queues do not preserve the order of scheduling accurately, so the load-balancer skips tasks that were running on a CPU 'recently'. this code is fundamental fragile: the boot-time migration cost detector doesnt really work on systems that had large L3 caches, it caused boot delays on large systems and the whole cache-hot concept made the balancing code pretty undeterministic as well. (and hey, i wrote most of it, so i can say it out loud that it sucks ;-) under CFS the same purpose of cache affinity can be achieved without any special cache-hot special-case: tasks are sorted in the 'timeline' tree and the SMP balancer picks tasks from the left side of the tree, thus the most cache-cold task is balanced automatically. Signed-off-by: Ingo Molnar <mingo@elte.hu>
* [SPARC64]: Need to set state to IDLE during sun4v IRQ enable.David S. Miller2007-06-261-0/+4
| | | | | | This fixes hypervisor console interrupts on LDOM guests. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix VIRQ enabling.David S. Miller2007-06-261-1/+7
| | | | | | | We were doing the wrong call to turn them on, and also when enabling we need to forcefully set the state to IDLE. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix args to sun4v_ldc_revoke().David S. Miller2007-06-131-2/+3
| | | | | | | First argument is LDC channel ID, then mapping cookie, then the MTE revoke cookie. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix IO/MEM space sizing for PCI.David S. Miller2007-06-131-3/+9
| | | | | | | | | | In pci_determine_mem_io_space(), do not hard code the region sizes. Instead, use the values given to us in the ranges property. Thanks goes to Mikael Petterson for the original Xorg failure bug repoert, and strace dumps from Mikael and Dmitry Artamonow. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Wire up cookie based sun4v interrupt registry.David S. Miller2007-06-131-9/+122
| | | | | | This will be used for logical domain channel interrupts. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Handle PCI bridges without 'ranges' property.David S. Miller2007-06-072-13/+103
| | | | | | | | | | | | | | | | | | | | | | | This fixes the IDE controller not showing up on Netra-T1 systems. Just like Simba bridges, some PCI bridges can lack the 'ranges' OBP property. So we handle this similarly to the existing Simba code: 1) In of_device register address resolving, we push the translation to the parent. 2) In PCI device scanning, we interrogate the PCI config space registers of the PCI bus device in order to resolve the resources, just like the generic Linux PCI probing code does. With much help and testing from Fabio, who also reported the initial problem. Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Fabio Massimo Di Nitto <fabbione@ubuntu.com>
* [SPARC64]: Include <linux/rwsem.h> instead of <asm/rwsem.h>.Robert P. J. Day2007-06-071-1/+1
| | | | | | | | To be consistent with other architectures, include the generic version of rwsem.h. Signed-off-by: Robert P. J. Day <rpjday@mindspring.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix SBUS IRQ regression caused by PCI-E driver.David S. Miller2007-06-072-54/+54
| | | | | | | | | | | | | We used to access the 64-bit IRQ IMAP and ICLR registers of bus controllers 4-bytes in and as a 32-bit register word, since only the low 32-bits were relevant. This seemed like a good idea at the time. But the PCI-E controller requires full 8-byte 64-bit access to these registers, so we switched over to accessing them fully. SBUS was not adjusted properly, which broke interrupts completely. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix 2 bugs in PCI Sabre bus scanning.David S. Miller2007-06-071-6/+11
| | | | | | | | | If we are on hummingbird, bus runs at 66MHZ. pbm->pci_bus should be setup with the result of pci_scan_one_pbm() or else we deref NULL pointers in the error interrupt handlers. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix {mc,smt}_capable().David S. Miller2007-06-043-0/+9
| | | | | | | It's not just sun4v hypervisor platforms that should return true for this, sun4u with UltraSPARC-IV should return true too. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Make core and sibling groups equal on UltraSPARC-IV.David S. Miller2007-06-041-1/+2
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Proper multi-core scheduling support.David S. Miller2007-06-044-1/+77
| | | | | | | | | | The scheduling domain hierarchy is: all cpus --> cpus that share an instruction cache --> cpus that share an integer execution unit Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Provide mmu statistics via sysfs.David Miller2007-06-042-15/+222
| | | | | | | | | | | | | | | If the system supports hypervisor based statistics, allow them to be fetched, enabled, and disabled via sysfs. Enable and disable via the boolean: /sys/devices/systems/cpu/cpuN/mmustat_enable Statistic values are provided under: /sys/devices/systems/cpu/cpuN/mmu_status/ Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Fix service channel hypervisor function names.David Miller2007-06-041-20/+20
| | | | | | sed 's/scv/svc/' Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Export basic cpu properties via sysfs.David S. Miller2007-06-041-0/+86
| | | | | | Cache sizes, udelay_val, and clock_tick. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Move topology init code into new file, sysfs.cDavid S. Miller2007-06-043-21/+28
| | | | | | | Also, use per-cpu data for struct cpu. Calling kmalloc for each cpu in topology_init() is just plain clumsy. Signed-off-by: David S. Miller <davem@davemloft.net>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild-fixLinus Torvalds2007-05-311-5/+6
|\ | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild-fix: sparc64: fix alignment bug in linker definition script
| * sparc64: fix alignment bug in linker definition scriptSam Ravnborg2007-05-291-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RO_DATA section were hardcoded to a specific alignment in include/asm-generic/vmlinux.h. But for sparc64 this did not match the PAGE_SIZE. Introduce a new section definition named: RO_DATA that takes actual alignment as parameter. RODATA are provided for backward compatibility. On top of this avoid hardcoding alignment for sparc64 in reset of the script Fix is build-tested on sparc64 + x86_64. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
* | [SPARC64]: Add missing NCS and SVC hypervisor interfaces.David S. Miller2007-05-311-0/+72
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* | [SPARC64]: Fill holes in hypervisor APIs and fix KTSB registry.David S. Miller2007-05-293-60/+567
| | | | | | | | | | | | | | | | | | | | | | Several interfaces were missing and others misnumbered or improperly documented. Also, make sure to check the return value when registering the kernel TSBs with the hypervisor. This helped to find the 4MB kernel TSB alignment bug fixed in a previous changeset. Signed-off-by: David S. Miller <davem@davemloft.net>
* | [SPARC64]: Fix two bugs wrt. kernel 4MB TSB.David S. Miller2007-05-292-6/+30
| | | | | | | | | | | | | | | | | | | | | | | | 1) The TSB lookup was not using the correct hash mask. 2) It was not aligned on a boundary equal to it's size, which is required by the sun4v Hypervisor. wasn't having it's return value checked, and that bug will be fixed up as well in a subsequent changeset. Signed-off-by: David S. Miller <davem@davemloft.net>
* | [SPARC64]: Fix _PAGE_EXEC_4U check in sun4u I-TLB miss handler.David S. Miller2007-05-291-2/+2
| | | | | | | | | | | | | | | | | | | | It was using an immediate _PAGE_EXEC_4U value in an 'and' instruction to perform the test. This doesn't work because the immediate field is signed 13-bit, this the mask being tested against the PTE was 0x1000 sign-extended to 32-bits instead of just plain 0x1000. Signed-off-by: David S. Miller <davem@davemloft.net>
* | [SPARC64]: arch/sparc64/time.c doesn't compile on Ultra 1 (no PCI)Horst H. von Brand2007-05-291-0/+6
| | | | | | | | | | | | | | | | | | | | This is bug 8540 on bugzilla.kernel.org arch/sparc64/time.c contains references to assorted bq4802 stuff if CONFIG_PCI is not set, and compile fails. I #ifdef'ed out everything that looks PCI-ish in that file. Signed-off-by: David S. Miller <davem@davemloft.net>
* | [SPARC64]: Eliminate NR_CPUS limitations.David S. Miller2007-05-294-11/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cheetah systems can have cpuids as large as 1023, although physical systems don't have that many cpus. Only three limitations existed in the kernel preventing arbitrary NR_CPUS values: 1) dcache dirty cpu state stored in page->flags on D-cache aliasing platforms. With some build time calculations and some build-time BUG checks on page->flags layout, this one was easily solved. 2) The cheetah XCALL delivery code could only handle a cpumask with up to 32 cpus set. Some simple looping logic clears that up too. 3) thread_info->cpu was a u8, easily changed to a u16. There are a few spots in the kernel that still put NR_CPUS sized arrays on the kernel stack, but that's not a sparc64 specific problem. Signed-off-by: David S. Miller <davem@davemloft.net>
* | [SPARC64]: Use machine description and OBP properly for cpu probing.David S. Miller2007-05-2913-380/+923
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* | [SPARC64]: Negotiate hypervisor API for PCI services.David S. Miller2007-05-291-0/+18
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* | [SPARC64]: Report proper system soft state to the hypervisor.David S. Miller2007-05-298-1/+148
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* | [SPARC64]: Fix typo in sun4v_hvapi_register error handling.David S. Miller2007-05-291-1/+1
| | | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* | [SPARC64]: PCI device scan is way too verbose by default.David S. Miller2007-05-291-14/+40
| | | | | | | | | | | | | | | | | | | | | | These messages were very useful when bringing up the OBP based PCI device scan code, but it's just a lot of noise every bootup now especially on big machines. The messages can be re-enabled via 'ofpci_debug=1' on the kernel command line. Signed-off-by: David S. Miller <davem@davemloft.net>
* | [SPARC64]: Don't be picky about virtual-dma values on sun4v.David S. Miller2007-05-291-26/+10
|/ | | | | | | | | Handle arbitrary base and length values as long as they are multiples of IO_PAGE_SIZE. Bug found by Arun Kumar Rao. Signed-off-by: David S. Miller <davem@davemloft.net>
* all-archs: consolidate .data section definition in asm-genericSam Ravnborg2007-05-191-1/+1
| | | | | | | With this consolidation we can now modify the .data section definition in one spot for all archs. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
* all-archs: consolidate .text section definition in asm-genericSam Ravnborg2007-05-191-1/+1
| | | | | | Move definition of .text section to asm-generic. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
* [SPARC64]: Fix sched_clock() et al.David S. Miller2007-05-171-1/+1
| | | | | | SPARC64_NSEC_PER_CYC_SHIFT was set too high. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add hypervisor API negotiation and fix console bugs.David S. Miller2007-05-154-1/+287
| | | | | | | | | | | | | | | | | | | | | | | Hypervisor interfaces need to be negotiated in order to use some API calls reliably. So add a small set of interfaces to request API versions and query current settings. This allows us to fix some bugs in the hypervisor console: 1) If we can negotiate API group CORE of at least major 1 minor 1 we can use con_read and con_write which can improve console performance quite a bit. 2) When we do a console write request, we should hold the spinlock around the whole request, not a byte at a time. What would happen is that it's easy for output from different cpus to get mixed with each other. 3) Use consistent udelay() based polling, udelay(1) each loop with a limit of 1000 polls to handle stuck hypervisor console. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Update defconfig.David S. Miller2007-05-141-22/+4
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add missing cpus_empty() check in hypervisor xcall handling.David S. Miller2007-05-141-0/+3
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Be more resiliant with PCI I/O space regs.David S. Miller2007-05-131-0/+7
| | | | | | | If we miss on the ranges, just toss the translation up to the parent instead of failing. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC]: Wire up signalfd/timerfd/eventfd syscalls.David S. Miller2007-05-111-3/+4
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Add support for bq4802 TOD chip, as found on ultra45.David S. Miller2007-05-111-20/+210
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Correct FIRE_IOMMU_FLUSHINV register offset.David S. Miller2007-05-111-1/+1
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Update defconfig.David S. Miller2007-05-111-8/+10
| | | | Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: pci_resource_adjust() cannot be __init.David S. Miller2007-05-111-2/+2
| | | | | | Noticed by Meelis Roos. Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Spelling fixes.Simon Arlott2007-05-117-8/+8
| | | | | | | Spelling fixes in arch/sparc64/. Signed-off-by: Simon Arlott <simon@fire.lp0.eu> Signed-off-by: David S. Miller <davem@davemloft.net>
* [SPARC64]: Kill LARGE_ALLOCS and update defconfig.David S. Miller2007-05-112-61/+52
| | | | | | | Let's use SLUB, since it works now, in order to get it tested a bit. Signed-off-by: David S. Miller <davem@davemloft.net>
* [PATCH] audit signal recipientsAmy Griffis2007-05-111-0/+9
| | | | | | | | | | | | | When auditing syscalls that send signals, log the pid and security context for each target process. Optimize the data collection by adding a counter for signal-related rules, and avoiding allocating an aux struct unless we have more than one target process. For process groups, collect pid/context data in blocks of 16. Move the audit_signal_info() hook up in check_kill_permission() so we audit attempts where permission is denied. Signed-off-by: Amy Griffis <amy.griffis@hp.com> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* [PATCH] add SIGNAL syscall class (v3)Amy Griffis2007-05-112-0/+13
| | | | | | | Add a syscall class for sending signals. Signed-off-by: Amy Griffis <amy.griffis@hp.com> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6Linus Torvalds2007-05-109-745/+226
|\ | | | | | | | | | | | | | | | | * master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6: [SPARC64]: Use alloc_pci_dev() in PCI bus probes. [SPARC64]: Bump PROMINTR_MAX to 32. [SPARC64]: Fix recursion in PROM tree building. [SERIAL] sunzilog: Interrupt enable before ISR handler installed [SPARC64] PCI: Consolidate PCI access code into pci_common.c
| * [SPARC64]: Use alloc_pci_dev() in PCI bus probes.David S. Miller2007-05-101-1/+1
| | | | | | | | | | | | | | Otherwise MSI explodes because pci_msi_init_pci_dev() does not get invoked. Signed-off-by: David S. Miller <davem@davemloft.net>
| * [SPARC64]: Fix recursion in PROM tree building.David S. Miller2007-05-101-4/+15
| | | | | | | | | | | | | | | | Use iteration for scanning of PROM node siblings. Based upon a patch by Greg Onufer, who found this bug. Signed-off-by: David S. Miller <davem@davemloft.net>
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