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* | | x86: clean up init_amd()Yinghai Lu2008-07-081-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. move out calling of check_enable_amd_mmconf_dmi out of setup_64.c put it into init_amd(), so don't need to make extra dmi check for system with other cpus. 2. 15 --> 0xf Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* | | Merge branch 'x86/nmi' into x86/develIngo Molnar2008-07-081-1/+3
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/x86/kernel/nmi.c arch/x86/kernel/nmi_32.c Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * \ \ Merge branch 'linus' into x86/nmiIngo Molnar2008-06-162-3/+14
| |\ \ \ | | | |/ | | |/| | | | | | | | | | | | | Conflicts: arch/x86/kernel/nmi_32.c
| * | | x86: watchdog - check for CPU is being supportedCyrill Gorcunov2008-06-051-1/+3
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does check if CPU is being recongnized before call the unreserve(). Since enable_lapic_nmi_watchdog() does have such a check the same is make sense here too in a sake of code consistency (but nothing more). Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com> Cc: mingo@redhat.com Cc: hpa@zytor.com Cc: macro@linux-mips.org Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* | | Merge branch 'x86/mpparse' into x86/develIngo Molnar2008-07-083-32/+910
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/x86/Kconfig arch/x86/kernel/io_apic_32.c arch/x86/kernel/setup_64.c arch/x86/mm/init_32.c Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | x86: rename two e820 related functionsYinghai Lu2008-07-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | rename update_memory_range to e820_update_range rename add_memory_region to e820_add_region to make it more clear that they are about e820 map operations. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | Merge branch 'linus' into tmp.x86.mpparse.newIngo Molnar2008-07-082-3/+14
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| * | | x86: mtrr cleanup for converting continuous to discrete layout - fix #2Yinghai Lu2008-05-251-31/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | disable the noisy print out. also use the one the less spare mtrr reg. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | x86: amd opteron TOM2 mask val fixYinghai Lu2008-05-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | there is a typo in the mask value, need to remove that extra 0, to avoid 4bit clearing. Signed-off-by: Yinghal Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | x86: process fam 10h like k8 with fixed mtrr settingYinghai Lu2008-05-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | otherwise fixed MTRR for family 10h may not be changed. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | | x86: mtrr cleanup for converting continuous to discrete - auto detect v4Yinghai Lu2008-05-251-146/+464
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loop through mtrr chunk_size and gran_size from 1M to 2G to find out the optimal value so user does not need to add mtrr_chunk_size and mtrr_gran_size to the kernel command line. If optimal value is not found, print out all list to help select less optimal value. Add mtrr_spare_reg_nr= so user could set 2 instead of 1, if the card need more entries. v2: find the one with more spare entries v3: fix hole_basek offset v4: tight the compare between range and range_new loop stop with 4g Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Gabriel C <nix.or.die@googlemail.com> Cc: Mika Fischer <mika.fischer@zoopnet.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | x86: mtrr cleanup for converting continuous to discrete layout v8 - fixYinghai Lu2008-05-251-74/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v9: address format change requests by Ingo more case handling in range_to_var_with_hole Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | | x86: fix trimming e820 with MTRR holes. - fixYinghai Lu2008-05-251-29/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2: process hole then end_pfn fix update_memory_range with whole cover comparing Signed-off-by: Yinghai Lu <yinghai.lu@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | | x86: fix trimming e820 with MTRR holes.Yinghai Lu2008-05-251-17/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | converting MTRR layout from continous to discrete, some time could run out of MTRRs. So add gran_sizek to prevent that by dumpping small RAM piece less than gran_sizek. previous trimming only can handle highest_pfn from mtrr to end_pfn from e820. when have more than 4g RAM installed, there will be holes below 4g. so need to check ram below 4g is coverred well. need to be applied after [PATCH] x86: mtrr cleanup for converting continuous to discrete layout v7 Signed-off-by: Yinghai Lu <yinghai.lu@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | | x86: mtrr cleanup for converting continuous to discrete layout, v8Yinghai Lu2008-05-253-14/+488
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | some BIOS like to use continus MTRR layout, and X driver can not add WB entries for graphical cards when 4g or more RAM installed. the patch will change MTRR to discrete. mtrr_chunk_size= could be used to have smaller continuous block to hold holes. default is 256m, could be set according to size of graphics card memory. mtrr_gran_size= could be used to send smallest mtrr block to avoid run out of MTRRs v2: fix -1 for UC checking v3: default to disable, and need use enable_mtrr_cleanup to enable this feature skip the var state change warning. remove next_basek in range_to_mtrr() v4: correct warning mask. v5: CONFIG_MTRR_SANITIZER v6: fix 1g, 2g, 512 aligment with extra hole v7: gran_sizek to prevent running out of MTRRs. v8: fix hole_basek caculation caused when removing next_basek gran_sizek using when basek is 0. need to apply [PATCH] x86: fix trimming e820 with MTRR holes. right after this one. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | | x86: fix sparse warning in mtrr/generic.cThomas Gleixner2008-05-251-4/+4
| | |/ | |/| | | | | | | | | | | | | | | | | | | arch/x86/kernel/cpu/mtrr/generic.c:216:12: warning: symbol 'lo' shadows an earlier one Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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*---------. \ \ Merge branches 'x86/numa-fixes', 'x86/apic', 'x86/apm', 'x86/bitops', ↵Ingo Molnar2008-07-0816-154/+543
|\ \ \ \ \ \ \ \ | |_|_|_|_|_|/ / |/| | | | | | / | | |_|_|_|_|/ | |/| | | | | 'x86/build', 'x86/cleanups', 'x86/cpa', 'x86/cpu', 'x86/defconfig', 'x86/gart', 'x86/i8259', 'x86/intel', 'x86/irqstats', 'x86/kconfig', 'x86/ldt', 'x86/mce', 'x86/memtest', 'x86/pat', 'x86/ptemask', 'x86/resumetrace', 'x86/threadinfo', 'x86/timers', 'x86/vdso' and 'x86/xen' into x86/devel
| | | | | | * Merge branch 'linus' into x86/patIngo Molnar2008-06-162-3/+14
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| | | | | | * x86: PAT: fixed checkpatch errors (and whitespaces)Andreas Herrmann2008-06-121-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | x86: PAT: fixed checkpatch errors (and whitespaces) Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | | | | | * x86: PAT: fix ambiguous paranoia check in pat_init()Andreas Herrmann2008-06-121-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Starting with commit 8d4a4300854f3971502e81dacd930704cb88f606 (x86: cleanup PAT cpu validation) the PAT CPU feature flag is not cleared anymore. Now the error message "PAT enabled, but CPU feature cleared" in pat_init() is misleading. Furthermore the current code does not check for existence of the PAT CPU feature flag if a CPU is whitelisted in validate_pat_support. This patch clears pat_wc_enabled if boot CPU has no PAT feature flag and adapts the paranoia check. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | | | | | * x86: unconditionally enable PAT for AMD CPUsAndreas Herrmann2008-06-121-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If PAT support is advertised it should just work. No errata known. Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | | | | | * x86: Add Centaur and Transmeta CPUs to PAT whitelistDave Jones2008-05-221-0/+3
| |_|_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unconditionally enable PAT support on Centaur and Transmeta CPUs. All known models that advertise PAT have no known errata. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
| | | | | * x86, mce_64.c: mce_cpu_quirks being ignoredVenki Pallipadi2008-07-031-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Quirks getting ignored was a bug. Below patch fixes the bug, until we have the dynamic banks support. Sysfs choice configuration should not have any issues with the earlier patch as we look for NR_SYSFS_BANKS in do_machine_check(). Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Cc: Andi Kleen <andi@firstfloor.org> Cc: Max Asbock <masbock@us.ibm.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | | | | * Merge commit 'v2.6.26-rc8' into x86/mceIngo Molnar2008-07-032-3/+14
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| | | | | * x86: correctly report NR_BANKS in mce_64.cDaniel Rahn2008-06-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | attached is a no-brainer that makes kernel correctly report NR_BANKS for MCE. We are right now limited to NR_BANKS==6, but the error message will use the available number of banks instead of the defined maximum. For a Nehalem based system it will print: "MCE: warning: using only 9 banks" while the correct message would be "MCE: warning: using only 6 banks" Signed-off-by: Pavel Machek <pavel@suse.cz> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | | | | * x86: remove 6 bank limitation in 64 bit MCE reporting codeVenki Pallipadi2008-05-121-8/+12
| |_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Eliminate the 6 bank restriction in 64 bit mce reporting code. This restriction is artificial (due to static creation of sysfs files) and 32 bit code does not have any such restriction. This change helps in reporting the details of machine checks on a machine check exception with errors in bank 6 and above on CPUs that support those banks. Without the patch, machine check errors in those banks are not reported. We still have 128 (MCE_EXTENDED_BANK) bank restriction instead of max 256 supported in hardware. That is not changed in the patch below as it will have some user level mcelog utility dependency, with bank 128 being used for thermal reporting currently. The patch below does not create sysfs control (bankNctl) for banks higher than 6 as well. That needs some pre-cleanup in /sysfs mce layout, removal of per cpu /sysfs entries for bankctl as they are really global system level control today. That change will follow. This basic change is critical to report the detailed errors on banks higher than 6. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | | | * x86: add new cache descriptorDave Jones2008-05-121-0/+1
| |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The latest rev of Intel doc AP-485 details a new cache descriptor that we don't yet support. A 6MB 24-way assoc L2 cache. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| | | * x86: make 64-bit identify_cpu use cpu_devYinghai Lu2008-07-084-10/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | we may need to move some functions to common.c later Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | | * x86: Move PCI IO ECS code to x86/pciRobert Richter2008-07-083-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | "Form follows function". Code is now where it belongs to. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | | * x86, clockevents: add C1E aware idle functionThomas Gleixner2008-07-082-55/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | C1E on AMD machines is like C3 but without control from the OS. Up to now we disabled the local apic timer for those machines as it stops when the CPU goes into C1E. This excludes those machines from high resolution timers / dynamic ticks, which hurts especially X2 based laptops. The current boot time C1E detection has another, more serious flaw as well: some BIOSes do not enable C1E until the ACPI processor module is loaded. This causes systems to stop working after that point. To work nicely with C1E enabled machines we use a separate idle function, which checks on idle entry whether C1E was enabled in the Interrupt Pending Message MSR. This allows us to do timer broadcasting for C1E and covers the late enablement of C1E as well. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | | * x86: use cpuinfo to check for interrupt pending message msrThomas Gleixner2008-06-102-49/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify code: no need to do a cpuid(1) again. The cpuinfo structure has all necessary information already. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | | * x86: cleanup C1E enabled detectionThomas Gleixner2008-06-102-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename the "MSR_K8_ENABLE_C1E" MSR to INT_PENDING_MSG, which is the name in the data sheet as well. Move the C1E mask to the header file. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | | * fix build bug in "x86: add PCI extended config space access for AMD Barcelona"Robert Richter2008-06-103-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Also much less code now. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | | * x86: move bugs_64.c to cpu/bugs_64.cHiroshi Shimamoto2008-06-032-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It looks good to move bugs_64.c to cpu/bugs_64.c. Signed-off-by: Hiroshi Shimamoto <h-shimamoto@ct.jp.nec.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
| | | * fix build bug in "x86: add PCI extended config space access for AMD Barcelona"Ingo Molnar2008-06-021-0/+1
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| | | * x86: add PCI extended config space access for AMD BarcelonaRobert Richter2008-06-022-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements PCI extended configuration space access for AMD's Barcelona CPUs. It extends the method using CF8/CFC IO addresses. An x86 capability bit has been introduced that is set for CPUs supporting PCI extended config space accesses. Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | | * x86: fix overlong line in arch/x86/kernel/cpu/amd_64.cH. Peter Anvin2008-05-301-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Clean up an overlong line in arch/x86/kernel/cpu/amd_64.c. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
| | | * x86: Move the 64-bit Centaur specific parts out of setup_64.cDave Jones2008-05-302-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a separate centaur_64.c file in the cpu/ dir for the useful parts to live in. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
| | | * x86: Remove workaround for prescott (32bit P4) from 64-bit code.Dave Jones2008-05-301-5/+0
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
| | | * x86: Move the 64-bit Intel specific parts out of setup_64.cDave Jones2008-05-302-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a separate intel_64.c file in the cpu/ dir for the useful parts to live in. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
| | | * x86: Move the AMD64 specific parts out of setup_64.cDave Jones2008-05-302-0/+236
| | |/ | |/| | | | | | | | | | | | | | | | | | | Create a separate amd_64.c file in the cpu/ dir for the useful parts to live in. Signed-off-by: Dave Jones <davej@redhat.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
| | * x86: coding style fixes to x86/kernel/cpu/cpufreq/cpufreq-nforce2.cPaolo Ciarrocchi2008-06-181-21/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: total: 22 errors, 8 warnings, 440 lines checked After: total: 0 errors, 8 warnings, 442 lines checked paolo@paolo-desktop:~/linux.trees.git$ md5sum /tmp/cpufreq-nforce2.o.* 3d4330a5d188fe904446e5948a618b48 /tmp/cpufreq-nforce2.o.after 1477e6b0dcd6f59b1fb6b4490042eca6 /tmp/cpufreq-nforce2.o.before ^^^ I guess this is because I fixed a few "do not initialise statics to 0 or NULL" paolo@paolo-desktop:~/linux.trees.git$ size /tmp/cpufreq-nforce2.o.* text data bss dec hex filename 1923 72 16 2011 7db /tmp/cpufreq-nforce2.o.after 1923 72 16 2011 7db /tmp/cpufreq-nforce2.o.before Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | * x86: coding style fixes to arch/x86/kernel/cpu/mcheck/k7.cPaolo Ciarrocchi2008-06-181-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: total: 6 errors, 13 warnings, 105 lines checked After: total: 0 errors, 0 warnings, 105 lines checked paolo@paolo-desktop:~/linux.trees.git$ size /tmp/k7* text data bss dec hex filename 1135 0 0 1135 46f /tmp/k7.o.after 1135 0 0 1135 46f /tmp/k7.o.before paolo@paolo-desktop:~/linux.trees.git$ md5sum /tmp/k7* 87b14954045aa37dbaee6fb7e022ed9a /tmp/k7.o.after 87b14954045aa37dbaee6fb7e022ed9a /tmp/k7.o.before Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | * x86: coding style fixes to arch/x86/kernel/cpu/mcheck/p4.cPaolo Ciarrocchi2008-06-181-45/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: total: 16 errors, 34 warnings, 257 lines checked After: total: 0 errors, 2 warnings, 257 lines checked No changes in the compiled code: paolo@paolo-desktop:~/linux.trees.git$ size /tmp/p4* text data bss dec hex filename 2644 4 4 2652 a5c /tmp/p4.o.after 2644 4 4 2652 a5c /tmp/p4.o.before paolo@paolo-desktop:~/linux.trees.git$ md5sum /tmp/p4* 13f1b21c4246b31a28aaff38184586ca /tmp/p4.o.after 13f1b21c4246b31a28aaff38184586ca /tmp/p4.o.before Signed-off-by: Paolo Ciarrocchi <paolo.ciarrocchi@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| | * Merge branch 'linus' into x86/cleanupsIngo Molnar2008-06-162-3/+14
| | |\ | | |/ | |/|
| | * x86: janitor work in bugs.cMiklos Vajna2008-05-251-8/+19
| |/ |/| | | | | | | | | | | | | Just moved trailing statements to the next line, removed space before open/close parenthesis, wrapped long lines. Signed-off-by: Miklos Vajna <vmiklos@frugalware.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * [CPUFREQ] Crusoe: longrun cpufreq module reports false min freqmaximilian attems2008-05-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The longrun cpufreq module reports a false minimum frequency 3MHz on 300-600MHz Crusoe processor. This may be due to a calculation bug in the module. Original patch from Kaz Sasayama <kazssym@hypercore.co.jp> submitted as http://bugs.debian.org/468149 patch ported to x86 Cc: Kaz Sasayama <kazssym@hypercore.co.jp> Signed-off-by: maximilian attems <max@stro.at> Signed-off-by: Dave Jones <davej@redhat.com>
| * [CPUFREQ] powernow-k8: improve error messagesMark Langsdorf2008-05-191-2/+13
|/ | | | | | | | | | | | | | | | The most common error with powernow-k8 is an ACPI _PSS error caused either by failure to load the ACPI processor module or a bad parse of the _PSS object. Make the error message returned to the user in these situations more straightforward and easier to understand. -Mark Langsdorf Operating System Research Center AMD Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com> Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com> Signed-off-by: Dave Jones <davej@redhat.com>
* x86: cleanup PAT cpu validationThomas Gleixner2008-05-082-25/+23
| | | | | | | | | | | | | | | | | | | | | | | | Move the scattered checks for PAT support to a single function. Its moved to addon_cpuid_features.c as this file is shared between 32 and 64 bit. Remove the manipulation of the PAT feature bit and just disable PAT in the PAT layer, based on the PAT bit provided by the CPU and the current CPU version/model white list. Change the boot CPU check so it works on Voyager somewhere in the future as well :) Also panic, when a secondary has PAT disabled but the primary one has alrady switched to PAT. We have no way to undo that. The white list is kept for now to ensure that we can rely on known to work CPU types and concentrate on the software induced problems instead of fighthing CPU erratas and subtle wreckage caused by not yet verified CPUs. Once the PAT code has stabilized enough, we can remove the white list and open the can of worms. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
* Merge branch 'for-linus' of ↵Linus Torvalds2008-04-291-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86-fixes * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86-fixes: x86: fix PCI MSI breaks when booting with nosmp x86: vget_cycles() __always_inline x86: add more boot protocol documentation bootprotocol: cleanup x86: fix warning in "x86: clean up vSMP detection" x86: !x & y typo in mtrr code
generated by cgit v1.1 at 2025-01-23 05:15:07 +0000