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| * | | MIPS: Loongson: Define rtc device on MC146818-equipped systemsArnaud Patard2010-07-053-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch declare the rtc device present on systems with clock compatible with the mc146818 and handled by rtc-cmos. Introduce a new Kconfig entry because there are some systems without rtc_cmos compatible clock. Signed-off-by: Arnaud Patard <apatard@mandriva.com> To: linux-mips@linux-mips.org Cc: aba@not.so.argh.org Patchwork: http://patchwork.linux-mips.org/patch/1320/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: MT: Fix FPU affinity.Ralf Baechle2010-07-051-26/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fragile MT sys_sched_setaffinity wrapper needs its regular dose of fixes. Nose-poked-at-pile-o-crap-by: Julia Lawall <julia@diku.dk> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Oprofile: Fixup of loongson2_exit()Wu Zhangjin2010-07-051-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When exiting from loongson2_exit(), we need to reset the counter register too, this patch adds a function reset_counters() to do it, by the way, this function will be shared by Perf. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1199/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Alchemy: sleepcode without compile-time cputype dependenciesManuel Lauss2010-07-053-32/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split the low-level sleepcode into per-cpu functions instead of relying on compile-time-defined cpu type. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1281/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Tracing: Cleanup of address space checkingWu Zhangjin2010-07-051-3/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds an inline function in_module() to check which space the instruction pointer in, kernel space or module space. Note: This will not work when the kernel space and module space are the same. If they are the same, we need to modify scripts/recordmcount.pl, ftrace_make_nop/call() and the other related parts to ensure the enabling/disabling of the calling site to _mcount is right for both kernel and module. [Ralf: It also is still incorrect for some 64-bit kernels.] Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Cc: David Daney <david.s.daney@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/1232/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Tracing: Cleanup of function graph tracerWu Zhangjin2010-07-051-22/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cleans up comments and ftrace_get_parent_addr() of function graph tracer. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Cc: David Daney <david.s.daney@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/1231/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Tracing: Reduce the overhead of dynamic Function TracerWu Zhangjin2010-07-051-44/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the help of uasm this patch encodes the instructions of the dynamic function tracer in ftrace_dyn_arch_init() when initializing it. As a result we can remove the dynamic encoding of instructions in ftrace_make_nop()/call(), ftrace_enable_ftrace_graph_caller() and remove the macro jump_insn_encode() and at last this reduce the overhead of dynamic Function Tracer. This also is cleaner. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Cc: David Daney <david.s.daney@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/1230/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Tracing: Cleanup of instructions usedWu Zhangjin2010-07-051-8/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds some cleanups of the instructions: o use macros instead of magic numbers o use macros instead of variables to reduce some overhead o add new macro for the jal instruction Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Cc: David Daney <david.s.daney@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/1229/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Tracing: Fix 32-bit support with -mmcount-ra-addressWu Zhangjin2010-07-051-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For 32-bit kernel the -mmcount-ra-address option of gcc 4.5 emits one extra instruction before calling to _mcount so we need to use a different "b 1f" for it. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Cc: David Daney <david.s.daney@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/1228/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Tracing: Fix argument passing of the 32bit support with gcc 4.5Wu Zhangjin2010-07-051-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As documented in the GCC 4.5 docs [1] -mmcount-ra-address uses register $12 to pass the stack offset of the return address to the _mcount function. On 64-bit kernels $12 is t0 but in 32-bit kernels it is t4 so we need to use $12 instead of t0 here to be correct for both kernel types. [1] GCC documentation: MIPS Options http://gcc.gnu.org/onlinedocs/gcc/MIPS-Options.html Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Cc: David Daney <david.s.daney@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/1227/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Tracing: Cleanup commentsWu Zhangjin2010-07-051-5/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Cc: David Daney <david.s.daney@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/1225/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Tracing: Cleanup the arguments passing of prepare_ftrace_returnWu Zhangjin2010-07-051-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Cc: David Daney <david.s.daney@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/1226/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Tracing: Merge adjacent #ifdefs with same condition.Wu Zhangjin2010-07-051-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips <linux-mips@linux-mips.org> Cc: David Daney <david.s.daney@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/1224/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: AR7, BCM63xx: fix gpio_to_irq() return valueYoichi Yuasa2010-07-052-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The return value of gpio_to_irq() is not a pointer but an integer. Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org> Cc: linux-mips <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1280/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Restore signalling NaN behaviour for abs.[sd]Chris Dearman2010-07-052-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Atsushi Nemoto <anemo@mba.ocn.ne.jp> spotted that this had been incorrectly removed in a previous patch Signed-off-by: Chris Dearman <chris@mips.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1213/ Tested-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Loongson: CS5536: Fix ISA supportWu Zhangjin2010-07-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function _wrmsr() called by divil_lbar_disable()/enable() should be called with the offset as the argument. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: Zhang Le <r0bertz@gentoo.org> Patchwork: http://patchwork.linux-mips.org/patch/1252/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Loongson: Add a missing break statement in CS5536 IDE codeWu Zhangjin2010-07-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: Zhang Le <r0bertz@gentoo.org> Cc: Hu Hongbing <huhb@lemote.com> Patchwork: http://patchwork.linux-mips.org/patch/1251/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: Loongson: CS5536: Add missing RDMSRs for IDE and USBWu Zhangjin2010-07-053-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add several missing RDMSRs for IDE and USB are missing to avoid the agressive modification of the high 32 bits of the MSR. Without this patch some usb devices may fail after printing "reset ehci host ....." when reading the partition information. Signed-off-by: Hu Hongbing <huhb@lemote.com> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Cc: Zhang Le <r0bertz@gentoo.org> Cc: Hu Hongbing <huhb@lemote.com> Patchwork: http://patchwork.linux-mips.org/patch/1250/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: AR7: Fix typo in ar7.hFlorian Fainelli2010-07-051-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes a typo on the AR7_RESET_PERIPHERAL define. Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1247/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | | MIPS: AR7: Use correct UART port typeFlorian Fainelli2010-07-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PORT_AR7 has the correct TRIG flag (UART_FCR_R_TRIG_00) as well as UART_CAP_AFE being set. This fixes UART on TNETD7300 revision 0x02, which would otherwise mangle some characters, no side effects on other revisions. Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1246/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | | | Merge master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2010-07-0419-52/+110
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/home/rmk/linux-2.6-arm: ARM: 6205/1: perf: ensure counter delta is treated as unsigned ARM: 6202/1: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards with L210/L220 ARM: 6201/1: RealView: Do not use outer_sync() on ARM11MPCore boards with L220 ARM: 6195/1: OMAP3: pmu: make CPU_HAS_PMU dependent on OMAP3_EMU ARM: 6194/1: change definition of cpu_relax() for ARM11MPCore ARM: 6193/1: RealView: Align the machine_desc.phys_io to 1MB section ARM: 6192/1: VExpress: Align the machine_desc.phys_io to 1MB section ARM: 6188/1: Add a config option for the ARM11MPCore DMA cache maintenance workaround ARM: 6187/1: The v6_dma_inv_range() function must preserve data on SMP ARM: 6186/1: Avoid the CONSISTENT_DMA_SIZE warning on noMMU builds ARM: mx3: mx31lilly: fix build error for !CONFIG_USB_ULPI [ARM] mmp: fix build failure due to IRQ_PMU depends on ARCH_PXA [ARM] pxa/mioa701: fix camera regression [ARM] pxa/z2: fix flash layout to final version [ARM] pxa/z2: fix missing include in battery driver [ARM] pxa: fix incorrect gpio type in udc_pxa2xx.h
| * | | | ARM: 6205/1: perf: ensure counter delta is treated as unsignedWill Deacon2010-07-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hardware performance counters on ARM are 32-bits wide but atomic64_t variables are used to represent counter data in the hw_perf_event structure. The armpmu_event_update function right-shifts a signed 64-bit delta variable and adds the result to the event count. This can lead to shifting in sign-bits if the MSB of the 32-bit counter value is set. This results in perf output such as: Performance counter stats for 'sleep 20': 18446744073460670464 cycles <-- 0xFFFFFFFFF12A6000 7783773 instructions # 0.000 IPC 465 context-switches 161 page-faults 1172393 branches 20.154242147 seconds time elapsed This patch ensures that the delta value is treated as unsigned so that the right shift sets the upper bits to zero. Cc: <stable@kernel.org> Acked-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 6202/1: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards with L210/L220Catalin Marinas2010-07-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RealView boards with certain revisions of the L210/L220 cache controller may have issues (hardware deadlock) with the mandatory barriers (DSB followed by an L2 cache sync) when ARM_DMA_MEM_BUFFERABLE is enabled. The patch disables ARM_DMA_MEM_BUFFERABLE for these boards. Tested-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | ARM: 6201/1: RealView: Do not use outer_sync() on ARM11MPCore boards with L220Catalin Marinas2010-07-022-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RealView boards with certain revisions of the L220 cache controller (ARM11* processors only) may have issues (hardware deadlock) with the recent changes to the mb() barrier implementation (DSB followed by an L2 cache sync). The patch redefines the RealView ARM11MPCore mandatory barriers without the outer_sync() call. Cc: <stable@kernel.org> Tested-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | Merge branch 'imx-for-2.6.35' of git://git.pengutronix.de/git/imx/linux-2.6Russell King2010-07-011-11/+22
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| | * | | | ARM: mx3: mx31lilly: fix build error for !CONFIG_USB_ULPIDaniel Mack2010-07-011-11/+22
| | | |/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arch/arm/mach-mx3/built-in.o: In function `mx31lilly_board_init': mach-kzm_arm11_01.c:(.init.text+0x674): undefined reference to `otg_ulpi_create' mach-kzm_arm11_01.c:(.init.text+0x68c): undefined reference to `otg_ulpi_create' mach-kzm_arm11_01.c:(.init.text+0x744): undefined reference to `mxc_ulpi_access_ops' make: *** [.tmp_vmlinux1] Error 1 Signed-off-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| * | | | Merge branch 'fix' of ↵Russell King2010-07-014-20/+15
| |\ \ \ \ | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
| | * | | | [ARM] mmp: fix build failure due to IRQ_PMU depends on ARCH_PXAJonathan Cameron2010-06-141-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PMU is not tested and enabled on MMP architecture at this moment, the device IRQ number, IRQ_PMU depends on ARCH_PXA. Build PMU only for ARCH_PXA. Signed-off-by: Jonathan Cameron <jic23@cam.ac.uk> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| | * | | | [ARM] pxa/mioa701: fix camera regressionRobert Jarzmik2010-06-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit a48c24a696f0d93c49f913b7818e9819612b1f4e, the camera is not working anymore. After the v4l2 migration, the mt9m111 camera board information was not passed to the i2c layer anymore, but stored for future use of v4l2 (through soc_camera). Because mioa701_i2c_devices[] was tagged as "__initdata", and because after the v4l2 migration, the new structure "iclink" references it, the mt9m111 driver is not probed anymore, as part of "iclink" is not valid (discarded after kernel init). Although there is not compilation error, nor runtime oops, this patch restores a working camera on the mioa701 board. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| | * | | | [ARM] pxa/z2: fix flash layout to final versionMarek Vasut2010-06-131-16/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes flash layout to it's final version. Also, I fixed the authorship information of this file as it's been totally reworked since Ken released his last version. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| | * | | | [ARM] pxa: fix incorrect gpio type in udc_pxa2xx.hSteve Bennett2010-06-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gpio must be int, not u16, otherwise -1 isn't recognised by gpio_is_valid(). Signed-off-by: Steve Bennett <steveb@workware.net.au> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * | | | | ARM: 6195/1: OMAP3: pmu: make CPU_HAS_PMU dependent on OMAP3_EMUWill Deacon2010-07-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPU performance event counters on v7 cores will only operate if either the NIDEN or DBGEN signals are driven high. For the OMAP3 platform, these signals are driven low by default but DBGEN can be asserted by selecting the OMAP3_EMU Kconfig option, which enables the virtual clock for hardware debugging peripherals. Acked-by: Jean Pihet <jpihet@mvista.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | ARM: 6194/1: change definition of cpu_relax() for ARM11MPCoreWill Deacon2010-07-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Linux expects that if a CPU modifies a memory location, then that modification will eventually become visible to other CPUs in the system. On an ARM11MPCore processor, loads are prioritised over stores so it is possible for a store operation to be postponed if a polling loop immediately follows it. If the variable being polled indirectly depends on the outstanding store [for example, another CPU may be polling the variable that is pending modification] then there is the potential for deadlock if interrupts are disabled. This deadlock occurs in the KGDB testsuire when executing on an SMP ARM11MPCore configuration. This patch changes the definition of cpu_relax() to smp_mb() for ARMv6 cores, forcing a flushing of the write buffer on SMP systems before the next load takes place. If the Kernel is not compiled for SMP support, this will expand to a barrier() as before. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | ARM: 6193/1: RealView: Align the machine_desc.phys_io to 1MB sectionCatalin Marinas2010-07-015-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When not aligned, random bits could be written in the initial page table by the __create_page_tables() function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | ARM: 6192/1: VExpress: Align the machine_desc.phys_io to 1MB sectionCatalin Marinas2010-07-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When not aligned, random bits could be written in the initial page table by the __create_page_tables() function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | ARM: 6188/1: Add a config option for the ARM11MPCore DMA cache maintenance ↵Catalin Marinas2010-07-012-3/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | workaround Commit f4d6477f introduced a workaround for the lack of hardware broadcasting of the cache maintenance operations on ARM11MPCore. However, the workaround is only valid on CPUs that do not do speculative loads into the D-cache. This patch adds a Kconfig option with the corresponding help to make the above clear. When the DMA_CACHE_RWFO option is disabled, the kernel behaviour is that prior to the f4d6477f commit. This also allows ARMv6 UP processors with speculative loads to work correctly. For other processors, a different workaround may be needed. Cc: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | ARM: 6187/1: The v6_dma_inv_range() function must preserve data on SMPCatalin Marinas2010-07-011-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent patch for DMA cache maintenance on ARM11MPCore added a write for ownership trick to the v6_dma_inv_range() function. Such operation destroys data already present in the buffer. However, this function is used with with dma_sync_single_for_device() which is supposed to preserve the existing data transfered into the buffer. This patch adds a combination of read/write for ownership to preserve the original data. Reported-by: Ronen Shitrit <rshitrit@marvell.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | | ARM: 6186/1: Avoid the CONSISTENT_DMA_SIZE warning on noMMU buildsCatalin Marinas2010-07-011-9/+9
| | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This macro is not defined when !CONFIG_MMU so this patch moves the CONSISTENT_* definitions to the CONFIG_MMU section. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | | Merge branch 'perf-fixes-for-linus' of ↵Linus Torvalds2010-07-042-3/+12
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: perf, x86: Fix incorrect branches event on AMD CPUs perf tools: Fix find tids routine by excluding "." and ".." x86: Send a SIGTRAP for user icebp traps
| * | | | | perf, x86: Fix incorrect branches event on AMD CPUsVince Weaver2010-07-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While doing some performance counter validation tests on some assembly language programs I noticed that the "branches:u" count was very wrong on AMD machines. It looks like the wrong event was selected. Signed-off-by: Vince Weaver <vweaver1@eecs.utk.edu> Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Robert Richter <robert.richter@amd.com> Cc: Borislav Petkov <borislav.petkov@amd.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: <stable@kernel.org> LKML-Reference: <alpine.DEB.2.00.1007011526010.23160@cl320.eecs.utk.edu> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | | | | x86: Send a SIGTRAP for user icebp trapsFrederic Weisbecker2010-06-301-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before we had a generic breakpoint layer, x86 used to send a sigtrap for any debug event that happened in userspace, except if it was caused by lazy dr7 switches. Currently we only send such signal for single step or breakpoint events. However, there are three other kind of debug exceptions: - debug register access detected: trigger an exception if the next instruction touches the debug registers. We don't use it. - task switch, but we don't use tss. - icebp/int01 trap. This instruction (0xf1) is undocumented and generates an int 1 exception. Unlike single step through TF flag, it doesn't set the single step origin of the exception in dr6. icebp then used to be reported in userspace using trap signals but this have been incidentally broken with the new breakpoint code. Reenable this. Since this is the only debug event that doesn't set anything in dr6, this is all we have to check. This fixes a regression in Wine where World Of Warcraft got broken as it uses this for software protection checks purposes. And probably other apps do. Reported-and-tested-by: Alexandre Julliard <julliard@winehq.org> Signed-off-by: Frederic Weisbecker <fweisbec@gmail.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Prasad <prasad@linux.vnet.ibm.com> Cc: 2.6.33.x 2.6.34.x <stable@kernel.org>
* | | | | | Merge branch 'release' of ↵Linus Torvalds2010-07-011-1/+1
|\ \ \ \ \ \ | |_|/ / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6 * 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6: [IA64] Fix spinaphore down_spin()
| * | | | | [IA64] Fix spinaphore down_spin()Tony Luck2010-06-301-1/+1
| | |_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Typo in down_spin() meant it only read the low 32 bits of the "serve" value, instead of the full 64 bits. This results in the system hanging when the values in ticket/serve get larger than 32-bits. A big enough system running the right test can hit this in a just a few hours. Broken since 883a3acf5b0d4782ac35981227a0d094e8b44850 [IA64] Re-implement spinaphores using ticket lock concepts Reported via IRC by Bjorn Helgaas Signed-off-by: Tony Luck <tony.luck@intel.com>
* | | | | Merge branch 'omap-fixes-for-linus' of ↵Linus Torvalds2010-06-308-12/+20
|\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: OMAP: hwmod: Fix the missing braces OMAP4: clock: Fix multi-omap boot with reset un-used clocks OMAP3: PM: fix IO daisy chain enable to use PM_WKEN reg omap: GPIO: fix auto-disable of debounce clock omap: DMTIMER: Ack pending interrupt always when stopping a timer omap: Stalker board: switch over to gpio_set_debounce omap: fix build failure due to missing include dma-mapping.h omap iommu: Fix Memory leak
| * \ \ \ \ Merge branch 'for_2.6.35rc' of git://git.pwsan.com/linux-2.6 into ↵Tony Lindgren2010-06-2843-61/+368
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | omap-fixes-for-linus
| | * | | | | OMAP: hwmod: Fix the missing bracesBenoit Cousson2010-06-231-3/+6
| | | |_|/ / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As reported by Sergei, a couple of braces were missing after the WARN removal patch. [07/22] OMAP: hwmod: Replace WARN by pr_warning if clock lookup failed https://patchwork.kernel.org/patch/100756/ Signed-off-by: Benoit Cousson <b-cousson@ti.com> [paul@pwsan.com: fixed patch description per Anand's E-mail] Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Sergei Shtylyov <sshtylyov@mvista.com> Cc: Anand Gadiyar <gadiyar@ti.com>
| * | | | | OMAP4: clock: Fix multi-omap boot with reset un-used clocksSantosh Shilimkar2010-06-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses "ENABLE_ON_INIT" flag on the emif clock nodes to avoid the emif clk getting cut as part of reset un-used clock routine which prevents boot. Since "omap4xxx_clk_init()" calls "clk_enable_init_clocks()" which increases the usecount on all ENABLE_ON_INIT clocks, it prevents "omap2_clk_disable_unused()" from disabling the clock. The real fix is to have driver for EMIF and do clock get/enable as part of it. The EMIF driver is planned to be done HWMOD way so till that available to keep omap3_defconfig booting on OMAP4430, this patch is necessary. (Will updated the auto-gen script for 44xx accordingly) The fix was suggested by Paul Walmsley Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | | | OMAP3: PM: fix IO daisy chain enable to use PM_WKEN regKevin Hilman2010-06-101-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Checking to se if the IO daisy chain is enabled should be checking the PM_WKEN register, not the PM_WKST register. Reading PM_WKST tells us if an event occurred, not whether or not it is enabled. Apparently, we've been lucky until now in that a pending event has not been there during enable. However, on 3630/Zoom3, I noticed because of the WARN that this timeout was always happening. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | | | omap: GPIO: fix auto-disable of debounce clockKevin Hilman2010-06-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The addition of the new debounce code (commit 168ef3d9a56bd8bffe0ef4189c450888b4aefefe) broke the auto-disable of debounce clocks on idle by forgetting to update the debounce clock enable mask. Add back the updating of bank->dbck_enable_mask so debounce clocks are auto-disabled. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | | | omap: DMTIMER: Ack pending interrupt always when stopping a timerTero Kristo2010-06-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The kernel timer queue is being run currently from a GP timer running in a one shot mode, which works in a way that when it expires, it will also stop. Usually during this situation, the interrupt handler will ack the interrupt, load a new value to the timer and start it again. During suspend, the situation is slightly different, as we disable interrupts just before timekeeping is suspended, which leaves a small window where the timer can expire before it is stopped, and will leave the interrupt flag pending. This pending interrupt will prevent ARM sleep entry, thus now we ack it always when we are attempting to stop a timer. Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> [tony@atomide.com: removed the ifdef to make the patch cover omap1 also] Signed-off-by: Tony Lindgren <tony@atomide.com>
generated by cgit v1.1 at 2025-02-14 02:37:15 +0000