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* tuna: add omaplfb platform dataZiyan2016-01-053-3/+21
| | | | | | | This allows us to disable the unused nonsecure tiler2d carveout (10 mb). Since the freed carveout memory will be added to tiler2d, we can lower its carveout size by this amount. Change-Id: I12b0eb55a4bbb2f6dc251697d93c96fc574cc472
* omap: Remove extra newline in resetreason.Kyle Repinski2016-01-051-1/+1
| | | | Change-Id: Ibab8e1b343555e9d359eff6eccbadfd07687a3da
* omap: ion: Remove extra space in debug message.Kyle Repinski2016-01-051-1/+1
| | | | Change-Id: I65bf354322fff214b72ca2950ada8c15a625e202
* tuna: very slightly relax ram timingsBoy Petersen2015-08-211-6/+6
| | | | | ...to avoid errors. Got a report via PM that the sharper values may cause instabilities. I guess these settings are final now.
* tuna: sharper ram timings according to specsBoy Petersen2015-08-211-8/+8
| | | | | | | | | | | Samsung K3PE7E700M RAM chips are CL5. Set it accordingly. Also, set tRCD and tRP to what's still stable. Adjust tWR, tCAS and tRAS to reflect sane values. Lower does not necessarily mean better in these cases. Information sources: http://en.wikipedia.org/wiki/SDRAM_latency http://forums.legitreviews.com/about20065.html
* tuna: defconfigs: do not disable selinuxZiyan2015-08-172-2/+2
| | | | Change-Id: Ia14955d0824e0ef4be802f27b8b14c2addb8e1c6
* tuna: vibrator: remove unnecessary loggingZiyan2015-05-101-8/+3
| | | | | | - don't log sysfs reads - make pwm value change log message clearer - only log vibrator events in dynamic debug mode
* defconfig: enable f2fsZiyan2015-05-022-0/+12
| | | | Change-Id: Ifbd5bb5e617e6ba3b27f1192545802f0ea7c0e82
* fs: push i_mutex and filemap_write_and_wait down into ->fsync() handlersJosef Bacik2015-05-021-2/+9
| | | | | | | | | | | | | | | | | | | | Btrfs needs to be able to control how filemap_write_and_wait_range() is called in fsync to make it less of a painful operation, so push down taking i_mutex and the calling of filemap_write_and_wait() down into the ->fsync() handlers. Some file systems can drop taking the i_mutex altogether it seems, like ext3 and ocfs2. For correctness sake I just pushed everything down in all cases to make sure that we keep the current behavior the same for everybody, and then each individual fs maintainer can make up their mind about what to do from there. Thanks, Acked-by: Jan Kara <jack@suse.cz> Signed-off-by: Josef Bacik <josef@redhat.com> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Conflicts: Documentation/filesystems/porting Change-Id: I7697244cce355e6d443a39c5133a5c94f02e199b
* tuna: nfc: Disable wakelock when powered off.Kyle Repinski2015-05-021-5/+10
| | | | | | | In less than a day's time I had quite a few minutes of nfc wakelock... Unsure if we should bail if enable/disable of wakelock fails, will revist. Signed-off-by: Kyle Repinski <repinski23@gmail.com>
* [TEST] revert rpc/rpmsg changesZiyan2015-05-017-414/+41
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* Revert "tuna: remove duplicated call"Ziyan2015-04-201-0/+1
| | | | This reverts commit b01a056a0b676685942d80886c069499e86058e0.
* OMAPDSS: DSS: Scale DSS OPP according to pixel clock rateTaras Kondratiuk2015-04-181-1/+3
| | | | | | | | | | Before enabling pixel clock DSS should set its OPP for OPP framework to set correct VDD_CORE voltage level. When pixel clock is disabled DSS can set the lowest OPP. Change-Id: Ia1459614ae306dba9b048b149e474442e2880bba Signed-off-by: Taras Kondratiuk <taras@ti.com>
* OMAPDSS: DSI: add missing includeZiyan2015-04-181-15/+16
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* tuna: update defconfigZiyan2015-04-172-8/+14
| | | | | | | | | | | - enable SLUB_DEBUG SLUB_DEBUG is very cheap by default, and allows more expensive poisoning to be turned on at runtime. It also makes /proc/slabinfo available, which is critical for debugging memory issues. - enable CONFIG_CRYPTO_AES_ARM - enable DHD_USE_SCHED_SCAN - normalize
* tuna: remove FB ram size from platform dataZiyan2015-04-151-7/+0
| | | | FB ram size should not be specified since it is being calculated.
* tuna: update regulator configurationsZiyan2015-04-151-0/+24
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* tuna: disable cgroup memory resource controllerZiyan2015-04-052-2/+2
| | | | | It causes more harm than good. http://lwn.net/Articles/516533/
* tuna: revert back to 2 fb's for nowZiyan2015-04-042-2/+2
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* staging: Remove the Android logger driverJohn Stultz2015-03-262-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the relase of Lollipop, Android no longer requires the logger driver. There are three patches which the android dev's still need before they drop logger on all their devices: [PATCH v4 1/5] pstores: use scnprintf [PATCH v2 2/5] pstore: remove superfluous memory size check [PATCH 3/5] pstore: handle zero-sized prz in series [PATCH v4 4/5] pstore: add pmsg [PATCH 5/5] pstore: selinux: add security in-core xattr support for pstore and debugfs But these seem to have been acked and are hopefully queued for upstream. So this patch removes the logger driver from staging. Cc: Rom Lemarchand <romlem@google.com>, Cc: Mark Salyzyn <salyzyn@google.com> Cc: Kees Cook <keescook@chromium.org> Cc: Android Kernel Team <kernel-team@android.com> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Bug: 13505761 Change-Id: I21b6897f01871851e05b6eb53c7c08a1cb597e3d Conflicts: drivers/staging/android/Kconfig drivers/staging/android/logger.c drivers/staging/android/logger.h
* ARM: 8120/1: crypto: sha512: add ARM NEON implementationJussi Kivilinna2015-03-193-0/+762
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds ARM NEON assembly implementation of SHA-512 and SHA-384 algorithms. tcrypt benchmark results on Cortex-A8, sha512-generic vs sha512-neon-asm: block-size bytes/update old-vs-new 16 16 2.99x 64 16 2.67x 64 64 3.00x 256 16 2.64x 256 64 3.06x 256 256 3.33x 1024 16 2.53x 1024 256 3.39x 1024 1024 3.52x 2048 16 2.50x 2048 256 3.41x 2048 1024 3.54x 2048 2048 3.57x 4096 16 2.49x 4096 256 3.42x 4096 1024 3.56x 4096 4096 3.59x 8192 16 2.48x 8192 256 3.42x 8192 1024 3.56x 8192 4096 3.60x 8192 8192 3.60x Change-Id: Ibc318f8c9136507f57e2bb8d8f51b4714d8ed70b Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Iliyan Malchev <malchev@google.com>
* ARM: 8119/1: crypto: sha1: add ARM NEON implementationJussi Kivilinna2015-03-195-3/+848
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds ARM NEON assembly implementation of SHA-1 algorithm. tcrypt benchmark results on Cortex-A8, sha1-arm-asm vs sha1-neon-asm: block-size bytes/update old-vs-new 16 16 1.04x 64 16 1.02x 64 64 1.05x 256 16 1.03x 256 64 1.04x 256 256 1.30x 1024 16 1.03x 1024 256 1.36x 1024 1024 1.52x 2048 16 1.03x 2048 256 1.39x 2048 1024 1.55x 2048 2048 1.59x 4096 16 1.03x 4096 256 1.40x 4096 1024 1.57x 4096 4096 1.62x 8192 16 1.03x 8192 256 1.40x 8192 1024 1.58x 8192 4096 1.63x 8192 8192 1.63x Change-Id: I6df3c0a9ba8d450d034cf78785b6ce80a72bef4a Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Iliyan Malchev <malchev@google.com>
* ARM: 8118/1: crypto: sha1/make use of common SHA-1 structuresJussi Kivilinna2015-03-191-28/+22
| | | | | | | | | | | Common SHA-1 structures are defined in <crypto/sha.h> for code sharing. This patch changes SHA-1/ARM glue code to use these structures. Change-Id: I5b82530706fa7c6f5ec08926992b86d26fa1c24d Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Jussi Kivilinna <jussi.kivilinna@iki.fi> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* crypto: arm-aes - fix encryption of unaligned dataMikulas Patocka2015-03-191-5/+5
| | | | | | | | | | | Fix the same alignment bug as in arm64 - we need to pass residue unprocessed bytes as the last argument to blkcipher_walk_done. Change-Id: Ia4d3cacb006269aa5b9c0c542256eff5822e84ac Signed-off-by: Mikulas Patocka <mpatocka@redhat.com> Cc: stable@vger.kernel.org # 3.13+ Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* CRYPTO: Fix more AES build errorsRussell King2015-03-192-2/+2
| | | | | | | | | | | | | | | | | | | | | Building a multi-arch kernel results in: arch/arm/crypto/built-in.o: In function `aesbs_xts_decrypt': sha1_glue.c:(.text+0x15c8): undefined reference to `bsaes_xts_decrypt' arch/arm/crypto/built-in.o: In function `aesbs_xts_encrypt': sha1_glue.c:(.text+0x1664): undefined reference to `bsaes_xts_encrypt' arch/arm/crypto/built-in.o: In function `aesbs_ctr_encrypt': sha1_glue.c:(.text+0x184c): undefined reference to `bsaes_ctr32_encrypt_blocks' arch/arm/crypto/built-in.o: In function `aesbs_cbc_decrypt': sha1_glue.c:(.text+0x19b4): undefined reference to `bsaes_cbc_encrypt' This code is already runtime-conditional on NEON being supported, so there's no point compiling it out depending on the minimum build architecture. Change-Id: Iff65acec7d30c508bf72132acad67332ea56bd3b Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: add .gitignore entry for aesbs-core.SRussell King2015-03-191-0/+1
| | | | | | | This avoids this file being incorrectly added to git. Change-Id: If8d1d669d8565b1f1cf3751b202bae052d26b53b Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: add support for bit sliced AES using NEON instructionsArd Biesheuvel2015-03-194-2/+5457
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bit sliced AES gives around 45% speedup on Cortex-A15 for encryption and around 25% for decryption. This implementation of the AES algorithm does not rely on any lookup tables so it is believed to be invulnerable to cache timing attacks. This algorithm processes up to 8 blocks in parallel in constant time. This means that it is not usable by chaining modes that are strictly sequential in nature, such as CBC encryption. CBC decryption, however, can benefit from this implementation and runs about 25% faster. The other chaining modes implemented in this module, XTS and CTR, can execute fully in parallel in both directions. The core code has been adopted from the OpenSSL project (in collaboration with the original author, on cc). For ease of maintenance, this version is identical to the upstream OpenSSL code, i.e., all modifications that were required to make it suitable for inclusion into the kernel have been made upstream. The original can be found here: http://git.openssl.org/gitweb/?p=openssl.git;a=commit;h=6f6a6130 Note to integrators: While this implementation is significantly faster than the existing table based ones (generic or ARM asm), especially in CTR mode, the effects on power efficiency are unclear as of yet. This code does fundamentally more work, by calculating values that the table based code obtains by a simple lookup; only by doing all of that work in a SIMD fashion, it manages to perform better. Change-Id: Ife4f79ce9e8994e248d6fc01fcb23b0534265418 Cc: Andy Polyakov <appro@openssl.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ARM: move AES typedefs and function prototypes to separate headerArd Biesheuvel2015-03-192-16/+25
| | | | | | | | | Put the struct definitions for AES keys and the asm function prototypes in a separate header and export the asm functions from the module. This allows other drivers to use them directly. Change-Id: Ic79a7da83232d4e3658f3fc64de4761c88ae73f3 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ARM: 7837/3: fix Thumb-2 bug in AES assembler codeArd Biesheuvel2015-03-191-3/+3
| | | | | | | | | | | | | | | | commit 40190c85f427dcfdbab5dbef4ffd2510d649da1f upstream. Patch 638591c enabled building the AES assembler code in Thumb2 mode. However, this code used arithmetic involving PC rather than adr{l} instructions to generate PC-relative references to the lookup tables, and this needs to take into account the different PC offset when running in Thumb mode. Change-Id: I7358a145be3f37420c8ce5b8fc83a761b0d863ac Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* ARM: 7723/1: crypto: sha1-armv4-large.S: fix SP handlingArd Biesheuvel2015-03-191-1/+1
| | | | | | | | | | | | | | Make the SHA1 asm code ABI conformant by making sure all stack accesses occur above the stack pointer. Origin: http://git.openssl.org/gitweb/?p=openssl.git;a=commit;h=1a9d60d2 Change-Id: I89fe44b5021ee3d37ac924f04a82e9631e31843e Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> Cc: stable@vger.kernel.org Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7626/1: arm/crypto: Make asm SHA-1 and AES code Thumb-2 compatibleDave Martin2015-03-192-59/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes aes-armv4.S and sha1-armv4-large.S to work natively in Thumb. This allows ARM/Thumb interworking workarounds to be removed. I also take the opportunity to convert some explicit assembler directives for exported functions to the standard ENTRY()/ENDPROC(). For the code itself: * In sha1_block_data_order, use of TEQ with sp is deprecated in ARMv7 and not supported in Thumb. For the branches back to .L_00_15 and .L_40_59, the TEQ is converted to a CMP, under the assumption that clobbering the C flag here will not cause incorrect behaviour. For the first branch back to .L_20_39_or_60_79 the C flag is important, so sp is moved temporarily into another register so that TEQ can be used for the comparison. * In the AES code, most forms of register-indexed addressing with shifts and rotates are not permitted for loads and stores in Thumb, so the address calculation is done using a separate instruction for the Thumb case. The resulting code is unlikely to be optimally scheduled, but it should not have a large impact given the overall size of the code. I haven't run any benchmarks. Change-Id: Ic80ff883d90ee1f83b775e0bb447672d81dff54b Signed-off-by: Dave Martin <dave.martin@linaro.org> Tested-by: David McCullough <ucdevel@gmail.com> (ARM only) Acked-by: David McCullough <ucdevel@gmail.com> Acked-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* arm/crypto: Add optimized AES and SHA1 routinesDavid McCullough2015-03-196-0/+1912
| | | | | | | | | | | | | | Add assembler versions of AES and SHA1 for ARM platforms. This has provided up to a 50% improvement in IPsec/TCP throughout for tunnels using AES128/SHA1. Platform CPU SPeed Endian Before (bps) After (bps) Improvement IXP425 533 MHz big 11217042 15566294 ~38% KS8695 166 MHz little 3828549 5795373 ~51% Change-Id: I5b77e7aa89c8b1d54aef75065827325e90305638 Signed-off-by: David McCullough <ucdevel@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* tuna: add back vmalloc=768MZiyan2015-01-272-2/+2
| | | | | | https://android.googlesource.com/kernel/omap.git/+/e04536e92ab7dd6a297a620282c910baec823544 Change-Id: I569dd38d187f6d2c6de3510d6d824944361dddc2
* tuna: update defconfigsZiyan2015-01-152-8/+40
| | | | | | | - enable Memory Resource Controller for Control Groups - enable tracer Change-Id: I8fe414599e8a730caec5da25585a87094190a2b0
* tuna: enable 512 MHz GPU frequency slotZiyan2014-12-233-0/+10
| | | | Change-Id: I859ed2cbb777dadc01be95ecf56b333f8940e848
* tuna: add cyanogenmod defconfigZiyan2014-12-161-0/+2802
| | | | | | To separate some non-stock features. Change-Id: Ic0a43d5b2c3399ff5ce1e0e56f98bf179ae6cb31
* tuna: update defconfigZiyan2014-12-161-14/+4
| | | | Change-Id: I1819e9b22c40f3fa875929f20672cc5b1d23e3dd
* Add sysfs vibrator intensity controlscodeworkx2014-12-161-2/+78
| | | | | | | | | | | | | Patch Set 2 Removed unused variable Patch Set 3 Use pwm_old variable Patch Set 4 Add authorship Change-Id: Ibcb887fe2c78cfd5740f363d33d1ed997c98b9c6
* optimized LPDDR RAM timings (~10% throughput increase)Boy Petersen2014-12-161-9/+9
| | | | | | | | | | | | | | | Tweaked the device's RAM timings. Benchmarks suggest a 10 percent thorughput improvement (RgBandwidth RAM misc benchmark; threads: 1. 20 benchmark instances each, best result wins): Stock Tweaked Copy 1249.9 MB/s -> 1373.0 MB/s --> 9.86 % improvement Scale 1084.8 MB/s -> 1188.1 MB/s --> 9.52 % improvement Add 938.4 MB/s -> 1050.2 MB/s --> 11.91 % improvement Triad 923.0 MB/s -> 1043.5 MB/s --> 13.06 % improvement Change-Id: I082e7515d2995910b115c3fe0283fe25808d1cfb
* ASoC: Tuna: separate tuna board fileZiyann2014-12-061-1/+1
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* tuna: remove fb1 and update tiler carveout accordinglyZiyann2014-11-281-2/+2
| | | | Credit to @MWisBest
* tuna: reduce reserved tiler memory size by 32 mbZiyann2014-11-271-1/+1
| | | | | The remaining tiler memory (96 mb) is still more than enough for 1080p video playback and recording. Adds back 32 mb of wasted memory.
* Revert "omap4: sdp/panda/tablet: reserve memory for dsp"Jesse Villarreal2014-11-261-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e699cc2c4cc3f369108d83370172138294f9840f. DSP currently requires 4MB of memory to be set-aside to meet its firmware requirements and can use either a fixed carveout or a dynamically assigned carveout. The above commit uses static carveouts for DSP in various board files. DSP does not have a mandatory requirement to use this fixed carveout, and has been switched over to use a dynamically allocated carveout address. The above commit is therefore being reverted to free up unused carveout memory. This change simultaneously fixes a build error when the DSP remoteproc is included in the build configuration. The build was by the following commit: "OMAP4: ion: remove hardcoded carveout sizes" Conflicts: arch/arm/mach-omap2/include/mach/omap4_ion.h Change-Id: Iee9be7dbc19dd580fabce6ae966cf86d1f54b5cb Signed-off-by: Jesse Villarreal <jesse.villarreal@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Conflicts: arch/arm/mach-omap2/board-4430sdp.c arch/arm/mach-omap2/board-44xx-tablet.c arch/arm/mach-omap2/board-omap4panda.c arch/arm/mach-omap2/include/mach/omap4_ion.h
* ARM: 7670/1: fix the memset fixNicolas Pitre2014-11-261-20/+13
| | | | | | | | | | | | | | | | | | | | | Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by recent GCC (4.7.2) optimizations") attempted to fix a compliance issue with the memset return value. However the memset itself became broken by that patch for misaligned pointers. This fixes the above by branching over the entry code from the misaligned fixup code to avoid reloading the original pointer. Also, because the function entry alignment is wrong in the Thumb mode compilation, that fixup code is moved to the end. While at it, the entry instructions are slightly reworked to help dual issue pipelines. Change-Id: Ib1cf34632f2dd8424866b89f8d2c6ad3272cfa48 Signed-off-by: Nicolas Pitre <nico@linaro.org> Tested-by: Alexander Holler <holler@ahsoftware.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: 7668/1: fix memset-related crashes caused by recent GCC (4.7.2) ↵Ivan Djelic2014-11-261-41/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | optimizations Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on assumptions about the implementation of memset and similar functions. The current ARM optimized memset code does not return the value of its first argument, as is usually expected from standard implementations. For instance in the following function: void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter) { memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter)); waiter->magic = waiter; INIT_LIST_HEAD(&waiter->list); } compiled as: 800554d0 <debug_mutex_lock_common>: 800554d0: e92d4008 push {r3, lr} 800554d4: e1a00001 mov r0, r1 800554d8: e3a02010 mov r2, #16 ; 0x10 800554dc: e3a01011 mov r1, #17 ; 0x11 800554e0: eb04426e bl 80165ea0 <memset> 800554e4: e1a03000 mov r3, r0 800554e8: e583000c str r0, [r3, #12] 800554ec: e5830000 str r0, [r3] 800554f0: e5830004 str r0, [r3, #4] 800554f4: e8bd8008 pop {r3, pc} GCC assumes memset returns the value of pointer 'waiter' in register r0; causing register/memory corruptions. This patch fixes the return value of the assembly version of memset. It adds a 'mov' instruction and merges an additional load+store into existing load/store instructions. For ease of review, here is a breakdown of the patch into 4 simple steps: Step 1 ====== Perform the following substitutions: ip -> r8, then r0 -> ip, and insert 'mov ip, r0' as the first statement of the function. At this point, we have a memset() implementation returning the proper result, but corrupting r8 on some paths (the ones that were using ip). Step 2 ====== Make sure r8 is saved and restored when (! CALGN(1)+0) == 1: save r8: - str lr, [sp, #-4]! + stmfd sp!, {r8, lr} and restore r8 on both exit paths: - ldmeqfd sp!, {pc} @ Now <64 bytes to go. + ldmeqfd sp!, {r8, pc} @ Now <64 bytes to go. (...) tst r2, #16 stmneia ip!, {r1, r3, r8, lr} - ldr lr, [sp], #4 + ldmfd sp!, {r8, lr} Step 3 ====== Make sure r8 is saved and restored when (! CALGN(1)+0) == 0: save r8: - stmfd sp!, {r4-r7, lr} + stmfd sp!, {r4-r8, lr} and restore r8 on both exit paths: bgt 3b - ldmeqfd sp!, {r4-r7, pc} + ldmeqfd sp!, {r4-r8, pc} (...) tst r2, #16 stmneia ip!, {r4-r7} - ldmfd sp!, {r4-r7, lr} + ldmfd sp!, {r4-r8, lr} Step 4 ====== Rewrite register list "r4-r7, r8" as "r4-r8". Change-Id: I33f8bd7227f88e627f943294f7838c15e5eb5777 Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com> Reviewed-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* tuna: enable CONFIG_MMC_SAMSUNG_SMARTZiyann2014-11-261-0/+1
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* Power: Add an API call to log wakeup reasonsZiyann2014-11-261-0/+3
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* tuna: update defconfigZiyann2014-11-261-17/+29
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* Fix build.Kyle Repinski2014-11-261-1/+1
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* Merge remote-tracking branch 'linux/linux-3.0.y' into stable-newpvrZiyann2014-11-2681-420/+616
|\ | | | | | | | | Conflicts: arch/arm/include/asm/hardware/cache-l2x0.h
generated by cgit v1.1 at 2025-01-22 19:24:05 +0000