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| * mmc: sdhci: add support for retuning mode 1Arindam Nath2011-05-242-3/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Host Controller v3.00 can support retuning modes 1,2 or 3 depending on the bits 46-47 of the Capabilities register. Also, the timer count for retuning is indicated by bits 40-43 of the same register. We initialize timer_list for retuning the first time we execute tuning procedure. This condition is indicated by SDHCI_NEEDS_RETUNING not being set. Since retuning mode 1 sets a limit of 4MB on the maximum data length, we set max_blk_count appropriately. Once the tuning timer expires, we set SDHCI_NEEDS_RETUNING flag, and if the flag is set, we execute tuning procedure before sending the next command. We need to restore mmc_request structure after executing retuning procedure since host->mrq is used inside the procedure to send CMD19. We also disable and re-enable this flag during suspend and resume respectively, as per the spec v3.00. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci: add support for programmable clock modeArindam Nath2011-05-242-15/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Host Controller v3.00 supports programmable clock mode as an optional feature. The support for this mode is indicated by non-zero value in bits 48-55 of the Capabilities register. If supported, the actual value of Clock Multiplier is one more than the value provided in the bit fields. We only set Clock Generator Select (bit 5) and SDCLK Frequency Select (bits 8-15) of the Clock Control register in case Preset Value Enable is not set, otherwise these fields are automatically set by the Host Controller based on the UHS mode selected. Also, since the maximum and minimum clock frequency in this mode can be (Base Clock * Clock Mul) and (Base Clock * Clock Mul)/1024 respectively, f_max and f_min have been recalculated to reflect this change. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci: enable preset value after uhs initializationArindam Nath2011-05-241-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the Host Controller spec v3.00, setting Preset Value Enable in the Host Control2 register lets SDCLK Frequency Select, Clock Generator Select and Driver Strength Select to be set automatically by the Host Controller based on the UHS-I mode set. This patch enables this feature. Since Preset Value Enable makes sense only for UHS-I cards, we enable this feature after successfull UHS-I initialization. We also reset Preset Value Enable next time before initialization. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sd: add support for tuning during uhs initializationArindam Nath2011-05-242-1/+170
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Host Controller needs tuning during initialization to operate SDR50 and SDR104 UHS-I cards. Whether SDR50 mode actually needs tuning is indicated by bit 45 of the Host Controller Capabilities register. A new command CMD19 has been defined in the Physical Layer spec v3.01 to request the card to send tuning pattern. We enable Buffer Read Ready interrupt at the very begining of tuning procedure, because that is the only interrupt generated by the Host Controller during tuning. We program the block size to 64 in the Block Size register. We make sure that DMA Enable and Multi Block Select in the Transfer Mode register are set to 0 before actually sending CMD19. The tuning block is sent by the card to the Host Controller using DAT lines, so we set Data Present Select (bit 5) in the Command register. The Host Controller is responsible for doing the verfication of tuning block sent by the card at the hardware level. After sending CMD19, we wait for Buffer Read Ready interrupt. In case we don't receive an interrupt after the specified timeout value, we fall back on fixed sampling clock by setting Execute Tuning (bit 6) and Sampling Clock Select (bit 7) of Host Control2 register to 0. Before exiting the tuning procedure, we disable Buffer Read Ready interrupt and re-enable other interrupts. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sd: set current limit for uhs cardsArindam Nath2011-05-241-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We decide on the current limit to be set for the card based on the Capability of Host Controller to provide current at 1.8V signalling, and the maximum current limit of the card as indicated by CMD6 mode 0. We then set the current limit for the card using CMD6 mode 1. As per the Physical Layer Spec v3.01, the current limit switch is only applicable for SDR50, SDR104, and DDR50 bus speed modes. For other UHS-I modes, we set the default current limit of 200mA. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sd: add support for uhs bus speed mode selectionArindam Nath2011-05-242-3/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for setting UHS-I bus speed mode during UHS-I initialization procedure. Since both the host and card can support more than one bus speed, we select the highest speed based on both of their capabilities. First we set the bus speed mode for the card using CMD6 mode 1, and then we program the host controller to support the required speed mode. We also set High Speed Enable in case one of the UHS-I modes is selected. We take care to reset SD clock before setting UHS mode in the Host Control2 register, and then re-enable it as per the Host Controller spec v3.00. We then set the clock frequency for the UHS-I mode selected. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci: reset sdclk before setting high speed enableArindam Nath2011-05-241-3/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per Host Controller spec v3.00, we reset SDCLK before setting High Speed Enable, and then set it back to avoid generating clock gliches. Before enabling SDCLK again, we make sure the clock is stable, so we use sdhci_set_clock(). Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sd: add support for driver type selectionArindam Nath2011-05-242-1/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for setting driver strength during UHS-I initialization procedure. Since UHS-I cards set S18A (bit 24) in response to ACMD41, we use this as a base for UHS-I initialization. We modify the parameter list of mmc_sd_get_cid() so that we can save the ROCR from ACMD41 to check whether bit 24 is set. We decide whether the Host Controller supports A, C, or D driver type depending on the Capabilities register. Driver type B is suported by default. We then set the appropriate driver type for the card using CMD6 mode 1. As per Host Controller spec v3.00, we set driver type for the host only if Preset Value Enable in the Host Control2 register is not set. SDHCI_HOST_CONTROL has been renamed to SDHCI_HOST_CONTROL1 to conform to the spec. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sd: add support for signal voltage switch procedureArindam Nath2011-05-242-15/+195
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Host Controller v3.00 adds another Capabilities register. Apart from other things, this new register indicates whether the Host Controller supports SDR50, SDR104, and DDR50 UHS-I modes. The spec doesn't mention about explicit support for SDR12 and SDR25 UHS-I modes, so the Host Controller v3.00 should support them by default. Also if the controller supports SDR104 mode, it will also support SDR50 mode as well. So depending on the host support, we set the corresponding MMC_CAP_* flags. One more new register. Host Control2 is added in v3.00, which is used during Signal Voltage Switch procedure described below. Since as per v3.00 spec, UHS-I supported hosts should set S18R to 1, we set S18R (bit 24) of OCR before sending ACMD41. We also need to set XPC (bit 28) of OCR in case the host can supply >150mA. This support is indicated by the Maximum Current Capabilities register of the Host Controller. If the response of ACMD41 has both CCS and S18A set, we start the signal voltage switch procedure, which if successfull, will switch the card from 3.3V signalling to 1.8V signalling. Signal voltage switch procedure adds support for a new command CMD11 in the Physical Layer Spec v3.01. As part of this procedure, we need to set 1.8V Signalling Enable (bit 3) of Host Control2 register, which if remains set after 5ms, means the switch to 1.8V signalling is successfull. Otherwise, we clear bit 24 of OCR and retry the initialization sequence. When we remove the card, and insert the same or another card, we need to make sure that we start with 3.3V signalling voltage. So we call mmc_set_signal_voltage() with MMC_SIGNAL_VOLTAGE_330 set so that we are back to 3.3V signalling voltage before we actually start initializing the card. Tested by Zhangfei Gao with a Toshiba uhs card and general hs card, on mmp2 in SDMA mode. Signed-off-by: Arindam Nath <arindam.nath@amd.com> Reviewed-by: Philip Rakity <prakity@marvell.com> Tested-by: Philip Rakity <prakity@marvell.com> Acked-by: Zhangfei Gao <zhangfei.gao@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci: Fix read-only detection with JMicron 388 chipTakashi Iwai2011-05-242-4/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On HP laptops with JMicron 388 chip, the write-locked SD card isn't detected correctly as read-only in many cases. This is because the PRESENT_STATE register becomes unsable just after plugging, and it returns the WRITE_PROTECT bit wrongly at the first read. This patch fixes the read-only detection by adding a new sdhci quirk indicating to check the register more intensively with a relatively long delay. The patch is tested with 2.6.39-rc4 kernel. Cc: Aries Lee <arieslee@jmicron.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci: Add pre and post reset processing for chip specific resetPhilip Rakity2011-05-242-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Marvell pxa controllers have private registers that may need to be modified before and after a reset is done. For example, the SD reset operation, RESET_ALL, will reset the private registers to their default state. This will cause the clock adjustment registers that may have been programmed to have incorrect values. RESET_DATA sometimes needs to be delayed before the reset is done (depending on SoC) to enable any transactions being handled by the SDIO card to be completed. Needed in pre SD 3.0 silicon to handle clock gating. Implement hooks to allow this to happen. Signed-off-by: Philip Rakity <prakity@marvell.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci: Fix SDHCI_QUIRK_TIMEOUT_USES_SDCLKMark Brown2011-05-241-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 373e6a (mmc: sdhci: R1B command handling + MMC_CAP_ERASE) moved the handling of SDHCI_QUIRK_TIMEOUT_USES_SDCLK from sdhci_calc_timeout() to sdhci_add_host(). This causes division by zero errors on at least the S3C SDHCI controller as the quirk implementation needs host->clock set to work but host->clock has not been set when sdhci_add_host() is called. Fix this by backing out that portion of the change, the clock may vary at runtime anyway. It does occur to me that we may want to move the quirk to where we set the clock but this seems more invasive and I'm concerned about undesirable side effects. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: Andrei Warkentin <andreiw@motorola.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci: work around broken dma boundary behaviorMikko Vinni2011-05-242-5/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SD host controllers (noticed on an integrated JMicron SD reader on an HP Pavilion dv5-1250eo laptop) don't update the dma address register before signaling a dma interrupt due to a dma boundary. Update the register manually to the next boundary (by default 512KiB), at which the transfer stopped. As long as each transfer is at most 512KiB in size (guaranteed by a BUG_ON in sdhci_prepare_data()) and the boundary is kept at the default value, this fix is needed at most once per transfer. Smaller boundaries are taken care of by counting the transferred bytes. Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=28462 Signed-off-by: Mikko Vinni <mmvinni@yahoo.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci: R1B command handling + MMC_CAP_ERASE.Andrei Warkentin2011-05-241-16/+26
| | | | | | | | | | | | | | | | | | | | | | ERASE command needs R1B response, so fix R1B-type command handling for SDHCI controller. For non-DAT commands using a busy response, the cmd->cmd_timeout_ms (in ms) field is used for timeout calculations. Based on patch by Chuanxiao Dong <chuanxiao.dong@intel.com> Signed-off-by: Andrei Warkentin <andreiw@motorola.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci-pci: Fix checkpatch.pl errorsAmeya Palande2011-05-241-23/+21
| | | | | | | | | | | | | | | | This patch fixes 21 errors and 6 warnings reported by checkpatch.pl. Signed-off-by: Ameya Palande <2ameya@gmail.com> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: sdhci: change CONFIG of MMC_SDHCI_TEGRA from 'tristate' to 'bool'Shawn Guo2011-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | This config option is used to decide whether tegra sdhci support should be build into the sdhci-platform module. So setting it 'm' is nonsense, since we can't build part of an module as a module. The effect for 'm' will probably be the same as for 'n'. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * mmc: tegra: add pm_flagsVenkat Rao2011-05-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable fast bcm4329 WIFI suspend/resume on Tegra2 board. This patch allows the mach-tegra support to tell the tegra MMC host controller to NOT turn off power for the MMC controller the WIFI part lives behind. Thus bcm4329 firmware doesn't need to be reloaded. Signed-off-by: Venkat Rao <vrao@broadcom.com> Tested-by: Grant Grundler <grundler@chromium.org> Reviewed-by: Olof Johansson <olof@lixom.net> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Chris Ball <cjb@laptop.org>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/brodo/pcmcia-2.6Linus Torvalds2011-05-241-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/brodo/pcmcia-2.6: pcmcia: Make struct pcmcia_device_id const, sound drivers edition staging: pcmcia: Convert pcmcia_device_id declarations to const pcmcia: Convert pcmcia_device_id declarations to const pcmcia: Make declaration and uses of struct pcmcia_device_id const pcmcia/sa1100: put sa11x0_pcmcia_hw_init[] to .devinit.data
| * | pcmcia: Convert pcmcia_device_id declarations to constJoe Perches2011-05-061-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | Saves about 50KB of data. Old/new size of all objects: text data bss dec hex filename 563015 80096 130684 773795 bcea3 (TOTALS) 610916 32256 130632 773804 bceac (TOTALS) Signed-off-by: Joe Perches <joe@perches.com> Acked-by: Kurt Van Dijck <kurt.van.dijck@eia.be> (for drivers/net/can/softing/softing_cs.c) Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net>
* | Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-armLinus Torvalds2011-05-232-16/+31
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (137 commits) ARM: bcmring: convert to use sp804 clockevents ARM: bcmring: convert to sp804 clocksource ARM: 6912/1: bcmring: Add clkdev table in init_early clockevents: ARM sp804: obtain sp804 timer rate via clks clockevents: ARM sp804: allow clockevent name to be specified clocksource: ARM sp804: obtain sp804 timer rate via clks clocksource: ARM sp804: allow clocksource name to be specified clocksource: convert OMAP1 to 32-bit down counting clocksource clocksource: convert MXS timrotv2 to 32-bit down counting clocksource clocksource: convert SPEAr platforms 16-bit up counting clocksource clocksource: convert Integrator/AP 16-bit down counting clocksource clocksource: convert W90x900 24-bit down counting clocksource clocksource: convert ARM 32-bit down counting clocksources clocksource: convert ARM 32-bit up counting clocksources clocksource: add common mmio clocksource ARM: update sa1100 to reflect PXA updates ARM: omap1: convert to using readl/writel instead of volatile struct ARM: omap1: delete useless interrupt handler ARM: s5p: consolidate selection of timer register ARM: 6939/1: fix missing 'cpu_relax()' declaration ...
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| *-----. \ Merge branches 'consolidate', 'ep93xx', 'fixes', 'misc', 'mmci', 'remove' ↵Russell King2011-05-232-16/+31
| |\ \ \ \ \ | | | |_|_|/ | | |/| | | | | | | | | and 'spear' into for-linus
| | | * | | ARM: 6858/1: mmci: force negative edge on clock bypass for ux500Linus Walleij2011-05-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes a regression on high clock speeds with the MMCI on ux500. We need to make sure we derive the passthru clock on the falling edge of the incoming clock if it shall work at high frequencies, and on the ux500's there is a special bit for this. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | * | | ARM: 6785/1: mmci: separate out ST Micro register definesLinus Walleij2011-05-112-16/+29
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mmci.h header contained a few registers not clearly marked as ST Micro only, rectify this and remove the HWFC magic in the process. The idea is to make the mmci.h header file more ordered so other vendors with PL180 derivates can see where to put in their custom register defines. Includes portions of an earlier patch from Sebastian Rasmussen. Acked-by: Sebastian Rasmussen <sebastian.rasmussen@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | | | Merge branch 'for-linus' of ↵Linus Torvalds2011-05-231-1/+1
|\ \ \ \ \ | |/ / / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (39 commits) b43: fix comment typo reqest -> request Haavard Skinnemoen has left Atmel cris: typo in mach-fs Makefile Kconfig: fix copy/paste-ism for dell-wmi-aio driver doc: timers-howto: fix a typo ("unsgined") perf: Only include annotate.h once in tools/perf/util/ui/browsers/annotate.c md, raid5: Fix spelling error in comment ('Ofcourse' --> 'Of course'). treewide: fix a few typos in comments regulator: change debug statement be consistent with the style of the rest Revert "arm: mach-u300/gpio: Fix mem_region resource size miscalculations" audit: acquire creds selectively to reduce atomic op overhead rtlwifi: don't touch with treewide double semicolon removal treewide: cleanup continuations and remove logging message whitespace ath9k_hw: don't touch with treewide double semicolon removal include/linux/leds-regulator.h: fix syntax in example code tty: fix typo in descripton of tty_termios_encode_baud_rate xtensa: remove obsolete BKL kernel option from defconfig m68k: fix comment typo 'occcured' arch:Kconfig.locks Remove unused config option. treewide: remove extra semicolons ...
| * | | | Haavard Skinnemoen has left AtmelJean Delvare2011-05-181-1/+1
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | Haavard's e-mail address at Atmel is no longer valid. Signed-off-by: Jean Delvare <khali@linux-fr.org> Acked-by: Havard Skinnemoen <hskinnemoen@gmail.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* | | | drivercore: revert addition of of_match to struct deviceGrant Likely2011-05-181-2/+5
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit b826291c, "drivercore/dt: add a match table pointer to struct device" added an of_match pointer to struct device to cache the of_match_table entry discovered at driver match time. This was unsafe because matching is not an atomic operation with probing a driver. If two or more drivers are attempted to be matched to a driver at the same time, then the cached matching entry pointer could get overwritten. This patch reverts the of_match cache pointer and reworks all users to call of_match_device() directly instead. Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* | | mmc: sdhci: Check mrq != NULL in sdhci_tasklet_finishChris Ball2011-04-271-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It seems that under certain circumstances the sdhci_tasklet_finish() call can be entered with mrq set to NULL, causing the system to crash with a NULL pointer de-reference. Seen on S3C6410 system. Based on a patch by Dimitris Papastamos. Reported-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> Cc: <stable@kernel.org> Signed-off-by: Chris Ball <cjb@laptop.org>
* | | mmc: sdhci: Check mrq->cmd in sdhci_tasklet_finishBen Dooks2011-04-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It seems that under certain circumstances that the sdhci_tasklet_finish() call can be entered with mrq->cmd set to NULL, causing the system to crash with a NULL pointer de-reference. Unable to handle kernel NULL pointer dereference at virtual address 00000000 PC is at sdhci_tasklet_finish+0x34/0xe8 LR is at sdhci_tasklet_finish+0x24/0xe8 Seen on S3C6410 system. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Cc: <stable@kernel.org> Signed-off-by: Chris Ball <cjb@laptop.org>
* | | mmc: tmio: fix .set_ios(MMC_POWER_UP) handlingGuennadi Liakhovetski2011-04-271-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | The aggressive clock gating for TMIO MMC patch has broken switching interface power on, using MFD or platform callbacks. Restore the ios->power_mode == MMC_POWER_UP && ios->clock == 0 case handling. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Chris Ball <cjb@laptop.org>
* | | mmc: omap: Fix possible NULL pointer derefMichael Buesch2011-04-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Either OMAP_MMC_STAT_CARD_ERR or OMAP_MMC_STAT_END_OF_CMD might fire if there is no host->cmd pointer. Check for a valid host->cmd pointer before calling mmc_omap_cmd_done(). Signed-off-by: Michael Buesch <mb@bu3sch.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Chris Ball <cjb@laptop.org>
* | | mmc: sdhci-pci: Fix error case in sdhci_pci_probe_slot()Chris Ball2011-04-271-0/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | If pci_ioremap_bar() fails during probe, we "goto release;" and free the host, but then we return 0 -- which tells sdhci_pci_probe() that the probe succeeded. Since we think the probe succeeded, when we unload sdhci we'll go to sdhci_pci_remove_slot() and it will try to dereference slot->host, which is now NULL because we freed it in the error path earlier. The patch simply sets ret appropriately, so that sdhci_pci_probe() will detect the failure immediately and bail out. Signed-off-by: Chris Ball <cjb@laptop.org> Cc: <stable@kernel.org>
* | Fix common misspellingsLucas De Marchi2011-03-315-10/+10
| | | | | | | | | | | | Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
* | Merge branch 'for-linus' of ↵Linus Torvalds2011-03-2917-1290/+1650
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cjb/mmc: (26 commits) mmc: SDHI should depend on SUPERH || ARCH_SHMOBILE mmc: tmio_mmc: Move some defines into a shared header mmc: tmio: support aggressive clock gating mmc: tmio: fix power-mode interpretation mmc: tmio: remove work-around for unmasked SDIO interrupts sh: fix SDHI IO address-range ARM: mach-shmobile: fix SDHI IO address-range mmc: tmio: only access registers above 0xff, if available mfd: remove now redundant sh_mobile_sdhi.h header sh: convert boards to use linux/mmc/sh_mobile_sdhi.h ARM: mach-shmobile: convert boards to use linux/mmc/sh_mobile_sdhi.h mmc: tmio: convert the SDHI MMC driver from MFD to a platform driver sh: ecovec: use the CONFIG_MMC_TMIO symbols instead of MFD mmc: tmio: split core functionality, DMA and MFD glue mmc: tmio: use PIO for short transfers mmc: tmio-mmc: Improve DMA stability on sh-mobile mmc: fix mmc_app_send_scr() for dma transfer mmc: sdhci-esdhc: enable esdhc on imx53 mmc: sdhci-esdhc: use writel/readl as general APIs mmc: sdhci: add the abort CMDTYPE bits definition ...
| * | mmc: SDHI should depend on SUPERH || ARCH_SHMOBILEGuennadi Liakhovetski2011-03-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix build breakage on platforms, not providing readsw and writesw functions, e.g., on x86(_64). Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: tmio_mmc: Move some defines into a shared headerSimon Horman2011-03-263-46/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also add TMIO_BBS. This allows these defines to also be used by zboot. Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Simon Horman <horms@verge.net.au> Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: tmio: support aggressive clock gatingGuennadi Liakhovetski2011-03-251-9/+8
| | | | | | | | | | | | | | | | | | Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: tmio: fix power-mode interpretationGuennadi Liakhovetski2011-03-251-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The power-mode sequence on MMC is MMC_POWER_OFF -> MMC_POWER_UP -> MMC_POWER_ON and not MMC_POWER_ON -> MMC_POWER_UP, as the driver currently is implying. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: tmio: remove work-around for unmasked SDIO interruptsGuennadi Liakhovetski2011-03-251-21/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SDIO IRQs got unmasked on sh-mobile while writing to the CTL_CLK_AND_WAIT_CTL register, because that register at address 0x138 is not implemented on those SoCs and writes to it overwrite the register at address 0x38: CTL_SDIO_IRQ_MASK. Previous patches eliminated access to register above 0xff on sh-mobile, so that this work-around isn't needed anymore. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: tmio: only access registers above 0xff, if availableGuennadi Liakhovetski2011-03-251-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Not all tmio implementations have registers above oxff. Accessing them on thise platforms is dangerous. In some cases it leads to address wrapping to addresses below 0x100, which corrupts random unrelated registers. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: tmio: convert the SDHI MMC driver from MFD to a platform driverGuennadi Liakhovetski2011-03-254-4/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On sh-mobile platforms the SDHI driver was using the tmio_mmc SD/SDIO MFD cell driver. Now that the tmio_mmc driver has been split into a core and a separate MFD glue, we can support SDHI natively without the need to emulate an MFD controller. This also allows to support systems with an on-SoC SDHI controller and a separate MFD with a TMIO core. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: tmio: split core functionality, DMA and MFD glueGuennadi Liakhovetski2011-03-256-1285/+1409
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TMIO MMC chips contain an SD / SDIO IP core from Panasonic, similar to the one, used in MN5774 and other MN57xx controllers. These IP cores are included in many multifunction devices, in sh-mobile chips from Renesas, in the latter case they can also use DMA. Some sh-mobile implementations also have some other specialities, that MFD-based solutions don't have. This makes supporting all these features in a monolithic driver inconveniet and error-prone. This patch splits the driver into 3 parts: the core, the MFD glue and the DMA support. In case of a modular build, two modules will be built: mmc_tmio_core and mmc_tmio. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: tmio: use PIO for short transfersGuennadi Liakhovetski2011-03-251-10/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows transferring of some requests in PIO and some in DMA mode and defaults to using DMA only for transfers longer than 8 bytes. This is especially useful with SDIO, which can have lots of 2- and 4-byte transfers, creating unnecessary high overhead, when executed in DMA. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: tmio-mmc: Improve DMA stability on sh-mobileGuennadi Liakhovetski2011-03-251-29/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On some SDHI tmio implementations the order of DMA and command completion interrupts swaps, which leads to malfunction. This patch postpones DMA activation until the MMC command completion IRQ time. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: sdhci-esdhc: enable esdhc on imx53Richard Zhu2011-03-251-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the NO INT in the Multi-BLK IO in SD/MMC, and Multi-BLK read in SDIO on imx53. The CMDTYPE of the CMD register (offset 0xE) should be set to "11" when the STOP CMD12 is issued on imx53 to abort one open ended multi-blk IO. Otherwise the TC INT wouldn't be generated. In exact block transfer, the controller doesn't complete the operations automatically as required at the end of the transfer and remains on hold if the abort command is not sent on imx53. As a result, the TC flag is not asserted and SW receives timeout exception. Set bit1 of Vendor Spec register to fix it. Signed-off-by: Richard Zhu <Hong-Xing.Zhu@freescale.com> Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: sdhci-esdhc: use writel/readl as general APIsRichard Zhu2011-03-252-8/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add one flag to indicate the GPIO CD/WP is enabled or not on imx platforms, and reuse the writel/readl as the general APIs for imx SOCs. Signed-off-by: Richard Zhu <Hong-Xing.Zhu@freescale.com> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: sdhci: add the abort CMDTYPE bits definitionRichard Zhu2011-03-251-0/+1
| | | | | | | | | | | | | | | | | | | | | Add the abort CMDTYPE bits definition of command register (offset 0xE) Signed-off-by: Richard Zhu <Hong-Xing.Zhu@freescale.com> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: sdhci-esdhc: remove SDHCI_QUIRK_NO_CARD_NO_RESET from esdhcRichard Zhu2011-03-252-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | sdhci-esdhc-imx does not need SDHCI_QUIRK_NO_CARD_NO_RESET. Make it OF-specific. Signed-off-by: Richard Zhu <Hong-Xing.Zhu@freescale.com> Tested-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: of_mmc_spi: Need to include irq.h and of_irq.hDavid Miller2011-03-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since these are the headers that provide irq_of_parse_and_map() and NO_IRQ. Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: mmci: Add ARM variant with extended FIFOPawel Moll2011-03-251-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New IO FPGA implementation for Versatile Express boards contain MMCI (PL180) cell with FIFO extended to 128 words (512 bytes). Matt Waddel reports that this patch improves MMC performance on his vexpress system, and also fixes "mmcblk0: error -5 transferring data" errors. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Tested-by: Matt Waddel <matt.waddel@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
| * | mmc: dw_mmc: set fixed burst in BMOD registerJaehoon Chung2011-03-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses the fixed burst bit when using an internal DMA controller. I found increased performance with IDMAC when this bit is set. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Chris Ball <cjb@laptop.org>
generated by cgit v1.1 at 2025-02-09 09:38:12 +0000