From 6ca05ee11f3da9484c5323aeaec7cee540af70ed Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 27 Apr 2009 13:17:47 -0500 Subject: powerpc/85xx: Add binding for LAWs and ECM The first 4k region of CCSR space is well defined for local access windows, CCSRBAR, etc. The second 4k region is well defined as register for configuring and getting errors for the ECM coherency module. Signed-off-by: Kumar Gala --- Documentation/powerpc/dts-bindings/ecm.txt | 64 ++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/powerpc/dts-bindings/ecm.txt (limited to 'Documentation/powerpc') diff --git a/Documentation/powerpc/dts-bindings/ecm.txt b/Documentation/powerpc/dts-bindings/ecm.txt new file mode 100644 index 0000000..f514f29 --- /dev/null +++ b/Documentation/powerpc/dts-bindings/ecm.txt @@ -0,0 +1,64 @@ +===================================================================== +E500 LAW & Coherency Module Device Tree Binding +Copyright (C) 2009 Freescale Semiconductor Inc. +===================================================================== + +Local Access Window (LAW) Node + +The LAW node represents the region of CCSR space where local access +windows are configured. For ECM based devices this is the first 4k +of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some +number of local access windows as specified by fsl,num-laws. + +PROPERTIES + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,ecm-law" + + - reg + Usage: required + Value type: + Definition: A standard property. The value specifies the + physical address offset and length of the CCSR space + registers. + + - fsl,num-laws + Usage: required + Value type: + Definition: The value specifies the number of local access + windows for this device. + +===================================================================== + +E500 Coherency Module Node + +The E500 LAW node represents the region of CCSR space where ECM config +and error reporting registers exist, this is the second 4k (0x1000) +of CCSR space. + +PROPERTIES + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,CHIP-ecm", "fsl,ecm" where + CHIP is the processor (mpc8572, mpc8544, etc.) + + - reg + Usage: required + Value type: + Definition: A standard property. The value specifies the + physical address offset and length of the CCSR space + registers. + + - interrupts + Usage: required + Value type: + + - interrupt-parent + Usage: required + Value type: + +===================================================================== -- cgit v1.1 From 5a928079c9b95e7c34526b07a3bb80b8d062347f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Wed, 22 Apr 2009 13:12:14 -0500 Subject: powerpc/86xx: Add binding for LAWs and MCM The first 4k region of CCSR space is well defined for local access windows, CCSRBAR, etc. The second 4k region is well defined as register for configuring and getting errors for the MPX coherency module. Signed-off-by: Kumar Gala --- Documentation/powerpc/dts-bindings/fsl/mcm.txt | 64 ++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 Documentation/powerpc/dts-bindings/fsl/mcm.txt (limited to 'Documentation/powerpc') diff --git a/Documentation/powerpc/dts-bindings/fsl/mcm.txt b/Documentation/powerpc/dts-bindings/fsl/mcm.txt new file mode 100644 index 0000000..4ceda9b --- /dev/null +++ b/Documentation/powerpc/dts-bindings/fsl/mcm.txt @@ -0,0 +1,64 @@ +===================================================================== +MPX LAW & Coherency Module Device Tree Binding +Copyright (C) 2009 Freescale Semiconductor Inc. +===================================================================== + +Local Access Window (LAW) Node + +The LAW node represents the region of CCSR space where local access +windows are configured. For MCM based devices this is the first 4k +of CCSR space that includes CCSRBAR, ALTCBAR, ALTCAR, BPTR, and some +number of local access windows as specified by fsl,num-laws. + +PROPERTIES + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,mcm-law" + + - reg + Usage: required + Value type: + Definition: A standard property. The value specifies the + physical address offset and length of the CCSR space + registers. + + - fsl,num-laws + Usage: required + Value type: + Definition: The value specifies the number of local access + windows for this device. + +===================================================================== + +MPX Coherency Module Node + +The MPX LAW node represents the region of CCSR space where MCM config +and error reporting registers exist, this is the second 4k (0x1000) +of CCSR space. + +PROPERTIES + + - compatible + Usage: required + Value type: + Definition: Must include "fsl,CHIP-mcm", "fsl,mcm" where + CHIP is the processor (mpc8641, mpc8610, etc.) + + - reg + Usage: required + Value type: + Definition: A standard property. The value specifies the + physical address offset and length of the CCSR space + registers. + + - interrupts + Usage: required + Value type: + + - interrupt-parent + Usage: required + Value type: + +===================================================================== -- cgit v1.1 From 06c4435021f4856261edd01e2691071edeb8fa51 Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 1 May 2009 15:40:47 -0400 Subject: powerpc/qe: update risc allocation for QE Change the RISC allocation to macros instead of enum, add function to read the number of risc engines from the new property "fsl,qe-num-riscs" under the qe node in dts. Add new property "fsl,qe-num-riscs" description in qe.txt Signed-off-by: Haiying Wang Acked-by: Timur Tabi Signed-off-by: Kumar Gala --- Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation/powerpc') diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt index 78790d5..39b5d1f 100644 --- a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt +++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt @@ -17,6 +17,7 @@ Required properties: - model : precise model of the QE, Can be "QE", "CPM", or "CPM2" - reg : offset and length of the device registers. - bus-frequency : the clock frequency for QUICC Engine. +- fsl,qe-num-riscs: define how many RISC engines the QE has. Recommended properties - brg-frequency : the internal clock source frequency for baud-rate -- cgit v1.1 From 98ca77af23da6682bb3e34961a3f32e2c064a4ce Mon Sep 17 00:00:00 2001 From: Haiying Wang Date: Fri, 1 May 2009 15:40:48 -0400 Subject: powerpc/qe: update QE Serial Number The latest QE chip may have more Serial Number(SNUM)s of thread to use. We will get the number of SNUMs from device tree by reading the new property "fsl,qe-num-snums", and set 28 as the default number of SNUMs so that it is compatible with the old QE chips' device trees which don't have this new property. The macro QE_NUM_OF_SNUM is defined as the maximum number in QE snum table which is 256. Also we update the snum_init[] array with 18 more new SNUMs which are confirmed to be useful on new chip. Signed-off-by: Haiying Wang Acked-by: Timur Tabi Signed-off-by: Kumar Gala --- Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt | 2 ++ 1 file changed, 2 insertions(+) (limited to 'Documentation/powerpc') diff --git a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt index 39b5d1f..6e37be1 100644 --- a/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt +++ b/Documentation/powerpc/dts-bindings/fsl/cpm_qe/qe.txt @@ -18,6 +18,8 @@ Required properties: - reg : offset and length of the device registers. - bus-frequency : the clock frequency for QUICC Engine. - fsl,qe-num-riscs: define how many RISC engines the QE has. +- fsl,qe-num-snums: define how many serial number(SNUM) the QE can use for the + threads. Recommended properties - brg-frequency : the internal clock source frequency for baud-rate -- cgit v1.1 From 404614728f857d0ac63d29c3a29d0cf392a15598 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 8 May 2009 08:47:45 -0500 Subject: powerpc/fsl: Update FSL esdhc binding Updated the binding spec to use "fsl,eshdc" as the base compatible rather than the first chip in the family. Signed-off-by: Kumar Gala --- Documentation/powerpc/dts-bindings/fsl/esdhc.txt | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'Documentation/powerpc') diff --git a/Documentation/powerpc/dts-bindings/fsl/esdhc.txt b/Documentation/powerpc/dts-bindings/fsl/esdhc.txt index 6008465..5093ddf 100644 --- a/Documentation/powerpc/dts-bindings/fsl/esdhc.txt +++ b/Documentation/powerpc/dts-bindings/fsl/esdhc.txt @@ -5,8 +5,7 @@ for MMC, SD, and SDIO types of memory cards. Required properties: - compatible : should be - "fsl,-esdhc", "fsl,mpc8379-esdhc" for MPC83xx processors. - "fsl,-esdhc", "fsl,mpc8536-esdhc" for MPC85xx processors. + "fsl,-esdhc", "fsl,esdhc" - reg : should contain eSDHC registers location and length. - interrupts : should contain eSDHC interrupt. - interrupt-parent : interrupt source phandle. @@ -15,7 +14,7 @@ Required properties: Example: sdhci@2e000 { - compatible = "fsl,mpc8378-esdhc", "fsl,mpc8379-esdhc"; + compatible = "fsl,mpc8378-esdhc", "fsl,esdhc"; reg = <0x2e000 0x1000>; interrupts = <42 0x8>; interrupt-parent = <&ipic>; -- cgit v1.1