From ff2e27ae0b17f53a6a289c87d325f706598f3788 Mon Sep 17 00:00:00 2001 From: Russell King Date: Sat, 4 Dec 2010 16:13:29 +0000 Subject: ARM: GIC: consolidate gic_cpu_base_addr to common GIC code Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: Catalin Marinas Tested-by: Abhijeet Dharmapurikar Signed-off-by: Russell King --- arch/arm/mach-s5pv310/cpu.c | 3 --- arch/arm/mach-s5pv310/include/mach/smp.h | 2 -- 2 files changed, 5 deletions(-) (limited to 'arch/arm/mach-s5pv310') diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c index bce3e91..72ab289 100644 --- a/arch/arm/mach-s5pv310/cpu.c +++ b/arch/arm/mach-s5pv310/cpu.c @@ -24,8 +24,6 @@ #include -void __iomem *gic_cpu_base_addr; - extern int combiner_init(unsigned int combiner_nr, void __iomem *base, unsigned int irq_start); extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq); @@ -122,7 +120,6 @@ void __init s5pv310_init_irq(void) { int irq; - gic_cpu_base_addr = S5P_VA_GIC_CPU; gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); for (irq = 0; irq < MAX_COMBINER_NR; irq++) { diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h index b7ec252..e1cc6a2 100644 --- a/arch/arm/mach-s5pv310/include/mach/smp.h +++ b/arch/arm/mach-s5pv310/include/mach/smp.h @@ -9,8 +9,6 @@ #include #include -extern void __iomem *gic_cpu_base_addr; - /* * We use IRQ1 as the IPI */ -- cgit v1.1