From a7cb03375d794d3494561bbad90aeab13ff7e4d0 Mon Sep 17 00:00:00 2001 From: Becky Bruce Date: Wed, 8 Feb 2006 16:41:26 -0600 Subject: [PATCH] powerpc/ppc: Add missing isyncs in head_fsl_booke.S The e500 core reference manual indicates that isync is required after mtmsr(DE bit) and mtspr DBCR0. Add isyncs to make the code conform to the spec. Signed-off-by: Becky Bruce Signed-off-by: Kumar Gala Signed-off-by: Paul Mackerras --- arch/ppc/kernel/head_fsl_booke.S | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/ppc') diff --git a/arch/ppc/kernel/head_fsl_booke.S b/arch/ppc/kernel/head_fsl_booke.S index 8d60fa9..0abd05f 100644 --- a/arch/ppc/kernel/head_fsl_booke.S +++ b/arch/ppc/kernel/head_fsl_booke.S @@ -316,6 +316,7 @@ skpinv: addi r6,r6,1 /* Increment */ */ lis r2,DBCR0_IDM@h mtspr SPRN_DBCR0,r2 + isync /* clear any residual debug events */ li r2,-1 mtspr SPRN_DBSR,r2 @@ -1002,12 +1003,15 @@ _GLOBAL(giveup_fpu) _GLOBAL(abort) li r13,0 mtspr SPRN_DBCR0,r13 /* disable all debug events */ + isync mfmsr r13 ori r13,r13,MSR_DE@l /* Enable Debug Events */ mtmsr r13 + isync mfspr r13,SPRN_DBCR0 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h mtspr SPRN_DBCR0,r13 + isync _GLOBAL(set_context) -- cgit v1.1