From 1f39847255a02c69190ae30c33b8ccf4c10840df Mon Sep 17 00:00:00 2001 From: Mark Lord Date: Tue, 27 May 2008 17:54:48 -0400 Subject: sata_mv: move SOC_FLAG to hpriv Convert the System-on-Chip flag from a host flag to an hpriv flag, for better consistency with other chip-rev flags, and for easier use in errata fixes etc. Also change the related "HAS_PCI()" into "!IS_SOC()" for better consistency of naming/use (everything else SOC-related already uses "SOC"). There are no functionality changes in this patch. Signed-off-by: Mark Lord Signed-off-by: Jeff Garzik --- drivers/ata/sata_mv.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) (limited to 'drivers/ata/sata_mv.c') diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index fb81f0c..f6a716e 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -122,8 +122,6 @@ enum { /* Host Flags */ MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */ - /* SoC integrated controllers, no PCI interface */ - MV_FLAG_SOC = (1 << 28), MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI | @@ -362,6 +360,7 @@ enum { MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ + MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ /* Port private flags (pp_flags) */ MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ @@ -374,7 +373,7 @@ enum { #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) -#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC)) +#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) #define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) #define WINDOW_BASE(i) (0x20034 + ((i) << 4)) @@ -652,7 +651,7 @@ static const struct ata_port_info mv_port_info[] = { .port_ops = &mv_iie_ops, }, { /* chip_soc */ - .flags = MV_GENIIE_FLAGS | MV_FLAG_SOC, + .flags = MV_GENIIE_FLAGS, .pio_mask = 0x1f, /* pio0-4 */ .udma_mask = ATA_UDMA6, .port_ops = &mv_iie_ops, @@ -1254,7 +1253,7 @@ static void mv_edma_cfg(struct ata_port *ap, int want_ncq) cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ cfg |= (1 << 22); /* enab 4-entry host queue cache */ - if (HAS_PCI(ap->host)) + if (!IS_SOC(hpriv)) cfg |= (1 << 18); /* enab early completion */ if (hpriv->hp_flags & MV_HP_CUT_THROUGH) cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ @@ -2225,7 +2224,7 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance) * a bogus register value which can indicate HW removal or PCI fault. */ if (pending_irqs && main_irq_cause != 0xffffffffU) { - if (unlikely((pending_irqs & PCI_ERR) && HAS_PCI(host))) + if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) handled = mv_pci_error(host, hpriv->base); else handled = mv_host_intr(host, pending_irqs); @@ -2876,7 +2875,7 @@ static unsigned int mv_in_pcix_mode(struct ata_host *host) void __iomem *mmio = hpriv->base; u32 reg; - if (!HAS_PCI(host) || !IS_PCIE(hpriv)) + if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) return 0; /* not PCI-X capable */ reg = readl(mmio + MV_PCI_MODE_OFS); if ((reg & MV_PCI_MODE_MASK) == 0) @@ -3018,7 +3017,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx) break; case chip_soc: hpriv->ops = &mv_soc_ops; - hp_flags |= MV_HP_ERRATA_60X1C0; + hp_flags |= MV_HP_FLAG_SOC | MV_HP_ERRATA_60X1C0; break; default: @@ -3062,12 +3061,12 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx) if (rc) goto done; - if (HAS_PCI(host)) { - hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS; - hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS; - } else { + if (IS_SOC(hpriv)) { hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS; hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS; + } else { + hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS; + hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS; } /* global interrupt mask: 0 == mask everything */ @@ -3093,7 +3092,7 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx) mv_port_init(&ap->ioaddr, port_mmio); #ifdef CONFIG_PCI - if (HAS_PCI(host)) { + if (!IS_SOC(hpriv)) { unsigned int offset = port_mmio - mmio; ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); @@ -3113,7 +3112,7 @@ static int mv_init_host(struct ata_host *host, unsigned int board_idx) writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS); } - if (HAS_PCI(host)) { + if (!IS_SOC(hpriv)) { /* Clear any currently outstanding host interrupt conditions */ writelfl(0, mmio + hpriv->irq_cause_ofs); -- cgit v1.1 From 8c30a8b9b574cf6c51e207464b852a6f559da153 Mon Sep 17 00:00:00 2001 From: Mark Lord Date: Tue, 27 May 2008 17:56:31 -0400 Subject: sata_mv: PHY_MODEx errata fixes Fix and update the errata handling for the PHY_MODEx registers. This improves receiver noise tolerance, among other things. Signed-off-by: Mark Lord Signed-off-by: Jeff Garzik --- drivers/ata/sata_mv.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'drivers/ata/sata_mv.c') diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index f6a716e..a39779a 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -2546,7 +2546,7 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); int fix_phy_mode4 = hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); - u32 m2, tmp; + u32 m2, m3; if (fix_phy_mode2) { m2 = readl(port_mmio + PHY_MODE2); @@ -2563,27 +2563,27 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, udelay(200); } - /* who knows what this magic does */ - tmp = readl(port_mmio + PHY_MODE3); - tmp &= ~0x7F800000; - tmp |= 0x2A800000; - writel(tmp, port_mmio + PHY_MODE3); + /* + * Gen-II/IIe PHY_MODE3 errata RM#2: + * Achieves better receiver noise performance than the h/w default: + */ + m3 = readl(port_mmio + PHY_MODE3); + m3 = (m3 & 0x1f) | (0x5555601 << 5); + writel(m3, port_mmio + PHY_MODE3); if (fix_phy_mode4) { u32 m4; m4 = readl(port_mmio + PHY_MODE4); - if (hp_flags & MV_HP_ERRATA_60X1B2) - tmp = readl(port_mmio + PHY_MODE3); - /* workaround for errata FEr SATA#10 (part 1) */ m4 = (m4 & ~(1 << 1)) | (1 << 0); - writel(m4, port_mmio + PHY_MODE4); + /* enforce bit restrictions on GenIIe devices */ + if (IS_GEN_IIE(hpriv)) + m4 = (m4 & ~0x5DE3FFFC) | (1 << 2); - if (hp_flags & MV_HP_ERRATA_60X1B2) - writel(tmp, port_mmio + PHY_MODE3); + writel(m4, port_mmio + PHY_MODE4); } /* Revert values of pre-emphasis and signal amps to the saved ones */ -- cgit v1.1 From 5cf73bfb061552aa18d816d2859409be9ace5306 Mon Sep 17 00:00:00 2001 From: Mark Lord Date: Tue, 27 May 2008 17:58:56 -0400 Subject: sata_mv: nuke unreleased GenIIe revisions The only public release of the 6042/7042 chips was/is revision "B0". Remove code that attempted to deal with earlier, non-released revs. This matches the logic of the current Marvell "proprietary" driver. Also, bump up the sata_mv version number, to reflect this batch of erratas. Signed-off-by: Mark Lord Signed-off-by: Jeff Garzik --- drivers/ata/sata_mv.c | 23 ++++------------------- 1 file changed, 4 insertions(+), 19 deletions(-) (limited to 'drivers/ata/sata_mv.c') diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index a39779a..969a769 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -72,7 +72,7 @@ #include #define DRV_NAME "sata_mv" -#define DRV_VERSION "1.21" +#define DRV_VERSION "1.22" enum { /* BAR's are enumerated in terms of pci_resource_start() terms */ @@ -354,7 +354,6 @@ enum { MV_HP_ERRATA_50XXB2 = (1 << 2), MV_HP_ERRATA_60X1B2 = (1 << 3), MV_HP_ERRATA_60X1C0 = (1 << 4), - MV_HP_ERRATA_XX42A0 = (1 << 5), MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ @@ -811,12 +810,7 @@ static void mv_set_edma_ptrs(void __iomem *port_mmio, writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS); writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, port_mmio + EDMA_REQ_Q_IN_PTR_OFS); - - if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) - writelfl((pp->crqb_dma & 0xffffffff) | index, - port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); - else - writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); + writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS); /* * initialize response queue @@ -826,13 +820,7 @@ static void mv_set_edma_ptrs(void __iomem *port_mmio, WARN_ON(pp->crpb_dma & 0xff); writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS); - - if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0) - writelfl((pp->crpb_dma & 0xffffffff) | index, - port_mmio + EDMA_RSP_Q_IN_PTR_OFS); - else - writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); - + writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS); writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS); } @@ -3002,10 +2990,7 @@ static int mv_chip_id(struct ata_host *host, unsigned int board_idx) hp_flags |= MV_HP_CUT_THROUGH; switch (pdev->revision) { - case 0x0: - hp_flags |= MV_HP_ERRATA_XX42A0; - break; - case 0x1: + case 0x2: /* Rev.B0: the first/only public release */ hp_flags |= MV_HP_ERRATA_60X1C0; break; default: -- cgit v1.1 From b406c7a6655da7a2fcd9f72e41262f93ff707748 Mon Sep 17 00:00:00 2001 From: Mark Lord Date: Wed, 28 May 2008 12:01:12 -0400 Subject: sata_mv: workaround for 60x1 errata sata13 The "B2" variant of the 6041/6081 (genII) chips requires that the PHY_MODE3 register be rewritten after any write to PHY_MODE4. This fixes a regression introduced by an earlier patch. Signed-off-by: Mark Lord Signed-off-by: Jeff Garzik --- drivers/ata/sata_mv.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers/ata/sata_mv.c') diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index 969a769..17093e6 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -72,7 +72,7 @@ #include #define DRV_NAME "sata_mv" -#define DRV_VERSION "1.22" +#define DRV_VERSION "1.23" enum { /* BAR's are enumerated in terms of pci_resource_start() terms */ @@ -2557,7 +2557,6 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, */ m3 = readl(port_mmio + PHY_MODE3); m3 = (m3 & 0x1f) | (0x5555601 << 5); - writel(m3, port_mmio + PHY_MODE3); if (fix_phy_mode4) { u32 m4; @@ -2573,6 +2572,12 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, writel(m4, port_mmio + PHY_MODE4); } + /* + * Workaround for 60x1-B2 errata SATA#13: + * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, + * so we must always rewrite PHY_MODE3 after PHY_MODE4. + */ + writel(m3, port_mmio + PHY_MODE3); /* Revert values of pre-emphasis and signal amps to the saved ones */ m2 = readl(port_mmio + PHY_MODE2); -- cgit v1.1 From 0388a8c0d54aa039758a8eca68d82325a563f8db Mon Sep 17 00:00:00 2001 From: Mark Lord Date: Wed, 28 May 2008 13:41:52 -0400 Subject: sata_mv: implement SoC guideline SATA_S11 The 5182 System-On-Chip (SOC) variant wants certain lower bits to be cleared on any write to the PHY_MODE3 register. If/when support is added for other SOC variants, we'll need some way to uniquely identify the 5182, and not perform this workaround for the others. But for now, it is the only SOC variant we support here. Signed-off-by: Mark Lord Signed-off-by: Jeff Garzik --- drivers/ata/sata_mv.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'drivers/ata/sata_mv.c') diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index 17093e6..acf347f 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -72,7 +72,7 @@ #include #define DRV_NAME "sata_mv" -#define DRV_VERSION "1.23" +#define DRV_VERSION "1.24" enum { /* BAR's are enumerated in terms of pci_resource_start() terms */ @@ -2558,6 +2558,10 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, m3 = readl(port_mmio + PHY_MODE3); m3 = (m3 & 0x1f) | (0x5555601 << 5); + /* Guideline 88F5182 (GL# SATA-S11) */ + if (IS_SOC(hpriv)) + m3 &= ~0x1c; + if (fix_phy_mode4) { u32 m4; -- cgit v1.1 From ba069e376cc0801cd28352ca5986ce20413acb21 Mon Sep 17 00:00:00 2001 From: Mark Lord Date: Sat, 31 May 2008 16:46:34 -0400 Subject: sata_mv: PHY_MODE4 cleanups The handling for PHY_MODE4 was originally just cloned from the Marvell proprietary driver (with their blessing). But we can do better than that. Tidy things up with some judicious mask definitions, to improve maintainability. Signed-off-by: Mark Lord Signed-off-by: Jeff Garzik --- drivers/ata/sata_mv.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) (limited to 'drivers/ata/sata_mv.c') diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index acf347f..60391e9 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -224,6 +224,11 @@ enum { PHY_MODE3 = 0x310, PHY_MODE4 = 0x314, + PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ + PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ + PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ + PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ + PHY_MODE2 = 0x330, SATA_IFCTL_OFS = 0x344, SATA_TESTCTL_OFS = 0x348, @@ -2563,17 +2568,16 @@ static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, m3 &= ~0x1c; if (fix_phy_mode4) { - u32 m4; - - m4 = readl(port_mmio + PHY_MODE4); - - /* workaround for errata FEr SATA#10 (part 1) */ - m4 = (m4 & ~(1 << 1)) | (1 << 0); - - /* enforce bit restrictions on GenIIe devices */ + u32 m4 = readl(port_mmio + PHY_MODE4); + /* + * Enforce reserved-bit restrictions on GenIIe devices only. + * For earlier chipsets, force only the internal config field + * (workaround for errata FEr SATA#10 part 1). + */ if (IS_GEN_IIE(hpriv)) - m4 = (m4 & ~0x5DE3FFFC) | (1 << 2); - + m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; + else + m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; writel(m4, port_mmio + PHY_MODE4); } /* -- cgit v1.1 From 3bd0a70ee9cc30ae81b39cb5ecad0fa7bcb4675b Mon Sep 17 00:00:00 2001 From: Mark Lord Date: Wed, 18 Jun 2008 12:11:16 -0400 Subject: sata_mv: enable async_notify for 60x1 Rev.C0 and higher The early chipsets cannot safely handle Async Notification (AN), but 6041/6081 chip revision "C0" (and newer) can handle it. So allow AN for "C0" and higher. This enables use of hotplug on PMP ports for the 6041/6081 PCI Rev.9 chips. Signed-off-by: Mark Lord Signed-off-by: Jeff Garzik --- drivers/ata/sata_mv.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/ata/sata_mv.c') diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index 60391e9..75fde48 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -1322,6 +1322,9 @@ static int mv_port_start(struct ata_port *ap) goto out_port_free_dma_mem; memset(pp->crpb, 0, MV_CRPB_Q_SZ); + /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ + if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) + ap->flags |= ATA_FLAG_AN; /* * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. * For later hardware, we need one unique sg_tbl per NCQ tag. -- cgit v1.1 From c6112bd86bc8f727bb732a47f2133e0ff12beda9 Mon Sep 17 00:00:00 2001 From: Mark Lord Date: Wed, 18 Jun 2008 12:13:02 -0400 Subject: sata_mv: warn on PIO with multiple DRQs Chip errata sometimes prevents reliable use of PIO commands which involve more than a single DRQ (data request). In normal operation, libata should not generate such PIO commands (uses DMA instead), but they could be sent in via SG_IO from userspace. A full workaround might be to break up such commands into sequences of single DRQ ones, but that's just way too complex for something that doesn't normally happen in real life. So, allow the attempt (it often works, despite the errata), but log the event for reference when somebody screams. Signed-off-by: Mark Lord Signed-off-by: Jeff Garzik --- drivers/ata/sata_mv.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'drivers/ata/sata_mv.c') diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index 75fde48..28092bc 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c @@ -1595,6 +1595,24 @@ static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) if ((qc->tf.protocol != ATA_PROT_DMA) && (qc->tf.protocol != ATA_PROT_NCQ)) { + static int limit_warnings = 10; + /* + * Errata SATA#16, SATA#24: warn if multiple DRQs expected. + * + * Someday, we might implement special polling workarounds + * for these, but it all seems rather unnecessary since we + * normally use only DMA for commands which transfer more + * than a single block of data. + * + * Much of the time, this could just work regardless. + * So for now, just log the incident, and allow the attempt. + */ + if (limit_warnings && (qc->nbytes / qc->sect_size) > 1) { + --limit_warnings; + ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME + ": attempting PIO w/multiple DRQ: " + "this may fail due to h/w errata\n"); + } /* * We're about to send a non-EDMA capable command to the * port. Turn off EDMA so there won't be problems accessing -- cgit v1.1