From 16fef5c05c2f1eee93546842c6d8377c2a1134cd Mon Sep 17 00:00:00 2001 From: Charulatha V Date: Fri, 3 Jun 2011 23:31:58 +0530 Subject: GPIO: OMAP: Fix use of readl/readw to access isr_reg In gpio_irq_handler, isr register is always accessed as 32 bit register and only for OMAP15xx the first 16 MSBs are masked. Correct this by using the appropriate readl/readw registers as per the bank width. Signed-off-by: Charulatha V --- drivers/gpio/gpio-omap.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers/gpio') diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 7d578e8..90a107a 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -583,10 +583,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) u32 enabled; enabled = _get_gpio_irqbank_mask(bank); - isr_saved = isr = __raw_readl(isr_reg) & enabled; - if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) - isr &= 0x0000ffff; + if (bank->width == 32) + isr = __raw_readl(isr_reg) & enabled; + else if (bank->width == 16) + isr = (__raw_readw(isr_reg) & enabled) & 0x0000ffff; + isr_saved = isr; if (bank->regs->leveldetect0) level_mask = bank->level_mask & enabled; -- cgit v1.1