From f40bc560ada309d036c3261d93ac8f9b01daf713 Mon Sep 17 00:00:00 2001
From: Rodrigo Obregon <robregon@ti.com>
Date: Tue, 21 Dec 2010 17:50:40 -0600
Subject: OMAP4: SGX-KM: Update DDK version to 1.6.16.4061
This patch updates the DDK to version 1.6.16.4061
The corresponding change in the user side most be
in place for this DDK to work.
Change-Id: I0e3ffff29506115fac5b215b1020d20559ee1853
Signed-off-by: Rodrigo Obregon <robregon@ti.com>
---
drivers/gpu/pvr/sgx/sgxconfig.h | 19 +++--
drivers/gpu/pvr/sgx/sgxinit.c | 145 +++++++++++++++++++-------------------
drivers/gpu/pvr/sgx/sgxkick.c | 2 +-
drivers/gpu/pvr/sgx/sgxpower.c | 10 +--
drivers/gpu/pvr/sgx/sgxreset.c | 10 ++-
drivers/gpu/pvr/sgx/sgxtransfer.c | 58 +++++++--------
drivers/gpu/pvr/sgx/sgxutils.c | 92 +++++++++++++-----------
drivers/gpu/pvr/sgx/sgxutils.h | 8 ++-
8 files changed, 186 insertions(+), 158 deletions(-)
(limited to 'drivers/gpu/pvr/sgx')
diff --git a/drivers/gpu/pvr/sgx/sgxconfig.h b/drivers/gpu/pvr/sgx/sgxconfig.h
index a0ca3e9..6d9d077 100644
--- a/drivers/gpu/pvr/sgx/sgxconfig.h
+++ b/drivers/gpu/pvr/sgx/sgxconfig.h
@@ -82,19 +82,24 @@
#define SGX_VERTEXSHADER_HEAP_BASE 0xFE000000
#define SGX_VERTEXSHADER_HEAP_SIZE (0x02000000-0x00001000)
-
+
#define SGX_CORE_IDENTIFIED
-#endif
+#endif
#if SGX_FEATURE_ADDRESS_SPACE_SIZE == 28
- #if defined(SUPPORT_SGX_GENERAL_MAPPING_HEAP)
+
+#if defined(SUPPORT_SGX_GENERAL_MAPPING_HEAP)
#define SGX_GENERAL_MAPPING_HEAP_BASE 0x00001000
#define SGX_GENERAL_MAPPING_HEAP_SIZE (0x01800000-0x00001000-0x00001000)
- #endif
-
+
#define SGX_GENERAL_HEAP_BASE 0x01800000
#define SGX_GENERAL_HEAP_SIZE (0x07000000-0x00001000)
+#else
+ #define SGX_GENERAL_HEAP_BASE 0x00001000
+ #define SGX_GENERAL_HEAP_SIZE (0x08800000-0x00001000-0x00001000)
+#endif
+
#define SGX_3DPARAMETERS_HEAP_BASE 0x08800000
#define SGX_3DPARAMETERS_HEAP_SIZE (0x04000000-0x00001000)
@@ -122,10 +127,10 @@
#define SGX_VERTEXSHADER_HEAP_BASE 0x0FC00000
#define SGX_VERTEXSHADER_HEAP_SIZE (0x00200000-0x00001000)
-
+
#define SGX_CORE_IDENTIFIED
-#endif
+#endif
#if !defined(SGX_CORE_IDENTIFIED)
#error "sgxconfig.h: ERROR: unspecified SGX Core version"
diff --git a/drivers/gpu/pvr/sgx/sgxinit.c b/drivers/gpu/pvr/sgx/sgxinit.c
index f822eb8..3872102 100644
--- a/drivers/gpu/pvr/sgx/sgxinit.c
+++ b/drivers/gpu/pvr/sgx/sgxinit.c
@@ -379,18 +379,19 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
PDUMP_FLAGS_CONTINUOUS,
MAKEUNIQUETAG(psDevInfo->psKernelCCBEventKickerMemInfo));
PDUMPREG(SGX_PDUMPREG_NAME, SGX_MP_CORE_SELECT(EUR_CR_EVENT_KICK, 0), EUR_CR_EVENT_KICK_NOW_MASK);
-#endif
+#endif
}
-#endif
+#endif
#if !defined(NO_HARDWARE)
-
+
if (PollForValueKM(&psSGXHostCtl->ui32InitStatus,
PVRSRV_USSE_EDM_INIT_COMPLETE,
PVRSRV_USSE_EDM_INIT_COMPLETE,
+ MAX_HW_TIME_US,
MAX_HW_TIME_US/WAIT_TRY_COUNT,
- WAIT_TRY_COUNT) != PVRSRV_OK)
+ IMG_FALSE) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR, "SGXInitialise: Wait for uKernel initialisation failed"));
#if !defined(FIX_HW_BRN_23281)
@@ -398,7 +399,7 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
#endif
return PVRSRV_ERROR_RETRY;
}
-#endif
+#endif
#if defined(PDUMP)
PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
@@ -410,19 +411,19 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
PDUMP_POLL_OPERATOR_EQUAL,
PDUMP_FLAGS_CONTINUOUS,
MAKEUNIQUETAG(psSGXHostCtlMemInfo));
-#endif
+#endif
#if defined(FIX_HW_BRN_22997) && defined(FIX_HW_BRN_23030) && defined(SGX_FEATURE_HOST_PORT)
-
+
WorkaroundBRN22997ReadHostPort(psDevInfo);
-#endif
+#endif
PVR_ASSERT(psDevInfo->psKernelCCBCtl->ui32ReadOffset == psDevInfo->psKernelCCBCtl->ui32WriteOffset);
bFirstTime = IMG_FALSE;
-
+
return PVRSRV_OK;
}
@@ -432,7 +433,7 @@ PVRSRV_ERROR SGXDeinitialise(IMG_HANDLE hDevCookie)
PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *) hDevCookie;
PVRSRV_ERROR eError;
-
+
if (psDevInfo->pvRegsBaseKM == IMG_NULL)
{
return PVRSRV_OK;
@@ -460,12 +461,12 @@ static PVRSRV_ERROR DevInitSGXPart1 (IMG_VOID *pvDeviceNode)
DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap = psDeviceNode->sDevMemoryInfo.psDeviceMemoryHeap;
PVRSRV_ERROR eError;
-
+
PDUMPCOMMENT("SGX Core Version Information: %s", SGX_CORE_FRIENDLY_NAME);
-
+
#if defined(SGX_FEATURE_MP)
PDUMPCOMMENT("SGX Multi-processor: %d cores", SGX_FEATURE_MP_CORE_COUNT);
- #endif
+ #endif
#if (SGX_CORE_REV == 0)
PDUMPCOMMENT("SGX Core Revision Information: head RTL");
@@ -477,8 +478,8 @@ static PVRSRV_ERROR DevInitSGXPart1 (IMG_VOID *pvDeviceNode)
PDUMPCOMMENT("SGX System Level Cache is present\r\n");
#if defined(SGX_BYPASS_SYSTEM_CACHE)
PDUMPCOMMENT("SGX System Level Cache is bypassed\r\n");
- #endif
- #endif
+ #endif
+ #endif
PDUMPCOMMENT("SGX Initialisation Part 1");
@@ -1027,10 +1028,10 @@ IMG_VOID HWRecoveryResetSGX (PVRSRV_DEVICE_NODE *psDeviceNode,
SGXDumpDebugInfo(psDeviceNode->pvDevice, IMG_TRUE);
-
+
PDUMPSUSPEND();
-
+
#if defined(FIX_HW_BRN_23281)
for (eError = PVRSRV_ERROR_RETRY; eError == PVRSRV_ERROR_RETRY;)
@@ -1044,19 +1045,19 @@ IMG_VOID HWRecoveryResetSGX (PVRSRV_DEVICE_NODE *psDeviceNode,
PVR_DPF((PVR_DBG_ERROR,"HWRecoveryResetSGX: SGXInitialise failed (%d)", eError));
}
-
+
PDUMPRESUME();
PVRSRVPowerUnlock(ui32CallerID);
-
+
SGXScheduleProcessQueuesKM(psDeviceNode);
-
-
+
+
PVRSRVProcessQueues(ui32CallerID, IMG_TRUE);
}
-#endif
+#endif
#if defined(SUPPORT_HW_RECOVERY)
@@ -1065,7 +1066,7 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
PVRSRV_DEVICE_NODE *psDeviceNode = pvData;
PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
static IMG_UINT32 ui32EDMTasks = 0;
- static IMG_UINT32 ui32LockupCounter = 0;
+ static IMG_UINT32 ui32LockupCounter = 0;
static IMG_UINT32 ui32NumResets = 0;
#if defined(FIX_HW_BRN_31093)
static IMG_BOOL bBRN31093Inval = IMG_FALSE;
@@ -1074,17 +1075,17 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
IMG_BOOL bLockup = IMG_FALSE;
IMG_BOOL bPoweredDown;
-
+
psDevInfo->ui32TimeStamp++;
#if defined(NO_HARDWARE)
bPoweredDown = IMG_TRUE;
#else
bPoweredDown = (SGXIsDevicePowered(psDeviceNode)) ? IMG_FALSE : IMG_TRUE;
-#endif
+#endif
+
+
-
-
if (bPoweredDown)
{
ui32LockupCounter = 0;
@@ -1094,7 +1095,7 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
}
else
{
-
+
ui32CurrentEDMTasks = OSReadHWReg(psDevInfo->pvRegsBaseKM, psDevInfo->ui32EDMTaskReg0);
if (psDevInfo->ui32EDMTaskReg1 != 0)
{
@@ -1156,14 +1157,14 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
{
SGXMKIF_HOST_CTL *psSGXHostCtl = (SGXMKIF_HOST_CTL *)psDevInfo->psSGXHostCtl;
-
+
psSGXHostCtl->ui32HostDetectedLockups ++;
-
+
HWRecoveryResetSGX(psDeviceNode, 0, KERNEL_ID);
}
}
-#endif
+#endif
#if defined(SYS_USING_INTERRUPTS)
@@ -1173,18 +1174,18 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData)
IMG_BOOL bInterruptProcessed = IMG_FALSE;
-
+
{
IMG_UINT32 ui32EventStatus, ui32EventEnable;
IMG_UINT32 ui32EventClear = 0;
#if defined(SGX_FEATURE_DATA_BREAKPOINTS)
IMG_UINT32 ui32EventStatus2, ui32EventEnable2;
-#endif
+#endif
IMG_UINT32 ui32EventClear2 = 0;
PVRSRV_DEVICE_NODE *psDeviceNode;
PVRSRV_SGXDEV_INFO *psDevInfo;
-
+
if(pvData == IMG_NULL)
{
PVR_DPF((PVR_DBG_ERROR, "SGX_ISRHandler: Invalid params\n"));
@@ -1197,18 +1198,18 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData)
ui32EventStatus = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS);
ui32EventEnable = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE);
-
+
ui32EventStatus &= ui32EventEnable;
#if defined(SGX_FEATURE_DATA_BREAKPOINTS)
ui32EventStatus2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS2);
ui32EventEnable2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE2);
-
+
ui32EventStatus2 &= ui32EventEnable2;
-#endif
+#endif
+
-
if (ui32EventStatus & EUR_CR_EVENT_STATUS_SW_EVENT_MASK)
{
@@ -1225,16 +1226,16 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData)
{
ui32EventClear2 |= EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK;
}
-#endif
+#endif
if (ui32EventClear || ui32EventClear2)
{
bInterruptProcessed = IMG_TRUE;
-
+
ui32EventClear |= EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK;
-
+
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR, ui32EventClear);
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2, ui32EventClear2);
}
@@ -1265,7 +1266,7 @@ static IMG_VOID SGX_MISRHandler (IMG_VOID *pvData)
SGXTestActivePowerEvent(psDeviceNode, ISR_ID);
}
-#endif
+#endif
@@ -1283,14 +1284,14 @@ PVRSRV_ERROR SGX_AllocMemTilingRange(PVRSRV_DEVICE_NODE *psDeviceNode,
IMG_UINT32 ui32Offset;
IMG_UINT32 ui32Val;
-
+
for(i=0; i<10; i++)
{
if((psDevInfo->ui32MemTilingUsage & (1U << i)) == 0)
{
-
+
psDevInfo->ui32MemTilingUsage |= 1U << i;
-
+
*pui32RangeIndex = i;
goto RangeAllocated;
}
@@ -1310,7 +1311,7 @@ RangeAllocated:
| (((ui32Start>>20) << EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT) & EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK)
| (0x8 << EUR_CR_BIF_TILE0_CFG_SHIFT);
-
+
OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val);
PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val);
@@ -1319,7 +1320,7 @@ RangeAllocated:
ui32Val = (((ui32End>>12) << EUR_CR_BIF_TILE0_ADDR_EXT_MAX_SHIFT) & EUR_CR_BIF_TILE0_ADDR_EXT_MAX_MASK)
| (((ui32Start>>12) << EUR_CR_BIF_TILE0_ADDR_EXT_MIN_SHIFT) & EUR_CR_BIF_TILE0_ADDR_EXT_MIN_MASK);
-
+
OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val);
PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val);
@@ -1349,14 +1350,14 @@ PVRSRV_ERROR SGX_FreeMemTilingRange(PVRSRV_DEVICE_NODE *psDeviceNode,
return PVRSRV_ERROR_INVALID_PARAMS;
}
-
+
psDevInfo->ui32MemTilingUsage &= ~(1<<ui32RangeIndex);
-
+
ui32Offset = EUR_CR_BIF_TILE0 + (ui32RangeIndex<<2);
ui32Val = 0;
-
+
OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val);
PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val);
@@ -1377,12 +1378,12 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
DEVICE_MEMORY_INFO *psDevMemoryInfo;
DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap;
-
+
psDeviceNode->sDevId.eDeviceType = DEV_DEVICE_TYPE;
psDeviceNode->sDevId.eDeviceClass = DEV_DEVICE_CLASS;
#if defined(PDUMP)
{
-
+
SGX_DEVICE_MAP *psSGXDeviceMemMap;
SysGetDeviceMemoryMap(PVRSRV_DEVICE_TYPE_SGX,
(IMG_VOID**)&psSGXDeviceMemMap);
@@ -1390,9 +1391,9 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
psDeviceNode->sDevId.pszPDumpDevName = psSGXDeviceMemMap->pszPDumpDevName;
PVR_ASSERT(psDeviceNode->sDevId.pszPDumpDevName != IMG_NULL);
}
-
+
psDeviceNode->sDevId.pszPDumpRegName = SGX_PDUMPREG_NAME;
-#endif
+#endif
psDeviceNode->pfnInitDevice = &DevInitSGXPart1;
psDeviceNode->pfnDeInitDevice = &DevDeInitSGX;
@@ -1402,7 +1403,7 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
psDeviceNode->pfnPDumpInitDevice = &SGXResetPDump;
psDeviceNode->pfnMMUGetContextID = &MMU_GetPDumpContextID;
#endif
-
+
psDeviceNode->pfnMMUInitialise = &MMU_Initialise;
psDeviceNode->pfnMMUFinalise = &MMU_Finalise;
@@ -1422,7 +1423,7 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
#endif
#if defined (SYS_USING_INTERRUPTS)
-
+
psDeviceNode->pfnDeviceISR = SGX_ISRHandler;
psDeviceNode->pfnDeviceMISR = SGX_MISRHandler;
@@ -1433,20 +1434,20 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
psDeviceNode->pfnFreeMemTilingRange = SGX_FreeMemTilingRange;
#endif
-
+
psDeviceNode->pfnDeviceCommandComplete = &SGXCommandComplete;
-
+
psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo;
-
+
psDevMemoryInfo->ui32AddressSpaceSizeLog2 = SGX_FEATURE_ADDRESS_SPACE_SIZE;
-
+
psDevMemoryInfo->ui32Flags = 0;
-
+
if(OSAllocMem( PVRSRV_OS_PAGEABLE_HEAP,
sizeof(DEVICE_MEMORY_HEAP_INFO) * SGX_MAX_HEAP_ID,
(IMG_VOID **)&psDevMemoryInfo->psDeviceMemoryHeap, 0,
@@ -1459,10 +1460,7 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
psDeviceMemoryHeap = psDevMemoryInfo->psDeviceMemoryHeap;
-
-
-
psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_GENERAL_HEAP_ID);
psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_GENERAL_HEAP_BASE;
psDeviceMemoryHeap->ui32HeapSize = SGX_GENERAL_HEAP_SIZE;
@@ -1472,16 +1470,16 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
psDeviceMemoryHeap->pszName = "General";
psDeviceMemoryHeap->pszBSName = "General BS";
psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT;
-
+
psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE;
#if !defined(SUPPORT_SGX_GENERAL_MAPPING_HEAP)
-
+
psDevMemoryInfo->ui32MappingHeapID = (IMG_UINT32)(psDeviceMemoryHeap - psDevMemoryInfo->psDeviceMemoryHeap);
#endif
psDeviceMemoryHeap++;
-
+
psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_TADATA_HEAP_ID);
psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_TADATA_HEAP_BASE;
psDeviceMemoryHeap->ui32HeapSize = SGX_TADATA_HEAP_SIZE;
@@ -1491,12 +1489,12 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
psDeviceMemoryHeap->pszName = "TA Data";
psDeviceMemoryHeap->pszBSName = "TA Data BS";
psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT;
-
+
psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE;
psDeviceMemoryHeap++;
-
+
psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_KERNEL_CODE_HEAP_ID);
psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_KERNEL_CODE_HEAP_BASE;
psDeviceMemoryHeap->ui32HeapSize = SGX_KERNEL_CODE_HEAP_SIZE;
@@ -1989,7 +1987,8 @@ PVRSRV_ERROR SGXGetMiscInfoUkernel(PVRSRV_SGXDEV_INFO *psDevInfo,
SGXMKIF_CMD_GETMISCINFO,
&sCommandData,
KERNEL_ID,
- 0);
+ 0,
+ IMG_FALSE);
if (eError != PVRSRV_OK)
{
@@ -2099,7 +2098,8 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
SGXMKIF_CMD_DATABREAKPOINT,
&sCommandData,
KERNEL_ID,
- 0);
+ 0,
+ IMG_FALSE);
if (eError != PVRSRV_OK)
{
@@ -2480,7 +2480,8 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
SGXMKIF_CMD_SETHWPERFSTATUS,
&sCommandData,
KERNEL_ID,
- 0);
+ 0,
+ IMG_FALSE);
return eError;
}
#endif
diff --git a/drivers/gpu/pvr/sgx/sgxkick.c b/drivers/gpu/pvr/sgx/sgxkick.c
index 8a229c9..581640b 100644
--- a/drivers/gpu/pvr/sgx/sgxkick.c
+++ b/drivers/gpu/pvr/sgx/sgxkick.c
@@ -550,7 +550,7 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
}
#endif
- eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_TA, &psCCBKick->sCommand, KERNEL_ID, 0);
+ eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_TA, &psCCBKick->sCommand, KERNEL_ID, 0, psCCBKick->bLastInScene);
if (eError == PVRSRV_ERROR_RETRY)
{
if (psCCBKick->bFirstKickOrResume && psCCBKick->ui32NumDstSyncObjects > 0)
diff --git a/drivers/gpu/pvr/sgx/sgxpower.c b/drivers/gpu/pvr/sgx/sgxpower.c
index aeac6e3..427cb50 100644
--- a/drivers/gpu/pvr/sgx/sgxpower.c
+++ b/drivers/gpu/pvr/sgx/sgxpower.c
@@ -197,8 +197,9 @@ static IMG_VOID SGXPollForClockGating (PVRSRV_SGXDEV_INFO *psDevInfo,
if (PollForValueKM((IMG_UINT32 *)psDevInfo->pvRegsBaseKM + (ui32Register >> 2),
0,
ui32RegisterValue,
+ MAX_HW_TIME_US,
MAX_HW_TIME_US/WAIT_TRY_COUNT,
- WAIT_TRY_COUNT) != PVRSRV_OK)
+ IMG_FALSE) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXPollForClockGating: %s failed.", pszComment));
PVR_DBG_BREAK;
@@ -251,7 +252,7 @@ PVRSRV_ERROR SGXPrePowerState (IMG_HANDLE hDevHandle,
sCommand.ui32Data[1] = ui32PowerCmd;
- eError = SGXScheduleCCBCommand(psDevInfo, SGXMKIF_CMD_POWER, &sCommand, KERNEL_ID, 0);
+ eError = SGXScheduleCCBCommand(psDevInfo, SGXMKIF_CMD_POWER, &sCommand, KERNEL_ID, 0, IMG_FALSE);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXPrePowerState: Failed to submit power down command"));
@@ -263,8 +264,9 @@ PVRSRV_ERROR SGXPrePowerState (IMG_HANDLE hDevHandle,
if (PollForValueKM(&psDevInfo->psSGXHostCtl->ui32PowerStatus,
ui32CompleteStatus,
ui32CompleteStatus,
+ MAX_HW_TIME_US,
MAX_HW_TIME_US/WAIT_TRY_COUNT,
- WAIT_TRY_COUNT) != PVRSRV_OK)
+ IMG_FALSE) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXPrePowerState: Wait for SGX ukernel power transition failed."));
PVR_DBG_BREAK;
@@ -371,7 +373,7 @@ PVRSRV_ERROR SGXPostPowerState (IMG_HANDLE hDevHandle,
SGXMKIF_COMMAND sCommand = {0};
sCommand.ui32Data[1] = PVRSRV_POWERCMD_RESUME;
- eError = SGXScheduleCCBCommand(psDevInfo, SGXMKIF_CMD_POWER, &sCommand, ISR_ID, 0);
+ eError = SGXScheduleCCBCommand(psDevInfo, SGXMKIF_CMD_POWER, &sCommand, ISR_ID, 0, IMG_FALSE);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXPostPowerState failed to schedule CCB command: %u", eError));
diff --git a/drivers/gpu/pvr/sgx/sgxreset.c b/drivers/gpu/pvr/sgx/sgxreset.c
index 57f6693..847ca24 100644
--- a/drivers/gpu/pvr/sgx/sgxreset.c
+++ b/drivers/gpu/pvr/sgx/sgxreset.c
@@ -199,8 +199,9 @@ static IMG_VOID SGXResetInvalDC(PVRSRV_SGXDEV_INFO *psDevInfo,
if (PollForValueKM((IMG_UINT32 *)((IMG_UINT8*)psDevInfo->pvRegsBaseKM + EUR_CR_BIF_MEM_REQ_STAT),
0,
EUR_CR_BIF_MEM_REQ_STAT_READS_MASK,
+ MAX_HW_TIME_US,
MAX_HW_TIME_US/WAIT_TRY_COUNT,
- WAIT_TRY_COUNT) != PVRSRV_OK)
+ IMG_FALSE) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"Wait for DC invalidate failed."));
PVR_DBG_BREAK;
@@ -329,6 +330,13 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
ui32RegVal = EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_MASK;
+ #if defined(FIX_HW_BRN_31195)
+ ui32RegVal |= EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE0_MASK |
+ EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE1_MASK |
+ EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE2_MASK |
+ EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE3_MASK |
+ EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TA_MASK;
+ #endif
OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
#endif
diff --git a/drivers/gpu/pvr/sgx/sgxtransfer.c b/drivers/gpu/pvr/sgx/sgxtransfer.c
index 317b73f..ab46ff7 100644
--- a/drivers/gpu/pvr/sgx/sgxtransfer.c
+++ b/drivers/gpu/pvr/sgx/sgxtransfer.c
@@ -131,7 +131,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
}
-
+
for (loop=0; loop<psKick->ui32NumSrcSync; loop++)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop];
@@ -146,7 +146,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
#if defined(PDUMP)
if ((PDumpIsCaptureFrameKM()
- || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0))
+ || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0))
&& (bPersistentProcess == IMG_FALSE) )
{
PDUMPCOMMENT("Shared part of transfer command\r\n");
@@ -194,7 +194,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal),
psKick->ui32PDumpFlags,
MAKEUNIQUETAG(psCCBMemInfo));
-
+
PDUMPCOMMENT("Hack dest surface read op in transfer cmd\r\n");
PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal,
psCCBMemInfo,
@@ -206,7 +206,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
}
}
-
+
if((psKick->ui32Flags & SGXMKIF_TQFLAGS_KEEPPENDING)== 0UL)
{
for (loop=0; loop<(psKick->ui32NumSrcSync); loop++)
@@ -224,16 +224,16 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
psSyncInfo->psSyncData->ui32LastOpDumpVal++;
}
}
- }
+ }
#endif
sCommand.ui32Data[1] = psKick->sHWTransferContextDevVAddr.uiAddr;
-
- eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_TRANSFER, &sCommand, KERNEL_ID, psKick->ui32PDumpFlags);
+
+ eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_TRANSFER, &sCommand, KERNEL_ID, psKick->ui32PDumpFlags, IMG_FALSE);
if (eError == PVRSRV_ERROR_RETRY)
{
-
+
if ((psKick->ui32Flags & SGXMKIF_TQFLAGS_KEEPPENDING) == 0UL)
{
if (psKick->ui32NumSrcSync > 0)
@@ -264,14 +264,14 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
#endif
}
-
+
if (psKick->hTASyncInfo != IMG_NULL)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->hTASyncInfo;
psSyncInfo->psSyncData->ui32WriteOpsPending--;
}
-
+
if (psKick->h3DSyncInfo != IMG_NULL)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->h3DSyncInfo;
@@ -284,14 +284,14 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
PVR_DPF((PVR_DBG_ERROR, "SGXSubmitTransferKM: SGXScheduleCCBCommandKM failed."));
return eError;
}
-
+
#if defined(NO_HARDWARE)
if ((psKick->ui32Flags & SGXMKIF_TQFLAGS_NOSYNCUPDATE) == 0)
{
IMG_UINT32 i;
-
+
for(i = 0; i < psKick->ui32NumSrcSync; i++)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[i];
@@ -326,7 +326,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
#if defined(SGX_FEATURE_2D_HARDWARE)
IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK *psKick)
-
+
{
PVRSRV_KERNEL_MEM_INFO *psCCBMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psKick->hCCBMemInfo;
SGXMKIF_COMMAND sCommand = {0};
@@ -336,7 +336,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
IMG_UINT32 i;
#if defined(PDUMP)
IMG_BOOL bPersistentProcess = IMG_FALSE;
-
+
{
PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData();
if(psPerProc != IMG_NULL)
@@ -344,20 +344,20 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
bPersistentProcess = psPerProc->bPDumpPersistent;
}
}
-#endif
+#endif
if (!CCB_OFFSET_IS_VALID(SGXMKIF_2DCMD_SHARED, psCCBMemInfo, psKick, ui32SharedCmdCCBOffset))
{
PVR_DPF((PVR_DBG_ERROR, "SGXSubmit2DKM: Invalid CCB offset"));
return PVRSRV_ERROR_INVALID_PARAMS;
}
-
-
+
+
ps2DCmd = CCB_DATA_FROM_OFFSET(SGXMKIF_2DCMD_SHARED, psCCBMemInfo, psKick, ui32SharedCmdCCBOffset);
OSMemSet(ps2DCmd, 0, sizeof(*ps2DCmd));
-
+
if (psKick->hTASyncInfo != IMG_NULL)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->hTASyncInfo;
@@ -365,11 +365,11 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
ps2DCmd->sTASyncData.ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending++;
ps2DCmd->sTASyncData.ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending;
- ps2DCmd->sTASyncData.sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr;
- ps2DCmd->sTASyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
+ ps2DCmd->sTASyncData.sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr;
+ ps2DCmd->sTASyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
}
-
+
if (psKick->h3DSyncInfo != IMG_NULL)
{
psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->h3DSyncInfo;
@@ -381,7 +381,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
ps2DCmd->s3DSyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
}
-
+
ps2DCmd->ui32NumSrcSync = psKick->ui32NumSrcSync;
for (i = 0; i < psKick->ui32NumSrcSync; i++)
{
@@ -405,7 +405,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
ps2DCmd->sDstSyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
}
-
+
for (i = 0; i < psKick->ui32NumSrcSync; i++)
{
psSyncInfo = psKick->ahSrcSyncInfo[i];
@@ -423,7 +423,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
|| ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0))
&& (bPersistentProcess == IMG_FALSE) )
{
-
+
PDUMPCOMMENT("Shared part of 2D command\r\n");
PDUMPMEM(ps2DCmd,
psCCBMemInfo,
@@ -474,7 +474,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
MAKEUNIQUETAG(psCCBMemInfo));
}
-
+
for (i = 0; i < psKick->ui32NumSrcSync; i++)
{
psSyncInfo = psKick->ahSrcSyncInfo[i];
@@ -486,16 +486,16 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
psSyncInfo = psKick->hDstSyncInfo;
psSyncInfo->psSyncData->ui32LastOpDumpVal++;
}
- }
+ }
#endif
sCommand.ui32Data[1] = psKick->sHW2DContextDevVAddr.uiAddr;
-
- eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_2D, &sCommand, KERNEL_ID, psKick->ui32PDumpFlags);
+
+ eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_2D, &sCommand, KERNEL_ID, psKick->ui32PDumpFlags, IMG_FALSE);
if (eError == PVRSRV_ERROR_RETRY)
{
-
+
#if defined(PDUMP)
if (PDumpIsCaptureFrameKM())
diff --git a/drivers/gpu/pvr/sgx/sgxutils.c b/drivers/gpu/pvr/sgx/sgxutils.c
index 83144de..7f64088 100644
--- a/drivers/gpu/pvr/sgx/sgxutils.c
+++ b/drivers/gpu/pvr/sgx/sgxutils.c
@@ -142,7 +142,7 @@ static INLINE SGXMKIF_COMMAND * SGXAcquireKernelCCBSlot(PVRSRV_SGX_CCB_INFO *psC
return &psCCB->psCommands[*psCCB->pui32WriteOffset];
}
- OSWaitus(MAX_HW_TIME_US/WAIT_TRY_COUNT);
+ OSSleepms(1);
} END_LOOP_UNTIL_TIMEOUT();
@@ -153,12 +153,12 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
SGXMKIF_CMD_TYPE eCmdType,
SGXMKIF_COMMAND *psCommandData,
IMG_UINT32 ui32CallerID,
- IMG_UINT32 ui32PDumpFlags)
+ IMG_UINT32 ui32PDumpFlags,
+ IMG_BOOL bLastInScene)
{
PVRSRV_SGX_CCB_INFO *psKernelCCB;
PVRSRV_ERROR eError = PVRSRV_OK;
SGXMKIF_COMMAND *psSGXCommand;
- SYS_DATA *psSysData;
#if defined(PDUMP)
IMG_VOID *pvDumpCommand;
IMG_BOOL bPDumpIsSuspended = PDumpIsSuspended();
@@ -187,7 +187,8 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
SGXMKIF_CMD_PROCESS_QUEUES,
&sCacheCommand,
ui32CallerID,
- ui32PDumpFlags);
+ ui32PDumpFlags,
+ bLastInScene);
if (eError != PVRSRV_OK)
{
goto Exit;
@@ -198,8 +199,9 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
if(PollForValueKM(&psSGXHostCtl->ui32InvalStatus,
PVRSRV_USSE_EDM_BIF_INVAL_COMPLETE,
PVRSRV_USSE_EDM_BIF_INVAL_COMPLETE,
- 2 * MAX_HW_TIME_US/WAIT_TRY_COUNT,
- WAIT_TRY_COUNT) != PVRSRV_OK)
+ 2 * MAX_HW_TIME_US,
+ MAX_HW_TIME_US/WAIT_TRY_COUNT,
+ IMG_FALSE) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXScheduleCCBCommand: Wait for uKernel to Invalidate BIF cache failed"));
PVR_DBG_BREAK;
@@ -224,7 +226,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
#endif
#if defined(PDUMP)
-
+
{
PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData();
if(psPerProc != IMG_NULL)
@@ -232,30 +234,30 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
bPersistentProcess = psPerProc->bPDumpPersistent;
}
}
-#endif
+#endif
psKernelCCB = psDevInfo->psKernelCCBInfo;
psSGXCommand = SGXAcquireKernelCCBSlot(psKernelCCB);
-
+
if(!psSGXCommand)
{
eError = PVRSRV_ERROR_TIMEOUT;
goto Exit;
}
-
+
psCommandData->ui32CacheControl = psDevInfo->ui32CacheControl;
#if defined(PDUMP)
-
+
psDevInfo->sPDContext.ui32CacheControl |= psDevInfo->ui32CacheControl;
#endif
-
+
psDevInfo->ui32CacheControl = 0;
-
+
*psSGXCommand = *psCommandData;
if (eCmdType >= SGXMKIF_CMD_MAX)
@@ -265,29 +267,34 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
goto Exit;
}
-
- SysAcquireData(&psSysData);
-
- if(psSysData->ePendingCacheOpType == PVRSRV_MISC_INFO_CPUCACHEOP_FLUSH)
+ if((eCmdType == SGXMKIF_CMD_TA) && bLastInScene)
{
- OSFlushCPUCacheKM();
- }
- else if(psSysData->ePendingCacheOpType == PVRSRV_MISC_INFO_CPUCACHEOP_CLEAN)
- {
- OSCleanCPUCacheKM();
- }
+ SYS_DATA *psSysData;
-
- psSysData->ePendingCacheOpType = PVRSRV_MISC_INFO_CPUCACHEOP_NONE;
+
+ SysAcquireData(&psSysData);
+
+ if(psSysData->ePendingCacheOpType == PVRSRV_MISC_INFO_CPUCACHEOP_FLUSH)
+ {
+ OSFlushCPUCacheKM();
+ }
+ else if(psSysData->ePendingCacheOpType == PVRSRV_MISC_INFO_CPUCACHEOP_CLEAN)
+ {
+ OSCleanCPUCacheKM();
+ }
+
+
+ psSysData->ePendingCacheOpType = PVRSRV_MISC_INFO_CPUCACHEOP_NONE;
+ }
PVR_ASSERT(eCmdType < SGXMKIF_CMD_MAX);
- psSGXCommand->ui32ServiceAddress = psDevInfo->aui32HostKickAddr[eCmdType];
+ psSGXCommand->ui32ServiceAddress = psDevInfo->aui32HostKickAddr[eCmdType];
#if defined(PDUMP)
if ((ui32CallerID != ISR_ID) && (bPDumpIsSuspended == IMG_FALSE) &&
(bPersistentProcess == IMG_FALSE) )
{
-
+
PDUMPCOMMENTWITHFLAGS(ui32PDumpFlags, "Poll for space in the Kernel CCB\r\n");
PDUMPMEMPOL(psKernelCCB->psCCBCtlMemInfo,
offsetof(PVRSRV_SGX_CCB_CTL, ui32ReadOffset),
@@ -307,7 +314,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
ui32PDumpFlags,
MAKEUNIQUETAG(psKernelCCB->psCCBMemInfo));
-
+
PDUMPMEM(&psDevInfo->sPDContext.ui32CacheControl,
psKernelCCB->psCCBMemInfo,
psKernelCCB->ui32CCBDumpWOff * sizeof(SGXMKIF_COMMAND) +
@@ -319,19 +326,20 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
if (PDumpIsCaptureFrameKM()
|| ((ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0))
{
-
+
psDevInfo->sPDContext.ui32CacheControl = 0;
}
}
#endif
#if defined(FIX_HW_BRN_26620) && defined(SGX_FEATURE_SYSTEM_CACHE) && !defined(SGX_BYPASS_SYSTEM_CACHE)
-
+
eError = PollForValueKM (psKernelCCB->pui32ReadOffset,
*psKernelCCB->pui32WriteOffset,
0xFF,
+ MAX_HW_TIME_US,
MAX_HW_TIME_US/WAIT_TRY_COUNT,
- WAIT_TRY_COUNT);
+ IMG_FALSE);
if (eError != PVRSRV_OK)
{
eError = PVRSRV_ERROR_TIMEOUT;
@@ -339,7 +347,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
}
#endif
-
+
*psKernelCCB->pui32WriteOffset = (*psKernelCCB->pui32WriteOffset + 1) & 255;
@@ -405,7 +413,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
OSMemoryBarrier();
#if defined(NO_HARDWARE)
-
+
*psKernelCCB->pui32ReadOffset = (*psKernelCCB->pui32ReadOffset + 1) & 255;
#endif
@@ -418,7 +426,8 @@ PVRSRV_ERROR SGXScheduleCCBCommandKM(PVRSRV_DEVICE_NODE *psDeviceNode,
SGXMKIF_CMD_TYPE eCmdType,
SGXMKIF_COMMAND *psCommandData,
IMG_UINT32 ui32CallerID,
- IMG_UINT32 ui32PDumpFlags)
+ IMG_UINT32 ui32PDumpFlags,
+ IMG_BOOL bLastInScene)
{
PVRSRV_ERROR eError;
PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
@@ -465,7 +474,7 @@ PVRSRV_ERROR SGXScheduleCCBCommandKM(PVRSRV_DEVICE_NODE *psDeviceNode,
return eError;
}
- eError = SGXScheduleCCBCommand(psDevInfo, eCmdType, psCommandData, ui32CallerID, ui32PDumpFlags);
+ eError = SGXScheduleCCBCommand(psDevInfo, eCmdType, psCommandData, ui32CallerID, ui32PDumpFlags, bLastInScene);
PVRSRVPowerUnlock(ui32CallerID);
@@ -497,7 +506,7 @@ PVRSRV_ERROR SGXScheduleProcessQueuesKM(PVRSRV_DEVICE_NODE *psDeviceNode)
return PVRSRV_OK;
}
- eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_PROCESS_QUEUES, &sCommand, ISR_ID, 0);
+ eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_PROCESS_QUEUES, &sCommand, ISR_ID, 0, IMG_FALSE);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXScheduleProcessQueuesKM failed to schedule CCB command: %u", eError));
@@ -551,7 +560,7 @@ IMG_VOID SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode,
sCommand.ui32Data[0] = ui32CleanupType;
sCommand.ui32Data[1] = (psHWDataDevVAddr == IMG_NULL) ? 0 : psHWDataDevVAddr->uiAddr;
- eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_CLEANUP, &sCommand, KERNEL_ID, 0);
+ eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_CLEANUP, &sCommand, KERNEL_ID, 0, IMG_FALSE);
if (eError != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Failed to submit clean-up command"));
@@ -563,8 +572,9 @@ IMG_VOID SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode,
if(PollForValueKM(&psSGXHostCtl->ui32CleanupStatus,
PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
- 2 * MAX_HW_TIME_US/WAIT_TRY_COUNT,
- WAIT_TRY_COUNT) != PVRSRV_OK)
+ 10 * MAX_HW_TIME_US,
+ 1000,
+ IMG_TRUE) != PVRSRV_OK)
{
PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Wait for uKernel to clean up (%u) failed", ui32CleanupType));
PVR_DBG_BREAK;
@@ -943,7 +953,7 @@ PVRSRV_ERROR SGX2DQueryBlitsCompleteKM(PVRSRV_SGXDEV_INFO *psDevInfo,
LOOP_UNTIL_TIMEOUT(MAX_HW_TIME_US)
{
- OSWaitus(MAX_HW_TIME_US/WAIT_TRY_COUNT);
+ OSSleepms(1);
if(SGX2DQuerySyncOpsComplete(psSyncInfo, ui32ReadOpsPending, ui32WriteOpsPending))
{
@@ -952,7 +962,7 @@ PVRSRV_ERROR SGX2DQueryBlitsCompleteKM(PVRSRV_SGXDEV_INFO *psDevInfo,
return PVRSRV_OK;
}
- OSWaitus(MAX_HW_TIME_US/WAIT_TRY_COUNT);
+ OSSleepms(1);
} END_LOOP_UNTIL_TIMEOUT();
diff --git a/drivers/gpu/pvr/sgx/sgxutils.h b/drivers/gpu/pvr/sgx/sgxutils.h
index 7b6e473..ef03e4f 100644
--- a/drivers/gpu/pvr/sgx/sgxutils.h
+++ b/drivers/gpu/pvr/sgx/sgxutils.h
@@ -42,17 +42,19 @@ IMG_VOID SGXTestActivePowerEvent(PVRSRV_DEVICE_NODE *psDeviceNode,
IMG_UINT32 ui32CallerID);
IMG_IMPORT
-PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
+PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
SGXMKIF_CMD_TYPE eCommandType,
SGXMKIF_COMMAND *psCommandData,
IMG_UINT32 ui32CallerID,
- IMG_UINT32 ui32PDumpFlags);
+ IMG_UINT32 ui32PDumpFlags,
+ IMG_BOOL bLastInScene);
IMG_IMPORT
PVRSRV_ERROR SGXScheduleCCBCommandKM(PVRSRV_DEVICE_NODE *psDeviceNode,
SGXMKIF_CMD_TYPE eCommandType,
SGXMKIF_COMMAND *psCommandData,
IMG_UINT32 ui32CallerID,
- IMG_UINT32 ui32PDumpFlags);
+ IMG_UINT32 ui32PDumpFlags,
+ IMG_BOOL bLastInScene);
IMG_IMPORT
PVRSRV_ERROR SGXScheduleProcessQueuesKM(PVRSRV_DEVICE_NODE *psDeviceNode);
--
cgit v1.1