From c27a444e54d531f8a0cd33e67dc46ff7c763cc4b Mon Sep 17 00:00:00 2001 From: Henrik Smiding Date: Wed, 15 Jan 2014 16:12:02 +0100 Subject: Add Silvermont architecture cache sizes Adds Silvermont specific cache sizes for memset16/32 SSE optimization. Change-Id: Ib5ea086d57544e74ac384ee1ef516b8511392f70 Signed-off-by: Henrik Smiding --- libcutils/arch-x86/cache_wrapper.S | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) (limited to 'libcutils') diff --git a/libcutils/arch-x86/cache_wrapper.S b/libcutils/arch-x86/cache_wrapper.S index 508fdd3..9eee25c 100644 --- a/libcutils/arch-x86/cache_wrapper.S +++ b/libcutils/arch-x86/cache_wrapper.S @@ -17,8 +17,15 @@ * Contributed by: Intel Corporation */ +#if defined(__slm__) +/* Values are optimized for Silvermont */ +#define SHARED_CACHE_SIZE (1024*1024) /* Silvermont L2 Cache */ +#define DATA_CACHE_SIZE (24*1024) /* Silvermont L1 Data Cache */ +#else /* Values are optimized for Atom */ -#define SHARED_CACHE_SIZE (512*1024) /* Atom L2 Cache */ -#define DATA_CACHE_SIZE (24*1024) /* Atom L1 Data Cache */ +#define SHARED_CACHE_SIZE (512*1024) /* Atom L2 Cache */ +#define DATA_CACHE_SIZE (24*1024) /* Atom L1 Data Cache */ +#endif + #define SHARED_CACHE_SIZE_HALF (SHARED_CACHE_SIZE / 2) #define DATA_CACHE_SIZE_HALF (DATA_CACHE_SIZE / 2) -- cgit v1.1