check in binutils sources for prebuilt toolchains in Eclair.

2615 files changed, 161263 insertions, 0 deletions

diff --git a/binutils-2.19/ld/testsuite/ChangeLog b/binutils-2.19/ld/testsuite/ChangeLog
new file mode 100644
index 0000000..6ca9266
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ChangeLog
@@ -0,0 +1,803 @@
+2008-09-30  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/extract-symbol-1sec.d: Correct section lma.
+
+2008-09-22  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* ld-mips-elf/reloc-estimate-1.d: Make endian-neutral.
+
+2008-09-20  Jan Kratochvil  <jan.kratochvil@redhat.com>
+
+	Provide virtual target "cfi" for targets supporting CFI.
+	* ld-elf/eh-frame-hdr.d: Replace target and xfail statements by single
+	`target: cfi'.
+	* ld-elf/eh-group.exp: Call check_as_cfi instead of is_elf_format.
+	* ld-elf/eh-group1.s, elf/eh-group2.s: Use more compatible section
+	flags prefix '%'.
+	* ld-elf/eh5.d: Replace target statement by `target: cfi' with an Alpha
+	exception.  Relax the `Code alignment factor' matching.
+	* lib/ld-lib.exp: Rename istarget as istarget_ld.
+	(istarget, check_as_cfi): New procedure.
+	(run_dump_test): New comment for the virtual target `cfi'.
+
+2008-09-17  Jan Kratochvil  <jan.kratochvil@redhat.com>
+
+	* ld-elf/eh-group.exp, ld-elf/eh-group1.s, ld-elf/eh-group2.s: New test.
+
+2008-08-26  Nick Clifton  <nickc@redhat.com>
+
+	* ld-arm/arm-elf.exp: Add farcall-thumb-arm-short test.
+	* ld-arm/farcall-group2.s: Fix comment.
+	* ld-arm/farcall-thumb-arm-short.d: New test.
+	* ld-arm/farcall-thumb-arm-short.s: New test.
+
+2008-08-22  Jan Kratochvil  <jan.kratochvil@redhat.com>
+
+	* ld-x86-64/dwarfreloc.exp, ld-x86-64/dwarfreloc.rd,
+	ld-x86-64/dwarfreloc1.s, ld-x86-64/dwarfreloc2.s: New test.
+
+2008-08-20  Bob Wilson  <bob.wilson@acm.org>
+	
+	* ld-xtensa/tlsbin.dd, ld-xtensa/tlsbin.rd, ld-xtensa/tlsbin.s,
+	ld-xtensa/tlsbin.sd, ld-xtensa/tlsbin.td, ld-xtensa/tlslib.s,
+	ld-xtensa/tlspic.dd, ld-xtensa/tlspic.rd, ld-xtensa/tlspic.sd,
+	ld-xtensa/tlspic.td, ld-xtensa/tlspic1.s, ld-xtensa/tlspic2.s: New.
+	* ld-xtensa/xtensa.exp: Run them.
+
+2008-08-18  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* ld-mips-elf/mips16-pic-4a.s, ld-mips-elf/mips16-pic-4b.s,
+	ld-mips-elf/mips16-pic-4.ver, ld-mips-elf/mips16-pic-4a.dd,
+	ld-mips-elf/mips16-pic-4a.nd, ld-mips-elf/mips16-pic-4a.gd,
+	ld-mips-elf/mips16-pic-4c.s, ld-mips-elf/mips16-pic-4b.dd: New tests.
+	* ld-mips-elf/mips-elf.exp: Run them.
+
+2008-08-17  Nick Clifton  <nickc@redhat.com>
+
+	* ld-elf/sec-to-seg1.s: Shorten test data to align the section to
+	a 4-byte boundary.
+
+2008-08-08  Richard Sandiford  <rdsandiford@googlemail.com>
+	    Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-mips-elf/mips16-pic-3a.s,
+	ld-mips-elf/mips16-pic-3b.s,
+	ld-mips-elf/mips16-pic-3.dd,
+	ld-mips-elf/mips16-pic-3.gd,
+	ld-mips-elf/mips16-pic-3.rd,
+	ld-mips-elf/mips16-pic-3.inc,
+	ld-mips-elf/pic-and-nonpic-1a.s,
+	ld-mips-elf/pic-and-nonpic-1b.s,
+	ld-mips-elf/pic-and-nonpic-1.ld,
+	ld-mips-elf/pic-and-nonpic-1.dd,
+	ld-mips-elf/pic-and-nonpic-1.nd,
+	ld-mips-elf/pic-and-nonpic-1-rel.dd,
+	ld-mips-elf/pic-and-nonpic-1-rel.nd,
+	ld-mips-elf/pic-and-nonpic-2a.s,
+	ld-mips-elf/pic-and-nonpic-2b.s,
+	ld-mips-elf/pic-and-nonpic-2.d,
+	ld-mips-elf/pic-and-nonpic-3a.s,
+	ld-mips-elf/pic-and-nonpic-3a.ld,
+	ld-mips-elf/pic-and-nonpic-3a.dd,
+	ld-mips-elf/pic-and-nonpic-3a.gd,
+	ld-mips-elf/pic-and-nonpic-3a.sd,
+	ld-mips-elf/pic-and-nonpic-3b.s,
+	ld-mips-elf/pic-and-nonpic-3b.ld,
+	ld-mips-elf/pic-and-nonpic-3b.ad,
+	ld-mips-elf/pic-and-nonpic-3b.dd,
+	ld-mips-elf/pic-and-nonpic-3b.gd,
+	ld-mips-elf/pic-and-nonpic-3b.nd,
+	ld-mips-elf/pic-and-nonpic-3b.pd,
+	ld-mips-elf/pic-and-nonpic-3b.rd,
+	ld-mips-elf/pic-and-nonpic-3b.sd,
+	ld-mips-elf/pic-and-nonpic-3-error.d,
+	ld-mips-elf/pic-and-nonpic-4a.s,
+	ld-mips-elf/pic-and-nonpic-4b.s,
+	ld-mips-elf/pic-and-nonpic-4b.ld,
+	ld-mips-elf/pic-and-nonpic-4b.ad,
+	ld-mips-elf/pic-and-nonpic-4b.dd,
+	ld-mips-elf/pic-and-nonpic-4b.gd,
+	ld-mips-elf/pic-and-nonpic-4b.nd,
+	ld-mips-elf/pic-and-nonpic-4b.rd,
+	ld-mips-elf/pic-and-nonpic-4b.sd,
+	ld-mips-elf/pic-and-nonpic-4-error.d,
+	ld-mips-elf/pic-and-nonpic-5a.s,
+	ld-mips-elf/pic-and-nonpic-5b.s,
+	ld-mips-elf/pic-and-nonpic-5b.ld,
+	ld-mips-elf/pic-and-nonpic-5b.ad,
+	ld-mips-elf/pic-and-nonpic-5b.dd,
+	ld-mips-elf/pic-and-nonpic-5b.gd,
+	ld-mips-elf/pic-and-nonpic-5b.nd,
+	ld-mips-elf/pic-and-nonpic-5b.rd,
+	ld-mips-elf/pic-and-nonpic-5b.sd,
+	ld-mips-elf/pic-and-nonpic-5b.pd,
+	ld-mips-elf/pic-and-nonpic-6.ld,
+	ld-mips-elf/pic-and-nonpic-6-o32a.s,
+	ld-mips-elf/pic-and-nonpic-6-o32b.s,
+	ld-mips-elf/pic-and-nonpic-6-o32c.s,
+	ld-mips-elf/pic-and-nonpic-6-o32.ad,
+	ld-mips-elf/pic-and-nonpic-6-o32.dd,
+	ld-mips-elf/pic-and-nonpic-6-o32.gd,
+	ld-mips-elf/pic-and-nonpic-6-o32.nd,
+	ld-mips-elf/pic-and-nonpic-6-o32.pd,
+	ld-mips-elf/pic-and-nonpic-6-o32.rd,
+	ld-mips-elf/pic-and-nonpic-6-o32.sd,
+	ld-mips-elf/pic-and-nonpic-6-n32a.s,
+	ld-mips-elf/pic-and-nonpic-6-n32b.s,
+	ld-mips-elf/pic-and-nonpic-6-n32c.s,
+	ld-mips-elf/pic-and-nonpic-6-n32.ad,
+	ld-mips-elf/pic-and-nonpic-6-n32.dd,
+	ld-mips-elf/pic-and-nonpic-6-n32.gd,
+	ld-mips-elf/pic-and-nonpic-6-n32.nd,
+	ld-mips-elf/pic-and-nonpic-6-n32.pd,
+	ld-mips-elf/pic-and-nonpic-6-n32.rd,
+	ld-mips-elf/pic-and-nonpic-6-n32.sd,
+	ld-mips-elf/pic-and-nonpic-6-n64a.s,
+	ld-mips-elf/pic-and-nonpic-6-n64b.s,
+	ld-mips-elf/pic-and-nonpic-6-n64c.s,
+	ld-mips-elf/pic-and-nonpic-6-n64.ad,
+	ld-mips-elf/pic-and-nonpic-6-n64.dd,
+	ld-mips-elf/pic-and-nonpic-6-n64.gd,
+	ld-mips-elf/pic-and-nonpic-6-n64.nd,
+	ld-mips-elf/pic-and-nonpic-6-n64.pd,
+	ld-mips-elf/pic-and-nonpic-6-n64.rd,
+	ld-mips-elf/pic-and-nonpic-6-n64.sd: New tests.
+	* ld-mips-elf/mips-elf.exp: Run them.
+
+2008-08-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* ld-mips-elf/tls-hidden4.got, ld-mips-elf/tls-hidden4.r: We have
+	removed an unused GOT entry that was allocated for the R_MIPS_32
+	relocation against "undef", so adjust addresses down by 4 bytes.
+	* ld-mips-elf/got-dump-1.d, ld-mips-elf/got-dump-2.d: We have
+	changed the order of the GOT entries so that reloc-only ones
+	come last.  "undef" is only referred to by dynamic relocations,
+	so it now comes after "glob".
+	* ld-mips-elf/mips16-pic-2.dd, ld-mips-elf/mips16-pic-2.gd,
+	ld-mips-elf/mips16-pic-2.nd, ld-mips-elf/mips16-pic-2.rd: We have
+	removed two unused local GOT entries that were originally created
+	as global entries for the hidden symbols "used2" and "used3".
+	"used4" and "used5" are only referred to by relocations, so they
+	now come after "used6" and "used7".
+
+2008-08-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* ld-mips-elf/got-vers-1a.s, ld-mips-elf/got-vers-1b.s,
+	ld-mips-elf/got-vers-1.ver, ld-mips-elf/got-vers-1.dd,
+	ld-mips-elf/got-vers-1.sd, ld-mips-elf/got-vers-1.rd: New tests.
+	* ld-mips-elf/mips-elf.exp: Run them.
+
+2008-08-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* ld-mips-elf/tlsdyn-o32-2.got, ld-mips-elf/tlsdyn-o32-3.got,
+	ld-mips-elf/tlsdyn-o32-2.d, ld-mips-elf/tlsdyn-o32-3.d: Change the
+	GOT layout as follows:
+
+	         BEFORE                  AFTER
+	   +0x08 %call16(__tls_get_addr) %call16(__tls_get_addr)
+	   +0x0c %tlsldm(tlsbin_ld)      %gottprel(tlsvar_ie)
+	   +0x10   "  "                  %tlsgd(tlsvar_gd)
+	   +0x14 %tlsgd(tlsvar_gd)          "  "
+	   +0x18   "  "                  %tlsgd(tlsbin_gd)
+	   +0x1c %gottprel(tlsvar_ie)       "  "
+	   +0x20 %tlsgd(tlsbin_gd)       %tlsldm(tlsbin_ld)
+	   +0x24   "  "                     "  "       
+	   +0x28 %gottprel(tlsbin_ie)    %gottprel(tlsbin_ie)
+
+2008-08-07  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* ld-mips-elf/reloc-estimate-1.d, ld-mips-elf/reloc-estimate-1.ld,
+	ld-mips-elf/reloc-estimate-1a.s, ld-mips-elf/reloc-estimate-1b.s:
+	New test.
+	* ld-mips-elf/mips-elf.exp: Run it.
+
+2008-08-06  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* ld-mips-elf/tls-hidden3.ld: Remove the unused .MIPS.stubs section.
+	Keep the text start address the same.
+	* ld-mips-elf/tls-multi-got-1.got: We have removed a .MIPS.stubs
+	section that contained only a 16-byte dummy stub.  Subtract 16
+	from addresses to account for the change.
+	* ld-mips-elf/tls-multi-got-1.r: Likewise.  Adjust MIPS_UNREFEXTNO
+	to account the removed section symbol.
+	* ld-mips-elf/tlsdyn-o32-1.d: We have deleted a .MIPS.stubs
+	section that contained only a 16-byte dummy stub.  Remove it
+	from the disassembly.
+	* ld-mips-elf/tlsdyn-o32-2.d: Likewise.
+	* ld-mips-elf/tlsdyn-o32-3.d: Likewise.
+	* ld-mips-elf/tlsdyn-o32.d: Likewise.
+	* ld-mips-elf/relax-jalr-n32-shared.d: Likewise.
+	* ld-mips-elf/relax-jalr-n64-shared.d: Likewise.
+
+2008-08-06  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* ld-mips-elf/mips16-local-stubs-1.d: Remove stub_for_h3,
+	which was only referenced by the .pdr section, and was not
+	actually needed by code.
+	* ld-mips-elf/mips16-intermix.d: Remove unused static function stubs.
+	* ld-mips-elf/mips16-pic-1a.s,
+	ld-mips-elf/mips16-pic-1b.s,
+	ld-mips-elf/mips16-pic-1-dummy.s,
+	ld-mips-elf/mips16-pic-1.dd,
+	ld-mips-elf/mips16-pic-1.gd,
+	ld-mips-elf/mips16-pic-1.inc,
+	ld-mips-elf/mips16-pic-1.ld,
+	ld-mips-elf/mips16-pic-2a.s,
+	ld-mips-elf/mips16-pic-2b.s,
+	ld-mips-elf/mips16-pic-2.ad,
+	ld-mips-elf/mips16-pic-2.dd,
+	ld-mips-elf/mips16-pic-2.gd,
+	ld-mips-elf/mips16-pic-2.nd,
+	ld-mips-elf/mips16-pic-2.rd: New tests.
+	* ld-mips-elf/mips-elf.exp: Run them.
+
+2008-08-06  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/extract-symbol-1sec.d: Update.
+
+2008-07-30  Nick Clifton  <nickc@redhat.com>
+
+	* ld-elf/sec-to-seg.exp: New test: Checks the assignment of
+	sections to segments.
+	* ld-elf/sec-to-seg1.s: Test source file.
+	* ld-elf/sec-to-seg2.s: Test source file.
+	* ld-elf/sec-to-seg-script-same-page.t: Test linker script.
+	* ld-elf/sec-to-seg-script-adjoining-pages.t: Test linker script.
+	* ld-elf/sec-to-seg-script-disjoint-pages.t: Test linker script.
+
+2008-07-28  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-i386/tlsbindesc.dd: Adjust incorrect expectations for LD to
+	LE relaxation.
+	* ld-x86-64/tlsbindesc.dd: Likewise.
+	* ld-i386/tlsbindesc.rd: Adjust address of _TLS_MODULE_BASE_.
+	* ld-x86-64/tlsbindesc.rd: Likewise.
+	Reported by Cary Coutant <ccoutant@google.com>
+
+2008-07-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-gc/gc.exp (test_gc): xfail powerpc64.
+
+2008-07-26  Michael Eager <eager@eagercon.com>
+
+	* ld-powerpc/powerpc.exp: Run new tests.
+	* ld-powerpc/attr-gnu-4-03.d: New file.
+	* ld-powerpc/attr-gnu-4-14.d: New file.
+	* ld-powerpc/attr-gnu-4-23.d: New file.
+	* ld-powerpc/attr-gnu-4-24.d: New file.
+	* ld-powerpc/attr-gnu-4-32.d: New file.
+	* ld-powerpc/attr-gnu-4-33.d: New file.
+	* ld-powerpc/attr-gnu-4-34.d: New file.
+	* ld-powerpc/attr-gnu-4-41.d: New file.
+	* ld-powerpc/attr-gnu-4-4.s: New file.
+	* ld-powerpc/attr-gnu-4-13.d: Adjust.
+	* ld-powerpc/attr-gnu-4-31.d: Adjust.
+
+2008-07-26  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/include.exp: Don't run test for aout.
+	* ld-scripts/include.s: Use .fill rather than .4byte.
+	* ld-scripts/include-1.d: Adjust.
+
+2008-07-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-alpha/tlsbin.rd: Update.
+	* ld-alpha/tlsbinr.rd: Update.
+	* ld-arm/mixed-app.sym: Update.
+	* ld-arm/use-thumb-lib.sym: Update.
+	* ld-cris/pv32-1.d: Update.
+
+2008-07-21  Nick Clifton  <nickc@redhat.com>
+
+	* ld-scripts/include-sections.t: Discard all sections not
+	explicitly requested by the rest of the linker script.
+	* ld-scripts/include-1.d: Expect test to fail for AIX ports.
+	Do not assume that the .text section will be marked readonly.
+	* ld-scripts/include.s: Replace .section directives with just
+	.text or .data.
+
+2008-07-18  Joseph Myers  <joseph@codesourcery.com>
+
+	* ld-arm/attr-merge-wchar-0.s,ld-arm/attr-merge-wchar-2.s,
+	ld-arm/attr-merge-wchar-4.s, ld-arm/attr-merge-wchar-00-nowarn.d,
+	ld-arm/attr-merge-wchar-00.d, ld-arm/attr-merge-wchar-02-nowarn.d,
+	ld-arm/attr-merge-wchar-02.d, ld-arm/attr-merge-wchar-04-nowarn.d,
+	ld-arm/attr-merge-wchar-04.d, ld-arm/attr-merge-wchar-20-nowarn.d,
+	ld-arm/attr-merge-wchar-20.d, ld-arm/attr-merge-wchar-22-nowarn.d,
+	ld-arm/attr-merge-wchar-22.d, ld-arm/attr-merge-wchar-24-nowarn.d,
+	ld-arm/attr-merge-wchar-24.d, ld-arm/attr-merge-wchar-40-nowarn.d,
+	ld-arm/attr-merge-wchar-40.d, ld-arm/attr-merge-wchar-42-nowarn.d,
+	ld-arm/attr-merge-wchar-42.d, ld-arm/attr-merge-wchar-44-nowarn.d,
+	ld-arm/attr-merge-wchar-44.d: New.
+	* ld-arm/arm-elf.exp: Run new tests.
+
+2008-07-11  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-m68k/got-12.s: Removed.
+	* ld-m68k/got-13.s: Likewise.
+	* ld-m68k/got-14.s: Likewise.
+	* ld-m68k/got-15.s: Likewise.
+	* ld-m68k/got-34.s: Likewise.
+	* ld-m68k/got-35.s: Likewise.
+	* ld-m68k/xgot-15.s: Likewise.
+
+	* ld-m68k/got-multigot-12-13-14-34-35-ok.d: Remove #source
+	and expected relocations.
+	* ld-m68k/got-multigot-14-ok.d: Likewise.
+	* ld-m68k/got-negative-12-13-14-34-ok.d: Likewise.
+	* ld-m68k/got-negative-14-ok.d: Likewise.
+	* ld-m68k/got-single-12-ok.d: Likewise.
+	* ld-m68k/got-xgot-12-13-14-15-34-35-ok.d: Likewise.
+	* ld-m68k/got-xgot-15-ok.d: Likewise.
+
+	* ld-m68k/got-multigot-15-er.d: Remove #source.
+	* ld-m68k/got-negative-12-13-14-35-er.d: Likewise.
+	* ld-m68k/got-negative-15-er.d: Likewise.
+	* ld-m68k/got-single-13-er.d: Likewise.
+
+	* ld-m68k/m68k.exp: Move GOT tests to ...
+	* ld-m68k/m68k-got.exp: This.  New.
+
+2008-07-10  Richard Sandiford  <rdsandiford@googlemail.com>
+
+	* ld-mips-elf/no-shared-1-o32.s,
+	ld-mips-elf/no-shared-1-o32.d,
+	ld-mips-elf/no-shared-1-n32.d,
+	ld-mips-elf/no-shared-1-n64.s,
+	ld-mips-elf/no-shared-1-n64.d,
+	ld-mips-elf/no-shared-1.ld: New tests.
+	* ld-mips-elf/mips-elf.exp: Run them.
+
+2008-07-07  Stan Shebs  <stan@codesourcery.com>
+
+	* ld-arm/arm-elf.exp: Use objdump -d for arm-be8 test.
+	* ld-arm/arm-be8.d: Change to test disassembly.
+
+2008-07-06  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-scripts/include-1.d: New.
+	* ld-scripts/include-1.t: New.
+	* ld-scripts/include-data.t: New.
+	* ld-scripts/include-mem.t: New.
+	* ld-scripts/include-ram.t: New.
+	* ld-scripts/include-sections.t: New.
+	* ld-scripts/include-subdata.t: New.
+	* ld-scripts/include.exp: New.
+	* ld-scripts/include.s: New.
+
+2008-06-29  Andreas Schwab  <schwab@suse.de>
+
+	* ld-m68k/got-1.s: New file.
+	* ld-m68k/got-1.d: New dump test.
+	* ld-m68k/m68k.exp: Run it.
+
+2008-06-24  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-arm/farcall-arm-arm-be8.d, ld-arm/farcall-arm-arm-pic-veneer.d,
+	ld-arm/farcall-arm-arm.d, ld-arm/farcall-arm-thumb-blx-pic-veneer.d,
+	ld-arm/farcall-arm-thumb-blx.d, ld-arm/farcall-arm-thumb-pic-veneer.d,
+	ld-arm/farcall-arm-thumb.d, ld-arm/farcall-group-size2.d,
+	ld-arm/farcall-group.d, ld-arm/farcall-mix.d, ld-arm/farcall-mix2.d,
+	ld-arm/farcall-thumb-arm-blx-pic-veneer.d,
+	ld-arm/farcall-thumb-arm-blx.d, ld-arm/farcall-thumb-arm.d,
+	ld-arm/farcall-thumb-thumb-blx-pic-veneer.d,
+	ld-arm/farcall-thumb-thumb-blx.d, ld-arm/farcall-thumb-thumb-m.d,
+	ld-arm/thumb2-bl-as-thumb1-bad.d, ld-arm/thumb2-bl-bad.d: Update for
+	stub symbols and stub corrections.
+
+2008-06-20  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-spu/ovl.d: Update.
+	* ld-spu/ovl2.d: Update.
+
+2008-06-16  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	PR gas/6607
+	* ld-mmix/loc10.d, ld-mmix/loc10.s, ld-mmix/loc10m.d, ld-mmix/loc8.d,
+	ld-mmix/loc8.s, ld-mmix/loc8m.d, ld-mmix/loc9.d, ld-mmix/loc9.s,
+	ld-mmix/loc9m.d: New tests.
+
+2008-06-12  Nick Clifton  <nickc@redhat.com>
+
+	* ld-scripts/overlay-size.t (end_of_bss_overlays): Define.
+	(end_of_text_overlays): Define.
+	(end_of_data_overlays): Define.
+	* ld-scripts/overlay-size-map.d: Add expected values for
+	end_of_bss_overlays, end_of_text_overlays and
+	end_of_data_overlays.
+
+2008-06-09  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/arch/arch_expected.txt: Regenerate.
+
+2008-06-09  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-arm/mixed-lib.d: Loosen pattern.
+
+2008-06-09  Christophe Lyon  <christophe.lyon@st.com>
+
+	* ld-arm/farcall-thumb-thumb-m.d: Fix branch type.
+	* ld-arm/farcall-thumb-arm.d: Likewise.
+
+2008-05-31  Nick Clifton  <nickc@redhat.com>
+
+	PR ld/6430
+	* ld-elfcomm/elfcomm.exp (test_sort_common): Test the
+	ascending/descending argument to the --sort-common command line
+	option.
+	* ld-elfcomm/sort-common.s: New file.
+
+2008-05-28  Christophe Lyon  <christophe.lyon@st.com>
+	
+	* ld-arm/arm-elf.exp: Skip farcalls tests for non-ARM-EABI
+	targets.
+	* ld-arm/thumb2-bl-as-thumb1-bad-noeabi.d: New file.
+	* ld-arm/thumb2-bl-bad-noeabi.d: Likewise.
+
+2008-05-22  Christophe Lyon  <christophe.lyon@st.com>
+
+	* ld-arm/farcall-arm-arm.s: Force function type on 'bar'.
+	* ld-arm/farcall-thumb-arm.s: Likewise.
+	* ld-arm/farcall-thumb-arm-blx.d: Fix encoding.
+	* ld-arm/farcall-thumb-arm.d: Likewise.
+	* ld-arm/farcall-thumb-arm-blx-pic-veneer.d: Likewise.
+	* ld-arm/arm-elf.exp (armelftests): Add farcall-mix, farcall-mix2,
+	farcall-group-default, farcall-group-size2, farcall-section Ignore
+	gas warnings in farcall-thumb-arm, farcall-thumb-arm-blx,
+	farcall-thumb-arm-blx-pic-veneer.
+
+2008-05-21  Maxim Kuvyrkov  <maxim@codesourcery.com>
+
+	* ld-m68k/got-12.s: New file.
+	* ld-m68k/got-13.s: New file.
+	* ld-m68k/got-14.s: New file.
+	* ld-m68k/got-15.s: New file.
+	* ld-m68k/got-34.s: New file.
+	* ld-m68k/got-35.s: New file.
+	* ld-m68k/got-single-12-ok.d: New dump test.
+	* ld-m68k/got-single-13-er.d: New dump test.
+	* ld-m68k/got-negative-14-ok.d: New dump test.
+	* ld-m68k/got-negative-15-er.d: New dump test.
+	* ld-m68k/got-negative-12-13-14-34-ok.d: New dump test.
+	* ld-m68k/got-negative-12-13-14-35-er.d: New dump test.
+	* ld-m68k/got-multigot-14-ok.d: New dump test.
+	* ld-m68k/got-multigot-15-er.d: New dump test.
+	* ld-m68k/got-multigot-12-13-14-34-35-ok.d: New dump test.
+	* ld-m68k/xgot-15.s: New source.
+	* ld-m68k/got-xgot-15-ok.d: New test.
+	* ld-m68k/got-xgot-12-13-14-15-34-35-ok.d: New test.
+	* ld-m68k/m68k.exp: Run new tests.
+
+2008-05-15  Christophe Lyon  <christophe.lyon@st.com>
+	
+	* ld-arm/arm-elf.exp (armelftests): Add farcall-arm-arm,
+	farcall-arm-arm-pic-veneer, farcall-arm-arm-be8 farcall-arm-thumb,
+	farcall-arm-thumb-blx, farcall-arm-thumb-pic-veneer,
+	farcall-arm-thumb-blx-pic-veneer, farcall-thumb-thumb,
+	farcall-thumb-thumb-pic-veneer, farcall-thumb-thumb-blx,
+	farcall-thumb-thumb-m, farcall-thumb-thumb-m-pic-veneer,
+	farcall-thumb-thumb-blx-pic-veneer, farcall-thumb-arm,
+	farcall-thumb-arm-pic-veneer, farcall-thumb-arm-blx,
+	farcall-thumb-arm-blx-pic-veneer.
+	Change thumb2-bl-as-thumb1-bad, thumb2-bl-bad.
+	* ld-arm/thumb2-bl-as-thumb1-bad.d: Reflects farcall stub
+	generation.
+	* ld-arm/thumb2-bl-bad.d: Likewise.
+	* ld-arm/thumb2-bl-as-thumb1-bad.s: Update comments.
+	* ld-arm/thumb2-bl-bad.s: Likewise.
+
+2008-05-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-spu/ear.s: Align various sections.
+	* ld-spu/embed.rd: Update.
+
+2008-05-05  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 6473
+	* ld-elf/lma.s, ld-elf/lma.lnk: New test.
+	* ld-elf/binutils.exp: Run it.
+
+2008-05-03  Mike Frysinger  <vapier@gentoo.org>
+
+	* ld-scripts/defined.s: Use .set syntax rather than =.
+
+2008-05-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/6475
+	* ld-scripts/rgn-over8-ok.d: Accept any alignment.
+
+2008-04-29  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-arm/symbian-seg1.s, ld-arm/symbian-seg1.d: New files.
+	* ld-arm/arm-elf.exp: Run symbian-seg1.
+
+2008-04-28  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-scripts/rgn-over8.s: Tweak.
+
+	* ld-scripts/rgn-over.exp: Allow -ok file names to pass.
+	* ld-scripts/rgn-over8.s: New.
+	* ld-scripts/rgn-over8.t: New.
+	* ld-scripts/rgn-over8-ok.d: New.
+
+2008-04-21  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-vxworks/plt-mips1.s: New.
+	* ld-vxworks/plt-mips1.d: New.
+
+2008-04-16  David S. Miller  <davem@davemloft.net>
+
+	* ld-sparc/gotop32.dd: New.
+	* ld-sparc/gotop32.rd: Likewise.
+	* ld-sparc/gotop32.s: Likewise.
+	* ld-sparc/gotop32.sd: Likewise.
+	* ld-sparc/gotop32.td: Likewise.
+	* ld-sparc/gotop64.dd: Likewise.
+	* ld-sparc/gotop64.rd: Likewise.
+	* ld-sparc/gotop64.s: Likewise.
+	* ld-sparc/gotop64.sd: Likewise.
+	* ld-sparc/gotop64.td: Likewise.
+	* ld-sparc/sparc.exp: Run new gotdata tests.
+
+2008-04-15  Andrew Stubbs  <andrew.stubbs@st.com>
+
+	* ld-sh/arch/sh-dsp.s: Regenerate.
+	* ld-sh/arch/sh.s: Regenerate.
+	* ld-sh/arch/sh2.s: Regenerate.
+	* ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s: Regenerate.
+	* ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Regenerate.
+	* ld-sh/arch/sh2a-nofpu.s: Regenerate.
+	* ld-sh/arch/sh2a-or-sh3e.s: Regenerate.: Regenerate.
+	* ld-sh/arch/sh2a-or-sh4.s: Regenerate.
+	* ld-sh/arch/sh2a.s: Regenerate.
+	* ld-sh/arch/sh2e.s: Regenerate.
+	* ld-sh/arch/sh3-dsp.s: Regenerate.
+	* ld-sh/arch/sh3-nommu.s: Regenerate.
+	* ld-sh/arch/sh3.s: Regenerate.
+	* ld-sh/arch/sh3e.s: Regenerate.
+	* ld-sh/arch/sh4-nofpu.s: Regenerate.
+	* ld-sh/arch/sh4-nommu-nofpu.s: Regenerate.
+	* ld-sh/arch/sh4.s: Regenerate.
+	* ld-sh/arch/sh4a-nofpu.s: Regenerate.
+	* ld-sh/arch/sh4a.s: Regenerate.
+	* ld-sh/arch/sh4al-dsp.s: Regenerate.
+
+2008-04-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-spu/ovl2.s: Extend to test jump table references and
+	absolute _SPUEAR_ syms.
+	* ld-spu/ovl2.d: Update.
+
+2008-03-28  Joseph Myers  <joseph@codesourcery.com>
+
+	* ld-elfcomm/elfcomm.exp: Run $READELF not readelf.
+
+2008-03-26  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-elf/flags1.d: Adjust for MIPS text alignment.
+
+2008-03-25  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-vxworks/tls-3.s: New.
+	* ld-vxworks/tls-3.d: New.
+
+2008-03-22  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/libdso-10.d: Adjust for change in objdump output.
+
+2008-03-21  Adam Nemet  <anemet@caviumnetworks.com>
+
+	* ld-mips-elf/dyn-sec64.d, ld-mips-elf/dyn-sec64.s,
+	ld-mips-elf/dyn-sec64.ld: New test.
+	* ld-mips-elf/mips-elf.exp: Run it.
+
+2008-03-20  Richard Sandiford  <rsandifo@nildram.co.uk>
+
+	* ld-mips-elf/got-dump-1.d, ld-mips-elf/got-dump-1.s,
+	ld-mips-elf/got-dump-1.ld, ld-mips-elf/got-dump-2.d,
+	ld-mips-elf/got-dump-2.s, ld-mips-elf/got-dump-2.ld: New tests.
+	* ld-mips-elf/mips-elf.exp: Run them.
+
+2008-03-20  Richard Sandiford  <rsandifo@nildram.co.uk>
+
+	* ld-mips-elf/elf-rel-got-n64-linux.d: Expect bit 63 rather than
+	bit 31 of the second GOT entry to be set.
+	* ld-mips-elf/elf-rel-got-n64.d: Likewise.
+	* ld-mips-elf/elf-rel-xgot-n64-linux.d: Likewise.
+	* ld-mips-elf/elf-rel-xgot-n64.d: Likewise.
+
+2008-03-17  Richard Sandiford  <rsandifo@nildram.co.uk>
+
+	* ld-mips-elf/eh-frame1-n32.d: Expect a warning about .eh_frame_hdr.
+	Remove duplicate CIEs.  Adjust relocation addresses and .eh_frame
+	offsets accordingly.  Do not allow there to be any trailing
+	R_MIPS_NONE relocations.
+	* ld-mips-elf/eh-frame1-n64.d: Likewise.
+	* ld-mips-elf/eh-frame2-n32.d: Likewise.
+	* ld-mips-elf/eh-frame2-n64.d: Likewise.
+
+2008-03-17  Richard Sandiford  <rsandifo@nildram.co.uk>
+
+	* ld-mips-elf/mips-elf.exp (o32_as_flags, o32_ld_flags): New variables.
+	(mips16_call_global_test, mips16_intermix_test): Use them.
+
+2008-03-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/5789
+	PR ld/5943
+	* ld-i386/hidden1.d: New.
+	* ld-i386/hidden1.s: Likewise.
+	* ld-i386/hidden2.d: Likewise.
+	* ld-i386/hidden2.s: Likewise.
+	* ld-i386/hidden3.d: Likewise.
+	* ld-i386/hidden4.s: Likewise.
+	* ld-i386/protected1.d: Likewise.
+	* ld-i386/protected1.s: Likewise.
+	* ld-i386/protected2.d: Likewise.
+	* ld-i386/protected2.s: Likewise.
+	* ld-i386/protected3.d: Likewise.
+	* ld-i386/protected3.s: Likewise.
+	* ld-x86-64/hidden1.d: Likewise.
+	* ld-x86-64/hidden1.s: Likewise.
+	* ld-x86-64/hidden2.d: Likewise.
+	* ld-x86-64/hidden2.s: Likewise.
+	* ld-x86-64/hidden3.d: Likewise.
+	* ld-x86-64/hidden3.s: Likewise.
+	* ld-x86-64/protected1.d: Likewise.
+	* ld-x86-64/protected1.s: Likewise.
+	* ld-x86-64/protected2.d: Likewise.
+	* ld-x86-64/protected2.s: Likewise.
+	* ld-x86-64/protected3.d: Likewise.
+	* ld-x86-64/protected3.s: Likewise.
+
+	* ld-i386/i386.exp: Run hidden1, hidden2, hidden3, protected1,
+	protected2 and protected3.
+	* ld-x86-64/x86-64.exp: Likewise.
+
+2008-03-14  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-spu/ovl2.s: Make setjmp global.
+	* ld-spu/ovl2.d: Update.
+
+2008-03-12  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 5900
+	* ld-elf/sec64k.exp: Update.
+
+2008-03-08  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-elf.exp (armeabitests): Add thumb2-b-interwork.
+	* ld-arm/thumb2-b-interwork.d: New test.
+	* ld-arm/thumb2-b-interwork.s: New test.
+
+2008-03-07  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-elf.exp (armelftests): Add movw-merge and arm-app-movw.
+	* ld-arm/arm-app-movw.s: New test.
+	* ld-arm/arm-app.r: Update expected output.
+	* ld-arm/movw-merge.d: New test.
+	* ld-arm/movw-merge.s: New test.
+
+2008-03-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/relbrlt.d: Update.  Also check .branch_lt section.
+
+2008-02-27  Catherine Moore  <clm@codesourcery.com>
+
+	* ld-cris/libdso-10.d: Update expected output for the Dynamic
+	Section to allow an arbitrary number of spaces.
+
+2008-02-20  Mark Mitchell  <mark@codesourcery.com>
+
+	ld/testsuite/
+	* ld-elf/seg.d: Expect .reginfo section on MIPS.
+
+2008-02-20  Pedro Alves  <pedro_alves@portugalmail.pt>
+
+	* ld-auto-import/auto-import.exp: Use $ld to link the dll for
+	cygwin, not $CC.
+
+2008-02-18  Hans-Peter Nilsson  <hp@axis.com>
+
+	* lib/ld-lib.exp (run_dump_test): Don't apply prune_warnings
+	for tool invocations where warnings or errors can be matched.
+
+2008-02-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-shared/sh1.c (shlib_overriddencall2): Moved to ...
+	* ld-shared/sh2.c (shlib_overriddencall2): Here.  New.
+
+2008-02-07  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-spu/ovl.d: Update.
+	* ld-spu/ovl2.d: Update.
+
+2008-02-04  Bob Wilson  <bob.wilson@acm.org>
+
+	* ld-undefined/undefined.exp: XFAIL for xtensa*-*-linux*.
+	
+2008-01-31  Marc Gauthier  <marc@tensilica.com>
+
+	* ld-elf/merge.d: Recognize Xtensa processor variants.
+	* ld-xtensa/coalesce.exp: Likewise.
+	* ld-xtensa/lcall.exp: Likewise.
+
+2008-01-28  Petr Muller  <pmuller@redhat.com>
+
+	* ld-elfvers/vers.exp (test_ar): Sort the expected output so that
+	it has matches the ordering of the obtained output.
+
+2008-01-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/eh1.d: Replace DW_CFA_def_cfa_reg with
+	DW_CFA_def_cfa_register. Updated for i386/x86-64 register
+	names.
+	* ld-elf/eh2.d: Likewise.
+	* ld-elf/eh3.d: Likewise.
+	* ld-elf/eh4.d: Likewise.
+	* ld-elf/eh5.d: Likewise.
+
+2008-01-28  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-spu/ovl.d: Update.
+	* ld-spu/ovl2.d: Update.
+
+2008-01-26  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/loadaddr.t: New, extracted from..
+	* ld-elf/loadaddr1.t: ..here.  Use insert.
+	* ld-elf/loadaddr2.t: Likewise.
+	* ld-elf/loadaddr1.d: Update.
+	* ld-elf/loadaddr2.d: Update.
+
+2008-01-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-spu/ovl.lnk: Delete overlay.
+	* ld-spu/ovl1.lnk: New file.
+	* ld-spu/ovl2.lnk: New file.
+	* ld-spu/ovl.d: Update.
+	* ld-spu/ovl2.d: Update.
+
+2008-01-23  Andreas Schwab  <schwab@suse.de>
+
+	* ld-gc/gc.c: Make sure used_func is not inlined.
+
+2008-01-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-gc/gc.exp: Use [which $CC] != 0.
+
+2008-01-14  Tristan Gingold  <gingold@adacore.com>
+
+	* ld-gc/gc.exp (test_gc): Let missing C compiler make tests
+	"untested" instead of "failed".
+
+2008-01-10  Tristan Gingold  <gingold@adacore.com>
+
+	* lib/ld-lib.exp (check_gc_sections_available): Now available on
+	VxWorks.
+	* ld-gc: New directory for testing --gc-sections.
+	* ld-gc/gc.c: New file.
+	* ld-gc/gc.exp: New file.
+	* ld-gc/noent.s: New file.
+	* ld-gc/noent.d: New file.
+
+2008-01-09  Richard Sandiford  <rsandifo@nildram.co.uk>
+
+	PR ld/5526
+	* ld-elf/eh6.s, ld-elf/eh6.d: New test.
+
+2008-01-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/5522
+	* ld-elf/noload-3.d: New file.
+	* ld-elf/noload-3.s: Likewise.
+	* ld-elf/noload-3.t: Likewise.
+
+For older changes see ChangeLog-2007
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.19/ld/testsuite/ChangeLog-2004 b/binutils-2.19/ld/testsuite/ChangeLog-2004
new file mode 100644
index 0000000..cc63b7e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ChangeLog-2004
@@ -0,0 +1,1085 @@
+2004-12-21  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* ld-crx/reloc-abs32.d: Update reference file according
+	to disassembler printing method.
+	* ld-crx/reloc-rel16.d: Likewise.
+	* ld-crx/reloc-rel24.d: Likewise.
+	* ld-crx/reloc-rel32.d: Likewise.
+	* ld-crx/reloc-rel4.d: Likewise.
+	* ld-crx/reloc-rel8-cmp.d: Likewise.
+	* ld-crx/reloc-rel8.d: Likewise.
+
+2004-12-16  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-v850: New directory.
+
+2004-12-14  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-mips-elf/jal-overflow-2.[sd]: New test.
+	* ld-mips-elf/mips-elf.exp: Run it.
+
+2004-12-13  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-mips-elf/mips-elf.exp: Only run jalbal if n32 is supported.
+
+2004-12-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-mmix/bpo-1.d: Update for changed section syms.
+	* ld-mmix/bpo-10.d: Likewise.
+	* ld-mmix/bpo-11.d: Likewise.
+	* ld-mmix/bpo-14.d: Likewise.
+	* ld-mmix/bpo-16.d: Likewise.
+	* ld-mmix/bpo-17.d: Likewise.
+	* ld-mmix/bpo-18.d: Likewise.
+	* ld-mmix/bpo-19.d: Likewise.
+	* ld-mmix/bpo-2.d: Likewise.
+	* ld-mmix/bpo-22.d: Likewise.
+	* ld-mmix/bpo-3.d: Likewise.
+	* ld-mmix/bpo-4.d: Likewise.
+	* ld-mmix/bpo-5.d: Likewise.
+	* ld-mmix/bpo-6.d: Likewise.
+	* ld-mmix/bpo-9.d: Likewise.
+	* ld-mmix/greg-1.d: Likewise.
+	* ld-mmix/greg-19.d: Likewise.
+	* ld-mmix/greg-2.d: Likewise.
+	* ld-mmix/greg-3.d: Likewise.
+	* ld-mmix/greg-4.d: Likewise.
+	* ld-mmix/greg-5.d: Likewise.
+	* ld-mmix/greg-5s.d: Likewise.
+	* ld-mmix/greg-6.d: Likewise.
+	* ld-mmix/greg-7.d: Likewise.
+	* ld-mmix/loc1.d: Likewise.
+	* ld-mmix/loc2.d: Likewise.
+	* ld-mmix/loc3.d: Likewise.
+	* ld-mmix/loc4.d: Likewise.
+	* ld-mmix/loc6.d: Likewise.
+	* ld-mmix/locdo-1.d: Likewise.
+	* ld-mmix/loct-1.d: Likewise.
+	* ld-mmix/locto-1.d: Likewise.
+	* ld-mmix/start-1.d: Likewise.
+	* ld-sh/sh64/abi32.xd: Likewise.
+	* ld-sh/sh64/abi64.xd: Likewise.
+	* ld-sh/sh64/cmpct1.xd: Likewise.
+	* ld-sh/sh64/mix1.xd: Likewise.
+	* ld-sh/sh64/mix2.xd: Likewise.
+	* ld-sh/sh64/rel32.xd: Likewise.
+	* ld-sh/sh64/rel64.xd: Likewise.
+	* ld-sh/sh64/shdl32.xd: Likewise.
+	* ld-sh/sh64/shdl64.xd: Likewise.
+
+2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
+
+	* ld-mips-elf/jalbal.d: New test.
+	* ld-mips-elf/jalbal.s: New test.
+	* ld-mips-elf/mips-elf.exp: Run it.
+
+2004-12-08  Ian Lance Taylor  <ian@wasabisystems.com>
+
+	* ld-mips-elf/jaloverflow.d: New test.
+	* ld-mips-elf/jaloverflow.s: New test.
+	* ld-mips-elf/mips-elf.exp: Run it.
+
+2004-12-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/group1.d: Support 64bit.
+
+2004-12-01  Paul Brook  <paul@codesourcery.com>
+
+	* ld-elf/group1.d: New test.
+	* ld-elf/group.ld, ld-elf/group1a.s, ld-elf/group1b.s: New test.
+
+2004-12-01  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-selective/selective.exp: Use -print-libgcc-file-name for
+	ARM and v850 also.
+
+2004-11-24  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/mixed-lib.sym: Update for THUMB_FUNC change.
+
+2004-11-19  Nick Clifton  <nickc@redhat.com>
+
+	* ld-scripts/script.exp: Add test of memory linker script.
+	Reorganise code to remove unnecessary indentation.
+	Fix target tests to avoid using --image-base with *-nto targets.
+	* ld-scripts/memory.t: New linker script to test the MEMORY
+	section and the ORIGIN and LENGTH operators.
+
+2004-11-17  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-arm/mixed-app.d, ld-arm/mixed-app.r, ld-arm/mixed-app.s,
+	ld-arm/mixed-app.sym, ld-arm/mixed-lib.d, ld-arm/mixed-lib.r,
+	ld-arm/mixed-lib.s, ld-arm/mixed-lib.sym, ld-arm/arm-dyn.ld,
+	ld-arm/arm-lib.ld: New files.
+	* ld-arm/arm-app-abs32.d, ld-arm/arm-app-abs32.r, ld-arm/arm-app.d,
+	ld-arm/arm-app.r, ld-arm/arm-lib-plt32.d, ld-arm/arm-lib-plt32.r,
+	ld-arm/arm-lib.d, ld-arm/arm-lib.r, ld-arm/arm-static-app.d,
+	ld-arm/arm-static-app.r: Update for big-endian.
+	* ld-arm/arm-elf.exp: Run the new tests.
+
+2004-11-16  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-mips-elf/eh-frame1.{s,ld},
+	* ld-mips-elf/eh-frame1-{n32,n64},d: New test.
+	* ld-mips-elf/mips-elf.exp: Run it.
+
+2004-11-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-d10v/reloc-003.d: Update for changed error message.
+	* ld-d10v/reloc-004.d: Likewise.
+	* ld-d10v/reloc-007.d: Likewise.
+	* ld-d10v/reloc-008.d: Likewise.
+	* ld-d10v/reloc-011.d: Likewise.
+	* ld-d10v/reloc-012.d: Likewise.
+	* ld-d10v/reloc-015.d: Likewise.
+	* ld-d10v/reloc-016.d: Likewise.
+
+2004-11-08  Aaron W. LaFramboise <aaron98wiridge9@aaronwl.com>
+
+	* ld-scripts/weak.exp: Enable test on PE, XFAIL non-i386 PE.
+	* ld-undefined/weak-undef.exp: Enable test on PE, XFAIL non-i386
+	PE.
+	* lib/ld-lib.exp (is_pecoff_format): New.
+
+2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
+	    Vineet Sharma      <vineets@noida.hcltech.com>
+
+	* ld-maxq: New directory.  Contains tests for the new maxq port.
+
+2004-11-04  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-elf/merge.d: xfail crisv32-*-*.
+	* ld-cris/dsov32-1.s, ld-cris/dsov32-2.s, ld-cris/dsov32-3.s,
+	ld-cris/dsov32-4.s, ld-cris/libdso-10.d, ld-cris/libdso-11.d,
+	ld-cris/libdso-12.d, ld-cris/libdso-13.d, ld-cris/libdso-14.d,
+	ld-cris/move-1.s, ld-cris/pv32-1.d, ld-cris/pv32.s,
+	ld-cris/start1.s, ld-cris/v10-v32.d, ld-cris/v10-va.d,
+	ld-cris/v32-ba-1.d, ld-cris/v32-ba-1.s, ld-cris/v32-bin-1.d,
+	ld-cris/v32-bin-1.s, ld-cris/v32-v10.d, ld-cris/v32-va.d,
+	ld-cris/va-v10.d, ld-cris/va-v32.d: New tests.
+	* ld-cris/ldsym1.d: Adjust for change in linker script.
+
+2004-11-02  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/expdyn1.d, ld-cris/expdyn5.d, ld-cris/expdyn6.d,
+	ld-cris/expdyn7.d, ld-cris/gotplt1.d, ld-cris/gotplt2.d,
+	ld-cris/gotplt3.d, ld-cris/hiddef1.d, ld-cris/libdso-2.d,
+	ld-cris/locref1.d, ld-cris/locref2.d, ld-cris/weakref2.d,
+	ld-i386/tlsbin.rd, ld-i386/tlsnopic.rd, ld-i386/tlspic.rd,
+	ld-ia64/tlsbin.dd, ld-ia64/tlsbin.rd, ld-ia64/tlspic.dd,
+	ld-ia64/tlspic.rd, ld-powerpc/tlsexe32.d, ld-powerpc/tlsexe32.g,
+	ld-powerpc/tlsexe32.r, ld-powerpc/tlsexe32.t,
+	ld-powerpc/tlsso32.d, ld-powerpc/tlsso32.g, ld-powerpc/tlsso32.r,
+	ld-powerpc/tlsso32.t, ld-s390/tlsbin.dd, ld-s390/tlsbin.rd,
+	ld-s390/tlspic.rd, ld-sparc/tlssunbin32.rd,
+	ld-sparc/tlssunpic32.rd, ld-x86-64/tlsbin.rd, ld-x86-64/tlspic.dd,
+	ld-x86-64/tlspic.rd: Adjust for _GLOBAL_OFFSET_TABLE_ now hidden.
+
+2004-10-26  Paul Brook  <paul@codesourcery.com>
+
+	* ld-elfvers/vers.exp (build_binary): Add ldargs parameter.
+	(build_vers_lib_pic_flags): New function.
+	Add vers29 test.
+	* ld-elfvers/vers29.c: New file.
+	* ld-elfvers/vers29.dsym: New file.
+	* ld-elfvers/vers29.ver: New file.
+
+2004-10-24  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/sec-8m.d: Adjust test for dump using correct section
+	length.
+	* ld-mmix/sec-9.d: Renamed test, formerly known as sec-5.d.
+	* ld-mmix/sec-5.d, ld-mmix/b-offloc.s: Rewritten test.
+
+	* ld-mmix/getaa-6b.d, ld-mmix/getaa-6f.d, ld-mmix/getaa14b.d,
+	ld-mmix/getaa14f.d, ld-mmix/jumpa-6b.d, ld-mmix/jumpa-6f.d,
+	ld-mmix/jumpa14b.d, ld-mmix/jumpa14f.d, ld-mmix/reg-1.d,
+	ld-mmix/reg-1m.d: Adjust for changed error message format.
+
+2004-10-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/exclude.exp: Allow cris-*-elf.
+
+	* ld-elf/exclude1.s: Add ".data". Remove "- include_sym".
+	* ld-elf/exclude2.s: Add ".data".
+
+2004-10-19  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-elf/exclude.exp: Don't run for cris-*-elf.
+
+2004-10-16  Daniel Jacobowitz  <dan@debian.org>
+
+	* ld-elf/exclude1.s, ld-elf/exclude2.s, ld-elf/exclude.exp: New.
+
+2004-10-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-crx/reloc-num8.d: Adjust for changed orphan placement.
+	* ld-crx/reloc-num16.d: Likewise.
+	* ld-crx/reloc-num32.d: Likewise.
+	* ld-scripts/provide-2.t: Start .data at 0x2000.
+	* ld-scripts/provide-2.d: Adjust.
+
+2004-10-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-scripts/sort.exp: Run for ELF targets only.
+
+2004-10-14  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/overlay-size.d: Update for changed orphan section
+	placement.
+	* ld-mmix/bpo-18.d: Likewise.
+
+2004-10-07  Bob Wilson  <bob.wilson@acm.org>
+
+	* ld-xtensa/lcall1.s: Use .literal directive.
+	* ld-xtensa/lcall2.s: Align function entry.
+	* ld-xtensa/coalesce2.s: Likewise.
+
+2004-10-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-scripts/sort.exp: New file for section sorting tests.
+	* ld-scripts/sort_b_a.d: Likewise
+	* ld-scripts/sort_b_a.s: Likewise
+	* ld-scripts/sort_b_a.t: Likewise
+	* ld-scripts/sort_b_a_a-1.d: Likewise
+	* ld-scripts/sort_b_a_a-2.d: Likewise
+	* ld-scripts/sort_b_a_a-3.d: Likewise
+	* ld-scripts/sort_b_a_a.t: Likewise
+	* ld-scripts/sort_b_a_n-1.d: Likewise
+	* ld-scripts/sort_b_a_n-2.d: Likewise
+	* ld-scripts/sort_b_a_n-3.d: Likewise
+	* ld-scripts/sort_b_a_n.t: Likewise
+	* ld-scripts/sort_b_n.d: Likewise
+	* ld-scripts/sort_b_n.s: Likewise
+	* ld-scripts/sort_b_n.t: Likewise
+	* ld-scripts/sort_b_n_a-1.d: Likewise
+	* ld-scripts/sort_b_n_a-2.d: Likewise
+	* ld-scripts/sort_b_n_a-3.d: Likewise
+	* ld-scripts/sort_b_n_a.t: Likewise
+	* ld-scripts/sort_b_n_n-1.d: Likewise
+	* ld-scripts/sort_b_n_n-2.d: Likewise
+	* ld-scripts/sort_b_n_n-3.d: Likewise
+	* ld-scripts/sort_b_n_n.t: Likewise
+	* ld-scripts/sort_n_a-a.s: Likewise
+	* ld-scripts/sort_n_a-b.s: Likewise
+	* ld-scripts/sort_no-1.d: Likewise
+	* ld-scripts/sort_no-2.d: Likewise
+	* ld-scripts/sort_no.t: Likewise
+
+2004-10-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-powerpc/tls.s: Don't set tls type for undefined syms.
+	* ld-powerpc/tls32.s: Likewise.
+	* ld-powerpc/tlstoc.s: Likewise.
+	* ld-s390/tlsbin.s: Likewise.
+	* ld-s390/tlsbin_64.s: Likewise.
+	* ld-s390/tlsbinpic.s: Likewise.
+	* ld-s390/tlsbinpic_64.s: Likewise.
+	* ld-s390/tlspic1.s: Likewise.
+	* ld-s390/tlspic1_64.s: Likewise.
+	* ld-sparc/tlssunbin32.s: Likewise.
+	* ld-sparc/tlssunbinpic32.s: Likewise.
+	* ld-sparc/tlssunnopic32.s: Likewise.
+	* ld-sparc/tlssunpic32.s: Likewise.
+
+2004-10-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-s390/tlsbin.s: Set tls type for undefined syms.
+	* ld-s390/tlsbin_64.s: Likewise.
+	* ld-s390/tlsbinpic.s: Likewise.
+	* ld-s390/tlsbinpic_64.s: Likewise.
+	* ld-s390/tlspic1.s: Likewise.
+	* ld-s390/tlspic1_64.s: Likewise.
+	* ld-sparc/tlssunbin32.s: Likewise.
+	* ld-sparc/tlssunbinpic32.s: Likewise.
+	* ld-sparc/tlssunnopic32.s: Likewise.
+	* ld-sparc/tlssunpic32.s: Likewise.
+
+2004-10-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-sparc/tlssunbin32.sd: Adjust for changed .dynamic location.
+
+2004-10-01  Nick Clifton  <nickc@redhat.com>
+
+	PR 371
+	* ld-undefined/undefined.exp: Remove redundant XPASS
+	specifications.
+
+2004-10-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tls.s (gd, ld): Set tls type for undefined syms.
+	* ld-powerpc/tls32.s (gd, ld): Likewise.
+	* ld-powerpc/tlstoc.s (gd, ld): Likewise.
+	* ld-powerpc/tlsso.r: Update.
+	* ld-powerpc/tlsso32.r: Update.
+	* ld-powerpc/tlstocso.r: Update.
+
+2004-09-30  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-elf.exp: Add test for --target2=abs.
+	* ld-arm/arm-target2-abs.d: New file.
+
+2004-09-29  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-pe/secrel1.s: Pad .rdata out to 16 byte boundary.
+	* ld-pe/secrel.d: Adjust to suit.
+
+2004-09-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elfvsb/elfvsb.exp: Remove file name from "undefined ref" string.
+
+2004-09-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-i386/tlsbin.rd: Update for changed segment map.
+	* ld-i386/tlsnopic.rd: Likewise.
+	* ld-i386/tlspic.rd: Likewise.
+	* ld-powerpc/tlsexe.r: Likewise.
+	* ld-powerpc/tlsexe32.r: Likewise.
+	* ld-powerpc/tlsexetoc.r: Likewise.
+	* ld-powerpc/tlsso.r: Likewise.
+	* ld-powerpc/tlsso32.r: Likewise.
+	* ld-powerpc/tlstocso.r: Likewise.
+	* ld-s390/tlsbin.rd: Likewise.
+	* ld-s390/tlsbin_64.rd: Likewise.
+	* ld-s390/tlspic.rd: Likewise.
+	* ld-s390/tlspic_64.rd: Likewise.
+	* ld-sh/tlsbin-2.d: Likewise.
+	* ld-sh/tlspic-2.d: Likewise.
+	* ld-x86-64/tlsbin.rd: Likewise.
+	* ld-x86-64/tlspic.rd: Likewise.
+
+2004-09-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/overlay-size.d: Don't check .mbss lma.
+	* ld-sh/sh64/mix1.xd: Update for changed .bss file offset.
+	* ld-sh/sh64/shdl32.xd: Likewise.
+	* ld-sh/sh64/shdl64.xd: Likewise.
+
+2004-09-17  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-target1-{abs,rel}.d}: New files.
+	* ld-arm/arm-target1.s: New file.
+	* ld-arm/arm-target2-{,got-}rel.d: New files.
+	* ld-arm/arm-target2.s: New file.
+	* ld-arm/arm-rel31.d: New files.
+	* ld-arm/arm-rel31.s: New files.
+	* ld-arm/arm.ld: New file.
+	* ld-arm/arm-elf.exp: Add new tests.
+
+2004-09-07  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/hiddef1.d, ld-cris/hiddef1.s, ld-cris/hidrefgotplt1.s:
+	New test.
+
+2004-09-03  Tomer Levi  <Tomer.Levi@nsc.com>
+
+	* ld-crx: New directory.
+	* ld-crx/crx.exp: New test script.
+	* ld-crx/crx.ld: New linker script.
+	* ld-crx/reloc-abs32.s: New file.
+	* ld-crx/reloc-abs32.d: Likewise.
+	* ld-crx/reloc-imm16.s: Likewise.
+	* ld-crx/reloc-imm16.d: Likewise.
+	* ld-crx/reloc-imm32.s: Likewise.
+	* ld-crx/reloc-imm32.d: Likewise.
+	* ld-crx/reloc-num8.s: Likewise.
+	* ld-crx/reloc-num8.d: Likewise.
+	* ld-crx/reloc-num16.s: Likewise.
+	* ld-crx/reloc-num16.d: Likewise.
+	* ld-crx/reloc-num32.s: Likewise.
+	* ld-crx/reloc-num32.d: Likewise.
+	* ld-crx/reloc-regrel12.s: Likewise.
+	* ld-crx/reloc-regrel12.d: Likewise.
+	* ld-crx/reloc-regrel22.s: Likewise.
+	* ld-crx/reloc-regrel22.d: Likewise.
+	* ld-crx/reloc-regrel28.s: Likewise.
+	* ld-crx/reloc-regrel28.d: Likewise.
+	* ld-crx/reloc-regrel32.s: Likewise.
+	* ld-crx/reloc-regrel32.d: Likewise.
+	* ld-crx/reloc-rel4.s: Likewise.
+	* ld-crx/reloc-rel4.d: Likewise.
+	* ld-crx/reloc-rel8.s: Likewise.
+	* ld-crx/reloc-rel8.d: Likewise.
+	* ld-crx/reloc-rel8-cmp.s: Likewise.
+	* ld-crx/reloc-rel8-cmp.d: Likewise.
+	* ld-crx/reloc-rel16.s: Likewise.
+	* ld-crx/reloc-rel16.d: Likewise.
+	* ld-crx/reloc-rel24.s: Likewise.
+	* ld-crx/reloc-rel24.d: Likewise.
+	* ld-crx/reloc-rel32.s: Likewise.
+	* ld-crx/reloc-rel32.d: Likewise.
+
+2004-08-21  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/expdyn1.d, ld-cris/expdyn5.d, ld-cris/expdyn6.d,
+	ld-cris/expdyn7.d, ld-cris/gotplt2.d, ld-cris/gotplt3.d,
+	ld-cris/libdso-1.d, ld-cris/libdso-2.d, ld-cris/locref1.d,
+	ld-cris/nodyn4.d, ld-cris/nodyn5.d: Adjust for reordered
+	sections.
+
+2004-08-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elfvsb/elfvsb.exp: Cope with ppc64 dot symbols.
+
+2004-08-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/cross1.t: Remove .opd section spec.
+
+2004-08-01  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* ld-undefined/undefined.exp: The undefine tests now work on
+	68HC11 and 68HC12.
+
+2004-07-29  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/sh64/crange3-cmpct.rd: Update.
+	* ld-sh/sh64/crange3-media.rd: Update.
+
+2004-07-27  Nitin Yewale  <nitiny@kpitcummins.com>
+
+	* ld-h8300/h8300.exp: Addition of new test case to check
+	relaxation for H8S target.
+	* ld-h8300/relax-6.s: New test source file.
+	* ld-h8300/relax-6.d: New test expected disassembly file.
+	* ld-h8300/relax-6-coff.d: New test expected disassembly file for
+	coff format.
+
+2004-07-22  Nick Clifton  <nickc@redhat.com>
+
+	PR/280
+	* ld-h8300/relax-3-coff.d: Remove duplicated raw insn values.
+	* ld-h8300/relax-3.d: Likewise.
+	* ld-h8300/relax-4-coff.d: Likewise.
+	* ld-h8300/relax-4.d: Likewise.
+	* ld-h8300/relax-5-coff.d: Likewise.
+	* ld-h8300/relax.d: Likewise.
+
+2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-scripts/crossref.exp: XFAIL ia64-*-* on the first test.
+
+2004-07-13  Nitin Yewale <nitiny@kpitcummins.com>
+
+	* ld-h8300/h8300.exp: Addition of gcsection test case.
+	* ld-h8300/gcsection.s: New test source file.
+	* ld-h8300/gcsection.d: New test expected disassembly file.
+
+2004-07-08  Maciej W. Rozycki  <macro@linux-mips.org>
+
+	* ld-mips-elf/reloc-merge-lo16.{s,d,ld}: New test.
+	* ld-mips-elf/mips-elf.exp: Run it.
+
+2004-07-02  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-elf/frame.exp: Don't run on sh*-*-elf*.
+	* ld-sh/shared-1.d: Adjust for section reordering changes.
+	* ld-sh/shared-2.d: Likewise.
+	* ld-sh/tlsbin-2.d: Likewise.
+	* ld-sh/tlspic-2.d: Likewise.
+	* ld-sh/sh64/abi32.xd: Likewise.
+	* ld-sh/sh64/abi64.xd: Likewise.
+	* ld-sh/sh64/cmpct1.xd: Likewise.
+	* ld-sh/sh64/crange1.rd: Likewise.
+	* ld-sh/sh64/crange2.rd: Likewise.
+	* ld-sh/sh64/crange3-cmpct.rd: Likewise.
+	* ld-sh/sh64/crange3-media.rd: Likewise.
+	* ld-sh/sh64/crange3.rd: Likewise.
+	* ld-sh/sh64/gotplt.d: Likewise.
+	* ld-sh/sh64/init-cmpct.d: Likewise.
+	* ld-sh/sh64/init-media.d: Likewise.
+	* ld-sh/sh64/init64.d: Likewise.
+	* ld-sh/sh64/mix1.xd: Likewise.
+	* ld-sh/sh64/mix2.xd: Likewise.
+	* ld-sh/sh64/shdl32.xd: Likewise.
+	* ld-sh/sh64/shdl64.xd: Likewise.
+
+2004-07-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-discard/static.d: Accept both original sym and section sym.
+
+2004-07-01  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-sparc/tlssunpic32.rd: Adjust for section reordering changes
+	and removal of unneeded STT_SECTION symbols from .dynsym.
+	* ld-sparc/tlssunbin32.rd: Likewise.
+	* ld-sparc/tlssunpic32.dd: Likewise.
+	* ld-sparc/tlssunpic32.sd: Likewise.
+	* ld-sparc/tlssunbin32.dd: Likewise.
+	* ld-sparc/tlssunbin32.sd: Likewise.
+	* ld-sparc/tlssunbin32.td: Likewise.
+
+2004-07-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-discard/extern.d: Update.
+	* ld-discard/start.d: Update.
+	* ld-discard/static.d: Update.
+
+2004-06-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 233
+	* ld-discard/extern.d: Updated.
+	* ld-discard/start.d: Likewise.
+	* ld-discard/static.d: Likewise.
+
+2004-06-29  J"orn Rennecke <joern.rennecke@superh.com>
+
+	Actually add these files:
+	2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
+	* ld-sh/arch/arch.exp: New test script.
+	* ld-sh/arch/arch_expected.txt: New file.
+	* ld-sh/arch/sh.s: New file.
+	* ld-sh/arch/sh2.s: New file.
+	* ld-sh/arch/sh-dsp.s: New file.
+	* ld-sh/arch/sh2e.s: New file.
+	* ld-sh/arch/sh3-nommu.s: New file.
+	* ld-sh/arch/sh3.s: New file.
+	* ld-sh/arch/sh3-dsp.s: New file.
+	* ld-sh/arch/sh3e.s: New file.
+	* ld-sh/arch/sh4-nommu-nofpu.s: New file.
+	* ld-sh/arch/sh4-nofpu.s: New file.
+	* ld-sh/arch/sh4.s: New file.
+	* ld-sh/arch/sh4a-nofpu.s: New file.
+	* ld-sh/arch/sh4al-dsp.s: New file.
+	* ld-sh/arch/sh4a.s: New file.
+
+2004-06-29  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/frame.exp: Don't run on mcore.
+
+2004-06-26  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-bootstrap/bootstrap.exp: Handle timestamps in more pe targets.
+
+2004-06-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elfvers/vers.exp: Use PIC for shared libraries by default.
+
+2004-06-21  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-frv/fdpic-pie-1.d: Adjust for pie-specific link script.
+	* ld-frv/fdpic-pie-2.d: Likewise.
+	* ld-frv/fdpic-pie-6.d: Likewise.
+	* ld-frv/fdpic-pie-7.d: Likewise.
+	* ld-frv/fdpic-pie-8.d: Likewise.
+	* ld-frv/fdpic-shared-1.d: Likewise.
+	* ld-frv/fdpic-shared-2.d: Likewise.
+	* ld-frv/fdpic-shared-3.d: Likewise.
+	* ld-frv/fdpic-shared-4.d: Likewise.
+	* ld-frv/fdpic-shared-5.d: Likewise.
+	* ld-frv/fdpic-shared-6.d: Likewise.
+	* ld-frv/fdpic-shared-7.d: Likewise.
+	* ld-frv/fdpic-shared-8.d: Likewise.
+	* ld-frv/fdpic-shared-local-2.d: Likewise.
+	* ld-frv/fdpic-shared-local-8.d: Likewise.
+
+2004-06-21  Nick Clifton  <nickc@redhat.com>
+
+	* ld-elf/frame.exp: Handle ports which do not support the --shared
+	linker switch.
+
+2004-06-18 Jan Beulich <jbeulich@novell.com>
+
+	* ld-elfvsb/main.c: Ensure visibility_def and visibility_func are
+	actually referenced (gcc 3.4 eliminates comparisons of addresses
+	of global symbols with NULL).
+	* ld-selective/selective.exp: Suppress -fvtable-gc tests for gcc
+	3.4.0 and above, as this option and its functionality is no longer
+	supported, making these tests fail).
+
+2004-05-28  Andrew Stubbs <andrew.stubbs@superh.com>
+
+	* ld-sh/arch/arch.exp: New test script.
+	* ld-sh/arch/arch_expected.txt: New file.
+	* ld-sh/arch/sh.s: New file.
+	* ld-sh/arch/sh2.s: New file.
+	* ld-sh/arch/sh-dsp.s: New file.
+	* ld-sh/arch/sh2e.s: New file.
+	* ld-sh/arch/sh3-nommu.s: New file.
+	* ld-sh/arch/sh3.s: New file.
+	* ld-sh/arch/sh3-dsp.s: New file.
+	* ld-sh/arch/sh3e.s: New file.
+	* ld-sh/arch/sh4-nommu-nofpu.s: New file.
+	* ld-sh/arch/sh4-nofpu.s: New file.
+	* ld-sh/arch/sh4.s: New file.
+	* ld-sh/arch/sh4a-nofpu.s: New file.
+	* ld-sh/arch/sh4al-dsp.s: New file.
+	* ld-sh/arch/sh4a.s: New file.
+
+2004-05-18  Nick Clifton  <nickc@redhat.com>
+
+	* ld-elf/frame.s: Replace @ with % so that the file can be
+	compiled by an ARM targeted GAS.
+	* ld-elf/table.s: Likewise.
+	* ld-elf/tbss.s: Likewise.  Also replace .align <foo> with
+	.p2align (log2 <foo>) to cope with the fact that the ARM .align
+	directive takes a power-of-two argument.
+
+2004-05-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/frame.exp: New file. Test read-only .eh_frame and
+	.gcc_except_table sections.
+	* ld-elf/frame.s: Likewise.
+	* ld-elf/table.s: Likewise.
+	* ld-elf/tbss.s: Likewise.
+
+2004-05-12  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/tlsbin-2.d: Adjust for section reordering changes
+	and removal of unneeded STT_SECTION symbols from .dynsym.
+	* ld-sh/tlsbin-3.d: Likewise.
+	* ld-sh/tlspic-2.d: Likewise.
+
+2004-05-12  Ben Elliston  <bje@au.ibm.com>
+
+	* ld-sh/sh64/relax.exp: Remove stray semicolons.
+	* ld-sh/sh64/relfail.exp: Likewise.
+	* lib/ld-lib.exp: Likewise.
+
+2004-05-11  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-i386/tlspic.rd: Adjust for section reordering changes
+	and removal of unneeded STT_SECTION symbols from .dynsym.
+	* ld-i386/tlspic.dd: Likewise.
+	* ld-i386/tlspic.sd: Likewise.
+	* ld-i386/tlsbin.rd: Likewise.
+	* ld-i386/tlsbinpic.s: Likewise.
+	* ld-i386/tlsbin.dd: Likewise.
+	* ld-i386/tlsbin.sd: Likewise.
+	* ld-i386/tlsnopic.rd: Likewise.
+	* ld-i386/tlsnopic1.s: Likewise.
+	* ld-i386/combreloc.d: Likewise.
+	* ld-i386/tlsnopic.dd: Likewise.
+	* ld-i386/tlsnopic.sd: Likewise.
+	* ld-x86-64/tlspic.rd: Likewise.
+	* ld-x86-64/tlspic.dd: Likewise.
+	* ld-x86-64/tlsbin.dd: Likewise.
+	* ld-x86-64/tlspic.sd: Likewise.
+	* ld-x86-64/tlsbin.sd: Likewise.
+	* ld-x86-64/tlspic.td: Likewise.
+	* ld-x86-64/tlsbin.td: Likewise.
+	* ld-x86-64/tlsbin.rd: Likewise.
+	* ld-s390/tlspic1.s: Likewise.
+	* ld-s390/tlsbinpic.s: Likewise.
+	* ld-s390/tlspic.rd: Likewise.
+	* ld-s390/tlsbin.rd: Likewise.
+	* ld-s390/tlspic.dd: Likewise.
+	* ld-s390/tlsbin.dd: Likewise.
+	* ld-s390/tlsbin.sd: Likewise.
+	* ld-s390/tlsbin.td: Likewise.
+	* ld-s390/tlspic.sd: Likewise.
+	* ld-s390/tlspic.td: Likewise.
+	* ld-s390/tlspic1_64.s: Likewise.
+	* ld-s390/tlsbinpic_64.s: Likewise.
+	* ld-s390/tlspic_64.rd: Likewise.
+	* ld-s390/tlsbin_64.rd: Likewise.
+	* ld-s390/tlspic_64.dd: Likewise.
+	* ld-s390/tlsbin_64.dd: Likewise.
+	* ld-s390/tlspic_64.sd: Likewise.
+	* ld-s390/tlspic_64.td: Likewise.
+	* ld-s390/tlsbin_64.td: Likewise.
+	* ld-s390/tlsbin_64.sd: Likewise.
+	* ld-powerpc/tlsexe32.r: Likewise.
+	* ld-powerpc/tlsso32.r: Likewise.
+	* ld-powerpc/tlsso32.d: Likewise.
+	* ld-powerpc/tlsso32.g: Likewise.
+	* ld-powerpc/tlsso32.t: Likewise.
+	* ld-powerpc/tlsexe.r: Likewise.
+	* ld-powerpc/tlsso.r: Likewise.
+	* ld-powerpc/tlsso.g: Likewise.
+	* ld-powerpc/tlsexetoc.r: Likewise.
+	* ld-powerpc/tlstocso.r: Likewise.
+	* ld-powerpc/tlstocso.g: Likewise.
+	* ld-ia64/tlspic.rd: Likewise.
+	* ld-ia64/tlspic.dd: Likewise.
+	* ld-ia64/tlspic.sd: Likewise.
+	* ld-ia64/tlspic.td: Likewise.
+	* ld-ia64/tlsbin.rd: Likewise.
+	* ld-ia64/tlsbin.sd: Likewise.
+	* ld-ia64/tlsbin.td: Likewise.
+	* ld-elfvsb/elfvsb.exp: XFAIL non-PIC load offset tests on s390x.
+	* ld-shared/shared.exp: Likewise.
+
+2004-05-10  John Paul Wallington  <jpw@gnu.org>
+
+	* ld-mmix/bspec2.d: Update sh_info to decimal.
+	* ld-mmix/local1.d: Likewise.
+	* ld-mmix/local3.d: Likewise.
+	* ld-mmix/local5.d: Likewise.
+	* ld-mmix/local7.d: Likewise.
+
+2004-05-05  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-frv/fdpic.exp: Restore $LDFLAGS at the end.
+	* ld-frv/fr450-link.d: Match fdpic as well.
+
+2004-05-05  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/sh64/crange1.rd: Update sh_info to decimal.
+	* ld-sh/sh64/crange2.rd: Likewise.
+	* ld-sh/sh64/crange3.rd: Likewise.
+	* ld-sh/sh64/crange3-cmpct.rd: Likewise.
+	* ld-sh/sh64/crange3-media.rd: Likewise.
+	* ld-sh/sh64/crangerel1.rd: Likewise.
+	* ld-sh/sh64/crangerel2.rd: Likewise.
+
+2004-05-05  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexe.r: Update sh_info to decimal.
+	* ld-powerpc/tlsexe32.r: Likewise.
+	* ld-powerpc/tlsexetoc.r: Likewise.
+	* ld-powerpc/tlsso.r: Likewise.
+	* ld-powerpc/tlsso32.r: Likewise.
+	* ld-powerpc/tlstocso.r: Likewise.
+
+2004-04-24  Chris Demetriou  <cgd@broadcom.com>
+
+	* ld-elf/merge.d: XFAIL on all MIPS targets.
+
+2004-04-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexe32.d: Update.
+	* ld-powerpc/tlsso32.d: Update.
+
+2004-04-23  Chris Demetriou  <cgd@broadcom.com>
+
+	* ld-mips-elf/reloc-3-r.d: Remove, as part of MIPS -membedded-pic
+	removal.
+	* ld-mips-elf/reloc-3-srec.d: Likewise.
+	* ld-mips-elf/reloc-3.ld: Likewise.
+	* ld-mips-elf/reloc-3a.s: Likewise.
+	* ld-mips-elf/reloc-3b.s: Likewise.
+	* ld-mips-elf/mips-elf.exp: Don't run now-removed tests.
+
+2004-04-22  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/tlsbin-1.d: Update
+	* ld-sh/tlspic-1.d: Update.
+
+2004-04-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-i386/tlspic.dd: Updated.
+
+2004-04-21  Chris Demetriou  <cgd@broadcom.com>
+
+	* ld-empic/run.c: Removed as part of MIPS --embedded-relocs removal.
+	* ld-empic/empic.exp: Likewise.
+	* ld-empic/relax.t: Likewise.
+	* ld-empic/relax1.c: Likewise.
+	* ld-empic/relax2.c: Likewise.
+	* ld-empic/relax3.c: Likewise.
+	* ld-empic/relax4.c: Likewise.
+	* ld-empic/runtest1.c: Likewise.
+	* ld-empic/runtest2.c: Likewise.
+	* ld-empic/runtesti.s: Likewise.
+	* ld-mips-elf/empic1-ln.d: Likewise.
+	* ld-mips-elf/empic1-lp.d: Likewise.
+	* ld-mips-elf/empic1-mn.d: Likewise.
+	* ld-mips-elf/empic1-mp.d: Likewise.
+	* ld-mips-elf/empic1-ref.s: Likewise.
+	* ld-mips-elf/empic1-sn.d: Likewise.
+	* ld-mips-elf/empic1-sp.d: Likewise.
+	* ld-mips-elf/empic1-space.s: Likewise.
+	* ld-mips-elf/empic1-tgt.s: Likewise.
+	* ld-mips-elf/empic2-fwd-0.d: Likewise.
+	* ld-mips-elf/empic2-fwd-1.d: Likewise.
+	* ld-mips-elf/empic2-fwd-tgt.s: Likewise.
+	* ld-mips-elf/empic2-ref.s: Likewise.
+	* ld-mips-elf/empic2-rev-0.d: Likewise.
+	* ld-mips-elf/empic2-rev-1.d: Likewise.
+	* ld-mips-elf/empic2-rev-tgt.s: Likewise.
+	* ld-mips-elf/empic2-space.s: Likewise.
+	* ld-mips-elf/emrelocs-eb.d: Likewise.
+	* ld-mips-elf/emrelocs-el.d: Likewise.
+	* ld-mips-elf/emrelocs.ld: Likewise.
+	* ld-mips-elf/emrelocs1.s: Likewise.
+	* ld-mips-elf/emrelocs2.s: Likewise.
+	* ld-mips-elf/mips-elf.exp: Don't run now-removed tests.
+
+2004-04-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elfweak/elfweak.exp: Add an undefined weak size change
+	test.
+
+	* ld-elfweak/size.dat: New file.
+	* ld-elfweak/size_bar.c: Likewise.
+	* ld-elfweak/size_foo.c: Likewise.
+	* ld-elfweak/size_main.c: Likewise.
+
+2004-04-14  Brian Ford  <ford@vss.fsi.com>
+	    DJ Delorie  <dj@redhat.com>
+
+	* ld-pe/pe.exp: New, tests for i?86 PE.
+	* ld-pe/secrel1.s: New, test R_SECREL32 reloc.
+	* ld-pe/secrel2.s: Likewise.
+	* ld-pe/secrel.d: Likewise.
+
+2004-04-19  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-elfvsb/elfvsb.exp: XFAIL some tests on sparc64.
+	* ld-shared/shared.exp: Likewise.
+
+2004-04-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-scripts/assert.s: Add a newline.
+	* ld-scripts/data.s: Likewise.
+
+2004-04-08  Alan Modra  <amodra@bigpond.net.au>
+
+	PR 47.
+	* ld-cdtest/cdtest.exp: Remove -fgnu-linker.
+
+2004-04-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/align.exp: Don't run on aix.
+	* ld-scripts/assert.s: Remove comment.
+	* ld-scripts/data.s: Likewise.
+	* ld-scripts/data.t: Set start address to allow for aout headers.
+	Make first LONG pc-relative.
+	* ld-scripts/data.d: Update.
+	* ld-scripts/defined2.d: Allow other random syms.
+	* ld-scripts/defined3.d: Likewise.
+	* ld-scripts/provide-1.s: Pad section.
+	* ld-scripts/provide-1.t: Set .data address and align.
+	* ld-scripts/provide-1.d: Update.
+	* ld-scripts/provide-2.s: Pad section.
+	* ld-scripts/provide-2.d: Allow random trailing syms.
+	* ld-scripts/provide-3.s: Pad section.
+	* ld-scripts/provide-3.d: Fix typos.
+	* ld-scripts/provide.exp: Don't run on aix.
+	* ld-scripts/size-1.s: Simplify test.
+	* ld-scripts/size-1.t: Rewrite.
+	* ld-scripts/size-1.d: Update.
+	* ld-scripts/size-2.s: Simplify.
+	* ld-scripts/size-2.t: Set start address.  Set exe flag on image.
+	* ld-scripts/size-2.d: Update.
+	* ld-scripts/size.exp: Don't run on aix.  Run size-2 on all elf
+	targets except mips.
+
+2004-03-27  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-frv/fdpic*.d: Adjust to compensate for page size change.
+
+2004-03-26  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexe.r: Update for changed sym type.
+	* ld-powerpc/tlsexetoc.r: Likewise.
+
+2004-03-22  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/dsofnf.s, ld-cris/dsofnf2.s, ld-cris/gotplt1.d,
+	ld-cris/gotplt2.d, ld-cris/gotplt3.d: New tests.
+
+2004-03-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elfvers/vers.exp: Add new tests for versioned weak
+	definition.
+
+	* ld-elfvers/vers28a.c: New file.
+	* ld-elfvers/vers28a.dsym: Likewise.
+	* ld-elfvers/vers28a.ver: Likewise.
+	* ld-elfvers/vers28b.c: Likewise.
+	* ld-elfvers/vers28b.dsym: Likewise.
+	* ld-elfvers/vers28b.map: Likewise.
+	* ld-elfvers/vers28b.ver: Likewise.
+	* ld-elfvers/vers28c.c: Likewise.
+	* ld-elfvers/vers28c.dsym: Likewise.
+	* ld-elfvers/vers28c.ver: Likewise.
+
+2004-03-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/provide-2.d: Ignore random symbols.
+
+2004-03-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tls.d: Update.
+	* ld-powerpc/tls32.d: Update.
+	* ld-powerpc/tlsexe.d: Update.
+	* ld-powerpc/tlsexe32.d: Update.
+	* ld-powerpc/tlsexetoc.d: Update.
+	* ld-powerpc/tlsso.d: Update.
+	* ld-powerpc/tlsso32.d: Update.
+	* ld-powerpc/tlstoc.d: Update.
+	* ld-powerpc/tlstocso.d: Update.
+
+2004-03-05  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-scripts/size-1.d: Add bigendian regexps.
+	* ld-scripts/size-2.d: Set --wide for readelf.
+
+	* ld-scripts/size.exp: New.
+	* ld-scripts/size-[12].{d,s,t}: New.
+
+2004-03-01  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-frv/fr450-link[abc].s, fr450-link.d: New test.
+	* ld-frv/frv.exp: New harness.
+
+2004-02-24  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-frv/fdpic-pie-2.d: Adjust for decay of FUNCDESC relocs that
+	bind locally.
+	* ld-frv/fdpic-pie-8.d: Likewise.
+	* ld-frv/fdpic-shared-4.d: Likewise.
+	* ld-frv/fdpic-pie-6-fail.d: Renamed from...
+	* ld-frv/fdpic-pie-6.d: New test.
+	* ld-frv/fdpic-shared-6-fail.d: Renamed from...
+	* ld-frv/fdpic-shared-6.d: New test.
+	* ld-frv/fdpic6.ldv: New.
+	* ld-frv/fdpic-static-6.d: Adjust test name.
+	* ld-frv/fdpic-pie-8-fail.d: Removed.
+	* ld-frv/fdpic.exp: Run new tests.
+
+2004-02-23  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-scripts/provide.exp: New.
+	* ld-scripts/provide-{1,2,3}.{s,t,d}.exp: New.
+
+2004-02-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/data.t: Set ".other" address so location doesn't
+	depend on target alignment.
+	* ld-scripts/data.d: Update.
+
+2004-02-20  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-scripts/align.{s,t,exp}: New.
+
+2004-02-19  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-scripts/data.{s,t,d,exp}: New.
+
+2004-02-18  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-scripts/assert.{s,t,exp}: New.
+
+2004-02-17  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-mips/elf/elf-rel-xgot-{n32,n64-linux}.d: Update after 2004-02-02
+	changes to the way large constants are added.
+	* ld-mips/elf/elf-rel-got-{n32,n64-linux}.d: Likewise.  Adjust order
+	of GOT entries after today's change to the handling of GOT_PAGE
+	relocations.
+
+2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
+
+	* ld-h8300/relax-5.s: New file: Source for relax-5 test.
+	* ld-h8300/relax-5.d: New file: Expected output and commands for
+	assembling and linking the relax-5 test.
+	* ld-h8300/relax-5-coff.d: New file: Variant for the COFF based
+	toolchain.
+	* ld-h8300/h8300-exp:  Run the relax-5 test.
+
+2004-01-23  Daniel Jacobowitz  <drow@mvista.com>
+
+	* ld-arm/arm-app-abs32.s, ld-arm/arm-app-abs32.r,
+	ld-arm/arm-app-abs32.d: New files.
+	* ld-arm/arm-elf.exp: Add arm-app-abs32 testcase.
+
+2004-01-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-i386/tlsbin.dd: Adjust for changed sib printing.
+
+2004-01-13  Daniel Jacobowitz  <drow@mvista.com>
+
+	* ld-arm/arm-elf.exp: Add arm-static-app test.
+	* ld-arm/arm-static-app.s, ld-arm/arm-static-app.d,
+	ld-arm/arm-static-app.r: New files.
+
+2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
+
+	* ld-h8300/h8300-exp:  Run the relax-4 test.
+	* ld-h8300/relax-4.s: New file: Source for relax-4 test.
+	* ld-h8300/relax-4.d: New file: Expected output and commands for
+	assembling and linking the relax-4 test.
+	* ld-h8300/relax-4-coff.d: New file: Variant for the COFF based
+	toolchain.
+
+2004-01-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-selective/selective.exp: Skip ia64-*-*.
+
+2004-01-09  Daniel Jacobowitz  <drow@mvista.com>
+
+	* ld-arm/arm-lib.d, ld-arm/arm-lib.r: Update for R_ARM_PLT32
+	changes.
+
+2004-01-06  Daniel Jacobowitz  <drow@mvista.com>
+
+	* ld-arm/arm-app.d, ld-arm/arm-app.r, ld-arm/arm-app.s,
+	ld-arm/arm-lib.d, ld-arm/arm-lib.r, ld-arm/arm-lib.s,
+	ld-arm/arm-lib-plt32.d, ld-arm/arm-lib-plt32.r,
+	ld-arm/arm-lib-plt32.s, ld-arm/arm-elf.exp: New files.
+
+2004-01-06  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-frv: Update .d files with correct addresses displayed for
+	dynamic relocations.
+	2003-12-02  Alexandre Oliva  <aoliva@redhat.com>
+	* ld-frv/fdpic1.s (.D0): Move to separate data section.
+	2003-11-28  Alexandre Oliva  <aoliva@redhat.com>
+	* ld-frv/fdpic-static-1.d, ld-frv/fdpic-static-2.d,
+	* ld-frv/fdpic-static-7.d, ld-frv/fdpic-static-8.d: Update to
+	reflect EMBEDDED= change in linker script.
+	2003-11-27  Alexandre Oliva  <aoliva@redhat.com>
+	* ld-frv: Update .d files to reflect changes in the page size, the
+	addition of a stack segment, the use of a NULL function descriptor
+	for weakundef functions and the change in the lazy funcdesc_value
+	in-place addend value.
+	2003-11-05  Alexandre Oliva  <aoliva@redhat.com>
+	* lib/ld-lib.exp (is_elf_format): Match frv-uclinux.
+	2003-10-06  Alexandre Oliva  <aoliva@redhat.com>
+	* ld-frv/fdpic-static-1.d, ld-frv/fdpic-static-2.d,
+	ld-frv/fdpic-static-7.d, ld-frv/fdpic-static-8.d: Addresses are
+	now _gp-based, not \.rofixup-based.
+	* ld-frv/fdpic-static-6.d: Likewise.  Match warning about
+	relocation to different section.
+	2003-09-30  Alexandre Oliva  <aoliva@redhat.com>
+	* ld-frv/fdpic.exp: Add -melf32frvfd to LDFLAGS.
+	2003-09-19  Alexandre Oliva  <aoliva@redhat.com>
+	* ld-frv/fdpic7.s, ld-frv/fdpic-static-7.d, ld-frv/fdpic-pie-7.d,
+	ld-frv/fdpic-shared-7.d: New.
+	* ld-frv/fdpic8.s, ld-frv/fdpic-static-8.d, ld-frv/fdpic-pie-8.d,
+	ld-frv/fdpic-shared-8.d: New.
+	* ld-frv/fdpic-pie-8-fail.d, ld-frv/fdpic-shared-8-fail.d: New.
+	* ld-frv/fdpic.exp: Run them.
+	* ld-frv/fdpic8.ldv, ld-frv/fdpic8min.ldv: New.
+	2003-09-18  Alexandre Oliva  <aoliva@redhat.com>
+	* ld-frv/fdpic5.s, ld-frv/fdpic-static-5.d, ld-frv/fdpic-pie-5.d,
+	ld-frv/fdpic-shared-5.d: New.
+	* ld-frv/fdpic6.s, ld-frv/fdpic-static-6.d, ld-frv/fdpic-pie-6.d,
+	ld-frv/fdpic-shared-6.d: New.
+	* ld-frv/fdpic.exp: Run them.
+	* ld-frv/fdpic*.d: Add -mfdpic to assembler flags.  Updated.
+	* ld-frv/fdpic2min.ldv: New, used by fdpic-shared-2.d.
+	* ld-frv/fdpic-shared-2-fail.d: New.
+	* ld-frv/fdpic.exp: Run it.
+	* ld-frv/fdpic4.s, ld-frv/fdpic-shared-4.d: New.
+	* ld-frv/fdpic.exp: Add new test.
+	* ld-frv/fdpic-pie-2.d: Remove unnecessary function descriptors.
+	* ld-frv/fdpic-shared-local-2.d, ld-frv/fdpic2.ldv: New.
+	* ld-frv/fdpic3.s, ld-frv/fdpic-shared-3.d: New.
+	* ld-frv/fdpic.exp: Add new tests.
+	* ld-frv/fdpic.exp, ld-frv/fdpic1.s, ld-frv/fdpic2.s,
+	* ld-frv/fdpic-static-1.d, ld-frv/fdpic-static-2.d,
+	* ld-frv/fdpic-pie-1.d, ld-frv/fdpic-pie-2.d,
+	* ld-frv/fdpic-shared-1.d, ld-frv/fdpic-shared-2.d: Renamed from
+	ucpic.
+	2003-09-15  Alexandre Oliva  <aoliva@redhat.com>
+	* ld-frv/ucpic.exp, ld-frv/ucpic1.s, ld-frv/ucpic2.s: New.
+	* ld-frv/ucpic-static-1.d, ld-frv/ucpic-static-2.d: New.
+	* ld-frv/ucpic-pie-1.d, ld-frv/ucpic-pie-2.d: New.
+	* ld-frv/ucpic-shared-1.d, ld-frv/ucpic-shared-2.d: New.
+
+2004-01-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-selective/sel-dump.exp: Use is_elf_format, xfail assorted targets.
+	* ld-selective/selective.exp: Likewise.
+
+For older changes see ChangeLog-9303
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.19/ld/testsuite/ChangeLog-2005 b/binutils-2.19/ld/testsuite/ChangeLog-2005
new file mode 100644
index 0000000..23efd89
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ChangeLog-2005
@@ -0,0 +1,1189 @@
+2005-12-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/orphan2.d: Undo the last change.
+
+2005-12-19  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-elf/unknown2.d: Only run for *-*-linux*.
+	* ld-elf/orphan2.d: Xfail everywhere.
+
+2005-12-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/2065
+	* ld-elf/orphan2.d: New file.
+	* ld-elf/orphan2.s: Likewise.
+
+2005-12-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/unknown2.d: New.
+	* ld-elf/unknown2.s: Likewise.
+
+2005-12-12  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-call.d: New test.
+	* ld-arm/arm-call1.s: New file.
+	* ld-arm/arm-call1.s: New file.
+	* ld-arm/arm-elf.exp: Add arm-call and mixed-app-v5.
+	* ld-arm/arm.ld: Add .glue_7 and .ARM.attribues.
+	* ld-arm/mixed-app-v5.d: New file.
+	* ld-arm/mixed-app.r: Tweak expected output.
+
+2005-11-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/symtocbase.d: Adjust for alignment change.
+
+2005-11-17  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/sec-1.d: Adjust section order for recent ELF section
+	rearrangement.
+
+2005-11-15  Jan Beulich  <jbeulich@novell.com>
+
+	* ld-bootstrap/bootstrap.exp: Delete ld-partial.o and ld[123]*
+	after test.
+	* ld-elf/elf.exp: Delete preinit, init, and fini after test.
+	* ld-elf/sec64k.exp: Use macro and repeat in generated source
+	files. Delete object files after test.
+
+2005-11-11  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/noov.d: Restrict to cris-*-*elf*.
+
+2005-10-31  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	PR ld/1501
+	* ld-mmix/bpo-10.d: Adjust for empty-section-removal.
+
+2005-10-28  Hans-Peter Nilsson  <hp@axis.com>
+
+	PR ld/1567
+	* ld-cris/noov.s, ld-cris/noov.d: New test.
+
+2005-10-26  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/empty2.d: Allow more symbols.
+
+2005-10-26  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/bpo-6.d, ld-mmix/bpo-19.d: Adjust for symbols between
+	section symbols and the _start symbol.
+
+2005-10-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/orphan.d: Adjust for mips.
+
+2005-10-24  Jan Beulich  <jbeulich@novell.com>
+
+	* ld-elf/empty2.[sd]: New.
+
+2005-10-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/1487
+	* ld-ia64/tlspic.rd: Updated.
+
+2005-10-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/1467
+	* ld-elf/orphan.d: New file.
+	* ld-elf/orphan.ld: Likewise.
+	* ld-elf/orphan.s: Likewise.
+
+2005-10-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-ia64/ia64.exp: Undo the last change. Add support for *.d.
+
+	* ld-ia64/link-order.d: New file.
+
+2005-10-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/251
+	* ld-elf/group2.d: New file.
+
+2005-10-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/1487
+	* ld-elf/unknown.d: New file.
+
+2005-10-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-ia64/ia64.exp: Check link order for ld -r.
+
+2005-10-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/crossref.exp: Add -mcall-aixdesc to CFLAGS for
+	powerpc64.
+
+2005-10-13 Mark Mitchell  <mark@codesourcery.com>
+
+	* ld-elfvers/vers.exp: Add vers31.
+	* ld-elfvers/vers31.c: New file.
+	* ld-elfvers/vers31.dsym: Likewise.
+	* ld-elfvers/vers31.map: Likewise.
+	* ld-elfvers/vers31.ver: Likewise.
+
+2005-10-08  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-rel31.d: Ignore Arm object attribute sections.
+	* ld-arm/arm-target1-abs.d: Ditto.
+	* ld-arm/arm-target1-rel.d: Ditto.
+	* ld-arm/arm-target2-abs.d: Ditto.
+	* ld-arm/arm-target2-got-rel.d: Ditto.
+	* ld-arm/arm-target2-rel.d: Ditto.
+
+2005-10-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/1396
+	* ld-scripts/cross3.t: New file.
+	* ld-scripts/cross4.c: Likewise.
+
+	* ld-scripts/crossref.exp: Add a new test for "ld -r".
+
+2005-09-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/sec64k.exp: Enabled for all ELF targets.
+
+2005-09-30  Catherine Moore  <clm@cm00re.com>
+
+	* ld-elf/merge.d: Xfail bfin.
+
+2005-09-28  Alexandre Oliva  <aoliva@redhat.com>
+
+	* symtocbase-1.s, symtocbase-2.s, symtocbase.d: New test.
+	* powerpc.exp: Run it.
+
+2005-09-28  Jan Beulich  <jbeulich@novell.com>
+
+	* ld-x86-64/tlspic.dd: Adjust.
+
+2005-09-01  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris: Skip tests unsuitable for testing target
+	cris-axis-linux-gnu.
+
+2005-08-18  David Daney  <ddaney@avtrex.com>
+
+	* ld-mips-elf/multi-got-1.d: Adjust for new ld behavior.
+	* ld-mips-elf/multi-got-no-shared.d: Likewise.
+	* ld-mips-elf/rel32-n32.d: Likewise.
+	* ld-mips-elf/rel32-o32.d: Likewise.
+	* ld-mips-elf/rel64.d: Likewise.
+
+2005-08-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-d10v/default_layout.d: Adjust for section removal.
+	* ld-elf/empty.s: Define "main".
+	* ld-elf/frame.exp: Don't run for hppa64 and v850.
+	* ld-elf/group1.d: xfail various targets.
+	* ld-elf/merge.d: Likewise.
+	* ld-elf/merge2.d: Likewise.
+	* ld-elf/warn1.d: Likewise.
+	* ld-scripts/defined2.d: Likewise.
+	* ld-scripts/defined3.d: Likewise.
+	* ld-scripts/empty-aligned.d: Likewise.
+	* ld-scripts/size-2.d: Likewise.
+	* ld-scripts/weak.exp: Likewise.
+	* ld-selective/sel-dump.exp: Likewise.
+	* ld-undefined/weak-undef.exp: Likewise.
+
+2005-08-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/crossref.exp: Remove a29k support.
+	* ld-srec/srec.exp: Likewise.
+
+2005-08-17  Jakub Jelinek  <jakub@redhat.com>
+
+	* lib/ld-lib.exp (default_ld_compile): Append $cc arguments after
+	$CFLAGS instead of prepending them.
+
+	* ld-elfvers/vers.exp: Add a new test, vers30.
+	* ld-elfvers/vers30.c: New file.
+	* ld-elfvers/vers30.map: New file.
+	* ld-elfvers/vers30.ver: New file.
+	* ld-elfvers/vers30.dsym: New file.
+
+2005-08-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-alpha/tlsbin.rd: Update.
+	* ld-alpha/tlsbinr.rd: Update.
+	* ld-cris/locref1.d: Update.
+	* ld-cris/locref2.d: Update.
+	* ld-i386/tlsbin.rd: Update.
+	* ld-ia64/tlsbin.rd: Update.
+	* ld-powerpc/tlsexe.r: Update.
+	* ld-powerpc/tlsexe32.r: Update.
+	* ld-powerpc/tlsexetoc.r: Update.
+	* ld-s390/tlsbin.rd: Update.
+	* ld-s390/tlsbin_64.rd: Update.
+	* ld-sparc/tlssunbin32.rd: Update.
+	* ld-sparc/tlssunbin64.rd: Update.
+	* ld-x86-64/tlsbin.rd: Update.
+
+2005-08-16  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/dso-1.s: Add missing alignment directive.
+	* ld-cris/libdso-10.d: Adjust accordingly.
+
+2005-08-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-alpha/tlsbin.rd: Adjust for dynamic sym changes.
+	* ld-alpha/tlsbinr.rd: Likewise.
+	* ld-alpha/tlspic.rd: Likewise.
+	* ld-arm/mixed-app.d: Likewise.
+	* ld-arm/mixed-app.sym: Likewise.
+	* ld-arm/mixed-lib.sym: Likewise.
+	* ld-arm/tls-app.d: Likewise.
+	* ld-arm/tls-app.r: Likewise.
+	* ld-cris/expdyn5.d: Likewise.
+	* ld-cris/expdyn6.d: Likewise.
+	* ld-cris/expdyn7.d: Likewise.
+	* ld-cris/gotplt1.d: Likewise.
+	* ld-cris/gotplt2.d: Likewise.
+	* ld-cris/gotplt3.d: Likewise.
+	* ld-cris/hiddef1.d: Likewise.
+	* ld-cris/libdso-10.d: Likewise.
+	* ld-cris/libdso-11.d: Likewise.
+	* ld-cris/libdso-12.d: Likewise.
+	* ld-cris/libdso-13.d: Likewise.
+	* ld-cris/libdso-14.d: Likewise.
+	* ld-cris/libdso-2.d: Likewise.
+	* ld-cris/pv32-1.d: Likewise.
+	* ld-cris/weakref2.d: Likewise.
+	* ld-frv/fdpic-pie-1.d: Likewise.
+	* ld-frv/fdpic-pie-2.d: Likewise.
+	* ld-frv/fdpic-pie-6.d: Likewise.
+	* ld-frv/fdpic-pie-7.d: Likewise.
+	* ld-frv/fdpic-pie-8.d: Likewise.
+	* ld-frv/fdpic-shared-1.d: Likewise.
+	* ld-frv/fdpic-shared-2.d: Likewise.
+	* ld-frv/fdpic-shared-3.d: Likewise.
+	* ld-frv/fdpic-shared-4.d: Likewise.
+	* ld-frv/fdpic-shared-5.d: Likewise.
+	* ld-frv/fdpic-shared-6.d: Likewise.
+	* ld-frv/fdpic-shared-7.d: Likewise.
+	* ld-frv/fdpic-shared-8.d: Likewise.
+	* ld-frv/fdpic-shared-local-2.d: Likewise.
+	* ld-frv/fdpic-shared-local-8.d: Likewise.
+	* ld-frv/fdpic-static-1.d: Likewise.
+	* ld-frv/fdpic-static-2.d: Likewise.
+	* ld-frv/fdpic-static-6.d: Likewise.
+	* ld-frv/fdpic-static-7.d: Likewise.
+	* ld-frv/fdpic-static-8.d: Likewise.
+	* ld-frv/tls-dynamic-1.d: Likewise.
+	* ld-frv/tls-dynamic-2.d: Likewise.
+	* ld-frv/tls-dynamic-3.d: Likewise.
+	* ld-frv/tls-initial-shared-2.d: Likewise.
+	* ld-frv/tls-pie-1.d: Likewise.
+	* ld-frv/tls-pie-3.d: Likewise.
+	* ld-frv/tls-relax-dynamic-1.d: Likewise.
+	* ld-frv/tls-relax-dynamic-2.d: Likewise.
+	* ld-frv/tls-relax-dynamic-3.d: Likewise.
+	* ld-frv/tls-relax-initial-shared-2.d: Likewise.
+	* ld-frv/tls-relax-pie-1.d: Likewise.
+	* ld-frv/tls-relax-pie-3.d: Likewise.
+	* ld-frv/tls-relax-shared-1.d: Likewise.
+	* ld-frv/tls-relax-shared-2.d: Likewise.
+	* ld-frv/tls-relax-shared-3.d: Likewise.
+	* ld-frv/tls-relax-static-1.d: Likewise.
+	* ld-frv/tls-shared-1.d: Likewise.
+	* ld-frv/tls-shared-2.d: Likewise.
+	* ld-frv/tls-shared-3.d: Likewise.
+	* ld-frv/tls-static-1.d: Likewise.
+	* ld-frv/tls-static-3.d: Likewise.
+	* ld-i386/tlsbin.rd: Likewise.
+	* ld-i386/tlsnopic.rd: Likewise.
+	* ld-i386/tlspic.rd: Likewise.
+	* ld-ia64/tlsbin.dd: Likewise.
+	* ld-ia64/tlsbin.rd: Likewise.
+	* ld-ia64/tlspic.dd: Likewise.
+	* ld-ia64/tlspic.rd: Likewise.
+	* ld-powerpc/tlsexe.g: Likewise.
+	* ld-powerpc/tlsexe.r: Likewise.
+	* ld-powerpc/tlsexe32.d: Likewise.
+	* ld-powerpc/tlsexe32.g: Likewise.
+	* ld-powerpc/tlsexe32.r: Likewise.
+	* ld-powerpc/tlsexetoc.g: Likewise.
+	* ld-powerpc/tlsexetoc.r: Likewise.
+	* ld-powerpc/tlsso.g: Likewise.
+	* ld-powerpc/tlsso.r: Likewise.
+	* ld-powerpc/tlsso32.d: Likewise.
+	* ld-powerpc/tlsso32.g: Likewise.
+	* ld-powerpc/tlsso32.r: Likewise.
+	* ld-powerpc/tlstocso.g: Likewise.
+	* ld-powerpc/tlstocso.r: Likewise.
+	* ld-s390/tlsbin.rd: Likewise.
+	* ld-s390/tlsbin_64.rd: Likewise.
+	* ld-s390/tlspic.rd: Likewise.
+	* ld-s390/tlspic_64.rd: Likewise.
+	* ld-sh/shared-1.d: Likewise.
+	* ld-sh/tlsbin-2.d: Likewise.
+	* ld-sh/tlsbin-3.d: Likewise.
+	* ld-sh/tlsbin-4.d: Likewise.
+	* ld-sh/tlspic-2.d: Likewise.
+	* ld-sh/sh64/abi32.xd: Likewise.
+	* ld-sh/sh64/abi64.xd: Likewise.
+	* ld-sh/sh64/cmpct1.xd: Likewise.
+	* ld-sh/sh64/crange1.rd: Likewise.
+	* ld-sh/sh64/crange2.rd: Likewise.
+	* ld-sh/sh64/crange3-cmpct.rd: Likewise.
+	* ld-sh/sh64/crange3-media.rd: Likewise.
+	* ld-sh/sh64/crange3.rd: Likewise.
+	* ld-sh/sh64/gotplt.d: Likewise.
+	* ld-sh/sh64/init-cmpct.d: Likewise.
+	* ld-sh/sh64/init-media.d: Likewise.
+	* ld-sh/sh64/init64.d: Likewise.
+	* ld-sh/sh64/mix1.xd: Likewise.
+	* ld-sh/sh64/mix2.xd: Likewise.
+	* ld-sh/sh64/sh64.exp: Likewise.
+	* ld-sh/sh64/shdl32.xd: Likewise.
+	* ld-sh/sh64/shdl64.xd: Likewise.
+	* ld-sparc/tlssunbin32.rd: Likewise.
+	* ld-sparc/tlssunbin64.rd: Likewise.
+	* ld-sparc/tlssunnopic32.rd: Likewise.
+	* ld-sparc/tlssunnopic64.rd: Likewise.
+	* ld-sparc/tlssunpic32.rd: Likewise.
+	* ld-sparc/tlssunpic64.rd: Likewise.
+	* ld-x86-64/tlsbin.rd: Likewise.
+	* ld-x86-64/tlspic.dd: Likewise.
+	* ld-x86-64/tlspic.rd: Likewise.
+
+2005-08-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/empty.s: Define "start".
+	* ld-elf/merge2.d: xfail arc-*-* and dlx-*-*.
+	* ld-scripts/empty-aligned.s: No .data section.
+	* ld-scripts/empty-aligned.t: Discard most sections.
+	* ld-scripts/empty-aligned.d: Adjust.
+
+2005-08-11  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/expdyn1.s (expobj): Set size here, at definition...
+	* ld-cris/pv32.s: ...not here.
+	* ld-cris/expdyn1.d, ld-cris/libdso-12.d, ld-cris/locref1.d:
+	Adjust for expobj size being set at definition.
+
+	* ld-cris/v32-ba-1.d: Regexpize to adjust for symbol change.
+
+2005-08-08  Richard Earnshaw  <richard.earnshaw@arm.com>
+
+	* ld-arm/mixed-app.sym: Expact _stack to be in the ABS section.
+	* ld-arm/mixed-lib.sym: Likewise.
+	* tls-lib.d: Use a regexp for the address locations.
+	* tls-lib.r: Likewise.
+
+2005-08-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-i386/pcrel16.d: Updated.
+	* ld-i386/pcrel16.s: Likewise.
+	* ld-x86-64/pcrel16.d: Likewise.
+
+2005-08-01  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips/mips-elf-flags.exp: Add more good_combination tests.
+
+2005-07-28  Ben Elliston  <bje@gnu.org>
+
+	* lib/ld-lib.exp (run_ld_link_exec_tests): Add new parameter
+	${targets_to_xfail} that is applied for each test item.
+	* ld-elf/elf.exp: Pass *-*-netbsdelf* as an xfailed target.
+
+2005-07-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elfweak/size2a.s: Extend test to check size for two weaks.
+	* ld-elfweak/size2b.s: Likewise.
+	* ld-elfweak/size2.d: Update.
+
+2005-07-18  Jan Beulich  <jbeulich@novell.com>
+
+	* ld-i386/abs.s, ld-i386/zero.s, ld-i386/abs.d, ld-x86-64/abs.d,
+	ld-i386/pcrel16.s, ld-i386/pcrel16.d, ld-x86-64/pcrel16.d,
+	ld-i386/pcrel8.s, ld-i386/pcrel8.d, ld-x86-64/pcrel8.d: New.
+	* ld-i386/i386.exp, ld-x86-64/x86-64.exp: Run new tests.
+
+2005-07-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* lib/ld-lib.exp (run_ld_link_exec_tests): Ignore assembler
+	warnings.
+
+2005-07-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* lib/ld-lib.exp (run_ld_link_exec_tests): Update comments.
+
+2005-07-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/elf.exp (array_tests): New.
+	Call run_ld_link_exec_tests with array_tests.
+
+	* ld-elf/fini.c: New file.
+	* ld-elf/fini.out: Likewise.
+	* ld-elf/init.c: Likewise.
+	* ld-elf/init.out: Likewise.
+	* ld-elf/preinit.c: Likewise.
+	* ld-elf/preinit.out: Likewise.
+
+	* lib/ld-lib.exp (run_ld_link_exec_tests): New.
+
+2005-07-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/sdalib.s (lib_var): Size it.
+
+2005-07-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-ia64/tlsbin.rd: Update for empty section removal change.
+	* ld-ia64/tlsbin.sd: Likewise.
+	* ld-ia64/tlspic.dd: Likewise.
+	* ld-ia64/tlspic.rd: Likewise.
+	* ld-ia64/tlspic.sd: Likewise.
+	* ld-x86-64/tlspic.dd: Likewise.
+	* ld-x86-64/tlspic.rd: Likewise.
+
+2005-07-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-cris/pv32.s: Give expobj a size.
+	* ld-cris/pv32-1.d: Update.
+	* ld-alpha/tlsbin.dd: Update for empty section removal change.
+	* ld-alpha/tlsbin.sd: Likewise.
+	* ld-alpha/tlsbin.td: Likewise.
+	* ld-alpha/tlsbinr.dd: Likewise.
+	* ld-alpha/tlsbinr.rd: Likewise.
+	* ld-alpha/tlspic.dd: Likewise.
+	* ld-alpha/tlspic.rd: Likewise.
+	* ld-alpha/tlspic.sd: Likewise.
+	* ld-alpha/tlspic.td: Likewise.
+	* ld-arm/tls-lib.d: Likewise.
+	* ld-arm/tls-lib.r: Likewise.
+	* ld-cris/gotplt2.d: Likewise.
+	* ld-cris/gotplt3.d: Likewise.
+	* ld-cris/hiddef1.d: Likewise.
+	* ld-cris/libdso-10.d: Likewise.
+	* ld-cris/libdso-11.d: Likewise.
+	* ld-cris/libdso-12.d: Likewise.
+	* ld-cris/libdso-14.d: Likewise.
+	* ld-cris/libdso-2.d: Likewise.
+	* ld-i386/tlsnopic.dd: Likewise.
+	* ld-i386/tlsnopic.rd: Likewise.
+	* ld-i386/tlsnopic.sd: Likewise.
+	* ld-i386/tlspic.rd: Likewise.
+	* ld-mmix/bpo-10.d: Likewise.
+	* ld-mmix/bpo-22.d: Likewise.
+	* ld-mmix/sec-7m.d: Likewise.
+	* ld-powerpc/tlsexe.r: Likewise.
+	* ld-powerpc/tlsexetoc.r: Likewise.
+	* ld-powerpc/tlsso.g: Likewise.
+	* ld-powerpc/tlsso.r: Likewise.
+	* ld-powerpc/tlsso32.d: Likewise.
+	* ld-powerpc/tlsso32.g: Likewise.
+	* ld-powerpc/tlsso32.r: Likewise.
+	* ld-powerpc/tlstocso.g: Likewise.
+	* ld-powerpc/tlstocso.r: Likewise.
+
+2005-06-23  Andreas Schwab  <schwab@suse.de>
+
+	* ld-elfweak/size_foo.c (foo): Fix warning about implicit return
+	type.
+
+2005-06-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-cris/libdso-10.d: Adjust for elf.sc .bss change.
+	* ld-cris/libdso-2.d: Likewise.
+	* ld-mmix/loc6.d: Likewise.
+
+2005-06-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/empty-aligned.t: Adjust alignment expressions so
+	that no .text? section is kept.  Also check setting vma and
+	lma.
+	* ld-scripts/empty-aligned.d: Update.
+
+2005-06-09  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/empty-aligned.d: Adjust.
+
+2005-06-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-cris/hiddef1.d: Undo the last change.
+	* ld-cris/libdso-10.d: Likewise.
+	* ld-cris/libdso-2.d: Likewise.
+
+2005-06-04  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-cris/hiddef1.d: Updated.
+	* ld-cris/libdso-10.d: Likewise.
+	* ld-cris/libdso-2.d: Likewise.
+
+2005-06-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/powerpc.exp (ppcelftests): Assemble sda test with -a32.
+
+2005-05-31  Zack Weinberg  <zack@codesourcery.com>
+
+	* ld-scripts/align.exp: Mark align1 XFAIL on PECOFF targets.
+	* ld-scripts/data.exp: Mark data UNSUPPORTED on a.out targets.
+	* ld-scripts/provide.exp, ld-scripts/size.exp: Mark all tests
+	UNSUPPORTED on a.out targets.  Tidy.
+
+2005-05-27  Mark Mitchell  <mark@codesourcery.com>
+
+	* config/default.exp (CC): Use find_gcc.
+	(CFLAGS): Define, if no definition has been provided by the user.
+	(CXX): Likewise.
+	(CXXFLAGS): Likewise.
+
+2005-05-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-mmix/bpo-6.d: Updated.
+	* ld-mmix/bpo-19.d: Likewise.
+
+2005-05-22  Richard Henderson  <rth@redhat.com>
+
+	* ld-elfweak/dsow.dsym: Adjust for non-zero ST_OTHER.
+	* ld-elfweak/weak.dsym: Likewise.
+
+	* ld-selective/selective.exp: Don't test alpha.
+
+2005-05-20  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-powerpc/sdalib.s, ld-powerpc/sdadyn.s, ld-powerpc/sdadyn.d: New
+	files.
+	* ld-powerpc/powerpc.exp: Run the new test.
+
+2005-05-20  Bob Wilson  <bob.wilson@acm.org>
+
+	* ld-undefined/undefined.exp: Revert xfail for xtensa-*-*.
+
+2005-05-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 797
+	* empty-aligned.d: New file.
+	* empty-aligned.exp: Likewise.
+	* empty-aligned.s: Likewise.
+	* empty-aligned.t: Likewise.
+
+2005-05-11  Bob Wilson  <bob.wilson@acm.org>
+
+	* ld-undefined/undefined.exp: xfail xtensa-*-*.
+
+2005-05-07  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexe32.d: Update for changed got layout.
+	* ld-powerpc/tlsexe32.g: Likewise.
+	* ld-powerpc/tlsexe32.r: Likewise.
+	* ld-powerpc/tlsso32.d: Likewise.
+	* ld-powerpc/tlsso32.g: Likewise.
+	* ld-powerpc/tlsso32.r: Likewise.
+
+2005-05-06  Nick Clifton  <nickc@redhat.com>
+
+	Update the address and phone number of the FSF organization in
+	the GPL notices in the following files:
+	* config/default.exp, ld-alpha/alpha.exp, ld-arm/arm-elf.exp,
+	ld-auto-import/auto-import.exp, ld-bootstrap/bootstrap.exp,
+	ld-cdtest/cdtest.exp, ld-checks/checks.exp, ld-cris/cris.exp,
+	ld-crx/crx.exp, ld-cygwin/exe-export.exp, ld-d10v/d10v.exp,
+	ld-discard/discard.exp, ld-elf/elf.exp, ld-elf/exclude.exp,
+	ld-elf/frame.exp, ld-elf/sec64k.exp, ld-elfcomm/elfcomm.exp,
+	ld-elfvers/vers.exp, ld-elfvsb/elfvsb.exp, ld-elfweak/elfweak.exp,
+	ld-fastcall/fastcall.exp, ld-frv/fdpic.exp, ld-frv/tls.exp,
+	ld-h8300/h8300.exp, ld-i386/i386.exp, ld-ia64/ia64.exp,
+	ld-linkonce/linkonce.exp, ld-m68hc11/m68hc11.exp,
+	ld-maxq/maxq.exp, ld-mips-elf/mips-elf-flags.exp,
+	ld-mips-elf/mips-elf.exp, ld-mmix/mmix.exp, ld-pe/pe.exp,
+	ld-powerpc/powerpc.exp, ld-s390/s390.exp, ld-scripts/align.exp,
+	ld-scripts/assert.exp, ld-scripts/crossref.exp,
+	ld-scripts/data.exp, ld-scripts/defined.exp,
+	ld-scripts/empty-orphan.exp, ld-scripts/map-address.exp,
+	ld-scripts/overlay-size.exp, ld-scripts/phdrs.exp,
+	ld-scripts/phdrs2.exp, ld-scripts/provide.exp,
+	ld-scripts/script.exp, ld-scripts/size.exp, ld-scripts/sizeof.exp,
+	ld-scripts/sort.exp, ld-scripts/weak.exp,
+	ld-selective/sel-dump.exp, ld-selective/selective.exp,
+	ld-sh/rd-sh.exp, ld-sh/arch/arch.exp, ld-sh/sh64/rd-sh64.exp,
+	ld-sh/sh64/relax.exp, ld-sh/sh64/relfail.exp, ld-sh/sh64/sh64.exp,
+	ld-shared/shared.exp, ld-sparc/sparc.exp,
+	ld-undefined/undefined.exp, ld-undefined/weak-undef.exp,
+	ld-versados/versados.exp, ld-x86-64/x86-64.exp,
+	ld-xstormy16/xstormy16.exp, ld-xtensa/coalesce.exp,
+	ld-xtensa/lcall.exp, lib/ld-lib.exp
+
+2005-05-05  Mike Frysinger  <vapier@gentoo.org>
+
+	* ld-srec/srec.exp: Replace linux-gnu with linux-* to allow for
+	versions of Linux which do not use glibc.
+	* ld-sh/sh.exp: Likewise
+
+2005-05-05  Paul Brook  <paul@codesourcery.com>
+
+	* lib/ld-lib.exp (regexp_diff): Pass test if last line is "#...".
+	* ld-elfweak/elfweak.exp: Run size2.d.
+	* ld-elfweak/size2.d: New file.
+	* ld-elfweak/size2a.s: New file.
+	* ld-elfweak/size2b.s: New file.
+
+2005-04-26  Mark Kettenis  <kettenis@gnu.org>
+
+	* ld-fastcall/fastcall.exp: Don't run on i*86-*-openbsd*.
+
+	* ld-srec/srec.exp (run_srec_test): Deal with ProPolice on
+	*-*-openbsd*.
+
+2005-04-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-discard/extern.d: Expect error.
+	* ld-discard/start.d: Likewise.
+	* ld-discard/static.d: Likewise.
+
+2005-04-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/reloc.d: Update to suit removal of non-alloc relocs.
+
+2005-04-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-d10v/default_layout.d: Update for unused section removal.
+
+2005-04-14  David S. Miller  <davem@davemloft.net>
+
+	* ld-selective/sel-dump.exp: Do not exclude sparc64-*.
+	* ld-selective/selective.exp: Likewise.
+	* ld-sparc/sparc.exp: Add {32,64}-bit prefix to test
+	names so we know which one is failing.  Run sparc64 TLS
+	tests on multi-arch sparc platforms.
+	* ld-sparc/tls64.sd, ld-sparc/tlssunbin64.dd,
+	ld-sparc/tlssunbin64.rd, ld/ld-sparc/tlssunbin64.sd,
+	ld-sparc/tlssunbin64.td, ld-sparc/tlssunnopic64.dd,
+	ld-sparc/tlssunnopic64.rd, ld-sparc/tlssunnopic64.sd,
+	ld-sparc/tlssunpic64.dd, ld-sparc/tlssunpic64.rd,
+	ld-sparc/tlssunpic64.sd, ld-sparc/tlssunpic64.td): Update now
+	that sparc64 ELF does support TLS.
+
+2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/empty.d: New file.
+	* ld-elf/empty.s: Likewise.
+
+2005-04-11  David S. Miller  <davem@davemloft.net>
+
+	* ld-sparc/tlssunbin32.dd: Update for TLS relocation fixes.
+	* ld-sparc/tlssunbin32.rd: Likewise.
+	* ld-sparc/tlssunbin32.sd: Likewise.
+	* ld-sparc/tlssunpic32.dd: Likewise.
+
+2005-03-30  Julian Brown  <julian@codesourcery.com>
+
+	* ld-arm/arm-app-abs32.d: Update expected output due to mapping symbols
+	being untyped.
+	* ld-arm/arm-app.d: Likewise.
+	* ld-arm/mixed-app.d: Likewise.
+
+2005-03-29  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-arm/tls-lib.s, ld-arm/tls-lib.d, ld-arm/tls-lib.r,
+	ld-arm/tls-app.s, ld-arm/tls-app.d, ld-arm/tls-app.r: New files.
+	* ld-arm/arm-lib.ld, ld-arm/arm-dyn.ld: Increase data segment
+	alignment.
+	* ld-arm/arm-elf.exp: Run TLS tests.
+
+2005-03-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 803
+	* ld-ia64/ia64.exp: Pass -mtune=itanium1 to as.
+
+2005-03-24  Mark Mitchell  <mark@codesourcery.com>
+
+	* config/default.exp: Do not load libpath.exp if it does not
+	exist.
+	(CC): Provide fallback definition.
+
+2005-03-24  Eric Christopher  <echristo@redhat.com>
+
+	* ld-mips-elf/rel32-n32.d: Revert changes.
+	* ld-mips-elf/rel32-o32.d: Ditto.
+	* ld-mips-elf/rel64.d: Ditto.
+
+2005-03-23  Eric Christopher  <echristo@redhat.com>
+
+	* ld-mips-elf/textrel-1.s, ld-mips-elf/textrel-1.d: New
+	test.
+	* ld-mips-elf/mips-elf.exp: Call it.
+	* ld-mips-elf/rel32-n32.d: Update for DF_TEXTREL removal.
+	* ld-mips-elf/rel32-o32.d: Ditto.
+	* ld-mips-elf/rel64.d: Ditto.
+
+2005-03-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-cris/expdyn5.d: Updated for alignment change in elf.sc.
+	* ld-cris/expdyn6.d: Likewise.
+	* ld-cris/expdyn7.d: Likewise.
+	* ld-cris/gotplt1.d: Likewise.
+	* ld-cris/gotplt2.d: Likewise.
+	* ld-cris/gotplt3.d: Likewise.
+	* ld-cris/libdso-10.d: Likewise.
+	* ld-cris/libdso-11.d: Likewise.
+	* ld-cris/libdso-12.d: Likewise.
+	* ld-cris/libdso-14.d: Likewise.
+	* ld-cris/libdso-2.d: Likewise.
+	* ld-cris/locref1.d: Likewise.
+	* ld-cris/locref2.d: Likewise.
+	* ld-cris/nodyn5.d: Likewise.
+	* ld-cris/pv32-1.d: Likewise.
+	* ld-cris/weakref2.d: Likewise.
+
+2005-03-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/tbss.s: Don't start directives in first column.
+	* ld-scripts/weak1.s: Likewise.
+	* ld-scripts/weak2.s: Likewise.
+	* ld-undefined/weak-undef.s: Likewise.
+	* ld-undefined/undefined.exp: Enable tests for hppa-elf.
+
+2005-03-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexe32.r: Update.
+	* ld-powerpc/tlsso32.d: Update.
+	* ld-powerpc/tlsso32.g: Update.
+	* ld-powerpc/tlsso32.r: Update.
+
+2005-03-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexe.r: Update.
+	* ld-powerpc/tlsexetoc.r: Update.
+	* ld-powerpc/tlsso.r: Update.
+	* ld-powerpc/tlstocso.r: Update.
+
+2005-03-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-mmix/bpo-1.d: Updated for empty section removal.
+	* ld-mmix/bpo-10.d: Likewise.
+	* ld-mmix/bpo-11.d: Likewise.
+	* ld-mmix/bpo-14.d: Likewise.
+	* ld-mmix/bpo-16.d: Likewise.
+	* ld-mmix/bpo-17.d: Likewise.
+	* ld-mmix/bpo-18.d: Likewise.
+	* ld-mmix/bpo-19.d: Likewise.
+	* ld-mmix/bpo-2.d: Likewise.
+	* ld-mmix/bpo-3.d: Likewise.
+	* ld-mmix/bpo-4.d: Likewise.
+	* ld-mmix/bpo-5.d: Likewise.
+	* ld-mmix/bpo-6.d: Likewise.
+	* ld-mmix/bpo-9.d: Likewise.
+	* ld-mmix/bspec1.d: Likewise.
+	* ld-mmix/bspec2.d: Likewise.
+	* ld-mmix/greg-1.d: Likewise.
+	* ld-mmix/greg-19.d: Likewise.
+	* ld-mmix/greg-2.d: Likewise.
+	* ld-mmix/greg-3.d: Likewise.
+	* ld-mmix/greg-4.d: Likewise.
+	* ld-mmix/greg-5.d: Likewise.
+	* ld-mmix/greg-5s.d: Likewise.
+	* ld-mmix/greg-6.d: Likewise.
+	* ld-mmix/greg-7.d: Likewise.
+	* ld-mmix/loc1.d: Likewise.
+	* ld-mmix/loc2.d: Likewise.
+	* ld-mmix/loc3.d: Likewise.
+	* ld-mmix/loc4.d: Likewise.
+	* ld-mmix/loc6.d: Likewise.
+	* ld-mmix/local1.d: Likewise.
+	* ld-mmix/local12.d: Likewise.
+	* ld-mmix/local3.d: Likewise.
+	* ld-mmix/local5.d: Likewise.
+	* ld-mmix/local7.d: Likewise.
+	* ld-mmix/locdo-1.d: Likewise.
+	* ld-mmix/loct-1.d: Likewise.
+	* ld-mmix/locto-1.d: Likewise.
+	* ld-mmix/start-1.d: Likewise.
+	* ld-mmix/undef-3.d: Likewise.
+
+2005-03-16  David Heine  <dlheine@tensilica.com>
+	    Bob Wilson  <bob.wilson@acm.org>
+
+	* ld-scripts/empty-orphan.d, ld-scripts/empty-orphan.exp,
+	ld-scripts/empty-orphan.s, ld-scripts/emtpy-orphan.t: New test.
+
+2005-03-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-cris/hiddef1.d: Updated for empty section removal.
+	* ld-cris/libdso-10.d: Likewise.
+	* ld-cris/libdso-2.d: Likewise.
+
+2005-03-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-alpha/tlsbin.rd: Updated for empty section removal.
+	* ld-alpha/tlsbinr.rd: Likewise.
+	* ld-alpha/tlspic.rd: Likewise.
+	* ld-arm/mixed-lib.sym: Likewise.
+	* ld-i386/tlsbin.rd: Likewise.
+	* ld-i386/tlsnopic.rd: Likewise.
+	* ld-i386/tlspic.rd: Likewise.
+	* ld-ia64/tlsbin.rd: Likewise.
+	* ld-ia64/tlspic.rd: Likewise.
+	* ld-powerpc/apuinfo.rd: Likewise.
+	* ld-powerpc/powerpc.exp: Likewise.
+	* ld-powerpc/tlsexe32.r: Likewise.
+	* ld-s390/tlsbin.rd: Likewise.
+	* ld-s390/tlsbin_64.rd: Likewise.
+	* ld-s390/tlspic.rd: Likewise.
+	* ld-s390/tlspic_64.rd: Likewise.
+	* ld-sh/tlsbin-2.d: Likewise.
+	* ld-sh/tlspic-2.d: Likewise.
+	* ld-sparc/tlssunbin32.rd: Likewise.
+	* ld-sparc/tlssunnopic32.rd: Likewise.
+	* ld-sparc/tlssunpic32.rd: Likewise.
+	* ld-x86-64/tlsbin.rd: Likewise.
+	* ld-x86-64/tlspic.rd: Likewise.
+
+2005-03-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexe32.d: Update.
+	* ld-powerpc/tlsexe32.g: Update.
+	* ld-powerpc/tlsexe32.r: Update.
+	* ld-powerpc/tlsexe32.t: Update.
+	* ld-powerpc/tlsso32.d: Update.
+	* ld-powerpc/tlsso32.g: Update.
+	* ld-powerpc/tlsso32.r: Update.
+	* ld-powerpc/tlsso32.t: Update.
+
+2005-03-08  Hans-Peter Nilsson  <hp@axis.com>
+
+	Adjust testsuite for cris-axis-aout.
+	* ld-cris/noglob1.d: Adjust regexp for a.out output.
+	* ld-cris/badgotr1.d, ld-cris/expdyn1.d, ld-cris/expdyn2.d,
+	ld-cris/expdyn3.d, ld-cris/expdyn4.d, ld-cris/expdyn5.d,
+	ld-cris/expdyn6.d, ld-cris/expdyn7.d, ld-cris/gotplt1.d,
+	ld-cris/gotplt2.d, ld-cris/gotplt3.d, ld-cris/hiddef1.d,
+	ld-cris/libdso-1.d, ld-cris/libdso-10.d, ld-cris/libdso-11.d,
+	ld-cris/libdso-12.d, ld-cris/libdso-13.d, ld-cris/libdso-14.d,
+	ld-cris/libdso-2.d, ld-cris/libdso-3.d, ld-cris/libdso-4.d,
+	ld-cris/locref1.d, ld-cris/locref2.d, ld-cris/nodyn4.d,
+	ld-cris/nodyn5.d, ld-cris/pv32-1.d, ld-cris/undef1.d,
+	ld-cris/weakref1.d: ld-cris/weakref2.d: Pass --em=criself to gas.
+	* ld-cris/v10-v32.d, ld-cris/v10-va.d, ld-cris/v32-ba-1.d,
+	ld-cris/v32-v10.d, ld-cris/v32-va.d, ld-cris/va-v10.d,
+	ld-cris/va-v32.d: Ditto.  Pass -m criself to gld.
+	* ld-cris/v32-bin-1.d: Pass -m criself to gld.
+
+2005-03-05  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-alpha/tlsbin.dd: Update to suit changed section layout and
+	removed section symbols.
+	* ld-alpha/tlsbin.rd: Likewise.
+	* ld-alpha/tlsbin.sd: Likewise.
+	* ld-alpha/tlsbinr.dd: Likewise.
+	* ld-alpha/tlsbinr.rd: Likewise.
+	* ld-alpha/tlspic.dd: Likewise.
+	* ld-alpha/tlspic.rd: Likewise.
+	* ld-alpha/tlspic.sd: Likewise.
+
+	* ld-powerpc/tlsexe.g: Update for removed dot-symbols.
+	* ld-powerpc/tlsexe.r: Likewise.
+	* ld-powerpc/tlsexetoc.g: Likewise.
+	* ld-powerpc/tlsexetoc.r: Likewise.
+
+2005-03-04  David Daney  <ddaney@avtrex.com>
+
+	* ld-mips-elf/multi-got-no-shared-1.s,
+	ld-mips-elf/multi-got-no-shared-2.s,
+	ld-mips-elf/multi-got-no-shared.d: New tests.
+	* ld-mips-elf/mips-elf.exp: Run them.
+
+2005-03-02  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-mips-elf/tlsbin-o32.s, ld-mips-elf/mips-dyn.ld,
+	ld-mips-elf/tlslib-o32.got, ld-mips-elf/tlslib-o32.d,
+	ld-mips-elf/tlslib-o32.s, ld-mips-elf/mips-lib.ld,
+	ld-mips-elf/tlsbin-o32.got, ld-mips-elf/tlsdyn-o32.d,
+	ld-mips-elf/tlsdyn-o32.got, ld-mips-elf/tlsbin-o32.d,
+	ld-mips-elf/tlsdyn-o32.s, ld-mips-elf/tls-multi-got-1.got,
+	ld-mips-elf/tls-multi-got-1-1.s, ld-mips-elf/tls-multi-got-1.d,
+	ld-mips-elf/tls-multi-got-1.r, ld-mips-elf/tls-multi-got-1-2.s,
+	ld-mips-elf/tlslib-o32-ver.got, ld-mips-elf/tlslib.ver,
+	ld-mips-elf/tlslib-o32-hidden.got, ld-mips-elf/tlslib-hidden.ver,
+	ld-mips-elf/tlsdyn-o32-1.d, ld-mips-elf/tlsdyn-o32-3.got,
+	ld-mips-elf/tlsdyn-o32-2.d, ld-mips-elf/tlsdyn-o32-2.s,
+	ld-mips-elf/tlsdyn-o32-3.d, ld-mips-elf/tlsdyn-o32-1.got,
+	ld-mips-elf/tlsdyn-o32-2.got: New files.
+	* ld-mips-elf/mips-elf.exp: Run the new tests.
+
+2005-03-01  Nick Clifton  <nickc@redhat.com>
+
+	* ld-d10v/default_layout.d: Adjust expected offsets to allow for
+	section alignment.
+
+	* ld-discard/extern.d: Adjust expected warning to take into
+	account the fact that the linker's name might be included and that
+	the reloc might have been adjusted to be against the section
+	symbol.
+
+2005-02-22  Eric Christopher  <echristo@redhat.com>
+
+	* ld-mips-elf/reloc-merge-lo16.d: Correct symbol
+	table size for __start.
+
+2005-02-22  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-elfvsb/hidden2.d: Expect OBJECT.
+	* ld-elfvsb/hidden2.s: Force type OBJECT.
+	* ld-elfvsb/hidden2.ld: Place .dynamic explicitly.
+	* ld-elf/start.s: Provide __start for MIPS.
+	* ld-elfcomm/elfcomm.exp: Accept MIPS common section.  XFAIL size change
+	test.
+	* ld-elf/warn1.d: Use group.ld instead of -Ttext.
+
+2005-02-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* lib/ld-lib.exp (run_dump_test): Don't require a dump program if
+	#warning given.  Rearrange to allow $program to remain unset.
+	Don't allow gas errors.  Append objcopy_as_link output to that
+	from the linker before testing against expected output.  Fail the
+	test if warning not found when expected.  Conversely fail the
+	test if ld errors or warnings given when not expected.
+
+2005-02-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/exclude1.s: Use ".dc.a".
+	* ld-elfvsb/hidden2.s: Likewise.
+
+2005-02-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/warn1.d: Specify -Ttext.
+	* ld-scripts/align.exp (align2a, align2b: Don't run on aout targets.
+	* ld-scripts/align2.t: Discard all but .text and .data.
+	* ld-scripts/align2a.d: Accept non-readonly for coff.
+	* ld-scripts/align2b.d: Likewise.
+	* lib/ld-lib.exp (is_aout_format): New function.
+
+2005-02-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/align2a.d: Don't assume anything about section
+	padding or alignment, or max page size.  Allow 64-bit addresses.
+	* ld-scripts/align2b.d: Likewise.
+
+2005-02-17  Zack Weinberg  <zack@codesourcery.com>
+
+	* ld-scripts/align.exp: Rename existing "ALIGN" test to "align1".
+	Add dump tests "align2a", "align2b", "align2c".
+	* ld-scripts/align2.t, ld-scripts/align2a.s, ld-scripts/align2a.d
+	* ld-scripts/align2b.s, ld-scripts/align2b.d
+	* ld-scripts/align2c.s, ld-scripts/align2c.d: New files.
+
+2005-02-17  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-frv/fdpic-static-6.d: Update.
+	* ld-frv/fdpic*.d: Remove explicit -mfdpic from #as.  Update
+	spelling of errors and warnings.
+
+2005-02-15  Nigel Stephens  <nigel@mips.com>
+	    Maciej W. Rozycki  <macro@mips.com>
+
+	* ld-mips-elf/mips16-hilo.d: New test for the R_MIPS16_HI16 and
+	R_MIPS16_LO16 relocs.
+	* ld-mips-elf/mips16-hilo-n32.d: Likewise, for the n32 ABI.
+	* ld-mips-elf/mips16-hilo.s: Auxiliary source for the new tests.
+	* ld-mips-elf/mips-elf.exp: Run the new tests.
+
+2005-02-14  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	* ld-sparc/sparc.exp: Enable on Solaris.  Disable 32-bit tests
+	on sparc64-elf.
+
+2005-02-13  Jan Beulich  <jbeulich@novell.com>
+
+	* ld-elfvers/vers.exp (as_options): New. Set to -x for ia64.
+	(build_binary): Pass as_options to ld_assemble.
+	(test_ldfail): Likewise.
+	(build_exec): Likewise.
+	Pass as_options to run_ld_link_tests.
+	* ld-ia64/tlsbin.s: Add .explicit.
+	* ld-ia64/tlsbinpic.s: Likewise.
+	* ld-ia64/tlspic1.s: Likewise.
+
+2005-02-13  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	* ld-sparc/tlssunnopic32.rd: Adjust for .dynsym changes.
+	* ld-sparc/tlssunpic32.rd: Likewise.
+
+2005-02-13  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	* ld-elf/warn1.d: Do not run on sparc64-*-solaris2*.
+
+2005-02-11  Paul Brook  <paul@codesourcery.com>
+
+	* ld-elf/symbol1w.s: Avoid using @function syntax.
+
+2005-02-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elfvsb/hidden2.s: Replace .word with .long.
+
+2005-02-10  Paul Brook  <paul@codesourcery.com>
+
+	* ld-elfvsb/hidden2.s: New file
+	* ld-elfvsb/hidden2.d: New file
+	* ld-elfvsb/hidden2.ld: New file
+
+2005-02-07  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-frv/fdpic-shared-8-fail.d: Tweak error messages.
+
+2005-02-07  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/libdso-13.d: Adjust for being identified as warning.
+
+	* ld-cris/globsymw2.s: New file.
+	* ld-cris/warn3.d, ld-cris/warn4.d: New tests.
+
+	* ld-discard/extern.d, ld-discard/start.d, ld-discard/static.d:
+	Adjust for being identified as warnings.
+
+	* ld-cris/stabs1.s: New file.
+	* ld-cris/undef2.d, ld-cris/undef3.d: New tests.
+
+	* ld-elf/start.s, ld-elf/symbolref.s, ld-elf/symbol1w.s,
+	ld-elf/warn1.d: New test.
+
+	* lib/ld-lib.exp: Support new directive "warning".
+
+2005-02-02  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-mips-elf/eh-frame3.d, ld-mips-elf/eh-frame4.d: Move comments
+	after test commands.
+	* ld-mips-elf/mips-elf.exp: Skip multi-got-1 on non-GNU/Linux
+	systems.
+
+2005-02-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsso.r: Update.
+	* ld-powerpc/tlstocso.r: Update.
+
+2005-01-31  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-mips-elf/elf-rel-got-n32.d, ld-mips-elf/elf-rel-got-n64-linux.d,
+	ld-mips-elf/elf-rel-got-n64.d, ld-mips-elf/elf-rel-xgot-n32.d,
+	ld-mips-elf/elf-rel-xgot-n64-linux.d, ld-mips-elf/elf-rel-xgot-n64.d,
+	ld-mips-elf/jalbal.d: Force big-endian.
+	* ld-mips-elf/multi-got-1.d: Make more flexible.
+	* ld-mips-elf/rel32-n32.d, ld-mips-elf/rel32-o32.d,
+	ld-mips-elf/rel64.d: Update offsets.
+
+2005-01-31  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-elf/group1.d: Accept OBJECT symbols.
+
+2005-01-31  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-mips-elf/eh-frame1.s: Create a .gcc_compiled_long32 if using
+	32-bit pointers.
+	* ld-mips-elf/eh-frame1.d: Link in .gcc_compiled_long32 sections.
+	* ld-mips-elf/eh-frame[34].d: New tests.
+	* ld-mips-elf/mips-elf.exp: Run them.
+
+2005-01-28  Jan Beulich  <jbeulich@novell.com>
+
+	* ld/ia64/tlsbin.[rt]d: Widen expected offset/size ranges.
+	* ld/ia64/tlspic.[rt]d: Likewise.
+
+2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-frv/fdpic.exp: Add -mfdpic to ASFLAGS.
+	* ld-frv/tls.exp: Likewise.
+	2004-11-26  Alexandre Oliva  <aoliva@redhat.com>
+	* ld-frv/tls-3.s: New.
+	* ld-frv/tls-static-3.d: New.
+	* ld-frv/tls-dynamic-3.d: New.
+	* ld-frv/tls-pie-3.d: New.
+	* ld-frv/tls-shared-3.d: New.
+	* ld-frv/tls-relax-static-3.d: New.
+	* ld-frv/tls-relax-dynamic-3.d: New.
+	* ld-frv/tls-relax-pie-3.d: New.
+	* ld-frv/tls-relax-shared-3.d: New.
+	* ld-frv/tls.exp: Run the new tests.
+	* ld-frv/tls-dynamic-2.d: Adjust for improved relaxation.
+	* ld-frv/tls-relax-dynamic-2.d: Likewise.
+	* ld-frv/tls-relax-initial-shared-2.d: Likewise.
+	2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
+	* ld-frv/tls-1-dep.s: New.
+	* ld-frv/tls-1-shared.lds: New.
+	* ld-frv/tls-1.s: New.
+	* ld-frv/tls-2.s: New.
+	* ld-frv/tls-dynamic-1.d: New.
+	* ld-frv/tls-dynamic-2.d: New.
+	* ld-frv/tls-initial-shared-2.d: New.
+	* ld-frv/tls-pie-1.d: New.
+	* ld-frv/tls-relax-dynamic-1.d: New.
+	* ld-frv/tls-relax-dynamic-2.d: New.
+	* ld-frv/tls-relax-initial-shared-2.d: New.
+	* ld-frv/tls-relax-pie-1.d: New.
+	* ld-frv/tls-relax-shared-1.d: New.
+	* ld-frv/tls-relax-shared-2.d: New.
+	* ld-frv/tls-relax-static-1.d: New.
+	* ld-frv/tls-shared-1-fail.d: New.
+	* ld-frv/tls-shared-1.d: New.
+	* ld-frv/tls-shared-2.d: New.
+	* ld-frv/tls-static-1.d: New.
+	* ld-frv/tls.exp: New.
+	* ld-frv/fdpic-pie-1.d: Adjust for 64-bit host.
+	* ld-frv/fdpic-pie-2.d: Likewise.
+	* ld-frv/fdpic-pie-6.d: Likewise.
+	* ld-frv/fdpic-pie-7.d: Likewise.
+	* ld-frv/fdpic-pie-8.d: Likewise.
+	* ld-frv/fdpic-shared-1.d: Likewise.
+	* ld-frv/fdpic-shared-2.d: Likewise.
+	* ld-frv/fdpic-shared-3.d: Likewise.
+	* ld-frv/fdpic-shared-4.d: Likewise.
+	* ld-frv/fdpic-shared-5.d: Likewise.
+	* ld-frv/fdpic-shared-6.d: Likewise.
+	* ld-frv/fdpic-shared-7.d: Likewise.
+	* ld-frv/fdpic-shared-8.d: Likewise.
+	* ld-frv/fdpic-shared-local-2.d: Likewise.
+	* ld-frv/fdpic-shared-local-8.d: Likewise.
+	* ld-frv/fdpic-static-1.d: Likewise.
+	* ld-frv/fdpic-static-2.d: Likewise.
+	* ld-frv/fdpic-static-6.d: Likewise.
+	* ld-frv/fdpic-static-7.d: Likewise.
+	* ld-frv/fdpic-static-8.d: Likewise.
+
+2005-01-17  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-mips-elf/eh-frame2-{n32,n64}.d: New tests.
+	* ld-mips-elf/mips-elf.exp: Run them.
+
+2005-01-17  Andrew Stubbs  <andrew.stubbs@st.com>
+
+	* ld-sh/arch/arch.exp: Correct the email address.
+	Correct a few comment typos.
+	(test_arch,test_arch_error): Use 'ld -r' to avoid illegal
+	relocations killing the test.
+	* ld-sh/arch/arch_expected.txt: Update/Correct the test results.
+	* ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s: Regenerate.
+	* ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s: Regenerate.
+	* ld-sh/arch/sh2a-nofpu.s: Generate new file.
+	* ld-sh/arch/sh2a-or-sh3e.s: Regenerate.
+	* ld-sh/arch/sh2a-or-sh4.s: Regenerate.
+	* ld-sh/arch/sh2a.s: Generate new file.
+	* ld-sh/arch/sh2e.s: Regenerate.
+	* ld-sh/arch/sh2.s: Regenerate.
+	* ld-sh/arch/sh3-dsp.s: Regenerate.
+	* ld-sh/arch/sh3e.s: Regenerate.
+	* ld-sh/arch/sh3-nommu.s: Regenerate.
+	* ld-sh/arch/sh3.s: Regenerate.
+	* ld-sh/arch/sh4al-dsp.s: Regenerate.
+	* ld-sh/arch/sh4a-nofpu.s: Regenerate.
+	* ld-sh/arch/sh4a.s: Regenerate.
+	* ld-sh/arch/sh4-nofpu.s: Regenerate.
+	* ld-sh/arch/sh4-nommu-nofpu.s: Regenerate.
+	* ld-sh/arch/sh4.s: Regenerate.
+	* ld-sh/arch/sh-dsp.s: Regenerate.
+	* ld-sh/arch/sh.s: Regenerate.
+
+2005-01-11  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/shared-1.d: Update for changed dynamic syms.
+	* ld-sh/sh64/gotplt.d: Likewise.
+	* ld-sh/sh64/init-cmpct.d: Likewise.
+	* ld-sh/sh64/init-media.d: Likewise.
+	* ld-sh/sh64/init64.d: Likewise.
+
+For older changes see ChangeLog-2004
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.19/ld/testsuite/ChangeLog-2006 b/binutils-2.19/ld/testsuite/ChangeLog-2006
new file mode 100644
index 0000000..2ff0c39
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ChangeLog-2006
@@ -0,0 +1,1285 @@
+2006-12-29  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/wrap.exp: New file.
+	* ld-elf/wrap1.c: Likewise.
+	* ld-elf/wrap1.out: Likewise.
+	* ld-elf/wrap1a.c: Likewise.
+	* ld-elf/wrap1b.c: Likewise.
+
+2006-12-18  Pedro Alves  <pedro_alves@portugalmail.pt>
+
+	* ld-pe/direct.exp: New file.
+	* ld-pe/direct_client.c: Likewise.
+	* ld-pe/direct_dll.c: Likewise.
+
+2006-12-13  Dave Brolley  <brolley@redhat.com>
+
+	* lib/ld-lib.exp (big_or_little_endian): Accept -meb and
+	-mel for big and little endian respectively.
+
+2006-12-12  Ina Pandit  <inap@kpitcummins.com>
+
+	* ld-scripts/overlay-size-map.d: Update.
+
+2006-12-07  H.J. Lu <hjl@gnu.org>
+
+	PR ld/3666
+	* ld-elf/group3a.d: New file.
+	* ld-elf/group3a.s: Likewise.
+	* ld-elf/group3b.d: Likewise.
+	* ld-elf/group3b.s: Likewise.
+
+2006-12-05  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-alpha/tlspic.rd: Update for unused section removal.
+	* ld-frv/fdpic-shared-6.d: Likewise.
+	* ld-frv/tls-dynamic-1.d: Update for symbol changes.
+	* ld-frv/tls-dynamic-2.d: Likewise.
+	* ld-frv/tls-dynamic-3.d: Likewise.
+	* ld-frv/tls-initial-shared-2.d: Likewise.
+	* ld-frv/tls-pie-1.d: Likewise.
+	* ld-frv/tls-pie-3.d: Likewise.
+	* ld-frv/tls-relax-dynamic-1.d: Likewise.
+	* ld-frv/tls-relax-dynamic-2.d: Likewise.
+	* ld-frv/tls-relax-dynamic-3.d: Likewise.
+	* ld-frv/tls-relax-initial-shared-2.d: Likewise.
+	* ld-frv/tls-relax-pie-1.d: Likewise.
+	* ld-frv/tls-relax-pie-3.d: Likewise.
+	* ld-frv/tls-relax-shared-1.d: Likewise.
+	* ld-frv/tls-relax-shared-2.d: Likewise.
+	* ld-frv/tls-relax-shared-3.d: Likewise.
+	* ld-frv/tls-relax-static-3.d: Likewise.
+	* ld-frv/tls-shared-1.d: Likewise.
+	* ld-frv/tls-shared-2.d: Likewise.
+	* ld-frv/tls-shared-3.d: Likewise.
+	* ld-frv/tls-static-1.d: Likewise.
+	* ld-frv/tls-static-3.d: Likewise.
+
+2006-12-05  Jakub Jelinek  <jakub@redhat.com>
+	    Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elfvsb/sh1.c (overriddenvar, shlib_overriddencall2,
+	shared_data): If !SHARED, move to...
+	* ld-elfvsb/sh2.c: ... here.
+	* ld-elfvsb/elfvsb.exp: Add -DSHARED to compiler options when
+	building with $picflag.
+
+2006-12-04  Jan Beulich  <jbeulich@novell.com>
+
+	* ld-elf/eh-frame-hdr.d: New.
+	* ld-elf/eh-frame-hdr.s: New.
+	* ld-ia64/tlsbin.dd, ld-ia64/tlsbin.sd: Don't depend on exact linkage
+	table layout.
+
+2006-11-23  Thiemo Seufer  <ths@mips.com>
+
+	* ld-elf/warn2.d: Match regex also for the second segment.
+
+2006-11-22  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-arm/mixed-app.d, ld-arm/tls-app.d, ld-arm/tls-lib.d: Update
+	for $d support.
+
+2006-11-21  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-elf/eh5.d: New test.
+	* ld-elf/eh5.s: New file.
+	* ld-elf/eh5a.s: New file.
+	* ld-elf/eh5b.s: New file.
+
+2006-11-13  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-arm/arm-dyn.ld, ld-arm/arm-lib.ld: Remove .stack.
+	* ld-arm/armthumb-lib.d, ld-arm/mixed-app.d, ld-arm/mixed-lib.d:
+	Allow smaller section gap.
+	* ld-arm/armthumb-lib.sym, ld-arm/mixed-lib.sym: Reorder.  Remove
+	_stack.
+	* ld-arm/mixed-app.sym: Remove _stack.
+	* ld-arm/tls-app.d: Update start address.
+
+2006-11-08  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/group.ld: Handle .rodata.brlt for powerpc64.
+
+2006-11-07  Vladimir Prus  <vladimir@codesourcery.com>
+
+	* testsuite/ld-elf/symbol2w.s: Use "%" instead of "@" to avoid
+	breakage on ARM.
+
+2006-11-06  Vladimir Prus  <vladimir@codesourcery.com>
+
+	* testsuite/ld-elf/symbol1ref.s: Use ".dc.a" instead
+	of ".long".
+
+2006-11-06  Vladimir Prus  <vladimir@codesourcery.com>
+
+	* testsuite/ld-elf/warn2.d: New.
+	* testsuite/ld-elf/symbol2w.s: New.
+	* testsuite/ld-elf/symbol2ref.s: New.
+
+2006-11-05  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/ldsym1.d: Adjust for semi-recent ld changes.
+
+2006-11-02  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-discard/zero-rel.d, ld-discard/zero-rel.s: New files.
+
+2006-11-01  Thiemo Seufer  <ths@mips.com>
+
+	* ld-mips-elf/mips16-intermix-1.s, ld-mips-elf/mips16-intermix-2.s,
+	ld-mips-elf/mips16-intermix.d: New testcase.
+	* ld-mips-elf/mips-elf.exp (mips16_intermix_test): Run new testcases.
+
+2006-10-29  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/sh64/abi32.xd, ld-sh/sh64/abi64.xd, ld-sh/sh64/cmpct1.xd,
+	* ld-sh/sh64/crange1.rd, ld-sh/sh64/crange2.rd,
+	* ld-sh/sh64/crange3-cmpct.rd, ld-sh/sh64/crange3-media.rd,
+	* ld-sh/sh64/crange3.rd, ld-sh/sh64/mix1.xd, ld-sh/sh64/mix2.xd,
+	* ld-sh/sh64/shdl32.xd, ld-sh/sh64/shdl64.xd: Update for removal
+	of empty sections.
+
+2006-10-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-spu/ovl.d: New file.
+	* ld-spu/ovl.lnk: New file.
+	* ld-spu/ovl.s: New file.
+	* ld-spu/spu.exp: New file.
+	* ld-elf/sec64k.exp: Tweak ld options for SPU.
+	* ld-scripts/empty-orphan.exp: Likewise.
+	* ld-scripts/phdrs.exp: Likewise.
+	* ld-scripts/phdrs2.exp: Likewise.
+
+2006-10-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/plt1.s: New.
+	* ld-powerpc/plt1.d: New.
+	* ld-powerpc/relbrlt.s: New.
+	* ld-powerpc/relbrlt.d: New.
+	* ld-powerpc/powerpc.exp: Run them.
+
+2006-10-21  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/sh64/abi32.xd, ld-sh/sh64/abi64.xd, ld-sh/sh64/cmpct1.xd,
+	* ld-sh/sh64/crange1.rd, ld-sh/sh64/crange2.rd,
+	* ld-sh/sh64/crange3-cmpct.rd, ld-sh/sh64/crange3-media.rd,
+	* ld-sh/sh64/crange3.rd, ld-sh/sh64/crangerel1.rd,
+	* ld-sh/sh64/crangerel2.rd, ld-sh/sh64/mix1.xd,
+	* ld-sh/sh64/mix2.xd, ld-sh/sh64/rel32.xd, ld-sh/sh64/rel64.xd,
+	* ld-sh/sh64/reldl32.rd, ld-sh/sh64/reldl64.rd,
+	* ld-sh/sh64/shdl32.xd, ld-sh/sh64/shdl64.xd: Update.
+
+2006-10-20  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/tlsbin-1.d: Update.
+	* ld-sh/tlspic-1.d: Likewise.
+	* ld-sh/tlstpoff-1.d: Likewise.
+
+2006-10-20  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/multi-got-1.d: Remove trailing R_MIPS_NONE entries.
+	* ld-mips-elf/tls-multi-got-1.got: Likewise.
+	* ld-mips-elf/tls-multi-got-1.r: Likewise.
+
+2006-10-20  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/multi-got-1.d: Do not expect a particular address
+	for DT_HASH.
+	* ld-mips-elf/rel32-o32.d: Bump addresses by 0x20 to account for
+	the extra program header.
+	* ld-mips-elf/rel32-n32.d: Likewise.
+	* ld-mips-elf/tlslib-o32.got: Likewise.
+	* ld-mips-elf/tlslib-o32-hidden.got: Likewise.
+	* ld-mips-elf/tlslib-o32-ver.got: Likewise.
+	* ld-mips-elf/tls-multi-got-1.got: Likewise.
+	* ld-mips-elf/tls-multi-got-1.r: Likewise.
+	* ld-mips-elf/rel64.d: Bump addresses by 0x30 to account for the
+	extra program header.
+	* ld-mips-elf/tlsdyn-o32.d: Reduce the GOT offset by 32 to account
+	for the extra program header, and thus the shorter gap between the
+	text and data segments.
+	* ld-mips-elf/tlsdyn-o32-1.d: Likewise.
+	* ld-mips-elf/tlsdyn-o32-2.d: Likewise.
+	* ld-mips-elf/tlsdyn-o32-3.d: Likewise.
+	* ld-mips-elf/tlsdyn-o32.got: Bump GOT text addresses by 0x20
+	to account for the extra program header.
+	* ld-mips-elf/tlsdyn-o32-1.got: Likewise.
+	* ld-mips-elf/tlsdyn-o32-2.got: Likewise.
+	* ld-mips-elf/tlsdyn-o32-3.got: Likewise.
+
+2006-10-20  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/rel32-o32.d: Bump the section number of .text by 1
+	to account for the fact that .rel.dyn is now before .text in the
+	section table.
+	* ld-mips-elf/rel32-n32.d: Likewise.
+	* ld-mips-elf/rel64.d: Likewise.
+
+2006-10-19  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/tlslib-o32-hidden.got: Sort relocations against the
+	same symbol in order of increasing r_offset.
+	* ld-mips-elf/tls-multi-got-1.got: Likewise.
+	* ld-mips-elf/tls-hidden3.r: Likewise.
+	* ld-mips-elf/tls-hidden4.r: Likewise.
+
+2006-10-19  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/multi-got-1.d: Remove DT_DEBUG tag.  Do not require
+	a specific file offset for .dynamic.  Reduce DT_HASH by 8 to account
+	for removed tag.
+	* ld-mips-elf/tls-multi-got-1.r: Likewise.  Also reduce DT_REL by 8.
+	Reduce PLTGOT and symbol values by 16 to account for the removed tag.
+	* ld-mips-elf/textrel-1.d: Remove DT_DEBUG tag.
+	* ld-mips-elf/rel32-n32.d: Reduce addresses by 16 to account for
+	removed DT_DEBUG tag.
+	* ld-mips-elf/rel64.d: Likewise.
+	* ld-mips-elf/tls-multi-got-1.got: Likewise.
+	* ld-mips-elf/tlslib-o32-hidden.got: Likewise.
+
+2006-10-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/3290
+	* ld-elf/dummy.c: New file.
+	* ld-elf/dwarf.exp: Likewise.
+	* ld-elf/dwarf1.c: Likewise.
+	* ld-elf/dwarf1.h: Likewise.
+	* ld-elf/dwarf1.out: Likewise.
+	* ld-elf/dwarf1main.c: Likewise.
+
+2006-10-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/dl4.c: New file.
+	* ld-elf/dl4.list: Likewise.
+	* ld-elf/dl4a.out: Likewise.
+	* ld-elf/dl4b.out: Likewise.
+	* ld-elf/dl4main.c: Likewise.
+	* ld-elf/dl4xxx.c: Likewise.
+	* ld-elf/dl4xxx.list: Likewise.
+
+	* ld-elf/shared.exp (build_tests): Add libdl4a.so and
+	libdl4b.so.
+	(run_tests): Likewise.
+
+2006-10-18  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/reloc-1-n64.d: Match 16-character VMAs on LP64 hosts.
+
+2006-10-18  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/rel32-n32.d: Bump addresses by 0x20 to account for
+	the fact that .reginfo is now placed before .text.  Change the
+	section number of .text accordingly.
+
+2006-10-18  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/elf-rel-got-n32.d: Adjust page gap from 0x100000
+	to 0x10000.  Move .reginfo before .text and bump .text addresses
+	by 0x10 to make room.  Move data segment down by 0x10 bytes to
+	account for new size of text segment.
+	* ld-mips-elf/elf-rel-xgot-n32.d: Likewise.
+	* ld-mips-elf/elf-rel-got-n64-linux.d: Adjust page gap from
+	0x100000 to 0x10000.
+	* ld-mips-elf/elf-rel-xgot-n64-linux.d: Likewise.
+
+2006-10-17  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* ld-arm/arm-elf.exp: Add thumb1-bl, thumb2-bl,
+	thumb2-bl-as-thumb1-bad and thumb2-bl-bad tests.
+	* ld-arm/thumb1-bl.d: New.
+	* ld-arm/thumb1-bl.s: New.
+	* ld-arm/thumb2-bl-as-thumb1-bad.d: New.
+	* ld-arm/thumb2-bl-as-thumb1-bad.s: New.
+	* ld-arm/thumb2-bl-bad.d: New.
+	* ld-arm/thumb2-bl-bad.s: New.
+	* ld-arm/thumb2-bl.d: New.
+	* ld-arm/thumb2-bl.s: New.
+
+2006-10-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-arm/mixed-app.sym, ld-cris/ldsym1.d, ld-cris/libdso-12.d,
+	* ld-cris/v32-ba-1.d, ld-elf/orphan.d, ld-elf/orphan2.d,
+	* ld-i386/tlsbin.rd, ld-i386/tlsbindesc.rd, ld-i386/tlsdesc.rd,
+	* ld-i386/tlsdesc.sd, ld-i386/tlsgdesc.rd, ld-i386/tlsnopic.rd,
+	* ld-i386/tlspic.rd, ld-ia64/tlspic.rd, ld-mips-elf/eh-frame1-n32.d,
+	* ld-mips-elf/eh-frame1-n64.d, ld-mips-elf/eh-frame2-n32.d,
+	* ld-mips-elf/eh-frame2-n64.d, ld-mips-elf/mips-elf.exp,
+	* ld-mips-elf/rel32-n32.d, ld-mips-elf/rel32-o32.d,
+	* ld-mips-elf/rel64.d, ld-mips-elf/tls-multi-got-1.got,
+	* ld-mips-elf/tls-multi-got-1.r, ld-mips-elf/tlsdyn-o32-1.d,
+	* ld-mips-elf/tlsdyn-o32-1.got, ld-mips-elf/tlsdyn-o32-2.d,
+	* ld-mips-elf/tlsdyn-o32-2.got, ld-mips-elf/tlsdyn-o32-3.d,
+	* ld-mips-elf/tlsdyn-o32-3.got, ld-mips-elf/tlsdyn-o32.d,
+	* ld-mips-elf/tlsdyn-o32.got, ld-mips-elf/tlslib-o32-hidden.got,
+	* ld-mips-elf/tlslib-o32-ver.got, ld-mips-elf/tlslib-o32.got,
+	* ld-mmix/bpo-10.d, ld-powerpc/tlsso.g, ld-powerpc/tlsso.r,
+	* ld-powerpc/tlsso32.d, ld-powerpc/tlsso32.g, ld-powerpc/tlsso32.r,
+	* ld-powerpc/tlstocso.g, ld-powerpc/tlstocso.r, ld-s390/tlspic.rd,
+	* ld-s390/tlspic_64.rd, ld-scripts/empty-address-1.d,
+	* ld-scripts/empty-address-3c.d, ld-scripts/empty-orphan.t,
+	* ld-sh/shared-1.d, ld-sh/tlspic-2.d, ld-sparc/tlssunbin32.rd,
+	* ld-sparc/tlssunbin64.rd, ld-sparc/tlssunpic32.rd,
+	* ld-sparc/tlssunpic64.rd, ld-x86-64/tlsdesc.pd, ld-x86-64/tlsdesc.rd,
+	* ld-x86-64/tlspic.rd: Update for section sym changes.
+
+2006-10-16  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/branch-misc-1.d: Set the start address to 0x20000000.
+	* ld-mips-elf/jalbal.d: Likewise 0x200000a0.
+	* ld-mips-elf/jaloverflow-2.d: Likewise 0x20000000.
+	* ld-mips-elf/reloc-3-n32.d: Likewise.
+	* ld-mips-elf/reloc-3.d: Likewise.
+	* ld-mips-elf/textrel-1.d: Don't require a specific file offset for
+	.dynamic.
+
+2006-10-03  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-elf/eh4.d: New test.
+	* ld-elf/eh4.s: New file.
+	* ld-elf/eh4a.s: New file.
+
+2006-10-02  Vladimir Prus  <vladimir@codesourcery.com>
+
+	* ld-arm/use-thumb-lib.sym: Robustify, by ignoring symbols we're
+	not interested in and bucket number.
+
+2006-10-02  Kai Tietz  <Kai.Tietz@onevision.com>
+
+	* ld-fastcall/fastcall.exp: Add x86_64-pc-mingw64 as valid target.
+	* ld-pe/pe.exp: Likewise.
+	* lib/ld-lib.exp ( is_pecoff_format): Accept x86_64-pc-mingw64.
+
+2006-09-29  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/tlspic-2.d: Update.
+
+2006-09-26  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/3223
+	PR ld/3267
+	* ld-scripts/empty-address-1.d: New file.
+	* ld-scripts/empty-address-1.s: Likewise.
+	* ld-scripts/empty-address-1.t: Likewise.
+	* ld-scripts/empty-address-2.s: Likewise.
+	* ld-scripts/empty-address-2a.d: Likewise.
+	* ld-scripts/empty-address-2a.t: Likewise.
+	* ld-scripts/empty-address-2b.d: Likewise.
+	* ld-scripts/empty-address-2b.t: Likewise.
+	* ld-scripts/empty-address-3.s: Likewise.
+	* ld-scripts/empty-address-3a.d: Likewise.
+	* ld-scripts/empty-address-3a.t: Likewise.
+	* ld-scripts/empty-address-3b.d: Likewise.
+	* ld-scripts/empty-address-3b.t: Likewise.
+	* ld-scripts/empty-address-3c.d: Likewise.
+	* ld-scripts/empty-address-3c.t: Likewise.
+	* ld-scripts/empty-address.exp: Likewise.
+
+2006-09-21  Andreas Schwab  <schwab@suse.de>
+
+	* ld-m68k/plt1-68020.d: Fix patterns to match also for 64-bit
+	hosts.
+
+2006-09-20  Kai Tietz  <Kai.Tietz@onevision.com>
+
+	* bootstrap/bootstrap.exp: Fix x86_64-mingw32 target test.
+	* ld-fastcall/fastcall.exp: Likewise.
+	* ld-scripts/align.exp: Likewise.
+	* ld-scripts/align2a.d: Likewise.
+	* ld-scripts/defined.exp: Likewise.
+	* ld-scripts/provide.exp: Likewise.
+	* ld-scripts/script.exp: Likewise.
+	* ld-scripts/weak.exp: Likewise.
+	* lib/ld-lib.exp: Detect target as pecoff file format.
+
+2006-09-18  Thiemo Seufer  <ths@networkno.de>
+	    Maciej W. Rozycki  <macro@mips.com>
+
+	* ld-mips-elf/mips-elf.exp: Add test for R_MIPS16_GPREL relocations.
+	* ld-mips-elf/reloc-3-n32.d, ld-mips-elf/reloc-3.d: New files.
+
+2006-09-18  Thiemo Seufer  <ths@networkno.de>
+
+	* ld-elfcomm/elfcomm.exp: Enable the alignment test for
+	mips*-*-*.
+
+2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
+
+	* ld-elf/merge.d: Add special case for Score target.
+	* ld-elfcomm/elfcomm.exp: Likewise.
+	* ld-srec/srec.exp: Likewise.
+
+2006-09-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-scripts/overlay-size.t: Discard .reginfo sections.
+
+2006-09-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/hash.d: Don't run for mips targets.
+
+2006-09-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/loadaddr.s: Pad sections to 16 bytes.
+	* ld-elf/loadaddr1.d: Updated.
+	* ld-elf/loadaddr2.d: Likewise.
+	* ld-elf/loadaddr3a.d: Likewise.
+	* ld-elf/loadaddr3b.d: Likewise.
+
+2006-09-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/3197
+	* ld-elf/hash.d: New test.
+
+2006-09-04  Vladimir Prus  <vladimir@codesourcery.com>
+
+	* ld-arm/use-thumb-lib.sym: Use regexps instead of
+	absolute addresses, for robustness.
+
+2006-09-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/dl1.c: New file.
+	* ld-elf/dl1.list: Likewise.
+	* ld-elf/dl1.out: Likewise.
+	* ld-elf/dl1main.c: Likewise.
+	* ld-elf/dl2.c: Likewise.
+	* ld-elf/dl2.list: Likewise.
+	* ld-elf/dl2a.out: Likewise.
+	* ld-elf/dl2b.out: Likewise.
+	* ld-elf/dl2main.c: Likewise.
+	* ld-elf/dl2xxx.c: Likewise.
+	* ld-elf/dl2xxx.list: Likewise.
+	* ld-elf/dl3.cc: Likewise.
+	* ld-elf/dl3.list: Likewise.
+	* ld-elf/dl3a.out: Likewise.
+	* ld-elf/dl3b.out: Likewise.
+	* ld-elf/dl3header.h: Likewise.
+	* ld-elf/dl3main.cc: Likewise.
+
+	* ld-elf/shared.exp: Updated.
+
+	* lib/ld-lib.exp (run_ld_link_exec_tests): Take an optional
+	argument for source language. Use CC/CXX for link, depending
+	on source language.
+	(run_cc_link_tests): Likewise.
+
+2006-08-29  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/loadaddr3a.d: Adjust target test.
+	* ld-elf/loadaddr3b.d: Likewise.
+
+2006-08-29  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-elf/loadaddr3.t: New.
+	* ld-elf/loadaddr3a.d: New.
+	* ld-elf/loadaddr3b.d: New.
+
+2006-08-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/plt1.s: New.
+	* ld-powerpc/plt1.d: New.
+	* ld-powerpc/powerpc.exp: Run it.
+
+2006-08-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/3052
+	* ld-elf/loadaddr1.t: Add "AT (ADDR(.data))".
+	* ld-elf/loadaddr2.t: Likewise.
+
+2006-08-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/3103
+	* ld-elf/overlay.d: New file.
+	* ld-elf/overlay.s: Likewise.
+	* ld-elf/overlay.t: Likewise.
+
+2006-08-18  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-elf.exp (armelftests): Add armthumb-lib.so.  Add
+	-use-blx to mixed-lib.so
+	* ld-arm/armthumb-lib.d: New file.
+	* ld-arm/armthumb-lib.sym: New file.
+
+2006-08-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/3052
+	* ld-elf/loadaddr.s: New file.
+	* ld-elf/loadaddr1.d: Likewise.
+	* ld-elf/loadaddr1.t: Likewise.
+	* ld-elf/loadaddr2.d: Likewise.
+	* ld-elf/loadaddr2.t: Likewise.
+
+2006-08-17  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexe.d: Update for lazy link stub change.
+	* ld-powerpc/tlsexe.r: Likewise.
+	* ld-powerpc/tlsexetoc.d: Likewise.
+	* ld-powerpc/tlsexetoc.r: Likewise.
+	* ld-powerpc/tlsso.d: Likewise.
+	* ld-powerpc/tlstocso.d: Likewise.
+
+2006-08-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/3015
+	* ld-elf/binutils.exp: Add tests for "-z relro".
+
+2006-08-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/overlay-size-map.d: Update.
+
+2006-08-11  Thiemo Seufer  <ths@mips.com>
+
+	* ld-elfcomm/elfcomm.exp (dump_common1): Extend regexp to match also
+	MIPS small commons.
+
+2006-08-08  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/3009
+	* ld-scripts/sort.t: New file.
+	* ld-scripts/sort_b_a-1.d: Likewise.
+	* ld-scripts/sort_b_a-1.s: Likewise.
+	* ld-scripts/sort_b_n-1.d: Likewise.
+	* ld-scripts/sort_b_n-1.s: Likewise.
+
+2006-08-05  Pedro Alves  <pedro_alves@portugalmail.pt>
+
+	* ld-pe/pe.exp: Enable tests on arm-wince-pe.
+	* ld-pe/secrel.d: Adjust test to work on arm-wince-pe too.
+
+2006-08-04  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-sh/rd-sh.exp: Treat vxworks1-static.d specially.
+	* ld-sh/sh-vxworks.exp: New file.
+	* ld-sh/sh.exp: Extend sh-linux SIZEOF_HEADERS handling to
+	sh-*-vxworks.
+	* ld-sh/vxworks1-le.dd, ld-sh/vxworks1-lib-le.dd,
+	* ld-sh/vxworks1-lib.dd, ld-sh/vxworks1-lib.nd,
+	* ld-sh/vxworks1-lib.rd, ld-sh/vxworks1-lib.s,
+	* ld-sh/vxworks1-static.d, ld-sh/vxworks1.dd,
+	* ld-sh/vxworks1.ld, ld-sh/vxworks1.rd, ld-sh/vxworks1.s,
+	* ld-sh/vxworks2-static.sd, ld-sh/vxworks2.s,
+	* ld-sh/vxworks2.sd, ld-sh/vxworks3-le.dd,
+	* ld-sh/vxworks3-lib-le.dd, ld-sh/vxworks3-lib.dd,
+	* ld-sh/vxworks3-lib.s, ld-sh/vxworks3.dd, ld-sh/vxworks3.s,
+	* ld-sh/vxworks4.d, ld-sh/vxworks4a.s, ld-sh/vxworks4b.s,
+	* ld-sh/reloc1.s, ld-sh/reloc1.d: New tests.
+
+2006-08-01  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/noload-1.d: New.
+	* ld-elf/noload-1.s: Likewise.
+	* ld-elf/noload-1.t: Likewise.
+
+2006-07-29  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/hash1.s, ld-mips-elf/hash1a.d,
+	* ld-mips-elf/hash1b.d, ld-mips-elf/hash1c.d: New tests.
+	* ld-mips-elf/mips-elf.exp: Run them.
+
+2006-07-25  Thiemo Seufer  <ths@mips.com>
+
+	* ld-mips-elf/mips16-call-global-2.s,
+	ld-mips-elf/mips16-call-global-3.s, ld-mips-elf/mips16-call-global.d:
+	Improve test robustness.
+
+2006-07-21  Nick Clifton  <nickc@redhat.com>
+
+	* ld-sh/arch/arch.exp (test_arch): Set the endian flag to suit the
+	multilib being tested.
+
+2006-07-20  Thiemo Seufer  <ths@mips.com>
+
+	* ld-mips-elf/mips16-call-global-1.s,
+	ld-mips-elf/mips16-call-global-2.s,
+	ld-mips-elf/mips16-call-global-3.s, ld-mips-elf/mips16-call-global.d:
+	Test linking of external mips16 jumps.
+	* ld-mips-elf/mips-elf.exp: Run new test.
+
+2006-07-19  Thiemo Seufer  <ths@mips.com>
+
+	* ld-selective/selective.exp: Fix selective testcases for MIPS.
+
+2006-07-13  Thiemo Seufer  <ths@mips.com>
+
+	* ld-mips-elf/tlslib-o32-ver.got, ld-mips-elf/tlslib-o32.got:
+	Update TLS testcases.
+
+2006-07-12  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/2884
+	* ld-elf/begin.c: New file.
+	* ld-elf/end.c: Likewise.
+	* ld-elf/endhidden.c: Likewise.
+	* ld-elf/endprotected.c: Likewise.
+	* ld-elf/foo.c: Likewise.
+	* ld-elf/foo.map: Likewise.
+	* ld-elf/hidden.out: Likewise.
+	* ld-elf/main.c: Likewise.
+	* ld-elf/normal.out: Likewise.
+	* ld-elf/shared.exp: Likewise.
+
+	* lib/ld-lib.exp (run_cc_link_tests): New.
+
+2006-07-12  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-m68k/merge-ok-1c.d: New test.
+	* ld-m68k/m68k.exp: Run it.
+
+2006-07-11  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/libdso-2.d: Adjust for recent hash-related changes.
+
+2006-07-10  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-powerpc/tlsso32.r: Adjust.
+	* ld-powerpc/tlsso32.d: Adjust.
+	* ld-powerpc/tlsso32.g: Adjust.
+	* ld-powerpc/tlsso.r: Adjust.
+	* ld-powerpc/tlsso.g: Adjust.
+	* ld-powerpc/tlstocso.g: Adjust.
+
+2006-07-05  Thiemo Seufer  <ths@mips.com>
+
+	* ld-mips-elf/multi-got-1.d, ld-mips-elf/tls-multi-got-1.got,
+	ld-mips-elf/tls-multi-got-1.r: Update multigot testcases.
+
+2006-06-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-i386/tlsbindesc.dd: Updated to expect xchg %ax,%ax instead
+	of 2 nops.
+	* ld-i386/tlsdesc.dd: Likewise.
+	* ld-i386/tlsgdesc.dd: Likewise.
+	* ld-x86-64/tlsbindesc.dd: Likewise.
+	* ld-x86-64/tlsdesc.dd: Likewise.
+	* ld-x86-64/tlsdesc.pd: Likewise.
+	* ld-x86-64/tlsgdesc.dd: Likewise.
+
+2006-06-29  Jakub Jelinek  <jakub@redhat.com>
+
+	PR ld/2513
+	* ld-i386/tlsbin.dd: Fix expected output.
+
+2006-06-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/tls_common.exp: Match 32-bit output.
+
+2006-06-20  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-elf/tls_common.exp: New test.
+	* ld-elf/tls_common.s: New file.
+
+2006-06-20  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/eh1.d: Update for fewer program headers.
+	* ld-elf/eh2.d: Likewise.
+	* ld-elf/eh3.d: Likewise.
+
+2006-06-19  Vladimir Prus  <vladimir@codesourcery.com>
+
+	* ld-arm/arm-elf.exp: New test.
+	* ld-arm/use-thumb-lib.s: New file.
+	* ld-arm/use-thumb-lib.sym: New file.
+
+2006-06-15  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* ld-arm/group-relocs-alu-bad.d: New test.
+	* ld-arm/group-relocs-alu-bad.s: New test.
+	* ld-arm/group-relocs.d: New test.
+	* ld-arm/group-relocs-ldc-bad.d: New test.
+	* ld-arm/group-relocs-ldc-bad.s: New test.
+	* ld-arm/group-relocs-ldr-bad.d: New test.
+	* ld-arm/group-relocs-ldr-bad.s: New test.
+	* ld-arm/group-relocs-ldrs-bad.d: New test.
+	* ld-arm/group-relocs-ldrs-bad.s: New test.
+	* ld-arm/group-relocs.s: New test.
+	* ld-arm/arm-elf.exp: Wire in new tests.
+
+2006-06-14  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-m68k/plt1.s, ld-m68k/plt1-empty.s, ld-m68k/plt1.ld: New files.
+	* ld-m68k/plt1-68020.d, ld-m68k/plt1-cpu32.d: Likewise.
+	* ld-m68k/plt1-isab.d: Likewise.
+	* ld-m68k/m68k.exp: Run new PLT tests.
+
+2006-06-12  Thiemo Seufer  <ths@mips.com>
+
+	* ld-mips-elf/multi-got-no-shared.d: Adjust for recent change of
+	ELF_MAXPAGESIZE.
+
+2006-06-11  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/stub-dynsym-1.s,
+	* ld-mips-elf/stub-dynsym-1.ld,
+	* ld-mips-elf/stub-dynsym-1-7fff.d,
+	* ld-mips-elf/stub-dynsym-1-8000.d,
+	* ld-mips-elf/stub-dynsym-1-fff0.d,
+	* ld-mips-elf/stub-dynsym-1-10000.d,
+	* ld-mips-elf/stub-dynsym-1-2fe80.d: New test.
+	* ld-mips-elf/mips-elf.exp: Run it.
+
+2006-06-06  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elfvers/vers.exp (objdump_versionstuff): Allow versions in
+	any order.
+	* ld-elfvers/vers1.ver: Update.
+	* ld-elfvers/vers2.ver: Update.
+	* ld-elfvers/vers4a.ver: Update.
+	* ld-elfvers/vers7a.ver: Update.
+	* ld-elfvers/vers8.ver: Update.
+	* ld-elfvers/vers9.ver: Update.
+	* ld-elfvers/vers15.ver: Update.
+	* ld-elfvers/vers16a.ver: Update.
+	* ld-elfvers/vers17.ver: Update.
+	* ld-elfvers/vers18.ver: Update.
+	* ld-elfvers/vers20.ver: Update.
+	* ld-elfvers/vers20a.ver: Update.
+	* ld-elfvers/vers21.ver: Update.
+	* ld-elfvers/vers22a.ver: Update.
+	* ld-elfvers/vers22b.ver: Update.
+	* ld-elfvers/vers23a.ver: Update.
+	* ld-elfvers/vers23b.ver: Update.
+	* ld-elfvers/vers23c.ver: Update.
+	* ld-elfvers/vers25a.ver: Update.
+	* ld-elfvers/vers26a.ver: Update.
+	* ld-elfvers/vers27a.ver: Update.
+	* ld-elfvers/vers27d.ver: Update.
+	* ld-elfvers/vers28b.ver: Update.
+	* ld-elfvers/vers29.ver: Update.
+	* ld-elfvers/vers30.ver: Update.
+	* ld-elfvers/vers31.ver: Update.
+
+2006-06-05  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/sec64k.exp: Add "main" symbol.  Use dc.a for addresses.
+	Cater for different address sizes.  Match end of line when
+	comparing symbols.
+	* ld-elf/start.s: Use dc.a for addresses.
+
+2006-06-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexe.r: Update for removal of some section syms.
+	* ld-powerpc/tlsexetoc.r: Likewise.
+	* ld-powerpc/tlsso.r: Likewise.
+	* ld-powerpc/tlstocso.r: Likewise.
+	* ld-s390/tlsbin_64.rd: Likewise.
+	* ld-s390/tlspic_64.rd: Likewise.
+
+2006-06-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/2723
+	* ld-alpha/tlsbin.rd: Update for removal of some section syms.
+	* ld-alpha/tlsbinr.rd: Likewise.
+	* ld-alpha/tlspic.rd: Likewise.
+	* ld-cris/hiddef1.d: Likewise.
+	* ld-cris/libdso-2.d: Likewise.
+	* ld-elf/sec64k.exp: Likewise.
+	* ld-i386/tlsbin.rd: Likewise.
+	* ld-i386/tlsbindesc.rd: Likewise.
+	* ld-i386/tlsdesc.rd: Likewise.
+	* ld-i386/tlsgdesc.rd: Likewise.
+	* ld-i386/tlsnopic.rd: Likewise.
+	* ld-i386/tlspic.rd: Likewise.
+	* ld-ia64/tlsbin.rd: Likewise.
+	* ld-ia64/tlspic.rd: Likewise.
+	* ld-mmix/bpo-1.d: Likewise.
+	* ld-mmix/bpo-10.d: Likewise.
+	* ld-mmix/bpo-11.d: Likewise.
+	* ld-mmix/bpo-14.d: Likewise.
+	* ld-mmix/bpo-16.d: Likewise.
+	* ld-mmix/bpo-17.d: Likewise.
+	* ld-mmix/bpo-18.d: Likewise.
+	* ld-mmix/bpo-19.d: Likewise.
+	* ld-mmix/bpo-2.d: Likewise.
+	* ld-mmix/bpo-22.d: Likewise.
+	* ld-mmix/bpo-3.d: Likewise.
+	* ld-mmix/bpo-4.d: Likewise.
+	* ld-mmix/bpo-5.d: Likewise.
+	* ld-mmix/bpo-6.d: Likewise.
+	* ld-mmix/bpo-9.d: Likewise.
+	* ld-mmix/bspec1.d: Likewise.
+	* ld-mmix/bspec2.d: Likewise.
+	* ld-mmix/greg-1.d: Likewise.
+	* ld-mmix/greg-19.d: Likewise.
+	* ld-mmix/greg-2.d: Likewise.
+	* ld-mmix/greg-3.d: Likewise.
+	* ld-mmix/greg-4.d: Likewise.
+	* ld-mmix/greg-5.d: Likewise.
+	* ld-mmix/greg-5s.d: Likewise.
+	* ld-mmix/greg-6.d: Likewise.
+	* ld-mmix/greg-7.d: Likewise.
+	* ld-mmix/loc1.d: Likewise.
+	* ld-mmix/loc2.d: Likewise.
+	* ld-mmix/loc3.d: Likewise.
+	* ld-mmix/loc4.d: Likewise.
+	* ld-mmix/loc6.d: Likewise.
+	* ld-mmix/local1.d: Likewise.
+	* ld-mmix/local3.d: Likewise.
+	* ld-mmix/local5.d: Likewise.
+	* ld-mmix/local7.d: Likewise.
+	* ld-mmix/locdo-1.d: Likewise.
+	* ld-mmix/loct-1.d: Likewise.
+	* ld-mmix/locto-1.d: Likewise.
+	* ld-mmix/start-1.d: Likewise.
+	* ld-mmix/undef-3.d: Likewise.
+	* ld-powerpc/tlsexe32.r: Likewise.
+	* ld-powerpc/tlsso32.r: Likewise.
+	* ld-s390/tlsbin.rd: Likewise.
+	* ld-s390/tlspic.rd: Likewise.
+	* ld-sparc/tlssunbin32.rd: Likewise.
+	* ld-sparc/tlssunbin64.rd: Likewise.
+	* ld-sparc/tlssunnopic32.rd: Likewise.
+	* ld-sparc/tlssunnopic64.rd: Likewise.
+	* ld-sparc/tlssunpic32.rd: Likewise.
+	* ld-sparc/tlssunpic64.rd: Likewise.
+	* ld-x86-64/tlsbin.rd: Likewise.
+	* ld-x86-64/tlsbindesc.rd: Likewise.
+	* ld-x86-64/tlsdesc.rd: Likewise.
+	* ld-x86-64/tlsgdesc.rd: Likewise.
+	* ld-x86-64/tlspic.rd: Likewise.
+
+2006-05-31  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/binutils.exp: Make it Linux only.
+	(strip_test): Renamed to binutils_test. Check for unsupported
+	options.
+	Add more tests.
+
+	* ld-elf/commonpage1.d: Make it Linux only.
+	* ld-elf/maxpage1.d: Likewise.
+
+	* ld-elf/maxpage1.s: Add main, start and __start.
+
+	* ld-elf/maxpage2.d: New file.
+	* ld-elf/tbss1.s: Likewise.
+	* ld-elf/tbss2.s: Likewise.
+	* ld-elf/tdata1.s: Likewise.
+	* ld-elf/tdata2.s: Likewise.
+
+2006-05-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/binutils.exp: New file.
+	* ld-elf/commonpage1.d: Likewise.
+	* ld-elf/maxpage1.d: Likewise.
+	* ld-elf/maxpage1.s: Likewise.
+
+2006-05-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-x86-64/tlsbin.dd: Updated for 2MB maximum page size.
+	* ld-x86-64/tlsbin.rd: Likewise.
+	* ld-x86-64/tlsbin.sd: Likewise.
+	* ld-x86-64/tlsbin.td: Likewise.
+	* ld-x86-64/tlsbindesc.dd: Likewise.
+	* ld-x86-64/tlsbindesc.rd: Likewise.
+	* ld-x86-64/tlsbindesc.sd: Likewise.
+	* ld-x86-64/tlsbindesc.td: Likewise.
+	* ld-x86-64/tlsdesc.dd: Likewise.
+	* ld-x86-64/tlsdesc.pd: Likewise.
+	* ld-x86-64/tlsdesc.rd: Likewise.
+	* ld-x86-64/tlsdesc.sd: Likewise.
+	* ld-x86-64/tlsdesc.td: Likewise.
+	* ld-x86-64/tlsgdesc.dd: Likewise.
+	* ld-x86-64/tlspic.dd: Likewise.
+	* ld-x86-64/tlspic.rd: Likewise.
+	* ld-x86-64/tlspic.sd: Likewise.
+	* ld-x86-64/tlspic.td: Likewise.
+
+2006-05-24  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-app-abs32.d: Update expected output.
+	* ld-arm/arm-app.d: Ditto.
+	* ld-arm/arm-lib-plt32.d: Ditto.
+	* ld-arm/arm-lib.d: Ditto.
+	* ld-arm/mixed-app-v5.d: Ditto.
+	* ld-arm/mixed-app.d: Ditto.
+	* ld-arm/mixed-lib.d: Ditto.
+
+2006-05-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/2655
+	PR ld/2657
+	* ld-elf/eh1.d: New file.
+	* ld-elf/eh1.s: Likewise.
+	* ld-elf/eh1a.s: Likewise.
+	* ld-elf/eh2.d: Likewise.
+	* ld-elf/eh2a.s: Likewise.
+	* ld-elf/eh3.d: Likewise.
+	* ld-elf/eh3.s: Likewise.
+	* ld-elf/eh3a.s: Likewise.
+
+2006-05-22  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-mips-elf/textrel-1.d: Relax some patterns.
+
+2006-05-22  Nick Clifton  <nickc@redhat.com>
+
+	* ld-elf/start.s (start): Add this symbol for SH targets.
+	(main): Add this symbol for HPPA targets.
+
+2006-05-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/empty-orphan.d: Update again.
+
+	* ld-scripts/empty-orphan.t: Discard .reginfo.
+	* ld-scripts/empty-orphan.d: Update.
+
+2006-05-17  Thiemo Seufer  <ths@mips.com>
+
+	* ld-elfweak/size2.d, ld-elfweak/size2a.s, ld-elfweak/size2b.s:
+	Add __start as entry symbol.
+
+2006-05-16  Thiemo Seufer  <ths@mips.com>
+
+	* ld-elf/orphan.ld: Add placement for MIPS .reginfo section.
+
+2006-05-15  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-be8.d: New test.
+	* ld-arm/arm-be8.s: New test.
+	* ld-arm/arm-elf.exp: Add arm-be8.
+
+2006-05-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/stab.d: Skip ia64-*-*.
+
+2006-05-11  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-elf.exp: Add arm-movwt.
+	* ld-arm/arm-movwt.d: New test.
+	* ld-arm/arm-movwt.s: New test.
+	* ld-arm/arm.ld: Add .far.
+
+2006-05-11  Mike Bland  <mbland@google.com>
+
+	* ld-elf/stab.d: New.
+
+2006-05-10  Thiemo Seufer  <ths@debian.org>
+
+	* ld-elf/sec64k.exp: Extend for MIPS ELF.
+
+2006-05-05  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexetoc.r: Update for correction to tls optimization.
+	* ld-powerpc/tlsexetoc.g: Likewise.
+
+2006-05-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-cdtest/cdtest-foo.cc (Foo::Foo): Add const to char *.
+	* ld-cdtest/cdtest-foo.h (Foo::Foo): Likewise.
+	* ld-srec/sr3.cc (Foo::Foo): Likewise.
+
+2006-05-02  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-elf.exp: Add thumb-rel32.
+	* ld-arm/thumb-rel32.d: New test.
+	* ld-arm/thumb-rel32.s: New test.
+
+2006-04-29  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elfvers/vers.exp: Xfail vers7a, vers7, vers23a, vers23b,
+	vers23c, vers23d, vers23, vers25a, vers25b1, vers25b2, vers27a,
+	vers27b, vers27c1, vers27c2, vers27d4 and vers27d5 if PIC is
+	required.
+
+2006-04-25  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-alpha/tlsbin.rd: Updated for readelf change.
+	* ld-alpha/tlsbinr.rd: Likewise.
+	* ld-alpha/tlspic.rd: Likewise.
+
+2006-04-05  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-sparc/vxworks1.dd, ld-sparc/vxworks1.ld, ld-sparc/vxworks1-lib.dd,
+	* ld-sparc/vxworks1-lib.nd, ld-sparc/vxworks1-lib.rd,
+	* ld-sparc/vxworks1-lib.s, ld-sparc/vxworks1.rd, ld-sparc/vxworks1.s,
+	* ld-sparc/vxworks1-static.d, ld-sparc/vxworks2.s,
+	* ld-sparc/vxworks2.sd, ld-sparc/vxworks2-static.sd: New tests.
+	* ld-sparc/sparc.exp: Run them.
+
+2006-04-05  Ben Elliston  <bje@au.ibm.com>
+
+	* lib/ld-lib.exp: Comment cleanups.
+
+2006-03-27  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/tls-hidden3a.s, ld-mips-elf/tls-hidden3b.s,
+	* ld-mips-elf/tls-hidden3.d, ld-mips-elf/tls-hidden3.got,
+	* ld-mips-elf/tls-hidden3.ld, ld-mips-elf/tls-hidden3.r,
+	* ld-mips-elf/tls-hidden4a.s, ld-mips-elf/tls-hidden4b.s,
+	* ld-mips-elf/tls-hidden4.got, ld-mips-elf/tls-hidden4.r: New tests.
+	* ld-mips-elf/mips-elf.exp: Run them.
+
+2006-03-25  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-m68k/merge-error-1a.s, ld-m68k/merge-error-1b.s,
+	* ld-m68k/merge-error-1a.d, ld-m68k/merge-error-1b.d,
+	* ld-m68k/merge-error-1c.d, ld-m68k/merge-error-1d.d,
+	* ld-m68k/merge-error-1e.d, ld-m68k/merge-ok-1a.d,
+	* ld-m68k/merge-ok-1b.d: New tests.
+	* ld-m68k/m68k.exp: Run them.
+
+2006-03-22  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips/vxworks1.dd, ld-mips/vxworks1.ld, ld-mips/vxworks1-lib.dd,
+	* ld-mips/vxworks1-lib.nd, ld-mips/vxworks1-lib.rd,
+	* ld-mips/vxworks1-lib.s, ld-mips/vxworks1.rd, ld-mips/vxworks1.s,
+	* ld-mips/vxworks1-static.d, ld-mips/vxworks2.s, ld-mips/vxworks2.sd,
+	* ld-mips/vxworks2-static.sd: New tests.
+	* ld-mips/mips-elf.exp: Run them.
+
+2006-03-17  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-powerpc/tls32.s: Verify that +32768 @plt addend is
+	discarded.
+
+2006-03-14  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips/emit-relocs-1a.s, ld-mips/emit-relocs-1b.s,
+	* ld-mips/emit-relocs-1.ld, ld-mips/emit-relocs-1.d: New test.
+	* ld-mips/mips-elf.exp: Run it.
+
+2006-03-07  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-arm/vxworks1.dd, ld-arm/vxworks1.ld, ld-arm/vxworks1-lib.dd,
+	* ld-arm/vxworks1-lib.nd, ld-arm/vxworks1-lib.rd,
+	* ld-arm/vxworks1-lib.s, ld-arm/vxworks1.rd, ld-arm/vxworks1.s,
+	* ld-arm/vxworks1-static.d, ld-arm/vxworks2.s, ld-arm/vxworks2.sd,
+	* ld-arm/vxworks2-static.sd: New tests.
+	* ld-arm/arm-elf.exp: Run them.
+
+2006-03-06  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-m68k: New tests.
+
+2006-03-03  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-i386/vxworks1-static.d, ld-i386/vxworks2.s,
+	* ld-i386/vxworks2.sd, ld-i386/vxworks2-static.sd: New tests.
+	* ld-i386/i386.exp: Run them.
+	* ld-powerpc/vxworks1-static.d, ld-powerpc/vxworks2.s,
+	* ld-powerpc/vxworks2.sd, ld-powerpc/vxworks2-static.sd: New tests.
+	* ld-powerpc/powerpc.exp: Run them.
+
+2006-03-02  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-powerpc/vxworks1.ld: Use a page alignment of 0x10000.
+	* ld-powerpc/vxworks1.dd: Update accordingly.
+	* ld-powerpc/vxworks1-lib.nd: Likewise.
+	* ld-powerpc/vxworks1-lib.rd: Likewise.
+	* ld-powerpc/vxworks1.rd: Likewise.
+
+2006-03-02  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-i386/vxworks1.ld (.data): New section.
+	* ld-i386/vxworks1-lib.s: Add a pointer to a local symbol.
+	* ld-i386/vxworks1-lib.rd: Test for the associated reloc.
+	* ld-powerpc/vxworks1.ld (.data): New section.
+	* ld-powerpc/vxworks1-lib.s: Add a pointer to a local symbol.
+	* ld-powerpc/vxworks1-lib.rd: Test for the associated reloc.
+
+2006-03-02  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-i386/ld-i386/vxworks1-lib.nd: New test.
+	* ld-i386/i386.exp: Run it.
+	* ld-powerpc/ld-powerpc/vxworks1-lib.nd: New test.
+	* ld-powerpc/powerc.exp: Run it.
+
+2006-03-02  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-i386/vxworks1.ld: Use bigger alignments.  Make sure .bss isn't
+	placed as an orphan.
+	* ld-i386/vxworks1-lib.dd, ld-i386/vxworks1.dd,
+	* ld-i386/vxworks1.rd: Update accordingly.
+	* ld-i386/vxworks1-lib.rd: Likewise.  Remove symbol indexes.
+
+2006-03-02  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-powerpc/vxworks1-lib.s, ld-powerpc/vxworks1-lib.dd,
+	* ld-powerpc/vxworks1-lib.rd, ld-powerpc/vxworks1.s,
+	* ld-powerpc/vxworks1.dd, ld-powerpc/vxworks1.rd,
+	* ld-powerpc/vxworks1.ld, ld-powerpc/vxworks1.sd: New test.
+	* ld-powerpc/powerpc.exp: Run it.
+
+2006-02-28  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-i386/vxworks1-lib.s, ld-i386/vxworks1-lib.dd,
+	* ld-i386/vxworks1-lib.rd, ld-i386/vxworks1.s, ld-i386/vxworks1.dd,
+	* ld-i386/vxworks1.rd, ld-i386/vxworks1.ld: New test.
+	* ld-i386/i386.exp: Run it.
+
+2006-02-28  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-i386/emit-relocs.s, ld-i386/emit-relocs.d: New test.
+	* ld-i386/i386.exp: Run it.
+
+2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-pie/weakundef-data.c: Fix the typo.
+
+2006-02-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-pie/pie.c: New file.
+
+	* ld-pie/pie.exp: Check if compiler supports -pie.
+
+2006-02-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/2218
+	* ld-pie/pie.exp: Add the weak undefined data test.
+
+	* ld-pie/weakundef-data.c: New file.
+
+2006-02-17  Shrirang Khisti  <shrirangk@kpitcummins.com>
+	    Anil Paranjape   <anilp1@kpitcummins.com>
+	    Shilin Shakti    <shilins@kpitcummins.com>
+
+	* ld-xc16x: New directory.
+	* ld-xc16x/absrel.d: New file.
+	* ld-xc16x/absrel.s: New file.
+	* ld-xc16x/offset.d: New file.
+	* ld-xc16x/offset.s: New file.
+	* ld-xc16x/pcreloc.d: New file.
+	* ld-xc16x/pcreloc.s: New file.
+	* ld-xc16x/xc16x.exp: New file.
+
+2006-02-07  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-elf.exp: Add thumb-entry test.
+	* ld-arm/thumb-entry.d: New test.
+	* ld-arm/thumb-entry.s: New test.
+
+2006-02-04  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/tls-hidden2a.s, ld-mips-elf/tls-hidden2b.s,
+	* ld/testsuite/ld-mips-elf/tls-hidden2.d,
+	* ld/testsuite/ld-mips-elf/tls-hidden2-got.d: New test.
+	* ld-mips-elf/mips-elf.exp: Run it.
+
+2006-02-04  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/rel32-n32.d: Adjust for changes in linker behaviour.
+	* ld-mips-elf/rel32-o32.d: Likewise.
+	* ld-mips-elf/rel64.d: Likewise.
+	* ld-mips-elf/tls-multi-got-1.got: Likewise.
+	* ld-mips-elf/tls-multi-got-1.r: Likewise.
+	* ld-mips-elf/tlsdyn-o32-1.d: Likewise.
+	* ld-mips-elf/tlsdyn-o32-1.got: Likewise.
+	* ld-mips-elf/tlsdyn-o32-2.d: Likewise.
+	* ld-mips-elf/tlsdyn-o32-2.got: Likewise.
+	* ld-mips-elf/tlsdyn-o32-3.d: Likewise.
+	* ld-mips-elf/tlsdyn-o32-3.got: Likewise.
+	* ld-mips-elf/tlsdyn-o32.d: Likewise.
+	* ld-mips-elf/tlsdyn-o32.got: Likewise.
+	* ld-mips-elf/tlslib-o32-hidden.got: Likewise.
+	* ld-mips-elf/tlslib-o32-ver.got: Likewise.
+	* ld-mips-elf/tlslib-o32.got: Likewise.
+
+2006-02-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-i386/tlsbin.rd: Undo the last change.
+	* ld-i386/tlsbindesc.rd: Likewise.
+	* ld-i386/tlsdesc.rd: Likewise.
+	* ld-i386/tlsnopic.rd: Likewise.
+	* ld-i386/tlspic.rd: Likewise.
+	* ld-powerpc/tlsexe.r: Likewise.
+	* ld-powerpc/tlsexe32.r: Likewise.
+	* ld-powerpc/tlsexetoc.r: Likewise.
+	* ld-powerpc/tlsso.r: Likewise.
+	* ld-powerpc/tlsso32.r: Likewise.
+	* ld-powerpc/tlstocso.r: Likewise.
+	* ld-s390/tlsbin.rd: Likewise.
+	* ld-s390/tlsbin_64.rd: Likewise.
+	* ld-s390/tlspic.rd: Likewise.
+	* ld-s390/tlspic_64.rd: Likewise.
+	* ld-sh/tlsbin-2.d: Likewise.
+	* ld-sh/tlspic-2.d: Likewise.
+	* ld-x86-64/tlsbin.rd: Likewise.
+	* ld-x86-64/tlsbindesc.rd: Likewise.
+	* ld-x86-64/tlsdesc.rd: Likewise.
+	* ld-x86-64/tlspic.rd: Likewise.
+
+2006-02-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-i386/tlsbin.rd: Update for changed segment map.
+	* ld-i386/tlsbindesc.rd: Likewise.
+	* ld-i386/tlsdesc.rd: Likewise.
+	* ld-i386/tlsnopic.rd: Likewise.
+	* ld-i386/tlspic.rd: Likewise.
+	* ld-powerpc/tlsexe.r: Likewise.
+	* ld-powerpc/tlsexe32.r: Likewise.
+	* ld-powerpc/tlsexetoc.r: Likewise.
+	* ld-powerpc/tlsso.r: Likewise.
+	* ld-powerpc/tlsso32.r: Likewise.
+	* ld-powerpc/tlstocso.r: Likewise.
+	* ld-s390/tlsbin.rd: Likewise.
+	* ld-s390/tlsbin_64.rd: Likewise.
+	* ld-s390/tlspic.rd: Likewise.
+	* ld-s390/tlspic_64.rd: Likewise.
+	* ld-sh/tlsbin-2.d: Likewise.
+	* ld-sh/tlspic-2.d: Likewise.
+	* ld-x86-64/tlsbin.rd: Likewise.
+	* ld-x86-64/tlsbindesc.rd: Likewise.
+	* ld-x86-64/tlsdesc.rd: Likewise.
+	* ld-x86-64/tlspic.rd: Likewise.
+
+2006-01-31  Eric Botcazou  <ebotcazou@libertysurf.fr>
+
+	* ld-sparc/sparc.exp: Do not run 64-bit tests on Solaris 2.5.1
+	and Solaris 2.6.
+
+2006-01-27  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/2218
+	* ld-pie/pie.exp: New file.
+	* ld-pie/weakundef.c: Likewise.
+	* ld-pie/weakundef.out: Likewise.
+
+	* lib/ld-lib.exp (run_ld_link_exec_tests): Fix nesting. Support
+	building PIE and shared library.
+
+2006-01-18  Alexandre Oliva  <aoliva@redhat.com>
+
+	Introduce TLS descriptors for i386 and x86_64.
+	* ld-i386/i386.exp: Run on x86_64-*-linux* and amd64-*-linux*.
+	Add new tests.
+	* ld-i386/pcrel16.d: Add -melf_i386.
+	* ld-i386/pcrel8.d: Likewise.
+	* ld-i386/tlsbindesc.dd: New.
+	* ld-i386/tlsbindesc.rd: New.
+	* ld-i386/tlsbindesc.s: New.
+	* ld-i386/tlsbindesc.sd: New.
+	* ld-i386/tlsbindesc.td: New.
+	* ld-i386/tlsdesc.dd: New.
+	* ld-i386/tlsdesc.rd: New.
+	* ld-i386/tlsdesc.s: New.
+	* ld-i386/tlsdesc.sd: New.
+	* ld-i386/tlsdesc.td: New.
+	* ld-i386/tlsgdesc.dd: New.
+	* ld-i386/tlsgdesc.rd: New.
+	* ld-i386/tlsgdesc.s: New.
+	* ld-x86-64/x86-64.exp: Run new tests.
+	* ld-x86-64/tlsbindesc.dd: New.
+	* ld-x86-64/tlsbindesc.rd: New.
+	* ld-x86-64/tlsbindesc.s: New.
+	* ld-x86-64/tlsbindesc.sd: New.
+	* ld-x86-64/tlsbindesc.td: New.
+	* ld-x86-64/tlsdesc.dd: New.
+	* ld-x86-64/tlsdesc.pd: New.
+	* ld-x86-64/tlsdesc.rd: New.
+	* ld-x86-64/tlsdesc.s: New.
+	* ld-x86-64/tlsdesc.sd: New.
+	* ld-x86-64/tlsdesc.td: New.
+	* ld-x86-64/tlsgdesc.dd: New.
+	* ld-x86-64/tlsgdesc.rd: New.
+	* ld-x86-64/tlsgdesc.s: New.
+
+2006-01-03  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/sec-1.d: Adjust for section order changes.
+
+For older changes see ChangeLog-2005
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.19/ld/testsuite/ChangeLog-2007 b/binutils-2.19/ld/testsuite/ChangeLog-2007
new file mode 100644
index 0000000..3f2fc96
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ChangeLog-2007
@@ -0,0 +1,1206 @@
+2007-12-31  Nick Clifton  <nickc@redhat.com>
+
+	* ld-elf/flags1.d: Add xfails for ports for which the test will
+	not work.
+
+2007-12-31  Nick Clifton  <nickc@redhat.com>
+
+	* ld-mn10300/i143317.s: New test - checks linker relaxation when
+	the symbols are in a merged section.
+	* ld-mn10300/i143317.d: Expected disassembly.
+	* ld-mn10300/i143317.t: Linker map.
+	* ld-mn10300/mn10300.exp (mn10300_tests): Add the i143317 test.
+
+2007-12-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/5488
+	* ld-elf/note-2.d: New.
+	* ld-elf/note-2.s: Likewise.
+	* ld-elf/note-2.t: Likewise.
+
+2007-12-20  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-elf/seg.d: Restrict to linux and vxworks.
+
+2007-12-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/seg.d: Adjusted for 64bit targets.
+
+2007-12-19  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-elf/seg.t: New.
+	* ld-elf/seg.d: New.
+	* ld-elf/seg.s: New.
+
+2007-12-15  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/rgn-over.exp: Add --no-overlays for spu.
+
+2007-11-28  Nick Clifton  <nickc@redhat.com>
+
+	* ld-mn10300/i135409-5.s: New test case.  Check for relaxation to
+	a 16-bit backward jump instruction.
+	* ld-mn10300/i135409-5.t: Linker script for the new test.
+	* ld-mn10300/i135409-5.d: Expected disassembly of new test.
+	* ld-mn10300/mn10300.exp: Run the new test.
+
+2007-11-21  Nick Clifton  <nickc@redhat.com>
+
+	* ld-mn10300/i135409-4.s: New test case.  Check for relaxation to
+	a 16-bit jump instruction.
+	* ld-mn10300/i135409-4.t: Linker script for the new test.
+	* ld-mn10300/i135409-4.d: Expected disassembly of new test.
+	* ld-mn10300/mn10300.exp: Run the new test.
+
+2007-11-20  Nick Clifton  <nickc@redhat.com>
+
+	* lib/ld-lib.exp (check_gc_sections_available): New proc, based
+	on the version in gcc/testsuite/lib/target-supports.exp.
+	* ld-elf/elf.exp: Use check_gc_sections_available.
+
+2007-11-20  Tristan Gingold  <gingold@adacore.com>
+
+	* ld-elf/tls_gc.s: New test.
+	* ld-elf/elf.exp: Add tls_gc test.
+
+2007-11-17  Thiemo Seufer  <ths@mips.com>
+
+	* ld-mips-elf/attr-gnu-4-14.d, ld-mips-elf/attr-gnu-4-41.d:
+	Adjust warning message for -mfp64 flag.
+	* ld-mips-elf/attr-gnu-4-5.s, ld-mips-elf/attr-gnu-4-04.d,
+	ld-mips-elf/attr-gnu-4-51.d, ld-mips-elf/attr-gnu-4-05.d,
+	ld-mips-elf/attr-gnu-4-15.d, ld-mips-elf/attr-gnu-4-24.d,
+	ld-mips-elf/attr-gnu-4-25.d, ld-mips-elf/attr-gnu-4-34.d,
+	ld-mips-elf/attr-gnu-4-35.d, ld-mips-elf/attr-gnu-4-42.d,
+	ld-mips-elf/attr-gnu-4-43.d, ld-mips-elf/attr-gnu-4-44.d,
+	ld-mips-elf/attr-gnu-4-45.d, ld-mips-elf/attr-gnu-4-40.d,
+	ld-mips-elf/attr-gnu-4-14.d: New testcases files.
+	* ld-mips-elf/mips-elf.exp: Run new testcases.
+
+2007-11-16  Nick Clifton  <nickc@redhat.com>
+
+	* ld-mn10300/mn10300.exp: Fix the start address of the .bss
+	section for the i1127740.s test.
+
+2007-11-14  Richard Sandiford  <richard@codesourcery.com>
+            Joseph Myers  <joseph@codesourcery.com>
+
+	* ld-mips-elf/got-page-1.d, ld-mips-elf/got-page-1.s,
+	* ld-mips-elf/got-page-2.d, ld-mips-elf/got-page-2.s,
+	* ld-mips-elf/got-page-3.d, ld-mips-elf/got-page-3a.s,
+	* ld-mips-elf/got-page-3b.s, ld-mips-elf/got-page-3c.s,
+	* ld-mips-elf/got-page-1.ld: New tests.
+	* ld-mips-elf/mips-elf.exp: Run them.
+	* ld-mips-elf/multi-got-1.d, ld-mips-elf/multi-got-no-shared.d,
+	* ld-mips-elf/tls-hidden2-got.d, ld-mips-elf/tls-hidden2.d,
+	* ld-mips-elf/tls-hidden3.d, ld-mips-elf/tls-hidden3.got,
+	* ld-mips-elf/tls-hidden3.r, ld-mips-elf/tls-hidden4.got,
+	* ld-mips-elf/tls-hidden4.r, ld-mips-elf/tls-multi-got-1.d,
+	* ld-mips-elf/tls-multi-got-1.got, ld-mips-elf/tls-multi-got-1.r,
+	* ld-mips-elf/tlsbin-o32.d, ld-mips-elf/tlsbin-o32.got,
+	* ld-mips-elf/tlsdyn-o32-1.d, ld-mips-elf/tlsdyn-o32-1.got,
+	* ld-mips-elf/tlsdyn-o32-2.d, ld-mips-elf/tlsdyn-o32-2.got,
+	* ld-mips-elf/tlsdyn-o32-3.d, ld-mips-elf/tlsdyn-o32-3.got,
+	* ld-mips-elf/tlsdyn-o32.d, ld-mips-elf/tlsdyn-o32.got,
+	* ld-mips-elf/tlslib-o32-hidden.got, ld-mips-elf/tlslib-o32-ver.got,
+	* ld-mips-elf/tlslib-o32.d, ld-mips-elf/tlslib-o32.got: Update for
+	GOT allocation changes.
+
+2007-11-14  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-elf/flags1.d: Generalize regexp for section size.
+
+2007-11-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/5233
+	* ld-elf/flags1.d: New.
+	* ld-elf/flags1.ld: Likewise.
+	* ld-elf/flags1.s: Likewise.
+
+2007-11-13  Nick Clifton  <nickc@redhat.com>
+
+	* ld-mn10300/i127740.s: New test: Checks relaxation and alignment.
+	* ld-mn10300/i127740.d: New file: Expected disassembly.
+	* ld-mn10300/i135409-3.s: New test: Check symbols inside a relaxed region.
+	* ld-mn10300/i135409-3.d: New file: Expected disassembly.
+	* ld-mn10300/mn10300.exp: Run new tests.
+
+2007-11-08  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-vxworks/tls-2.d: New.
+	* ld-vxworks/tls-2.s: New.
+
+2007-11-07  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-vxworks/tls-1.d: New.
+	* ld-vxworks/tls-1.s: New.
+
+2007-11-06  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsso.d: Update for changed got alloc order.
+	* ld-powerpc/tlsso.r: Likewise.
+
+	* ld-powerpc/tlsso32.d: Update for changed got alloc order.
+
+2007-11-05  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/merge3.d, ld-elf/merge3.s: Delete.
+
+2007-11-05  Danny Smith  <dannysmith@users.sourceforge.net>
+
+	* ld-scripts/align.exp: Enable for PECOFF.
+	* ld-scripts/alignof.exp: Likewise.
+
+2007-11-01  Joseph Myers  <joseph@codesourcery.com>
+
+	* ld-elf/merge3.d, ld-elf/merge3.s: New.
+
+2007-10-30  Nick Clifton  <nickc@redhat.com>
+
+	* ld-mn10300/mn10300.exp: Run new tests.  Skip i126256 test if
+	a compiler is not available.
+	* ld-mn10300/i112045-3.s: New test.
+	* ld-mn10300/i112045-3.d: Expected disassembly.
+	* ld-mn10300/i135409.s: Rename to i135409-1.s.
+	* ld-mn10300/i135409.d: Rename to i135409-1.d
+	* ld-mn10300/i135409-2.s: New test.
+	* ld-mn10300/i135409-2.d: Expected symbol table.
+        * ld-mn10300/i36434.d: Adjust expected disassembly.
+
+2007-10-26  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/rgn-over1.d: Accept extra LOAD at end of map file.
+	* ld-scripts/rgn-over2.d: Likewise.
+	* ld-scripts/rgn-over3.d: Likewise.
+	* ld-scripts/rgn-over4.d: Likewise.
+	* ld-scripts/rgn-over5.d: Likewise.
+	* ld-scripts/rgn-over6.d: Likewise.
+	* ld-scripts/rgn-over7.d: Likewise.
+
+2007-10-25  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-powerpc/attr-gnu-8-1.s, ld-powerpc/attr-gnu-8-11.d,
+	ld-powerpc/attr-gnu-8-2.s, ld-powerpc/attr-gnu-8-23.d,
+	ld-powerpc/attr-gnu-8-3.s, ld-powerpc/attr-gnu-8-31.d: New.
+	* ld-powerpc/powerpc.exp: Run new tests.
+
+2007-10-19  Nick Clifton  <nickc@redhat.com>
+
+	* ld-mn10300: New test directory.
+	* ld-mn10300/mn10300.exp: Run the new tests.
+	* ld-mn10300/i112045-1.s: Linker relaxation test.
+	* ld-mn10300/i112045-1.d: Expected disassembly.
+	* ld-mn10300/i112045-2.s: Linker relaxation test.
+	* ld-mn10300/i112045-2.d: Expected disassembly.
+	* ld-mn10300/i126256-1.c: Test source.
+	* ld-mn10300/i126256-2.c: Test source.
+	* ld-mn10300/i135409.s: Linker relaxation test.
+	* ld-mn10300/i135409.d: Expected symbol table contents.
+	* ld-mn10300/i136434.s: Linker string section merge test.
+	* ld-mn10300/i136434.d: Expected disassembly.
+	* ld-mn10300/i136434-2.s: Test source file.
+
+2007-10-17  Zack Weinberg  <zack@codesourcery.com>
+	    Daniel Jacobowitz  <dan@codesourcery.com>
+	    Mark Shinwell  <shinwell@codesourcery.com>
+	    Joseph Myers  <joseph@codesourcery.com>
+
+	* ld-scripts/rgn-over.exp: New driver.
+	* ld-scripts/rgn-over.s: New file.
+	* ld-scripts/rgn-over1.d, ld-scripts/rgn-over1.t,
+	ld-scripts/rgn-over2.d, ld-scripts/rgn-over2.t,
+	ld-scripts/rgn-over3.d, ld-scripts/rgn-over3.t,
+	ld-scripts/rgn-over4.d, ld-scripts/rgn-over4.t,
+	ld-scripts/rgn-over5.d, ld-scripts/rgn-over5.t,
+	ld-scripts/rgn-over6.d, ld-scripts/rgn-over6.t,
+	ld-scripts/rgn-over7.d, ld-scripts/rgn-over7.t:
+	New test cases.
+
+2007-10-16  Nick Clifton  <nickc@redhat.com>
+
+	* ld-elfcomm/elfcomm.exp: Add tests of STT_COMMON symbol
+	generation.
+
+2007-10-12  Joseph Myers  <joseph@codesourcery.com>
+
+	* ld-mips-elf/multi-got-hidden-1.d,
+	ld-mips-elf/multi-got-hidden-1.s,
+	ld-mips-elf/multi-got-hidden-2.d,
+	ld-mips-elf/multi-got-hidden-2.s: New.
+	* ld-mips-elf/mips-elf.exp: Run multi-got-hidden tests.
+
+2007-10-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-srec/srec.exp: Define __stack_chk_fail sym.
+
+2007-10-09  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/4476
+	* ld-elf/hash.d: Check "-s -D" for readelf.
+
+2007-10-02  Ralf Habecker  <ralf.habacker@freenet.de>
+
+	PR linker/4844
+	* ld-auto-import/auto-import.exp: Extend test to include running
+	the application and checking for some output.
+	* ld-auto-import/client.c (struct TEST): Include a variable field
+	with an offset.
+	(const_xyz): A const version of the xyz structure used to test the
+	initialization of constant data.
+
+2007-09-30  Mike Frysinger  <vapier@gentoo.org>
+
+	* ld-selective/selective.exp: Set $compiler based on $testtype and
+	use that instead of $CC.
+
+2007-09-29  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-selective/sel-dump.exp: Add am33, m88k, mep to xfails.
+	* ld-selective/selective.exp: Don't run for same target list
+	we xfail sel-dump.
+
+2007-09-29  Mike Frysinger  <vapier@gentoo.org>
+
+	* ld-alpha/tlsbin.rd: Use [0-9]+ to match section header count and
+	0x[0-9a-f]+ to match section header offset.  Match section indexes
+	with \[[ 0-9]+\].  Use [0-9]+ to match program header count and
+	0x[0-9a-f]+ to match program header offset.  Match .dynsym and
+	.symtab entry counts with [0-9]+.
+	* ld-alpha/tlsbinr.rd: Likewise.
+	* ld-alpha/tlspic.rd: Likewise.
+	* ld-i386/tlsbin.rd: Likewise.
+	* ld-i386/tlsbindesc.rd: Likewise.
+	* ld-i386/tlsdesc.rd: Likewise.
+	* ld-i386/tlsgdesc.rd: Likewise.
+	* ld-i386/tlsnopic.rd: Likewise.
+	* ld-i386/tlspic.rd: Likewise.
+	* ld-ia64/tlsbin.rd: Likewise.
+	* ld-ia64/tlspic.rd: Likewise.
+	* ld-powerpc/tlsexe.r: Likewise.
+	* ld-powerpc/tlsexe32.r: Likewise.
+	* ld-powerpc/tlsexetoc.r: Likewise.
+	* ld-powerpc/tlsso.r: Likewise.
+	* ld-powerpc/tlsso32.r: Likewise.
+	* ld-powerpc/tlstocso.r: Likewise.
+	* ld-s390/tlsbin.rd: Likewise.
+	* ld-s390/tlsbin_64.rd: Likewise.
+	* ld-s390/tlspic.rd: Likewise.
+	* ld-s390/tlspic_64.rd: Likewise.
+	* ld-sparc/tlssunbin32.rd: Likewise.
+	* ld-sparc/tlssunbin64.rd: Likewise.
+	* ld-sparc/tlssunnopic32.rd: Likewise.
+	* ld-sparc/tlssunnopic64.rd: Likewise.
+	* ld-sparc/tlssunpic32.rd: Likewise.
+	* ld-sparc/tlssunpic64.rd: Likewise.
+	* ld-x86-64/tlsbin.rd: Likewise.
+	* ld-x86-64/tlsbindesc.rd: Likewise.
+	* ld-x86-64/tlsdesc.rd: Likewise.
+	* ld-x86-64/tlsgdesc.rd: Likewise.
+	* ld-x86-64/tlspic.rd: Likewise.
+
+2007-09-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-spu/ovl.d: Adjust for stub relocs.
+	* ld-spu/ovl2.d: Likewise.
+
+2007-09-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 658
+	* ld-i386/tlsbin.dd: Updated.
+	* ld-i386/tlsld1.dd: Likewise.
+
+2007-09-19  Nick Clifton  <nickc@redhat.com>
+
+	* ld-scripts/crossref.exp: Compile test source with -mtiny=0 in
+	order to prevent the use of the small data area.
+
+2007-09-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/3281
+	PR binutils/5037
+	* ld-elf/binutils.exp: Update "-z relro" tests to use relro1.s.
+	Add "-z relro" tests with relro2.s.  Add "-z relro" tests with
+	TLS for objcopy.
+
+	* ld-elf/relro1.s: New file.
+	* ld-elf/relro2.s: Likewise.
+
+2007-09-04  Mike Frysinger  <vapier@gentoo.org>
+
+	* lib/ld-lib.exp (default_ld_compile): Pull in global CXXFLAGS and
+	add it to $flags when $ccexe matches *++*.
+	(run_ld_link_exec_tests): Pull in global CXXFLAGS and execute CXX
+	with CXXFLAGS when $lang matches c++.
+	(run_cc_link_tests): Likewise.
+
+2007-09-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/4986
+	* ld-ia64/line.exp: New.
+	* ld-ia64/undefined.s: Likewise.
+
+	* ld-x86-64/line.exp: Don't check CC.
+
+2007-08-31  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/4986
+	* ld-x86-64/line.exp: New
+	* ld-x86-64/undefined.s: Likewise.
+
+2007-08-31  Tristan Gingold  <gingold@adacore.com>
+
+	* ld-script/map-address.t: Add a test for testing DEFINED in map
+	output.
+	* ld-script/map-address.d: Update expected output.
+
+2007-08-28  Mark Shinwell  <shinwell@codesourcery.com>
+	    Joseph Myers  <joseph@codesourcery.com>
+
+	* ld-elfcomm/elfcomm.exp: Use run_host_cmd.  Only check "which
+	$CC" if host is local.
+	* ld-checks/checks.exp: Use run_host_cmd.
+	* ld-elf/exclude.exp: Likewise.
+	* ld-elf/elf.exp: Download merge.ld if host is remote.
+	* ld-elf/binutils.exp (binutils_test): Use remote_exec.
+	* ld-elf/tls_common.exp: Use run_host_cmd.
+	* lib/ld-lib.exp (ld_version): Only check "which $ld" if host is
+	local.  Use remote_exec.
+	(run_host_cmd): New.
+	(run_host_cmd_yesno): New.
+	(default_ld_relocate): Use run_host_cmd_yesno.
+	(default_ld_link): Likewise.
+	(default_ld_simple_link): Use run_host_cmd.
+	(default_ld_compile): Only check "which $ccprog" if host is local.
+	Use remote_file and remote_exec.
+	(default_ld_assemble): Only check "which $as" if host is local.
+	Use run_host_cmd.
+	(default_ld_nm): Use remote_exec, remote_upload and remote_file.
+	(run_dump_test): Use remote_exec, remote_upload and remote_file.
+	Only check "which $binary" if host is local.
+	(run_ld_link_tests): Use remote_exec, remote_upload and
+	remote_file.
+	* ld-selective/selective.exp: Only check "which $CXX" if host is
+	local.  Use remote_exec.
+	* ld-scripts/phdrs.exp: Only check "which $objdump" if host is
+	local.  Use run_host_cmd.
+	* ld-scripts/phdrs2.exp: Likewise.
+	* ld-scripts/weak.exp: Likewise.
+	* ld-undefined/weak-undef.exp: Likewise.
+	* ld-scripts/crossref.exp: Only check "which $CC" if host is local.
+	Use run_host_cmd.
+	* ld-scripts/map-address.exp: Upload map_address.map if host is
+	remote.
+	* ld-srec/srec.exp (run_srec_tests): Use run_host_cmd.  Only check
+	"which $CC" and "which $CXX" if host is local.
+	* ld-undefined/undefined.exp: Only check "which $CC" if host is
+	local.  Use remote_file and run_host_cmd.
+	* config/default.exp: Use remote_exec to create tmpdir.
+
+2007-08-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-i386/i386.exp (i386tests): Add a test for TLS IE->LE
+	transition.
+	Run tlsie2, tlsie3, tlsie4 and tlsie5.
+
+	* ld-i386/tlsie1.dd: New file.
+	* ld-i386/tlsie1.s: Likewise.
+	* ld-i386/tlsie2.d: Likewise.
+	* ld-i386/tlsie2.s: Likewise.
+	* ld-i386/tlsie3.d: Likewise.
+	* ld-i386/tlsie3.s: Likewise.
+	* ld-i386/tlsie4.d: Likewise.
+	* ld-i386/tlsie4.s: Likewise.
+	* ld-i386/tlsie5.d: Likewise.
+	* ld-i386/tlsie5.s: Likewise.
+	* ld-x86-64/tlsgd2.d: Likewise.
+	* ld-x86-64/tlsgd2.s: Likewise.
+	* ld-x86-64/tlsgd3.d: Likewise.
+	* ld-x86-64/tlsgd3.s: Likewise.
+	* ld-x86-64/tlsie1.dd: Likewise.
+	* ld-x86-64/tlsie1.s: Likewise.
+	* ld-x86-64/tlsie2.d: Likewise.
+	* ld-x86-64/tlsie2.s: Likewise.
+	* ld-x86-64/tlsie3.d: Likewise.
+	* ld-x86-64/tlsie3.s: Likewise.
+
+	* ld-x86-64/x86-64.exp (x86_64tests): Add a test for TLS LD->LE
+	transition.
+	Run tlsgd2, tlsgd3, tlsie2 and tlsie3.
+
+2007-08-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-i386/tlsbinpic.s: Add a new GD -> IE test.
+
+	* ld-i386/tlsgd1.s: Add a new GD -> LE test.
+
+	* ld-i386/tlsbin.dd: Updated.
+	* ld-i386/tlsbin.rd: Likewise.
+	* ld-i386/tlsgd1.dd: Likewise.
+
+2007-08-17  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-sparc/tlssunnopic32.dd: Fix up #target.
+	* ld-sparc/tlssunnopic32.rd: Likewise.
+	* ld-sparc/tlssunnopic32.sd: Likewise.
+	* ld-sparc/tlssunnopic64.dd: Likewise.
+	* ld-sparc/tlssunnopic64.rd: Likewise.
+	* ld-sparc/tlssunnopic64.sd: Likewise.
+
+2007-08-17  Richard Sandiford  <richard@codesourcery.com>
+
+	* lib/ld-lib.exp (run_dump_test): Allow [big_or_little_endian]
+	to appear in assembler and linker options.
+	* ld-mips-elf/vxworks1-static.d (ld): Add [big_or_little_endian].
+
+2007-08-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-srec/srec.exp: Always pass "-G 0".  Remove all powerpc
+	xfails.
+
+2007-08-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/4918
+	* ld-i386/i386.exp (i386tests): Add tlsgd1 and tlsld1 tests.
+	* ld-x86-64/x86-64.exp (x86_64tests): Likewise.
+
+	* ld-i386/tlsgd1.dd: New file.
+	* ld-i386/tlsgd1.s: Likewise.
+	* ld-i386/tlsld1.dd: Likewise.
+	* ld-i386/tlsld1.s: Likewise.
+	* ld-x86-64/tlsgd1.dd: Likewise.
+	* ld-x86-64/tlsgd1.s: Likewise.
+	* ld-x86-64/tlsld1.dd: Likewise.
+	* ld-x86-64/tlsld1.s: Likewise.
+
+2007-08-13  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/vxworks-forced-local-1.d,
+	* ld-mips-elf/vxworks-forced-local-1.s,
+	* ld-mips-elf/vxworks-forced-local-1.ver: New test.
+	* ld-mips-elf/mips-elf.exp: Run it.
+	* ld-mips-elf/tlsdyn-o32-2.d: Adjust for removal of unnecessary
+	local GOT entry.
+	* ld-mips-elf/tlsdyn-o32-2.got: Likewise.
+	* ld-mips-elf/tlsdyn-o32-3.d: Likewise.
+	* ld-mips-elf/tlsdyn-o32-3.got: Likewise.
+	* ld-mips-elf/vxworks1-lib.dd: Likewise.
+	* ld-mips-elf/vxworks1-lib.rd: Likewise.
+
+2007-08-13  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/relbrlt.s (.text.pad2): Adjust space.
+	* ld-powerpc/relbrlt.d: Update.
+	* ld-powerpc/tlsexe.d: Update.
+	* ld-powerpc/tlsexe.g: Update.
+	* ld-powerpc/tlsexe.r: Update.
+	* ld-powerpc/tlsexetoc.d: Update.
+	* ld-powerpc/tlsexetoc.g: Update.
+	* ld-powerpc/tlsexetoc.r: Update.
+	* ld-powerpc/tlsso.d: Update.
+	* ld-powerpc/tlsso.g: Update.
+	* ld-powerpc/tlsso.r: Update.
+	* ld-powerpc/tlstocso.d: Update.
+	* ld-powerpc/tlstocso.g: Update.
+
+2007-08-06  Kai Tietz   <kai.tietz@onevision.com>
+
+	PR ld/4877
+	* ld-pe/pe.exp: Special diff file for x86_64-mingw target.
+	* ld-pe/secrel_64.d: New.
+
+2007-08-03  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-srec/srec.exp: XFAIL for powerpc*-*-*.
+
+2007-08-01  Adam Nemet  <anemet@caviumnetworks.com>
+
+	* ld-mips-elf/reloc-4.s, ld-mips-elf/reloc-4.d,
+	ld-mips-elf/reloc-5.s, ld-mips-elf/reloc-5.d: New tests.
+	* ld-mips-elf/mips-elf.exp: Invoke them.
+
+2007-07-29  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/weak-dyn-1.rd: Adjust.
+
+2007-07-25  Daniel Jacobowitz  <dan@codesourcery.com>
+
+	* ld-cdtest/cdtest-foo.cc (strncpy): Fix parameter name.
+
+2007-07-24  Nick Clifton  <nickc@redhat.com>
+
+	* ld-arm/arm-elf.exp: Move EABI attribute tests into EABI only
+	section.
+
+2007-07-23  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-elf/weak-dyn-1a.s, ld-elf/weak-dyn-1b.s, ld-elf/weak-dyn-1.ld,
+	* ld-elf/weak-dyn-1.rd: New test.
+	* ld-elf/elf.exp: Run it.
+
+2007-07-13  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-scripts/assert.t: Tweak to avoid relying on empty's VMA being
+	zero.
+
+2007-07-10  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elfvers/vers.exp: Add tests for --defsym.
+
+	* ld-elfvers/vers32.map: Likewise.
+	* ld-elfvers/vers32a.c: Likewise.
+	* ld-elfvers/vers32a.dsym: Likewise.
+	* ld-elfvers/vers32a.ver: Likewise.
+	* ld-elfvers/vers32b.c: Likewise.
+	* ld-elfvers/vers32b.dsym: Likewise.
+	* ld-elfvers/vers32b.ver: Likewise.
+	* ld-elfvers/vers32c.dsym: Likewise.
+	* ld-elfvers/vers32c.ver: Likewise.
+	* ld-elfvers/vers32d.ver: Likewise.
+
+2007-07-06  Nick Clifton  <nickc@redhat.com>
+
+	* lib/default.exp: Update copyright notice to refer to GPLv3.
+	* config/default.exp, ld-alpha/alpha.exp, ld-arm/arm-elf.exp,
+	ld-auto-import/auto-import.exp, ld-bootstrap/bootstrap.exp,
+	ld-cdtest/cdtest.exp, ld-checks/checks.exp, ld-cris/cris.exp,
+	ld-crx/crx.exp, ld-cygwin/exe-export.exp, ld-d10v/d10v.exp,
+	ld-discard/discard.exp, ld-elf/elf.exp, ld-elf/exclude.exp,
+	ld-elf/frame.exp, ld-elf/sec64k.exp, ld-elf/binutils.exp,
+	ld-elf/tls_common.exp, ld-elf/shared.exp, ld-elf/dwarf.exp,
+	ld-elf/wrap.exp, ld-elfcomm/elfcomm.exp, ld-elfvers/vers.exp,
+	ld-elfvsb/elfvsb.exp, ld-elfweak/elfweak.exp, ld-xc16x/xc16x.exp,
+	ld-fastcall/fastcall.exp, ld-frv/tls.exp, ld-h8300/h8300.exp,
+	ld-i386/i386.exp, ld-ia64/ia64.exp, ld-linkonce/linkonce.exp,
+	ld-m68hc11/m68hc11.exp, ld-maxq/maxq.exp,
+	ld-mips-elf/mips-elf-flags.exp, ld-mips-elf/mips-elf.exp,
+	ld-mmix/mmix.exp, ld-pe/pe.exp, ld-pe/direct.exp,
+	ld-powerpc/powerpc.exp, ld-s390/s390.exp, ld-scripts/align.exp,
+	ld-scripts/alignof.exp, ld-scripts/assert.exp,
+	ld-scripts/crossref.exp, ld-scripts/data.exp,
+	ld-scripts/default-script.exp, ld-scripts/defined.exp,
+	ld-scripts/empty-address.exp, ld-scripts/empty-aligned.exp,
+	ld-scripts/empty-orphan.exp, ld-scripts/expr.exp,
+	ld-scripts/extern.exp, ld-scripts/map-address.exp,
+	ld-scripts/overlay-size.exp, ld-scripts/phdrs.exp,
+	ld-scripts/phdrs2.exp, ld-scripts/provide.exp,
+	ld-scripts/script.exp, ld-scripts/size.exp, ld-scripts/sizeof.exp,
+	ld-scripts/sort.exp, ld-scripts/weak.exp,
+	ld-selective/sel-dump.exp, ld-selective/selective.exp,
+	ld-sh/arch/arch.exp, ld-sh/sh64/rd-sh64.exp, ld-sh/sh64/relax.exp,
+	ld-sh/sh64/relfail.exp, ld-sh/sh64/sh64.exp, ld-sh/rd-sh.exp,
+	ld-sh/sh.exp, ld-shared/shared.exp, ld-sparc/sparc.exp,
+	ld-srec/srec.exp, ld-undefined/undefined.exp,
+	ld-undefined/weak-undef.exp, ld-versados/versados.exp,
+	ld-x86-64/x86-64.exp, ld-xstormy16/xstormy16.exp,
+	ld-xtensa/coalesce.exp, ld-xtensa/lcall.exp, ld-pie/pie.exp,
+	ld-m68k/m68k.exp, ld-mep/mep.exp, ld-spu/spu.exp,
+	ld-vxworks/vxworks.exp, lib/ld-lib.exp: Likewise.
+	* ld-frv/frv-elf.exp: Add copyright notice.
+	* ld-libs/libs.exp, ld-sh/sh-vxworks.exp,
+	ld-scripts/dynamic-sections.exp, ld-v850.v850.exp: Likewise.
+	
+2007-07-05  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/powerpc.exp: Disable for lynxos and nto.
+
+2007-07-03  Joseph Myers  <joseph@codesourcery.com>
+
+	* ld-arm/attr-merge-2a.s, ld-arm/attr-merge-2b.s,
+	ld-arm/attr-merge-2.attr: New.
+	* ld-arm/arm-elf.exp (armelftests): Add new test.
+
+2007-07-02  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-scripts/alignof.exp: Skip on non-elf
+
+2007-06-29  Joseph Myers  <joseph@codesourcery.com>
+
+	* ld-powerpc/attr-gnu-4-0.s, ld-powerpc/attr-gnu-4-00.d,
+	ld-powerpc/attr-gnu-4-01.d, ld-powerpc/attr-gnu-4-02.d,
+	ld-powerpc/attr-gnu-4-1.s, ld-powerpc/attr-gnu-4-10.d,
+	ld-powerpc/attr-gnu-4-11.d, ld-powerpc/attr-gnu-4-12.d,
+	ld-powerpc/attr-gnu-4-13.d, ld-powerpc/attr-gnu-4-2.s,
+	ld-powerpc/attr-gnu-4-20.d, ld-powerpc/attr-gnu-4-21.d,
+	ld-powerpc/attr-gnu-4-22.d, ld-powerpc/attr-gnu-4-3.s,
+	ld-powerpc/attr-gnu-4-31.d: New.
+	* ld-powerpc/powerpc.exp: Run these new tests.
+
+2007-06-29  Joseph Myers  <joseph@codesourcery.com>
+
+	* ld-mips-elf/attr-gnu-4-0.s, ld-mips-elf/attr-gnu-4-00.d,
+	ld-mips-elf/attr-gnu-4-01.d, ld-mips-elf/attr-gnu-4-02.d,
+	ld-mips-elf/attr-gnu-4-03.d, ld-mips-elf/attr-gnu-4-1.s,
+	ld-mips-elf/attr-gnu-4-10.d, ld-mips-elf/attr-gnu-4-11.d,
+	ld-mips-elf/attr-gnu-4-12.d, ld-mips-elf/attr-gnu-4-13.d,
+	ld-mips-elf/attr-gnu-4-14.d, ld-mips-elf/attr-gnu-4-2.s,
+	ld-mips-elf/attr-gnu-4-20.d, ld-mips-elf/attr-gnu-4-21.d,
+	ld-mips-elf/attr-gnu-4-22.d, ld-mips-elf/attr-gnu-4-23.d,
+	ld-mips-elf/attr-gnu-4-3.s, ld-mips-elf/attr-gnu-4-30.d,
+	ld-mips-elf/attr-gnu-4-31.d, ld-mips-elf/attr-gnu-4-32.d,
+	ld-mips-elf/attr-gnu-4-33.d, ld-mips-elf/attr-gnu-4-4.s,
+	ld-mips-elf/attr-gnu-4-41.d: New.
+	* ld-mips-elf/mips-elf.exp: Run these new tests.
+
+2007-06-29  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-elf.exp (armelftests): Add callweak.
+	* ld-arm/callweak.d: New test.
+	* ld-arm/callweak.s: New test.
+
+2007-06-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/4701
+	* ld-elf/noload-2.d: New.
+
+2007-06-29  H.J. Lu <hjl@gnu.org>
+
+	* ld-scripts/assert.t: Discard .reginfo sections.
+
+2007-06-26  Joseph Myers  <joseph@codesourcery.com>
+
+	* ld-arm/attr-merge.s, ld-arm/attr-merge.attr: New.
+	* ld-arm/arm-elf.exp (armelftests): Add new test.
+
+2007-06-25  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/mips16-local-stubs-1.s,
+	* ld-mips-elf/mips16-local-stubs-1.d: New tests.
+	* ld-mips-elf/mips-elf.exp: Run them.
+
+2007-06-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/4590
+	* ld-ia64/merge1.d: New.
+	* ld-ia64/merge1.s: Likewise.
+	* ld-ia64/merge2.d: Likewise.
+	* ld-ia64/merge2.s: Likewise.
+	* ld-ia64/merge3.d: Likewise.
+	* ld-ia64/merge3.s: Likewise.
+	* ld-ia64/merge4.d: Likewise.
+	* ld-ia64/merge4.s: Likewise.
+	* ld-ia64/merge5.d: Likewise.
+	* ld-ia64/merge5.s: Likewise.
+
+2007-06-18  Andreas Schwab  <schwab@suse.de>
+
+	* ld-scripts/cross3.t: Add .opd section.
+
+2007-06-18  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-scripts/alignof.s: New.
+	* ld-scripts/alignof.t: New
+	* ld-scripts/alignof.exp: New.
+
+2007-06-14  Alan Modra  <alan@grove.modra.org>
+
+	* ld-spu/ovl.d: Update.
+	* ld-spu/ovl2.d: Update.
+
+2007-05-24  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-scripts/assert.t: Add additional cases.
+	* ld-scripts/extern.t, ld-scripts/extern.s,
+	ld-scripts/extern.exp: New.
+
+2007-05-22  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-pic-veneer.d: Update expected output.
+	* ld-arm/arm-call.d: Ditto.
+
+2007-05-22  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm-mixed-lib.d: Update expected output.
+	* ld-arm/arm-app.d: Ditto.
+	* ld-arm/mixed-app.d: Ditto.
+	* ld-arm/arm-lib-plt32.d: Ditto.
+	* ld-arm/arm-app-abs32.d: Ditto.
+	* ld-arm/mixed-app-v5.d: Ditto.
+	* ld-arm/armthumb-lib.d: Ditto.
+	* ld-arm/arm-lib.d: Ditto.
+
+2007-05-21  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-arm/emit-relocs1.d, ld-arm/emit-relocs1.s,
+	* ld-arm/emit-relocs1-vxworks.d: New tests.
+	* ld-arm/arm-elf.exp: Run them.
+	* ld-arm/vxworks1.dd: Expect proper branch targets.
+
+2007-05-18  Joseph Myers  <joseph@codesourcery.com>
+
+	* ld-elf/group.ld: Discard .reginfo.
+
+2007-05-18  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-call.d: Update expected output.
+
+2007-05-17  Paul Brook  <paul@codesourcery.com>
+
+	* ld-elf/multibss1.s: Use %nobits instead of @nobits.
+
+2007-05-17  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-m68k/merge-error-1a.d: Mismatch is an error.
+	* ld-m68k/merge-error-1b.d: Likewise.
+	* ld-m68k/merge-error-1c.d: Likewise.
+	* ld-m68k/merge-error-1d.d: Likewise.
+	* ld-m68k/merge-error-1e.d: Likewise.
+
+2007-05-15  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/4504
+	* ld-elf/data1.c: New file.
+	* ld-elf/data1.h: Likewise.
+	* ld-elf/dynbss1.c: Likewise.
+	* ld-elf/pass.out: Likewise.
+
+	* ld-elf/shared.exp (build_tests): Add "Build libdata1.so".
+	(run_tests): Add "Run with libdata1.so".
+
+2007-05-15  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-arm/vxworks1.ld: Swap .bss and .data.
+	* ld-arm/vxworks1-lib.rd: Update accordingly.
+	* ld-arm/vxworks1-lib.td: New test.
+	* ld-arm/arm-elf.exp: Run it.
+
+	* ld-i386/vxworks1.ld: Swap .bss and .data.
+	* ld-i386/vxworks1-lib.rd: Update accordingly.
+	* ld-i386/vxworks1-lib.td: New test.
+	* ld-i386/i386.exp: Run it.
+
+	* ld-mips-elf/vxworks1.ld: Swap .bss and .data.
+	* ld-mips-elf/vxworks1-lib.rd: Update accordingly.
+	* ld-mips-elf/vxworks1.rd: Likewise.
+
+	* ld-powerpc/vxworks1.ld: Swap .bss and .data.
+	* ld-powerpc/vxworks1-lib.rd: Update accordingly.
+	* ld-powerpc/vxworks1-lib.td: New test.
+	* ld-powerpc/powerpc.exp: Run it.
+
+	* ld-sh/vxworks1.ld: Swap .bss and .data.
+	* ld-sh/vxworks1-lib.rd: Update accordingly.
+	* ld-sh/vxworks1-lib.td: New test.
+	* ld-sh/sh-vxworks.exp: Run it.
+
+	* ld-sparc/vxworks1.ld: Swap .bss and .data.
+	* ld-sparc/vxworks1-lib.rd: Update accordingly.
+	* ld-sparc/vxworks1-lib.td: New test.
+	* ld-sparc/sparc.exp: Run it.
+
+2007-05-15  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/vxworks1-lib.rd: Expect the GOT relocation to be
+	against symbol 0.
+
+2007-05-15  Mark Shinwell  <shinwell@codesourcery.com>
+
+	* ld-arm/arm-elf.exp: Add jump19 testcase.
+	* ld-arm/jump19.d: New.
+	* ld-arm/jump19.s: New.
+
+2007-05-14  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-sh/vxworks1.dd: Remove hexadecimal prefixes from constant pool
+	contents.  Consistently use "!" as the comment character.
+	Consistently use _PROCEDURE_LINKAGE_TABLE_ in the first PLT entry.
+	* ld-sh/vxworks1-le.dd: Likewise.
+	* ld-sh/vxworks1-lib.dd: Likewise.
+	* ld-sh/vxworks1-lib-le.dd: Likewise.
+	* ld-sh/vxworks3.dd: Likewise.
+	* ld-sh/vxworks3-le.dd: Likewise.
+
+2007-05-14  Andreas Schwab  <schwab@suse.de>
+
+	* ld-elf/dl2a.list: New file.
+	* ld-elf/shared.exp: Add test using --dynamic-list=dl2a.list.
+
+2007-05-10  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-arm/vxworks1-lib.dd: Expect "push" instead of stmdb and
+	"pop" instead of ldmia.  Don't require specific symbolic addresses
+	for in-text addresses.  Expect data to be rendered as .words rather
+	than disassembled.
+	* ld-arm/vxworks1.dd: Likewise.
+
+2007-05-10  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-elf/multibss1.d, ld-elf/multibss1.s: New test.
+
+2007-04-27  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-m68k/plt1-isac.d: New.
+	* ld-m68k/m68k.exp: Add it.
+
+2007-04-26  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutils/4430
+	* ld-i386/tlsbin.dd: Updated.
+	* ld-i386/tlsbindesc.dd: Likewise
+	* ld-i386/tlsdesc.dd: Likewise
+	* ld-i386/tlsgdesc.dd: Likewise
+	* ld-i386/tlsnopic.dd: Likewise
+	* ld-i386/tlspic.dd: Likewise
+	* ld-x86-64/tlsbin.dd: Likewise
+	* ld-x86-64/tlsbindesc.dd: Likewise
+	* ld-x86-64/tlsdesc.dd: Likewise
+	* ld-x86-64/tlsgdesc.dd: Likewise
+	* ld-x86-64/tlspic.dd: Likewise
+
+2007-04-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-linkonce/x.s: Use .gcc_except_table instead of .eh_frame
+	to test that entry for deleted function is zeroed.  Add a
+	somewhat closer to normal .eh_frame to test that fde for
+	deleted function is removed.
+	* ld-linkonce/y.s: Likewise.
+	* ld-linkonce/zeroeh.ld: Place .gcc_except_table too.
+	* ld-linkonce/zeroehl32.d: Update.
+
+2007-04-21  Richard Earnshaw  <rearnsha@arm.com>
+
+	* ld-arm/arm-app-abs32.d: Convert to unified syntax.
+	* ld-arm/arm-app.d: Likewise.
+	* ld-arm/arm-lib-plt32.d: Likewise.
+	* ld-arm/arm-lib.d: Likewise.
+	* ld-arm/arm-static-app.d: Likewise.
+	* ld-arm/armthumb-lib.d: Likewise.
+	* ld-arm/mixed-app-v5.d: Likewise.
+	* ld-arm/mixed-app.d: Likewise.
+	* ld-arm/mixed-lib.d: Likewise.
+
+2007-04-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-spu/ovl.lnk: Use OVERLAY keyword.
+
+2007-04-17  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/preempt-app.s: New test.
+	* ld-arm/preempt-app.sym: New.
+	* ld-arm/arm-elf.exp: Add preempt-app.
+
+2007-04-12  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-mips-elf/vxworks1-lib.td: New test.
+	* ld-mips-elf/mips-elf.exp: Run it.
+
+2007-04-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/4304
+	* ld-i386/i386.exp: Run "warn1".
+
+	* ld-i386/warn1.d: New file.
+	* ld-i386/warn1.s: Likewise.
+
+2007-04-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-i386/combreloc.d: Remove #target: i?86-*-*.
+	* ld-i386/reloc.d: Likewise.
+
+2007-04-05  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-spu/ovl2.d: Update.
+
+2007-04-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/4090
+	* ld-elf/expr1.d: New file.
+	* ld-elf/expr1.s: Likewise.
+	* ld-elf/expr1.t: Likewise.
+
+2007-03-29  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-libs/lib-1.s, ld-libs/lib-2.s, ld-libs/lib-2.d,
+	* ld-libs/libs.exp: New files.
+
+2007-03-28  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-vxworks/rpath-1.s, ld-vxworks/rpath-1.d,
+	* ld-vxworks/vxworks.exp: New files.
+
+2007-03-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/note-1.s: Increase .foo size.
+
+2007-03-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-spu/spu.exp (embed_test): New.
+	* ld-spu/ear.s: New.
+	* ld-spu/ear.d: New.
+	* ld-spu/embed.rd: New.
+	* ld-spu/ovl2.s: New.
+	* ld-spu/ovl2.d: New.
+
+2007-03-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/overlay.d: -u symbols we want to see in the output.
+
+2007-03-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-spu/ovl.s (f4_a2): Tail call.
+	* ld-spu/ovl.d: Add --emit-relocs to ld options, -r to objdump.
+	Update expected results.
+
+2007-03-23  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/ld-r-1.d: Update.
+	* ld-sh/shared-1.d: Likewise.
+
+2007-03-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/elf.exp: Add "--local-store 0:0" to LDFLAGS for spu.
+
+2007-03-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/4210
+	* ld-pe/image_size.d: New file.
+	* ld-pe/image_size.s: Likewise.
+	* ld-pe/image_size.t: Likewise.
+
+	* ld-pe/pe.exp: Run image_size.
+
+2007-03-22  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/4007
+	* ld-elf/note-1.d: New file.
+	* ld-elf/note-1.s: Likewise.
+	* ld-elf/note-1.t: Likewise.
+	* ld-i386/alloc.d: Likewise.
+	* ld-i386/alloc.s: Likewise.
+	* ld-i386/alloc.t: Likewise.
+
+	* ld-i386/i386.exp: Run "alloc".
+
+2007-03-20  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-elf.exp (ld-arm/arm-elf.exp): Add arm-pic-veneer.
+	* ld-arm/arm-pic-veneer.d: New test.
+	* ld-arm/arm-pic-veneer.s: New test.
+
+2007-03-08  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-elf/extract-symbol-1.ld (data): Explicitly set the start address
+	to 0.
+
+2007-03-07  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/extract-symbol-1sec.d: xfail hppa.
+	* ld-elf/extract-symbol-1sym.d: xfail hppa.
+
+2007-03-07  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR 3958
+	* ld-elf/linkonce1.d: New.
+	* ld-elf/linkonce1a.s: New.
+	* ld-elf/linkonce1b.s: New.
+	* ld-elf/linkonce2.d: New.
+	* ld-i386/pcrel16abs.d: New.
+	* ld-i386/pcrel16abs.s: New.
+	* ld-i386/i386.exp: Run it.
+
+2007-03-06  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/4144
+	* ld-elf/nobits-1.d: New file.
+	* ld-elf/nobits-1.s: Likewise.
+	* ld-elf/nobits-1.t: Likewise.
+
+2007-03-02  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-elf/binutils.exp: Revert last change.
+
+2007-03-01  Richard Sandiford  <richard@codesourcery.com>
+
+	* ld-elf/extract-symbol-1sym.d, ld-elf/extract-symbol-1sec.d,
+	* ld-elf/extract-symbol-1.s, ld-elf/extract-symbol-1.ld: New tests.
+	* ld-elf/binutils.exp: Run them.
+
+2007-02-28  Nick Clifton  <nickc@redhat.com>
+
+	PR ld/3796
+	* ld-arm/arm-elf.exp (armelftests): Move "Thumb-2 BL" test into...
+	(armeabitests): ... here, a new array for EABI specific tests.
+	(armelftests): Add extra command line options for VFP11 fix tests
+	and thumb shared library test.
+
+2007-02-22  Paul Brook  <paul@codesourcery.com>
+
+	* ld-arm/arm-elf.exp (armelftests): Add gc-unwind.h.
+	* ld-arm/gc-unwind.s: New file.
+	* ld-arm/gc-unwind.d: New file.
+
+2007-02-14  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/3953
+	* ld-elf/beginwarn.c: New file.
+	* ld-elf/warn.out: Likewise.
+
+	* ld-elf/shared.exp (build_tests): Add "Build warn libbar.so".
+	(run_tests): Add "Run warn with versioned libfoo.so".
+
+	* lib/ld-lib.exp (default_ld_relocate): Make exec_output global
+	and remove target first.
+	(default_ld_link): Likewise.
+	(default_ld_simple_link): Likewise.
+	(run_ld_link_exec_tests): Take an optional linker warning and
+	check it.
+	(default_ld_link): Check pruned linker output.
+
+2007-02-13  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-scripts/default-script1.d: Expect extra symbols.
+	* ld-scripts/default-script2.d: Likewise.
+	* ld-scripts/default-script3.d: Likewise.
+	* ld-scripts/default-script4.d: Likewise.
+
+2007-02-13  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/relbrlt.d: Update.
+	* ld-powerpc/tlsexe.r: Update.
+	* ld-powerpc/tlsexetoc.r: Update.
+	* ld-powerpc/tlsso.r: Update.
+	* ld-powerpc/tlstocso.r: Update.
+
+2007-02-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/relbrlt.d: Update.
+
+2007-02-06  Nick Clifton  <nickc@redhat.com>
+
+	PR ld/3805
+	* ld-elf/sec64k.exp: Expect the relocatable version of this test
+	to fail for the m32r because it creates both .rel and .rela
+	sections.
+
+2007-02-05  Dave Brolley  <brolley@redhat.com>
+
+	* ld-undefined/undefined.exp: XFAIL the undefined test
+	* ld-mep: New, with content.
+
+2007-02-05  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-i386/pcrel16.d: Undo the last change.
+	* ld-x86-64/pcrel16.d: Likewise.
+
+2007-02-02  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-i386/pcrel16.d: Updated.
+	* ld-x86-64/pcrel16.d: Likewise.
+
+2007-02-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/default-script.exp: Add "--local-store 0:0" to
+	LDFLAGS for spu.
+
+2007-01-29  Julian Brown  <julian@codesourcery.com>
+
+	* ld-arm/arm-elf.exp: Add VFP11 tests.
+	* ld-arm/vfp11-fix-none.s: New file.
+	* ld-arm/vfp11-fix-none.d: Expected disassembly of above.
+	* ld-arm/vfp11-fix-scalar.s: New file.
+	* ld-arm/vfp11-fix-scalar.d: Expected disassembly of above.
+	* ld-arm/vfp11-fix-vector.s: New file.
+	* ld-arm/vfp11-fix-vector.d: Expected disassembly of above.
+
+2007-01-23  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-elf/header.d: Reduce page size, restrict to linux & vxworks
+	* ld-elf/header.s: Adjust.
+	* ld-elf/header.t: Reduce initial offset.
+
+2007-01-23  Andreas Schwab  <schwab@suse.de>
+
+	* lib/ld-lib.exp (run_dump_test): Don't prematurely remove
+	assembler output.
+
+2007-01-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/dl6.c: New file.
+	* ld-elf/dl6a.out: Likewise.
+	* ld-elf/dl6amain.c: Likewise.
+	* ld-elf/dl6b.out: Likewise.
+	* ld-elf/dl6bmain.c: Likewise.
+	* ld-elf/dl6cmain.c: Likewise.
+	* ld-elf/dl6dmain.c: Likewise.
+
+	* ld-elf/shared.exp: Add new tests for -Bsymbolic,
+	-Bsymbolic-functions, --dynamic-list-data and
+	--dynamic-list-cpp-new.
+
+2007-01-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/maxpage3.t: New file.
+	* ld-elf/maxpage3a.d: Likewise.
+	* ld-elf/maxpage3b.d: Likewise.
+	* ld-elf/maxpage3c.d: Likewise.
+
+2007-01-19  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-scripts/default-script.exp: New file.
+	* ld-scripts/default-script.s: Likewise.
+	* ld-scripts/default-script.t: Likewise.
+	* ld-scripts/default-script1.d: Likewise.
+	* ld-scripts/default-script2.d: Likewise.
+	* ld-scripts/default-script3.d: Likewise.
+	* ld-scripts/default-script4.d: Likewise.
+
+2007-01-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/1283
+	* lib/ld-lib.exp (run_dump_test): Remove output file first.
+
+2007-01-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/header.d: Adjust for .text section with 16byte
+	alignment.
+
+2007-01-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elf/dl1main.c (main): Fix a typo.
+
+2007-01-16  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR ld/3831
+	* ld-elf/del.cc: New.
+	* ld-elf/dl5.cc: Likewise.
+	* ld-elf/dl5.out: Likewise.
+	* ld-elf/new.cc: Likewise.
+
+	* ld-elf/shared.exp: Add tests for --dynamic-list-data and
+	 --dynamic-list-cpp-new.
+
+2007-01-12  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-elf/header.d: Allow arbitrary lines between "Program Header"
+	and "Sections".  Only run on *-*-linux*.
+
+2007-01-11  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-elf/header.d: New.
+	* ld-elf/header.t: New.
+	* ld-elf/header.s: New.
+
+2007-01-08  Kai Tietz	<kai.tietz@onevision.com>
+
+	* ld-fastcall/fastcall.exp: Renamed target x86_64-*-mingw64 to
+	x86_64-*-mingw*.
+	* ld-pe/pe.exp: Ditto.
+	* ld-scripts/align.exp: Ditto.
+	* ld-scripts/defined.exp: Ditto.
+	* ld-scripts/provide.exp: Ditto.
+	* ld-scripts/weak.exp: Ditto.
+
+2007-01-06  Nathan Sidwell  <nathan@codesourcery.com>
+
+	* ld-scripts/expr.exp: New.
+	* ld-scripts/expr1.s: New.
+	* ld-scripts/expr1.d: New.
+	* ld-scripts/expr1.t: New.
+
+For older changes see ChangeLog-2006
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.19/ld/testsuite/ChangeLog-9303 b/binutils-2.19/ld/testsuite/ChangeLog-9303
new file mode 100644
index 0000000..895eb03
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ChangeLog-9303
@@ -0,0 +1,3376 @@
+2003-12-30  Mark Mitchell  <mark@codesourcery.com>
+
+	* ld-srec/srec.exp (run_srec_test): Remove -fgnu-linker, since GCC
+	3.4 does not support it.
+
+2003-12-18  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-mips-elf/reloc-1[ab].s: New source files.
+	* ld-mips-elf/reloc-1-{n32,n64,rel}.d: New tests.
+	* ld-mips-elf/reloc-2[ab].s: New source files.
+	* ld-mips-elf/reloc-2.{d,ld}: New test.
+	* ld-mips-elf/reloc-3[ab].s: New source files.
+	* ld-mips-elf/reloc-3-{r,srec}.d: New tests.
+	* ld-mips-elf/mips-elf.exp: Run them.
+
+2003-12-07  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-mips-elf/elf-rel-xgot-n32.d: Fix offset for "lw $5,dl1+34($5)".
+	* ld-mips-elf/elf-rel-xgot-n64-linux.d: Likewise.
+
+2003-12-01  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/sh64/shmix-1.s: Add align to match data alignment.
+	* ld-sh/sh64/shmix-3.s: Likewise.
+	* ld-sh/sh64/mix1.sd: Update.
+	* ld-sh/sh64/mix1.xd: Likewise.
+	* ld-sh/sh64/mix1-noexp.sd: Likewise.
+	* ld-sh/sh64/mix2.sd: Likewise.
+	* ld-sh/sh64/mix2.xd: Likewise.
+	* ld-sh/sh64/mix2-noexp.sd: Likewise.
+
+2003-12-01  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-sh/tlsbin-2.d: Update section alignment.
+	* ld-sh/tlspic-2.d: Likewise.
+	* ld-sh/sh64/abi32.xd: Likewise.
+	* ld-sh/sh64/abi64.xd: Likewise.
+	* ld-sh/sh64/cmpct1.xd: Likewise.
+	* ld-sh/sh64/rel32.xd: Likewise.
+	* ld-sh/sh64/rel64.xd: Likewise.
+	* ld-sh/sh64/shdl32.xd: Likewise.
+	* ld-sh/sh64/shdl64.xd: Likewise.
+
+2003-11-19  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexe32.d: Update for changed symbols from objdump.
+	* ld-powerpc/tlsso32.d: Likewise.
+
+2003-10-27  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* ld-undefined/undefined.exp: Mark as xfail for m6811 and m6812
+	due to elf/Dwarf2 binutils limitation.
+
+2003-10-23  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-elfvers/vers.exp (test_ldfail): Add "-Wl," to pass the
+	linker option from gcc.
+
+2003-10-23  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexetoc.d: Correct.
+	* ld-powerpc/tlstoc.d: Correct.
+
+2003-10-18  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/greg-14.d, ld-mmix/greg-5.d, ld-mmix/pushja1b.d,
+	ld-mmix/pushja1f.d, ld-mmix/pushja7b.d, ld-mmix/pushja7f.d: Pass
+	--no-pushj-stubs to the assembler.
+	* ld-mmix/pushjs2b.d, ld-mmix/greg-14s.d, ld-mmix/pushjs1.d,
+	ld-mmix/greg-5s.d, ld-mmix/pushjs3b.d, ld-mmix/pushja1f-s.d,
+	ld-mmix/pushjs1m.d, ld-mmix/pushja7b-s.d, ld-mmix/pushja7f-s.d,
+	ld-mmix/pushja1b-s.d, ld-mmix/pushjs2.d, ld-mmix/pushjs3.d,
+	ld-mmix/pushjs4b.d, ld-mmix/pushjs4.d, ld-mmix/pushjs1bm.d,
+	ld-mmix/pushjs1b.d, ld-mmix/pushjs2m.d, ld-mmix/pushjs1r.d,
+	ld-mmix/pushjs3m.d, ld-mmix/pushjs2bm.d, ld-mmix/pushjs4m.d,
+	ld-mmix/pushjs3bm.d, ld-mmix/pushjs2r.d, ld-mmix/pushjs4bm.d,
+	ld-mmix/pushjs3r.d, ld-mmix/pushjs4r.d: New tests.
+
+2003-10-15  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/sh64/rd-sh64.exp: If the test matches *-dso.d, copy
+	the output of linker to the file tmpdir/*-dso.so.
+	* ld-sh/sh64/stobin-0-dso.d: New.
+	* ld-sh/sh64/stobin-1.d: New.
+	* ld-sh/sh64/stobin.s: New.
+	* ld-sh/sh64/stolib.s: New.
+
+2003-10-13  Richard Sandiford  <rsandifo@redht.com>
+
+	* ld-mips-elf/multi-got-1.d (RELSZ): Don't include the size of the
+	trailing null relocs.
+
+2003-10-12  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/rd-sh.exp (LDFLAGS): Define appropriately for each
+	sh64/sh5 targets.
+	* ld-sh/sh.exp: Don't do relaxing test for sh64*-*-* and
+	sh5*-*-* targets.
+	* ld-sh/sh64/relax.exp (emul32): Set to shelf32_nbsd for netbsd.
+	* ld-sh/sh64/relfail.exp: Set parameters for netbsd.
+	* ld-sh/sh64/sh64.exp: Skip this for netbsd.  Trim the section
+	numbers for crangerel1 and crengerel2 tests.
+	* ld-sh/sh64/abi32.sd: Update.
+	* ld-sh/sh64/abi32.xd: Likewise.
+	* ld-sh/sh64/abi64.sd: Likewise.
+	* ld-sh/sh64/abi64.xd: Likewise.
+	* ld-sh/sh64/abixx-noexp.sd: Likewise.
+	* ld-sh/sh64/cmpct1.sd: Likewise.
+	* ld-sh/sh64/cmpct1.xd: Likewise.
+	* ld-sh/sh64/crange1.rd: Likewise.
+	* ld-sh/sh64/crange2.rd: Likewise.
+	* ld-sh/sh64/crange3-cmpct.rd: Likewise.
+	* ld-sh/sh64/crange3-media.rd: Likewise.
+	* ld-sh/sh64/crange3.rd: Likewise.
+	* ld-sh/sh64/crangerel1.rd: Likewise.
+	* ld-sh/sh64/crangerel2.rd: Likewise.
+	* ld-sh/sh64/dlsection.sd: Likewise.
+	* ld-sh/sh64/endian.sbd: Likewise.
+	* ld-sh/sh64/endian.sld: Likewise.
+	* ld-sh/sh64/gotplt.d: Likewise.
+	* ld-sh/sh64/init-cmpct.d: Likewise.
+	* ld-sh/sh64/init-media.d: Likewise.
+	* ld-sh/sh64/init.s: Align functions.
+	* ld-sh/sh64/init64.d: Update.
+	* ld-sh/sh64/mix1-noexp.sd: Likewise.
+	* ld-sh/sh64/mix1.sd: Likewise.
+	* ld-sh/sh64/mix1.xd: Likewise.
+	* ld-sh/sh64/mix2-noexp.sd: Likewise.
+	* ld-sh/sh64/mix2.sd: Likewise.
+	* ld-sh/sh64/mix2.xd:Likewise.
+	* ld-sh/sh64/rel32.xd: Likewise.
+	* ld-sh/sh64/rel64.xd: Likewise.
+	* ld-sh/sh64/reldl32.rd: Likewise.
+	* ld-sh/sh64/reldl64.rd: Likewise.
+	* ld-sh/sh64/shdl32.xd: Update.
+	* ld-sh/sh64/shdl64.sd: Likewise.
+	* ld-sh/sh64/shdl64.xd: Likewise.
+	* ld-sh/shared-1.d: Add -z nocombreloc to ld option.  Update.
+	* ld-sh/sub2l-1.d: Make file format match with elf32-sh.*.
+	* ld-sh/weak1.d: Likewise.
+
+2003-10-11  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-scripts/defined3.d, ld-scripts/defined3.t: New test.
+	* ld-scripts/defined.exp: Run defined3.
+
+2003-10-08  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-scripts/defined2.d, ld-scripts/defined2.t: New test.
+	* ld-scripts/defined.exp: Run defined2.
+
+2003-10-07  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
+
+	* ld-elfvsb/elfvsb.exp: xfail non-pic shared library tests for
+	non 64-bit hppa*-*-linux* targets.
+	* ld-elfvsb/main.c (main_visibility_check): Cast value returned by
+	visibility_funptr () to a function pointer.
+	* ld-shared/shared.exp: xfail shared (non PIC), shared (non PIC, load
+	offset), and shared (PIC main, non PIC so) tests for non 64-bit
+	hppa*-*-linux* targets.
+
+2003-09-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-checks/checks.exp (section_check): Remove ia64-*-elf*.
+
+2003-09-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-checks/checks.exp (section_check): Skip ia64-*-* instead
+	of ia64-*-linux*.
+
+2003-09-30  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-ia64/ia64.exp: Remove -melf64_ia64.
+
+	* ld-ia64/tlsbin.dd: Remove -melf64_ia64. Match elf..-ia64-.*
+	instead of elf64-ia64-little.
+	* ld-ia64/tlsbin.rd: Likewise.
+	* ld-ia64/tlsbin.sd: Likewise.
+	* ld-ia64/tlsbin.td: Likewise.
+	* ld-ia64/tlsg.sd: Likewise.
+	* ld-ia64/tlspic.dd: Likewise.
+	* ld-ia64/tlspic.rd: Likewise.
+	* ld-ia64/tlspic.sd: Likewise.
+	* ld-ia64/tlspic.td: Likewise.
+
+2003-09-30  Chris Demetriou  <cgd@broadcom.com>
+
+	* ld-mips-elf/mips-elf-flags.exp: Add tests for combinations
+	with MIPS64r2.
+
+2003-09-29  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* lib/ld-lib.exp (proc is_elf64): New.
+
+	* ld-scripts/phdrs.exp: Use is_elf_format and is_elf64.
+
+2003-09-23  Alan Modra  <alan@modra.org>
+
+	* ld-discard/exit.s: Correct .text.exit attributes.
+	* ld-discard/extern.s: Likewise.
+	* ld-discard/static.s: Likewise.
+
+2003-09-21  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* ld-mips-elf/relax-jalr-n32.d: Fix little endian test failure.
+	* ld-mips-elf/relax-jalr-n32-shared.d: Likewise.
+	* ld-mips-elf/relax-jalr-n64.d: Likewise.
+	* ld-mips-elf/relax-jalr-n64-shared.d: Likewise.
+
+2003-09-14  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/bpo-1.d, ld-mmix/bpo-10.d, ld-mmix/bpo-11.d,
+	ld-mmix/bpo-14.d, ld-mmix/bpo-16.d, ld-mmix/bpo-17.d,
+	ld-mmix/bpo-18.d, ld-mmix/bpo-19.d, ld-mmix/bpo-2.d,
+	ld-mmix/bpo-22.d, ld-mmix/bpo-3.d, ld-mmix/bpo-4.d,
+	ld-mmix/bpo-5.d, ld-mmix/bpo-6.d, ld-mmix/bpo-9.d,
+	ld-mmix/greg-19.d, ld-mmix/loc1.d, ld-mmix/loc2.d, ld-mmix/loc3.d,
+	ld-mmix/loc4.d, ld-mmix/loc6.d, ld-mmix/local12.d,
+	ld-mmix/locdo-1.d, ld-mmix/loct-1.d, ld-mmix/locto-1.d: Adjust for
+	objdump -d change.
+
+2003-09-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/merge2.s: New.
+	* ld-elf/merge2.d: New.
+
+2003-08-16  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/bpo-9.d, ld-mmix/bpo-10.d, ld-mmix/bpo-11.d: Adjust for
+	recent objdump "Contents of ..." change.
+
+2003-08-02  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/shared-2.d, ld-sh/textrel1.s, ld-sh/textrel2.s: New test.
+
+2003-08-02  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-d10v/reloc-001.d: Adjust for objdump -d change.
+	* ld-d10v/reloc-002.d: Likewise.
+	* ld-d10v/reloc-005.d: Likewise.
+	* ld-d10v/reloc-006.d: Likewise.
+	* ld-d10v/reloc-009.d: Likewise.
+	* ld-d10v/reloc-010.d: Likewise.
+	* ld-d10v/reloc-013.d: Likewise.
+	* ld-d10v/reloc-014.d: Likewise.
+	* ld-xstormy16/pcrel.d: Likewise.
+
+2003-07-29  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-elfvsb/elf-offset.ld: Add .rel.toc, .rela.toc and .toc
+	sections.
+
+2003-07-29  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsso.r: Update.
+	* ld-powerpc/tlstocso.r: Update.
+
+2003-07-29  Nick Clifton  <nickc@redhat.com>
+
+	* ld-alpha/tlsbin.dd: Update to account for .eh_frame section.
+	* ld-alpha/tlsbin.rd: Likewise.
+	* ld-alpha/tlsbin.sd: Likewise.
+	* ld-alpha/tlsbinr.dd: Likewise.
+	* ld-alpha/tlsbinr.rd: Likewise.
+	* ld-alpha/tlsbinr.sd: Likewise.
+	* ld-alpha/tlspic.dd: Likewise.
+	* ld-alpha/tlspic.rd: Likewise.
+	* ld-alpha/tlspic.sd: Likewise.
+
+2003-07-26  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexe32.d: Update.
+	* ld-powerpc/tlsso32.d: Update.
+
+2003-07-24  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* ld-powerpc/tlsexe.r: .sbss is NOBITS, not PROGBITS.
+	* ld-powerpc/tlsexetoc.r: Likewise.
+	* ld-powerpc/tlsso.r: Likewise.
+	* ld-powerpc/tlstocso.r: Likewise.
+
+2003-07-23  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* ld-srec/srec.exp: For m6811/m6812 use --defsym to define _.z soft
+	register.
+
+2003-07-22  H.J. Lu <hongjiu.lu@intel.com>
+
+	* ld-selective/selective.exp: Skip "ia64-*-*".
+
+	* ld-srec/srec.exp: Make xfail on "ia64-*-*".
+
+2003-07-11  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-h8300/relax-3{.s,.d,-coff.d}: New test.
+	* ld-h8300/h8300.exp: Run it.
+
+2003-07-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/powerpc.exp: Dump output .got section rather than .toc.
+	* ld-powerpc/tlsexetoc.g: Update.
+	* ld-powerpc/tlsexetoc.r: Update.
+	* ld-powerpc/tlstoc.g: Update.
+	* ld-powerpc/tlstocso.g: Update.
+	* ld-powerpc/tlstocso.r: Update.
+
+2003-07-04  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-h8300/h8300.exp: Replace loop with explicit list.  Run relax.d
+	unconditionally.  Run relax-2.d for *-elf targets.
+	* ld-h8300/relax.d: Fix typo.
+	* ld-h8300/relax.s: Add 0x prefixes.
+	* ld-h8300/relad-2.[sd]: New test.
+
+2003-06-29  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* ld-mips-elf/mips-elf.exp: Use is_elf_format.
+
+2003-06-29  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* ld-mips-elf/mips-elf-flags.exp: Use -melf32bsmip for IRIX6.
+
+2003-06-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/apuinfo.rd: Update.
+
+2003-06-21  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* ld-mips-elf/elf-rel-got-n32.d: Remove special handling for n32 ABI.
+	* ld-mips-elf/elf-rel-xgot-n32.d: Likewise.
+
+2003-06-18  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/locref1.d, ld-cris/locref1.s, ld-cris/locref2.d,
+	ld-cris/locref2.s: New tests.
+
+	* ld-elfcomm/elfcomm.exp (dump_common1): Use $READELF, not plain
+	readelf as found using default path.
+
+2003-06-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* lib/ld-lib.exp (default_ld_simple_link): Trim ld parms before
+	trying to trim ld path.
+	(default_ld_compile): Likewise for cc.
+
+	* lib/ld-lib.exp (default_ld_simple_link): Trim ld path before
+	looking for gcc match.
+	(default_ld_compile): Likewise for cc.
+
+2003-06-17  Loren James Rittle  <rittle@latour.rsch.comm.mot.com>
+
+	* ld-undefined/undefined.exp (i?86-*-freebsd*): Remove xfail.
+
+2003-06-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexetoc.d: Update.
+	* ld-powerpc/tlsso.d: Update.
+	* ld-powerpc/tlstoc.d: Update.
+	* ld-powerpc/tlstocso.d: Update.
+	* ld-powerpc/tlstocso.r: Update.
+
+2003-06-16  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/ldsym1.d: Restrict to cris-*-*elf* and cris-*-*aout*.
+	* ld-cris/noglob1.d: Ditto.
+	* ld-cris/badgotr1.d: Pass --underscore to gas.
+
+2003-06-12  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* ld-mips-elf/elf-rel-got-n64-linux.d: New file.
+	* ld-mips-elf/elf-rel-xgot-n64-linux.d: New file.
+	* ld-mips-elf/mips-elf.exp: Use the new files for Linux.
+
+2003-06-12  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* ld-mips-elf/relax-jalr.s: Fix testsuite breakage.
+	* ld-mips-elf/relax-jalr-n32.d: Likewise.
+	* ld-mips-elf/relax-jalr-n32-shared.d: Likewise.
+	* ld-mips-elf/relax-jalr-n64.d: Likewise.
+	* ld-mips-elf/relax-jalr-n64-shared.d: Likewise.
+
+2003-06-11  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* ld-mips-elf/multi-got-1.d: Adjust addresses.
+	* ld-mips-elf/rel32-n32.d: Likewise.
+
+2003-06-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-srec/srec.exp (run_srec_test): Remove powerpc64 xfails, and
+	xfail for hppa duplicated elsewhere.
+
+2003-06-10  Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+	* ld-mips-elf/rel32-n32.d: Force big endian assembly.
+	* ld-mips-elf/rel32-o32.d: Likewise.
+	* ld-mips-elf/rel64.d: Likewise.
+
+2003-06-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elfvsb/elfvsb.exp: Run for powerpc64 too.
+	* ld-powerpc/tls.t: Update.
+	* ld-powerpc/tlsexe.d: Update.
+	* ld-powerpc/tlsexe.r: Update.
+	* ld-powerpc/tlsexetoc.d: Update.
+	* ld-powerpc/tlsexetoc.r: Update.
+	* ld-powerpc/tlsexetoc.t: Update.
+	* ld-powerpc/tlsso.d: Update.
+	* ld-powerpc/tlsso.g: Update.
+	* ld-powerpc/tlsso.r: Update.
+	* ld-powerpc/tlsso.t: Update.
+	* ld-powerpc/tlstocso.d: Update.
+	* ld-powerpc/tlstocso.g: Update.
+	* ld-powerpc/tlstocso.r: Update.
+	* ld-powerpc/tlstocso.t: Update.
+
+2003-06-03  H.J. Lu <hongjiu.lu@intel.com>
+
+	* ld-discard/extern.d: Updated.
+	* ld-discard/start.d: Likewise.
+	* ld-discard/static.d: Likewise.
+
+2003-06-03  H.J. Lu <hongjiu.lu@intel.com>
+
+	* ld-elfcomm/elfcomm.exp: Mark tests untested if compiler is
+	not available.
+
+2003-06-02  Fabrizio Gennari  <fabrizio.ge@tiscalinet.it>
+
+	* ld-cygwin: New directory.
+	* ld-cygwin/exe-export.exp: New test script.  Checks building
+	cygwin executables with an export table.
+	* ld-cygwin/testdll.def: New source file.
+	* ld-cygwin/testexe.def: New source file.
+	* ld-cygwin/testdll.c: New source file.
+	* ld-cygwin/testexe.c: New source file.
+
+2003-05-30  H.J. Lu <hongjiu.lu@intel.com>
+
+	* config/default.exp: Load tmpdir/libpath.exp.
+	(gcc_ld_flag): Set from $libpath.
+
+2003-05-27  Jason Thorpe  <thorpej@wasabisystems.com>
+
+	* ld-elf/elf.exp: Use if_elf_format.
+	* ld-elf/sec64k.exp: Likewise.
+	* ld-elfcomm/elfcomm.exp: Likewise.
+	* lib/ld-lib.exp (is_elf_format): Match hppa*64*-*-hpux*.
+
+2003-05-25  Jason Thorpe  <thorpej@wasabisystems.com>
+
+	* ld-mips-elf/mips-elf.exp: Make all NetBSD targets match as elf.
+
+2003-05-20  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-elfvsb/common.c: New file.
+	* ld-elfvsb/elfvsb.exp: Add common.
+
+2003-05-20  H.J. Lu <hongjiu.lu@intel.com>
+
+	* ld-elfvsb/sh3.c: New file.
+	* ld-elfvsb/test.c: Likewise.
+
+	* ld-elfvsb/elfvsb.exp: Add new weak hidden symbol tests.
+
+2003-05-15  H.J. Lu <hongjiu.lu@intel.com>
+
+	* config/default.exp (gcc_ld_flag): New. Make the newly built
+	linker available to gcc.
+	* lib/ld-lib.exp (default_ld_simple_link): Pass $gcc_ld_flag
+	to gcc.
+
+	* ld-elfvers/vers.exp: Use "ld_simple_link $CC" to build shared
+	libraries.
+	* ld-elfvsb/elfvsb.exp: Likewise.
+	* ld-elfweak/elfweak.exp: Likewise.
+	* ld-shared/shared.exp: Likewise.
+
+	* ld-elfvers/vers.exp: Use "-Wl,-rpath,." to build shared
+	libraries.
+	* ld-elfvsb/elfvsb.exp: Likewise.
+
+	* ld-elfvsb/elfvsb.exp: Remove xfail for powerpc-*-linux*.
+
+	* ld-elfweak/elfweak.exp: Use PIC for shared libraries.
+
+2003-05-13  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* ld-m68hc11/link-hcs12.d: New test.
+	* ld-m68hc11/link-hcs12.s: New file.
+	* ld-m68hc11/link-hc12.s: New file.
+
+2003-05-13  H.J. Lu <hongjiu.lu@intel.com>
+
+	* ld-elfweak/elfweak.exp: Fix typo.
+
+2003-05-13  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-elfvers/vers.exp: Run on sh[34]*-*-linux*.
+	* ld-elfvsb/elfvsb.exp: Likewise.
+	* ld-elfweak/elfweak.exp: Likewise.
+
+2003-05-12  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/b-fixo2.d, ld-mmix/bpo-18.d, ld-mmix/bpo-18m.d,
+	ld-mmix/loc4.d, ld-mmix/loc4m.d, ld-mmix/loc6.d, ld-mmix/loc6m.d,
+	ld-mmix/locdo-1.d, ld-mmix/sec-1.d, ld-mmix/sec-2.d,
+	ld-mmix/sec-3.d, ld-mmix/sec-4.d, ld-mmix/sec-5.d,
+	ld-mmix/sec-7m.d, ld-mmix/sec-8m.d, ld-mmix/spec802.d,
+	ld-mmix/spec803.d, ld-mmix/spec804.d, ld-mmix/spec805.d,
+	ld-mmix/spec806.d, ld-mmix/spec807.d, ld-mmix/spec808.d: Tweak for
+	objdump no longer truncating dump addresses.
+
+2003-05-09  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* ld-elfvsb/elf-offset.ld: Add .rel.eh_frame and .rela.eh_frame
+	to linker script.
+	* ld-elfvsb/elfvsb.exp (visibility_run): Add setup_xfails for s390x.
+	* ld-selective/selective.exp: Disable for s390 and s390x.
+	* ld-shared/elf-offset.ld: Add .rel.eh_frame and .rela.eh_frame
+	to linker script.
+	* ld-shared/shared.exp (shared_test): Add setup_xfails for s390x.
+	* ld-undefined/undefined.exp (checkund): Remove setup_xfail for s390x.
+
+2003-05-08  H.J. Lu <hongjiu.lu@intel.com>
+
+	* ld-elfvers/vers.exp: Add vers27d4 and vers27d5 to test
+	versioned reference for hidden symbol.
+
+	* ld-elfvers/vers27d4.dsym: New file.
+	* ld-elfvers/vers27d4.ver: Likewise.
+
+2003-05-07  H.J. Lu <hongjiu.lu@intel.com>
+
+	* ld-elfvers/vers27d3.c (__start): New.
+	(start): New.
+
+2003-05-07  H.J. Lu <hongjiu.lu@intel.com>
+
+	* ld-elfvers/vers.exp (build_binary): Support build exeutable.
+	(build_binary): Renamed from ...
+	(build_vers_lib): This.
+	(build_vers_lib_no_pic): Updated.
+	(build_vers_lib_pic): Likewise.
+	Add vers27d1, vers27d2 and vers27d3 to test versioned
+	definition for hidden symbol referenced by a DSO.
+
+	* ld-elfvers/vers27d.dsym: New file.
+	* ld-elfvers/vers27d.sym: Likewise.
+	* ld-elfvers/vers27d.ver: Likewise.
+	* ld-elfvers/vers27d1.c: Likewise.
+	* ld-elfvers/vers27d2.c: Likewise.
+	* ld-elfvers/vers27d3.c: Likewise.
+
+2003-05-07  Andreas Schwab  <schwab@suse.de>
+
+	* ld-elfvsb/elfvsb.exp: Run dump tests even when cross
+	compiling.
+
+2003-05-06  Alexandre Oliva  <aoliva@redhat.com>
+
+	* config/default.exp (gcc_gas_flags): Force ABI to n32 on
+	mips64-linux.
+	* ld-elf/merge.d: Xfail on mips64*-linux-gnu*.
+	* ld-mips-elf/mips-elf-flags.exp (ldemul): Set to o32-compatible
+	on mips-sgi-irix6*, mips64-linux-gnu and mips64el-linux-gnu.
+	(good_combination, bad_combination): Use it.
+	Add -32 or -mabi=o64 wherever the ABI was formerly implied.
+
+2003-05-06  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvers/vers.exp (objdump_versionstuff): Support comment
+	in expected version file.
+
+	* ld-elfvers/vers25b.c: Add a line of comment.
+	* ld-elfvers/vers25b.dsym: Likwise.
+	* ld-elfvers/vers25b.ver: Likwise.
+	* ld-elfvers/vers26b.dsym: Likwise.
+	* ld-elfvers/vers26b.ver: Likwise.
+	* ld-elfvers/vers27b.dsym: Likwise.
+	* ld-elfvers/vers27b.ver: Likwise.
+	* ld-elfvers/vers27c.c: Likwise.
+	* ld-elfvers/vers27c.dsym: Likwise.
+	* ld-elfvers/vers27c.ver: Likwise.
+
+2003-05-04  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvsb/main.c: Updated.
+	* ld-elfvsb/sh1.c: Likewise.
+
+2003-05-04  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvers/vers18.dsym: Updated for weak definiton change.
+	* ld-elfvers/vers18.ver: Likewise.
+	* ld-elfvers/vers19.ver: Likewise.
+	* ld-elfweak/dsowdata.dsym: Likewise.
+	* ld-elfweak/elfweak.exp: Likewise.
+	* ld-elfweak/weakdata.dsym: Likewise.
+
+	* ld-elfweak/elfweak.exp: Remove xfail.
+
+2003-05-04  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-mips-elf/multi-got-1.d: Force into big-endian mode.
+	Turn relocation offsets into regexps.
+
+2003-05-03  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvers/vers.exp: Add vers27a, vers27b, vers27c1 and
+	vers27c2 to test versioned definition vs. hidden definition in
+	different files.
+
+	* ld-elfvers/vers27a.c: New file.
+	* ld-elfvers/vers27a.dsym: Likewise.
+	* ld-elfvers/vers27a.map: Likewise.
+	* ld-elfvers/vers27a.ver: Likewise.
+	* ld-elfvers/vers27b.c: Likewise.
+
+	* ld-elfvers/vers27b.dsym: New empty file.
+	* ld-elfvers/vers27b.ver: Likwise.
+	* ld-elfvers/vers27c.c: Likwise.
+	* ld-elfvers/vers27c.dsym: Likwise.
+	* ld-elfvers/vers27c.ver: Likwise.
+
+2003-05-02  Nick Clifton  <nickc@redhat.com>
+
+	* ld-xstormy16: New directory.
+	* ld-xstormy16/xstormy16.exp: New test script.
+	* ld-xstormy16/pcrel.s: Test assembler source file.
+	* ld-xstormy16/external.s: Test assembler source file.
+	* ld-xstormy16/pcrel.d: Test expected disassembly.
+
+2003-05-02  Andreas Jaeger  <aj@suse.de>
+
+	* ld-elfvers/vers.exp (build_exec): Disable vers26b3 on x86-64-linux.
+
+2003-04-29  H.J. Lu <hjl@gnu.org>
+
+	* ld-ia64/tlsbin.dd: Updated.
+	* ld-ia64/tlsbin.rd: Likewise.
+	* ld-ia64/tlsbin.sd: Likewise.
+	* ld-ia64/tlsbin.td: Likewise.
+	* ld-ia64/tlspic.rd: Likewise.
+	* ld-ia64/tlspic.sd: Likewise.
+	* ld-ia64/tlspic.td: Likewise.
+
+2003-04-29  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* ld-selective/3.cc (start): New function.
+	* ld-selective/4.cc: Likewise.
+	* ld-selective/5.cc: Likewise.
+
+2003-04-28  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvers/vers.exp (picflag): Set PIC flag for compiler.
+	(build_vers_lib): Support PIC.
+	(build_vers_lib_no_pic): New. Change all calls to build_vers_lib
+	to build_vers_lib_no_pic.
+	(build_vers_lib_pic): New.
+	Add tests vers26a, vers26b1, vers26b2 and vers26b3 for versioned
+	definition vs. normal definition in different files.
+
+	* ld-elfvers/vers26a.c: New file.
+	* ld-elfvers/vers26a.dsym: Likewise.
+	* ld-elfvers/vers26a.map: Likewise.
+	* ld-elfvers/vers26a.ver: Likewise.
+	* ld-elfvers/vers26b.c: Likewise.
+
+	* ld-elfvers/vers26b.dsym: New empty file.
+	* ld-elfvers/vers26b.ver: Likewise.
+
+2003-04-27  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvsb/elfvsb.dat: Updated.
+	* ld-elfvsb/elfvsb.exp: Likewise.
+	* ld-elfvsb/main.c: Likewise.
+	* ld-elfvsb/sh1.c: Likewise.
+	* ld-elfvsb/sh2.c: Likewise.
+
+2003-04-26  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* ld-m68hc11/bug-3331.d: New test.
+	* ld-m68hc11/bug-3331.s: New file.
+
+2003-04-25  Nick Clifton <nickc@redhat.com>
+	    J"orn Rennecke <joern.rennecke@superh.com>
+
+	* lib/ld-lib.exp (big_or_little_endian): Also check for -mb and -ml.
+
+2003-04-24  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* ld-elfcomm/elfcomm.exp: Allow symbols to have '_' prepended.
+
+2003-04-23  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/tlsbin-1.d, ld-sh/tlsbin-2.d, ld-sh/tlsbin-3.d,
+	ld-sh/tlstpoff-1.d, ld-sh/tlstpoff-2.d: Update for removing
+	unnecessary TLS relocs.
+
+2003-04-23  J"orn Rennecke <joern.rennecke@superh.com>
+
+	* ld-sh/sh64/crange3-cmpct.rd (Machine): Change to refer to SuperH.
+	* ld-sh/sh64/crange3-media.rd (Machine): Likewise.
+
+2003-04-23  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvers/vers.exp (objdump_dynsymstuff): Support empty
+	files.
+	(objdump_versionstuff): Likewise.
+	Add tests vers25a, vers25b1 and vers25b2 for versioned
+	definition vs. normal definition in different files.
+
+	* ld-elfvers/vers25a.c: New file.
+	* ld-elfvers/vers25a.dsym: Likewise.
+	* ld-elfvers/vers25a.map: Likewise.
+	* ld-elfvers/vers25a.ver: Likewise.
+
+	* ld-elfvers/vers25b.c: New empty file.
+	* ld-elfvers/vers25b.dsym: Likewise.
+	* ld-elfvers/vers25b.ver: Likewise.
+
+2003-04-22  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfcomm/elfcomm.exp: Support 64bit targets.
+
+2003-04-21  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* ld-m68hc11/far-hc11.s: New file.
+	* ld-m68hc11/far-hc11.d: New test for HC11 trampoline generation.
+	* ld-m68hc11/far-hc12.s: New file.
+	* ld-m68hc11/far-hc12.d: New test for HC12 trampoline generation.
+	* ld-m68hc11/far-hc12.ld: New file.
+
+2003-04-15  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfcom/elfcom.exp: Fix a typo.
+
+2003-04-14  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfcom: New directory.
+	* ld-elfcom/elfcom.exp: New file: Test alignment of common symbols
+	under ELF.
+	* ld-elfcom/common1a.c: New file: Test source code.
+	* ld-elfcom/common1b.c: New file: Test source code.
+
+2003-04-15  Rohit Kumar Srivastava <rohits@kpitcummins.com>
+
+	* ld-sh/sh64/crange3-cmpct.rd: Replace occurrances of 'Hitachi'
+	with 'Renesas'.
+	* ld-sh/sh64/crange3-media.rd: Likewise.
+
+2002-04-13  Daniel Jacobowitz  <drow@mvista.com>
+
+	* ld-discard/extern.s, ld-discard/start.s, ld-discard/static.s,
+	ld-sh/refdbg.s: Add leading 0 to .debug_info to prevent parsing it
+	for error messages.
+
+2003-04-10  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-mips-elf/elf-rel-got-n32.d,
+	ld-mips-elf/elf-rel-got-n64.d, ld-mips-elf/elf-rel-xgot-n32.d,
+	ld-mips-elf/elf-rel-xgot-n64.d: New.
+	* ld-mips-elf/mips-elf.exp (hasn32): Define as condition for
+	new tests to run.
+
+2003-04-04  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* ld-m68hc11/bug-1417.d: Update to take into account jsr->bsr relax.
+
+2003-04-02  Bob Wilson  <bob.wilson@acm.org>
+
+	* ld-xtensa/coalesce.exp: Skip if target is not xtensa-*-*.
+	* ld-xtensa/lcall.exp: Likewise.
+
+2003-04-01  Bob Wilson  <bob.wilson@acm.org>
+
+	* ld-elf/merge.d: xfail xtensa-*-*.
+	* ld-scripts/crossref.exp: Add -mtext-section-literals to CFLAGS
+	for Xtensa targets.
+	* ld-srec/srec.exp: Add -no-relax flag for Xtensa targets.
+	* ld-xtensa/coalesce1.s: New file.
+	* ld-xtensa/coalesce2.s: Likewise.
+	* ld-xtensa/coalesce.exp: Likewise.
+	* ld-xtensa/coalesce.t: Likewise.
+	* ld-xtensa/lcall1.s: Likewise.
+	* ld-xtensa/lcall2.s: Likewise.
+	* ld-xtensa/lcall.exp: Likewise.
+	* ld-xtensa/lcall.t: Likewise.
+
+2003-03-25  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-mips-elf/mips-elf.exp: Added...
+	* ld-mips-elf/relax-jalr.s, ld-mips-elf/relax-jalr-n32.d,
+	ld-mips-elf/relax-jalr-n32-shared.d, ld-mips-elf/relax-jalr-n64.d,
+	ld-mips-elf/relax-jalr-n64-shared.d: New tests.
+
+2003-03-11  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-mips-elf/mips-elf.exp (linux_gnu): New variable.  Add:
+	* ld-mips-elf/rel32-o32.d, ld-mips-elf/rel32-n32.d,
+	ld-mips-elf/rel64.d, ld-mips-elf/rel32.s, ld-mips-elf/rel64.s: New
+	tests.
+
+2003-03-11  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsso.r: Adjust for corrected zero symbol index relocs.
+	* ld-powerpc/tlsso32.r: Likewise.
+
+2003-02-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexe.d: Update for changed handling of invalid LD
+	relocs.
+	* ld-powerpc/tlsexe.g: Likewise.
+	* ld-powerpc/tlsexe.r: Likewise.
+	* ld-powerpc/tlsexe.t: Likewise.
+
+	* ld-powerpc/tls32.s: New file.
+	* ld-powerpc/tlslib32.s: New file.
+	* ld-powerpc/tls32.d: New file.
+	* ld-powerpc/tls32.g: New file.
+	* ld-powerpc/tls32.t: New file.
+	* ld-powerpc/tlsexe32.d: New file.
+	* ld-powerpc/tlsexe32.g: New file.
+	* ld-powerpc/tlsexe32.r: New file.
+	* ld-powerpc/tlsexe32.t: New file.
+	* ld-powerpc/tlsso32.d: New file.
+	* ld-powerpc/tlsso32.g: New file.
+	* ld-powerpc/tlsso32.r: New file.
+	* ld-powerpc/tlsso32.t: New file.
+	* ld-powerpc/powerpc.exp: Run new tests.
+
+2003-02-18  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlsexe.g: Update for 2003-02-14 elf64-ppc.c change.
+
+2003-02-10  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-shared/shared.exp: Run on s390*-*-linux* and x86_64-*-linux* too.
+	xfail tests linking non-pic code into shared libs on x86_64-*-linux*.
+	* ld-elfvsb/elfvsb.exp: Likewise.
+	* ld-elfvers/vers.exp: Likewise.  Add vers24a, vers24b and vers24c
+	tests.
+	* ld-elfvers/vers3.ver: Allow VERS_2.0 to come before GLIBC_*
+	version.
+	* ld-elfvers/vers19.ver: Likewise.
+	* ld-elfvers/vers24a.c: New test.
+	* ld-elfvers/vers24b.c: New test.
+	* ld-elfvers/vers24c.c: New test.
+	* ld-elfvers/vers24.map: New test.
+	* ld-elfvers/vers24.rd: New test.
+	* lib/ld-lib.exp (run_ld_link_tests): Add optional 7th argument
+	cflags.  If source files have .c extension, compile them first.
+
+2003-02-10  Kaz kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/tlstpoff-1.d: New.
+	* ld-sh/tlstpoff-2.d: New.
+	* ld-sh/tlstpoff1.s: New.
+	* ld-sh/tlstpoff2.s: New.
+
+2003-02-09  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/tlslib.s: Give .__tls_get_addr function type.
+	* ld-powerpc/tlsexe.d: Update for changed handling of (invalid) ld var
+	in dynamic lib.
+	* ld-powerpc/tlsexe.g: Likewise.
+	* ld-powerpc/tlsexe.r: Likewise.
+	* ld-powerpc/tlsexe.t: Likewise.
+	* ld-powerpc/tlsexetoc.d: Likewise.
+	* ld-powerpc/tlsexetoc.g: Likewise.
+	* ld-powerpc/tlsexetoc.r: Likewise.
+	* ld-powerpc/tlsexetoc.t: Likewise.
+
+2003-02-05  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/powerpc.exp (supports_ppc64): New.
+	(ppcelftests): Force 32 bit mode.
+	(ppc64elftests): New.
+	* ld-powerpc/tls.d: New.
+	* ld-powerpc/tls.g: New.
+	* ld-powerpc/tls.s: New.
+	* ld-powerpc/tls.t: New.
+	* ld-powerpc/tlsexe.d: New.
+	* ld-powerpc/tlsexe.g: New.
+	* ld-powerpc/tlsexe.r: New.
+	* ld-powerpc/tlsexe.t: New.
+	* ld-powerpc/tlsexetoc.d: New.
+	* ld-powerpc/tlsexetoc.g: New.
+	* ld-powerpc/tlsexetoc.r: New.
+	* ld-powerpc/tlsexetoc.t: New.
+	* ld-powerpc/tlslib.s: New.
+	* ld-powerpc/tlsso.d: New.
+	* ld-powerpc/tlsso.g: New.
+	* ld-powerpc/tlsso.r: New.
+	* ld-powerpc/tlsso.t: New.
+	* ld-powerpc/tlstoc.d: New.
+	* ld-powerpc/tlstoc.g: New.
+	* ld-powerpc/tlstoc.s: New.
+	* ld-powerpc/tlstoc.t: New.
+	* ld-powerpc/tlstocso.d: New.
+	* ld-powerpc/tlstocso.g: New.
+	* ld-powerpc/tlstocso.r: New.
+	* ld-powerpc/tlstocso.t: New.
+
+2003-01-27  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-mips-elf/multi-got-1.d: New.
+	* ld-mips-elf/multi-got-1-1.s: New.
+	* ld-mips-elf/multi-got-1-2.s: New.
+	* ld-mips-elf/mips-elf.exp (elf): mips*-*-irix* is elf.
+	Run multi-got-1.
+
+2003-01-25  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-sparc/sparc.exp: New.
+	* ld-sparc/tlsg32.s: New test.
+	* ld-sparc/tlsg32.sd: Likewise.
+	* ld-sparc/tlsg64.s: Likewise.
+	* ld-sparc/tlsg64.sd: Likewise.
+	* ld-sparc/tlslib.s: Likewise.
+	* ld-sparc/tlsnopic.s: Likewise.
+	* ld-sparc/tlspic.s: Likewise.
+	* ld-sparc/tlssunbin32.dd: Likewise.
+	* ld-sparc/tlssunbin32.rd: Likewise.
+	* ld-sparc/tlssunbin32.s: Likewise.
+	* ld-sparc/tlssunbin32.sd: Likewise.
+	* ld-sparc/tlssunbin32.td: Likewise.
+	* ld-sparc/tlssunbin64.dd: Likewise.
+	* ld-sparc/tlssunbin64.rd: Likewise.
+	* ld-sparc/tlssunbin64.s: Likewise.
+	* ld-sparc/tlssunbin64.sd: Likewise.
+	* ld-sparc/tlssunbin64.td: Likewise.
+	* ld-sparc/tlssunbinpic32.s: Likewise.
+	* ld-sparc/tlssunbinpic64.s: Likewise.
+	* ld-sparc/tlssunnopic32.dd: Likewise.
+	* ld-sparc/tlssunnopic32.rd: Likewise.
+	* ld-sparc/tlssunnopic32.s: Likewise.
+	* ld-sparc/tlssunnopic32.sd: Likewise.
+	* ld-sparc/tlssunnopic64.dd: Likewise.
+	* ld-sparc/tlssunnopic64.rd: Likewise.
+	* ld-sparc/tlssunnopic64.s: Likewise.
+	* ld-sparc/tlssunnopic64.sd: Likewise.
+	* ld-sparc/tlssunpic32.dd: Likewise.
+	* ld-sparc/tlssunpic32.rd: Likewise.
+	* ld-sparc/tlssunpic32.s: Likewise.
+	* ld-sparc/tlssunpic32.sd: Likewise.
+	* ld-sparc/tlssunpic32.td: Likewise.
+	* ld-sparc/tlssunpic64.dd: Likewise.
+	* ld-sparc/tlssunpic64.rd: Likewise.
+	* ld-sparc/tlssunpic64.s: Likewise.
+	* ld-sparc/tlssunpic64.sd: Likewise.
+	* ld-sparc/tlssunpic64.td: Likewise.
+
+2003-01-24  Martin Schwidefsky  <schwidefsky@de.ibm.com>
+
+	* ld-s390/s390.exp: New file.
+	* ld-s390/tlsbin_64.dd: New file.
+	* ld-s390/tlsbin_64.rd: New file.
+	* ld-s390/tlsbin_64.s: New file.
+	* ld-s390/tlsbin_64.sd: New file.
+	* ld-s390/tlsbin_64.td: New file.
+	* ld-s390/tlsbin.dd: New file.
+	* ld-s390/tlsbinpic_64.s: New file.
+	* ld-s390/tlsbinpic.s: New file.
+	* ld-s390/tlsbin.rd: New file.
+	* ld-s390/tlsbin.s: New file.
+	* ld-s390/tlsbin.sd: New file.
+	* ld-s390/tlsbin.td: New file.
+	* ld-s390/tlslib_64.s: New file.
+	* ld-s390/tlslib.s: New file.
+	* ld-s390/tlspic1_64.s: New file.
+	* ld-s390/tlspic1.s: New file.
+	* ld-s390/tlspic2_64.s: New file.
+	* ld-s390/tlspic2.s: New file.
+	* ld-s390/tlspic_64.dd: New file.
+	* ld-s390/tlspic_64.rd: New file.
+	* ld-s390/tlspic_64.sd: New file.
+	* ld-s390/tlspic_64.td: New file.
+	* ld-s390/tlspic.dd: New file.
+	* ld-s390/tlspic.rd: New file.
+	* ld-s390/tlspic.sd: New file.
+	* ld-s390/tlspic.td: New file.
+
+2003-01-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-alpha/tlsbin.sd: Cope with truncated address in data dumps.
+	* ld-alpha/tlsbin.td: Likewise.
+	* ld-alpha/tlsbinr.sd: Likewise.
+
+2003-01-21  Richard Henderson  <rth@redhat.com>
+
+	* ld-alpha/alpha.exp: New.
+	* ld-alpha/align.s: New.
+	* ld-alpha/tlsbin.dd: New.
+	* ld-alpha/tlsbin.rd: New.
+	* ld-alpha/tlsbin.s: New.
+	* ld-alpha/tlsbin.sd: New.
+	* ld-alpha/tlsbin.td: New.
+	* ld-alpha/tlsbinpic.s: New.
+	* ld-alpha/tlsbinr.dd: New.
+	* ld-alpha/tlsbinr.rd: New.
+	* ld-alpha/tlsbinr.sd: New.
+	* ld-alpha/tlsg.s: New.
+	* ld-alpha/tlsg.sd: New.
+	* ld-alpha/tlslib.s: New.
+	* ld-alpha/tlspic.dd: New.
+	* ld-alpha/tlspic.rd: New.
+	* ld-alpha/tlspic.sd: New.
+	* ld-alpha/tlspic.td: New.
+	* ld-alpha/tlspic1.s: New.
+	* ld-alpha/tlspic2.s: New.
+
+2003-01-20  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-srec/srec.exp (run_srec_test): Pass --traditional-format to ld.
+
+2003-01-18  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-ia64/tlspic1.s: Add tests for IE in shared libraries.
+	* ld-ia64/tlspic.rd: Adjust.
+	* ld-ia64/tlspic.dd: Adjust.
+	* ld-ia64/tlspic.sd: Adjust.
+
+2003-01-16  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-ia64/ia64.exp: New.
+	* ld-ia64/tlsbin.dd: New test.
+	* ld-ia64/tlsbinpic.s: New test.
+	* ld-ia64/tlsbin.rd: New test.
+	* ld-ia64/tlsbin.s: New test.
+	* ld-ia64/tlsbin.sd: New test.
+	* ld-ia64/tlsbin.td: New test.
+	* ld-ia64/tlsg.s: New test.
+	* ld-ia64/tlsg.sd: New test.
+	* ld-ia64/tlslib.s: New test.
+	* ld-ia64/tlspic1.s: New test.
+	* ld-ia64/tlspic2.s: New test.
+	* ld-ia64/tlspic.dd: New test.
+	* ld-ia64/tlspic.rd: New test.
+	* ld-ia64/tlspic.sd: New test.
+	* ld-ia64/tlspic.td: New test.
+
+2003-01-02  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-mips-elf/mips-elf-flags.exp: Add -mips4 to a -mgp64 test.
+
+2003-01-02  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-mips-elf/jr.s: New file.
+	* ld-mips-elf/mips-elf-flags.exp: New test.
+
+2002-12-18  Ralf Habacker  <ralf.habacker@freenet.de>
+
+	* ld-auto-import: New directory.
+	* ld-auto-import/auto-import.exp: Test the auto importing direct
+	from a dll functionality.
+	* ld-auto-import/client.c: Source code for test.
+	* ld-auto-import/dll.c: Likewise.
+
+2002-12-12  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-mips-elf/mips-elf.exp: Remove branch-misc-2 test.
+	* ld-mips-elf/branch-misc-2.d: Removed.
+
+2002-12-10  Jason Thorpe  <thorpej@wasabisystems.com>
+
+	* lib/ld-lib.exp (is_elf_format): Match NetBSD ELF targets.
+
+2002-12-03  Nick Clifton  <nickc@redhat.com>
+
+	* ld-powerpc/powerpc.exp (ppcelftests): Add apuinfo merging
+	test.
+	* ld-powerpc/apuinfo1.s: New assembler source file.
+	* ld-powerpc/apuinfo2.s: New assembler source file.
+	* ld-powerpc/apuinfo.rd: New expected output file.
+
+2002-12-01  Stephane Carrez  <stcarrez@nerim.fr>
+
+	Fix PR savannah/1417:
+	* ld-m68hc11/bug-1417.s: New test.
+	* ld-m68hc11/bug-1417.d: Likewise.
+
+2002-11-28  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-i386/tlsnopic.rd: Change NOTYPE to TLS for UND sg* symbols.
+
+2002-11-28  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/refdbg-0-dso.d: New test.
+	* ld-sh/refdbg-1.d: Likewise.
+	* ld-sh/refdbg.s: Likewise.
+	* ld-sh/refdbglib.s: Likewise.
+
+2002-11-22  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/elf.exp: Remove sec64k test.
+	* ld-elf/sec64k.exp: Reinstate.
+
+2002-11-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elf/elf.exp: Renamed from sec64k.exp.  Add test_list loop.
+	* ld-elf/merge.s: New file.
+	* ld-elf/merge.d: New file.
+	* ld-elf/merge.ld: New file.
+
+2002-11-18  Svein E. Seldal  <Svein.Seldal@solidas.com>
+
+	* ld-scripts/script.exp: Setup for tic4x testcase
+
+2002-11-15  Nick Clifton  <nickc@redhat.com>
+
+	* ld-h8300: New directory.
+	* ld-h8300/h8300.exp: New expect script.  Only run tests for h8300
+	targets.
+	* ld-h8300/relax.s: New assembler source file.
+	* ld-h8300/relax.d: New expected output file.
+
+2002-11-11  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-elf/sec64k.exp: New test.
+	* lib/ld-lib.exp (run_dump_test): Don't prepend "$srcdir/$subdir/"
+	to a source file starting with "/".
+
+2002-11-10  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/local1.d, ld-mmix/local3.d, ld-mmix/local5.d,
+	ld-mmix/local7.d: Tweak for change in readelf output.
+
+2002-11-09  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-elfvsb/define.s: Avoid use of @ in .type directive.
+
+2002-11-07  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/expdyn6.d, ld-cris/weakref2.d, ld-cris/expdyn7.d,
+	ld-cris/nodyn5.d, ld-cris/expdyn5.d: New tests.
+
+2002-11-07  Nick Clifton  <nickc@redhat.com>
+
+	* ld-fastcall/fastcall.exp: Only run tests for PE type x86
+	targets.
+
+2002-11-07  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/rd-sh.exp: Set asflags_save always.
+
+2002-11-07  Casper S. Hornstrup  <chorns@users.sourceforge.net>
+
+	* ld-fastcall: New directory for testing fastcall support.
+	* ld-fastcall/export.s: New file for testing fastcall symbol
+	handling.
+	* ld-fastcall/import.s: Likewise.
+	* ld-fastcall/fastcall.exp: Likewise.
+
+2002-11-03  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/rd-sh.exp: Add -isa=SHcompact to ASFLAGS for SH-5.
+	* ld-sh/tlsbin-1.d: Handle GOT_BIAS appropriately for SH-5.
+	* ld-sh/tlspic-1.d: Likewise.
+	* ld-sh/tlspic-2.d: Likewise.
+	* ld-sh/tlsbin-2.d: Likewise. Make it robust for the symbols
+	defined by the linker scripts.
+
+2002-10-14  Stephane Carrez  <stcarrez@nerim.fr>
+
+	* ld-m68hc11/m68hc11.exp: Specific tests for 68HC11/68HC12.
+	* ld-m68hc11/adj-jump.d: New test for linker relaxation.
+	* ld-m68hc11/adj-jump.s: Likewise.
+	* ld-m68hc11/adj-brset.s: Likewise.
+	* ld-m68hc11/adj-brset.d: Likewise.
+	* ld-m68hc11/relax-direct.s: Likewise.
+	* ld-m68hc11/relax-direct.d: Likewise.
+	* ld-m68hc11/relax-group.s: Likewise.
+	* ld-m68hc11/relax-group.d: Likewise.
+	* ld-m68hc11/bug-1403.d: Likewise.
+	* ld-m68hc11/bug-1403.s: Likewise.
+
+2002-10-14  Stephen Clarke <stephen.clarke@superh.com>
+	* ld-sh/ld-r-1.d: Disable for sh64*-*-linux*.
+	* ld-sh/sh64/sh64.exp: Likewise.
+	* ld-sh/sh.exp: Disable relaxing tests for sh64*-*-linux*.
+	* ld-sh/sh64/abi32.sd: Adjust expected output to include
+	sh64*-*-linux* formats too.
+	* ld-sh/sh64/relax.exp: Add emul32 variable to hold target
+	emulation, and set it appropriately for sh*-*-linux*.
+	* ld-sh/sh64/relfail.exp: Add variables to hold target
+	emulation, output format, start symbol, and whether target
+	supports 64-bit ABI.  Set appropriately for sh*-*-linux*.
+
+2002-10-12  H.J. Lu  (hjl@gnu.org)
+
+	* ld-discard/extern.d: Remove $srcdir/$subdir/.
+	* ld-discard/start.d: Likewise.
+	* ld-discard/static.d: Likewise.
+	* ld-linkonce/zeroehl32.d: Likewise.
+	* ld-selective/keepdot.d: Likewise.
+	* ld-selective/keepdot0.d: Likewise.
+
+2002-10-11  Kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/rd-sh.exp: If the test matches *-dso.d, copy the output
+	of linker to the file tmpdir/*-dso.so.
+	* ld-sh/tlsbin.s, ld-sh/tlsbinpic.s, ld-sh/tlslib.s: New.
+	* ld-sh/tlsbin-0-dso.d: New.
+	* ld-sh/tlsbin-1.d: New.
+	* ld-sh/tlsbin-2.d: New.
+	* ld-sh/tlsbin-3.d: New.
+	* ld-sh/tlsbin-4.d: New.
+	* ld-sh/tlspic1.s, ld-sh/tlspic2.s: New.
+	* ld-sh/tlspic-1.d: New.
+	* ld-sh/tlspic-2.d: New.
+	* ld-sh/tlspic-3.d: New.
+	* ld-sh/tlspic-4.d: New.
+
+2002-10-10  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-i386/combreloc.s: New test.
+	* ld-i386/combreloc.d: New test.
+	* ld-i386/i386.exp (i386tests): Add it.
+
+2002-10-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-i386/i386.exp (reloc): Turn off combreloc.
+	* ld-i386/reloc.d: Likewise.
+	* ld-powerpc/powerpc.exp: Likewise.
+	* ld-powerpc/reloc.d: Likewise.
+
+2002-10-03  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvers/vers21.c (_old_foobar): Initialized to -1 for gcc
+	3.x.
+
+2002-10-03  Chris Demetriou  <cgd@broadcom.com>
+
+	* ld-mips-elf/branch-misc-1.d: Link at 0x500000 and use -N, to be
+	more compatible with non-embedded targets.
+	* ld-mips-elf/branch-misc-2.d: Likewise.
+
+	* ld-mips-elf/mips-elf.exp: Clean up some comments about embedded
+	PIC tests.
+	(elf): New variable, to control whether generic ELF tests are run.
+	(embedded_elf): New variable, to control whether ELF tests
+	requiring embedded PIC or embedded relocs are run.
+
+2002-10-02  Stephen Clarke <stephen.clarke@superh.com>
+
+	* ld-sh/sh64/gotplt.d, ld-sh/sh64/gotplt.map,
+	ld-sh/sh64/gotplt.s: New test.
+
+2002-10-02  Stephen Clarke <stephen.clarke@superh.com>
+	* ld-sh/sh64/cmpct1.sd : Fix linked file name.
+	* ld-sh/sh64/crange3.dd: Likewise.
+
+2002-10-01  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-i386/i386.exp: Add tlsindntpoff test.
+	* ld-i386/tlsindntpoff.s: New test.
+	* ld-i386/tlsindntpoff.dd: New test.
+
+2002-10-01  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-x86-64/tlspic1.s: Change TLSGD sequences.
+	* ld-x86-64/tlsbinpic.s: Likewise.
+	* ld-x86-64/tlspic.dd: Adjust.
+
+2002-10-01  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-i386/i386.exp: Add tlsg test.
+	* ld-i386/tlsg.s: New test.
+	* ld-i386/tlsg.sd: New test.
+	* ld-i386/tlsbin.dd: Change LD into LD -> LE in comments.
+	* ld-i386/tlsbinpic.s: Likewise.
+	* ld-x86-64/x86-64.exp: Add tlsg test.
+	* ld-x86-64/tlsg.s: New test.
+	* ld-x86-64/tlsg.sd: New test.
+	* ld-x86-64/tlsbin.dd: Change LD into LD -> LE in comments.
+	* ld-x86-64/tlsbinpic.s: Likewise.
+
+2002-09-30  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/powerpc.exp: Restrict to 32 bit ELF.
+
+2002-09-30  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-powerpc/reloc.s, ld-powerpc/reloc.d: New.
+	* ld-powerpc/powerpc.exp: New.
+
+	* ld-i386/reloc.s, ld-i386/reloc.d: New.
+	* ld-i386/i386.exp: Run new test.
+
+2002-09-27  Jakub Jelinek  <jakub@redhat.com>
+
+	* lib/ld-lib.exp (run_ld_link_tests): Add.
+	* ld-sh/sh64/sh64.exp (run_ld_link_tests, regexp_diff,
+	file_contents): Remove.
+	(sh64tests): Add 6th field to the tests array.
+	* ld-i386/i386.exp (run_ld_link_tests): Remove.
+	* ld-x86-64/x86-64.exp: New.
+	* ld-x86-64/tlsbin.dd: New test.
+	* ld-x86-64/tlsbinpic.s: New test.
+	* ld-x86-64/tlsbin.rd: New test.
+	* ld-x86-64/tlsbin.s: New test.
+	* ld-x86-64/tlsbin.sd: New test.
+	* ld-x86-64/tlsbin.td: New test.
+	* ld-x86-64/tlslib.s: New test.
+	* ld-x86-64/tlspic1.s: New test.
+	* ld-x86-64/tlspic2.s: New test.
+	* ld-x86-64/tlspic.dd: New test.
+	* ld-x86-64/tlspic.rd: New test.
+	* ld-x86-64/tlspic.sd: New test.
+	* ld-x86-64/tlspic.td: New test.
+
+2002-09-21  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-undefined/undefined.exp: Adjust function test.
+
+2002-09-20  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-i386/i386.exp: Only run tests on ELF targets.
+
+2002-09-19  Jakub Jelinek  <jakub@redhat.com>
+
+	* ld-i386/i386.exp: New.
+	* ld-i386/tlsbin.dd: New test.
+	* ld-i386/tlsbinpic.s: New test.
+	* ld-i386/tlsbin.rd: New test.
+	* ld-i386/tlsbin.s: New test.
+	* ld-i386/tlsbin.sd: New test.
+	* ld-i386/tlsbin.td: New test.
+	* ld-i386/tlslib.s: New test.
+	* ld-i386/tlsnopic1.s: New test.
+	* ld-i386/tlsnopic2.s: New test.
+	* ld-i386/tlsnopic.dd: New test.
+	* ld-i386/tlsnopic.rd: New test.
+	* ld-i386/tlsnopic.sd: New test.
+	* ld-i386/tlspic1.s: New test.
+	* ld-i386/tlspic2.s: New test.
+	* ld-i386/tlspic.dd: New test.
+	* ld-i386/tlspic.rd: New test.
+	* ld-i386/tlspic.sd: New test.
+	* ld-i386/tlspic.td: New test.
+
+2002-09-18  Chris Demetriou  <cgd@broadcom.com>
+
+	* ld-mips-elf/branch-misc-1.d: New file.
+	* ld-mips-elf/branch-misc-2.d: New file.
+	* ld-mips-elf/mips-elf.exp: Run new tests.
+
+2002-09-05  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-sh/sh64/cmpct1.xd: Adjust for lack of abs section sym.
+	* ld-sh/sh64/crange3-cmpct.rd: Likewise.
+	* ld-sh/sh64/crange3-media.rd: Likewise.
+	* ld-sh/sh64/crange3.rd: Likewise.
+
+2002-08-31  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/bpo-10.d: Tweak for change in symbols handling.
+	* ld-mmix/bpo-11.d: Ditto.
+
+	* ld-mmix/b-nosym.d: Adjust for changed output for absence of
+	symbols.
+
+	* ld-mmix/sec-7m.d: Rename tested section from .debug_info to
+	.di.
+	* ld-mmix/sec-7a.s, ld-mmix/sec-7b.s, ld-mmix/sec-7c.s,
+	ld-mmix/sec-7d.s, ld-mmix/sec-7e.s: Ditto.
+
+2002-08-28  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-discard/discard.exp: xfail m6812.
+	* ld-scripts/map-address.d: Adjust for extras emitted by pe targets.
+
+2002-08-27  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-mmix/b-nosym.d: Revert last change.
+
+2002-08-26  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-mmix/b-nosym.d: Adjust for "no symbols" on stdout.
+
+2002-08-23  Stephen Clarke <stephen.clarke@superh.com>
+
+	* ld-sh/sh64/rd-sh64.exp: New framework file.
+	* ld-sh/sh64/init-cmpct.d, ld-sh/sh64/init-media.d,
+	ld-sh/sh64/init64.d, ld-sh/sh64/init.s: New tests for
+	correct setting of ISA bit for init and fini entry-points.
+
+2002-08-16  Stephen Clarke <stephen.clarke@superh.com>
+
+	* ld-sh/sh64/sh64.exp: Add dlsection.
+	* ld-sh/sh64/dlsection-1.s, ld-sh/sh64/dlsection.sd: New.
+
+2002-08-16  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-discard/discard.exp: xfail targets using generic linker.
+	* ld-discard/extern.d: Allow "data" to be reduced to a section sym.
+
+2002-08-15  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/libdso-4.d, ld-cris/undef1.d: New test.
+
+2002-08-13  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvers/vers.exp: Add vers23c and vers23d.
+
+	* ld-elfvers/vers23c.ver: New.
+	* ld-elfvers/vers23d.dsym: New.
+
+2002-08-12  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvers/vers.exp: Add vers23.
+
+	* ld-elfvers/vers23.c: New.
+	* ld-elfvers/vers23.dsym: New.
+	* ld-elfvers/vers23.ver: New.
+	* ld-elfvers/vers23a.c: New.
+	* ld-elfvers/vers23a.dsym: New.
+	* ld-elfvers/vers23a.map: New.
+	* ld-elfvers/vers23a.sym: New.
+	* ld-elfvers/vers23a.ver: New.
+	* ld-elfvers/vers23b.c: New.
+	* ld-elfvers/vers23b.dsym: New.
+	* ld-elfvers/vers23b.map: New.
+	* ld-elfvers/vers23b.ver: New.
+
+2002-08-12  Stephen Clarke <stephen.clarke@superh.com>
+
+	* ld-sh/sh64/abi32.xd: Adjust whitespace in elf32 section
+	listing.
+	* ld-sh/sh64/cmpct1.xd, ld-sh/sh64/mix1.xd, ld-sh/sh64/mix2.xd,
+	ld-sh/sh64/rel32.xd, ld-sh/sh64/shdl32.xd: Likewise.
+	* ld-sh/sh64/abi32.xd: Adjust as type of linker-script-symbols
+	is no longer set to object.
+	* ld-sh/sh64/abi64.xd, ld-sh/sh64/cmpct1.xd, ld-sh/sh64/crange1.rd,
+	ld-sh/sh64/crange2.rd, ld-sh/sh64/crange3-cmpct.rd,
+	ld-sh/sh64/crange3-media.rd, ld-sh/sh64/crange3.rd,
+	ld-sh/sh64/mix1.xd, ld-sh/sh64/mix2.xd, ld-sh/sh64/shdl32.xd,
+	ld-sh/sh64/shdl64.xd: Likewise.
+
+2002-08-10  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-discard/discard.exp: Don't run on linuxaout or linuxoldld.
+	* ld-linkonce/linkonce.exp: Likewise.
+	* ld-selective/sel-dump.exp: Likewise.
+	* ld-selective/selective.exp: Don't run on aout or bout.
+
+2002-08-08  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvers/vers.exp: Add vers22.
+
+	* ld-elfvers/vers22.c: New.
+	* ld-elfvers/vers22.dsym: New.
+	* ld-elfvers/vers22.map: New.
+	* ld-elfvers/vers22.ver: New.
+	* ld-elfvers/vers22a.c: New.
+	* ld-elfvers/vers22a.dsym: New.
+	* ld-elfvers/vers22a.sym: New.
+	* ld-elfvers/vers22a.ver: New.
+	* ld-elfvers/vers22b.c: New.
+	* ld-elfvers/vers22b.dsym: New.
+	* ld-elfvers/vers22b.ver: New.
+
+2002-08-07  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvers/vers.exp: Add --no-undefined-version.
+
+	* ld-elfvers/vers1.map: Remove the unused foo1 and foo2.
+	* ld-elfvers/vers8.map: Likewise.
+	* ld-elfvers/vers18.map: Likewise.
+
+2002-07-30  John David Anglin  <dave@hiauly1.hia.nrc.ca>
+
+	* ld-discard/discard.exp, ld-scripts/phdrs.exp, ld-scripts/phdrs2.exp,
+	ld-selective/sel-dump.exp: Test hppa*64*-*-hpux* target.
+	* ld-elfvers/vers.exp, ld-elfvsb/elfvsb.exp, ld-elfweak/elfweak.exp,
+	ld-linkonce/linkonce.exp, ld-shared/shared.exp,
+	ld-undefined/weak-undef.exp:  Test hppa*64*-*-hpux* and hppa*-*-linux*
+	targets.
+	* ld-discard/exit.s, ld-discard/extern.s, ld-discard/start.s,
+	ld-discard/static.s: Add whitespace before assembler directives.
+
+2002-07-29  Chris Demetriou  <cgd@broadcom.com>
+
+	* ld-mips-elf/mips16-1.d: Check that ASE flag is actually set.
+
+2002-07-26  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-mips-elf/mips16-1.d,
+	* ld-mips-elf/mips16-1[ab].s: New test.
+	* ld-mips-elf/mips-elf.exp: Run it.
+
+2002-07-19  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/sec-1.d: Adjust for changes in padding.
+	* ld-mmix/sec-3.d: Ditto.
+
+2002-07-15  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvers/vers.exp: Add vers21.
+
+	* ld-elfvers/vers21.c: New.
+	* ld-elfvers/vers21.dsym: New.
+	* ld-elfvers/vers21.map: New.
+	* ld-elfvers/vers21.sym: New.
+	* ld-elfvers/vers21.ver: New.
+
+2002-07-12  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/nodyn4.d, ld-cris/expdyn4.d, ld-cris/comref1.s,
+	ld-cris/euwref1.s, ld-cris/expdyn3.d, ld-cris/expdyn2.d,
+	ld-cris/expdref1.s: New tests.
+
+2002-07-09  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-scripts/dynamic-sections*: New test.
+
+2002-07-09  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/libdso-3.d, ld-cris/dso-3.s, ld-cris/noglob1.s,
+	ld-cris/noglob1.d: New tests.
+
+	* ld-cris/libdso-1.d: Tweak for change in size of dynamic sections.
+
+2002-07-03  Alan Modra  <amodra@bigpond.net.au>
+
+	* lib/ld-lib.exp (default_ld_nm): Run nm with LC_ALL=C to ensure
+	consistent sorting.
+	(run_dump_test): Likewise for objdump/nm/objcopy/readelf.
+	* ld-sh/sh64/sh64.exp (run_ld_link_tests): Likewise.
+
+2002-06-29  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/sec-8m.d, ld-mmix/sec-8m.s, ld-mmix/sec-8a.s,
+	ld-mmix/sec-8b.s, ld-mmix/sec-8d.s: New test.
+
+2002-06-18  Chris Demetriou  <cgd@broadcom.com>
+
+	* ld-mips-elf/empic2-ref.s: Add a missing .end, apparently
+	turned up by recent assembler changes.
+
+2002-06-17  Tom Rix  <trix@redhat.com>
+
+	* ld-d10v/d10v.exp: New driver for d10v.
+	* ld-d10v/default_layout.d : New test.
+	* ld-d10v/regression-001.lt: New test for a linker regression.
+	* ld-d10v/linktest-002.lt: New test for run_link_test.
+	* ld-d10v/reloc-001.d - reloc-016.d: New tests.
+
+2002-06-11  John David Anglin  <dave@hiauly1.hia.nrc.ca>
+
+	* ld-scripts/cross1.t: Add .hash, .dynstr and .dynsym sections to
+	script.
+
+2002-06-11  Andreas Jaeger  <aj@suse.de>
+
+	* ld-undefined/undefined.exp: Add s390x to dwarf2 xfails.
+
+2002-06-10  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-mips-elf/region1a.s,
+	* ld-mips-elf/region1b.s,
+	* ld-mips-elf/region1.t,
+	* ld-mips-elf/region1.d: New test.
+	* ld-mips-elf/mips-elf.exp: Run it.
+
+2002-06-07  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* ld-scripts/phdrs2.s: Use .p2align instead of .align.
+	Use section names .foo and .bar instead of .text and .data.
+	* ld-scripts/phdrs2.t: Refer to .foo and .bar instead of .text
+	and .data.
+
+2002-06-06  David Heine <dlheine@tensilica.com>
+
+	* ld-scripts/phdrs2.exp: New file: Run second phdrs test.
+	* ld-scripts/phdrs2.s: New file: Dummy assembler source.
+	* ld-scripts/phdrs2.t: New file: Linker script with an empty
+	section at the start of a loadable segment.
+
+2005-06-02  H.J. Lu <hjl@gnu.org>
+
+	* ld-srec/sr3.cc (__dso_handle): Added for gcc 3.1 with
+	-fuse-cxa-atexit.
+	(__cxa_atexit): Likewise.
+
+2002-05-30  Richard Henderson  <rth@redhat.com>
+
+	* ld-bootstrap/bootstrap.exp: Test --relax.
+
+2002-05-28  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/libdso-2.d: Tweak for combreloc now default on.
+
+2002-05-07  Richard Sandiford  <rsandifo@redhat.com>
+
+	* lib/ld-lib.exp (run_dump_test): Add -L$srcdir/$subdir.
+	(is_elf_format): New, extracted from...
+	* ld-scripts/weak.exp: ...here.
+	* ld-scripts/overlay-size.exp: New test.
+	* ld-scripts/overlay-size.[tsd],
+	* ld-scripts/overlay-size-map.d: New files for it.
+
+2002-05-02  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-scripts/map-address.exp: Quote conditions.
+
+2002-04-30  Richard Sandiford  <rsandifo@redhat.com>
+
+	* ld-scripts/map-address.exp: New test.
+	* ld-scripts/map-address.[td]: New files for it.
+
+2002-04-19  Richard Henderson  <rth@redhat.com>
+
+	* ld-elfvsb/elfvsb.exp: Mirror ia64 non-pic xfails for alpha.
+	* ld-shared/shared.exp: Likewise.
+	* ld-selective/selective.exp: Disable for alpha.
+	* ld-undefined/undefined.exp: Add alpha to dwarf2 xfails.
+
+2002-04-05  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/libdso-2.d, ld-cris/dso-2.s, ld-cris/hide1: New test.
+
+2002-03-19  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/ldsym1.d: New test.
+
+	* ld-mmix/bpo-1.d: Tweak for type of linker-script-symbols no
+	longer set to object.
+	* ld-mmix/undef-3.d, ld-mmix/start-1.d, ld-mmix/locto-1.d,
+	ld-mmix/loct-1.d, ld-mmix/locdo-1.d, ld-mmix/local7.d,
+	ld-mmix/local5.d, ld-mmix/local3.d, ld-mmix/local1.d,
+	ld-mmix/loc6.d, ld-mmix/loc4.d, ld-mmix/loc3.d, ld-mmix/loc2.d,
+	ld-mmix/loc1.d, ld-mmix/greg-7.d, ld-mmix/greg-6.d,
+	ld-mmix/greg-5.d, ld-mmix/greg-4.d, ld-mmix/greg-3.d,
+	ld-mmix/greg-2.d, ld-mmix/greg-19.d, ld-mmix/greg-1.d,
+	ld-mmix/bspec2.d, ld-mmix/bspec1.d, ld-mmix/bpo-9.d,
+	ld-mmix/bpo-6.d, ld-mmix/bpo-5.d, ld-mmix/bpo-4.d,
+	ld-mmix/bpo-3.d, ld-mmix/bpo-2.d, ld-mmix/bpo-19.d,
+	ld-mmix/bpo-18.d, ld-mmix/bpo-17.d, ld-mmix/bpo-16.d,
+	ld-mmix/bpo-14.d, ld-mmix/bpo-11.d, ld-mmix/bpo-10.d: Ditto.
+
+2002-03-11  Andreas Jaeger  <aj@suse.de>
+
+	* ld-elfweak/strongdata.sym: Allow bss section for GCC 3.2 that
+	places zero initialized data in the bss.
+	* ld-elfweak/lddsodata.dsym: Likewise.
+
+2002-03-07  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/expdyn1.d: Tweak for change in elf.sc.
+
+2002-02-24  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-sh/ld-r-1.d: Adjust to changes in readelf output.
+	* ld-sh/shared-1.d, ld-sh/sh64/crangerel1.rd, ld-sh/crangerel2.rd,
+	ld-sh/sh64/reldl32.rd, ld-sh/sh64/reldl64.rd: Ditto.
+
+2002-02-18  Daniel Jacobowitz  <drow@mvista.com>
+
+	* ld-elfvsb/sh1.c: Fix typo in last change.
+
+2002-02-17  Daniel Jacobowitz  <drow@mvista.com>
+
+	* ld-elfvsb/sh1.c: Use #pragma weak.
+
+2002-02-17  Daniel Jacobowitz  <drow@mvista.com>
+
+	* vers.exp: Do not call diff -q.
+
+2002-02-17  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/b-nosym.d, ld-mmix/sec-6.d: Tweak for change in symbol
+	output.
+	* ld-mmix/sec-7m.d, ld-mmix/sec-7a.s, ld-mmix/sec-7b.s,
+	ld-mmix/sec-7c.s, ld-mmix/sec-7d.s, ld-mmix/sec-7e.s: New test.
+
+	* ld-mmix/bpo-22.d: New test.
+
+	* ld-mmix/local12.d (Sections): Match any LMA for .data, .sbss,
+	and .bss.
+
+2002-02-12  John David Anglin  <dave@hiauly1.hia.nrc.ca>
+
+	* ld-selective/selective.exp: Link against libgcc on
+	hppa*-*-linux* targets.
+
+2002-02-11  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-sh/sh64/reldl64.rd: Add relocation symbol data in info field.
+	* ld-sh/sh64/crange-2i.s: Add align to match align in crange-2h.s.
+	* ld-sh/sh64/crange3-cmpct.rd: Adjust to reflect modifications
+	in section ordering.
+	* ld-sh/sh64/crange3-media.rd: Likewise.
+	* ld-sh/sh64/crange3.rd: Likewise.
+	* ld-sh/sh64/crange3.dd: Likewise.
+
+	* ld-sh/shared-1.d: Fix relocation addend.
+
+2002-02-09  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/bpo-21.d, ld-mmix/bpo-21m.d, ld-mmix/bpo-11.s: New
+	tests.
+
+2002-02-08  Alexandre Oliva  <aoliva@redhat.com>
+
+	Contribute sh64-elf.
+	2002-02-02  Alexandre Oliva  <aoliva@redhat.com>
+	* ld-sh/sh64/crange3-cmpct.rd: Adjust offsets.
+	* ld-sh/sh64/crange3-media.rd: Likewise.
+	* ld-sh/sh64/crange3.rd: Likewise.
+	* ld-sh/sh64/crangerel1.rd: Likewise.
+	* ld-sh/sh64/crangerel2.rd: Likewise.
+	* ld-sh/sh64/reldl32.rd: Likewise.
+	* ld-sh/sh64/reldl64.rd: Likewise.
+	2002-01-28  Alexandre Oliva  <aoliva@redhat.com>
+	* ld-sh/sh64/abi32.xd: Formatting changes to match the current
+	output of objdump.
+	* ld-sh/sh64/cmpct1.xd: Likewise.
+	* ld-sh/sh64/crange1.rd: Likewise.
+	* ld-sh/sh64/crange2.rd: Likewise.
+	* ld-sh/sh64/crange3-cmpct.rd: Likewise.
+	* ld-sh/sh64/crange3-media.rd: Likewise.
+	* ld-sh/sh64/crange3.rd: Likewise.
+	* ld-sh/sh64/crangerel1.rd: Likewise.
+	* ld-sh/sh64/crangerel2.rd: Likewise.
+	* ld-sh/sh64/mix1.xd: Likewise.
+	* ld-sh/sh64/mix2.xd: Likewise.
+	* ld-sh/sh64/rel32.xd: Likewise.
+	* ld-sh/sh64/reldl32.rd: Likewise.
+	* ld-sh/sh64/reldl64.rd: Likewise.
+	* ld-sh/sh64/sh64.exp: Likewise.  Reordered cranges and stack
+	sessions, to match changes in the linker script.
+	2001-06-14  Alexandre Oliva  <aoliva@redhat.com>
+	* ld-sh/sh64/reldl32.rd, ld-sh/sh64/reldl64.rd: Adjust relocation
+	info to reflect renumbering of relocation types.
+	2001-03-14  DJ Delorie	<dj@redhat.com>
+	* ld-sh/sh64/endian.dbd: New file, endian tests.
+	* ld-sh/sh64/endian.dld: Ditto.
+	* ld-sh/sh64/endian.ld: Ditto.
+	* ld-sh/sh64/endian.s: Ditto.
+	* ld-sh/sh64/endian.sbd: Ditto.
+	* ld-sh/sh64/endian.sld: Ditto.
+	* ld-sh/sh64/sh64.exp: Add above tests.  Add -L option to ld.
+	2001-03-12  DJ Delorie	<dj@redhat.com>
+	* ld-sh/sh64/relax.exp: New file, test disabling relaxing.
+	* ld-sh/sh64/relax1.s: Ditto.
+	* ld-sh/sh64/relax2.s: Ditto.
+	* ld-sh/sh64/relax3.s: Ditto.
+	* ld-sh/sh64/relax4.s: Ditto.
+	* ld-sh/sh64/relfail.exp: New file, test for bogus relocs.
+	* ld-sh/sh64/relfail.s: Ditto.
+	2001-03-12  DJ Delorie	<dj@redhat.com>
+	* ld-sh/sh.exp: This test isn't appropriate for SH64 since it
+	uses SH32 assembler files.
+	2001-03-07  DJ Delorie	<dj@redhat.com>
+	* ld-selective/selective.exp: Pass "-e _start" for sh64 to
+	accomodate expected start symbol in test.
+	2001-03-06  DJ Delorie	<dj@redhat.com>
+	* ld-scripts/crossref.exp: Pass -mshelf32 to the linker for sh64,
+	to match what gcc passes to the linker by default.
+	* ld-selective/selective.exp: Ditto.
+	* ld-srec/srec.exp: Ditto, plus XFAIL for sh64.
+	* ld-undefined/undefined.exp: Add XFAIL for sh64 (it's dwarf2).
+	2001-03-06  DJ Delorie	<dj@redhat.com>
+	* ld-sh/sh64/abi32.xd (stack): Adjust for new default stack layout.
+	* ld-sh/sh64/abi64.xd (stack): Ditto.
+	* ld-sh/sh64/cmpct1.xd (stack): Ditto.
+	* ld-sh/sh64/crange1.rd (stack): Ditto.
+	* ld-sh/sh64/crange2.rd (stack): Ditto.
+	* ld-sh/sh64/crange3-cmpct.rd (stack): Ditto.
+	* ld-sh/sh64/crange3-media.rd (stack): Ditto.
+	* ld-sh/sh64/crange3.rd (stack): Ditto.
+	* ld-sh/sh64/mix1.xd (stack): Ditto.
+	* ld-sh/sh64/mix2.xd (stack): Ditto.
+	* ld-sh/sh64/shdl32.xd (stack): Ditto.
+	* ld-sh/sh64/shdl64.xd (stack): Ditto.
+	2001-01-14  Hans-Peter Nilsson	<hpn@cygnus.com>
+	* ld-sh/sh64/mix1.xd: Add SORT_ENTRIES for .cranges section.
+	* ld-sh/sh64/mix2.xd: Ditto.
+	2001-01-08  Hans-Peter Nilsson	<hpn@cygnus.com>
+	* ld-sh/sh64/abi32.xd: Adjust for bit 0 set on an entry address
+	being SHmedia.
+	* ld-sh/sh64/shdl64.xd: Ditto.
+	* ld-sh/sh64/shdl32.xd: Ditto.
+	* ld-sh/sh64/mix2.xd: Ditto.
+	* ld-sh/sh64/crange3-media.rd: Ditto.
+	* ld-sh/sh64/abi64.xd: Ditto.
+	2001-01-06  Hans-Peter Nilsson	<hpn@cygnus.com>
+	* ld-sh/sh64/crange-2a.s (diversion2): New global symbol.
+	* ld-sh/sh64/crange1.rd: Adjust to presence of new symbol.
+	Adjust section type for .cranges; expect sorted contents.
+	* ld-sh/sh64/crange2.rd: Ditto.
+	* ld-sh/sh64/crange3.dd, ld-sh/sh64/crange3.rd: Ditto.
+	* ld-sh/sh64/crangerel1.rd: Adjust to presence of new symbol.
+	* ld-sh/sh64/crangerel2.rd: Ditto.
+	* ld-sh/sh64/mix1.xd: Adjust to DEBUGGING being set for .cranges.
+	* ld-sh/sh64/mix2.xd: Ditto.
+	* ld-sh/sh64/crange3-cmpct.rd, ld-sh/sh64/crange3-media.rd: New
+	tests.
+	* ld-sh/sh64/sh64.exp: Tweak test message.  Run new tests.
+	2001-01-05  Hans-Peter Nilsson	<hpn@cygnus.com>
+	* ld-sh/sh64/shmix-1.s (start2): Add a NOP to provide a valid
+	target for (unexpanded) PTB.  Add an .align 2 to SHmedia code to
+	keep properly aligned.
+	* ld-sh/sh64/mix1.sd, ld-sh/sh64/mix1.xd: Adjust accordingly.
+	* ld-sh/sh64/mix1-noexp.sd, ld-sh/sh64/mix2-noexp.sd,
+	ld-sh/sh64/abixx-noexp.sd: New tests for GAS -no-expand and
+	R_SH_PT_16 relocation.
+	* ld-sh/sh64/sh64.exp: Run new tests.
+	2000-12-30  Hans-Peter Nilsson	<hpn@cygnus.com>
+	* ld-sh/sh64/crange-2f.s, ld-sh/sh64/crange-2g.s,
+	ld-sh/sh64/crange-2h.s, ld-sh/sh64/crange-2i.s,
+	ld-sh/sh64/crange3.dd, ld-sh/sh64/crange3.rd: New tests.
+	* ld-sh/sh64/sh64.exp: Run new tests.
+	* ld-sh/sh64/crange1.rd: Correct section flags.
+	* ld-sh/sh64/crange2.rd: Ditto.
+	* ld-sh/sh64/crangerel1.rd: Ditto.
+	2000-12-18  Hans-Peter Nilsson	<hpn@cygnus.com>
+	* ld-sh/sh64/crange-1.s, ld-sh/sh64/crange-2a.s,
+	ld-sh/sh64/crange-2b.s, ld-sh/sh64/crange-2c.s,
+	ld-sh/sh64/crange-2d.s, ld-sh/sh64/crange-2e.s,
+	ld-sh/sh64/crange1.rd, ld-sh/sh64/crange2.rd,
+	ld-sh/sh64/crangerel1.rd, ld-sh/sh64/crangerel2.rd: New tests for
+	handling .cranges section.
+	* ld-sh/sh64/sh64.exp: Run new tests.
+	* ld-sh/sh64/mix1.sd, ld-sh/sh64/mix1.xd, ld-sh/sh64/mix2.sd,
+	ld-sh/sh64/mix2.xd: Adjust for .cranges section.
+	2000-12-15  Hans-Peter Nilsson	<hpn@cygnus.com>
+	* ld-sh/sh64/abi32.sd, ld-sh/sh64/abi32.xd, ld-sh/sh64/abi64.sd,
+	ld-sh/sh64/abi64.xd, ld-sh/sh64/cmpct1.xd, ld-sh/sh64/mix1.sd,
+	ld-sh/sh64/mix1.xd, ld-sh/sh64/mix2.sd, ld-sh/sh64/mix2.xd,
+	ld-sh/sh64/shdl32.xd, ld-sh/sh64/shdl64.xd: Adjust to .bss and
+	.data individually 8-byte aligned.
+	2000-12-09  Hans-Peter Nilsson	<hpn@cygnus.com>
+	* ld-sh/sh64/rel-1.s, ld-sh/sh64/rel-2.s, ld-sh/sh64/rel32.xd,
+	ld-sh/sh64/rel64.xd, ld-sh/sh64/reldl-1.s, ld-sh/sh64/reldl-2.s,
+	ld-sh/sh64/reldl32.rd, ld-sh/sh64/reldl64.rd: New tests.
+	* ld-sh/sh64/sh64.exp: Make it possible to use readelf as
+	inspection tool.  Run new tests.
+	2000-12-07  Hans-Peter Nilsson	<hpn@cygnus.com>
+	* ld-sh/sh64/abi64.sd, ld-sh/sh64/abi32.sd, ld-sh/sh64/mix1.sd,
+	ld-sh/sh64/mix2.sd: Correct offsets in PT/PTA/PTB expansions.
+	* ld-sh/sh64/shdl-1.s, ld-sh/sh64/shdl-2.s, ld-sh/sh64/shdl64.sd,
+	ld-sh/sh64/shdl64.xd, ld-sh/sh64/shdl32.xd: New tests.
+	* ld-sh/sh64/sh64.exp: Run new tests.
+	2000-12-01  Hans-Peter Nilsson	<hpn@cygnus.com>
+	* ld-sh/sh64/cmpct1.sd, ld-sh/sh64/cmpct1.xd,
+	ld-sh/sh64/shcmp-1.s: New test.
+	* ld-sh/sh64/sh64.exp: Add new test to sh64tests.  Reformat.
+	2000-11-30  Hans-Peter Nilsson	<hpn@cygnus.com>
+	* ld-sh/sh64/sh64.exp: Use linker option -mshelf64 for 64-bit ABI
+	test.
+	* ld-sh/sh64/abi64.xd: Tweak for 64-bit ELF.
+	2000-11-29  Hans-Peter Nilsson	<hpn@cygnus.com>
+	* ld-sh/sh64/sh64.exp (sh64tests): Use linker option -mshelf32 for
+	tests.
+	2000-11-27  Hans-Peter Nilsson	<hpn@cygnus.com>
+	* ld-sh/sh64/abi32.sd, ld-sh/sh64/abi64.sd: Correct MOVI
+	registers.
+	* ld-sh/sh64/mix1.sd, ld-sh/sh64/mix1.xd, ld-sh/sh64/shmix-1.s:
+	New test.
+	* ld-sh/sh64/mix2.sd, ld-sh/sh64/mix2.xd, ld-sh/sh64/shmix-2.s,
+	ld-sh/sh64/shmix-3.s: New test.
+	* ld-sh/sh64/sh64.exp: Add new tests to sh64tests.
+	2000-11-26  Hans-Peter Nilsson	<hpn@cygnus.com>
+	* ld-sh/sh64: New testsuite.
+
+2002-02-07  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-selective/keepdot.s: Remove section specifier.
+
+2002-02-05  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-selective/keepdot.d, ld-selective/keepdot.ld,
+	ld-selective/keepdot.s, ld-selective/keepdot0.d: New tests.
+	* ld-selective/sel-dump.exp: New, driver for run_dump_test:s.
+
+2002-02-04  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/bpo-18.d, ld-mmix/bpo64addr.ld, ld-mmix/bpo-18m.d,
+	ld-mmix/bpo-9.s, ld-mmix/bpo-19.d, ld-mmix/bpo-19m.d,
+	ld-mmix/bpo-10.s, ld-mmix/bpo-20.d, ld-mmix/bpo-20m.d: New tests
+	for on-demand global register allocation.
+
+2002-02-02  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-sh/shared-1.d: Fix incorrect offsets.
+
+2002-02-01  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/bpo-1.d, ld-mmix/bpo-1.s, ld-mmix/bpo-1m.d,
+	ld-mmix/bpo-15.d, ld-mmix/bpo-4.s, ld-mmix/bpo-6.d,
+	ld-mmix/bpo-6.s, ld-mmix/bpo-2.d, ld-mmix/bpo-6m.d,
+	ld-mmix/bpo-12m.d, ld-mmix/bpo-2m.d, ld-mmix/bpo-2.s,
+	ld-mmix/bpo-5.s, ld-mmix/bpo-3.d, ld-mmix/start3.s,
+	ld-mmix/bpo-3m.d, ld-mmix/bpo-9m.d, ld-mmix/bpo-4.d,
+	ld-mmix/bpo-3.s, ld-mmix/bpo-4m.d, ld-mmix/bpo-7.d,
+	ld-mmix/bpo-5.d, ld-mmix/bpo-16.d, ld-mmix/bpo-5m.d,
+	ld-mmix/bpo-7m.d, ld-mmix/bpo-9.d, ld-mmix/bpo-8.d,
+	ld-mmix/start4.s, ld-mmix/bpo-8m.d, ld-mmix/bpo-13m.d,
+	ld-mmix/bpo-15m.d, ld-mmix/bpo-10.d, ld-mmix/bpo-11.d,
+	ld-mmix/bpo-14m.d, ld-mmix/bpo-13.d, ld-mmix/bpo-7.s,
+	ld-mmix/bpo-12.d, ld-mmix/bpo-16m.d, ld-mmix/bpo-14.d,
+	ld-mmix/bpo-8.s, ld-mmix/bpo-17.d, ld-mmix/bpo-17m.d: New tests.
+
+2002-01-31  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris/weakref1.d, ld-cris/libdso-1.d, ld-cris/gotrel2.s,
+	ld-cris/expdyn1.d, ld-cris/expdyn1.s, ld-cris/dso-1.s: New tests.
+	* ld-cris/cris.exp: Split run_dump_tests in two parts, executing
+	tests named *dso-*.d first and copying their tmpdir/dump to files
+	named as the .d-file.
+
+2002-01-31  Alan Modra  <amodra@bigpond.net.au>
+
+	* ld-scripts/crossref.exp: Allow foo to have a leading dot.
+	* ld-scripts/cross1.t: Add .opd.
+	* ld-undefined/undefined.exp: Allow leading dot on sym names.
+	* lib/ld-lib.exp (default_ld_nm): Strip leading dots from syms.
+
+2002-01-29  Chris Demetriou  <cgd@broadcom.com>
+
+	* ld-mips-elf/emrelocs-eb.d: New file to test --embedded-relocs.
+	* ld-mips-elf/emrelocs-el.d: Likewise.
+	* ld-mips-elf/emrelocs1.s: Likewise.
+	* ld-mips-elf/emrelocs2.s: Likewise.
+	* ld-mips-elf/emrelocs.ld: Likewise.
+	* ld-mips-elf/mips-elf.exp: Add the above to the list of tests.
+
+2002-01-21  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-cris: New testsuite directory.
+
+2002-01-15  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* ld-sh/sh.exp: Copy start.s file into test directory.
+
+2002-01-14  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* ld-selective/selective.exp: For ARM targets, link with libgcc.a.
+
+2002-01-02  Chris Demetriou  <cgd@broadcom.com>
+
+	* ld-mips-elf/empic1-ln.d: New file to test basic linking of
+	R_MIPS_GNU_REL_HI16 and R_MIPS_GNU_REL_LO16 relocations.
+	* ld-mips-elf/empic1-lp.d: Likewise.
+	* ld-mips-elf/empic1-mn.d: Likewise.
+	* ld-mips-elf/empic1-mp.d: Likewise.
+	* ld-mips-elf/empic1-sn.d: Likewise.
+	* ld-mips-elf/empic1-sp.d: Likewise.
+	* ld-mips-elf/empic1-ref.s: Likewise.
+	* ld-mips-elf/empic1-space.s: Likewise.
+	* ld-mips-elf/empic1-tgt.s: Likewise.
+	* ld-mips-elf/empic2-fwd-0.d: New file to test
+	R_MIPS_GNU_REL_HI16 and R_MIPS_GNU_REL_LO16 relocation edge
+	cases.
+	* ld-mips-elf/empic2-fwd-1.d: Likewise.
+	* ld-mips-elf/empic2-rev-0.d: Likewise.
+	* ld-mips-elf/empic2-rev-1.d: Likewise.
+	* ld-mips-elf/empic2-ref.s: Likewise.
+	* ld-mips-elf/empic2-space.s: Likewise.
+	* ld-mips-elf/empic2-fwd-tgt.s: Likewise.
+	* ld-mips-elf/empic2-rev-tgt.s: Likewise.
+	* ld-mips-elf/mips-elf.exp: New file to run MIPS 32-bit ELF
+	tests (including those above).
+
+2001-11-30  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvers/vers.exp (build_vers_lib): Preserve the library
+	order.
+
+2001-11-29  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvers/vers.exp (build_vers_lib): Support linking against
+	more than one libraries.
+	Add "vers20a" and "vers20" tests for common symbols.
+
+	* ld-elfvers/vers20.c: New.
+	* ld-elfvers/vers20.dsym: New.
+	* ld-elfvers/vers20.map: New.
+	* ld-elfvers/vers20.ver: New.
+	* ld-elfvers/vers20a.ver: New.
+
+2001-11-19  H.J. Lu <hjl@gnu.org>
+
+	* ld-elfvsb/define.s: Mark all global lables as object.
+
+	* ld-elfvsb/hidden0.d: Match large section number.
+	* ld-elfvsb/hidden1.d: Likewise.
+	* ld-elfvsb/internal0.d: Likewise.
+	* ld-elfvsb/internal1.d: Likewise.
+	* ld-elfvsb/protected0.d: Likewise.
+	* ld-elfvsb/protected1.d: Likewise.
+
+	* ld-elfvsb/hidden0.d: Change NOTYPE to OBJECT.
+	* ld-elfvsb/internal0.d: Likewise.
+	* ld-elfvsb/protected0.d: Likewise.
+
+2001-11-15  H.J. Lu <hjl@gnu.org>
+
+	* ld-sh/ld-r-1.d: Updated.
+
+2001-11-14  Nick Clifton  <nickc@cambridge.redhat.com>
+
+	* ld-bootstrap/bootstrap.exp: Only scan tail of executable for
+	PE targets.
+
+2001-11-12  Donn Terry <donnte@microsoft.com>
+
+	* ld-bootstrap/bootstrap.exp: Only compare the tail end of the two
+	binary files produced in order to avoid date stamp present in PE
+	binaries.
+
+2001-11-11  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/sec-5.d (Sections): Add whitespace missing in commit.
+
+2001-11-09  H.J. Lu <hjl@gnu.org>
+
+	* ld-discard/discard.exp: New. Test ld discard.
+	* ld-discard/discard.ld: Likewise.
+	* ld-discard/exit.s: Likewise.
+	* ld-discard/extern.d: Likewise.
+	* ld-discard/extern.s: Likewise.
+	* ld-discard/start.d: Likewise.
+	* ld-discard/start.s: Likewise.
+	* ld-discard/static.d: Likewise.
+	* ld-discard/static.s: Likewise.
+
+2001-11-02  H.J. Lu  <hjl@gnu.org>
+
+	* ld-elfvsb/elfvsb.exp: Add the "ld -r" test.
+
+	* ld-elfvsb/hidden0.d: New.
+	* ld-elfvsb/hidden1.d: New.
+	* ld-elfvsb/internal0.d: New.
+	* ld-elfvsb/internal1.d: New.
+	* ld-elfvsb/protected0.d: New.
+	* ld-elfvsb/protected1.d: New.
+	* ld-elfvsb/undef.s: New.
+	* ld-elfvsb/undef.s: New.
+
+2001-11-02  NIIBE Yutaka  <gniibe@m17n.org>
+
+	* ld-sh/sh.exp: Have its own start.s for linux.
+
+2001-10-31  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix/locdo-1.d: Prune character dump part.
+	* ld-mmix/local7m.d, ld-mmix/loc4.d, ld-mmix/loc4m.d,
+	ld-mmix/loc1.d, ld-mmix/bspec1m.d, ld-mmix/bspec2m.d,
+	ld-mmix/b-nosym.d, ld-mmix/b-fixo2.d, ld-mmix/b-loc64k.d,
+	ld-mmix/undef-3m.d, ld-mmix/locto.s, ld-mmix/loct.s,
+	ld-mmix/local3m.d, ld-mmix/local1m.d, ld-mmix/loc6m.d,
+	ld-mmix/loc2.s, ld-mmix/loc1.s, ld-mmix/gregldo1.s,
+	ld-mmix/dloc1.s, ld-mmix/b-widec3.s, ld-mmix/b-nosym.s: Remove
+	unnecessary empty lines.
+
+2001-10-30  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-mmix: New testsuite directory.
+
+2001-10-14  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-sh/sub2l-1.d, ld-sh/shared-1.d, ld-sh/weak1.d: Only run on
+	sh*-*-elf.
+
+	* lib/ld-lib.exp (run_dump_test): Fix typo: asflags(), not asflags{}.
+
+	* ld-sh/rd-sh.exp: New framework file.
+	* ld-sh/ld-r-1.d, ld-sh/ldr1.s, ld-sh/ldr2.s, ld-sh/shared-1.d,
+	ld-sh/weak1.s, ld-sh/weak1.d, ld-sh/sub2l.s, ld-sh/sub2l-1.d: New
+	test files.
+
+2001-09-29  Hans-Peter Nilsson  <hp@axis.com>
+
+	* ld-linkonce/linkonce.exp: New file.
+	* ld-linkonce/x.s, ld-linkonce/y.s, ld-linkonce/zeroeh.ld,
+	ld-linkonce/zeroehl32.d: New test.
+
+2001-09-25  H.J. Lu  <hjl@gnu.org>
+
+	* ld-elfweak/dso.dsym: Updated for alpha.
+	* ld-elfweak/dsodata.dsym: Likewise.
+	* ld-elfweak/strong.sym: Likewise.
+	* ld-elfweak/strongcomm.sym: Likewise.
+	* ld-elfweak/strongdata.sym: Likewise.
+
+2001-09-15  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* lib/ld-lib.exp (run_dump_test): Handle new option
+	"objcopy_linked_file".  Return after failing, if errors were
+	expected but none were found.
+	(slurp_options): Support underscores in option names.
+
+2001-09-14  H.J. Lu  <hjl@gnu.org>
+
+	* ld-elfweak/bar.c: Updated.
+	* ld-elfweak/bar1a.c: Likewise.
+	* ld-elfweak/main.c: Likewise.
+	* ld-elfweak/main1.c: Likewise.
+	* ld-elfweak/elfweak.exp: Likewise.
+	* ld-elfweak/weakdata.dsym: Updated.
+
+2001-09-11  H.J. Lu  <hjl@gnu.org>
+
+	* ld-elfweak/elfweak.exp (build_lib): Take a list of object
+	files.
+	(build_exec): Likewise.
+	Add more tests and make some xfail.
+
+	* ld-elfweak/dso.dsym: Support symbol versioning.
+	* ld-elfweak/dsow.dsym: Likewise.
+
+	* ld-elfweak/main1.c: New.
+	* ld-elfweak/bar1a.c: Likewise.
+	* ld-elfweak/bar1b.c: Likewise.
+	* ld-elfweak/bar1c.c: Likewise.
+	* ld-elfweak/foo1a.c: Likewise.
+	* ld-elfweak/foo1b.c: Likewise.
+	* ld-elfweak/dsodata.dsym: Likewise.
+	* ld-elfweak/dsowdata.dsym: Likewise.
+	* ld-elfweak/weakdata.dsym: Likewise.
+	* ld-elfweak/strongcomm.sym: Likewise.
+	* ld-elfweak/strongdata.sym: Likewise.
+	* ld-elfweak/weakdata.dat: Likewise.
+	* ld-elfweak/strongdata.dat: Likewise.
+
+2001-09-10  H.J. Lu  <hjl@gnu.org>
+
+	* ld-elfweak/elfweak.exp: New.
+	* ld-elfweak/bar.c: Likewise.
+	* ld-elfweak/foo.c: Likewise.
+	* ld-elfweak/main.c: Likewise.
+	* ld-elfweak/dso.dsym: Likewise.
+	* ld-elfweak/dsow.dsym: Likewise.
+	* ld-elfweak/strong.sym: Likewise.
+	* ld-elfweak/strong.dat: Likewise.
+	* ld-elfweak/weak.dat: Likewise.
+
+2001-08-27  Alan Modra  <amodra@bigpond.net.au>
+	    Linus Nordberg  <linus@swox.se>
+
+	* ld-checks/checks.exp: .lcomm is incompatible with ppc coff.
+	* ld-scripts/cross1.t: Add .toc section.
+	* ld-scripts/cross2.t: Likewise.
+	* ld-scripts/phdrs.exp: powerpc64 is 64 bit.
+	* ld-srec/srec.exp: xfail powerpc64
+
+2001-08-21  John David Anglin  <dave@hiauly1.hia.nrc.ca>
+
+	* ld-selective/selective.exp: Return if target is `vax-*-ultrix*'.
+	Continue with other tests when there is a compilation error.
+
+2001-08-01  Loren J. Rittle  <ljrittle@acm.org>
+
+	* ld-cdtest/cdtest-nrv.dat: New file.
+	* ld-cdtest/cdtest.exp: Do not require any exception support
+	library.  Check results against NRV.
+
+2001-08-01  Loren J. Rittle  <ljrittle@acm.org>
+
+	* ld-srec/srec.exp: Do not require any exception support
+	library.
+
+2001-07-27  H.J. Lu  <hjl@gnu.org>
+
+	* ld-selective/selective.exp: Fix the error in the last change.
+
+2001-07-24  Loren J. Rittle  <ljrittle@acm.org>
+
+	* ld-selective/selective.exp: Support g++ V3 ABI (along side
+	the old ABI).  Make comparisons against normalized (to
+	V3-style) demangled nm output.
+
+2001-07-24  Alan Modra  <amodra@bigpond.net.au>
+
+	* config/default.exp (ld_nm): Add "nmflags" arg.
+	* lib/ld-lib.exp (default_ld_nm): Likewise.
+	* ld-empic/empic.exp: Adjust call to ld_nm.
+	* ld-scripts/defined.exp: Likewise.
+	* ld-scripts/script.exp: Likewise.
+	* ld-scripts/sizeof.exp: Likewise.
+	* ld-selective/selective.exp: Likewise.
+	* ld-sh/sh.exp: Likewise.
+
+2001-07-12  H.J. Lu  <hjl@gnu.org>
+
+	* ld-selective/selective.exp: Mark selective1, selective2,
+	selective4 and selective5 xfail on alpha*-*.
+
+2001-06-13  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* config/default.exp (AS, GASP, OBJDUMP, NM, NMFLAGS, OBJCOPY,
+	OBJCOPYFLAGS, READELF, READELFFLAGS, LD, LDFLAGS): Provide
+	default.
+
+	* lib/ld-lib.exp (run_dump_test): Import from gas testsuite.  Add
+	new options "ld", "source", "xfail", "target", "notarget" and
+	"error".  Support the runtest_file_p "*.exp=testname" feature.
+	(slurp_options, regexp_diff, file_contents, verbose_eval): Import
+	from gas testsuite.
+
+2001-06-12  Martin Schwidefsky <schwidefsky@de.ibm.com>
+
+	* testsuite/ld-undefined/undefined.exp: Correct setup_xfail rule.
+
+2001-06-06  H.J. Lu  <hjl@gnu.org>
+
+	* ld-bootstrap/bootstrap.exp: Rebuild tmpdir/ld2 with tmpdir/ld3
+	on Linux/mips.
+
+	* ld-elfvers/vers.exp: Also run on Linux/mips.
+	* ld-elfvsb/elfvsb.exp: Likewise.
+	* ld-shared/shared.exp: Likewise.
+
+	* ld-selective/selective.exp: Mark selective2, selective3,
+	selective4 and selective5 xfail on Linux/mips.
+
+	* ld-shared/main.c: Skip invalid -Bsymbolic tests on Linux/mips.
+
+	* symbolic.dat: Remove invalid -Bsymbolic tests on Linux/mips.
+
+	* ld-srec/srec.exp: Add Linux/mips to xfail.
+
+2001-06-06  Martin Schwidefsky <schwidefsky@de.ibm.com>
+
+	* ld-undefined/undefined.exp: Add a setup_xfail line for a test
+	that will always fail on s/390.
+
+2001-05-28  kaz Kojima  <kkojima@rr.iij4u.or.jp>
+
+	* ld-sh/sh.exp: For sh-*-linux-gnu target add a start address for
+	the text section.
+
+2001-05-25  Alan Modra  <amodra@one.net.au>
+
+	* ld-elfvers/vers.exp: Replace linuxoldld with linux*oldld and
+	linuxaout with linux*aout.
+
+2001-05-24  H.J. Lu  <hjl@gnu.org>
+
+	* ld-scripts/phdrs.exp: Add sparc64 to 64 bit platform.
+
+2001-05-18  H.J. Lu  <hjl@gnu.org>
+
+	* ld-elfvers/vers.exp: Revert the last change.
+
+	* ld-elfvers/vers2.ver: Put back "tmpdir/" the version
+	references.
+	* ld-elfvers/vers3.ver: Likewise.
+	* ld-elfvers/vers6.ver: Likewise.
+	* ld-elfvers/vers18.ver: Likewise.
+
+2001-05-17  H.J. Lu  <hjl@gnu.org>
+
+	* ld-elfvers/vers.exp: Pass "-rpath .:$tmpdir" to "vers19".
+
+	* ld-elfvers/vers1.ver: Remove "tmpdir/" from the version
+	definition.
+	* ld-elfvers/vers2.ver: Likewise.
+	* ld-elfvers/vers3.ver: Likewise.
+	* ld-elfvers/vers4a.ver: Likewise.
+	* ld-elfvers/vers6.ver: Likewise.
+	* ld-elfvers/vers7a.ver: Likewise.
+	* ld-elfvers/vers8.ver: Likewise.
+	* ld-elfvers/vers9.ver: Likewise.
+	* ld-elfvers/vers15.ver: Likewise.
+	* ld-elfvers/vers16a.ver: Likewise.
+	* ld-elfvers/vers17.ver: Likewise.
+	* ld-elfvers/vers18.ver: Likewise.
+
+2001-05-03  H.J. Lu  <hjl@gnu.org>
+
+	* ld-elfvers/vers19.ver: Expect vers17.so instead of
+	*tmpdir/vers17.so.
+
+2001-05-01  Andreas Jaeger  <aj@suse.de>, Andreas Schwab <schwab@suse.de>
+
+	* ld-scripts/phdrs.exp: Fix regexp, s390x is 64 bit platform.
+
+	* ld-scripts/phdrs.t: Use startaddress that's greater than any
+	MAXPAGESIZE used.
+
+2001-04-29  H.J. Lu  <hjl@gnu.org>
+
+	* ld-shared/symbolic.dat: New.
+
+	* ld-shared/shared.exp: Also check -Bsymbolic.
+
+2001-04-28  Andreas Jaeger  <aj@suse.de>
+
+	* ld-scripts/phdrs.exp: x86-64 is a 64 bit ELF platform, handle it
+	special.
+
+2001-04-01  David O'Brien  <obrien@FreeBSD.org>
+	* ld-undefined/undefined.exp: XFAIL on FreeBSD/i386 for the usual (even
+	though it doesn't use DWARF2 yet (but its output is identical).
+
+2001-04-01  David O'Brien  <obrien@FreeBSD.org>
+
+	* ld-selective/selective.exp: Use -O with gcc rather than -O2.
+	This optimization level is buggy on some platforms, and this test
+	is not intended to test compiler optimizations.
+
+2001-03-06  DJ Delorie  <dj@redhat.com>
+
+	* ld-scripts/cross2.t: Support any type of text/data sections, not
+	just the canonical ones.
+
+2001-02-28  Matt Hiller  <hiller@redhat.com>
+
+	* ld-scripts/crossref.exp: Initialize flags to [big_or_little_endian].
+	* ld-undefined/undefined.exp: Ditto, and include $flags in ld
+	invocations.
+	* lib/ld-lib.exp (big_or_little_endian): Recognize -EB, -eb, -EL
+	and -el.
+	(is_endian_output_format): New function.
+	(default_ld_link): Set flags to [big_or_little_endian] only if ld
+	is being invoked such that the output format being used is of
+	known endianness.
+	(default_ld_simple_link): Ditto.
+
+2001-02-22  Timothy Wall  <twall@cygnus.com>
+
+	* ld-bootstrap/bootstrap.exp: Exclude ia64 flavor from
+	AIX-specific test.
+
+2001-02-14  H.J. Lu  <hjl@gnu.org>
+
+	* ld-bootstrap/bootstrap.exp: Rebuild tmpdir/ld2 with tmpdir/ld3
+	for -static on ia64.
+
+	* ld-checks/checks.exp: Don't run on ia64-*-elf* nor
+	ia64-*-linux*.
+
+	* ld-elfvers/vers.exp: Also run ia64-*-elf* and ia64-*-linux*.
+
+	* ld-elfvsb/elfvsb.exp: Use i?86-*-*. Also run on ia64-*-linux*.
+	Set up expected failures for ia64-*-linux*.
+	* ld-shared/shared.exp: Likewise.
+
+2001-02-08  Stephane Carrez  <Stephane.Carrez@worldnet.fr>
+
+	* ld-srec/srec.exp (run_srec_test): m6811 code has references
+	to soft registers, define them with --defsym.
+	* ld-selective/selective.exp: Likewise.
+
+2000-01-23  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* ld-srec/sr3.cc (__rethrow): New.
+
+2001-01-14  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-sh/sh.exp: Use --oformat srec, not -oformat srec.
+
+2001-01-03  Philip Blundell  <pb@futuretv.com>
+
+	* ld-elfvsb/elfvsb.exp: Run test on Linux/Alpha.
+	* ld-shared/shared.exp: Likewise.
+
+2001-01-01  Philip Blundell  <philb@gnu.org>
+
+	* ld-undefined/weak-undef.exp: New test.
+	* ld-undefined/weak-undef.s, ld-undefined/weak-undef.t: Supporting
+	files for above.
+
+	* ld-elfvers/vers.exp: Run test on Linux/ARM.
+	* ld-elfvsb/elfvsb.exp: Likewise.
+	* ld-shared/shared.exp: Likewise.
+
+2000-12-31  Nick Clifton  <nickc@redhat.com>
+
+	* ld-srec/srec.exp: Use --oformat instead of -oformat.
+
+2000-12-09  Nick Clifton  <nickc@redhat.com>
+
+	* ld-selective/selective.exp: Link in libgcc when target is v850.
+
+	* ld-srec/srec.exp: Expect the srec_test to fail for ARM targets
+	because the -oformat linker command switch cannot be used.
+
+2000-11-06  Alan Modra  <alan@linuxcare.com.au>
+
+	* ld-elfvsb/main.c (PROTECTED_CHECK): Include stdio.h.
+	(main): Prune unused args.
+
+2000-10-29  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-selective/selective.exp <no CXX>: Fix typo for argument to
+	"untested".
+
+2000-10-19  H.J. Lu  (hjl@gnu.org)
+
+	* ld-elfvsb/elfvsb.exp (visibility_run): Set expected failures
+	for Linux/PPC.
+	* ld-shared/shared.exp: Likewise.
+
+2000-10-09  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-selective/selective.exp: Rearrange to be table-driven.
+
+2000-10-07  Alan Modra  <alan@linuxcare.com.au>
+
+	* ld-scripts/phdrs.exp: hppa*64*-*-* is 64-bit ELF too.
+
+2000-10-02  Alan Modra  <alan@linuxcare.com.au>
+
+	* ld-scripts/weak.exp: Don't set $global$ for hppa-elf any more.
+	* ld-scripts/crossref.exp: Ditto.
+
+2000-09-29  Hans-Peter Nilsson  <hp@bitrange.com>
+
+	* ld-selective/5.cc: New test.
+	* ld-selective/selective.exp: Run it as xfailed.
+
+	* ld-selective/4.cc: Correct spelling of "lose".
+
+2000-09-05  Alan Modra  <alan@linuxcare.com.au>
+
+	* ld-selective/selective.exp: Remove the xfails for hppa.
+
+2000-08-30  Alexandre Oliva  <aoliva@redhat.com>
+
+	* ld-undefined/undefined.exp (hppa*64*-*-*, mn10300-*-elf,
+	sh-*-*): With dwarf-2, `undefined function' can't pass.
+
+2000-08-03  H.J. Lu  (hjl@gnu.org)
+
+	* ld-bootstrap/bootstrap.exp: Add strip.
+
+2000-07-24  H.J. Lu  (hjl@gnu.org)
+
+	* ld-elfvsb/elfvsb.exp: Add -g to $CC to get the location of
+	the undefined reference.
+
+2000-07-16  H.J. Lu  (hjl@gnu.org)
+
+	* ld-elfvsb/elfvsb.exp (support_protected): New variable. Check
+	and set to "yes" if the protected visibility is expected to
+	pass.
+	(visibility_run): Set expected to fail for the "protected"
+	and "protected_undef_def" tests only if $support_protected is
+	"no".
+
+	* ld-elfvsb/main.c (PROTECTED_CHECK): Check for the protected
+	visibility support if defined.
+
+2000-07-15  H.J. Lu  (hjl@gnu.org)
+
+	* ld-elfvsb/elfvsb.exp (visibility_run): Set expected failure
+	for "protected_undef_def".
+
+	* ld-elfvsb/main.c: Don't define HIDDEN_UNDEF_TEST when
+	PROTECTED_WEAK_TEST is defined.
+	Don't define PROTECTED_UNDEF_TEST when PROTECTED_WEAK_TEST is
+	defined.
+	Define PROTECTED_TEST when PROTECTED_UNDEF_TEST is defined.
+
+	* ld-elfvsb/sh1.c (visibility): Mark protected only if
+	PROTECTED_TEST, PROTECTED_UNDEF_TEST or PROTECTED_WEAK_TEST
+	is defined.
+	(visibility_var): Likewise.
+
+2000-07-10  Alan Modra  <alan@linuxcare.com.au>
+
+	* ld-srec/srec.exp: xfail hppa.
+
+	* ld-scripts/weak.exp: Define $global$ for hppa.
+
+	* ld-scripts/crossref.exp: Fix string quoting.
+
+2000-06-05  H.J. Lu  (hjl@gnu.org)
+
+	* lib/ld-lib.exp (default_ld_link): Redirect the linker output
+	to link_output and make it global.
+
+	* ld-elfvsb/elfvsb.exp (visibility_test): Add "hidden_undef",
+	"hidden_undef_def", "hidden_weak", "protected_undef",
+	"protected_undef_def" and "protected_weak".
+	(visibility_run): Likewise.
+	* ld-elfvsb/main.c: Likewise.
+	* ld-elfvsb/sh1.c: Likewise.
+	* ld-elfvsb/sh2.c: Likewise.
+
+	* ld-elfvsb/elfvsb.dat: Updated.
+
+2000-05-21  H.J. Lu  (hjl@gnu.org)
+
+	* ld-elfvsb/main.c (main_visibility_check): Fix the protected
+	visibility test.
+
+2000-05-13  H.J. Lu  (hjl@gnu.org)
+
+	* lib/ld-lib.exp (default_ld_link): Redirect the linker output
+	to link_output and make it global.
+
+	* ld-elfvsb/elf-offset.ld: New. ELF visibility fearture
+	tests.
+	* ld-elfvsb/elfvsb.dat: Likewise.
+	* ld-elfvsb/elfvsb.exp: Likewise.
+	* ld-elfvsb/main.c: Likewise.
+	* ld-elfvsb/sh1.c: Likewise.
+	* ld-elfvsb/sh2.c: Likewise.
+
+Fri Apr 21 15:16:07 2000  Richard Henderson  <rth@cygnus.com>
+
+	* ld-scripts/phdrs.exp: IA-64 is 64-bit ELF too.
+
+2000-04-12  Alan Modra  <alan@linuxcare.com.au>
+
+	* ld-selective/3.cc (_start): Add cheat for gcc-2.95.2 failure.
+
+	* ld-selective/selective.exp (test4): Test for presence of
+	foo__1B, not absence.  Also check for foo__1A and _start.
+	White space changes throughout file.
+
+2000-03-13  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-scripts/phdrs.t: Discard all unexpected sections.
+
+2000-02-27 H.J. Lu  (hjl@gnu.org)
+
+	* lib/ld-lib.exp (default_ld_link): Added "$LIBS" to libs.
+
+1999-11-01  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-selective/selective.exp: Fix test to disable these checks for
+	PE based targets.
+
+1999-10-29  Catherine Moore  <clm@cygnus.com>
+
+	* ld-selective/selective.exp:  Remove test6.
+	* ld-selective/5.cc: Delete.
+
+1999-10-28  Scott Bambrough  <scottb@netwinder.org>
+
+	* ld-srec/srec.exp: Setup expected failures for
+	srec tests on ARM Linux.
+
+1999-09-17  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* ld-shared/shared.exp: xfail linux*libc1 shared (non PIC, load
+	offset) test.
+
+1999-09-12  Ian Lance Taylor  <ian@zembu.com>
+
+	* ld-scripts/script.exp: Add --image-base 0 for PE targets.
+
+1999-08-17  H.J. Lu  <hjl@gnu.org>
+
+	* ld-cdtest/cdtest-foo.cc (Foo::init_foo): Use "%ld" for sizeof.
+
+1999-08-09  Jakub Jelinek  <jj@ultra.linux.cz>
+
+	* ld-elfvers/vers.exp: Run tests on sparc*-*-linux*.
+	* ld-shared/shared.exp: Likewise.
+
+1999-07-28  Nick Clifton  <nickc@cygnus.com>
+
+	* lib/ld-lib.exp (proc big_or_little_endian): New proc.
+	Determine if a big endian or little endian output format hass
+	been selected by any of the multilib options, and if so return
+	a suitable command line option for the linker/assembler.
+	(proc default_ld_link): Include the result of proc
+	big_or_little_endian on the command line to the linker.
+	(proc ld_simple_link): Include the result of proc
+	big_or_little_endian on the command line to the linker.
+	(proc default_ld_compile): Append multilib flags to compiler
+	switches.
+	(proc default_ld_assemble): Include the result of proc
+	big_or_little_endian on the command line to the linker.
+
+1999-07-21  H.J. Lu  <hjl@gnu.org>
+
+	* ld-elfvers/vers1.c: Add missing prototypes and include
+	<stdio.h> if necessary.
+	* ld-elfvers/vers15.c: Likewise.
+	* ld-elfvers/vers19.c: Likewise.
+	* ld-elfvers/vers2.c: Likewise.
+	* ld-elfvers/vers3.c: Likewise.
+	* ld-elfvers/vers4.c: Likewise.
+	* ld-elfvers/vers6.c: Likewise.
+	* ld-elfvers/vers7.c: Likewise.
+	* ld-elfvers/vers9.c: Likewise.
+	* ld-shared/main.c: Likewise.
+	* ld-srec/sr3.cc (Foo::Foo): Remove arg name.
+
+Thu Jul 15 18:00:30 1999  Mark P. Mitchell  <mark@codesourcery.com>
+
+	* ld-undefined/undefined.exp: XFAIL on IRIX6 for the usual as
+	with other DWARF2 targets.
+
+1999-07-13  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-undefined/undefined.exp: Do not expect arm toolchains to fail
+	the undefined line test.
+
+1999-07-10  Ian Lance Taylor  <ian@zembu.com>
+
+	* ld-elfvers/vers.exp: Use -rpath in new vers19 test.
+
+1999-07-07  Ian Lance Taylor  <ian@zembu.com>
+
+	* ld-elfvers/vers.exp: Add new tests vers17 to vers19.
+	* ld-elfvers/{vers17.*, vers18.*, vers19.*}: New files.
+
+1999-06-13  Ian Lance Taylor  <ian@zembu.com>
+
+	* ld-checks/asm.s: Use a symbol name for .lcomm.
+	* ld-checks/checks.exp: Use different names for the two tests.
+	Don't add extra text when invoking fail.
+
+1999-06-12  Ian Lance Taylor  <ian@zembu.com>
+
+	* ld-scripts/phdrs.exp: Change target check from "*-*-linuxaout*"
+	to "*-*-linux*aout*".
+	* ld-scripts/weak.exp: Likewise.
+	* ld-shared/shared.exp: Likewise.  Simplify condition a bit.
+
+Wed Jun  9 12:02:33 1999  Andreas Schwab  <schwab@issan.cs.uni-dortmund.de>
+
+	* ld-cdtest/cdtest-main.cc: Avoid `implicit int' warning.
+	* ld-shared/sh1.c: Fix typo.
+
+1999-06-04  H.J. Lu  <hjl@gnu.org>
+
+	* lib/ld-lib.exp (default_ld_nm): Clear nm_output first if
+	necessary.
+
+1999-05-17  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-undefined/undefined.exp: Add xfail for mcore-elf.
+
+1999-05-11  DJ Delorie  <dj@cygnus.com>
+
+	* ld-srec/srec.exp: Do not run tests for PE based ports.
+
+1999-03-05  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-selective/selective.exp: Do not run tests for COFF or PE
+	based ports.
+
+1999-02-17  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-undefined/undefined.exp: Add expected failures for StrongARM
+	targets.
+
+	* ld-srec/srec.exp: Add expected failures for StrongARM targets.
+
+	* ld-selective/selective.exp: Add expected failure for ARM-COFF
+	targets.
+
+1999-02-16  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-checks/asm.s: Use .long instead of .word.
+	Replace custom section names with .text, .data and .bss.
+	* ld-checks/script: Replace custom section names with .text, .data
+	and .bss.
+	* ld-checks/checks.exp: Replace custom section names with .text,
+	.data and .bss.
+
+1999-02-11  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-checks: New directory:  Tests for the linker's
+	--check-sections option.
+	* ld-checks/checks.exp: New file.
+	* ld-checks/script: Bogus linker script.
+	* ld-checks/asm.s: Simple test assembler file.
+
+Tue Feb  2 19:15:02 1999  Catherine Moore  <clm@cygnus.com>
+
+	* ld-selective/selective.exp:  Disable test for unsupported
+	targets.  Change tests to check for absence of symbols instead
+	of address zero.
+
+Mon Jan 18 03:44:52 1999  Ian Lance Taylor  <ian@cygnus.com>
+
+	* config/default.exp (get_link_files): Quote target_triplet and CC
+	when invoking shell.
+	(get_target_emul): Likewise.
+
+1999-01-03  Ken Raeburn  <raeburn@cygnus.com>
+
+	* config/default.exp (get_link_files, get_target_emul): New procs;
+	run shell commands to extract information from configure.host and
+	configure.tgt in the source tree.
+	(top level): Use them to get information needed to run tests, if
+	not otherwise provided.
+
+	* ld-shared/elf-offset.ld: New file.  Builds a shared library, but
+	gives non-zero addresses for memory region.
+	* ld-shared/shared.exp: Run the non-PIC non-AIX test again using
+	the new linker script.
+
+Tue Dec  8 22:56:05 1998  Geoff Keating  <geoffk@ozemail.com.au>
+
+	* ld-srec/srec.exp: Delete xfails for PPC Linux targets,
+	newer glibc lets link succeed.
+
+Sun Dec  6 12:59:37 1998  H.J. Lu  <hjl@gnu.org>
+
+	* ld-elfvers/vers1.c: Add missing return types and values.
+	* ld-elfvers/vers2.c: Likewise.
+	* ld-elfvers/vers3.c: Likewise.
+	* ld-elfvers/vers4.c: Likewise.
+	* ld-elfvers/vers5.c: Likewise.
+	* ld-elfvers/vers6.c: Likewise.
+	* ld-elfvers/vers7.c: Likewise.
+	* ld-elfvers/vers9.c: Likewise.
+	* ld-elfvers/vers15.c: Likewise.
+
+Fri Oct 23 16:28:29 1998 Catherine Moore  <clm@cygnus.com>
+
+	* ld-selective: New directory with new files to test
+	selective linking.
+
+	* lib/ld-lib.exp (ld_nm): Strip leading underscore from $name.
+
+Sun Oct  4 22:17:05 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-elfvers/vers16.dsym: Work correctly on a system without
+	versioned system libraries.
+
+Mon Sep 28 21:31:12 1998  Richard Henderson  <rth@cygnus.com>
+
+	* ld-elfvers/vers.exp: Run tests on alpha-linux.
+	* ld-elfvers/*.sym, ld-elfvers/*.dsym: Adjust patters to match
+	Alpha's use of st_other.
+
+1998-09-27  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
+
+	* ld-elfvers/vers.exp (vers16, vers16a): New tests.
+	* ld-elfvers/{vers16.*, vers16a.*}: New files.
+
+Thu Sep 17 17:18:19 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-undefined/undefined.exp: Make undefined line test be an xfail
+	for arm/thunb elf toolchains.
+
+Wed Sep  9 14:10:15 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-undefined/undefined.exp: change test for elf/dwarf2 targets.
+
+	* ld-srec/srec.exp: Arm-elf now passes this test.
+
+Wed Aug 19 11:59:19 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-srec/srec.exp: Add arm/thumb-elf expected failures.
+
+Thu Aug 13 12:41:58 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-bootstrap/bootstrap.exp: Don't run the --static bootstrap
+	test if we don't have a static libbfd.a.
+
+Wed Aug 12 15:19:35 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	Based on patch from H.J. Lu <hjl@gnu.org>:
+	* ld-srec/srec.exp: Add xfails for Alpha ELF targets.
+
+Mon Aug 10 15:42:20 1998  Richard Henderson  <rth@cygnus.com>
+
+	* ld-scripts/weak.t (.text, .data): Focus data to be used.
+	(/DISCARD/): All the rest.
+	* ld-scripts/weak1.s, ld-scripts/weak2.s: Put stuff in .data.
+
+Fri Jul 24 18:37:17 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* config/default.exp: Create tmpdir/gas subdirectory, add a
+	symlink to as-new, and set gcc_gas_flag variable.
+	* lib/ld-lib.exp (default_ld_compile): If the compiler appears to
+	be gcc, use gcc_gas_flag when compiling.
+
+Thu Jul 23 12:23:29 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-elfvers/vers.exp: Just check for i?86 rather than checking
+	for i386, i486, and i586.
+	(objdump_versionstuff): If we can't find the line, dump the file.
+
+Fri Jul  3 00:27:41 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-scripts/phdrs.exp: Run test on *-*-eabi*.
+	* ld-scripts/weak.exp: Likewise.
+
+Wed Jul  1 10:51:46 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-srec/srec.exp: Add xfail for v850.
+
+	* ld-undefined/undefined.exp: arm and thumb PE toolchains now pass
+	these tests.
+
+Fri Jun 19 17:12:52 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-scripts/weak.exp: New test.
+	* ld-scripts/weak.t: New file.
+	* ld-scripts/weak1.s: New file.
+	* ld-scripts/weak2.s: New file.
+
+Tue Jun 16 12:40:38 1998  Geoff Keating  <geoffk@ozemail.com.au>
+
+	* ld-elfvers/vers.exp: Run tests on powerpc ELF targets.
+	* ld-shared/shared.exp: Likewise.
+	* ld-elfvers/vers1.dsym: Allow for .sdata.
+	* ld-srec/srec.exp: Add setup_xfails for PowerPC Linux.
+
+Fri May 29 15:02:50 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-srec/srec.exp: Add xfails for powerpc*-*-eabi.
+	(run_srec_test): On mn10200, define __truncsipsi2_do_d2.
+	* ld-srec/sr1.c (__main): Change return type to void.
+	* ld-srec/sr3.cc (__main): Likewise.
+	(__builtin_delete, __builtin_new): Likewise.
+	(__get_dynamic_handler_chain): Return 0.
+	(__get_eh_context): Likewise.
+
+Thu May 21 15:21:33 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-undefined/undefined.exp: Add support for thumb-pe target.
+	* ld-srec/srec.exp: Add support for arm-pe and thumb-pe targets.
+
+Mon May  4 17:54:20 1998  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
+
+	* ld-shared/shared.exp: Remove setup_xfails for m68k-linux.
+
+Mon May  4 17:12:06 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-shared/main.c (shlib_overriddencall2): New function.
+	(main): Call shlib_shlibcall2.
+	* ld-shared/sh1.c (shlib_shlibcall2): New function.
+	(shlib_overriddencall2): New function.
+	* ld-shared/shared.dat: Add output line for new test.
+	* ld-shared/sun4.dat: Likewise.
+
+	* ld-srec/sr3.cc (__get_eh_context): New function.
+
+Tue Apr  7 12:50:17 1998  Manfred Hollstein  <manfred@s-direktnet.de>
+
+	* ld-cdtest/cdtest-foo.h (class Foo): Declare len to be static to
+	avoid compiler warning.
+	* ld-srec/sr3.cc (class Foo): Likewise.
+
+Tue Feb 10 16:42:40 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-srec/sr3.cc (__get_dynamic_handler_chain): New function.
+
+Mon Feb  2 14:17:48 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-scripts/phdrs.exp: Adjust phdrs_regexp for a 64 bit target.
+
+Thu Dec 18 11:13:28 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-srec/srec.exp: Duplicated Arm patch for Thumb targets.
+
+Tue Dec  2 09:50:19 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-srec/srec.exp: Applied patch from Tony.Thompson@arm.com which
+	fixes ARM tests.
+
+Mon Dec  1 16:12:05 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* ld-srec/srec.exp: Add expected failures of tests 1 and 2 for ARM
+	coff targets.
+
+Wed Nov 12 14:18:31 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-cdtest/cdtest-foo.h (class Foo): Declare len to be int to
+	avoid compiler warning.
+	* ld-srec/sr3.cc (class Foo): Likewise.
+
+Mon Nov 10 14:25:43 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* lib/ld-lib.exp (default_ld_simple_link): Permit the linker to
+	have any name when looking for entry symbol warnings.
+
+	* ld-srec/sr3.cc (__eh_pc): Define.
+
+Mon Oct 20 14:36:39 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-srec/sr3.cc: Add definitions for terminate, __terminate, and
+	__throw, since the current g++ expects them to be defined.
+
+Fri Oct  3 12:24:03 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-elfvers/vers.exp (objdump_emptyverstuff): Accept the output
+	file if the string libc appears in it.
+	(objdump_versionstuff): Accept unexpected lines in the output
+	file.  Compare lines using string match.
+	* ld-elfvers/vers6.ver: Permit any value in the vna_other field.
+
+Tue Aug 12 16:01:22 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-scripts/crossref.exp: Correct string quoting.
+
+Sat Aug  9 00:56:03 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* config/default.exp: Change ld, as, nm and strip from .new to
+	-new.  Load ld-lib.exp rather than ld.exp.
+	* ld-bootstrap/bootstrap.exp: Use ld-new rather than ld.new.
+	* lib/ld-lib.exp: Rename from lib/ld.exp, for the benefit of
+	DejaGnu changes.
+
+Thu Jun 26 12:07:03 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-elfvers/vers.exp: Use egrep rather than grep when looking for
+	an alternation.  From Greg Margo <gmargo@dl.com>.
+
+Wed Jun 25 12:47:22 1997  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
+
+	* ld-shared/shared.exp: Add setup_xfail for m68k-linux on tests
+	with non PIC shared libraries.
+
+Fri Jun  6 17:35:47 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-elfvers/vers6.ver: Update for recent elflink.h patch to
+	version handling.
+
+Wed Jun  4 12:06:48 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-srec/srec.exp: Define ___get_dynamic_handler_chain as well.
+
+Fri May 30 12:21:39 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-srec/srec.exp: Define __get_dynamic_handler_chain when
+	linking.
+
+Mon May 12 11:17:55 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* config/default.exp: Use $base_dir rather than $objdir when
+	setting ld.  From John David Anglin <dave@hiauly1.hia.nrc.ca>.
+
+Fri Apr 25 09:07:00 1997  Jeffrey A Law  (law@cygnus.com)
+
+	* ld-srec/srec.exp: Define various out of line prologue/epilogue
+	functions for the mn10200 to avoid needing libgcc.a.
+
+Wed Mar 26 13:56:10 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-srec/srec.exp: Don't expect failures on mips*-*-elf*.
+
+Mon Mar 17 19:27:13 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-elfvers/vers.exp: Don't run on SunOS or AIX.
+
+Wed Mar 12 21:44:19 1997  Eric Youngdale  <eric@andante.jic.com>
+
+	* ld-elfvers/vers.exp, *: New tests for symbol versioning.
+	* config/default.exp: Set ar and strip.
+
+Fri Feb  7 16:47:02 1997  Bob Manson  <manson@charmed.cygnus.com>
+
+	* ld-bootstrap/bootstrap.exp: Use prune_warnings instead of
+	prune_system_crud.
+	* ld-cdtest/cdtest.exp: Ditto.
+	* ld-scripts/crossref.exp: Ditto.
+	* ld-sh/sh.exp: Ditto.
+	* ld-shared/shared.exp: Ditto.
+	* ld-srec/srec.exp: Ditto.
+	* lib/ld.exp: Ditto.
+
+Wed Jan 29 00:47:29 1997  Bob Manson  <manson@charmed.cygnus.com>
+
+	* ld-cdtest/cdtest.exp: Put a slash between $srcdir/$subdir.
+	* ld-scripts/script.exp: Ditto.
+	* ld-sh/sh.exp: Ditto.
+	* ld-undefined/undefined.exp: Ditto.
+	* ld-versados/versados.exp: Ditto.
+	* lib/ld.exp: Ditto.
+
+Mon Dec 30 17:08:04 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-scripts/crossref.exp: Fix quoting for --defsym $global$.
+
+Tue Oct  1 15:52:31 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* lib/ld.exp (default_ld_version): Fix for current version
+	printing.
+
+Fri Sep 13 15:51:45 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-scripts/crossref.exp: Define $global$ for hppa-elf.
+
+Thu Aug  8 14:29:32 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-scripts/cross2.t: Map XCOFF sections to .text or .data.
+
+	* lib/ld.exp: Use verbose -log instead of calling both verbose and
+	send_log.
+
+Wed Aug  7 18:00:58 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-scripts/phdrs.exp: New test.
+	* ld-scripts/phdrs.s, ld-scripts/phdrs.t: New files.
+
+Sun Aug  4 21:58:12 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-scripts/crossref.exp: On a29k targets, use --defsym to define
+	V_SPILL and V_FILL.
+
+Thu Aug  1 14:10:27 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-scripts/crossref.exp: New test.
+	* ld-scripts/{cross1.c, cross2.c, cross3.c}: New files.
+	* ld-scripts/{cross1.t, cross2.t}: New files.
+
+Sat Jun 29 13:40:11 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-sh/sh.exp: Fix debugging messages.
+	* ld-sh/sh1.s: Use .align 4.
+
+Wed May  1 16:45:13 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-sh/sh.exp: Use -O when compiling with -mrelax.
+
+Mon Apr 29 10:33:10 1996  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
+
+	* ld-shared/shared.exp: Run the shared library tests on
+	Linux/m68k.
+
+Fri Apr  5 16:20:55 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-shared/shared.exp: Run the shared library tests on Linux.
+
+Mon Feb 26 12:45:26 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-shared/shared.exp: Don't use -fpic on MIPS targets.
+
+Wed Jan 31 15:09:57 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* ld-srec/srec.exp: Add xfails for hppa*-*-*elf*.
+	* ld-undefined/undefined.exp: Likewise.
+
+Fri Jan 26 18:43:03 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-undefined/undefined.exp: ELF targets should now pass the
+	undefined line test.
+
+Thu Jan 25 15:36:13 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-empic/empic.exp: Update for change to MIPS disassembler.
+
+Mon Jan 15 15:05:53 1996  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-bootstrap/bootstrap.exp: Expect failure for mips*-*-irix5*
+	when doing the --static test.
+	* ld-shared/shared.exp: Run tests on mips*-*-irix5*.
+
+Fri Dec 29 12:33:09 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-bootstrap/bootstrap.exp: On AIX, don't pass the -bI option
+	when creating ld-partial.o.
+
+Tue Dec 26 17:37:23 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-srec/srec.exp: If powerpc*-*-eabi*, use --defsym to define
+	__eabi.
+
+Tue Dec 19 18:01:01 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-srec/srec.exp: Add setup_xfails for XCOFF targets.
+
+Fri Dec 15 16:36:17 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-srec/srec.exp: On a29k targets, use --defsym to define
+	V_SPILL and V_FILL.
+	* ld-srec/sr1.c (V_SPILL, V_FILL): Remove definitions.
+	* ld-srec/sr3.cc: Likewise.
+
+	* ld-srec/srec.exp: Remove i960 COFF setup_xfail.
+
+Sat Dec  2 01:20:31 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-srec/srec.exp: Don't use [] in setup_xfail expressions.
+
+Fri Dec  1 13:18:18 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-srec/srec.exp: Add setup_xfails for MIPS ELF targets.
+
+Wed Nov 29 13:01:10 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-srec/srec.exp: Add setup_xfail for i960 COFF targets.
+
+Mon Nov 27 14:36:11 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-srec/srec.exp: Add setup_xfail calls for i[345]86-*-aout*.
+
+	* ld-srec/sr1.c (V_SPILL, V_FILL): Define.
+	* ld-srec/sr3.cc: Likewise.
+
+Tue Nov 21 16:05:53 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-empic/empic.exp: Update for changes in objdump output.
+
+Wed Nov 15 17:42:48 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-srec/srec.exp: New tests.
+	* ld-srec/sr1.c, ld-srec/sr2.c, ld-srec/sr3.cc: New files.
+	* lib/ld.exp (ld_simple_link): Discard warnings about not being
+	able to find the entry symbol.
+
+Tue Nov 14 20:03:54 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-sh/sh2.c (__main): Define.
+
+Mon Nov  6 14:39:18 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-empic/empic.exp: Accept a . in the address symbol.
+
+	* ld-shared/shared.exp: Run tests on rs6000*-*-aix* and
+	powerpc*-*-aix*.  Add code to create appropriate exports files,
+	and pass appropriate compilation flags, and test against
+	appropriate expected output.
+	* ld-shared/xcoff.dat: New file.
+	* ld-shared/main.c: Put #ifndef XCOFF_TEST around tests that can
+	not be linked using XCOFF.  Use shlib_shlibvar1 as a sample
+	function pointer, rather than shlib_mainvar.
+	* ld-shared/sh1.c: Likewise.
+	* ld-shared/shared.dat: Update for change from using shlib_mainvar
+	to using shlib_shlibvar1.
+	* ld-shared/sun4.dat: Likewise.
+
+Sat Oct 28 01:54:25 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-scripts/script.t: Put .pr in .text, and .rw in .data, for
+	convenience when testing XCOFF.
+
+Thu Oct 26 22:53:17 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-bootstrap/bootstrap.exp: On AIX, pass -bI/lib/syscalls.exp
+	along with --static.
+
+	* ld-scripts/script.s: Make symbols global.
+
+Fri Oct 20 12:22:16 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-undefined/undefined.exp: Add setup_xfails for arm*-*-pe*.
+
+Fri Sep 29 11:06:10 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-undefined/undefined.exp: Use -e when invoking the linker, to
+	prevent the SunOS linker from trying to create a shared library.
+
+Thu Sep 28 12:37:14 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-shared/shared.exp: Run the tests on sparc*-*-sunos4*.  Add
+	appropriate modifications and setup_xfails.
+	* ld-shared/sun4.dat: New file.
+
+Mon Sep 18 14:12:56 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* lib/ld.exp (default_ld_version): Call prune_system_crud.
+	(default_ld_relocate, default_ld_link): Likewise.
+	(default_ld_simple_link, default_ld_compile): Likewise.
+	(default_ld_assemble, default_ld_nm): Likewise.
+
+Fri Sep  8 17:15:38 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-cdtest/cdtest.exp: If the compiler does not exist, mark the
+	tests as untested rather than unresolved.
+
+Wed Aug 23 10:46:38 1995  Ian Lance Taylor  (ian@cygnus.com)
+
+	* ld-sh/sh.exp: Call prune_system_crud on the output of cmp.
+
+Tue Aug 15 17:35:35 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-scripts/script.exp: Split script verification into a proc.
+	Add simple test of MRI script.
+	* ld-scripts/scriptm.t: New file.
+
+Wed Jul 26 11:38:58 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-sh/sh.exp: Mark `SH confirm relaxing' test unresolved when
+	appropriate.
+
+Mon Jul 24 15:34:31 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* config/default.exp: Define objcopy if it is not defined.
+	* ld-sh/*: New tests for SH relaxing.
+
+	* ld-empic/empic.exp: If $CC does not exist, call untested rather
+	than unresolved.
+
+Thu Jul 20 15:09:26 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-undefined/undefined.exp: If $CC does not exist, mark the
+	tests as untested rather than unresolved.  Clear ELF xfails for
+	mips*, not just mips.
+
+Tue Jul 18 12:00:41 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-undefined/undefined.exp: Add setup_xfail for sh-*-* for
+	undefined line test.
+
+Fri Jul 14 13:07:48 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-undefined/undefined.exp: New test, to check reporting of
+	undefined symbols.
+	* ld-undefined/undefined.c: New file.
+
+Mon Jul 10 11:13:39 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-versados/versados.exp: If a test fails, report it correctly:
+	don't try to run the next test, and don't report a pass as well as
+	a fail.
+
+Mon Jul  3 14:26:37 1995  Steve Chamberlain  <sac@slash.cygnus.com>
+
+	* versados/(t1,t2).ld: End in newlines.
+
+Mon May 22 20:19:38 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	* lib/ld.exp (default_ld_compile): If cc argument is multiple
+	words, use only the first when trying to verify the availability
+	of the compiler.
+
+Mon Feb  6 11:46:49 1995  Ian Lance Taylor  <ian@cygnus.com>
+
+	* ld-scripts/defined.t: Mention .data and .bss explicitly.
+
+Tue Jan 24 14:51:48 1995  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+
+	* ld-bootstrap/bootstrap.exp: If not in the ld build directory,
+	call untested for each test, rather than ignoring it.  If one test
+	fails, go on to the next one instead of returning.
+	* ld-cdtest/cdtest.exp: If compilations fail, mark tests as
+	unresolved.
+	* ld-empic/empic.exp: Likewise.  Also, always pass the same test
+	name to pass or fail.
+	* ld-shared/shared.exp: Likewise.  Also, always run all tests.
+	* ld-scripts/defined.exp: If as or nm fail, mark test as
+	unresolved.  Always pass the same test name to pass or fail.
+	* ld-scripts/script.exp: Likewise.
+	* ld-scripts/sizeof.exp: Likewise.
+
+Wed Jan 11 11:48:31 1995  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+
+	* ld-scripts/sizeof.exp: New test, based on bug report from
+	anders.blomdell@control.lth.se.
+	* ld-scripts/sizeof.s: New file.
+	* ld-scripts/sizeof.t: New file.
+
+Wed Jan  4 18:56:27 1995  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+
+	* lib/ld.exp: Use [which $ld] rather than [file exists $ld] to see
+	if the linker exists.
+
+Wed Dec 14 16:39:03 1994  Ken Raeburn  <raeburn@cujo.cygnus.com>
+
+	* lib/ld.exp (prune_system_crud): Define if not already defined,
+	in case the user isn't using the newest DejaGnu version that we
+	haven't released to the net yet.
+
+Fri Dec  2 14:17:02 1994  Ian Lance Taylor  <ian@rtl.cygnus.com>
+
+	* config/default.exp: Define objdump if it is not defined.
+	* ld-empic/*: New tests to test -membedded-pic code.
+
+Mon Nov 28 11:24:36 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+
+	* ld-bootstrap/bootstrap.exp: Pass cmp output through
+	prune_system_crud.
+	* ld-cdtest/cdtest.exp: Pass diff output through
+	prune_system_crud.
+	* ld-shared/shared.exp: Likewise.
+
+	* config/default.exp: Remove unused and useless proc ld_load.
+
+Sun Oct 30 13:02:34 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+
+	* lib/ld.exp (default_ld_compile): Remove the output file before
+	compiling.
+
+	* ld-shared/shared.exp: Move common test code into a procedure.
+	Add tests for compiling the non shared code PIC.
+	* ld-shared/main.c (main): Call main_called, and print the result.
+	* ld-shared/shared.dat: Adjust accordingly.
+
+Thu Oct 27 17:30:12 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
+
+	* ld-shared: New directory, with new files to test generating ELF
+	shared libraries.
+
+	* lib/ld.exp (default_ld_compile): If the compilation worked, but
+	no object file was created, check to see if the compiler foolishly
+	ignored the -o switch when compiling, and move the resulting
+	object if it did.
+
+Thu Sep 29 12:36:51 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
+
+	* VMS does not permits `.' in directory names.  Renamed
+	ld.bootstrap to ld-bootstrap, ld.cdtest to ld-cdtest, and
+	ld.scripts to ld-scripts.
+
+Wed Sep 28 12:18:54 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
+
+	* config/default.exp: Set variables as and nm.  Create tmpdir if
+	it does not already exist.
+	* ld.bootstrap/bootstrap.exp: Don't create tmpdir here.
+	* ld.cdtest/cdtest.exp: Likewise.
+	* ld.scripts/defined.exp: Likewise.  Also, don't set as and nm
+	here.  Change perror for no variables found to fail.
+	* ld.scripts/script.exp: New test.
+	* ld.scripts/script.t, ld.scripts/script.s: New files.
+
+Tue Sep 27 14:59:51 1994  Ian Lance Taylor  (ian@sanguine.cygnus.com)
+
+	* ld.scripts: New directory.
+	* ld.scripts/defined.exp, ld.scripts/defined.s: New files.
+	* ld.scripts/defined.t: New file.
+	* lib/ld.exp (default_ld_simple_link): New function.
+	(default_ld_assemble, default_ld_nm): New functions.
+	* config/default.exp: Rename from unix-ld.exp.
+	(ld_simple_link, ld_assemble, ld_nm): New functions.
+
+	* config/unix-ld.exp: Set ld using findfile.
+	* lib/ld.exp (default_ld_relocate): Return a value.  Change format
+	of log messages.
+	(default_ld_compile): Likewise.
+	(default_ld_link): Likewise.  Also, don't include $BFDLIB and
+	$LIBIBERTY in link.
+	* ld.bootstrap/bootstrap.exp: Rewrite.
+	* ld.cdtest/cdtest.exp: Rewrite.
+	* ld.cdtest/cdtest-foo.cc: Update from top level ld directory.
+	* ld.cdtest/cdtest-foo.h: Likewise.
+	* ld.cdtest/cdtest-main.cc: Likewise.
+
+Fri May 27 09:35:04 1994  Ken Raeburn  (raeburn@cygnus.com)
+
+	* ld.cdtest/cdtest.exp: Don't look for $result before it's
+	defined.
+
+Tue May 17 15:06:49 1994  Bill Cox  (bill@rtl.cygnus.com)
+
+	* ld.bootstrap/bootstrap.exp, lib/ld.exp: Replace error proc
+	calls with perror calls.
+
+Wed May 11 16:47:46 1994  Ken Raeburn  (raeburn@rtl.cygnus.com)
+
+	* ld.cdtest/cdtest-bar.cc: Renamed from cdtest-func.cc.
+	* ld.cdtest/cdtest.exp: Adjusted.
+
+Fri Jan 28 13:25:41 1994  Ken Raeburn  (raeburn@cujo.cygnus.com)
+
+	* lib/ld.exp (simple_diff): Indicate failure if files have
+	different numbers of lines.  Don't muck with $differences to avoid
+	indicating a pass, just return.
+
+	* ld.cdtest/{cdtest-foo.h,cdtest-foo.cc,cdtest-main.cc}:
+	Fix test case to be valid ANSI C++.  Don't require use of header
+	files, so "../gcc/xgcc -B../gcc/" can be used for CXX.
+	* ld.cdtest/cdtest.exp: Combine "rm" lines.  Add some
+	commentary on things that are still broken with this test case.
+
+Fri Sep 10 09:58:23 1993  Jeffrey Wheat  (cassidy@cygnus.com)
+
+	* ld.cdtest/cdtest.exp: Added CXXFLAGS to compile stage.
+
+Thu Aug 12 16:05:37 1993  Jeffrey Wheat  (cassidy@cygnus.com)
+
+	* lib/ld.exp: add compiler and linker support
+	* config/unix-ld.exp: add compiler and linker support
+	* ld.bootstrap/bootstrap.exp: fixed to do partial links
+	* ld.cdtest/cdtest.exp: constructor/destructor testscase
+
+Wed Aug  4 21:00:18 1993  Jeffrey Wheat  (cassidy@cygnus.com)
+
+	* lib/ld.exp: new file
+	* config/unix-ld.exp: new file
+	* ld.bootstrap/bootstrap.exp: new file
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/binutils-2.19/ld/testsuite/config/default.exp b/binutils-2.19/ld/testsuite/config/default.exp
new file mode 100644
index 0000000..ab35ecf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/config/default.exp
@@ -0,0 +1,270 @@
+# Basic expect script for LD Regression Tests
+#   Copyright 1993, 1994, 1995, 1997, 1998, 1999, 2001, 2003, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This file is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Jeffrey Wheat (cassidy@cygnus.com)
+#
+
+if ![info exists ld] then {
+    set ld [findfile $base_dir/ld-new $base_dir/ld-new [transform ld]]
+}
+
+if ![info exists as] then {
+    set as [findfile $base_dir/../gas/as-new $base_dir/../gas/as-new [transform as]]
+}
+
+if ![info exists nm] then {
+    set nm [findfile $base_dir/../binutils/nm-new $base_dir/../binutils/nm-new [transform nm]]
+}
+
+if ![info exists objdump] then {
+    set objdump [findfile $base_dir/../binutils/objdump]
+}
+
+if ![info exists objcopy] then {
+    set objcopy [findfile $base_dir/../binutils/objcopy]
+}
+
+if ![info exists ar] then {
+    set ar [findfile $base_dir/../binutils/ar]
+}
+
+if ![info exists strip] then {
+    set strip [findfile $base_dir/../binutils/strip-new $base_dir/../binutils/strip-new [transform strip]]
+}
+
+remote_exec host "mkdir -p tmpdir"
+
+# Make a symlink from tmpdir/as to the assembler in the build tree, so
+# that we can use a -B option to gcc to force it to use the newly
+# built assembler.
+if {![file isdirectory tmpdir/gas]} then {
+    catch "exec mkdir tmpdir/gas" status
+    catch "exec ln -s ../../../gas/as-new tmpdir/gas/as" status
+}
+set gcc_gas_flag "-B[pwd]/tmpdir/gas/"
+
+# Make a symlink from tmpdir/ld to the linker in the build tree, so
+# that we can use a -B option to gcc to force it to use the newly
+# built linker. 
+if {![file isdirectory tmpdir/ld]} then {
+    catch "exec mkdir tmpdir/ld" status
+    catch "exec ln -s ../../ld-new tmpdir/ld/ld" status
+}
+set gcc_ld_flag "-B[pwd]/tmpdir/ld/"
+
+# load the linker path
+if {[file exists tmpdir/libpath.exp]} {
+    load_lib tmpdir/libpath.exp
+
+    foreach dir $libpath {
+	set gcc_ld_flag "$gcc_ld_flag -L$dir"
+    }
+}
+
+# The "make check" target in the Makefile passes in
+# "CC=$(CC_FOR_TARGET)".  But, if the user invokes runtest directly
+# (as when testing an installed linker), these flags may not be set.  
+if {![info exists CC]} {
+    set CC [find_gcc]
+}
+if {![info exists CFLAGS]} {
+    set CFLAGS "-g -O2"
+}
+if {![info exists CXX]} {
+    set CXX [find_g++]
+}
+if {![info exists CXXFLAGS]} {
+    set CXXFLAGS ""
+}
+
+# The mips64-*-linux-gnu compiler defaults to the N32 ABI after
+# installed, but to the O32 ABI in the build tree, because of some
+# specs-file hacks.  Make sure we use an ABI that is compatible with
+# the one we expect.
+if {[istarget mips64*-*-linux*] &&
+    (![board_info [target_info name] exists multilib_flags] ||
+     ![string match "*-mabi" [board_info [target_info name] multilib_flags]])
+   } {
+    append gcc_gas_flag " -mabi=n32"
+}
+
+# load the utility procedures
+load_lib ld-lib.exp
+
+proc get_link_files {varname} {
+    global $varname
+    global target_triplet
+    global srcdir
+    global CC
+    if ![info exists $varname] {
+	set status [catch "exec sh -c \"host='$target_triplet' && CC='$CC' && . $srcdir/../configure.host && eval echo \\$$varname\"" result]
+	if $status { error "Error getting native link files: $result" }
+	set $varname $result
+    }
+}
+
+proc get_target_emul {} {
+    global target_triplet
+    global srcdir
+    set status [catch "exec sh -c \"targ='$target_triplet' && . $srcdir/../configure.tgt && echo \\\$targ_emul\"" result]
+    if $status { error "Error getting emulation name: $result" }
+    return $result
+}
+
+if [isnative] {
+    foreach x {HOSTING_CRT0 HOSTING_LIBS} {
+	get_link_files $x
+    }
+} else {
+    foreach x {HOSTING_CRT0 HOSTING_LIBS} { set $x "" }
+}
+if ![info exists HOSTING_EMU] { set HOSTING_EMU "-m [get_target_emul]" }
+
+#
+# ld_version -- extract and print the version number of ld compiler (GCC)
+#
+proc ld_version {} {
+    global ld
+    default_ld_version $ld
+}
+
+#
+# ld_exit -- just a stub for ld
+#
+proc ld_exit {} {
+}
+
+#
+# ld_start 
+#	relink the linker
+#
+proc ld_start { ld target } {
+	#
+}
+
+#
+# ld_relocate 
+#	link an object using relocation
+#
+proc ld_relocate { ld target objects } {
+	default_ld_relocate $ld $target $objects
+}
+
+#
+# ld_link 
+#	link a program using ld
+#
+proc ld_link { ld target objects } {
+	default_ld_link $ld $target $objects
+}
+
+#
+# ld_simple_link 
+#	link a program using ld, without including any libraries
+#
+proc ld_simple_link { ld target objects } {
+	default_ld_simple_link $ld $target $objects
+}
+
+#
+# ld_compile 
+#	compile an object using $cc
+#
+proc ld_compile { cc source object } {
+	default_ld_compile $cc $source $object 
+}
+
+#
+# ld_assemble
+#	assemble a file
+#
+proc ld_assemble { as source object } {
+	default_ld_assemble $as $source $object 
+}
+
+#
+# ld_nm
+#	run nm on a file
+#
+proc ld_nm { nm nmflags object } {
+	default_ld_nm $nm $nmflags $object
+}
+
+#
+# ld_exec
+#	execute ithe target
+#
+proc ld_exec { target output } {
+	default_ld_exec $target $output
+}
+
+# From gas-defs.exp, to support run_dump_test.
+if ![info exists AS] then {
+    set AS $as
+}
+
+if ![info exists GASP] then {
+    set GASP [findfile $base_dir/../gas/gasp-new $base_dir/../gas/gasp-new [transform gasp]]
+}
+
+if ![info exists ASFLAGS] then {
+    set ASFLAGS ""
+}
+
+if ![info exists OBJDUMP] then {
+    set OBJDUMP $objdump
+}
+
+if ![info exists OBJDUMPFLAGS] then {
+    set OBJDUMPFLAGS {}
+}
+
+if ![info exists NM] then {
+    set NM $nm
+}
+
+if ![info exists NMFLAGS] then {
+    set NMFLAGS {}
+}
+
+if ![info exists OBJCOPY] then {
+    set OBJCOPY $objcopy
+}
+
+if ![info exists OBJCOPYFLAGS] then {
+    set OBJCOPYFLAGS {}
+}
+
+if ![info exists READELF] then {
+    set READELF [findfile $base_dir/../binutils/readelf]
+}
+
+if ![info exists READELFFLAGS] then {
+    set READELFFLAGS {}
+}
+
+if ![info exists LD] then {
+    set LD [findfile $base_dir/ld-new ./ld-new [transform ld]]
+}
+
+if ![info exists LDFLAGS] then {
+    set LDFLAGS {}
+}
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/align.s b/binutils-2.19/ld/testsuite/ld-alpha/align.s
new file mode 100644
index 0000000..6c48ba9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/align.s
@@ -0,0 +1,9 @@
+	/* Force .data aligned to 4K, so that .got very likely gets
+	   placed at 0x1200131d0.  */
+	.data
+	.balign	4096
+
+	/* Force .text aligned to 4K, so it very likely gets placed at
+	   0x120001000.  */
+	.text
+	.balign	4096
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/alpha.exp b/binutils-2.19/ld/testsuite/ld-alpha/alpha.exp
new file mode 100644
index 0000000..263053e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/alpha.exp
@@ -0,0 +1,64 @@
+# Expect script for ld-alpha tests
+#   Copyright (C) 2003, 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Test Alpha ELF linking; all types of relocs.  This tests the
+# assembler and tools like objdump as well as the linker.
+
+if { !([istarget "alpha*-*-elf*"]
+       || [istarget "alpha*-*-linux*"]) } {
+    return
+}
+
+# List contains test-items with 3 items followed by 2 lists:
+# 0:name 1:ld options 2:assembler options
+# 3:filenames of assembler files 4: action and options. 5: name of output file
+
+# Actions:
+# objdump: Apply objdump options on result.  Compare with regex (last arg).
+# nm: Apply nm options on result.  Compare with regex (last arg).
+# readelf: Apply readelf options on result.  Compare with regex (last arg).
+
+set alphatests {
+    {"TLS -fpic -shared" "-shared -melf64alpha"
+     "" {align.s tlspic1.s tlspic2.s}
+     {{readelf -WSsrl tlspic.rd} {objdump -drj.text tlspic.dd}
+      {objdump -sj.got tlspic.sd} {objdump -sj.tdata tlspic.td}}
+      "libtlspic.so"}
+    {"Helper shared library" "-shared -melf64alpha"
+     "" {tlslib.s} {} "libtlslib.so"}
+    {"TLS -fpic and -fno-pic exec"
+     "-melf64alpha tmpdir/libtlslib.so" "" {align.s tlsbinpic.s tlsbin.s}
+     {{readelf -WSsrl tlsbin.rd} {objdump -drj.text tlsbin.dd}
+      {objdump -sj.got tlsbin.sd} {objdump -sj.tdata tlsbin.td}}
+      "tlsbin"}
+    {"TLS -fpic and -fno-pic exec -relax"
+     "-relax -melf64alpha tmpdir/libtlslib.so" "" {align.s tlsbinpic.s tlsbin.s}
+     {{readelf -WSsrl tlsbinr.rd} {objdump -drj.text tlsbinr.dd}
+      {objdump -sj.got tlsbinr.sd}}
+      "tlsbinr"}
+}
+
+# Not implemented yet
+#   {"TLS in debug sections" "-melf64alpha"
+#    "" {tlsg.s}
+#    {{objdump -sj.debug_foobar tlsg.sd}} "tlsg"}
+
+run_ld_link_tests $alphatests
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlsbin.dd b/binutils-2.19/ld/testsuite/ld-alpha/tlsbin.dd
new file mode 100644
index 0000000..674ec37
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlsbin.dd
@@ -0,0 +1,62 @@
+#source: align.s
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as:
+#ld: -melf64alpha
+#objdump: -drj.text
+#target: alpha*-*-*
+
+.*: +file format elf64-alpha
+
+Disassembly of section \.text:
+
+0+120001000 <fn2>:
+   120001000:	02 00 bb 27 	ldah	gp,2\(t12\)
+   120001004:	c0 82 bd 23 	lda	gp,-32064\(gp\)
+   120001008:	3e 15 c2 43 	subq	sp,0x10,sp
+   12000100c:	00 00 5e b7 	stq	ra,0\(sp\)
+   120001010:	18 80 1d 22 	lda	a0,-32744\(gp\)
+   120001014:	08 80 7d a7 	ldq	t12,-32760\(gp\)
+   120001018:	00 40 5b 6b 	jsr	ra,\(t12\),12000101c <.*>
+   12000101c:	02 00 ba 27 	ldah	gp,2\(ra\)
+   120001020:	a4 82 bd 23 	lda	gp,-32092\(gp\)
+   120001024:	38 80 1d 22 	lda	a0,-32712\(gp\)
+   120001028:	08 80 7d a7 	ldq	t12,-32760\(gp\)
+   12000102c:	00 40 5b 6b 	jsr	ra,\(t12\),120001030 <.*>
+   120001030:	02 00 ba 27 	ldah	gp,2\(ra\)
+   120001034:	90 82 bd 23 	lda	gp,-32112\(gp\)
+   120001038:	28 80 1d 22 	lda	a0,-32728\(gp\)
+   12000103c:	08 80 7d a7 	ldq	t12,-32760\(gp\)
+   120001040:	00 40 5b 6b 	jsr	ra,\(t12\),120001044 <.*>
+   120001044:	02 00 ba 27 	ldah	gp,2\(ra\)
+   120001048:	7c 82 bd 23 	lda	gp,-32132\(gp\)
+   12000104c:	21 00 20 20 	lda	t0,33\(v0\)
+   120001050:	28 80 1d 22 	lda	a0,-32728\(gp\)
+   120001054:	08 80 7d a7 	ldq	t12,-32760\(gp\)
+   120001058:	00 40 5b 6b 	jsr	ra,\(t12\),12000105c <.*>
+   12000105c:	02 00 ba 27 	ldah	gp,2\(ra\)
+   120001060:	64 82 bd 23 	lda	gp,-32156\(gp\)
+   120001064:	40 00 20 20 	lda	t0,64\(v0\)
+   120001068:	46 00 20 20 	lda	t0,70\(v0\)
+   12000106c:	00 00 20 24 	ldah	t0,0\(v0\)
+   120001070:	4b 00 21 20 	lda	t0,75\(t0\)
+   120001074:	10 80 3d a4 	ldq	t0,-32752\(gp\)
+   120001078:	01 04 20 40 	addq	t0,v0,t0
+   12000107c:	00 00 5e a7 	ldq	ra,0\(sp\)
+   120001080:	1e 14 c2 43 	addq	sp,0x10,sp
+   120001084:	01 80 fa 6b 	ret
+
+0+120001088 <_start>:
+   120001088:	9e 00 00 00 	rduniq
+   12000108c:	09 04 e0 47 	mov	v0,s0
+   120001090:	00 80 3d a4 	ldq	t0,-32768\(gp\)
+   120001094:	01 04 29 40 	addq	t0,s0,t0
+   120001098:	48 80 3d a4 	ldq	t0,-32696\(gp\)
+   12000109c:	01 04 29 40 	addq	t0,s0,t0
+   1200010a0:	10 00 29 20 	lda	t0,16\(s0\)
+   1200010a4:	96 00 29 20 	lda	t0,150\(s0\)
+   1200010a8:	00 00 29 24 	ldah	t0,0\(s0\)
+   1200010ac:	57 00 21 20 	lda	t0,87\(t0\)
+   1200010b0:	50 80 3d a4 	ldq	t0,-32688\(gp\)
+   1200010b4:	01 04 29 40 	addq	t0,s0,t0
+   1200010b8:	01 80 fa 6b 	ret
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlsbin.rd b/binutils-2.19/ld/testsuite/ld-alpha/tlsbin.rd
new file mode 100644
index 0000000..7641cce
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlsbin.rd
@@ -0,0 +1,133 @@
+#source: align.s
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as:
+#ld: -melf64alpha
+#readelf: -WSsrl
+#target: alpha*-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0
+ +\[[ 0-9]+\] .interp +.*
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .rela.plt +.*
+ +\[[ 0-9]+\] .text +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +AX +0 +0 4096
+ +\[[ 0-9]+\] .eh_frame +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +A +0 +0 +8
+ +\[[ 0-9]+\] .tdata +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 WAT +0 +0 +4
+ +\[[ 0-9]+\] .tbss +NOBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 10 +WA +4 +0 +8
+ +\[[ 0-9]+\] .plt +.*
+ +\[[ 0-9]+\] .got +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +WA +0 +0 +8
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+#...
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x[0-9a-f]+
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  PHDR +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+150 R E 0x8
+  INTERP +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x1
+.*Requesting program interpreter.*
+  LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R E 0x10000
+  LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RWE 0x10000
+  DYNAMIC +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW +0x8
+  TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x4
+#...
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 3 entries:
+ +Offset +Info +Type +Symbol's Value  Symbol's Name \+ Addend
+[0-9a-f]+  [0-9a-f]+ R_ALPHA_TPREL64 +0+ sG2 \+ 0
+[0-9a-f]+  [0-9a-f]+ R_ALPHA_DTPMOD64 +0+ sG1 \+ 0
+[0-9a-f]+  [0-9a-f]+ R_ALPHA_DTPREL64 +0+ sG1 \+ 0
+
+Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ +Offset +Info +Type +Symbol's Value  Symbol's Name \+ Addend
+[0-9a-f]+  [0-9a-f]+ R_ALPHA_JMP_SLOT +[0-9a-f]+ __tls_get_addr \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+[0-9 ]+: [0-9a-f]+ +0 NOTYPE +LOCAL +DEFAULT +UND *
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +UND sG2
+[0-9 ]+: [0-9a-f]+ +0 FUNC +GLOBAL DEFAULT +UND __tls_get_addr
+[0-9 ]+: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +UND sG1
+[0-9 ]+: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _edata
+[0-9 ]+: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+[0-9 ]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +1 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +2 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +3 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +4 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +5 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +6 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +7 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +8 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +9 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +10 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +11 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +12 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +13 
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl1
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl2
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl3
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl4
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl5
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl6
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl7
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl8
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl1
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl2
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl3
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl4
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl5
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl6
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl7
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl8
+[0-9 ]+: [0-9a-f]+ +0 OBJECT +LOCAL +HIDDEN +11 _DYNAMIC
+[0-9 ]+: [0-9a-f]+ +0 OBJECT +LOCAL +HIDDEN +12 _PROCEDURE_LINKAGE_TABLE_
+[0-9 ]+: [0-9a-f]+ +0 OBJECT +LOCAL +HIDDEN +13 _GLOBAL_OFFSET_TABLE_
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg8
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg8
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg6
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg3
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg3
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh3
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +UND sG2
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg4
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg5
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg5
+[0-9 ]+: [0-9a-f]+ +0 FUNC +GLOBAL DEFAULT +UND __tls_get_addr
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh7
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh8
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg1
+[0-9 ]+: [0-9a-f]+ +52 FUNC +GLOBAL DEFAULT +7 _start
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh4
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg7
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh5
+[0-9 ]+: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+[0-9 ]+: [0-9a-f]+ +136 FUNC +GLOBAL DEFAULT +\[<other>: 88\] +7 fn2
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg2
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +UND sG1
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh1
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg6
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg7
+[0-9 ]+: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _edata
+[0-9 ]+: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _end
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh2
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh6
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg2
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg1
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg4
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlsbin.s b/binutils-2.19/ld/testsuite/ld-alpha/tlsbin.s
new file mode 100644
index 0000000..a772a7e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlsbin.s
@@ -0,0 +1,46 @@
+	.section ".tbss", "awT", @nobits
+	.globl bg1, bg2, bg3, bg4, bg5, bg6, bg7, bg8
+bg1:	.space 4
+bg2:	.space 4
+bg3:	.space 4
+bg4:	.space 4
+bg5:	.space 4
+bg6:	.space 4
+bg7:	.space 4
+bg8:	.space 4
+bl1:	.space 4
+bl2:	.space 4
+bl3:	.space 4
+bl4:	.space 4
+bl5:	.space 4
+bl6:	.space 4
+bl7:	.space 4
+bl8:	.space 4
+
+	.text
+	.globl	_start
+	.ent	_start
+_start:
+	rduniq
+	mov	$0, $9
+
+	/* IE */
+	ldq	$1, sG2($gp)	!gottprel
+	addq	$1, $9, $1
+
+	/* IE against global symbol in exec */
+	ldq	$1, bl1($gp)	!gottprel
+	addq	$1, $9, $1
+
+	/* LE */
+	lda	$1, sg1($9)	!tprel
+	lda	$1, bl2+2($9)	!tprel
+
+	ldah	$1, sh2+3($9)	!tprelhi
+	lda	$1, sh2+3($1)	!tprello
+
+	ldq	$1, bl2+4($gp)	!gottprel
+	addq	$1, $9, $1
+
+	ret
+	.end	_start
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlsbin.sd b/binutils-2.19/ld/testsuite/ld-alpha/tlsbin.sd
new file mode 100644
index 0000000..1bf0278
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlsbin.sd
@@ -0,0 +1,17 @@
+#source: align.s
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as:
+#ld: -melfalpha
+#objdump: -sj.got
+#target: alpha*-*-*
+
+.*: +file format elf64-alpha
+
+Contents of section .got:
+ [0-9a-f]+ 00000000 00000000 b0120120 01000000  .*
+ [0-9a-f]+ 56000000 00000000 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 01000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 01000000 00000000  .*
+ [0-9a-f]+ 24000000 00000000 90000000 00000000  .*
+ [0-9a-f]+ 98000000 00000000                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlsbin.td b/binutils-2.19/ld/testsuite/ld-alpha/tlsbin.td
new file mode 100644
index 0000000..8bd7a6c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlsbin.td
@@ -0,0 +1,17 @@
+#source: align.s
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as:
+#ld: -melf64alpha
+#objdump: -sj.tdata
+#target: alpha*-*-*
+
+.*: +file format elf64-alpha
+
+Contents of section .tdata:
+ 1?200110f0 11000000 12000000 13000000 14000000  .*
+ 1?20011100 15000000 16000000 17000000 18000000  .*
+ 1?20011110 41000000 42000000 43000000 44000000  .*
+ 1?20011120 45000000 46000000 47000000 48000000  .*
+ 1?20011130 01010000 02010000 03010000 04010000  .*
+ 1?20011140 05010000 06010000 07010000 08010000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlsbinpic.s b/binutils-2.19/ld/testsuite/ld-alpha/tlsbinpic.s
new file mode 100644
index 0000000..7a94eb1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlsbinpic.s
@@ -0,0 +1,74 @@
+	.section ".tdata", "awT", @progbits
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+
+	.text
+	.globl	fn2
+	.ent	fn2
+fn2:
+	.frame	$sp, 16, $26, 0
+	ldgp	$gp, 0($27)
+	subq	$sp, 16, $sp
+	stq	$26, 0($sp)
+	.prologue 1
+	
+	/* GD */
+	lda	$16, sG1($gp)			!tlsgd!1
+	ldq	$27, __tls_get_addr($gp)	!literal!1
+	jsr	$26, ($27), __tls_get_addr	!lituse_tlsgd!1
+	ldgp	$gp, 0($26)
+
+	/* GD against local symbol */
+	lda	$16, sl2($gp)			!tlsgd!2
+	ldq	$27, __tls_get_addr($gp)	!literal!2
+	jsr	$26, ($27), __tls_get_addr	!lituse_tlsgd!2
+	ldgp	$gp, 0($26)
+
+	/* LD */
+	lda	$16, sl1($gp)			!tlsldm!3
+	ldq	$27, __tls_get_addr($gp)	!literal!3
+	jsr	$26, ($27), __tls_get_addr	!lituse_tlsldm!3
+	ldgp	$gp, 0($26)
+	lda	$1, sl1+1($0)			!dtprel
+
+	/* LD with 4 variables */
+	lda	$16, sh1($gp)			!tlsldm!4
+	ldq	$27, __tls_get_addr($gp)	!literal!4
+	jsr	$26, ($27), __tls_get_addr	!lituse_tlsldm!4
+	ldgp	$gp, 0($26)
+	lda	$1, sh1($0)			!dtprel
+	lda	$1, sh2+2($0)			!dtprel
+	ldah	$1, sh3+3($0)			!dtprelhi
+	lda	$1, sh3+3($1)			!dtprello
+	ldq	$1, sh4+10($gp)			!gotdtprel
+	addq	$1, $0, $1
+
+	ldq	$26, 0($sp)
+	addq	$sp, 16, $sp
+	ret
+	.end	fn2
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlsbinr.dd b/binutils-2.19/ld/testsuite/ld-alpha/tlsbinr.dd
new file mode 100644
index 0000000..16d024d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlsbinr.dd
@@ -0,0 +1,62 @@
+#source: align.s
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as:
+#ld: -relax -melf64alpha
+#objdump: -drj.text
+#target: alpha*-*-*
+
+.*: +file format elf64-alpha
+
+Disassembly of section \.text:
+
+0+120001000 <fn2>:
+   120001000:	02 00 bb 27 	ldah	gp,2\(t12\)
+   120001004:	90 82 bd 23 	lda	gp,-32112\(gp\)
+   120001008:	3e 15 c2 43 	subq	sp,0x10,sp
+   12000100c:	00 00 5e b7 	stq	ra,0\(sp\)
+   120001010:	08 80 1d a6 	ldq	a0,-32760\(gp\)
+   120001014:	00 00 fe 2f 	unop	
+   120001018:	9e 00 00 00 	rduniq
+   12000101c:	00 04 00 42 	addq	a0,v0,v0
+   120001020:	00 00 fe 2f 	unop	
+   120001024:	34 00 1f 22 	lda	a0,52
+   120001028:	00 00 fe 2f 	unop	
+   12000102c:	9e 00 00 00 	rduniq
+   120001030:	00 04 00 42 	addq	a0,v0,v0
+   120001034:	00 00 fe 2f 	unop	
+   120001038:	10 00 1f 22 	lda	a0,16
+   12000103c:	00 00 fe 2f 	unop	
+   120001040:	9e 00 00 00 	rduniq
+   120001044:	00 04 00 42 	addq	a0,v0,v0
+   120001048:	00 00 fe 2f 	unop	
+   12000104c:	21 00 20 20 	lda	t0,33\(v0\)
+   120001050:	10 00 1f 22 	lda	a0,16
+   120001054:	00 00 fe 2f 	unop	
+   120001058:	9e 00 00 00 	rduniq
+   12000105c:	00 04 00 42 	addq	a0,v0,v0
+   120001060:	00 00 fe 2f 	unop	
+   120001064:	40 00 20 20 	lda	t0,64\(v0\)
+   120001068:	46 00 20 20 	lda	t0,70\(v0\)
+   12000106c:	00 00 20 24 	ldah	t0,0\(v0\)
+   120001070:	4b 00 21 20 	lda	t0,75\(t0\)
+   120001074:	56 00 3f 20 	lda	t0,86
+   120001078:	01 04 20 40 	addq	t0,v0,t0
+   12000107c:	00 00 5e a7 	ldq	ra,0\(sp\)
+   120001080:	1e 14 c2 43 	addq	sp,0x10,sp
+   120001084:	01 80 fa 6b 	ret
+
+0000000120001088 <_start>:
+   120001088:	9e 00 00 00 	rduniq
+   12000108c:	09 04 e0 47 	mov	v0,s0
+   120001090:	00 80 3d a4 	ldq	t0,-32768\(gp\)
+   120001094:	01 04 29 40 	addq	t0,s0,t0
+   120001098:	90 00 3f 20 	lda	t0,144
+   12000109c:	01 04 29 40 	addq	t0,s0,t0
+   1200010a0:	10 00 29 20 	lda	t0,16\(s0\)
+   1200010a4:	96 00 29 20 	lda	t0,150\(s0\)
+   1200010a8:	00 00 29 24 	ldah	t0,0\(s0\)
+   1200010ac:	57 00 21 20 	lda	t0,87\(t0\)
+   1200010b0:	98 00 3f 20 	lda	t0,152
+   1200010b4:	01 04 29 40 	addq	t0,s0,t0
+   1200010b8:	01 80 fa 6b 	ret
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlsbinr.rd b/binutils-2.19/ld/testsuite/ld-alpha/tlsbinr.rd
new file mode 100644
index 0000000..8751428
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlsbinr.rd
@@ -0,0 +1,128 @@
+#source: align.s
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as:
+#ld: -relax -melf64alpha
+#readelf: -WSsrl
+#target: alpha*-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+ +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] \.interp +.*
+ +\[[ 0-9]+\] \.hash +.*
+ +\[[ 0-9]+\] \.dynsym +.*
+ +\[[ 0-9]+\] \.dynstr +.*
+ +\[[ 0-9]+\] \.rela\.dyn +.*
+ +\[[ 0-9]+\] \.rela\.plt +.*
+ +\[[ 0-9]+\] \.text +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ +AX +0 +0 4096
+ +\[[ 0-9]+\] \.eh_frame +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +A +0 +0 +8
+ +\[[ 0-9]+\] \.tdata +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ WAT +0 +0 +4
+ +\[[ 0-9]+\] \.tbss +NOBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ WAT +0 +0 +1
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 10 +WA +4 +0 +8
+ +\[[ 0-9]+\] \.plt +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ WAX +0 +0 +16
+ +\[[ 0-9]+\] \.got +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ +WA +0 +0 +8
+ +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
+#...
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x[0-9a-f]+
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+ +PHDR +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R E 0x8
+ +INTERP +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x1
+.*Requesting program interpreter.*
+ +LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R E 0x10000
+ +LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RWE 0x10000
+ +DYNAMIC +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW +0x8
+ +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x4
+#...
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 2 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f]+ +0+100000026 R_ALPHA_TPREL64 +0+ sG2 \+ 0
+[0-9a-f]+ +0+400000026 R_ALPHA_TPREL64 +0+ sG1 \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+[0-9 ]+: 0+ +0 NOTYPE +LOCAL +DEFAULT +UND 
+[0-9 ]+: 0+ +0 TLS +GLOBAL DEFAULT +UND sG2
+[0-9 ]+: 0+ +0 FUNC +GLOBAL DEFAULT +UND __tls_get_addr
+[0-9 ]+: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+[0-9 ]+: 0+ +0 TLS +GLOBAL DEFAULT +UND sG1
+[0-9 ]+: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _edata
+[0-9 ]+: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+[0-9 ]+: [0-9a-f]+ +0 NOTYPE +LOCAL +DEFAULT +UND 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +1 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +2 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +3 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +4 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +5 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +6 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +7 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +8 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +9 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +10 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +11 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +12 
+[0-9 ]+: [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +13 
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl1
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl2
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl3
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl4
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl5
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl6
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl7
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +9 sl8
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl1
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl2
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl3
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl4
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl5
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl6
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl7
+[0-9 ]+: [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +10 bl8
+[0-9 ]+: [0-9a-f]+ +0 OBJECT +LOCAL +HIDDEN +11 _DYNAMIC
+[0-9 ]+: [0-9a-f]+ +0 OBJECT +LOCAL +HIDDEN +12 _PROCEDURE_LINKAGE_TABLE_
+[0-9 ]+: [0-9a-f]+ +0 OBJECT +LOCAL +HIDDEN +13 _GLOBAL_OFFSET_TABLE_
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg8
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg8
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg6
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg3
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg3
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh3
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +UND sG2
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg4
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg5
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg5
+[0-9 ]+: [0-9a-f]+ +0 FUNC +GLOBAL DEFAULT +UND __tls_get_addr
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh7
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh8
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg1
+[0-9 ]+: [0-9a-f]+ +52 FUNC +GLOBAL DEFAULT +7 _start
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh4
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg7
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh5
+[0-9 ]+: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+[0-9 ]+: [0-9a-f]+ +136 FUNC +GLOBAL DEFAULT +\[<other>: 88\] +7 fn2
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg2
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +UND sG1
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh1
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg6
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +9 sg7
+[0-9 ]+: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _edata
+[0-9 ]+: [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _end
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh2
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +9 sh6
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg2
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg1
+[0-9 ]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +10 bg4
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlsbinr.sd b/binutils-2.19/ld/testsuite/ld-alpha/tlsbinr.sd
new file mode 100644
index 0000000..59e9449
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlsbinr.sd
@@ -0,0 +1,12 @@
+#source: align.s
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as:
+#ld: -relax -melfalpha
+#objdump: -sj.got
+#target: alpha*-*-*
+
+.*: +file format elf64-alpha
+
+Contents of section .got:
+ [0-9a-f]+ 00000000 00000000 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlsg.s b/binutils-2.19/ld/testsuite/ld-alpha/tlsg.s
new file mode 100644
index 0000000..99fb84a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlsg.s
@@ -0,0 +1,14 @@
+	.section	.tbss,"awT",@nobits
+	.align 4
+	.skip	24
+	.type	a,@object
+	.size	a,4
+a:
+	.long	0
+	.text
+	.globl	_start
+	.ent	_start
+_start:
+	.end	_start
+	.section	.debug_foobar
+	.quad	a !dtprel
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlsg.sd b/binutils-2.19/ld/testsuite/ld-alpha/tlsg.sd
new file mode 100644
index 0000000..c426a99
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlsg.sd
@@ -0,0 +1,10 @@
+#source: tlsg.s
+#as:
+#ld: -melf64_ia64
+#objdump: -sj.debug_foobar
+#target: ia64-*-*
+
+.*: +file format elf64-ia64-little
+
+Contents of section .debug_foobar:
+ 0+ 18000000 0+  +.*
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlslib.s b/binutils-2.19/ld/testsuite/ld-alpha/tlslib.s
new file mode 100644
index 0000000..88cdff2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlslib.s
@@ -0,0 +1,19 @@
+	.section ".tdata", "awT", @progbits
+	.globl sG1, sG2, sG3, sG4, sG5, sG6, sG7, sG8
+sG1:	.long 513
+sG2:	.long 514
+sG3:	.long 515
+sG4:	.long 516
+sG5:	.long 517
+sG6:	.long 518
+sG7:	.long 519
+sG8:	.long 520
+
+	.text
+	/* Dummy.  */
+	.globl	__tls_get_addr
+	.ent	__tls_get_addr
+__tls_get_addr:
+	.prologue 0
+	ret
+	.end   __tls_get_addr
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlspic.dd b/binutils-2.19/ld/testsuite/ld-alpha/tlspic.dd
new file mode 100644
index 0000000..63f150c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlspic.dd
@@ -0,0 +1,56 @@
+#source: align.s
+#source: tlspic1.s
+#source: tlspic2.s
+#as:
+#ld: -shared -melf64alpha
+#objdump: -drj.text
+#target: alpha*-*-*
+
+.*: +file format elf64-alpha
+
+Disassembly of section .text:
+
+0+1000 <fn1>:
+    1000:	02 00 bb 27 	ldah	gp,2\(t12\)
+    1004:	a0 82 bd 23 	lda	gp,-32096\(gp\)
+    1008:	3e 15 c2 43 	subq	sp,0x10,sp
+    100c:	00 00 5e b7 	stq	ra,0\(sp\)
+    1010:	08 00 3e b5 	stq	s0,8\(sp\)
+    1014:	9e 00 00 00 	rduniq
+    1018:	09 04 e0 47 	mov	v0,s0
+    101c:	08 80 1d 22 	lda	a0,-32760\(gp\)
+    1020:	00 80 7d a7 	ldq	t12,-32768\(gp\)
+    1024:	00 40 5b 6b 	jsr	ra,\(t12\),1028 <.*>
+    1028:	02 00 ba 27 	ldah	gp,2\(ra\)
+    102c:	78 82 bd 23 	lda	gp,-32136\(gp\)
+    1030:	30 80 1d 22 	lda	a0,-32720\(gp\)
+    1034:	00 80 7d a7 	ldq	t12,-32768\(gp\)
+    1038:	00 40 5b 6b 	jsr	ra,\(t12\),103c <.*>
+    103c:	02 00 ba 27 	ldah	gp,2\(ra\)
+    1040:	64 82 bd 23 	lda	gp,-32156\(gp\)
+    1044:	40 80 1d 22 	lda	a0,-32704\(gp\)
+    1048:	00 80 7d a7 	ldq	t12,-32768\(gp\)
+    104c:	00 40 5b 6b 	jsr	ra,\(t12\),1050 <.*>
+    1050:	02 00 ba 27 	ldah	gp,2\(ra\)
+    1054:	50 82 bd 23 	lda	gp,-32176\(gp\)
+    1058:	21 00 20 20 	lda	t0,33\(v0\)
+    105c:	40 80 1d 22 	lda	a0,-32704\(gp\)
+    1060:	00 80 7d a7 	ldq	t12,-32768\(gp\)
+    1064:	00 40 5b 6b 	jsr	ra,\(t12\),1068 <.*>
+    1068:	02 00 ba 27 	ldah	gp,2\(ra\)
+    106c:	38 82 bd 23 	lda	gp,-32200\(gp\)
+    1070:	40 00 20 20 	lda	t0,64\(v0\)
+    1074:	62 00 20 20 	lda	t0,98\(v0\)
+    1078:	00 00 20 24 	ldah	t0,0\(v0\)
+    107c:	53 00 21 20 	lda	t0,83\(t0\)
+    1080:	18 80 3d a4 	ldq	t0,-32744\(gp\)
+    1084:	01 04 20 40 	addq	t0,v0,t0
+    1088:	20 80 3d a4 	ldq	t0,-32736\(gp\)
+    108c:	01 04 29 40 	addq	t0,s0,t0
+    1090:	50 80 3d a4 	ldq	t0,-32688\(gp\)
+    1094:	28 80 5d a4 	ldq	t1,-32728\(gp\)
+    1098:	01 04 29 40 	addq	t0,s0,t0
+    109c:	02 04 49 40 	addq	t1,s0,t1
+    10a0:	00 00 5e a7 	ldq	ra,0\(sp\)
+    10a4:	1e 14 c2 43 	addq	sp,0x10,sp
+    10a8:	01 80 fa 6b 	ret
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlspic.rd b/binutils-2.19/ld/testsuite/ld-alpha/tlspic.rd
new file mode 100644
index 0000000..b442f74
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlspic.rd
@@ -0,0 +1,128 @@
+#source: align.s
+#source: tlspic1.s
+#source: tlspic2.s
+#as:
+#ld: -shared -melf64alpha
+#readelf: -WSsrl
+#target: alpha*-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+ +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .rela.plt +.*
+ +\[[ 0-9]+\] .text +PROGBITS +0+1000 0+1000 0+ac 0+ +AX +0 +0 4096
+ +\[[ 0-9]+\] .eh_frame +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +A +0 +0 +8
+ +\[[ 0-9]+\] .tdata +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ WAT +0 +0 +4
+ +\[[ 0-9]+\] .tbss +NOBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 10 +WA +3 +0 +8
+ +\[[ 0-9]+\] .plt +.*
+ +\[[ 0-9]+\] .got +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ +WA +0 +0 +8
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+#...
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x1000
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+ +LOAD +0x0+ 0x0+ 0x0+ 0x[0-9a-f]+ 0x[0-9a-f]+ R E 0x10000
+ +LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RWE 0x10000
+ +DYNAMIC +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW +0x8
+ +TLS +0x0+10e0 0x0+110e0 0x0+110e0 0x0+60 0x0+80 R +0x4
+#...
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 7 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f]+ +[0-9a-f]+ R_ALPHA_DTPMOD64 +0+ sg1 \+ 0
+[0-9a-f]+ +[0-9a-f]+ R_ALPHA_DTPREL64 +0+ sg1 \+ 0
+[0-9a-f]+ +[0-9a-f]+ R_ALPHA_TPREL64 +0+4 sg2 \+ 0
+[0-9a-f]+ +[0-9a-f]+ R_ALPHA_TPREL64 +0+44
+[0-9a-f]+ +[0-9a-f]+ R_ALPHA_DTPMOD64 +0+
+[0-9a-f]+ +[0-9a-f]+ R_ALPHA_DTPMOD64 +0+
+[0-9a-f]+ +[0-9a-f]+ R_ALPHA_TPREL64 +0+24
+
+Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f]+ +[0-9a-f]+ R_ALPHA_JMP_SLOT +0+ __tls_get_addr \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+   Num:    Value          Size Type    Bind   Vis      Ndx Name
+.* [0-9a-f]+     0 NOTYPE  LOCAL  DEFAULT  UND 
+.* [0-9a-f]+     0 TLS     GLOBAL DEFAULT    8 sg8
+.* [0-9a-f]+     0 TLS     GLOBAL DEFAULT    8 sg3
+.* [0-9a-f]+     0 TLS     GLOBAL DEFAULT    8 sg4
+.* [0-9a-f]+     0 TLS     GLOBAL DEFAULT    8 sg5
+.* [0-9a-f]+     0 NOTYPE  GLOBAL DEFAULT  UND __tls_get_addr
+.* [0-9a-f]+     0 TLS     GLOBAL DEFAULT    8 sg1
+.* [0-9a-f]+   172 FUNC    GLOBAL DEFAULT \[<other>: 88\]     6 fn1
+.* [0-9a-f]+     0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.* [0-9a-f]+     0 TLS     GLOBAL DEFAULT    8 sg2
+.* [0-9a-f]+     0 TLS     GLOBAL DEFAULT    8 sg6
+.* [0-9a-f]+     0 TLS     GLOBAL DEFAULT    8 sg7
+.* [0-9a-f]+     0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+.* [0-9a-f]+     0 NOTYPE  GLOBAL DEFAULT  ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* [0-9a-f]+ +0 NOTYPE +LOCAL +DEFAULT +UND 
+.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +1 
+.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +2 
+.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +3 
+.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +4 
+.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +5 
+.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +6 
+.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +7 
+.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +8 
+.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +9 
+.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +10 
+.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +11 
+.* [0-9a-f]+ +0 SECTION LOCAL +DEFAULT +12 
+.* [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl1
+.* [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl2
+.* [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl3
+.* [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl4
+.* [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl5
+.* [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl6
+.* [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl7
+.* [0-9a-f]+ +0 TLS +LOCAL +DEFAULT +8 sl8
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +9 sH1
+.* [0-9a-f]+ +0 OBJECT +LOCAL +HIDDEN +ABS _DYNAMIC
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +8 sh3
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +9 sH2
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +9 sH7
+.* [0-9a-f]+ +0 OBJECT +LOCAL +HIDDEN +ABS _PROCEDURE_LINKAGE_TABLE_
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +8 sh7
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +8 sh8
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +9 sH4
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +8 sh4
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +9 sH3
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +8 sh5
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +9 sH5
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +9 sH6
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +9 sH8
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +8 sh1
+.* [0-9a-f]+ +0 OBJECT +LOCAL +HIDDEN +ABS _GLOBAL_OFFSET_TABLE_
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +8 sh2
+.* [0-9a-f]+ +0 TLS +LOCAL +HIDDEN +8 sh6
+.* [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg8
+.* [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg3
+.* [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg4
+.* [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg5
+.* [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr
+.* [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg1
+.* [0-9a-f]+ +172 FUNC +GLOBAL DEFAULT +\[<other>: 88\] +6 fn1
+.* [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg2
+.* [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg6
+.* [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg7
+.* [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* [0-9a-f]+ +0 NOTYPE +GLOBAL DEFAULT +ABS _end
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlspic.sd b/binutils-2.19/ld/testsuite/ld-alpha/tlspic.sd
new file mode 100644
index 0000000..772cbaf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlspic.sd
@@ -0,0 +1,17 @@
+#source: align.s
+#source: tlspic1.s
+#source: tlspic2.s
+#as:
+#ld: -shared -melf64alpha
+#objdump: -sj.got
+#target: alpha*-*-*
+
+.*: +file format elf64-alpha
+
+Contents of section .got:
+ 112a0 90120100 00000000 00000000 00000000  .*
+ 112b0 00000000 00000000 71000000 00000000  .*
+ 112c0 00000000 00000000 00000000 00000000  .*
+ 112d0 00000000 00000000 44000000 00000000  .*
+ 112e0 00000000 00000000 00000000 00000000  .*
+ 112f0 00000000 00000000                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlspic.td b/binutils-2.19/ld/testsuite/ld-alpha/tlspic.td
new file mode 100644
index 0000000..cd09609
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlspic.td
@@ -0,0 +1,17 @@
+#source: align.s
+#source: tlspic1.s
+#source: tlspic2.s
+#as:
+#ld: -shared -melf64alpha
+#objdump: -sj.tdata
+#target: alpha*-*-*
+
+.*: +file format elf64-alpha
+
+Contents of section .tdata:
+ 110e0 11000000 12000000 13000000 14000000  .*
+ 110f0 15000000 16000000 17000000 18000000  .*
+ 11100 41000000 42000000 43000000 44000000  .*
+ 11110 45000000 46000000 47000000 48000000  .*
+ 11120 01010000 02010000 03010000 04010000  .*
+ 11130 05010000 06010000 07010000 08010000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlspic1.s b/binutils-2.19/ld/testsuite/ld-alpha/tlspic1.s
new file mode 100644
index 0000000..822f36d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlspic1.s
@@ -0,0 +1,87 @@
+	.section ".tdata", "awT", @progbits
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+	.text
+	.globl	fn1
+	.ent	fn1
+fn1:
+	.frame	$sp, 16, $26, 0
+	ldgp	$gp, 0($27)
+	subq	$sp, 16, $sp
+	stq	$26, 0($sp)
+	stq	$9, 8($sp)
+	.prologue 1
+
+	rduniq
+	mov	$0, $9
+
+	/* GD */
+	lda	$16, sg1($gp)			!tlsgd!1
+	ldq	$27, __tls_get_addr($gp)	!literal!1
+	jsr	$26, ($27), __tls_get_addr	!lituse_tlsgd!1
+	ldgp	$gp, 0($26)
+
+	/* GD against hidden symbol */
+	lda	$16, sh2($gp)			!tlsgd!2
+	ldq	$27, __tls_get_addr($gp)	!literal!2
+	jsr	$26, ($27), __tls_get_addr	!lituse_tlsgd!2
+	ldgp	$gp, 0($26)
+
+	/* LD */
+	lda	$16, sl1($gp)			!tlsldm!3
+	ldq	$27, __tls_get_addr($gp)	!literal!3
+	jsr	$26, ($27), __tls_get_addr	!lituse_tlsldm!3
+	ldgp	$gp, 0($26)
+	lda	$1, sl1+1($0)			!dtprel
+
+	/* LD with 4 variables */
+	lda	$16, sh1($gp)			!tlsldm!4
+	ldq	$27, __tls_get_addr($gp)	!literal!4
+	jsr	$26, ($27), __tls_get_addr	!lituse_tlsldm!4
+	ldgp	$gp, 0($26)
+	lda	$1, sh1($0)			!dtprel
+	lda	$1, sH1+2($0)			!dtprel
+	ldah	$1, sh5+3($0)			!dtprelhi
+	lda	$1, sh5+3($1)			!dtprello
+	ldq	$1, sH5+1($gp)			!gotdtprel
+	addq	$1, $0, $1
+
+	/* IE against global */
+	ldq	$1, sg2($gp)			!gottprel
+	addq	$1, $9, $1
+
+	/* IE against local and hidden */
+	ldq	$1, sl2($gp)			!gottprel
+	ldq	$2, sh2($gp)			!gottprel
+	addq	$1, $9, $1
+	addq	$2, $9, $2
+
+	ldq	$26, 0($sp)
+	addq	$sp, 16, $sp
+	ret
+	.end	fn1
diff --git a/binutils-2.19/ld/testsuite/ld-alpha/tlspic2.s b/binutils-2.19/ld/testsuite/ld-alpha/tlspic2.s
new file mode 100644
index 0000000..5513f9b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-alpha/tlspic2.s
@@ -0,0 +1,11 @@
+	.section ".tbss", "awT", @nobits
+	.globl sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+	.hidden sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+sH1:	.space 4
+sH2:	.space 4
+sH3:	.space 4
+sH4:	.space 4
+sH5:	.space 4
+sH6:	.space 4
+sH7:	.space 4
+sH8:	.space 4
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-app-abs32.d b/binutils-2.19/ld/testsuite/ld-arm/arm-app-abs32.d
new file mode 100644
index 0000000..ce684d4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-app-abs32.d
@@ -0,0 +1,29 @@
+
+tmpdir/arm-app-abs32:     file format elf32-(little|big)arm
+architecture: arm, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address .*
+
+Disassembly of section .plt:
+
+.* <.plt>:
+    .*:	e52de004 	push	{lr}		; \(str lr, \[sp, #-4\]!\)
+    .*:	e59fe004 	ldr	lr, \[pc, #4\]	; .* <_start-0x10>
+    .*:	e08fe00e 	add	lr, pc, lr
+    .*:	e5bef008 	ldr	pc, \[lr, #8\]!
+    .*:	.* 	.*
+    .*:	e28fc6.* 	add	ip, pc, #.*	; .*
+    .*:	e28cca.* 	add	ip, ip, #.*	; .*
+    .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+Disassembly of section .text:
+
+.* <_start>:
+    .*:	e1a0c00d 	mov	ip, sp
+    .*:	e92dd800 	push	{fp, ip, lr, pc}
+    .*:	e59f0004 	ldr	r0, \[pc, #4\]	; .* <_start\+0x14>
+    .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+    .*:	e12fff1e 	bx	lr
+    .*:	.* 	.*
+
+.* <app_func2>:
+    .*:	e12fff1e 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-app-abs32.r b/binutils-2.19/ld/testsuite/ld-arm/arm-app-abs32.r
new file mode 100644
index 0000000..08d668c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-app-abs32.r
@@ -0,0 +1,8 @@
+
+tmpdir/arm-app-abs32:     file format elf32-(little|big)arm
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+.* R_ARM_JUMP_SLOT   lib_func1
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-app-abs32.s b/binutils-2.19/ld/testsuite/ld-arm/arm-app-abs32.s
new file mode 100644
index 0000000..a1cf526
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-app-abs32.s
@@ -0,0 +1,16 @@
+	.text
+	.globl _start
+_start:
+	mov	ip, sp
+	stmdb	sp!, {r11, ip, lr, pc}
+	ldr	a1, .Lval
+	ldmia	sp, {r11, sp, lr}
+	bx	lr
+
+.Lval:
+	.long	lib_func1
+
+	.globl app_func2
+app_func2:
+	bx	lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-app-movw.s b/binutils-2.19/ld/testsuite/ld-arm/arm-app-movw.s
new file mode 100644
index 0000000..55ced97
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-app-movw.s
@@ -0,0 +1,11 @@
+	.text
+	.globl _start
+_start:
+	movw	r0, #:lower16:data_obj
+	movt	r0, #:upper16:data_obj
+	movw	r0, #:lower16:lib_func1
+	movt	r0, #:upper16:lib_func1
+
+	.globl app_func2
+app_func2:
+	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-app.d b/binutils-2.19/ld/testsuite/ld-arm/arm-app.d
new file mode 100644
index 0000000..3ed76f0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-app.d
@@ -0,0 +1,35 @@
+
+tmpdir/arm-app:     file format elf32-(little|big)arm
+architecture: arm, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x.*
+
+Disassembly of section .plt:
+
+.* <.plt>:
+ .*:	e52de004 	push	{lr}		; \(str lr, \[sp, #-4\]!\)
+ .*:	e59fe004 	ldr	lr, \[pc, #4\]	; .* <_start-0x10>
+ .*:	e08fe00e 	add	lr, pc, lr
+ .*:	e5bef008 	ldr	pc, \[lr, #8\]!
+ .*:	.*
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+Disassembly of section .text:
+
+.* <_start>:
+ .*:	e1a0c00d 	mov	ip, sp
+ .*:	e92dd800 	push	{fp, ip, lr, pc}
+ .*:	eb000001 	bl	.* <app_func>
+ .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+ .*:	e12fff1e 	bx	lr
+
+.* <app_func>:
+ .*:	e1a0c00d 	mov	ip, sp
+ .*:	e92dd800 	push	{fp, ip, lr, pc}
+ .*:	ebfffff4 	bl	.* <_start-0xc>
+ .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+ .*:	e12fff1e 	bx	lr
+
+.* <app_func2>:
+ .*:	e12fff1e 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-app.r b/binutils-2.19/ld/testsuite/ld-arm/arm-app.r
new file mode 100644
index 0000000..4b25e70
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-app.r
@@ -0,0 +1,9 @@
+
+tmpdir/arm-app.*:     file format elf32-(little|big)arm
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+.* R_ARM_COPY        data_obj
+.* R_ARM_JUMP_SLOT   lib_func1
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-app.s b/binutils-2.19/ld/testsuite/ld-arm/arm-app.s
new file mode 100644
index 0000000..8f6d27c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-app.s
@@ -0,0 +1,23 @@
+	.text
+	.globl _start
+_start:
+	mov	ip, sp
+	stmdb	sp!, {r11, ip, lr, pc}
+	bl	app_func
+	ldmia	sp, {r11, sp, lr}
+	bx lr
+
+	.globl app_func
+app_func:
+	mov	ip, sp
+	stmdb	sp!, {r11, ip, lr, pc}
+	bl	lib_func1
+	ldmia	sp, {r11, sp, lr}
+	bx lr
+
+	.globl app_func2
+app_func2:
+	bx	lr
+
+	.data
+	.long data_obj
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-be8.d b/binutils-2.19/ld/testsuite/ld-arm/arm-be8.d
new file mode 100644
index 0000000..68a4ea3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-be8.d
@@ -0,0 +1,16 @@
+
+.*:     file format.*
+
+Disassembly of section .text:
+
+00008000 <arm>:
+    8000:	0000a0e3 	mov	r0, #0	; 0x0
+    8004:	1eff2fe1 	bx	lr
+
+00008008 <thumb>:
+    8008:	c046      	nop			\(mov r8, r8\)
+    800a:	7047      	bx	lr
+    800c:	fff7 fcff 	bl	8008 <thumb>
+
+00008010 <data>:
+    8010:	12345678 	.word	0x12345678
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-be8.s b/binutils-2.19/ld/testsuite/ld-arm/arm-be8.s
new file mode 100644
index 0000000..871b691
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-be8.s
@@ -0,0 +1,14 @@
+.arch armv6
+.text
+arm:
+mov r0, #0
+$m:
+bx lr
+.thumb
+.thumb_func
+thumb:
+nop
+bx lr
+bl thumb
+data:
+.word 0x12345678
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-call.d b/binutils-2.19/ld/testsuite/ld-arm/arm-call.d
new file mode 100644
index 0000000..f4a9d78
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-call.d
@@ -0,0 +1,58 @@
+
+.*:     file format.*
+
+Disassembly of section .text:
+
+00008000 <_start>:
+    8000:	eb00000d 	bl	803c <arm>
+    8004:	fa00000d 	blx	8040 <t1>
+    8008:	fb00000c 	blx	8042 <t2>
+    800c:	fb00000d 	blx	804a <t5>
+    8010:	fa00000a 	blx	8040 <t1>
+    8014:	fb000009 	blx	8042 <t2>
+    8018:	ea000012 	b	8068 <__t1_from_arm>
+    801c:	ea00000f 	b	8060 <__t2_from_arm>
+    8020:	1b000010 	blne	8068 <__t1_from_arm>
+    8024:	1b00000d 	blne	8060 <__t2_from_arm>
+    8028:	1b000003 	blne	803c <arm>
+    802c:	eb000002 	bl	803c <arm>
+    8030:	faffffff 	blx	8034 <thumblocal>
+
+00008034 <thumblocal>:
+    8034:	4770      	bx	lr
+
+00008036 <t3>:
+    8036:	4770      	bx	lr
+
+00008038 <t4>:
+    8038:	4770      	bx	lr
+    803a:	46c0      	nop			\(mov r8, r8\)
+
+0000803c <arm>:
+    803c:	e12fff1e 	bx	lr
+
+00008040 <t1>:
+    8040:	4770      	bx	lr
+
+00008042 <t2>:
+    8042:	f7ff fff8 	bl	8036 <t3>
+    8046:	f7ff fff7 	bl	8038 <t4>
+
+0000804a <t5>:
+    804a:	f000 f801 	bl	8050 <local_thumb>
+    804e:	46c0      	nop			\(mov r8, r8\)
+
+00008050 <local_thumb>:
+    8050:	f7ff fff1 	bl	8036 <t3>
+    8054:	f7ff efd4 	blx	8000 <_start>
+    8058:	f7ff efd2 	blx	8000 <_start>
+    805c:	0000      	lsls	r0, r0, #0
+	...
+
+00008060 <__t2_from_arm>:
+    8060:	e51ff004 	ldr	pc, \[pc, #-4\]	; 8064 <__t2_from_arm\+0x4>
+    8064:	00008043 	.word	0x00008043
+
+00008068 <__t1_from_arm>:
+    8068:	e51ff004 	ldr	pc, \[pc, #-4\]	; 806c <__t1_from_arm\+0x4>
+    806c:	00008041 	.word	0x00008041
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-call1.s b/binutils-2.19/ld/testsuite/ld-arm/arm-call1.s
new file mode 100644
index 0000000..e6ea1f2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-call1.s
@@ -0,0 +1,30 @@
+# Test R_ARM_CALL and R_ARM_JUMP24 relocations and interworking
+	.text
+	.arch armv5t
+	.global _start
+_start:
+	bl arm
+	bl t1
+	bl t2
+	bl t5
+	blx t1
+	blx t2
+	b t1
+	b t2
+	blne t1
+	blne t2
+	blne arm
+	blx arm
+	blx thumblocal
+	.thumb
+thumblocal:
+	bx lr
+	.global t3
+	.thumb_func
+t3:
+	bx lr
+	.global t4
+	.thumb_func
+t4:
+	bx lr
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-call2.s b/binutils-2.19/ld/testsuite/ld-arm/arm-call2.s
new file mode 100644
index 0000000..30ae349
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-call2.s
@@ -0,0 +1,24 @@
+	.text
+	.arch armv5t
+	.global arm
+	.global t1
+	.global t2
+	.global t5
+arm:
+	bx lr
+	.thumb
+	.thumb_func
+t1:
+	bx lr
+	.thumb_func
+t2:
+	bl t3
+	bl t4
+	.thumb_func
+t5:
+	bl local_thumb
+	nop
+local_thumb:
+	blx t3
+	bl _start
+	blx _start
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-dyn.ld b/binutils-2.19/ld/testsuite/ld-arm/arm-dyn.ld
new file mode 100644
index 0000000..4f2e0de
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-dyn.ld
@@ -0,0 +1,194 @@
+/* Script for -z combreloc: combine and sort reloc sections */
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x8000); . = 0x8000;
+  .interp         : { *(.interp) }
+  .hash           : { *(.hash) }
+  .dynsym         : { *(.dynsym) }
+  .dynstr         : { *(.dynstr) }
+  .gnu.version    : { *(.gnu.version) }
+  .gnu.version_d  : { *(.gnu.version_d) }
+  .gnu.version_r  : { *(.gnu.version_r) }
+  .rel.dyn        :
+    {
+      *(.rel.init)
+      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
+      *(.rel.fini)
+      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
+      *(.rel.data.rel.ro*)
+      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
+      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
+      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
+      *(.rel.ctors)
+      *(.rel.dtors)
+      *(.rel.got)
+      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
+    }
+  .rela.dyn       :
+    {
+      *(.rela.init)
+      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+      *(.rela.fini)
+      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+      *(.rela.ctors)
+      *(.rela.dtors)
+      *(.rela.got)
+      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+    }
+  .rel.plt        : { *(.rel.plt) }
+  .rela.plt       : { *(.rela.plt) }
+  .init           :
+  {
+    KEEP (*(.init))
+  } =0
+  .plt            : { *(.plt) }
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7)
+  } =0
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } =0
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
+  .rodata1        : { *(.rodata1) }
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
+   __exidx_start = .;
+  .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
+   __exidx_end = .;
+  .eh_frame_hdr : { *(.eh_frame_hdr) }
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN (0x8000) - ((0x8000 - .) & (0x8000 - 1)); . = DATA_SEGMENT_ALIGN (0x8000, 0x1000);
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  . = ALIGN(32 / 8);
+  PROVIDE (__preinit_array_start = .);
+  .preinit_array     : { KEEP (*(.preinit_array)) }
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) }
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) }
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  }
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  }
+  .jcr            : { KEEP (*(.jcr)) }
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }
+  .dynamic        : { *(.dynamic) }
+  .got            : { *(.got.plt) *(.got) }
+  .data           :
+  {
+    __data_start = . ;
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  }
+  .data1          : { *(.data1) }
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  __bss_start__ = .;
+  .bss            :
+  {
+   *(.dynbss)
+   *(.bss .bss.* .gnu.linkonce.b.*)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   . = ALIGN(32 / 8);
+  }
+  . = ALIGN(32 / 8);
+  _end = .;
+  _bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
+  PROVIDE (end = .);
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-elf.exp b/binutils-2.19/ld/testsuite/ld-arm/arm-elf.exp
new file mode 100644
index 0000000..6aa4a97
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-elf.exp
@@ -0,0 +1,408 @@
+# Expect script for various ARM ELF tests.
+#   Copyright 2002, 2003, 2004, 2007, 2008 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+if {[istarget "arm-*-vxworks"]} {
+    set armvxworkstests {
+	{"VxWorks shared library test 1" "-shared -Tvxworks1.ld"
+	 "" {vxworks1-lib.s}
+	 {{readelf --relocs vxworks1-lib.rd} {objdump -dr vxworks1-lib.dd}
+	  {readelf --symbols vxworks1-lib.nd} {readelf -d vxworks1-lib.td}}
+	 "libvxworks1.so"}
+	{"VxWorks executable test 1 (dynamic)" \
+	 "tmpdir/libvxworks1.so -Tvxworks1.ld -q --force-dynamic"
+	 "" {vxworks1.s}
+	 {{readelf --relocs vxworks1.rd} {objdump -dr vxworks1.dd}}
+	 "vxworks1"}
+	{"VxWorks executable test 2 (dynamic)" \
+	 "-Tvxworks1.ld -q --force-dynamic"
+	 "" {vxworks2.s}
+	 {{readelf --segments vxworks2.sd}}
+	 "vxworks2"}
+	{"VxWorks executable test 2 (static)"
+	 "-Tvxworks1.ld"
+	 "" {vxworks2.s}
+	 {{readelf --segments vxworks2-static.sd}}
+	 "vxworks2"}
+    }
+    run_ld_link_tests $armvxworkstests
+    run_dump_test "vxworks1-static"
+    run_dump_test "emit-relocs1-vxworks"
+}
+
+if { [istarget "arm*-*-symbianelf*"] } {
+    run_dump_test "symbian-seg1"
+}
+
+# Exclude non-ARM-ELF targets.
+
+if { ![is_elf_format] || ![istarget "arm*-*-*"] } {
+    return
+}
+
+# List contains test-items with 3 items followed by 2 lists:
+# 0:name 1:ld options 2:assembler options
+# 3:filenames of assembler files 4: action and options. 5: name of output file
+
+# Actions:
+# objdump: Apply objdump options on result.  Compare with regex (last arg).
+# nm: Apply nm options on result.  Compare with regex (last arg).
+# readelf: Apply readelf options on result.  Compare with regex (last arg).
+
+set armelftests {
+    {"Group relocations" "-Ttext 0x8000 --section-start zero=0x0 --section-start alpha=0xeef0 --section-start beta=0xffeef0" "" {group-relocs.s}
+     {{objdump -Dr group-relocs.d}}
+     "group-relocs"}
+    {"Thumb-1 BL" "-Ttext 0x1000 --section-start .foo=0x401000" "" {thumb1-bl.s}
+     {{objdump -dr thumb1-bl.d}}
+     "thumb1-bl"}
+    {"Simple non-PIC shared library" "-shared" "" {arm-lib.s}
+     {{objdump -fdw arm-lib.d} {objdump -Rw arm-lib.r}}
+     "arm-lib.so"}
+    {"Simple PIC shared library" "-shared" "" {arm-lib-plt32.s}
+     {{objdump -fdw arm-lib-plt32.d} {objdump -Rw arm-lib-plt32.r}}
+     "arm-lib-plt32.so"}
+    {"Simple dynamic application" "tmpdir/arm-lib.so" "" {arm-app.s}
+     {{objdump -fdw arm-app.d} {objdump -Rw arm-app.r}}
+     "arm-app"}
+    {"Simple static application" "" "" {arm-static-app.s}
+     {{objdump -fdw arm-static-app.d} {objdump -rw arm-static-app.r}}
+     "arm-static-app"}
+    {"Non-pcrel function reference" "tmpdir/arm-lib.so" "" {arm-app-abs32.s}
+     {{objdump -fdw arm-app-abs32.d} {objdump -Rw arm-app-abs32.r}}
+     "arm-app-abs32"}
+    {"Thumb shared library with ARM entry points" "-shared -T arm-lib.ld" "-mthumb-interwork"
+     {mixed-lib.s}
+     {{objdump -fdw armthumb-lib.d} {readelf -Ds armthumb-lib.sym}}
+     "armthumb-lib.so"}
+    {"Mixed ARM/Thumb shared library" "-shared -T arm-lib.ld -use-blx" ""
+     {mixed-lib.s}
+     {{objdump -fdw mixed-lib.d} {objdump -Rw mixed-lib.r}
+      {readelf -Ds mixed-lib.sym}}
+     "mixed-lib.so"}
+    {"Mixed ARM/Thumb dynamic application" "tmpdir/mixed-lib.so -T arm-dyn.ld" ""
+     {mixed-app.s}
+     {{objdump -fdw mixed-app.d} {objdump -Rw mixed-app.r}
+      {readelf -Ds mixed-app.sym}}
+     "mixed-app"}
+    {"Mixed ARM/Thumb arch5 dynamic application" "tmpdir/mixed-lib.so -T arm-dyn.ld --use-blx" ""
+     {mixed-app.s}
+     {{objdump -fdw mixed-app-v5.d} {objdump -Rw mixed-app.r}
+      {readelf -Ds mixed-app.sym}}
+     "mixed-app-v5"}
+    {"target1-abs" "-static --target1-abs -T arm.ld" "" {arm-target1.s}
+     {{objdump -s arm-target1-abs.d}}
+     "arm-target1-abs"}
+    {"target1-rel" "-static --target1-rel -T arm.ld" "" {arm-target1.s}
+     {{objdump -s arm-target1-rel.d}}
+     "arm-target1-rel"}
+    {"target2-rel" "-static --target2=rel -T arm.ld" "" {arm-target2.s}
+     {{objdump -s arm-target2-rel.d}}
+     "arm-target2-rel"}
+    {"target2-abs" "-static --target2=abs -T arm.ld" "" {arm-target2.s}
+     {{objdump -s arm-target2-abs.d}}
+     "arm-target2-abs"}
+    {"target2-got-rel" "-static --target2=got-rel -T arm.ld" "" {arm-target2.s}
+     {{objdump -s arm-target2-got-rel.d}}
+     "arm-target2-got-rel"}
+    {"arm-rel31" "-static -T arm.ld" "" {arm-rel31.s}
+     {{objdump -s arm-rel31.d}}
+     "arm-rel31"}
+    {"arm-call" "-static -T arm.ld" "-meabi=4" {arm-call1.s arm-call2.s}
+     {{objdump -d arm-call.d}}
+     "arm-call"}
+    {"TLS shared library" "-shared -T arm-lib.ld" "" {tls-lib.s}
+     {{objdump -fdw tls-lib.d} {objdump -Rw tls-lib.r}}
+     "tls-lib.so"}
+    {"TLS dynamic application" "-T arm-dyn.ld tmpdir/tls-lib.so" "" {tls-app.s}
+     {{objdump -fdw tls-app.d} {objdump -Rw tls-app.r}}
+     "tls-app"}
+    {"Thumb entry point" "-T arm.ld" "" {thumb-entry.s}
+     {{readelf -h thumb-entry.d}}
+     "thumb-entry"}
+    {"thumb-rel32" "-static -T arm.ld" "" {thumb-rel32.s}
+     {{objdump -s thumb-rel32.d}}
+     "thumb-rel32"}
+    {"MOVW/MOVT" "-static -T arm.ld" "" {arm-movwt.s}
+     {{objdump -dw arm-movwt.d}}
+     "arm-movwt"}
+    {"BE8 Mapping Symbols" "-static -T arm.ld -EB --be8" "-EB" {arm-be8.s}
+     {{objdump -d arm-be8.d}}
+     "arm-be8"}
+    {"Using Thumb lib by another lib" "-shared tmpdir/mixed-lib.so" "" {use-thumb-lib.s}
+     {{readelf -Ds use-thumb-lib.sym}}
+     "use-thumb-lib.so"}
+    {"VFP11 denorm erratum fix, scalar operation"
+     "-EL --vfp11-denorm-fix=scalar -Ttext=0x8000" "-EL -mfpu=vfpxd" {vfp11-fix-scalar.s}
+     {{objdump -dr vfp11-fix-scalar.d}}
+     "vfp11-fix-scalar"}
+    {"VFP11 denorm erratum fix, vector operation"
+     "-EB --vfp11-denorm-fix=vector -Ttext=0x8000" "-EB -mfpu=vfpxd" {vfp11-fix-vector.s}
+     {{objdump -dr vfp11-fix-vector.d}}
+     "vfp11-fix-vector"}
+    {"VFP11 denorm erratum fix, embedded code-like data"
+     "-EL --vfp11-denorm-fix=scalar -Ttext=0x8000" "-EL -mfpu=vfpxd" {vfp11-fix-none.s}
+     {{objdump -dr vfp11-fix-none.d}}
+     "vfp11-fix-none"}
+    {"Cortex-A8 erratum fix, b.w"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-b.s}
+     {{objdump -dr cortex-a8-fix-b.d}}
+     "cortex-a8-fix-b"}
+    {"Cortex-A8 erratum fix, bl.w"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-bl.s}
+     {{objdump -dr cortex-a8-fix-bl.d}}
+     "cortex-a8-fix-bl"}
+    {"Cortex-A8 erratum fix, bcc.w"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-bcc.s}
+     {{objdump -dr cortex-a8-fix-bcc.d}}
+     "cortex-a8-fix-bcc"}
+    {"Cortex-A8 erratum fix, blx.w"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-blx.s}
+     {{objdump -dr cortex-a8-fix-blx.d}}
+     "cortex-a8-fix-blx"}
+    {"Cortex-A8 erratum fix, relocate b.w to ARM"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-arm-target.s cortex-a8-fix-b-rel.s}
+     {{objdump -dr cortex-a8-fix-b-rel-arm.d}}
+     "cortex-a8-fix-b-rel-arm"}
+    {"Cortex-A8 erratum fix, relocate b.w to Thumb"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-b-rel.s}
+     {{objdump -dr cortex-a8-fix-b-rel-thumb.d}}
+     "cortex-a8-fix-b-rel-thumb"}
+    {"Cortex-A8 erratum fix, relocate bl.w to ARM"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-arm-target.s cortex-a8-fix-bl-rel.s}
+     {{objdump -dr cortex-a8-fix-bl-rel-arm.d}}
+     "cortex-a8-fix-bl-rel-arm"}
+    {"Cortex-A8 erratum fix, relocate bl.w to Thumb"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-bl-rel.s}
+     {{objdump -dr cortex-a8-fix-bl-rel-thumb.d}}
+     "cortex-a8-fix-bl-rel-thumb"}
+    {"Cortex-A8 erratum fix, relocate b<cond>.w to Thumb"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-bcc-rel.s}
+     {{objdump -dr cortex-a8-fix-bcc-rel-thumb.d}}
+     "cortex-a8-fix-bcc-rel-thumb"}
+    {"Cortex-A8 erratum fix, relocate blx.w to ARM"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-arm-target.s cortex-a8-fix-blx-rel.s}
+     {{objdump -dr cortex-a8-fix-blx-rel-arm.d}}
+     "cortex-a8-fix-blx-rel-arm"}
+    {"Cortex-A8 erratum fix, relocate blx.w to Thumb"
+     "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-blx-rel.s}
+     {{objdump -dr cortex-a8-fix-blx-rel-thumb.d}}
+     "cortex-a8-fix-blx-rel-thumb"}
+    {"Cortex-A8 erratum fix, relocate bl.w and far call"
+     "-EL -Ttext=0x00 --fix-cortex-a8 --defsym far_fn1=0x80000000 --defsym far_fn2=0x80000004  --defsym far_fn=0x7fff0000 --defsym _start=0" "-EL" {cortex-a8-far-1.s cortex-a8-far-2.s}
+     {{objdump -dr cortex-a8-far.d}}
+     "cortex-a8-far"}
+    {"Unwinding and -gc-sections" "-gc-sections" "" {gc-unwind.s}
+     {{objdump -sj.data gc-unwind.d}}
+     "gc-unwind"}
+    {"arm-pic-veneer" "-static -T arm.ld --pic-veneer" "" {arm-pic-veneer.s}
+     {{objdump -d arm-pic-veneer.d}}
+     "arm-pic-veneer"}
+    {"Preempt Thumb symbol" "tmpdir/mixed-lib.so -T arm-dyn.ld --use-blx" ""
+     {preempt-app.s}
+     {{readelf -Ds preempt-app.sym}}
+     "preempt-app"}
+    {"jump19" "-static -T arm.ld" "" {jump19.s}
+     {{objdump -dr jump19.d}}
+     "jump19"}
+    {"callweak" "-static -T arm.ld" "" {callweak.s}
+     {{objdump -dr callweak.d}}
+     "callweak"}
+}
+
+run_ld_link_tests $armelftests
+run_dump_test "group-relocs-alu-bad"
+run_dump_test "group-relocs-ldr-bad"
+run_dump_test "group-relocs-ldrs-bad"
+run_dump_test "group-relocs-ldc-bad"
+run_dump_test "thumb2-bl-undefweak"
+run_dump_test "thumb2-bl-undefweak1"
+run_dump_test "emit-relocs1"
+
+# Exclude non-ARM-EABI targets.
+
+if { ![istarget "arm*-*-*eabi"] } {
+    # Special variants of these tests, as a different farcall stub is
+    # generated for a non-ARM-EABI target: indeed in such a case,
+    # there are no attributes to indicate that blx can be used.
+
+    set arm_noeabi_tests {
+	{"Thumb-2-as-Thumb-1 BL" "-Ttext 0x1000 --section-start .foo=0x100100c" "" {thumb2-bl-as-thumb1-bad.s}
+	    {{objdump -d thumb2-bl-as-thumb1-bad-noeabi.d}}
+	    "thumb2-bl-as-thumb1-bad"}
+	{"Thumb-2 BL bad" "-Ttext 0x1000 --section-start .foo=0x100100c" "" {thumb2-bl-bad.s}
+	    {{objdump -d thumb2-bl-bad-noeabi.d}}
+	    "thumb2-bl-bad"}
+    }
+    run_ld_link_tests $arm_noeabi_tests
+
+    return
+}
+
+# Farcalls stubs are fully supported for ARM-EABI only
+set armeabitests {
+     {"EABI attribute merging" "-r" "" {attr-merge.s attr-merge.s}
+      {{readelf -A attr-merge.attr}}
+      "attr-merge"}
+     {"EABI attribute merging 2" "-r" "" {attr-merge-2a.s attr-merge-2b.s}
+      {{readelf -A attr-merge-2.attr}}
+      "attr-merge-2"}
+     {"Thumb-2 BL" "-Ttext 0x1000 --section-start .foo=0x1001000" "" {thumb2-bl.s}
+      {{objdump -dr thumb2-bl.d}}
+      "thumb2-bl"}
+
+    {"ARMv4 interworking" "-static -T arm.ld --fix-v4bx-interworking" "--fix-v4bx -meabi=4" {armv4-bx.s}
+     {{objdump -d armv4-bx.d}}
+     "armv4-bx"}
+    {"MOVW/MOVT and merged sections" "-T arm.ld" "" {movw-merge.s}
+     {{objdump -dw movw-merge.d}}
+     "movw-merge"}
+    {"MOVW/MOVT against shared libraries" "tmpdir/arm-lib.so" "" {arm-app-movw.s}
+     {{objdump -Rw arm-app.r}}
+     "arm-app-movw"}
+    {"Thumb-2-as-Thumb-1 BL" "-Ttext 0x1000 --section-start .foo=0x100100c" "" {thumb2-bl-as-thumb1-bad.s}
+     {{objdump -d thumb2-bl-as-thumb1-bad.d}}
+     "thumb2-bl-as-thumb1-bad"}
+    {"Thumb-2 BL" "-Ttext 0x1000 --section-start .foo=0x100100c" "" {thumb2-bl-bad.s}
+     {{objdump -d thumb2-bl-bad.d}}
+     "thumb2-bl-bad"}
+
+    {"ARM-ARM farcall" "-Ttext 0x1000 --section-start .foo=0x2001020" "" {farcall-arm-arm.s}
+     {{objdump -d farcall-arm-arm.d}}
+     "farcall-arm-arm"}
+    {"ARM-ARM farcall (PIC veneer)" "-Ttext 0x1000 --section-start .foo=0x2001020 --pic-veneer" "" {farcall-arm-arm.s}
+     {{objdump -d farcall-arm-arm-pic-veneer.d}}
+     "farcall-arm-arm-pic-veneer"}
+    {"ARM-ARM farcall (BE8)" "-Ttext 0x1000 --section-start .foo=0x2001020 -EB --be8" "-EB" {farcall-arm-arm.s}
+     {{objdump -d farcall-arm-arm-be8.d}}
+     "farcall-arm-arm-be8"}
+    {"ARM-ARM farcall (BE)" "-Ttext 0x1000 --section-start .foo=0x2001020 -EB" "-EB" {farcall-arm-arm.s}
+     {{objdump -d farcall-arm-arm.d}}
+     "farcall-arm-arm-be"}
+
+    {"ARM-Thumb farcall" "-Ttext 0x1000 --section-start .foo=0x2001014" "" {farcall-arm-thumb.s}
+     {{objdump -d farcall-arm-thumb.d}}
+     "farcall-arm-thumb"}
+    {"ARM-Thumb farcall with BLX" "-Ttext 0x1000 --section-start .foo=0x2001014" "-march=armv5t" {farcall-arm-thumb.s}
+     {{objdump -d farcall-arm-thumb-blx.d}}
+     "farcall-arm-thumb-blx"}
+    {"ARM-Thumb farcall (PIC veneer)" "-Ttext 0x1000 --section-start .foo=0x2001014 --pic-veneer" "" {farcall-arm-thumb.s}
+     {{objdump -d farcall-arm-thumb-pic-veneer.d}}
+     "farcall-arm-thumb-pic-veneer"}
+    {"ARM-Thumb farcall with BLX (PIC veneer)" "-Ttext 0x1000 --section-start .foo=0x2001014 --pic-veneer" "-march=armv5t" {farcall-arm-thumb.s}
+     {{objdump -d farcall-arm-thumb-blx-pic-veneer.d}}
+     "farcall-arm-thumb-blx-pic-veneer"}
+
+    {"Thumb-Thumb farcall with BLX" "-Ttext 0x1000 --section-start .foo=0x2001014" "-march=armv5t" {farcall-thumb-thumb.s}
+     {{objdump -d farcall-thumb-thumb-blx.d}}
+     "farcall-thumb-thumb-blx"}
+    {"Thumb-Thumb farcall M profile" "-Ttext 0x1000 --section-start .foo=0x2001014" "-march=armv7m" {farcall-thumb-thumb.s}
+     {{objdump -d farcall-thumb-thumb-m.d}}
+     "farcall-thumb-thumb-m"}
+    {"Thumb-Thumb farcall" "-Ttext 0x1000 --section-start .foo=0x2001014" "-march=armv4t" {farcall-thumb-thumb.s}
+     {{objdump -d farcall-thumb-thumb.d}}
+     "farcall-thumb-thumb"}
+    {"Thumb-Thumb farcall with BLX (PIC veneer)" "-Ttext 0x1000 --section-start .foo=0x2001014 --pic-veneer" "-march=armv5t" {farcall-thumb-thumb.s}
+     {{objdump -d farcall-thumb-thumb-blx-pic-veneer.d}}
+     "farcall-thumb-thumb-blx-pic-veneer"}
+    {"Thumb-Thumb farcall M profile (PIC veneer)" "-Ttext 0x1000 --section-start .foo=0x2001014 --pic-veneer" "-march=armv7m" {farcall-thumb-thumb.s}
+     {{objdump -d farcall-thumb-thumb-m-pic-veneer.d}}
+     "farcall-thumb-thumb-m-pic-veneer"}
+    {"Thumb-Thumb farcall (PIC veneer)" "-Ttext 0x1000 --section-start .foo=0x2001014 --pic-veneer" "-march=armv4t" {farcall-thumb-thumb.s}
+     {{objdump -d farcall-thumb-thumb-pic-veneer.d}}
+     "farcall-thumb-thumb-pic-veneer"}
+
+    {"Thumb-ARM farcall" "-Ttext 0x1000 --section-start .foo=0x2001014" "-W" {farcall-thumb-arm.s}
+     {{objdump -d farcall-thumb-arm.d}}
+     "farcall-thumb-arm"}
+    {"Thumb-ARM farcall (BE8)" "-Ttext 0x1000 --section-start .foo=0x2001014 -EB --be8" "-W -EB" {farcall-thumb-arm.s}
+     {{objdump -d farcall-thumb-arm-be8.d}}
+     "farcall-thumb-arm-be8"}
+    {"Thumb-ARM farcall (BE)" "-Ttext 0x1000 --section-start .foo=0x2001014 -EB" "-W -EB" {farcall-thumb-arm.s}
+     {{objdump -d farcall-thumb-arm.d}}
+     "farcall-thumb-arm-be"}
+    {"Thumb-ARM (short) call" "-Ttext 0x1000 --section-start .foo=0x0002014" "-W" {farcall-thumb-arm-short.s}
+     {{objdump -d farcall-thumb-arm-short.d}}
+     "farcall-thumb-arm-short"}
+    {"Thumb-ARM farcall with BLX" "-Ttext 0x1000 --section-start .foo=0x2001014" "-W -march=armv5t" {farcall-thumb-arm.s}
+     {{objdump -d farcall-thumb-arm-blx.d}}
+     "farcall-thumb-arm-blx"}
+    {"Thumb-ARM farcall with BLX (PIC veneer)" "-Ttext 0x1000 --section-start .foo=0x2001014 --pic-veneer" "-W -march=armv5t" {farcall-thumb-arm.s}
+     {{objdump -d farcall-thumb-arm-blx-pic-veneer.d}}
+     "farcall-thumb-arm-blx-pic-veneer"}
+    {"Thumb-ARM farcall (PIC veneer)" "-Ttext 0x1000 --section-start .foo=0x2001014 --pic-veneer" "-W" {farcall-thumb-arm.s}
+     {{objdump -d farcall-thumb-arm-pic-veneer.d}}
+     "farcall-thumb-arm-pic-veneer"}
+
+    {"Multiple farcalls" "-Ttext 0x1000 --section-start .foo=0x2002020" "" {farcall-mix.s}
+     {{objdump -d farcall-mix.d}}
+     "farcall-mix"}
+    {"Multiple farcalls from several sections" "-Ttext 0x1000 --section-start .mytext=0x2000 --section-start .foo=0x2003020" "" {farcall-mix2.s}
+     {{objdump -d farcall-mix2.d}}
+     "farcall-mix2"}
+
+    {"Default group size" "-Ttext 0x1000 --section-start .foo=0x2003020" "" {farcall-group.s farcall-group2.s}
+     {{objdump -d farcall-group.d}}
+     "farcall-group-default"}
+    {"Group size=2" "-Ttext 0x1000 --section-start .foo=0x2003020 --stub-group-size=2" "" {farcall-group.s farcall-group2.s}
+     {{objdump -d farcall-group-size2.d}}
+     "farcall-group-size2"}
+    {"Group size limit" "-Ttext 0x1000 --section-start .far=0x2003020" "" {farcall-group3.s farcall-group4.s}
+     {{objdump -d farcall-group-limit.d}}
+     "farcall-group-limit"}
+
+    {"Mixed ARM/Thumb dynamic application with farcalls" "tmpdir/mixed-lib.so -T arm-dyn.ld --section-start .far_arm=0x2100000 --section-start .far_thumb=0x2200000" ""
+     {farcall-mixed-app.s}
+     {{objdump -fdw farcall-mixed-app.d} {objdump -Rw farcall-mixed-app.r}
+      {readelf -Ds farcall-mixed-app.sym}}
+     "farcall-mixed-app"}
+    {"Mixed ARM/Thumb arch5 dynamic application with farcalls" "tmpdir/mixed-lib.so -T arm-dyn.ld --use-blx --section-start .far_arm=0x2100000 --section-start .far_thumb=0x2200000" ""
+     {farcall-mixed-app.s}
+     {{objdump -fdw farcall-mixed-app-v5.d} {objdump -Rw farcall-mixed-app.r}
+      {readelf -Ds farcall-mixed-app.sym}}
+     "farcall-mixed-app-v5"}
+
+    {"Mixed ARM/Thumb shared library with long branches" "-shared -T arm-lib.ld" ""
+     {farcall-mixed-lib1.s farcall-mixed-lib2.s}
+     {{objdump -fdw farcall-mixed-lib.d}}
+     "farcall-mixed-lib.so"}
+
+}
+
+run_ld_link_tests $armeabitests
+run_dump_test "attr-merge-wchar-00"
+run_dump_test "attr-merge-wchar-02"
+run_dump_test "attr-merge-wchar-04"
+run_dump_test "attr-merge-wchar-20"
+run_dump_test "attr-merge-wchar-22"
+run_dump_test "attr-merge-wchar-24"
+run_dump_test "attr-merge-wchar-40"
+run_dump_test "attr-merge-wchar-42"
+run_dump_test "attr-merge-wchar-44"
+run_dump_test "attr-merge-wchar-00-nowarn"
+run_dump_test "attr-merge-wchar-02-nowarn"
+run_dump_test "attr-merge-wchar-04-nowarn"
+run_dump_test "attr-merge-wchar-20-nowarn"
+run_dump_test "attr-merge-wchar-22-nowarn"
+run_dump_test "attr-merge-wchar-24-nowarn"
+run_dump_test "attr-merge-wchar-40-nowarn"
+run_dump_test "attr-merge-wchar-42-nowarn"
+run_dump_test "attr-merge-wchar-44-nowarn"
+run_dump_test "farcall-section"
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-lib-plt32.d b/binutils-2.19/ld/testsuite/ld-arm/arm-lib-plt32.d
new file mode 100644
index 0000000..d1b7944
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-lib-plt32.d
@@ -0,0 +1,28 @@
+
+tmpdir/arm-lib-plt32.so:     file format elf32-(little|big)arm
+architecture: arm, flags 0x00000150:
+HAS_SYMS, DYNAMIC, D_PAGED
+start address 0x.*
+
+Disassembly of section .plt:
+
+.* <.plt>:
+ .*:	e52de004 	push	{lr}		; \(str lr, \[sp, #-4\]!\)
+ .*:	e59fe004 	ldr	lr, \[pc, #4\]	; .* <lib_func1-0x10>
+ .*:	e08fe00e 	add	lr, pc, lr
+ .*:	e5bef008 	ldr	pc, \[lr, #8\]!
+ .*:	.*
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+Disassembly of section .text:
+
+.* <lib_func1>:
+ .*:	e1a0c00d 	mov	ip, sp
+ .*:	e92dd800 	push	{fp, ip, lr, pc}
+ .*:	ebfffff9 	bl	.* <lib_func1-0xc>
+ .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+ .*:	e12fff1e 	bx	lr
+
+.* <lib_func2>:
+ .*:	e12fff1e 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-lib-plt32.r b/binutils-2.19/ld/testsuite/ld-arm/arm-lib-plt32.r
new file mode 100644
index 0000000..3515539
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-lib-plt32.r
@@ -0,0 +1,8 @@
+
+tmpdir/arm-lib-plt32.so:     file format elf32-(little|big)arm
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+.* R_ARM_JUMP_SLOT   app_func2
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-lib-plt32.s b/binutils-2.19/ld/testsuite/ld-arm/arm-lib-plt32.s
new file mode 100644
index 0000000..d6c4787
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-lib-plt32.s
@@ -0,0 +1,17 @@
+	.text
+
+	.globl lib_func1
+	.type lib_func1, %function
+lib_func1:
+	mov	ip, sp
+	stmdb	sp!, {r11, ip, lr, pc}
+	bl	app_func2(PLT)
+	ldmia	sp, {r11, sp, lr}
+	bx lr
+	.size lib_func1, . - lib_func1
+
+	.globl lib_func2
+	.type lib_func2, %function
+lib_func2:
+	bx lr
+	.size lib_func2, . - lib_func2
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-lib.d b/binutils-2.19/ld/testsuite/ld-arm/arm-lib.d
new file mode 100644
index 0000000..9d25bbb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-lib.d
@@ -0,0 +1,28 @@
+
+tmpdir/arm-lib.so:     file format elf32-(little|big)arm
+architecture: arm, flags 0x00000150:
+HAS_SYMS, DYNAMIC, D_PAGED
+start address 0x.*
+
+Disassembly of section .plt:
+
+.* <.plt>:
+ .*:	e52de004 	push	{lr}		; \(str lr, \[sp, #-4\]!\)
+ .*:	e59fe004 	ldr	lr, \[pc, #4\]	; .* <lib_func1-0x10>
+ .*:	e08fe00e 	add	lr, pc, lr
+ .*:	e5bef008 	ldr	pc, \[lr, #8\]!
+ .*:	.*
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+Disassembly of section .text:
+
+.* <lib_func1>:
+ .*:	e1a0c00d 	mov	ip, sp
+ .*:	e92dd800 	push	{fp, ip, lr, pc}
+ .*:	ebfffff9 	bl	.* <lib_func1-0xc>
+ .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+ .*:	e12fff1e 	bx	lr
+
+.* <lib_func2>:
+ .*:	e12fff1e 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-lib.ld b/binutils-2.19/ld/testsuite/ld-arm/arm-lib.ld
new file mode 100644
index 0000000..2d2850e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-lib.ld
@@ -0,0 +1,187 @@
+/* Script for --shared -z combreloc: shared library, combine & sort relocs */
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = 0 + SIZEOF_HEADERS;
+  .hash           : { *(.hash) }
+  .dynsym         : { *(.dynsym) }
+  .dynstr         : { *(.dynstr) }
+  .gnu.version    : { *(.gnu.version) }
+  .gnu.version_d  : { *(.gnu.version_d) }
+  .gnu.version_r  : { *(.gnu.version_r) }
+  .rel.dyn        :
+    {
+      *(.rel.init)
+      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
+      *(.rel.fini)
+      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
+      *(.rel.data.rel.ro*)
+      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
+      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
+      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
+      *(.rel.ctors)
+      *(.rel.dtors)
+      *(.rel.got)
+      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
+    }
+  .rela.dyn       :
+    {
+      *(.rela.init)
+      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+      *(.rela.fini)
+      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+      *(.rela.ctors)
+      *(.rela.dtors)
+      *(.rela.got)
+      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+    }
+  .rel.plt        : { *(.rel.plt) }
+  .rela.plt       : { *(.rela.plt) }
+  .init           :
+  {
+    KEEP (*(.init))
+  } =0
+  .plt            : { *(.plt) }
+  .text           :
+  {
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7)
+  } =0
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } =0
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
+  .rodata1        : { *(.rodata1) }
+  .ARM.extab   : { *(.ARM.extab* .gnu.linkonce.armextab.*) }
+   __exidx_start = .;
+  .ARM.exidx   : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) }
+   __exidx_end = .;
+  .eh_frame_hdr : { *(.eh_frame_hdr) }
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN (0x8000) - ((0x8000 - .) & (0x8000 - 1)); . = DATA_SEGMENT_ALIGN (0x8000, 0x1000);
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  . = ALIGN(32 / 8);
+  .preinit_array     : { KEEP (*(.preinit_array)) }
+  .init_array     : { KEEP (*(.init_array)) }
+  .fini_array     : { KEEP (*(.fini_array)) }
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  }
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  }
+  .jcr            : { KEEP (*(.jcr)) }
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }
+  .dynamic        : { *(.dynamic) }
+  .got            : { *(.got.plt) *(.got) }
+  .data           :
+  {
+    __data_start = . ;
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  }
+  .data1          : { *(.data1) }
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  __bss_start__ = .;
+  .bss            :
+  {
+   *(.dynbss)
+   *(.bss .bss.* .gnu.linkonce.b.*)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   . = ALIGN(32 / 8);
+  }
+  . = ALIGN(32 / 8);
+  _end = .;
+  _bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
+  PROVIDE (end = .);
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-lib.r b/binutils-2.19/ld/testsuite/ld-arm/arm-lib.r
new file mode 100644
index 0000000..a7dde47
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-lib.r
@@ -0,0 +1,8 @@
+
+tmpdir/arm-lib.so:     file format elf32-(little|big)arm
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+.* R_ARM_JUMP_SLOT   app_func2
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-lib.s b/binutils-2.19/ld/testsuite/ld-arm/arm-lib.s
new file mode 100644
index 0000000..949f61c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-lib.s
@@ -0,0 +1,24 @@
+	.text
+
+	.globl lib_func1
+	.type lib_func1, %function
+lib_func1:
+	mov	ip, sp
+	stmdb	sp!, {r11, ip, lr, pc}
+	bl	app_func2
+	ldmia	sp, {r11, sp, lr}
+	bx lr
+	.size lib_func1, . - lib_func1
+
+	.globl lib_func2
+	.type lib_func2, %function
+lib_func2:
+	bx lr
+	.size lib_func2, . - lib_func2
+
+	.data
+	.globl data_obj
+	.type data_obj, %object
+data_obj:
+	.long 0
+	.size data_obj, . - data_obj
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-movwt.d b/binutils-2.19/ld/testsuite/ld-arm/arm-movwt.d
new file mode 100644
index 0000000..bf55164
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-movwt.d
@@ -0,0 +1,39 @@
+
+.*:     file format.*
+
+Disassembly of section .text:
+
+00008000 <[^>]*>:
+    8000:	e3000000 	movw	r0, #0	; 0x0
+    8004:	e3411234 	movt	r1, #4660	; 0x1234
+    8008:	e3082000 	movw	r2, #32768	; 0x8000
+    800c:	e3413233 	movt	r3, #4659	; 0x1233
+    8010:	e3004011 	movw	r4, #17	; 0x11
+    8014:	e3415234 	movt	r5, #4660	; 0x1234
+    8018:	e3086011 	movw	r6, #32785	; 0x8011
+    801c:	e3417233 	movt	r7, #4659	; 0x1233
+
+00008020 <[^>]*>:
+    8020:	f240 0700 	movw	r7, #0	; 0x0
+    8024:	f2c1 2634 	movt	r6, #4660	; 0x1234
+    8028:	f248 0500 	movw	r5, #32768	; 0x8000
+    802c:	f2c1 2433 	movt	r4, #4659	; 0x1233
+    8030:	f240 0311 	movw	r3, #17	; 0x11
+    8034:	f2c1 2234 	movt	r2, #4660	; 0x1234
+    8038:	f248 0111 	movw	r1, #32785	; 0x8011
+    803c:	f2c1 2033 	movt	r0, #4659	; 0x1233
+
+Disassembly of section .far:
+
+12340000 <[^>]*>:
+12340000:	e3080000 	movw	r0, #32768	; 0x8000
+12340004:	e34e0dcc 	movt	r0, #60876	; 0xedcc
+12340008:	e3080021 	movw	r0, #32801	; 0x8021
+1234000c:	e34e0dcc 	movt	r0, #60876	; 0xedcc
+
+12340010 <[^>]*>:
+12340010:	f248 0000 	movw	r0, #32768	; 0x8000
+12340014:	f6ce 50cc 	movt	r0, #60876	; 0xedcc
+12340018:	f248 0021 	movw	r0, #32801	; 0x8021
+1234001c:	f6ce 50cc 	movt	r0, #60876	; 0xedcc
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-movwt.s b/binutils-2.19/ld/testsuite/ld-arm/arm-movwt.s
new file mode 100644
index 0000000..ba8b1c5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-movwt.s
@@ -0,0 +1,44 @@
+	.text
+	.arch armv6t2
+	.syntax unified
+	.global	_start
+	.type	_start, %function
+_start:
+base1:
+arm1:
+	movw r0, #:lower16:arm2
+	movt r1, #:upper16:arm2
+	movw r2, #:lower16:(arm2 - arm1)
+	movt r3, #:upper16:(arm2 - arm1)
+	movw r4, #:lower16:thumb2
+	movt r5, #:upper16:thumb2
+	movw r6, #:lower16:(thumb2 - arm1)
+	movt r7, #:upper16:(thumb2 - arm1)
+	.thumb
+	.type thumb1, %function
+	.thumb_func
+thumb1:
+	movw r7, #:lower16:arm2
+	movt r6, #:upper16:arm2
+	movw r5, #:lower16:(arm2 - arm1)
+	movt r4, #:upper16:(arm2 - arm1)
+	movw r3, #:lower16:thumb2
+	movt r2, #:upper16:thumb2
+	movw r1, #:lower16:(thumb2 - arm1)
+	movt r0, #:upper16:(thumb2 - arm1)
+
+	.section .far, "ax", %progbits
+	.arm
+arm2:
+	movw r0, #:lower16:(arm1 - arm2)
+	movt r0, #:upper16:(arm1 - arm2)
+	movw r0, #:lower16:(thumb1 - arm2)
+	movt r0, #:upper16:(thumb1 - arm2)
+	.thumb
+	.type thumb2, %function
+	.thumb_func
+thumb2:
+	movw r0, #:lower16:(arm1 - arm2)
+	movt r0, #:upper16:(arm1 - arm2)
+	movw r0, #:lower16:(thumb1 - arm2)
+	movt r0, #:upper16:(thumb1 - arm2)
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-pic-veneer.d b/binutils-2.19/ld/testsuite/ld-arm/arm-pic-veneer.d
new file mode 100644
index 0000000..d3a8cf6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-pic-veneer.d
@@ -0,0 +1,17 @@
+
+.*:     file format.*
+
+Disassembly of section .text:
+
+00008000 <_start>:
+    8000:	ea000000 	b	8008 <__foo_from_arm>
+
+00008004 <foo>:
+    8004:	46c0      	nop			\(mov r8, r8\)
+    8006:	4770      	bx	lr
+
+00008008 <__foo_from_arm>:
+    8008:	e59fc004 	ldr	ip, \[pc, #4\]	; 8014 <__foo_from_arm\+0xc>
+    800c:	e08fc00c 	add	ip, pc, ip
+    8010:	e12fff1c 	bx	ip
+    8014:	fffffff1 	.word	0xfffffff1
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-pic-veneer.s b/binutils-2.19/ld/testsuite/ld-arm/arm-pic-veneer.s
new file mode 100644
index 0000000..9e09ed6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-pic-veneer.s
@@ -0,0 +1,14 @@
+.text
+.arm
+.global _start
+.type _start, %function
+_start:
+b foo
+
+.thumb
+.global foo
+.type foo, %function
+foo:
+nop
+bx lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-rel31.d b/binutils-2.19/ld/testsuite/ld-arm/arm-rel31.d
new file mode 100644
index 0000000..ac99e92
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-rel31.d
@@ -0,0 +1,7 @@
+
+.*:     file format.*
+
+Contents of section .text:
+ 8000 (10000000 fcffff7f 08000080 f4ffffff|00000010 7ffffffc 80000008 fffffff4) .*
+# Ignore .ARM.attributes section
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-rel31.s b/binutils-2.19/ld/testsuite/ld-arm/arm-rel31.s
new file mode 100644
index 0000000..37eee66
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-rel31.s
@@ -0,0 +1,11 @@
+# Test the R_ARM_REL31 relocation
+	.section .before
+	.global _start
+_start:
+	.text
+	.rel31 0, foo
+	.rel31 0, _start
+	.rel31 1, foo
+	.rel31 1, _start
+	.section .after
+foo:
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-static-app.d b/binutils-2.19/ld/testsuite/ld-arm/arm-static-app.d
new file mode 100644
index 0000000..f18f3c6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-static-app.d
@@ -0,0 +1,24 @@
+
+tmpdir/arm-static-app:     file format elf32-(little|big)arm
+architecture: arm, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x.*
+
+Disassembly of section .text:
+
+.* <_start>:
+    .*:	e1a0c00d 	mov	ip, sp
+    .*:	e92dd800 	push	{fp, ip, lr, pc}
+    .*:	eb000001 	bl	.* <app_func>
+    .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+    .*:	e12fff1e 	bx	lr
+
+.* <app_func>:
+    .*:	e1a0c00d 	mov	ip, sp
+    .*:	e92dd800 	push	{fp, ip, lr, pc}
+    .*:	eb000001 	bl	.* <app_func2>
+    .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+    .*:	e12fff1e 	bx	lr
+
+.* <app_func2>:
+    .*:	e12fff1e 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-static-app.r b/binutils-2.19/ld/testsuite/ld-arm/arm-static-app.r
new file mode 100644
index 0000000..6034b7f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-static-app.r
@@ -0,0 +1,3 @@
+
+tmpdir/arm-static-app:     file format elf32-(little|big)arm
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-static-app.s b/binutils-2.19/ld/testsuite/ld-arm/arm-static-app.s
new file mode 100644
index 0000000..99c579f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-static-app.s
@@ -0,0 +1,20 @@
+	.text
+	.globl _start
+_start:
+	mov	ip, sp
+	stmdb	sp!, {r11, ip, lr, pc}
+	bl	app_func
+	ldmia	sp, {r11, sp, lr}
+	bx lr
+
+	.globl app_func
+app_func:
+	mov	ip, sp
+	stmdb	sp!, {r11, ip, lr, pc}
+	bl	app_func2
+	ldmia	sp, {r11, sp, lr}
+	bx lr
+
+	.globl app_func2
+app_func2:
+	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-target1-abs.d b/binutils-2.19/ld/testsuite/ld-arm/arm-target1-abs.d
new file mode 100644
index 0000000..af64e60
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-target1-abs.d
@@ -0,0 +1,7 @@
+
+.*:     file format.*
+
+Contents of section .text:
+ 8000 (04800000|00008004) .*
+# Ignore .ARM.attributes section
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-target1-rel.d b/binutils-2.19/ld/testsuite/ld-arm/arm-target1-rel.d
new file mode 100644
index 0000000..fcd6c1a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-target1-rel.d
@@ -0,0 +1,7 @@
+
+.*:     file format .*
+
+Contents of section .text:
+ 8000 (04000000|00000004) .*
+# Ignore .ARM.attributes section
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-target1.s b/binutils-2.19/ld/testsuite/ld-arm/arm-target1.s
new file mode 100644
index 0000000..5a7ba91
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-target1.s
@@ -0,0 +1,6 @@
+# Test the R_ARM_TARGET1 relocation
+	.text
+	.global _start
+_start:
+	.word foo(target1)
+foo:
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-target2-abs.d b/binutils-2.19/ld/testsuite/ld-arm/arm-target2-abs.d
new file mode 100644
index 0000000..af64e60
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-target2-abs.d
@@ -0,0 +1,7 @@
+
+.*:     file format.*
+
+Contents of section .text:
+ 8000 (04800000|00008004) .*
+# Ignore .ARM.attributes section
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-target2-got-rel.d b/binutils-2.19/ld/testsuite/ld-arm/arm-target2-got-rel.d
new file mode 100644
index 0000000..1a996f0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-target2-got-rel.d
@@ -0,0 +1,9 @@
+
+.*:     file format.*
+
+Contents of section .text:
+ 8000 (00100000|00001000) .*
+Contents of section .got:
+ 9000 (04800000|00008004) .*
+# Ignore .ARM.attributes section
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-target2-rel.d b/binutils-2.19/ld/testsuite/ld-arm/arm-target2-rel.d
new file mode 100644
index 0000000..569d6b5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-target2-rel.d
@@ -0,0 +1,7 @@
+
+.*:     file format.*
+
+Contents of section .text:
+ 8000 (04000000|00000004) .*
+# Ignore .ARM.attributes section
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm-target2.s b/binutils-2.19/ld/testsuite/ld-arm/arm-target2.s
new file mode 100644
index 0000000..0c343ef
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm-target2.s
@@ -0,0 +1,6 @@
+# Test the R_ARM_TARGET2 relocation
+	.text
+	.global _start
+_start:
+	.word foo(target2)
+foo:
diff --git a/binutils-2.19/ld/testsuite/ld-arm/arm.ld b/binutils-2.19/ld/testsuite/ld-arm/arm.ld
new file mode 100644
index 0000000..cb73fb3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/arm.ld
@@ -0,0 +1,21 @@
+/* Script for ld testsuite */
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x8000); . = 0x8000;
+  .text           :
+  {
+    *(.before)
+    *(.text)
+    *(.after)
+    *(.glue_7)
+    *(.v4_bx)
+  } =0
+  . = 0x9000;
+  .got            : { *(.got) *(.got.plt)}
+  . = 0x12340000;
+  .far : { *(.far) }
+  .ARM.attribues 0 : { *(.ARM.atttributes) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-arm/armthumb-lib.d b/binutils-2.19/ld/testsuite/ld-arm/armthumb-lib.d
new file mode 100644
index 0000000..cc922f1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/armthumb-lib.d
@@ -0,0 +1,44 @@
+
+tmpdir/armthumb-lib.so:     file format elf32-(little|big)arm
+architecture: arm, flags 0x00000150:
+HAS_SYMS, DYNAMIC, D_PAGED
+start address 0x.*
+
+Disassembly of section .plt:
+
+.* <.plt>:
+ .*:	e52de004 	push	{lr}		; \(str lr, \[sp, #-4\]!\)
+ .*:	e59fe004 	ldr	lr, \[pc, #4\]	; .* <lib_func1-0x1.>
+ .*:	e08fe00e 	add	lr, pc, lr
+ .*:	e5bef008 	ldr	pc, \[lr, #8\]!
+ .*:	.*
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+Disassembly of section .text:
+
+.* <lib_func1>:
+ .*:	e1a0c00d 	mov	ip, sp
+ .*:	e92dd800 	push	{fp, ip, lr, pc}
+ .*:	ebfffff. 	bl	.* <lib_func1-0x..?>
+ .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+ .*:	e12fff1e 	bx	lr
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+
+.* <__real_lib_func2>:
+ .*:	4770      	bx	lr
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+
+.* <lib_func2>:
+ .*:	e59fc004 	ldr	ip, \[pc, #4\]	; .* <lib_func2\+0xc>
+ .*:	e08cc00f 	add	ip, ip, pc
+ .*:	e12fff1c 	bx	ip
+ .*:	ffffffe5 	.*
diff --git a/binutils-2.19/ld/testsuite/ld-arm/armthumb-lib.sym b/binutils-2.19/ld/testsuite/ld-arm/armthumb-lib.sym
new file mode 100644
index 0000000..d482ccd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/armthumb-lib.sym
@@ -0,0 +1,17 @@
+
+Symbol table for image:
+  Num Buc:    Value  Size   Type   Bind Vis      Ndx Name
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS _edata
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __bss_start__
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS _end
+   ..  ..: ........     4  OBJECT GLOBAL DEFAULT   9 data_obj
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __bss_end__
+   ..  ..: .......0    20    FUNC GLOBAL DEFAULT   6 lib_func1
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __exidx_start
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT   9 __data_start
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __end__
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __bss_start
+   ..  ..: 00000000     0  NOTYPE GLOBAL DEFAULT UND app_func2
+   ..  ..: .......0     2    FUNC GLOBAL DEFAULT   6 lib_func2
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS _bss_end__
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __exidx_end
diff --git a/binutils-2.19/ld/testsuite/ld-arm/armv4-bx.d b/binutils-2.19/ld/testsuite/ld-arm/armv4-bx.d
new file mode 100644
index 0000000..095b387
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/armv4-bx.d
@@ -0,0 +1,19 @@
+
+.*: .*file format elf32-(big|little)arm
+
+Disassembly of section \.text:
+
+00008000 <_start>:
+    8000:	ea000001 	b	800c \<__bx_r14\>
+    8004:	ea000003 	b	8018 \<__bx_r0\>
+    8008:	0a000002 	beq	8018 \<__bx_r0\>
+
+0000800c <__bx_r14>:
+    800c:	e31e0001 	tst	lr, #1	; 0x1
+    8010:	01a0f00e 	moveq	pc, lr
+    8014:	e12fff1e 	bx	lr
+
+00008018 <__bx_r0>:
+    8018:	e3100001 	tst	r0, #1	; 0x1
+    801c:	01a0f000 	moveq	pc, r0
+    8020:	e12fff10 	bx	r0
diff --git a/binutils-2.19/ld/testsuite/ld-arm/armv4-bx.s b/binutils-2.19/ld/testsuite/ld-arm/armv4-bx.s
new file mode 100644
index 0000000..ef86357
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/armv4-bx.s
@@ -0,0 +1,8 @@
+.text
+.arch armv4
+.global _start
+.type _start, %function
+_start:
+bx lr
+bx r0
+bxeq r0
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-2.attr b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-2.attr
new file mode 100644
index 0000000..341e6d1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-2.attr
@@ -0,0 +1,12 @@
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 4
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-2a.s b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-2a.s
new file mode 100644
index 0000000..0303163
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-2a.s
@@ -0,0 +1,10 @@
+	.cpu arm7tdmi
+	.fpu softvfp
+	.eabi_attribute 20, 1
+	.eabi_attribute 21, 1
+	.eabi_attribute 23, 3
+	.eabi_attribute 24, 1
+	.eabi_attribute 25, 1
+	.eabi_attribute 26, 1
+	.eabi_attribute 30, 6
+	.file	"attr-merge-2a.s"
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-2b.s b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-2b.s
new file mode 100644
index 0000000..047890a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-2b.s
@@ -0,0 +1,11 @@
+	.cpu arm7tdmi
+	.fpu softvfp
+	.eabi_attribute 20, 1
+	.eabi_attribute 21, 1
+	.eabi_attribute 23, 3
+	.eabi_attribute 24, 1
+	.eabi_attribute 25, 1
+	.eabi_attribute 26, 1
+	.eabi_attribute 30, 6
+	.eabi_attribute 18, 4
+	.file	"attr-merge-2b.s"
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-0.s b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-0.s
new file mode 100644
index 0000000..ef19a88
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-0.s
@@ -0,0 +1,11 @@
+	.cpu arm7tdmi
+	.fpu softvfp
+	.eabi_attribute 20, 1
+	.eabi_attribute 21, 1
+	.eabi_attribute 23, 3
+	.eabi_attribute 24, 1
+	.eabi_attribute 25, 1
+	.eabi_attribute 26, 1
+	.eabi_attribute 30, 6
+	.eabi_attribute 18, 0
+	.file	"attr-merge-wchar-0.s"
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-00-nowarn.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-00-nowarn.d
new file mode 100644
index 0000000..e850c64
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-00-nowarn.d
@@ -0,0 +1,17 @@
+#source: attr-merge-wchar-0.s
+#source: attr-merge-wchar-0.s
+#as:
+#ld: -r --no-wchar-size-warning
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-00.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-00.d
new file mode 100644
index 0000000..1fcf7c0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-00.d
@@ -0,0 +1,17 @@
+#source: attr-merge-wchar-0.s
+#source: attr-merge-wchar-0.s
+#as:
+#ld: -r
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-02-nowarn.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-02-nowarn.d
new file mode 100644
index 0000000..f6b7a68
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-02-nowarn.d
@@ -0,0 +1,18 @@
+#source: attr-merge-wchar-0.s
+#source: attr-merge-wchar-2.s
+#as:
+#ld: -r --no-wchar-size-warning
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 2
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-02.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-02.d
new file mode 100644
index 0000000..dc907ee
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-02.d
@@ -0,0 +1,18 @@
+#source: attr-merge-wchar-0.s
+#source: attr-merge-wchar-2.s
+#as:
+#ld: -r
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 2
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-04-nowarn.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-04-nowarn.d
new file mode 100644
index 0000000..b369b78
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-04-nowarn.d
@@ -0,0 +1,18 @@
+#source: attr-merge-wchar-0.s
+#source: attr-merge-wchar-4.s
+#as:
+#ld: -r --no-wchar-size-warning
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 4
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-04.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-04.d
new file mode 100644
index 0000000..9aa3c47
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-04.d
@@ -0,0 +1,18 @@
+#source: attr-merge-wchar-0.s
+#source: attr-merge-wchar-4.s
+#as:
+#ld: -r
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 4
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-2.s b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-2.s
new file mode 100644
index 0000000..4b3b96b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-2.s
@@ -0,0 +1,11 @@
+	.cpu arm7tdmi
+	.fpu softvfp
+	.eabi_attribute 20, 1
+	.eabi_attribute 21, 1
+	.eabi_attribute 23, 3
+	.eabi_attribute 24, 1
+	.eabi_attribute 25, 1
+	.eabi_attribute 26, 1
+	.eabi_attribute 30, 6
+	.eabi_attribute 18, 2
+	.file	"attr-merge-wchar-2.s"
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-20-nowarn.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-20-nowarn.d
new file mode 100644
index 0000000..8cfb682
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-20-nowarn.d
@@ -0,0 +1,18 @@
+#source: attr-merge-wchar-2.s
+#source: attr-merge-wchar-0.s
+#as:
+#ld: -r --no-wchar-size-warning
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 2
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-20.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-20.d
new file mode 100644
index 0000000..1ba47f1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-20.d
@@ -0,0 +1,18 @@
+#source: attr-merge-wchar-2.s
+#source: attr-merge-wchar-0.s
+#as:
+#ld: -r
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 2
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-22-nowarn.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-22-nowarn.d
new file mode 100644
index 0000000..4a3d37e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-22-nowarn.d
@@ -0,0 +1,18 @@
+#source: attr-merge-wchar-2.s
+#source: attr-merge-wchar-2.s
+#as:
+#ld: -r --no-wchar-size-warning
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 2
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-22.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-22.d
new file mode 100644
index 0000000..23c0726
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-22.d
@@ -0,0 +1,18 @@
+#source: attr-merge-wchar-2.s
+#source: attr-merge-wchar-2.s
+#as:
+#ld: -r
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 2
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-24-nowarn.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-24-nowarn.d
new file mode 100644
index 0000000..cadd7da
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-24-nowarn.d
@@ -0,0 +1,18 @@
+#source: attr-merge-wchar-2.s
+#source: attr-merge-wchar-4.s
+#as:
+#ld: -r --no-wchar-size-warning
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 2
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-24.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-24.d
new file mode 100644
index 0000000..46d6c66
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-24.d
@@ -0,0 +1,5 @@
+#source: attr-merge-wchar-2.s
+#source: attr-merge-wchar-4.s
+#as:
+#ld: -r
+#warning: warning: .* uses 4-byte wchar_t yet the output is to use 2-byte wchar_t; use of wchar_t values across objects may fail
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-4.s b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-4.s
new file mode 100644
index 0000000..fdd03f9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-4.s
@@ -0,0 +1,11 @@
+	.cpu arm7tdmi
+	.fpu softvfp
+	.eabi_attribute 20, 1
+	.eabi_attribute 21, 1
+	.eabi_attribute 23, 3
+	.eabi_attribute 24, 1
+	.eabi_attribute 25, 1
+	.eabi_attribute 26, 1
+	.eabi_attribute 30, 6
+	.eabi_attribute 18, 4
+	.file	"attr-merge-wchar-4.s"
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-40-nowarn.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-40-nowarn.d
new file mode 100644
index 0000000..9d6e040
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-40-nowarn.d
@@ -0,0 +1,18 @@
+#source: attr-merge-wchar-4.s
+#source: attr-merge-wchar-0.s
+#as:
+#ld: -r --no-wchar-size-warning
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 4
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-40.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-40.d
new file mode 100644
index 0000000..fcf9b54
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-40.d
@@ -0,0 +1,18 @@
+#source: attr-merge-wchar-4.s
+#source: attr-merge-wchar-0.s
+#as:
+#ld: -r
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 4
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-42-nowarn.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-42-nowarn.d
new file mode 100644
index 0000000..8dbc442
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-42-nowarn.d
@@ -0,0 +1,18 @@
+#source: attr-merge-wchar-4.s
+#source: attr-merge-wchar-2.s
+#as:
+#ld: -r --no-wchar-size-warning
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 4
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-42.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-42.d
new file mode 100644
index 0000000..c2aca5e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-42.d
@@ -0,0 +1,5 @@
+#source: attr-merge-wchar-4.s
+#source: attr-merge-wchar-2.s
+#as:
+#ld: -r
+#warning: warning: .* uses 2-byte wchar_t yet the output is to use 4-byte wchar_t; use of wchar_t values across objects may fail
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-44-nowarn.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-44-nowarn.d
new file mode 100644
index 0000000..7566d2a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-44-nowarn.d
@@ -0,0 +1,18 @@
+#source: attr-merge-wchar-4.s
+#source: attr-merge-wchar-4.s
+#as:
+#ld: -r --no-wchar-size-warning
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 4
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-44.d b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-44.d
new file mode 100644
index 0000000..430de30
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge-wchar-44.d
@@ -0,0 +1,18 @@
+#source: attr-merge-wchar-4.s
+#source: attr-merge-wchar-4.s
+#as:
+#ld: -r
+#readelf: -A
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 4
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge.attr b/binutils-2.19/ld/testsuite/ld-arm/attr-merge.attr
new file mode 100644
index 0000000..341e6d1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge.attr
@@ -0,0 +1,12 @@
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "ARM7TDMI"
+  Tag_CPU_arch: v4T
+  Tag_ABI_PCS_wchar_t: 4
+  Tag_ABI_FP_denormal: Needed
+  Tag_ABI_FP_exceptions: Needed
+  Tag_ABI_FP_number_model: IEEE 754
+  Tag_ABI_align8_needed: Yes
+  Tag_ABI_align8_preserved: Yes, except leaf SP
+  Tag_ABI_enum_size: small
+  Tag_ABI_optimization_goals: Aggressive Debug
diff --git a/binutils-2.19/ld/testsuite/ld-arm/attr-merge.s b/binutils-2.19/ld/testsuite/ld-arm/attr-merge.s
new file mode 100644
index 0000000..b56f6e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/attr-merge.s
@@ -0,0 +1,11 @@
+	.cpu arm7tdmi
+	.fpu softvfp
+	.eabi_attribute 20, 1
+	.eabi_attribute 21, 1
+	.eabi_attribute 23, 3
+	.eabi_attribute 24, 1
+	.eabi_attribute 25, 1
+	.eabi_attribute 26, 1
+	.eabi_attribute 30, 6
+	.eabi_attribute 18, 4
+	.file	"attr-merge.s"
diff --git a/binutils-2.19/ld/testsuite/ld-arm/callweak.d b/binutils-2.19/ld/testsuite/ld-arm/callweak.d
new file mode 100644
index 0000000..3dffcc4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/callweak.d
@@ -0,0 +1,17 @@
+
+.*:     file format.*
+
+Disassembly of section .far:
+
+12340000 <[^>]*>:
+12340000:	eaffffff 	b	12340004 <[^>]*>
+12340004:	0affffff 	beq	12340008 <[^>]*>
+
+12340008 <[^>]*>:
+12340008:	e000      	b.n	1234000c <[^>]*>
+1234000a:	bf00      	nop
+1234000c:	2000      	movs	r0, #0
+1234000e:	e000      	b.n	12340012 <[^>]*>
+12340010:	bf00      	nop
+12340012:	4770      	bx	lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/callweak.s b/binutils-2.19/ld/testsuite/ld-arm/callweak.s
new file mode 100644
index 0000000..6850da3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/callweak.s
@@ -0,0 +1,16 @@
+	.syntax unified
+	.weak bar
+	.section .far, "ax", %progbits
+	.global	_start
+	.type	_start, %function
+_start:
+	bl bar
+	bleq bar
+	.thumb
+	.type foo, %function
+	.thumb_func
+foo:
+	bl bar
+	movs r0, #0
+	bl bar
+	bx lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-arm-target.s b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-arm-target.s
new file mode 100644
index 0000000..d5174c4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-arm-target.s
@@ -0,0 +1,9 @@
+	.syntax unified
+	.cpu cortex-a8
+	.text
+	.arm
+	.align 3
+	.global targetfn
+	.type targetfn, %function
+targetfn:
+	bx lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-far-1.s b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-far-1.s
new file mode 100644
index 0000000..09d3583
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-far-1.s
@@ -0,0 +1,8 @@
+	.syntax unified
+	.thumb
+	.globl two
+two:	
+	bl far_fn
+	.rept 0x200000
+	.long 0
+	.endr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-far-2.s b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-far-2.s
new file mode 100644
index 0000000..22fd40f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-far-2.s
@@ -0,0 +1,20 @@
+	.syntax unified
+	.thumb
+three:
+	bl far_fn1
+	bl far_fn2
+	.rept 1016
+	.long 0
+	.endr
+	nop
+label1:	
+	eor.w   r0, r1, r2
+	beq.w     label1
+
+	eor.w   r0, r1, r2
+ 
+	eor.w   r0, r1, r2
+	b.w     label1
+
+	eor.w   r0, r1, r2
+	eor.w   r0, r1, r2
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-far.d b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-far.d
new file mode 100644
index 0000000..3d9059d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-far.d
@@ -0,0 +1,40 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00000000 <two>:
+       0:	f000 c802 	blx	800008 <__far_fn_from_thumb>
+	...
+#...
+00800008 <__far_fn_from_thumb>:
+  800008:	e51ff004 	ldr	pc, \[pc, #-4\]	; 80000c <__far_fn_from_thumb\+0x4>
+  80000c:	7fff0000 	.word	0x7fff0000
+
+00800010 <three>:
+  800010:	f001 e806 	blx	801020 <__far_fn1_from_thumb>
+  800014:	f001 e800 	blx	801018 <__far_fn2_from_thumb>
+	...
+  800ff8:	bf00      	nop
+
+00800ffa <label1>:
+  800ffa:	ea81 0002 	eor.w	r0, r1, r2
+  800ffe:	f000 b813 	b.w	801028 <__far_fn1_from_thumb\+0x8>
+  801002:	ea81 0002 	eor.w	r0, r1, r2
+  801006:	ea81 0002 	eor.w	r0, r1, r2
+  80100a:	f7ff bff6 	b.w	800ffa <label1>
+  80100e:	ea81 0002 	eor.w	r0, r1, r2
+  801012:	ea81 0002 	eor.w	r0, r1, r2
+	...
+
+00801018 <__far_fn2_from_thumb>:
+  801018:	e51ff004 	ldr	pc, \[pc, #-4\]	; 80101c <__far_fn2_from_thumb\+0x4>
+  80101c:	80000004 	.word	0x80000004
+
+00801020 <__far_fn1_from_thumb>:
+  801020:	e51ff004 	ldr	pc, \[pc, #-4\]	; 801024 <__far_fn1_from_thumb\+0x4>
+  801024:	80000000 	.word	0x80000000
+  801028:	d001      	beq.n	80102e <__far_fn1_from_thumb\+0xe>
+  80102a:	f7ff bfea 	b.w	801002 <label1\+0x8>
+  80102e:	f7ff bfe4 	b.w	800ffa <label1>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d
new file mode 100644
index 0000000..0a2b0bd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d
@@ -0,0 +1,83 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <targetfn>:
+    8f00:	e12fff1e 	bx	lr
+    8f04:	e320f000 	nop	\{0\}
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f000 b87f 	b\.w	9010 <__targetfn_from_thumb>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f000 b87b 	b\.w	9010 <__targetfn_from_thumb>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f000 b877 	b\.w	9010 <__targetfn_from_thumb>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f000 b873 	b\.w	9010 <__targetfn_from_thumb>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f000 b86f 	b\.w	9010 <__targetfn_from_thumb>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f000 b86b 	b\.w	9010 <__targetfn_from_thumb>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f000 b867 	b\.w	9010 <__targetfn_from_thumb>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f000 b863 	b\.w	9010 <__targetfn_from_thumb>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f000 b85f 	b\.w	9010 <__targetfn_from_thumb>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f000 b85b 	b\.w	9010 <__targetfn_from_thumb>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f000 b857 	b\.w	9010 <__targetfn_from_thumb>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f000 b853 	b\.w	9010 <__targetfn_from_thumb>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f000 b84f 	b\.w	9010 <__targetfn_from_thumb>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f000 b84b 	b\.w	9010 <__targetfn_from_thumb>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f000 b847 	b\.w	9010 <__targetfn_from_thumb>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f000 b843 	b\.w	9010 <__targetfn_from_thumb>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f000 b83f 	b\.w	9010 <__targetfn_from_thumb>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f000 b83b 	b\.w	9010 <__targetfn_from_thumb>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f000 b837 	b\.w	9010 <__targetfn_from_thumb>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f000 b833 	b\.w	9010 <__targetfn_from_thumb>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f000 b82f 	b\.w	9010 <__targetfn_from_thumb>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f000 b82b 	b\.w	9010 <__targetfn_from_thumb>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f000 b827 	b\.w	9010 <__targetfn_from_thumb>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f000 b823 	b\.w	9010 <__targetfn_from_thumb>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f000 b81f 	b\.w	9010 <__targetfn_from_thumb>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f000 b81b 	b\.w	9010 <__targetfn_from_thumb>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f000 b817 	b\.w	9010 <__targetfn_from_thumb>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f000 b813 	b\.w	9010 <__targetfn_from_thumb>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f000 b80f 	b\.w	9010 <__targetfn_from_thumb>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f000 b80b 	b\.w	9010 <__targetfn_from_thumb>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 b807 	b\.w	9010 <__targetfn_from_thumb>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f000 b803 	b\.w	9010 <__targetfn_from_thumb>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+
+00009010 <__targetfn_from_thumb>:
+    9010:	4778      	bx	pc
+    9012:	46c0      	nop			\(mov r8, r8\)
+    9014:	eaffffb9 	b	8f00 <targetfn>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-thumb.d b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-thumb.d
new file mode 100644
index 0000000..60a254b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-thumb.d
@@ -0,0 +1,80 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <targetfn>:
+    8f00:	4770      	bx	lr
+    8f02:	bf00      	nop
+    8f04:	f3af 8000 	nop\.w
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff bff7 	b\.w	8f00 <targetfn>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff bff3 	b\.w	8f00 <targetfn>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff bfef 	b\.w	8f00 <targetfn>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff bfeb 	b\.w	8f00 <targetfn>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff bfe7 	b\.w	8f00 <targetfn>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff bfe3 	b\.w	8f00 <targetfn>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff bfdf 	b\.w	8f00 <targetfn>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff bfdb 	b\.w	8f00 <targetfn>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff bfd7 	b\.w	8f00 <targetfn>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff bfd3 	b\.w	8f00 <targetfn>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff bfcf 	b\.w	8f00 <targetfn>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff bfcb 	b\.w	8f00 <targetfn>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff bfc7 	b\.w	8f00 <targetfn>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff bfc3 	b\.w	8f00 <targetfn>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff bfbf 	b\.w	8f00 <targetfn>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff bfbb 	b\.w	8f00 <targetfn>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff bfb7 	b\.w	8f00 <targetfn>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff bfb3 	b\.w	8f00 <targetfn>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff bfaf 	b\.w	8f00 <targetfn>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff bfab 	b\.w	8f00 <targetfn>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff bfa7 	b\.w	8f00 <targetfn>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff bfa3 	b\.w	8f00 <targetfn>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff bf9f 	b\.w	8f00 <targetfn>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff bf9b 	b\.w	8f00 <targetfn>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff bf97 	b\.w	8f00 <targetfn>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff bf93 	b\.w	8f00 <targetfn>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff bf8f 	b\.w	8f00 <targetfn>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff bf8b 	b\.w	8f00 <targetfn>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff bf87 	b\.w	8f00 <targetfn>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff bf83 	b\.w	8f00 <targetfn>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 b807 	b\.w	9010 <_start\+0x108>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f7ff bf7b 	b\.w	8f00 <targetfn>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+    9010:	f7ff bf76 	b\.w	8f00 <targetfn>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-b-rel.s b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-b-rel.s
new file mode 100644
index 0000000..3ec95ab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-b-rel.s
@@ -0,0 +1,41 @@
+	.syntax unified
+	.cpu cortex-a8
+	.thumb
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+1:
+        add.w r0, r1, r2
+        b.w targetfn
+        add.w r0, r1, r2
+        b.w targetfn
+        add.w r0, r1, r2
+        b.w targetfn
+        add.w r0, r1, r2
+        b.w targetfn
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+        .align  3
+        .global _start
+        .thumb
+        .thumb_func
+        .type   _start, %function
+_start:
+	nop
+
+	@ If branching to an ARM destination, we *don't* want to create a
+	@ Cortex-A8 stub: the Thumb-to-ARM stub will suffice (and we need it
+	@ to change mode).
+	bw2
+	bw2
+
+        bx      lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-b.d b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-b.d
new file mode 100644
index 0000000..b2d4481
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-b.d
@@ -0,0 +1,75 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <_start>:
+    8f00:	bf00      	nop
+    8f02:	eb01 0002 	add\.w	r0, r1, r2
+    8f06:	f7ff bffc 	b\.w	8f02 <_start\+0x2>
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff bff8 	b\.w	8f02 <_start\+0x2>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff bff4 	b\.w	8f02 <_start\+0x2>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff bff0 	b\.w	8f02 <_start\+0x2>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff bffc 	b\.w	8f22 <_start\+0x22>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff bff8 	b\.w	8f22 <_start\+0x22>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff bff4 	b\.w	8f22 <_start\+0x22>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff bff0 	b\.w	8f22 <_start\+0x22>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff bffc 	b\.w	8f42 <_start\+0x42>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff bff8 	b\.w	8f42 <_start\+0x42>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff bff4 	b\.w	8f42 <_start\+0x42>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff bff0 	b\.w	8f42 <_start\+0x42>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff bffc 	b\.w	8f62 <_start\+0x62>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff bff8 	b\.w	8f62 <_start\+0x62>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff bff4 	b\.w	8f62 <_start\+0x62>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff bff0 	b\.w	8f62 <_start\+0x62>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff bffc 	b\.w	8f82 <_start\+0x82>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff bff8 	b\.w	8f82 <_start\+0x82>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff bff4 	b\.w	8f82 <_start\+0x82>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff bff0 	b\.w	8f82 <_start\+0x82>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff bffc 	b\.w	8fa2 <_start\+0xa2>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff bff8 	b\.w	8fa2 <_start\+0xa2>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff bff4 	b\.w	8fa2 <_start\+0xa2>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff bff0 	b\.w	8fa2 <_start\+0xa2>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff bffc 	b\.w	8fc2 <_start\+0xc2>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff bff8 	b\.w	8fc2 <_start\+0xc2>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff bff4 	b\.w	8fc2 <_start\+0xc2>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff bff0 	b\.w	8fc2 <_start\+0xc2>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff bffc 	b\.w	8fe2 <_start\+0xe2>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff bff8 	b\.w	8fe2 <_start\+0xe2>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff bff4 	b\.w	8fe2 <_start\+0xe2>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 b803 	b\.w	9008 <_start\+0x108>
+    9002:	4770      	bx	lr
+    9004:	f3af 8000 	nop\.w
+    9008:	f7ff bfeb 	b\.w	8fe2 <_start\+0xe2>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-b.s b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-b.s
new file mode 100644
index 0000000..c0f21ac
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-b.s
@@ -0,0 +1,39 @@
+	.syntax unified
+	.cpu cortex-a8
+	.thumb
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+1:
+        add.w r0, r1, r2
+        b.w 1b
+        add.w r0, r1, r2
+        b.w 1b
+        add.w r0, r1, r2
+        b.w 1b
+        add.w r0, r1, r2
+        b.w 1b
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+        .align  3
+        .global _start
+        .thumb
+        .thumb_func
+        .type   _start, %function
+_start:
+        nop
+
+	@ Trigger Cortex-A8 erratum workaround with b instructions.
+        bw2
+        bw2
+
+        bx      lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel-thumb.d b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel-thumb.d
new file mode 100644
index 0000000..27a7fd4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel-thumb.d
@@ -0,0 +1,82 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <targetfn>:
+    8f00:	4770      	bx	lr
+    8f02:	bf00      	nop
+    8f04:	f3af 8000 	nop\.w
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f53f aff7 	bmi\.w	8f00 <targetfn>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f53f aff3 	bmi\.w	8f00 <targetfn>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f53f afef 	bmi\.w	8f00 <targetfn>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f53f afeb 	bmi\.w	8f00 <targetfn>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f53f afe7 	bmi\.w	8f00 <targetfn>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f53f afe3 	bmi\.w	8f00 <targetfn>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f53f afdf 	bmi\.w	8f00 <targetfn>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f53f afdb 	bmi\.w	8f00 <targetfn>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f53f afd7 	bmi\.w	8f00 <targetfn>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f53f afd3 	bmi\.w	8f00 <targetfn>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f53f afcf 	bmi\.w	8f00 <targetfn>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f53f afcb 	bmi\.w	8f00 <targetfn>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f53f afc7 	bmi\.w	8f00 <targetfn>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f53f afc3 	bmi\.w	8f00 <targetfn>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f53f afbf 	bmi\.w	8f00 <targetfn>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f53f afbb 	bmi\.w	8f00 <targetfn>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f53f afb7 	bmi\.w	8f00 <targetfn>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f53f afb3 	bmi\.w	8f00 <targetfn>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f53f afaf 	bmi\.w	8f00 <targetfn>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f53f afab 	bmi\.w	8f00 <targetfn>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f53f afa7 	bmi\.w	8f00 <targetfn>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f53f afa3 	bmi\.w	8f00 <targetfn>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f53f af9f 	bmi\.w	8f00 <targetfn>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f53f af9b 	bmi\.w	8f00 <targetfn>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f53f af97 	bmi\.w	8f00 <targetfn>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f53f af93 	bmi\.w	8f00 <targetfn>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f53f af8f 	bmi\.w	8f00 <targetfn>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f53f af8b 	bmi\.w	8f00 <targetfn>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f53f af87 	bmi\.w	8f00 <targetfn>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f53f af83 	bmi\.w	8f00 <targetfn>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 b807 	b\.w	9010 <_start\+0x108>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f53f af7b 	bmi\.w	8f00 <targetfn>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+    9010:	d401      	bmi\.n	9016 <_start\+0x10e>
+    9012:	f7ff bff6 	b\.w	9002 <_start\+0xfa>
+    9016:	f7ff bf73 	b\.w	8f00 <targetfn>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel.s b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel.s
new file mode 100644
index 0000000..b7b9451
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel.s
@@ -0,0 +1,38 @@
+	.syntax unified
+	.cpu cortex-a8
+	.thumb
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+1:
+        add.w r0, r1, r2
+        bmi.w targetfn
+        add.w r0, r1, r2
+        bmi.w targetfn
+        add.w r0, r1, r2
+        bmi.w targetfn
+        add.w r0, r1, r2
+        bmi.w targetfn
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+        .align  3
+        .global _start
+        .thumb
+        .thumb_func
+        .type   _start, %function
+_start:
+	nop
+
+	bw2
+	bw2
+
+        bx      lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bcc.d b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bcc.d
new file mode 100644
index 0000000..44b8110
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bcc.d
@@ -0,0 +1,77 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <_start>:
+    8f00:	bf00      	nop
+    8f02:	eb01 0002 	add\.w	r0, r1, r2
+    8f06:	f4ff affc 	bcc\.w	8f02 <_start\+0x2>
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f4ff aff8 	bcc\.w	8f02 <_start\+0x2>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f4ff aff4 	bcc\.w	8f02 <_start\+0x2>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f4ff aff0 	bcc\.w	8f02 <_start\+0x2>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f4ff affc 	bcc\.w	8f22 <_start\+0x22>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f4ff aff8 	bcc\.w	8f22 <_start\+0x22>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f4ff aff4 	bcc\.w	8f22 <_start\+0x22>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f4ff aff0 	bcc\.w	8f22 <_start\+0x22>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f4ff affc 	bcc\.w	8f42 <_start\+0x42>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f4ff aff8 	bcc\.w	8f42 <_start\+0x42>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f4ff aff4 	bcc\.w	8f42 <_start\+0x42>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f4ff aff0 	bcc\.w	8f42 <_start\+0x42>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f4ff affc 	bcc\.w	8f62 <_start\+0x62>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f4ff aff8 	bcc\.w	8f62 <_start\+0x62>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f4ff aff4 	bcc\.w	8f62 <_start\+0x62>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f4ff aff0 	bcc\.w	8f62 <_start\+0x62>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f4ff affc 	bcc\.w	8f82 <_start\+0x82>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f4ff aff8 	bcc\.w	8f82 <_start\+0x82>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f4ff aff4 	bcc\.w	8f82 <_start\+0x82>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f4ff aff0 	bcc\.w	8f82 <_start\+0x82>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f4ff affc 	bcc\.w	8fa2 <_start\+0xa2>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f4ff aff8 	bcc\.w	8fa2 <_start\+0xa2>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f4ff aff4 	bcc\.w	8fa2 <_start\+0xa2>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f4ff aff0 	bcc\.w	8fa2 <_start\+0xa2>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f4ff affc 	bcc\.w	8fc2 <_start\+0xc2>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f4ff aff8 	bcc\.w	8fc2 <_start\+0xc2>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f4ff aff4 	bcc\.w	8fc2 <_start\+0xc2>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f4ff aff0 	bcc\.w	8fc2 <_start\+0xc2>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f4ff affc 	bcc\.w	8fe2 <_start\+0xe2>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f4ff aff8 	bcc\.w	8fe2 <_start\+0xe2>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f4ff aff4 	bcc\.w	8fe2 <_start\+0xe2>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 b803 	b\.w	9008 <_start\+0x108>
+    9002:	4770      	bx	lr
+    9004:	f3af 8000 	nop\.w
+    9008:	d301      	bcc\.n	900e <_start\+0x10e>
+    900a:	f7ff bffa 	b\.w	9002 <_start\+0x102>
+    900e:	f7ff bfe8 	b\.w	8fe2 <_start\+0xe2>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bcc.s b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bcc.s
new file mode 100644
index 0000000..8a667a3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bcc.s
@@ -0,0 +1,39 @@
+	.syntax unified
+	.cpu cortex-a8
+	.thumb
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+1:
+        add.w r0, r1, r2
+        bcc.w 1b
+        add.w r0, r1, r2
+        bcc.w 1b
+        add.w r0, r1, r2
+        bcc.w 1b
+        add.w r0, r1, r2
+        bcc.w 1b
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+        .align  3
+        .global _start
+        .thumb
+        .thumb_func
+        .type   _start, %function
+_start:
+        nop
+
+	@ Trigger Cortex-A8 erratum workaround with conditional branches.
+        bw2
+        bw2
+
+        bx      lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-arm.d b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-arm.d
new file mode 100644
index 0000000..fcb3bab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-arm.d
@@ -0,0 +1,79 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <targetfn>:
+    8f00:	e12fff1e 	bx	lr
+    8f04:	e320f000 	nop	\{0\}
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff eff8 	blx	8f00 <targetfn>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff eff4 	blx	8f00 <targetfn>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff eff0 	blx	8f00 <targetfn>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff efec 	blx	8f00 <targetfn>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff efe8 	blx	8f00 <targetfn>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff efe4 	blx	8f00 <targetfn>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff efe0 	blx	8f00 <targetfn>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff efdc 	blx	8f00 <targetfn>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff efd8 	blx	8f00 <targetfn>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff efd4 	blx	8f00 <targetfn>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff efd0 	blx	8f00 <targetfn>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff efcc 	blx	8f00 <targetfn>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff efc8 	blx	8f00 <targetfn>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff efc4 	blx	8f00 <targetfn>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff efc0 	blx	8f00 <targetfn>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff efbc 	blx	8f00 <targetfn>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff efb8 	blx	8f00 <targetfn>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff efb4 	blx	8f00 <targetfn>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff efb0 	blx	8f00 <targetfn>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff efac 	blx	8f00 <targetfn>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff efa8 	blx	8f00 <targetfn>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff efa4 	blx	8f00 <targetfn>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff efa0 	blx	8f00 <targetfn>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff ef9c 	blx	8f00 <targetfn>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff ef98 	blx	8f00 <targetfn>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff ef94 	blx	8f00 <targetfn>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff ef90 	blx	8f00 <targetfn>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff ef8c 	blx	8f00 <targetfn>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff ef88 	blx	8f00 <targetfn>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff ef84 	blx	8f00 <targetfn>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 e808 	blx	9010 <_start\+0x108>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f7ff ef7c 	blx	8f00 <targetfn>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+    9010:	eaffffba 	b	8f00 <targetfn>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-thumb.d b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-thumb.d
new file mode 100644
index 0000000..8cbd3e0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-thumb.d
@@ -0,0 +1,80 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <targetfn>:
+    8f00:	4770      	bx	lr
+    8f02:	bf00      	nop
+    8f04:	f3af 8000 	nop\.w
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff fff7 	bl	8f00 <targetfn>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff fff3 	bl	8f00 <targetfn>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff ffef 	bl	8f00 <targetfn>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff ffeb 	bl	8f00 <targetfn>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff ffe7 	bl	8f00 <targetfn>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff ffe3 	bl	8f00 <targetfn>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff ffdf 	bl	8f00 <targetfn>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff ffdb 	bl	8f00 <targetfn>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff ffd7 	bl	8f00 <targetfn>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff ffd3 	bl	8f00 <targetfn>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff ffcf 	bl	8f00 <targetfn>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff ffcb 	bl	8f00 <targetfn>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff ffc7 	bl	8f00 <targetfn>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff ffc3 	bl	8f00 <targetfn>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff ffbf 	bl	8f00 <targetfn>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff ffbb 	bl	8f00 <targetfn>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff ffb7 	bl	8f00 <targetfn>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff ffb3 	bl	8f00 <targetfn>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff ffaf 	bl	8f00 <targetfn>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff ffab 	bl	8f00 <targetfn>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff ffa7 	bl	8f00 <targetfn>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff ffa3 	bl	8f00 <targetfn>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff ff9f 	bl	8f00 <targetfn>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff ff9b 	bl	8f00 <targetfn>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff ff97 	bl	8f00 <targetfn>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff ff93 	bl	8f00 <targetfn>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff ff8f 	bl	8f00 <targetfn>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff ff8b 	bl	8f00 <targetfn>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff ff87 	bl	8f00 <targetfn>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff ff83 	bl	8f00 <targetfn>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 f807 	bl	9010 <_start\+0x108>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f7ff ff7b 	bl	8f00 <targetfn>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+    9010:	f7ff bf76 	b\.w	8f00 <targetfn>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel.s b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel.s
new file mode 100644
index 0000000..2d21bbf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel.s
@@ -0,0 +1,40 @@
+	.syntax unified
+	.cpu cortex-a8
+	.thumb
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+1:
+        add.w r0, r1, r2
+        bl.w targetfn
+        add.w r0, r1, r2
+        bl.w targetfn
+        add.w r0, r1, r2
+        bl.w targetfn
+        add.w r0, r1, r2
+        bl.w targetfn
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+        .align  3
+        .global _start
+        .thumb
+        .thumb_func
+        .type   _start, %function
+_start:
+	nop
+
+	@ If calling an ARM destination, we *don't* want to create a
+	@ Cortex-A8 stub: the Thumb-to-ARM stub will suffice.
+	bw2
+	bw2
+
+        bx      lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bl.d b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bl.d
new file mode 100644
index 0000000..50dcd4f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bl.d
@@ -0,0 +1,75 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <_start>:
+    8f00:	bf00      	nop
+    8f02:	eb01 0002 	add\.w	r0, r1, r2
+    8f06:	f7ff fffc 	bl	8f02 <_start\+0x2>
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff fff8 	bl	8f02 <_start\+0x2>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff fff4 	bl	8f02 <_start\+0x2>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff fff0 	bl	8f02 <_start\+0x2>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff fffc 	bl	8f22 <_start\+0x22>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff fff8 	bl	8f22 <_start\+0x22>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff fff4 	bl	8f22 <_start\+0x22>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff fff0 	bl	8f22 <_start\+0x22>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff fffc 	bl	8f42 <_start\+0x42>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff fff8 	bl	8f42 <_start\+0x42>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff fff4 	bl	8f42 <_start\+0x42>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff fff0 	bl	8f42 <_start\+0x42>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff fffc 	bl	8f62 <_start\+0x62>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff fff8 	bl	8f62 <_start\+0x62>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff fff4 	bl	8f62 <_start\+0x62>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff fff0 	bl	8f62 <_start\+0x62>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff fffc 	bl	8f82 <_start\+0x82>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff fff8 	bl	8f82 <_start\+0x82>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff fff4 	bl	8f82 <_start\+0x82>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff fff0 	bl	8f82 <_start\+0x82>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff fffc 	bl	8fa2 <_start\+0xa2>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff fff8 	bl	8fa2 <_start\+0xa2>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff fff4 	bl	8fa2 <_start\+0xa2>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff fff0 	bl	8fa2 <_start\+0xa2>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff fffc 	bl	8fc2 <_start\+0xc2>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff fff8 	bl	8fc2 <_start\+0xc2>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff fff4 	bl	8fc2 <_start\+0xc2>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff fff0 	bl	8fc2 <_start\+0xc2>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff fffc 	bl	8fe2 <_start\+0xe2>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff fff8 	bl	8fe2 <_start\+0xe2>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff fff4 	bl	8fe2 <_start\+0xe2>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 f803 	bl	9008 <_start\+0x108>
+    9002:	4770      	bx	lr
+    9004:	f3af 8000 	nop\.w
+    9008:	f7ff bfeb 	b\.w	8fe2 <_start\+0xe2>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bl.s b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bl.s
new file mode 100644
index 0000000..6e40fb8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-bl.s
@@ -0,0 +1,39 @@
+	.syntax unified
+	.cpu cortex-a8
+	.thumb
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+1:
+        add.w r0, r1, r2
+        bl.w 1b
+        add.w r0, r1, r2
+        bl.w 1b
+        add.w r0, r1, r2
+        bl.w 1b
+        add.w r0, r1, r2
+        bl.w 1b
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+        .align  3
+        .global _start
+        .thumb
+        .thumb_func
+        .type   _start, %function
+_start:
+        nop
+
+	@ Trigger Cortex-A8 erratum workaround with bl instructions.
+        bw2
+        bw2
+
+        bx      lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-arm.d b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-arm.d
new file mode 100644
index 0000000..fcb3bab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-arm.d
@@ -0,0 +1,79 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <targetfn>:
+    8f00:	e12fff1e 	bx	lr
+    8f04:	e320f000 	nop	\{0\}
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff eff8 	blx	8f00 <targetfn>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff eff4 	blx	8f00 <targetfn>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff eff0 	blx	8f00 <targetfn>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff efec 	blx	8f00 <targetfn>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff efe8 	blx	8f00 <targetfn>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff efe4 	blx	8f00 <targetfn>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff efe0 	blx	8f00 <targetfn>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff efdc 	blx	8f00 <targetfn>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff efd8 	blx	8f00 <targetfn>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff efd4 	blx	8f00 <targetfn>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff efd0 	blx	8f00 <targetfn>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff efcc 	blx	8f00 <targetfn>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff efc8 	blx	8f00 <targetfn>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff efc4 	blx	8f00 <targetfn>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff efc0 	blx	8f00 <targetfn>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff efbc 	blx	8f00 <targetfn>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff efb8 	blx	8f00 <targetfn>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff efb4 	blx	8f00 <targetfn>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff efb0 	blx	8f00 <targetfn>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff efac 	blx	8f00 <targetfn>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff efa8 	blx	8f00 <targetfn>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff efa4 	blx	8f00 <targetfn>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff efa0 	blx	8f00 <targetfn>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff ef9c 	blx	8f00 <targetfn>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff ef98 	blx	8f00 <targetfn>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff ef94 	blx	8f00 <targetfn>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff ef90 	blx	8f00 <targetfn>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff ef8c 	blx	8f00 <targetfn>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff ef88 	blx	8f00 <targetfn>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff ef84 	blx	8f00 <targetfn>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 e808 	blx	9010 <_start\+0x108>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f7ff ef7c 	blx	8f00 <targetfn>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+    9010:	eaffffba 	b	8f00 <targetfn>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-thumb.d b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-thumb.d
new file mode 100644
index 0000000..8cbd3e0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-thumb.d
@@ -0,0 +1,80 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <targetfn>:
+    8f00:	4770      	bx	lr
+    8f02:	bf00      	nop
+    8f04:	f3af 8000 	nop\.w
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff fff7 	bl	8f00 <targetfn>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff fff3 	bl	8f00 <targetfn>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff ffef 	bl	8f00 <targetfn>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff ffeb 	bl	8f00 <targetfn>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff ffe7 	bl	8f00 <targetfn>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff ffe3 	bl	8f00 <targetfn>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff ffdf 	bl	8f00 <targetfn>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff ffdb 	bl	8f00 <targetfn>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff ffd7 	bl	8f00 <targetfn>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff ffd3 	bl	8f00 <targetfn>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff ffcf 	bl	8f00 <targetfn>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff ffcb 	bl	8f00 <targetfn>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff ffc7 	bl	8f00 <targetfn>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff ffc3 	bl	8f00 <targetfn>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff ffbf 	bl	8f00 <targetfn>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff ffbb 	bl	8f00 <targetfn>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff ffb7 	bl	8f00 <targetfn>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff ffb3 	bl	8f00 <targetfn>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff ffaf 	bl	8f00 <targetfn>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff ffab 	bl	8f00 <targetfn>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff ffa7 	bl	8f00 <targetfn>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff ffa3 	bl	8f00 <targetfn>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff ff9f 	bl	8f00 <targetfn>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff ff9b 	bl	8f00 <targetfn>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff ff97 	bl	8f00 <targetfn>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff ff93 	bl	8f00 <targetfn>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff ff8f 	bl	8f00 <targetfn>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff ff8b 	bl	8f00 <targetfn>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff ff87 	bl	8f00 <targetfn>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff ff83 	bl	8f00 <targetfn>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 f807 	bl	9010 <_start\+0x108>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f7ff ff7b 	bl	8f00 <targetfn>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+    9010:	f7ff bf76 	b\.w	8f00 <targetfn>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel.s b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel.s
new file mode 100644
index 0000000..efbfb4b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel.s
@@ -0,0 +1,38 @@
+	.syntax unified
+	.cpu cortex-a8
+	.thumb
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+1:
+        add.w r0, r1, r2
+        blx.w targetfn
+        add.w r0, r1, r2
+        blx.w targetfn
+        add.w r0, r1, r2
+        blx.w targetfn
+        add.w r0, r1, r2
+        blx.w targetfn
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+        .align  3
+        .global _start
+        .thumb
+        .thumb_func
+        .type   _start, %function
+_start:
+	nop
+
+	bw2
+	bw2
+
+        bx      lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-blx.d b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-blx.d
new file mode 100644
index 0000000..4805256
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-blx.d
@@ -0,0 +1,79 @@
+
+.*:     file format .*
+
+
+Disassembly of section \.text:
+
+00008f00 <armfn>:
+    8f00:	e1a02413 	lsl	r2, r3, r4
+    8f04:	e12fff1e 	bx	lr
+
+00008f08 <_start>:
+    8f08:	bf00      	nop
+    8f0a:	eb01 0002 	add\.w	r0, r1, r2
+    8f0e:	f7ff eff8 	blx	8f00 <armfn>
+    8f12:	eb01 0002 	add\.w	r0, r1, r2
+    8f16:	f7ff eff4 	blx	8f00 <armfn>
+    8f1a:	eb01 0002 	add\.w	r0, r1, r2
+    8f1e:	f7ff eff0 	blx	8f00 <armfn>
+    8f22:	eb01 0002 	add\.w	r0, r1, r2
+    8f26:	f7ff efec 	blx	8f00 <armfn>
+    8f2a:	eb01 0002 	add\.w	r0, r1, r2
+    8f2e:	f7ff efe8 	blx	8f00 <armfn>
+    8f32:	eb01 0002 	add\.w	r0, r1, r2
+    8f36:	f7ff efe4 	blx	8f00 <armfn>
+    8f3a:	eb01 0002 	add\.w	r0, r1, r2
+    8f3e:	f7ff efe0 	blx	8f00 <armfn>
+    8f42:	eb01 0002 	add\.w	r0, r1, r2
+    8f46:	f7ff efdc 	blx	8f00 <armfn>
+    8f4a:	eb01 0002 	add\.w	r0, r1, r2
+    8f4e:	f7ff efd8 	blx	8f00 <armfn>
+    8f52:	eb01 0002 	add\.w	r0, r1, r2
+    8f56:	f7ff efd4 	blx	8f00 <armfn>
+    8f5a:	eb01 0002 	add\.w	r0, r1, r2
+    8f5e:	f7ff efd0 	blx	8f00 <armfn>
+    8f62:	eb01 0002 	add\.w	r0, r1, r2
+    8f66:	f7ff efcc 	blx	8f00 <armfn>
+    8f6a:	eb01 0002 	add\.w	r0, r1, r2
+    8f6e:	f7ff efc8 	blx	8f00 <armfn>
+    8f72:	eb01 0002 	add\.w	r0, r1, r2
+    8f76:	f7ff efc4 	blx	8f00 <armfn>
+    8f7a:	eb01 0002 	add\.w	r0, r1, r2
+    8f7e:	f7ff efc0 	blx	8f00 <armfn>
+    8f82:	eb01 0002 	add\.w	r0, r1, r2
+    8f86:	f7ff efbc 	blx	8f00 <armfn>
+    8f8a:	eb01 0002 	add\.w	r0, r1, r2
+    8f8e:	f7ff efb8 	blx	8f00 <armfn>
+    8f92:	eb01 0002 	add\.w	r0, r1, r2
+    8f96:	f7ff efb4 	blx	8f00 <armfn>
+    8f9a:	eb01 0002 	add\.w	r0, r1, r2
+    8f9e:	f7ff efb0 	blx	8f00 <armfn>
+    8fa2:	eb01 0002 	add\.w	r0, r1, r2
+    8fa6:	f7ff efac 	blx	8f00 <armfn>
+    8faa:	eb01 0002 	add\.w	r0, r1, r2
+    8fae:	f7ff efa8 	blx	8f00 <armfn>
+    8fb2:	eb01 0002 	add\.w	r0, r1, r2
+    8fb6:	f7ff efa4 	blx	8f00 <armfn>
+    8fba:	eb01 0002 	add\.w	r0, r1, r2
+    8fbe:	f7ff efa0 	blx	8f00 <armfn>
+    8fc2:	eb01 0002 	add\.w	r0, r1, r2
+    8fc6:	f7ff ef9c 	blx	8f00 <armfn>
+    8fca:	eb01 0002 	add\.w	r0, r1, r2
+    8fce:	f7ff ef98 	blx	8f00 <armfn>
+    8fd2:	eb01 0002 	add\.w	r0, r1, r2
+    8fd6:	f7ff ef94 	blx	8f00 <armfn>
+    8fda:	eb01 0002 	add\.w	r0, r1, r2
+    8fde:	f7ff ef90 	blx	8f00 <armfn>
+    8fe2:	eb01 0002 	add\.w	r0, r1, r2
+    8fe6:	f7ff ef8c 	blx	8f00 <armfn>
+    8fea:	eb01 0002 	add\.w	r0, r1, r2
+    8fee:	f7ff ef88 	blx	8f00 <armfn>
+    8ff2:	eb01 0002 	add\.w	r0, r1, r2
+    8ff6:	f7ff ef84 	blx	8f00 <armfn>
+    8ffa:	eb01 0002 	add\.w	r0, r1, r2
+    8ffe:	f000 e808 	blx	9010 <_start\+0x108>
+    9002:	eb01 0002 	add\.w	r0, r1, r2
+    9006:	f7ff ef7c 	blx	8f00 <armfn>
+    900a:	4770      	bx	lr
+    900c:	f3af 8000 	nop\.w
+    9010:	eaffffba 	b	8f00 <armfn>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-blx.s b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-blx.s
new file mode 100644
index 0000000..5d74024
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-fix-blx.s
@@ -0,0 +1,44 @@
+	.syntax unified
+	.cpu cortex-a8
+	.text
+
+	@ expansion 32 bytes
+        .macro bw1
+        add.w r0, r1, r2
+        blx.w armfn
+        add.w r0, r1, r2
+        blx.w armfn
+        add.w r0, r1, r2
+        blx.w armfn
+        add.w r0, r1, r2
+        blx.w armfn
+        .endm
+
+        @ expansion 128 bytes
+        .macro bw2
+        bw1
+        bw1
+        bw1
+        bw1
+        .endm
+
+	.arm
+        .align  2
+armfn:
+	mov	r2, r3, asl r4
+	bx	lr
+
+        .global _start
+
+	.thumb
+        .thumb_func
+	.align 3
+        .type   _start, %function
+_start:
+        nop
+
+	@ Trigger Cortex-A8 erratum workaround with blx instructions.
+        bw2
+        bw2
+
+        bx      lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-thumb-target.s b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-thumb-target.s
new file mode 100644
index 0000000..96c180f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/cortex-a8-thumb-target.s
@@ -0,0 +1,10 @@
+	.syntax unified
+	.cpu cortex-a8
+	.text
+	.thumb
+	.thumb_func
+	.align 3
+	.global targetfn
+	.type targetfn, %function
+targetfn:
+	bx lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/emit-relocs1-vxworks.d b/binutils-2.19/ld/testsuite/ld-arm/emit-relocs1-vxworks.d
new file mode 100644
index 0000000..6d84a4c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/emit-relocs1-vxworks.d
@@ -0,0 +1,12 @@
+#source: emit-relocs1.s
+#ld: -Ttext 0x10000 --defsym target=0xc000 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000:	e1a00000 	nop	.*
+ +10004:	e1a00000 	nop	.*
+ +10008:	e1a00000 	nop	.*
+ +1000c:	e1a00000 	nop	.*
+ +10010:	eaffeffa 	b	c000 <target>
+	+10010: R_ARM_PC24	target\+0xf+8
+ +10014:	eaffeffd 	b	c010 <target\+0x10>
+	+10014: R_ARM_PC24	target\+0x8
diff --git a/binutils-2.19/ld/testsuite/ld-arm/emit-relocs1.d b/binutils-2.19/ld/testsuite/ld-arm/emit-relocs1.d
new file mode 100644
index 0000000..191cb52
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/emit-relocs1.d
@@ -0,0 +1,12 @@
+#source: emit-relocs1.s
+#ld: -Ttext 0x10000 --defsym target=0xc000 -e0 --emit-relocs
+#objdump: -dr
+#...
+ +10000:	e1a00000 	nop	.*
+ +10004:	e1a00000 	nop	.*
+ +10008:	e1a00000 	nop	.*
+ +1000c:	e1a00000 	nop	.*
+ +10010:	eaffeffa 	b	c000 <target>
+	+10010: R_ARM_(JUMP|PC)24	target
+ +10014:	eaffeffd 	b	c010 <target\+0x10>
+	+10014: R_ARM_(JUMP|PC)24	target
diff --git a/binutils-2.19/ld/testsuite/ld-arm/emit-relocs1.s b/binutils-2.19/ld/testsuite/ld-arm/emit-relocs1.s
new file mode 100644
index 0000000..8971d4d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/emit-relocs1.s
@@ -0,0 +1,6 @@
+	nop
+	nop
+	nop
+	nop
+	b	target
+	b	target+16
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-arm-be8.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-arm-be8.d
new file mode 100644
index 0000000..cf3aa07
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-arm-be8.d
@@ -0,0 +1,15 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	000000eb 	bl	1008 <__bar_veneer>
+    1004:	00000000 	andeq	r0, r0, r0
+
+00001008 <__bar_veneer>:
+    1008:	04f01fe5 	ldr	pc, \[pc, #-4\]	; 100c <__bar_veneer\+0x4>
+    100c:	02001020 	.word	0x02001020
+Disassembly of section .foo:
+
+02001020 <bar>:
+ 2001020:	1eff2fe1 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-arm-pic-veneer.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-arm-pic-veneer.d
new file mode 100644
index 0000000..f5ff227
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-arm-pic-veneer.d
@@ -0,0 +1,17 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	eb000000 	bl	1008 <__bar_veneer>
+    1004:	00000000 	andeq	r0, r0, r0
+
+00001008 <__bar_veneer>:
+    1008:	e59fc000 	ldr	ip, \[pc, #0\]	; 1010 <__bar_veneer\+0x8>
+    100c:	e08ff00c 	add	pc, pc, ip
+    1010:	0200000c 	.word	0x0200000c
+    1014:	00000000 	.word	0x00000000
+Disassembly of section .foo:
+
+02001020 <bar>:
+ 2001020:	e12fff1e 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-arm.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-arm.d
new file mode 100644
index 0000000..7ee6d66
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-arm.d
@@ -0,0 +1,15 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	eb000000 	bl	1008 <__bar_veneer>
+    1004:	00000000 	andeq	r0, r0, r0
+
+00001008 <__bar_veneer>:
+    1008:	e51ff004 	ldr	pc, \[pc, #-4\]	; 100c <__bar_veneer\+0x4>
+    100c:	02001020 	.word	0x02001020
+Disassembly of section .foo:
+
+02001020 <bar>:
+ 2001020:	e12fff1e 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-arm.s b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-arm.s
new file mode 100644
index 0000000..00c1e48
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-arm.s
@@ -0,0 +1,20 @@
+@ Test to ensure that a ARM to ARM call exceeding 32Mb generates a stub.
+
+	.global _start
+	.syntax unified
+
+@ We will place the section .text at 0x1000.
+
+	.text
+
+_start:
+	bl bar
+
+@ We will place the section .foo at 0x2001020.
+
+	.section .foo, "xa"
+
+	.type bar, %function
+bar:
+	bx lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-thumb-blx-pic-veneer.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-thumb-blx-pic-veneer.d
new file mode 100644
index 0000000..45bc01c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-thumb-blx-pic-veneer.d
@@ -0,0 +1,17 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	eb000000 	bl	1008 <__bar_from_arm>
+    1004:	00000000 	andeq	r0, r0, r0
+
+00001008 <__bar_from_arm>:
+    1008:	e59fc004 	ldr	ip, \[pc, #4\]	; 1014 <__bar_from_arm\+0xc>
+    100c:	e08fc00c 	add	ip, pc, ip
+    1010:	e12fff1c 	bx	ip
+    1014:	02000001 	.word	0x02000001
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-thumb-blx.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-thumb-blx.d
new file mode 100644
index 0000000..993a028
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-thumb-blx.d
@@ -0,0 +1,15 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	eb000000 	bl	1008 <__bar_from_arm>
+    1004:	00000000 	andeq	r0, r0, r0
+
+00001008 <__bar_from_arm>:
+    1008:	e51ff004 	ldr	pc, \[pc, #-4\]	; 100c <__bar_from_arm\+0x4>
+    100c:	02001015 	.word	0x02001015
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-thumb-pic-veneer.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-thumb-pic-veneer.d
new file mode 100644
index 0000000..45bc01c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-thumb-pic-veneer.d
@@ -0,0 +1,17 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	eb000000 	bl	1008 <__bar_from_arm>
+    1004:	00000000 	andeq	r0, r0, r0
+
+00001008 <__bar_from_arm>:
+    1008:	e59fc004 	ldr	ip, \[pc, #4\]	; 1014 <__bar_from_arm\+0xc>
+    100c:	e08fc00c 	add	ip, pc, ip
+    1010:	e12fff1c 	bx	ip
+    1014:	02000001 	.word	0x02000001
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-thumb.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-thumb.d
new file mode 100644
index 0000000..8291be3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-thumb.d
@@ -0,0 +1,17 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	eb000000 	bl	1008 <__bar_from_arm>
+    1004:	00000000 	andeq	r0, r0, r0
+
+00001008 <__bar_from_arm>:
+    1008:	e59fc000 	ldr	ip, \[pc, #0\]	; 1010 <__bar_from_arm\+0x8>
+    100c:	e12fff1c 	bx	ip
+    1010:	02001015 	.word	0x02001015
+    1014:	00000000 	.word	0x00000000
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-thumb.s b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-thumb.s
new file mode 100644
index 0000000..c69f31c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-arm-thumb.s
@@ -0,0 +1,20 @@
+@ Test to ensure that a ARM to Thumb call exceeding 32Mb generates a stub.
+
+	.global _start
+	.global bar
+	.syntax unified
+
+@ We will place the section .text at 0x1000.
+
+	.text
+
+_start:
+	bl bar
+
+@ We will place the section .foo at 0x2001010.
+
+	.section .foo, "xa"
+	.thumb_func
+bar:
+	bx lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-group-limit.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-group-limit.d
new file mode 100644
index 0000000..204dcd8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-group-limit.d
@@ -0,0 +1,21 @@
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	eb000000 	bl	1008 <__bar_veneer>
+    1004:	00000000 	andeq	r0, r0, r0
+
+00001008 <__bar_veneer>:
+    1008:	e51ff004 	ldr	pc, \[pc, #-4\]	; 100c <__bar_veneer\+0x4>
+    100c:	02003020 	.word	0x02003020
+
+00001010 <myfunc>:
+	...
+ 2001010:	eb000802 	bl	2003020 <bar>
+
+Disassembly of section .far:
+
+02003020 <bar>:
+ 2003020:	e12fff1e 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-group-size2.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-group-size2.d
new file mode 100644
index 0000000..79306ee
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-group-size2.d
@@ -0,0 +1,51 @@
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	eb000000 	bl	1008 <__bar_from_arm>
+    1004:	eb000002 	bl	1014 <__bar2_veneer>
+00001008 <__bar_from_arm>:
+    1008:	e59fc000 	ldr	ip, \[pc, #0\]	; 1010 <__bar_from_arm\+0x8>
+    100c:	e12fff1c 	bx	ip
+    1010:	02003021 	.word	0x02003021
+00001014 <__bar2_veneer>:
+    1014:	e51ff004 	ldr	pc, \[pc, #-4\]	; 1018 <__bar2_veneer\+0x4>
+    1018:	02003024 	.word	0x02003024
+    101c:	00000000 	.word	0x00000000
+00001020 <myfunc>:
+    1020:	eb000008 	bl	1048 <__bar3_veneer>
+    1024:	eb000004 	bl	103c <__bar4_from_arm>
+    1028:	eb000000 	bl	1030 <__bar5_from_arm>
+    102c:	00000000 	andeq	r0, r0, r0
+00001030 <__bar5_from_arm>:
+    1030:	e59fc000 	ldr	ip, \[pc, #0\]	; 1038 <__bar5_from_arm\+0x8>
+    1034:	e12fff1c 	bx	ip
+    1038:	0200302f 	.word	0x0200302f
+0000103c <__bar4_from_arm>:
+    103c:	e59fc000 	ldr	ip, \[pc, #0\]	; 1044 <__bar4_from_arm\+0x8>
+    1040:	e12fff1c 	bx	ip
+    1044:	0200302d 	.word	0x0200302d
+00001048 <__bar3_veneer>:
+    1048:	e51ff004 	ldr	pc, \[pc, #-4\]	; 104c <__bar3_veneer\+0x4>
+    104c:	02003028 	.word	0x02003028
+	...
+
+Disassembly of section .foo:
+
+02003020 <bar>:
+ 2003020:	4770      	bx	lr
+	...
+
+02003024 <bar2>:
+ 2003024:	e12fff1e 	bx	lr
+
+02003028 <bar3>:
+ 2003028:	e12fff1e 	bx	lr
+
+0200302c <bar4>:
+ 200302c:	4770      	bx	lr
+
+0200302e <bar5>:
+ 200302e:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-group.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-group.d
new file mode 100644
index 0000000..10e983e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-group.d
@@ -0,0 +1,51 @@
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	eb00000c 	bl	1038 <__bar_from_arm>
+    1004:	eb00000e 	bl	1044 <__bar2_veneer>
+
+00001008 <myfunc>:
+    1008:	eb000008 	bl	1030 <__bar3_veneer>
+    100c:	eb000004 	bl	1024 <__bar4_from_arm>
+    1010:	eb000000 	bl	1018 <__bar5_from_arm>
+    1014:	00000000 	andeq	r0, r0, r0
+
+00001018 <__bar5_from_arm>:
+    1018:	e59fc000 	ldr	ip, \[pc, #0\]	; 1020 <__bar5_from_arm\+0x8>
+    101c:	e12fff1c 	bx	ip
+    1020:	0200302f 	.word	0x0200302f
+00001024 <__bar4_from_arm>:
+    1024:	e59fc000 	ldr	ip, \[pc, #0\]	; 102c <__bar4_from_arm\+0x8>
+    1028:	e12fff1c 	bx	ip
+    102c:	0200302d 	.word	0x0200302d
+00001030 <__bar3_veneer>:
+    1030:	e51ff004 	ldr	pc, \[pc, #-4\]	; 1034 <__bar3_veneer\+0x4>
+    1034:	02003028 	.word	0x02003028
+00001038 <__bar_from_arm>:
+    1038:	e59fc000 	ldr	ip, \[pc, #0\]	; 1040 <__bar_from_arm\+0x8>
+    103c:	e12fff1c 	bx	ip
+    1040:	02003021 	.word	0x02003021
+00001044 <__bar2_veneer>:
+    1044:	e51ff004 	ldr	pc, \[pc, #-4\]	; 1048 <__bar2_veneer\+0x4>
+    1048:	02003024 	.word	0x02003024
+	...
+Disassembly of section .foo:
+
+02003020 <bar>:
+ 2003020:	4770      	bx	lr
+	...
+
+02003024 <bar2>:
+ 2003024:	e12fff1e 	bx	lr
+
+02003028 <bar3>:
+ 2003028:	e12fff1e 	bx	lr
+
+0200302c <bar4>:
+ 200302c:	4770      	bx	lr
+
+0200302e <bar5>:
+ 200302e:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-group.s b/binutils-2.19/ld/testsuite/ld-arm/farcall-group.s
new file mode 100644
index 0000000..0ede36d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-group.s
@@ -0,0 +1,44 @@
+@ Test to ensure that ARM calls exceeding 32Mb generate stubs.
+
+	.global _start
+	.syntax unified
+
+@ We will place the section .text at 0x1000.
+
+	.text
+
+_start:
+	bl bar
+	bl bar2
+
+
+@ We will place the section .foo at 0x2003020.
+
+	.section .foo, "xa"
+
+	.global bar
+	.thumb_func
+bar:
+	bx lr
+
+	.arm
+	.global bar2
+	.type bar2, %function
+bar2:
+	bx lr
+
+	.global bar3
+	.type bar3, %function
+bar3:
+	bx lr
+
+	.global bar4
+	.thumb_func
+bar4:
+	bx lr
+
+	.global bar5
+	.type bar5, %function
+bar5:
+	bx lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-group2.s b/binutils-2.19/ld/testsuite/ld-arm/farcall-group2.s
new file mode 100644
index 0000000..774869f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-group2.s
@@ -0,0 +1,7 @@
+@ Test to ensure that ARM calls exceeding 32Mb generate stubs.
+
+	.text
+myfunc:
+	bl bar3
+	bl bar4
+	bl bar5
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-group3.s b/binutils-2.19/ld/testsuite/ld-arm/farcall-group3.s
new file mode 100644
index 0000000..ea2ce7f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-group3.s
@@ -0,0 +1,9 @@
+@ Test to ensure that ARM calls exceeding 32Mb generate stubs,
+@ and that stubs are correctly inserted between input sections
+@ when one contribution size exceeds the limit.
+
+	.text
+	.global bar
+	.global _start
+_start:
+	bl bar
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-group4.s b/binutils-2.19/ld/testsuite/ld-arm/farcall-group4.s
new file mode 100644
index 0000000..17f503b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-group4.s
@@ -0,0 +1,13 @@
+@ Test to ensure that ARM calls exceeding 32Mb generate stubs,
+@ and that a large input section forces stub insertion before its
+@ contribution.
+
+	.text
+myfunc:
+	.space 0x2000000
+	bl bar
+
+	.section .far, "xa"
+	.global bar
+bar:
+	bx lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-mix.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-mix.d
new file mode 100644
index 0000000..669a79b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-mix.d
@@ -0,0 +1,49 @@
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	eb000009 	bl	102c <__bar_from_arm>
+    1004:	eb00000b 	bl	1038 <__bar2_veneer>
+    1008:	eb000005 	bl	1024 <__bar3_veneer>
+    100c:	eb00000b 	bl	1040 <__bar4_from_arm>
+    1010:	eb000000 	bl	1018 <__bar5_from_arm>
+    1014:	00000000 	andeq	r0, r0, r0
+
+00001018 <__bar5_from_arm>:
+    1018:	e59fc000 	ldr	ip, \[pc, #0\]	; 1020 <__bar5_from_arm\+0x8>
+    101c:	e12fff1c 	bx	ip
+    1020:	0200202f 	.word	0x0200202f
+00001024 <__bar3_veneer>:
+    1024:	e51ff004 	ldr	pc, \[pc, #-4\]	; 1028 <__bar3_veneer\+0x4>
+    1028:	02002028 	.word	0x02002028
+0000102c <__bar_from_arm>:
+    102c:	e59fc000 	ldr	ip, \[pc, #0\]	; 1034 <__bar_from_arm\+0x8>
+    1030:	e12fff1c 	bx	ip
+    1034:	02002021 	.word	0x02002021
+00001038 <__bar2_veneer>:
+    1038:	e51ff004 	ldr	pc, \[pc, #-4\]	; 103c <__bar2_veneer\+0x4>
+    103c:	02002024 	.word	0x02002024
+00001040 <__bar4_from_arm>:
+    1040:	e59fc000 	ldr	ip, \[pc, #0\]	; 1048 <__bar4_from_arm\+0x8>
+    1044:	e12fff1c 	bx	ip
+    1048:	0200202d 	.word	0x0200202d
+	...
+Disassembly of section .foo:
+
+02002020 <bar>:
+ 2002020:	4770      	bx	lr
+	...
+
+02002024 <bar2>:
+ 2002024:	e12fff1e 	bx	lr
+
+02002028 <bar3>:
+ 2002028:	e12fff1e 	bx	lr
+
+0200202c <bar4>:
+ 200202c:	4770      	bx	lr
+
+0200202e <bar5>:
+ 200202e:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-mix.s b/binutils-2.19/ld/testsuite/ld-arm/farcall-mix.s
new file mode 100644
index 0000000..41b27f2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-mix.s
@@ -0,0 +1,46 @@
+@ Test to ensure that ARM calls exceeding 32Mb generate stubs.
+
+	.global _start
+	.syntax unified
+
+@ We will place the section .text at 0x1000.
+
+	.text
+
+_start:
+	bl bar
+	bl bar2
+	bl bar3
+	bl bar4
+	bl bar5
+
+@ We will place the section .foo at 0x2002020.
+
+	.section .foo, "xa"
+
+	.global bar
+	.thumb_func
+bar:
+	bx lr
+
+	.arm
+	.global bar2
+	.type bar2, %function
+bar2:
+	bx lr
+
+	.global bar3
+	.type bar3, %function
+bar3:
+	bx lr
+
+	.global bar4
+	.thumb_func
+bar4:
+	bx lr
+
+	.global bar5
+	.type bar5, %function
+bar5:
+	bx lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-mix2.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-mix2.d
new file mode 100644
index 0000000..2a08c11
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-mix2.d
@@ -0,0 +1,53 @@
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	eb000000 	bl	1008 <__bar_from_arm>
+    1004:	eb000002 	bl	1014 <__bar2_veneer>
+
+00001008 <__bar_from_arm>:
+    1008:	e59fc000 	ldr	ip, \[pc, #0\]	; 1010 <__bar_from_arm\+0x8>
+    100c:	e12fff1c 	bx	ip
+    1010:	02003021 	.word	0x02003021
+00001014 <__bar2_veneer>:
+    1014:	e51ff004 	ldr	pc, \[pc, #-4\]	; 1018 <__bar2_veneer\+0x4>
+    1018:	02003024 	.word	0x02003024
+    101c:	00000000 	.word	0x00000000
+Disassembly of section .mytext:
+
+00002000 <__bar5_from_arm-0x10>:
+    2000:	eb000008 	bl	2028 <__bar3_veneer>
+    2004:	eb000004 	bl	201c <__bar4_from_arm>
+    2008:	eb000000 	bl	2010 <__bar5_from_arm>
+    200c:	00000000 	andeq	r0, r0, r0
+00002010 <__bar5_from_arm>:
+    2010:	e59fc000 	ldr	ip, \[pc, #0\]	; 2018 <__bar5_from_arm\+0x8>
+    2014:	e12fff1c 	bx	ip
+    2018:	0200302f 	.word	0x0200302f
+0000201c <__bar4_from_arm>:
+    201c:	e59fc000 	ldr	ip, \[pc, #0\]	; 2024 <.*>
+    2020:	e12fff1c 	bx	ip
+    2024:	0200302d 	.word	0x0200302d
+00002028 <__bar3_veneer>:
+    2028:	e51ff004 	ldr	pc, \[pc, #-4\]	; 202c <__bar3_veneer\+0x4>
+    202c:	02003028 	.word	0x02003028
+	...
+Disassembly of section .foo:
+
+02003020 <bar>:
+ 2003020:	4770      	bx	lr
+	...
+
+02003024 <bar2>:
+ 2003024:	e12fff1e 	bx	lr
+
+02003028 <bar3>:
+ 2003028:	e12fff1e 	bx	lr
+
+0200302c <bar4>:
+ 200302c:	4770      	bx	lr
+
+0200302e <bar5>:
+ 200302e:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-mix2.s b/binutils-2.19/ld/testsuite/ld-arm/farcall-mix2.s
new file mode 100644
index 0000000..803e8d0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-mix2.s
@@ -0,0 +1,51 @@
+@ Test to ensure that ARM calls exceeding 32Mb generate stubs.
+
+	.global _start
+	.syntax unified
+
+@ We will place the section .text at 0x1000.
+
+	.text
+
+_start:
+	bl bar
+	bl bar2
+
+
+@ We will place the section .mytext at 0x2000.
+
+	.section .mytext, "xa"
+	bl bar3
+	bl bar4
+	bl bar5
+
+@ We will place the section .foo at 0x2003020.
+
+	.section .foo, "xa"
+
+	.global bar
+	.thumb_func
+bar:
+	bx lr
+
+	.arm
+	.global bar2
+	.type bar2, %function
+bar2:
+	bx lr
+
+	.global bar3
+	.type bar3, %function
+bar3:
+	bx lr
+
+	.global bar4
+	.thumb_func
+bar4:
+	bx lr
+
+	.global bar5
+	.type bar5, %function
+bar5:
+	bx lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-app-v5.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-app-v5.d
new file mode 100644
index 0000000..d34a686
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-app-v5.d
@@ -0,0 +1,85 @@
+
+tmpdir/farcall-mixed-app-v5:     file format elf32-(little|big)arm
+architecture: arm, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x.*
+
+Disassembly of section .plt:
+
+.* <.plt>:
+ .*:	e52de004 	push	{lr}		; \(str lr, \[sp, #-4\]!\)
+ .*:	e59fe004 	ldr	lr, \[pc, #4\]	; .* <_start-0x1c>
+ .*:	e08fe00e 	add	lr, pc, lr
+ .*:	e5bef008 	ldr	pc, \[lr, #8\]!
+ .*:	.*
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+
+Disassembly of section .text:
+
+.* <_start>:
+ .*:	e1a0c00d 	mov	ip, sp
+ .*:	e92dd800 	push	{fp, ip, lr, pc}
+ .*:	eb000008 	bl	.* <__app_func_veneer>
+ .*:	ebfffff8 	bl	.* <_start-0xc>
+ .*:	ebfffff4 	bl	.* <_start-0x18>
+ .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+ .*:	e12fff1e 	bx	lr
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+
+.* <app_tfunc_close>:
+ .*:	b500      	push	{lr}
+ .*:	f7ff efe2 	blx	.* <_start-0x18>
+ .*:	bd00      	pop	{pc}
+ .*:	4770      	bx	lr
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+
+.* <__app_func_veneer>:
+ .*:	e51ff004 	ldr	pc, \[pc, #-4\]	; .* <__app_func_veneer\+0x4>
+ .*:	02100000 	.word	0x02100000
+
+Disassembly of section .far_arm:
+
+.* <app_func>:
+ .*:	e1a0c00d 	mov	ip, sp
+ .*:	e92dd800 	push	{fp, ip, lr, pc}
+ .*:	eb00000a 	bl	.* <__lib_func1_veneer>
+ .*:	eb000007 	bl	.* <__lib_func2_veneer>
+ .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+ .*:	e12fff1e 	bx	lr
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+
+.* <app_func2>:
+ .*:	e12fff1e 	bx	lr
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+
+.* <__lib_func2_veneer>:
+ .*:	e51ff004 	ldr	pc, \[pc, #-4\]	; 2100034 <__lib_func2_veneer\+0x4>
+ .*:	00008218 	.word	0x00008218
+.* <__lib_func1_veneer>:
+ .*:	e51ff004 	ldr	pc, \[pc, #-4\]	; 210003c <__lib_func1_veneer\+0x4>
+ .*:	00008224 	.word	0x00008224
+
+Disassembly of section .far_thumb:
+
+.* <app_tfunc>:
+ .*:	b500      	push	{lr}
+ .*:	f000 e806 	blx	.* <__lib_func2_from_thumb>
+ .*:	bd00      	pop	{pc}
+ .*:	4770      	bx	lr
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+
+.* <__lib_func2_from_thumb>:
+ .*:	e51ff004 	ldr	pc, \[pc, #-4\]	; 2200014 <__lib_func2_from_thumb\+0x4>
+ .*:	00008218 	.word	0x00008218
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-app.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-app.d
new file mode 100644
index 0000000..fac7037
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-app.d
@@ -0,0 +1,90 @@
+
+tmpdir/farcall-mixed-app:     file format elf32-(little|big)arm
+architecture: arm, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x.*
+
+Disassembly of section .plt:
+
+.* <.plt>:
+ .*:	e52de004 	push	{lr}		; \(str lr, \[sp, #-4\]!\)
+ .*:	e59fe004 	ldr	lr, \[pc, #4\]	; .* <_start-0x2c>
+ .*:	e08fe00e 	add	lr, pc, lr
+ .*:	e5bef008 	ldr	pc, \[lr, #8\]!
+ .*:	.*
+ .*:	4778      	bx	pc
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+
+Disassembly of section .text:
+
+.* <_start>:
+ .*:	e1a0c00d 	mov	ip, sp
+ .*:	e92dd800 	push	{fp, ip, lr, pc}
+ .*:	eb000008 	bl	.* <__app_func_veneer>
+ .*:	ebfffff5 	bl	.* <_start-0x18>
+ .*:	ebfffff1 	bl	.* <_start-0x24>
+ .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+ .*:	e12fff1e 	bx	lr
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+
+.* <app_tfunc_close>:
+ .*:	b500      	push	{lr}
+ .*:	f7ff ffd9 	bl	8218 <_start-0x28>
+ .*:	bd00      	pop	{pc}
+ .*:	4770      	bx	lr
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+
+.* <__app_func_veneer>:
+ .*:	e51ff004 	ldr	pc, \[pc, #-4\]	; 8274 <__app_func_veneer\+0x4>
+ .*:	02100000 	.word	0x02100000
+
+Disassembly of section .far_arm:
+
+.* <app_func>:
+ .*:	e1a0c00d 	mov	ip, sp
+ .*:	e92dd800 	push	{fp, ip, lr, pc}
+ .*:	eb00000a 	bl	.* <__lib_func1_veneer>
+ .*:	eb000007 	bl	.* <__lib_func2_veneer>
+ .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+ .*:	e12fff1e 	bx	lr
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+
+.* <app_func2>:
+ .*:	e12fff1e 	bx	lr
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+
+.* <__lib_func2_veneer>:
+ .*:	e51ff004 	ldr	pc, \[pc, #-4\]	; 2100034 <__lib_func2_veneer\+0x4>
+ .*:	0000821c 	.word	0x0000821c
+.* <__lib_func1_veneer>:
+ .*:	e51ff004 	ldr	pc, \[pc, #-4\]	; 210003c <__lib_func1_veneer\+0x4>
+ .*:	00008228 	.word	0x00008228
+
+Disassembly of section .far_thumb:
+
+.* <app_tfunc>:
+ .*:	b500      	push	{lr}
+ .*:	f000 f805 	bl	.* <__lib_func2_from_thumb>
+ .*:	bd00      	pop	{pc}
+ .*:	4770      	bx	lr
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+
+.* <__lib_func2_from_thumb>:
+ .*:	4778      	bx	pc
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	e51ff004 	ldr	pc, \[pc, #-4\]	; 2200018 <__lib_func2_from_thumb\+0x8>
+ .*:	0000821c 	.word	0x0000821c
+ .*:	00000000 	.word	0x00000000
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-app.r b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-app.r
new file mode 100644
index 0000000..910a361
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-app.r
@@ -0,0 +1,10 @@
+
+tmpdir/farcall-mixed-app.*:     file format elf32-(little|big)arm
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+.* R_ARM_COPY        data_obj
+.* R_ARM_JUMP_SLOT   lib_func2
+.* R_ARM_JUMP_SLOT   lib_func1
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-app.s b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-app.s
new file mode 100644
index 0000000..e462ba3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-app.s
@@ -0,0 +1,61 @@
+	.text
+	.p2align 4
+	.globl _start
+_start:
+	mov	ip, sp
+	stmdb	sp!, {r11, ip, lr, pc}
+	bl	app_func
+	bl	lib_func1
+	bl	lib_func2
+	ldmia	sp, {r11, sp, lr}
+	bx lr
+
+	.p2align 4
+	.globl app_tfunc_close
+	.type app_tfunc_close,%function
+	.thumb_func
+	.code 16
+app_tfunc_close:
+	push	{lr}
+	bl	lib_func2
+	pop	{pc}
+	bx	lr
+
+@ We will place the section .far_arm at 0x2100000.
+	.section .far_arm, "xa"
+
+	.arm
+	.p2align 4
+	.globl app_func
+	.type app_func,%function
+app_func:
+	mov	ip, sp
+	stmdb	sp!, {r11, ip, lr, pc}
+	bl	lib_func1
+	bl	lib_func2
+	ldmia	sp, {r11, sp, lr}
+	bx lr
+
+	.arm
+	.p2align 4
+	.globl app_func2
+	.type app_func2,%function
+app_func2:
+	bx	lr
+
+@ We will place the section .far_thumb at 0x2200000.
+	.section .far_thumb, "xa"
+
+	.p2align 4
+	.globl app_tfunc
+	.type app_tfunc,%function
+	.thumb_func
+	.code 16
+app_tfunc:
+	push	{lr}
+	bl	lib_func2
+	pop	{pc}
+	bx	lr
+
+	.data
+	.long data_obj
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-app.sym b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-app.sym
new file mode 100644
index 0000000..a403cf1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-app.sym
@@ -0,0 +1,17 @@
+
+Symbol table for image:
+  Num Buc:    Value  Size   Type   Bind Vis      Ndx Name
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS _edata
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __bss_start__
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS _end
+   ..  ..: ........     4  OBJECT GLOBAL DEFAULT  12 data_obj
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __bss_end__
+   ..  ..: 0*[^0]*.*    0    FUNC GLOBAL DEFAULT UND lib_func1
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __exidx_start
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT  11 __data_start
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __end__
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __bss_start
+   ..  ..: .......0     0    FUNC GLOBAL DEFAULT  13 app_func2
+   ..  ..: 0*[^0]*.*    0    FUNC GLOBAL DEFAULT UND lib_func2
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS _bss_end__
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __exidx_end
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-lib.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-lib.d
new file mode 100644
index 0000000..18e7ef0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-lib.d
@@ -0,0 +1,92 @@
+tmpdir/farcall-mixed-lib.so:     file format elf32-(little|big)arm
+architecture: arm, flags 0x00000150:
+HAS_SYMS, DYNAMIC, D_PAGED
+start address 0x.*
+
+Disassembly of section .plt:
+
+.* <.plt>:
+ .*:	e52de004 	push	{lr}		; \(str lr, \[sp, #-4\]!\)
+ .*:	e59fe004 	ldr	lr, \[pc, #4\]	; .* <lib_func1-0x.*>
+ .*:	e08fe00e 	add	lr, pc, lr
+ .*:	e5bef008 	ldr	pc, \[lr, #8\]!
+ .*:	.*
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+
+Disassembly of section .text:
+
+.* <lib_func1>:
+ .*:	e1a0c00d 	mov	ip, sp
+ .*:	e92dd800 	push	{fp, ip, lr, pc}
+ .*:	ebfffff. 	bl	.* <lib_func1-0x..?>
+ .*:	ebfffff. 	bl	.* <lib_func1-0x..?>
+ .*:	ebfffff. 	bl	.* <lib_func1-0x..?>
+ .*:	ebfffff. 	bl	.* <lib_func1-0x..?>
+ .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+ .*:	e12fff1e 	bx	lr
+	...
+
+.* <lib_func2>:
+ .*:	f000 e80e 	blx	1000350 <__app_func_from_thumb>
+ .*:	f000 e818 	blx	1000368 <__app_func_weak_from_thumb>
+ .*:	f000 e810 	blx	100035c <__lib_func3_from_thumb>
+ .*:	f000 e81a 	blx	1000374 <__lib_func4_from_thumb>
+ .*:	4770      	bx	lr
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+
+.* <__app_func_from_thumb>:
+ .*:	e59fc000 	ldr	ip, \[pc, #0\]	; 1000358 <__app_func_from_thumb\+0x8>
+ .*:	e08ff00c 	add	pc, pc, ip
+ .*:	feffff84 	.word	0xfeffff84
+
+.* <__lib_func3_from_thumb>:
+ .*:	e59fc000 	ldr	ip, \[pc, #0\]	; 1000364 <__lib_func3_from_thumb\+0x8>
+ .*:	e08ff00c 	add	pc, pc, ip
+ .*:	feffff90 	.word	0xfeffff90
+
+.* <__app_func_weak_from_thumb>:
+ .*:	e59fc000 	ldr	ip, \[pc, #0\]	; 1000370 <__app_func_weak_from_thumb\+0x8>
+ .*:	e08ff00c 	add	pc, pc, ip
+ .*:	feffff78 	.word	0xfeffff78
+
+.* <__lib_func4_from_thumb>:
+ .*:	e59fc000 	ldr	ip, \[pc, #0\]	; 100037c <__lib_func4_from_thumb\+0x8>
+ .*:	e08ff00c 	add	pc, pc, ip
+ .*:	feffff84 	.word	0xfeffff84
+	...
+
+.* <lib_func3>:
+ .*:	f000 e80c 	blx	20003ac <__app_func_from_thumb>
+ .*:	f000 e804 	blx	20003a0 <__app_func_weak_from_thumb>
+ .*:	4770      	bx	lr
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+
+.* <__app_func_weak_from_thumb>:
+ .*:	e59fc000 	ldr	ip, \[pc, #0\]	; 20003a8 <__app_func_weak_from_thumb\+0x8>
+ .*:	e08ff00c 	add	pc, pc, ip
+ .*:	fdffff40 	.word	0xfdffff40
+
+.* <__app_func_from_thumb>:
+ .*:	e59fc000 	ldr	ip, \[pc, #0\]	; 20003b4 <__app_func_from_thumb\+0x8>
+ .*:	e08ff00c 	add	pc, pc, ip
+ .*:	fdffff28 	.word	0xfdffff28
+	...
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-lib.r b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-lib.r
new file mode 100644
index 0000000..a44f83b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-lib.r
@@ -0,0 +1,8 @@
+
+tmpdir/farcall-mixed-lib.so:     file format elf32-(little|big)arm
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+.* R_ARM_JUMP_SLOT   app_func2
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-lib1.s b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-lib1.s
new file mode 100644
index 0000000..f13e717
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-lib1.s
@@ -0,0 +1,35 @@
+@ Create a large shared library so that calls through PLT to an undef
+@ symbol require insertion of a long branch stub.
+@ Check also calls to an undef weak symbol.
+
+	.text
+	.arch armv5t
+
+	.p2align 4
+	.globl lib_func1
+	.type lib_func1, %function
+lib_func1:
+	mov	ip, sp
+	stmdb	sp!, {r11, ip, lr, pc}
+	bl	app_func
+	.weak	app_func_weak
+	bl	app_func_weak
+	bl	lib_func3
+	bl	lib_func4
+	ldmia	sp, {r11, sp, lr}
+	bx lr
+	.size lib_func1, . - lib_func1
+
+	.space 0x1000000
+	.p2align 4
+	.globl lib_func2
+	.type lib_func2, %function
+	.thumb_func
+	.code 16
+lib_func2:
+	bl	app_func
+	bl	app_func_weak
+	bl	lib_func3
+	bl	lib_func4
+	bx lr
+	.size lib_func2, . - lib_func2
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-lib2.s b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-lib2.s
new file mode 100644
index 0000000..cd5a71f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-mixed-lib2.s
@@ -0,0 +1,19 @@
+@ Create a large shared library so that calls through PLT to an undef
+@ symbol require insertion of a long branch stub.
+@ Check also calls to an undef weak symbol.
+
+	.text
+	.arch armv5t
+
+	.space 0x1000000
+	.p2align 4
+	.globl lib_func3
+	.type lib_func3, %function
+	.thumb_func
+	.code 16
+lib_func3:
+	bl	app_func
+	.weak	app_func_weak
+	bl	app_func_weak
+	bx lr
+	.size lib_func3, . - lib_func3
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-section.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-section.d
new file mode 100644
index 0000000..4e6d37d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-section.d
@@ -0,0 +1,5 @@
+#name: ARM-ARM farcall to symbol of type STT_SECTION
+#source: farcall-section.s
+#as:
+#ld: -Ttext 0x1000 --section-start .foo=0x2001014
+#error: .*\(.text\+0x0\): relocation truncated to fit: R_ARM_CALL against `.foo'
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-section.s b/binutils-2.19/ld/testsuite/ld-arm/farcall-section.s
new file mode 100644
index 0000000..31c9038
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-section.s
@@ -0,0 +1,20 @@
+@ Test to ensure that a ARM to ARM call exceeding 32Mb generates an error
+@ if the destination is of type STT_SECTION (eg non-global symbol)
+
+	.global _start
+	.syntax unified
+
+@ We will place the section .text at 0x1000.
+
+	.text
+
+_start:
+	bl bar
+
+@ We will place the section .foo at 0x2001020.
+
+	.section .foo, "xa"
+
+bar:
+	bx lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-be8.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-be8.d
new file mode 100644
index 0000000..c7d68e0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-be8.d
@@ -0,0 +1,19 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	00f0 02f8 	bl	1008 <__bar_from_thumb>
+    1004:	0000      	lsls	r0, r0, #0
+	\.\.\.
+
+00001008 <__bar_from_thumb>:
+    1008:	7847      	bx	pc
+    100a:	c046      	nop.*
+    100c:	04f01fe5 	ldr	pc, \[pc, #-4\]	; 1010 <__bar_from_thumb\+0x8>
+    1010:	02001014 	.word	0x02001014
+    1014:	00000000 	.word	0x00000000
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	1eff2fe1 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-blx-pic-veneer.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-blx-pic-veneer.d
new file mode 100644
index 0000000..b2ec457
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-blx-pic-veneer.d
@@ -0,0 +1,18 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f000 e802 	blx	1008 <__bar_from_thumb>
+    1004:	0000      	lsls	r0, r0, #0
+	\.\.\.
+
+00001008 <__bar_from_thumb>:
+    1008:	e59fc000 	ldr	ip, \[pc, #0\]	; 1010 <__bar_from_thumb\+0x8>
+    100c:	e08ff00c 	add	pc, pc, ip
+    1010:	02000000 	.word	0x02000000
+    1014:	00000000 	.word	0x00000000
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	e12fff1e 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-blx.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-blx.d
new file mode 100644
index 0000000..9f70091
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-blx.d
@@ -0,0 +1,16 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f000 e802 	blx	1008 <__bar_from_thumb>
+    1004:	0000      	lsls	r0, r0, #0
+	\.\.\.
+
+00001008 <__bar_from_thumb>:
+    1008:	e51ff004 	ldr	pc, \[pc, #-4\]	; 100c <__bar_from_thumb\+0x4>
+    100c:	02001014 	.word	0x02001014
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	e12fff1e 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d
new file mode 100644
index 0000000..6ac6e5c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d
@@ -0,0 +1,20 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f000 f802 	bl	1008 <__bar_from_thumb>
+    1004:	0000      	lsls	r0, r0, #0
+	...
+
+00001008 <__bar_from_thumb>:
+    1008:	4778      	bx	pc
+    100a:	46c0      	nop			\(mov r8, r8\)
+    100c:	e59fc000 	ldr	ip, \[pc, #0\]	; 1014 <__bar_from_thumb\+0xc>
+    1010:	e08cf00f 	add	pc, ip, pc
+    1014:	01fffffc 	.word	0x01fffffc
+
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	e12fff1e 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-short.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-short.d
new file mode 100644
index 0000000..ed235d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-short.d
@@ -0,0 +1,17 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f000 f802 	bl	1008 <__bar_from_thumb>
+    1004:	0000      	lsls	r0, r0, #0
+	\.\.\.
+
+00001008 <__bar_from_thumb>:
+    1008:	4778      	bx	pc
+    100a:	46c0      	nop			\(mov r8, r8\)
+    100c:	ea000400 	b	2014 <bar>
+Disassembly of section .foo:
+
+00002014 <bar>:
+    2014:	e12fff1e 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-short.s b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-short.s
new file mode 100644
index 0000000..1865380
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm-short.s
@@ -0,0 +1,21 @@
+@ Test to ensure that a Thumb to ARM call within 4Mb does not generate a stub.
+
+	.global _start
+	.syntax unified
+
+@ We will place the section .text at 0x1000.
+
+	.text
+	.thumb_func
+_start:
+	bl bar
+
+@ We will place the section .foo at 0x2014.
+
+	.section .foo, "xa"
+
+	.arm
+	.type bar, %function
+bar:
+	bx lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm.d
new file mode 100644
index 0000000..25ee1f4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm.d
@@ -0,0 +1,19 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f000 f802 	bl	1008 <__bar_from_thumb>
+    1004:	0000      	lsls	r0, r0, #0
+	\.\.\.
+
+00001008 <__bar_from_thumb>:
+    1008:	4778      	bx	pc
+    100a:	46c0      	nop			\(mov r8, r8\)
+    100c:	e51ff004 	ldr	pc, \[pc, #-4\]	; 1010 <__bar_from_thumb\+0x8>
+    1010:	02001014 	.word	0x02001014
+    1014:	00000000 	.word	0x00000000
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	e12fff1e 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm.s b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm.s
new file mode 100644
index 0000000..6fcdbfc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-arm.s
@@ -0,0 +1,21 @@
+@ Test to ensure that a Thumb to ARM call exceeding 4Mb generates a stub.
+
+	.global _start
+	.syntax unified
+
+@ We will place the section .text at 0x1000.
+
+	.text
+	.thumb_func
+_start:
+	bl bar
+
+@ We will place the section .foo at 0x2001014.
+
+	.section .foo, "xa"
+
+	.arm
+	.type bar, %function
+bar:
+	bx lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d
new file mode 100644
index 0000000..86c0ca0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d
@@ -0,0 +1,18 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f000 e802 	blx	1008 <__bar_veneer>
+    1004:	0000      	lsls	r0, r0, #0
+	\.\.\.
+
+00001008 <__bar_veneer>:
+    1008:	e59fc004 	ldr	ip, \[pc, #4\]	; 1014 <__bar_veneer\+0xc>
+    100c:	e08fc00c 	add	ip, pc, ip
+    1010:	e12fff1c 	bx	ip
+    1014:	02000001 	.word	0x02000001
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d
new file mode 100644
index 0000000..5e9ac5a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d
@@ -0,0 +1,16 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f000 e802 	blx	1008 <__bar_veneer>
+    1004:	0000      	lsls	r0, r0, #0
+	\.\.\.
+
+00001008 <__bar_veneer>:
+    1008:	e51ff004 	ldr	pc, \[pc, #-4\]	; 100c <__bar_veneer\+0x4>
+    100c:	02001015 	.word	0x02001015
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d
new file mode 100644
index 0000000..c96ea3f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d
@@ -0,0 +1,22 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f000 f802 	bl	1008 <__bar_veneer>
+    1004:	0000      	lsls	r0, r0, #0
+	...
+
+00001008 <__bar_veneer>:
+    1008:	b401      	push	{r0}
+    100a:	4802      	ldr	r0, \[pc, #8\]	\(1014 <__bar_veneer\+0xc>\)
+    100c:	46fc      	mov	ip, pc
+    100e:	4484      	add	ip, r0
+    1010:	bc01      	pop	{r0}
+    1012:	4760      	bx	ip
+    1014:	02000005 	.word	0x02000005
+
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb-m.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb-m.d
new file mode 100644
index 0000000..c98f00a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb-m.d
@@ -0,0 +1,21 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f000 f802 	bl	1008 <__bar_veneer>
+    1004:	0000      	lsls	r0, r0, #0
+	\.\.\.
+
+00001008 <__bar_veneer>:
+    1008:	b401      	push	{r0}
+    100a:	4802      	ldr	r0, \[pc, #8\]	\(1014 <__bar_veneer\+0xc>\)
+    100c:	4684      	mov	ip, r0
+    100e:	bc01      	pop	{r0}
+    1010:	4760      	bx	ip
+    1012:	bf00      	nop
+    1014:	02001015 	.word	0x02001015
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d
new file mode 100644
index 0000000..96549a5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d
@@ -0,0 +1,22 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f000 f802 	bl	1008 <__bar_veneer>
+    1004:	0000      	lsls	r0, r0, #0
+	...
+
+00001008 <__bar_veneer>:
+    1008:	4778      	bx	pc
+    100a:	46c0      	nop			\(mov r8, r8\)
+    100c:	e59fc004 	ldr	ip, \[pc, #4\]	; 1018 <__bar_veneer\+0x10>
+    1010:	e08fc00c 	add	ip, pc, ip
+    1014:	e12fff1c 	bx	ip
+    1018:	01fffffd 	.word	0x01fffffd
+    101c:	00000000 	.word	0x00000000
+
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb.d b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb.d
new file mode 100644
index 0000000..e4a96ea
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb.d
@@ -0,0 +1,19 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f000 f802 	bl	1008 <__bar_veneer>
+    1004:	0000      	lsls	r0, r0, #0
+	\.\.\.
+
+00001008 <__bar_veneer>:
+    1008:	4778      	bx	pc
+    100a:	46c0      	nop			\(mov r8, r8\)
+    100c:	e59fc000 	ldr	ip, \[pc, #0\]	; 1014 <__bar_veneer\+0xc>
+    1010:	e12fff1c 	bx	ip
+    1014:	02001015 	.word	0x02001015
+Disassembly of section .foo:
+
+02001014 <bar>:
+ 2001014:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb.s b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb.s
new file mode 100644
index 0000000..650b1a6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/farcall-thumb-thumb.s
@@ -0,0 +1,19 @@
+@ Test to ensure that a Thumb to Thumb call exceeding 4Mb generates a stub.
+
+	.global _start
+	.syntax unified
+
+@ We will place the section .text at 0x1000.
+
+	.text
+	.thumb_func
+_start:
+	bl bar
+
+@ We will place the section .foo at 0x02001014.
+
+	.section .foo, "xa"
+	.thumb_func
+bar:
+	bx lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/gc-unwind.d b/binutils-2.19/ld/testsuite/ld-arm/gc-unwind.d
new file mode 100644
index 0000000..fbb7911
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/gc-unwind.d
@@ -0,0 +1,5 @@
+
+.*:     file format.*
+
+Contents of section .data:
+ [^ ]* 22222222                            .*
diff --git a/binutils-2.19/ld/testsuite/ld-arm/gc-unwind.s b/binutils-2.19/ld/testsuite/ld-arm/gc-unwind.s
new file mode 100644
index 0000000..c5326c2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/gc-unwind.s
@@ -0,0 +1,38 @@
+@ Test -gc-sections and unwinding tables.  .data.eh should be pulled in
+@ via the EH tables, .data.foo should not.
+.text
+.global _start
+.fnstart
+_start:
+bx lr
+.personality my_pr
+.handlerdata
+.word 0
+.fnend
+
+.section .data.foo
+my_foo:
+.word 0x11111111
+
+.section .text.foo
+.fnstart
+foo:
+bx lr
+.personality my_pr
+.handlerdata
+.word my_foo
+.fnend
+
+.section .data.eh
+my_eh:
+.word 0x22222222
+
+.section .text.eh
+.fnstart
+my_pr:
+bx lr
+.personality my_pr
+.handlerdata
+.word my_eh
+.fnend
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/group-relocs-alu-bad.d b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-alu-bad.d
new file mode 100644
index 0000000..0346db1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-alu-bad.d
@@ -0,0 +1,4 @@
+#name: ALU group relocations failure test
+#source: group-relocs-alu-bad.s
+#ld: -Ttext 0x8000 --section-start foo=0x9010
+#error: Overflow whilst splitting 0x1010 for group relocation
diff --git a/binutils-2.19/ld/testsuite/ld-arm/group-relocs-alu-bad.s b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-alu-bad.s
new file mode 100644
index 0000000..e644669
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-alu-bad.s
@@ -0,0 +1,20 @@
+@ Test intended to fail for ALU group relocations.
+@
+@ Beware when editing this file: it is carefully crafted so that
+@ a specific PC-relative offset arises.
+
+@ We will place .text at 0x8000.
+
+	.text
+	.globl _start
+
+_start:
+	add r0, r0, #:pc_g0:(bar)
+
+@ We will place the section foo at 0x9004.
+
+	.section foo
+
+bar:
+	mov r0, #0
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldc-bad.d b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldc-bad.d
new file mode 100644
index 0000000..d4bfb2d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldc-bad.d
@@ -0,0 +1,4 @@
+#name: LDC group relocations failure test
+#source: group-relocs-ldc-bad.s
+#ld: -Ttext 0x8000 --section-start foo=0x118400
+#error: Overflow whilst splitting 0x110400 for group relocation
diff --git a/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldc-bad.s b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldc-bad.s
new file mode 100644
index 0000000..611255b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldc-bad.s
@@ -0,0 +1,19 @@
+@ Test intended to fail for LDC group relocations.
+
+@ We will place .text at 0x8000.
+
+	.text
+	.globl _start
+
+_start:
+	add	r0, r0, #:pc_g0_nc:(bar)
+	ldc	0, c0, [r0, #:pc_g1:(bar + 4)]
+
+@ We will place the section foo at 0x118400.
+@ (The relocations above would be OK if it were at 0x118200, for example.)
+
+	.section foo
+
+bar:
+	mov r0, #0
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldr-bad.d b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldr-bad.d
new file mode 100644
index 0000000..04586af
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldr-bad.d
@@ -0,0 +1,4 @@
+#name: LDR group relocations failure test
+#source: group-relocs-ldr-bad.s
+#ld: -Ttext 0x8000 --section-start foo=0x8001000
+#error: .*Overflow whilst splitting 0x8001000 for group relocation.*
diff --git a/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldr-bad.s b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldr-bad.s
new file mode 100644
index 0000000..6ab4f3c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldr-bad.s
@@ -0,0 +1,18 @@
+@ Test intended to fail for LDR group relocations.
+
+@ We will place .text at 0x8000.
+
+	.text
+	.globl _start
+
+_start:
+	add	r0, r0, #:sb_g0_nc:(bar)
+	ldr	r1, [r0, #:sb_g1:(bar)]
+
+@ We will place the section foo at 0x8001000.
+
+	.section foo
+
+bar:
+	mov r0, #0
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldrs-bad.d b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldrs-bad.d
new file mode 100644
index 0000000..0520184
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldrs-bad.d
@@ -0,0 +1,4 @@
+#name: LDRS group relocations failure test
+#source: group-relocs-ldrs-bad.s
+#ld: -Ttext 0x8000 --section-start foo=0x8000100
+#error: Overflow whilst splitting 0x8000100 for group relocation
diff --git a/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldrs-bad.s b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldrs-bad.s
new file mode 100644
index 0000000..4480d4a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/group-relocs-ldrs-bad.s
@@ -0,0 +1,17 @@
+@ Test intended to fail for LDRS group relocations.
+
+@ We will place .text at 0x8000.
+
+	.text
+	.globl _start
+
+_start:
+	add	r0, r0, #:sb_g0_nc:(bar)
+	ldrd	r2, [r0, #:sb_g1:(bar)]
+
+@ We will place the section foo at 0x8000100.
+
+	.section foo
+
+bar:
+	mov r0, #0
diff --git a/binutils-2.19/ld/testsuite/ld-arm/group-relocs.d b/binutils-2.19/ld/testsuite/ld-arm/group-relocs.d
new file mode 100644
index 0000000..d1fdc7d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/group-relocs.d
@@ -0,0 +1,69 @@
+
+tmpdir/group-relocs:     file format elf32-(little|big)arm
+
+Disassembly of section .text:
+
+00008000 <_start>:
+    8000:	e28f00bc 	add	r0, pc, #188	; 0xbc
+    8004:	e28f0c6e 	add	r0, pc, #28160	; 0x6e00
+    8008:	e28000ec 	add	r0, r0, #236	; 0xec
+    800c:	e28f08ff 	add	r0, pc, #16711680	; 0xff0000
+    8010:	e2800c6e 	add	r0, r0, #28160	; 0x6e00
+    8014:	e28000e4 	add	r0, r0, #228	; 0xe4
+    8018:	e2800000 	add	r0, r0, #0	; 0x0
+    801c:	e28f0cee 	add	r0, pc, #60928	; 0xee00
+    8020:	e28000f0 	add	r0, r0, #240	; 0xf0
+    8024:	e28008ff 	add	r0, r0, #16711680	; 0xff0000
+    8028:	e2800cee 	add	r0, r0, #60928	; 0xee00
+    802c:	e28000f0 	add	r0, r0, #240	; 0xf0
+    8030:	e2800c6e 	add	r0, r0, #28160	; 0x6e00
+    8034:	e59010c0 	ldr	r1, \[r0, #192\]
+    8038:	e28008ff 	add	r0, r0, #16711680	; 0xff0000
+    803c:	e2800c6e 	add	r0, r0, #28160	; 0x6e00
+    8040:	e59010b8 	ldr	r1, \[r0, #184\]
+    8044:	e5901000 	ldr	r1, \[r0\]
+    8048:	e2800cee 	add	r0, r0, #60928	; 0xee00
+    804c:	e59010f0 	ldr	r1, \[r0, #240\]
+    8050:	e28008ff 	add	r0, r0, #16711680	; 0xff0000
+    8054:	e2800cee 	add	r0, r0, #60928	; 0xee00
+    8058:	e59010f0 	ldr	r1, \[r0, #240\]
+    805c:	e1c026d0 	ldrd	r2, \[r0, #96\]
+    8060:	e2800c6e 	add	r0, r0, #28160	; 0x6e00
+    8064:	e1c029d0 	ldrd	r2, \[r0, #144\]
+    8068:	e28008ff 	add	r0, r0, #16711680	; 0xff0000
+    806c:	e2800c6e 	add	r0, r0, #28160	; 0x6e00
+    8070:	e1c028d8 	ldrd	r2, \[r0, #136\]
+    8074:	e1c020d0 	ldrd	r2, \[r0\]
+    8078:	e2800cee 	add	r0, r0, #60928	; 0xee00
+    807c:	e1c02fd0 	ldrd	r2, \[r0, #240\]
+    8080:	e28008ff 	add	r0, r0, #16711680	; 0xff0000
+    8084:	e2800cee 	add	r0, r0, #60928	; 0xee00
+    8088:	e1c02fd0 	ldrd	r2, \[r0, #240\]
+    808c:	ed90000c 	ldc	0, cr0, \[r0, #48\]
+    8090:	e2800c6e 	add	r0, r0, #28160	; 0x6e00
+    8094:	ed900018 	ldc	0, cr0, \[r0, #96\]
+    8098:	e28008ff 	add	r0, r0, #16711680	; 0xff0000
+    809c:	e2800c6e 	add	r0, r0, #28160	; 0x6e00
+    80a0:	ed900016 	ldc	0, cr0, \[r0, #88\]
+    80a4:	ed900000 	ldc	0, cr0, \[r0\]
+    80a8:	e2800cee 	add	r0, r0, #60928	; 0xee00
+    80ac:	ed90003c 	ldc	0, cr0, \[r0, #240\]
+    80b0:	e28008ff 	add	r0, r0, #16711680	; 0xff0000
+    80b4:	e2800cee 	add	r0, r0, #60928	; 0xee00
+    80b8:	ed90003c 	ldc	0, cr0, \[r0, #240\]
+
+000080bc <one_group_needed_alu_pc>:
+    80bc:	e3a00000 	mov	r0, #0	; 0x0
+Disassembly of section zero:
+
+00000000 <one_group_needed_alu_sb>:
+   0:	e3a00000 	mov	r0, #0	; 0x0
+Disassembly of section alpha:
+
+0000eef0 <two_groups_needed_alu_pc>:
+    eef0:	e3a00000 	mov	r0, #0	; 0x0
+Disassembly of section beta:
+
+00ffeef0 <three_groups_needed_alu_pc>:
+  ffeef0:	e3a00000 	mov	r0, #0	; 0x0
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-arm/group-relocs.s b/binutils-2.19/ld/testsuite/ld-arm/group-relocs.s
new file mode 100644
index 0000000..da1a150
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/group-relocs.s
@@ -0,0 +1,156 @@
+@ Tests for group relocations.
+@
+@ Beware when editing this file: it is carefully crafted so that
+@ specific PC- and SB-relative offsets arise.
+@
+@ Note that the gas tests have already checked that group relocations are
+@ handled in the same way for local and external symbols.
+
+@ We will place .text at 0x8000.
+
+	.text
+	.globl _start
+
+_start:
+	@ ALU, PC-relative
+
+	@ Instructions start at .text + 0x0
+	add	r0, r15, #:pc_g0:(one_group_needed_alu_pc)
+
+	@ Instructions start at .text + 0x4
+	add	r0, r15, #:pc_g0_nc:(two_groups_needed_alu_pc)
+	add	r0, r0, #:pc_g1:(two_groups_needed_alu_pc + 4)
+
+	@ Instructions start at .text + 0xc
+	add	r0, r15, #:pc_g0_nc:(three_groups_needed_alu_pc)
+	add	r0, r0, #:pc_g1_nc:(three_groups_needed_alu_pc + 4)
+	add	r0, r0, #:pc_g2:(three_groups_needed_alu_pc + 8)
+
+	@ ALU, SB-relative
+
+	add	r0, r0, #:sb_g0:(one_group_needed_alu_sb)
+
+	add	r0, r15, #:sb_g0_nc:(two_groups_needed_alu_sb)
+	add	r0, r0, #:sb_g1:(two_groups_needed_alu_sb)
+
+	add	r0, r0, #:sb_g0_nc:(three_groups_needed_alu_sb)
+	add	r0, r0, #:sb_g1_nc:(three_groups_needed_alu_sb)
+	add	r0, r0, #:sb_g2:(three_groups_needed_alu_sb)
+
+	@ LDR, PC-relative
+
+	@ Instructions start at .text + 0x30
+	add	r0, r0, #:pc_g0_nc:(two_groups_needed_ldr_pc)
+	ldr	r1, [r0, #:pc_g1:(two_groups_needed_ldr_pc + 4)]
+
+	@ Instructions start at .text + 0x38
+	add	r0, r0, #:pc_g0_nc:(three_groups_needed_ldr_pc)
+	add	r0, r0, #:pc_g1_nc:(three_groups_needed_ldr_pc + 4)
+	ldr	r1, [r0, #:pc_g2:(three_groups_needed_ldr_pc + 8)]
+
+	@ LDR, SB-relative
+
+	ldr	r1, [r0, #:sb_g0:(one_group_needed_ldr_sb)]
+
+	add	r0, r0, #:sb_g0_nc:(two_groups_needed_ldr_sb)
+	ldr	r1, [r0, #:sb_g1:(two_groups_needed_ldr_sb)]
+
+	add	r0, r0, #:sb_g0_nc:(three_groups_needed_ldr_sb)
+	add	r0, r0, #:sb_g1_nc:(three_groups_needed_ldr_sb)
+	ldr	r1, [r0, #:sb_g2:(three_groups_needed_ldr_sb)]
+
+	@ LDRS, PC-relative
+
+	@ Instructions start at .text + 0x5c
+	ldrd	r2, [r0, #:pc_g0:(one_group_needed_ldrs_pc)]
+
+	@ Instructions start at .text + 0x60
+	add	r0, r0, #:pc_g0_nc:(two_groups_needed_ldrs_pc)
+	ldrd	r2, [r0, #:pc_g1:(two_groups_needed_ldrs_pc + 4)]
+
+	@ Instructions start at .text + 0x68
+	add	r0, r0, #:pc_g0_nc:(three_groups_needed_ldrs_pc)
+	add	r0, r0, #:pc_g1_nc:(three_groups_needed_ldrs_pc + 4)
+	ldrd	r2, [r0, #:pc_g2:(three_groups_needed_ldrs_pc + 8)]
+
+	@ LDRS, SB-relative
+
+	ldrd	r2, [r0, #:sb_g0:(one_group_needed_ldrs_sb)]
+
+	add	r0, r0, #:sb_g0_nc:(two_groups_needed_ldrs_sb)
+	ldrd	r2, [r0, #:sb_g1:(two_groups_needed_ldrs_sb)]
+
+	add	r0, r0, #:sb_g0_nc:(three_groups_needed_ldrs_sb)
+	add	r0, r0, #:sb_g1_nc:(three_groups_needed_ldrs_sb)
+	ldrd	r2, [r0, #:sb_g2:(three_groups_needed_ldrs_sb)]
+
+	@ LDC, PC-relative
+
+	@ Instructions start at .text + 0x8c
+	ldc	0, c0, [r0, #:pc_g0:(one_group_needed_ldc_pc)]
+
+	@ Instructions start at .text + 0x90
+	add	r0, r0, #:pc_g0_nc:(two_groups_needed_ldc_pc)
+	ldc	0, c0, [r0, #:pc_g1:(two_groups_needed_ldc_pc + 4)]
+
+	@ Instructions start at .text + 0x98
+	add	r0, r0, #:pc_g0_nc:(three_groups_needed_ldc_pc)
+	add	r0, r0, #:pc_g1_nc:(three_groups_needed_ldc_pc + 4)
+	ldc	0, c0, [r0, #:pc_g2:(three_groups_needed_ldc_pc + 8)]
+
+	@ LDC, SB-relative
+
+	ldc	0, c0, [r0, #:sb_g0:(one_group_needed_ldc_sb)]
+
+	add	r0, r0, #:sb_g0_nc:(two_groups_needed_ldc_sb)
+	ldc	0, c0, [r0, #:sb_g1:(two_groups_needed_ldc_sb)]
+
+	add	r0, r0, #:sb_g0_nc:(three_groups_needed_ldc_sb)
+	add	r0, r0, #:sb_g1_nc:(three_groups_needed_ldc_sb)
+	ldc	0, c0, [r0, #:sb_g2:(three_groups_needed_ldc_sb)]
+
+@ This point in the file is .text + 0xbc.
+
+one_group_needed_alu_pc:
+one_group_needed_ldrs_pc:
+one_group_needed_ldc_pc:
+	mov	r0, #0
+
+@ We will place the section zero at 0x0.
+
+	.section zero
+
+one_group_needed_alu_sb:
+one_group_needed_ldr_sb:
+one_group_needed_ldrs_sb:
+one_group_needed_ldc_sb:
+	mov	r0, #0
+
+@ We will place the section alpha at 0xeef0.
+
+	.section alpha
+
+two_groups_needed_alu_sb:
+two_groups_needed_ldr_sb:
+two_groups_needed_ldrs_sb:
+two_groups_needed_ldc_sb:
+two_groups_needed_alu_pc:
+two_groups_needed_ldr_pc:
+two_groups_needed_ldrs_pc:
+two_groups_needed_ldc_pc:
+	mov	r0, #0
+
+@ We will place the section beta at 0xffeef0.
+
+	.section beta
+
+three_groups_needed_alu_sb:
+three_groups_needed_ldr_sb:
+three_groups_needed_ldrs_sb:
+three_groups_needed_ldc_sb:
+three_groups_needed_alu_pc:
+three_groups_needed_ldr_pc:
+three_groups_needed_ldrs_pc:
+three_groups_needed_ldc_pc:
+	mov	r0, #0
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/jump19.d b/binutils-2.19/ld/testsuite/ld-arm/jump19.d
new file mode 100644
index 0000000..303477f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/jump19.d
@@ -0,0 +1,12 @@
+
+.*jump19:     file format elf32-(big|little)arm
+
+Disassembly of section .text:
+
+00008000 <_start>:
+    8000:	4280      	cmp	r0, r0
+    8002:	f010 8000 	beq.w	18006 <bar>
+	...
+
+00018006 <bar>:
+   18006:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/jump19.s b/binutils-2.19/ld/testsuite/ld-arm/jump19.s
new file mode 100644
index 0000000..1e3ddf0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/jump19.s
@@ -0,0 +1,12 @@
+@ Test the Thumb-2 JUMP19 relocation.
+
+	.syntax unified
+	.thumb
+	.global _start
+_start:
+	cmp	r0, r0
+	beq.w   bar
+	.space 65536
+	.weak bar
+bar:
+	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/mixed-app-v5.d b/binutils-2.19/ld/testsuite/ld-arm/mixed-app-v5.d
new file mode 100644
index 0000000..88317d2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/mixed-app-v5.d
@@ -0,0 +1,56 @@
+
+tmpdir/mixed-app-v5:     file format elf32-(little|big)arm
+architecture: arm, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x.*
+
+Disassembly of section .plt:
+
+.* <.plt>:
+ .*:	e52de004 	push	{lr}		; \(str lr, \[sp, #-4\]!\)
+ .*:	e59fe004 	ldr	lr, \[pc, #4\]	; .* <_start-0x1c>
+ .*:	e08fe00e 	add	lr, pc, lr
+ .*:	e5bef008 	ldr	pc, \[lr, #8\]!
+ .*:	.*
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+Disassembly of section .text:
+
+.* <_start>:
+ .*:	e1a0c00d 	mov	ip, sp
+ .*:	e92dd800 	push	{fp, ip, lr, pc}
+ .*:	eb000004 	bl	.* <app_func>
+ .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+ .*:	e12fff1e 	bx	lr
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+
+.* <app_func>:
+ .*:	e1a0c00d 	mov	ip, sp
+ .*:	e92dd800 	push	{fp, ip, lr, pc}
+ .*:	ebfffff. 	bl	.*
+ .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+ .*:	e12fff1e 	bx	lr
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+
+.* <app_func2>:
+ .*:	e12fff1e 	bx	lr
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+
+.* <app_tfunc>:
+ .*:	b500      	push	{lr}
+ .*:	f7ff efc. 	blx	.* <_start-0x..>
+ .*:	bd00      	pop	{pc}
+ .*:	4770      	bx	lr
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
diff --git a/binutils-2.19/ld/testsuite/ld-arm/mixed-app.d b/binutils-2.19/ld/testsuite/ld-arm/mixed-app.d
new file mode 100644
index 0000000..a3679dd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/mixed-app.d
@@ -0,0 +1,58 @@
+
+tmpdir/mixed-app:     file format elf32-(little|big)arm
+architecture: arm, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x.*
+
+Disassembly of section .plt:
+
+.* <.plt>:
+ .*:	e52de004 	push	{lr}		; \(str lr, \[sp, #-4\]!\)
+ .*:	e59fe004 	ldr	lr, \[pc, #4\]	; .* <_start-0x2c>
+ .*:	e08fe00e 	add	lr, pc, lr
+ .*:	e5bef008 	ldr	pc, \[lr, #8\]!
+ .*:	.*
+ .*:	4778      	bx	pc
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+Disassembly of section .text:
+
+.* <_start>:
+ .*:	e1a0c00d 	mov	ip, sp
+ .*:	e92dd800 	push	{fp, ip, lr, pc}
+ .*:	eb000004 	bl	.* <app_func>
+ .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+ .*:	e12fff1e 	bx	lr
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+
+.* <app_func>:
+ .*:	e1a0c00d 	mov	ip, sp
+ .*:	e92dd800 	push	{fp, ip, lr, pc}
+ .*:	ebffff.. 	bl	.*
+ .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+ .*:	e12fff1e 	bx	lr
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+
+.* <app_func2>:
+ .*:	e12fff1e 	bx	lr
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+
+.* <app_tfunc>:
+ .*:	b500      	push	{lr}
+ .*:	f7ff ffc. 	bl	.* <_start-0x..>
+ .*:	bd00      	pop	{pc}
+ .*:	4770      	bx	lr
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
diff --git a/binutils-2.19/ld/testsuite/ld-arm/mixed-app.r b/binutils-2.19/ld/testsuite/ld-arm/mixed-app.r
new file mode 100644
index 0000000..648e92f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/mixed-app.r
@@ -0,0 +1,10 @@
+
+tmpdir/mixed-app.*:     file format elf32-(little|big)arm
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+.* R_ARM_COPY        data_obj
+.* R_ARM_JUMP_SLOT   lib_func2
+.* R_ARM_JUMP_SLOT   lib_func1
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/mixed-app.s b/binutils-2.19/ld/testsuite/ld-arm/mixed-app.s
new file mode 100644
index 0000000..ce82487
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/mixed-app.s
@@ -0,0 +1,39 @@
+	.text
+	.p2align 4
+	.globl _start
+_start:
+	mov	ip, sp
+	stmdb	sp!, {r11, ip, lr, pc}
+	bl	app_func
+	ldmia	sp, {r11, sp, lr}
+	bx lr
+
+	.p2align 4
+	.globl app_func
+	.type app_func,%function
+app_func:
+	mov	ip, sp
+	stmdb	sp!, {r11, ip, lr, pc}
+	bl	lib_func1
+	ldmia	sp, {r11, sp, lr}
+	bx lr
+
+	.p2align 4
+	.globl app_func2
+	.type app_func2,%function
+app_func2:
+	bx	lr
+
+	.p2align 4
+	.globl app_tfunc
+	.type app_tfunc,%function
+	.thumb_func
+	.code 16
+app_tfunc:
+	push	{lr}
+	bl	lib_func2
+	pop	{pc}
+	bx	lr
+
+	.data
+	.long data_obj
diff --git a/binutils-2.19/ld/testsuite/ld-arm/mixed-app.sym b/binutils-2.19/ld/testsuite/ld-arm/mixed-app.sym
new file mode 100644
index 0000000..a507681
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/mixed-app.sym
@@ -0,0 +1,17 @@
+
+Symbol table for image:
+  Num Buc:    Value  Size   Type   Bind Vis      Ndx Name
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS _edata
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __bss_start__
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS _end
+   ..  ..: ........     4  OBJECT GLOBAL DEFAULT  12 data_obj
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __bss_end__
+   ..  ..: 0*[^0]*.*    0    FUNC GLOBAL DEFAULT UND lib_func1
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __exidx_start
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT  11 __data_start
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __end__
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __bss_start
+   ..  ..: .......0     0    FUNC GLOBAL DEFAULT   8 app_func2
+   ..  ..: 0*[^0]*.*    0    FUNC GLOBAL DEFAULT UND lib_func2
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS _bss_end__
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __exidx_end
diff --git a/binutils-2.19/ld/testsuite/ld-arm/mixed-lib.d b/binutils-2.19/ld/testsuite/ld-arm/mixed-lib.d
new file mode 100644
index 0000000..ce488a6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/mixed-lib.d
@@ -0,0 +1,38 @@
+
+tmpdir/mixed-lib.so:     file format elf32-(little|big)arm
+architecture: arm, flags 0x00000150:
+HAS_SYMS, DYNAMIC, D_PAGED
+start address 0x.*
+
+Disassembly of section .plt:
+
+.* <.plt>:
+ .*:	e52de004 	push	{lr}		; \(str lr, \[sp, #-4\]!\)
+ .*:	e59fe004 	ldr	lr, \[pc, #4\]	; .* <lib_func1-0x.*>
+ .*:	e08fe00e 	add	lr, pc, lr
+ .*:	e5bef008 	ldr	pc, \[lr, #8\]!
+ .*:	.*
+ .*:	e28fc6.* 	add	ip, pc, #.*	; 0x.*
+ .*:	e28cca.* 	add	ip, ip, #.*	; 0x.*
+ .*:	e5bcf.* 	ldr	pc, \[ip, #.*\]!
+Disassembly of section .text:
+
+.* <lib_func1>:
+ .*:	e1a0c00d 	mov	ip, sp
+ .*:	e92dd800 	push	{fp, ip, lr, pc}
+ .*:	ebfffff. 	bl	.* <lib_func1-0x..?>
+ .*:	e89d6800 	ldm	sp, {fp, sp, lr}
+ .*:	e12fff1e 	bx	lr
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+
+.* <lib_func2>:
+ .*:	4770      	bx	lr
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
+ .*:	46c0      	nop			\(mov r8, r8\)
diff --git a/binutils-2.19/ld/testsuite/ld-arm/mixed-lib.r b/binutils-2.19/ld/testsuite/ld-arm/mixed-lib.r
new file mode 100644
index 0000000..0137880
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/mixed-lib.r
@@ -0,0 +1,8 @@
+
+tmpdir/mixed-lib.so:     file format elf32-(little|big)arm
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+.* R_ARM_JUMP_SLOT   app_func2
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/mixed-lib.s b/binutils-2.19/ld/testsuite/ld-arm/mixed-lib.s
new file mode 100644
index 0000000..86f5ace
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/mixed-lib.s
@@ -0,0 +1,28 @@
+	.text
+
+	.p2align 4
+	.globl lib_func1
+	.type lib_func1, %function
+lib_func1:
+	mov	ip, sp
+	stmdb	sp!, {r11, ip, lr, pc}
+	bl	app_func2
+	ldmia	sp, {r11, sp, lr}
+	bx lr
+	.size lib_func1, . - lib_func1
+
+	.p2align 4
+	.globl lib_func2
+	.type lib_func2, %function
+	.thumb_func
+	.code 16
+lib_func2:
+	bx lr
+	.size lib_func2, . - lib_func2
+
+	.data
+	.globl data_obj
+	.type data_obj, %object
+data_obj:
+	.long 0
+	.size data_obj, . - data_obj
diff --git a/binutils-2.19/ld/testsuite/ld-arm/mixed-lib.sym b/binutils-2.19/ld/testsuite/ld-arm/mixed-lib.sym
new file mode 100644
index 0000000..677d2ed
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/mixed-lib.sym
@@ -0,0 +1,17 @@
+
+Symbol table for image:
+  Num Buc:    Value  Size   Type   Bind Vis      Ndx Name
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS _edata
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __bss_start__
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS _end
+   ..  ..: ........     4  OBJECT GLOBAL DEFAULT   9 data_obj
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __bss_end__
+   ..  ..: .......0    20    FUNC GLOBAL DEFAULT   6 lib_func1
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __exidx_start
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT   9 __data_start
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __end__
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __bss_start
+   ..  ..: 00000000     0  NOTYPE GLOBAL DEFAULT UND app_func2
+   ..  ..: .......1     2    FUNC GLOBAL DEFAULT   6 lib_func2
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS _bss_end__
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __exidx_end
diff --git a/binutils-2.19/ld/testsuite/ld-arm/movw-merge.d b/binutils-2.19/ld/testsuite/ld-arm/movw-merge.d
new file mode 100644
index 0000000..2df4737
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/movw-merge.d
@@ -0,0 +1,13 @@
+
+.*:     file format.*
+
+Disassembly of section .text:
+
+00008000 <[^>]*>:
+    8000:	e3080013 	movw	r0, #32787	; 0x8013
+    8004:	e3400000 	movt	r0, #0	; 0x0
+
+00008008 <[^>]*>:
+    8008:	f248 0013 	movw	r0, #32787	; 0x8013
+    800c:	f2c0 0000 	movt	r0, #0	; 0x0
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/movw-merge.s b/binutils-2.19/ld/testsuite/ld-arm/movw-merge.s
new file mode 100644
index 0000000..17c70a5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/movw-merge.s
@@ -0,0 +1,20 @@
+	.arch armv7-a
+	.syntax unified
+	.text
+	.global	_start
+	.type	_start, %function
+_start:
+	movw	r0, #:lower16:.LC0
+	movt	r0, #:upper16:.LC0
+	.thumb
+	.global	tfunc
+	.type	tfunc, %function
+tfunc:
+	movw	r0, #:lower16:.LC0
+	movt	r0, #:upper16:.LC0
+
+	.section	.rodata.str1.4,"aMS",%progbits,1
+	.align	2
+	.ascii "pad"
+.LC0:
+	.ascii	"inner: cont \000"
diff --git a/binutils-2.19/ld/testsuite/ld-arm/preempt-app.s b/binutils-2.19/ld/testsuite/ld-arm/preempt-app.s
new file mode 100644
index 0000000..f1eccc2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/preempt-app.s
@@ -0,0 +1,27 @@
+	@ Preempt an ARM shared library function with a Thumb function
+	@ in the application.
+	.text
+	.p2align 4
+	.globl _start
+_start:
+	mov	ip, sp
+	stmdb	sp!, {r11, ip, lr, pc}
+	bl	lib_func1
+	ldmia	sp, {r11, sp, lr}
+	bx lr
+
+	.p2align 4
+	.globl app_func2
+	.type app_func2,%function
+app_func2:
+	bx	lr
+
+	.p2align 4
+	.globl lib_func1
+	.type lib_func1,%function
+	.thumb_func
+lib_func1:
+	bx lr
+
+	.data
+	.long data_obj
diff --git a/binutils-2.19/ld/testsuite/ld-arm/preempt-app.sym b/binutils-2.19/ld/testsuite/ld-arm/preempt-app.sym
new file mode 100644
index 0000000..d8ebf3b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/preempt-app.sym
@@ -0,0 +1,16 @@
+
+Symbol table for image:
+  Num Buc:    Value  Size   Type   Bind Vis      Ndx Name
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS _edata
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __bss_start__
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS _end
+   ..  ..: ........     4  OBJECT GLOBAL DEFAULT  10 data_obj
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __bss_end__
+   ..  ..: .......1    20    FUNC GLOBAL DEFAULT   6 lib_func1
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __exidx_start
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT   9 __data_start
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __end__
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __bss_start
+   ..  ..: .......0     0    FUNC GLOBAL DEFAULT   6 app_func2
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS _bss_end__
+   ..  ..: ........     0  NOTYPE GLOBAL DEFAULT ABS __exidx_end
diff --git a/binutils-2.19/ld/testsuite/ld-arm/symbian-seg1.d b/binutils-2.19/ld/testsuite/ld-arm/symbian-seg1.d
new file mode 100644
index 0000000..21d8a00
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/symbian-seg1.d
@@ -0,0 +1,8 @@
+#source: symbian-seg1.s
+#ld: -Ttext 0x10000 -Tdata 0x400000
+#objdump: -dR
+#...
+ +10000:	00400000 	.word	0x00400000
+	+10000: R_ARM_RELATIVE	.data
+ +10004:	00010008 	.word	0x00010008
+	+10004: R_ARM_RELATIVE	.text
diff --git a/binutils-2.19/ld/testsuite/ld-arm/symbian-seg1.s b/binutils-2.19/ld/testsuite/ld-arm/symbian-seg1.s
new file mode 100644
index 0000000..8f893a2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/symbian-seg1.s
@@ -0,0 +1,13 @@
+        .text
+	.globl	_start
+_start:
+        .word   datavar
+        .word   rodatavar
+
+        .section ".rodata", "a"
+rodatavar:
+        .word 0
+
+        .section ".data", "aw"
+datavar:
+        .word 0
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb-entry.d b/binutils-2.19/ld/testsuite/ld-arm/thumb-entry.d
new file mode 100644
index 0000000..602fd6c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb-entry.d
@@ -0,0 +1,3 @@
+#...
+  Entry point address:               0x8001
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb-entry.s b/binutils-2.19/ld/testsuite/ld-arm/thumb-entry.s
new file mode 100644
index 0000000..5b3659d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb-entry.s
@@ -0,0 +1,8 @@
+	.text
+	.arch armv4t
+	.thumb
+	.global _start
+	.thumb_func
+_start:
+	bx lr
+	
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb-rel32.d b/binutils-2.19/ld/testsuite/ld-arm/thumb-rel32.d
new file mode 100644
index 0000000..34cde4d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb-rel32.d
@@ -0,0 +1,7 @@
+
+.*:     file format.*
+
+Contents of section .text:
+ 8000 (00000011 fffffffd 00ffffff f8000000|11000000 fdffffff 00f8ffff ff000000) .*
+# Ignore .ARM.attributes section
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb-rel32.s b/binutils-2.19/ld/testsuite/ld-arm/thumb-rel32.s
new file mode 100644
index 0000000..83eb0e5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb-rel32.s
@@ -0,0 +1,18 @@
+	.text
+	.arch armv4t
+	.global	_start
+	.type	_start, %function
+	.thumb_func
+_start:
+	.word bar - .
+	.word _start - .
+	.byte 0
+	.4byte (_start - .) + 1
+	.byte 0, 0, 0
+	.section .after, "ax", %progbits
+	.global bar
+	.type bar, %function
+	.thumb_func
+bar:
+	.word 0
+	.ident	"GCC: (GNU) 4.1.0 (CodeSourcery ARM)"
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb1-bl.d b/binutils-2.19/ld/testsuite/ld-arm/thumb1-bl.d
new file mode 100644
index 0000000..09d7095
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb1-bl.d
@@ -0,0 +1,11 @@
+
+.*thumb1-bl:     file format elf32-.*arm
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f3ff fffe 	bl	401000 <bar>
+Disassembly of section .foo:
+
+00401000 <bar>:
+  401000:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb1-bl.s b/binutils-2.19/ld/testsuite/ld-arm/thumb1-bl.s
new file mode 100644
index 0000000..cdecaa4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb1-bl.s
@@ -0,0 +1,22 @@
+@ Test to ensure that a Thumb-1 BL works.
+
+	.arch armv5t
+	.global _start
+	.syntax unified
+
+@ We will place the section .text at 0x1000.
+
+	.text
+	.thumb_func
+
+_start:
+	bl bar
+
+@ We will place the section .foo at 0x401000.
+
+	.section .foo, "xa"
+	.thumb_func
+
+bar:
+	bx lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb2-b-interwork.d b/binutils-2.19/ld/testsuite/ld-arm/thumb2-b-interwork.d
new file mode 100644
index 0000000..b2f9a01
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb2-b-interwork.d
@@ -0,0 +1,16 @@
+
+.*thumb2-b-interwork:     file format elf32-.*arm
+
+Disassembly of section .text:
+
+00008000 <_start>:
+    8000:	f000 b802 	b.w	8008 <__bar_from_thumb>
+
+00008004 <bar>:
+    8004:	e12fff1e 	bx	lr
+
+00008008 <__bar_from_thumb>:
+    8008:	4778      	bx	pc
+    800a:	46c0      	nop			\(mov r8, r8\)
+    800c:	eafffffc 	b	8004 <bar>
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb2-b-interwork.s b/binutils-2.19/ld/testsuite/ld-arm/thumb2-b-interwork.s
new file mode 100644
index 0000000..4452a8f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb2-b-interwork.s
@@ -0,0 +1,20 @@
+@ Test to ensure that a Thumb-2 B.W can branch to an ARM funtion.
+
+	.arch armv7-a
+	.global _start
+	.syntax unified
+	.text
+	.thumb_func
+
+_start:
+	b.w bar
+
+@ Put this in a separate section to force the assembler to generate a reloc
+
+	.arm
+	.section .after, "xa"
+	.global bar
+	.type bar, %function
+bar:
+	bx lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad-noeabi.d b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad-noeabi.d
new file mode 100644
index 0000000..fdf9d8a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad-noeabi.d
@@ -0,0 +1,19 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <__bar_veneer>:
+    1000:	b401      	push	{r0}
+    1002:	4802      	ldr	r0, \[pc, #8\]	\(100c <__bar_veneer\+0xc>\)
+    1004:	4684      	mov	ip, r0
+    1006:	bc01      	pop	{r0}
+    1008:	4760      	bx	ip
+    100a:	bf00      	nop
+    100c:	0100100d 	.word	0x0100100d
+
+00001010 <_start>:
+    1010:	f7ff fff6 	bl	1000 <__bar_veneer>
+Disassembly of section .foo:
+
+0100100c <bar>:
+ 100100c:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d
new file mode 100644
index 0000000..04eb991
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d
@@ -0,0 +1,17 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f000 e802 	blx	1008 <__bar_veneer>
+    1004:	0000      	lsls	r0, r0, #0
+	\.\.\.
+
+00001008 <__bar_veneer>:
+    1008:	e51ff004 	ldr	pc, \[pc, #-4\]	; 100c <__bar_veneer\+0x4>
+    100c:	0100100d 	.word	0x0100100d
+
+Disassembly of section .foo:
+
+0100100c <bar>:
+ 100100c:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.s b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.s
new file mode 100644
index 0000000..834001c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.s
@@ -0,0 +1,22 @@
+@ Test to ensure that a Thumb-1 BL with a Thumb-2-only offset makes the linker generate a stub.
+
+	.arch armv5t
+	.global _start
+	.syntax unified
+
+@ We will place the section .text at 0x1000.
+
+	.text
+	.thumb_func
+
+_start:
+	bl bar
+
+@ We will place the section .foo at 0x100100c.
+
+	.section .foo, "xa"
+	.thumb_func
+
+bar:
+	bx lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-bad-noeabi.d b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-bad-noeabi.d
new file mode 100644
index 0000000..fdf9d8a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-bad-noeabi.d
@@ -0,0 +1,19 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <__bar_veneer>:
+    1000:	b401      	push	{r0}
+    1002:	4802      	ldr	r0, \[pc, #8\]	\(100c <__bar_veneer\+0xc>\)
+    1004:	4684      	mov	ip, r0
+    1006:	bc01      	pop	{r0}
+    1008:	4760      	bx	ip
+    100a:	bf00      	nop
+    100c:	0100100d 	.word	0x0100100d
+
+00001010 <_start>:
+    1010:	f7ff fff6 	bl	1000 <__bar_veneer>
+Disassembly of section .foo:
+
+0100100c <bar>:
+ 100100c:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-bad.d b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-bad.d
new file mode 100644
index 0000000..89c7a55
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-bad.d
@@ -0,0 +1,16 @@
+.*:     file format .*
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f000 e802 	blx	1008 <__bar_veneer>
+    1004:	0000      	lsls	r0, r0, #0
+	\.\.\.
+
+00001008 <__bar_veneer>:
+    1008:	e51ff004 	ldr	pc, \[pc, #-4\]	; 100c <__bar_veneer\+0x4>
+    100c:	0100100d 	.word	0x0100100d
+Disassembly of section .foo:
+
+0100100c <bar>:
+ 100100c:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-bad.s b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-bad.s
new file mode 100644
index 0000000..7685860
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-bad.s
@@ -0,0 +1,22 @@
+@ Test to ensure that a Thumb-2 BL with an oversize offset  makes the linker generate a stub.
+
+	.arch armv7
+	.global _start
+	.syntax unified
+
+@ We will place the section .text at 0x1000.
+
+	.text
+	.thumb_func
+
+_start:
+	bl bar
+
+@ We will place the section .foo at 0x100100c.
+
+	.section .foo, "xa"
+	.thumb_func
+
+bar:
+	bx lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-undefweak.d b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-undefweak.d
new file mode 100644
index 0000000..d06f1ab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-undefweak.d
@@ -0,0 +1,9 @@
+#source: thumb2-bl-undefweak.s
+#as:
+#ld: -shared
+#objdump: -dr
+#...
+Disassembly of section .text:
+
+.* <foo>:
+ .*:	.... .... 	blx	... <foo-0x.*>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-undefweak.s b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-undefweak.s
new file mode 100644
index 0000000..5e70eea
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-undefweak.s
@@ -0,0 +1,10 @@
+@ Test that calls to undefined weak functions resolve to call through
+@ the PLT in shared libraries.
+
+	.arch armv7
+	.syntax unified
+	.text
+	.thumb_func
+foo:
+	bl bar
+	.weak bar
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-undefweak1.d b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-undefweak1.d
new file mode 100644
index 0000000..929d180
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-undefweak1.d
@@ -0,0 +1,9 @@
+#source: thumb2-bl-undefweak1.s
+#as:
+#ld: -shared
+#objdump: -dr
+#...
+Disassembly of section .text:
+
+.* <foo>:
+ .*:	........ 	bl	... <foo-0x.*>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-undefweak1.s b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-undefweak1.s
new file mode 100644
index 0000000..a302811
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl-undefweak1.s
@@ -0,0 +1,9 @@
+@ Test that calls to undefined weak functions resolve to call through
+@ the PLT in shared libraries in ARM mode.
+
+	.arch armv6
+	.syntax unified
+	.text
+foo:
+	bl bar
+	.weak bar
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl.d b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl.d
new file mode 100644
index 0000000..bdfb9b7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl.d
@@ -0,0 +1,11 @@
+
+.*thumb2-bl:     file format elf32-.*arm
+
+Disassembly of section .text:
+
+00001000 <_start>:
+    1000:	f3ff d7fe 	bl	1001000 <bar>
+Disassembly of section .foo:
+
+01001000 <bar>:
+ 1001000:	4770      	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl.s b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl.s
new file mode 100644
index 0000000..ddb1cd3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/thumb2-bl.s
@@ -0,0 +1,23 @@
+@ Test to ensure that a Thumb-2 BL works with an offset that is
+@ not permissable for Thumb-1.
+
+	.arch armv7
+	.global _start
+	.syntax unified
+
+@ We will place the section .text at 0x1000.
+
+	.text
+	.thumb_func
+
+_start:
+	bl bar
+
+@ We will place the section .foo at 0x1001000.
+
+	.section .foo, "xa"
+	.thumb_func
+
+bar:
+	bx lr
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/tls-app.d b/binutils-2.19/ld/testsuite/ld-arm/tls-app.d
new file mode 100644
index 0000000..fd3d638
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/tls-app.d
@@ -0,0 +1,18 @@
+
+.*:     file format elf32-.*arm
+architecture: arm, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x00008204
+
+Disassembly of section .text:
+
+00008204 <foo>:
+    8204:	e1a00000 	nop			\(mov r0,r0\)
+    8208:	e1a00000 	nop			\(mov r0,r0\)
+    820c:	e1a0f00e 	mov	pc, lr
+    8210:	000080bc 	.word	0x000080bc
+    8214:	000080b4 	.word	0x000080b4
+    8218:	000080ac 	.word	0x000080ac
+    821c:	00000004 	.word	0x00000004
+    8220:	000080c4 	.word	0x000080c4
+    8224:	00000014 	.word	0x00000014
diff --git a/binutils-2.19/ld/testsuite/ld-arm/tls-app.r b/binutils-2.19/ld/testsuite/ld-arm/tls-app.r
new file mode 100644
index 0000000..af6c2d7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/tls-app.r
@@ -0,0 +1,10 @@
+
+.*:     file format elf32-.*arm
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+[0-9a-f]+ R_ARM_TLS_DTPMOD32  app_gd
+[0-9a-f]+ R_ARM_TLS_DTPOFF32  app_gd
+[0-9a-f]+ R_ARM_TLS_DTPMOD32  lib_gd
+[0-9a-f]+ R_ARM_TLS_DTPOFF32  lib_gd
+[0-9a-f]+ R_ARM_TLS_TPOFF32  app_ie
diff --git a/binutils-2.19/ld/testsuite/ld-arm/tls-app.s b/binutils-2.19/ld/testsuite/ld-arm/tls-app.s
new file mode 100644
index 0000000..d505295
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/tls-app.s
@@ -0,0 +1,34 @@
+	.text
+	.globl foo
+	.type foo, %function
+foo:
+	nop
+.L2:
+	nop
+	mov	pc, lr
+
+.Lpool:
+	.word	lib_gd(tlsgd) + (. - .L2 - 8)
+	.word	app_gd(tlsgd) + (. - .L2 - 8)
+	.word	app_ld(tlsldm) + (. - .L2 - 8)
+	.word	app_ld(tlsldo)
+	.word	app_ie(gottpoff) + (. - .L2 - 8)
+	.word	app_le(tpoff)
+
+	.section .tdata,"awT"
+	.global app_gd
+app_gd:
+	.space	4
+
+	.global app_ld
+app_ld:
+	.space	4
+
+	.section .tbss,"awT",%nobits
+	.global app_ie
+app_ie:
+	.space	4
+
+	.global app_le
+app_le:
+	.space	4
diff --git a/binutils-2.19/ld/testsuite/ld-arm/tls-lib.d b/binutils-2.19/ld/testsuite/ld-arm/tls-lib.d
new file mode 100644
index 0000000..774ac91
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/tls-lib.d
@@ -0,0 +1,15 @@
+
+.*:     file format elf32-.*arm
+architecture: arm, flags 0x00000150:
+HAS_SYMS, DYNAMIC, D_PAGED
+start address 0x.*
+
+Disassembly of section .text:
+
+.* <foo>:
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a00000 	nop			\(mov r0,r0\)
+ .*:	e1a0f00e 	mov	pc, lr
+ .*:	00008098 	.word	0x00008098
+ .*:	0000808c 	.word	0x0000808c
+ .*:	00000004 	.word	0x00000004
diff --git a/binutils-2.19/ld/testsuite/ld-arm/tls-lib.r b/binutils-2.19/ld/testsuite/ld-arm/tls-lib.r
new file mode 100644
index 0000000..279b805
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/tls-lib.r
@@ -0,0 +1,10 @@
+
+.*:     file format elf32-.*arm
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+.* R_ARM_TLS_DTPMOD32  \*ABS\*
+.* R_ARM_TLS_DTPMOD32  lib_gd
+.* R_ARM_TLS_DTPOFF32  lib_gd
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/tls-lib.s b/binutils-2.19/ld/testsuite/ld-arm/tls-lib.s
new file mode 100644
index 0000000..fa928c0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/tls-lib.s
@@ -0,0 +1,22 @@
+	.text
+	.globl foo
+	.type foo, %function
+foo:
+	nop
+.L2:
+	nop
+	mov	pc, lr
+
+.Lpool:
+	.word	lib_gd(tlsgd) + (. - .L2 - 8)
+	.word	lib_ld(tlsldm) + (. - .L2 - 8)
+	.word	lib_ld(tlsldo)
+
+	.section .tdata,"awT"
+	.global lib_gd
+lib_gd:
+	.space	4
+
+	.global lib_ld
+lib_ld:
+	.space	4
diff --git a/binutils-2.19/ld/testsuite/ld-arm/use-thumb-lib.s b/binutils-2.19/ld/testsuite/ld-arm/use-thumb-lib.s
new file mode 100644
index 0000000..07a7f57
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/use-thumb-lib.s
@@ -0,0 +1,25 @@
+	.cpu arm10tdmi
+	.fpu softvfp
+	.eabi_attribute 18, 4
+	.eabi_attribute 20, 1
+	.eabi_attribute 21, 1
+	.eabi_attribute 23, 3
+	.eabi_attribute 24, 1
+	.eabi_attribute 25, 1
+	.eabi_attribute 26, 2
+	.eabi_attribute 30, 6
+	.file	"use_thumb_lib.c"
+	.text
+	.align	2
+	.global	foo
+	.type	foo, %function
+foo:
+	@ args = 0, pretend = 0, frame = 0
+	@ frame_needed = 1, uses_anonymous_args = 0
+	mov	ip, sp
+	stmfd	sp!, {fp, ip, lr, pc}
+	sub	fp, ip, #4
+	bl	lib_func2
+	ldmfd	sp, {fp, sp, pc}
+	.size	foo, .-foo
+	.ident	"GCC: (GNU) 4.1.0 (CodeSourcery ARM 2006q1-7)"
diff --git a/binutils-2.19/ld/testsuite/ld-arm/use-thumb-lib.sym b/binutils-2.19/ld/testsuite/ld-arm/use-thumb-lib.sym
new file mode 100644
index 0000000..eafbcf7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/use-thumb-lib.sym
@@ -0,0 +1,4 @@
+#...
+   ..  ..: 00000000     0    FUNC GLOBAL DEFAULT UND lib_func2
+#pass
+
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-none.d b/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-none.d
new file mode 100644
index 0000000..64a67ae
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-none.d
@@ -0,0 +1,9 @@
+
+.*: .*file format elf32-(big|little)arm
+
+Disassembly of section \.text:
+
+00008000 <_start>:
+    8000:	ee474a20 	\.word	0xee474a20
+    8004:	ed927a00 	\.word	0xed927a00
+    8008:	e12fff1e 	bx	lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-none.s b/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-none.s
new file mode 100644
index 0000000..a016c49
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-none.s
@@ -0,0 +1,7 @@
+	.arm
+	.text
+	.globl _start
+_start:
+	.word 0xee474a20
+	.word 0xed927a00
+	bx lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-scalar.d b/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-scalar.d
new file mode 100644
index 0000000..b7fe136
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-scalar.d
@@ -0,0 +1,15 @@
+
+.*: .*file format elf32-(big|little)arm
+
+Disassembly of section \.text:
+
+00008000 <_start>:
+    8000:	0a000001 	beq	800c <__vfp11_veneer_0>
+
+00008004 <__vfp11_veneer_0_r>:
+    8004:	ed927a00 	flds	s14, \[r2\]
+    8008:	e12fff1e 	bx	lr
+
+0000800c <__vfp11_veneer_0>:
+    800c:	0e474a20 	fmacseq	s9, s14, s1
+    8010:	eafffffb 	b	8004 <__vfp11_veneer_0_r>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-scalar.s b/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-scalar.s
new file mode 100644
index 0000000..4ffb891
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-scalar.s
@@ -0,0 +1,7 @@
+	.arm
+	.text
+	.globl _start
+_start:
+	fmacseq s9, s14, s1
+	flds s14, [r2]
+	bx lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-vector.d b/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-vector.d
new file mode 100644
index 0000000..3474b8c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-vector.d
@@ -0,0 +1,16 @@
+
+.*: .*file format elf32-(big|little)arm
+
+Disassembly of section \.text:
+
+00008000 <_start>:
+    8000:	0a000002 	beq	8010 <__vfp11_veneer_0>
+
+00008004 <__vfp11_veneer_0_r>:
+    8004:	e1a02003 	mov	r2, r3
+    8008:	ed927a00 	flds	s14, \[r2\]
+    800c:	e12fff1e 	bx	lr
+
+00008010 <__vfp11_veneer_0>:
+    8010:	0e474a20 	fmacseq	s9, s14, s1
+    8014:	eafffffa 	b	8004 <__vfp11_veneer_0_r>
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-vector.s b/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-vector.s
new file mode 100644
index 0000000..05b6100
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vfp11-fix-vector.s
@@ -0,0 +1,8 @@
+	.arm
+	.text
+	.globl _start
+_start:
+	fmacseq s9, s14, s1
+	mov r2,r3
+	flds s14, [r2]
+	bx lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vxworks1-lib.dd b/binutils-2.19/ld/testsuite/ld-arm/vxworks1-lib.dd
new file mode 100644
index 0000000..77bdf72
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vxworks1-lib.dd
@@ -0,0 +1,41 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+00080800 <_PROCEDURE_LINKAGE_TABLE_>:
+   80800:	e59fc000 	ldr	ip, \[pc, #0\]	; 80808 <.*>
+   80804:	e79cf009 	ldr	pc, \[ip, r9\]
+   80808:	0000000c 	.word	0x0000000c
+   8080c:	e59fc000 	ldr	ip, \[pc, #0\]	; 80814 <.*>
+   80810:	e599f008 	ldr	pc, \[r9, #8\]
+   80814:	00000000 	.word	0x00000000
+   80818:	e59fc000 	ldr	ip, \[pc, #0\]	; 80820 <.*>
+   8081c:	e79cf009 	ldr	pc, \[ip, r9\]
+   80820:	00000010 	.word	0x00000010
+   80824:	e59fc000 	ldr	ip, \[pc, #0\]	; 8082c <.*>
+   80828:	e599f008 	ldr	pc, \[r9, #8\]
+   8082c:	0000000c 	.word	0x0000000c
+Disassembly of section \.text:
+
+00080c00 <foo>:
+   80c00:	e92dc200 	push	{r9, lr, pc}
+   80c04:	e59f9024 	ldr	r9, \[pc, #36\]	; 80c30 <.*>
+   80c08:	e5999000 	ldr	r9, \[r9\]
+   80c0c:	e5999000 	ldr	r9, \[r9\]
+   80c10:	e59f001c 	ldr	r0, \[pc, #28\]	; 80c34 <.*>
+   80c14:	e7991000 	ldr	r1, \[r9, r0\]
+   80c18:	e2811001 	add	r1, r1, #1	; 0x1
+   80c1c:	e7891000 	str	r1, \[r9, r0\]
+   80c20:	eb000004 	bl	80c38 <slocal>
+   80c24:	ebfffefb 	bl	80818 <.*>
+   80c28:	ebfffef4 	bl	80800 <.*>
+   80c2c:	e8bd8200 	pop	{r9, pc}
+   80c30:	00000000 	.word	0x00000000
+   80c34:	00000014 	.word	0x00000014
+
+00080c38 <slocal>:
+   80c38:	e1a0f00e 	mov	pc, lr
+
+00080c3c <sglobal>:
+   80c3c:	e1a0f00e 	mov	pc, lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vxworks1-lib.nd b/binutils-2.19/ld/testsuite/ld-arm/vxworks1-lib.nd
new file mode 100644
index 0000000..edf3db3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vxworks1-lib.nd
@@ -0,0 +1,9 @@
+#...
+Symbol table '\.dynsym' .*:
+#...
+.*: 00081400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
+#...
+Symbol table '\.symtab' .*:
+#...
+.*: 00081400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vxworks1-lib.rd b/binutils-2.19/ld/testsuite/ld-arm/vxworks1-lib.rd
new file mode 100644
index 0000000..226bd09
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vxworks1-lib.rd
@@ -0,0 +1,12 @@
+
+Relocation section '\.rela\.plt' at offset .* contains 2 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+0008140c  .*16 R_ARM_JUMP_SLOT   00000000   sexternal \+ 0
+00081410  .*16 R_ARM_JUMP_SLOT   00080c3c   sglobal \+ 0
+
+Relocation section '\.rela\.dyn' at offset .* contains 4 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+00081800  00000017 R_ARM_RELATIVE * 00080c38
+00080c0c  .*06 R_ARM_ABS12       00000000   __GOTT_INDEX__ \+ 0
+00080c30  .*02 R_ARM_ABS32       00000000   __GOTT_BASE__ \+ 0
+00081414  .*15 R_ARM_GLOB_DAT    00081c00   x \+ 0
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vxworks1-lib.s b/binutils-2.19/ld/testsuite/ld-arm/vxworks1-lib.s
new file mode 100644
index 0000000..66dfd1e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vxworks1-lib.s
@@ -0,0 +1,36 @@
+	.text
+	.globl	foo
+	.type	foo, %function
+foo:
+	stmfd	sp!, {r9, lr, pc}
+	ldr	r9, 1f
+	ldr	r9, [r9]
+	ldr	r9, [r9, #__GOTT_INDEX__]
+	ldr	r0, 1f + 4
+	ldr	r1, [r9, r0]
+	add	r1, r1, #1
+	str	r1, [r9, r0]
+	bl	slocal(PLT)
+	bl	sglobal(PLT)
+	bl	sexternal(PLT)
+	ldmfd	sp!, {r9, pc}
+1:
+	.word	__GOTT_BASE__
+	.word	x(got)
+	.size	foo, .-foo
+
+	.type	slocal, %function
+slocal:
+	mov	pc,lr
+	.size	slocal, .-slocal
+
+	.globl	sglobal
+	.type	sglobal, %function
+sglobal:
+	mov	pc,lr
+	.size	sglobal, .-sglobal
+
+	.data
+	.4byte	slocal
+
+	.comm	x,4,4
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vxworks1-lib.td b/binutils-2.19/ld/testsuite/ld-arm/vxworks1-lib.td
new file mode 100644
index 0000000..9f223e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vxworks1-lib.td
@@ -0,0 +1,3 @@
+#...
+ 0x0+16 \(TEXTREL\) +0x0
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vxworks1-static.d b/binutils-2.19/ld/testsuite/ld-arm/vxworks1-static.d
new file mode 100644
index 0000000..88c0baf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vxworks1-static.d
@@ -0,0 +1,4 @@
+#name: VxWorks executable test 1 (static)
+#source: vxworks1.s
+#ld: tmpdir/libvxworks1.so -Tvxworks1.ld
+#error: Dynamic sections created in non-dynamic link
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vxworks1.dd b/binutils-2.19/ld/testsuite/ld-arm/vxworks1.dd
new file mode 100644
index 0000000..0443122
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vxworks1.dd
@@ -0,0 +1,37 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+00080800 <_PROCEDURE_LINKAGE_TABLE_>:
+   80800:	e52dc008 	str	ip, \[sp, #-8\]!
+   80804:	e59fc000 	ldr	ip, \[pc, #0\]	; 8080c <.*>
+   80808:	e59cf008 	ldr	pc, \[ip, #8\]
+   8080c:	00081400 	.word	0x00081400
+			8080c: R_ARM_ABS32	_GLOBAL_OFFSET_TABLE_
+   80810:	e59fc000 	ldr	ip, \[pc, #0\]	; 80818 <.*>
+   80814:	e59cf000 	ldr	pc, \[ip\]
+   80818:	0008140c 	.word	0x0008140c
+			80818: R_ARM_ABS32	_GLOBAL_OFFSET_TABLE_\+0xc
+   8081c:	e59fc000 	ldr	ip, \[pc, #0\]	; 80824 <.*>
+   80820:	eafffff6 	b	80800 <.*>
+   80824:	00000000 	.word	0x00000000
+   80828:	e59fc000 	ldr	ip, \[pc, #0\]	; 80830 <.*>
+   8082c:	e59cf000 	ldr	pc, \[ip\]
+   80830:	00081410 	.word	0x00081410
+			80830: R_ARM_ABS32	_GLOBAL_OFFSET_TABLE_\+0x10
+   80834:	e59fc000 	ldr	ip, \[pc, #0\]	; 8083c <.*>
+   80838:	eafffff0 	b	80800 <.*>
+   8083c:	0000000c 	.word	0x0000000c
+Disassembly of section \.text:
+
+00080c00 <_start>:
+   80c00:	ebffff08 	bl	80828 <.*>
+			80c00: R_ARM_PC24	\.plt\+0x20
+   80c04:	eb000000 	bl	80c0c <sexternal>
+			80c04: R_ARM_PC24	sexternal\+0xfffffff8
+   80c08:	eaffff00 	b	80810 <.*>
+			80c08: R_ARM_PC24	\.plt\+0x8
+
+00080c0c <sexternal>:
+   80c0c:	e1a0f00e 	mov	pc, lr
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vxworks1.ld b/binutils-2.19/ld/testsuite/ld-arm/vxworks1.ld
new file mode 100644
index 0000000..65bf65d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vxworks1.ld
@@ -0,0 +1,30 @@
+SECTIONS
+{
+  . = 0x80000;
+  .interp : { *(.interp) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+
+  . = ALIGN (0x400);
+  .rela.dyn : { *(.rela.dyn) }
+  .rela.plt : { *(.rela.plt) }
+
+  . = ALIGN (0x400);
+  .plt : { *(.plt) }
+
+  . = ALIGN (0x400);
+  .text : { *(.text) }
+
+  . = ALIGN (0x1000);
+  .dynamic : { *(.dynamic) }
+
+  . = ALIGN (0x400);
+  .got : { *(.got.plt) *(.got) }
+
+  . = ALIGN (0x400);
+  .data : { *(.data) }
+
+  . = ALIGN (0x400);
+  .bss : { *(.bss) *(.dynbss) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vxworks1.rd b/binutils-2.19/ld/testsuite/ld-arm/vxworks1.rd
new file mode 100644
index 0000000..8d7d5cb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vxworks1.rd
@@ -0,0 +1,19 @@
+
+Relocation section '\.rela\.plt' at offset .* contains 2 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+0008140c  .*16 R_ARM_JUMP_SLOT   00080810   sglobal \+ 0
+00081410  .*16 R_ARM_JUMP_SLOT   00080828   foo \+ 0
+
+Relocation section '\.rela\.text' at offset .* contains 3 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name \+ Addend
+00080c00  .*01 R_ARM_PC24        00080800   \.plt \+ 20
+00080c04  .*01 R_ARM_PC24        00080c0c   sexternal \+ fffffff8
+00080c08  .*01 R_ARM_PC24        00080800   \.plt \+ 8
+
+Relocation section '\.rela\.plt\.unloaded' at offset .* contains 5 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+0008080c  .*02 R_ARM_ABS32       00081400   _GLOBAL_OFFSET_TABLE_ \+ 0
+00080818  .*02 R_ARM_ABS32       00081400   _GLOBAL_OFFSET_TABLE_ \+ c
+0008140c  .*02 R_ARM_ABS32       00080800   _PROCEDURE_LINKAGE_TAB.* \+ 0
+00080830  .*02 R_ARM_ABS32       00081400   _GLOBAL_OFFSET_TABLE_ \+ 10
+00081410  .*02 R_ARM_ABS32       00080800   _PROCEDURE_LINKAGE_TAB.* \+ 0
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vxworks1.s b/binutils-2.19/ld/testsuite/ld-arm/vxworks1.s
new file mode 100644
index 0000000..0139a11
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vxworks1.s
@@ -0,0 +1,14 @@
+	.text
+	.globl	_start
+	.type	_start, %function
+_start:
+	bl	foo
+	bl	sexternal
+	b	sglobal
+	.size	_start, .-_start
+
+	.globl	sexternal
+	.type	sexternal, %function
+sexternal:
+	mov	pc, lr
+	.size	sexternal, .-sexternal
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vxworks2-static.sd b/binutils-2.19/ld/testsuite/ld-arm/vxworks2-static.sd
new file mode 100644
index 0000000..912755b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vxworks2-static.sd
@@ -0,0 +1,9 @@
+#...
+Elf file type is EXEC \(Executable file\)
+Entry point 0x80000
+#...
+Program Headers:
+  Type .*
+  LOAD .* 0x00080000 0x00080000 .* R E 0x1000
+
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vxworks2.s b/binutils-2.19/ld/testsuite/ld-arm/vxworks2.s
new file mode 100644
index 0000000..1bd207b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vxworks2.s
@@ -0,0 +1,5 @@
+	.globl	_start
+	.type	_start, %function
+_start:
+	mov	pc, lr
+	.end	_start
diff --git a/binutils-2.19/ld/testsuite/ld-arm/vxworks2.sd b/binutils-2.19/ld/testsuite/ld-arm/vxworks2.sd
new file mode 100644
index 0000000..5ff87d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-arm/vxworks2.sd
@@ -0,0 +1,13 @@
+#...
+Elf file type is EXEC \(Executable file\)
+Entry point 0x80400
+#...
+Program Headers:
+  Type .*
+  PHDR .*
+#...
+  LOAD .* 0x00080000 0x00080000 .* R E 0x1000
+  LOAD .* 0x00081000 0x00081000 .* RW  0x1000
+  DYNAMIC .*
+
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-auto-import/auto-import.exp b/binutils-2.19/ld/testsuite/ld-auto-import/auto-import.exp
new file mode 100644
index 0000000..5b3a484
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-auto-import/auto-import.exp
@@ -0,0 +1,177 @@
+# Expect script for ld-auto-import tests
+#   Copyright 2002, 2007, 2008
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Ralf.Habacker@freenet.de
+# Based on ls-shared/shared.exp by Ian Lance Taylor (ian@cygnus.com)
+#
+ 
+# Note: 
+# 
+# This script tests some auto-import functionality:
+#
+#  A. "auto importing direct from a dll" functionality, which dramatically reduces the 
+#     linking time for big libraries and applications by skipping creating/using 
+#     import libraries. Instead it links directly to the related dll or to a symlinked 
+#     dll for replacing regular import libraries. The test has 6 stages: 
+#  
+#     1. compile and link a test dll exporting some text and data symbols and a 
+#     standard import library
+#
+#     2. create a symbolic link to this dll to simulate a replaced import library. 
+#
+#     3. compile and link a client application with the standard import library. 
+#     This should produce no errors. 
+#
+#     4. compile and link a client application with the created dll. 
+#     This should also produce no errors. 
+#
+#     5. compile and link a client application using the "import library". 
+#     This should also produce no errors. 
+#
+#     6. compile and link a client application with auto-import disabled. 
+#     This should produce a linking error. 
+#
+# B. runtime check if there are no segfaults when importing const data variables 
+#
+
+# This test can only be run if ld generates native executables.
+if ![isnative] then {return}
+
+# This test can only be run on a couple of platforms.
+# Square bracket expressions seem to confuse istarget.
+if { ![istarget *-pc-cygwin]    
+     && ![istarget *-pc-mingw*] } {
+    return
+}
+
+if [istarget *-pc-mingw*] {
+    # FIXME: Add support for this target.
+    unsupported "mingw currently not supported"
+}
+
+# No compiler, no test.
+if { [which $CC] == 0 } {
+    untested "Auto import test (compiler not found)"
+    return
+}
+
+# ld_special_link
+#	link a program using ld, without including any libraries
+#
+proc ld_special_link { ld target objects } {
+    global host_triplet
+    global link_output
+
+    if { [which $ld] == 0 } then {
+	perror "$ld does not exist"
+	return 0
+    }
+
+    if [is_endian_output_format $objects] then {
+	set flags [big_or_little_endian]
+    } else {
+	set flags ""
+    }
+
+    verbose -log "$ld $flags -o $target $objects"
+
+    catch "exec $ld $flags -o $target $objects" link_output
+    set exec_output [prune_warnings $link_output]
+
+    # We don't care if we get a warning about a non-existent start
+    # symbol, since the default linker script might use ENTRY.
+    regsub -all "(^|\n)(\[^\n\]*: warning: cannot find entry symbol\[^\n\]*\n?)" $exec_output "\\1" exec_output
+
+    # We don't care if we get a message about creating a library file.
+    regsub -all "(^|\n)(Creating library file\[^\n\]*\n?)" $exec_output "\\1" exec_output
+
+    if [string match "" $exec_output] then {
+	return 1
+    }
+
+    verbose -log "$exec_output"
+    return 0
+}
+
+set tmpdir tmpdir
+set SHCFLAG ""
+
+if [istarget *-pc-cygwin] {
+    # Set some libs needed for cygwin.
+    set MYLIBS "-L/usr/lib -lcygwin -L/usr/lib/w32api -lkernel32"
+    
+    # Compile the dll.
+    if ![ld_compile "$CC $CFLAGS $SHCFLAG" $srcdir/$subdir/dll.c $tmpdir/dll.o] {
+	fail "compiling shared lib"
+    }
+    if ![ld_special_link "$ld -shared --enable-auto-import --out-implib=$tmpdir/libstandard.dll.a" $tmpdir/dll.dll "$tmpdir/dll.o $MYLIBS"] {
+	fail "linking shared lib"
+    }
+
+    # Create symbolic link.
+    catch "exec ln -fs dll.dll $tmpdir/libsymlinked_dll.dll.a" ln_catch
+
+    # Compile and link the client program.
+    if ![ld_compile "$CC $CFLAGS $SHCFLAG" $srcdir/$subdir/client.c $tmpdir/client.o] {
+        fail "compiling client"
+    }
+
+    # Check linking with import library.
+    set msg "linking auto-import client using a standard import library"
+    if [ld_special_link $ld $tmpdir/client-linklib.exe "--enable-auto-import --enable-runtime-pseudo-reloc /lib/crt0.o $tmpdir/client.o -L$tmpdir -lstandard $MYLIBS"] {
+	pass $msg
+    } else {
+	fail $msg 
+    }
+
+    # Check linking directly with dll.
+    set msg "linking auto-import client using the dll"
+    if [ld_special_link $ld $tmpdir/client-linkdll.exe "--enable-auto-import --enable-runtime-pseudo-reloc /lib/crt0.o $tmpdir/client.o -L$tmpdir -ldll $MYLIBS"] {
+	pass $msg
+    } else {
+	fail $msg 
+    }
+
+    # Check linking with symlinked dll.
+    set msg "linking auto-import client using symbolic linked dll"
+    if [ld_special_link $ld $tmpdir/client-symlinkeddll.exe "--enable-auto-import --enable-runtime-pseudo-reloc /lib/crt0.o $tmpdir/client.o -L$tmpdir -lsymlinked_dll $MYLIBS"] {
+	pass $msg
+    } else {
+	fail $msg 
+    }
+
+    # Check linking with disabled auto-import, this must produce linking error.
+    set msg "linking with disabled auto-import"
+    if ![ld_special_link $ld $tmpdir/client-failed.exe "--disable-auto-import --enable-runtime-pseudo-reloc /lib/crt0.o $tmpdir/client.o -L$tmpdir -ldll $MYLIBS"] {
+	pass $msg
+    } else {
+	fail $msg
+    }
+
+    # Check that the app works - ie that there is output when the applications runs.
+    set msg "application runtime segfault check" 
+    catch "exec $tmpdir/client-linklib.exe" exec_output
+    if ![string match "" $exec_output] then {
+    	pass $msg
+    } else {
+    	fail $msg
+    }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-auto-import/client.c b/binutils-2.19/ld/testsuite/ld-auto-import/client.c
new file mode 100644
index 0000000..b883fdb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-auto-import/client.c
@@ -0,0 +1,60 @@
+#include <stdio.h>

+

+extern int var;

+extern void (*func_ptr)(void);

+extern void print_var (void);

+extern void print_foo (void);

+extern int foo;

+extern int var2[2];

+

+typedef struct

+{

+  int *   var;

+  void (* func_ptr)(void);

+  int *   var_with_offset;

+}

+TEST;

+

+TEST xyz = { & var, print_var, & var };

+

+const TEST const_xyz = { & var, print_var, & var };

+

+int

+main (void)

+{

+  print_var ();

+

+  printf ("We see var = %d\n", var);

+  printf ("Setting var = 456\n");

+

+  var = 456;

+

+  print_var ();

+  printf ("We see var = %d\n\n", var);

+

+  var = 90;

+  print_var ();

+  printf ("We see var = %d\n\n", var);

+

+  print_foo ();

+  printf ("We see foo = %d\n", foo);

+  printf ("Setting foo = 19\n");

+  foo = 19;

+  print_foo ();

+  printf ("We see foo = %d\n\n", foo);

+  fflush (stdout);

+

+  printf ("Calling dllimported function pointer\n");

+  func_ptr ();

+

+  printf ("Calling functions using global structure\n"); 

+  xyz.func_ptr ();

+  * xyz.var = 40;

+  xyz.func_ptr ();

+

+  printf ("We see var2[0] = %d\n\n", var2[0]);

+

+  printf ("We see const xyz %x %x\n", const_xyz.var, const_xyz.var_with_offset);

+

+  return 0;

+}

diff --git a/binutils-2.19/ld/testsuite/ld-auto-import/dll.c b/binutils-2.19/ld/testsuite/ld-auto-import/dll.c
new file mode 100644
index 0000000..ccf85e4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-auto-import/dll.c
@@ -0,0 +1,20 @@
+int var = 123;

+int foo = 121;

+

+int var2[2]= { 123, 456 };

+

+#include <stdio.h>

+

+void

+print_var (void)

+{

+  printf ("DLL sees var = %d\n", var);

+}

+

+void

+print_foo (void)

+{

+  printf ("DLL sees foo = %d\n", foo);

+}

+

+void (* func_ptr)(void) = print_foo;

diff --git a/binutils-2.19/ld/testsuite/ld-bootstrap/bootstrap.exp b/binutils-2.19/ld/testsuite/ld-bootstrap/bootstrap.exp
new file mode 100644
index 0000000..fdeffe3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-bootstrap/bootstrap.exp
@@ -0,0 +1,177 @@
+# Expect script for LD Bootstrap Tests
+#   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2004,
+#   2006, 2007  Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Jeffrey Wheat (cassidy@cygnus.com)
+# Rewritten by Ian Lance Taylor (ian@cygnus.com)
+#
+
+# Make sure that ld can bootstrap itself.
+
+# This test can only be run if ld generates native executables.
+if ![isnative] {
+    return
+}
+
+# Bootstrap ld.  First link the object files together using -r, in
+# order to test -r.  Then link the result into an executable, ld1, to
+# really test -r.  Use ld1 to link a fresh ld, ld2.  Use ld2 to link a
+# new ld, ld3.  ld2 and ld3 should be identical.
+
+foreach flags {"" "strip" "--static" "--traditional-format"
+	       "--no-keep-memory" "--relax"} {
+    set do_strip "no"
+    if {"$flags" == "strip"} { 
+	set testname "bootstrap with $flags"
+        set flags ""
+	set do_strip "yes"
+    } else { if {"$flags" != ""} { 
+	set testname "bootstrap with $flags"
+    } else {
+	set testname "bootstrap"
+    }}
+
+    # --static is meaningless and --relax is incompatible with -r.
+    set partial_flags "$flags"
+    if { "$flags" == "--static" || "$flags" == "--relax" } {
+	set partial_flags ""
+    }
+
+    # This test can only be run if we have the ld build directory,
+    # since we need the object files.
+    if {$ld != "$objdir/ld-new"} {
+	untested $testname
+	continue
+    }
+
+    # If we only have a shared libbfd, we probably can't run the
+    # --static test.
+    if { $flags == "--static" && ! [string match "*libbfd.a*" $BFDLIB] } then {
+	untested $testname
+	continue
+    }
+
+    if ![ld_relocate $ld tmpdir/ld-partial.o "$partial_flags $OFILES"] {
+	fail $testname
+	continue
+    }
+
+    # On AIX, you need to specify an import list when using --static.
+    # You only want the import list when creating the final
+    # executable.
+    if { [istarget "*-*-aix*"] 
+         && ![istarget "ia64-*-aix*"]} {
+	if {"$flags" == "--static"} {
+	    set flags "--static -bI:/lib/syscalls.exp"
+	}
+    }
+
+    # On Irix 5, linking with --static only works if all the files are
+    # compiled using -non_shared.
+    if {"$flags" == "--static"} {
+	setup_xfail "mips*-*-irix5*"
+    }
+
+    if ![ld_link $ld tmpdir/ld1 "$flags tmpdir/ld-partial.o $BFDLIB $LIBIBERTY"] {
+	fail $testname
+	continue
+    }
+
+    if {"$do_strip" == "yes"} { 
+	verbose -log "$strip tmpdir/ld1"     
+	catch "exec $strip tmpdir/ld1" exec_output
+	if ![string match "" $exec_output] then {
+	    verbose -log "$exec_output"
+	    fail $testname
+	    continue
+	}
+    }
+
+    if ![ld_link tmpdir/ld1 tmpdir/ld2 "$flags $OFILES $BFDLIB $LIBIBERTY"] {
+	fail $testname
+	continue
+    }
+
+    if ![ld_link tmpdir/ld2 tmpdir/ld3 "$flags $OFILES $BFDLIB $LIBIBERTY"] {
+	fail $testname
+	continue
+    }
+
+    if {"$flags" == "--static"} {
+	if { [istarget ia64-*-elf*]
+	     || [istarget ia64-*-linux*] } {
+	    # On ia64, tmpdir/ld2 != tmpdir/ld3 is normal since they are
+	    # generated by different linkers, tmpdir/ld1 and tmpdir/ld2.
+	    # So we rebuild tmpdir/ld2 with tmpdir/ld3.
+	    if ![ld_link tmpdir/ld3 tmpdir/ld2 "$flags $OFILES $BFDLIB $LIBIBERTY"] {
+		fail $testname
+		continue
+	    }
+	}
+    } else {
+	if { [istarget mips*-*-linux*] } {
+	    # On Linux/mips, tmpdir/ld2 != tmpdir/ld3 is normal since
+	    # they are generated by different linkers, tmpdir/ld1 and
+	    # tmpdir/ld2. So we rebuild tmpdir/ld2 with tmpdir/ld3.
+	    if ![ld_link tmpdir/ld3 tmpdir/ld2 "$flags $OFILES $BFDLIB $LIBIBERTY"] {
+		fail $testname
+		continue
+	    }
+	}
+    }
+
+    send_log "compare (tail of) tmpdir/ld2 tmpdir/ld3\n"
+    verbose  "compare (tail of) tmpdir/ld2 tmpdir/ld3"
+    if {[istarget "*-*-pe"]
+	|| [istarget "*-*-wince"]
+	|| [istarget "*-*-cygwin*"]
+	|| [istarget "*-*-winnt*"]
+	|| [istarget "*-*-mingw*"]
+	|| [istarget "*-*-interix*"]
+	|| [istarget "*-*-beospe*"]
+	|| [istarget "*-*-netbsdpe*"]} {
+        # Trim off the date present in PE binaries by only looking
+        #   at the ends of the files
+        # Although this works, a way to set the date would be better.
+        # Removing or zeroing the date stamp in the binary produced by
+        # the linker is not possible as it is required by the target OS.
+        exec tail +140 tmpdir/ld2 >tmpdir/ld2tail
+        exec tail +140 tmpdir/ld3 >tmpdir/ld3tail
+        catch "exec cmp tmpdir/ld2tail tmpdir/ld3tail" exec_output
+        exec rm tmpdir/ld2tail tmpdir/ld3tail
+    } else {
+        send_log "cmp tmpdir/ld2 tmpdir/ld3\n"
+        verbose  "cmp tmpdir/ld2 tmpdir/ld3"
+        catch "exec cmp tmpdir/ld2 tmpdir/ld3" exec_output
+    }
+    set exec_output [prune_warnings $exec_output]
+
+    if [string match "" $exec_output] then {
+	pass $testname
+    } else {
+	send_log "$exec_output\n"
+	verbose "$exec_output" 1
+
+	fail $testname
+    }
+}
+
+catch "exec rm -f tmpdir/ld-partial.o tmpdir/ld1 tmpdir/ld2 tmpdir/ld3" status
+catch "exec rm -f tmpdir/ld1tail tmpdir/ld2tail tmpdir/ld3tail" status
diff --git a/binutils-2.19/ld/testsuite/ld-cdtest/cdtest-bar.cc b/binutils-2.19/ld/testsuite/ld-cdtest/cdtest-bar.cc
new file mode 100644
index 0000000..79000e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cdtest/cdtest-bar.cc
@@ -0,0 +1,17 @@
+// test program for Class Foo
+
+#include "cdtest-foo.h"
+
+static Foo static_foo( "static_foo"); 
+
+Foo f()
+{
+    Foo x;
+    return x;
+}
+
+void g()
+{
+    Foo other_foo1 = Foo( "other_foo1"), other_foo2 = Foo( "other_foo2");
+    other_foo2 = other_foo1;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-cdtest/cdtest-foo.cc b/binutils-2.19/ld/testsuite/ld-cdtest/cdtest-foo.cc
new file mode 100644
index 0000000..d8e5cbe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cdtest/cdtest-foo.cc
@@ -0,0 +1,89 @@
+// Class Foo
+#pragma implementation
+
+
+// We don't use header files, since we only want to see, whether the
+// compiler is installed properly.
+//
+#if (__GNUG__ == 2)
+typedef __SIZE_TYPE__ size_t;
+#else
+typedef unsigned int size_t;
+#endif
+
+extern "C" {
+    char *strncpy (char* dest, const char* src, size_t len);
+    int printf (const char*, ...);
+};
+
+#include "cdtest-foo.h"
+
+int Foo::foos = 0;
+
+void Foo::init_foo ()
+{
+    printf ("BROKENLY calling Foo::init_foo from __init_start; size_of(Foo) = %ld\n", (long) sizeof(Foo));
+    foos = FOOLISH_NUMBER;
+}
+
+
+Foo::Foo ()
+{
+    i = ++foos;
+    strncpy (message, "default-foo", len);
+#ifdef WITH_ADDR
+    printf ("Constructing Foo(%d) \"default-foo\" at %08x\n", i, this);
+#else
+    printf ("Constructing Foo(%d) \"default-foo\"\n", i);
+#endif
+}
+
+Foo::Foo (const char* msg)
+{
+    i = ++foos;
+    strncpy( message, msg, len);
+#ifdef WITH_ADDR
+    printf ( "Constructing Foo(%d) \"%s\" at %08x\n", i, message, this);
+#else
+    printf ( "Constructing Foo(%d) \"%s\"\n", i, message);
+#endif
+}
+
+
+Foo::Foo (const Foo& foo)
+{
+    i = ++foos;
+#ifdef WITH_ADDR
+    printf ("Initializing Foo(%d) \"%s\" at %08x with Foo(%d) %08x\n", 
+	    i, foo.message, this, foo.i, &foo);
+#else
+   printf ("Initializing Foo(%d) \"%s\" with Foo(%d)\n",i, foo.message, foo.i);
+#endif
+    for ( int k = 0; k < FOO_MSG_LEN; k++) message[k] = foo.message[k];
+}
+
+
+Foo& Foo::operator= (const Foo& foo)
+{
+#ifdef WITH_ADDR
+    printf ("Copying Foo(%d) \"%s\" at %08x to Foo(%d) %08x\n", 
+	    foo.i, foo.message, &foo, i, this);
+#else
+   printf ("Copying Foo(%d) \"%s\" to Foo(%d)\n", foo.i, foo.message, i);
+#endif
+    for ( int k = 0; k < FOO_MSG_LEN; k++) message[k] = foo.message[k];
+    return *this;
+}
+
+
+Foo::~Foo ()
+{
+    foos--;
+#ifdef WITH_ADDR
+    printf ("Destructing Foo(%d) \"%s\" at %08x (remaining foos: %d)\n",
+	    i, message, this, foos);
+#else
+    printf ("Destructing Foo(%d) \"%s\" (remaining foos: %d)\n",
+	    i, message, foos);
+#endif
+}
diff --git a/binutils-2.19/ld/testsuite/ld-cdtest/cdtest-foo.h b/binutils-2.19/ld/testsuite/ld-cdtest/cdtest-foo.h
new file mode 100644
index 0000000..f36efb7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cdtest/cdtest-foo.h
@@ -0,0 +1,24 @@
+// Class Foo
+
+#pragma interface
+
+#define FOOLISH_NUMBER -4711
+
+#ifndef FOO_MSG_LEN
+#define FOO_MSG_LEN 80
+#endif
+ 
+class Foo {
+    static int foos;
+    int i;
+    static const int len = FOO_MSG_LEN;
+    char message[len];
+public: 
+    static void init_foo ();
+    static int nb_foos() { return foos; }
+    Foo();
+    Foo(const char* message);
+    Foo(const Foo&);
+    Foo & operator= (const Foo&);
+    ~Foo ();
+}; 
diff --git a/binutils-2.19/ld/testsuite/ld-cdtest/cdtest-main.cc b/binutils-2.19/ld/testsuite/ld-cdtest/cdtest-main.cc
new file mode 100644
index 0000000..bc881da
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cdtest/cdtest-main.cc
@@ -0,0 +1,40 @@
+// main program for Class Foo
+
+extern "C" {
+// Some <assert.h> implementations (e.g. SUNOS 4.1) are broken,
+// in that they require <stdio.h>.  But, if gcc/g++ is installed
+// correctly, you should get gcc's assert.h.
+// If the compile fails, it means the wrong include files are in use!
+#include <assert.h>
+};
+#include "cdtest-foo.h"
+
+extern "C" void __init_start();
+
+extern Foo f(void);
+extern void g(void);
+
+/* This function should *not* be called by the environment.  There is
+   no way in C++ to ``run something after the initializers but before main()''.
+   The library that depends on this (NIHCL) is broken.  -- John Gilmore 
+   We leave this here to test that future changes to the compiler
+   do not re-introduce this losing ``feature''.  */
+void 
+__init_start()
+{
+    Foo::init_foo();
+}
+
+static Foo static_foo( "static_foo"); 
+
+int main() 
+{ 
+    assert (Foo::nb_foos() == 2);
+    Foo automatic_foo( "automatic_foo");
+    Foo bla_foo = f();
+    assert (Foo::nb_foos() == 4);
+    g();
+    assert (Foo::nb_foos() == 4);
+    // `automatic_foo' and `bla_foo' are destructed here 
+} 
+ 
diff --git a/binutils-2.19/ld/testsuite/ld-cdtest/cdtest-nrv.dat b/binutils-2.19/ld/testsuite/ld-cdtest/cdtest-nrv.dat
new file mode 100644
index 0000000..d3f871f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cdtest/cdtest-nrv.dat
@@ -0,0 +1,13 @@
+Constructing Foo(1) "static_foo"
+Constructing Foo(2) "static_foo"
+Constructing Foo(3) "automatic_foo"
+Constructing Foo(4) "default-foo"
+Constructing Foo(5) "other_foo1"
+Constructing Foo(6) "other_foo2"
+Copying Foo(5) "other_foo1" to Foo(6)
+Destructing Foo(6) "other_foo1" (remaining foos: 5)
+Destructing Foo(5) "other_foo1" (remaining foos: 4)
+Destructing Foo(4) "default-foo" (remaining foos: 3)
+Destructing Foo(3) "automatic_foo" (remaining foos: 2)
+Destructing Foo(2) "static_foo" (remaining foos: 1)
+Destructing Foo(1) "static_foo" (remaining foos: 0)
diff --git a/binutils-2.19/ld/testsuite/ld-cdtest/cdtest.dat b/binutils-2.19/ld/testsuite/ld-cdtest/cdtest.dat
new file mode 100644
index 0000000..39be0db
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cdtest/cdtest.dat
@@ -0,0 +1,15 @@
+Constructing Foo(1) "static_foo"
+Constructing Foo(2) "static_foo"
+Constructing Foo(3) "automatic_foo"
+Constructing Foo(4) "default-foo"
+Initializing Foo(5) "default-foo" with Foo(4)
+Destructing Foo(4) "default-foo" (remaining foos: 4)
+Constructing Foo(5) "other_foo1"
+Constructing Foo(6) "other_foo2"
+Copying Foo(5) "other_foo1" to Foo(6)
+Destructing Foo(6) "other_foo1" (remaining foos: 5)
+Destructing Foo(5) "other_foo1" (remaining foos: 4)
+Destructing Foo(5) "default-foo" (remaining foos: 3)
+Destructing Foo(3) "automatic_foo" (remaining foos: 2)
+Destructing Foo(2) "static_foo" (remaining foos: 1)
+Destructing Foo(1) "static_foo" (remaining foos: 0)
diff --git a/binutils-2.19/ld/testsuite/ld-cdtest/cdtest.exp b/binutils-2.19/ld/testsuite/ld-cdtest/cdtest.exp
new file mode 100644
index 0000000..82fbb88
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cdtest/cdtest.exp
@@ -0,0 +1,127 @@
+# Expect script for LD cdtest Tests
+#   Copyright 1993, 1994, 1995, 1997, 2001, 2004, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Jeffrey Wheat (cassidy@cygnus.com)
+# Rewritten by Ian Lance Taylor (ian@cygnus.com)
+#
+
+# Make sure that constructors are handled correctly.
+
+set test1 "cdtest"
+set test2 "cdtest with -Ur"
+
+# This test requires running the executable generated by ld.
+if ![isnative] {
+    return
+}
+
+if { [which $CXX] == 0 } {
+    untested $test1
+    untested $test2
+    return
+}
+
+if {   ![ld_compile "$CXX $CXXFLAGS -fno-exceptions" $srcdir/$subdir/cdtest-foo.cc tmpdir/cdtest-foo.o]
+    || ![ld_compile "$CXX $CXXFLAGS -fno-exceptions" $srcdir/$subdir/cdtest-bar.cc tmpdir/cdtest-bar.o]
+    || ![ld_compile "$CXX $CXXFLAGS -fno-exceptions" $srcdir/$subdir/cdtest-main.cc tmpdir/cdtest-main.o] } {
+    unresolved $test1
+    unresolved $test2
+    return
+}
+
+set expected_output "$srcdir/$subdir/cdtest.dat"
+
+if ![ld_link $ld tmpdir/cdtest {tmpdir/cdtest-foo.o tmpdir/cdtest-bar.o tmpdir/cdtest-main.o}] {
+    fail $test1
+} else {
+    send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
+    verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
+    catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
+
+    if ![string match "" $exec_output] then {
+	send_log "$exec_output\n"
+	verbose "$exec_output" 1
+
+	fail $test1
+    } else {
+	send_log   "diff tmpdir/cdtest.out $expected_output\n"
+	verbose    "diff tmpdir/cdtest.out $expected_output"
+	catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
+	set exec_output [prune_warnings $exec_output]
+
+	if ![string match "" $exec_output] then {
+	    send_log "$exec_output\n"
+	    verbose  "$exec_output" 1
+
+	    send_log "Checking against Named Return Value optimization\n"
+	    verbose  "Checking against Named Return Value optimization" 1
+
+	    set expected_output "$srcdir/$subdir/cdtest-nrv.dat"
+
+	    send_log   "diff tmpdir/cdtest.out $expected_output\n"
+	    verbose    "diff tmpdir/cdtest.out $expected_output"
+	    catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
+	    set exec_output [prune_warnings $exec_output]
+	}
+
+	if [string match "" $exec_output] then {
+	    pass $test1
+	} else {
+	    send_log "$exec_output\n"
+	    verbose  "$exec_output" 1
+
+	    fail $test1
+	}
+    }
+}
+
+if ![ld_relocate $ld tmpdir/cdtest.o {-Ur tmpdir/cdtest-foo.o tmpdir/cdtest-bar.o tmpdir/cdtest-main.o}] {
+    fail $test2
+} else {
+    if ![ld_link $ld tmpdir/cdtest tmpdir/cdtest.o] {
+	fail $test2
+    } else {
+	send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
+	verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
+	catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
+
+	if ![string match "" $exec_output] then {
+	    send_log "$exec_output\n"
+	    verbose  "$exec_output" 1
+
+	    fail $test2
+	} else {
+	    send_log   "diff tmpdir/cdtest.out $expected_output\n"
+	    verbose    "diff tmpdir/cdtest.out $expected_output"
+	    catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
+	    set exec_output [prune_warnings $exec_output]
+
+	    if [string match "" $exec_output] then {
+		pass $test2
+	    } else {
+		send_log "$exec_output\n"
+		verbose  "$exec_output" 1
+
+		fail $test2
+	    }
+	}
+    }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-checks/asm.s b/binutils-2.19/ld/testsuite/ld-checks/asm.s
new file mode 100644
index 0000000..86e7310
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-checks/asm.s
@@ -0,0 +1,11 @@
+ .text
+	.global foo
+foo:
+	.long 0x12345678
+
+ .data
+	.global bar
+bar:
+	.long 0x87654321
+
+	.lcomm dummy, 0x12
diff --git a/binutils-2.19/ld/testsuite/ld-checks/checks.exp b/binutils-2.19/ld/testsuite/ld-checks/checks.exp
new file mode 100644
index 0000000..39e9ac7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-checks/checks.exp
@@ -0,0 +1,82 @@
+# Expect script for LD section checks tests
+#   Copyright 1999, 2001, 2003, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Nick Clifton (nickc@cygnus.com)
+
+proc section_check {} {
+    global ld_flags
+    global as
+    global ld
+    global srcdir
+    global subdir
+    
+    # The usage of .lcomm in asm.s is incompatible with ia64 and ppc coff.
+    if { [istarget ia64-*-*]
+	 || [istarget powerpc*-*-aix*] || [istarget powerpc-*-beos*]
+	 || [istarget rs6000-*-*] } {
+	return
+    }
+    set test "check sections 1"
+    
+    set ldflags "--check-sections"
+
+    if { ![ld_assemble $as $srcdir/$subdir/asm.s tmpdir/asm.o]} {
+	unresolved $test
+	return
+    }
+
+    if ![ld_simple_link $ld tmpdir/asm.x "$ldflags tmpdir/asm.o"] {
+	fail $test
+    } else {
+	pass $test
+    }
+
+    set test "check sections 2"
+
+    # Change the linker flags so that our "buggy" linker
+    # script is used.
+    set ldflags "--check-sections -T $srcdir/$subdir/script -e foo"
+
+    # Perform the equivalent of invoking ld_simple_link
+    # except that we need to massage the output futher.
+    
+    set exec_output [run_host_cmd "$ld" "-o tmpdir/asm.x $ldflags tmpdir/asm.o"]
+    set exec_output [prune_warnings $exec_output]
+
+    # Make sure that we got some output from the linker
+    if [string match "" $exec_output] then {
+	fail $test
+    } 
+
+    # Now remove our expected error message
+    regsub -all ".*: section .data .* overlaps section .text .*" $exec_output "" exec_output
+
+    # And check to see if anything else, (unexpected) was left
+    if [string match "" $exec_output] then {
+	pass $test
+    } else {
+	verbose -log "Unexpected linker message(s): $exec_output"
+	fail $test
+    }
+}
+
+section_check
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-checks/script b/binutils-2.19/ld/testsuite/ld-checks/script
new file mode 100644
index 0000000..44c6a08
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-checks/script
@@ -0,0 +1,6 @@
+SECTIONS {
+        .text 0x100 :             { *(.text) }
+	.data 0x100 : AT (0x100)  { *(.data) }
+	.bss  0x100 : AT (0x4000) { *(.bss)  }
+}
+
diff --git a/binutils-2.19/ld/testsuite/ld-cris/badgotr1.d b/binutils-2.19/ld/testsuite/ld-cris/badgotr1.d
new file mode 100644
index 0000000..7ef7036
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/badgotr1.d
@@ -0,0 +1,11 @@
+#source: gotrel1.s
+#as: --pic --underscore --em=criself
+#ld: -m crislinux -shared
+#objdump: -dr
+#error: ^[^c][^h][^i][^l][^d].* uses _-prefixed .* failed to merge .* no GOT .* Bad value$
+
+# The error regex above is supposed to not match if we get a
+# SEGV, in which case we'll see "child killed: segmentation
+# violation", supposedly at the beginning (seen) or end (in
+# theory) of it.  The input ELF type (with underscores on
+# symbols) mismatches the output type (no underscores).
diff --git a/binutils-2.19/ld/testsuite/ld-cris/comref1.s b/binutils-2.19/ld/testsuite/ld-cris/comref1.s
new file mode 100644
index 0000000..5be25d8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/comref1.s
@@ -0,0 +1,8 @@
+ .text
+y:
+ .comm c1,4,1
+ .comm c2,4,1
+ .comm c3,4,1
+ move.d c1,$r10
+ move.d c2:GOT,$r10
+ move.d c3:PLT,$r10
diff --git a/binutils-2.19/ld/testsuite/ld-cris/cris.exp b/binutils-2.19/ld/testsuite/ld-cris/cris.exp
new file mode 100644
index 0000000..0cb4779
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/cris.exp
@@ -0,0 +1,58 @@
+# Expect script for ld-cris tests
+#   Copyright 2002, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Hans-Peter Nilsson (hp@axis.com)
+#
+
+if ![istarget cris-*-*] {
+    return
+}
+
+set rd_test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+
+# First, execute those tests that are named to indicate that they create a
+# DSO.  Copy the file from the run_dump_test "tmpdir/dump" to a unique
+# expected name.
+# FIXME: Add option "output: filename" to run_dump_test.
+# FIXME: Add option "ldtail: option" to run_dump_test, so we can link
+# libraries in the right order.
+foreach atest $rd_test_list {
+    # We need to check against runtest_file_p too, or we'd mindlessly copy
+    # the last tmpdir/dump in selective test-runs.
+    if { [string match $srcdir/$subdir/*dso-*.d $atest] \
+	    && [runtest_file_p $runtests [file tail $atest]] } {
+	verbose [file rootname $atest]
+	run_dump_test [file rootname $atest]
+	set cmd "cp tmpdir/dump tmpdir/[file rootname [file tail $atest]].so"
+	send_log "$cmd\n"
+	set cmdret [catch "exec $cmd" comp_output]
+	send_log "$comp_output\n"
+	# FIXME: What if it fails?  Need we do something?
+    }
+}
+
+# Then run the ordinary tests.  This round, exclude the dso-* tests.
+foreach atest $rd_test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    if { ! [string match $srcdir/$subdir/*dso-*.d $atest] } {
+	verbose [file rootname $atest]
+	run_dump_test [file rootname $atest]
+    }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-cris/def2.d b/binutils-2.19/ld/testsuite/ld-cris/def2.d
new file mode 100644
index 0000000..ff75d88
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/def2.d
@@ -0,0 +1,10 @@
+#source: start1.s
+#source: stabs1.s
+#source: globsymw1.s
+#target: cris-*-*elf* cris-*-*aout*
+#as: --em=crisaout
+#ld: -mcrisaout
+#objdump: -p
+# Just checking that undef2 links correctly when given a symbol.
+.*:     file format a\.out-cris
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/def3.d b/binutils-2.19/ld/testsuite/ld-cris/def3.d
new file mode 100644
index 0000000..e1ae3c5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/def3.d
@@ -0,0 +1,10 @@
+#source: start1.s
+#source: stabs1.s
+#source: globsymw1.s
+#target: cris-*-*elf* cris-*-*aout*
+#as: --em=criself
+#ld: -mcriself
+#objdump: -p
+# Just checking that undef3 links correctly when given a symbol.
+.*:     file format elf32.*-cris
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/dso-1.s b/binutils-2.19/ld/testsuite/ld-cris/dso-1.s
new file mode 100644
index 0000000..6c621b5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/dso-1.s
@@ -0,0 +1,8 @@
+	.text
+	.global	dsofn
+	.type	dsofn,@function
+	.p2align 1
+dsofn:
+	nop
+.Lfe:
+	.size	dsofn,.Lfe1-dsofn
diff --git a/binutils-2.19/ld/testsuite/ld-cris/dso-2.s b/binutils-2.19/ld/testsuite/ld-cris/dso-2.s
new file mode 100644
index 0000000..f7c38a6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/dso-2.s
@@ -0,0 +1,6 @@
+	.text
+	.global	export_1
+	.type	export_1,@function
+export_1:
+	jump [$r1+dsofn:GOTPLT16]
+	jump [$r1+dsofn:GOTPLT]
diff --git a/binutils-2.19/ld/testsuite/ld-cris/dso-3.s b/binutils-2.19/ld/testsuite/ld-cris/dso-3.s
new file mode 100644
index 0000000..6610504
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/dso-3.s
@@ -0,0 +1,20 @@
+; The visibility definitions here override the default
+; definitions in the object where the symbols are defined.  We
+; check STV_HIDDEN and STV_PROTECTED with function and object
+; definition respectively.  This is by no means a full coverage,
+; just enough to be a test-case for the bug described in
+; libdso-3.d.  Use ld-elfvsb for general visibility tests.
+
+ .hidden expobj
+ .protected expfn
+
+ .text
+ .global globsym
+ .type	globsym,@function
+globsym:
+ move.d	expfn:GOTOFF,$r3
+ move.d	expfn:PLTG,$r3
+ move.d	expfn:PLT,$r3
+ move.d	expobj:GOTOFF,$r3
+.Lfe1:
+ .size	globsym,.Lfe1-globsym
diff --git a/binutils-2.19/ld/testsuite/ld-cris/dsofnf.s b/binutils-2.19/ld/testsuite/ld-cris/dsofnf.s
new file mode 100644
index 0000000..bf0a4fa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/dsofnf.s
@@ -0,0 +1,7 @@
+ .text
+ .global f
+ .type f,@function
+f:
+ move.d [$r0+dsofn:GOT],$r1
+0:
+ .size f,0b-f
diff --git a/binutils-2.19/ld/testsuite/ld-cris/dsofnf2.s b/binutils-2.19/ld/testsuite/ld-cris/dsofnf2.s
new file mode 100644
index 0000000..fbf2384
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/dsofnf2.s
@@ -0,0 +1,8 @@
+ .text
+ .global f
+ .type f,@function
+f:
+ move.d [$r0+dsofn:GOT],$r1
+ move.d dsofn,$r2
+0:
+ .size f,0b-f
diff --git a/binutils-2.19/ld/testsuite/ld-cris/dsov32-1.s b/binutils-2.19/ld/testsuite/ld-cris/dsov32-1.s
new file mode 100644
index 0000000..07a3e9c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/dsov32-1.s
@@ -0,0 +1,8 @@
+	.text
+	.global	dsofn3
+	.type	dsofn3,@function
+dsofn3:
+	bsr	dsofn:PLT
+	nop
+.Lfe1:
+	.size	dsofn3,.Lfe1-dsofn3
diff --git a/binutils-2.19/ld/testsuite/ld-cris/dsov32-2.s b/binutils-2.19/ld/testsuite/ld-cris/dsov32-2.s
new file mode 100644
index 0000000..672f273
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/dsov32-2.s
@@ -0,0 +1,10 @@
+	.text
+	.global	dsofn4
+	.type	dsofn4,@function
+dsofn4:
+	lapc	_GLOBAL_OFFSET_TABLE_,$r0
+	addo.w	expobj:GOT16,$r0,$acr
+	bsr	dsofn4:PLT
+	nop
+.Lfe1:
+	.size	dsofn4,.Lfe1-dsofn4
diff --git a/binutils-2.19/ld/testsuite/ld-cris/dsov32-3.s b/binutils-2.19/ld/testsuite/ld-cris/dsov32-3.s
new file mode 100644
index 0000000..768b06c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/dsov32-3.s
@@ -0,0 +1,8 @@
+	.text
+	.global	dsofn5
+	.type	dsofn5,@function
+dsofn5:
+	bsr	dsofn
+	nop
+.Lfe1:
+	.size	dsofn5,.Lfe1-dsofn5
diff --git a/binutils-2.19/ld/testsuite/ld-cris/dsov32-4.s b/binutils-2.19/ld/testsuite/ld-cris/dsov32-4.s
new file mode 100644
index 0000000..d06768a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/dsov32-4.s
@@ -0,0 +1,14 @@
+	.text
+	.global	dsofn5
+	.type	dsofn5,@function
+dsofn5:
+	bsr	localfn
+	nop
+.Lfe:
+	.size	dsofn5,.Lfe-dsofn5
+
+	.type	localfn,@function
+localfn:
+	nop
+.Lfe1:
+	.size	localfn,.Lfe1-localfn
diff --git a/binutils-2.19/ld/testsuite/ld-cris/euwref1.s b/binutils-2.19/ld/testsuite/ld-cris/euwref1.s
new file mode 100644
index 0000000..5d21f4a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/euwref1.s
@@ -0,0 +1,8 @@
+ .text
+y:
+ .weak uw1
+ .weak uw2
+ .weak uw3
+ move.d uw1,$r10
+ move.d uw2:GOT,$r10
+ move.d uw3:PLT,$r10
diff --git a/binutils-2.19/ld/testsuite/ld-cris/expdref1.s b/binutils-2.19/ld/testsuite/ld-cris/expdref1.s
new file mode 100644
index 0000000..58faa60
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/expdref1.s
@@ -0,0 +1,6 @@
+  .text
+x:
+  move.d expobj:GOT,$r10
+  move.d expobj:PLT,$r10
+  move.d expfn:GOT,$r10
+  move.d expfn:PLT,$r10
diff --git a/binutils-2.19/ld/testsuite/ld-cris/expdyn1.d b/binutils-2.19/ld/testsuite/ld-cris/expdyn1.d
new file mode 100644
index 0000000..51d875d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/expdyn1.d
@@ -0,0 +1,14 @@
+#source: expdyn1.s
+#as: --no-underscore --em=criself
+#ld: -m crislinux -export-dynamic tmpdir/libdso-1.so
+#objdump: -T
+
+.*:     file format elf32-cris
+
+# Exporting dynamic symbols means objects as well as functions.
+
+DYNAMIC SYMBOL TABLE:
+#...
+00080... g    DF .text	0+2 expfn
+00082... g    DO .data	0+4 expobj
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/expdyn1.s b/binutils-2.19/ld/testsuite/ld-cris/expdyn1.s
new file mode 100644
index 0000000..646be85
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/expdyn1.s
@@ -0,0 +1,18 @@
+	.data
+	.global expobj
+	.type	expobj,@object
+	.size	expobj,4
+expobj:
+	.dword 0
+
+	.text
+	.global _start
+_start:
+	nop
+	.global expfn
+expfn:
+	.type	expfn,@function
+	nop
+.Lfe1:
+	.size	expfn,.Lfe1-expfn
+
diff --git a/binutils-2.19/ld/testsuite/ld-cris/expdyn2.d b/binutils-2.19/ld/testsuite/ld-cris/expdyn2.d
new file mode 100644
index 0000000..6c5faa5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/expdyn2.d
@@ -0,0 +1,16 @@
+#source: expdyn1.s
+#source: expdref1.s --pic
+#as: --no-underscore --em=criself
+#ld: -m crislinux --export-dynamic tmpdir/libdso-1.so
+#objdump: -R
+
+# Programs linked with --export-dynamic threw away .rela.got for exported
+# symbols, but since got reference counter wasn't reset, there was a SEGV
+# trying to generate the .rela.got relocations.  In this test, we have an
+# object in the program that has pic-relocations to an exported symbol,
+# but those relocations can be resolved at link-time.  We link to a DSO to
+# get dynamic linking.
+
+.*:     file format elf32-cris
+
+DYNAMIC RELOCATION RECORDS \(none\)
diff --git a/binutils-2.19/ld/testsuite/ld-cris/expdyn3.d b/binutils-2.19/ld/testsuite/ld-cris/expdyn3.d
new file mode 100644
index 0000000..34f2a5e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/expdyn3.d
@@ -0,0 +1,12 @@
+#source: expdyn1.s
+#source: expdref1.s --pic
+#source: euwref1.s --pic
+#as: --no-underscore --em=criself
+#ld: -m crislinux --export-dynamic tmpdir/libdso-1.so
+#objdump: -R
+
+# Like expdyn2.d, but also weakly referencing symbols.
+
+.*:     file format elf32-cris
+
+DYNAMIC RELOCATION RECORDS \(none\)
diff --git a/binutils-2.19/ld/testsuite/ld-cris/expdyn4.d b/binutils-2.19/ld/testsuite/ld-cris/expdyn4.d
new file mode 100644
index 0000000..e932056
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/expdyn4.d
@@ -0,0 +1,12 @@
+#source: expdyn1.s
+#source: expdref1.s --pic
+#source: comref1.s --pic
+#as: --no-underscore --em=criself
+#ld: -m crislinux --export-dynamic tmpdir/libdso-1.so
+#objdump: -R
+
+# Like expdyn2.d, but referencing COMMON symbols.
+
+.*:     file format elf32-cris
+
+DYNAMIC RELOCATION RECORDS \(none\)
diff --git a/binutils-2.19/ld/testsuite/ld-cris/expdyn5.d b/binutils-2.19/ld/testsuite/ld-cris/expdyn5.d
new file mode 100644
index 0000000..5504534
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/expdyn5.d
@@ -0,0 +1,13 @@
+#source: expdyn1.s
+#source: expdref1.s --pic
+#as: --no-underscore --em=criself
+#ld: -m crislinux --export-dynamic tmpdir/libdso-1.so
+#objdump: -s -j .got
+
+# Like expdyn2.d, but testing that the .got contents is correct.  There
+# needs to be a .got due to the GOT relocs, but the entry is constant.
+
+.*:     file format elf32-cris
+Contents of section \.got:
+ 82244 dc210800 00000000 00000000 bf010800  .*
+ 82254 58220800                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-cris/expdyn6.d b/binutils-2.19/ld/testsuite/ld-cris/expdyn6.d
new file mode 100644
index 0000000..43d04ff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/expdyn6.d
@@ -0,0 +1,13 @@
+#source: expdyn1.s
+#source: expdref1.s --pic
+#source: euwref1.s --pic
+#as: --no-underscore --em=criself
+#ld: -m crislinux --export-dynamic tmpdir/libdso-1.so
+#objdump: -s -j .got
+
+# Like expdyn5.d, weakly referencing symbols.
+
+.*:     file format elf32-cris
+Contents of section \.got:
+ 822a0 38220800 00000000 00000000 00000000  .*
+ 822b0 07020800 b8220800                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-cris/expdyn7.d b/binutils-2.19/ld/testsuite/ld-cris/expdyn7.d
new file mode 100644
index 0000000..7bd91e0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/expdyn7.d
@@ -0,0 +1,13 @@
+#source: expdyn1.s
+#source: expdref1.s --pic
+#source: comref1.s --pic
+#as: --no-underscore --em=criself
+#ld: -m crislinux --export-dynamic tmpdir/libdso-1.so
+#objdump: -s -j .got
+
+# Like expdyn5.d, referencing COMMON symbols.
+
+.*:     file format elf32-cris
+Contents of section \.got:
+ 8229c 34220800 00000000 00000000 b8220800  .*
+ 822ac 04020800 b4220800                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-cris/globsym1ref.s b/binutils-2.19/ld/testsuite/ld-cris/globsym1ref.s
new file mode 100644
index 0000000..03d4477
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/globsym1ref.s
@@ -0,0 +1 @@
+ .long globsym1
diff --git a/binutils-2.19/ld/testsuite/ld-cris/globsymw1.s b/binutils-2.19/ld/testsuite/ld-cris/globsymw1.s
new file mode 100644
index 0000000..955014d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/globsymw1.s
@@ -0,0 +1,15 @@
+	.text
+	.stabn	162,0,0,0
+	.global globsym1
+	.type	globsym1, @function
+globsym1:
+	.stabd	46,0,0
+	.stabn	68,0,16,LM0-globsym1
+LM0:
+	.long 0
+	.size	globsym1, .-globsym1
+	.stabs	"",100,0,0,Letext0
+Letext0:
+;# This must be the last line; the point is that the warning symbol
+;# construct is last, but is missing the actual symbol warned about.
+	.stabs "isatty is not implemented and will always fail",30,0,0,0
diff --git a/binutils-2.19/ld/testsuite/ld-cris/globsymw2.s b/binutils-2.19/ld/testsuite/ld-cris/globsymw2.s
new file mode 100644
index 0000000..a9e11ff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/globsymw2.s
@@ -0,0 +1,16 @@
+	.text
+	.stabn	162,0,0,0
+;# A bit like globsymw1.s but containing a valid, working, stabs
+;# symbol warning construct.
+	.stabs "isatty is not implemented and will always fail",30,0,0,0
+	.stabs "globsym1",1,0,0,0
+	.global globsym1
+	.type	globsym1, @function
+globsym1:
+	.stabd	46,0,0
+	.stabn	68,0,16,LM0-globsym1
+LM0:
+	.long 0
+	.size	globsym1, .-globsym1
+	.stabs	"",100,0,0,Letext0
+Letext0:
diff --git a/binutils-2.19/ld/testsuite/ld-cris/gotplt1.d b/binutils-2.19/ld/testsuite/ld-cris/gotplt1.d
new file mode 100644
index 0000000..8fcb7b5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/gotplt1.d
@@ -0,0 +1,48 @@
+#source: dso-2.s
+#source: dsofnf2.s
+#source: gotrel1.s
+#as: --pic --no-underscore --em=criself
+#ld: -m crislinux tmpdir/libdso-1.so
+#objdump: -sR
+
+# Make sure we don't merge a PLT-specific entry
+# (R_CRIS_JUMP_SLOT) with a non-PLT-GOT-specific entry
+# (R_CRIS_GLOB_DAT) in an executable, since they may have
+# different contents there.  (If we merge them in a DSO it's ok:
+# we make a round-trip to the PLT in the executable if it's
+# referenced there, but that's still perceived as better than
+# having an unnecessary PLT, dynamic reloc and lookup in the
+# DSO.)  In the executable, the GOT contents for the non-PLT
+# reloc should be constant.
+
+.*:     file format elf32-cris
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+00082280 R_CRIS_JUMP_SLOT  dsofn
+
+Contents of section .*
+#...
+Contents of section \.rela\.plt:
+ 80190 80220800 0b040000 00000000           .*
+Contents of section \.plt:
+ 8019c fce17e7e 7f0d7822 0800307a 7f0d7c22  .*
+ 801ac 08003009 7f0d8022 08003009 3f7e0000  .*
+ 801bc 00002ffe d8ffffff                    .*
+Contents of section \.text:
+ 801c4 5f1d0c00 30096f1d 0c000000 30090000  .*
+ 801d4 6f0d1000 0000611a 6f2eb001 08000000  .*
+ 801e4 6f3e70df ffff0000                    .*
+Contents of section \.dynamic:
+ 821ec 01000000 01000000 04000000 e4000800  .*
+ 821fc 05000000 5c010800 06000000 0c010800  .*
+ 8220c 0a000000 32000000 0b000000 10000000  .*
+ 8221c 15000000 00000000 03000000 74220800  .*
+ 8222c 02000000 0c000000 14000000 07000000  .*
+ 8223c 17000000 90010800 00000000 00000000  .*
+ 8224c 00000000 00000000 00000000 00000000  .*
+ 8225c 00000000 00000000 00000000 00000000  .*
+ 8226c 00000000 00000000                    .*
+Contents of section \.got:
+ 82274 ec210800 00000000 00000000 b8010800  .*
+ 82284 b0010800                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-cris/gotplt2.d b/binutils-2.19/ld/testsuite/ld-cris/gotplt2.d
new file mode 100644
index 0000000..48f1413
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/gotplt2.d
@@ -0,0 +1,37 @@
+#source: dso-2.s
+#source: dsofnf.s
+#source: gotrel1.s
+#as: --pic --no-underscore --em=criself
+#ld: -shared -m crislinux -z nocombreloc
+#objdump: -sR
+
+# Make sure we merge a PLT-specific entry (usually
+# R_CRIS_JUMP_SLOT) with a GOT-specific entry (R_CRIS_GLOB_DAT)
+# in a DSO.  It's ok: we make a round-trip to the PLT in the
+# executable if it's referenced there, but that's still
+# perceived as better than having an unnecessary PLT, dynamic
+# reloc and lookup in the DSO.)
+
+.*:     file format elf32-cris
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+00002230 R_CRIS_GLOB_DAT   dsofn
+
+Contents of section .*
+#...
+Contents of section \.rela\.got:
+ 0188 30220000 0a080000 00000000           .*
+Contents of section \.text:
+ 0194 5f1d0c00 30096f1d 0c000000 30090000  .*
+ 01a4 6f0d0c00 0000611a 6f3e88df ffff0000  .*
+Contents of section \.dynamic:
+ 21b4 04000000 94000000 05000000 5c010000  .*
+ 21c4 06000000 cc000000 0a000000 2a000000  .*
+ 21d4 0b000000 10000000 07000000 88010000  .*
+ 21e4 08000000 0c000000 09000000 0c000000  .*
+ 21f4 00000000 00000000 00000000 00000000  .*
+ 2204 00000000 00000000 00000000 00000000  .*
+ 2214 00000000 00000000 00000000 00000000  .*
+Contents of section \.got:
+ 2224 b4210000 00000000 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-cris/gotplt3.d b/binutils-2.19/ld/testsuite/ld-cris/gotplt3.d
new file mode 100644
index 0000000..f4cb4be
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/gotplt3.d
@@ -0,0 +1,35 @@
+#source: dso-2.s
+#source: dsofnf.s
+#source: gotrel1.s
+#source: dso-1.s
+#as: --pic --no-underscore --em=criself
+#ld: -shared -m crislinux -z nocombreloc
+#objdump: -sR
+
+# Like gotplt2, but make sure we merge right when we have a
+# definition of the function too.
+
+.*:     file format elf32-cris
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+00002234 R_CRIS_GLOB_DAT   dsofn
+
+Contents of section .*
+#...
+Contents of section \.rela\.got:
+ 0188 34220000 0a080000 00000000           .*
+Contents of section \.text:
+ 0194 5f1d0c00 30096f1d 0c000000 30090000  .*
+ 01a4 6f0d0c00 0000611a 6f3e84df ffff0000  .*
+ 01b4 0f050000                             .*
+Contents of section \.dynamic:
+ 21b8 04000000 94000000 05000000 5c010000  .*
+ 21c8 06000000 cc000000 0a000000 2a000000  .*
+ 21d8 0b000000 10000000 07000000 88010000  .*
+ 21e8 08000000 0c000000 09000000 0c000000  .*
+ 21f8 00000000 00000000 00000000 00000000  .*
+ 2208 00000000 00000000 00000000 00000000  .*
+ 2218 00000000 00000000 00000000 00000000  .*
+Contents of section \.got:
+ 2228 b8210000 00000000 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-cris/gotrel1.s b/binutils-2.19/ld/testsuite/ld-cris/gotrel1.s
new file mode 100644
index 0000000..68f035d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/gotrel1.s
@@ -0,0 +1,4 @@
+	.global _start
+_start:
+localsym:
+	move.d	localsym:GOTOFF,$r3
diff --git a/binutils-2.19/ld/testsuite/ld-cris/gotrel2.s b/binutils-2.19/ld/testsuite/ld-cris/gotrel2.s
new file mode 100644
index 0000000..3f98674
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/gotrel2.s
@@ -0,0 +1,5 @@
+	.text
+	.weak undefweak
+	.global _start
+_start:
+	move.d	[$r0+undefweak:GOT],$r3
diff --git a/binutils-2.19/ld/testsuite/ld-cris/hiddef1.d b/binutils-2.19/ld/testsuite/ld-cris/hiddef1.d
new file mode 100644
index 0000000..b3bd87d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/hiddef1.d
@@ -0,0 +1,28 @@
+#source: gotrel1.s
+#source: hiddef1.s
+#source: hidrefgotplt1.s
+#ld: -shared -m crislinux
+#as: --pic --no-underscore -I$srcdir/$subdir --em=criself
+#readelf: -S -s -r
+
+# Regression test for mishandling of GOTPLT relocs against a
+# hidden symbol, where the reloc is found after the symbol
+# definition.  There should be no PLT, just a single GOT entry
+# from a GOTPLT reloc moved to the .got section.  It's hard to
+# check for absence of a .plt section, so we just check the
+# number of symbols and sections.  When the number of symbols
+# and sections change, make sure that there's no .plt and that
+# dsofn is hidden (not exported as a dynamic symbol).
+
+There are 11 section headers, starting at offset 0x[0-9a-f]+:
+#...
+  \[[ 0-9]+\] \.got              PROGBITS        [0-9a-f]+ [0-9a-f]+ 0+10 04  WA  0   0  4
+#...
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 1 entries:
+#...
+[0-9a-f]+  0+c R_CRIS_RELATIVE                              [0-9a-f]+
+#...
+Symbol table '\.dynsym' contains 6 entries:
+#...
+Symbol table '\.symtab' contains 16 entries:
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/hiddef1.s b/binutils-2.19/ld/testsuite/ld-cris/hiddef1.s
new file mode 100644
index 0000000..ac24c81
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/hiddef1.s
@@ -0,0 +1,2 @@
+ .include "dso-1.s"
+ .hidden dsofn
diff --git a/binutils-2.19/ld/testsuite/ld-cris/hide1 b/binutils-2.19/ld/testsuite/ld-cris/hide1
new file mode 100644
index 0000000..655871d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/hide1
@@ -0,0 +1 @@
+TST1 { global: export_*; local: *; };
diff --git a/binutils-2.19/ld/testsuite/ld-cris/hidrefgotplt1.s b/binutils-2.19/ld/testsuite/ld-cris/hidrefgotplt1.s
new file mode 100644
index 0000000..020ff16
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/hidrefgotplt1.s
@@ -0,0 +1,2 @@
+ .text
+ move.d [$r0+dsofn:GOTPLT],$r1
diff --git a/binutils-2.19/ld/testsuite/ld-cris/ldsym1.d b/binutils-2.19/ld/testsuite/ld-cris/ldsym1.d
new file mode 100644
index 0000000..e8dcd32
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/ldsym1.d
@@ -0,0 +1,20 @@
+# source: expdyn1.s
+# target: cris-*-*elf* cris-*-*aout*
+# as: --em=criself
+# ld: -mcriself
+# objdump: -d
+
+# Note that the linker script symbol __start is set to the same
+# value as _start, and will collate before _start and be chosen
+# as the presentation symbol at disassembly.  Anyway, __start
+# shouldn't hinder disassembly by posing as an object symbol.
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+0+ <(___init__start|__start|__Stext)>:
+   0:	0f05                	nop 
+
+0+2 <expfn>:
+   2:	0f05                	nop 
diff --git a/binutils-2.19/ld/testsuite/ld-cris/libdso-1.d b/binutils-2.19/ld/testsuite/ld-cris/libdso-1.d
new file mode 100644
index 0000000..dec0ccd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/libdso-1.d
@@ -0,0 +1,13 @@
+#source: dso-1.s
+#as: --pic --no-underscore --em=criself
+#ld: --shared -m crislinux
+#objdump: -T
+
+# Just check that we actually got a DSO with the dsofn symbol.
+
+.*:     file format elf32-cris
+
+DYNAMIC SYMBOL TABLE:
+#...
+00000[12].[02468ace] g    DF .text	00000000 dsofn
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/libdso-10.d b/binutils-2.19/ld/testsuite/ld-cris/libdso-10.d
new file mode 100644
index 0000000..43d96bd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/libdso-10.d
@@ -0,0 +1,37 @@
+#source: dso-1.s
+#as: --pic --no-underscore --march=v32 --em=criself
+#ld: --shared -m crislinux
+#objdump: -p -h
+
+# Sanity check; just an empty GOT.
+
+.*:     file format elf32-cris
+
+Program Header:
+    LOAD off    0x0+ vaddr 0x0+ paddr 0x0+ align 2\*\*13
+         filesz 0x0+144 memsz 0x0+144 flags r-x
+    LOAD off    0x0+144 vaddr 0x0+2144 paddr 0x0+2144 align 2\*\*13
+         filesz 0x0+64 memsz 0x0+64 flags rw-
+ DYNAMIC off    0x0+144 vaddr 0x0+2144 paddr 0x0+2144 align 2\*\*2
+         filesz 0x0+58 memsz 0x0+58 flags rw-
+Dynamic Section:
+  HASH.*0x0*94
+  STRTAB.*0x0*120
+  SYMTAB.*0x0*c0
+  STRSZ.*0x0*1f
+  SYMENT.*0x0*10
+private flags = 2: \[v32\]
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 \.hash         0+2c  0+94  0+94  0+94  2\*\*2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  1 \.dynsym       0+60  0+c0  0+c0  0+c0  2\*\*2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  2 \.dynstr       0+1f  0+120  0+120  0+120  2\*\*0
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  3 \.text         0+4  0+140  0+140  0+140  2\*\*1
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  4 \.dynamic      0+58  0+2144  0+2144  0+144  2\*\*2
+                  CONTENTS, ALLOC, LOAD, DATA
+  5 \.got          0+c  0+219c  0+219c  0+19c  2\*\*2
+                  CONTENTS, ALLOC, LOAD, DATA
diff --git a/binutils-2.19/ld/testsuite/ld-cris/libdso-11.d b/binutils-2.19/ld/testsuite/ld-cris/libdso-11.d
new file mode 100644
index 0000000..754edff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/libdso-11.d
@@ -0,0 +1,27 @@
+#source: dso-1.s
+#source: dsov32-1.s
+#as: --pic --no-underscore --march=v32 --em=criself
+#ld: --shared -m crislinux
+#objdump: -s -T
+
+.*:     file format elf32-cris
+
+DYNAMIC SYMBOL TABLE:
+#...
+0+1a0 g    DF \.text	0+8 dsofn3
+#...
+0+19c g    DF \.text	0+ dsofn
+#...
+Contents of section \.rela\.plt:
+ 015c 2c220000 0b060000 00000000           .*
+Contents of section \.plt:
+ 0168 84e20401 7e7a3f7a 04f26ffa bf09b005  .*
+ 0178 00000000 00000000 00006f0d 0c000000  .*
+ 0188 6ffabf09 b0053f7e 00000000 bf0ed4ff  .*
+ 0198 ffffb005                             .*
+Contents of section \.text:
+ 019c b0050000 bfbee2ff ffffb005           .*
+Contents of section \.dynamic:
+#...
+Contents of section \.got:
+ 2220 a8210000 00000000 00000000 8e010000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-cris/libdso-12.d b/binutils-2.19/ld/testsuite/ld-cris/libdso-12.d
new file mode 100644
index 0000000..c8a4f62
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/libdso-12.d
@@ -0,0 +1,51 @@
+#source: expdyn1.s
+#source: dsov32-1.s
+#source: dsov32-2.s
+#as: --pic --no-underscore --march=v32 --em=criself
+#ld: --shared -m crislinux -z nocombreloc
+#objdump: -s -T
+
+# Check for common DSO contents; load of GOT register, branch to
+# function PLT, undefined symbol, GOT reloc.
+
+.*:     file format elf32-cris
+
+DYNAMIC SYMBOL TABLE:
+#...
+0+23e g    DF \.text	0+12 dsofn4
+0+234 g    DF \.text	0+2 expfn
+0+22fc g    DO \.data	0+4 expobj
+#...
+0+236 g    DF \.text	0+8 dsofn3
+#...
+0+      D  \*UND\*	0+ dsofn
+#...
+Contents of section \.rela\.got:
+ 01c0 f8220000 0a040000 00000000           .*
+Contents of section \.rela\.plt:
+ 01cc f0220000 0b020000 00000000 f4220000  .*
+ 01dc 0b0a0000 00000000                    .*
+Contents of section \.plt:
+ 01e4 84e20401 7e7a3f7a 04f26ffa bf09b005  .*
+ 01f4 00000000 00000000 00006f0d 0c000000  .*
+ 0204 6ffabf09 b0053f7e 00000000 bf0ed4ff  .*
+ 0214 ffffb005 6f0d1000 00006ffa bf09b005  .*
+ 0224 3f7e0c00 0000bf0e baffffff b005      .*
+Contents of section \.text:
+ 0232 b005b005 bfbee2ff ffffb005 7f0da620  .*
+ 0242 00005f0d 1400bfbe b6ffffff b0050000  .*
+Contents of section \.dynamic:
+ 2254 04000000 94000000 05000000 84010000  .*
+ 2264 06000000 d4000000 0a000000 3a000000  .*
+ 2274 0b000000 10000000 03000000 e4220000  .*
+ 2284 02000000 18000000 14000000 07000000  .*
+ 2294 17000000 cc010000 07000000 c0010000  .*
+ 22a4 08000000 0c000000 09000000 0c000000  .*
+ 22b4 00000000 00000000 00000000 00000000  .*
+ 22c4 00000000 00000000 00000000 00000000  .*
+ 22d4 00000000 00000000 00000000 00000000  .*
+Contents of section \.got:
+ 22e4 54220000 00000000 00000000 0a020000  .*
+ 22f4 24020000 00000000                    .*
+Contents of section \.data:
+ 22fc 00000000                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-cris/libdso-13.d b/binutils-2.19/ld/testsuite/ld-cris/libdso-13.d
new file mode 100644
index 0000000..4e66a5f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/libdso-13.d
@@ -0,0 +1,30 @@
+#source: dso-1.s
+#source: dsov32-3.s
+#as: --pic --no-underscore --march=v32 --em=criself
+#ld: --shared -m crislinux -z nocombreloc
+#readelf: -d -r
+#warning: relocation R_CRIS_32_PCREL should not be used in a shared object; recompile with -fPIC
+
+# Check that a TEXTREL reloc is correctly generated for PCREL
+# relocations against global symbols.
+# FIXME: Have a textrel-enabling(-disabling) linker option.
+# (Warning always generated unless [other option] warnings are
+# generally disabled.)  Split out the expected readelf output
+# into a separate test using that option.
+
+Dynamic section at offset 0x[0-9a-f][0-9a-f][0-9a-f] contains 10 entries:
+  Tag[ 	]+Type[ 	]+Name/Value
+ 0x0+4 \(HASH\)[ 	]+0x94
+ 0x0+5 \(STRTAB\)[ 	]+0x[12][0-9a-f][0-9a-f]
+ 0x0+6 \(SYMTAB\)[ 	]+0x[0-9a-f][0-9a-f]
+ 0x0+a \(STRSZ\)[ 	]+38 \(bytes\)
+ 0x0+b \(SYMENT\)[ 	]+16 \(bytes\)
+ 0x0+7 \(RELA\)[ 	]+0x[12][0-9a-f][0-9a-f]
+ 0x0+8 \(RELASZ\)[ 	]+12 \(bytes\)
+ 0x0+9 \(RELAENT\)[ 	]+12 \(bytes\)
+ 0x0+16 \(TEXTREL\)[ 	]+0x0
+ 0x0+ \(NULL\)[ 	]+0x0
+
+Relocation section '\.rela\.text' at offset 0x[12][0-9a-f][0-9a-f] contains 1 entries:
+ Offset[ 	]+Info[ 	]+Type[ 	]+Sym\.Value  Sym\. Name \+ Addend
+0+[12][0-9a-f][0-9a-f]  0+[0-9a-f]06 R_CRIS_32_PCREL[ 	]+0+[0-f]+[ 	]+dsofn \+ 6
diff --git a/binutils-2.19/ld/testsuite/ld-cris/libdso-14.d b/binutils-2.19/ld/testsuite/ld-cris/libdso-14.d
new file mode 100644
index 0000000..c0a20e8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/libdso-14.d
@@ -0,0 +1,19 @@
+#source: dso-1.s
+#source: dsov32-4.s
+#as: --pic --no-underscore --march=v32 --em=criself
+#ld: --shared -m crislinux
+#readelf: -d -r
+
+# Checking that a bsr to a non-PLT-decorated nonvisible function
+# doesn't make the DSO textrel.
+
+Dynamic section at offset 0x16c contains 6 entries:
+  Tag[ 	]+Type[ 	]+Name/Value
+ 0x0+4 \(HASH\)[ 	]+0x94
+ 0x0+5 \(STRTAB\)[ 	]+0x134
+ 0x0+6 \(SYMTAB\)[ 	]+0xc4
+ 0x0+a \(STRSZ\)[ 	]+38 \(bytes\)
+ 0x0+b \(SYMENT\)[ 	]+16 \(bytes\)
+ 0x0+ \(NULL\)[ 	]+0x0
+
+There are no relocations in this file.
diff --git a/binutils-2.19/ld/testsuite/ld-cris/libdso-2.d b/binutils-2.19/ld/testsuite/ld-cris/libdso-2.d
new file mode 100644
index 0000000..1417745
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/libdso-2.d
@@ -0,0 +1,58 @@
+#source: dso-1.s
+#source: dso-2.s
+#as: --pic --no-underscore --em=criself
+#ld: --shared -m crislinux --version-script $srcdir/$subdir/hide1
+#readelf: -S -s -r
+
+# Use "dsofn" from dso-1 in a GOTPLT reloc, but hide it in a
+# version script.  This will change the incoming GOTPLT reloc to
+# instead be a (local) GOT reloc.  There are no other .rela.got
+# entries.  This formerly SEGV:ed because .rela.got was created
+# too late to have it mapped to an output section.
+
+There are 13 section headers.*
+#...
+  \[ 1\] \.hash             HASH     .*
+  \[ 2\] \.dynsym           DYNSYM   .*
+  \[ 3\] \.dynstr           STRTAB   .*
+  \[ 4\] \.gnu\.version      VERSYM  .*
+  \[ 5\] \.gnu\.version_d    VERDEF  .*
+  \[ 6\] \.rela\.dyn         RELA    .*
+  \[ 7\] \.text             PROGBITS .*
+  \[ 8\] \.dynamic          DYNAMIC  .*
+  \[ 9\] \.got              PROGBITS .*
+  \[10\] \.shstrtab         STRTAB   .*
+  \[11\] \.symtab           SYMTAB   .*
+  \[12\] \.strtab           STRTAB   .*
+#...
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 1 entries:
+#...
+00002[12][0-9a-f][048c]  0000000c R_CRIS_RELATIVE                              00000150
+#...
+Symbol table '\.dynsym' contains 4 entries:
+   Num:    Value  Size Type    Bind   Vis      Ndx Name
+     0: 0+     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: [0-9a-f]+     0 SECTION LOCAL  DEFAULT    7 
+     2: 0+     0 OBJECT  GLOBAL DEFAULT  ABS TST1
+     3: 0+154     0 FUNC    GLOBAL DEFAULT    7 export_1@@TST1
+
+Symbol table '\.symtab' contains 18 entries:
+   Num:    Value  Size Type    Bind   Vis      Ndx Name
+     0: 0+     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: [0-9a-f]+     0 SECTION LOCAL  DEFAULT    1 
+     2: [0-9a-f]+     0 SECTION LOCAL  DEFAULT    2 
+     3: [0-9a-f]+     0 SECTION LOCAL  DEFAULT    3 
+     4: [0-9a-f]+     0 SECTION LOCAL  DEFAULT    4 
+     5: [0-9a-f]+     0 SECTION LOCAL  DEFAULT    5 
+     6: [0-9a-f]+     0 SECTION LOCAL  DEFAULT    6 
+     7: [0-9a-f]+     0 SECTION LOCAL  DEFAULT    7 
+     8: [0-9a-f]+     0 SECTION LOCAL  DEFAULT    8 
+     9: [0-9a-f]+     0 SECTION LOCAL  DEFAULT    9 
+    10: 0+2..[046c]     0 OBJECT  LOCAL  HIDDEN  ABS _DYNAMIC
+    11: 0+2..[046c]     0 NOTYPE  LOCAL  DEFAULT  ABS __bss_start
+    12: 0+2..[046c]     0 NOTYPE  LOCAL  DEFAULT  ABS _edata
+    13: 0+2..[046c]     0 OBJECT  LOCAL  HIDDEN  ABS _GLOBAL_OFFSET_TABLE_
+    14: 0+2..[046c]     0 NOTYPE  LOCAL  DEFAULT  ABS _end
+    15: 0+150     0 FUNC    LOCAL  DEFAULT    7 dsofn
+    16: 0+     0 OBJECT  GLOBAL DEFAULT  ABS TST1
+    17: 0+154     0 FUNC    GLOBAL DEFAULT    7 export_1
diff --git a/binutils-2.19/ld/testsuite/ld-cris/libdso-3.d b/binutils-2.19/ld/testsuite/ld-cris/libdso-3.d
new file mode 100644
index 0000000..9e18c59
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/libdso-3.d
@@ -0,0 +1,14 @@
+#source: expdyn1.s
+#source: dso-3.s
+#as: --pic --no-underscore --em=criself
+#ld: --shared -m crislinux
+#objdump: -R
+
+# GOTOFF relocs against global symbols with non-default
+# visibility got a linker error.  (A non-default visibility is
+# to be treated as a local definition for the reloc.)  We also
+# make sure we don't get unnecessary dynamic relocations.
+
+.*:     file format elf32-cris
+
+DYNAMIC RELOCATION RECORDS \(none\)
diff --git a/binutils-2.19/ld/testsuite/ld-cris/libdso-4.d b/binutils-2.19/ld/testsuite/ld-cris/libdso-4.d
new file mode 100644
index 0000000..b7cc840
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/libdso-4.d
@@ -0,0 +1,11 @@
+#source: dso-2.s
+#as: --pic --no-underscore --em=criself
+#ld: --shared -m crislinux
+#objdump: -T
+
+# DSO with an undef symbol "dsofn".  See undef1.d.
+
+.*:     file format elf32-cris
+#...
+0+      D  \*UND\*	0+ dsofn
+
diff --git a/binutils-2.19/ld/testsuite/ld-cris/locref1.d b/binutils-2.19/ld/testsuite/ld-cris/locref1.d
new file mode 100644
index 0000000..e38c642
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/locref1.d
@@ -0,0 +1,22 @@
+#as: --no-underscore --pic --em=criself
+#source: expdyn1.s
+#source: locref1.s
+#ld: -m crislinux
+#objdump: -dt
+
+# Referencing a "normal" (non-hidden) symbol with a local-only PIC
+# relocation is ok when building an executable.
+
+.*:     file format elf32-cris
+
+SYMBOL TABLE:
+#...
+0+82084 l     O \.got	0+ \.hidden _GLOBAL_OFFSET_TABLE_
+0+80076 g     F \.text	0+2 expfn
+0+82090 g     O \.data	0+4 expobj
+#...
+Disassembly of section \.text:
+#...
+0+80078 <y>:
+   80078:	6fae f2df ffff  .*
+   8007e:	6fbe 0c00 0000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-cris/locref1.s b/binutils-2.19/ld/testsuite/ld-cris/locref1.s
new file mode 100644
index 0000000..7a29841
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/locref1.s
@@ -0,0 +1,3 @@
+y:
+ move.d expfn:GOTOFF,$r10
+ move.d expobj:GOTOFF,$r11
diff --git a/binutils-2.19/ld/testsuite/ld-cris/locref2.d b/binutils-2.19/ld/testsuite/ld-cris/locref2.d
new file mode 100644
index 0000000..8b51d45
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/locref2.d
@@ -0,0 +1,22 @@
+#as: --no-underscore --pic --em=criself
+#source: gotrel1.s
+#source: locref2.s
+#ld: -m crislinux
+#objdump: -dt
+
+# Referencing an undefined weak (non-hidden) symbol with a local-only
+# PIC relocation is ok when building an executable.
+
+.*:     file format elf32-cris
+
+SYMBOL TABLE:
+#...
+0+82088 l     O \.got	0+ \.hidden _GLOBAL_OFFSET_TABLE_
+0+  w      \*UND\*	0+ expfn
+0+  w      \*UND\*	0+ expobj
+#...
+Disassembly of section \.text:
+#...
+0+8007c <y>:
+   8007c:	6fae 78df f7ff  .*
+   80082:	6fbe 78df f7ff  .*
diff --git a/binutils-2.19/ld/testsuite/ld-cris/locref2.s b/binutils-2.19/ld/testsuite/ld-cris/locref2.s
new file mode 100644
index 0000000..3b407a6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/locref2.s
@@ -0,0 +1,5 @@
+ .weak expfn
+ .weak expobj
+y:
+ move.d expfn:GOTOFF,$r10
+ move.d expobj:GOTOFF,$r11
diff --git a/binutils-2.19/ld/testsuite/ld-cris/move-1.s b/binutils-2.19/ld/testsuite/ld-cris/move-1.s
new file mode 100644
index 0000000..c023285
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/move-1.s
@@ -0,0 +1,3 @@
+ .text
+localsym:
+ moveq 1,$r10
diff --git a/binutils-2.19/ld/testsuite/ld-cris/nodyn4.d b/binutils-2.19/ld/testsuite/ld-cris/nodyn4.d
new file mode 100644
index 0000000..c1af092
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/nodyn4.d
@@ -0,0 +1,19 @@
+#source: expdyn1.s
+#source: expdref1.s --pic
+#source: comref1.s --pic
+#as: --no-underscore --em=criself
+#ld: -m crislinux
+#readelf: -l
+
+# Like expdyn4.d, but no --export-dynamic.  Got a BFD_ASSERT at one time.
+# Check that we get the expected sections.
+
+#...
+There are 2 program headers, .*
+#...
+  LOAD [0-9a-fx ]+ R E 0x2000
+  LOAD [0-9a-fx ]+ RW  0x2000
+#...
+   00     \.text[ ]*
+   01     \.got \.data \.bss[ ]*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/nodyn5.d b/binutils-2.19/ld/testsuite/ld-cris/nodyn5.d
new file mode 100644
index 0000000..28b581e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/nodyn5.d
@@ -0,0 +1,13 @@
+#source: expdyn1.s
+#source: expdref1.s --pic
+#source: comref1.s --pic
+#as: --no-underscore --em=criself
+#ld: -m crislinux
+#objdump: -s -j .got
+
+# Like nodyn4.d, but checking .got contents.
+
+.*:     file format elf32-cris
+Contents of section \.got:
+ 820a4 00000000 00000000 00000000 c0200800  .*
+ 820b4 76000800 bc200800                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-cris/noglob1.d b/binutils-2.19/ld/testsuite/ld-cris/noglob1.d
new file mode 100644
index 0000000..49ca3b6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/noglob1.d
@@ -0,0 +1,9 @@
+#ld:
+#target: cris-*-*elf* cris-*-*aout*
+#objdump: -p
+
+# Check that we can link an object that doesn't have any global symbols;
+# where elf_sym_hashes(bfd) is NULL.
+
+.*:     file format .*-cris
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/noglob1.s b/binutils-2.19/ld/testsuite/ld-cris/noglob1.s
new file mode 100644
index 0000000..62111bf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/noglob1.s
@@ -0,0 +1,4 @@
+; See noglob1.d
+ .text
+x:
+ move.d .,$r0
diff --git a/binutils-2.19/ld/testsuite/ld-cris/noov.d b/binutils-2.19/ld/testsuite/ld-cris/noov.d
new file mode 100644
index 0000000..c591583
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/noov.d
@@ -0,0 +1,13 @@
+#target: cris-*-*elf*
+#ld: --section-start=.text=0xc0010000
+#objdump: -s -j .text
+
+# Check that we don't get a "relocation truncated to fit", when a
+# relocation would overflow if it hadn't been wrapping.  We always
+# want 32-bit-wrapping on a 32-bit target for the benefit of Linux
+# address-mapping macros.
+
+.*:     file format elf32.*-cris
+
+Contents of section \.text:
+ c0010000 04200100 00200100                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-cris/noov.s b/binutils-2.19/ld/testsuite/ld-cris/noov.s
new file mode 100644
index 0000000..88e803f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/noov.s
@@ -0,0 +1,14 @@
+ .text
+ ; Test that this works both with a symbol defined in a section...
+ .dword __Edata+0x40000000
+
+ ; ...as well as absolute symbol (defined outside sections in the
+ ; linker script).
+ .dword __Sdata+0x40000000
+
+ .data
+ ; Make sure we get the same section alignment for *-elf as for *-linux*.
+ .balign 0x2000
+
+ ; Make .data non-empty.
+ .dword 0
diff --git a/binutils-2.19/ld/testsuite/ld-cris/pv32-1.d b/binutils-2.19/ld/testsuite/ld-cris/pv32-1.d
new file mode 100644
index 0000000..16113a2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/pv32-1.d
@@ -0,0 +1,40 @@
+#source: pv32.s
+#as: --march=v32 --no-underscore --em=criself
+#ld: -e here -m crislinux tmpdir/libdso-12.so
+#objdump: -s -T
+
+# Trivial test of linking a program to a v32 DSO.
+
+.*:     file format elf32-cris
+
+DYNAMIC SYMBOL TABLE:
+0+8021e      DF \*UND\*	0+ expfn
+0+82324 g    DO \.bss	0+4 expobj
+0+82324 g    D  \*ABS\*	0+ __bss_start
+0+80238      DF \*UND\*	0+ dsofn3
+0+82324 g    D  \*ABS\*	0+ _edata
+0+82340 g    D  \*ABS\*	0+ _end
+0+80264 g    DF \.text	0+8 dsofn
+
+Contents of section \.interp:
+ 800d4 2f6c6962 2f6c642e 736f2e31 00        .*
+#...
+Contents of section \.rela\.dyn:
+ 801e0 24230800 09020000 00000000           .*
+Contents of section \.rela\.plt:
+ 801ec 1c230800 0b010000 00000000 20230800  .*
+ 801fc 0b040000 00000000                    .*
+Contents of section \.plt:
+ 80204 84e26ffe 14230800 7e7a3f7a 04f26ffa  .*
+ 80214 bf09b005 00000000 00006ffe 1c230800  .*
+ 80224 6ffabf09 b0053f7e 00000000 bf0ed4ff  .*
+ 80234 ffffb005 6ffe2023 08006ffa bf09b005  .*
+ 80244 3f7e0c00 0000bf0e baffffff b005      .*
+Contents of section \.text:
+ 80252 b005bfbe caffffff b005bfbe dcffffff  .*
+ 80262 b0056fae 24230800 b0050000           .*
+Contents of section \.dynamic:
+#...
+Contents of section \.got:
+ 82310 70220800 00000000 00000000 2a020800  .*
+ 82320 44020800                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-cris/pv32.s b/binutils-2.19/ld/testsuite/ld-cris/pv32.s
new file mode 100644
index 0000000..d5ef7c6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/pv32.s
@@ -0,0 +1,24 @@
+	.global here
+	.type	here,@function
+here:
+	nop
+.Lfe3:
+	.size	here,.Lfe3-dsofn
+
+	.type	pfn,@function
+pfn:
+	bsr	expfn
+	nop
+	bsr	dsofn3
+	nop
+.Lfe1:
+	.size	pfn,.Lfe1-pfn
+
+	.global dsofn
+	.type	dsofn,@function
+dsofn:
+	move.d	expobj,$r10
+	nop
+.Lfe2:
+	.size	dsofn,.Lfe2-dsofn
+
diff --git a/binutils-2.19/ld/testsuite/ld-cris/stabs1.s b/binutils-2.19/ld/testsuite/ld-cris/stabs1.s
new file mode 100644
index 0000000..837d69d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/stabs1.s
@@ -0,0 +1,26 @@
+	.stabs	"/x/y/z/",100,0,2,Ltext0
+	.stabs	"/blah/foo.c",100,0,2,Ltext0
+	.text
+Ltext0:
+	.global _xyzzy
+	.type	_xyzzy, @function
+_xyzzy:
+	.stabd	46,0,0
+	.stabn	68,0,95,LM16-_xyzzy
+LM16:
+	.long 0
+	.stabn	68,0,96,LM17-_xyzzy
+LM17:
+	.long globsym1
+	.stabn	68,0,88,LM25-_xyzzy
+LM25:
+	.long 0
+	.size	_xyzzy, .-_xyzzy
+	.stabn	192,0,0,_xyzzy-_xyzzy
+	.stabn	224,0,0,Lscope0-_xyzzy
+Lscope0:
+;# This is the stabs construct that was barfed upon; BFD for
+;# a.out expects it to be of two parts, like the construct at
+;# the top of this file.
+	.stabs	"",100,0,0,Letext0
+Letext0:
diff --git a/binutils-2.19/ld/testsuite/ld-cris/start1.s b/binutils-2.19/ld/testsuite/ld-cris/start1.s
new file mode 100644
index 0000000..ef09d37
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/start1.s
@@ -0,0 +1,5 @@
+ .global _start
+_start:
+; This must be compilable with --march=common_v10_v32.
+ moveq 1,r11
+
diff --git a/binutils-2.19/ld/testsuite/ld-cris/undef1.d b/binutils-2.19/ld/testsuite/ld-cris/undef1.d
new file mode 100644
index 0000000..70d007e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/undef1.d
@@ -0,0 +1,13 @@
+#source: dso-1.s
+#source: gotrel1.s --pic
+#as: --no-underscore --em=criself
+#ld: -m crislinux tmpdir/libdso-4.so
+#objdump: -T
+
+# The DSO used has an undef reference to the symbol "dsofn", which is
+# supposed to cause the program to automatically export it as a dynamic
+# symbol; no --export-dynamic is supposed to be needed.
+
+#...
+[0-9a-f]+ g    DF .text	00000000 dsofn
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/undef2.d b/binutils-2.19/ld/testsuite/ld-cris/undef2.d
new file mode 100644
index 0000000..46015c0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/undef2.d
@@ -0,0 +1,6 @@
+# source: start1.s
+# source: stabs1.s
+# target: cris-*-*elf* cris-*-*aout*
+# as: --em=crisaout
+# ld: -mcrisaout
+# error: .o:/blah/foo.c:96: undefined reference to `globsym1'$
diff --git a/binutils-2.19/ld/testsuite/ld-cris/undef3.d b/binutils-2.19/ld/testsuite/ld-cris/undef3.d
new file mode 100644
index 0000000..e7bca10
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/undef3.d
@@ -0,0 +1,6 @@
+#source: start1.s
+#source: stabs1.s
+#target: cris-*-*elf* cris-*-*aout*
+#as: --em=criself
+#ld: -mcriself
+#error: .o:/blah/foo.c:96: undefined reference to `globsym1'$
diff --git a/binutils-2.19/ld/testsuite/ld-cris/v10-v32.d b/binutils-2.19/ld/testsuite/ld-cris/v10-v32.d
new file mode 100644
index 0000000..d692926
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/v10-v32.d
@@ -0,0 +1,10 @@
+# notarget: cris*-*-linux-gnu
+# source: start1.s --march=v32
+# source: move-1.s --march=v0_v10
+# as: --em=criself
+# ld: -m criself
+# error: contains non-CRIS-v32 code
+
+# Test that linking a (classic) v10 object to a v32 object does
+# not work.  Source code and "-m criself" doesn't work with *-linux-gnu.
+
diff --git a/binutils-2.19/ld/testsuite/ld-cris/v10-va.d b/binutils-2.19/ld/testsuite/ld-cris/v10-va.d
new file mode 100644
index 0000000..c6db037
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/v10-va.d
@@ -0,0 +1,14 @@
+# notarget: cris*-*-linux-gnu
+# source: start1.s --march=common_v10_v32
+# source: move-1.s --march=v0_v10
+# as: --em=criself
+# ld: -m criself
+# objdump: -p
+
+# Test that linking a v10 compatible object to a v10+v32 object
+# does work and results in the output marked as a v10 object.
+# Source code and "-m criself" doesn't work with *-linux-gnu.
+
+#...
+private flags = 1: \[symbols have a _ prefix\]
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/v32-ba-1.d b/binutils-2.19/ld/testsuite/ld-cris/v32-ba-1.d
new file mode 100644
index 0000000..b4ce78d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/v32-ba-1.d
@@ -0,0 +1,20 @@
+# notarget: cris*-*-linux-gnu
+# as: --march=v32 --em=criself
+# ld: -m criself
+# objdump: -d
+
+# Check that 32-bit branches (PCREL:s) are relocated right.
+# Source code and "-m criself" doesn't work with *-linux-gnu.
+
+.*:     file format elf32-us-cris
+
+Disassembly of section \.text:
+
+0+ <(a|__Stext)>:
+   0:	bf0e 0800 0000      	ba 8 <b>
+   6:	5e82                	moveq 30,r8
+
+0+8 <b>:
+   8:	4312                	moveq 3,r1
+   a:	bf0e f6ff ffff      	ba 0 <[^>]*>
+  10:	4db2                	moveq 13,r11
diff --git a/binutils-2.19/ld/testsuite/ld-cris/v32-ba-1.s b/binutils-2.19/ld/testsuite/ld-cris/v32-ba-1.s
new file mode 100644
index 0000000..189769e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/v32-ba-1.s
@@ -0,0 +1,11 @@
+ .global a
+a:
+ ba b
+ moveq 30,r8
+
+ .section .text.2,"ax"
+ .global b
+b:
+ moveq 3,r1
+ ba a
+ moveq 13,r11
diff --git a/binutils-2.19/ld/testsuite/ld-cris/v32-bin-1.d b/binutils-2.19/ld/testsuite/ld-cris/v32-bin-1.d
new file mode 100644
index 0000000..3a8714b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/v32-bin-1.d
@@ -0,0 +1,13 @@
+#notarget: cris*-*-linux-gnu
+#as: --em=criself --march=v32
+#ld: -m criself --oformat binary --defsym ext1=0x4000 --defsym ext2=0x6000
+#objdump: -s -b binary
+
+# Test that pcrel relocs work with --oformat binary.
+# Source code and "-m criself" doesn't work with *-linux-gnu.
+
+.*:     file format binary
+
+Contents of section \.data:
+ 0000 7f5d0020 0000bfbe fa7f0000 b0057f3d  .*
+ 0010 f23f0000 bfbeec5f 0000b005           .*
diff --git a/binutils-2.19/ld/testsuite/ld-cris/v32-bin-1.s b/binutils-2.19/ld/testsuite/ld-cris/v32-bin-1.s
new file mode 100644
index 0000000..1f021d8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/v32-bin-1.s
@@ -0,0 +1,7 @@
+x:
+ lapc 0x2000,r5
+ bsr 0x8000
+ nop
+ lapc ext1,r3
+ bsr ext2
+ nop
diff --git a/binutils-2.19/ld/testsuite/ld-cris/v32-v10.d b/binutils-2.19/ld/testsuite/ld-cris/v32-v10.d
new file mode 100644
index 0000000..a96120f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/v32-v10.d
@@ -0,0 +1,10 @@
+# notarget: cris*-*-linux-gnu
+# source: start1.s --march=v0_v10
+# source: move-1.s --march=v32
+# as: --em=criself
+# ld: -m criself
+# error: contains CRIS v32 code
+
+# Test that linking a v32 object to a (classic) v10 object does
+# not work.
+# Source code and "-m criself" doesn't work with *-linux-gnu.
diff --git a/binutils-2.19/ld/testsuite/ld-cris/v32-va.d b/binutils-2.19/ld/testsuite/ld-cris/v32-va.d
new file mode 100644
index 0000000..526d3c3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/v32-va.d
@@ -0,0 +1,14 @@
+# notarget: cris*-*-linux-gnu
+# source: start1.s --march=common_v10_v32
+# source: move-1.s --march=v32
+# as: --em=criself
+# ld: -m criself
+# objdump: -p
+
+# Test that linking a v32 object to a v10+v32 object
+# does work and results in the output marked as a v32 object.
+# Source code and "-m criself" doesn't work with *-linux-gnu.
+
+#...
+private flags = 3: \[symbols have a _ prefix\] \[v32\]
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/va-v10.d b/binutils-2.19/ld/testsuite/ld-cris/va-v10.d
new file mode 100644
index 0000000..d6bda58
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/va-v10.d
@@ -0,0 +1,14 @@
+# notarget: cris*-*-linux-gnu
+# source: start1.s --march=v0_v10
+# source: move-1.s --march=common_v10_v32
+# as: --em=criself
+# ld: -m criself
+# objdump: -p
+
+# Test that linking a v10+v32 compatible object to a v10 object
+# does work and results in the output marked as a v10 object.
+# Source code and "-m criself" doesn't work with *-linux-gnu.
+
+#...
+private flags = 1: \[symbols have a _ prefix\]
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/va-v32.d b/binutils-2.19/ld/testsuite/ld-cris/va-v32.d
new file mode 100644
index 0000000..b598ff5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/va-v32.d
@@ -0,0 +1,14 @@
+# notarget: cris*-*-linux-gnu
+# source: start1.s --march=v32
+# source: move-1.s --march=common_v10_v32
+# as: --em=criself
+# ld: -m criself
+# objdump: -p
+
+# Test that linking a v10+v32 compatible object to a v32 object
+# does work and results in the output marked as a v32 object.
+# Source code and "-m criself" doesn't work with *-linux-gnu.
+
+#...
+private flags = 3: \[symbols have a _ prefix\] \[v32\]
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/warn1.d b/binutils-2.19/ld/testsuite/ld-cris/warn1.d
new file mode 100644
index 0000000..ecdf19e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/warn1.d
@@ -0,0 +1,11 @@
+#source: start1.s
+#source: globsym1ref.s
+#source: globsymw1.s
+#target: cris-*-*elf* cris-*-*aout*
+#as: --em=crisaout
+#ld: -mcrisaout
+#objdump: -p
+# There should be no warning, since the symbol warned about is
+# missing from the construct.
+.*:     file format a\.out-cris
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/warn2.d b/binutils-2.19/ld/testsuite/ld-cris/warn2.d
new file mode 100644
index 0000000..96f089e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/warn2.d
@@ -0,0 +1,11 @@
+#source: start1.s
+#source: globsym1ref.s
+#source: globsymw1.s
+#target: cris-*-*elf* cris-*-*aout*
+#as: --em=criself
+#ld: -mcriself
+#objdump: -p
+# There should be no warning, since the symbol warned about is
+# missing from the construct.
+.*:     file format elf32.*-cris
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/warn3.d b/binutils-2.19/ld/testsuite/ld-cris/warn3.d
new file mode 100644
index 0000000..c01b6cb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/warn3.d
@@ -0,0 +1,10 @@
+#source: start1.s
+#source: globsym1ref.s
+#source: globsymw2.s
+#target: cris-*-*elf* cris-*-*aout*
+#as: --em=crisaout
+#ld: -mcrisaout
+#warning: warning: isatty is not implemented and will always fail$
+#objdump: -p
+.*:     file format a\.out-cris
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/warn4.d b/binutils-2.19/ld/testsuite/ld-cris/warn4.d
new file mode 100644
index 0000000..dc096b6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/warn4.d
@@ -0,0 +1,13 @@
+#source: start1.s
+#source: globsym1ref.s
+#source: globsymw2.s
+#target: cris-*-*elf* cris-*-*aout*
+#as: --em=criself
+#ld: -mcriself
+#warning: warning: isatty is not implemented and will always fail$
+#objdump: -p
+#xfail: *-*-*
+# The test is xfailed because ELF stabs doesn't handle the stabs
+# warning construct.
+.*:     file format elf32.*-cris
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-cris/weakref1.d b/binutils-2.19/ld/testsuite/ld-cris/weakref1.d
new file mode 100644
index 0000000..6dab5e4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/weakref1.d
@@ -0,0 +1,17 @@
+#source: gotrel2.s
+#as: --pic --no-underscore --em=criself
+#ld: -m crislinux tmpdir/libdso-1.so
+#objdump: -R
+
+# A dynamic reloc for an undefined weak reference in a program got a
+# confused symbol reference count mismatch with a bfd assertion.  Linking
+# with a DSO was needed as a catalyst to get to the faulty code; nothing
+# in the DSO was needed.  We just check that we don't get the bfd
+# assertion.  Note that no actual dynamic reloc is created for the
+# unresolved weak.  Perhaps it should; the symbol could be defined in a
+# preloaded object or a new version of the DSO.  FIXME: Revisit and adjust
+# test-result.
+
+.*:     file format elf32-cris
+
+DYNAMIC RELOCATION RECORDS \(none\)
diff --git a/binutils-2.19/ld/testsuite/ld-cris/weakref2.d b/binutils-2.19/ld/testsuite/ld-cris/weakref2.d
new file mode 100644
index 0000000..b78ccca
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cris/weakref2.d
@@ -0,0 +1,10 @@
+#source: gotrel2.s
+#as: --pic --no-underscore --em=criself
+#ld: -m crislinux tmpdir/libdso-1.so
+#objdump: -s -j .got
+
+# Like weakref1.d, but check contents of .got.
+
+.*:     file format elf32-cris
+Contents of section \.got:
+ 821e4 7c210800 00000000 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-crx/crx.exp b/binutils-2.19/ld/testsuite/ld-crx/crx.exp
new file mode 100644
index 0000000..af0d1c4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/crx.exp
@@ -0,0 +1,35 @@
+# Expect script for ld-crx tests
+# Copyright 2004, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Tomer Levi, Tomer.Levi@nsc.com
+#
+
+# Test CRX
+
+if ![istarget crx-*-*] {
+    return
+}
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach test $test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname $test]
+    run_dump_test [file rootname $test]
+}
diff --git a/binutils-2.19/ld/testsuite/ld-crx/crx.ld b/binutils-2.19/ld/testsuite/ld-crx/crx.ld
new file mode 100644
index 0000000..703b934
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/crx.ld
@@ -0,0 +1,84 @@
+/* 8 bit data address relocations (R_CRX_NUM8).  */
+d8 = 0x12;
+/* 16 bit data address relocations (R_CRX_NUM16).  */
+d16 = 0x1234;
+/* 32 bit data address relocations (R_CRX_NUM32).  */
+d32 = 0x12345678;
+
+SECTIONS
+{
+/* 4 bit relocations:
+   Relative address (R_CRX_REL4) : 0x6 + 2 = 0x8
+*/
+  .text_4 0xa :
+  { 
+	*(.text_4)   
+	foo4 = (. + 0x6);
+  }
+
+/* 8 bit relocations:
+   Relative address (R_CRX_REL8): 0x10 + 2 = 0x12
+   Relative address (R_CRX_REL8_CMP) : 0x10 + 4 = 0x14
+*/
+  .text_8 0xe0 :
+  { 
+	*(.text_8)   
+	foo8 = (. + 0x10);
+  }
+
+/* 12 bit relocations:
+   Absolute address (R_CRX_REGREL12) : 0x0101 + 0x700 + 4 = 0x805
+*/
+  .text_12 0x0101 :
+  { 
+	*(.text_12)   
+	foo12 = (. + 0x700);
+  }
+
+/* 16 bit relocations:
+   Relative address (R_CRX_REL16) : 0x1000 + 4 = 0x1004
+   Absolute address (R_CRX_IMM16) : 0x01010 + 0x1000 + 4 = 0x2014
+*/
+  .text_16 0x01010 :
+  { 
+	*(.text_16)   
+	foo16 = (. + 0x1000);
+  }
+
+/* 22 bit relocations:
+   Absolute address (R_CRX_REGREL22) : 0x0201400 + 0x100000 + 6 = 0x301406
+*/
+  .text_22 0x0201400 :
+  { 
+	*(.text_22)   
+	foo22 = (. + 0x100000);
+  }
+
+/* 24 bit relocations:
+   Relative address (R_CRX_REL24) : 0xe00000 + 6 = 0xe00006
+*/
+  .text_24 0x0f01400 :
+  { 
+	*(.text_24)   
+	foo24 = (. + 0xe00000);
+  }
+
+/* 28 bit relocations:
+   Absolute address (R_CRX_REGREL28) : 0x06201400 + 0x3100000 + 6 = 0x9301406
+*/
+  .text_28 0x06201400 :
+  { 
+	*(.text_28)   
+	foo28 = (. + 0x3100000);
+  }
+
+/* 32 bit relocations:
+   Absolute address (R_CRX_ABS32, R_CRX_IMM32) : 0x11014000 + 0x11000000 + 6 = 0x22014006
+   Relative address (R_CRX_REL32) : 0x11000000 + 6 = 0x11000006
+*/
+  .text_32 0x11014000 :
+  { 
+	*(.text_32)   
+	foo32 = (. + 0x11000000);
+  }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-abs32.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-abs32.d
new file mode 100644
index 0000000..c4bd8cf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-abs32.d
@@ -0,0 +1,13 @@
+#source: reloc-abs32.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test absolute relocation R_CRX_ABS32
+
+.*:     file format elf32-crx
+
+Disassembly of section .text_32:
+
+11014000 <_start>:
+11014000:	01 33 01 22 	loadb	0x22014006 [-_<>+0-9a-z]*, r1
+11014004:	06 40 
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-abs32.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-abs32.s
new file mode 100644
index 0000000..40ead76
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-abs32.s
@@ -0,0 +1,7 @@
+# Test absolute relocation R_CRX_ABS32
+
+	.section	.text_32,"ax","progbits"
+	.global _start
+_start:
+	loadb foo32, r1
+
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-imm16.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-imm16.d
new file mode 100644
index 0000000..31aab63
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-imm16.d
@@ -0,0 +1,12 @@
+#source: reloc-imm16.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test immediate relocation R_CRX_IMM16
+
+.*:     file format elf32-crx
+
+Disassembly of section .text_16:
+
+00001010 <_start>:
+    1010:	ee 11 14 20 	addw	\$0x2014, r14
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-imm16.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-imm16.s
new file mode 100644
index 0000000..3e0cc2e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-imm16.s
@@ -0,0 +1,7 @@
+# Test immediate relocation R_CRX_IMM16
+
+	.section	.text_16,"ax","progbits"
+	.global _start
+_start:
+	addw $foo16 , ra
+
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-imm32.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-imm32.d
new file mode 100644
index 0000000..9831a68
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-imm32.d
@@ -0,0 +1,13 @@
+#source: reloc-imm32.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test immediate relocation R_CRX_IMM32
+
+.*:     file format elf32-crx
+
+Disassembly of section .text_32:
+
+11014000 <_start>:
+11014000:	f6 21 01 22 	addd	\$0x22014006, r6
+11014004:	06 40 
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-imm32.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-imm32.s
new file mode 100644
index 0000000..ccf71be
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-imm32.s
@@ -0,0 +1,7 @@
+# Test immediate relocation R_CRX_IMM32
+
+	.section	.text_32,"ax","progbits"
+	.global _start
+_start:
+	addd $foo32, r6
+
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-num16.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-num16.d
new file mode 100644
index 0000000..72bf342
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-num16.d
@@ -0,0 +1,12 @@
+#source: reloc-num16.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test relocation on data R_CRX_NUM16
+
+.*:     file format elf32-crx
+
+Disassembly of section .text:
+
+.* <_start>:
+.*:	34 12       	addcw	\$0x3, r4
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-num16.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-num16.s
new file mode 100644
index 0000000..ff033e1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-num16.s
@@ -0,0 +1,6 @@
+# Test relocation on data R_CRX_NUM16
+
+	.text
+	.global _start
+_start:
+	.word d16
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-num32.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-num32.d
new file mode 100644
index 0000000..bdd9ee9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-num32.d
@@ -0,0 +1,13 @@
+#source: reloc-num32.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test relocation on data R_CRX_NUM32
+
+.*:     file format elf32-crx
+
+Disassembly of section .text:
+
+.* <_start>:
+.*:	78 56       	orw	r7, r8
+.*:	34 12       	addcw	\$0x3, r4
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-num32.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-num32.s
new file mode 100644
index 0000000..201682c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-num32.s
@@ -0,0 +1,6 @@
+# Test relocation on data R_CRX_NUM32
+
+	.text
+	.global _start
+_start:
+	.long d32
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-num8.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-num8.d
new file mode 100644
index 0000000..38927de
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-num8.d
@@ -0,0 +1,12 @@
+#source: reloc-num8.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test relocation on data R_CRX_NUM8
+
+.*:     file format elf32-crx
+
+Disassembly of section .text:
+
+.* <_start>:
+.*:	12 00       	addub	\$0x1, r2
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-num8.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-num8.s
new file mode 100644
index 0000000..4dc70b5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-num8.s
@@ -0,0 +1,6 @@
+# Test relocation on data R_CRX_NUM8
+
+	.text
+	.global _start
+_start:
+	.byte d8
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel12.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel12.d
new file mode 100644
index 0000000..e681d9f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel12.d
@@ -0,0 +1,12 @@
+#source: reloc-regrel12.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test register relative relocation R_CRX_REGREL12
+
+.*:     file format elf32-crx
+
+Disassembly of section .text_12:
+
+00000101 <_start>:
+ 101:	85 32 05 78 	loadb	0x805\(r7\)\+, r5
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel12.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel12.s
new file mode 100644
index 0000000..060502b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel12.s
@@ -0,0 +1,6 @@
+# Test register relative relocation R_CRX_REGREL12
+
+	.section	.text_12,"ax","progbits"
+	.global _start
+_start:
+	loadb foo12(r7)+, r5
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel22.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel22.d
new file mode 100644
index 0000000..7c4ba1b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel22.d
@@ -0,0 +1,13 @@
+#source: reloc-regrel22.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test register relative relocation R_CRX_REGREL22
+
+.*:     file format elf32-crx
+
+Disassembly of section .text_22:
+
+00201400 <_start>:
+  201400:	cd 33 70 9c 	loadb	0x301406\(r9,r12,2\), r13
+  201404:	06 14 
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel22.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel22.s
new file mode 100644
index 0000000..478b5e2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel22.s
@@ -0,0 +1,6 @@
+# Test register relative relocation R_CRX_REGREL22
+
+	.section	.text_22,"ax","progbits"
+	.global _start
+_start:
+	loadb foo22(r9,r12,2), r13
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel28.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel28.d
new file mode 100644
index 0000000..057118b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel28.d
@@ -0,0 +1,13 @@
+#source: reloc-regrel28.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test register relative relocation R_CRX_REGREL28
+
+.*:     file format elf32-crx
+
+Disassembly of section .text_28:
+
+06201400 <_start>:
+ 6201400:	7f 3b 30 99 	cbitd	\$0x1f, 0x9301406\(r9\)
+ 6201404:	06 14 
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel28.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel28.s
new file mode 100644
index 0000000..2be418f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel28.s
@@ -0,0 +1,6 @@
+# Test register relative relocation R_CRX_REGREL28
+
+	.section	.text_28,"ax","progbits"
+	.global _start
+_start:
+	cbitd $31, foo28(r9)
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel32.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel32.d
new file mode 100644
index 0000000..9022520
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel32.d
@@ -0,0 +1,13 @@
+#source: reloc-regrel32.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test register relative relocation R_CRX_REGREL32
+
+.*:     file format elf32-crx
+
+Disassembly of section .text_32:
+
+11014000 <_start>:
+11014000:	f5 87 01 22 	loadb	0x22014006\(r5\), r7
+11014004:	06 40 
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel32.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel32.s
new file mode 100644
index 0000000..dcfc0cd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-regrel32.s
@@ -0,0 +1,6 @@
+# Test register relative relocation R_CRX_REGREL32
+
+	.section	.text_32,"ax","progbits"
+	.global _start
+_start:
+	loadb foo32(r5), r7
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-rel16.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel16.d
new file mode 100644
index 0000000..15b820e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel16.d
@@ -0,0 +1,12 @@
+#source: reloc-rel16.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test pc relative relocation R_CRX_REL16
+
+.*:     file format elf32-crx
+
+Disassembly of section .text_16:
+
+00001010 <_start>:
+    1010:	7e 30 02 08 	bal	r14, 0x[0-9a-f]* [-_<>+0-9a-z]*
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-rel16.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel16.s
new file mode 100644
index 0000000..65ec197
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel16.s
@@ -0,0 +1,8 @@
+# Test pc relative relocation R_CRX_REL16
+
+	.section	.text_16,"ax","progbits"
+	.global _start
+	.global foo16
+_start:
+	bal ra, foo16
+foo16:
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-rel24.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel24.d
new file mode 100644
index 0000000..c72af5a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel24.d
@@ -0,0 +1,13 @@
+#source: reloc-rel24.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test pc relative relocation R_CRX_REL24
+
+.*:     file format elf32-crx
+
+Disassembly of section .text_24:
+
+00f01400 <_start>:
+  f01400:	81 31 70 20 	cmpbeqb	r1, r2, 0x[0-9a-f]* [-_<>+0-9a-z]*
+  f01404:	03 00 
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-rel24.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel24.s
new file mode 100644
index 0000000..e772ddd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel24.s
@@ -0,0 +1,6 @@
+# Test pc relative relocation R_CRX_REL24
+
+	.section	.text_24,"ax","progbits"
+	.global _start
+_start:
+	cmpbeqb r1, r2, foo24
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-rel32.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel32.d
new file mode 100644
index 0000000..31f462b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel32.d
@@ -0,0 +1,13 @@
+#source: reloc-rel32.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test pc relative relocation R_CRX_REL32
+
+.*:     file format elf32-crx
+
+Disassembly of section .text_32:
+
+11014000 <_start>:
+11014000:	7f 7e 80 08 	br	0x[0-9a-f]* [-_<>+0-9a-z]*
+11014004:	03 00 
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-rel32.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel32.s
new file mode 100644
index 0000000..6b010a9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel32.s
@@ -0,0 +1,6 @@
+# Test pc relative relocation R_CRX_REL32
+
+	.section	.text_32,"ax","progbits"
+	.global _start
+_start:
+	br foo32
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-rel4.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel4.d
new file mode 100644
index 0000000..be9ff36
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel4.d
@@ -0,0 +1,12 @@
+#source: reloc-rel4.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test pc relative relocation R_CRX_REL4
+
+.*:     file format elf32-crx
+
+Disassembly of section .text_4:
+
+0000000a <_start>:
+   a:	3a b0       	beq0b	r10, 0x8 [-_<>+0-9a-z]*
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-rel4.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel4.s
new file mode 100644
index 0000000..138f6b6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel4.s
@@ -0,0 +1,8 @@
+# Test pc relative relocation R_CRX_REL4
+
+	.section	.text_4,"ax","progbits"
+	.global _start
+	.global foo4
+_start:
+	beq0b r10 , foo4
+foo4:
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-rel8-cmp.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel8-cmp.d
new file mode 100644
index 0000000..2d1a245
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel8-cmp.d
@@ -0,0 +1,12 @@
+#source: reloc-rel8-cmp.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test pc relative relocation R_CRX_REL8_CMP
+
+.*:     file format elf32-crx
+
+Disassembly of section .text_8:
+
+000000e0 <_start>:
+  e0:	81 30 0a 20 	cmpbeqb	r1, r2, 0x[0-9a-f]* [-_<>+0-9a-z]*
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-rel8-cmp.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel8-cmp.s
new file mode 100644
index 0000000..61e5dd4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel8-cmp.s
@@ -0,0 +1,8 @@
+# Test pc relative relocation R_CRX_REL8_CMP
+
+	.section	.text_8,"ax","progbits"
+	.global _start
+	.global foo8
+_start:
+	cmpbeqb r1, r2, foo8
+foo8:
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-rel8.d b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel8.d
new file mode 100644
index 0000000..d76ec63
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel8.d
@@ -0,0 +1,12 @@
+#source: reloc-rel8.s
+#ld: -T $srcdir/$subdir/crx.ld
+#objdump: -D
+
+# Test pc relative relocation R_CRX_REL8
+
+.*:     file format elf32-crx
+
+Disassembly of section .text_8:
+
+000000e0 <_start>:
+  e0:	09 70       	beq	0x[0-9a-f]* [-_<>+0-9a-z]*
diff --git a/binutils-2.19/ld/testsuite/ld-crx/reloc-rel8.s b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel8.s
new file mode 100644
index 0000000..9692f3c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-crx/reloc-rel8.s
@@ -0,0 +1,8 @@
+# Test pc relative relocation R_CRX_REL8
+
+	.section	.text_8,"ax","progbits"
+	.global _start
+	.global foo8
+_start:
+	beq foo8
+foo8:
diff --git a/binutils-2.19/ld/testsuite/ld-cygwin/exe-export.exp b/binutils-2.19/ld/testsuite/ld-cygwin/exe-export.exp
new file mode 100644
index 0000000..5fd3cf7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cygwin/exe-export.exp
@@ -0,0 +1,154 @@
+# Expect script for export table in executables tests

+#   Copyright 2003, 2007

+#   Free Software Foundation, Inc.

+#

+# This file is part of the GNU Binutils.

+#

+# This program is free software; you can redistribute it and/or modify

+# it under the terms of the GNU General Public License as published by

+# the Free Software Foundation; either version 3 of the License, or

+# (at your option) any later version.

+#

+# This program is distributed in the hope that it will be useful,

+# but WITHOUT ANY WARRANTY; without even the implied warranty of

+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+# GNU General Public License for more details.

+#

+# You should have received a copy of the GNU General Public License

+# along with this program; if not, write to the Free Software

+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,

+# MA 02110-1301, USA.

+#

+# Written by Fabrizio Gennari <fabrizio.ge@tiscalinet.it>

+# Based on auto-import.exp  by Ralf.Habacker@freenet.de

+#

+ 

+# This test can only be run on a cygwin platforms.

+if {![istarget *-pc-cygwin]} {

+    verbose "Not a cygwin target."

+    return

+}

+

+# No compiler, no test.

+if { [which $CC] == 0 } {

+    untested "Exe export test (no compiler available)"

+    return

+}

+

+proc run_dlltool { lib_file def_file } {

+    global dlltool

+    global base_dir

+    global as

+    

+    if ![info exists dlltool] then {

+	set dlltool [findfile $base_dir/../binutils/dlltool]

+    }

+

+    if { [which $dlltool] == 0 } then {

+	verbose "$dlltool does not exist"

+	return 0

+    }

+

+    verbose "$dlltool --as $as -l $lib_file -d $def_file"

+    catch "exec $dlltool --as $as -l $lib_file -d $def_file" dlltool_output

+

+    #remove empty lines

+    regsub -all "\n+" $dlltool_output "" dlltool_output

+

+    if [string match "" $dlltool_output] then {

+        return 1

+    }

+

+    verbose -log "$dlltool_output"

+    return 0

+}

+

+# ld_special_link

+#       A copy of ld_simple_link (from ld-lib.exp) with extra

+#       code to strip warnings about creating libraries.

+#

+proc ld_special_link { ld target objects } {

+    global host_triplet

+    global link_output

+

+    if { [which $ld] == 0 } then {

+	verbose "$ld does not exist"

+	return 0

+    }

+

+    if [is_endian_output_format $objects] then {

+        set flags [big_or_little_endian]

+    } else {

+        set flags ""

+    }

+

+    verbose -log "$ld $flags -o $target $objects"

+    catch "exec $ld $flags -o $target $objects" link_output

+

+    set exec_output [prune_warnings $link_output]

+

+    # We don't care if we get a warning about a non-existent start

+    # symbol, since the default linker script might use ENTRY.

+    regsub -all "(^|\n)(\[^\n\]*: warning: cannot find entry symbol\[^\n\]*\n?)" $exec_output "\\1" exec_output

+

+    # We don't care if we get a message about creating a library file.

+    regsub -all "(^|\n)(Creating library file\[^\n\]*\n?)" $exec_output "\\1" exec_output

+

+    if [string match "" $exec_output] then {

+        return 1

+    }

+

+    verbose -log "$exec_output"

+    return 0

+}

+

+set tmpdir tmpdir

+

+# Set some libs needed for cygwin.

+set MYLDFLAGS "-Wl,--out-implib,$tmpdir/testexe.lib -nostartfiles -nostdlib"

+

+# Build an export library for testdll

+if ![run_dlltool $tmpdir/testdll.lib $srcdir/$subdir/testdll.def] {

+    fail "building an export library for the shared lib"

+    return

+} 

+

+# Compile the executable.

+if ![ld_compile "$CC $CFLAGS" $srcdir/$subdir/testexe.c $tmpdir/testexe.o] {

+    fail "compiling executable"

+    return

+}

+

+if ![ld_special_link "$CC $LDFLAGS $MYLDFLAGS -e _testexe_main@16" $tmpdir/testexe.exe "$tmpdir/testexe.o $srcdir/$subdir/testexe.def $tmpdir/testdll.lib"] {

+    fail "linking executable"

+    return

+} 

+

+# Compile the dll.

+if ![ld_compile "$CC $CFLAGS" $srcdir/$subdir/testdll.c $tmpdir/testdll.o] {

+    fail "compiling shared lib"

+    return

+}

+

+if ![ld_special_link "$CC $LDFLAGS -nostartfiles -nostdlib -e _testdll_main@12" $tmpdir/testdll.dll "$tmpdir/testdll.o $srcdir/$subdir/testdll.def $tmpdir/testexe.lib"] {

+    fail "linking shared lib"

+    return

+} 

+

+# This is as far as we can go with a cross-compiler

+if ![isnative] then {

+    verbose "Not running natively, so cannot execute binary"

+    pass "Compile and link and executable with an export table"

+    return

+}

+

+verbose -log "executing $tmpdir/testexe.exe"

+catch "exec $tmpdir/testexe.exe" prog_output

+

+set expected ""

+if [string match $expected $prog_output] then {

+    pass "export table in executable"

+} else {

+    verbose $prog_output

+    fail "Output does not match expected string $expected"

+}

diff --git a/binutils-2.19/ld/testsuite/ld-cygwin/testdll.c b/binutils-2.19/ld/testsuite/ld-cygwin/testdll.c
new file mode 100644
index 0000000..2064307
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cygwin/testdll.c
@@ -0,0 +1,14 @@
+extern void exewrite (void);
+__attribute((dllimport)) int  global_a;
+
+void 
+dllwrite (void)
+{
+  global_a = 3;
+  exewrite ();
+}
+
+int _stdcall testdll_main(int p1, unsigned long p2, void* p3)
+{
+	return 1;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-cygwin/testdll.def b/binutils-2.19/ld/testsuite/ld-cygwin/testdll.def
new file mode 100644
index 0000000..05e6c88
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cygwin/testdll.def
@@ -0,0 +1,4 @@
+LIBRARY testdll

+

+EXPORTS

+dllwrite

diff --git a/binutils-2.19/ld/testsuite/ld-cygwin/testexe.c b/binutils-2.19/ld/testsuite/ld-cygwin/testexe.c
new file mode 100644
index 0000000..333c389
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cygwin/testexe.c
@@ -0,0 +1,16 @@
+int global_a = 2;
+
+void 
+exewrite (void)
+{
+  global_a = 1;
+}
+
+extern void dllwrite (void);
+
+int _stdcall
+testexe_main (void* p1, void *p2, char* p3, int p4)
+{
+  dllwrite ();
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-cygwin/testexe.def b/binutils-2.19/ld/testsuite/ld-cygwin/testexe.def
new file mode 100644
index 0000000..7570578
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-cygwin/testexe.def
@@ -0,0 +1,5 @@
+NAME testexe.exe

+

+EXPORTS

+exewrite

+global_a DATA

diff --git a/binutils-2.19/ld/testsuite/ld-d10v/d10v.exp b/binutils-2.19/ld/testsuite/ld-d10v/d10v.exp
new file mode 100644
index 0000000..86c3026
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/d10v.exp
@@ -0,0 +1,253 @@
+# Expect script for ld-d10v tests
+# Copyright 2002, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Tom Rix, trix@redhat.com
+#
+
+# Test d10v 
+
+if ![istarget d10v-*-*] {
+    return
+}
+
+# run_link_test FILE 
+# Copied from run_dump_test, with the dumping part removed.
+#
+# Assemble a .s file, then run some utility on it and check the output.
+# 
+# There should be an assembly language file named FILE.s in the test
+# suite directory.  `run_link_test' will assemble and link FILE.s 
+#
+# The FILE.lt file begins with zero or more option lines, which specify
+# flags to pass to the assembler, the program to run to dump the
+# assembler's output, and the options it wants.  The option lines have
+# the syntax:
+# 
+#         # OPTION: VALUE
+# 
+# OPTION is the name of some option, like "name" or "ld", and
+# VALUE is OPTION's value.  The valid options are described below.
+# Whitespace is ignored everywhere, except within VALUE.  The option
+# list ends with the first line that doesn't match the above syntax
+# (hmm, not great for error detection).
+#
+# The interesting options are:
+# 
+#   name: TEST-NAME
+#	The name of this test, passed to DejaGNU's `pass' and `fail'
+#       commands.  If omitted, this defaults to FILE, the root of the
+#       .s and .d files' names.
+# 
+#   as: FLAGS
+#	When assembling, pass FLAGS to the assembler.
+#       If assembling several files, you can pass different assembler
+#       options in the "source" directives.  See below.
+#
+#   ld: FLAGS
+#       Link assembled files using FLAGS, in the order of the "source"
+#       directives, when using multiple files.
+#
+#   source: SOURCE [FLAGS]
+#	Assemble the file SOURCE.s using the flags in the "as" directive
+#       and the (optional) FLAGS.  If omitted, the source defaults to
+#       FILE.s.
+#       This is useful if several .x files want to share a .s file.
+#       More than one "source" directive can be given, which is useful
+#       when testing linking.
+#
+#   xfail: TARGET
+#       The test is expected to fail on TARGET.  This may occur more than
+#       once.
+#
+#   target: TARGET
+#       Only run the test for TARGET.  This may occur more than once; the
+#       target being tested must match at least one.
+#
+#   notarget: TARGET
+#       Do not run the test for TARGET.  This may occur more than once;
+#       the target being tested must not match any of them.
+#
+# Each option may occur at most once unless otherwise mentioned.
+#
+
+proc run_link_test { name } {
+    global subdir srcdir
+    global AS LD
+    global ASFLAGS LDFLAGS
+    global host_triplet runtests
+
+    if [string match "*/*" $name] {
+	set file $name
+	set name [file tail $name]
+    } else {
+	set file "$srcdir/$subdir/$name"
+    }
+
+    if ![runtest_file_p $runtests $name] then {
+	return
+    }
+
+    set opt_array [slurp_options "${file}.lt"]
+    if { $opt_array == -1 } {
+	perror "error reading options from $file.lt"
+	unresolved $subdir/$name
+	return
+    }
+    set dumpfile tmpdir/dump.out
+    set run_ld 0
+    set opts(as) {}
+    set opts(ld) {}
+    set opts(xfail) {}
+    set opts(target) {}
+    set opts(notarget) {}
+    set opts(name) {}
+    set opts(source) {}
+    set asflags(${file}.s) {}
+
+    foreach i $opt_array {
+	set opt_name [lindex $i 0]
+	set opt_val [lindex $i 1]
+	if ![info exists opts($opt_name)] {
+	    perror "unknown option $opt_name in file $file.lt"
+	    unresolved $subdir/$name
+	    return
+	}
+
+	switch -- $opt_name {
+	    xfail {}
+	    target {}
+	    notarget {}
+	    source {
+		# Move any source-specific as-flags to a separate array to
+		# simplify processing.
+		if { [llength $opt_val] > 1 } {
+		    set asflags([lindex $opt_val 0]) [lrange $opt_val 1 end]
+		    set opt_val [lindex $opt_val 0]
+		} else {
+		    set asflags($opt_val) {}
+		}
+	    }
+	    default {
+		if [string length $opts($opt_name)] {
+		    perror "option $opt_name multiply set in $file.lt"
+		    unresolved $subdir/$name
+		    return
+		}
+	    }
+	}
+	set opts($opt_name) [concat $opts($opt_name) $opt_val]
+    }
+
+    # Decide early whether we should run the test for this target.
+    if { [llength $opts(target)] > 0 } {
+	set targmatch 0
+	foreach targ $opts(target) {
+	    if [istarget $targ] {
+		set targmatch 1
+		break
+	    }
+	}
+	if { $targmatch == 0 } {
+	    return
+	}
+    }
+    foreach targ $opts(notarget) {
+	if [istarget $targ] {
+	    return
+	}
+    }
+
+    if { $opts(name) == "" } {
+	set testname "$subdir/$name"
+    } else {
+	set testname $opts(name)
+    }
+
+    if { $opts(source) == "" } {
+	set sourcefiles [list ${file}.s]
+    } else {
+	set sourcefiles {}
+	foreach sf $opts(source) {
+	    lappend sourcefiles "$srcdir/$subdir/$sf"
+	    # Must have asflags indexed on source name.
+	    set asflags($srcdir/$subdir/$sf) $asflags($sf)
+	}
+    }
+
+    # Time to setup xfailures.
+    foreach targ $opts(xfail) {
+	setup_xfail $targ
+    }
+
+    # Assemble each file.
+    set objfiles {}
+    for { set i 0 } { $i < [llength $sourcefiles] } { incr i } {
+	set sourcefile [lindex $sourcefiles $i]
+
+	set objfile "tmpdir/dump$i.o"
+	lappend objfiles $objfile
+	set cmd "$AS $ASFLAGS $opts(as) $asflags($sourcefile) -o $objfile $sourcefile"
+
+	send_log "$cmd\n"
+	set cmdret [catch "exec $cmd" comp_output]
+	set comp_output [prune_warnings $comp_output]
+
+	# We accept errors at assembly stage too, unless we're supposed to
+	# link something.
+	if { $cmdret != 0 || ![string match "" $comp_output] } then {
+	    send_log "$comp_output\n"
+	    verbose "$comp_output" 3
+	    fail $testname
+	    return
+	}
+    }
+
+    # Link the file(s).
+    set objfile "tmpdir/dump"
+    set cmd "$LD $LDFLAGS $opts(ld) -o $objfile $objfiles"
+
+    send_log "$cmd\n"
+    set cmdret [catch "exec $cmd" comp_output]
+    set comp_output [prune_warnings $comp_output]
+
+    if { $cmdret != 0 || ![string match "" $comp_output] } then {
+	
+	send_log "$comp_output\n"
+	verbose "$comp_output" 3
+	fail $testname
+	return
+    }
+    pass $testname
+}
+
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach test $test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname $test]
+    run_dump_test [file rootname $test]
+}
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.lt]]
+foreach test $test_list {
+    # We need to strip the ".lt", but can leave the dirname.
+    verbose [file rootname $test]
+    run_link_test [file rootname $test]
+}
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/default_layout.d b/binutils-2.19/ld/testsuite/ld-d10v/default_layout.d
new file mode 100644
index 0000000..c14feb4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/default_layout.d
@@ -0,0 +1,10 @@
+#source: simple.s
+#ld: 
+#objdump: -h
+
+.*:     file format elf32-d10v
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 \.text         00000004  01014000  01014000  00001000  2\*\*0
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/linktest-001.s b/binutils-2.19/ld/testsuite/ld-d10v/linktest-001.s
new file mode 100644
index 0000000..fc8916c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/linktest-001.s
@@ -0,0 +1,4 @@
+	.section .data
+	.global bar
+bar:
+	.space 64
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/linktest-002.lt b/binutils-2.19/ld/testsuite/ld-d10v/linktest-002.lt
new file mode 100644
index 0000000..ffc6cfd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/linktest-002.lt
@@ -0,0 +1,2 @@
+#source: linktest-001.s
+#source: linktest-002.s
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/linktest-002.s b/binutils-2.19/ld/testsuite/ld-d10v/linktest-002.s
new file mode 100644
index 0000000..3295559
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/linktest-002.s
@@ -0,0 +1,4 @@
+	.section .text
+	.global _start
+_start:	
+	ldi r0,bar
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/regression-001.lt b/binutils-2.19/ld/testsuite/ld-d10v/regression-001.lt
new file mode 100644
index 0000000..6481a59
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/regression-001.lt
@@ -0,0 +1,3 @@
+#source: regression-001.s
+#as: -W
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/regression-001.s b/binutils-2.19/ld/testsuite/ld-d10v/regression-001.s
new file mode 100644
index 0000000..60226c1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/regression-001.s
@@ -0,0 +1,14 @@
+	.section .data
+	;;
+	;; The next line caused an earlier ld to core dump.
+	.global  .data
+foo:
+	.space 0x0064
+
+	.section .text
+	.global _test
+	.global _start
+_test:	
+	ldi r0,foo
+_start:
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-001.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-001.d
new file mode 100644
index 0000000..8cbe9f0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-001.d
@@ -0,0 +1,12 @@
+#source: reloc-001.s
+#ld: -T $srcdir/$subdir/reloc-001.ld
+#objdump: -D
+
+# Test 10 bit pc rel reloc normal case
+
+.*:     file format elf32-d10v
+
+Disassembly of section .text:
+
+01014000 <_start>:
+ 1014000:	65 20 cc 1a 	brf0f.s	1014104 <foo>	->	jmp	r13
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-001.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-001.ld
new file mode 100644
index 0000000..a3275f5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-001.ld
@@ -0,0 +1,10 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	*(.text)   
+	foo = (. + 0x100);
+  }
+}
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-001.s b/binutils-2.19/ld/testsuite/ld-d10v/reloc-001.s
new file mode 100644
index 0000000..bed56c7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-001.s
@@ -0,0 +1,11 @@
+	;; Test pc relative relocation
+
+	.text	
+	.global _start
+_start:
+	 brf0f.s foo 
+	jmp r13	
+
+
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-002.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-002.d
new file mode 100644
index 0000000..c80b3ff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-002.d
@@ -0,0 +1,12 @@
+#source: reloc-001.s
+#ld: -T $srcdir/$subdir/reloc-002.ld
+#objdump: -D
+
+# Test 10 bit pc rel reloc good boundary.
+
+.*:     file format elf32-d10v
+
+Disassembly of section .text:
+
+01014000 <_start>:
+ 1014000:	65 3f cc 1a 	brf0f.s	10141fc <foo>	->	jmp	r13
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-002.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-002.ld
new file mode 100644
index 0000000..8f991b2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-002.ld
@@ -0,0 +1,10 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	*(.text)   
+	foo = (. + 0x1F8);
+  }
+}
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-003.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-003.d
new file mode 100644
index 0000000..009e228
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-003.d
@@ -0,0 +1,5 @@
+#source: reloc-001.s
+#ld: -T $srcdir/$subdir/reloc-003.ld
+#error: relocation truncated to fit: R_D10V_10_PCREL_L
+
+# Test 10 bit pc rel reloc bad boundary.
\ No newline at end of file
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-003.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-003.ld
new file mode 100644
index 0000000..7008d9d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-003.ld
@@ -0,0 +1,10 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	*(.text)   
+	foo = (. + 0x1FC);
+  }
+}
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-004.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-004.d
new file mode 100644
index 0000000..49801de
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-004.d
@@ -0,0 +1,5 @@
+#source: reloc-001.s
+#ld: -T $srcdir/$subdir/reloc-004.ld
+#error: relocation truncated to fit: R_D10V_10_PCREL_L
+
+# Test 10 bit pc rel reloc normal bad.
\ No newline at end of file
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-004.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-004.ld
new file mode 100644
index 0000000..5f06d60
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-004.ld
@@ -0,0 +1,10 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	foo = .;
+	. = (. + 0x400);
+  }
+}
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-005.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-005.d
new file mode 100644
index 0000000..633de71
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-005.d
@@ -0,0 +1,13 @@
+#source: reloc-005.s
+#ld: -T $srcdir/$subdir/reloc-005.ld
+#objdump: -D
+
+# Test 18 bit pc rel reloc normal case
+
+.*:     file format elf32-d10v
+
+Disassembly of section .text:
+
+01014000 <_start>:
+ 1014000:	e4 00 10 02 	bra.l	1018008 <foo>
+ 1014004:	26 0d 5e 00 	jmp	r13	||	nop	
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-005.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-005.ld
new file mode 100644
index 0000000..a3f5b06
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-005.ld
@@ -0,0 +1,10 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	*(.text)   
+	foo = (. + 0x4000);
+  }
+}
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-005.s b/binutils-2.19/ld/testsuite/ld-d10v/reloc-005.s
new file mode 100644
index 0000000..34ebb05
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-005.s
@@ -0,0 +1,11 @@
+	;; Test 18 bit pc rel relocation
+
+	.text	
+	.global _start
+_start:
+	bra.l foo 
+	jmp r13	
+
+
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-006.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-006.d
new file mode 100644
index 0000000..b0fd080
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-006.d
@@ -0,0 +1,13 @@
+#source: reloc-005.s
+#ld: -T $srcdir/$subdir/reloc-006.ld
+#objdump: -D
+
+# Test 18 bit pc rel reloc good boundary
+
+.*:     file format elf32-d10v
+
+Disassembly of section .text:
+
+01014000 <_start>:
+ 1014000:	e4 00 7f ff 	bra.l	1033ffc <foo>
+ 1014004:	26 0d 5e 00 	jmp	r13	||	nop	
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-006.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-006.ld
new file mode 100644
index 0000000..3d1a0f6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-006.ld
@@ -0,0 +1,8 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	*(.text)   
+	foo = (. + 0x1fff4);
+  }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-007.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-007.d
new file mode 100644
index 0000000..2edb862
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-007.d
@@ -0,0 +1,7 @@
+#source: reloc-005.s
+#ld: -T $srcdir/$subdir/reloc-007.ld
+#objdump: -D
+#error: relocation truncated to fit: R_D10V_18_PCREL
+
+# Test 18 bit pc rel reloc bad boundary
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-007.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-007.ld
new file mode 100644
index 0000000..10c50ff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-007.ld
@@ -0,0 +1,8 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	*(.text)   
+	foo = (. + 0x1fff8);
+  }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-008.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-008.d
new file mode 100644
index 0000000..cb3cf4b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-008.d
@@ -0,0 +1,7 @@
+#source: reloc-005.s
+#ld: -T $srcdir/$subdir/reloc-008.ld
+#objdump: -D
+#error: relocation truncated to fit: R_D10V_18_PCREL
+
+# Test 18 bit pc rel reloc normal bad
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-008.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-008.ld
new file mode 100644
index 0000000..d42e0ee
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-008.ld
@@ -0,0 +1,8 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	*(.text)   
+	foo = (. + 0x41fff8);
+  }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-009.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-009.d
new file mode 100644
index 0000000..45373c9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-009.d
@@ -0,0 +1,15 @@
+#source: reloc-009.s
+#ld: -T $srcdir/$subdir/reloc-009.ld
+#objdump: -D
+
+# Test 10 bit pc rel reloc negative normal case
+
+.*:     file format elf32-d10v
+Disassembly of section .text:
+
+01014000 <foo>:
+	...
+
+01014100 <_start>:
+ 1014100:	6f 00 4a c0 	nop		->	brf0f.s	1014000 <foo>
+ 1014104:	26 0d 5e 00 	jmp	r13	||	nop	
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-009.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-009.ld
new file mode 100644
index 0000000..af6e775
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-009.ld
@@ -0,0 +1,11 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	foo = .;
+	. = (. + 0x100);
+	*(.text)   
+  }
+}
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-009.s b/binutils-2.19/ld/testsuite/ld-d10v/reloc-009.s
new file mode 100644
index 0000000..fb2ebce
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-009.s
@@ -0,0 +1,12 @@
+	;; Test pc relative relocation
+
+	.text	
+	.global _start
+_start:
+	nop
+	brf0f.s foo 
+	jmp r13	
+
+
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-010.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-010.d
new file mode 100644
index 0000000..47e048f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-010.d
@@ -0,0 +1,16 @@
+#source: reloc-009.s
+#ld: -T $srcdir/$subdir/reloc-010.ld
+#objdump: -D
+
+# Test 10 bit pc rel reloc negative good boundary case
+
+.*:     file format elf32-d10v
+
+Disassembly of section .text:
+
+01014000 <foo>:
+	...
+
+01014200 <_start>:
+ 1014200:	6f 00 4a 80 	nop		->	brf0f.s	1014000 <foo>
+ 1014204:	26 0d 5e 00 	jmp	r13	||	nop	
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-010.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-010.ld
new file mode 100644
index 0000000..9b3d81a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-010.ld
@@ -0,0 +1,11 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	foo = .;
+	. = (. + 0x200);
+	*(.text)   
+  }
+}
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-011.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-011.d
new file mode 100644
index 0000000..2bfc903
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-011.d
@@ -0,0 +1,6 @@
+#source: reloc-009.s
+#ld: -T $srcdir/$subdir/reloc-011.ld
+#error: relocation truncated to fit: R_D10V_10_PCREL_R
+
+# Test 10 bit pc rel reloc negative bad boundary.
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-011.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-011.ld
new file mode 100644
index 0000000..e7a8151
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-011.ld
@@ -0,0 +1,11 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	foo = .;
+	. = (. + 0x204);
+	*(.text)   
+  }
+}
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-012.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-012.d
new file mode 100644
index 0000000..ffb03d4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-012.d
@@ -0,0 +1,6 @@
+#source: reloc-009.s
+#ld: -T $srcdir/$subdir/reloc-012.ld
+#error: relocation truncated to fit: R_D10V_10_PCREL_R
+
+# Test 10 bit pc rel reloc negative normal bad.
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-012.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-012.ld
new file mode 100644
index 0000000..10b7e7c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-012.ld
@@ -0,0 +1,11 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	foo = .;
+	. = (. + 0x80004);
+	*(.text)   
+  }
+}
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-013.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-013.d
new file mode 100644
index 0000000..a422fb0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-013.d
@@ -0,0 +1,16 @@
+#source: reloc-005.s
+#ld: -T $srcdir/$subdir/reloc-013.ld
+#objdump: -D
+
+# Test 18 bit pc rel reloc negative normal case
+
+.*:     file format elf32-d10v
+
+Disassembly of section .text:
+
+01014000 <foo>:
+	...
+
+01014400 <_start>:
+ 1014400:	e4 00 ff 00 	bra.l	1014000 <foo>
+ 1014404:	26 0d 5e 00 	jmp	r13	||	nop	
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-013.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-013.ld
new file mode 100644
index 0000000..a6c0808
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-013.ld
@@ -0,0 +1,12 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	foo = .;
+	. = (. + 0x400);
+	*(.text)   
+  }
+}
+
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-014.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-014.d
new file mode 100644
index 0000000..5035a29
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-014.d
@@ -0,0 +1,16 @@
+#source: reloc-005.s
+#ld: -T $srcdir/$subdir/reloc-014.ld
+#objdump: -D
+
+# Test 18 bit pc rel reloc negative good boundary case
+
+.*:     file format elf32-d10v
+
+Disassembly of section .text:
+
+01014000 <foo>:
+	...
+
+01034000 <_start>:
+ 1034000:	e4 00 80 00 	bra.l	1014000 <foo>
+ 1034004:	26 0d 5e 00 	jmp	r13	||	nop	
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-014.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-014.ld
new file mode 100644
index 0000000..7cda1ac
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-014.ld
@@ -0,0 +1,12 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	foo = .;
+	. = (. + 0x20000);
+	*(.text)   
+  }
+}
+
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-015.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-015.d
new file mode 100644
index 0000000..5888aa7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-015.d
@@ -0,0 +1,7 @@
+#source: reloc-005.s
+#ld: -T $srcdir/$subdir/reloc-015.ld
+#objdump: -D
+#error: relocation truncated to fit: R_D10V_18_PCREL
+
+# Test 18 bit pc rel negative reloc bad boundary
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-015.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-015.ld
new file mode 100644
index 0000000..ab1b183
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-015.ld
@@ -0,0 +1,12 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	foo = .;
+	. = (. + 0x20004);
+	*(.text)   
+  }
+}
+
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-016.d b/binutils-2.19/ld/testsuite/ld-d10v/reloc-016.d
new file mode 100644
index 0000000..402bcff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-016.d
@@ -0,0 +1,7 @@
+#source: reloc-005.s
+#ld: -T $srcdir/$subdir/reloc-016.ld
+#objdump: -D
+#error: relocation truncated to fit: R_D10V_18_PCREL
+
+# Test 18 bit pc rel negative reloc normal bad
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/reloc-016.ld b/binutils-2.19/ld/testsuite/ld-d10v/reloc-016.ld
new file mode 100644
index 0000000..6b5704c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/reloc-016.ld
@@ -0,0 +1,12 @@
+SECTIONS
+{
+  .text 0x01014000 :
+  { 
+	foo = .;
+	. = (. + 0x800004);
+	*(.text)   
+  }
+}
+
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-d10v/simple.s b/binutils-2.19/ld/testsuite/ld-d10v/simple.s
new file mode 100644
index 0000000..8a304f9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-d10v/simple.s
@@ -0,0 +1,5 @@
+	.text
+	.global _start
+_start:	
+	jmp r13
+	
diff --git a/binutils-2.19/ld/testsuite/ld-discard/discard.exp b/binutils-2.19/ld/testsuite/ld-discard/discard.exp
new file mode 100644
index 0000000..a1e65a3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-discard/discard.exp
@@ -0,0 +1,50 @@
+# Expect script for ld discard tests
+#   Copyright 2001, 2002, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Hans-Peter Nilsson (hp@axis.com)
+#	     H.J. Lu (hjl@gnu.org)
+#
+
+# Test for ELF here, so we don't have to qualify on ELF specifically
+# in every .d-file.
+
+if { ![istarget *-*-linux*] \
+     && ![istarget *-*-gnu] \
+     && ![istarget hppa*64*-*-hpux*] \
+     && ![istarget *-*-elf] } {
+    return
+}
+
+if { [istarget *-*-linux*aout*] \
+     || [istarget *-*-linux*oldld*] } {
+    return
+}
+
+load_lib ld-lib.exp
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+for { set i 0 } { $i < [llength $test_list] } { incr i } {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname [lindex $test_list $i]]
+    # These fail because they use the generic linker.
+    setup_xfail "arc-*" "d30v-*" "dlx-*" "i960-*" "m6812-*" "m68hc12-*"
+    setup_xfail "or32-*" "pj-*"
+    run_dump_test [file rootname [lindex $test_list $i]]
+}
diff --git a/binutils-2.19/ld/testsuite/ld-discard/discard.ld b/binutils-2.19/ld/testsuite/ld-discard/discard.ld
new file mode 100644
index 0000000..a7ff4a5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-discard/discard.ld
@@ -0,0 +1,9 @@
+ENTRY(_start)
+SECTIONS
+{
+  /* Sections to be discarded */
+  /DISCARD/ : {
+	*(.data.exit)
+	*(.text.exit)
+	}
+}
diff --git a/binutils-2.19/ld/testsuite/ld-discard/exit.s b/binutils-2.19/ld/testsuite/ld-discard/exit.s
new file mode 100644
index 0000000..c852978
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-discard/exit.s
@@ -0,0 +1,6 @@
+	.globl data
+	.section	.data.exit,"aw"
+data:
+	.globl text
+	.section	.text.exit,"ax"
+text:
diff --git a/binutils-2.19/ld/testsuite/ld-discard/extern.d b/binutils-2.19/ld/testsuite/ld-discard/extern.d
new file mode 100644
index 0000000..9033792
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-discard/extern.d
@@ -0,0 +1,11 @@
+#source: extern.s
+#ld: -T discard.ld
+#error: .*data.* referenced in section `\.text' of tmpdir/dump0.o: defined in discarded section `\.data\.exit' of tmpdir/dump0.o
+#objdump: -p
+#pass
+# The expected warning used to start with "`data' referenced..." but
+# this has two problems: 1) It does not include the name of the linker
+# command which will be present in the message, eg "../ld-new"
+# 2) Targets which define EXTERN_FORCE_RELOC to 0 in their
+# gas/config/tc-xxx.h file will convert the symbol in the reloc from
+# "data" to the section symbol ".data.exit".
diff --git a/binutils-2.19/ld/testsuite/ld-discard/extern.s b/binutils-2.19/ld/testsuite/ld-discard/extern.s
new file mode 100644
index 0000000..464be8b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-discard/extern.s
@@ -0,0 +1,13 @@
+	.globl data
+	.section	.data.exit,"aw"
+data:
+	.globl text
+	.section	.text.exit,"ax"
+text:
+	.text
+	.globl _start
+_start:
+	.long	data
+	.section	.debug_info
+	.long	0
+	.long	text
diff --git a/binutils-2.19/ld/testsuite/ld-discard/start.d b/binutils-2.19/ld/testsuite/ld-discard/start.d
new file mode 100644
index 0000000..5c685e8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-discard/start.d
@@ -0,0 +1,6 @@
+#source: start.s
+#source: exit.s
+#ld: -T discard.ld
+#error: `data' referenced in section `\.text' of tmpdir/dump0.o: defined in discarded section `\.data\.exit' of tmpdir/dump1.o
+#objdump: -p
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-discard/start.s b/binutils-2.19/ld/testsuite/ld-discard/start.s
new file mode 100644
index 0000000..70f4187
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-discard/start.s
@@ -0,0 +1,7 @@
+	.text
+	.globl _start
+_start:
+	.long	data
+	.section	.debug_info
+	.long	0
+	.long	text
diff --git a/binutils-2.19/ld/testsuite/ld-discard/static.d b/binutils-2.19/ld/testsuite/ld-discard/static.d
new file mode 100644
index 0000000..3b5255b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-discard/static.d
@@ -0,0 +1,5 @@
+#source: static.s
+#ld: -T discard.ld
+#error: `(\.data\.exit|data)' referenced in section `\.text' of tmpdir/dump0.o: defined in discarded section `\.data\.exit' of tmpdir/dump0.o
+#objdump: -p
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-discard/static.s b/binutils-2.19/ld/testsuite/ld-discard/static.s
new file mode 100644
index 0000000..a0f4569
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-discard/static.s
@@ -0,0 +1,11 @@
+	.section	.data.exit,"aw"
+data:
+	.section	.text.exit,"ax"
+text:
+	.text
+	.globl _start
+_start:
+	.long	data
+	.section	.debug_info
+	.long	0
+	.long	text
diff --git a/binutils-2.19/ld/testsuite/ld-discard/zero-rel.d b/binutils-2.19/ld/testsuite/ld-discard/zero-rel.d
new file mode 100644
index 0000000..1f73775
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-discard/zero-rel.d
@@ -0,0 +1,8 @@
+#source: zero-rel.s
+#ld: -T discard.ld
+#objdump: -s -j .debug_info
+
+.*:     file format .*elf.*
+
+Contents of section .debug_info:
+ 0000 0+( 0+)? +(\.+) .*
diff --git a/binutils-2.19/ld/testsuite/ld-discard/zero-rel.s b/binutils-2.19/ld/testsuite/ld-discard/zero-rel.s
new file mode 100644
index 0000000..f3f0b3c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-discard/zero-rel.s
@@ -0,0 +1,11 @@
+	.text
+	.globl _start
+_start:
+
+	.section	.debug_info
+	.long	.Ltext
+	.long	.Ltext + 2
+
+	.section	.text.exit,"ax"
+.Ltext:
+	.long	0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/begin.c b/binutils-2.19/ld/testsuite/ld-elf/begin.c
new file mode 100644
index 0000000..ccc47d4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/begin.c
@@ -0,0 +1,5 @@
+extern void foo (void);
+
+static void (*const init_array []) (void)
+  __attribute__ ((used, section (".init_array"), aligned (sizeof (void *))))
+  = { foo };
diff --git a/binutils-2.19/ld/testsuite/ld-elf/beginwarn.c b/binutils-2.19/ld/testsuite/ld-elf/beginwarn.c
new file mode 100644
index 0000000..ebe2819
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/beginwarn.c
@@ -0,0 +1,9 @@
+static const char _evoke_link_warning_foo []
+  __attribute__ ((used, section (".gnu.warning.foo")))
+    = "function foo is deprecated";
+
+extern void foo (void);
+
+static void (*const init_array []) (void)
+  __attribute__ ((used, section (".init_array"), aligned (sizeof (void *))))
+  = { foo };
diff --git a/binutils-2.19/ld/testsuite/ld-elf/binutils.exp b/binutils-2.19/ld/testsuite/ld-elf/binutils.exp
new file mode 100644
index 0000000..6907560
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/binutils.exp
@@ -0,0 +1,147 @@
+# Expect script for binutils tests
+#   Copyright 2006, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by H.J. Lu (hongjiu.lu@intel.com)
+#
+
+# Make sure that binutils can correctly handle ld output in ELF.
+
+# Run on Linux only.
+if { ![istarget *-*-linux*] } {
+    return
+}
+
+if { [istarget *-*-linux*aout*]
+     || [istarget *-*-linux*oldld*] } {
+    return
+}
+
+proc binutils_test { prog_name ld_options test } {
+    global as
+    global ld
+    global READELF
+    global objcopy
+    global strip
+    global srcdir
+    global subdir
+    global link_output
+
+    eval set prog \$$prog_name
+    set test_name "$prog_name $ld_options ($test)"
+
+    if { ![ld_assemble $as $srcdir/$subdir/$test.s tmpdir/$test.o ] } {
+	unresolved "$test_name"
+	return
+    }
+
+    if { ![ld_simple_link $ld tmpdir/$test "$ld_options tmpdir/$test.o"] } {
+	if { [string match "*not supported*" $link_output]
+	     || [string match "*unrecognized option*" $link_output] } {
+	    unsupported "$ld_options is not supported by this target"
+	} else {
+	    unresolved "$test_name"
+	}
+	return
+    }
+
+    send_log "$READELF -l --wide tmpdir/$test > tmpdir/$test.exp\n"
+    set got [remote_exec host "$READELF -l --wide tmpdir/$test" "" "/dev/null" "tmpdir/$test.exp"]
+    if { [lindex $got 0] != 0 || ![string match "" [lindex $got 1]] } then {
+	send_log "$got\n"
+	unresolved "$test_name"
+	return
+    }
+
+    send_log "$prog tmpdir/$test\n"
+    set got [remote_exec host "$prog tmpdir/$test"]
+    if { [lindex $got 0] != 0 || ![string match "" [lindex $got 1]] } then {
+	send_log "$got\n"
+	fail "$test_name"
+	return
+    }
+
+    send_log "$READELF -l --wide tmpdir/$test > tmpdir/$test.out\n"
+    set got [remote_exec host "$READELF -l --wide tmpdir/$test" "" "/dev/null" "tmpdir/$test.out"]
+    if { [lindex $got 0] != 0 || ![string match "" [lindex $got 1]] } then {
+	send_log "$got\n"
+	unresolved "$test_name"
+	return
+    }
+
+    if { [catch {exec cmp tmpdir/$test.exp tmpdir/$test.out}] } then {
+	send_log "tmpdir/$test.exp tmpdir/$test.out differ.\n"
+	fail "$test_name"
+	return
+    }
+
+    pass "$test_name"
+}
+
+binutils_test strip "-z max-page-size=0x200000" maxpage1
+binutils_test strip "-z max-page-size=0x200000 -z common-page-size=0x100000" maxpage1
+binutils_test strip "-z max-page-size=0x100000" maxpage1
+binutils_test strip "-z max-page-size=0x100000 -z common-page-size=0x1000" maxpage1
+
+binutils_test strip "" maxpage1
+binutils_test strip "-shared" maxpage1
+binutils_test objcopy "" maxpage1
+binutils_test objcopy "-shared" maxpage1
+
+binutils_test strip "-z relro" relro1
+binutils_test strip "-z relro -shared" relro1
+binutils_test objcopy "-z relro" relro1
+binutils_test objcopy "-z relro -shared" relro1
+if { ([istarget "i?86-*-elf*"]		
+      || ([istarget "i?86-*-linux*"]
+	  && ![istarget "*-*-*aout*"]
+	  && ![istarget "*-*-*oldld*"])
+      || [istarget "x86_64-*-linux*"]
+      || [istarget "amd64-*-linux*"]) } {
+    binutils_test strip "-z relro -shared" relro2
+    binutils_test objcopy "-z relro -shared" relro2
+}
+
+binutils_test strip "-T ${srcdir}/${subdir}/lma.lnk" lma
+
+binutils_test objcopy "" tbss1
+binutils_test objcopy "-z relro" tbss1
+binutils_test objcopy "-shared" tbss1
+binutils_test objcopy "-shared -z relro" tbss1
+binutils_test objcopy "-z max-page-size=0x100000" tbss1
+binutils_test objcopy "-z max-page-size=0x100000 -z common-page-size=0x1000" tbss1
+binutils_test objcopy "" tdata1
+binutils_test objcopy "-z relro" tdata1
+binutils_test objcopy "-shared" tdata1
+binutils_test objcopy "-shared -z relro" tdata1
+binutils_test objcopy "-z max-page-size=0x100000" tdata1
+binutils_test objcopy "-z max-page-size=0x100000 -z common-page-size=0x1000" tdata1
+binutils_test objcopy "" tbss2
+binutils_test objcopy "-z relro" tbss2
+binutils_test objcopy "-shared" tbss2
+binutils_test objcopy "-shared -z relro" tbss2
+binutils_test objcopy "-z max-page-size=0x100000" tbss2
+binutils_test objcopy "-z max-page-size=0x100000 -z common-page-size=0x1000" tbss2
+
+binutils_test objcopy "" tdata2
+binutils_test objcopy "-z relro" tdata2
+binutils_test objcopy "-shared" tdata2
+binutils_test objcopy "-shared -z relro" tdata2
+binutils_test objcopy "-z max-page-size=0x100000" tdata2
+binutils_test objcopy "-z max-page-size=0x100000 -z common-page-size=0x1000" tdata2
diff --git a/binutils-2.19/ld/testsuite/ld-elf/commonpage1.d b/binutils-2.19/ld/testsuite/ld-elf/commonpage1.d
new file mode 100644
index 0000000..76dc056
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/commonpage1.d
@@ -0,0 +1,9 @@
+#source: maxpage1.s
+#ld: -z max-page-size=0x200000 -z common-page-size=0x100000
+#readelf: -l --wide
+#target: *-*-linux*
+
+#...
+  LOAD+.*0x200000
+  LOAD+.*0x200000
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/data1.c b/binutils-2.19/ld/testsuite/ld-elf/data1.c
new file mode 100644
index 0000000..c205f82
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/data1.c
@@ -0,0 +1,6 @@
+#include "data1.h"
+
+char a1[1] __attribute__ ((aligned (ALIGNMENT1))) = { 10 };
+char a2[2] __attribute__ ((aligned (ALIGNMENT2)));
+char a3[3] __attribute__ ((aligned (ALIGNMENT3)));
+char a4[4] __attribute__ ((aligned (ALIGNMENT4)));
diff --git a/binutils-2.19/ld/testsuite/ld-elf/data1.h b/binutils-2.19/ld/testsuite/ld-elf/data1.h
new file mode 100644
index 0000000..529ee4b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/data1.h
@@ -0,0 +1,9 @@
+#define ALIGNMENT1 0x800
+#define ALIGNMENT2 0x400
+#define ALIGNMENT3 0x200
+#define ALIGNMENT4 0x100
+
+extern char a1[1];
+extern char a2[2];
+extern char a3[3];
+extern char a4[4];
diff --git a/binutils-2.19/ld/testsuite/ld-elf/del.cc b/binutils-2.19/ld/testsuite/ld-elf/del.cc
new file mode 100644
index 0000000..4e2cc60
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/del.cc
@@ -0,0 +1,29 @@
+#include <new>
+
+extern "C" void free (void *);
+
+void
+operator delete (void *ptr, const std::nothrow_t&) throw ()
+{
+  if (ptr)
+    free (ptr);
+}
+
+void
+operator delete (void *ptr) throw ()
+{
+  if (ptr)
+    free (ptr);
+}
+
+void
+operator delete[] (void *ptr) throw ()
+{
+  ::operator delete (ptr);
+}
+
+void
+operator delete[] (void *ptr, const std::nothrow_t&) throw ()
+{
+  ::operator delete (ptr);
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl1.c b/binutils-2.19/ld/testsuite/ld-elf/dl1.c
new file mode 100644
index 0000000..09426f3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl1.c
@@ -0,0 +1,10 @@
+#include <stdio.h>
+
+extern int bar;
+
+void
+foo (void)
+{
+  if (bar == -20)
+    printf ("OK\n");
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl1.list b/binutils-2.19/ld/testsuite/ld-elf/dl1.list
new file mode 100644
index 0000000..9ffada0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl1.list
@@ -0,0 +1,6 @@
+{
+  extern "C"
+    {
+      bar;
+    };
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl1.out b/binutils-2.19/ld/testsuite/ld-elf/dl1.out
new file mode 100644
index 0000000..d86bac9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl1.out
@@ -0,0 +1 @@
+OK
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl1main.c b/binutils-2.19/ld/testsuite/ld-elf/dl1main.c
new file mode 100644
index 0000000..f224e12
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl1main.c
@@ -0,0 +1,33 @@
+#include <stdio.h>
+#include <dlfcn.h>
+
+int bar = -20;
+
+int 
+main (void)
+{
+  int ret = 0;
+  void *handle;
+  void (*fcn) (void);
+
+  handle = dlopen("./tmpdir/libdl1.so", RTLD_GLOBAL|RTLD_LAZY);
+  if (!handle)
+    {
+      printf("dlopen ./tmpdir/libdl1.so: %s\n", dlerror ());
+      return 1;
+    }
+
+  fcn = (void (*)(void)) dlsym(handle, "foo");
+  if (!fcn)
+    {
+      printf("dlsym foo: %s\n", dlerror ());
+      ret += 1;
+    }
+  else
+    {
+      (*fcn) ();
+    }
+
+  dlclose (handle);
+  return ret;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl2.c b/binutils-2.19/ld/testsuite/ld-elf/dl2.c
new file mode 100644
index 0000000..b5cd927
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl2.c
@@ -0,0 +1,16 @@
+#include <stdio.h>
+
+int foo;
+
+extern void xxx (void);
+
+void
+bar (int x)
+{
+  if (foo == 1)
+    printf ("OK1\n");
+  else if (foo == 0)
+    printf ("OK2\n");
+  foo = -1;
+  xxx ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl2.list b/binutils-2.19/ld/testsuite/ld-elf/dl2.list
new file mode 100644
index 0000000..e985dcf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl2.list
@@ -0,0 +1,3 @@
+{
+  foo;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl2a.list b/binutils-2.19/ld/testsuite/ld-elf/dl2a.list
new file mode 100644
index 0000000..989646e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl2a.list
@@ -0,0 +1,3 @@
+{
+  "foo";
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl2a.out b/binutils-2.19/ld/testsuite/ld-elf/dl2a.out
new file mode 100644
index 0000000..f3d5b9f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl2a.out
@@ -0,0 +1,3 @@
+OK1
+DSO
+OK1
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl2b.out b/binutils-2.19/ld/testsuite/ld-elf/dl2b.out
new file mode 100644
index 0000000..f30cead
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl2b.out
@@ -0,0 +1,3 @@
+OK1
+MAIN
+OK1
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl2main.c b/binutils-2.19/ld/testsuite/ld-elf/dl2main.c
new file mode 100644
index 0000000..ddf677f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl2main.c
@@ -0,0 +1,22 @@
+#include <stdio.h>
+
+extern int foo;
+extern void bar (void);
+
+void
+xxx (void)
+{
+  printf ("MAIN\n");
+}
+
+int
+main (void)
+{
+  foo = 1;
+  bar ();
+  if (foo == -1)
+    printf ("OK1\n");
+  else if (foo == 1)
+    printf ("OK2\n");
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl2xxx.c b/binutils-2.19/ld/testsuite/ld-elf/dl2xxx.c
new file mode 100644
index 0000000..cf3a1d0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl2xxx.c
@@ -0,0 +1,7 @@
+#include <stdio.h>
+
+void
+xxx (void)
+{
+  printf ("DSO\n");
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl2xxx.list b/binutils-2.19/ld/testsuite/ld-elf/dl2xxx.list
new file mode 100644
index 0000000..9388cda
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl2xxx.list
@@ -0,0 +1,3 @@
+{
+  xxx;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl3.cc b/binutils-2.19/ld/testsuite/ld-elf/dl3.cc
new file mode 100644
index 0000000..558e49f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl3.cc
@@ -0,0 +1,7 @@
+#include "dl3header.h"
+
+void
+f (void)
+{
+  throw (A (42));
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl3.list b/binutils-2.19/ld/testsuite/ld-elf/dl3.list
new file mode 100644
index 0000000..0b347ea
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl3.list
@@ -0,0 +1,6 @@
+{
+  extern "C++"
+  {
+    typeinfo*;
+  };
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl3a.out b/binutils-2.19/ld/testsuite/ld-elf/dl3a.out
new file mode 100644
index 0000000..d86bac9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl3a.out
@@ -0,0 +1 @@
+OK
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl3b.out b/binutils-2.19/ld/testsuite/ld-elf/dl3b.out
new file mode 100644
index 0000000..8a15044
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl3b.out
@@ -0,0 +1 @@
+BAD2
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl3header.h b/binutils-2.19/ld/testsuite/ld-elf/dl3header.h
new file mode 100644
index 0000000..66f7d46
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl3header.h
@@ -0,0 +1,5 @@
+struct A
+{
+  int i;
+  A (int i): i(i) {}
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl3main.cc b/binutils-2.19/ld/testsuite/ld-elf/dl3main.cc
new file mode 100644
index 0000000..977f9bb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl3main.cc
@@ -0,0 +1,25 @@
+#include <stdio.h>
+#include "dl3header.h"
+
+extern void f (void);
+
+int
+main (void)
+{
+  try
+    {
+      f();
+    }
+  catch (A a)
+    {
+      if (a.i == 42)
+	printf ("OK\n");
+      else
+	printf ("BAD1\n");
+    }
+  catch (...)
+    {
+      printf ("BAD2\n");
+    }
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl4.c b/binutils-2.19/ld/testsuite/ld-elf/dl4.c
new file mode 100644
index 0000000..bf6f070
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl4.c
@@ -0,0 +1,24 @@
+#include <stdio.h>
+
+int foo1;
+int foo2;
+
+extern void xxx1 (void);
+extern void xxx2 (void);
+
+void
+bar (int x)
+{
+  if (foo1 == 1)
+    printf ("bar OK1\n");
+  else if (foo1 == 0)
+    printf ("bar OK2\n");
+  if (foo2 == 1)
+    printf ("bar OK3\n");
+  else if (foo2 == 0)
+    printf ("bar OK4\n");
+  foo1 = -1;
+  foo2 = -1;
+  xxx1 ();
+  xxx2 ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl4.list b/binutils-2.19/ld/testsuite/ld-elf/dl4.list
new file mode 100644
index 0000000..e932e23
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl4.list
@@ -0,0 +1,4 @@
+{
+  foo1;
+  foo2;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl4a.out b/binutils-2.19/ld/testsuite/ld-elf/dl4a.out
new file mode 100644
index 0000000..871c5be
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl4a.out
@@ -0,0 +1,6 @@
+bar OK1
+bar OK3
+DSO1
+DSO2
+OK1
+OK3
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl4b.out b/binutils-2.19/ld/testsuite/ld-elf/dl4b.out
new file mode 100644
index 0000000..b838f5b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl4b.out
@@ -0,0 +1,6 @@
+bar OK1
+bar OK3
+MAIN1
+MAIN2
+OK1
+OK3
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl4main.c b/binutils-2.19/ld/testsuite/ld-elf/dl4main.c
new file mode 100644
index 0000000..173450d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl4main.c
@@ -0,0 +1,34 @@
+#include <stdio.h>
+
+extern int foo1;
+extern int foo2;
+extern void bar (void);
+
+void
+xxx1 (void)
+{
+  printf ("MAIN1\n");
+}
+
+void
+xxx2 (void)
+{
+  printf ("MAIN2\n");
+}
+
+int
+main (void)
+{
+  foo1 = 1;
+  foo2 = 1;
+  bar ();
+  if (foo1 == -1)
+    printf ("OK1\n");
+  else if (foo1 == 1)
+    printf ("OK2\n");
+  if (foo2 == -1)
+    printf ("OK3\n");
+  else if (foo2 == 1)
+    printf ("OK4\n");
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl4xxx.c b/binutils-2.19/ld/testsuite/ld-elf/dl4xxx.c
new file mode 100644
index 0000000..8180eb1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl4xxx.c
@@ -0,0 +1,13 @@
+#include <stdio.h>
+
+void
+xxx1 (void)
+{
+  printf ("DSO1\n");
+}
+
+void
+xxx2 (void)
+{
+  printf ("DSO2\n");
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl4xxx.list b/binutils-2.19/ld/testsuite/ld-elf/dl4xxx.list
new file mode 100644
index 0000000..f39ce14
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl4xxx.list
@@ -0,0 +1,4 @@
+{
+  xxx1;
+  xxx2;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl5.cc b/binutils-2.19/ld/testsuite/ld-elf/dl5.cc
new file mode 100644
index 0000000..cc40455
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl5.cc
@@ -0,0 +1,61 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <new>
+
+int pass = 0;
+
+void *
+operator new (size_t sz, const std::nothrow_t&) throw ()
+{
+  void *p;
+  pass++;
+  p = malloc(sz);
+  return p;
+}
+
+void *
+operator new (size_t sz) throw (std::bad_alloc)
+{
+  void *p;
+  pass++;
+  p = malloc(sz);
+  return p;
+}
+
+void
+operator delete (void *ptr) throw ()
+{
+  pass++;
+  if (ptr)
+    free (ptr);
+}
+
+class A 
+{
+public:
+  A() {}
+  ~A() { }
+  int a;
+  int b;
+};
+
+
+int
+main (void)
+{
+  A *bb = new A[10];
+  delete [] bb;
+  bb = new (std::nothrow) A [10];
+  delete [] bb;
+
+  if (pass == 4)
+    {
+      printf ("PASS\n");
+      return 0;
+    }
+  else
+    {
+      printf ("FAIL\n");
+      return 1;
+    }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl5.out b/binutils-2.19/ld/testsuite/ld-elf/dl5.out
new file mode 100644
index 0000000..7ef22e9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl5.out
@@ -0,0 +1 @@
+PASS
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl6.c b/binutils-2.19/ld/testsuite/ld-elf/dl6.c
new file mode 100644
index 0000000..f655ca6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl6.c
@@ -0,0 +1,14 @@
+#include <stdio.h>
+
+int bar = 10;
+
+void
+foo (void)
+{
+  if (bar == 10)
+    printf ("bar is in DSO.\n");
+  else if (bar == -20)
+    printf ("bar is in main.\n");
+  else
+    printf ("FAIL\n");
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl6a.out b/binutils-2.19/ld/testsuite/ld-elf/dl6a.out
new file mode 100644
index 0000000..186e848
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl6a.out
@@ -0,0 +1 @@
+bar is in main.
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl6amain.c b/binutils-2.19/ld/testsuite/ld-elf/dl6amain.c
new file mode 100644
index 0000000..9824224
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl6amain.c
@@ -0,0 +1,33 @@
+#include <stdio.h>
+#include <dlfcn.h>
+
+int bar = -20;
+
+int 
+main (void)
+{
+  int ret = 0;
+  void *handle;
+  void (*fcn) (void);
+
+  handle = dlopen("./tmpdir/libdl6a.so", RTLD_GLOBAL|RTLD_LAZY);
+  if (!handle)
+    {
+      printf("dlopen ./tmpdir/libdl6a.so: %s\n", dlerror ());
+      return 1;
+    }
+
+  fcn = (void (*)(void)) dlsym(handle, "foo");
+  if (!fcn)
+    {
+      printf("dlsym foo: %s\n", dlerror ());
+      ret += 1;
+    }
+  else
+    {
+      (*fcn) ();
+    }
+
+  dlclose (handle);
+  return ret;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl6b.out b/binutils-2.19/ld/testsuite/ld-elf/dl6b.out
new file mode 100644
index 0000000..8cc87f5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl6b.out
@@ -0,0 +1 @@
+bar is in DSO.
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl6bmain.c b/binutils-2.19/ld/testsuite/ld-elf/dl6bmain.c
new file mode 100644
index 0000000..df9dbcc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl6bmain.c
@@ -0,0 +1,33 @@
+#include <stdio.h>
+#include <dlfcn.h>
+
+int bar = -20;
+
+int 
+main (void)
+{
+  int ret = 0;
+  void *handle;
+  void (*fcn) (void);
+
+  handle = dlopen("./tmpdir/libdl6b.so", RTLD_GLOBAL|RTLD_LAZY);
+  if (!handle)
+    {
+      printf("dlopen ./tmpdir/libdl6b.so: %s\n", dlerror ());
+      return 1;
+    }
+
+  fcn = (void (*)(void)) dlsym(handle, "foo");
+  if (!fcn)
+    {
+      printf("dlsym foo: %s\n", dlerror ());
+      ret += 1;
+    }
+  else
+    {
+      (*fcn) ();
+    }
+
+  dlclose (handle);
+  return ret;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl6cmain.c b/binutils-2.19/ld/testsuite/ld-elf/dl6cmain.c
new file mode 100644
index 0000000..f6c285c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl6cmain.c
@@ -0,0 +1,33 @@
+#include <stdio.h>
+#include <dlfcn.h>
+
+int bar = -20;
+
+int 
+main (void)
+{
+  int ret = 0;
+  void *handle;
+  void (*fcn) (void);
+
+  handle = dlopen("./tmpdir/libdl6c.so", RTLD_GLOBAL|RTLD_LAZY);
+  if (!handle)
+    {
+      printf("dlopen ./tmpdir/libdl6c.so: %s\n", dlerror ());
+      return 1;
+    }
+
+  fcn = (void (*)(void)) dlsym(handle, "foo");
+  if (!fcn)
+    {
+      printf("dlsym foo: %s\n", dlerror ());
+      ret += 1;
+    }
+  else
+    {
+      (*fcn) ();
+    }
+
+  dlclose (handle);
+  return ret;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dl6dmain.c b/binutils-2.19/ld/testsuite/ld-elf/dl6dmain.c
new file mode 100644
index 0000000..2e57eb7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dl6dmain.c
@@ -0,0 +1,33 @@
+#include <stdio.h>
+#include <dlfcn.h>
+
+int bar = -20;
+
+int 
+main (void)
+{
+  int ret = 0;
+  void *handle;
+  void (*fcn) (void);
+
+  handle = dlopen("./tmpdir/libdl6d.so", RTLD_GLOBAL|RTLD_LAZY);
+  if (!handle)
+    {
+      printf("dlopen ./tmpdir/libdl6d.so: %s\n", dlerror ());
+      return 1;
+    }
+
+  fcn = (void (*)(void)) dlsym(handle, "foo");
+  if (!fcn)
+    {
+      printf("dlsym foo: %s\n", dlerror ());
+      ret += 1;
+    }
+  else
+    {
+      (*fcn) ();
+    }
+
+  dlclose (handle);
+  return ret;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dummy.c b/binutils-2.19/ld/testsuite/ld-elf/dummy.c
new file mode 100644
index 0000000..5c03287
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dummy.c
@@ -0,0 +1 @@
+/* An empty file.  */
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dwarf.exp b/binutils-2.19/ld/testsuite/ld-elf/dwarf.exp
new file mode 100644
index 0000000..c313236
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dwarf.exp
@@ -0,0 +1,114 @@
+# Expect script for various DWARF tests.
+#   Copyright 2006, 2007  Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+#
+# Written by H.J. Lu (hongjiu.lu@intel.com)
+#
+
+# Exclude non-ELF targets.
+
+if ![is_elf_format] {
+    return
+}
+
+# The following tests require running the executable generated by ld.
+if ![isnative] {
+    return
+}
+
+# Check if compiler works
+if { [which $CC] == 0 } {
+    return
+}
+
+# Skip if -feliminate-dwarf2-dups isn't supported.
+if ![ld_compile "$CC -g -feliminate-dwarf2-dups" $srcdir/$subdir/dummy.c tmpdir/dummy.o] {
+    return
+}
+
+set build_tests {
+  {"Build libdwarf1.so"
+   "-s -shared" "-fPIC -g -feliminate-dwarf2-dups"
+   {dwarf1.c} {} "libdwarf1.so"}
+}
+
+set run_tests {
+    {"Run with libdwarf1.so first"
+     "tmpdir/libdwarf1.so" ""
+     {dwarf1main.c} "dwarf1a" "dwarf1.out"
+     "-g -feliminate-dwarf2-dups"}
+    {"Run with libdwarf1.so last"
+     "tmpdir/dwarf1main.o tmpdir/libdwarf1.so" ""
+     {dummy.c} "dwarf1b" "dwarf1.out"
+     "-g -feliminate-dwarf2-dups"}
+}
+
+run_cc_link_tests $build_tests
+run_ld_link_exec_tests [] $run_tests
+
+proc strip_test {} {
+    global ld
+    global strip
+    global NM
+
+    set test "libdwarf1c.so"
+    set test_name "Strip -s $test"
+    set prog $strip
+
+    if ![ld_simple_link $ld tmpdir/$test "-shared tmpdir/dwarf1.o"] {
+	unresolved "$test_name"
+	return
+    }
+
+    send_log "$NM -D tmpdir/$test > tmpdir/$test.exp\n"
+    catch "exec $NM -D tmpdir/$test > tmpdir/$test.exp" got
+    if ![string match "" $got] then {
+	send_log "$got\n"
+	unresolved "$test_name"
+	return
+    }
+
+    send_log "$prog -s tmpdir/$test\n"
+    catch "exec $prog -s tmpdir/$test" got
+    if ![string match "" $got] then {
+	send_log "$got\n"
+	fail "$test_name"
+	return
+    }
+
+    send_log "$NM -D tmpdir/$test > tmpdir/$test.out\n"
+    catch "exec $NM -D tmpdir/$test > tmpdir/$test.out" got
+    if ![string match "" $got] then {
+	send_log "$got\n"
+	unresolved "$test_name"
+ 	return
+    }
+
+    if { [catch {exec cmp tmpdir/$test.exp tmpdir/$test.out}] } then {
+	send_log "tmpdir/$test.exp tmpdir/$test.out differ.\n"
+ 	fail "$test_name"
+ 	return
+    }
+
+    pass "$test_name"
+}
+
+strip_test
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dwarf1.c b/binutils-2.19/ld/testsuite/ld-elf/dwarf1.c
new file mode 100644
index 0000000..2895d4c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dwarf1.c
@@ -0,0 +1,10 @@
+#include <stdio.h>
+#include "dwarf1.h"
+
+struct foo_s foo;
+
+void
+doprintf (void)
+{
+  printf ("OK\n");
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dwarf1.h b/binutils-2.19/ld/testsuite/ld-elf/dwarf1.h
new file mode 100644
index 0000000..3cd7918
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dwarf1.h
@@ -0,0 +1,6 @@
+struct foo_s
+{
+  int foo;
+};
+
+extern void doprintf (void);
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dwarf1.out b/binutils-2.19/ld/testsuite/ld-elf/dwarf1.out
new file mode 100644
index 0000000..d86bac9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dwarf1.out
@@ -0,0 +1 @@
+OK
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dwarf1main.c b/binutils-2.19/ld/testsuite/ld-elf/dwarf1main.c
new file mode 100644
index 0000000..9045198
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dwarf1main.c
@@ -0,0 +1,10 @@
+#include "dwarf1.h"
+
+struct foo_s foo;
+
+int
+main (void)
+{
+  doprintf ();
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/dynbss1.c b/binutils-2.19/ld/testsuite/ld-elf/dynbss1.c
new file mode 100644
index 0000000..eb5f067
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/dynbss1.c
@@ -0,0 +1,20 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include "data1.h"
+
+int
+main (void)
+{
+  if ((((long) (&a1)) & (ALIGNMENT1 - 1)))
+    abort ();
+  if ((((long) (&a2)) & (ALIGNMENT2 - 1)))
+    abort ();
+  if ((((long) (&a2)) & (ALIGNMENT3 - 1)))
+    abort ();
+  if ((((long) (&a3)) & (ALIGNMENT4 - 1)))
+    abort ();
+
+  printf ("PASS\n");
+
+  return(0) ;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh-frame-hdr.d b/binutils-2.19/ld/testsuite/ld-elf/eh-frame-hdr.d
new file mode 100644
index 0000000..af8ae04
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh-frame-hdr.d
@@ -0,0 +1,7 @@
+#source: eh-frame-hdr.s
+#ld: -e _start --eh-frame-hdr
+#objdump: -hw
+#target: cfi
+#...
+  [0-9] .eh_frame_hdr 0*[12][048c] .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh-frame-hdr.s b/binutils-2.19/ld/testsuite/ld-elf/eh-frame-hdr.s
new file mode 100644
index 0000000..e5d3318
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh-frame-hdr.s
@@ -0,0 +1,6 @@
+	.text
+	.global _start
+_start:
+	.cfi_startproc
+	.skip 16
+	.cfi_endproc
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh-group.exp b/binutils-2.19/ld/testsuite/ld-elf/eh-group.exp
new file mode 100644
index 0000000..c55e06e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh-group.exp
@@ -0,0 +1,51 @@
+# Expect script for .eh_frame entries to a removed section.
+#   Copyright 2008  Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+#
+# Written by Jan Kratochvil (jan.kratochvil@redhat.com)
+#
+# .eh_frame with relocations to a removed (group) section did result to:
+# error in tmpdir/eh-group.o(.eh_frame); no .eh_frame_hdr table will be created.
+# The purpose of this test is to merge two .o files with -r and then link this
+# merged file (containing a discarded R_X86_64_NONE relocation) to the final
+# executable trying to create .eh_frame_hdr.  It needs a separate .exp file due
+# to the requirement of two `ld' runs.
+
+# Exclude non-CFI (such as ia64) targets.
+
+if {![check_as_cfi]} {
+    return
+}
+
+set build_tests_ld {
+  {"Build eh-group1.o"
+   "-r" ""
+   {eh-group1.s eh-group2.s} {} "eh-group.o"}
+}
+
+run_ld_link_tests $build_tests_ld
+
+set testname "Link eh-group.o to eh-group"
+if [ld_simple_link $ld "tmpdir/eh-group" "-e _start tmpdir/eh-group.o"] {
+    pass $testname
+} else {
+    fail $testname
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh-group1.s b/binutils-2.19/ld/testsuite/ld-elf/eh-group1.s
new file mode 100644
index 0000000..d6fdb88
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh-group1.s
@@ -0,0 +1,6 @@
+	.section	sect, "axG", %progbits, sectgroup, comdat
+	.global	_start
+_start:
+	.cfi_startproc
+	.skip 16
+	.cfi_endproc
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh-group2.s b/binutils-2.19/ld/testsuite/ld-elf/eh-group2.s
new file mode 100644
index 0000000..2ec8919
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh-group2.s
@@ -0,0 +1,4 @@
+	.section	sect, "axG", %progbits, sectgroup, comdat
+	.cfi_startproc
+	.skip 16
+	.cfi_endproc
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh1.d b/binutils-2.19/ld/testsuite/ld-elf/eh1.d
new file mode 100644
index 0000000..a672f5b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh1.d
@@ -0,0 +1,33 @@
+#source: eh1.s
+#source: eh1a.s
+#ld:
+#readelf: -wf
+#target: x86_64-*-*
+
+The section .eh_frame contains:
+
+00000000 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          ""
+  Code alignment factor: 1
+  Data alignment factor: -8
+  Return address column: 16
+
+  DW_CFA_def_cfa: r7 \(rsp\) ofs 8
+  DW_CFA_offset: r16 \(rip\) at cfa-8
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000018 0000001c 0000001c FDE cie=00000000 pc=00400078..00400078
+  DW_CFA_advance_loc: 0 to 00400078
+  DW_CFA_def_cfa_offset: 16
+  DW_CFA_offset: r6 \(rbp\) at cfa-16
+  DW_CFA_advance_loc: 0 to 00400078
+  DW_CFA_def_cfa_register: r6 \(rbp\)
+
+00000038 ZERO terminator
+
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh1.s b/binutils-2.19/ld/testsuite/ld-elf/eh1.s
new file mode 100644
index 0000000..a605209
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh1.s
@@ -0,0 +1,47 @@
+	.text
+.globl _start
+	.type	_start, %function
+_start:
+.LFB2:
+.LCFI0:
+.LCFI1:
+.LFE2:
+	.size	_start, .-_start
+	.section	.eh_frame,"a",%progbits
+.Lframe1:
+	.long	.LECIE1-.LSCIE1
+.LSCIE1:
+	.long	0x0
+	.byte	0x1
+	.string	""
+	.uleb128 0x1
+	.sleb128 -8
+	.byte	0x10
+	.byte	0xc
+	.uleb128 0x7
+	.uleb128 0x8
+	.byte	0x90
+	.uleb128 0x1
+	.align 8
+.LECIE1:
+.LSFDE1:
+	.long	.LEFDE1-.LASFDE1
+.LASFDE1:
+	.long	.LASFDE1-.Lframe1
+	.quad	.LFB2
+	.quad	.LFE2-.LFB2
+	.byte	0x4
+	.long	.LCFI0-.LFB2
+	.byte	0xe
+	.uleb128 0x10
+	.byte	0x86
+	.uleb128 0x2
+	.byte	0x4
+	.long	.LCFI1-.LCFI0
+	.byte	0xd
+	.uleb128 0x6
+	.byte 0x0
+	.byte 0x0
+	.byte 0x0
+	.byte 0x0
+.LEFDE1:
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh1a.s b/binutils-2.19/ld/testsuite/ld-elf/eh1a.s
new file mode 100644
index 0000000..c644014
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh1a.s
@@ -0,0 +1,3 @@
+	.section	.eh_frame,"a",%progbits
+	.align	8
+	.zero	4
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh2.d b/binutils-2.19/ld/testsuite/ld-elf/eh2.d
new file mode 100644
index 0000000..788d23d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh2.d
@@ -0,0 +1,33 @@
+#source: eh1.s
+#source: eh2a.s
+#ld:
+#readelf: -wf
+#target: x86_64-*-*
+
+The section .eh_frame contains:
+
+00000000 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          ""
+  Code alignment factor: 1
+  Data alignment factor: -8
+  Return address column: 16
+
+  DW_CFA_def_cfa: r7 \(rsp\) ofs 8
+  DW_CFA_offset: r16 \(rip\) at cfa-8
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000018 0000001c 0000001c FDE cie=00000000 pc=00400078..00400078
+  DW_CFA_advance_loc: 0 to 00400078
+  DW_CFA_def_cfa_offset: 16
+  DW_CFA_offset: r6 \(rbp\) at cfa-16
+  DW_CFA_advance_loc: 0 to 00400078
+  DW_CFA_def_cfa_register: r6 \(rbp\)
+
+00000038 ZERO terminator
+
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh2a.s b/binutils-2.19/ld/testsuite/ld-elf/eh2a.s
new file mode 100644
index 0000000..2c024f8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh2a.s
@@ -0,0 +1,3 @@
+	.section	.eh_frame,"a",%progbits
+	.align	4
+	.zero	4
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh3.d b/binutils-2.19/ld/testsuite/ld-elf/eh3.d
new file mode 100644
index 0000000..6816313
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh3.d
@@ -0,0 +1,33 @@
+#source: eh3.s
+#source: eh3a.s
+#ld:
+#readelf: -wf
+#target: x86_64-*-*
+
+The section .eh_frame contains:
+
+00000000 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          ""
+  Code alignment factor: 1
+  Data alignment factor: -8
+  Return address column: 16
+
+  DW_CFA_def_cfa: r7 \(rsp\) ofs 8
+  DW_CFA_offset: r16 \(rip\) at cfa-8
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000018 0000001c 0000001c FDE cie=00000000 pc=00400078..00400078
+  DW_CFA_advance_loc: 0 to 00400078
+  DW_CFA_def_cfa_offset: 16
+  DW_CFA_offset: r6 \(rbp\) at cfa-16
+  DW_CFA_advance_loc: 0 to 00400078
+  DW_CFA_def_cfa_register: r6 \(rbp\)
+
+00000038 ZERO terminator
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh3.s b/binutils-2.19/ld/testsuite/ld-elf/eh3.s
new file mode 100644
index 0000000..24bd90d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh3.s
@@ -0,0 +1,48 @@
+	.text
+.globl _start
+	.type	_start, %function
+_start:
+.LFB2:
+.LCFI0:
+.LCFI1:
+.LFE2:
+	.size	_start, .-_start
+	.section	.eh_frame,"a",%progbits
+	.align 16
+.Lframe1:
+	.long	.LECIE1-.LSCIE1
+.LSCIE1:
+	.long	0x0
+	.byte	0x1
+	.string	""
+	.uleb128 0x1
+	.sleb128 -8
+	.byte	0x10
+	.byte	0xc
+	.uleb128 0x7
+	.uleb128 0x8
+	.byte	0x90
+	.uleb128 0x1
+	.align 8
+.LECIE1:
+.LSFDE1:
+	.long	.LEFDE1-.LASFDE1
+.LASFDE1:
+	.long	.LASFDE1-.Lframe1
+	.quad	.LFB2
+	.quad	.LFE2-.LFB2
+	.byte	0x4
+	.long	.LCFI0-.LFB2
+	.byte	0xe
+	.uleb128 0x10
+	.byte	0x86
+	.uleb128 0x2
+	.byte	0x4
+	.long	.LCFI1-.LCFI0
+	.byte	0xd
+	.uleb128 0x6
+	.byte 0x0
+	.byte 0x0
+	.byte 0x0
+	.byte 0x0
+.LEFDE1:
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh3a.s b/binutils-2.19/ld/testsuite/ld-elf/eh3a.s
new file mode 100644
index 0000000..c245871
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh3a.s
@@ -0,0 +1,3 @@
+	.section	.eh_frame,"a",%progbits
+	.align	8
+	.zero	8
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh4.d b/binutils-2.19/ld/testsuite/ld-elf/eh4.d
new file mode 100644
index 0000000..5efecab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh4.d
@@ -0,0 +1,32 @@
+#source: eh4.s
+#source: eh4a.s
+#ld: -shared
+#readelf: -wf
+#target: x86_64-*-*
+
+The section .eh_frame contains:
+
+00000000 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zR"
+  Code alignment factor: 1
+  Data alignment factor: -8
+  Return address column: 16
+  Augmentation data:     1b
+
+  DW_CFA_def_cfa: r7 \(rsp\) ofs 8
+  DW_CFA_offset: r16 \(rip\) at cfa-8
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000018 00000014 0000001c FDE cie=00000000 pc=00000400..00000413
+  DW_CFA_set_loc: 00000404
+  DW_CFA_def_cfa_offset: 80
+
+00000030 00000014 00000034 FDE cie=00000000 pc=00000413..00000426
+  DW_CFA_set_loc: 00000417
+  DW_CFA_def_cfa_offset: 80
+
+00000048 ZERO terminator
+#pass
+
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh4.s b/binutils-2.19/ld/testsuite/ld-elf/eh4.s
new file mode 100644
index 0000000..2714ad6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh4.s
@@ -0,0 +1,92 @@
+	.text
+	.align	512
+	.globl foo
+	.type	foo, @function
+foo:
+.LFB1:
+	subq	$72, %rsp
+.LCFI1:
+	xorl	%eax, %eax
+	movq	%rsp, %rdi
+	call	bar@PLT
+	addq	$72, %rsp
+	ret
+.LFE1:
+	.size	foo, .-foo
+	.globl bar
+	.type	bar, @function
+bar:
+.LFB2:
+	subq	$72, %rsp
+.LCFI2:
+	xorl	%eax, %eax
+	movq	%rsp, %rdi
+	call	bar@PLT
+	addq	$72, %rsp
+	ret
+.LFE2:
+	.size	bar, .-bar
+	.section	.eh_frame,"a",@progbits
+.Lframe1:
+	.long	.LECIE1-.LSCIE1	# Length of Common Information Entry
+.LSCIE1:
+	.long	0x0	# CIE Identifier Tag
+	.byte	0x1	# CIE Version
+	.ascii "zR\0"	# CIE Augmentation
+	.uleb128 0x1	# CIE Code Alignment Factor
+	.sleb128 -8	# CIE Data Alignment Factor
+	.byte	0x10	# CIE RA Column
+	.uleb128 0x1	# Augmentation size
+	.byte	0x1b	# FDE Encoding (pcrel sdata4)
+	.byte	0xc	# DW_CFA_def_cfa
+	.uleb128 0x7
+	.uleb128 0x8
+	.byte	0x90	# DW_CFA_offset, column 0x10
+	.uleb128 0x1
+	.align 8
+.LECIE1:
+.LSFDE1:
+	.long	.LEFDE1-.LASFDE1	# FDE Length
+.LASFDE1:
+	.long	.LASFDE1-.Lframe1	# FDE CIE offset
+	.long	.LFB1-.	# FDE initial location
+	.long	.LFE1-.LFB1	# FDE address range
+	.uleb128 0x0	# Augmentation size
+	.byte	0x1	# DW_CFA_set_loc
+	.long	.LCFI1-.
+	.byte	0xe	# DW_CFA_def_cfa_offset
+	.uleb128 0x50
+	.align 8
+.LEFDE1:
+.Lframe2:
+	.long	.LECIE2-.LSCIE2	# Length of Common Information Entry
+.LSCIE2:
+	.long	0x0	# CIE Identifier Tag
+	.byte	0x1	# CIE Version
+	.ascii "zR\0"	# CIE Augmentation
+	.uleb128 0x1	# CIE Code Alignment Factor
+	.sleb128 -8	# CIE Data Alignment Factor
+	.byte	0x10	# CIE RA Column
+	.uleb128 0x1	# Augmentation size
+	.byte	0x1b	# FDE Encoding (pcrel sdata4)
+	.byte	0xc	# DW_CFA_def_cfa
+	.uleb128 0x7
+	.uleb128 0x8
+	.byte	0x90	# DW_CFA_offset, column 0x10
+	.uleb128 0x1
+	.align 8
+.LECIE2:
+.LSFDE2:
+	.long	.LEFDE2-.LASFDE2	# FDE Length
+.LASFDE2:
+	.long	.LASFDE2-.Lframe2	# FDE CIE offset
+	.long	.LFB2-.	# FDE initial location
+	.long	.LFE2-.LFB2	# FDE address range
+	.uleb128 0x0	# Augmentation size
+	.byte	0x1	# DW_CFA_set_loc
+	.long	.LCFI2-.
+	.byte	0xe	# DW_CFA_def_cfa_offset
+	.uleb128 0x50
+	.align 8
+.LEFDE2:
+	.section	.note.GNU-stack,"",@progbits
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh4a.s b/binutils-2.19/ld/testsuite/ld-elf/eh4a.s
new file mode 100644
index 0000000..c245871
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh4a.s
@@ -0,0 +1,3 @@
+	.section	.eh_frame,"a",%progbits
+	.align	8
+	.zero	8
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh5.d b/binutils-2.19/ld/testsuite/ld-elf/eh5.d
new file mode 100644
index 0000000..051eaca
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh5.d
@@ -0,0 +1,162 @@
+#source: eh5.s
+#source: eh5a.s
+#source: eh5b.s
+#ld:
+#readelf: -wf
+#target: cfi
+#notarget: alpha*
+
+The section .eh_frame contains:
+
+00000000 0000001[04] 00000000 CIE
+  Version:               1
+  Augmentation:          "zR"
+  Code alignment factor: .*
+  Data alignment factor: .*
+  Return address column: .*
+  Augmentation data:     1b
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+#...
+0000001[48] 00000014 0000001[8c] FDE cie=00000000 pc=.*
+  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000(2c|30) 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zPR"
+  Code alignment factor: .*
+  Data alignment factor: .*
+  Return address column: .*
+  Augmentation data:     03 .. .. .. .. 1b
+
+  DW_CFA_nop
+
+0000004[48] 00000014 0000001c FDE cie=000000(2c|30) pc=.*
+  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000(5c|60) 00000014 0000006[04] FDE cie=00000000 pc=.*
+  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+0000007[48] 0000001[8c] 00000000 CIE
+  Version:               1
+  Augmentation:          "zPLR"
+  Code alignment factor: .*
+  Data alignment factor: .*
+  Return address column: .*
+  Augmentation data:     03 .. .. .. .. 0c 1b
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+#...
+0000009[08] 0000001c 0000002[04] FDE cie=0000007[48] pc=.*
+  Augmentation data:     (ef be ad de 00 00 00 00|00 00 00 00 de ad be ef)
+
+  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000b[08] 0000001[04] 00000000 CIE
+  Version:               1
+  Augmentation:          "zR"
+  Code alignment factor: .*
+  Data alignment factor: .*
+  Return address column: .*
+  Augmentation data:     1b
+
+  DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16
+#...
+000000(c4|d0) 0000001[04] 0000001[8c] FDE cie=000000b[08] pc=.*
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+#...
+000000[de]8 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zPR"
+  Code alignment factor: .*
+  Data alignment factor: .*
+  Return address column: .*
+  Augmentation data:     03 .. .. .. .. 1b
+
+  DW_CFA_nop
+
+00000(0f|10)0 00000014 0000001c FDE cie=000000[de]8 pc=.*
+  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001[01]8 0000001[04] 000000(5c|64) FDE cie=000000b[08] pc=.*
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+#...
+000001(1c|30) 0000001[8c] 00000000 CIE
+  Version:               1
+  Augmentation:          "zPLR"
+  Code alignment factor: .*
+  Data alignment factor: .*
+  Return address column: .*
+  Augmentation data:     03 .. .. .. .. 0c 1b
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+#...
+000001(38|50) 0000001c 0000002[04] FDE cie=000001(1c|30) pc=.*
+  Augmentation data:     (ef be ad de 00 00 00 00|00 00 00 00 de ad be ef)
+
+  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001(58|70) 00000014 000001(5c|74) FDE cie=00000000 pc=.*
+  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001(70|88) 00000014 000001(48|5c) FDE cie=000000(2c|30) pc=.*
+  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001(88|a0) 00000014 000001(8c|a4) FDE cie=00000000 pc=.*
+  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001(a0|b8) 0000001c 000001(30|44) FDE cie=0000007[48] pc=.*
+  Augmentation data:     (ef be ad de 00 00 00 00|00 00 00 00 de ad be ef)
+
+  DW_CFA_advance_loc: 4 to .*
+  DW_CFA_def_cfa: r0( \([er]ax\)|) ofs 16
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh5.s b/binutils-2.19/ld/testsuite/ld-elf/eh5.s
new file mode 100644
index 0000000..6af48c2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh5.s
@@ -0,0 +1,29 @@
+	.text
+	.cfi_startproc simple
+	.long 0
+	.cfi_def_cfa 0, 16
+	.long 0
+	.cfi_endproc
+
+	.cfi_startproc simple
+	.cfi_personality 3, my_personality_v0
+	.long 0
+	.cfi_def_cfa 0, 16
+	.cfi_endproc
+
+	.cfi_startproc simple
+	.long 0
+	.cfi_def_cfa 0, 16
+	.long 0
+	.cfi_endproc
+
+	.cfi_startproc simple
+	.cfi_personality 3, my_personality_v0
+	.cfi_lsda 12, 0xdeadbeef
+	.long 0
+	.cfi_def_cfa 0, 16
+	.cfi_endproc
+
+	.globl my_personality_v0
+my_personality_v0:
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh5a.s b/binutils-2.19/ld/testsuite/ld-elf/eh5a.s
new file mode 100644
index 0000000..a74b2cc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh5a.s
@@ -0,0 +1,27 @@
+	.text
+	.cfi_startproc simple
+	.cfi_def_cfa 0, 16
+	.long 0
+	.cfi_endproc
+
+	.cfi_startproc simple
+	.cfi_personality 3, my_personality_v1
+	.long 0
+	.cfi_def_cfa 0, 16
+	.cfi_endproc
+
+	.cfi_startproc simple
+	.cfi_def_cfa 0, 16
+	.long 0
+	.cfi_endproc
+
+	.cfi_startproc simple
+	.cfi_personality 3, my_personality_v1
+	.cfi_lsda 12, 0xdeadbeef
+	.long 0
+	.cfi_def_cfa 0, 16
+	.cfi_endproc
+
+	.globl my_personality_v1
+my_personality_v1:
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh5b.s b/binutils-2.19/ld/testsuite/ld-elf/eh5b.s
new file mode 100644
index 0000000..3e5e010
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh5b.s
@@ -0,0 +1,29 @@
+	.text
+	.cfi_startproc simple
+	.long 0
+	.cfi_def_cfa 0, 16
+	.long 0
+	.cfi_endproc
+
+	.cfi_startproc simple
+	.cfi_personality 3, my_personality_v0
+	.long 0
+	.cfi_def_cfa 0, 16
+	.cfi_endproc
+
+	.cfi_startproc simple
+	.long 0
+	.cfi_def_cfa 0, 16
+	.long 0
+	.cfi_endproc
+
+	.cfi_startproc simple
+	.cfi_personality 3, my_personality_v0
+	.cfi_lsda 12, 0xdeadbeef
+	.long 0
+	.cfi_def_cfa 0, 16
+	.cfi_endproc
+
+	.globl _start
+_start:
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh6.d b/binutils-2.19/ld/testsuite/ld-elf/eh6.d
new file mode 100644
index 0000000..7f4e47a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh6.d
@@ -0,0 +1,17 @@
+#source: eh6.s
+#ld: --gc-sections -shared
+#readelf: -wf
+#target: x86_64-*-linux-gnu i?86-*-linux-gnu
+
+The section .eh_frame contains:
+
+00000000 0000001[4c] 00000000 CIE
+  Version:               1
+  Augmentation:          "zPR"
+  Code alignment factor: 1
+  Data alignment factor: .*
+  Return address column: .*
+  Augmentation data:     80 .* 1b
+
+  DW_CFA_nop
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/eh6.s b/binutils-2.19/ld/testsuite/ld-elf/eh6.s
new file mode 100644
index 0000000..bdc7dd1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/eh6.s
@@ -0,0 +1,17 @@
+	.section .text.foo, "ax", @progbits
+	.globl	foo
+	.type	foo, @function
+foo:
+	.cfi_startproc simple
+	.cfi_personality 0x80, indirect_ptr
+	ret
+	.cfi_endproc
+	.size	foo, . - foo
+
+	.section .data.rel.ro, "a", @progbits
+indirect_ptr:
+	.long my_personality_v0
+
+	.globl my_personality_v0
+my_personality_v0:
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/elf.exp b/binutils-2.19/ld/testsuite/ld-elf/elf.exp
new file mode 100644
index 0000000..080d985
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/elf.exp
@@ -0,0 +1,80 @@
+# Expect script for various ELF tests.
+#   Copyright 2002, 2003, 2005, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Exclude non-ELF targets.
+
+if ![is_elf_format] {
+    return
+}
+
+if { [istarget spu*-*-*] } {
+    set LDFLAGS "$LDFLAGS --local-store 0:0"
+}
+
+if { [is_remote host] } then {
+    remote_download host merge.ld
+}
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach t $test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname $t]
+    run_dump_test [file rootname $t]
+}
+
+if { [istarget *-*-linux*] } {
+    run_ld_link_tests {
+	{"Weak symbols in dynamic objects 1 (support)"
+	    "-shared" "" {weak-dyn-1a.s}
+	    {}
+	    "libweakdyn1a.so"}
+	{"Weak symbols in dynamic objects 1 (main test)"
+	    "-shared tmpdir/libweakdyn1a.so -Tweak-dyn-1.ld" "" {weak-dyn-1b.s}
+	    {{readelf {--relocs --wide} weak-dyn-1.rd}}
+	    "libweakdyn1b.so"}
+    }
+}
+
+if { [check_gc_sections_available] } {
+    run_ld_link_tests {
+	{"--gc-sections on tls variable"
+	    "--gc-section" "" {tls_gc.s} {} "tls_gc"}
+    }
+}
+
+# The following tests require running the executable generated by ld.
+if ![isnative] {
+    return
+}
+
+set array_tests {
+    {"preinit array" "" "" {preinit.c} "preinit" "preinit.out"}
+    {"static preinit array" "-static" "" {preinit.c} "preinit" "preinit.out"}
+    {"init array" "" "" {init.c} "init" "init.out"}
+    {"static init array" "-static" "" {init.c} "init" "init.out"}
+    {"fini array" "" "" {fini.c} "fini" "fini.out"}
+    {"static fini array" "-static" "" {fini.c} "fini" "fini.out"}
+}
+
+# NetBSD ELF systems do not currently support the .*_array sections.
+run_ld_link_exec_tests [list "*-*-netbsdelf*"] $array_tests
+
+catch "exec rm -f tmpdir/preinit tmpdir/init tmpdir/fini" status
diff --git a/binutils-2.19/ld/testsuite/ld-elf/empty.d b/binutils-2.19/ld/testsuite/ld-elf/empty.d
new file mode 100644
index 0000000..ecf8aea
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/empty.d
@@ -0,0 +1,7 @@
+#source: empty.s
+#ld:
+#readelf: -s
+
+#...
+[ 	]+[0-9]+:[ 	]+[0-9a-f]+[ 	]+[0-9]+[ 	]+FUNC[	 ]+GLOBAL DEFAULT[ 	]+[1-9] _start
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/empty.s b/binutils-2.19/ld/testsuite/ld-elf/empty.s
new file mode 100644
index 0000000..8c2d0e6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/empty.s
@@ -0,0 +1,16 @@
+	.section .bss
+bar:
+	.text
+	.type start,"function"
+	.global start
+start:
+	.type _start,"function"
+	.global _start
+_start:
+	.type __start,"function"
+	.global __start
+__start:
+	.type main,"function"
+	.global main
+main:
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/empty2.d b/binutils-2.19/ld/testsuite/ld-elf/empty2.d
new file mode 100644
index 0000000..8da351a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/empty2.d
@@ -0,0 +1,12 @@
+#source: empty2.s
+#ld:
+#readelf: -s
+#xfail: "d30v-*-*" "dlx-*-*" "hppa*-*-*" "i960-*-*" "or32-*-*" "pj-*-*"
+
+#...
+[ 	]+[0-9]+:[ 	]+0+[ 	]+0[ 	]+FILE[	 ]+LOCAL[ 	]+DEFAULT[ 	]+ABS empty2.s
+#...
+[ 	]+[0-9]+:[ 	]+0*12345678[ 	]+0[ 	]+NOTYPE[	 ]+LOCAL[ 	]+DEFAULT[ 	]+ABS constant
+#...
+[ 	]+[0-9]+:[ 	]+[0-9a-f]+[ 	]+[0-9]+[ 	]+FUNC[	 ]+GLOBAL[ 	]+DEFAULT[ 	]+[1-9] _start
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/empty2.s b/binutils-2.19/ld/testsuite/ld-elf/empty2.s
new file mode 100644
index 0000000..deed318
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/empty2.s
@@ -0,0 +1,18 @@
+	.file "empty2.s"
+	.equiv constant, 0x12345678
+	.section .bss
+bar:
+	.text
+	.type start,"function"
+	.global start
+start:
+	.type _start,"function"
+	.global _start
+_start:
+	.type __start,"function"
+	.global __start
+__start:
+	.type main,"function"
+	.global main
+main:
+	.long constant
diff --git a/binutils-2.19/ld/testsuite/ld-elf/end.c b/binutils-2.19/ld/testsuite/ld-elf/end.c
new file mode 100644
index 0000000..f7b681a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/end.c
@@ -0,0 +1,7 @@
+#include <stdio.h>
+
+void
+foo ()
+{
+  printf ("TEST1\n");
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/endhidden.c b/binutils-2.19/ld/testsuite/ld-elf/endhidden.c
new file mode 100644
index 0000000..2cab97a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/endhidden.c
@@ -0,0 +1,8 @@
+#include <stdio.h>
+
+__attribute__ ((visibility ("hidden")))
+void
+foo ()
+{
+  printf ("TEST1\n");
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/endprotected.c b/binutils-2.19/ld/testsuite/ld-elf/endprotected.c
new file mode 100644
index 0000000..b6b39ea
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/endprotected.c
@@ -0,0 +1,8 @@
+#include <stdio.h>
+
+__attribute__ ((visibility ("protected")))
+void
+foo ()
+{
+  printf ("TEST1\n");
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/exclude.exp b/binutils-2.19/ld/testsuite/ld-elf/exclude.exp
new file mode 100644
index 0000000..264c138
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/exclude.exp
@@ -0,0 +1,140 @@
+# Expect script for --exclude-libs tests
+#   Copyright 2004, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# Make sure that ld can hide symbols from libraries when building a shared
+# library.
+
+# This test can only be run on ELF platforms.
+if ![is_elf_format] {
+    return
+}
+
+# No shared lib support on this target.
+if { [istarget "mcore-*-*"] } {
+    return
+}
+
+global ar
+global as
+global ld
+global nm
+global nm_output
+
+set test1 "ld link shared library"
+set test2 "ld export symbols from archive"
+set test3 "ld link shared library with --exclude-libs"
+set test4 "ld exclude symbols from archive - --exclude-libs libexclude"
+set test5 "ld exclude symbols from archive - --exclude-libs libexclude.a"
+set test6 "ld exclude symbols from archive - --exclude-libs ALL"
+set test7 "ld exclude symbols from archive - --exclude-libs foo:libexclude.a"
+set test8 "ld exclude symbols from archive - --exclude-libs foo,libexclude.a"
+set test9 "ld don't exclude symbols from archive - --exclude-libs foo:bar"
+
+if { ![ld_assemble $as $srcdir/$subdir/exclude1.s tmpdir/exclude1.o ]
+     || ![ld_assemble $as $srcdir/$subdir/exclude2.s tmpdir/exclude2.o] } {
+    unresolved $test1
+    return
+}
+
+remote_file host delete "tmpdir/libexclude.a"
+set catch_output [run_host_cmd "$ar" "cq tmpdir/libexclude.a tmpdir/exclude2.o"]
+if {![string match "" $catch_output]} {
+    unresolved $test1
+    return
+}
+
+# Test that the symbol is normally exported.
+
+if { [ld_simple_link $ld tmpdir/exclude.so "--shared tmpdir/exclude1.o -Ltmpdir -lexclude"] } {
+    pass $test1
+} else {
+    if [string match "*shared not supported*" $link_output] {
+	unsupported "$test1 - -shared is not supported by this target"
+    } else {
+	fail $test1
+    }
+    return
+}
+
+if ![ld_nm $nm "-D" tmpdir/exclude.so] {
+    unresolved $test2
+} elseif { [info exists nm_output(exclude_sym)] } {
+    pass $test2
+} else {
+    fail $test2
+}
+
+# Test --exclude-libs libexclude
+
+if { [ld_simple_link $ld tmpdir/exclude.so "--exclude-libs libexclude --shared tmpdir/exclude1.o -Ltmpdir -lexclude"] } {
+    pass $test3
+} else {
+    fail $test3
+}
+
+if ![ld_nm $nm "-D" tmpdir/exclude.so] {
+    unresolved $test4
+} elseif { ! [info exists nm_output(exclude_sym)] } {
+    pass $test4
+} else {
+    fail $test4
+}
+
+# Test alternate spellings of --exclude-libs
+
+if { [ld_simple_link $ld tmpdir/exclude.so "--exclude-libs libexclude.a --shared tmpdir/exclude1.o -Ltmpdir -lexclude"]
+     && [ld_nm $nm "-D" tmpdir/exclude.so]
+     && ! [info exists nm_output(exclude_sym)] } {
+    pass $test5
+} else {
+    fail $test5
+}
+
+if { [ld_simple_link $ld tmpdir/exclude.so "--exclude-libs ALL --shared tmpdir/exclude1.o -Ltmpdir -lexclude"]
+     && [ld_nm $nm "-D" tmpdir/exclude.so]
+     && ! [info exists nm_output(exclude_sym)] } {
+    pass $test6
+} else {
+    fail $test6
+}
+
+if { [ld_simple_link $ld tmpdir/exclude.so "--exclude-libs foo:libexclude.a --shared tmpdir/exclude1.o -Ltmpdir -lexclude"]
+     && [ld_nm $nm "-D" tmpdir/exclude.so]
+     && ! [info exists nm_output(exclude_sym)] } {
+    pass $test7
+} else {
+    fail $test7
+}
+
+if { [ld_simple_link $ld tmpdir/exclude.so "--exclude-libs foo,libexclude.a --shared tmpdir/exclude1.o -Ltmpdir -lexclude"]
+     && [ld_nm $nm "-D" tmpdir/exclude.so]
+     && ! [info exists nm_output(exclude_sym)] } {
+    pass $test8
+} else {
+    fail $test8
+}
+
+if { [ld_simple_link $ld tmpdir/exclude.so "--exclude-libs foo:bar --shared tmpdir/exclude1.o -Ltmpdir -lexclude"]
+     && [ld_nm $nm "-D" tmpdir/exclude.so]
+     && [info exists nm_output(exclude_sym)] } {
+    pass $test9
+} else {
+    fail $test9
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/exclude1.s b/binutils-2.19/ld/testsuite/ld-elf/exclude1.s
new file mode 100644
index 0000000..99efc7e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/exclude1.s
@@ -0,0 +1,4 @@
+	.globl include_sym
+	.data
+include_sym:
+	.dc.a	exclude_sym
diff --git a/binutils-2.19/ld/testsuite/ld-elf/exclude2.s b/binutils-2.19/ld/testsuite/ld-elf/exclude2.s
new file mode 100644
index 0000000..e9b5819
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/exclude2.s
@@ -0,0 +1,4 @@
+	.globl exclude_sym
+	.data
+exclude_sym:
+	.long	0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/expr1.d b/binutils-2.19/ld/testsuite/ld-elf/expr1.d
new file mode 100644
index 0000000..7bf5d22
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/expr1.d
@@ -0,0 +1,2 @@
+# ld: -T expr1.t
+# error: expr1.t:3: nonconstant expression for load base
diff --git a/binutils-2.19/ld/testsuite/ld-elf/expr1.s b/binutils-2.19/ld/testsuite/ld-elf/expr1.s
new file mode 100644
index 0000000..998bbc0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/expr1.s
@@ -0,0 +1,4 @@
+	.section .bar,"ax","progbits"
+	.byte 0
+	.section .foo,"aw","progbits"
+	.byte 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/expr1.t b/binutils-2.19/ld/testsuite/ld-elf/expr1.t
new file mode 100644
index 0000000..9670e25
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/expr1.t
@@ -0,0 +1,6 @@
+SECTIONS
+{
+  .bar : AT ((ADDR(.foo) + 4095) & ~(4095)) { *(.bar) }
+  .foo : { *(.foo) }
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/extract-symbol-1.ld b/binutils-2.19/ld/testsuite/ld-elf/extract-symbol-1.ld
new file mode 100644
index 0000000..53e95c6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/extract-symbol-1.ld
@@ -0,0 +1,18 @@
+ENTRY(_entry)
+PHDRS
+{
+  data PT_LOAD AT (0);
+}
+SECTIONS
+{
+  . = 0x10000;
+  .foo : { *(.foo) } :data
+
+  . = 0x20000;
+  .bar : { *(.bar) } :data
+
+  /DISCARD/ : { *(*) }
+
+  _entry = 0x30000;
+  linker_symbol = 0x40000;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/extract-symbol-1.s b/binutils-2.19/ld/testsuite/ld-elf/extract-symbol-1.s
new file mode 100644
index 0000000..0971500
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/extract-symbol-1.s
@@ -0,0 +1,15 @@
+	.globl		B
+	.globl		C
+
+	.section	.foo,"awx",%progbits
+	.4byte		1,2,3,4
+B:
+	.4byte		5,6,7
+
+	.section	.bar,"ax",%nobits
+	.space		0x123
+C:
+	.space		0x302
+
+	.globl		D
+	.equ		D,0x12345678
diff --git a/binutils-2.19/ld/testsuite/ld-elf/extract-symbol-1sec.d b/binutils-2.19/ld/testsuite/ld-elf/extract-symbol-1sec.d
new file mode 100644
index 0000000..cbe0144
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/extract-symbol-1sec.d
@@ -0,0 +1,13 @@
+#name: --extract-symbol test 1 (sections)
+#source: extract-symbol-1.s
+#ld: -Textract-symbol-1.ld
+#objcopy_linked_file: --extract-symbol
+#objdump: --headers
+#xfail: "hppa*-*-*"
+#...
+Sections:
+ *Idx +Name +Size +VMA +LMA .*
+ *0 +\.foo +0+ +0+10000 +0+ .*
+ *CONTENTS, ALLOC, LOAD, CODE
+ *1 +\.bar +0+ +0+20000 +0+10000 .*
+ *ALLOC, READONLY, CODE
diff --git a/binutils-2.19/ld/testsuite/ld-elf/extract-symbol-1sym.d b/binutils-2.19/ld/testsuite/ld-elf/extract-symbol-1sym.d
new file mode 100644
index 0000000..f372932
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/extract-symbol-1sym.d
@@ -0,0 +1,11 @@
+#name: --extract-symbol test 1 (symbols)
+#source: extract-symbol-1.s
+#ld: -Textract-symbol-1.ld
+#objcopy_linked_file: --extract-symbol
+#nm: -n
+#xfail: "hppa*-*-*"
+0*00010010 T B
+0*00020123 T C
+0*00030000 A _entry
+0*00040000 A linker_symbol
+0*12345678 A D
diff --git a/binutils-2.19/ld/testsuite/ld-elf/fini.c b/binutils-2.19/ld/testsuite/ld-elf/fini.c
new file mode 100644
index 0000000..cb60655
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/fini.c
@@ -0,0 +1,34 @@
+#include <stdio.h>
+
+static void
+fini_0 (void)
+{
+  printf ("fini array 0\n");
+}
+
+static void
+fini_1 (void)
+{
+  printf ("fini array 1\n");
+}
+
+static void
+fini_2 (void)
+{
+  printf ("fini array 2\n");
+}
+
+void (*const fini_array []) (void)
+     __attribute__ ((section (".fini_array"),
+		     aligned (sizeof (void *)))) =
+{
+  &fini_0,
+  &fini_1,
+  &fini_2
+};
+
+int
+main (void)
+{
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/fini.out b/binutils-2.19/ld/testsuite/ld-elf/fini.out
new file mode 100644
index 0000000..2bab6e6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/fini.out
@@ -0,0 +1,3 @@
+fini array 2
+fini array 1
+fini array 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/flags1.d b/binutils-2.19/ld/testsuite/ld-elf/flags1.d
new file mode 100644
index 0000000..2d079c0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/flags1.d
@@ -0,0 +1,21 @@
+#name: --set-section-flags test 1 (sections)
+#ld: -Tflags1.ld
+#objcopy_linked_file: --set-section-flags .post_text_reserve=contents,alloc,load,readonly,code 
+#readelf: -l --wide
+#xfail: "arm*-*-*" "xscale-*-*"
+#xfail: "avr-*-*" "dlx-*-*" "h8300-*-*" "m32r-*-*" "msp430-*-*"
+#xfail: "*-*-hpux*"
+# Fails on the ARM because the .section type character is % rather than @.
+# Fails on the AVR, DLX, H8300, M32R and MSP430 because the two sections
+#  are not merged into one segment.  (There is no good reason why they have to be).
+# Fails on HPUX systems because the .type pseudo-op behaves differently.
+
+#...
+Program Headers:
+  Type.*
+  LOAD +0x[0-9a-f]+ 0x0*0 0x0*0 0x0*01(6[1-9a-f]|70) 0x0*01(6[1-9a-f]|70) RWE 0x[0-9a-f]+
+
+#...
+  Segment Sections...
+   00[ \t]+.text .post_text_reserve[ \t]*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/flags1.ld b/binutils-2.19/ld/testsuite/ld-elf/flags1.ld
new file mode 100644
index 0000000..a94cbe8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/flags1.ld
@@ -0,0 +1,12 @@
+SECTIONS
+{
+  .text :
+  {
+    *(.text)
+  } =0
+  .post_text_reserve :
+  {
+    . += 0x160;
+  }
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/flags1.s b/binutils-2.19/ld/testsuite/ld-elf/flags1.s
new file mode 100644
index 0000000..0562131
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/flags1.s
@@ -0,0 +1,5 @@
+	.text
+.globl start
+	.type	start, @function
+start:
+	.byte 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/foo.c b/binutils-2.19/ld/testsuite/ld-elf/foo.c
new file mode 100644
index 0000000..c84baee
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/foo.c
@@ -0,0 +1,11 @@
+#include <stdio.h>
+
+void
+foo (void)
+{
+  printf ("TEST2\n");
+}
+
+static void (*const init_array []) (void)
+  __attribute__ ((used, section (".init_array"), aligned (sizeof (void *))))
+  = { foo };
diff --git a/binutils-2.19/ld/testsuite/ld-elf/foo.map b/binutils-2.19/ld/testsuite/ld-elf/foo.map
new file mode 100644
index 0000000..6b993de
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/foo.map
@@ -0,0 +1,4 @@
+FOO {
+  global: foo;
+  local: *;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elf/frame.exp b/binutils-2.19/ld/testsuite/ld-elf/frame.exp
new file mode 100644
index 0000000..9f5a787
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/frame.exp
@@ -0,0 +1,82 @@
+# Expect script for frame section tests
+#   Copyright 2004, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by H.J. Lu (hongjiu.lu@intel.com)
+#
+
+# Make sure that ld correctly handles frame sections in ELF.
+
+# This test can only be run on ELF platforms.
+if ![is_elf_format] {
+    return
+}
+
+# No shared lib support on this target.
+if { [istarget "mcore-*-*"] } {
+    return
+}
+
+# Too small MAXPAGESIZE on this target.
+if { [istarget "sh*-*-elf*"] } {
+    return
+}
+
+# ??? These targets have their own .tbss section, with different meaning
+# to the usual ELF .tbss.
+if { [istarget "hppa64-*-*"] || [istarget "v850-*-*"] } {
+    return
+}
+
+set test1	"read-only .eh_frame section"
+set test2	"read-only .gcc_except_table section"
+
+global as
+global ld
+
+if { ![ld_assemble $as $srcdir/$subdir/tbss.s tmpdir/tbss.o ]
+     || ![ld_assemble $as $srcdir/$subdir/frame.s tmpdir/frame.o] } {
+    unresolved "$test1"
+    return
+}
+
+if { [ld_simple_link $ld tmpdir/frame.so "--shared tmpdir/frame.o tmpdir/tbss.o"] } {
+    pass "$test1"
+} else {
+    if [string match "*shared not supported*" $link_output] {
+	unsupported "-shared is not supported by this target"
+    } else {
+	fail "$test1"
+    }
+}
+
+if ![ld_assemble $as $srcdir/$subdir/table.s tmpdir/table.o ] {
+    unresolved "$test2"
+    return
+}
+
+if { [ld_simple_link $ld tmpdir/table.so "--shared tmpdir/table.o tmpdir/tbss.o"] } {
+    pass "$test2"
+} else {
+    if [string match "*shared not supported*" $link_output] {
+	unsupported "-shared is not supported by this target"
+    } else {
+	fail "$test2"
+    }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/frame.s b/binutils-2.19/ld/testsuite/ld-elf/frame.s
new file mode 100644
index 0000000..c752263
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/frame.s
@@ -0,0 +1,2 @@
+	.section	.eh_frame,"a",%progbits
+	.4byte	0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/group.ld b/binutils-2.19/ld/testsuite/ld-elf/group.ld
new file mode 100644
index 0000000..58d78da
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/group.ld
@@ -0,0 +1,6 @@
+SECTIONS
+{
+  . = 0x1000;
+  .text : { *(.text) *(.rodata.brlt) }
+  /DISCARD/ : { *(.reginfo) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/group1.d b/binutils-2.19/ld/testsuite/ld-elf/group1.d
new file mode 100644
index 0000000..0d65932
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/group1.d
@@ -0,0 +1,10 @@
+#source: group1a.s
+#source: group1b.s
+#ld: -T group.ld
+#readelf: -s
+#xfail: "arc-*-*" "d30v-*-*" "dlx-*-*" "i960-*-*" "or32-*-*" "pj-*-*"
+Symbol table '.symtab' contains .* entries:
+#...
+    .*: 0[0]*1000     0 (NOTYPE|OBJECT)  WEAK   DEFAULT    . foo
+    .*: 0[0]*0000     0 (NOTYPE|OBJECT)  GLOBAL DEFAULT  UND bar
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-elf/group1a.s b/binutils-2.19/ld/testsuite/ld-elf/group1a.s
new file mode 100644
index 0000000..296e76e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/group1a.s
@@ -0,0 +1,4 @@
+	.section .text,"axG",%progbits,foo_group,comdat
+	.weak foo
+foo:
+	.word 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/group1b.s b/binutils-2.19/ld/testsuite/ld-elf/group1b.s
new file mode 100644
index 0000000..b66cba9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/group1b.s
@@ -0,0 +1,6 @@
+	.section .text,"axG",%progbits,foo_group,comdat
+	.global foo
+	.global bar
+foo:
+	.word 0
+bar:
diff --git a/binutils-2.19/ld/testsuite/ld-elf/group2.d b/binutils-2.19/ld/testsuite/ld-elf/group2.d
new file mode 100644
index 0000000..b4d0b81
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/group2.d
@@ -0,0 +1,16 @@
+#source: ../../../binutils/testsuite/binutils-all/group.s
+#ld: -r
+#readelf: -Sg --wide
+
+#...
+  \[[ 0-9]+\] foo_group[ \t]+GROUP[ \t]+.*
+#...
+  \[[ 0-9]+\] \.text.*[ \t]+PROGBITS[ \t0-9a-f]+AXG.*
+#...
+  \[[ 0-9]+\] \.data.*[ \t]+PROGBITS[ \t0-9a-f]+WAG.*
+#...
+COMDAT group section \[[ 0-9]+\] `foo_group' \[foo_group\] contains 2 sections:
+   \[Index\]    Name
+   \[[ 0-9]+\]   .text.*
+   \[[ 0-9]+\]   .data.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/group3a.d b/binutils-2.19/ld/testsuite/ld-elf/group3a.d
new file mode 100644
index 0000000..83c5161
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/group3a.d
@@ -0,0 +1,8 @@
+#source: group3a.s
+#source: group3b.s
+#ld: -T group.ld
+#readelf: -s
+Symbol table '.symtab' contains .* entries:
+#...
+    .*: 0[0]*1000     0 OBJECT  GLOBAL HIDDEN    . foo
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-elf/group3a.s b/binutils-2.19/ld/testsuite/ld-elf/group3a.s
new file mode 100644
index 0000000..5e6a686
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/group3a.s
@@ -0,0 +1,5 @@
+	.section .data,"awG",%progbits,foo_group,comdat
+	.globl foo
+	.type foo,%object
+foo:
+	.word 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/group3b.d b/binutils-2.19/ld/testsuite/ld-elf/group3b.d
new file mode 100644
index 0000000..82c18e4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/group3b.d
@@ -0,0 +1,8 @@
+#source: group3b.s
+#source: group3a.s
+#ld: -T group.ld
+#readelf: -s
+Symbol table '.symtab' contains .* entries:
+#...
+    .*: 0[0]*1000     0 OBJECT  GLOBAL HIDDEN    . foo
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-elf/group3b.s b/binutils-2.19/ld/testsuite/ld-elf/group3b.s
new file mode 100644
index 0000000..6c101bc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/group3b.s
@@ -0,0 +1,6 @@
+	.section .data,"awG",%progbits,foo_group,comdat
+	.hidden foo
+	.globl foo
+	.type foo,%object
+foo:
+	.word 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/hash.d b/binutils-2.19/ld/testsuite/ld-elf/hash.d
new file mode 100644
index 0000000..b3769aa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/hash.d
@@ -0,0 +1,17 @@
+#source: start.s
+#readelf: -d -s -D
+#ld: -shared --hash-style=gnu
+#target: *-*-linux*
+#notarget: mips*-*-*
+
+#...
+[ 	]*0x[0-9a-z]+[ 	]+\(GNU_HASH\)[ 	]+0x[0-9a-z]+
+#...
+[ 	]+[0-9]+[ 	]+[0-9]+:[ 	]+[0-9a-f]+[ 	]+[0-9]+[ 	]+NOTYPE[	 ]+GLOBAL DEFAULT[ 	]+[1-9] _start
+#...
+[ 	]+[0-9]+[ 	]+[0-9]+:[ 	]+[0-9a-f]+[ 	]+[0-9]+[ 	]+NOTYPE[	 ]+GLOBAL DEFAULT[ 	]+[1-9] main
+#...
+[ 	]+[0-9]+[ 	]+[0-9]+:[ 	]+[0-9a-f]+[ 	]+[0-9]+[ 	]+NOTYPE[	 ]+GLOBAL DEFAULT[ 	]+[1-9] start
+#...
+[ 	]+[0-9]+[ 	]+[0-9]+:[ 	]+[0-9a-f]+[ 	]+[0-9]+[ 	]+NOTYPE[	 ]+GLOBAL DEFAULT[ 	]+[1-9] __start
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-elf/header.d b/binutils-2.19/ld/testsuite/ld-elf/header.d
new file mode 100644
index 0000000..d438832
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/header.d
@@ -0,0 +1,5 @@
+# target: *-*-linux*  *-*-vxworks
+# ld: -T header.t -z max-page-size=0x100
+# objdump: -hpw
+
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-elf/header.s b/binutils-2.19/ld/testsuite/ld-elf/header.s
new file mode 100644
index 0000000..38f2228
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/header.s
@@ -0,0 +1,8 @@
+	.text
+	.globl main
+main:
+	.rept 0x40 - 0x15
+	.long 0xfedcba98
+	.endr
+	.data
+	.long 0x76543210
diff --git a/binutils-2.19/ld/testsuite/ld-elf/header.t b/binutils-2.19/ld/testsuite/ld-elf/header.t
new file mode 100644
index 0000000..c378fbe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/header.t
@@ -0,0 +1,8 @@
+ENTRY(main)
+
+SECTIONS
+{
+  . = 0x100 + SIZEOF_HEADERS;
+  .text : { *(.text) }
+  .data : { *(.data) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/hidden.out b/binutils-2.19/ld/testsuite/ld-elf/hidden.out
new file mode 100644
index 0000000..7ad7cbe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/hidden.out
@@ -0,0 +1,3 @@
+TEST2
+TEST1
+MAIN
diff --git a/binutils-2.19/ld/testsuite/ld-elf/init.c b/binutils-2.19/ld/testsuite/ld-elf/init.c
new file mode 100644
index 0000000..3b1ffb1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/init.c
@@ -0,0 +1,34 @@
+#include <stdio.h>
+
+static void
+init_0 (void)
+{
+  printf ("init array 0\n");
+}
+
+static void
+init_1 (void)
+{
+  printf ("init array 1\n");
+}
+
+static void
+init_2 (void)
+{
+  printf ("init array 2\n");
+}
+
+void (*const init_array []) (void)
+     __attribute__ ((section (".init_array"),
+		     aligned (sizeof (void *)))) =
+{
+  &init_0,
+  &init_1,
+  &init_2
+};
+
+int
+main (void)
+{
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/init.out b/binutils-2.19/ld/testsuite/ld-elf/init.out
new file mode 100644
index 0000000..f988b84
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/init.out
@@ -0,0 +1,3 @@
+init array 0
+init array 1
+init array 2
diff --git a/binutils-2.19/ld/testsuite/ld-elf/linkonce1.d b/binutils-2.19/ld/testsuite/ld-elf/linkonce1.d
new file mode 100644
index 0000000..35e1787
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/linkonce1.d
@@ -0,0 +1,12 @@
+#source: linkonce1a.s
+#source: linkonce1b.s
+#ld: -r
+#objdump: -r
+
+.*:     file format .*
+
+RELOCATION RECORDS FOR \[.debug_frame\]:
+OFFSET[ 	]+TYPE[ 	]+VALUE[ 	]*
+.*(NONE|unused).*\*ABS\*
+
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/linkonce1a.s b/binutils-2.19/ld/testsuite/ld-elf/linkonce1a.s
new file mode 100644
index 0000000..5c2d8c2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/linkonce1a.s
@@ -0,0 +1,3 @@
+        .section .gnu.linkonce.d.dummy,"aw"
+bar:
+        .long    0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/linkonce1b.s b/binutils-2.19/ld/testsuite/ld-elf/linkonce1b.s
new file mode 100644
index 0000000..fd45cec
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/linkonce1b.s
@@ -0,0 +1,17 @@
+	.globl main
+	.globl start
+	.globl _start
+	.globl __start
+	.text
+main:
+start:
+_start:
+__start:
+	.long	0
+
+        .section .gnu.linkonce.d.dummy,"aw"
+        .long    0
+foo:
+        .long    0
+ 	.section        .debug_frame,"",%progbits
+        .long    foo
diff --git a/binutils-2.19/ld/testsuite/ld-elf/linkonce2.d b/binutils-2.19/ld/testsuite/ld-elf/linkonce2.d
new file mode 100644
index 0000000..33eb14f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/linkonce2.d
@@ -0,0 +1,12 @@
+#source: linkonce1a.s
+#source: linkonce1b.s
+#ld: -emit-relocs
+#objdump: -r
+
+.*:     file format .*
+
+RELOCATION RECORDS FOR \[.debug_frame\]:
+OFFSET[ 	]+TYPE[ 	]+VALUE[ 	]*
+.*(NONE|unused).*\*ABS\*
+
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/lma.lnk b/binutils-2.19/ld/testsuite/ld-elf/lma.lnk
new file mode 100644
index 0000000..7aac6d0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/lma.lnk
@@ -0,0 +1,6 @@
+SECTIONS
+{
+  . = -0x100000;
+  .text : AT(ADDR(.text) + 0x100000) { *(.text) }
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/lma.s b/binutils-2.19/ld/testsuite/ld-elf/lma.s
new file mode 100644
index 0000000..039d26b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/lma.s
@@ -0,0 +1,4 @@
+ .text
+ .global _start
+_start:
+ .long 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/loadaddr.s b/binutils-2.19/ld/testsuite/ld-elf/loadaddr.s
new file mode 100644
index 0000000..0a14169
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/loadaddr.s
@@ -0,0 +1,20 @@
+	.text
+	.globl main
+	.globl start
+	.globl _start
+	.globl __start
+main:
+start:
+_start:
+__start:
+	.byte 0,0,0,0,0,0,0,0
+	.byte 0,0,0,0,0,0,0,0
+	.section .bar,"ax","progbits"
+	.byte 0,0,0,0,0,0,0,0
+	.byte 0,0,0,0,0,0,0,0
+	.section .foo,"aw","progbits"
+	.byte 0,0,0,0,0,0,0,0
+	.byte 0,0,0,0,0,0,0,0
+	.data
+	.byte 0,0,0,0,0,0,0,0
+	.byte 0,0,0,0,0,0,0,0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/loadaddr.t b/binutils-2.19/ld/testsuite/ld-elf/loadaddr.t
new file mode 100644
index 0000000..91e9ef2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/loadaddr.t
@@ -0,0 +1,10 @@
+SECTIONS
+{
+  . = -0x7ff00000;
+  .text : {*(.text .text.*)}
+  . = ALIGN(64);
+  .foo : { *(.foo) }
+  . = ALIGN(8192);
+  .data : AT (ADDR(.data)) { *(.data) }
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/loadaddr1.d b/binutils-2.19/ld/testsuite/ld-elf/loadaddr1.d
new file mode 100644
index 0000000..2d3469b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/loadaddr1.d
@@ -0,0 +1,10 @@
+#source: loadaddr.s
+#ld: -T loadaddr1.t -T loadaddr.t -z max-page-size=0x200000
+#readelf: -l --wide
+#target: *-*-linux*
+
+#...
+  LOAD +0x000000 0xf*80000000 0xf*80000000 0x100050 0x100050 RWE 0x200000
+  LOAD +0x200000 0xf*ff600000 0xf*80101000 0x0*10 0x0*10 R E 0x200000
+  LOAD +0x302000 0xf*80102000 0xf*80102000 0x0*10 0x0*10 RW  0x200000
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/loadaddr1.t b/binutils-2.19/ld/testsuite/ld-elf/loadaddr1.t
new file mode 100644
index 0000000..5037b4f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/loadaddr1.t
@@ -0,0 +1,7 @@
+SECTIONS
+{
+  .bar -0xa00000 : AT ((LOADADDR(.foo) + SIZEOF(.foo) + 4095) & ~(4095))
+    { *(.bar) }
+  . = LOADADDR(.bar) + 4096;
+}
+INSERT AFTER .foo;
diff --git a/binutils-2.19/ld/testsuite/ld-elf/loadaddr2.d b/binutils-2.19/ld/testsuite/ld-elf/loadaddr2.d
new file mode 100644
index 0000000..e447e38
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/loadaddr2.d
@@ -0,0 +1,10 @@
+#source: loadaddr.s
+#ld: -T loadaddr2.t -T loadaddr.t -z max-page-size=0x200000
+#readelf: -l --wide
+#target: *-*-linux*
+
+#...
+  LOAD +0x000000 0xf*80000000 0xf*80000000 0x100050 0x100050 RWE 0x200000
+  LOAD +0x110000 0xf*80110000 0xf*80101000 0x0*10 0x0*10 R E 0x200000
+  LOAD +0x302000 0xf*80302000 0xf*80302000 0x0*10 0x0*10 RW  0x200000
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/loadaddr2.t b/binutils-2.19/ld/testsuite/ld-elf/loadaddr2.t
new file mode 100644
index 0000000..0ad16df
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/loadaddr2.t
@@ -0,0 +1,7 @@
+SECTIONS
+{
+  .bar -0x7fef0000 : AT ((LOADADDR(.foo) + SIZEOF(.foo) + 4095) & ~(4095))
+    { *(.bar) }
+  . = LOADADDR(.bar) + 0x200000;
+}
+INSERT BEFORE .data;
diff --git a/binutils-2.19/ld/testsuite/ld-elf/loadaddr3.t b/binutils-2.19/ld/testsuite/ld-elf/loadaddr3.t
new file mode 100644
index 0000000..789f61e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/loadaddr3.t
@@ -0,0 +1,16 @@
+
+MEMORY
+{
+  rom (rx) : ORIGIN = 0x100, LENGTH = 0x100
+  ram (rwx) : ORIGIN = 0x200, LENGTH = 0x100
+
+}
+
+SECTIONS
+{
+  .text : {*(.text .text.*)} >rom
+  .data : {data_load = LOADADDR (.data);
+	   data_start = ADDR (.data);
+	   *(.data .data.*)} >ram AT>rom
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/loadaddr3a.d b/binutils-2.19/ld/testsuite/ld-elf/loadaddr3a.d
new file mode 100644
index 0000000..b2ace66
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/loadaddr3a.d
@@ -0,0 +1,9 @@
+#source: loadaddr.s
+#ld: -T loadaddr3.t -z max-page-size=0x200000
+#readelf: -l --wide
+#target: *-*-linux*
+
+#...
+  LOAD +0x000000 0x0*00000000 0x0*00000000 0x0*0110 0x0*0110 R E 0x.*
+  LOAD +0x000200 0x0*00000200 0x0*00000110 0x0*0010 0x0*0010 RW  0x.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/loadaddr3b.d b/binutils-2.19/ld/testsuite/ld-elf/loadaddr3b.d
new file mode 100644
index 0000000..af7e6e4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/loadaddr3b.d
@@ -0,0 +1,13 @@
+#source: loadaddr.s
+#ld: -T loadaddr3.t -z max-page-size=0x200000
+#objdump: -t
+#target: *-*-linux*
+
+#...
+0+0000100 l    d  .text	0+0000000 .text
+0+0000200 l    d  .data	0+0000000 .data
+#...
+0+0000110 g       \*ABS\*	0+0000000 data_load
+#...
+0+0000200 g       .data	0+0000000 data_start
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/main.c b/binutils-2.19/ld/testsuite/ld-elf/main.c
new file mode 100644
index 0000000..24f9dcc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/main.c
@@ -0,0 +1,8 @@
+#include <stdio.h>
+
+int
+main (void)
+{
+  printf ("MAIN\n");
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/maxpage1.d b/binutils-2.19/ld/testsuite/ld-elf/maxpage1.d
new file mode 100644
index 0000000..57acda0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/maxpage1.d
@@ -0,0 +1,9 @@
+#source: maxpage1.s
+#ld: -z max-page-size=0x200000
+#readelf: -l --wide
+#target: *-*-linux*
+
+#...
+  LOAD+.*0x200000
+  LOAD+.*0x200000
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/maxpage1.s b/binutils-2.19/ld/testsuite/ld-elf/maxpage1.s
new file mode 100644
index 0000000..1a7735a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/maxpage1.s
@@ -0,0 +1,13 @@
+	.globl main
+	.globl start
+	.globl _start
+	.globl __start
+	.text
+main:
+start:
+_start:
+__start:
+	.long	0
+
+	.data
+	.long	0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/maxpage2.d b/binutils-2.19/ld/testsuite/ld-elf/maxpage2.d
new file mode 100644
index 0000000..7fe9379
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/maxpage2.d
@@ -0,0 +1,9 @@
+#source: maxpage1.s
+#ld: -z max-page-size=0x100000
+#readelf: -l --wide
+#target: *-*-linux*
+
+#...
+  LOAD+.*0x100000
+  LOAD+.*0x100000
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/maxpage3.t b/binutils-2.19/ld/testsuite/ld-elf/maxpage3.t
new file mode 100644
index 0000000..556dcd5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/maxpage3.t
@@ -0,0 +1,7 @@
+SECTIONS
+{
+  .text : {*(.text)}
+  . = ALIGN(CONSTANT (MAXPAGESIZE));
+  .data : {*(.data)}
+  /DISCARD/ : {*(*)}
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/maxpage3a.d b/binutils-2.19/ld/testsuite/ld-elf/maxpage3a.d
new file mode 100644
index 0000000..0e46b6b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/maxpage3a.d
@@ -0,0 +1,11 @@
+#source: maxpage1.s
+#ld: -z max-page-size=0x10000000 -T maxpage3.t
+#readelf: -lS --wide
+#target: *-*-linux*
+
+#...
+  \[[ 0-9]+\] \.data[ \t]+PROGBITS[ \t]+0*10000000[ \t]+[ \t0-9a-f]+WA?.*
+#...
+  LOAD+.*0x10000000
+  LOAD+.*0x10000000
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/maxpage3b.d b/binutils-2.19/ld/testsuite/ld-elf/maxpage3b.d
new file mode 100644
index 0000000..4bee0ec
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/maxpage3b.d
@@ -0,0 +1,10 @@
+#source: maxpage1.s
+#ld: -T maxpage3.t -z max-page-size=0x10000000
+#readelf: -lS --wide
+#target: x86_64-*-linux*
+
+#...
+  \[[ 0-9]+\] \.data[ \t]+PROGBITS[ \t]+0*200000[ \t]+[ \t0-9a-f]+WA?.*
+#...
+  LOAD+.*0x10000000
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/maxpage3c.d b/binutils-2.19/ld/testsuite/ld-elf/maxpage3c.d
new file mode 100644
index 0000000..cdc3eaf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/maxpage3c.d
@@ -0,0 +1,12 @@
+#source: maxpage1.s
+#as: --32
+#ld: -m elf_i386 -z max-page-size=0x10000000 -T maxpage3.t
+#readelf: -lS --wide
+#target: x86_64-*-linux*
+
+#...
+  \[[ 0-9]+\] \.data[ \t]+PROGBITS[ \t]+0*10000000[ \t]+[ \t0-9a-f]+WA?.*
+#...
+  LOAD+.*0x10000000
+  LOAD+.*0x10000000
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/merge.d b/binutils-2.19/ld/testsuite/ld-elf/merge.d
new file mode 100644
index 0000000..4a7eefc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/merge.d
@@ -0,0 +1,16 @@
+#source: merge.s
+#ld: -T merge.ld
+#objdump: -s
+#xfail: "arc-*-*" "avr-*-*" "bfin-*-*" "cris*-*-*" "crx-*-*" "d10v-*-*" "d30v-*-*"
+#xfail: "dlx-*-*" "fr30-*-*" "frv-*-*" "hppa*-*-*" "h8300-*-*" "score-*-*"
+#xfail: "i370-*-*" "i860-*-*" "i960-*-*" "ip2k-*-*" "iq2000-*-*"
+#xfail: "mcore-*-*" "mn102*-*-*" "mips*-*-*" "ms1-*-*" "msp430-*-*"
+#xfail: "or32-*-*" "pj-*-*" "sparc*-*-*" "vax-*-*" "xstormy16-*-*" "xtensa*-*-*"
+
+.*:     file format .*elf.*
+
+Contents of section .text:
+ 1000 (1010)?0000(1010)? (1210)?0000(1012)? (0c)?000000(0c)? (0e)?000000(0e)? .*
+Contents of section .rodata:
+ 1010 61626300 .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/merge.ld b/binutils-2.19/ld/testsuite/ld-elf/merge.ld
new file mode 100644
index 0000000..dce91bb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/merge.ld
@@ -0,0 +1,7 @@
+SECTIONS
+{
+  . = 0x1000;
+  .text : { *(.text .text.* .gnu.linkonce.t.*) }
+  .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
+  .junk : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/merge.s b/binutils-2.19/ld/testsuite/ld-elf/merge.s
new file mode 100644
index 0000000..1e6e0e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/merge.s
@@ -0,0 +1,14 @@
+	.section .rodata.str,"aMS","progbits",1
+.LC0:
+	.asciz	"abc"
+.LC1:
+	.asciz	"c"
+
+	.text
+	.global _start
+_start:
+	.long	.LC0
+.LT0:
+	.long	.LC1
+	.long	.LC0-.LT0
+	.long	.LC1-.LT0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/merge2.d b/binutils-2.19/ld/testsuite/ld-elf/merge2.d
new file mode 100644
index 0000000..40884a3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/merge2.d
@@ -0,0 +1,17 @@
+#source: merge2.s
+#ld: -T merge.ld
+#objdump: -s
+#xfail: "arc-*-*" "d30v-*-*" "dlx-*-*" "hppa64-*-*"
+#xfail: "i960-*-*" "ip2k-*-*" "iq2000-*-*" "or32-*-*" "pj-*-*"
+
+.*:     file format .*elf.*
+
+Contents of section .text:
+ 1000 (3010)?0000(1030)? (3210)?0000(1032)? (3110)?0000(1031)? (3410)?0000(1034)?  .*
+ 1010 (4010)?0000(1040)? (3810)?0000(1038)? (4810)?0000(1048)? (3c10)?0000(103c)?  .*
+ 1020 (5010)?0000(1050)? (5410)?0000(1054)? (5810)?0000(1058)? (5010)?0000(1050)?  .*
+Contents of section .rodata:
+ 1030 61626300 62000000 (78563412|12345678) 99999999  .*
+ 1040 (78563412|12345678) 00000000 99999999 00000000  .*
+ 1050 (78563412|12345678) 99999999 00000000           .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/merge2.s b/binutils-2.19/ld/testsuite/ld-elf/merge2.s
new file mode 100644
index 0000000..41d066a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/merge2.s
@@ -0,0 +1,58 @@
+	.section .rodata.str,"aMS","progbits",1
+.LC0:
+	.asciz	"abc"
+.LC1:
+	.asciz	"c"
+.LC2:
+	.asciz	"bc"
+.LC3:
+	.asciz	"b"
+
+
+	.section .rodata.str2,"aMS","progbits",4
+	.p2align 2
+.LC4:
+	.long	0x12345678
+	.long	0
+.LC5:
+	.long	0x12345678
+	.long	0x99999999
+	.long	0x12345678
+	.long	0
+.LC6:
+	.long	0x99999999
+	.long	0
+.LC7:
+	.long	0x99999999
+	.long	0x12345678
+	.long	0
+
+
+	.section .rodata.m,"aM","progbits",4
+	.p2align 2
+.LC8:
+	.long	0x12345678
+.LC9:
+	.long	0x99999999
+.LC10:
+	.long	0
+.LC11:
+	.long	0x12345678
+
+
+	.text
+	.global _start
+_start:
+	.long	.LC0
+.LT0:
+	.long	.LC1
+	.long	.LC2
+	.long	.LC3
+	.long	.LC4
+	.long	.LC5
+	.long	.LC6
+	.long	.LC7
+	.long	.LC8
+	.long	.LC9
+	.long	.LC10
+	.long	.LC11
diff --git a/binutils-2.19/ld/testsuite/ld-elf/multibss1.d b/binutils-2.19/ld/testsuite/ld-elf/multibss1.d
new file mode 100644
index 0000000..8074fe3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/multibss1.d
@@ -0,0 +1,9 @@
+#source: multibss1.s
+#ld: -e 0
+#readelf: -l --wide
+#target: *-*-linux*
+
+#...
+ +LOAD +0x[^ ]+ +0x[^ ]+ +0x[^ ]+ +0x[^ ]+ +0x500000 .*
+#       p_offset p_vaddr  p_paddr  p_filesz
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/multibss1.s b/binutils-2.19/ld/testsuite/ld-elf/multibss1.s
new file mode 100644
index 0000000..94b84f9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/multibss1.s
@@ -0,0 +1,11 @@
+	.macro	makebss
+	.section .bss_\@,"aw",%nobits
+	.space	0x10000
+	.endm
+
+	.rept	80
+	makebss
+	.endr
+
+	.text
+	.space	0x10
diff --git a/binutils-2.19/ld/testsuite/ld-elf/new.cc b/binutils-2.19/ld/testsuite/ld-elf/new.cc
new file mode 100644
index 0000000..b4c8882
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/new.cc
@@ -0,0 +1,48 @@
+#include <new>
+#include <exception_defines.h>
+
+using std::bad_alloc;
+
+extern "C" void *malloc (std::size_t);
+extern "C" void abort (void);
+
+void *
+operator new (std::size_t sz, const std::nothrow_t&) throw()
+{
+  void *p;
+
+  /* malloc (0) is unpredictable; avoid it.  */
+  if (sz == 0)
+    sz = 1;
+  p = (void *) malloc (sz);
+  return p;
+}
+
+void *
+operator new (std::size_t sz) throw (std::bad_alloc)
+{
+  void *p;
+
+  /* malloc (0) is unpredictable; avoid it.  */
+  if (sz == 0)
+    sz = 1;
+  p = (void *) malloc (sz);
+  while (p == 0)
+    {
+      ::abort();
+    }
+
+  return p;
+}
+
+void*
+operator new[] (std::size_t sz) throw (std::bad_alloc)
+{
+  return ::operator new(sz);
+}
+
+void *
+operator new[] (std::size_t sz, const std::nothrow_t& nothrow) throw()
+{
+  return ::operator new(sz, nothrow);
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/nobits-1.d b/binutils-2.19/ld/testsuite/ld-elf/nobits-1.d
new file mode 100644
index 0000000..9b90b6f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/nobits-1.d
@@ -0,0 +1,7 @@
+#ld: -Tnobits-1.t
+#readelf: -l --wide
+
+#...
+ Section to Segment mapping:
+  Segment Sections...
+   00     .foo .bar 
diff --git a/binutils-2.19/ld/testsuite/ld-elf/nobits-1.s b/binutils-2.19/ld/testsuite/ld-elf/nobits-1.s
new file mode 100644
index 0000000..8fb1365
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/nobits-1.s
@@ -0,0 +1,6 @@
+	.globl _entry
+	.section .foo,"awx",%progbits
+_entry:
+	.byte 0
+	.section .bar,"ax",%nobits
+	.byte 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/nobits-1.t b/binutils-2.19/ld/testsuite/ld-elf/nobits-1.t
new file mode 100644
index 0000000..2004330
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/nobits-1.t
@@ -0,0 +1,13 @@
+ENTRY(_entry)
+PHDRS
+{
+  data PT_LOAD;
+}
+SECTIONS
+{
+  . = 0x1000000;
+  .foo : { *(.foo) } :data
+  . = 0x2000000;
+  .bar : { *(.bar) } :data
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/noload-1.d b/binutils-2.19/ld/testsuite/ld-elf/noload-1.d
new file mode 100644
index 0000000..7cae479
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/noload-1.d
@@ -0,0 +1,7 @@
+#source: noload-1.s
+#ld: -T noload-1.t
+#readelf: -S --wide
+
+#...
+  \[[ 0-9]+\] TEST[ \t]+NOBITS[ \t0-9a-f]+WA.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/noload-1.s b/binutils-2.19/ld/testsuite/ld-elf/noload-1.s
new file mode 100644
index 0000000..ad0479e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/noload-1.s
@@ -0,0 +1,2 @@
+	.section TEST,"aw",%progbits
+	.byte 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/noload-1.t b/binutils-2.19/ld/testsuite/ld-elf/noload-1.t
new file mode 100644
index 0000000..1efd06c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/noload-1.t
@@ -0,0 +1,8 @@
+SECTIONS
+{
+  TEST (NOLOAD) :
+  {
+    *(TEST)
+  }
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/noload-2.d b/binutils-2.19/ld/testsuite/ld-elf/noload-2.d
new file mode 100644
index 0000000..633bf45
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/noload-2.d
@@ -0,0 +1,8 @@
+#source: noload-1.s
+#ld: -T noload-1.t -z max-page-size=0x200000
+#readelf: -Sl --wide
+#target: *-*-linux*
+
+#...
+ +LOAD +0x200000 +0x0+ +0x0+ +0x0+ +0x0+1 +RW +0x200000
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/noload-3.d b/binutils-2.19/ld/testsuite/ld-elf/noload-3.d
new file mode 100644
index 0000000..84b27d7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/noload-3.d
@@ -0,0 +1,7 @@
+#ld: -T noload-3.t
+#objdump: -s -j .foo1
+
+#...
+Contents of section .foo1:
+ [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ [0-9a-f]+[ \t]+This is a test.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/noload-3.s b/binutils-2.19/ld/testsuite/ld-elf/noload-3.s
new file mode 100644
index 0000000..84aa2e2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/noload-3.s
@@ -0,0 +1,6 @@
+	.section .foo2,"aw",%progbits
+	.byte 1
+	.section .foo1,"w",%progbits
+	.string "This is a test."
+	.section .foo,"aw",%progbits
+	.space 16
diff --git a/binutils-2.19/ld/testsuite/ld-elf/noload-3.t b/binutils-2.19/ld/testsuite/ld-elf/noload-3.t
new file mode 100644
index 0000000..fbb5166
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/noload-3.t
@@ -0,0 +1,7 @@
+SECTIONS
+{
+  .foo2 : { *(.foo2) }
+  .foo1 : { *(.foo1) }
+  .foo (NOLOAD) : { *(.foo) }
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/normal.out b/binutils-2.19/ld/testsuite/ld-elf/normal.out
new file mode 100644
index 0000000..3b721f0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/normal.out
@@ -0,0 +1,3 @@
+TEST1
+TEST1
+MAIN
diff --git a/binutils-2.19/ld/testsuite/ld-elf/note-1.d b/binutils-2.19/ld/testsuite/ld-elf/note-1.d
new file mode 100644
index 0000000..a5fc40f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/note-1.d
@@ -0,0 +1,8 @@
+#ld: -Tnote-1.t
+#readelf: -l --wide
+
+#...
+ Section to Segment mapping:
+  Segment Sections...
+   00     .foo 
+   01     .note 
diff --git a/binutils-2.19/ld/testsuite/ld-elf/note-1.s b/binutils-2.19/ld/testsuite/ld-elf/note-1.s
new file mode 100644
index 0000000..844188b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/note-1.s
@@ -0,0 +1,6 @@
+	.globl _entry
+	.section .foo,"awx",%progbits
+_entry:
+	.byte 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+	.section .note,"",%note
+	.byte 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/note-1.t b/binutils-2.19/ld/testsuite/ld-elf/note-1.t
new file mode 100644
index 0000000..031fe82
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/note-1.t
@@ -0,0 +1,14 @@
+ENTRY(_entry)
+PHDRS
+{
+  data PT_LOAD;
+  note PT_NOTE;
+}
+SECTIONS
+{
+  . = 0x1000000;
+  .foo : { *(.foo) } :data
+  . = 0x2000000;
+  .note : { *(.note) } :note
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/note-2.d b/binutils-2.19/ld/testsuite/ld-elf/note-2.d
new file mode 100644
index 0000000..aff3240
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/note-2.d
@@ -0,0 +1,15 @@
+#ld: -Tnote-2.t
+#objcopy_linked_file: -R .foo 
+#readelf: -l --wide
+
+#...
+Program Headers:
+  Type.*
+  LOAD +0x[0-9a-f]+ .*
+  NOTE +0x[0-9a-f]+ .*
+
+#...
+  Segment Sections...
+   00[ \t]+.text *
+   01[ \t]+.note *
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/note-2.s b/binutils-2.19/ld/testsuite/ld-elf/note-2.s
new file mode 100644
index 0000000..93d6b36
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/note-2.s
@@ -0,0 +1,8 @@
+	.globl _entry
+	.text
+_entry:
+	.byte 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+	.section .foo,"awx",%progbits
+	.byte 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+	.section .note,"",%note
+	.byte 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/note-2.t b/binutils-2.19/ld/testsuite/ld-elf/note-2.t
new file mode 100644
index 0000000..a507da9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/note-2.t
@@ -0,0 +1,13 @@
+ENTRY(_entry)
+PHDRS
+{
+  data PT_LOAD;
+  note PT_NOTE;
+}
+SECTIONS
+{
+  .text : { *(.text) } :data
+  .foo : { *(.foo) } :data
+  .note : { *(.note) } :note
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/orphan.d b/binutils-2.19/ld/testsuite/ld-elf/orphan.d
new file mode 100644
index 0000000..54d10df
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/orphan.d
@@ -0,0 +1,13 @@
+#source: orphan.s
+#ld: -T orphan.ld
+#readelf: -S --wide
+
+#...
+  \[[ 0-9]+\] \.(text|notbad)[ \t]+PROGBITS[ \t0-9a-f]+AX?.*
+#...
+  \[[ 0-9]+\] \.(text|notbad)[ \t]+PROGBITS[ \t0-9a-f]+AX?.*
+  \[[ 0-9]+\] \.data[ \t]+PROGBITS[ \t0-9a-f]+WA.*
+#...
+  \[[ 0-9]+\] \.note[ \t]+NOTE[ \t0-9a-f]+A.*
+  \[[ 0-9]+\] \.note.bar[ \t]+NOTE[ \t0-9a-f]+A.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/orphan.ld b/binutils-2.19/ld/testsuite/ld-elf/orphan.ld
new file mode 100644
index 0000000..8ce83f1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/orphan.ld
@@ -0,0 +1,8 @@
+SECTIONS
+{
+  .text : { *(.text) }
+  .data : { *(.data) }
+  .bss : { *(.bss) *(COMMON) }
+  .note : { *(.note) }
+  .reginfo : { *(.reginfo) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/orphan.s b/binutils-2.19/ld/testsuite/ld-elf/orphan.s
new file mode 100644
index 0000000..d46f21d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/orphan.s
@@ -0,0 +1,10 @@
+	.text
+	.long 0
+	.data
+	.long 0
+	.section .note,"a","note"
+	.long 0
+	.section .notbad,"a","progbits"
+	.long 0
+	.section .note.bar,"a","note"
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/orphan2.d b/binutils-2.19/ld/testsuite/ld-elf/orphan2.d
new file mode 100644
index 0000000..a82e721
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/orphan2.d
@@ -0,0 +1,9 @@
+#source: orphan2.s
+#ld: -r
+#readelf: -S --wide
+
+#...
+  \[[ 0-9]+\] \.text[ \t]+PROGBITS[ \t0-9a-f]+AX?.*
+#...
+  \[[ 0-9]+\] \.modinfo[ \t]+PROGBITS[ \t0-9a-f]+A.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/orphan2.s b/binutils-2.19/ld/testsuite/ld-elf/orphan2.s
new file mode 100644
index 0000000..bed8dcd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/orphan2.s
@@ -0,0 +1,4 @@
+	.text
+	.long 0
+	.section .modinfo,"a","progbits"
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/overlay.d b/binutils-2.19/ld/testsuite/ld-elf/overlay.d
new file mode 100644
index 0000000..00d25d5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/overlay.d
@@ -0,0 +1,12 @@
+# ld: -T overlay.t -u __load_start_text1 -u __load_start_text2 -u __load_stop_text1 -u __load_stop_text2
+#readelf: -s
+
+#...
+[ 	]+[0-9]+:[ 	]+0*4000[ 	]+0[ 	]+NOTYPE[ 	]+GLOBAL[ 	]+DEFAULT[ 	]+ABS __load_start_text1
+#...
+[ 	]+[0-9]+:[ 	]+0*4010[ 	]+0[ 	]+NOTYPE[ 	]+GLOBAL[ 	]+DEFAULT[ 	]+ABS __load_start_text2
+#...
+[ 	]+[0-9]+:[ 	]+0*4030[ 	]+0[ 	]+NOTYPE[ 	]+GLOBAL[ 	]+DEFAULT[ 	]+ABS __load_stop_text2
+#...
+[ 	]+[0-9]+:[ 	]+0*4010[ 	]+0[ 	]+NOTYPE[ 	]+GLOBAL[ 	]+DEFAULT[ 	]+ABS __load_stop_text1
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/overlay.s b/binutils-2.19/ld/testsuite/ld-elf/overlay.s
new file mode 100644
index 0000000..f153044
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/overlay.s
@@ -0,0 +1,6 @@
+	.section .text1,"ax",%progbits
+	.space 0x10
+	.section .text2,"ax",%progbits
+	.space 0x20
+	.text
+	.space 0x30
diff --git a/binutils-2.19/ld/testsuite/ld-elf/overlay.t b/binutils-2.19/ld/testsuite/ld-elf/overlay.t
new file mode 100644
index 0000000..bdb33c8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/overlay.t
@@ -0,0 +1,10 @@
+SECTIONS
+{
+  .text : { *(.text) }
+  OVERLAY 0x1000 : AT (0x4000)
+  {
+    .text1 {*(.text1)}
+    .text2 {*(.text2)}
+  }
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/pass.out b/binutils-2.19/ld/testsuite/ld-elf/pass.out
new file mode 100644
index 0000000..7ef22e9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/pass.out
@@ -0,0 +1 @@
+PASS
diff --git a/binutils-2.19/ld/testsuite/ld-elf/preinit.c b/binutils-2.19/ld/testsuite/ld-elf/preinit.c
new file mode 100644
index 0000000..9ef2a89
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/preinit.c
@@ -0,0 +1,34 @@
+#include <stdio.h>
+
+static void
+preinit_0 (void)
+{
+  printf ("preinit array 0\n");
+}
+
+static void
+preinit_1 (void)
+{
+  printf ("preinit array 1\n");
+}
+
+static void
+preinit_2 (void)
+{
+  printf ("preinit array 2\n");
+}
+
+void (*const preinit_array []) (void)
+     __attribute__ ((section (".preinit_array"),
+		     aligned (sizeof (void *)))) =
+{
+  &preinit_0,
+  &preinit_1,
+  &preinit_2
+};
+
+int
+main (void)
+{
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/preinit.out b/binutils-2.19/ld/testsuite/ld-elf/preinit.out
new file mode 100644
index 0000000..6a30bc6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/preinit.out
@@ -0,0 +1,3 @@
+preinit array 0
+preinit array 1
+preinit array 2
diff --git a/binutils-2.19/ld/testsuite/ld-elf/relro1.s b/binutils-2.19/ld/testsuite/ld-elf/relro1.s
new file mode 100644
index 0000000..76c956d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/relro1.s
@@ -0,0 +1,14 @@
+	.globl main
+	.globl start
+	.globl _start
+	.globl __start
+	.text
+main:
+start:
+_start:
+__start:
+	.long	0
+	.data
+	.long	0
+	.section .data.rel.ro,"aw",%progbits
+	.long	0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/relro2.s b/binutils-2.19/ld/testsuite/ld-elf/relro2.s
new file mode 100644
index 0000000..0bbf366
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/relro2.s
@@ -0,0 +1,5 @@
+	.text
+	.globl x
+	.type	x, @function
+x:
+	jmp foo@PLT
diff --git a/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg-script-adjoining-pages.t b/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg-script-adjoining-pages.t
new file mode 100644
index 0000000..763fcb7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg-script-adjoining-pages.t
@@ -0,0 +1,11 @@
+SECTIONS
+{
+  . = 0x1000;
+  .sec1 : { *sec-to-seg1.o(.rodata) }
+  . += CONSTANT(MAXPAGESIZE);
+  .sec2  : { *sec-to-seg2.o(.rodata) }
+
+  .data : { *(.data) } /* For hppa64.  */
+  
+  /DISCARD/	: {*(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg-script-disjoint-pages.t b/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg-script-disjoint-pages.t
new file mode 100644
index 0000000..25023cc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg-script-disjoint-pages.t
@@ -0,0 +1,11 @@
+SECTIONS
+{
+  . = 0x1000;
+  .sec1 : { *sec-to-seg1.o(.rodata) }
+  . += CONSTANT(MAXPAGESIZE) * 2;
+  .sec2  : { *sec-to-seg2.o(.rodata) }
+
+  .data : { *(.data) } /* For hppa64.  */
+  
+  /DISCARD/	: {*(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg-script-same-page.t b/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg-script-same-page.t
new file mode 100644
index 0000000..2b50f7e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg-script-same-page.t
@@ -0,0 +1,10 @@
+SECTIONS
+{
+  . = 0x1000;
+  .sec1 : { *sec-to-seg1.o(.rodata) }
+  .sec2 : { *sec-to-seg2.o(.rodata) }
+
+  .data : { *(.data) } /* For hppa64.  */
+
+  /DISCARD/ : {*(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg.exp b/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg.exp
new file mode 100644
index 0000000..a576fce
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg.exp
@@ -0,0 +1,97 @@
+# Test the assigment of sections to segments.
+#
+# Copyright 2008   Free Software Foundation, Inc.
+# Contributed by Red Hat.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+set testname "assignment of ELF sections to segments"
+
+if {! [is_elf_format] } {
+    unsupported $testname
+    return
+}
+
+if {   ! [ld_assemble $as $srcdir/$subdir/sec-to-seg1.s tmpdir/sec-to-seg1.o]
+    || ! [ld_assemble $as $srcdir/$subdir/sec-to-seg2.s tmpdir/sec-to-seg2.o]} then {
+    unresolved $testname
+    return
+}
+
+proc sec_to_seg_test { testname scriptname same_seg } {
+    global srcdir
+    global subdir
+    global ld
+    global exec_output
+    global READELF
+    
+    if {! [ld_simple_link $ld tmpdir/sec-to-seg "-T $srcdir/$subdir/$scriptname tmpdir/sec-to-seg1.o tmpdir/sec-to-seg2.o"] } then {
+	fail $testname
+	return 0
+    }
+
+    send_log "$READELF --program-headers --section-headers tmpdir/sec-to-seg\n"
+    set exec_output [run_host_cmd "$READELF" "--program-headers --section-headers tmpdir/sec-to-seg"]
+
+    if { $same_seg == 1 } {
+      if {! [regexp ".*.sec1 .sec2" $exec_output] } {
+	  fail $testname
+	  return 0
+      }
+    } else {
+      if {  [regexp ".*.sec1 .sec2" $exec_output] } {
+	  fail $testname
+	  return 0
+      }
+    }
+
+    pass $testname
+    return 1
+}
+
+# Assuming a pagesize of 0x1000 then:
+#
+# Test  Sec1 End  Sec 2 Start    Expected Result
+# ----  --------  -----------    ---------------
+#  A    00001042   00001043      Both sections on same page: assign to same segment.
+#  B    00001042   00002044      Sections on adjacent pages: assign to same segment.
+#  C    00001042   00003044      Sections on disjoint pages: assign to separate segments.
+
+# These targets have a pagesize of 1, so they will always end up
+# placing the two sections in separate segments in the B test.
+if {    [istarget avr-*-*]
+     || [istarget cr16-*-*]
+     || [istarget crx-*-*]
+     || [istarget dlx-*-*]
+     || [istarget h8300-*-*]
+     || [istarget ip2k-*-*]
+     || [istarget m32r-*-*]
+     || [istarget m88k-*-*]
+     || [istarget msp430-*-*]
+    } {
+    set B_test_same_seg 0
+} else {
+    set B_test_same_seg 1
+}
+
+sec_to_seg_test "assignment of ELF sections to segments (same page)"      "sec-to-seg-script-same-page.t" 1
+sec_to_seg_test "assignment of ELF sections to segments (adjacent pages)" "sec-to-seg-script-adjoining-pages.t" $B_test_same_seg
+sec_to_seg_test "assignment of ELF sections to segments (disjoint pages)" "sec-to-seg-script-disjoint-pages.t" 0
+
+
+# FIXME: Add more tests to check other rules of section to segment assignment.
diff --git a/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg1.s b/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg1.s
new file mode 100644
index 0000000..1e8e2bb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg1.s
@@ -0,0 +1,9 @@
+	.file	"sec-to-seg1.s"
+
+	.section	.rodata
+	.align	2
+	.ascii	"aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa\000"
+	.align	2
+	.ascii	"0000000000000000000000000000000\000"
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg2.s b/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg2.s
new file mode 100644
index 0000000..b1dd078
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/sec-to-seg2.s
@@ -0,0 +1,13 @@
+	.file	"sec-to-seg2.s"
+
+	.section	.rodata
+	.align	2
+	.ascii	"zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz\000"
+	.align	2
+	.ascii	"55555555555555555555555555555555\000"
+	.align	2
+	.ascii	"xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx\000"
+	.align	2
+	.ascii	"99999999999999999999999999999999\000"
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-elf/sec64k.exp b/binutils-2.19/ld/testsuite/ld-elf/sec64k.exp
new file mode 100644
index 0000000..349477f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/sec64k.exp
@@ -0,0 +1,170 @@
+# Expect script for tests for >64k sections
+#   Copyright 2002, 2003, 2006, 2007, 2008 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Hans-Peter Nilsson (hp@axis.com)
+#
+
+# Exclude non-ELF targets.
+
+if ![is_elf_format] {
+    return
+}
+
+# Test >64k sections, with and without -r.  First, create the assembly
+# files.  Have a relocation to another section and one within the local
+# section.
+
+set test1 "64ksec-r"
+set test2 "64ksec"
+
+if { ![runtest_file_p $runtests $test1] \
+	&& ![runtest_file_p $runtests $test2] } {
+    return
+}
+
+set sfiles {}
+set max_sec 66000
+set secs_per_file 1000
+for { set i 0 } { $i < $max_sec / $secs_per_file } { incr i } {
+    set sfile "$objdir/tmpdir/sec64-$i.s"
+    lappend sfiles $sfile
+    if [catch { set ofd [open $sfile w] } x] {
+	perror "$x"
+	unresolved $test1
+	unresolved $test2
+	return
+    }
+
+    if { $i == 0 } {
+	puts $ofd " .global start"
+	puts $ofd "start:"
+	puts $ofd " .global _start"
+	puts $ofd "_start:"
+	puts $ofd " .global __start"
+	puts $ofd "__start:"
+	puts $ofd " .global main"
+	puts $ofd "main:"
+	puts $ofd " .global foo_0"
+	puts $ofd "foo_0: .dc.a 0"
+    }
+
+    # Make sure the used section is not covered by common linker scripts.
+    # They should get separate section entries even without -r.
+    puts $ofd " .altmacro"
+    puts $ofd " .macro sec secn, secp"
+    puts $ofd "  .section .foo.\\secn,\"ax\""
+    puts $ofd "  .global foo_\\secn"
+    puts $ofd "foo_\\secn:"
+    puts $ofd "  .dc.a foo_\\secp"
+    puts $ofd "bar_\\secn:"
+    puts $ofd "  .dc.a bar_\\secn"
+    puts $ofd " .endm"
+    puts $ofd " secn = [expr $i * $secs_per_file]"
+    puts $ofd " .rept $secs_per_file"
+    puts $ofd "  secn = secn + 1"
+    puts $ofd "  sec %(secn), %(secn-1)"
+    puts $ofd " .endr"
+
+    close $ofd
+}
+
+if [catch { set ofd [open "tmpdir/$test1.d" w] } x] {
+    perror "$x"
+    unresolved $test1
+    unresolved $test2
+    return
+}
+
+# The ld-r linked file will contain relocation-sections too, so make it
+# half the size in order to try and keep the test-time down.
+
+# The m32r target generates both REL and RELA relocs (for historical
+# reasons) so the expected number of sections will be much more than
+# 68000, which throws this particular test right off.
+if {![istarget "m32r-*-*"]} then {
+    foreach sfile [lrange $sfiles 0 [expr [llength $sfiles] / 2]] {
+	puts $ofd "#source: $sfile"
+    }
+    puts $ofd "#ld: -r"
+    puts $ofd "#readelf: -W -Ss"
+    puts $ofd "There are 680.. section headers.*:"
+    puts $ofd "#..."
+    puts $ofd "  \\\[ 0\\\] .* 680\[0-9\]\[0-9\]\[ \]+0\[ \]+0"
+    puts $ofd "#..."
+    puts $ofd "  \\\[ \[0-9\]\\\] \.foo\.1\[ \]+PROGBITS\[ \]+.*"
+    puts $ofd "#..."
+    puts $ofd "  \\\[65279\\\] (.rel\[a\]?)?\\.foo\\.\[0-9\]+ .*"
+    puts $ofd "  \\\[65280\\\] (.rel\[a\]?)?\\.foo\\.\[0-9\]+ .*"
+    puts $ofd "#..."
+    puts $ofd " 340..: 0+\[ \]+0\[ \]+SECTION\[ \]+LOCAL\[ \]+DEFAULT\[ \]+68... "
+    puts $ofd "#..."
+    puts $ofd " 340..: 0+(2|4|8)\[ \]+0\[ \]+NOTYPE\[ \]+LOCAL\[ \]+DEFAULT\[ \]+\[23\] bar_1$"
+    puts $ofd "#..."
+    puts $ofd ".* bar_34000$"
+    puts $ofd "#..."
+    # Global symbols are not in "alphanumeric" order, so we just check
+    # that the first and the last are present in any order (assuming no
+    # duplicates).
+    puts $ofd ".* (\[0-9\] foo_1|68... foo_34000)$"
+    puts $ofd "#..."
+    puts $ofd ".* (\[0-9\] foo_1|68... foo_34000)$"
+    puts $ofd "#pass"
+    close $ofd
+    run_dump_test "tmpdir/$test1"
+}
+
+if [catch { set ofd [open "tmpdir/$test2.d" w] } x] {
+    perror "$x"
+    unresolved $test2
+    return
+}
+foreach sfile $sfiles { puts $ofd "#source: $sfile" }
+if { [istarget spu*-*-*] } {
+    puts $ofd "#ld: --local-store 0:0"
+} else {
+    puts $ofd "#ld:"
+}
+puts $ofd "#readelf: -W -Ss"
+puts $ofd "There are 660.. section headers.*:"
+puts $ofd "#..."
+puts $ofd "  \\\[ 0\\\] .* 660..\[ \]+0\[ \]+0"
+puts $ofd "#..."
+puts $ofd "  \\\[65279\\\] \\.foo\\.\[0-9\]+ .*"
+puts $ofd "  \\\[65280\\\] \\.foo\\.\[0-9\]+ .*"
+puts $ofd "#..."
+puts $ofd " 660..: \[0-9a-f\]+\[ \]+0\[ \]+SECTION\[ \]+LOCAL\[ \]+DEFAULT\[ \]+660.. "
+puts $ofd "#..."
+puts $ofd " 660..: \[0-9a-f\]+\[ \]+0\[ \]+NOTYPE\[ \]+LOCAL\[ \]+DEFAULT\[ \]+\[0-9\] bar_1$"
+puts $ofd "#..."
+puts $ofd ".* bar_66000$"
+puts $ofd "#..."
+# Global symbols are not in "alphanumeric" order, so we just check
+# that the first and the last are present in any order (assuming no
+# duplicates).
+puts $ofd ".* (\[0-9\] foo_1|66... foo_66000)$"
+puts $ofd "#..."
+puts $ofd ".* (\[0-9\] foo_1|66... foo_66000)$"
+puts $ofd "#pass"
+close $ofd
+run_dump_test "tmpdir/$test2"
+
+for { set i 1 } { $i < $max_sec / $secs_per_file } { incr i } {
+    catch "exec rm -f tmpdir/dump$i.o" status
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/seg.d b/binutils-2.19/ld/testsuite/ld-elf/seg.d
new file mode 100644
index 0000000..c858c13
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/seg.d
@@ -0,0 +1,19 @@
+#target: *-*-linux* *-*-vxworks
+#source: seg.s
+#ld: -T seg.t -z max-page-size=0x1000
+#readelf: -l --wide
+
+#...
+Program Headers:
+  Type           Offset   VirtAddr.*
+# On MIPS, the first segment is for .reginfo.
+#...
+  LOAD           .*
+  LOAD           0x0*001000 0xf*fffff000 0xf*fffff000 0x0*1000 0x0*1000 .*
+
+ Section to Segment mapping:
+  Segment Sections...
+   00     .*
+# On MIPS, the first segment is for .reginfo.
+#...
+   0.     reset boot 
diff --git a/binutils-2.19/ld/testsuite/ld-elf/seg.s b/binutils-2.19/ld/testsuite/ld-elf/seg.s
new file mode 100644
index 0000000..24ec567
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/seg.s
@@ -0,0 +1,6 @@
+	.section boot,"ax"
+	.4byte 0x76543210
+	.section reset,"ax"
+	.4byte 0xfedcba98
+	.text
+	.4byte 0x12345678
diff --git a/binutils-2.19/ld/testsuite/ld-elf/seg.t b/binutils-2.19/ld/testsuite/ld-elf/seg.t
new file mode 100644
index 0000000..2f86acf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/seg.t
@@ -0,0 +1,16 @@
+
+SECTIONS
+{
+  reset - 4 :
+  {
+    *(reset)
+  }
+  boot - 0x1000 :
+  {
+    *(boot)
+  } = 0xffff
+  . = + SIZEOF_HEADERS;
+  .text : { *(.text) }
+  .data : { *(.data) }
+  .bss : { *(.bss) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/shared.exp b/binutils-2.19/ld/testsuite/ld-elf/shared.exp
new file mode 100644
index 0000000..846027e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/shared.exp
@@ -0,0 +1,286 @@
+# Expect script for various ELF tests.
+#   Copyright 2006, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Exclude non-ELF targets.
+
+if ![is_elf_format] {
+    return
+}
+
+# The following tests require running the executable generated by ld.
+if ![isnative] {
+    return
+}
+
+# Check if compiler works
+if { [which $CC] == 0 } {
+    return
+}
+
+set build_tests {
+  {"Build libfoo.so"
+   "-shared" "-fPIC"
+   {foo.c} {} "libfoo.so"}
+  {"Build versioned libfoo.so"
+   "-shared -Wl,--version-script=foo.map" "-fPIC"
+   {foo.c} {} "libfoov.so"}
+  {"Build libbar.so"
+   "-shared" "-fPIC"
+   {begin.c end.c} {} "libbar.so"}
+  {"Build warn libbar.so"
+   "-shared" "-fPIC"
+   {beginwarn.c end.c} {} "libbarw.so"}
+  {"Build hidden libbar.so"
+   "-shared" "-fPIC"
+   {begin.c endhidden.c} {} "libbarh.so"}
+  {"Build protected libbar.so"
+   "-shared" "-fPIC"
+   {begin.c endprotected.c} {} "libbarp.so"}
+  {"Build libbar.so with libfoo.so"
+   "-shared tmpdir/begin.o tmpdir/libfoo.so" "-fPIC"
+   {end.c} {} "libbarfoo.so"}
+  {"Build libar.so with versioned libfoo.so"
+   "-shared tmpdir/begin.o tmpdir/libfoov.so" "-fPIC"
+   {end.c} {} "libbarfoov.so"}
+  {"Build hidden libbar.so with libfoo.so"
+   "-shared tmpdir/begin.o tmpdir/libfoo.so" "-fPIC"
+   {endhidden.c} {} "libbarhfoo.so"}
+  {"Build hidden libar.so with versioned libfoo.so"
+   "-shared tmpdir/begin.o tmpdir/libfoov.so" "-fPIC"
+   {endhidden.c} {} "libbarhfoov.so"}
+  {"Build protected libbar.so with libfoo.so"
+   "-shared tmpdir/begin.o tmpdir/libfoo.so" "-fPIC"
+   {endprotected.c} {} "libbarpfoo.so"}
+  {"Build protected libbar.so with versioned libfoo.so"
+   "-shared tmpdir/begin.o tmpdir/libfoov.so" "-fPIC"
+   {endprotected.c} {} "libbarpfoov.so"}
+  {"Build libdl1.so"
+   "-shared" "-fPIC"
+   {dl1.c} {} "libdl1.so"}
+  {"Build libdl2a.so with --dynamic-list=dl2.list"
+   "-shared -Wl,--dynamic-list=dl2.list" "-fPIC"
+   {dl2.c dl2xxx.c} {} "libdl2a.so"}
+  {"Build libdl2a.so with --dynamic-list=dl2a.list"
+   "-shared -Wl,--dynamic-list=dl2a.list" "-fPIC"
+   {dl2.c dl2xxx.c} {} "libdl2a.so"}
+  {"Build libdl2a.so with --dynamic-list-data"
+   "-shared -Wl,--dynamic-list-data" "-fPIC"
+   {dl2.c dl2xxx.c} {} "libdl2a.so"}
+  {"Build libdl2b.so with --dynamic-list=dl2.list and dl2xxx.list"
+   "-shared -Wl,--dynamic-list=dl2.list,--dynamic-list=dl2xxx.list" "-fPIC"
+   {dl2.c dl2xxx.c} {} "libdl2b.so"}
+  {"Build libdl2c.so with --dynamic-list-data and dl2xxx.list"
+   "-shared -Wl,--dynamic-list-data,--dynamic-list=dl2xxx.list" "-fPIC"
+   {dl2.c dl2xxx.c} {} "libdl2c.so"}
+  {"Build libdl4a.so with --dynamic-list=dl4.list"
+   "-shared -Wl,--dynamic-list=dl4.list" "-fPIC"
+   {dl4.c dl4xxx.c} {} "libdl4a.so"}
+  {"Build libdl4b.so with --dynamic-list-data"
+   "-shared -Wl,--dynamic-list-data" "-fPIC"
+   {dl4.c dl4xxx.c} {} "libdl4b.so"}
+  {"Build libdl4c.so with --dynamic-list=dl4.list and dl4xxx.list"
+   "-shared -Wl,--dynamic-list=dl4.list,--dynamic-list=dl4xxx.list" "-fPIC"
+   {dl4.c dl4xxx.c} {} "libdl4c.so"}
+  {"Build libdl4d.so with --dynamic-list-data and dl4xxx.list"
+   "-shared -Wl,--dynamic-list-data,--dynamic-list=dl4xxx.list" "-fPIC"
+   {dl4.c dl4xxx.c} {} "libdl4d.so"}
+  {"Build libdl4e.so with -Bsymbolic-functions --dynamic-list-cpp-new"
+   "-shared -Wl,-Bsymbolic-functions,--dynamic-list-cpp-new" "-fPIC"
+   {dl4.c dl4xxx.c} {} "libdl4e.so"}
+  {"Build libdl4f.so with --dynamic-list-cpp-new -Bsymbolic-functions"
+   "-shared -Wl,--dynamic-list-cpp-new,-Bsymbolic-functions" "-fPIC"
+   {dl4.c dl4xxx.c} {} "libdl4f.so"}
+  {"Build libdl6a.so"
+   "-shared" "-fPIC"
+   {dl6.c} {} "libdl6a.so"}
+  {"Build libdl6b.so with -Bsymbolic --dynamic-list-data"
+   "-shared -Wl,-Bsymbolic,--dynamic-list-data" "-fPIC"
+   {dl6.c} {} "libdl6b.so"}
+  {"Build libdl6c.so with -Bsymbolic"
+   "-shared -Wl,-Bsymbolic" "-fPIC"
+   {dl6.c} {} "libdl6c.so"}
+  {"Build libdl6d.so with --dynamic-list-data -Bsymbolic"
+   "-shared -Wl,--dynamic-list-data,-Bsymbolic" "-fPIC"
+   {dl6.c} {} "libdl6d.so"}
+  {"Build libdata1.so"
+   "-shared" "-fPIC"
+   {data1.c} {} "libdata1.so"}
+}
+
+set run_tests {
+    {"Run normal with libfoo.so"
+     "tmpdir/begin.o tmpdir/libfoo.so tmpdir/end.o" ""
+     {main.c} "normal" "normal.out"}
+    {"Run protected with libfoo.so"
+     "tmpdir/begin.o tmpdir/libfoo.so tmpdir/endprotected.o" ""
+     {main.c} "protected" "normal.out"}
+    {"Run hidden with libfoo.so"
+     "tmpdir/begin.o tmpdir/libfoo.so tmpdir/endhidden.o" ""
+     {main.c} "hidden" "hidden.out"}
+    {"Run normal with versioned libfoo.so"
+     "tmpdir/begin.o tmpdir/libfoov.so tmpdir/end.o" ""
+     {main.c} "normalv" "normal.out"}
+    {"Run warn with versioned libfoo.so"
+     "tmpdir/beginwarn.o tmpdir/libfoov.so" ""
+     {main.c} "warn" "warn.out"
+     "" "" "^.*\\\): warning: function foo is deprecated$"}
+    {"Run protected with versioned libfoo.so"
+     "tmpdir/begin.o tmpdir/libfoov.so tmpdir/endprotected.o" ""
+     {main.c} "protected" "normal.out"}
+    {"Run hidden with versioned libfoo.so"
+     "tmpdir/begin.o tmpdir/libfoov.so tmpdir/endhidden.o" ""
+     {main.c} "hiddenv" "hidden.out"}
+    {"Run normal libbar.so with libfoo.so"
+     "tmpdir/libbarfoo.so tmpdir/libfoo.so" ""
+     {main.c} "normal" "normal.out"}
+    {"Run protected libbar.so with libfoo.so"
+     "tmpdir/libbarpfoo.so tmpdir/libfoo.so" ""
+     {main.c} "protected" "normal.out"}
+    {"Run hidden libbar.so with libfoo.so"
+     "tmpdir/libbarhfoo.so tmpdir/libfoo.so" ""
+     {main.c} "hidden" "hidden.out"}
+    {"Run normal libbar.so with versioned libfoo.so"
+     "tmpdir/libbarfoov.so tmpdir/libfoov.so" ""
+     {main.c} "normal" "normal.out"}
+    {"Run protected libbar.so with versioned libfoo.so"
+     "tmpdir/libbarpfoov.so tmpdir/libfoov.so" ""
+     {main.c} "protected" "normal.out"}
+    {"Run hidden libbar.so with versioned libfoo.so"
+     "tmpdir/libbarhfoov.so tmpdir/libfoov.so" ""
+     {main.c} "hidden" "hidden.out"}
+    {"Run dl1a with --dynamic-list=dl1.list and dlopen on libdl1.so"
+     "--dynamic-list=dl1.list -ldl" ""
+     {dl1main.c} "dl1a" "dl1.out"}
+    {"Run dl1b with --dynamic-list-data and dlopen on libdl1.so"
+     "--dynamic-list-data -ldl" ""
+     {dl1main.c} "dl1b" "dl1.out"}
+    {"Run with libdl2a.so"
+     "tmpdir/libdl2a.so" ""
+     {dl2main.c} "dl2a" "dl2a.out"}
+    {"Run with libdl2b.so"
+     "tmpdir/libdl2b.so" ""
+     {dl2main.c} "dl2b" "dl2b.out"}
+    {"Run with libdl2c.so"
+     "tmpdir/libdl2c.so" ""
+     {dl2main.c} "dl2c" "dl2b.out"}
+    {"Run with libdl4a.so"
+     "tmpdir/libdl4a.so" ""
+     {dl4main.c} "dl4a" "dl4a.out"}
+    {"Run with libdl4b.so"
+     "tmpdir/libdl4b.so" ""
+     {dl4main.c} "dl4b" "dl4a.out"}
+    {"Run with libdl4c.so"
+     "tmpdir/libdl4c.so" ""
+     {dl4main.c} "dl4c" "dl4b.out"}
+    {"Run with libdl4d.so"
+     "tmpdir/libdl4d.so" ""
+     {dl4main.c} "dl4d" "dl4b.out"}
+    {"Run with libdl4e.so"
+     "tmpdir/libdl4e.so" ""
+     {dl4main.c} "dl4e" "dl4a.out"}
+    {"Run with libdl4f.so"
+     "tmpdir/libdl4f.so" ""
+     {dl4main.c} "dl4f" "dl4a.out"}
+    {"Run dl6a1 with --dynamic-list-data and dlopen on libdl6a.so"
+     "--dynamic-list-data -ldl" ""
+     {dl6amain.c} "dl6a1" "dl6a.out"}
+    {"Run dl6a2 with -Bsymbolic-functions and dlopen on libdl6a.so"
+     "-Bsymbolic-functions -ldl" ""
+     {dl6amain.c} "dl6a2" "dl6b.out"}
+    {"Run dl6a3 with -Bsymbolic and dlopen on libdl6a.so"
+     "-Bsymbolic -ldl" ""
+     {dl6amain.c} "dl6a3" "dl6b.out"}
+    {"Run dl6a4 with -Bsymbolic --dynamic-list-data and dlopen on libdl6a.so"
+     "-Bsymbolic --dynamic-list-data -ldl" ""
+     {dl6amain.c} "dl6a4" "dl6a.out"}
+    {"Run dl6a5 with -Bsymbolic-functions --dynamic-list-cpp-new and dlopen on libdl6a.so"
+     "-Bsymbolic-functions --dynamic-list-cpp-new -ldl" ""
+     {dl6amain.c} "dl6a5" "dl6b.out"}
+    {"Run dl6a6 with --dynamic-list-cpp-new -Bsymbolic-functions and dlopen on libdl6a.so"
+     "--dynamic-list-cpp-new -Bsymbolic-functions -ldl" ""
+     {dl6amain.c} "dl6a6" "dl6b.out"}
+    {"Run dl6a7 with --dynamic-list-data -Bsymbolic and dlopen on libdl6a.so"
+     "--dynamic-list-data -Bsymbolic -ldl" ""
+     {dl6amain.c} "dl6a7" "dl6a.out"}
+    {"Run dl6b1 with --dynamic-list-data and dlopen on libdl6b.so"
+     "--dynamic-list-data -ldl" ""
+     {dl6bmain.c} "dl6b1" "dl6a.out"}
+    {"Run dl6b2 with dlopen on libdl6b.so"
+     "-ldl" ""
+     {dl6bmain.c} "dl6b2" "dl6b.out"}
+    {"Run dl6c1 with --dynamic-list-data and dlopen on libdl6c.so"
+     "--dynamic-list-data -ldl" ""
+     {dl6cmain.c} "dl6c1" "dl6b.out"}
+    {"Run dl6d1 with --dynamic-list-data and dlopen on libdl6d.so"
+     "--dynamic-list-data -ldl" ""
+     {dl6dmain.c} "dl6d1" "dl6b.out"}
+    {"Run with libdata1.so"
+     "tmpdir/libdata1.so" ""
+     {dynbss1.c} "dynbss1" "pass.out"}
+}
+
+run_cc_link_tests $build_tests
+# NetBSD ELF systems do not currently support the .*_array sections.
+run_ld_link_exec_tests [list "*-*-netbsdelf*"] $run_tests
+
+# Check if compiler works
+if { [which $CXX] == 0 } {
+    return
+}
+
+set build_cxx_tests {
+  {"Build libdl3a.so with --dynamic-list=dl3.list"
+   "-shared -Wl,--dynamic-list=dl3.list" "-fPIC"
+   {dl3.cc} {} "libdl3a.so" "c++"}
+  {"Build libdl3b.so with -Bsymbolic"
+   "-shared -Wl,-Bsymbolic" "-fPIC"
+   {dl3.cc} {} "libdl3b.so" "c++"}
+  {"Build libdl3a.so with --dynamic-list-cpp-typeinfo"
+   "-shared -Wl,--dynamic-list-cpp-typeinfo" "-fPIC"
+   {dl3.cc} {} "libdl3c.so" "c++"}
+  {"Build libdnew1a.so with --Bsymbolic-functions --dynamic-list-cpp-new"
+   "-shared -Wl,-Bsymbolic-functions,--dynamic-list-cpp-new" "-fPIC"
+   {del.cc new.cc} {} "libnew1a.so" "c++"}
+  {"Build libdnew1b.so with --dynamic-list-data --dynamic-list-cpp-new"
+   "-shared -Wl,--dynamic-list-data,--dynamic-list-cpp-new" "-fPIC"
+   {del.cc new.cc} {} "libnew1b.so" "c++"}
+}
+
+set run_cxx_tests {
+    {"Run with libdl3a.so"
+     "tmpdir/libdl3a.so" ""
+     {dl3main.cc} "dl3a" "dl3a.out" "" "c++"}
+    {"Run with libdl3b.so"
+     "tmpdir/libdl3b.so" ""
+     {dl3main.cc} "dl3b" "dl3b.out" "" "c++"}
+    {"Run with libdl3c.so"
+     "tmpdir/libdl3c.so" ""
+     {dl3main.cc} "dl3c" "dl3a.out" "" "c++"}
+    {"Run with libnew1a.so"
+     "tmpdir/libnew1a.so" ""
+     {dl5.cc} "dl5a" "dl5.out" "" "c++"}
+    {"Run with libnew1b.so"
+     "tmpdir/libnew1b.so" ""
+     {dl5.cc} "dl5b" "dl5.out" "" "c++"}
+}
+
+run_cc_link_tests $build_cxx_tests
+run_ld_link_exec_tests [] $run_cxx_tests
diff --git a/binutils-2.19/ld/testsuite/ld-elf/stab.d b/binutils-2.19/ld/testsuite/ld-elf/stab.d
new file mode 100644
index 0000000..6676238
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/stab.d
@@ -0,0 +1,11 @@
+#source: start.s
+#as: -gstabs
+#readelf: -S --wide
+#ld:
+#notarget: ia64-*-*
+
+#...
+  \[[0-9 ][0-9]\] \.stab +PROGBITS +0+ [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ +[1-9]+ +0.*
+#...
+  \[[0-9 ][0-9]\] \.stabstr +STRTAB +0+ [0-9a-f]+ [0-9a-f]+ 00 +0 +0.*
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-elf/start.s b/binutils-2.19/ld/testsuite/ld-elf/start.s
new file mode 100644
index 0000000..d8655be
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/start.s
@@ -0,0 +1,10 @@
+	.text
+	.global start	/* Used by SH targets.  */
+start:
+	.global _start
+_start:
+	.global __start
+__start:
+	.global main	/* Used by HPPA targets.  */
+main:
+	.dc.a 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/symbol1ref.s b/binutils-2.19/ld/testsuite/ld-elf/symbol1ref.s
new file mode 100644
index 0000000..15725cb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/symbol1ref.s
@@ -0,0 +1,3 @@
+	.text
+	.dc.a symbol1
+
diff --git a/binutils-2.19/ld/testsuite/ld-elf/symbol1w.s b/binutils-2.19/ld/testsuite/ld-elf/symbol1w.s
new file mode 100644
index 0000000..38778d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/symbol1w.s
@@ -0,0 +1,10 @@
+	.section .gnu.warning.symbol1
+	.asciz "witty one-liner"
+	.text
+	.type symbol1,"function"
+	.global symbol1
+symbol1:
+.L1:
+	.long 0
+.L0:
+	.size symbol1,.L0-.L1
diff --git a/binutils-2.19/ld/testsuite/ld-elf/symbol2ref.s b/binutils-2.19/ld/testsuite/ld-elf/symbol2ref.s
new file mode 100644
index 0000000..d2710f9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/symbol2ref.s
@@ -0,0 +1,3 @@
+	.text
+	.dc.a Foo
+
diff --git a/binutils-2.19/ld/testsuite/ld-elf/symbol2w.s b/binutils-2.19/ld/testsuite/ld-elf/symbol2w.s
new file mode 100644
index 0000000..794a753
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/symbol2w.s
@@ -0,0 +1,6 @@
+        .section        .gnu.warning,"a",%progbits
+	.global Foo
+        .type   Foo, %object
+        .size   Foo, 20
+Foo:
+        .string "function 'Foo' used"
diff --git a/binutils-2.19/ld/testsuite/ld-elf/table.s b/binutils-2.19/ld/testsuite/ld-elf/table.s
new file mode 100644
index 0000000..2b13f70
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/table.s
@@ -0,0 +1 @@
+	.section	.gcc_except_table,"a",%progbits
diff --git a/binutils-2.19/ld/testsuite/ld-elf/tbss.s b/binutils-2.19/ld/testsuite/ld-elf/tbss.s
new file mode 100644
index 0000000..cc43340
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/tbss.s
@@ -0,0 +1,15 @@
+	.file	"x.c"
+	.globl bss
+	.section	.bss,"aw",%nobits
+	.p2align 12
+	.type	bss,%object
+	.size	bss,4096
+bss:
+	.zero	4096
+	.globl tbss
+	.section	.tbss,"awT",%nobits
+	.p2align 12
+	.type	tbss,%object
+	.size	tbss,4096
+tbss:
+	.zero	4096
diff --git a/binutils-2.19/ld/testsuite/ld-elf/tbss1.s b/binutils-2.19/ld/testsuite/ld-elf/tbss1.s
new file mode 100644
index 0000000..4f1631f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/tbss1.s
@@ -0,0 +1,24 @@
+	.globl main
+	.globl start
+	.globl _start
+	.globl __start
+	.text
+main:
+start:
+_start:
+__start:
+	.byte 0
+	.globl bss
+	.section	.bss,"aw",%nobits
+	.p2align 12
+	.type	bss,%object
+	.size	bss,4096
+bss:
+	.zero	4096
+	.globl tbss
+	.section	.tbss,"awT",%nobits
+	.p2align 12
+	.type	tbss,%object
+	.size	tbss,4096
+tbss:
+	.zero	4096
diff --git a/binutils-2.19/ld/testsuite/ld-elf/tbss2.s b/binutils-2.19/ld/testsuite/ld-elf/tbss2.s
new file mode 100644
index 0000000..b980925
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/tbss2.s
@@ -0,0 +1,16 @@
+	.globl main
+	.globl start
+	.globl _start
+	.globl __start
+	.text
+main:
+start:
+_start:
+__start:
+	.byte 0
+	.globl tbss
+	.section	.tbss,"awT",%nobits
+	.type	tbss,%object
+	.size	tbss,1
+tbss:
+	.zero	1
diff --git a/binutils-2.19/ld/testsuite/ld-elf/tdata1.s b/binutils-2.19/ld/testsuite/ld-elf/tdata1.s
new file mode 100644
index 0000000..6ea57b6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/tdata1.s
@@ -0,0 +1,24 @@
+	.globl main
+	.globl start
+	.globl _start
+	.globl __start
+	.text
+main:
+start:
+_start:
+__start:
+	.byte 0
+	.globl data
+	.section	.data,"aw",%progbits
+	.p2align 4
+	.type	data,%object
+	.size	data,4096
+data:
+	.zero	4096
+	.globl tdata
+	.section	.tdata,"awT",%progbits
+	.p2align 4
+	.type	tdata,%object
+	.size	tdata,4096
+tdata:
+	.zero	4096
diff --git a/binutils-2.19/ld/testsuite/ld-elf/tdata2.s b/binutils-2.19/ld/testsuite/ld-elf/tdata2.s
new file mode 100644
index 0000000..1da459f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/tdata2.s
@@ -0,0 +1,16 @@
+	.globl main
+	.globl start
+	.globl _start
+	.globl __start
+	.text
+main:
+start:
+_start:
+__start:
+	.byte 0
+	.globl tdata
+	.section	.tdata,"awT",%progbits
+	.type	tdata,%object
+	.size	tdata,1
+tdata:
+	.byte 0
diff --git a/binutils-2.19/ld/testsuite/ld-elf/tls_common.exp b/binutils-2.19/ld/testsuite/ld-elf/tls_common.exp
new file mode 100644
index 0000000..66a550c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/tls_common.exp
@@ -0,0 +1,72 @@
+# Expect script for .tls_common tests
+#   Copyright 2006, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Jakub Jelinek (jakub@redhat.com)
+#
+
+# Make sure that binutils can correctly handle ld output in ELF.
+
+# Run on Linux only.
+if { ![istarget *-*-linux*] } {
+    return
+}
+
+if { [istarget *-*-linux*aout*]
+     || [istarget *-*-linux*oldld*] } {
+    return
+}
+
+global as
+global ld
+global READELF
+global srcdir
+global subdir
+global link_output
+
+if { ![ld_assemble $as $srcdir/$subdir/tls_common.s tmpdir/tls_common.o ] } {
+    unresolved "tls_common"
+    return
+}
+
+if { ![ld_simple_link $ld tmpdir/tls_common1.o "-r tmpdir/tls_common.o"] } {
+    fail "tls_common"
+    return
+}
+
+if { ![ld_simple_link $ld tmpdir/tls_common "tmpdir/tls_common1.o"] } {
+    if { [string match "*not supported*" $link_output]
+	 || [string match "*unrecognized option*" $link_output] } {
+	unsupported "$ld_options is not supported by this target"
+    } elseif { [string match "*Warning*alignment*of common symbol*" $link_output] } {
+	fail "tls_common"
+    } else {
+	unresolved "tls_common"
+    }
+    return
+} 
+
+set readelf_output [run_host_cmd "$READELF" "-l --wide tmpdir/tls_common"]
+if ![regexp ".*TLS.*0x0+ 0x0+4 R .*" $readelf_output] then {
+    send_log "$readelf_output\n"
+    fail "tls_common"
+    return
+}
+
+pass "tls_common"
diff --git a/binutils-2.19/ld/testsuite/ld-elf/tls_common.s b/binutils-2.19/ld/testsuite/ld-elf/tls_common.s
new file mode 100644
index 0000000..502d8f3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/tls_common.s
@@ -0,0 +1,11 @@
+	.globl main
+	.globl start
+	.globl _start
+	.globl __start
+	.text
+main:
+start:
+_start:
+__start:
+	.byte 0
+	.tls_common	foo,4,4
diff --git a/binutils-2.19/ld/testsuite/ld-elf/tls_gc.s b/binutils-2.19/ld/testsuite/ld-elf/tls_gc.s
new file mode 100644
index 0000000..db93eba
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/tls_gc.s
@@ -0,0 +1,16 @@
+	.globl main
+	.globl start
+	.globl _start
+	.globl __start
+	.text
+main:
+start:
+_start:
+__start:
+	.byte 0
+	.globl var
+	.section	.tbss.var,"awT",%nobits
+	.type	var,%object
+	.size	var,1
+var:
+	.zero	1
diff --git a/binutils-2.19/ld/testsuite/ld-elf/unknown.d b/binutils-2.19/ld/testsuite/ld-elf/unknown.d
new file mode 100644
index 0000000..636e6c7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/unknown.d
@@ -0,0 +1,7 @@
+#source: ../../../binutils/testsuite/binutils-all/unknown.s
+#ld: -r
+#readelf: -S
+
+#...
+  \[[ 0-9]+\] \.foo[ \t]+NOTE[ \t]+.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/unknown2.d b/binutils-2.19/ld/testsuite/ld-elf/unknown2.d
new file mode 100644
index 0000000..467d5d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/unknown2.d
@@ -0,0 +1,8 @@
+#source: unknown2.s
+#ld: -shared
+#readelf: -S
+#target: *-*-linux*
+
+#...
+  \[[ 0-9]+\] \.note.foo[ \t]+NOTE[ \t]+.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/unknown2.s b/binutils-2.19/ld/testsuite/ld-elf/unknown2.s
new file mode 100644
index 0000000..8592820
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/unknown2.s
@@ -0,0 +1,6 @@
+	.section .note.foo,"a","note"
+	.space 16
+	.section .data,"aw"
+	.space 3800
+	.section .rodata,"a"
+	.space 4
diff --git a/binutils-2.19/ld/testsuite/ld-elf/warn.out b/binutils-2.19/ld/testsuite/ld-elf/warn.out
new file mode 100644
index 0000000..ba836ce
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/warn.out
@@ -0,0 +1,3 @@
+TEST2
+TEST2
+MAIN
diff --git a/binutils-2.19/ld/testsuite/ld-elf/warn1.d b/binutils-2.19/ld/testsuite/ld-elf/warn1.d
new file mode 100644
index 0000000..7beb9da
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/warn1.d
@@ -0,0 +1,15 @@
+#source: start.s
+#source: symbol1ref.s
+#source: symbol1w.s
+#ld: -T group.ld
+#warning: ^[^\\n]*\): warning: witty one-liner$
+#readelf: -s
+#notarget: "sparc64-*-solaris2*" "sparcv9-*-solaris2*"
+#xfail: "arc-*-*" "d30v-*-*" "dlx-*-*" "i960-*-*" "or32-*-*" "pj-*-*"
+
+# Check that warnings are generated for the .gnu.warning.SYMBOL
+# construct and that the symbol still appears as expected.
+
+#...
+[ 	]+[0-9]+:[ 	]+[0-9a-f]+[ 	]+[48][ 	]+FUNC[	 ]+GLOBAL DEFAULT[ 	]+[1-9] symbol1
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/warn2.d b/binutils-2.19/ld/testsuite/ld-elf/warn2.d
new file mode 100644
index 0000000..97d4f59
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/warn2.d
@@ -0,0 +1,15 @@
+#source: start.s
+#source: symbol2ref.s
+#source: symbol2w.s
+#ld: -T group.ld
+#warning: ^[^\\n]*\.[obj]+: warning: function 'Foo' used$
+#readelf: -s
+#notarget: "sparc64-*-solaris2*" "sparcv9-*-solaris2*"
+#xfail: "arc-*-*" "d30v-*-*" "dlx-*-*" "i960-*-*" "or32-*-*" "pj-*-*"
+
+# Check that warnings are generated for the symbols in .gnu.warning
+# construct and that the symbol still appears as expected.
+
+#...
+[ 	]+[0-9]+:[ 	]+[0-9a-f]+[ 	]+20[ 	]+OBJECT[	 ]+GLOBAL DEFAULT[ 	]+[1-2] Foo
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/weak-dyn-1.ld b/binutils-2.19/ld/testsuite/ld-elf/weak-dyn-1.ld
new file mode 100644
index 0000000..495b712
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/weak-dyn-1.ld
@@ -0,0 +1,8 @@
+SECTIONS
+{
+  . = 0x800000;
+  PROVIDE (bar = .);
+  .data : {
+    *(.data)
+  }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/weak-dyn-1.rd b/binutils-2.19/ld/testsuite/ld-elf/weak-dyn-1.rd
new file mode 100644
index 0000000..ab5e0ba
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/weak-dyn-1.rd
@@ -0,0 +1,3 @@
+#...
+.* foo.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elf/weak-dyn-1a.s b/binutils-2.19/ld/testsuite/ld-elf/weak-dyn-1a.s
new file mode 100644
index 0000000..bb81d3a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/weak-dyn-1a.s
@@ -0,0 +1,13 @@
+	.globl	foo
+	.weak	foo
+	.type	foo,%object
+	.size	foo,1
+
+	.globl	bar
+	.type	bar,%object
+	.size	bar,1
+
+	.data
+foo:
+bar:
+	.byte	1
diff --git a/binutils-2.19/ld/testsuite/ld-elf/weak-dyn-1b.s b/binutils-2.19/ld/testsuite/ld-elf/weak-dyn-1b.s
new file mode 100644
index 0000000..23f187a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/weak-dyn-1b.s
@@ -0,0 +1,2 @@
+	.data
+	.dc.a	foo
diff --git a/binutils-2.19/ld/testsuite/ld-elf/wrap.exp b/binutils-2.19/ld/testsuite/ld-elf/wrap.exp
new file mode 100644
index 0000000..70e433d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/wrap.exp
@@ -0,0 +1,57 @@
+# Expect script for wrap ELF tests.
+#   Copyright 2006, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Exclude non-ELF targets.
+
+if ![is_elf_format] {
+    return
+}
+
+# The following tests require running the executable generated by ld.
+if ![isnative] {
+    return
+}
+
+# Check if compiler works
+if { [which $CC] == 0 } {
+    return
+}
+
+set build_tests {
+  {"Build libwrap1a.so"
+   "-shared" "-fPIC"
+   {wrap1a.c} {} "libwrap1a.so"}
+  {"Build libwrap1b.so"
+   "-shared tmpdir/libwrap1a.so" "-fPIC"
+   {wrap1b.c} {} "libwrap1b.so"}
+}
+
+set run_tests {
+    {"Run with libwrap1a.so and libwrap1b.so"
+     "--wrap par tmpdir/libwrap1a.so tmpdir/libwrap1b.so" ""
+     {wrap1.c} "wrap1" "wrap1.out"}
+    {"Run with libwrap1b.so and libwrap1a.so"
+     "--wrap par tmpdir/libwrap1b.so tmpdir/libwrap1a.so" ""
+     {wrap1.c} "wrap1" "wrap1.out"}
+}
+
+run_cc_link_tests $build_tests
+run_ld_link_exec_tests [] $run_tests
diff --git a/binutils-2.19/ld/testsuite/ld-elf/wrap1.c b/binutils-2.19/ld/testsuite/ld-elf/wrap1.c
new file mode 100644
index 0000000..1ff250e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/wrap1.c
@@ -0,0 +1,8 @@
+extern void par (void);
+
+int
+main (void)
+{
+  par ();
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/wrap1.out b/binutils-2.19/ld/testsuite/ld-elf/wrap1.out
new file mode 100644
index 0000000..7c1938f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/wrap1.out
@@ -0,0 +1,3 @@
+__wrap_par 
+__real_par 
+par
diff --git a/binutils-2.19/ld/testsuite/ld-elf/wrap1a.c b/binutils-2.19/ld/testsuite/ld-elf/wrap1a.c
new file mode 100644
index 0000000..75c94e0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/wrap1a.c
@@ -0,0 +1,6 @@
+#include <stdio.h>
+
+void par (void)
+{
+  printf ("par\n");
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elf/wrap1b.c b/binutils-2.19/ld/testsuite/ld-elf/wrap1b.c
new file mode 100644
index 0000000..abd39aa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elf/wrap1b.c
@@ -0,0 +1,16 @@
+#include <stdio.h>
+
+extern void par (void);
+
+void __real_par (void)
+{
+  printf ("__real_par \n");
+  par ();
+}
+
+void
+__wrap_par (void)
+{
+  printf ("__wrap_par \n");
+  __real_par ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfcomm/common1a.c b/binutils-2.19/ld/testsuite/ld-elfcomm/common1a.c
new file mode 100644
index 0000000..eb8fbef
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfcomm/common1a.c
@@ -0,0 +1,2 @@
+char foo1 [2] __attribute__((aligned(64)));
+char foo2 [2] __attribute__((aligned(128)));
diff --git a/binutils-2.19/ld/testsuite/ld-elfcomm/common1b.c b/binutils-2.19/ld/testsuite/ld-elfcomm/common1b.c
new file mode 100644
index 0000000..4ed9e03
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfcomm/common1b.c
@@ -0,0 +1,3 @@
+static char dummy1 = 'X';
+char foo1 [] = "Aligned at odd byte.";
+char foo2 [4];
diff --git a/binutils-2.19/ld/testsuite/ld-elfcomm/elfcomm.exp b/binutils-2.19/ld/testsuite/ld-elfcomm/elfcomm.exp
new file mode 100644
index 0000000..daed58b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfcomm/elfcomm.exp
@@ -0,0 +1,240 @@
+# Expect script for common symbol tests
+#   Copyright 2003, 2005, 2006, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by H.J. Lu (hjl@gnu.org)
+#
+
+# Make sure that ld correctly handles common symbols in ELF.
+
+# This test can only be run on ELF platforms.
+if ![is_elf_format] {
+    return
+}
+
+proc test_sort_common {} {
+    global exec_output
+    global objdump
+    global srcdir
+    global subdir
+    global as
+    global ld
+  
+    set test "--sort-common (descending)"
+  
+    verbose "Check to see that --sort-common sorts in descending alignment"
+
+    # We do not run the sort common tests for the DLX target because we know that the linker
+    # will seg-fault.  The built-in DLX linker script requires that there be something in the
+    # .text section and our sort-common.s file does not provide anything.
+    if [istarget dlx-*-*] {
+	untested "$test"
+	return 0
+    }
+    
+    if { ![ld_assemble $as $srcdir/$subdir/sort-common.s tmpdir/sort-common.o] } {
+	unresolved "$test"
+	return 0
+    }
+
+    if { ![ld_simple_link $ld tmpdir/sort-common.dx "--sort-common=descending tmpdir/sort-common.o"] } {
+	fail "$test"
+	return 0
+    }
+
+    send_log "$objdump --syms tmpdir/sort-common.dx | grep var | sort\n"
+    set exec_output [run_host_cmd "$objdump" "--syms tmpdir/sort-common.dx | grep var | sort"]
+
+    # Don't know why, but the CR ports fail this test.
+    setup_xfail "cr16-*-*" "crx-*-*"
+
+    # Note: The second regexp is for targets which put small commons in a .sbss
+    #  section and large commons in a .bss section.
+    if {   ![regexp ".*var_16.*var_8.*var_4.*var_2.*var_1.*" $exec_output]
+        && ![regexp ".*sbss.*var_8.*var_4.*var_2.*var_1.*bss.*var_16.*" $exec_output] } {      
+	fail $test
+    } else {
+	pass $test
+    }
+
+    set test "--sort-common (ascending)"
+  
+    verbose "Check to see that --sort-common=ascending sorts in ascending alignment"
+
+    if { ![ld_simple_link $ld tmpdir/sort-common.ax "--sort-common=ascending tmpdir/sort-common.o"] } {
+	fail "$test"
+	return 0
+    }
+
+    send_log "$objdump --syms tmpdir/sort-common.ax | grep var | sort\n"
+    set exec_output [run_host_cmd "$objdump" "--syms tmpdir/sort-common.ax | grep var | sort"]
+
+    if {![regexp ".*var_1.*var_2.*var_4.*var_8.*var_16.*" $exec_output]} {      
+	fail $test
+	return 0
+    }
+
+    pass $test
+    return 1
+}
+
+test_sort_common
+
+set test1	"size/aligment change of common symbols"
+set test1w1	"$test1 (warning 1)"
+set test1w2	"$test1 (warning 2)"
+set test1c1	"$test1 (change 1)"
+set test1c2	"$test1 (change 2)"
+
+if { ![is_remote host] && [which $CC] == 0 } {
+    untested $test1w1
+    untested $test1w2
+    untested $test1c1
+    untested $test1c2
+    return
+}
+if { [istarget score-*-*] } {
+    untested $test1w1
+    untested $test1w2
+    untested $test1c1
+    untested $test1c2
+    return
+}
+
+proc dump_common1 { testname } {
+    global exec_output
+    global READELF
+
+    send_log "$READELF --syms tmpdir/common1.o | grep foo\n"
+    set exec_output [run_host_cmd "$READELF" "--syms tmpdir/common1.o | grep foo"]
+
+    if {   ![regexp "(\[ 	\]*)(\[0-9\]+):(\[ 	\]*)(\[0\]*)80(\[ 	\]+)4(\[ 	\]+)(COMMON|OBJECT)(\[ 	\]+)GLOBAL(\[ 	\]+)DEFAULT(\[ 	\]+)(PRC\\\[0xff03\\\]|COM|SCOM)(\[ 	\]+)_?foo2" $exec_output]
+	|| ![regexp "(\[ 	\]*)(\[0-9\]+):(\[ 	\]*)(\[0-9\]+)(\[ 	\]+)21(\[ 	\]+)OBJECT(\[ 	\]+)GLOBAL(\[ 	\]+)DEFAULT(\[ 	\]+)(\[0-9\]+)(\[ 	\]+)_?foo1" $exec_output] } {
+	verbose $exec_output
+	fail $testname
+	return 0
+    }
+
+    return 1
+}
+
+proc stt_common_test { options testname } {
+    global exec_output
+    global READELF
+    global ld
+
+    set options "$options tmpdir/common1a.o"
+
+    if { ! [ld_simple_link $ld tmpdir/common.exe $options] } {
+      unresolved $testname
+      return 0
+    }
+
+    send_log "$READELF --syms tmpdir/common.exe | grep foo\n"
+    set exec_output [run_host_cmd "$READELF" "--syms tmpdir/common.exe | grep foo"]
+
+    if {![regexp "(\[ 	\]*)(\[0-9\]+):(\[ 	\]*)(\[0-9\]+)(\[ 	\]+)(\[0-9\]+)(\[ 	\]+)COMMON(\[ 	\]+)GLOBAL(\[ 	\]+)DEFAULT(\[ 	\]+)(\[0-9\]+)(\[ 	\]+)_?foo2" $exec_output] } {
+	fail $testname
+	return 0
+    }
+
+    pass $testname
+    return 1
+}
+
+# Check to see if the assembler is generating symbols with the STT_COMMON type.
+proc assembler_generates_commons {} {
+    global exec_output
+    global READELF
+
+    verbose "Check to see if STT_COMMON symbols are being generated:"
+    set exec_output [run_host_cmd "$READELF" "--syms tmpdir/common1a.o | grep foo"]
+
+    if { ![regexp "(\[ 	\]*)(\[0-9\]+):(\[ 	\]*)(\[0\]*)80(\[ 	\]+).(\[ 	\]+)COMMON(\[ 	\]+)GLOBAL(\[ 	\]+)DEFAULT(\[ 	\]+)(PRC\\\[0xff03\\\]|COM|SCOM)(\[ 	\]+)_?foo2" $exec_output] } {
+	verbose "STT_COMMON not generated"
+	return 0
+    }
+
+    verbose "STT_COMMON's are generated"
+    return 1
+}
+
+
+if {   ![ld_compile "$CC $CFLAGS" $srcdir/$subdir/common1a.c tmpdir/common1a.o]
+    || ![ld_compile "$CC $CFLAGS" $srcdir/$subdir/common1b.c tmpdir/common1b.o] } {
+    unresolved $test1
+    return
+}
+
+global ld
+global link_output
+
+if { [ld_simple_link $ld tmpdir/common1.o "-r tmpdir/common1a.o tmpdir/common1b.o"] } {
+    unresolved $test1w1
+    return
+}
+
+# This test fails on MIPS because the backend sets type_change_ok.
+# The size change warning is suppressed.
+if {[istarget mips*-*-*]} {
+    if { ![regexp "Warning: alignment (\[0-9\]+) of symbol \`_?foo1\' in tmpdir/common1b.o is smaller than 64 in tmpdir/common1a.o" $link_output] } {
+        fail $test1w1
+    } else {
+        pass $test1w1
+    }
+} else {
+    if { ![regexp "Warning: alignment (\[0-9\]+) of symbol \`_?foo1\' in tmpdir/common1b.o is smaller than 64 in tmpdir/common1a.o" $link_output]
+         || ![regexp "Warning: size of symbol \`_?foo1\' changed from 2 in tmpdir/common1a.o to 21 in tmpdir/common1b.o" $link_output] } {
+        fail $test1w1
+    } else {
+        pass $test1w1
+    }
+}
+
+if { [dump_common1 $test1c1] } {
+    pass $test1c1
+}
+
+if { [ld_simple_link $ld tmpdir/common1.o "-r tmpdir/common1b.o tmpdir/common1a.o"] } {
+    unresolved $test1w2
+    return
+}
+
+if { ![regexp "Warning: alignment (\[0-9\]+) of symbol \`_?foo1\' in tmpdir/common1b.o is smaller than 64 in tmpdir/common1a.o" $link_output] } {
+    fail $test1w2
+} else {
+    pass $test1w2
+}
+
+if { [dump_common1 $test1c2] } {
+    pass $test1c2
+}
+
+#
+# The following tests are for when we are generating STT_COMMON symbols only.
+#
+
+if { ![assembler_generates_commons] } {
+    return
+}
+
+stt_common_test "-static -e 0" "static link of common symbols"
+stt_common_test "-shared"      "shared link of common symbols"
+stt_common_test "-pie"         "position independent link of common symbols"
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfcomm/sort-common.s b/binutils-2.19/ld/testsuite/ld-elfcomm/sort-common.s
new file mode 100644
index 0000000..478d73e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfcomm/sort-common.s
@@ -0,0 +1,6 @@
+        .comm   var_1byte_align,1,1
+        .comm   var_2byte_align,2,2
+        .comm   var_4byte_align,4,4
+        .comm   var_8byte_align,8,8
+        .comm   var_16byte_align,16,16
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers.exp b/binutils-2.19/ld/testsuite/ld-elfvers/vers.exp
new file mode 100644
index 0000000..e2f658d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers.exp
@@ -0,0 +1,999 @@
+# Expect script for ld-version tests
+#   Copyright 1997, 1998, 1999, 2001, 2002, 2003, 2004, 2005, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Eric Youngdale (eric@andante.jic.com)
+
+#
+
+# This test can only be run if ld generates native executables.
+if ![isnative] then {return}
+
+# This test can only be run on a couple of ELF platforms.
+# Square bracket expressions seem to confuse istarget.
+# This is similar to the test that is used in ld-shared, BTW.
+if { ![istarget hppa*64*-*-hpux*] \
+     && ![istarget hppa*-*-linux*] \
+     && ![istarget i?86-*-sysv4*] \
+     && ![istarget i?86-*-unixware] \
+     && ![istarget i?86-*-elf*] \
+     && ![istarget i?86-*-linux*] \
+     && ![istarget ia64-*-elf*] \
+     && ![istarget ia64-*-linux*] \
+     && ![istarget m68k-*-linux*] \
+     && ![istarget mips*-*-irix5*] \
+     && ![istarget powerpc-*-elf*] \
+     && ![istarget powerpc-*-linux*] \
+     && ![istarget powerpc-*-sysv4*] \
+     && ![istarget sparc*-*-elf] \
+     && ![istarget sparc*-*-solaris2*] \
+     && ![istarget sparc*-*-linux*] \
+     && ![istarget arm*-*-linux*] \
+     && ![istarget mips*-*-linux*] \
+     && ![istarget alpha*-*-linux*] \
+     && ![istarget s390*-*-linux*] \
+     && ![istarget sh\[34\]*-*-linux*] \
+     && ![istarget x86_64-*-linux*] } {
+    return
+}
+
+if { [istarget i?86-*-linux*aout*] \
+     || [istarget i?86-*-linux*oldld*] \
+     || [istarget m68k-*-linux*aout*] } {
+    return
+}
+
+if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+    return
+}
+
+set diff diff
+set tmpdir tmpdir
+set VOBJDUMP_FLAGS --private-headers
+set DOBJDUMP_FLAGS --dynamic-syms
+set SOBJDUMP_FLAGS --syms
+set shared "--shared --no-undefined-version"
+set script --version-script
+
+if [istarget mips*-*-*] {
+    set picflag ""
+} else {
+    # Unfortunately, the gcc argument is -fpic and the cc argument is
+    # -KPIC.  We have to try both.
+    set picflag "-fpic"
+    send_log "$CC $picflag\n"
+    verbose "$CC $picflag"
+    catch "exec $CC $picflag" exec_output
+    send_log "$exec_output\n"
+    verbose "--" "$exec_output"
+    if { [string match "*illegal option*" $exec_output] \
+	 || [string match "*option ignored*" $exec_output] \
+	 || [string match "*unrecognized option*" $exec_output] \
+	 || [string match "*passed to ld*" $exec_output] } {
+	if [istarget *-*-sunos4*] {
+	    set picflag "-pic"
+	} else {
+	    set picflag "-KPIC"
+	}
+    }
+}
+
+case $target_triplet in {
+    { ia64-*-* } { set as_options "-x" }
+    default { set as_options "" }
+}
+
+proc test_ar { test lib object expect } {
+    global ar
+    global nm
+    global tmpdir
+    global srcdir
+    global subdir
+    global diff
+
+    verbose -log "$ar -cr $tmpdir/$lib $tmpdir/$object"
+    catch "exec $ar -cr $tmpdir/$lib $tmpdir/$object" exec_output
+    set exec_output [prune_warnings $exec_output]
+    if ![string match "" $exec_output] {
+	verbose -log "$exec_output"
+	unresolved "$test"
+	return
+    }
+    
+    verbose -log "$nm --print-armap $tmpdir/$lib | grep \" in \" | egrep \"VERS\\|bar\\|foo\" | sort > $tmpdir/nm.out"
+
+    catch "exec $nm --print-armap $tmpdir/$lib | grep \\\ in\\\  | egrep VERS\\\|bar\\\|foo | sort > $tmpdir/nm.out" exec_output
+    if [string match "" $exec_output] then {
+	catch "exec sort $srcdir/$subdir/$expect | $diff $tmpdir/nm.out -" exec_output
+	set exec_output [prune_warnings $exec_output]
+	if [string match "" $exec_output] then {
+	    pass $test
+	    return
+	} else {
+	    verbose -log "$exec_output"
+	    fail "$test"
+	    return
+	}
+    } else {
+	verbose -log "$exec_output"
+	fail "$test"
+    }
+}
+
+#
+# objdump_emptysymstuff
+#	Check non-dynamic symbols and make sure there are none with '@'.
+#
+proc objdump_emptysymstuff { objdump object } {
+    global SOBJDUMP_FLAGS
+    global version_output
+    global diff
+
+    if ![info exists SOBJDUMP_FLAGS] { set SOBJDUMP_FLAGS "" }
+
+    verbose -log "$objdump $SOBJDUMP_FLAGS $object | sed -n /\@/p"
+
+    catch "exec $objdump $SOBJDUMP_FLAGS $object | sed -n /\@/p" exec_output
+    set exec_output [prune_warnings $exec_output]
+    if [string match "" $exec_output] then {
+# We shouldn't get anything here.
+	return 1
+    } else {
+# it is not normal to come here - we have no output to compare.
+	verbose -log "$exec_output"
+	verbose -log "objdump_emptysymstuff: did not expect any output from objdump"
+	return 0
+    }
+
+}
+
+#
+# objdump_emptydynsymstuff
+#	Check dynamic symbols and make sure there are none with '@'.
+#
+proc objdump_emptydynsymstuff { objdump object } {
+    global DOBJDUMP_FLAGS
+    global version_output
+    global diff
+
+    if ![info exists VOBJDUMP_FLAGS] { set VOBJDUMP_FLAGS "" }
+
+    verbose -log "$objdump $DOBJDUMP_FLAGS $object | sed -n /VERS/p\\\;/show/p"
+
+    catch "exec $objdump $DOBJDUMP_FLAGS $object | sed -n /VERS/p\\\;/show/p" exec_output
+    set exec_output [prune_warnings $exec_output]
+    if [string match "" $exec_output] then {
+# We shouldn't get anything here.
+	return 1
+    } else { if [string match "*objdump: *: not a dynamic object" $exec_output] then {
+	return 1
+    } else {
+# it is not normal to come here - we have no output to compare.
+	verbose -log "$exec_output"
+	verbose -log "objdump_emptydynsymstuff: did not expect any output from objdump"
+	return 0
+    } }
+}
+
+#
+# objdump_emptyverstuff
+#	Make sure there is no version information
+#
+proc objdump_emptyverstuff { objdump object } {
+    global VOBJDUMP_FLAGS
+    global version_output
+    global diff
+    global tmpdir
+
+    if {[which $objdump] == 0} then {
+	perror "$objdump does not exist"
+	return 0
+    }
+
+    if ![info exists VOBJDUMP_FLAGS] { set VOBJDUMP_FLAGS "" }
+
+    verbose -log "$objdump $VOBJDUMP_FLAGS $object | sed -n /Version/,\\\$p > $tmpdir/objdump.out"
+
+    catch "exec $objdump $VOBJDUMP_FLAGS $object | sed -n /Version/,\\\$p" exec_output
+    set exec_output [prune_warnings $exec_output]
+    if [string match "" $exec_output] then {
+# it is normal to fail here - we have no output to compare.
+	return 1
+    } else { if { [string match "*libc*" $exec_output] } then {
+# this probably means that there is version information in libc, so we
+# can't really perform this test.
+	return 1
+    } else {
+	verbose -log "$exec_output"
+	verbose -log "objdump_emptyverstuff: did not expect any output from objdump"
+	return 0
+    } }
+
+}
+
+#
+# objdump_symstuff
+#	Dump non-dynamic symbol stuff and make sure that it is sane.
+#
+proc objdump_symstuff { objdump object expectfile } {
+    global SOBJDUMP_FLAGS
+    global version_output
+    global diff
+    global tmpdir
+
+    if ![info exists SOBJDUMP_FLAGS] { set SOBJDUMP_FLAGS "" }
+
+    verbose -log "$objdump $SOBJDUMP_FLAGS $object | grep \@ | sort  > $tmpdir/objdump.out"
+
+    catch "exec $objdump $SOBJDUMP_FLAGS $object | grep \@ | sort  > $tmpdir/objdump.out" exec_output
+    set exec_output [prune_warnings $exec_output]
+    if [string match "" $exec_output] then {
+
+# Now do a line-by-line comparison to effectively diff the darned things
+# The stuff coming from the expectfile is actually a regex, so we can
+# skip over the actual addresses and so forth.  This is currently very
+# simpleminded - it expects a one-to-one correspondence in terms of line
+# numbers.
+
+	if [file exists $expectfile] then {
+	    set file_a [open $expectfile r]
+	} else {
+	    perror "$expectfile doesn't exist"
+	    return 0
+	}
+	
+	if [file exists $tmpdir/objdump.out] then {
+	    set file_b [open $tmpdir/objdump.out r]
+	} else {
+	    perror "$tmpdir/objdump.out doesn't exist"
+	    return 0
+	}
+
+	verbose "# Diff'ing: $expectfile $tmpdir/objdump.out" 2
+
+	set eof -1
+	set differences 0
+
+	while { [gets $file_a line] != $eof } {
+	    if [regexp "^#.*$" $line] then {
+		continue
+	    } else {
+		lappend list_a $line
+	    }
+	}
+	close $file_a
+
+	while { [gets $file_b line] != $eof } {
+	    if [regexp "^#.*$" $line] then {
+		continue
+	    } else {
+		lappend list_b $line
+	    }
+	}
+	close $file_b
+	
+	for { set i 0 } { $i < [llength $list_a] } { incr i } {
+	    set line_a [lindex $list_a $i]
+	    set line_b [lindex $list_b $i]
+	    
+
+	    verbose "\t$expectfile: $i: $line_a" 3
+	    verbose "\t/tmp/objdump.out: $i: $line_b" 3
+	    if [regexp $line_a $line_b] then {
+		continue
+	    } else {
+		verbose -log "\t$expectfile: $i: $line_a"
+		verbose -log "\t$tmpdir/objdump.out: $i: $line_b"
+		
+		return 0
+	    }
+	}
+	
+	if { [llength $list_a] != [llength $list_b] } {
+	    verbose -log "Line count"
+	    return 0
+	}
+	
+	if $differences<1 then {
+	    return 1
+	}
+	
+	return 0
+    } else {
+	verbose -log "$exec_output"
+	return 0
+    }
+
+}
+
+#
+# objdump_dymsymstuff
+#	Dump dynamic symbol stuff and make sure that it is sane.
+#
+proc objdump_dynsymstuff { objdump object expectfile } {
+    global DOBJDUMP_FLAGS
+    global version_output
+    global diff
+    global tmpdir
+
+    if ![info exists DOBJDUMP_FLAGS] { set DOBJDUMP_FLAGS "" }
+
+    verbose -log "$objdump $DOBJDUMP_FLAGS $object | sed -n /VERS/p\\\;/show/p | sort | uniq  > $tmpdir/objdump.out"
+
+    catch "exec $objdump $DOBJDUMP_FLAGS $object | sed -n /VERS/p\\\;/show/p | sort | uniq  > $tmpdir/objdump.out" exec_output
+    set exec_output [prune_warnings $exec_output]
+    if [string match "" $exec_output] then {
+
+# Now do a line-by-line comparison to effectively diff the darned things
+# The stuff coming from the expectfile is actually a regex, so we can
+# skip over the actual addresses and so forth.  This is currently very
+# simpleminded - it expects a one-to-one correspondence in terms of line
+# numbers.
+
+	if [file exists $expectfile] then {
+	    set file_a [open $expectfile r]
+	} else {
+	    warning "$expectfile doesn't exist"
+	    return 0
+	}
+	
+	if [file exists $tmpdir/objdump.out] then {
+	    set file_b [open $tmpdir/objdump.out r]
+	} else {
+	    fail "$tmpdir/objdump.out doesn't exist"
+	    return 0
+	}
+
+	verbose "# Diff'ing: $expectfile $tmpdir/objdump.out" 2
+
+	set eof -1
+	set differences 0
+
+	while { [gets $file_a line] != $eof } {
+	    if [regexp "^#.*$" $line] then {
+		continue
+	    } else {
+		lappend list_a $line
+	    }
+	}
+	close $file_a
+
+	while { [gets $file_b line] != $eof } {
+	    if [regexp "^#.*$" $line] then {
+		continue
+	    } else {
+		lappend list_b $line
+	    }
+	}
+	close $file_b
+	
+	# Support empty files.
+	if { ![info exists list_a] && ![info exists list_b] } then {
+	    return 1
+	}
+
+	for { set i 0 } { $i < [llength $list_b] } { incr i } {
+	    set line_b [lindex $list_b $i]
+	    
+# The tests are rigged so that we should never export a symbol with the
+# word 'hide' in it.  Thus we just search for it, and bail if we find it.
+	    if [regexp "hide" $line_b] then {
+		verbose -log "\t$tmpdir/objdump.out: $i: $line_b"
+		
+		return 0
+	    }
+
+	    verbose "\t$expectfile: $i: $line_b" 3
+
+	    # We can't assume that the sort is consistent across
+	    # systems, so we must check each regexp.  When we find a
+	    # regexp, we null it out, so we don't match it twice.
+	    for { set j 0 } { $j < [llength $list_a] } { incr j } {
+		set line_a [lindex $list_a $j]
+
+		if [regexp $line_a $line_b] then {
+		    lreplace $list_a $j $j "CAN NOT MATCH"
+		    break
+		}
+	    }
+
+	    if { $j >= [llength $list_a] } {
+		verbose -log "\t$tmpdir/objdump.out: $i: $line_b"
+		
+		return 0
+	    }
+	}
+	
+	if { [llength $list_a] != [llength $list_b] } {
+	    verbose -log "Line count"
+	    return 0
+	}
+	
+	if $differences<1 then {
+	    return 1
+	}
+	
+	return 0
+    } else {
+	verbose -log "$exec_output"
+	return 0
+    }
+
+}
+
+#
+# objdump_versionstuff
+#	Dump version definitions/references and make sure that it is sane.
+#
+proc objdump_versionstuff { objdump object expectfile } {
+    global VOBJDUMP_FLAGS
+    global version_output
+    global diff
+    global tmpdir
+
+    if {[which $objdump] == 0} then {
+	perror "$objdump does not exist"
+	return 0
+    }
+
+    if ![info exists VOBJDUMP_FLAGS] { set VOBJDUMP_FLAGS "" }
+
+    verbose -log "$objdump $VOBJDUMP_FLAGS $object | sed -n /Version/,\\\$p > $tmpdir/objdump.out"
+
+    catch "exec $objdump $VOBJDUMP_FLAGS $object | sed -n /Version/,\\\$p > $tmpdir/objdump.out" exec_output
+    set exec_output [prune_warnings $exec_output]
+    if [string match "" $exec_output] then {
+
+	# It's OK if there are extra lines in the actual output; they
+	# may come from version information in libc.  We require that
+	# every line in EXPECTFILE appear in the output in any order.
+
+	set f2 [open $expectfile r]
+	while { [gets $f2 l2] != -1 } {
+	    if { ![regexp "^#.*$" $l2] } then {
+		set f1 [open $tmpdir/objdump.out r]
+		while { [gets $f1 l1] != -1 } {
+		    if { [string match $l2 $l1] } then {
+			break
+		    }
+		}
+		close $f1
+
+		if { ![string match $l2 $l1] } then {
+		    verbose -log "Did not find \"$l2\""
+		    set f1 [open $tmpdir/objdump.out r]
+		    while { [gets $f1 l1] != -1 } {
+			verbose -log $l1
+		    }
+		    close $f1
+		    close $f2
+		    return 0
+		}
+	    }
+	}
+	close $f2
+	return 1
+    } else {
+	verbose -log "$exec_output"
+	return 0
+    }
+}
+
+proc build_binary { shared pic test source libname other mapfile verexp versymexp symexp ldargs } {
+    global ld
+    global srcdir
+    global subdir
+    global exec_output
+    global host_triplet
+    global tmpdir
+    global as
+    global as_options
+    global objdump
+    global CC
+    global CFLAGS
+    global script
+
+    if ![ld_compile "$CC -S $pic $CFLAGS" $srcdir/$subdir/$source $tmpdir/$libname.s]     {
+	unresolved "$test"
+	return
+    }
+
+    if ![ld_assemble $as "$as_options $tmpdir/$libname.s" $tmpdir/$libname.o ]     {
+	unresolved "$test"
+	return
+    }
+
+    set other_lib ""
+    if ![string match "" $other] then {
+	foreach o $other {
+	    set other_lib "$other_lib $tmpdir/$o"
+	}
+    }
+
+    if [string match "" $mapfile] then {
+	set script_arg ""
+    } else {
+	set script_arg "$script $srcdir/$subdir/$mapfile"
+    }
+
+    if {![ld_simple_link $ld $tmpdir/$libname.so "$shared $tmpdir/$libname.o $other_lib $script_arg $ldargs"]}     {
+	fail "$test"
+	return
+    }
+
+    if {![objdump_versionstuff $objdump $tmpdir/$libname.so $srcdir/$subdir/$verexp ]}     {
+	fail "$test"
+	return
+    }
+
+    if {![objdump_dynsymstuff $objdump $tmpdir/$libname.so $srcdir/$subdir/$versymexp ]}     {
+	fail "$test"
+	return
+    }
+
+    if [string match "" $symexp] then {
+	if {![objdump_emptysymstuff $objdump $tmpdir/$libname.o ]}     {
+	    fail "$test"
+	    return
+	}
+    } else {
+	if {![objdump_symstuff $objdump $tmpdir/$libname.o $srcdir/$subdir/$symexp ]}     {
+	    fail "$test"
+	    return
+	}
+    }
+
+    pass $test
+    
+}
+
+proc build_executable { test source libname other mapfile verexp versymexp symexp } {
+  build_binary "" "" $test $source $libname $other $mapfile $verexp $versymexp $symexp ""
+}
+
+proc build_vers_lib_no_pic { test source libname other mapfile verexp versymexp symexp } {
+  global shared
+  build_binary $shared "" $test $source $libname $other $mapfile $verexp $versymexp $symexp ""
+}
+
+proc build_vers_lib_pic { test source libname other mapfile verexp versymexp symexp } {
+  global picflag
+  global shared
+  build_binary $shared $picflag $test $source $libname $other $mapfile $verexp $versymexp $symexp ""
+}
+
+proc build_vers_lib_pic_flags { test source libname other mapfile verexp versymexp symexp ldargs } {
+  global picflag
+  global shared
+  build_binary $shared $picflag $test $source $libname $other $mapfile $verexp $versymexp $symexp $ldargs
+}
+
+proc test_ldfail { test flag source execname other mapfile whyfail } {
+    global srcdir
+    global subdir
+    global exec_output
+    global host_triplet
+    global tmpdir
+    global as
+    global as_options
+    global objdump
+    global CC
+    global CFLAGS
+    global script
+
+    if [string match "" $other] then {
+	set other_lib ""
+    } else {
+	set other_lib $tmpdir/$other
+    }
+
+    if ![ld_compile "$CC -S $flag $CFLAGS" $srcdir/$subdir/$source $tmpdir/$execname.s]     {
+	unresolved "$test"
+	return
+    }
+
+    if ![ld_assemble $as "$as_options $tmpdir/$execname.s" $tmpdir/$execname.o ]     {
+	unresolved "$test"
+	return
+    }
+
+    verbose -log "This link should fail because of $whyfail"
+
+    if [string match "" $mapfile] then {
+	set script_arg ""
+    } else {
+	set script_arg "-Wl,$script $srcdir/$subdir/$mapfile"
+    }
+
+    if {![ld_simple_link $CC $tmpdir/$execname "$tmpdir/$execname.o $other_lib $script_arg"]}     {
+	pass "$test"
+	return
+    }
+    fail "$test"
+}
+
+proc test_asfail { test flag source execname whyfail } {
+    global srcdir
+    global subdir
+    global tmpdir
+    global as
+    global CC
+    global CFLAGS
+
+    if ![ld_compile "$CC -S $flag $CFLAGS" $srcdir/$subdir/$source $tmpdir/$execname.s]     {
+	unresolved "$test"
+	return
+    }
+
+    verbose -log "This assemble should fail because of $whyfail"
+    catch "exec $as -o $tmpdir/$execname.o $tmpdir/$execname.s" exec_output
+    set exec_output [prune_warnings $exec_output]
+    if [string match "" $exec_output] then {
+	fail "$test"
+	return
+    }
+    verbose -log "$exec_output"
+    pass "$test"
+}
+
+proc test_strip_vers_lib { test srclib libname verexp versymexp } {
+    global strip
+    global srcdir
+    global subdir
+    global exec_output
+    global host_triplet
+    global tmpdir
+    global objdump
+
+    verbose -log "cp $tmpdir/$srclib $tmpdir/$libname.so"
+    exec cp $tmpdir/$srclib $tmpdir/$libname.so
+
+    verbose -log "$strip $tmpdir/$libname.so"
+    catch "exec $strip $tmpdir/$libname.so" exec_output
+    if [string match "" $exec_output] then {
+
+# If strip went OK, then run the usual tests on the thing to make sure that
+# it is sane.
+	if {![objdump_versionstuff $objdump $tmpdir/$libname.so $srcdir/$subdir/$verexp ]}     {
+	    fail "$test"
+	    return
+	}
+	
+	if {![objdump_dynsymstuff $objdump $tmpdir/$libname.so $srcdir/$subdir/$versymexp ]}     {
+	    fail "$test"
+	    return
+	}
+	
+    } else {
+	verbose -log "$exec_output"
+	fail "$test"
+	return
+    }
+    pass $test
+}
+
+
+proc build_exec { test source execname flags solibname verexp versymexp symexp } {
+    global srcdir
+    global subdir
+    global exec_output
+    global host_triplet
+    global tmpdir
+    global as
+    global as_options
+    global objdump
+    global CC
+    global CFLAGS
+
+    set shared "--shared --no-undefined-version"
+    set script --version-script
+    if ![ld_compile "$CC -S $CFLAGS" $srcdir/$subdir/$source $tmpdir/$execname.s]     {
+	unresolved "$test"
+	return
+    }
+
+    if ![ld_assemble $as "$as_options $tmpdir/$execname.s" $tmpdir/$execname.o ]     {
+	unresolved "$test"
+	return
+    }
+
+    if [string match "" $solibname] then {
+	set solibname_lib ""
+    } else {
+	set solibname_lib $tmpdir/$solibname
+    }
+
+    if {![ld_simple_link $CC $tmpdir/$execname "$flags $tmpdir/$execname.o $solibname_lib"]}     {
+	fail "$test"
+	return
+    }
+
+    if [string match "" $verexp] then {
+#
+# Make sure we get nothing back.
+#
+	if {![objdump_emptyverstuff $objdump $tmpdir/$execname ]}     {
+	    fail "$test"
+	    return
+	}
+    } else {
+	if {![objdump_versionstuff $objdump $tmpdir/$execname $srcdir/$subdir/$verexp ]}     {
+	    fail "$test"
+	    return
+	}
+    }
+
+    if [string match "" $versymexp] then {
+	if {![objdump_emptydynsymstuff $objdump $tmpdir/$execname ]}     {
+	    fail "$test"
+	    return
+	}
+    } else {
+	if {![objdump_dynsymstuff $objdump $tmpdir/$execname $srcdir/$subdir/$versymexp ]}     {
+	    fail "$test"
+	    return
+	}
+    }
+
+    if [string match "" $symexp] then {
+	if {![objdump_emptysymstuff $objdump $tmpdir/$execname.o ]}     {
+	    fail "$test"
+	    return
+	}
+    } else {
+	if {![objdump_symstuff $objdump $tmpdir/$execname.o $srcdir/$subdir/$symexp ]}     {
+	    fail "$test"
+	    return
+	}
+    }
+
+    pass $test
+}
+
+if [istarget x86_64-*-linux*] {
+    # x86_64 doesn't like non-pic shared libraries
+    set pic "yes"
+} else {
+    set pic "no"
+}
+
+#
+# Basic test - build a library with versioned symbols.
+#
+build_vers_lib_pic "vers1" vers1.c vers1 "" vers1.map vers1.ver vers1.dsym vers1.sym
+
+
+#
+# Test #2 - build a library, and link it against the library we built in step
+# 1.
+#
+build_vers_lib_pic "vers2" vers2.c vers2 vers1.so vers2.map vers2.ver vers2.dsym ""
+
+#
+# Test #3 - build an executable, and link it against vers1.so.
+#
+build_exec "vers3" vers3.c vers3 "" vers1.so vers3.ver vers3.dsym ""
+
+#
+# Test #4 - Make sure a version implicitly defined in an executable
+# causes a version node to be created.  Verify this both with and without
+# --export-dynamic.
+#
+
+# This test fails on MIPS.  On the MIPS we must put foo in the dynamic
+# symbol table, which the test does not expect.
+setup_xfail "mips*-*-*"
+build_exec "vers4" vers4.c vers4 "" "" "" "" vers4.sym
+
+build_exec "vers4a" vers4.c vers4a "-export-dynamic" "" vers4a.ver vers4a.dsym vers4a.sym
+
+
+#
+# Try multiple definitions foo@BAR and foo@@BAR and make sure the linker
+# complains.
+#
+test_ldfail "vers5" "" vers5.c vers5 "" "" "multiple definition of foo@VERS_1.2"
+
+#
+#
+# Now build a test that should reference a bunch of versioned symbols.
+# All of them should be correctly referenced.
+#
+build_exec "vers6" vers6.c vers6 "" vers1.so vers6.ver vers6.dsym vers6.sym
+
+#
+# Another test to verify that something made local via 'local' is truly not
+# accessible.
+#
+if [string match "yes" $pic] then {
+    xfail "vers7a"
+    xfail "vers7"
+} else {
+    build_vers_lib_no_pic "vers7a" vers7a.c vers7a "" vers7.map vers7a.ver vers7a.dsym vers7a.sym
+
+    test_ldfail "vers7" "" vers7.c vers7 vers7a.so "" "undefined reference to hide_a"
+}
+
+
+#
+# This test is designed to verify that we can pass a linker script on the
+# command line as if it were a normal .o file.
+#
+catch "exec cp $srcdir/$subdir/vers8.map $tmpdir/" ignore_output
+build_vers_lib_pic "vers8" vers1.c vers8 vers8.map "" vers8.ver vers1.dsym vers1.sym
+
+#
+# This test tries to make sure that version references to versioned symbols
+# don't collide with default definitions with the same symbol.
+#
+build_exec "vers9" vers9.c vers9 "-export-dynamic" "" vers9.ver vers9.dsym vers9.sym
+
+
+#
+# Try and use a non-existant version node.  The linker should fail with
+# an error message.
+#
+test_ldfail "vers10" "-DDO_TEST10" vers1.c vers10 "" "vers1.map --shared" "invalid version"
+
+#
+# Try and some things the assembler should complain about.
+#
+test_asfail "vers11" "-DDO_TEST11" vers1.c vers11 "no @ in symver"
+
+test_asfail "vers12" "-DDO_TEST12" vers1.c vers12 "extern version definition"
+
+#
+# Put a shared library in an archive library, and make sure the global
+# archive symbol table is sane.
+#
+test_ar "ar with versioned solib" vers13.a vers1.so vers13.asym
+
+#
+# Strip a shared library, and make sure we didn't screw something up in there.
+#
+test_strip_vers_lib "vers14" vers1.so vers14 vers1.ver vers1.dsym 
+
+
+#
+# Build another test with some versioned symbols.  Here we are going to 
+# try and override something from the library, and we shouldn't get
+# any errors.
+#
+build_exec "vers15" vers15.c vers15 "" vers1.so vers15.ver vers15.dsym vers15.sym
+
+#
+# Test that when we override a versioned symbol from the library this
+# symbol appears in the dynamic symbol table of the executable.
+#
+build_vers_lib_pic "vers16a" vers16a.c vers16a "" vers16.map vers16a.ver vers16a.dsym ""
+build_exec "vers16" vers16.c vers16 "" vers16a.so "" vers16.dsym ""
+
+# Test a weak versioned symbol.
+build_vers_lib_pic "vers17" vers17.c vers17 "" vers17.map vers17.ver vers17.dsym ""
+build_vers_lib_pic "vers18" vers18.c vers18 vers17.so vers18.map vers18.ver vers18.dsym vers18.sym
+build_exec "vers19" vers19.c vers19 "-Wl,-rpath,." vers18.so vers19.ver vers19.dsym ""
+
+build_vers_lib_no_pic "vers20a" vers20.c vers20a "" vers20.map vers20a.ver vers20.dsym ""
+exec cp $tmpdir/vers20a.so $tmpdir/vers20b.so
+build_vers_lib_no_pic "vers20" vers20.c vers20 "vers20a.so vers20b.so" vers20.map vers20.ver vers20.dsym ""
+
+# Test .symver override.
+build_vers_lib_pic "vers21" vers21.c vers21 "" vers21.map vers21.ver vers21.dsym vers21.sym
+
+# Test moving default definition from one DSO to another.
+build_vers_lib_pic "vers22a" vers22a.c vers22a "" vers22.map vers22a.ver vers22a.dsym vers22a.sym
+build_vers_lib_pic "vers22b" vers22b.c vers22b "" vers22.map vers22b.ver vers22b.dsym ""
+build_vers_lib_pic "vers22" vers22.c vers22 "vers22a.so vers22b.so" "" vers22.ver vers22.dsym ""
+
+# Test versioned definitions in different files.
+if [string match "yes" $pic] then {
+    xfail "vers23a" 
+    xfail "vers23b"
+    xfail "vers23c"
+    xfail "vers23d"
+    xfail "vers23"
+} else {
+    build_vers_lib_no_pic "vers23a" vers23a.c vers23a "" vers23a.map vers23a.ver vers23a.dsym vers23a.sym
+    build_vers_lib_no_pic "vers23b" vers23b.c vers23b "" vers23b.map vers23b.ver vers23b.dsym ""
+    build_vers_lib_no_pic "vers23c" vers23b.c vers23c "vers23a.so" vers23b.map vers23c.ver vers23b.dsym ""
+    build_exec "vers23d" vers23.c vers23d "tmpdir/vers23a.so tmpdir/vers23c.so" "" vers23.ver vers23d.dsym ""
+    build_exec "vers23" vers23.c vers23 "tmpdir/vers23a.so tmpdir/vers23b.o tmpdir/vers23b.so" "" vers23.ver vers23.dsym ""
+}
+
+# Test .symver x,x@VERS.0
+set as_pic_flags ""
+if [istarget sparc*-*-*] {
+  set as_pic_flags "-K PIC"
+}
+run_ld_link_tests [list "\"vers24a\"
+			 \"-shared --version-script $srcdir/$subdir/vers24.map\"
+			 \"$as_pic_flags $as_options\" {vers24a.c vers24b.c} { { readelf -Wrs vers24.rd } }
+			 \"libvers24a.so\" \"-fpic\""]
+run_ld_link_tests [list "\"vers24b\"
+			 \"-shared --version-script $srcdir/$subdir/vers24.map\"
+			 \"$as_pic_flags $as_options\" {vers24b.c vers24a.c} { { readelf -Wrs vers24.rd } }
+			 \"libvers24b.so\" \"-fpic\""]
+run_ld_link_tests [list "\"vers24c\"
+			 \"-shared --version-script $srcdir/$subdir/vers24.map\"
+			 \"$as_pic_flags $as_options\" {vers24c.c} { { readelf -Wrs vers24.rd } }
+			 \"libvers24c.so\" \"-fpic\""]
+
+# Test versioned definition vs. normal definition in different files.
+if [string match "yes" $pic] then {
+    xfail "vers25a"
+    xfail "vers25b1"
+    xfail "vers25b2"
+} else {
+    build_vers_lib_no_pic "vers25a" vers25a.c vers25a "" vers25a.map vers25a.ver vers25a.dsym ""
+    build_vers_lib_no_pic "vers25b1" vers25b.c vers25b1 "vers25a.o vers25a.so" "" vers25b.ver vers25b.dsym ""
+    build_vers_lib_no_pic "vers25b2" vers25b.c vers25b2 "vers25a.so vers25a.o" "" vers25b.ver vers25b.dsym ""
+}
+
+build_vers_lib_pic "vers26a" vers26a.c vers26a "" vers26a.map vers26a.ver vers26a.dsym ""
+build_vers_lib_pic "vers26b1" vers26b.c vers26b1 "" "" vers26b.ver vers26b.dsym ""
+build_vers_lib_pic "vers26b2" vers26b.c vers26b2 "vers26a.so vers26b1.so vers26a.o" "" vers26b.ver vers26b.dsym ""
+if [string match "yes" $pic] then {
+    xfail "vers26b3"
+} else {
+    build_vers_lib_no_pic "vers26b3" vers26b.c vers26b3 "vers26a.so vers26b1.so vers26a.o" "" vers26b.ver vers26b.dsym ""
+}
+
+# Test versioned definition vs. hidden definition in different files.
+if [string match "yes" $pic] then {
+    xfail "vers27a"
+    xfail "vers27b"
+    xfail "vers27c1"
+    xfail "vers27c2"
+    xfail "vers27d1"
+    xfail "vers27d2"
+    xfail "vers27d3"
+    xfail "vers27d4"
+    xfail "vers27d5"
+} else {
+    build_vers_lib_no_pic "vers27a" vers27a.c vers27a "" vers27a.map vers27a.ver vers27a.dsym ""
+    build_vers_lib_no_pic "vers27b" vers27b.c vers27b "" "" vers27b.ver vers27b.dsym ""
+    build_vers_lib_no_pic "vers27c1" vers27c.c vers27c1 "vers27b.o vers27a.so" "" vers27c.ver vers27c.dsym ""
+    build_vers_lib_no_pic "vers27c2" vers27c.c vers27c2 "vers27a.so vers27b.o" "" vers27c.ver vers27c.dsym ""
+    build_vers_lib_pic "vers27d1" vers27d1.c vers27d1 "" vers27a.map vers27d.ver vers27d.dsym vers27d.sym
+   build_vers_lib_pic "vers27d2" vers27d2.c vers27d2 "" "" vers27b.ver vers27b.dsym ""
+    build_executable "vers27d3" vers27d3.c vers27d3 "vers27b.o vers27d2.so vers27d1.so" "" vers27b.ver vers27b.dsym ""
+    build_vers_lib_pic "vers27d4" vers27d2.c vers27d4 "vers27a.so" "" vers27d4.ver vers27d4.dsym ""
+    build_executable "vers27d5" vers27d3.c vers27d5 "vers27d4.so vers27b.o vers27a.so" "" vers27b.ver vers27b.dsym ""
+}
+
+# Test weak versioned definition vs. strong definition in different
+# files.
+build_vers_lib_pic "vers28a" vers28a.c vers28a "" "" vers28a.ver vers28a.dsym ""
+build_vers_lib_pic "vers28b" vers28b.c vers28b "" vers28b.map vers28b.ver vers28b.dsym ""
+build_vers_lib_pic "vers28c" vers28c.c vers28c "vers28b.so vers28a.so" "" vers28c.ver vers28c.dsym ""
+build_vers_lib_pic_flags "vers29" vers29.c vers29 "" "" vers29.ver vers29.dsym "" "--default-symver"
+
+# Test #30 - test handling of symbol names global, local and extern in the
+# version script.
+build_vers_lib_pic "vers30" vers30.c vers30 "" vers30.map vers30.ver vers30.dsym ""
+
+# Test #31 -- quoted strings in version sections.
+build_vers_lib_pic "vers31" vers31.c vers31 "" vers31.map vers31.ver vers31.dsym ""
+
+# Test #32 -- linker --defsym
+build_vers_lib_pic "vers32a" vers32a.c vers32a "" vers32.map vers32a.ver vers32a.dsym ""
+build_vers_lib_pic_flags "vers32b" vers32b.c vers32b "vers32a.so" vers32.map vers32b.ver vers32b.dsym "" "--defsym foo=0"
+build_vers_lib_pic_flags "vers32c" vers32a.c vers32c "vers32a.so" vers32.map vers32c.ver vers32c.dsym "" "--defsym foo=0"
+build_vers_lib_pic_flags "vers32d" vers32a.c vers32d "" vers32.map vers32d.ver vers32c.dsym "" "--defsym foo=0"
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers1.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers1.c
new file mode 100644
index 0000000..c27bc3b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers1.c
@@ -0,0 +1,101 @@
+/*
+ * Basic test of versioning.  The idea with this is that we define
+ * a bunch of definitions of the same symbol, and we can theoretically
+ * then link applications against varying sets of these.
+ */
+const char * show_bar1 = "asdf";
+const char * show_bar2 = "asdf";
+
+extern int new2_foo();
+extern int bar33();
+
+int
+bar()
+{
+	return 3;
+}
+
+/*
+ * The 'hide' prefix is something so that we can automatically search the
+ * symbol table and verify that none of these symbols were actually exported.
+ */
+int
+hide_original_foo()
+{
+	return 1+bar();
+
+}
+
+int
+hide_old_foo()
+{
+	return 10+bar();
+
+}
+
+int
+hide_old_foo1()
+{
+	return 100+bar();
+
+}
+
+int
+hide_new_foo()
+{
+	return 1000+bar();
+
+}
+
+__asm__(".symver hide_original_foo,show_foo@");
+__asm__(".symver hide_old_foo,show_foo@VERS_1.1");
+__asm__(".symver hide_old_foo1,show_foo@VERS_1.2");
+__asm__(".symver hide_new_foo,show_foo@@VERS_2.0");
+
+
+
+#ifdef DO_TEST10
+/* In test 10, we try and define a non-existant version node.  The linker
+ * should catch this and complain. */
+int
+hide_new_bogus_foo()
+{
+	return 1000+bar();
+
+}
+__asm__(".symver hide_new_bogus_foo,show_foo@VERS_2.2");
+#endif
+
+
+
+
+#ifdef DO_TEST11
+/*
+ * This test is designed to catch a couple of syntactic errors.  The assembler
+ * should complain about both of the directives below.
+ */
+void
+xyzzz()
+{
+  new2_foo();
+  bar33();
+}
+
+__asm__(".symver new2_foo,fooVERS_2.0");
+__asm__(".symver bar33,bar@@VERS_2.0");
+#endif
+
+#ifdef DO_TEST12
+/*
+ * This test is designed to catch a couple of syntactic errors.  The assembler
+ * should complain about both of the directives below.
+ */
+void
+xyzzz()
+{
+  new2_foo();
+  bar33();
+}
+
+__asm__(".symver bar33,bar@@VERS_2.0");
+#endif
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers1.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers1.dsym
new file mode 100644
index 0000000..834434b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers1.dsym
@@ -0,0 +1,9 @@
+[0]* g    DO \*ABS\*	[0]*  VERS_1.1    VERS_1.1
+[0]* g    DO \*ABS\*	[0]*  VERS_1.2    VERS_1.2
+[0]* g    DO \*ABS\*	[0]*  VERS_2.0    VERS_2.0
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]* \(Base\)       (0x[0-9a-f][0-9a-f] )?show_foo
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]* \(VERS_1.1\)   (0x[0-9a-f][0-9a-f] )?show_foo
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]* \(VERS_1.2\)   (0x[0-9a-f][0-9a-f] )?show_foo
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]*  VERS_2.0    (0x[0-9a-f][0-9a-f] )?show_foo
+[0-9a-f]* g    DO (.s?data|\*ABS\*)	[0-9a-f]*  VERS_2.0    show_bar1
+[0-9a-f]* g    DO (.s?data|\*ABS\*)	[0-9a-f]*  VERS_2.0    show_bar2
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers1.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers1.map
new file mode 100644
index 0000000..767915c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers1.map
@@ -0,0 +1,13 @@
+VERS_1.1 {
+	 local:
+		 hide_old*; 
+		 hide_original*; 
+		 hide_new*; 
+};
+
+VERS_1.2 {
+} VERS_1.1;
+
+VERS_2.0 {
+		 show_bar1; show_bar2;
+} VERS_1.2;
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers1.sym b/binutils-2.19/ld/testsuite/ld-elfvers/vers1.sym
new file mode 100644
index 0000000..70ff855
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers1.sym
@@ -0,0 +1,4 @@
+[0-9a-f]* g     F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?show_foo@
+[0-9a-f]* g     F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?show_foo@VERS_1.1
+[0-9a-f]* g     F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?show_foo@VERS_1.2
+[0-9a-f]* g     F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?show_foo@@VERS_2.0
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers1.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers1.ver
new file mode 100644
index 0000000..a42b970
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers1.ver
@@ -0,0 +1,8 @@
+Version definitions:
+[1-4] 0x01 0x0c96425f vers1.so
+[1-4] 0x00 0x0a7927b1 VERS_1.1
+[1-4] 0x00 0x0a7927b2 VERS_1.2
+	VERS_1.1 
+[1-4] 0x00 0x0a7922b0 VERS_2.0
+	VERS_1.2 
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers13.asym b/binutils-2.19/ld/testsuite/ld-elfvers/vers13.asym
new file mode 100644
index 0000000..d446144
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers13.asym
@@ -0,0 +1,10 @@
+VERS_1.1 in vers1.so
+VERS_1.2 in vers1.so
+VERS_2.0 in vers1.so
+bar in vers1.so
+show_bar1 in vers1.so
+show_bar2 in vers1.so
+show_foo@ in vers1.so
+show_foo@@VERS_2.0 in vers1.so
+show_foo@VERS_1.1 in vers1.so
+show_foo@VERS_1.2 in vers1.so
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers15.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers15.c
new file mode 100644
index 0000000..4e22cac
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers15.c
@@ -0,0 +1,36 @@
+/*
+ * Testcase to make sure that if we externally reference a versioned symbol
+ * that we always get the right one.
+ */
+#include <stdio.h>
+
+int
+foo_1()
+{
+  return 1034;
+}
+
+int
+foo_2()
+{
+  return 1343;
+}
+
+int
+foo_3()
+{
+  return 1334;
+}
+
+int
+main()
+{
+  printf("Expect 4,    get %d\n", foo_1());
+  printf("Expect 13,   get %d\n", foo_2());
+  printf("Expect 103,  get %d\n", foo_3());
+  return 0;
+}
+
+__asm__(".symver foo_1,show_foo@");
+__asm__(".symver foo_2,show_foo@VERS_1.1");
+__asm__(".symver foo_3,show_foo@@VERS_1.2");
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers15.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers15.dsym
new file mode 100644
index 0000000..1f5e15c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers15.dsym
@@ -0,0 +1,5 @@
+[0]* g    DO \*ABS\*	[0]*  VERS_1.1    VERS_1.1
+[0]* g    DO \*ABS\*	[0]*  VERS_1.2    VERS_1.2
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]* \(Base\)       (0x[0-9a-f][0-9a-f] )?show_foo
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]* \(VERS_1.1\)   (0x[0-9a-f][0-9a-f] )?show_foo
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]*  VERS_1.2    (0x[0-9a-f][0-9a-f] )?show_foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers15.sym b/binutils-2.19/ld/testsuite/ld-elfvers/vers15.sym
new file mode 100644
index 0000000..87bab62
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers15.sym
@@ -0,0 +1,3 @@
+[0-9a-f]* g     F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?show_foo@
+[0-9a-f]* g     F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?show_foo@VERS_1.1
+[0-9a-f]* g     F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?show_foo@@VERS_1.2
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers15.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers15.ver
new file mode 100644
index 0000000..3f960fd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers15.ver
@@ -0,0 +1,5 @@
+Version definitions:
+[1-3] 0x01 0x07cc9645 vers15
+[1-3] 0x00 0x0a7927b1 VERS_1.1
+[1-3] 0x00 0x0a7927b2 VERS_1.2
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers16.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers16.c
new file mode 100644
index 0000000..6668bc6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers16.c
@@ -0,0 +1,10 @@
+int show_bar ()
+{
+  return 0;
+}
+extern int show_foo ();
+
+int main ()
+{
+  return show_foo ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers16.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers16.dsym
new file mode 100644
index 0000000..6c424c3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers16.dsym
@@ -0,0 +1,2 @@
+[0-9a-f]* g    DF (\.text|\*ABS\*)	[0-9a-f]*(  Base       )? (0x[0-9a-f][0-9a-f] )?show_bar
+[0-9a-f]*      DF \*UND\*	[0-9a-f]*(             )? (0x[0-9a-f][0-9a-f] )?show_foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers16.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers16.map
new file mode 100644
index 0000000..766332f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers16.map
@@ -0,0 +1,3 @@
+VERS_1.1 {
+  global: show_bar;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers16a.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers16a.c
new file mode 100644
index 0000000..153b1fd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers16a.c
@@ -0,0 +1,8 @@
+int show_bar ()
+{
+  return 1;
+}
+int show_foo ()
+{
+  return show_bar ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers16a.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers16a.dsym
new file mode 100644
index 0000000..058df47
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers16a.dsym
@@ -0,0 +1,3 @@
+[0-9a-f]* g    DO (\.text|\*ABS\*)	[0-9a-f]*  VERS_1\.1    VERS_1\.1
+[0-9a-f]* g    DF (\.text|\*ABS\*)	[0-9a-f]*  VERS_1\.1    (0x[0-9a-f][0-9a-f] )?show_bar
+[0-9a-f]* g    DF (\.text|\*ABS\*)	[0-9a-f]*  Base        (0x[0-9a-f][0-9a-f] )?show_foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers16a.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers16a.ver
new file mode 100644
index 0000000..7b50067
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers16a.ver
@@ -0,0 +1,3 @@
+Version definitions:
+[1-2] 0x01 0x064c090f vers16a.so
+[1-2] 0x00 0x0a7927b1 VERS_1.1
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers17.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers17.c
new file mode 100644
index 0000000..3bcd647
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers17.c
@@ -0,0 +1,5 @@
+int
+show_foo ()
+{
+  return 99;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers17.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers17.dsym
new file mode 100644
index 0000000..8decc0a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers17.dsym
@@ -0,0 +1,2 @@
+[0]* g    DO \*ABS\*	[0]*  VERS_2.0    VERS_2.0
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]*  VERS_2.0    (0x[0-9a-f][0-9a-f] )?show_foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers17.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers17.map
new file mode 100644
index 0000000..a5c9cf6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers17.map
@@ -0,0 +1,4 @@
+VERS_2.0 {
+	 global:
+		 show_foo;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers17.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers17.ver
new file mode 100644
index 0000000..b234c9b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers17.ver
@@ -0,0 +1,3 @@
+Version definitions:
+[1-2] 0x01 0x0964f95f vers17.so
+[1-2] 0x00 0x0a7922b0 VERS_2.0
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers18.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers18.c
new file mode 100644
index 0000000..25dcc25
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers18.c
@@ -0,0 +1,42 @@
+int
+bar ()
+{
+  return 3;
+}
+
+#pragma weak hide_original_foo
+
+int
+hide_original_foo ()
+{
+  return 1 + bar ();
+}
+
+#pragma weak hide_old_foo
+
+int
+hide_old_foo ()
+{
+  return 10 + bar();
+}
+
+#pragma weak hide_old_foo1
+
+int
+hide_old_foo1 ()
+{
+  return 100 + bar ();
+}
+
+#pragma weak hide_new_foo
+
+int
+hide_new_foo ()
+{
+  return 1000 + bar ();
+}
+
+__asm__(".symver hide_original_foo,show_foo@");
+__asm__(".symver hide_old_foo,show_foo@VERS_1.1");
+__asm__(".symver hide_old_foo1,show_foo@VERS_1.2");
+__asm__(".symver hide_new_foo,show_foo@@VERS_2.0");
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers18.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers18.dsym
new file mode 100644
index 0000000..c60237a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers18.dsym
@@ -0,0 +1,7 @@
+[0]* g    DO \*ABS\*	[0]*  VERS_1.1    VERS_1.1
+[0]* g    DO \*ABS\*	[0]*  VERS_1.2    VERS_1.2
+[0]* g    DO \*ABS\*	[0]*  VERS_2.0    VERS_2.0
+[0-9a-f]*  w   DF (.text|\*ABS\*)	[0-9a-f]* \(Base\)       (0x[0-9a-f][0-9a-f] )?show_foo
+[0-9a-f]*  w   DF (.text|\*ABS\*)	[0-9a-f]* \(VERS_1.1\)   (0x[0-9a-f][0-9a-f] )?show_foo
+[0-9a-f]*  w   DF (.text|\*ABS\*)	[0-9a-f]* \(VERS_1.2\)   (0x[0-9a-f][0-9a-f] )?show_foo
+[0-9a-f]*  w   DF (.text|\*ABS\*)	[0-9a-f]*  VERS_2.0    (0x[0-9a-f][0-9a-f] )?show_foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers18.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers18.map
new file mode 100644
index 0000000..8dcff39
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers18.map
@@ -0,0 +1,12 @@
+VERS_1.1 {
+	 local:
+		 hide_old*; 
+		 hide_original*; 
+		 hide_new*; 
+};
+
+VERS_1.2 {
+} VERS_1.1;
+
+VERS_2.0 {
+} VERS_1.2;
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers18.sym b/binutils-2.19/ld/testsuite/ld-elfvers/vers18.sym
new file mode 100644
index 0000000..f9cefdf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers18.sym
@@ -0,0 +1,4 @@
+[0-9a-f]*  w    F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?show_foo@
+[0-9a-f]*  w    F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?show_foo@VERS_1.1
+[0-9a-f]*  w    F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?show_foo@VERS_1.2
+[0-9a-f]*  w    F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?show_foo@@VERS_2.0
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers18.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers18.ver
new file mode 100644
index 0000000..c6023de
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers18.ver
@@ -0,0 +1,7 @@
+Version definitions:
+[1-4] 0x01 0x0964e95f vers18.so
+[1-4] 0x00 0x0a7927b1 VERS_1.1
+[1-4] 0x00 0x0a7927b2 VERS_1.2
+	VERS_1.1 
+[1-4] 0x00 0x0a7922b0 VERS_2.0
+	VERS_1.2 
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers19.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers19.c
new file mode 100644
index 0000000..c1bf27a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers19.c
@@ -0,0 +1,10 @@
+#include <stdio.h>
+
+extern int show_foo ();
+
+int
+main ()
+{
+  printf ("%d\n", show_foo ());
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers19.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers19.dsym
new file mode 100644
index 0000000..c9c2642
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers19.dsym
@@ -0,0 +1 @@
+[0-9a-f]*      DF \*UND\*	[0-9a-f]*  VERS_2.0    (0x[0-9a-f][0-9a-f] )?show_foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers19.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers19.ver
new file mode 100644
index 0000000..28a52c4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers19.ver
@@ -0,0 +1,3 @@
+Version References:
+  required from tmpdir/vers18.so:
+    0x0a7922b0 0x00 0[23] VERS_2.0
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers2.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers2.c
new file mode 100644
index 0000000..eda54cb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers2.c
@@ -0,0 +1,13 @@
+/*
+ * Test function.  This is built into a shared library, and references a
+ * versioned symbol foo that is in test.so.
+ */
+#include <stdio.h>
+
+extern int show_foo ();
+
+void
+show_xyzzy()
+{
+  printf("%d", show_foo());
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers2.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers2.dsym
new file mode 100644
index 0000000..99985c2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers2.dsym
@@ -0,0 +1,3 @@
+[0-9a-f]*      DF \*UND\*	[0-9a-f]*  VERS_2.0    (0x[0-9a-f][0-9a-f] )?show_foo
+[0]* g    DO \*ABS\*	[0]*  VERS_XXX_1.1 VERS_XXX_1.1
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]*  VERS_XXX_1.1 (0x[0-9a-f][0-9a-f] )?show_xyzzy
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers2.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers2.map
new file mode 100644
index 0000000..cd57d7e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers2.map
@@ -0,0 +1,4 @@
+
+VERS_XXX_1.1 {
+		 show_xyzzy;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers2.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers2.ver
new file mode 100644
index 0000000..ea992ff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers2.ver
@@ -0,0 +1,8 @@
+Version definitions:
+[1-2] 0x01 0x0c96525f vers2.so
+[1-2] 0x00 0x08785b51 VERS_XXX_1.1
+
+Version References:
+  required from tmpdir/vers1.so:
+    0x0a7922b0 0x00 03 VERS_2.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers20.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers20.c
new file mode 100644
index 0000000..01a6ff2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers20.c
@@ -0,0 +1 @@
+int show_foo;
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers20.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers20.dsym
new file mode 100644
index 0000000..70aa05e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers20.dsym
@@ -0,0 +1,2 @@
+[0]*[ 	]+g[ 	]+DO[ 	]+\*ABS\*[ 	]+[0]*[ 	]+VERS_1.1[ 	]+VERS_1.1
+[0-9a-f]*[ 	]+g[ 	]+DO[ 	]+.(s|)bss[	]+[0-9a-f]*[ 	]+VERS_1.1[ 	]+show_foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers20.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers20.map
new file mode 100644
index 0000000..e683565
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers20.map
@@ -0,0 +1,7 @@
+VERS_1.1 {
+  global:
+    show_foo;
+  local:
+    *;
+};
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers20.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers20.ver
new file mode 100644
index 0000000..1339147
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers20.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x0965695f vers20.so
+[1-2] 0x00 0x0a7927b1 VERS_1.1
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers20a.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers20a.ver
new file mode 100644
index 0000000..c7e11fb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers20a.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x0652090f vers20a.so
+[1-2] 0x00 0x0a7927b1 VERS_1.1
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers21.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers21.c
new file mode 100644
index 0000000..2879c7f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers21.c
@@ -0,0 +1,32 @@
+__asm__(".symver _old_foo,foo@VERS.0");
+__asm__(".symver _old_bar,bar@VERS.0");
+__asm__(".symver _old_foobar,foobar@VERS.0");
+__asm__(".weak  _old_bar");
+
+int
+bar () 
+{
+  return 1;
+}
+
+int
+_old_bar () 
+{
+  return bar ();
+}
+
+int
+foo () 
+{
+  return 2;
+}
+
+int
+_old_foo () 
+{
+  return foo ();
+}
+
+int _old_foobar = -1;
+
+int foobar = 1;
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers21.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers21.dsym
new file mode 100644
index 0000000..2096b5d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers21.dsym
@@ -0,0 +1,4 @@
+[0]*[ 	]+g[ 	]+DO[ 	]+\*ABS\*[ 	]+[0]*[ 	]+VERS.0[ 	]+VERS.0
+[0-9a-f]*[ 	]+w[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+\(VERS.0\)[ 	]+(0x[0-9a-f]*|)[ 	]*bar
+[0-9a-f]*[ 	]+g[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+\(VERS.0\)[ 	]+(0x[0-9a-f]*|)[ 	]*foo
+[0-9a-f]*[ 	]+g[ 	]+DO[ 	]+.s?data[	]+[0-9a-f]*[ 	]+\(VERS.0\)[ 	]+foobar
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers21.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers21.map
new file mode 100644
index 0000000..08f748a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers21.map
@@ -0,0 +1,8 @@
+VERS.0 {
+  global:
+    bar;
+    foo;
+    foobar;
+  local:
+    *;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers21.sym b/binutils-2.19/ld/testsuite/ld-elfvers/vers21.sym
new file mode 100644
index 0000000..bcb6359
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers21.sym
@@ -0,0 +1,3 @@
+[0-9a-f]*[ 	]+g[ 	]+O[ 	]+.s?data[ 	]+[0-9a-f]* (0x[0-9a-f][0-9a-f] )?foobar@VERS.0
+[0-9a-f]*[ 	]+w[ 	]+F[ 	]+.text[ 	]+[0-9a-f]* (0x[0-9a-f][0-9a-f] )?bar@VERS.0
+[0-9a-f]*[ 	]+g[ 	]+F[ 	]+.text[ 	]+[0-9a-f]* (0x[0-9a-f][0-9a-f] )?foo@VERS.0
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers21.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers21.ver
new file mode 100644
index 0000000..76e4a52
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers21.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x0965595f vers21.so
+[1-2] 0x00 0x05aa7610 VERS.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers22.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers22.c
new file mode 100644
index 0000000..a04695b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers22.c
@@ -0,0 +1,7 @@
+extern void bar ();
+
+void 
+foo ()
+{
+  bar ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers22.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers22.dsym
new file mode 100644
index 0000000..bef7c56
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers22.dsym
@@ -0,0 +1 @@
+[0-9a-f]*      DF \*UND\*	[0-9a-f]*  VERS.0      (0x[0-9a-f][0-9a-f] )?bar
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers22.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers22.map
new file mode 100644
index 0000000..9a03b0b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers22.map
@@ -0,0 +1,4 @@
+VERS.0 {
+  global:
+    bar;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers22.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers22.ver
new file mode 100644
index 0000000..05afce7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers22.ver
@@ -0,0 +1,4 @@
+Version References:
+  required from tmpdir/vers22b.so:
+    0x05aa7610 0x00 02 VERS.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers22a.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers22a.c
new file mode 100644
index 0000000..288c820
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers22a.c
@@ -0,0 +1,6 @@
+__asm__(".symver _old_bar,bar@VERS.0");
+
+void
+_old_bar () 
+{
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers22a.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers22a.dsym
new file mode 100644
index 0000000..b710e71
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers22a.dsym
@@ -0,0 +1,2 @@
+[0]*[ 	]+g[ 	]+DO[ 	]+\*ABS\*[ 	]+[0]*[ 	]+VERS.0[ 	]+VERS.0
+[0-9a-f]*[ 	]+g[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+\(VERS.0\)[ 	]+(0x[0-9a-f]*|)[ 	]*bar
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers22a.sym b/binutils-2.19/ld/testsuite/ld-elfvers/vers22a.sym
new file mode 100644
index 0000000..39fd10a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers22a.sym
@@ -0,0 +1 @@
+[0-9a-f]*[ 	]+g[ 	]+F[ 	]+.text[ 	]+[0-9a-f]* (0x[0-9a-f][0-9a-f] )?bar@VERS.0
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers22a.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers22a.ver
new file mode 100644
index 0000000..b7e1f62
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers22a.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x0660090f vers22a.so
+[1-2] 0x00 0x05aa7610 VERS.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers22b.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers22b.c
new file mode 100644
index 0000000..9e559cc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers22b.c
@@ -0,0 +1,4 @@
+void
+bar () 
+{
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers22b.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers22b.dsym
new file mode 100644
index 0000000..25d78fa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers22b.dsym
@@ -0,0 +1,2 @@
+[0]*[ 	]+g[ 	]+DO[ 	]+\*ABS\*[ 	]+[0]*[ 	]+VERS.0[ 	]+VERS.0
+[0-9a-f]*[ 	]+g[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+VERS.0[ 	]+(0x[0-9a-f]*|)[ 	]*bar
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers22b.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers22b.ver
new file mode 100644
index 0000000..b20f636
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers22b.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x065f990f vers22b.so
+[1-2] 0x00 0x05aa7610 VERS.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers23.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers23.c
new file mode 100644
index 0000000..9797725
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers23.c
@@ -0,0 +1,10 @@
+extern void bar ();
+extern void foo ();
+
+int
+main ()
+{
+  bar ();
+  foo ();
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers23.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers23.dsym
new file mode 100644
index 0000000..d800afa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers23.dsym
@@ -0,0 +1 @@
+[0-9a-f]*      DF \*UND\*	[0-9a-f]*  VERS.0      (0x[0-9a-f][0-9a-f] )?foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers23.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers23.ver
new file mode 100644
index 0000000..983355b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers23.ver
@@ -0,0 +1,4 @@
+Version References:
+  required from tmpdir/vers23a.so:
+    0x05aa7610 0x00 ?? VERS.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers23a.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers23a.c
new file mode 100644
index 0000000..250d6f9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers23a.c
@@ -0,0 +1,11 @@
+__asm__(".symver _old_bar,bar@VERS.0");
+
+void
+_old_bar (void) 
+{
+}
+
+void
+foo (void) 
+{
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers23a.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers23a.dsym
new file mode 100644
index 0000000..c96aa2f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers23a.dsym
@@ -0,0 +1,3 @@
+[0]*[ 	]+g[ 	]+DO[ 	]+\*ABS\*[ 	]+[0]*[ 	]+VERS.0[ 	]+VERS.0
+[0-9a-f]*[ 	]+g[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+\(VERS.0\)[ 	]+(0x[0-9a-f]*|)[ 	]*bar
+[0-9a-f]*[ 	]+g[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+VERS.0[ 	]+(0x[0-9a-f]*|)[ 	]*foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers23a.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers23a.map
new file mode 100644
index 0000000..325fb38
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers23a.map
@@ -0,0 +1,5 @@
+VERS.0 {
+  global:
+    bar;
+    foo;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers23a.sym b/binutils-2.19/ld/testsuite/ld-elfvers/vers23a.sym
new file mode 100644
index 0000000..39fd10a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers23a.sym
@@ -0,0 +1 @@
+[0-9a-f]*[ 	]+g[ 	]+F[ 	]+.text[ 	]+[0-9a-f]* (0x[0-9a-f][0-9a-f] )?bar@VERS.0
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers23a.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers23a.ver
new file mode 100644
index 0000000..3f3e3c0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers23a.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x065f090f vers23a.so
+[1-2] 0x00 0x05aa7610 VERS.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers23b.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers23b.c
new file mode 100644
index 0000000..299e2be
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers23b.c
@@ -0,0 +1,4 @@
+void
+bar (void) 
+{
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers23b.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers23b.dsym
new file mode 100644
index 0000000..25d78fa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers23b.dsym
@@ -0,0 +1,2 @@
+[0]*[ 	]+g[ 	]+DO[ 	]+\*ABS\*[ 	]+[0]*[ 	]+VERS.0[ 	]+VERS.0
+[0-9a-f]*[ 	]+g[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+VERS.0[ 	]+(0x[0-9a-f]*|)[ 	]*bar
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers23b.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers23b.map
new file mode 100644
index 0000000..9a03b0b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers23b.map
@@ -0,0 +1,4 @@
+VERS.0 {
+  global:
+    bar;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers23b.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers23b.ver
new file mode 100644
index 0000000..4e3edb3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers23b.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x065e990f vers23b.so
+[1-2] 0x00 0x05aa7610 VERS.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers23c.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers23c.ver
new file mode 100644
index 0000000..1fc69e8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers23c.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x065ea90f vers23c.so
+[1-2] 0x00 0x05aa7610 VERS.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers23d.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers23d.dsym
new file mode 100644
index 0000000..b31b82b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers23d.dsym
@@ -0,0 +1,2 @@
+[0-9a-f]*      DF \*UND\*	[0-9a-f]*  VERS.0      (0x[0-9a-f][0-9a-f] )?bar
+[0-9a-f]*      DF \*UND\*	[0-9a-f]*  VERS.0      (0x[0-9a-f][0-9a-f] )?foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers24.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers24.map
new file mode 100644
index 0000000..06ea42f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers24.map
@@ -0,0 +1,4 @@
+VERS.0 {
+  global: x; foo;
+  local: *;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers24.rd b/binutils-2.19/ld/testsuite/ld-elfvers/vers24.rd
new file mode 100644
index 0000000..9ed8762
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers24.rd
@@ -0,0 +1,15 @@
+Relocation section .*
+# Ensure there is a dynamic relocation against x
+#...
+[0-9a-f]+ +[0-9a-f]+ R_.* +x(| \+ 0)
+#...
+Symbol table '.dynsym' contains [0-9]+ entries:
+# And ensure the dynamic symbol table contains at least x@VERS.0
+# and foo@@VERS.0 symbols
+#...
+ +[0-9]+: [0-9a-f]+ +(4 OBJECT +GLOBAL DEFAULT +[0-9]+ x|[0-9]+ FUNC +GLOBAL DEFAULT +[0-9]+ foo@)@VERS\.0
+#...
+ +[0-9]+: [0-9a-f]+ +(4 OBJECT +GLOBAL DEFAULT +[0-9]+ x|[0-9]+ FUNC +GLOBAL DEFAULT +[0-9]+ foo@)@VERS\.0
+#...
+Symbol table '.symtab' contains [0-9]+ entries:
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers24a.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers24a.c
new file mode 100644
index 0000000..7fef8d8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers24a.c
@@ -0,0 +1,5 @@
+/* Test whether .symver x, x@foo
+   causes relocations against x within the same shared library
+   to become dynamic relocations against x@foo.  */
+int x = 12;
+__asm__ (".symver x, x@VERS.0");
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers24b.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers24b.c
new file mode 100644
index 0000000..8a18b3a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers24b.c
@@ -0,0 +1,5 @@
+extern int x;
+void foo (void)
+{
+  x = 24;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers24c.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers24c.c
new file mode 100644
index 0000000..267c424
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers24c.c
@@ -0,0 +1,9 @@
+/* Test whether .symver x, x@foo
+   causes relocations against x within the same shared library
+   to become dynamic relocations against x@foo.  */
+int x = 12;
+__asm__ (".symver x, x@VERS.0");
+void foo (void)
+{
+  x = 24;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers25a.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers25a.c
new file mode 100644
index 0000000..f5be371
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers25a.c
@@ -0,0 +1 @@
+void foo () {}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers25a.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers25a.dsym
new file mode 100644
index 0000000..fcf6384
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers25a.dsym
@@ -0,0 +1,2 @@
+[0]*[ 	]+g[ 	]+DO[ 	]+\*ABS\*[ 	]+[0]*[ 	]+VERS.0[ 	]+VERS.0
+[0-9a-f]*[ 	]+g[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+VERS.0[ 	]+(0x[0-9a-f]*|)[ 	]*foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers25a.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers25a.map
new file mode 100644
index 0000000..31bfc76
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers25a.map
@@ -0,0 +1,5 @@
+VERS.0 {
+  global:
+    foo;
+  local: *;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers25a.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers25a.ver
new file mode 100644
index 0000000..df3aad0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers25a.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x065d090f vers25a.so
+[1-2] 0x00 0x05aa7610 VERS.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers25b.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers25b.c
new file mode 100644
index 0000000..b119c69
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers25b.c
@@ -0,0 +1 @@
+/* Empty file  */
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers25b.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers25b.dsym
new file mode 100644
index 0000000..71923c3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers25b.dsym
@@ -0,0 +1 @@
+# Empty file.
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers25b.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers25b.ver
new file mode 100644
index 0000000..932b798
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers25b.ver
@@ -0,0 +1 @@
+# Empty file
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers26a.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers26a.c
new file mode 100644
index 0000000..5b5ccbf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers26a.c
@@ -0,0 +1,4 @@
+void
+foo ()
+{
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers26a.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers26a.dsym
new file mode 100644
index 0000000..fcf6384
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers26a.dsym
@@ -0,0 +1,2 @@
+[0]*[ 	]+g[ 	]+DO[ 	]+\*ABS\*[ 	]+[0]*[ 	]+VERS.0[ 	]+VERS.0
+[0-9a-f]*[ 	]+g[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+VERS.0[ 	]+(0x[0-9a-f]*|)[ 	]*foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers26a.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers26a.map
new file mode 100644
index 0000000..31bfc76
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers26a.map
@@ -0,0 +1,5 @@
+VERS.0 {
+  global:
+    foo;
+  local: *;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers26a.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers26a.ver
new file mode 100644
index 0000000..5462658
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers26a.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x065c090f vers26a.so
+[1-2] 0x00 0x05aa7610 VERS.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers26b.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers26b.c
new file mode 100644
index 0000000..c724c32
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers26b.c
@@ -0,0 +1,10 @@
+#pragma weak foo 
+
+void foo ();
+
+void
+ref ()
+{
+  if (foo)
+    foo ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers26b.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers26b.dsym
new file mode 100644
index 0000000..932b798
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers26b.dsym
@@ -0,0 +1 @@
+# Empty file
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers26b.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers26b.ver
new file mode 100644
index 0000000..932b798
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers26b.ver
@@ -0,0 +1 @@
+# Empty file
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27a.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers27a.c
new file mode 100644
index 0000000..f5be371
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27a.c
@@ -0,0 +1 @@
+void foo () {}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27a.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers27a.dsym
new file mode 100644
index 0000000..fcf6384
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27a.dsym
@@ -0,0 +1,2 @@
+[0]*[ 	]+g[ 	]+DO[ 	]+\*ABS\*[ 	]+[0]*[ 	]+VERS.0[ 	]+VERS.0
+[0-9a-f]*[ 	]+g[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+VERS.0[ 	]+(0x[0-9a-f]*|)[ 	]*foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27a.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers27a.map
new file mode 100644
index 0000000..31bfc76
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27a.map
@@ -0,0 +1,5 @@
+VERS.0 {
+  global:
+    foo;
+  local: *;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27a.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers27a.ver
new file mode 100644
index 0000000..634f1f0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27a.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x065b090f vers27a.so
+[1-2] 0x00 0x05aa7610 VERS.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27b.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers27b.c
new file mode 100644
index 0000000..7b164c4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27b.c
@@ -0,0 +1,2 @@
+void foo () {}
+asm (".hidden foo");
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27b.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers27b.dsym
new file mode 100644
index 0000000..932b798
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27b.dsym
@@ -0,0 +1 @@
+# Empty file
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27b.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers27b.ver
new file mode 100644
index 0000000..932b798
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27b.ver
@@ -0,0 +1 @@
+# Empty file
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27c.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers27c.c
new file mode 100644
index 0000000..b119c69
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27c.c
@@ -0,0 +1 @@
+/* Empty file  */
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27c.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers27c.dsym
new file mode 100644
index 0000000..932b798
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27c.dsym
@@ -0,0 +1 @@
+# Empty file
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27c.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers27c.ver
new file mode 100644
index 0000000..932b798
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27c.ver
@@ -0,0 +1 @@
+# Empty file
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27d.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d.dsym
new file mode 100644
index 0000000..9813d95
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d.dsym
@@ -0,0 +1,2 @@
+[0]*[ 	]+g[ 	]+DO[ 	]+\*ABS\*[ 	]+[0]*[ 	]+VERS.0[ 	]+VERS.0
+[0-9a-f]*[ 	]+g[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+\(VERS.0\)[ 	]+(0x[0-9a-f]*|)[ 	]*foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27d.sym b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d.sym
new file mode 100644
index 0000000..2069993
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d.sym
@@ -0,0 +1 @@
+[0-9a-f]*[ 	]+g[ 	]+F[ 	]+.text[ 	]+[0-9a-f]* (0x[0-9a-f][0-9a-f] )?foo@VERS.0
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27d.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d.ver
new file mode 100644
index 0000000..8343f3a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x05ac0cff vers27d1.so
+[1-2] 0x00 0x05aa7610 VERS.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27d1.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d1.c
new file mode 100644
index 0000000..3fc60b0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d1.c
@@ -0,0 +1,6 @@
+void
+foo ()
+{
+}
+
+asm (".symver foo,foo@VERS.0");
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27d2.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d2.c
new file mode 100644
index 0000000..a98f38a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d2.c
@@ -0,0 +1,7 @@
+void foo ();
+
+void
+ref ()
+{
+  foo ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27d3.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d3.c
new file mode 100644
index 0000000..b265880
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d3.c
@@ -0,0 +1,21 @@
+extern void ref ();
+extern void foo ();
+
+void
+_start ()
+{
+  foo ();
+  ref ();
+}
+
+void
+__start ()
+{
+  _start ();
+}
+
+void
+start ()
+{
+  __start ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27d4.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d4.dsym
new file mode 100644
index 0000000..d800afa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d4.dsym
@@ -0,0 +1 @@
+[0-9a-f]*      DF \*UND\*	[0-9a-f]*  VERS.0      (0x[0-9a-f][0-9a-f] )?foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers27d4.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d4.ver
new file mode 100644
index 0000000..12c79c9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers27d4.ver
@@ -0,0 +1,3 @@
+Version References:
+  required from tmpdir/vers27a.so:
+    0x05aa7610 0x00 02 VERS.0
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers28a.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers28a.c
new file mode 100644
index 0000000..f5be371
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers28a.c
@@ -0,0 +1 @@
+void foo () {}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers28a.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers28a.dsym
new file mode 100644
index 0000000..932b798
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers28a.dsym
@@ -0,0 +1 @@
+# Empty file
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers28a.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers28a.ver
new file mode 100644
index 0000000..932b798
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers28a.ver
@@ -0,0 +1 @@
+# Empty file
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers28b.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers28b.c
new file mode 100644
index 0000000..8186782
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers28b.c
@@ -0,0 +1,3 @@
+#pragma weak foo
+
+void foo () {}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers28b.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers28b.dsym
new file mode 100644
index 0000000..e174c91
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers28b.dsym
@@ -0,0 +1,2 @@
+[0]*[ 	]+g[ 	]+DO[ 	]+\*ABS\*[ 	]+[0]*[ 	]+VERS.0[ 	]+VERS.0
+[0-9a-f]*[ 	]+w[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+VERS.0[ 	]+(0x[0-9a-f]*|)[ 	]*foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers28b.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers28b.map
new file mode 100644
index 0000000..31bfc76
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers28b.map
@@ -0,0 +1,5 @@
+VERS.0 {
+  global:
+    foo;
+  local: *;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers28b.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers28b.ver
new file mode 100644
index 0000000..b826c53
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers28b.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x0659990f vers28b.so
+[1-2] 0x00 0x05aa7610 VERS.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers28c.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers28c.c
new file mode 100644
index 0000000..55afb6c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers28c.c
@@ -0,0 +1,7 @@
+extern void foo ();
+
+void
+bar ()
+{
+  foo ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers28c.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers28c.dsym
new file mode 100644
index 0000000..37a1c43
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers28c.dsym
@@ -0,0 +1 @@
+[0-9a-f]*[ 	]+DF[ 	]+\*UND\*[	]+[0-9a-f]*[ 	]+VERS.0[ 	]+(0x[0-9a-f]*|)[ 	]*foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers28c.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers28c.ver
new file mode 100644
index 0000000..1462686
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers28c.ver
@@ -0,0 +1,4 @@
+Version References:
+  required from tmpdir/vers28b.so:
+    0x05aa7610 0x00 02 VERS.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers29.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers29.c
new file mode 100644
index 0000000..15c63a8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers29.c
@@ -0,0 +1,5 @@
+/* Test for default versioning. */
+void show()
+{
+}
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers29.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers29.dsym
new file mode 100644
index 0000000..2e7bbde
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers29.dsym
@@ -0,0 +1 @@
+[0-9a-f]*[ 	]+g[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+vers29.so[ 	]+(0x[0-9a-f]*|)[ 	]*show
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers29.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers29.ver
new file mode 100644
index 0000000..5e73fab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers29.ver
@@ -0,0 +1,3 @@
+Version definitions:
+[1-2] 0x01 0x0965d95f vers29.so
+[1-2] 0x00 0x0965d95f vers29.so
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers3.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers3.c
new file mode 100644
index 0000000..dbb4daf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers3.c
@@ -0,0 +1,13 @@
+/*
+ * Main program for test1, test2.
+ */
+#include <stdio.h>
+
+extern int show_foo ();
+
+int
+main()
+{
+  printf("%d\n", show_foo());
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers3.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers3.dsym
new file mode 100644
index 0000000..c9c2642
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers3.dsym
@@ -0,0 +1 @@
+[0-9a-f]*      DF \*UND\*	[0-9a-f]*  VERS_2.0    (0x[0-9a-f][0-9a-f] )?show_foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers3.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers3.ver
new file mode 100644
index 0000000..41dad48
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers3.ver
@@ -0,0 +1,4 @@
+Version References:
+  required from tmpdir/vers1.so:
+    0x0a7922b0 0x00 0[23] VERS_2.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers30.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers30.c
new file mode 100644
index 0000000..65dba2f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers30.c
@@ -0,0 +1,7 @@
+void global (void) {}
+void local (void) {}
+void foo (void) {}
+void bar (void) {}
+void info (void) {}
+void baz (void) __asm ("extern");
+void baz (void) {}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers30.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers30.dsym
new file mode 100644
index 0000000..1f358d4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers30.dsym
@@ -0,0 +1,5 @@
+[0]* g    DO \*ABS\*	[0]*  VERS_30.0   VERS_30.0
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]*  VERS_30.0   global
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]*  VERS_30.0   foo
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]*  VERS_30.0   info
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]*  VERS_30.0   extern
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers30.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers30.map
new file mode 100644
index 0000000..71d06d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers30.map
@@ -0,0 +1,6 @@
+VERS_30.0 {
+  global:
+    foo; info; global; extern "C" { extern; };
+  local:
+    local; bar; *;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers30.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers30.ver
new file mode 100644
index 0000000..e0968b9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers30.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x0966695f vers30.so
+[1-2] 0x00 0x079239b0 VERS_30.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers31.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers31.c
new file mode 100644
index 0000000..78d3927
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers31.c
@@ -0,0 +1,6 @@
+/* void f<int [3], char>(int (*) [3], char) */
+void _Z1fIA3_icEvPT_T0_() {}
+
+/* void f<double [3], long>(double (*) [3], long) */
+void _Z1fIA3_dlEvPT_T0_() {}
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers31.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers31.dsym
new file mode 100644
index 0000000..8924ed8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers31.dsym
@@ -0,0 +1,2 @@
+[0]* g    DO \*ABS\*	[0]*  VERS_31.0   VERS_31.0
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]*  VERS_31.0   _Z1fIA3_icEvPT_T0
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers31.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers31.map
new file mode 100644
index 0000000..e2d4baf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers31.map
@@ -0,0 +1,5 @@
+VERS_31.0 {
+  extern "C++" {
+    "void f<int [3], char>(int (*) [3], char)";
+  }; 	
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers31.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers31.ver
new file mode 100644
index 0000000..c1a0ed4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers31.ver
@@ -0,0 +1,3 @@
+Version definitions:
+[1-2] 0x01 0x0966595f vers31.so
+[1-2] 0x00 0x07923ab0 VERS_31.0
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers32.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers32.map
new file mode 100644
index 0000000..aef2bd9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers32.map
@@ -0,0 +1 @@
+VERS_1 { foo; };
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers32a.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers32a.c
new file mode 100644
index 0000000..a53eae6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers32a.c
@@ -0,0 +1 @@
+void foo(void) {}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers32a.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers32a.dsym
new file mode 100644
index 0000000..14f15d4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers32a.dsym
@@ -0,0 +1,2 @@
+[0]* g    DO \*ABS\*	[0]*  VERS_1      VERS_1
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]*  VERS_1      (0x[0-9a-f][0-9a-f] )?foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers32a.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers32a.ver
new file mode 100644
index 0000000..80c04c8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers32a.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x0670090f vers32a.so
+[1-2] 0x00 0x05aa7921 VERS_1
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers32b.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers32b.c
new file mode 100644
index 0000000..710cecc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers32b.c
@@ -0,0 +1 @@
+/* Empty */
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers32b.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers32b.dsym
new file mode 100644
index 0000000..8cc620c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers32b.dsym
@@ -0,0 +1,2 @@
+[0-9a-f]* g    D  \*ABS\*	[0-9a-f]*  VERS_1      (0x[0-9a-f][0-9a-f] )?foo
+[0]* g    DO \*ABS\*	[0]*  VERS_1      VERS_1
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers32b.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers32b.ver
new file mode 100644
index 0000000..126129a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers32b.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x066f990f vers32b.so
+[1-2] 0x00 0x05aa7921 VERS_1
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers32c.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers32c.dsym
new file mode 100644
index 0000000..70c7428
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers32c.dsym
@@ -0,0 +1,2 @@
+[0-9a-f]* g    DF \*ABS\*	[0-9a-f]*  VERS_1      (0x[0-9a-f][0-9a-f] )?foo
+[0]* g    DO \*ABS\*	[0]*  VERS_1      VERS_1
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers32c.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers32c.ver
new file mode 100644
index 0000000..be90471
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers32c.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x066fa90f vers32c.so
+[1-2] 0x00 0x05aa7921 VERS_1
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers32d.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers32d.ver
new file mode 100644
index 0000000..9d70622
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers32d.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x066fb90f vers32d.so
+[1-2] 0x00 0x05aa7921 VERS_1
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers4.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers4.c
new file mode 100644
index 0000000..453f2eb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers4.c
@@ -0,0 +1,31 @@
+/*
+ * Testcase to make sure that a versioned symbol definition in an
+ * application correctly defines the version node, if and only if
+ * the actual symbol is exported.  This is built both with and without
+ * -export-dynamic.
+ */
+#include <stdio.h>
+
+extern int foo ();
+
+int
+bar()
+{
+	return 3;
+}
+
+int
+new_foo()
+{
+	return 1000+bar();
+
+}
+
+__asm__(".symver new_foo,foo@@VERS_2.0");
+
+int
+main()
+{
+  printf("%d\n", foo());
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers4.sym b/binutils-2.19/ld/testsuite/ld-elfvers/vers4.sym
new file mode 100644
index 0000000..7449446
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers4.sym
@@ -0,0 +1 @@
+[0-9a-f]* g     F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?foo@@VERS_2.0
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers4a.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers4a.dsym
new file mode 100644
index 0000000..f7f9fda
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers4a.dsym
@@ -0,0 +1,2 @@
+[0]* g    DO \*ABS\*	[0]*  VERS_2.0    VERS_2.0
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]*  VERS_2.0    (0x[0-9a-f][0-9a-f] )?foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers4a.sym b/binutils-2.19/ld/testsuite/ld-elfvers/vers4a.sym
new file mode 100644
index 0000000..7449446
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers4a.sym
@@ -0,0 +1 @@
+[0-9a-f]* g     F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?foo@@VERS_2.0
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers4a.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers4a.ver
new file mode 100644
index 0000000..1f02b9d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers4a.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x07cc96a1 vers4a
+[1-2] 0x00 0x0a7922b0 VERS_2.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers5.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers5.c
new file mode 100644
index 0000000..cc6ea40
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers5.c
@@ -0,0 +1,51 @@
+/*
+ * Testcase to verify that foo@BAR and foo@@BAR are correctly detected
+ * as a multiply defined symbol.
+ */
+const char * bar1 = "asdf";
+const char * bar2 = "asdf";
+
+int
+bar()
+{
+	return 3;
+}
+
+int
+original_foo()
+{
+	return 1+bar();
+
+}
+
+int
+old_foo()
+{
+	return 10+bar();
+
+}
+
+int
+old_foo1()
+{
+	return 100+bar();
+
+}
+
+int
+new_foo()
+{
+	return 1000+bar();
+
+}
+
+__asm__(".symver original_foo,foo@");
+__asm__(".symver old_foo,foo@VERS_1.1");
+__asm__(".symver old_foo1,foo@VERS_1.2");
+__asm__(".symver new_foo,foo@@VERS_1.2");
+
+int
+main ()
+{
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers6.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers6.c
new file mode 100644
index 0000000..9e48df9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers6.c
@@ -0,0 +1,25 @@
+/*
+ * Testcase to make sure that if we externally reference a versioned symbol
+ * that we always get the right one.
+ */
+#include <stdio.h>
+
+extern int foo_1();
+extern int foo_2();
+extern int foo_3();
+extern int foo_4();
+
+int
+main()
+{
+  printf("Expect 4,    get %d\n", foo_1());
+  printf("Expect 13,   get %d\n", foo_2());
+  printf("Expect 103,  get %d\n", foo_3());
+  printf("Expect 1003, get %d\n", foo_4());
+  return 0;
+}
+
+__asm__(".symver foo_1,show_foo@");
+__asm__(".symver foo_2,show_foo@VERS_1.1");
+__asm__(".symver foo_3,show_foo@VERS_1.2");
+__asm__(".symver foo_4,show_foo@VERS_2.0");
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers6.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers6.dsym
new file mode 100644
index 0000000..7e851d4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers6.dsym
@@ -0,0 +1,4 @@
+[0-9a-f]*      DF \*UND\*	[0-9a-f]*              (0x[0-9a-f][0-9a-f] )?show_foo
+[0-9a-f]*      DF \*UND\*	[0-9a-f]*  VERS_2.0    (0x[0-9a-f][0-9a-f] )?show_foo
+[0-9a-f]*      DF \*UND\*	[0-9a-f]*  VERS_1.2    (0x[0-9a-f][0-9a-f] )?show_foo
+[0-9a-f]*      DF \*UND\*	[0-9a-f]*  VERS_1.1    (0x[0-9a-f][0-9a-f] )?show_foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers6.sym b/binutils-2.19/ld/testsuite/ld-elfvers/vers6.sym
new file mode 100644
index 0000000..d7b5cc7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers6.sym
@@ -0,0 +1,4 @@
+[0]* *F? *\*UND\*	[0]* show_foo@
+[0]* *F? *\*UND\*	[0]* show_foo@VERS_1.1
+[0]* *F? *\*UND\*	[0]* show_foo@VERS_1.2
+[0]* *F? *\*UND\*	[0]* show_foo@VERS_2.0
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers6.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers6.ver
new file mode 100644
index 0000000..48a2b46
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers6.ver
@@ -0,0 +1,6 @@
+Version References:
+  required from tmpdir/vers1.so:
+    0x0a7927b1 0x00 ?? VERS_1.1
+    0x0a7927b2 0x00 ?? VERS_1.2
+    0x0a7922b0 0x00 ?? VERS_2.0
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers7.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers7.c
new file mode 100644
index 0000000..54316c9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers7.c
@@ -0,0 +1,13 @@
+/*
+ * Test program that goes with test7.so
+ */
+
+extern int hide_a();
+extern int show_b();
+
+int
+main()
+{
+  return hide_a(1) + show_b(1);
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers7.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers7.map
new file mode 100644
index 0000000..65fd501
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers7.map
@@ -0,0 +1,6 @@
+VERS_1 {
+	global:
+		show_b ;
+	local:
+		hide_a;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers7a.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers7a.c
new file mode 100644
index 0000000..7bee8c7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers7a.c
@@ -0,0 +1,18 @@
+/*
+ * Test supplied by Ulrich.  Verify that we can correctly force 'a'
+ * to local scope.
+ */
+int
+__a_internal (int e)
+{
+  return e + 10;
+}
+
+int
+__b_internal (int e)
+{
+  return e + 42;
+}
+
+asm (".symver __a_internal,hide_a@@VERS_1");
+asm (".symver __b_internal,show_b@@VERS_1");
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers7a.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers7a.dsym
new file mode 100644
index 0000000..06696c7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers7a.dsym
@@ -0,0 +1,2 @@
+[0]* g    DO \*ABS\*	[0]*  VERS_1      VERS_1
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]*  VERS_1      (0x[0-9a-f][0-9a-f] )?show_b
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers7a.sym b/binutils-2.19/ld/testsuite/ld-elfvers/vers7a.sym
new file mode 100644
index 0000000..b99bd61
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers7a.sym
@@ -0,0 +1,2 @@
+[0-9a-f]* g     F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?hide_a@@VERS_1
+[0-9a-f]* g     F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?show_b@@VERS_1
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers7a.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers7a.ver
new file mode 100644
index 0000000..eeac5c5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers7a.ver
@@ -0,0 +1,4 @@
+Version definitions:
+[1-2] 0x01 0x096d595f vers7a.so
+[1-2] 0x00 0x05aa7921 VERS_1
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers8.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers8.c
new file mode 100644
index 0000000..a14586c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers8.c
@@ -0,0 +1,5 @@
+int
+main()
+{
+  return a(1) + b(1);
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers8.map b/binutils-2.19/ld/testsuite/ld-elfvers/vers8.map
new file mode 100644
index 0000000..c24fb10
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers8.map
@@ -0,0 +1,15 @@
+VERSION {
+	VERS_1.1 {
+		 local:
+			 hide_old*; 
+			 hide_original*; 
+			 hide_new*; 
+	};
+	
+	VERS_1.2 {
+	} VERS_1.1;
+	
+	VERS_2.0 {
+			 show_bar1; show_bar2;
+	} VERS_1.2;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers8.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers8.ver
new file mode 100644
index 0000000..47996c9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers8.ver
@@ -0,0 +1,8 @@
+Version definitions:
+[1-4] 0x01 0x0c96b25f vers8.so
+[1-4] 0x00 0x0a7927b1 VERS_1.1
+[1-4] 0x00 0x0a7927b2 VERS_1.2
+	VERS_1.1 
+[1-4] 0x00 0x0a7922b0 VERS_2.0
+	VERS_1.2 
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers9.c b/binutils-2.19/ld/testsuite/ld-elfvers/vers9.c
new file mode 100644
index 0000000..bef1402
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers9.c
@@ -0,0 +1,47 @@
+/*
+ * Testcase to verify that reference to foo@BAR and a definition of foo@@BAR
+ * are not treated as a multiple def.
+ */
+const char * bar1 = "asdf";
+const char * bar2 = "asdf";
+
+extern int old_foo1();
+
+int
+bar()
+{
+	return 3;
+}
+
+int
+original_foo()
+{
+	return 1+bar();
+
+}
+
+int
+old_foo()
+{
+	return 10+bar();
+
+}
+
+int
+new_foo()
+{
+	return 1000+bar();
+
+}
+
+int
+main()
+{
+  old_foo1();
+  return 0;
+}
+
+__asm__(".symver original_foo,foo@");
+__asm__(".symver old_foo,foo@VERS_1.1");
+__asm__(".symver old_foo1,foo@VERS_1.2");
+__asm__(".symver new_foo,foo@@VERS_1.2");
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers9.dsym b/binutils-2.19/ld/testsuite/ld-elfvers/vers9.dsym
new file mode 100644
index 0000000..9793002
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers9.dsym
@@ -0,0 +1,4 @@
+[0]* g    DO \*ABS\*	[0]*  VERS_1.1    VERS_1.1
+[0]* g    DO \*ABS\*	[0]*  VERS_1.2    VERS_1.2
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]* \(VERS_1.1\)   (0x[0-9a-f][0-9a-f] )?foo
+[0-9a-f]* g    DF (.text|\*ABS\*)	[0-9a-f]*  VERS_1.2    (0x[0-9a-f][0-9a-f] )?foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers9.sym b/binutils-2.19/ld/testsuite/ld-elfvers/vers9.sym
new file mode 100644
index 0000000..8231516
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers9.sym
@@ -0,0 +1,4 @@
+[0]* *F? *\*UND\*	[0]* foo@VERS_1.2
+[0-9a-f]* g     F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?foo@
+[0-9a-f]* g     F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?foo@VERS_1.1
+[0-9a-f]* g     F .text	[0-9a-f]* (0x[0-9a-f][0-9a-f] )?foo@@VERS_1.2
diff --git a/binutils-2.19/ld/testsuite/ld-elfvers/vers9.ver b/binutils-2.19/ld/testsuite/ld-elfvers/vers9.ver
new file mode 100644
index 0000000..fce267c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvers/vers9.ver
@@ -0,0 +1,5 @@
+Version definitions:
+[1-3] 0x01 0x007cc969 vers9
+[1-3] 0x00 0x0a7927b1 VERS_1.1
+[1-3] 0x00 0x0a7927b2 VERS_1.2
+
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/common.c b/binutils-2.19/ld/testsuite/ld-elfvsb/common.c
new file mode 100644
index 0000000..7d05eb7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/common.c
@@ -0,0 +1,14 @@
+int foo;
+asm (".hidden foo");
+
+int
+_start (void)
+{
+  return foo;
+}
+
+int
+__start (void)
+{
+  return _start ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/define.s b/binutils-2.19/ld/testsuite/ld-elfvsb/define.s
new file mode 100644
index 0000000..b38e3e0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/define.s
@@ -0,0 +1,10 @@
+	.data
+	.globl protected
+	.type protected,"object"
+protected:
+	.globl hidden
+	.type hidden,"object"
+hidden:
+	.globl internal
+	.type internal,"object"
+internal:
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/elf-offset.ld b/binutils-2.19/ld/testsuite/ld-elfvsb/elf-offset.ld
new file mode 100644
index 0000000..7c64824
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/elf-offset.ld
@@ -0,0 +1,173 @@
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = 0x100000;
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .gnu.version   : { *(.gnu.version)	}
+  .gnu.version_d   : { *(.gnu.version_d)	}
+  .gnu.version_r   : { *(.gnu.version_r)	}
+  .rel.text      :
+    {
+      *(.rel.text)
+      *(.rel.text.*)
+      *(.rel.gnu.linkonce.t*)
+    }
+  .rela.text     :
+    {
+      *(.rela.text)
+      *(.rela.text.*)
+      *(.rela.gnu.linkonce.t*)
+    }
+  .rel.data      :
+    {
+      *(.rel.data)
+      *(.rel.data.*)
+      *(.rel.gnu.linkonce.d*)
+    }
+  .rela.data     :
+    {
+      *(.rela.data)
+      *(.rela.data.*)
+      *(.rela.gnu.linkonce.d*)
+    }
+  .rel.rodata    :
+    {
+      *(.rel.rodata)
+      *(.rel.rodata.*)
+      *(.rel.gnu.linkonce.r*)
+    }
+  .rela.rodata   :
+    {
+      *(.rela.rodata)
+      *(.rela.rodata.*)
+      *(.rela.gnu.linkonce.r*)
+    }
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.toc       : { *(.rel.toc)		}
+  .rela.toc      : { *(.rela.toc)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.init      : { *(.rel.init)	}
+  .rela.init     : { *(.rela.init)	}
+  .rel.fini      : { *(.rel.fini)	}
+  .rela.fini     : { *(.rela.fini)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .rel.eh_frame  : { *(.rel.eh_frame)		}
+  .rela.eh_frame : { *(.rela.eh_frame)		}
+  .init          : { KEEP (*(.init))	}
+  .plt      : { *(.plt)	}
+  .text      :
+  {
+    *(.text)
+    *(.text.*)
+    *(.stub)
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.gnu.linkonce.t*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .fini      : { KEEP (*(.fini))		} =0x9090
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r*)
+  }
+  .rodata1   : { *(.rodata1) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN(0x1000) + (. & (0x1000 - 1));
+  .data    :
+  {
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d*)
+    SORT(CONSTRUCTORS)
+  }
+  .data1   : { *(.data1) }
+  .ctors         :
+  {
+    /* gcc uses crtbegin.o to find the start of the constructors, so
+       we make sure it is first.  Because this is a wildcard, it
+       doesn't matter if the user does not actually link against
+       crtbegin.o; the linker won't look for a file to match a
+       wildcard.  The wildcard also means that it doesn't matter which
+       directory crtbegin.o is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  }
+  .dtors         :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  }
+  .got           : { *(.got.plt) *(.got) }
+  .toc           : { *(.toc) }
+  .dynamic       : { *(.dynamic) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata     : { *(.sdata) *(.sdata.*) }
+  _edata  =  .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .sbss      : { *(.sbss) *(.scommon) }
+  .bss       :
+  {
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   . = ALIGN(32 / 8);
+  }
+  . = ALIGN(32 / 8);
+  _end = . ;
+  PROVIDE (end = .);
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment 0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  /* These must appear regardless of  .  */
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/elfvsb.dat b/binutils-2.19/ld/testsuite/ld-elfvsb/elfvsb.dat
new file mode 100644
index 0000000..bad3b1e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/elfvsb.dat
@@ -0,0 +1,26 @@
+mainvar == 1
+overriddenvar == 2
+shlibvar1 == 3
+shlib_mainvar () == 1
+shlib_overriddenvar () == 2
+shlib_shlibvar1 () == 3
+shlib_shlibvar2 () == 4
+shlib_shlibcall () == 5
+shlib_shlibcall2 () == 8
+shlib_maincall () == 6
+main_called () == 6
+shlib_checkfunptr1 (shlib_shlibvar1) == 1
+shlib_checkfunptr2 (main_called) == 1
+shlib_getfunptr1 () == shlib_shlibvar1
+shlib_getfunptr2 () == main_called
+shlib_check () == 1
+visibility_check () == 1
+visibility_checkfunptr () == 1
+main_visibility_check () == 1
+visibility_checkvar () == 1
+visibility_checkvarptr () == 1
+main_visibility_checkvar () == 1
+main_visibility_checkcom () == 1
+shlib_visibility_checkcom () == 1
+main_visibility_checkweak () == 1
+shlib_visibility_checkweak () == 1
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/elfvsb.exp b/binutils-2.19/ld/testsuite/ld-elfvsb/elfvsb.exp
new file mode 100644
index 0000000..7931c66
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/elfvsb.exp
@@ -0,0 +1,475 @@
+# Expect script for ld-visibility tests
+#   Copyright 2000, 2001, 2002, 2003, 2004, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Ian Lance Taylor (ian@cygnus.com)
+#	     and H.J. Lu (hjl@gnu.org)
+#
+
+# Make sure that ld can generate ELF shared libraries with visibility.
+
+# This test can only be run on a couple of ELF platforms.
+# Square bracket expressions seem to confuse istarget.
+if { ![istarget hppa*64*-*-hpux*] \
+     && ![istarget hppa*-*-linux*] \
+     && ![istarget i?86-*-linux*] \
+     && ![istarget ia64-*-linux*] \
+     && ![istarget m68k-*-linux*] \
+     && ![istarget mips*-*-linux*] \
+     && ![istarget powerpc*-*-linux*] \
+     && ![istarget arm*-*-linux*] \
+     && ![istarget alpha*-*-linux*] \
+     && ![istarget sparc*-*-linux*] \
+     && ![istarget s390*-*-linux*] \
+     && ![istarget sh\[34\]*-*-linux*] \
+     && ![istarget x86_64-*-linux*] } {
+    return
+}
+
+if { [istarget *-*-linux*aout*] \
+     || [istarget *-*-linux*oldld*] } {
+    return
+}
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach t $test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname $t]
+    run_dump_test [file rootname $t]
+}
+
+# The remaining tests can only be run if ld generates native executables.
+if ![isnative] then {return}
+
+set tmpdir tmpdir
+set SHCFLAG ""
+
+if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+
+    # AIX shared libraries do not seem to support useful features,
+    # like overriding the shared library function or letting the
+    # shared library refer to objects defined in the main program.  We
+    # avoid testing those features.
+    set SHCFLAG "-DXCOFF_TEST"
+
+    # The AIX 3.2.5 loader appears to randomly fail when loading
+    # shared libraries from NSF mounted partitions, so we avoid any
+    # potential problems by using a local directory.
+    catch {exec /bin/sh -c "echo $$"} pid
+    set tmpdir /usr/tmp/ld.$pid
+    catch "exec mkdir $tmpdir" exec_status
+
+    # On AIX, we need to explicitly export the symbols the shared
+    # library is going to provide, and need.
+    set file [open $tmpdir/xcoff.exp w]
+    puts $file shlibvar1
+    puts $file shlibvar2
+    puts $file shlib_shlibvar1
+    puts $file shlib_shlibvar2
+    puts $file shlib_shlibcall
+    puts $file shlib_shlibcalled
+    puts $file shlib_checkfunptr1
+    puts $file shlib_getfunptr1
+    puts $file shlib_check
+    close $file
+}
+
+set support_protected "no"
+
+if [istarget *-*-linux*] {
+    if [ld_compile "$CC -g $CFLAGS -DPROTECTED_CHECK" $srcdir/$subdir/main.c $tmpdir/main.o] {
+      if [ld_simple_link $CC $tmpdir/main "$tmpdir/main.o"] {
+	catch "exec $tmpdir/main" support_protected
+      }
+    }
+}
+
+# The test procedure.
+proc visibility_test { visibility progname testname main sh1 sh2 dat args } {
+    global CC
+    global srcdir
+    global subdir
+    global exec_output
+    global link_output
+    global host_triplet
+    global tmpdir
+
+    if [llength $args] { set shldflags [lindex $args 0] } else { set shldflags "" }
+
+    # Build the shared library.
+    # On AIX, we need to use an export file.
+    set shared -shared
+    if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+	set shared "-bM:SRE -bE:$tmpdir/xcoff.exp"
+    }
+    if {![ld_simple_link $CC $tmpdir/$progname.so "$shared $shldflags $tmpdir/$sh1 $tmpdir/$sh2"]} {
+	if { [ string match $visibility "hidden_undef" ]
+	     && [regexp "undefined reference to \`\.?visibility\'" $link_output]
+	     && [regexp "undefined reference to \`visibility_var\'" $link_output] } {
+    	    pass "$testname"
+	} else { if { [ string match $visibility "protected_undef" ]
+	     && [regexp "undefined reference to \`\.?visibility\'" $link_output]
+	     && [regexp "undefined reference to \`visibility_var\'" $link_output] } {
+    	    pass "$testname"
+	} else {
+	    fail "$testname"
+	}}
+    	return
+    }
+
+    # Link against the shared library.  Use -rpath so that the
+    # dynamic linker can locate the shared library at runtime.
+    # On AIX, we must include /lib in -rpath, as otherwise the loader
+    # can not find -lc.
+    set rpath $tmpdir
+    if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+	set rpath /lib:$tmpdir
+    }
+    if ![ld_simple_link $CC $tmpdir/$progname "-Wl,-rpath,$rpath $tmpdir/$main $tmpdir/$progname.so"] {
+	if { [ string match $visibility "hidden" ]
+	     && [regexp "undefined reference to \`\.?visibility\'" $link_output]
+	     && [regexp "undefined reference to \`visibility_var\'" $link_output] } {
+    	    pass "$testname"
+	} else { if { [ string match $visibility "hidden_undef_def" ]
+	     && [regexp "undefined reference to \`\.?visibility\'" $link_output]
+	     && [regexp "undefined reference to \`visibility_def\'" $link_output]
+	     && [regexp "undefined reference to \`\.?visibility_func\'" $link_output]
+	     && [regexp "undefined reference to \`visibility_var\'" $link_output] } {
+    	    pass "$testname"
+	} else {
+    	    fail "$testname"
+	}}
+    	return
+    }
+
+    if { [ string match $visibility "hidden" ]
+	 || [ string match $visibility "hidden_undef" ]
+	 || [ string match $visibility "protected_undef" ] } {
+	fail "$testname"
+    }
+
+    # Run the resulting program
+    send_log "$tmpdir/$progname >$tmpdir/$progname.out\n"
+    verbose "$tmpdir/$progname >$tmpdir/$progname.out"
+    catch "exec $tmpdir/$progname >$tmpdir/$progname.out" exec_output
+    if ![string match "" $exec_output] then {
+	send_log "$exec_output\n"
+	verbose "$exec_output"
+	fail "$testname"
+    	return
+    }
+
+    send_log "diff $tmpdir/$progname.out $srcdir/$subdir/$dat.dat\n"
+    verbose "diff $tmpdir/$progname.out $srcdir/$subdir/$dat.dat"
+    catch "exec diff $tmpdir/$progname.out $srcdir/$subdir/$dat.dat" exec_output
+    set exec_output [prune_warnings $exec_output]
+
+    if {![string match "" $exec_output]} then {
+	send_log "$exec_output\n"
+	verbose "$exec_output"
+	fail "$testname"
+        return
+    }
+
+    pass "$testname"
+}
+
+proc visibility_run {visibility} {
+    global CC
+    global CFLAGS
+    global SHCFLAG
+    global srcdir
+    global subdir
+    global tmpdir
+    global picflag
+    global target_triplet
+    global support_protected
+
+    if [ string match $visibility "hidden" ] {
+	set VSBCFLAG "-DHIDDEN_TEST"
+    } else { if [ string match $visibility "hidden_normal" ] {
+	set VSBCFLAG "-DHIDDEN_NORMAL_TEST"
+    } else { if [ string match $visibility "hidden_undef" ] {
+	set VSBCFLAG "-DHIDDEN_UNDEF_TEST"
+    } else { if [ string match $visibility "hidden_undef_def" ] {
+	set VSBCFLAG "-DHIDDEN_UNDEF_TEST -DDSO_DEFINE_TEST"
+    } else { if [ string match $visibility "hidden_weak" ] {
+	set VSBCFLAG "-DHIDDEN_WEAK_TEST"
+    } else { if [ string match $visibility "protected" ] {
+	set VSBCFLAG "-DPROTECTED_TEST"
+    } else { if [ string match $visibility "protected_undef" ] {
+	set VSBCFLAG "-DPROTECTED_UNDEF_TEST"
+    } else { if [ string match $visibility "protected_undef_def" ] {
+	set VSBCFLAG "-DPROTECTED_UNDEF_TEST -DDSO_DEFINE_TEST"
+    } else { if [ string match $visibility "protected_weak" ] {
+	set VSBCFLAG "-DPROTECTED_WEAK_TEST"
+    } else {
+	set VSBCFLAG ""
+    }}}}}}}}}
+
+    # Compile the main program.
+    if ![ld_compile "$CC -g $CFLAGS $SHCFLAG $VSBCFLAG" $srcdir/$subdir/main.c $tmpdir/mainnp.o] {
+	unresolved "visibility ($visibility) (non PIC)"
+	unresolved "visibility ($visibility)"
+    } else {
+	# The shared library is composed of two files.  First compile them
+	# without using -fpic.  That should work on an ELF system,
+	# although it will be less efficient because the dynamic linker
+	# will need to do more relocation work.  However, note that not
+	# using -fpic will cause some of the tests to return different
+	# results.
+	if { ![ld_compile "$CC -g $CFLAGS $SHCFLAG $VSBCFLAG" $srcdir/$subdir/sh1.c $tmpdir/sh1np.o]
+	     || ![ld_compile "$CC -g $CFLAGS $SHCFLAG $VSBCFLAG" $srcdir/$subdir/sh2.c $tmpdir/sh2np.o] } {
+	    unresolved "visibility ($visibility) (non PIC)"
+	} else { if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+	    visibility_test $visibility vnp "visibility ($visibility) (non PIC)" mainnp.o sh1np.o sh2np.o xcoff
+	} else {
+	    # SunOS non PIC shared libraries don't permit some cases of
+	    # overriding.
+	    if { [ string match $visibility "protected" ]
+		 || [ string match $visibility "protected_undef_def" ] } {
+		if [ string match $support_protected "no" ] {
+		    setup_xfail $target_triplet
+		}
+	    } else {
+		setup_xfail "*-*-sunos4*"
+	    }
+
+	    # Non-pic code uses name binding rules for applications to
+	    # reference variables by gp-relative relocs, which can't be
+	    # used with overridable symbols.
+	    if { ![ string match $visibility "hidden_undef" ]
+		 && ![ string match $visibility "protected_undef" ] } {
+		setup_xfail "ia64-*-linux*"
+		setup_xfail "alpha*-*-linux*"
+	    }
+	    if { ![ string match $visibility "hidden" ]
+		 && ![ string match $visibility "hidden_undef" ]
+		 && ![ string match $visibility "hidden_undef_def" ]
+		 && ![ string match $visibility "protected_undef" ] } {
+		setup_xfail "s390x-*-linux*"
+		if { [istarget sparc*-*-linux*] && [is_elf64 $tmpdir/mainnp.o] } {
+		    setup_xfail "sparc*-*-linux*"
+		}
+	    }
+	    setup_xfail "x86_64-*-linux*"
+	    if { ![istarget hppa*64*-*-linux*] } {
+		setup_xfail "hppa*-*-linux*"
+	    }
+
+	    visibility_test $visibility vnp "visibility ($visibility) (non PIC)" mainnp.o sh1np.o sh2np.o elfvsb
+
+	    # Test ELF shared library relocations with a non-zero load
+	    # address for the library.  Near as I can tell, the R_*_RELATIVE
+	    # relocations for various targets are broken in the case where
+	    # the load address is not zero (which is the default).
+	    if { [ string match $visibility "protected" ]
+		 || [ string match $visibility "protected_undef_def" ] } {
+		if [ string match $support_protected "no" ] {
+		    setup_xfail $target_triplet
+		}
+	    } else {
+		setup_xfail "*-*-sunos4*"
+		setup_xfail "*-*-linux*libc1"
+	    }
+	    if { [ string match $visibility "hidden_normal" ]
+		 || [ string match $visibility "hidden_weak" ]
+		 || [ string match $visibility "protected" ]
+		 || [ string match $visibility "protected_undef_def" ]
+		 || [ string match $visibility "protected_weak" ]
+		 || [ string match $visibility "normal" ] } {
+		setup_xfail "powerpc-*-linux*"
+		setup_xfail "s390x-*-linux*"
+		if { [istarget sparc*-*-linux*] && [is_elf64 $tmpdir/mainnp.o] } {
+		    setup_xfail "sparc*-*-linux*"
+		}
+	    }
+	    if { ![ string match $visibility "hidden_undef" ]
+		 && ![ string match $visibility "protected_undef" ] } {
+		setup_xfail "ia64-*-linux*"
+		setup_xfail "alpha*-*-linux*"
+		setup_xfail "mips*-*-linux*"
+	    }
+	    setup_xfail "x86_64-*-linux*"
+	    if { ![istarget hppa*64*-*-linux*] } {
+		setup_xfail "hppa*-*-linux*"
+	    }
+
+	    visibility_test $visibility vnp "visibility ($visibility) (non PIC, load offset)" \
+		mainnp.o sh1np.o sh2np.o elfvsb \
+		"-T $srcdir/$subdir/elf-offset.ld"
+	} }
+
+	# Now compile the code using -fpic.
+
+	if { ![ld_compile "$CC -g $CFLAGS $SHCFLAG $VSBCFLAG -DSHARED $picflag" $srcdir/$subdir/sh1.c $tmpdir/sh1p.o] 
+	    || ![ld_compile "$CC -g $CFLAGS $SHCFLAG $VSBCFLAG -DSHARED $picflag" $srcdir/$subdir/sh2.c $tmpdir/sh2p.o] } {
+	    unresolved "visibility ($visibility)"
+	} else {
+	    if { [ string match $visibility "protected" ]
+		 || [ string match $visibility "protected_undef_def" ] } {
+		if [ string match $support_protected "no" ] {
+		    setup_xfail $target_triplet
+		}
+	    }
+	    # SunOS can not compare function pointers correctly
+	    if [istarget "*-*-sunos4*"] {
+		visibility_test $visibility vp "visibility ($visibility)" mainnp.o sh1p.o sh2p.o sun4
+	    } else { if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+		visibility_test $visibility vp "visibility ($visibility)" mainnp.o sh1p.o sh2p.o xcoff
+	    } else {
+		visibility_test $visibility vp "visibility ($visibility)" mainnp.o sh1p.o sh2p.o elfvsb
+	    } }
+	}
+    }
+
+    # Now do the same tests again, but this time compile main.c PIC.
+    if ![ld_compile "$CC -g $CFLAGS $SHCFLAG $VSBCFLAG -DSHARED $picflag" $srcdir/$subdir/main.c $tmpdir/mainp.o] {
+	unresolved "visibility ($visibility) (PIC main, non PIC so)"
+	unresolved "visibility ($visibility) (PIC main)"
+    } else {
+	if { [file exists $tmpdir/sh1np.o ] && [ file exists $tmpdir/sh2np.o ] } {
+	    if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+		visibility_test $visibility vmpnp "visibility ($visibility) (PIC main, non PIC so)" mainp.o sh1np.o sh2np.o xcoff
+	    } else {
+		# SunOS non PIC shared libraries don't permit some cases of
+		# overriding.
+		if { [ string match $visibility "protected" ]
+		     || [ string match $visibility "protected_undef_def" ] } {
+		    if [ string match $support_protected "no" ] {
+			setup_xfail $target_triplet
+		    }
+		} else {
+		    setup_xfail "*-*-sunos4*"
+		}
+		if { ![ string match $visibility "hidden_undef" ]
+		     && ![ string match $visibility "protected_undef" ] } {
+		    setup_xfail "ia64-*-linux*"
+		    setup_xfail "alpha*-*-linux*"
+		}
+		if { ![ string match $visibility "hidden" ]
+		     && ![ string match $visibility "hidden_undef" ]
+		     && ![ string match $visibility "hidden_undef_def" ]
+		     && ![ string match $visibility "protected_undef" ] } {
+		    setup_xfail "s390x-*-linux*"
+		    if { [istarget sparc*-*-linux*] && [is_elf64 $tmpdir/mainp.o] } {
+			setup_xfail "sparc*-*-linux*"
+		    }
+		}
+		setup_xfail "x86_64-*-linux*"
+		if { ![istarget hppa*64*-*-linux*] } {
+		    setup_xfail "hppa*-*-linux*"
+		}
+
+		visibility_test $visibility vmpnp "visibility ($visibility) (PIC main, non PIC so)" mainp.o sh1np.o sh2np.o elfvsb
+	    }
+	} else {
+	    unresolved "visibility (PIC main, non PIC so)"
+	}
+
+	if { [file exists $tmpdir/sh1p.o ] && [ file exists $tmpdir/sh2p.o ] } {
+	    if { [ string match $visibility "protected" ]
+		 || [ string match $visibility "protected_undef_def" ] } {
+		if [ string match $support_protected "no" ] {
+		    setup_xfail $target_triplet
+		}
+	    }
+	    if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+		visibility_test $visibility vmpp "visibility ($visibility) (PIC main)" mainp.o sh1p.o sh2p.o xcoff
+	    } else {
+		visibility_test $visibility vmpp "visibility ($visibility) (PIC main)" mainp.o sh1p.o sh2p.o elfvsb
+	    }
+	} else {
+	    unresolved "visibility ($visibility) (PIC main)"
+	}
+    }
+}
+
+if [istarget mips*-*-*] {
+    set picflag ""
+} else {
+    # Unfortunately, the gcc argument is -fpic and the cc argument is
+    # -KPIC.  We have to try both.
+    set picflag "-fpic"
+    send_log "$CC $picflag\n"
+    verbose "$CC $picflag"
+    catch "exec $CC $picflag" exec_output
+    send_log "$exec_output\n"
+    verbose "--" "$exec_output"
+    if { [string match "*illegal option*" $exec_output] \
+	 || [string match "*option ignored*" $exec_output] \
+	 || [string match "*unrecognized option*" $exec_output] \
+	 || [string match "*passed to ld*" $exec_output] } {
+	if [istarget *-*-sunos4*] {
+	    set picflag "-pic"
+	} else {
+	    set picflag "-KPIC"
+	}
+    }
+}
+verbose "Using $picflag to compile PIC code"
+
+visibility_run hidden
+visibility_run hidden_normal
+visibility_run hidden_undef
+visibility_run hidden_undef_def
+visibility_run hidden_weak
+visibility_run protected
+visibility_run protected_undef
+visibility_run protected_undef_def
+visibility_run protected_weak
+visibility_run normal
+
+if { ![ld_compile "$CC -g $CFLAGS" $srcdir/$subdir/common.c tmpdir/common.o] } {
+    unresolved "common hidden symbol"
+} else {
+    if ![ld_simple_link $ld tmpdir/common "tmpdir/common.o"] {
+	fail "common hidden symbol"
+    } else {
+	pass "common hidden symbol"
+    }
+}
+
+if { ![ld_compile "$CC -g $CFLAGS" $srcdir/$subdir/test.c tmpdir/test.o] } {
+    unresolved "weak hidden symbol"
+} else {
+   if { ![ld_compile "$CC -g $CFLAGS -DSHARED $picflag" $srcdir/$subdir/sh3.c tmpdir/sh3.o] } {
+	unresolved "weak hidden symbol"
+    } else {
+	if ![ld_simple_link $ld tmpdir/sh3.so "-shared tmpdir/sh3.o"] {
+	    fail "weak hidden symbol"
+	} else {
+	    if ![ld_simple_link $ld tmpdir/weak "tmpdir/test.o tmpdir/sh3.o"] {
+		fail "weak hidden symbol DSO last"
+	    } else {
+		pass "weak hidden symbol DSO last"
+	    }
+	    if ![ld_simple_link $ld tmpdir/weak "tmpdir/sh3.so tmpdir/test.o"] {
+		fail "weak hidden symbol DSO first"
+	    } else {
+		pass "weak hidden symbol DSO first"
+	    }
+	}
+    }
+}
+
+if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+    # Remove the temporary directory.
+    catch "exec rm -rf $tmpdir" exec_status
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/hidden0.d b/binutils-2.19/ld/testsuite/ld-elfvsb/hidden0.d
new file mode 100644
index 0000000..46fc647
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/hidden0.d
@@ -0,0 +1,10 @@
+#source: define.s
+#source: undef.s
+#ld: -r
+#readelf: -s
+
+Symbol table '.symtab' contains .* entries:
+   Num:    Value[ 	]+Size Type    Bind   Vis      Ndx Name
+#...
+[ 	]*[0-9]+: [0-9a-fA-F]*     0 OBJECT  GLOBAL HIDDEN    . hidden
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/hidden1.d b/binutils-2.19/ld/testsuite/ld-elfvsb/hidden1.d
new file mode 100644
index 0000000..667f108
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/hidden1.d
@@ -0,0 +1,9 @@
+#source: undef.s
+#ld: -r
+#readelf: -s
+
+Symbol table '.symtab' contains .* entries:
+   Num:    Value[ 	]+Size Type    Bind   Vis      Ndx Name
+#...
+[ 	]*[0-9]+: [0-9a-fA-F]*     0 NOTYPE  GLOBAL HIDDEN  UND hidden
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/hidden2.d b/binutils-2.19/ld/testsuite/ld-elfvsb/hidden2.d
new file mode 100644
index 0000000..14b0b30
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/hidden2.d
@@ -0,0 +1,9 @@
+#source: hidden2.s
+#ld: -shared -T hidden2.ld
+#readelf: -Ds
+# It is also ok to remove this symbol, but we currently make it local.
+
+Symbol table for image:
+#...
+[ 	]*[0-9]+ +[0-9]+: [0-9a-fA-F]* +0  OBJECT  LOCAL HIDDEN +ABS foo
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/hidden2.ld b/binutils-2.19/ld/testsuite/ld-elfvsb/hidden2.ld
new file mode 100644
index 0000000..3c414db
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/hidden2.ld
@@ -0,0 +1,7 @@
+SECTIONS
+{
+  . = 0x1000;
+  PROVIDE (foo = .);
+  .data : { *(.data) }
+  .dynamic : { *(.dynamic) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/hidden2.s b/binutils-2.19/ld/testsuite/ld-elfvsb/hidden2.s
new file mode 100644
index 0000000..62f1107
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/hidden2.s
@@ -0,0 +1,5 @@
+	.data
+	.hidden foo
+	.global foo
+	.type foo,%object
+	.dc.a foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/internal0.d b/binutils-2.19/ld/testsuite/ld-elfvsb/internal0.d
new file mode 100644
index 0000000..a42ae02
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/internal0.d
@@ -0,0 +1,10 @@
+#source: define.s
+#source: undef.s
+#ld: -r
+#readelf: -s
+
+Symbol table '.symtab' contains .* entries:
+   Num:    Value[ 	]+Size Type    Bind   Vis      Ndx Name
+#...
+[ 	]*[0-9]+: [0-9a-fA-F]*     0 OBJECT  GLOBAL INTERNAL    . internal
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/internal1.d b/binutils-2.19/ld/testsuite/ld-elfvsb/internal1.d
new file mode 100644
index 0000000..c110ac6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/internal1.d
@@ -0,0 +1,9 @@
+#source: undef.s
+#ld: -r
+#readelf: -s
+
+Symbol table '.symtab' contains .* entries:
+   Num:    Value[ 	]+Size Type    Bind   Vis      Ndx Name
+#...
+[ 	]*[0-9]+: [0-9a-fA-F]*     0 NOTYPE  GLOBAL INTERNAL  UND internal
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/main.c b/binutils-2.19/ld/testsuite/ld-elfvsb/main.c
new file mode 100644
index 0000000..b498d43
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/main.c
@@ -0,0 +1,306 @@
+#ifdef PROTECTED_CHECK
+#include <features.h>
+#include <stdio.h>
+
+int
+main (void)
+{
+#if defined (__GLIBC__) && (__GLIBC__ > 2 \
+			    || (__GLIBC__ == 2 \
+				&&  __GLIBC_MINOR__ >= 2))
+  puts ("yes");
+#else
+  puts ("no");
+#endif
+  return 0;
+}
+#else
+/* This is the main program for the shared library test.  */
+
+#include <stdio.h>
+
+int mainvar = 1;
+int overriddenvar = 2;
+extern int shlibvar1;
+
+extern int shlib_mainvar ();
+extern int shlib_overriddenvar ();
+extern int shlib_shlibvar1 ();
+extern int shlib_shlibvar2 ();
+extern int shlib_shlibcall ();
+extern int shlib_maincall ();
+extern int shlib_checkfunptr1 ();
+extern int shlib_checkfunptr2 ();
+extern int (*shlib_getfunptr1 ()) ();
+extern int (*shlib_getfunptr2 ()) ();
+extern int shlib_check ();
+extern int shlib_shlibcall2 ();
+extern int visibility_check ();
+extern int visibility_checkfunptr ();
+extern void *visibility_funptr ();
+extern int visibility_checkvar ();
+extern int visibility_checkvarptr ();
+extern int visibility_varval ();
+extern void *visibility_varptr ();
+extern int shlib_visibility_checkcom ();
+extern int shlib_visibility_checkweak ();
+
+int shlib_visibility_com = 1;
+
+int shlib_visibility_var_weak = 1;
+
+int
+shlib_visibility_func_weak ()
+{
+  return 1;
+}
+
+#ifdef HIDDEN_WEAK_TEST
+#define WEAK_TEST
+#endif
+
+#ifdef PROTECTED_WEAK_TEST
+#define WEAK_TEST
+#endif
+
+#ifdef PROTECTED_UNDEF_TEST
+#define PROTECTED_TEST
+#endif
+
+#ifndef WEAK_TEST
+extern int visibility ();
+extern int visibility_var;
+#endif
+
+#if !defined (HIDDEN_TEST) && defined (PROTECTED_TEST)
+int
+visibility (void)
+{
+  return 1;
+}
+
+static int
+main_visibility_check (void)
+{
+  return ((int (*) (void)) visibility_funptr ()) != visibility;
+}
+
+int visibility_var = 1;
+
+static int
+main_visibility_checkvar (void)
+{
+  return visibility_varval () != visibility_var
+	 && visibility_varptr () != &visibility_var;
+}
+
+#ifndef PROTECTED_UNDEF_TEST
+int shared_data = 1;
+asm (".protected shared_data");
+
+int
+shared_func (void)
+{
+  return 1;
+}
+
+asm (".protected shared_func");
+
+extern int * shared_data_p ();
+typedef int (*func) ();
+extern func shared_func_p ();
+#endif
+#else
+static int
+main_visibility_check (void)
+{
+#ifdef WEAK_TEST
+  return visibility_funptr () == NULL;
+#else
+  return ((int (*) (void)) visibility_funptr ()) == visibility;
+#endif
+}
+
+static int
+main_visibility_checkvar (void)
+{
+#ifdef WEAK_TEST
+  return visibility_varval () == 0
+	 && visibility_varptr () == NULL;
+#else
+  return visibility_varval () == visibility_var
+	 && visibility_varptr () == &visibility_var;
+#endif
+}
+#endif
+
+/* This function is called by the shared library.  */
+
+int
+main_called (void)
+{
+  return 6;
+}
+
+/* This function overrides a function in the shared library.  */
+
+int
+shlib_overriddencall2 (void)
+{
+  return 8;
+}
+
+#ifdef HIDDEN_NORMAL_TEST
+int visibility_com;
+asm (".hidden visibility_com");
+
+int
+main_visibility_checkcom (void)
+{
+  return visibility_com == 0;
+}
+
+int
+main_visibility_checkweak (void)
+{
+  return 1;
+}
+#elif defined (HIDDEN_WEAK_TEST)
+int
+main_visibility_checkcom (void)
+{
+  return 1;
+}
+
+#pragma weak visibility_undef_var_weak
+extern int visibility_undef_var_weak;
+asm (".hidden visibility_undef_var_weak");
+
+#pragma weak visibility_undef_func_weak
+extern int visibility_undef_func_weak ();
+asm (".hidden visibility_undef_func_weak");
+
+#pragma weak visibility_var_weak
+extern int visibility_var_weak;
+asm (".hidden visibility_var_weak");
+
+#pragma weak visibility_func_weak
+extern int visibility_func_weak ();
+asm (".hidden visibility_func_weak");
+
+int
+main_visibility_checkweak ()
+{
+  return &visibility_undef_var_weak == NULL
+	 && &visibility_undef_func_weak == NULL
+	 && &visibility_func_weak == NULL
+	 && &visibility_var_weak == NULL;
+}
+#elif defined (HIDDEN_UNDEF_TEST)
+extern int visibility_def;
+asm (".hidden visibility_def");
+extern int visibility_func ();
+asm (".hidden visibility_func");
+
+int
+main_visibility_checkcom (void)
+{
+  return & visibility_def != NULL && visibility_def == 2;
+}
+
+int
+main_visibility_checkweak (void)
+{
+  return & visibility_func != NULL && visibility_func () == 2;
+}
+#else
+int
+main_visibility_checkcom (void)
+{
+  return 1;
+}
+
+int
+main_visibility_checkweak (void)
+{
+  return 1;
+}
+#endif
+
+int
+main (void)
+{
+  int (*p) ();
+  int ret = 0;
+
+  printf ("mainvar == %d\n", mainvar);
+  printf ("overriddenvar == %d\n", overriddenvar);
+  printf ("shlibvar1 == %d\n", shlibvar1);
+#ifndef XCOFF_TEST
+  printf ("shlib_mainvar () == %d\n", shlib_mainvar ());
+  printf ("shlib_overriddenvar () == %d\n", shlib_overriddenvar ());
+#endif
+  printf ("shlib_shlibvar1 () == %d\n", shlib_shlibvar1 ());
+  printf ("shlib_shlibvar2 () == %d\n", shlib_shlibvar2 ());
+  printf ("shlib_shlibcall () == %d\n", shlib_shlibcall ());
+#ifndef XCOFF_TEST
+  printf ("shlib_shlibcall2 () == %d\n", shlib_shlibcall2 ());
+  printf ("shlib_maincall () == %d\n", shlib_maincall ());
+#endif
+  printf ("main_called () == %d\n", main_called ());
+  printf ("shlib_checkfunptr1 (shlib_shlibvar1) == %d\n",
+	  shlib_checkfunptr1 (shlib_shlibvar1));
+#ifndef XCOFF_TEST
+  printf ("shlib_checkfunptr2 (main_called) == %d\n",
+	  shlib_checkfunptr2 (main_called));
+#endif
+  p = shlib_getfunptr1 ();
+  printf ("shlib_getfunptr1 () ");
+  if (p == shlib_shlibvar1)
+    printf ("==");
+  else
+    printf ("!=");
+  printf (" shlib_shlibvar1\n");
+#ifndef XCOFF_TEST
+  p = shlib_getfunptr2 ();
+  printf ("shlib_getfunptr2 () ");
+  if (p == main_called)
+    printf ("==");
+  else
+    printf ("!=");
+  printf (" main_called\n");
+#endif
+  printf ("shlib_check () == %d\n", shlib_check ());
+  printf ("visibility_check () == %d\n", visibility_check ());
+  printf ("visibility_checkfunptr () == %d\n",
+	  visibility_checkfunptr ());
+  printf ("main_visibility_check () == %d\n", main_visibility_check ());
+  printf ("visibility_checkvar () == %d\n", visibility_checkvar ());
+  printf ("visibility_checkvarptr () == %d\n",
+	  visibility_checkvarptr ());
+  printf ("main_visibility_checkvar () == %d\n",
+	  main_visibility_checkvar ());
+  printf ("main_visibility_checkcom () == %d\n",
+	  main_visibility_checkcom ());
+  printf ("shlib_visibility_checkcom () == %d\n",
+	  shlib_visibility_checkcom ());
+  printf ("main_visibility_checkweak () == %d\n",
+	  main_visibility_checkweak ());
+  printf ("shlib_visibility_checkweak () == %d\n",
+	  shlib_visibility_checkweak ());
+
+#if !defined (PROTECTED_UNDEF_TEST) && defined (PROTECTED_TEST)
+  if (&shared_data != shared_data_p ())
+    ret = 1;
+  p = shared_func_p ();
+  if (shared_func != p)
+    ret = 1;
+  if (shared_data != *shared_data_p ())
+    ret = 1;
+  if (shared_func () != (*p) () )
+    ret = 1;
+#endif
+
+  return ret;
+}
+#endif
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/protected0.d b/binutils-2.19/ld/testsuite/ld-elfvsb/protected0.d
new file mode 100644
index 0000000..48b7885
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/protected0.d
@@ -0,0 +1,10 @@
+#source: define.s
+#source: undef.s
+#ld: -r
+#readelf: -s
+
+Symbol table '.symtab' contains .* entries:
+   Num:    Value[ 	]+Size Type    Bind   Vis      Ndx Name
+#...
+[ 	]*[0-9]+: [0-9a-fA-F]*     0 OBJECT  GLOBAL PROTECTED    . protected
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/protected1.d b/binutils-2.19/ld/testsuite/ld-elfvsb/protected1.d
new file mode 100644
index 0000000..2f4931a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/protected1.d
@@ -0,0 +1,9 @@
+#source: undef.s
+#ld: -r
+#readelf: -s
+
+Symbol table '.symtab' contains .* entries:
+   Num:    Value[ 	]+Size Type    Bind   Vis      Ndx Name
+#...
+[ 	]*[0-9]+: [0-9a-fA-F]*     0 NOTYPE  GLOBAL PROTECTED  UND protected
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/sh1.c b/binutils-2.19/ld/testsuite/ld-elfvsb/sh1.c
new file mode 100644
index 0000000..b275424
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/sh1.c
@@ -0,0 +1,421 @@
+#ifndef NULL
+#define NULL ((void *) 0)
+#endif
+
+/* This is part of the shared library ld test.  This file becomes part
+   of a shared library.  */
+
+/* This variable is supplied by the main program.  */
+#ifndef XCOFF_TEST
+extern int mainvar;
+#endif
+
+/* This variable is defined in the shared library, and overridden by
+   the main program.  */
+#ifndef XCOFF_TEST
+#ifdef SHARED
+/* SHARED is defined if we are compiling with -fpic/-fPIC.  */
+int overriddenvar = -1;
+#else
+/* Without -fpic, newer versions of gcc assume that we are not
+   compiling for a shared library, and thus that overriddenvar is
+   local.  */
+extern int overriddenvar;
+#endif
+#endif
+
+/* This variable is defined in the shared library.  */
+int shlibvar1 = 3;
+
+/* This variable is defined by another object in the shared library.  */
+extern int shlibvar2;
+
+/* These functions return the values of the above variables as seen in
+   the shared library.  */
+
+#ifndef XCOFF_TEST
+int
+shlib_mainvar ()
+{
+  return mainvar;
+}
+#endif
+
+#ifndef XCOFF_TEST
+int
+shlib_overriddenvar ()
+{
+  return overriddenvar;
+}
+#endif
+
+int
+shlib_shlibvar1 ()
+{
+  return shlibvar1;
+}
+
+int
+shlib_shlibvar2 ()
+{
+  return shlibvar2;
+}
+
+/* This function calls a function defined by another object in the
+   shared library.  */
+
+extern int shlib_shlibcalled ();
+
+int
+shlib_shlibcall ()
+{
+  return shlib_shlibcalled ();
+}
+
+#ifndef XCOFF_TEST
+/* This function calls a function defined in this object in the shared
+   library.  The main program will override the called function.  */
+
+extern int shlib_overriddencall2 ();
+
+int
+shlib_shlibcall2 ()
+{
+  return shlib_overriddencall2 ();
+}
+
+#ifdef SHARED
+int
+shlib_overriddencall2 ()
+{
+  return 7;
+}
+#endif
+#endif
+
+/* This function calls a function defined by the main program.  */
+
+#ifndef XCOFF_TEST
+extern int main_called ();
+
+int
+shlib_maincall ()
+{
+  return main_called ();
+}
+#endif
+
+/* This function is passed a function pointer to shlib_mainvar.  It
+   confirms that the pointer compares equally.  */
+
+int 
+shlib_checkfunptr1 (p)
+     int (*p) ();
+{
+  return p == shlib_shlibvar1;
+}
+
+/* This function is passed a function pointer to main_called.  It
+   confirms that the pointer compares equally.  */
+
+#ifndef XCOFF_TEST
+int
+shlib_checkfunptr2 (p)
+     int (*p) ();
+{
+  return p == main_called;
+}
+#endif
+
+/* This function returns a pointer to shlib_mainvar.  */
+
+int
+(*shlib_getfunptr1 ()) ()
+{
+  return shlib_shlibvar1;
+}
+
+/* This function returns a pointer to main_called.  */
+
+#ifndef XCOFF_TEST
+int
+(*shlib_getfunptr2 ()) ()
+{
+  return main_called;
+}
+#endif
+
+/* This function makes sure that constant data and local functions
+   work.  */
+
+#ifndef __STDC__
+#define const
+#endif
+
+static int i = 6;
+static const char *str = "Hello, world\n";
+
+int
+shlib_check ()
+{
+  const char *s1, *s2;
+
+  if (i != 6)
+    return 0;
+
+  /* To isolate the test, don't rely on any external functions, such
+     as strcmp.  */
+  s1 = "Hello, world\n";
+  s2 = str;
+  while (*s1 != '\0')
+    if (*s1++ != *s2++)
+      return 0;
+  if (*s2 != '\0')
+    return 0;
+
+  if (shlib_shlibvar1 () != 3)
+    return 0;
+
+  return 1;
+}
+
+#ifdef HIDDEN_WEAK_TEST
+#define HIDDEN_UNDEF_TEST
+#define WEAK_TEST
+#endif
+
+#ifdef PROTECTED_WEAK_TEST
+#define PROTECTED_UNDEF_TEST
+#define WEAK_TEST
+#endif
+
+#if defined (HIDDEN_UNDEF_TEST) || defined (PROTECTED_UNDEF_TEST)
+#ifdef WEAK_TEST
+#pragma weak visibility
+#endif
+extern int visibility ();
+#else
+int
+visibility ()
+{
+  return 2;
+}
+#endif
+
+#ifdef HIDDEN_NORMAL_TEST
+asm (".hidden visibility_normal");
+
+int
+visibility_normal ()
+{
+  return 2;
+}
+#endif
+
+int
+visibility_checkfunptr ()
+{
+#ifdef WEAK_TEST
+  return 1;
+#else
+#ifdef HIDDEN_NORMAL_TEST
+  int (*v) () = visibility_normal;
+#else
+  int (*v) () = visibility;
+#endif
+  return (*v) () == 2;
+#endif
+}
+
+int
+visibility_check ()
+{
+#ifdef WEAK_TEST
+  if (&visibility)
+    return visibility () == 1;
+  else
+    return 1;
+#else
+#ifdef HIDDEN_NORMAL_TEST
+  return visibility_normal () == 2;
+#else
+  return visibility () == 2;
+#endif
+#endif
+}
+
+void *
+visibility_funptr ()
+{
+#ifdef WEAK_TEST
+  if (&visibility == NULL)
+    return NULL;
+  else
+#endif
+    return visibility;
+}
+
+#if defined (HIDDEN_UNDEF_TEST) || defined (PROTECTED_UNDEF_TEST)
+#ifdef WEAK_TEST
+#pragma weak visibility_var
+#endif
+extern int visibility_var;
+#else
+int visibility_var = 2;
+#endif
+
+#ifdef HIDDEN_NORMAL_TEST
+asm (".hidden visibility_var_normal");
+
+int visibility_var_normal = 2;
+#endif
+
+int
+visibility_checkvarptr ()
+{
+#ifdef WEAK_TEST
+  if (&visibility_var)
+    return visibility_var == 1;
+  else
+    return 1;
+#else
+#ifdef HIDDEN_NORMAL_TEST
+  int *v = &visibility_var_normal;
+#else
+  int *v = &visibility_var;
+#endif
+  return *v == 2;
+#endif
+}
+
+int
+visibility_checkvar ()
+{
+#ifdef WEAK_TEST
+  return 1;
+#else
+#ifdef HIDDEN_NORMAL_TEST
+  return visibility_var_normal == 2;
+#else
+  return visibility_var == 2;
+#endif
+#endif
+}
+
+void *
+visibility_varptr ()
+{
+#ifdef WEAK_TEST
+  if (&visibility_var == NULL)
+    return NULL;
+  else
+#endif
+    return &visibility_var;
+}
+
+int
+visibility_varval ()
+{
+#ifdef WEAK_TEST
+  if (&visibility_var == NULL)
+    return 0;
+  else
+#endif
+    return visibility_var;
+}
+
+#if defined (HIDDEN_TEST) || defined (HIDDEN_UNDEF_TEST)
+asm (".hidden visibility");
+asm (".hidden visibility_var");
+#else
+#if defined (PROTECTED_TEST) || defined (PROTECTED_UNDEF_TEST) || defined (PROTECTED_WEAK_TEST)
+asm (".protected visibility");
+asm (".protected visibility_var");
+#endif
+#endif
+
+#ifdef HIDDEN_NORMAL_TEST
+int shlib_visibility_com;
+asm (".hidden shlib_visibility_com");
+
+int
+shlib_visibility_checkcom ()
+{
+  return shlib_visibility_com == 0;
+}
+
+int
+shlib_visibility_checkweak ()
+{
+  return 1;
+}
+#elif defined (HIDDEN_WEAK_TEST)
+#pragma weak shlib_visibility_undef_var_weak
+extern int shlib_visibility_undef_var_weak;
+asm (".hidden shlib_visibility_undef_var_weak");
+
+#pragma weak shlib_visibility_undef_func_weak
+extern int shlib_visibility_undef_func_weak ();
+asm (".hidden shlib_visibility_undef_func_weak");
+
+#pragma weak shlib_visibility_var_weak
+extern int shlib_visibility_var_weak;
+asm (".hidden shlib_visibility_var_weak");
+
+#pragma weak shlib_visibility_func_weak
+extern int shlib_visibility_func_weak ();
+asm (".hidden shlib_visibility_func_weak");
+
+int
+shlib_visibility_checkcom ()
+{
+  return 1;
+}
+
+int
+shlib_visibility_checkweak ()
+{
+  return &shlib_visibility_undef_var_weak == NULL
+	 && &shlib_visibility_undef_func_weak == NULL
+	 && &shlib_visibility_func_weak == NULL
+	 && &shlib_visibility_var_weak == NULL;
+}
+#else
+int
+shlib_visibility_checkcom ()
+{
+  return 1;
+}
+
+int
+shlib_visibility_checkweak ()
+{
+  return 1;
+}
+#endif
+
+#ifdef PROTECTED_TEST
+#ifdef SHARED
+int shared_data = 100;
+#else
+extern int shared_data;
+#endif
+ 
+int *
+shared_data_p ()
+{
+  return &shared_data;
+}
+ 
+int
+shared_func ()
+{
+  return 100;
+}
+ 
+void *
+shared_func_p ()
+{
+  return shared_func;
+}
+#endif
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/sh2.c b/binutils-2.19/ld/testsuite/ld-elfvsb/sh2.c
new file mode 100644
index 0000000..e9a9687
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/sh2.c
@@ -0,0 +1,61 @@
+/* This is part of the shared library ld test.  This file becomes part
+   of a shared library.  */
+
+/* This variable is defined here, and referenced by another file in
+   the shared library.  */
+int shlibvar2 = 4;
+
+/* This variable is defined here, and shouldn't be used to resolve a
+   reference with non-default visibility in another shared library.  */
+int visibility_com = 2;
+
+/* This function is called by another file in the shared library.  */
+
+int
+shlib_shlibcalled ()
+{
+  return 5;
+}
+
+#ifdef DSO_DEFINE_TEST
+int
+visibility ()
+{
+  return 2;
+}
+
+int visibility_var = 2;
+
+int visibility_def = 2;
+
+int
+visibility_func ()
+{
+  return 2;
+}
+#endif
+
+#ifdef HIDDEN_WEAK_TEST
+int visibility_var_weak = 2;
+
+int
+visibility_func_weak ()
+{
+  return 2;
+}
+#endif
+
+#ifndef SHARED
+# ifndef XCOFF_TEST
+int overriddenvar = -1;
+
+int
+shlib_overriddencall2 ()
+{
+  return 7;
+}
+# endif
+# ifdef PROTECTED_TEST
+int shared_data = 100;
+# endif
+#endif
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/sh3.c b/binutils-2.19/ld/testsuite/ld-elfvsb/sh3.c
new file mode 100644
index 0000000..a6d5dc8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/sh3.c
@@ -0,0 +1,7 @@
+int main_hidden_data = 1;
+
+int
+main_hidden_func ()
+{
+  return 1;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/test.c b/binutils-2.19/ld/testsuite/ld-elfvsb/test.c
new file mode 100644
index 0000000..ca23d38
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/test.c
@@ -0,0 +1,26 @@
+#pragma weak main_hidden_data
+extern int main_hidden_data;
+asm (".hidden main_hidden_data");
+ 
+#pragma weak main_hidden_func
+extern int main_hidden_func ();
+asm (".hidden main_hidden_func");
+
+int
+_start (void)
+{
+  int ret = 0;
+
+  if (&main_hidden_data != 0)
+    ret = 1;
+  if (main_hidden_func != 0)
+    ret = 1;
+
+  return ret;
+}
+
+int
+__start (void)
+{
+  return _start ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfvsb/undef.s b/binutils-2.19/ld/testsuite/ld-elfvsb/undef.s
new file mode 100644
index 0000000..5b99d6f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfvsb/undef.s
@@ -0,0 +1,3 @@
+	.protected protected
+	.hidden hidden
+	.internal internal
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/bar.c b/binutils-2.19/ld/testsuite/ld-elfweak/bar.c
new file mode 100644
index 0000000..6317518
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/bar.c
@@ -0,0 +1,16 @@
+#include <stdio.h>
+
+extern void foo ();
+extern void foobar ();
+
+void
+foo ()
+{
+  printf ("strong foo\n");
+}
+
+void
+foobar ()
+{
+  foo ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/bar1a.c b/binutils-2.19/ld/testsuite/ld-elfweak/bar1a.c
new file mode 100644
index 0000000..daf0c58
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/bar1a.c
@@ -0,0 +1,26 @@
+#include <stdio.h>
+
+extern int deallocate_foo;
+
+extern int * bar ();
+extern int * foo ();
+extern void abort ();
+extern void foobar ();
+
+void
+foobar ()
+{
+  if (&deallocate_foo != bar () || &deallocate_foo != foo ())
+    abort ();
+
+  if (deallocate_foo)
+    printf ("weak deallocate_foo\n");
+  else
+    printf ("strong deallocate_foo\n");
+}
+
+int *
+bar()
+{
+  return &deallocate_foo;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/bar1b.c b/binutils-2.19/ld/testsuite/ld-elfweak/bar1b.c
new file mode 100644
index 0000000..bab68ab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/bar1b.c
@@ -0,0 +1,7 @@
+int deallocate_foo = 0;
+
+int *
+bar()
+{
+  return &deallocate_foo;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/bar1c.c b/binutils-2.19/ld/testsuite/ld-elfweak/bar1c.c
new file mode 100644
index 0000000..901f065
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/bar1c.c
@@ -0,0 +1,7 @@
+int deallocate_foo;
+
+int *
+bar()
+{
+  return &deallocate_foo;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/dso.dsym b/binutils-2.19/ld/testsuite/ld-elfweak/dso.dsym
new file mode 100644
index 0000000..be1b186
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/dso.dsym
@@ -0,0 +1 @@
+[0-9a-f]*[ 	]+g[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+(Base[ 	]+|[ 	]*)(0x[0-9a-f]+|)[ 	]*foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/dsodata.dsym b/binutils-2.19/ld/testsuite/ld-elfweak/dsodata.dsym
new file mode 100644
index 0000000..2b1f934
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/dsodata.dsym
@@ -0,0 +1,2 @@
+[0-9a-f]*[ 	]+g[ 	]+DO[ 	]+.(s|)(data|bss)[	]+[0-9a-f]*[ 	]+(Base[ 	]+|[ 	]*)deallocate_foo
+[0-9a-f]*[ 	]+g[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+(Base[ 	]+|[ 	]*)(0x[0-9a-f]*|)[ 	]*foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/dsow.dsym b/binutils-2.19/ld/testsuite/ld-elfweak/dsow.dsym
new file mode 100644
index 0000000..cc36c6f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/dsow.dsym
@@ -0,0 +1 @@
+[0-9a-f]*[ 	]+w[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+(Base[ 	]+|[ 	]*)(0x[0-9a-f]+|)[ 	]*foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/dsowdata.dsym b/binutils-2.19/ld/testsuite/ld-elfweak/dsowdata.dsym
new file mode 100644
index 0000000..e0f579a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/dsowdata.dsym
@@ -0,0 +1 @@
+[0-9a-f]*[ 	]+w[ 	]+DO[ 	]+.(s|)data[	]+[0-9a-f]*[ 	]+(Base[ 	]+|[ 	]*)deallocate_foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/elfweak.exp b/binutils-2.19/ld/testsuite/ld-elfweak/elfweak.exp
new file mode 100644
index 0000000..fb913c5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/elfweak.exp
@@ -0,0 +1,501 @@
+# Expect script for ld-weak tests
+#   Copyright 2001, 2002, 2003, 2004, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by H.J. Lu (hjl@gnu.org)
+#	     Eric Youngdale (eric@andante.jic.com)
+#
+
+# This test can only be run if ld generates native executables.
+if ![isnative] then {return}
+
+# This test can only be run on a couple of ELF platforms.
+# Square bracket expressions seem to confuse istarget.
+# This is similar to the test that is used in ld-shared, BTW.
+if {    ![istarget alpha*-*-linux*] \
+     && ![istarget arm*-*-linux*] \
+     && ![istarget hppa*64*-*-hpux*] \
+     && ![istarget hppa*-*-linux*] \
+     && ![istarget i?86-*-sysv4*] \
+     && ![istarget i?86-*-unixware] \
+     && ![istarget i?86-*-elf*] \
+     && ![istarget i?86-*-linux*] \
+     && ![istarget ia64-*-elf*] \
+     && ![istarget ia64-*-linux*] \
+     && ![istarget m68k-*-linux*] \
+     && ![istarget mips*-*-irix5*] \
+     && ![istarget mips*-*-linux*] \
+     && ![istarget powerpc-*-elf*] \
+     && ![istarget powerpc-*-linux*] \
+     && ![istarget powerpc-*-sysv4*] \
+     && ![istarget sh\[34\]*-*-linux*] \
+     && ![istarget sparc*-*-elf] \
+     && ![istarget sparc*-*-solaris2*] \
+     && ![istarget sparc*-*-linux*] } {
+    return
+}
+
+if { [istarget i?86-*-linux*aout*] \
+     || [istarget i?86-*-linux*oldld*] \
+     || [istarget m68k-*-linux*aout*] } {
+    return
+}
+
+if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+    return
+}
+
+set diff diff
+set tmpdir tmpdir
+set DOBJDUMP_FLAGS --dynamic-syms
+set SOBJDUMP_FLAGS --syms
+set shared --shared
+
+#
+# objdump_symstuff
+#	Dump non-dynamic symbol stuff and make sure that it is sane.
+#
+proc objdump_symstuff { objdump object expectfile } {
+    global SOBJDUMP_FLAGS
+    global version_output
+    global diff
+    global tmpdir
+
+    if ![info exists SOBJDUMP_FLAGS] { set SOBJDUMP_FLAGS "" }
+
+    verbose -log "$objdump $SOBJDUMP_FLAGS $object | grep foo$  > $tmpdir/objdump.out"
+
+    catch "exec $objdump $SOBJDUMP_FLAGS $object | grep foo$  > $tmpdir/objdump.out" exec_output
+    set exec_output [prune_warnings $exec_output]
+    if [string match "" $exec_output] then {
+
+# Now do a line-by-line comparison to effectively diff the darned things
+# The stuff coming from the expectfile is actually a regex, so we can
+# skip over the actual addresses and so forth.  This is currently very
+# simpleminded - it expects a one-to-one correspondence in terms of line
+# numbers.
+
+	if [file exists $expectfile] then {
+	    set file_a [open $expectfile r]
+	} else {
+	    perror "$expectfile doesn't exist"
+	    return 0
+	}
+	
+	if [file exists $tmpdir/objdump.out] then {
+	    set file_b [open $tmpdir/objdump.out r]
+	} else {
+	    perror "$tmpdir/objdump.out doesn't exist"
+	    return 0
+	}
+
+	verbose "# Diff'ing: $expectfile $tmpdir/objdump.out" 2
+
+	set eof -1
+	set differences 0
+
+	while { [gets $file_a line] != $eof } {
+	    if [regexp "^#.*$" $line] then {
+		continue
+	    } else {
+		lappend list_a $line
+	    }
+	}
+	close $file_a
+
+	while { [gets $file_b line] != $eof } {
+	    if [regexp "^#.*$" $line] then {
+		continue
+	    } else {
+		lappend list_b $line
+	    }
+	}
+	close $file_b
+	
+	for { set i 0 } { $i < [llength $list_a] } { incr i } {
+	    set line_a [lindex $list_a $i]
+	    set line_b [lindex $list_b $i]
+	    
+
+	    verbose "\t$expectfile: $i: $line_a" 3
+	    verbose "\t/tmp/objdump.out: $i: $line_b" 3
+	    if [regexp $line_a $line_b] then {
+		continue
+	    } else {
+		verbose -log "\t$expectfile: $i: $line_a"
+		verbose -log "\t$tmpdir/objdump.out: $i: $line_b"
+		
+		return 0
+	    }
+	}
+	
+	if { [llength $list_a] != [llength $list_b] } {
+	    verbose -log "Line count"
+	    return 0
+	}
+	
+	if $differences<1 then {
+	    return 1
+	}
+	
+	return 0
+    } else {
+	verbose -log "$exec_output"
+	return 0
+    }
+
+}
+
+#
+# objdump_dymsymstuff
+#	Dump dynamic symbol stuff and make sure that it is sane.
+#
+proc objdump_dynsymstuff { objdump object expectfile } {
+    global DOBJDUMP_FLAGS
+    global version_output
+    global diff
+    global tmpdir
+
+    if ![info exists DOBJDUMP_FLAGS] { set DOBJDUMP_FLAGS "" }
+
+    verbose -log "$objdump $DOBJDUMP_FLAGS $object | grep foo$ > $tmpdir/objdump.out"
+
+    catch "exec $objdump $DOBJDUMP_FLAGS $object | grep foo$ > $tmpdir/objdump.out" exec_output
+    set exec_output [prune_warnings $exec_output]
+    if [string match "" $exec_output] then {
+
+# Now do a line-by-line comparison to effectively diff the darned things
+# The stuff coming from the expectfile is actually a regex, so we can
+# skip over the actual addresses and so forth.  This is currently very
+# simpleminded - it expects a one-to-one correspondence in terms of line
+# numbers.
+
+	if [file exists $expectfile] then {
+	    set file_a [open $expectfile r]
+	} else {
+	    warning "$expectfile doesn't exist"
+	    return 0
+	}
+	
+	if [file exists $tmpdir/objdump.out] then {
+	    set file_b [open $tmpdir/objdump.out r]
+	} else {
+	    fail "$tmpdir/objdump.out doesn't exist"
+	    return 0
+	}
+
+	verbose "# Diff'ing: $expectfile $tmpdir/objdump.out" 2
+
+	set eof -1
+	set differences 0
+
+	while { [gets $file_a line] != $eof } {
+	    if [regexp "^#.*$" $line] then {
+		continue
+	    } else {
+		lappend list_a $line
+	    }
+	}
+	close $file_a
+
+	while { [gets $file_b line] != $eof } {
+	    if [regexp "^#.*$" $line] then {
+		continue
+	    } else {
+		lappend list_b $line
+	    }
+	}
+	close $file_b
+	
+	for { set i 0 } { $i < [llength $list_b] } { incr i } {
+	    set line_b [lindex $list_b $i]
+	    
+# The tests are rigged so that we should never export a symbol with the
+# word 'hide' in it.  Thus we just search for it, and bail if we find it.
+	    if [regexp "hide" $line_b] then {
+		verbose -log "\t$tmpdir/objdump.out: $i: $line_b"
+		
+		return 0
+	    }
+
+	    verbose "\t$expectfile: $i: $line_b" 3
+
+	    # We can't assume that the sort is consistent across
+	    # systems, so we must check each regexp.  When we find a
+	    # regexp, we null it out, so we don't match it twice.
+	    for { set j 0 } { $j < [llength $list_a] } { incr j } {
+		set line_a [lindex $list_a $j]
+
+		if [regexp $line_a $line_b] then {
+		    lreplace $list_a $j $j "CAN NOT MATCH"
+		    break
+		}
+	    }
+
+	    if { $j >= [llength $list_a] } {
+		verbose -log "\t$tmpdir/objdump.out: $i: $line_b"
+		
+		return 0
+	    }
+	}
+	
+	if { [llength $list_a] != [llength $list_b] } {
+	    verbose -log "Line count"
+	    return 0
+	}
+	
+	if $differences<1 then {
+	    return 1
+	}
+	
+	return 0
+    } else {
+	verbose -log "$exec_output"
+	return 0
+    }
+
+}
+
+proc build_lib {test libname objs dynsymexp} {
+    global CC
+    global objdump
+    global tmpdir
+    global shared
+    global srcdir
+    global subdir
+
+    set files ""
+    foreach obj $objs {
+      set files "$files $tmpdir/$obj"
+    }
+
+    if {![ld_simple_link $CC $tmpdir/$libname.so "$shared $files"]} {
+	fail $test
+	return
+    }
+
+    if {![string match "" $dynsymexp] \
+	&& ![objdump_dynsymstuff $objdump $tmpdir/$libname.so $srcdir/$subdir/$dynsymexp]} {
+	fail $test
+	return
+    }
+    pass $test
+}
+
+proc build_exec { test execname objs flags dat dynsymexp symexp} {
+    global CC
+    global objdump
+    global tmpdir
+    global shared
+    global srcdir
+    global subdir
+    global exec_output
+
+    set files ""
+    foreach obj $objs {
+      set files "$files $tmpdir/$obj"
+    }
+
+    if {![ld_simple_link $CC $tmpdir/$execname "$flags $files"]} {
+	fail "$test"
+	return
+    }
+
+    if {![string match "" $dynsymexp]} then {
+        if {![objdump_dynsymstuff $objdump $tmpdir/$execname $srcdir/$subdir/$dynsymexp]} {
+	    fail $test
+	    return
+	}
+    }
+
+    if {![string match "" $symexp]} then {
+        if {![objdump_symstuff $objdump $tmpdir/$execname $srcdir/$subdir/$symexp]} {
+	    fail $test
+	    return
+	}
+    }
+
+    # Run the resulting program
+    send_log "$tmpdir/$execname >$tmpdir/$execname.out\n"
+    verbose "$tmpdir/$execname >$tmpdir/$execname.out"
+    catch "exec $tmpdir/$execname >$tmpdir/$execname.out" exec_output
+    if ![string match "" $exec_output] then {
+	send_log "$exec_output\n"
+	verbose "$exec_output"
+	fail $test
+	return
+    }
+
+    send_log "diff $tmpdir/$execname.out $srcdir/$subdir/$dat.dat\n"
+    verbose "diff $tmpdir/$execname.out $srcdir/$subdir/$dat.dat"
+    catch "exec diff $tmpdir/$execname.out $srcdir/$subdir/$dat.dat" exec_output
+    set exec_output [prune_warnings $exec_output]
+
+    if {![string match "" $exec_output]} then {
+	send_log "$exec_output\n"
+	verbose "$exec_output"
+	fail $test
+        return
+    }
+
+    pass $test
+}
+
+if [istarget mips*-*-*] {
+    set picflag ""
+} else {
+    # Unfortunately, the gcc argument is -fpic and the cc argument is
+    # -KPIC.  We have to try both.
+    set picflag "-fpic"
+    send_log "$CC $picflag\n"
+    verbose "$CC $picflag"
+    catch "exec $CC $picflag" exec_output
+    send_log "$exec_output\n"
+    verbose "--" "$exec_output"
+    if { [string match "*illegal option*" $exec_output] \
+	 || [string match "*option ignored*" $exec_output] \
+	 || [string match "*unrecognized option*" $exec_output] \
+	 || [string match "*passed to ld*" $exec_output] } {
+	if [istarget *-*-sunos4*] {
+	    set picflag "-pic"
+	} else {
+	    set picflag "-KPIC"
+	}
+    }
+}
+verbose "Using $picflag to compile PIC code"
+
+if ![ld_compile "$CC $CFLAGS $picflag" $srcdir/$subdir/foo.c $tmpdir/foo.o] {
+    unresolved "ELF weak"
+    return
+}
+
+if ![ld_compile "$CC $CFLAGS $picflag" $srcdir/$subdir/bar.c $tmpdir/bar.o] {
+    unresolved "ELF weak"
+    return
+}
+
+if ![ld_compile "$CC $CFLAGS" $srcdir/$subdir/main.c $tmpdir/main.o] {
+    unresolved "ELF weak"
+    return
+}
+
+if {![ld_simple_link $CC $tmpdir/libbar.so "$shared $tmpdir/bar.o"]} {
+    fail "ELF weak"
+    return
+}
+
+if ![ld_compile "$CC $CFLAGS $picflag" $srcdir/$subdir/foo1a.c $tmpdir/foo1a.o] {
+    unresolved "ELF weak"
+    return
+}
+
+if ![ld_compile "$CC $CFLAGS $picflag" $srcdir/$subdir/foo1b.c $tmpdir/foo1b.o] {
+    unresolved "ELF weak"
+    return
+}
+
+if ![ld_compile "$CC $CFLAGS $picflag" $srcdir/$subdir/bar1a.c $tmpdir/bar1a.o] {
+    unresolved "ELF weak"
+    return
+}
+
+if ![ld_compile "$CC $CFLAGS $picflag" $srcdir/$subdir/bar1b.c $tmpdir/bar1b.o] {
+    unresolved "ELF weak"
+    return
+}
+
+if ![ld_compile "$CC $CFLAGS $picflag" $srcdir/$subdir/bar1c.c $tmpdir/bar1c.o] {
+    unresolved "ELF weak"
+    return
+}
+
+if ![ld_compile "$CC $CFLAGS" $srcdir/$subdir/main1.c $tmpdir/main1.o] {
+    unresolved "ELF weak"
+    return
+}
+
+if {![ld_simple_link $CC $tmpdir/libfoo1a.so "$shared $tmpdir/foo1a.o"]} {
+    fail "ELF weak"
+    return
+}
+
+if {![ld_simple_link $CC $tmpdir/libfoo1b.so "$shared $tmpdir/foo1b.o"]} {
+    fail "ELF weak"
+    return
+}
+
+if {![ld_simple_link $CC $tmpdir/libbar1a.so "$shared $tmpdir/bar1a.o $tmpdir/libfoo1a.so"]} {
+    fail "ELF weak"
+    return
+}
+
+build_lib "ELF DSO weak func first" libfoo "foo.o bar.o" dso.dsym
+build_lib "ELF DSO weak func last" libfoo "bar.o foo.o" dso.dsym
+build_lib "ELF DSO weak func first DSO" libfoo "foo.o libbar.so" dsow.dsym
+build_lib "ELF DSO weak func last DSO" libfoo "libbar.so foo.o" dsow.dsym
+build_exec "ELF weak func first" foo "main.o bar.o" "" strong "" strong.sym
+build_exec "ELF weak func last" foo "bar.o main.o" "" strong "" strong.sym
+build_exec "ELF weak func first DSO" foo "main.o libbar.so" "-Wl,-rpath,." weak weak.dsym ""
+build_exec "ELF weak func last DSO" foo "libbar.so main.o" "-Wl,-rpath,." weak weak.dsym ""
+
+build_lib "ELF DSO weak data first" libfoo "bar1a.o foo1a.o" dsodata.dsym
+build_lib "ELF DSO weak data last" libfoo "foo1a.o bar1a.o" dsodata.dsym
+build_lib "ELF DSO weak data first DSO" libfoo "main1.o libfoo1a.so" dsowdata.dsym
+build_lib "ELF DSO weak data last DSO" libfoo "libfoo1a.so main1.o" dsowdata.dsym
+build_lib "ELF DSO weak data first DSO common" libfoo "main1.o libfoo1b.so" dsowdata.dsym
+build_lib "ELF DSO weak data last DSO common" libfoo "libfoo1b.so main1.o" dsowdata.dsym
+build_exec "ELF weak data first" foo "main1.o bar1a.o foo1a.o" "" strongdata "" strongdata.sym
+build_exec "ELF weak data last" foo "foo1a.o main1.o bar1a.o" "" strongdata "" strongdata.sym
+build_exec "ELF weak data first common" foo "main1.o bar1a.o foo1b.o" "" strongdata "" strongcomm.sym
+build_exec "ELF weak data last common" foo "foo1b.o main1.o bar1a.o" "" strongdata "" strongcomm.sym
+build_exec "ELF weak data first DSO" foo "main1.o libbar1a.so libfoo1a.so" "-Wl,-rpath,." weakdata weakdata.dsym ""
+build_exec "ELF weak data last DSO" foo "libfoo1a.so main1.o libbar1a.so" "-Wl,-rpath,." weakdata weakdata.dsym ""
+build_exec "ELF weak data first DSO common" foo "main1.o libbar1a.so libfoo1b.so" "-Wl,-rpath,." weakdata weakdata.dsym ""
+build_exec "ELF weak data last DSO common" foo "libfoo1b.so main1.o libbar1a.so" "-Wl,-rpath,." weakdata weakdata.dsym ""
+
+if ![ld_compile "$CC $CFLAGS $picflag" $srcdir/$subdir/size_foo.c $tmpdir/size_foo.o] {
+    unresolved "ELF weak (size)"
+    return
+}
+
+if ![ld_compile "$CC $CFLAGS $picflag" $srcdir/$subdir/size_bar.c $tmpdir/size_bar.o] {
+    unresolved "ELF weak (size)"
+    return
+}
+
+build_lib "ELF DSO small bar (size)" libsize_bar "size_bar.o" ""
+build_lib "ELF DSO foo with small bar (size)" libsize_foo "size_foo.o libsize_bar.so" ""
+
+if ![ld_compile "$CC $CFLAGS $picflag -DSIZE_BIG" $srcdir/$subdir/size_bar.c $tmpdir/size_bar.o] {
+    unresolved "ELF weak (size)"
+    return
+}
+
+build_lib "ELF DSO big bar (size)" libsize_bar "size_bar.o" ""
+
+if ![ld_compile "$CC $CFLAGS" $srcdir/$subdir/size_main.c $tmpdir/size_main.o] {
+    unresolved "ELF weak (size)"
+    return
+}
+
+build_exec "ELF weak size" size_main "size_main.o libsize_foo.so libsize_bar.so" "-Wl,-rpath,." size "" ""
+
+verbose "size2"
+run_dump_test $srcdir/$subdir/size2
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/foo.c b/binutils-2.19/ld/testsuite/ld-elfweak/foo.c
new file mode 100644
index 0000000..d00b1b5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/foo.c
@@ -0,0 +1,8 @@
+#pragma weak foo
+
+extern void foo ();
+
+void
+foo ()
+{
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/foo1a.c b/binutils-2.19/ld/testsuite/ld-elfweak/foo1a.c
new file mode 100644
index 0000000..a653020
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/foo1a.c
@@ -0,0 +1,7 @@
+int deallocate_foo = 0;
+
+int *
+foo ()
+{
+  return &deallocate_foo;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/foo1b.c b/binutils-2.19/ld/testsuite/ld-elfweak/foo1b.c
new file mode 100644
index 0000000..d71a635
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/foo1b.c
@@ -0,0 +1,7 @@
+int deallocate_foo;
+
+int *
+foo ()
+{
+  return &deallocate_foo;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/main.c b/binutils-2.19/ld/testsuite/ld-elfweak/main.c
new file mode 100644
index 0000000..5ea170c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/main.c
@@ -0,0 +1,19 @@
+#include <stdio.h>
+
+#pragma weak foo
+
+extern void foo ();
+extern void foobar ();
+
+void
+foo ()
+{
+  printf ("weak foo\n");
+}
+
+int
+main ()
+{
+  foobar ();
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/main1.c b/binutils-2.19/ld/testsuite/ld-elfweak/main1.c
new file mode 100644
index 0000000..39f819e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/main1.c
@@ -0,0 +1,11 @@
+#pragma weak deallocate_foo
+int deallocate_foo = 1;
+
+extern void foobar ();
+
+int
+main ()
+{
+  foobar ();
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/size.dat b/binutils-2.19/ld/testsuite/ld-elfweak/size.dat
new file mode 100644
index 0000000..01e79c3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/size.dat
@@ -0,0 +1,3 @@
+1
+2
+3
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/size2.d b/binutils-2.19/ld/testsuite/ld-elfweak/size2.d
new file mode 100644
index 0000000..4468dda
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/size2.d
@@ -0,0 +1,10 @@
+#source: size2a.s
+#source: size2b.s
+#ld:
+#readelf: -s
+Symbol table '.symtab' contains .* entries:
+#...
+    .*: [0-9a-f]* +1 +FUNC +GLOBAL +DEFAULT +[0-9] +__?start
+#...
+    .*: [0-9a-f]* +1 +FUNC +WEAK +DEFAULT +[0-9] +foo
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/size2a.s b/binutils-2.19/ld/testsuite/ld-elfweak/size2a.s
new file mode 100644
index 0000000..c9ad914
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/size2a.s
@@ -0,0 +1,16 @@
+	.text
+	.global _start
+	.global __start
+	.type _start, "function"
+	.type __start, "function"
+_start:
+__start:
+	.byte 0
+	.size _start, 1
+	.size __start, 1
+
+	.weak foo
+	.type foo, "function"
+foo:
+	.byte 0
+	.size foo, 1
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/size2b.s b/binutils-2.19/ld/testsuite/ld-elfweak/size2b.s
new file mode 100644
index 0000000..946c838
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/size2b.s
@@ -0,0 +1,18 @@
+	.text
+	.weak _start
+	.weak __start
+	.type _start, "function"
+	.type __start, "function"
+_start:
+__start:
+	.byte 0
+	.byte 0
+	.size _start, 2
+	.size __start, 2
+
+	.weak foo
+	.type foo, "function"
+foo:
+	.byte 0
+	.byte 0
+	.size foo, 2
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/size_bar.c b/binutils-2.19/ld/testsuite/ld-elfweak/size_bar.c
new file mode 100644
index 0000000..7f32890
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/size_bar.c
@@ -0,0 +1,11 @@
+#include <stdio.h>
+
+void
+bar ()
+{
+#ifdef SIZE_BIG
+  printf ("1\n");
+  printf ("2\n");
+  printf ("3\n");
+#endif
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/size_foo.c b/binutils-2.19/ld/testsuite/ld-elfweak/size_foo.c
new file mode 100644
index 0000000..f7a605a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/size_foo.c
@@ -0,0 +1,9 @@
+#pragma weak bar
+
+extern void bar ();
+
+void
+foo ()
+{
+  bar ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/size_main.c b/binutils-2.19/ld/testsuite/ld-elfweak/size_main.c
new file mode 100644
index 0000000..2cee0a9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/size_main.c
@@ -0,0 +1,8 @@
+extern void foo ();
+
+int
+main ()
+{
+  foo ();
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/strong.dat b/binutils-2.19/ld/testsuite/ld-elfweak/strong.dat
new file mode 100644
index 0000000..13693db
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/strong.dat
@@ -0,0 +1 @@
+strong foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/strong.sym b/binutils-2.19/ld/testsuite/ld-elfweak/strong.sym
new file mode 100644
index 0000000..85e06f7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/strong.sym
@@ -0,0 +1 @@
+[0-9a-f]*[ 	]+g[ 	]+F[ 	]+.text[	]+[0-9a-f]*[ 	]+(0x[0-9a-f]*|)[ 	]*foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/strongcomm.sym b/binutils-2.19/ld/testsuite/ld-elfweak/strongcomm.sym
new file mode 100644
index 0000000..c0ae401
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/strongcomm.sym
@@ -0,0 +1,2 @@
+[0-9a-f]*[ 	]+g[ 	]+O[ 	]+.(s|)bss[	]+[0-9a-f]*[ 	]+deallocate_foo
+[0-9a-f]*[ 	]+g[ 	]+F[ 	]+.text[	]+[0-9a-f]*[ 	]+(0x[0-9a-f]*|)[ 	]*foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/strongdata.dat b/binutils-2.19/ld/testsuite/ld-elfweak/strongdata.dat
new file mode 100644
index 0000000..8232e85
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/strongdata.dat
@@ -0,0 +1 @@
+strong deallocate_foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/strongdata.sym b/binutils-2.19/ld/testsuite/ld-elfweak/strongdata.sym
new file mode 100644
index 0000000..9b94377
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/strongdata.sym
@@ -0,0 +1,2 @@
+[0-9a-f]*[ 	]+g[ 	]+O[ 	]+.(s|)(data|bss)[	]+[0-9a-f]*[ 	]+deallocate_foo
+[0-9a-f]*[ 	]+g[ 	]+F[ 	]+.text[	]+[0-9a-f]*[ 	]+(0x[0-9a-f]*|)[ 	]*foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/weak.dat b/binutils-2.19/ld/testsuite/ld-elfweak/weak.dat
new file mode 100644
index 0000000..0b54d97
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/weak.dat
@@ -0,0 +1 @@
+weak foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/weak.dsym b/binutils-2.19/ld/testsuite/ld-elfweak/weak.dsym
new file mode 100644
index 0000000..cc36c6f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/weak.dsym
@@ -0,0 +1 @@
+[0-9a-f]*[ 	]+w[ 	]+DF[ 	]+.text[	]+[0-9a-f]*[ 	]+(Base[ 	]+|[ 	]*)(0x[0-9a-f]+|)[ 	]*foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/weakdata.dat b/binutils-2.19/ld/testsuite/ld-elfweak/weakdata.dat
new file mode 100644
index 0000000..96668fa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/weakdata.dat
@@ -0,0 +1 @@
+weak deallocate_foo
diff --git a/binutils-2.19/ld/testsuite/ld-elfweak/weakdata.dsym b/binutils-2.19/ld/testsuite/ld-elfweak/weakdata.dsym
new file mode 100644
index 0000000..e0f579a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-elfweak/weakdata.dsym
@@ -0,0 +1 @@
+[0-9a-f]*[ 	]+w[ 	]+DO[ 	]+.(s|)data[	]+[0-9a-f]*[ 	]+(Base[ 	]+|[ 	]*)deallocate_foo
diff --git a/binutils-2.19/ld/testsuite/ld-fastcall/export.s b/binutils-2.19/ld/testsuite/ld-fastcall/export.s
new file mode 100644
index 0000000..d8df66d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-fastcall/export.s
@@ -0,0 +1,3 @@
+	.text
+.globl @extern_fastcall_function@0
+@extern_fastcall_function@0:
diff --git a/binutils-2.19/ld/testsuite/ld-fastcall/fastcall.exp b/binutils-2.19/ld/testsuite/ld-fastcall/fastcall.exp
new file mode 100644
index 0000000..a8c0b33
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-fastcall/fastcall.exp
@@ -0,0 +1,52 @@
+# Test that the linker can handle fastcall symbols correctly.
+# Copyright 2002, 2006, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+set testname "ld (fastcall symbols)"
+
+if {![istarget "i*86-*-*"] && ![istarget "x86_64-*-mingw*"] } {
+    return
+}
+
+if {  !([istarget "i*86-*-*pe*"] && ![istarget "i*86-*-opensd*"]) \
+    && ![istarget "i*86-*-cygwin*"] \
+    && ![istarget "x86_64-*-mingw*"] \
+    && ![istarget "i*86-*-mingw*"] } {
+    return
+}
+
+set ldflags ""
+
+if ![ld_assemble $as $srcdir/$subdir/export.s tmpdir/export.o] {
+    verbose "Unable to assemble test file!" 1
+    unresolved $testname
+    return
+}
+
+if ![ld_assemble $as $srcdir/$subdir/import.s tmpdir/import.o] {
+    verbose "Unable to assemble test file!" 1
+    unresolved $testname
+    return
+}
+
+if ![ld_simple_link $ld tmpdir/extern.x "$ldflags tmpdir/export.o tmpdir/import.o"] {
+    fail $testname
+} else {
+    pass $testname
+}
diff --git a/binutils-2.19/ld/testsuite/ld-fastcall/import.s b/binutils-2.19/ld/testsuite/ld-fastcall/import.s
new file mode 100644
index 0000000..e33918b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-fastcall/import.s
@@ -0,0 +1,4 @@
+	.text
+.globl _start
+_start:
+	call	@extern_fastcall_function@0
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-1.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-1.d
new file mode 100644
index 0000000..0e37324
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-1.d
@@ -0,0 +1,57 @@
+#name: FRV uClinux PIC relocs to local symbols, pie linking
+#source: fdpic1.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -pie
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+ <F1>:
+[0-9a-f ]+:	80 3c 00 01 	call [0-9a-f]+ <\.F0>
+
+[0-9a-f ]+<\.F0>:
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 0c 	setlos 0xc,gr0
+[0-9a-f ]+:	80 f4 00 0c 	setlo 0xc,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 10 	setlos 0x10,gr0
+[0-9a-f ]+:	80 f4 00 10 	setlo 0x10,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff f8 	setlos 0xf+ff8,gr0
+[0-9a-f ]+:	80 f4 ff f8 	setlo 0xfff8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff ec 	addi gr15,-20,gr0
+[0-9a-f ]+:	80 fc ff ec 	setlos 0xf+fec,gr0
+[0-9a-f ]+:	80 f4 ff ec 	setlo 0xffec,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.data:
+
+[0-9a-f ]+<D1>:
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
+
+[0-9a-f ]+<\.D0>:
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x8>:
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-2.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-2.d
new file mode 100644
index 0000000..3583a3b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-2.d
@@ -0,0 +1,71 @@
+#name: FRV uClinux PIC relocs to global symbols, pie linking
+#source: fdpic2.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -pie
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<F2>:
+[0-9a-f ]+:	80 3c 00 01 	call [0-9a-f]+ <GF0>
+
+[0-9a-f ]+<GF0>:
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 24 	setlos 0x24,gr0
+[0-9a-f ]+:	80 f4 00 20 	setlo 0x20,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 18 	setlos 0x18,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff f0 	setlos 0xf+ff0,gr0
+[0-9a-f ]+:	80 f4 ff e8 	setlo 0xffe8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff dc 	addi gr15,-36,gr0
+[0-9a-f ]+:	80 fc ff dc 	setlos 0xf+fdc,gr0
+[0-9a-f ]+:	80 f4 ff dc 	setlo 0xffdc,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 1c 	setlo 0x1c,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D2>:
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
+
+[0-9a-f ]+<GD0>:
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x18>:
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-5.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-5.d
new file mode 100644
index 0000000..8565024
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-5.d
@@ -0,0 +1,5 @@
+#name: FRV uClinux PIC relocs to undefined symbols, pie linking
+#source: fdpic5.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -pie
+#error: undefined reference
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-6-fail.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-6-fail.d
new file mode 100644
index 0000000..b7e93ae
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-6-fail.d
@@ -0,0 +1,5 @@
+#name: FRV uClinux PIC relocs to undefined symbols, pie linking
+#source: fdpic6.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -pie
+#error: different segment
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-6.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-6.d
new file mode 100644
index 0000000..7bdda5d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-6.d
@@ -0,0 +1,73 @@
+#name: FRV uClinux PIC relocs to weak undefined symbols, pie linking
+#source: fdpic6.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -pie --defsym WD1=D6
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.plt:
+
+[0-9a-f ]+<\.plt>:
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f ]+:	c0 1a 00 06 	bra [0-9a-f]+ <F6-0x10>
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	c0 1a 00 04 	bra [0-9a-f]+ <F6-0x10>
+[0-9a-f ]+:	00 00 00 10 	add\.p gr0,gr16,gr0
+[0-9a-f ]+:	c0 1a 00 02 	bra [0-9a-f]+ <F6-0x10>
+[0-9a-f ]+:	00 00 00 18 	add\.p gr0,gr24,gr0
+[0-9a-f ]+:	88 08 f1 40 	ldd @\(gr15,gr0\),gr4
+[0-9a-f ]+:	80 30 40 00 	jmpl @\(gr4,gr0\)
+[0-9a-f ]+:	9c cc ff f0 	lddi @\(gr15,-16\),gr14
+[0-9a-f ]+:	80 30 e0 00 	jmpl @\(gr14,gr0\)
+Disassembly of section \.text:
+
+[0-9a-f ]+<F6>:
+[0-9a-f ]+:	fe 3f ff fe 	call [0-9a-f]+ <F6-0x8>
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 24 	setlos 0x24,gr0
+[0-9a-f ]+:	80 f4 00 20 	setlo 0x20,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 18 	setlos 0x18,gr0
+[0-9a-f ]+:	80 f4 00 1c 	setlo 0x1c,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff e8 	setlos 0xf*ffffffe8,gr0
+[0-9a-f ]+:	80 f4 ff e0 	setlo 0xffe0,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 ff d0 	setlo 0xffd0,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D6>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_32	WD0
+[0-9a-f	 ]+: R_FRV_FUNCDESC	WFb
+[0-9a-f	 ]+: R_FRV_32	WFb
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x20>:
+[0-9a-f ]+:	00 00 04 b8 	.*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	WF9
+[0-9a-f ]+:	00 00 00 02 	.*
+[0-9a-f ]+:	00 00 04 b0 	.*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	WF8
+[0-9a-f ]+:	00 00 00 02 	.*
+[0-9a-f ]+:	00 00 04 a8 	.*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	WF0
+[0-9a-f ]+:	00 00 00 02 	.*
+[0-9a-f ]+:	00 00 04 a0 	.*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	WF7
+[0-9a-f ]+:	00 00 00 02 	.*
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_32	WF1
+[0-9a-f	 ]+: R_FRV_FUNCDESC	WF4
+[0-9a-f	 ]+: R_FRV_32	WD2
+[0-9a-f	 ]+: R_FRV_FUNCDESC	WF5
+[0-9a-f	 ]+: R_FRV_FUNCDESC	WF6
+[0-9a-f	 ]+: R_FRV_32	WF3
+[0-9a-f	 ]+: R_FRV_32	WF2
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-7.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-7.d
new file mode 100644
index 0000000..7ebd0b7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-7.d
@@ -0,0 +1,57 @@
+#name: FRV uClinux PIC relocs to local symbols with addends, pie linking
+#source: fdpic7.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -pie
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<F7>:
+[0-9a-f ]+:	80 3c 00 02 	call [0-9a-f]+ <\.F0\+0x4>
+
+[0-9a-f ]+<\.F0>:
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 0c 	setlos 0xc,gr0
+[0-9a-f ]+:	80 f4 00 0c 	setlo 0xc,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 10 	setlos 0x10,gr0
+[0-9a-f ]+:	80 f4 00 10 	setlo 0x10,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff f8 	setlos 0xf*fffffff8,gr0
+[0-9a-f ]+:	80 f4 ff f8 	setlo 0xfff8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff f0 	addi gr15,-16,gr0
+[0-9a-f ]+:	80 fc ff f0 	setlos 0xf+ff0,gr0
+[0-9a-f ]+:	80 f4 ff f0 	setlo 0xfff0,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D7>:
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
+
+[0-9a-f ]+<\.D0>:
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x8>:
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-8.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-8.d
new file mode 100644
index 0000000..0de4a81
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-pie-8.d
@@ -0,0 +1,71 @@
+#name: FRV uClinux PIC relocs to global symbols with addends, pie linking
+#source: fdpic8.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -pie
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<F8>:
+[0-9a-f ]+:	80 3c 00 02 	call [0-9a-f]+ <GF0\+0x4>
+
+[0-9a-f ]+<GF0>:
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 14 	setlos 0x14,gr0
+[0-9a-f ]+:	80 f4 00 24 	setlo 0x24,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 1c 	setlos 0x1c,gr0
+[0-9a-f ]+:	80 f4 00 18 	setlo 0x18,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff f0 	setlos 0xf+ff0,gr0
+[0-9a-f ]+:	80 f4 ff e8 	setlo 0xffe8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff e0 	addi gr15,-32,gr0
+[0-9a-f ]+:	80 fc ff e0 	setlos 0xf+fe0,gr0
+[0-9a-f ]+:	80 f4 ff e0 	setlo 0xffe0,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 20 	setlo 0x20,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D8>:
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
+
+[0-9a-f ]+<GD0>:
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC	\.text
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x18>:
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC	\.text
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC	\.text
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-1.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-1.d
new file mode 100644
index 0000000..7f88e18
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-1.d
@@ -0,0 +1,57 @@
+#name: FRV uClinux PIC relocs to local symbols, shared linking
+#source: fdpic1.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -shared
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<F1>:
+[0-9a-f ]+:	80 3c 00 01 	call [0-9a-f]+ <\.F0>
+
+[0-9a-f ]+<\.F0>:
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 0c 	setlos 0xc,gr0
+[0-9a-f ]+:	80 f4 00 0c 	setlo 0xc,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 10 	setlos 0x10,gr0
+[0-9a-f ]+:	80 f4 00 10 	setlo 0x10,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff f8 	setlos 0xf+ff8,gr0
+[0-9a-f ]+:	80 f4 ff f8 	setlo 0xfff8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff ec 	addi gr15,-20,gr0
+[0-9a-f ]+:	80 fc ff ec 	setlos 0xf+fec,gr0
+[0-9a-f ]+:	80 f4 ff ec 	setlo 0xffec,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D1>:
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
+
+[0-9a-f ]+<\.D0>:
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x8>:
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-2-fail.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-2-fail.d
new file mode 100644
index 0000000..0cec4f6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-2-fail.d
@@ -0,0 +1,4 @@
+#name: FRV uClinux PIC relocs to global symbols, failing shared linking
+#source: fdpic2.s
+#ld: -shared
+#error: different segment
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-2.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-2.d
new file mode 100644
index 0000000..cb4b68d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-2.d
@@ -0,0 +1,80 @@
+#name: FRV uClinux PIC relocs to (mostly) global symbols, shared linking
+#source: fdpic2.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -shared --version-script fdpic2min.ldv
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.plt:
+
+[0-9a-f ]+ <\.plt>:
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	c0 1a 00 06 	bra [0-9a-f]+ <F2-0x10>
+[0-9a-f ]+:	00 00 00 10 	add\.p gr0,gr16,gr0
+[0-9a-f ]+:	c0 1a 00 04 	bra [0-9a-f]+ <F2-0x10>
+[0-9a-f ]+:	00 00 00 18 	add\.p gr0,gr24,gr0
+[0-9a-f ]+:	c0 1a 00 02 	bra [0-9a-f]+ <F2-0x10>
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f ]+:	88 08 f1 40 	ldd @\(gr15,gr0\),gr4
+[0-9a-f ]+:	80 30 40 00 	jmpl @\(gr4,gr0\)
+[0-9a-f ]+:	9c cc ff f8 	lddi @\(gr15,-8\),gr14
+[0-9a-f ]+:	80 30 e0 00 	jmpl @\(gr14,gr0\)
+Disassembly of section \.text:
+
+[0-9a-f ]+<F2>:
+[0-9a-f ]+:	fe 3f ff fe 	call [0-9a-f]+ <F2-0x8>
+
+[0-9a-f ]+<GF0>:
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 24 	setlos 0x24,gr0
+[0-9a-f ]+:	80 f4 00 20 	setlo 0x20,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 18 	setlos 0x18,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f0 	addi gr15,-16,gr0
+[0-9a-f ]+:	80 fc ff e8 	setlos 0xf*ffffffe8,gr0
+[0-9a-f ]+:	80 f4 ff e0 	setlo 0xffe0,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff d8 	addi gr15,-40,gr0
+[0-9a-f ]+:	80 fc ff d8 	setlos 0xf+fd8,gr0
+[0-9a-f ]+:	80 f4 ff d8 	setlo 0xffd8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 1c 	setlo 0x1c,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D2>:
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_32	GD0
+
+[0-9a-f ]+<GD0>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_FUNCDESC	GFb
+[0-9a-f	 ]+: R_FRV_32	GFb
+[0-9A-F ]+isassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x20>:
+[0-9a-f ]+:	00 00 04 a4 	.*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	GF9
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f ]+:	00 00 04 9c 	.*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	GF8
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f ]+:	00 00 04 ac 	.*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	GF7
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f ]+:	00 00 04 94 	.*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	GF0
+[0-9a-f ]+:	00 00 00 00 	.*
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_FUNCDESC	GF4
+[0-9a-f	 ]+: R_FRV_32	GF1
+[0-9a-f	 ]+: R_FRV_FUNCDESC	GF6
+[0-9a-f	 ]+: R_FRV_FUNCDESC	GF5
+[0-9a-f	 ]+: R_FRV_32	GD4
+[0-9a-f	 ]+: R_FRV_32	GF3
+[0-9a-f	 ]+: R_FRV_32	GF2
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-3.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-3.d
new file mode 100644
index 0000000..fceb16a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-3.d
@@ -0,0 +1,83 @@
+#name: FRV uClinux PIC relocs to hidden symbols, shared linking
+#source: fdpic3.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -shared
+
+.*:     file format elf.*frv.*
+
+[0-9A-F ]+isassembly of section \.text:
+
+[0-9a-f ]+<F3>:
+[0-9a-f ]+:	80 3c 00 01 	call [0-9a-f]+ <HF0>
+
+[0-9a-f ]+<HF0>:
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 18 	setlos 0x18,gr0
+[0-9a-f ]+:	80 f4 00 1c 	setlo 0x1c,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 20 	setlos 0x20,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff e8 	setlos 0xf*ffffffe8,gr0
+[0-9a-f ]+:	80 f4 ff d8 	setlo 0xffd8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff bc 	addi gr15,-68,gr0
+[0-9a-f ]+:	80 fc ff bc 	setlos 0xf+fbc,gr0
+[0-9a-f ]+:	80 f4 ff bc 	setlo 0xffbc,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 24 	setlo 0x24,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D3>:
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
+
+[0-9a-f ]+<HD0>:
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x38>:
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 28 	add\.p gr0,gr40,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 18 	add\.p gr0,gr24,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-4.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-4.d
new file mode 100644
index 0000000..4045562
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-4.d
@@ -0,0 +1,71 @@
+#name: FRV uClinux PIC relocs to protected symbols, shared linking
+#source: fdpic4.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -shared
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<F4>:
+[0-9a-f ]+:	80 3c 00 01 	call [0-9a-f]+ <PF0>
+
+[0-9a-f ]+<PF0>:
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 20 	setlos 0x20,gr0
+[0-9a-f ]+:	80 f4 00 1c 	setlo 0x1c,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 24 	setlos 0x24,gr0
+[0-9a-f ]+:	80 f4 00 18 	setlo 0x18,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff f0 	setlos 0xf+ff0,gr0
+[0-9a-f ]+:	80 f4 ff e8 	setlo 0xffe8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff dc 	addi gr15,-36,gr0
+[0-9a-f ]+:	80 fc ff dc 	setlos 0xf+fdc,gr0
+[0-9a-f ]+:	80 f4 ff dc 	setlo 0xffdc,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D4>:
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
+
+[0-9a-f ]+<PD0>:
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x18>:
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC	\.text
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-5.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-5.d
new file mode 100644
index 0000000..009c62c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-5.d
@@ -0,0 +1,82 @@
+#name: FRV uClinux PIC relocs to undefined symbols, shared linking
+#source: fdpic5.s
+#objdump: -DRz -j .text -j .data -j .got -j .plt
+#ld: -shared
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.plt:
+
+[0-9a-f ]+<\.plt>:
+[0-9a-f ]+:	00 00 00 10 	add\.p gr0,gr16,gr0
+[0-9a-f ]+:	c0 1a 00 06 	bra [0-9a-f]+ <F5-0x10>
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f ]+:	c0 1a 00 04 	bra [0-9a-f]+ <F5-0x10>
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	c0 1a 00 02 	bra [0-9a-f]+ <F5-0x10>
+[0-9a-f ]+:	00 00 00 18 	add\.p gr0,gr24,gr0
+[0-9a-f ]+:	88 08 f1 40 	ldd @\(gr15,gr0\),gr4
+[0-9a-f ]+:	80 30 40 00 	jmpl @\(gr4,gr0\)
+[0-9a-f ]+:	9c cc ff f0 	lddi @\(gr15,-16\),gr14
+[0-9a-f ]+:	80 30 e0 00 	jmpl @\(gr14,gr0\)
+Disassembly of section \.text:
+
+[0-9a-f ]+<F5>:
+[0-9a-f ]+:	fe 3f ff fe 	call [0-9a-f]+ <F5-0x8>
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 24 	setlos 0x24,gr0
+[0-9a-f ]+:	80 f4 00 20 	setlo 0x20,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 1c 	setlos 0x1c,gr0
+[0-9a-f ]+:	80 f4 00 18 	setlo 0x18,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff e8 	setlos 0xf*ffffffe8,gr0
+[0-9a-f ]+:	80 f4 ff e0 	setlo 0xffe0,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D5>:
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_32	UD0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC	UFb
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_32	UFb
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x20>:
+[0-9a-f ]+:	00 00 04 7c 	.*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	UF9
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f ]+:	00 00 04 64 	.*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	UF8
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f ]+:	00 00 04 74 	.*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	UF0
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f ]+:	00 00 04 6c 	.*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	UF7
+[0-9a-f ]+:	00 00 00 00 	.*
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f	 ]+: R_FRV_32	UF1
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f	 ]+: R_FRV_FUNCDESC	UF4
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f	 ]+: R_FRV_32	UD1
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f	 ]+: R_FRV_FUNCDESC	UF6
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f	 ]+: R_FRV_FUNCDESC	UF5
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f	 ]+: R_FRV_32	UF3
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f	 ]+: R_FRV_32	UF2
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-6-fail.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-6-fail.d
new file mode 100644
index 0000000..23a245b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-6-fail.d
@@ -0,0 +1,5 @@
+#name: FRV uClinux PIC relocs to undefined symbols, shared linking
+#source: fdpic6.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -shared
+#error: different segment
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-6.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-6.d
new file mode 100644
index 0000000..06a335f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-6.d
@@ -0,0 +1,73 @@
+#name: FRV uClinux PIC relocs to weak undefined symbols, shared linking
+#source: fdpic6.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -shared --defsym WD1=D6 --version-script fdpic6.ldv
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.plt:
+
+[0-9a-f ]+<\.plt>:
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f ]+:	c0 1a 00 06 	bra [0-9a-f]+ <F6-0x10>
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	c0 1a 00 04 	bra [0-9a-f]+ <F6-0x10>
+[0-9a-f ]+:	00 00 00 10 	add\.p gr0,gr16,gr0
+[0-9a-f ]+:	c0 1a 00 02 	bra [0-9a-f]+ <F6-0x10>
+[0-9a-f ]+:	00 00 00 18 	add\.p gr0,gr24,gr0
+[0-9a-f ]+:	88 08 f1 40 	ldd @\(gr15,gr0\),gr4
+[0-9a-f ]+:	80 30 40 00 	jmpl @\(gr4,gr0\)
+[0-9a-f ]+:	9c cc ff f0 	lddi @\(gr15,-16\),gr14
+[0-9a-f ]+:	80 30 e0 00 	jmpl @\(gr14,gr0\)
+Disassembly of section \.text:
+
+[0-9a-f ]+<F6>:
+[0-9a-f ]+:	fe 3f ff fe 	call [0-9a-f]+ <F6-0x8>
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 24 	setlos 0x24,gr0
+[0-9a-f ]+:	80 f4 00 20 	setlo 0x20,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 18 	setlos 0x18,gr0
+[0-9a-f ]+:	80 f4 00 1c 	setlo 0x1c,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff e8 	setlos 0xf*ffffffe8,gr0
+[0-9a-f ]+:	80 f4 ff e0 	setlo 0xffe0,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 ff d0 	setlo 0xffd0,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D6>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_32	WD0
+[0-9a-f	 ]+: R_FRV_FUNCDESC	WFb
+[0-9a-f	 ]+: R_FRV_32	WFb
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x20>:
+[0-9a-f ]+:	00 00 03 60 .*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	WF9
+[0-9a-f ]+:	00 00 00 00 .*
+[0-9a-f ]+:	00 00 03 58 .*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	WF8
+[0-9a-f ]+:	00 00 00 00 .*
+[0-9a-f ]+:	00 00 03 50 .*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	WF0
+[0-9a-f ]+:	00 00 00 00 .*
+[0-9a-f ]+:	00 00 03 48 .*
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	WF7
+[0-9a-f ]+:	00 00 00 00 .*
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_32	WF1
+[0-9a-f	 ]+: R_FRV_FUNCDESC	WF4
+[0-9a-f	 ]+: R_FRV_32	WD2
+[0-9a-f	 ]+: R_FRV_FUNCDESC	WF5
+[0-9a-f	 ]+: R_FRV_FUNCDESC	WF6
+[0-9a-f	 ]+: R_FRV_32	WF3
+[0-9a-f	 ]+: R_FRV_32	WF2
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-7.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-7.d
new file mode 100644
index 0000000..2004a84
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-7.d
@@ -0,0 +1,57 @@
+#name: FRV uClinux PIC relocs to local symbols with addends, shared linking
+#source: fdpic7.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -shared
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<F7>:
+[0-9a-f ]+:	80 3c 00 02 	call [0-9a-f]+ <\.F0\+0x4>
+
+[0-9a-f ]+<\.F0>:
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 0c 	setlos 0xc,gr0
+[0-9a-f ]+:	80 f4 00 0c 	setlo 0xc,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 10 	setlos 0x10,gr0
+[0-9a-f ]+:	80 f4 00 10 	setlo 0x10,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff f8 	setlos 0xf*fffffff8,gr0
+[0-9a-f ]+:	80 f4 ff f8 	setlo 0xfff8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff f0 	addi gr15,-16,gr0
+[0-9a-f ]+:	80 fc ff f0 	setlos 0xf+ff0,gr0
+[0-9a-f ]+:	80 f4 ff f0 	setlo 0xfff0,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D7>:
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
+
+[0-9a-f ]+<\.D0>:
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x8>:
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-8-fail.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-8-fail.d
new file mode 100644
index 0000000..5634040
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-8-fail.d
@@ -0,0 +1,5 @@
+#name: FRV uClinux PIC relocs to (mostly) global symbols with addends, failing shared linking
+#source: fdpic8.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -shared
+#error: (nonzero addend|may have caused)
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-8.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-8.d
new file mode 100644
index 0000000..543d313
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-8.d
@@ -0,0 +1,83 @@
+#name: FRV uClinux PIC relocs to (mostly) global symbols with addends, shared linking
+#source: fdpic8.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -shared --version-script fdpic8min.ldv
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<F8>:
+[0-9a-f ]+:	80 3c 00 02 	call [0-9a-f]+ <GF1\+0x4>
+
+[0-9a-f ]+<GF1>:
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 14 	setlos 0x14,gr0
+[0-9a-f ]+:	80 f4 00 24 	setlo 0x24,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 1c 	setlos 0x1c,gr0
+[0-9a-f ]+:	80 f4 00 18 	setlo 0x18,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff f0 	setlos 0xf+ff0,gr0
+[0-9a-f ]+:	80 f4 ff c8 	setlo 0xffc8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff c0 	addi gr15,-64,gr0
+[0-9a-f ]+:	80 fc ff c0 	setlos 0xf+fc0,gr0
+[0-9a-f ]+:	80 f4 ff c0 	setlo 0xffc0,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 20 	setlo 0x20,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9A-F ]+isassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D8>:
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	GD0
+
+[0-9a-f ]+<GD0>:
+[0-9a-f ]+:	00 00 00 10 	add\.p gr0,gr16,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x38>:
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	GF1
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	GF2
+[0-9a-f ]+:	00 00 00 20 	add\.p gr0,gr32,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 18 	add\.p gr0,gr24,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	GD4
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	GF3
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-local-2.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-local-2.d
new file mode 100644
index 0000000..51ca126
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-local-2.d
@@ -0,0 +1,83 @@
+#name: FRV uClinux PIC relocs to forced-local symbols, shared linking
+#source: fdpic2.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -shared --version-script fdpic2.ldv
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<F2>:
+[0-9a-f ]+:	80 3c 00 01 	call [0-9a-f]+ <GF0>
+
+[0-9a-f ]+<GF0>:
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 24 	setlos 0x24,gr0
+[0-9a-f ]+:	80 f4 00 20 	setlo 0x20,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 18 	setlos 0x18,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff d0 	setlos 0xf+fd0,gr0
+[0-9a-f ]+:	80 f4 ff c8 	setlo 0xffc8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff c0 	addi gr15,-64,gr0
+[0-9a-f ]+:	80 fc ff c0 	setlos 0xf+fc0,gr0
+[0-9a-f ]+:	80 f4 ff c0 	setlo 0xffc0,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 1c 	setlo 0x1c,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D2>:
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
+
+[0-9a-f ]+<GD0>:
+[0-9a-f ]+:	00 00 00 18 	add\.p gr0,gr24,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x38>:
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 00 00 10 	add\.p gr0,gr16,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 28 	add\.p gr0,gr40,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 20 	add\.p gr0,gr32,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 04 	add\.p gr0,gr4,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-local-8.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-local-8.d
new file mode 100644
index 0000000..8d2c67e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-shared-local-8.d
@@ -0,0 +1,83 @@
+#name: FRV uClinux PIC relocs to forced-local symbols with addends, shared linking
+#source: fdpic8.s
+#objdump: -DR -j .text -j .data -j .got -j .plt
+#ld: -shared --version-script fdpic8.ldv
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<F8>:
+[0-9a-f ]+:	80 3c 00 02 	call [0-9a-f]+ <GF0\+0x4>
+
+[0-9a-f ]+<GF0>:
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 14 	setlos 0x14,gr0
+[0-9a-f ]+:	80 f4 00 24 	setlo 0x24,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 1c 	setlos 0x1c,gr0
+[0-9a-f ]+:	80 f4 00 18 	setlo 0x18,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff f0 	setlos 0xf+ff0,gr0
+[0-9a-f ]+:	80 f4 ff c8 	setlo 0xffc8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff c4 	addi gr15,-60,gr0
+[0-9a-f ]+:	80 fc ff c4 	setlos 0xf+fc4,gr0
+[0-9a-f ]+:	80 f4 ff c4 	setlo 0xffc4,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 20 	setlo 0x20,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D8>:
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
+
+[0-9a-f ]+<GD0>:
+[0-9a-f ]+:	00 00 00 10 	add\.p gr0,gr16,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x38>:
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_FUNCDESC_VALUE	\.text
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
+[0-9a-f ]+:	00 00 00 20 	add\.p gr0,gr32,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 18 	add\.p gr0,gr24,gr0
+[0-9a-f	 ]+: R_FRV_32	\.got
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.data
+[0-9a-f ]+:	00 00 00 08 	add\.p gr0,gr8,gr0
+[0-9a-f	 ]+: R_FRV_32	\.text
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-1.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-1.d
new file mode 100644
index 0000000..1c4dce1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-1.d
@@ -0,0 +1,62 @@
+#name: FRV uClinux PIC relocs to local symbols, static linking
+#source: fdpic1.s
+#objdump: -D
+#ld: -static
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<F1>:
+[0-9a-f ]+:	80 3c 00 01 	call [0-9a-f]+ <\.F0>
+
+[0-9a-f ]+<\.F0>:
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 0c 	setlos 0xc,gr0
+[0-9a-f ]+:	80 f4 00 0c 	setlo 0xc,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 10 	setlos 0x10,gr0
+[0-9a-f ]+:	80 f4 00 10 	setlo 0x10,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff f8 	setlos 0xf*fffffff8,gr0
+[0-9a-f ]+:	80 f4 ff f8 	setlo 0xfff8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff f0 	addi gr15,-16,gr0
+[0-9a-f ]+:	80 fc ff f0 	setlos 0xf*fffffff0,gr0
+[0-9a-f ]+:	80 f4 ff f0 	setlo 0xfff0,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.rofixup:
+
+[0-9a-f ]+<__ROFIXUP_LIST__>:
+[0-9a-f ]+:	00 01 41 24 	sub\.p gr20,gr36,gr0
+[0-9a-f ]+:	00 01 41 28 	sub\.p gr20,gr40,gr0
+[0-9a-f ]+:	00 01 41 10 	sub\.p gr20,gr16,gr0
+[0-9a-f ]+:	00 01 41 14 	sub\.p gr20,gr20,gr0
+[0-9a-f ]+:	00 01 41 2c 	sub\.p gr20,gr44,gr0
+[0-9a-f ]+:	00 01 41 04 	sub\.p gr20,gr4,gr0
+[0-9a-f ]+:	00 01 41 08 	sub\.p gr20,gr8,gr0
+[0-9a-f ]+:	00 01 41 0c 	sub\.p gr20,gr12,gr0
+[0-9a-f ]+:	00 01 41 18 	sub\.p gr20,gr24,gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D1>:
+[0-9a-f ]+:	00 01 41 08 	sub\.p gr20,gr8,gr0
+
+[0-9a-f ]+<\.D0>:
+[0-9a-f ]+:	00 01 41 10 	sub\.p gr20,gr16,gr0
+[0-9a-f ]+:	00 01 00 98 	addx\.p gr16,gr24,gr0,icc0
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x8>:
+[0-9a-f ]+:	00 01 00 98 	addx\.p gr16,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 41 18 	sub\.p gr20,gr24,gr0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 01 00 98 	addx\.p gr16,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 41 10 	sub\.p gr20,gr16,gr0
+[0-9a-f ]+:	00 01 41 08 	sub\.p gr20,gr8,gr0
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-2.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-2.d
new file mode 100644
index 0000000..d2b794f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-2.d
@@ -0,0 +1,94 @@
+#name: FRV uClinux PIC relocs to global symbols, static linking
+#source: fdpic2.s
+#objdump: -D
+#ld: -static
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<F2>:
+[0-9a-f ]+:	80 3c 00 01 	call [0-9a-f]+ <GF0>
+
+[0-9a-f ]+<GF0>:
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 24 	setlos 0x24,gr0
+[0-9a-f ]+:	80 f4 00 20 	setlo 0x20,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 18 	setlos 0x18,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff d0 	setlos 0xf*ffffffd0,gr0
+[0-9a-f ]+:	80 f4 ff c8 	setlo 0xffc8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff c0 	addi gr15,-64,gr0
+[0-9a-f ]+:	80 fc ff c0 	setlos 0xf*ffffffc0,gr0
+[0-9a-f ]+:	80 f4 ff c0 	setlo 0xffc0,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 1c 	setlo 0x1c,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.rofixup:
+
+[0-9a-f ]+<__ROFIXUP_LIST__>:
+[0-9a-f ]+:	00 01 41 98 	subx\.p gr20,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 41 ac 	subx\.p gr20,gr44,gr0,icc0
+[0-9a-f ]+:	00 01 41 a8 	subx\.p gr20,gr40,gr0,icc0
+[0-9a-f ]+:	00 01 41 94 	subx\.p gr20,gr20,gr0,icc0
+[0-9a-f ]+:	00 01 41 60 	subcc\.p gr20,gr32,gr0,icc0
+[0-9a-f ]+:	00 01 41 64 	subcc\.p gr20,gr36,gr0,icc0
+[0-9a-f ]+:	00 01 41 a0 	subx\.p gr20,gr32,gr0,icc0
+[0-9a-f ]+:	00 01 41 70 	subcc\.p gr20,gr48,gr0,icc0
+[0-9a-f ]+:	00 01 41 74 	subcc\.p gr20,gr52,gr0,icc0
+[0-9a-f ]+:	00 01 41 9c 	subx\.p gr20,gr28,gr0,icc0
+[0-9a-f ]+:	00 01 41 78 	subcc\.p gr20,gr56,gr0,icc0
+[0-9a-f ]+:	00 01 41 7c 	subcc\.p gr20,gr60,gr0,icc0
+[0-9a-f ]+:	00 01 41 80 	subx\.p gr20,gr0,gr0,icc0
+[0-9a-f ]+:	00 01 41 84 	subx\.p gr20,gr4,gr0,icc0
+[0-9a-f ]+:	00 01 41 58 	subcc\.p gr20,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 41 5c 	subcc\.p gr20,gr28,gr0,icc0
+[0-9a-f ]+:	00 01 41 50 	subcc\.p gr20,gr16,gr0,icc0
+[0-9a-f ]+:	00 01 41 54 	subcc\.p gr20,gr20,gr0,icc0
+[0-9a-f ]+:	00 01 41 a4 	subx\.p gr20,gr36,gr0,icc0
+[0-9a-f ]+:	00 01 41 44 	subcc\.p gr20,gr4,gr0,icc0
+[0-9a-f ]+:	00 01 41 68 	subcc\.p gr20,gr40,gr0,icc0
+[0-9a-f ]+:	00 01 41 6c 	subcc\.p gr20,gr44,gr0,icc0
+[0-9a-f ]+:	00 01 41 48 	subcc\.p gr20,gr8,gr0,icc0
+[0-9a-f ]+:	00 01 41 4c 	subcc\.p gr20,gr12,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D2>:
+[0-9a-f ]+:	00 01 41 48 	subcc\.p gr20,gr8,gr0,icc0
+
+[0-9a-f ]+<GD0>:
+[0-9a-f ]+:	00 01 41 68 	subcc\.p gr20,gr40,gr0,icc0
+[0-9a-f ]+:	00 01 00 98 	addx\.p gr16,gr24,gr0,icc0
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x38>:
+[0-9a-f ]+:	00 01 00 98 	addx\.p gr16,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+[0-9a-f ]+:	00 01 00 98 	addx\.p gr16,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+[0-9a-f ]+:	00 01 00 98 	addx\.p gr16,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+[0-9a-f ]+:	00 01 00 98 	addx\.p gr16,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+[0-9a-f ]+:	00 01 00 98 	addx\.p gr16,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+[0-9a-f ]+:	00 01 00 98 	addx\.p gr16,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+[0-9a-f ]+:	00 01 00 98 	addx\.p gr16,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 01 41 60 	subcc\.p gr20,gr32,gr0,icc0
+[0-9a-f ]+:	00 01 00 98 	addx\.p gr16,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 41 78 	subcc\.p gr20,gr56,gr0,icc0
+[0-9a-f ]+:	00 01 41 70 	subcc\.p gr20,gr48,gr0,icc0
+[0-9a-f ]+:	00 01 41 48 	subcc\.p gr20,gr8,gr0,icc0
+[0-9a-f ]+:	00 01 00 98 	addx\.p gr16,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 00 98 	addx\.p gr16,gr24,gr0,icc0
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-5.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-5.d
new file mode 100644
index 0000000..ce687b8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-5.d
@@ -0,0 +1,5 @@
+#name: FRV uClinux PIC relocs to undefined symbols, static linking
+#source: fdpic5.s
+#objdump: -D
+#ld: -static
+#error: undefined reference
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-6.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-6.d
new file mode 100644
index 0000000..491b7c7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-6.d
@@ -0,0 +1,43 @@
+#name: FRV uClinux PIC relocs to weak undefined symbols, static linking
+#source: fdpic6.s
+#objdump: -D
+#ld: -static
+#warning: different segment
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<F6>:
+[0-9a-f ]+:	fe 3f bf db 	call 0 <_gp-0xf8d8>
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 24 	setlos 0x24,gr0
+[0-9a-f ]+:	80 f4 00 20 	setlo 0x20,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 18 	setlos 0x18,gr0
+[0-9a-f ]+:	80 f4 00 1c 	setlo 0x1c,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff f0 	setlos 0xf*fffffff0,gr0
+[0-9a-f ]+:	80 f4 ff e8 	setlo 0xffe8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 be e0 	setlo 0xbee0,gr0
+[0-9a-f ]+:	80 f8 ff fe 	sethi 0xfffe,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.rofixup:
+
+[0-9a-f ]+<__ROFIXUP_LIST__>:
+[0-9a-f ]+:	00 01 41 20 	sub\.p gr20,gr32,gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D6>:
+	\.\.\.
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x38>:
+	\.\.\.
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-7.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-7.d
new file mode 100644
index 0000000..6f8313c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-7.d
@@ -0,0 +1,62 @@
+#name: FRV uClinux PIC relocs to local symbols with addends, static linking
+#source: fdpic7.s
+#objdump: -D
+#ld: -static
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<F7>:
+[0-9a-f ]+:	80 3c 00 02 	call [0-9a-f]+ <\.F0\+0x4>
+
+[0-9a-f ]+<\.F0>:
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 0c 	setlos 0xc,gr0
+[0-9a-f ]+:	80 f4 00 0c 	setlo 0xc,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 10 	setlos 0x10,gr0
+[0-9a-f ]+:	80 f4 00 10 	setlo 0x10,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff f8 	setlos 0xf*fffffff8,gr0
+[0-9a-f ]+:	80 f4 ff f8 	setlo 0xfff8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff f4 	addi gr15,-12,gr0
+[0-9a-f ]+:	80 fc ff f4 	setlos 0xf*fffffff4,gr0
+[0-9a-f ]+:	80 f4 ff f4 	setlo 0xfff4,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 14 	setlo 0x14,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.rofixup:
+
+[0-9a-f ]+<__ROFIXUP_LIST__>:
+[0-9a-f ]+:	00 01 41 24 	sub\.p gr20,gr36,gr0
+[0-9a-f ]+:	00 01 41 28 	sub\.p gr20,gr40,gr0
+[0-9a-f ]+:	00 01 41 10 	sub\.p gr20,gr16,gr0
+[0-9a-f ]+:	00 01 41 14 	sub\.p gr20,gr20,gr0
+[0-9a-f ]+:	00 01 41 2c 	sub\.p gr20,gr44,gr0
+[0-9a-f ]+:	00 01 41 04 	sub\.p gr20,gr4,gr0
+[0-9a-f ]+:	00 01 41 08 	sub\.p gr20,gr8,gr0
+[0-9a-f ]+:	00 01 41 0c 	sub\.p gr20,gr12,gr0
+[0-9a-f ]+:	00 01 41 18 	sub\.p gr20,gr24,gr0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D7>:
+[0-9a-f ]+:	00 01 41 0c 	sub\.p gr20,gr12,gr0
+
+[0-9a-f ]+<\.D0>:
+[0-9a-f ]+:	00 01 41 10 	sub\.p gr20,gr16,gr0
+[0-9a-f ]+:	00 01 00 9c 	addx\.p gr16,gr28,gr0,icc0
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x8>:
+[0-9a-f ]+:	00 01 00 9c 	addx\.p gr16,gr28,gr0,icc0
+[0-9a-f ]+:	00 01 41 18 	sub\.p gr20,gr24,gr0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 01 00 9c 	addx\.p gr16,gr28,gr0,icc0
+[0-9a-f ]+:	00 01 41 10 	sub\.p gr20,gr16,gr0
+[0-9a-f ]+:	00 01 41 0c 	sub\.p gr20,gr12,gr0
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-8.d b/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-8.d
new file mode 100644
index 0000000..c0cc732
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic-static-8.d
@@ -0,0 +1,94 @@
+#name: FRV uClinux PIC relocs to global symbols with addends, static linking
+#source: fdpic8.s
+#objdump: -D
+#ld: -static
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<F8>:
+[0-9a-f ]+:	80 3c 00 02 	call [0-9a-f]+ <GF0\+0x4>
+
+[0-9a-f ]+<GF0>:
+[0-9a-f ]+:	80 40 f0 10 	addi gr15,16,gr0
+[0-9a-f ]+:	80 fc 00 14 	setlos 0x14,gr0
+[0-9a-f ]+:	80 f4 00 24 	setlo 0x24,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 f0 0c 	addi gr15,12,gr0
+[0-9a-f ]+:	80 fc 00 1c 	setlos 0x1c,gr0
+[0-9a-f ]+:	80 f4 00 18 	setlo 0x18,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+[0-9a-f ]+:	80 40 ff f8 	addi gr15,-8,gr0
+[0-9a-f ]+:	80 fc ff f0 	setlos 0xf*fffffff0,gr0
+[0-9a-f ]+:	80 f4 ff c8 	setlo 0xffc8,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 40 ff c4 	addi gr15,-60,gr0
+[0-9a-f ]+:	80 fc ff c4 	setlos 0xf*ffffffc4,gr0
+[0-9a-f ]+:	80 f4 ff c4 	setlo 0xffc4,gr0
+[0-9a-f ]+:	80 f8 ff ff 	sethi 0xffff,gr0
+[0-9a-f ]+:	80 f4 00 20 	setlo 0x20,gr0
+[0-9a-f ]+:	80 f8 00 00 	sethi hi\(0x0\),gr0
+Disassembly of section \.rofixup:
+
+[0-9a-f ]+<__ROFIXUP_LIST__>:
+[0-9a-f ]+:	00 01 41 98 	subx\.p gr20,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 41 9c 	subx\.p gr20,gr28,gr0,icc0
+[0-9a-f ]+:	00 01 41 ac 	subx\.p gr20,gr44,gr0,icc0
+[0-9a-f ]+:	00 01 41 94 	subx\.p gr20,gr20,gr0,icc0
+[0-9a-f ]+:	00 01 41 58 	subcc\.p gr20,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 41 5c 	subcc\.p gr20,gr28,gr0,icc0
+[0-9a-f ]+:	00 01 41 a4 	subx\.p gr20,gr36,gr0,icc0
+[0-9a-f ]+:	00 01 41 68 	subcc\.p gr20,gr40,gr0,icc0
+[0-9a-f ]+:	00 01 41 6c 	subcc\.p gr20,gr44,gr0,icc0
+[0-9a-f ]+:	00 01 41 a0 	subx\.p gr20,gr32,gr0,icc0
+[0-9a-f ]+:	00 01 41 70 	subcc\.p gr20,gr48,gr0,icc0
+[0-9a-f ]+:	00 01 41 74 	subcc\.p gr20,gr52,gr0,icc0
+[0-9a-f ]+:	00 01 41 80 	subx\.p gr20,gr0,gr0,icc0
+[0-9a-f ]+:	00 01 41 84 	subx\.p gr20,gr4,gr0,icc0
+[0-9a-f ]+:	00 01 41 78 	subcc\.p gr20,gr56,gr0,icc0
+[0-9a-f ]+:	00 01 41 7c 	subcc\.p gr20,gr60,gr0,icc0
+[0-9a-f ]+:	00 01 41 50 	subcc\.p gr20,gr16,gr0,icc0
+[0-9a-f ]+:	00 01 41 54 	subcc\.p gr20,gr20,gr0,icc0
+[0-9a-f ]+:	00 01 41 a8 	subx\.p gr20,gr40,gr0,icc0
+[0-9a-f ]+:	00 01 41 44 	subcc\.p gr20,gr4,gr0,icc0
+[0-9a-f ]+:	00 01 41 60 	subcc\.p gr20,gr32,gr0,icc0
+[0-9a-f ]+:	00 01 41 64 	subcc\.p gr20,gr36,gr0,icc0
+[0-9a-f ]+:	00 01 41 48 	subcc\.p gr20,gr8,gr0,icc0
+[0-9a-f ]+:	00 01 41 4c 	subcc\.p gr20,gr12,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+Disassembly of section \.dat[0-9a-f ]+:
+
+[0-9a-f ]+<D8>:
+[0-9a-f ]+:	00 01 41 4c 	subcc\.p gr20,gr12,gr0,icc0
+
+[0-9a-f ]+<GD0>:
+[0-9a-f ]+:	00 01 41 60 	subcc\.p gr20,gr32,gr0,icc0
+[0-9a-f ]+:	00 01 00 9c 	addx\.p gr16,gr28,gr0,icc0
+Disassembly of section \.got:
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x38>:
+[0-9a-f ]+:	00 01 00 9c 	addx\.p gr16,gr28,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+[0-9a-f ]+:	00 01 00 9c 	addx\.p gr16,gr28,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+[0-9a-f ]+:	00 01 00 9c 	addx\.p gr16,gr28,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+[0-9a-f ]+:	00 01 00 9c 	addx\.p gr16,gr28,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+[0-9a-f ]+:	00 01 00 9c 	addx\.p gr16,gr28,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+[0-9a-f ]+:	00 01 00 9c 	addx\.p gr16,gr28,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+[0-9a-f ]+:	00 01 00 9c 	addx\.p gr16,gr28,gr0,icc0
+[0-9a-f ]+:	00 01 41 88 	subx\.p gr20,gr8,gr0,icc0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 01 41 58 	subcc\.p gr20,gr24,gr0,icc0
+[0-9a-f ]+:	00 01 00 9c 	addx\.p gr16,gr28,gr0,icc0
+[0-9a-f ]+:	00 01 00 9c 	addx\.p gr16,gr28,gr0,icc0
+[0-9a-f ]+:	00 01 41 70 	subcc\.p gr20,gr48,gr0,icc0
+[0-9a-f ]+:	00 01 41 68 	subcc\.p gr20,gr40,gr0,icc0
+[0-9a-f ]+:	00 01 41 4c 	subcc\.p gr20,gr12,gr0,icc0
+[0-9a-f ]+:	00 01 00 9c 	addx\.p gr16,gr28,gr0,icc0
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic.exp b/binutils-2.19/ld/testsuite/ld-frv/fdpic.exp
new file mode 100644
index 0000000..90da0d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic.exp
@@ -0,0 +1,69 @@
+# Expect script for FRV FDPIC linker tests
+#   Copyright 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+if {![istarget frv*-*-*] || ![is_elf_format]} {
+    return
+}
+
+global ASFLAGS
+set saved_ASFLAGS "$ASFLAGS"
+set ASFLAGS "$ASFLAGS -mfdpic"
+
+global LDFLAGS
+set saved_LDFLAGS "$LDFLAGS"
+set LDFLAGS "$LDFLAGS -melf32frvfd"
+
+run_dump_test "fdpic-static-1"
+run_dump_test "fdpic-pie-1"
+run_dump_test "fdpic-shared-1"
+
+run_dump_test "fdpic-static-2"
+run_dump_test "fdpic-pie-2"
+run_dump_test "fdpic-shared-2-fail"
+run_dump_test "fdpic-shared-2"
+run_dump_test "fdpic-shared-local-2"
+
+run_dump_test "fdpic-shared-3"
+
+run_dump_test "fdpic-shared-4"
+
+run_dump_test "fdpic-static-5"
+run_dump_test "fdpic-pie-5"
+run_dump_test "fdpic-shared-5"
+
+run_dump_test "fdpic-static-6"
+run_dump_test "fdpic-pie-6-fail"
+run_dump_test "fdpic-pie-6"
+run_dump_test "fdpic-shared-6-fail"
+run_dump_test "fdpic-shared-6"
+
+run_dump_test "fdpic-static-7"
+run_dump_test "fdpic-pie-7"
+run_dump_test "fdpic-shared-7"
+
+run_dump_test "fdpic-static-8"
+run_dump_test "fdpic-pie-8"
+run_dump_test "fdpic-shared-8-fail"
+run_dump_test "fdpic-shared-8"
+run_dump_test "fdpic-shared-local-8"
+
+set LDFLAGS "$saved_LDFLAGS"
+set ASFLAGS "$saved_ASFLAGS"
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic1.s b/binutils-2.19/ld/testsuite/ld-frv/fdpic1.s
new file mode 100644
index 0000000..29f7fff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic1.s
@@ -0,0 +1,64 @@
+	.text
+	.weak _start
+_start:
+	.global F1
+	.type F1,@function
+F1:
+	call	.F0
+
+.F0:
+.F1:
+.F2:
+.F3:
+.F4:
+.F5:
+.F6:
+.F7:
+.F8:
+.F9:
+.Fa:
+.Fb:
+.Fc:
+	addi	gr15, #got12(.F1), gr0
+	
+	setlos	#gotlo(.F2), gr0
+	
+	setlo	#gotlo(.F3), gr0
+	sethi	#gothi(.F3), gr0
+
+	addi	gr15, #gotfuncdesc12(.F4), gr0
+
+	setlos	#gotfuncdesclo(.F5), gr0
+
+	setlo	#gotfuncdesclo(.F6), gr0
+	sethi	#gotfuncdeschi(.F6), gr0
+
+	addi	gr15, #gotofffuncdesc12(.F7), gr0
+
+	setlos	#gotofffuncdesclo(.F8), gr0
+
+	setlo	#gotofffuncdesclo(.F9), gr0
+	sethi	#gotofffuncdeschi(.F9), gr0
+
+	addi	gr15, #gotoff12(.D1), gr0
+	
+	setlos	#gotofflo(.D2), gr0
+
+	setlo	#gotofflo(.D3), gr0
+	sethi	#gotoffhi(.D3), gr0
+
+	setlo	#gotlo(.D4), gr0
+	sethi	#gothi(.D4), gr0
+
+	.data
+	.global D1
+D1:
+	.word	.D0
+	.section .data.rel.local
+.D0:
+.D1:
+.D2:
+.D3:
+.D4:
+	.picptr funcdesc(.Fb)
+	.word	.Fb
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic2.ldv b/binutils-2.19/ld/testsuite/ld-frv/fdpic2.ldv
new file mode 100644
index 0000000..b5aad4f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic2.ldv
@@ -0,0 +1 @@
+{ global: _start; F2; D2; local: *; };
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic2.s b/binutils-2.19/ld/testsuite/ld-frv/fdpic2.s
new file mode 100644
index 0000000..2987643
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic2.s
@@ -0,0 +1,81 @@
+	.text
+	.weak _start
+_start:
+	.global F2
+	.type F2,@function
+F2:
+	call	GF0
+	.global GF0
+	.global GF1
+	.global GF2
+	.global GF3
+	.global GF4
+	.global GF5
+	.global GF6
+	.global GF7
+	.global GF8
+	.global GF9
+	.global GFa
+	.global GFb
+	.global GFc
+GF0:
+GF1:
+GF2:
+GF3:
+GF4:
+GF5:
+GF6:
+GF7:
+GF8:
+GF9:
+GFa:
+GFb:
+GFc:
+	addi	gr15, #got12(GF1), gr0
+	
+	setlos	#gotlo(GF2), gr0
+	
+	setlo	#gotlo(GF3), gr0
+	sethi	#gothi(GF3), gr0
+
+	addi	gr15, #gotfuncdesc12(GF4), gr0
+
+	setlos	#gotfuncdesclo(GF5), gr0
+
+	setlo	#gotfuncdesclo(GF6), gr0
+	sethi	#gotfuncdeschi(GF6), gr0
+
+	addi	gr15, #gotofffuncdesc12(GF7), gr0
+
+	setlos	#gotofffuncdesclo(GF8), gr0
+
+	setlo	#gotofffuncdesclo(GF9), gr0
+	sethi	#gotofffuncdeschi(GF9), gr0
+
+	addi	gr15, #gotoff12(GD1), gr0
+	
+	setlos	#gotofflo(GD2), gr0
+
+	setlo	#gotofflo(GD3), gr0
+	sethi	#gotoffhi(GD3), gr0
+
+	setlo	#gotlo(GD4), gr0
+	sethi	#gothi(GD4), gr0
+
+	.data
+	.global D2
+D2:
+	.word	GD0
+	
+	.global GD0
+	.global GD1
+	.global GD2
+	.global GD3
+	.global GD4
+GD0:
+GD1:
+GD2:
+GD3:
+GD4:
+	.picptr funcdesc(GFb)
+	.word	GFb
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic2min.ldv b/binutils-2.19/ld/testsuite/ld-frv/fdpic2min.ldv
new file mode 100644
index 0000000..2804526
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic2min.ldv
@@ -0,0 +1 @@
+{ global: _start; F*; GF*; D2; GD0; GD4; local: GD1; GD2; GD3; };
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic3.s b/binutils-2.19/ld/testsuite/ld-frv/fdpic3.s
new file mode 100644
index 0000000..f867b93
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic3.s
@@ -0,0 +1,99 @@
+	.text
+	.weak _start
+_start:
+	.global F3
+	.type F3,@function
+F3:
+	call	HF0
+	.global HF0
+	.hidden HF0
+	.global HF1
+	.hidden HF1
+	.global HF2
+	.hidden HF2
+	.global HF3
+	.hidden HF3
+	.global HF4
+	.hidden HF4
+	.global HF5
+	.hidden HF5
+	.global HF6
+	.hidden HF6
+	.global HF7
+	.hidden HF7
+	.global HF8
+	.hidden HF8
+	.global HF9
+	.hidden HF9
+	.global HFa
+	.hidden HFa
+	.global HFb
+	.hidden HFb
+	.global HFc
+	.hidden HFc
+HF0:
+HF1:
+HF2:
+HF3:
+HF4:
+HF5:
+HF6:
+HF7:
+HF8:
+HF9:
+HFa:
+HFb:
+HFc:
+	addi	gr15, #got12(HF1), gr0
+	
+	setlos	#gotlo(HF2), gr0
+	
+	setlo	#gotlo(HF3), gr0
+	sethi	#gothi(HF3), gr0
+
+	addi	gr15, #gotfuncdesc12(HF4), gr0
+
+	setlos	#gotfuncdesclo(HF5), gr0
+
+	setlo	#gotfuncdesclo(HF6), gr0
+	sethi	#gotfuncdeschi(HF6), gr0
+
+	addi	gr15, #gotofffuncdesc12(HF7), gr0
+
+	setlos	#gotofffuncdesclo(HF8), gr0
+
+	setlo	#gotofffuncdesclo(HF9), gr0
+	sethi	#gotofffuncdeschi(HF9), gr0
+
+	addi	gr15, #gotoff12(HD1), gr0
+	
+	setlos	#gotofflo(HD2), gr0
+
+	setlo	#gotofflo(HD3), gr0
+	sethi	#gotoffhi(HD3), gr0
+
+	setlo	#gotlo(HD4), gr0
+	sethi	#gothi(HD4), gr0
+
+	.data
+	.global D3
+D3:
+	.word	HD0
+	
+	.global HD0
+	.hidden HD0
+	.global HD1
+	.hidden HD1
+	.global HD2
+	.hidden HD2
+	.global HD3
+	.hidden HD3
+	.global HD4
+	.hidden HD4
+HD0:
+HD1:
+HD2:
+HD3:
+HD4:
+	.picptr funcdesc(HFb)
+	.word	HFb
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic4.s b/binutils-2.19/ld/testsuite/ld-frv/fdpic4.s
new file mode 100644
index 0000000..795ae45
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic4.s
@@ -0,0 +1,99 @@
+	.text
+	.weak _start
+_start:
+	.global F4
+	.type F4,@function
+F4:
+	call	PF0
+	.global PF0
+	.protected PF0
+	.global PF1
+	.protected PF1
+	.global PF2
+	.protected PF2
+	.global PF3
+	.protected PF3
+	.global PF4
+	.protected PF4
+	.global PF5
+	.protected PF5
+	.global PF6
+	.protected PF6
+	.global PF7
+	.protected PF7
+	.global PF8
+	.protected PF8
+	.global PF9
+	.protected PF9
+	.global PFa
+	.protected PFa
+	.global PFb
+	.protected PFb
+	.global PFc
+	.protected PFc
+PF0:
+PF1:
+PF2:
+PF3:
+PF4:
+PF5:
+PF6:
+PF7:
+PF8:
+PF9:
+PFa:
+PFb:
+PFc:
+	addi	gr15, #got12(PF1), gr0
+	
+	setlos	#gotlo(PF2), gr0
+	
+	setlo	#gotlo(PF3), gr0
+	sethi	#gothi(PF3), gr0
+
+	addi	gr15, #gotfuncdesc12(PF4), gr0
+
+	setlos	#gotfuncdesclo(PF5), gr0
+
+	setlo	#gotfuncdesclo(PF6), gr0
+	sethi	#gotfuncdeschi(PF6), gr0
+
+	addi	gr15, #gotofffuncdesc12(PF7), gr0
+
+	setlos	#gotofffuncdesclo(PF8), gr0
+
+	setlo	#gotofffuncdesclo(PF9), gr0
+	sethi	#gotofffuncdeschi(PF9), gr0
+
+	addi	gr15, #gotoff12(PD1), gr0
+	
+	setlos	#gotofflo(PD2), gr0
+
+	setlo	#gotofflo(PD3), gr0
+	sethi	#gotoffhi(PD3), gr0
+
+	setlo	#gotlo(PD4), gr0
+	sethi	#gothi(PD4), gr0
+
+	.data
+	.global D4
+D4:
+	.word	PD0
+	
+	.global PD0
+	.protected PD0
+	.global PD1
+	.protected PD1
+	.global PD2
+	.protected PD2
+	.global PD3
+	.protected PD3
+	.global PD4
+	.protected PD4
+PD0:
+PD1:
+PD2:
+PD3:
+PD4:
+	.picptr funcdesc(PFb)
+	.word	PFb
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic5.s b/binutils-2.19/ld/testsuite/ld-frv/fdpic5.s
new file mode 100644
index 0000000..f4d466a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic5.s
@@ -0,0 +1,38 @@
+	.text
+	.weak _start
+_start:
+	.global F5
+	.type F5,@function
+F5:
+	call	UF0
+	addi	gr15, #got12(UF1), gr0
+	
+	setlos	#gotlo(UF2), gr0
+	
+	setlo	#gotlo(UF3), gr0
+	sethi	#gothi(UF3), gr0
+
+	addi	gr15, #gotfuncdesc12(UF4), gr0
+
+	setlos	#gotfuncdesclo(UF5), gr0
+
+	setlo	#gotfuncdesclo(UF6), gr0
+	sethi	#gotfuncdeschi(UF6), gr0
+
+	addi	gr15, #gotofffuncdesc12(UF7), gr0
+
+	setlos	#gotofffuncdesclo(UF8), gr0
+
+	setlo	#gotofffuncdesclo(UF9), gr0
+	sethi	#gotofffuncdeschi(UF9), gr0
+
+	setlo	#gotlo(UD1), gr0
+	sethi	#gothi(UD1), gr0
+
+	.data
+	.global D5
+D5:
+	.word	UD0
+	
+	.picptr funcdesc(UFb)
+	.word	UFb
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic6.ldv b/binutils-2.19/ld/testsuite/ld-frv/fdpic6.ldv
new file mode 100644
index 0000000..5e46c03
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic6.ldv
@@ -0,0 +1 @@
+{ global: _start; F6; D6; WF*; local: *; };
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic6.s b/binutils-2.19/ld/testsuite/ld-frv/fdpic6.s
new file mode 100644
index 0000000..cd8e1d0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic6.s
@@ -0,0 +1,55 @@
+	.text
+	.weak _start
+_start:
+	.weak WF0
+	.weak WF1
+	.weak WF2
+	.weak WF3
+	.weak WF4
+	.weak WF5
+	.weak WF6
+	.weak WF7
+	.weak WF8
+	.weak WF9
+	.weak WFb
+	.weak WD0
+	.weak WD1
+	.weak WD2
+	.global F6
+	.type F6,@function
+F6:
+	call	WF0
+	addi	gr15, #got12(WF1), gr0
+	
+	setlos	#gotlo(WF2), gr0
+	
+	setlo	#gotlo(WF3), gr0
+	sethi	#gothi(WF3), gr0
+
+	addi	gr15, #gotfuncdesc12(WF4), gr0
+
+	setlos	#gotfuncdesclo(WF5), gr0
+
+	setlo	#gotfuncdesclo(WF6), gr0
+	sethi	#gotfuncdeschi(WF6), gr0
+
+	addi	gr15, #gotofffuncdesc12(WF7), gr0
+
+	setlos	#gotofffuncdesclo(WF8), gr0
+
+	setlo	#gotofffuncdesclo(WF9), gr0
+	sethi	#gotofffuncdeschi(WF9), gr0
+
+	setlo	#gotofflo(WD1), gr0
+	sethi	#gotoffhi(WD1), gr0
+
+	setlo	#gotlo(WD2), gr0
+	sethi	#gothi(WD2), gr0
+
+	.data
+	.global D6
+D6:
+	.word	WD0
+	
+	.picptr funcdesc(WFb)
+	.word	WFb
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic7.s b/binutils-2.19/ld/testsuite/ld-frv/fdpic7.s
new file mode 100644
index 0000000..ceac5fc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic7.s
@@ -0,0 +1,63 @@
+	.text
+	.weak _start
+_start:
+	.global F7
+	.type F7,@function
+F7:
+	call	.F0+4
+
+.F0:
+.F1:
+.F2:
+.F3:
+.F4:
+.F5:
+.F6:
+.F7:
+.F8:
+.F9:
+.Fa:
+.Fb:
+.Fc:
+	addi	gr15, #got12(.F1+4), gr0
+	
+	setlos	#gotlo(.F2+4), gr0
+	
+	setlo	#gotlo(.F3+4), gr0
+	sethi	#gothi(.F3+4), gr0
+
+	addi	gr15, #gotfuncdesc12(.F4+4), gr0
+
+	setlos	#gotfuncdesclo(.F5+4), gr0
+
+	setlo	#gotfuncdesclo(.F6+4), gr0
+	sethi	#gotfuncdeschi(.F6+4), gr0
+
+	addi	gr15, #gotofffuncdesc12(.F7+4), gr0
+
+	setlos	#gotofffuncdesclo(.F8+4), gr0
+
+	setlo	#gotofffuncdesclo(.F9+4), gr0
+	sethi	#gotofffuncdeschi(.F9+4), gr0
+
+	addi	gr15, #gotoff12(.D1+4), gr0
+	
+	setlos	#gotofflo(.D2+4), gr0
+
+	setlo	#gotofflo(.D3+4), gr0
+	sethi	#gotoffhi(.D3+4), gr0
+
+	setlo	#gotlo(.D4+4), gr0
+	sethi	#gothi(.D4+4), gr0
+
+	.data
+	.global D7
+D7:
+	.word	.D0+4
+.D0:
+.D1:
+.D2:
+.D3:
+.D4:
+	.picptr funcdesc(.Fb+4)
+	.word	.Fb+4
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic8.ldv b/binutils-2.19/ld/testsuite/ld-frv/fdpic8.ldv
new file mode 100644
index 0000000..d258f96
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic8.ldv
@@ -0,0 +1 @@
+{ global: _start; F8; D8; local: *; };
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic8.s b/binutils-2.19/ld/testsuite/ld-frv/fdpic8.s
new file mode 100644
index 0000000..037250f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic8.s
@@ -0,0 +1,81 @@
+	.text
+	.weak _start
+_start:
+	.global F8
+	.type F8,@function
+F8:
+	call	GF0+4
+	.global GF0
+	.global GF1
+	.global GF2
+	.global GF3
+	.global GF4
+	.global GF5
+	.global GF6
+	.global GF7
+	.global GF8
+	.global GF9
+	.global GFa
+	.global GFb
+	.global GFc
+GF0:
+GF1:
+GF2:
+GF3:
+GF4:
+GF5:
+GF6:
+GF7:
+GF8:
+GF9:
+GFa:
+GFb:
+GFc:
+	addi	gr15, #got12(GF1+4), gr0
+	
+	setlos	#gotlo(GF2+4), gr0
+	
+	setlo	#gotlo(GF3+4), gr0
+	sethi	#gothi(GF3+4), gr0
+
+	addi	gr15, #gotfuncdesc12(GF4+4), gr0
+
+	setlos	#gotfuncdesclo(GF5+4), gr0
+
+	setlo	#gotfuncdesclo(GF6+4), gr0
+	sethi	#gotfuncdeschi(GF6+4), gr0
+
+	addi	gr15, #gotofffuncdesc12(GF7+4), gr0
+
+	setlos	#gotofffuncdesclo(GF8+4), gr0
+
+	setlo	#gotofffuncdesclo(GF9+4), gr0
+	sethi	#gotofffuncdeschi(GF9+4), gr0
+
+	addi	gr15, #gotoff12(GD1+4), gr0
+	
+	setlos	#gotofflo(GD2+4), gr0
+
+	setlo	#gotofflo(GD3+4), gr0
+	sethi	#gotoffhi(GD3+4), gr0
+
+	setlo	#gotlo(GD4+4), gr0
+	sethi	#gothi(GD4+4), gr0
+
+	.data
+	.global D8
+D8:
+	.word	GD0+4
+	
+	.global GD0
+	.global GD1
+	.global GD2
+	.global GD3
+	.global GD4
+GD0:
+GD1:
+GD2:
+GD3:
+GD4:
+	.picptr funcdesc(GFb+4)
+	.word	GFb+4
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fdpic8min.ldv b/binutils-2.19/ld/testsuite/ld-frv/fdpic8min.ldv
new file mode 100644
index 0000000..aeadb79
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fdpic8min.ldv
@@ -0,0 +1 @@
+{ global: _start; F8; GF1; GF2; GF3; D8; GD0; GD4; local: GF0; GF4; GF5; GF6; GF7; GF8; GF9; GFb; GD1; GD2; GD3; };
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fr450-link.d b/binutils-2.19/ld/testsuite/ld-frv/fr450-link.d
new file mode 100644
index 0000000..1ab80b0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fr450-link.d
@@ -0,0 +1,11 @@
+#source: fr450-linka.s -mcpu=fr400
+#source: fr450-linkb.s -mcpu=fr405
+#source: fr450-linkc.s -mcpu=fr450
+#source: fr450-linkb.s -mcpu=fr405
+#source: fr450-linka.s -mcpu=fr400
+#ld: -r
+#objdump: -p
+
+.*:     file format elf32-frv(|fdpic)
+private flags = 0x800[08]000: -mcpu=fr450(| -mfdpic)
+
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fr450-linka.s b/binutils-2.19/ld/testsuite/ld-frv/fr450-linka.s
new file mode 100644
index 0000000..4e7fe2f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fr450-linka.s
@@ -0,0 +1 @@
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fr450-linkb.s b/binutils-2.19/ld/testsuite/ld-frv/fr450-linkb.s
new file mode 100644
index 0000000..4e7fe2f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fr450-linkb.s
@@ -0,0 +1 @@
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-frv/fr450-linkc.s b/binutils-2.19/ld/testsuite/ld-frv/fr450-linkc.s
new file mode 100644
index 0000000..4e7fe2f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/fr450-linkc.s
@@ -0,0 +1 @@
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-frv/frv-elf.exp b/binutils-2.19/ld/testsuite/ld-frv/frv-elf.exp
new file mode 100644
index 0000000..961e0de
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/frv-elf.exp
@@ -0,0 +1,23 @@
+# Expect script for FRV specific linker tests
+#   Copyright (C) 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+if [istarget frv*-*-*] {
+    run_dump_test "fr450-link"
+}
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-1-dep.s b/binutils-2.19/ld/testsuite/ld-frv/tls-1-dep.s
new file mode 100644
index 0000000..75daab7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-1-dep.s
@@ -0,0 +1,7 @@
+        .section        .tbss,"awT",@nobits
+        .align 4
+	.globl x
+        .type   x, @tls_object
+        .size   x, 4
+x:
+        .zero   4
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-1-shared.lds b/binutils-2.19/ld/testsuite/ld-frv/tls-1-shared.lds
new file mode 100644
index 0000000..3769e01
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-1-shared.lds
@@ -0,0 +1,3 @@
+{
+  local: x; i;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-1.s b/binutils-2.19/ld/testsuite/ld-frv/tls-1.s
new file mode 100644
index 0000000..a13c91b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-1.s
@@ -0,0 +1,85 @@
+        .section        .tbss,"awT",@nobits
+        .align 4
+	.globl i
+        .type   i, @object
+        .size   i, 4
+i:
+        .zero   4
+        .align 4
+        .type   l, @object
+        .size   l, 4
+l:
+        .zero   4
+	.text
+	.globl	_start
+_start:
+	call	#gettlsoff(x)
+
+	sethi.p	#gottlsdeschi(x), gr14
+	setlo	#gottlsdesclo(x), gr14
+	ldd	#tlsdesc(x)@(gr15, gr14), gr8
+	calll	#gettlsoff(x)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(x)), gr8
+	setlos	#gottlsdesclo(x), gr14
+	calll	#gettlsoff(x)@(gr8, gr0)
+
+	call	#gettlsoff(i)
+
+	sethi.p	#gottlsdeschi(i), gr14
+	setlo	#gottlsdesclo(i), gr14
+	ldd	#tlsdesc(i)@(gr15, gr14), gr8
+	calll	#gettlsoff(i)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(i)), gr8
+	setlos	#gottlsdesclo(i), gr14
+	calll	#gettlsoff(i)@(gr8, gr0)
+
+	call	#gettlsoff(l)
+
+	sethi.p	#gottlsdeschi(l), gr14
+	setlo	#gottlsdesclo(l), gr14
+	ldd	#tlsdesc(l)@(gr15, gr14), gr8
+	calll	#gettlsoff(l)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(l)), gr8
+	setlos	#gottlsdesclo(l), gr14
+	calll	#gettlsoff(l)@(gr8, gr0)
+
+	call	#gettlsoff(0)
+
+	sethi.p	#gottlsdeschi(0), gr14
+	setlo	#gottlsdesclo(0), gr14
+	ldd	#tlsdesc(0)@(gr15, gr14), gr8
+	calll	#gettlsoff(0)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(0)), gr8
+	setlos	#gottlsdesclo(0), gr14
+	calll	#gettlsoff(0)@(gr8, gr0)
+
+	sethi.p	#tlsmoffhi(l), gr8
+	setlo	#tlsmofflo(l), gr8
+
+	sethi.p	#tlsmoffhi(i), gr9
+	setlo	#tlsmofflo(i), gr9
+
+	ldi	@(gr15, #gottlsoff12(x)), gr9
+	ldi	@(gr15, #gottlsoff12(i)), gr9
+	ldi	@(gr15, #gottlsoff12(l)), gr9
+	ldi	@(gr15, #gottlsoff12(0)), gr9
+
+	sethi.p	#gottlsoffhi(x), gr14
+	setlo	#gottlsofflo(x), gr14
+	ld	#tlsoff(x)@(gr15, gr14), gr9
+
+	sethi.p	#gottlsoffhi(i), gr14
+	setlo	#gottlsofflo(i), gr14
+	ld	#tlsoff(i)@(gr15, gr14), gr9
+	
+	sethi.p	#gottlsoffhi(l), gr14
+	setlo	#gottlsofflo(l), gr14
+	ld	#tlsoff(l)@(gr15, gr14), gr9
+
+	sethi.p	#gottlsoffhi(0), gr14
+	setlo	#gottlsofflo(0), gr14
+	ld	#tlsoff(0)@(gr15, gr14), gr9
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-2.s b/binutils-2.19/ld/testsuite/ld-frv/tls-2.s
new file mode 100644
index 0000000..f0712e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-2.s
@@ -0,0 +1,183 @@
+        .section        .tbss,"awT",@nobits
+        .align 4
+        .type   l, @object
+        .size   l, 4
+l:
+        .zero   4
+        .align 4
+	.globl i
+        .type   i, @object
+        .size   i, 4
+i:
+        .zero   4
+	.text
+	.globl	_start
+_start:
+	call	#gettlsoff(l+1)
+	call	#gettlsoff(l+1+4096)
+	call	#gettlsoff(l+1+65536)
+
+	sethi.p	#gottlsdeschi(l+2), gr14
+	setlo	#gottlsdesclo(l+2), gr14
+	ldd	#tlsdesc(l+2)@(gr15, gr14), gr8
+	calll	#gettlsoff(l+2)@(gr8, gr0)
+
+	sethi.p	#gottlsdeschi(l+2+4096), gr14
+	setlo	#gottlsdesclo(l+2+4096), gr14
+	ldd	#tlsdesc(l+2+4096)@(gr15, gr14), gr8
+	calll	#gettlsoff(l+2+4096)@(gr8, gr0)
+
+	sethi.p	#gottlsdeschi(l+2+65536), gr14
+	setlo	#gottlsdesclo(l+2+65536), gr14
+	ldd	#tlsdesc(l+2+65536)@(gr15, gr14), gr8
+	calll	#gettlsoff(l+2+65536)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(l+3)), gr8
+	setlos	#gottlsdesclo(l+3), gr14
+	calll	#gettlsoff(l+3)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(l+3+4096)), gr8
+	setlos	#gottlsdesclo(l+3+4096), gr14
+	calll	#gettlsoff(l+3+4096)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(l+3+65536)), gr8
+	setlos	#gottlsdesclo(l+3+65536), gr14
+	calll	#gettlsoff(l+3+65536)@(gr8, gr0)
+
+	sethi	#tlsmoffhi(l+4), gr9
+	setlo	#tlsmofflo(l+4), gr9
+
+	sethi	#tlsmoffhi(l+4+4096), gr9
+	setlo	#tlsmofflo(l+4+4096), gr9
+
+	sethi	#tlsmoffhi(l+4+65536), gr9
+	setlo	#tlsmofflo(l+4+65536), gr9
+
+	call	#gettlsoff(i+1)
+	call	#gettlsoff(i+1+4096)
+	call	#gettlsoff(i+1+65536)
+
+	sethi.p	#gottlsdeschi(i+2), gr14
+	setlo	#gottlsdesclo(i+2), gr14
+	ldd	#tlsdesc(i+2)@(gr15, gr14), gr8
+	calll	#gettlsoff(i+2)@(gr8, gr0)
+
+	sethi.p	#gottlsdeschi(i+2+4096), gr14
+	setlo	#gottlsdesclo(i+2+4096), gr14
+	ldd	#tlsdesc(i+2+4096)@(gr15, gr14), gr8
+	calll	#gettlsoff(i+2+4096)@(gr8, gr0)
+
+	sethi.p	#gottlsdeschi(i+2+65536), gr14
+	setlo	#gottlsdesclo(i+2+65536), gr14
+	ldd	#tlsdesc(i+2+65536)@(gr15, gr14), gr8
+	calll	#gettlsoff(i+2+65536)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(i+3)), gr8
+	setlos	#gottlsdesclo(i+3), gr14
+	calll	#gettlsoff(i+3)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(i+3+4096)), gr8
+	setlos	#gottlsdesclo(i+3+4096), gr14
+	calll	#gettlsoff(i+3+4096)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(i+3+65536)), gr8
+	setlos	#gottlsdesclo(i+3+65536), gr14
+	calll	#gettlsoff(i+3+65536)@(gr8, gr0)
+
+	sethi	#tlsmoffhi(i+4), gr9
+	setlo	#tlsmofflo(i+4), gr9
+
+	sethi	#tlsmoffhi(i+4+4096), gr9
+	setlo	#tlsmofflo(i+4+4096), gr9
+
+	sethi	#tlsmoffhi(i+4+65536), gr9
+	setlo	#tlsmofflo(i+4+65536), gr9
+
+	call	#gettlsoff(0+1)
+	call	#gettlsoff(0+1+4096)
+	call	#gettlsoff(0+1+65536)
+
+	sethi.p	#gottlsdeschi(0+2), gr14
+	setlo	#gottlsdesclo(0+2), gr14
+	ldd	#tlsdesc(0+2)@(gr15, gr14), gr8
+	calll	#gettlsoff(0+2)@(gr8, gr0)
+
+	sethi.p	#gottlsdeschi(0+2+4096), gr14
+	setlo	#gottlsdesclo(0+2+4096), gr14
+	ldd	#tlsdesc(0+2+4096)@(gr15, gr14), gr8
+	calll	#gettlsoff(0+2+4096)@(gr8, gr0)
+
+	sethi.p	#gottlsdeschi(0+2+65536), gr14
+	setlo	#gottlsdesclo(0+2+65536), gr14
+	ldd	#tlsdesc(0+2+65536)@(gr15, gr14), gr8
+	calll	#gettlsoff(0+2+65536)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(0+3)), gr8
+	setlos	#gottlsdesclo(0+3), gr14
+	calll	#gettlsoff(0+3)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(0+3+4096)), gr8
+	setlos	#gottlsdesclo(0+3+4096), gr14
+	calll	#gettlsoff(0+3+4096)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(0+3+65536)), gr8
+	setlos	#gottlsdesclo(0+3+65536), gr14
+	calll	#gettlsoff(0+3+65536)@(gr8, gr0)
+
+	sethi	#tlsmoffhi(0+4), gr9
+	setlo	#tlsmofflo(0+4), gr9
+
+	sethi	#tlsmoffhi(0+4+4096), gr9
+	setlo	#tlsmofflo(0+4+4096), gr9
+
+	sethi	#tlsmoffhi(0+4+65536), gr9
+	setlo	#tlsmofflo(0+4+65536), gr9
+
+	call	#gettlsoff(x+1)
+	call	#gettlsoff(x+1+4096)
+	call	#gettlsoff(x+1+65536)
+
+	sethi.p	#gottlsdeschi(x+2), gr14
+	setlo	#gottlsdesclo(x+2), gr14
+	ldd	#tlsdesc(x+2)@(gr15, gr14), gr8
+	calll	#gettlsoff(x+2)@(gr8, gr0)
+
+	sethi.p	#gottlsdeschi(x+2+4096), gr14
+	setlo	#gottlsdesclo(x+2+4096), gr14
+	ldd	#tlsdesc(x+2+4096)@(gr15, gr14), gr8
+	calll	#gettlsoff(x+2+4096)@(gr8, gr0)
+
+	sethi.p	#gottlsdeschi(x+2+65536), gr14
+	setlo	#gottlsdesclo(x+2+65536), gr14
+	ldd	#tlsdesc(x+2+65536)@(gr15, gr14), gr8
+	calll	#gettlsoff(x+2+65536)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(x+3)), gr8
+	setlos	#gottlsdesclo(x+3), gr14
+	calll	#gettlsoff(x+3)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(x+3+4096)), gr8
+	setlos	#gottlsdesclo(x+3+4096), gr14
+	calll	#gettlsoff(x+3+4096)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(x+3+65536)), gr8
+	setlos	#gottlsdesclo(x+3+65536), gr14
+	calll	#gettlsoff(x+3+65536)@(gr8, gr0)
+
+.ifdef	static_tls
+	ldi	@(gr15, #gottlsoff12(l+1)), gr9
+	ldi	@(gr15, #gottlsoff12(l+1+65536)), gr9
+	ldi	@(gr15, #gottlsoff12(i+1)), gr9
+	ldi	@(gr15, #gottlsoff12(i+1+65536)), gr9
+	ldi	@(gr15, #gottlsoff12(0+1)), gr9
+	ldi	@(gr15, #gottlsoff12(0+1+65536)), gr9
+	ldi	@(gr15, #gottlsoff12(x+1)), gr9
+	ldi	@(gr15, #gottlsoff12(x+1+65536)), gr9
+	
+	setlos	#gottlsofflo(l+1+4096), gr8
+	ld	#tlsoff(l+1+4096)@(gr15, gr8), gr9
+	
+	sethi	#gottlsoffhi(i+1+4096), gr8
+	setlo	#gottlsofflo(i+1+4096), gr8
+	ld	#tlsoff(i+1+4096)@(gr15, gr8), gr9
+.endif
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-3.s b/binutils-2.19/ld/testsuite/ld-frv/tls-3.s
new file mode 100644
index 0000000..6dd7972
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-3.s
@@ -0,0 +1,20 @@
+	.text
+	.weak	u
+	.globl	_start
+_start:
+	call	#gettlsoff(u)
+
+	sethi.p	#gottlsdeschi(u), gr14
+	setlo	#gottlsdesclo(u), gr14
+	ldd	#tlsdesc(u)@(gr15, gr14), gr8
+	calll	#gettlsoff(u)@(gr8, gr0)
+
+	lddi.p	@(gr15, #gottlsdesc12(u)), gr8
+	setlos	#gottlsdesclo(u), gr14
+	calll	#gettlsoff(u)@(gr8, gr0)
+
+	ldi	@(gr15, #gottlsoff12(u)), gr9
+
+	sethi.p	#gottlsoffhi(u), gr14
+	setlo	#gottlsofflo(u), gr14
+	ld	#tlsoff(u)@(gr15, gr14), gr9
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-dynamic-1.d b/binutils-2.19/ld/testsuite/ld-frv/tls-dynamic-1.d
new file mode 100644
index 0000000..b95505e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-dynamic-1.d
@@ -0,0 +1,71 @@
+#name: FRV TLS relocs, dynamic linking
+#source: tls-1.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: tmpdir/tls-1-dep.so
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 10 	ldi\.p @\(gr15,16\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc f8 10 	setlos\.p 0xf*fffff810,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc f8 20 	setlos\.p 0xf*fffff820,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc 00 00 	setlos\.p lo\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	90 fc f8 20 	setlos 0xf*fffff820,gr8
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
+[0-9a-f ]+:	ff ff f8 20 	cop2 -32,cpr63,cpr32,cpr63
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	ff ff f8 10 	cop2 -32,cpr63,cpr16,cpr63
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-dynamic-2.d b/binutils-2.19/ld/testsuite/ld-frv/tls-dynamic-2.d
new file mode 100644
index 0000000..07bf332
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-dynamic-2.d
@@ -0,0 +1,200 @@
+#name: FRV TLS relocs with addends, dynamic linking
+#source: tls-2.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: tmpdir/tls-1-dep.so
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.plt:
+
+[0-9a-f ]+<\.plt>:
+[0-9a-f ]+:	c0 3a 40 00 	bralr
+[0-9a-f ]+:	92 fc 08 21 	setlos 0x821,gr9
+[0-9a-f ]+:	c0 3a 40 00 	bralr
+[0-9a-f ]+:	12 f8 00 00 	sethi\.p hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 21 	setlo 0xf821,gr9
+[0-9a-f ]+:	c0 3a 40 00 	bralr
+[0-9a-f ]+:	92 fc 00 01 	setlos 0x1,gr9
+[0-9a-f ]+:	c0 3a 40 00 	bralr
+[0-9a-f ]+:	92 c8 ff bc 	ldi @\(gr15,-68\),gr9
+[0-9a-f ]+:	c0 3a 40 00 	bralr
+[0-9a-f ]+:	92 fc f8 11 	setlos 0xf*fffff811,gr9
+[0-9a-f ]+:	c0 3a 40 00 	bralr
+[0-9a-f ]+:	92 fc 10 01 	setlos 0x1001,gr9
+[0-9a-f ]+:	c0 3a 40 00 	bralr
+[0-9a-f ]+:	92 c8 ff d4 	ldi @\(gr15,-44\),gr9
+[0-9a-f ]+:	c0 3a 40 00 	bralr
+[0-9a-f ]+:	92 fc 08 11 	setlos 0x811,gr9
+[0-9a-f ]+:	c0 3a 40 00 	bralr
+[0-9a-f ]+:	12 f8 00 01 	sethi\.p 0x1,gr9
+[0-9a-f ]+:	92 f4 00 01 	setlo 0x1,gr9
+[0-9a-f ]+:	c0 3a 40 00 	bralr
+[0-9a-f ]+:	92 c8 ff ec 	ldi @\(gr15,-20\),gr9
+[0-9a-f ]+:	c0 3a 40 00 	bralr
+[0-9a-f ]+:	12 f8 00 00 	sethi\.p hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 11 	setlo 0xf811,gr9
+[0-9a-f ]+:	c0 3a 40 00 	bralr
+[0-9a-f ]+:	92 fc f8 21 	setlos 0xf*fffff821,gr9
+[0-9a-f ]+:	c0 3a 40 00 	bralr
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 fc f8 11 	setlos 0xf*fffff811,gr9
+[0-9a-f ]+:	92 fc 08 11 	setlos 0x811,gr9
+[0-9a-f ]+:	92 c8 ff f4 	ldi @\(gr15,-12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 12 	setlos 0xf*fffff812,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 12 	setlos 0x812,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 12 	setlo 0xf812,gr9
+[0-9a-f ]+:	12 fc f8 13 	setlos\.p 0xf*fffff813,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc 08 13 	setlos\.p 0x813,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 f8 00 00 	sethi\.p hi\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 f4 f8 13 	setlo 0xf813,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 14 	setlos 0xf*fffff814,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 14 	setlos 0x814,gr9
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 14 	setlo 0xf814,gr9
+[0-9a-f ]+:	92 fc f8 21 	setlos 0xf*fffff821,gr9
+[0-9a-f ]+:	92 fc 08 21 	setlos 0x821,gr9
+[0-9a-f ]+:	92 c8 ff ac 	ldi @\(gr15,-84\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 22 	setlos 0xf*fffff822,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 22 	setlos 0x822,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 22 	setlo 0xf822,gr9
+[0-9a-f ]+:	12 fc f8 23 	setlos\.p 0xf*fffff823,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc 08 23 	setlos\.p 0x823,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 f8 00 00 	sethi\.p hi\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 f4 f8 23 	setlo 0xf823,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 24 	setlos 0xf*fffff824,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 24 	setlos 0x824,gr9
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 24 	setlo 0xf824,gr9
+[0-9a-f ]+:	92 fc 00 01 	setlos 0x1,gr9
+[0-9a-f ]+:	92 fc 10 01 	setlos 0x1001,gr9
+[0-9a-f ]+:	92 c8 ff e4 	ldi @\(gr15,-28\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 02 	setlos 0x2,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 10 02 	setlos 0x1002,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 f8 00 01 	sethi 0x1,gr9
+[0-9a-f ]+:	92 f4 00 02 	setlo 0x2,gr9
+[0-9a-f ]+:	12 fc 00 03 	setlos\.p 0x3,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc 10 03 	setlos\.p 0x1003,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 f8 00 01 	sethi\.p 0x1,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 f4 00 03 	setlo 0x3,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 04 	setlos 0x4,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 10 04 	setlos 0x1004,gr9
+[0-9a-f ]+:	92 f8 00 01 	sethi 0x1,gr9
+[0-9a-f ]+:	92 f4 00 04 	setlo 0x4,gr9
+[0-9a-f ]+:	92 c8 ff bc 	ldi @\(gr15,-68\),gr9
+[0-9a-f ]+:	92 c8 ff d4 	ldi @\(gr15,-44\),gr9
+[0-9a-f ]+:	92 c8 ff ec 	ldi @\(gr15,-20\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 20 	ldi @\(gr15,32\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 1c 	ldi @\(gr15,28\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 18 	ldi @\(gr15,24\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 0c 	ldi\.p @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 10 	ldi\.p @\(gr15,16\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 14 	ldi\.p @\(gr15,20\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_-0x60)>:
+[0-9a-f ]+:	00 01 02 c0 	.*
+[0-9a-f ]+:	00 00 08 21 	.*
+[0-9a-f ]+:	00 01 02 c0 	.*
+[0-9a-f ]+:	00 00 f8 21 	.*
+[0-9a-f ]+:	00 01 02 c0 	.*
+[0-9a-f ]+:	00 00 00 01 	.*
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 00 00 01 	.*
+[0-9a-f ]+:	00 01 02 c0 	.*
+[0-9a-f ]+:	ff ff f8 11 	.*
+[0-9a-f ]+:	00 01 02 c0 	.*
+[0-9a-f ]+:	00 00 10 01 	.*
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 00 10 01 	.*
+[0-9a-f ]+:	00 01 02 c0 	.*
+[0-9a-f ]+:	00 00 08 11 	.*
+[0-9a-f ]+:	00 01 02 c0 	.*
+[0-9a-f ]+:	00 01 00 01 	.*
+[0-9a-f ]+:	00 00 00 00 	.*
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 01 00 01 	.*
+[0-9a-f ]+:	00 01 02 c0 	.*
+[0-9a-f ]+:	00 00 f8 11 	.*
+[0-9a-f ]+:	00 01 02 c0 	.*
+[0-9a-f ]+:	ff ff f8 21 	.*
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 00 00 03 	.*
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 10 03 	.*
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 01 00 03 	.*
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 01 00 02 	.*
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 10 02 	.*
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 00 02 	.*
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-dynamic-3.d b/binutils-2.19/ld/testsuite/ld-frv/tls-dynamic-3.d
new file mode 100644
index 0000000..c9750d2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-dynamic-3.d
@@ -0,0 +1,27 @@
+#name: FRV TLS undefweak relocs, dynamic linking
+#source: tls-3.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: tmpdir/tls-1-dep.so
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 0c 	ldi\.p @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_TLSOFF	u
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-initial-shared-2.d b/binutils-2.19/ld/testsuite/ld-frv/tls-initial-shared-2.d
new file mode 100644
index 0000000..e4ea6a1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-initial-shared-2.d
@@ -0,0 +1,235 @@
+#name: FRV TLS relocs with addends, shared linking with static TLS
+#source: tls-2.s
+#as: --defsym static_tls=1
+#objdump: -DR -j .text -j .got -j .plt
+#ld: -shared tmpdir/tls-1-dep.so --version-script tls-1-shared.lds
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.plt:
+
+[0-9a-f ]+<\.plt>:
+[0-9a-f ]+:	92 c8 f0 5c 	ldi @\(gr15,92\),gr9
+[0-9a-f ]+:	c0 3a 40 00 	bralr
+[0-9a-f ]+:	90 cc ff e8 	lddi @\(gr15,-24\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	92 c8 f0 78 	ldi @\(gr15,120\),gr9
+[0-9a-f ]+:	c0 3a 40 00 	bralr
+[0-9a-f ]+:	90 cc ff f8 	lddi @\(gr15,-8\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 c8 f0 30 	ldi @\(gr15,48\),gr9
+[0-9a-f ]+:	92 c8 f0 78 	ldi @\(gr15,120\),gr9
+[0-9a-f ]+:	92 c8 f0 4c 	ldi @\(gr15,76\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 70 	ldi @\(gr15,112\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 7c 	ldi @\(gr15,124\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 8c 	ldi @\(gr15,140\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 34 	ldi\.p @\(gr15,52\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 3c 	ldi\.p @\(gr15,60\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 50 	ldi\.p @\(gr15,80\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 14 	setlos 0xf*fffff814,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 14 	setlos 0x814,gr9
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 14 	setlo 0xf814,gr9
+[0-9a-f ]+:	92 c8 f0 54 	ldi @\(gr15,84\),gr9
+[0-9a-f ]+:	92 c8 f0 5c 	ldi @\(gr15,92\),gr9
+[0-9a-f ]+:	92 c8 f0 18 	ldi @\(gr15,24\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 90 	ldi @\(gr15,144\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 60 	ldi @\(gr15,96\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 64 	ldi @\(gr15,100\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 58 	ldi\.p @\(gr15,88\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 0c 	ldi\.p @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 1c 	ldi\.p @\(gr15,28\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 24 	setlos 0xf*fffff824,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 24 	setlos 0x824,gr9
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 24 	setlo 0xf824,gr9
+[0-9a-f ]+:	92 c8 f0 24 	ldi @\(gr15,36\),gr9
+[0-9a-f ]+:	fe 3f ff c1 	call .*
+[0-9a-f ]+:	92 c8 f0 40 	ldi @\(gr15,64\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 68 	ldi @\(gr15,104\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 80 	ldi @\(gr15,128\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 84 	ldi @\(gr15,132\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 28 	ldi\.p @\(gr15,40\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 38 	ldi\.p @\(gr15,56\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 44 	ldi\.p @\(gr15,68\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 04 	setlos 0x4,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 10 04 	setlos 0x1004,gr9
+[0-9a-f ]+:	92 f8 00 01 	sethi 0x1,gr9
+[0-9a-f ]+:	92 f4 00 04 	setlo 0x4,gr9
+[0-9a-f ]+:	92 c8 f0 2c 	ldi @\(gr15,44\),gr9
+[0-9a-f ]+:	fe 3f ff 9f 	call .*
+[0-9a-f ]+:	92 c8 f0 48 	ldi @\(gr15,72\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 6c 	ldi @\(gr15,108\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 74 	ldi @\(gr15,116\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 88 	ldi @\(gr15,136\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 10 	ldi\.p @\(gr15,16\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 14 	ldi\.p @\(gr15,20\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 20 	ldi\.p @\(gr15,32\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 30 	ldi @\(gr15,48\),gr9
+[0-9a-f ]+:	92 c8 f0 4c 	ldi @\(gr15,76\),gr9
+[0-9a-f ]+:	92 c8 f0 54 	ldi @\(gr15,84\),gr9
+[0-9a-f ]+:	92 c8 f0 18 	ldi @\(gr15,24\),gr9
+[0-9a-f ]+:	92 c8 f0 24 	ldi @\(gr15,36\),gr9
+[0-9a-f ]+:	92 c8 f0 40 	ldi @\(gr15,64\),gr9
+[0-9a-f ]+:	92 c8 f0 2c 	ldi @\(gr15,44\),gr9
+[0-9a-f ]+:	92 c8 f0 48 	ldi @\(gr15,72\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 78 	ldi @\(gr15,120\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 5c 	ldi @\(gr15,92\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_-0x20)>:
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 10 11 	add\.p sp,gr17,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 00 10 01 	add\.p sp,sp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 10 01 	add\.p sp,sp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 17 f1 	\*unknown\*
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f ]+:	00 00 10 13 	add\.p sp,gr19,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 00 03 	add\.p gr0,gr3,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 10 03 	add\.p sp,gr3,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 01 00 11 	add\.p gr16,gr17,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 00 13 	add\.p gr16,gr19,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 00 03 	add\.p gr16,gr3,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 07 f1 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 07 f3 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 00 01 	add\.p gr0,sp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 00 01 	add\.p gr0,sp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 00 03 	add\.p gr0,gr3,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 17 f3 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 10 03 	add\.p sp,gr3,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 07 f1 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 07 f3 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 00 01 	add\.p gr16,sp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 01 00 01 	add\.p gr16,sp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 00 03 	add\.p gr16,gr3,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 00 11 	add\.p gr0,gr17,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 00 13 	add\.p gr0,gr19,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 10 11 	add\.p sp,gr17,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 10 12 	add\.p sp,gr18,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 00 12 	add\.p gr16,gr18,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 07 f2 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 10 02 	add\.p sp,fp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 10 01 	add\.p sp,sp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 10 02 	add\.p sp,fp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 17 f2 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 07 f2 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 00 02 	add\.p gr16,fp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 01 00 02 	add\.p gr16,fp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 00 12 	add\.p gr0,gr18,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-pie-1.d b/binutils-2.19/ld/testsuite/ld-frv/tls-pie-1.d
new file mode 100644
index 0000000..0ced90a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-pie-1.d
@@ -0,0 +1,71 @@
+#name: FRV TLS relocs, pie linking
+#source: tls-1.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: -pie tmpdir/tls-1-dep.so
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 10 	ldi\.p @\(gr15,16\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc f8 10 	setlos\.p 0xf*fffff810,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc f8 20 	setlos\.p 0xf*fffff820,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc 00 00 	setlos\.p lo\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	90 fc f8 20 	setlos 0xf*fffff820,gr8
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
+[0-9a-f ]+:	ff ff f8 20 	cop2 -32,cpr63,cpr32,cpr63
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	ff ff f8 10 	cop2 -32,cpr63,cpr16,cpr63
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-pie-3.d b/binutils-2.19/ld/testsuite/ld-frv/tls-pie-3.d
new file mode 100644
index 0000000..4dc3469
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-pie-3.d
@@ -0,0 +1,27 @@
+#name: FRV TLS undefweak relocs, pie linking
+#source: tls-3.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: -pie
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 0c 	ldi\.p @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_TLSOFF	u
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-relax-dynamic-1.d b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-dynamic-1.d
new file mode 100644
index 0000000..3d7ec36
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-dynamic-1.d
@@ -0,0 +1,67 @@
+#name: FRV TLS relocs, dynamic linking with relaxation
+#source: tls-1.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: tmpdir/tls-1-dep.so --relax
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 0c 	ldi\.p @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc f8 10 	setlos\.p 0xf*fffff810,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc f8 20 	setlos\.p 0xf*fffff820,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc 00 00 	setlos\.p lo\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	90 fc f8 20 	setlos 0xf*fffff820,gr8
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-relax-dynamic-2.d b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-dynamic-2.d
new file mode 100644
index 0000000..59577d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-dynamic-2.d
@@ -0,0 +1,149 @@
+#name: FRV TLS relocs with addends, dynamic linking, relaxing
+#source: tls-2.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: tmpdir/tls-1-dep.so --relax
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 fc f8 11 	setlos 0xf*fffff811,gr9
+[0-9a-f ]+:	92 fc 08 11 	setlos 0x811,gr9
+[0-9a-f ]+:	92 c8 f0 2c 	ldi @\(gr15,44\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 12 	setlos 0xf*fffff812,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 12 	setlos 0x812,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 12 	setlo 0xf812,gr9
+[0-9a-f ]+:	12 fc f8 13 	setlos\.p 0xf*fffff813,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc 08 13 	setlos\.p 0x813,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 f8 00 00 	sethi\.p hi\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 f4 f8 13 	setlo 0xf813,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 14 	setlos 0xf*fffff814,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 14 	setlos 0x814,gr9
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 14 	setlo 0xf814,gr9
+[0-9a-f ]+:	92 fc f8 21 	setlos 0xf*fffff821,gr9
+[0-9a-f ]+:	92 fc 08 21 	setlos 0x821,gr9
+[0-9a-f ]+:	92 c8 f0 14 	ldi @\(gr15,20\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 22 	setlos 0xf*fffff822,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 22 	setlos 0x822,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 22 	setlo 0xf822,gr9
+[0-9a-f ]+:	12 fc f8 23 	setlos\.p 0xf*fffff823,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc 08 23 	setlos\.p 0x823,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 f8 00 00 	sethi\.p hi\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 f4 f8 23 	setlo 0xf823,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 24 	setlos 0xf*fffff824,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 24 	setlos 0x824,gr9
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 24 	setlo 0xf824,gr9
+[0-9a-f ]+:	92 fc 00 01 	setlos 0x1,gr9
+[0-9a-f ]+:	92 fc 10 01 	setlos 0x1001,gr9
+[0-9a-f ]+:	92 c8 f0 24 	ldi @\(gr15,36\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 02 	setlos 0x2,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 10 02 	setlos 0x1002,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 f8 00 01 	sethi 0x1,gr9
+[0-9a-f ]+:	92 f4 00 02 	setlo 0x2,gr9
+[0-9a-f ]+:	12 fc 00 03 	setlos\.p 0x3,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc 10 03 	setlos\.p 0x1003,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 f8 00 01 	sethi\.p 0x1,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 f4 00 03 	setlo 0x3,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 04 	setlos 0x4,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 10 04 	setlos 0x1004,gr9
+[0-9a-f ]+:	92 f8 00 01 	sethi 0x1,gr9
+[0-9a-f ]+:	92 f4 00 04 	setlo 0x4,gr9
+[0-9a-f ]+:	92 c8 f0 18 	ldi @\(gr15,24\),gr9
+[0-9a-f ]+:	92 c8 f0 1c 	ldi @\(gr15,28\),gr9
+[0-9a-f ]+:	92 c8 f0 28 	ldi @\(gr15,40\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 38 	ldi @\(gr15,56\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 34 	ldi @\(gr15,52\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 30 	ldi @\(gr15,48\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 0c 	ldi\.p @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 10 	ldi\.p @\(gr15,16\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 20 	ldi\.p @\(gr15,32\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
+[0-9a-f ]+:	00 00 00 03 	add\.p gr0,gr3,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 10 03 	add\.p sp,gr3,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 f8 21 	\*unknown\*
+[0-9a-f ]+:	00 00 00 01 	add\.p gr0,sp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 10 01 	add\.p sp,sp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 01 00 03 	add\.p gr16,gr3,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 01 00 01 	add\.p gr16,sp,gr0
+[0-9a-f ]+:	00 01 00 01 	add\.p gr16,sp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 f8 11 	\*unknown\*
+[0-9a-f ]+:	00 01 00 02 	add\.p gr16,fp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 10 02 	add\.p sp,fp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-relax-dynamic-3.d b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-dynamic-3.d
new file mode 100644
index 0000000..43cbdc7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-dynamic-3.d
@@ -0,0 +1,27 @@
+#name: FRV TLS undefweak relocs, dynamic linking with relaxation
+#source: tls-3.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: tmpdir/tls-1-dep.so --relax
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 0c 	ldi\.p @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_TLSOFF	u
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-relax-initial-shared-2.d b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-initial-shared-2.d
new file mode 100644
index 0000000..824cf65
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-initial-shared-2.d
@@ -0,0 +1,214 @@
+#name: FRV TLS relocs with addends, shared linking with static TLS, relaxing
+#source: tls-2.s
+#as: --defsym static_tls=1
+#objdump: -DR -j .text -j .got -j .plt
+#ld: -shared tmpdir/tls-1-dep.so --version-script tls-1-shared.lds --relax
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 c8 f0 34 	ldi @\(gr15,52\),gr9
+[0-9a-f ]+:	92 c8 f0 44 	ldi @\(gr15,68\),gr9
+[0-9a-f ]+:	92 c8 f0 5c 	ldi @\(gr15,92\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 7c 	ldi @\(gr15,124\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 84 	ldi @\(gr15,132\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 94 	ldi @\(gr15,148\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 38 	ldi\.p @\(gr15,56\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 48 	ldi\.p @\(gr15,72\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 60 	ldi\.p @\(gr15,96\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 14 	setlos 0xf*fffff814,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 14 	setlos 0x814,gr9
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 14 	setlo 0xf814,gr9
+[0-9a-f ]+:	92 c8 f0 64 	ldi @\(gr15,100\),gr9
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	92 c8 f0 1c 	ldi @\(gr15,28\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 98 	ldi @\(gr15,152\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 6c 	ldi @\(gr15,108\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 70 	ldi @\(gr15,112\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 68 	ldi\.p @\(gr15,104\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 10 	ldi\.p @\(gr15,16\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 20 	ldi\.p @\(gr15,32\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 24 	setlos 0xf*fffff824,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 24 	setlos 0x824,gr9
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 24 	setlo 0xf824,gr9
+[0-9a-f ]+:	92 c8 f0 28 	ldi @\(gr15,40\),gr9
+[0-9a-f ]+:	92 c8 f0 4c 	ldi @\(gr15,76\),gr9
+[0-9a-f ]+:	92 c8 f0 50 	ldi @\(gr15,80\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 74 	ldi @\(gr15,116\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 88 	ldi @\(gr15,136\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 8c 	ldi @\(gr15,140\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 2c 	ldi\.p @\(gr15,44\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 3c 	ldi\.p @\(gr15,60\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 54 	ldi\.p @\(gr15,84\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 04 	setlos 0x4,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 10 04 	setlos 0x1004,gr9
+[0-9a-f ]+:	92 f8 00 01 	sethi 0x1,gr9
+[0-9a-f ]+:	92 f4 00 04 	setlo 0x4,gr9
+[0-9a-f ]+:	92 c8 f0 30 	ldi @\(gr15,48\),gr9
+[0-9a-f ]+:	92 c8 f0 40 	ldi @\(gr15,64\),gr9
+[0-9a-f ]+:	92 c8 f0 58 	ldi @\(gr15,88\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 78 	ldi @\(gr15,120\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 80 	ldi @\(gr15,128\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 90 	ldi @\(gr15,144\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 14 	ldi\.p @\(gr15,20\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 18 	ldi\.p @\(gr15,24\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 24 	ldi\.p @\(gr15,36\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 34 	ldi @\(gr15,52\),gr9
+[0-9a-f ]+:	92 c8 f0 5c 	ldi @\(gr15,92\),gr9
+[0-9a-f ]+:	92 c8 f0 64 	ldi @\(gr15,100\),gr9
+[0-9a-f ]+:	92 c8 f0 1c 	ldi @\(gr15,28\),gr9
+[0-9a-f ]+:	92 c8 f0 28 	ldi @\(gr15,40\),gr9
+[0-9a-f ]+:	92 c8 f0 50 	ldi @\(gr15,80\),gr9
+[0-9a-f ]+:	92 c8 f0 30 	ldi @\(gr15,48\),gr9
+[0-9a-f ]+:	92 c8 f0 58 	ldi @\(gr15,88\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 44 	ldi @\(gr15,68\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
+[0-9a-f ]+:	00 00 10 11 	add\.p sp,gr17,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 10 13 	add\.p sp,gr19,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 00 03 	add\.p gr0,gr3,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 10 03 	add\.p sp,gr3,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 01 00 11 	add\.p gr16,gr17,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 00 13 	add\.p gr16,gr19,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 00 03 	add\.p gr16,gr3,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 07 f1 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 07 f3 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 00 01 	add\.p gr0,sp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 00 01 	add\.p gr0,sp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 00 03 	add\.p gr0,gr3,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 17 f3 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 10 01 	add\.p sp,sp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 10 01 	add\.p sp,sp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 10 03 	add\.p sp,gr3,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 17 f1 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 07 f1 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 07 f3 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 00 01 	add\.p gr16,sp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 01 00 01 	add\.p gr16,sp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 00 03 	add\.p gr16,gr3,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 00 11 	add\.p gr0,gr17,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 00 13 	add\.p gr0,gr19,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 10 12 	add\.p sp,gr18,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 00 12 	add\.p gr16,gr18,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 07 f2 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 10 02 	add\.p sp,fp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 00 10 02 	add\.p sp,fp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 17 f2 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 07 f2 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 01 00 02 	add\.p gr16,fp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f ]+:	00 01 00 02 	add\.p gr16,fp,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 00 12 	add\.p gr0,gr18,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-relax-pie-1.d b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-pie-1.d
new file mode 100644
index 0000000..579047e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-pie-1.d
@@ -0,0 +1,67 @@
+#name: FRV TLS relocs, pie linking with relaxation
+#source: tls-1.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: -pie tmpdir/tls-1-dep.so --relax
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 0c 	ldi\.p @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc f8 10 	setlos\.p 0xf*fffff810,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc f8 20 	setlos\.p 0xf*fffff820,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc 00 00 	setlos\.p lo\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	90 fc f8 20 	setlos 0xf*fffff820,gr8
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-relax-pie-3.d b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-pie-3.d
new file mode 100644
index 0000000..da26ca0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-pie-3.d
@@ -0,0 +1,27 @@
+#name: FRV TLS undefweak relocs, pie linking with relaxation
+#source: tls-3.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: -pie --relax
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 0c 	ldi\.p @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_TLSOFF	u
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-relax-shared-1.d b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-shared-1.d
new file mode 100644
index 0000000..ba3b532
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-shared-1.d
@@ -0,0 +1,73 @@
+#name: FRV TLS relocs, shared linking with relaxation
+#source: tls-1.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: -shared tmpdir/tls-1-dep.so --version-script tls-1-shared.lds --relax
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 10 	ldi\.p @\(gr15,16\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 14 	ldi @\(gr15,20\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 14 	ldi @\(gr15,20\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 14 	ldi\.p @\(gr15,20\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 0c 	ldi\.p @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 18 	ldi @\(gr15,24\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 18 	ldi @\(gr15,24\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 18 	ldi\.p @\(gr15,24\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	90 fc f8 20 	setlos 0xf*fffff820,gr8
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	92 c8 f0 14 	ldi @\(gr15,20\),gr9
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	92 c8 f0 18 	ldi @\(gr15,24\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 14 	ldi @\(gr15,20\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 18 	ldi @\(gr15,24\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
+[0-9a-f ]+:	00 00 00 10 	add\.p gr0,gr16,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 07 f0 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-relax-shared-2.d b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-shared-2.d
new file mode 100644
index 0000000..c07bb35
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-shared-2.d
@@ -0,0 +1,264 @@
+#name: FRV TLS relocs with addends, shared linking, relaxing
+#source: tls-2.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: -shared tmpdir/tls-1-dep.so --version-script tls-1-shared.lds --relax
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.plt:
+
+[0-9a-f ]+<\.plt>:
+[0-9a-f ]+:	90 cc f0 10 	lddi @\(gr15,16\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc f0 30 	lddi @\(gr15,48\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc f0 40 	lddi @\(gr15,64\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc f0 50 	lddi @\(gr15,80\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc f0 58 	lddi @\(gr15,88\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc f0 68 	lddi @\(gr15,104\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc ff a8 	lddi @\(gr15,-88\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc ff b0 	lddi @\(gr15,-80\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc ff c8 	lddi @\(gr15,-56\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc ff d8 	lddi @\(gr15,-40\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc ff e0 	lddi @\(gr15,-32\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc ff f0 	lddi @\(gr15,-16\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	fe 3f ff f0 	call .*
+[0-9a-f ]+:	fe 3f ff f5 	call .*
+[0-9a-f ]+:	fe 3f ff fa 	call .*
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 98 	setlo 0x98,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 a8 	setlo 0xa8,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 c0 	setlo 0xc0,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc f0 60 	lddi\.p @\(gr15,96\),gr8
+[0-9a-f ]+:	9c fc 00 60 	setlos 0x60,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc ff b8 	lddi\.p @\(gr15,-72\),gr8
+[0-9a-f ]+:	9c fc ff b8 	setlos 0xf*ffffffb8,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc ff e8 	lddi\.p @\(gr15,-24\),gr8
+[0-9a-f ]+:	9c fc ff e8 	setlos 0xf*ffffffe8,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 14 	setlos 0xf*fffff814,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 14 	setlos 0x814,gr9
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 14 	setlo 0xf814,gr9
+[0-9a-f ]+:	fe 3f ff e0 	call .*
+[0-9a-f ]+:	fe 3f ff c9 	call .*
+[0-9a-f ]+:	fe 3f ff ca 	call .*
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 c8 	setlo 0xc8,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 78 	setlo 0x78,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 88 	setlo 0x88,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc ff f8 	lddi\.p @\(gr15,-8\),gr8
+[0-9a-f ]+:	9c fc ff f8 	setlos 0xf*fffffff8,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc f0 18 	lddi\.p @\(gr15,24\),gr8
+[0-9a-f ]+:	9c fc 00 18 	setlos 0x18,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc f0 38 	lddi\.p @\(gr15,56\),gr8
+[0-9a-f ]+:	9c fc 00 38 	setlos 0x38,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 24 	setlos 0xf*fffff824,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 24 	setlos 0x824,gr9
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 24 	setlo 0xf824,gr9
+[0-9a-f ]+:	fe 3f ff b0 	call .*
+[0-9a-f ]+:	fe 3f ff b5 	call .*
+[0-9a-f ]+:	fe 3f ff ba 	call .*
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 90 	setlo 0x90,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 a0 	setlo 0xa0,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 b8 	setlo 0xb8,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc f0 48 	lddi\.p @\(gr15,72\),gr8
+[0-9a-f ]+:	9c fc 00 48 	setlos 0x48,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc ff a0 	lddi\.p @\(gr15,-96\),gr8
+[0-9a-f ]+:	9c fc ff a0 	setlos 0xf*ffffffa0,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc ff d0 	lddi\.p @\(gr15,-48\),gr8
+[0-9a-f ]+:	9c fc ff d0 	setlos 0xf*ffffffd0,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 04 	setlos 0x4,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 10 04 	setlos 0x1004,gr9
+[0-9a-f ]+:	92 f8 00 01 	sethi 0x1,gr9
+[0-9a-f ]+:	92 f4 00 04 	setlo 0x4,gr9
+[0-9a-f ]+:	fe 3f ff 94 	call .*
+[0-9a-f ]+:	fe 3f ff 99 	call .*
+[0-9a-f ]+:	fe 3f ff 9e 	call .*
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 b0 	setlo 0xb0,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 80 	setlo 0x80,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 70 	setlo 0x70,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc f0 20 	lddi\.p @\(gr15,32\),gr8
+[0-9a-f ]+:	9c fc 00 20 	setlos 0x20,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc f0 28 	lddi\.p @\(gr15,40\),gr8
+[0-9a-f ]+:	9c fc 00 28 	setlos 0x28,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc ff c0 	lddi\.p @\(gr15,-64\),gr8
+[0-9a-f ]+:	9c fc ff c0 	setlos 0xf*ffffffc0,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_-0x60)>:
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 17 f3 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 00 10 01 	add\.p sp,sp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 10 01 	add\.p sp,sp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 10 03 	add\.p sp,gr3,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 01 00 03 	add\.p gr16,gr3,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 07 f1 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 07 f3 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 01 00 01 	add\.p gr16,sp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 00 01 	add\.p gr16,sp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 00 03 	add\.p gr16,gr3,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 00 11 	add\.p gr0,gr17,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 00 13 	add\.p gr0,gr19,gr0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 10 11 	add\.p sp,gr17,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 10 13 	add\.p sp,gr19,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 00 00 03 	add\.p gr0,gr3,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 00 10 03 	add\.p sp,gr3,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 00 11 	add\.p gr16,gr17,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 00 13 	add\.p gr16,gr19,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 07 f1 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 07 f3 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 00 00 01 	add\.p gr0,sp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 00 01 	add\.p gr0,sp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 00 03 	add\.p gr0,gr3,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 17 f1 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 01 00 02 	add\.p gr16,fp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 10 12 	add\.p sp,gr18,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 00 10 02 	add\.p sp,fp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 00 12 	add\.p gr16,gr18,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 07 f2 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 17 f2 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 10 02 	add\.p sp,fp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 07 f2 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 00 02 	add\.p gr16,fp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 00 12 	add\.p gr0,gr18,gr0
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-relax-shared-3.d b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-shared-3.d
new file mode 100644
index 0000000..b766a00
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-shared-3.d
@@ -0,0 +1,27 @@
+#name: FRV TLS undefweak relocs, shared linking with relaxation
+#source: tls-3.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: -shared --relax
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 0c 	ldi\.p @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_TLSOFF	u
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-relax-static-1.d b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-static-1.d
new file mode 100644
index 0000000..d87d22c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-static-1.d
@@ -0,0 +1,62 @@
+#name: FRV TLS relocs, static linking with relaxation
+#source: tls-1.s
+#objdump: -D -j .text -j .got -j .plt
+#ld: -static tmpdir/tls-1-dep.o --relax
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc f8 10 	setlos\.p 0xf*fffff810,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc f8 20 	setlos\.p 0xf*fffff820,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 30 	setlos 0xf*fffff830,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 30 	setlos 0xf*fffff830,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc f8 30 	setlos\.p 0xf*fffff830,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc 00 00 	setlos\.p lo\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	90 fc f8 30 	setlos 0xf*fffff830,gr8
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	92 fc f8 30 	setlos 0xf*fffff830,gr9
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 30 	setlos 0xf*fffff830,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-relax-static-3.d b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-static-3.d
new file mode 100644
index 0000000..ed3c07a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-relax-static-3.d
@@ -0,0 +1,26 @@
+#name: FRV TLS undefweak relocs, static linking with relaxation
+#source: tls-3.s
+#objdump: -D -j .text -j .got -j .plt
+#ld: -static --relax
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+00010094 <_start>:
+   10094:	92 fc 00 00 	setlos lo\(0x0\),gr9
+   10098:	00 88 00 00 	nop\.p
+   1009c:	80 88 00 00 	nop
+   100a0:	92 fc 00 00 	setlos lo\(0x0\),gr9
+   100a4:	80 88 00 00 	nop
+   100a8:	12 fc 00 00 	setlos\.p lo\(0x0\),gr9
+   100ac:	80 88 00 00 	nop
+   100b0:	80 88 00 00 	nop
+   100b4:	92 fc 00 00 	setlos lo\(0x0\),gr9
+   100b8:	00 88 00 00 	nop\.p
+   100bc:	80 88 00 00 	nop
+   100c0:	92 fc 00 00 	setlos lo\(0x0\),gr9
+Disassembly of section \.got:
+
+000140c8 <(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-shared-1-fail.d b/binutils-2.19/ld/testsuite/ld-frv/tls-shared-1-fail.d
new file mode 100644
index 0000000..8cb220d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-shared-1-fail.d
@@ -0,0 +1,4 @@
+#name: FRV TLS relocs, shared linking
+#source: tls-1.s
+#ld: -shared tmpdir/tls-1-dep.so
+#error: different segment
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-shared-1.d b/binutils-2.19/ld/testsuite/ld-frv/tls-shared-1.d
new file mode 100644
index 0000000..2a29ba5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-shared-1.d
@@ -0,0 +1,73 @@
+#name: FRV TLS relocs, shared linking with local binding
+#source: tls-1.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: -shared tmpdir/tls-1-dep.so --version-script tls-1-shared.lds
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 10 	ldi\.p @\(gr15,16\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 14 	ldi @\(gr15,20\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 14 	ldi @\(gr15,20\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 14 	ldi\.p @\(gr15,20\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 0c 	ldi\.p @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 18 	ldi @\(gr15,24\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 18 	ldi @\(gr15,24\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 18 	ldi\.p @\(gr15,24\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	90 fc f8 20 	setlos 0xf*fffff820,gr8
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	92 c8 f0 14 	ldi @\(gr15,20\),gr9
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	92 c8 f0 18 	ldi @\(gr15,24\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 10 	ldi @\(gr15,16\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 14 	ldi @\(gr15,20\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 18 	ldi @\(gr15,24\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
+[0-9a-f ]+:	00 00 00 10 	add\.p gr0,gr16,gr0
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_TLSOFF	x
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
+[0-9a-f ]+:	00 00 07 f0 	\*unknown\*
+[0-9a-f	 ]+: R_FRV_TLSOFF	\.tbss
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-shared-2.d b/binutils-2.19/ld/testsuite/ld-frv/tls-shared-2.d
new file mode 100644
index 0000000..bd92cdb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-shared-2.d
@@ -0,0 +1,264 @@
+#name: FRV TLS relocs with addends, shared linking
+#source: tls-2.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: -shared tmpdir/tls-1-dep.so --version-script tls-1-shared.lds
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.plt:
+
+[0-9a-f ]+<\.plt>:
+[0-9a-f ]+:	90 cc f0 10 	lddi @\(gr15,16\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc f0 30 	lddi @\(gr15,48\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc f0 40 	lddi @\(gr15,64\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc f0 50 	lddi @\(gr15,80\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc f0 58 	lddi @\(gr15,88\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc f0 68 	lddi @\(gr15,104\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc ff a8 	lddi @\(gr15,-88\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc ff b0 	lddi @\(gr15,-80\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc ff c8 	lddi @\(gr15,-56\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc ff d8 	lddi @\(gr15,-40\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc ff e0 	lddi @\(gr15,-32\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+[0-9a-f ]+:	90 cc ff f0 	lddi @\(gr15,-16\),gr8
+[0-9a-f ]+:	80 30 80 00 	jmpl @\(gr8,gr0\)
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	fe 3f ff f0 	call .*
+[0-9a-f ]+:	fe 3f ff f5 	call .*
+[0-9a-f ]+:	fe 3f ff fa 	call .*
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 98 	setlo 0x98,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 a8 	setlo 0xa8,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 c0 	setlo 0xc0,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc f0 60 	lddi\.p @\(gr15,96\),gr8
+[0-9a-f ]+:	9c fc 00 60 	setlos 0x60,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc ff b8 	lddi\.p @\(gr15,-72\),gr8
+[0-9a-f ]+:	9c fc ff b8 	setlos 0xf*ffffffb8,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc ff e8 	lddi\.p @\(gr15,-24\),gr8
+[0-9a-f ]+:	9c fc ff e8 	setlos 0xf*ffffffe8,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 14 	setlos 0xf*fffff814,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 14 	setlos 0x814,gr9
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 14 	setlo 0xf814,gr9
+[0-9a-f ]+:	fe 3f ff e0 	call .*
+[0-9a-f ]+:	fe 3f ff c9 	call .*
+[0-9a-f ]+:	fe 3f ff ca 	call .*
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 c8 	setlo 0xc8,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 78 	setlo 0x78,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 88 	setlo 0x88,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc ff f8 	lddi\.p @\(gr15,-8\),gr8
+[0-9a-f ]+:	9c fc ff f8 	setlos 0xf*fffffff8,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc f0 18 	lddi\.p @\(gr15,24\),gr8
+[0-9a-f ]+:	9c fc 00 18 	setlos 0x18,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc f0 38 	lddi\.p @\(gr15,56\),gr8
+[0-9a-f ]+:	9c fc 00 38 	setlos 0x38,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 24 	setlos 0xf*fffff824,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 08 24 	setlos 0x824,gr9
+[0-9a-f ]+:	92 f8 00 00 	sethi hi\(0x0\),gr9
+[0-9a-f ]+:	92 f4 f8 24 	setlo 0xf824,gr9
+[0-9a-f ]+:	fe 3f ff b0 	call .*
+[0-9a-f ]+:	fe 3f ff b5 	call .*
+[0-9a-f ]+:	fe 3f ff ba 	call .*
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 90 	setlo 0x90,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 a0 	setlo 0xa0,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 b8 	setlo 0xb8,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc f0 48 	lddi\.p @\(gr15,72\),gr8
+[0-9a-f ]+:	9c fc 00 48 	setlos 0x48,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc ff a0 	lddi\.p @\(gr15,-96\),gr8
+[0-9a-f ]+:	9c fc ff a0 	setlos 0xf*ffffffa0,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc ff d0 	lddi\.p @\(gr15,-48\),gr8
+[0-9a-f ]+:	9c fc ff d0 	setlos 0xf*ffffffd0,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 04 	setlos 0x4,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 10 04 	setlos 0x1004,gr9
+[0-9a-f ]+:	92 f8 00 01 	sethi 0x1,gr9
+[0-9a-f ]+:	92 f4 00 04 	setlo 0x4,gr9
+[0-9a-f ]+:	fe 3f ff 94 	call .*
+[0-9a-f ]+:	fe 3f ff 99 	call .*
+[0-9a-f ]+:	fe 3f ff 9e 	call .*
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 b0 	setlo 0xb0,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 80 	setlo 0x80,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	1c f8 00 00 	sethi\.p hi\(0x0\),gr14
+[0-9a-f ]+:	9c f4 00 70 	setlo 0x70,gr14
+[0-9a-f ]+:	90 08 f1 4e 	ldd @\(gr15,gr14\),gr8
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc f0 20 	lddi\.p @\(gr15,32\),gr8
+[0-9a-f ]+:	9c fc 00 20 	setlos 0x20,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc f0 28 	lddi\.p @\(gr15,40\),gr8
+[0-9a-f ]+:	9c fc 00 28 	setlos 0x28,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+[0-9a-f ]+:	10 cc ff c0 	lddi\.p @\(gr15,-64\),gr8
+[0-9a-f ]+:	9c fc ff c0 	setlos 0xf*ffffffc0,gr14
+[0-9a-f ]+:	82 30 80 00 	calll @\(gr8,gr0\)
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_-0x60)>:
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 17 f3 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 00 10 01 	add\.p sp,sp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 10 01 	add\.p sp,sp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 10 03 	add\.p sp,gr3,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 01 00 03 	add\.p gr16,gr3,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 07 f1 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 07 f3 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 01 00 01 	add\.p gr16,sp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 00 01 	add\.p gr16,sp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 00 03 	add\.p gr16,gr3,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 00 11 	add\.p gr0,gr17,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 00 13 	add\.p gr0,gr19,gr0
+
+[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 10 11 	add\.p sp,gr17,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 10 13 	add\.p sp,gr19,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 00 00 03 	add\.p gr0,gr3,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 00 10 03 	add\.p sp,gr3,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 00 11 	add\.p gr16,gr17,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 00 13 	add\.p gr16,gr19,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 07 f1 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 07 f3 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 00 00 01 	add\.p gr0,sp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 00 01 	add\.p gr0,sp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 00 03 	add\.p gr0,gr3,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 17 f1 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 01 00 02 	add\.p gr16,fp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 10 12 	add\.p sp,gr18,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 00 10 02 	add\.p sp,fp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 00 12 	add\.p gr16,gr18,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 07 f2 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 17 f2 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 10 02 	add\.p sp,fp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	x
+[0-9a-f ]+:	00 00 00 02 	add\.p gr0,fp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 07 f2 	\*unknown\*
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 01 00 02 	add\.p gr16,fp,gr0
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
+[0-9a-f	 ]+: R_FRV_TLSDESC_VALUE	\.tbss
+[0-9a-f ]+:	00 00 00 12 	add\.p gr0,gr18,gr0
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-shared-3.d b/binutils-2.19/ld/testsuite/ld-frv/tls-shared-3.d
new file mode 100644
index 0000000..c4eed38
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-shared-3.d
@@ -0,0 +1,27 @@
+#name: FRV TLS undefweak relocs, shared linking
+#source: tls-3.s
+#objdump: -DR -j .text -j .got -j .plt
+#ld: -shared
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 c8 f0 0c 	ldi\.p @\(gr15,12\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 c8 f0 0c 	ldi @\(gr15,12\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
+[0-9a-f	 ]+: R_FRV_TLSOFF	u
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-static-1.d b/binutils-2.19/ld/testsuite/ld-frv/tls-static-1.d
new file mode 100644
index 0000000..d33d8cf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-static-1.d
@@ -0,0 +1,70 @@
+#name: FRV TLS relocs, static linking
+#source: tls-1.s
+#objdump: -D -j .text -j .got -j .plt
+#ld: -static tmpdir/tls-1-dep.o
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc f8 10 	setlos\.p 0xf*fffff810,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc f8 20 	setlos\.p 0xf*fffff820,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 30 	setlos 0xf*fffff830,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 30 	setlos 0xf*fffff830,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc f8 30 	setlos\.p 0xf*fffff830,gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc 00 00 	setlos\.p lo\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	90 fc f8 30 	setlos 0xf*fffff830,gr8
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	92 fc f8 30 	setlos 0xf*fffff830,gr9
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 10 	setlos 0xf*fffff810,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 20 	setlos 0xf*fffff820,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc f8 30 	setlos 0xf*fffff830,gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
+[0-9a-f ]+:	ff ff f8 30 	cop2 -32,cpr63,cpr48,cpr63
+[0-9a-f ]+:	ff ff f8 10 	cop2 -32,cpr63,cpr16,cpr63
+[0-9a-f ]+:	ff ff f8 20 	cop2 -32,cpr63,cpr32,cpr63
+[0-9a-f ]+:	00 00 00 00 	add\.p gr0,gr0,gr0
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls-static-3.d b/binutils-2.19/ld/testsuite/ld-frv/tls-static-3.d
new file mode 100644
index 0000000..e761cc8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls-static-3.d
@@ -0,0 +1,26 @@
+#name: FRV TLS undefweak relocs, static linking
+#source: tls-3.s
+#objdump: -D -j .text -j .got -j .plt
+#ld: -static
+
+.*:     file format elf.*frv.*
+
+Disassembly of section \.text:
+
+[0-9a-f ]+<_start>:
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	12 fc 00 00 	setlos\.p lo\(0x0\),gr9
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+[0-9a-f ]+:	00 88 00 00 	nop\.p
+[0-9a-f ]+:	80 88 00 00 	nop
+[0-9a-f ]+:	92 fc 00 00 	setlos lo\(0x0\),gr9
+Disassembly of section \.got:
+
+[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_)>:
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-frv/tls.exp b/binutils-2.19/ld/testsuite/ld-frv/tls.exp
new file mode 100644
index 0000000..bb3d6a3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-frv/tls.exp
@@ -0,0 +1,65 @@
+# Expect script for FRV FDPIC TLS linker tests
+#   Copyright 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+if {![istarget frv*-*-*] || ![is_elf_format]} {
+    return
+}
+
+global ASFLAGS
+set saved_ASFLAGS "$ASFLAGS"
+set ASFLAGS "$ASFLAGS -mfdpic"
+
+global LDFLAGS
+set saved_LDFLAGS "$LDFLAGS"
+set LDFLAGS "$LDFLAGS -melf32frvfd"
+
+run_ld_link_tests [list [list "tls-1-dep" "$LDFLAGS -shared" "" "tls-1-dep.s" [list] "tls-1-dep.so" ""]]
+run_dump_test "tls-static-1"
+run_dump_test "tls-dynamic-1"
+run_dump_test "tls-pie-1"
+run_dump_test "tls-shared-1-fail"
+run_dump_test "tls-shared-1"
+
+run_dump_test "tls-relax-static-1"
+run_dump_test "tls-relax-dynamic-1"
+run_dump_test "tls-relax-pie-1"
+run_dump_test "tls-relax-shared-1"
+
+run_dump_test "tls-dynamic-2"
+run_dump_test "tls-shared-2"
+run_dump_test "tls-initial-shared-2"
+
+run_dump_test "tls-relax-dynamic-2"
+run_dump_test "tls-relax-shared-2"
+run_dump_test "tls-relax-initial-shared-2"
+
+run_dump_test "tls-static-3"
+run_dump_test "tls-dynamic-3"
+run_dump_test "tls-pie-3"
+run_dump_test "tls-shared-3"
+
+run_dump_test "tls-relax-static-3"
+run_dump_test "tls-relax-dynamic-3"
+run_dump_test "tls-relax-pie-3"
+run_dump_test "tls-relax-shared-3"
+
+set LDFLAGS "$saved_LDFLAGS"
+set ASFLAGS "$saved_ASFLAGS"
diff --git a/binutils-2.19/ld/testsuite/ld-gc/gc.c b/binutils-2.19/ld/testsuite/ld-gc/gc.c
new file mode 100644
index 0000000..6b356ad
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-gc/gc.c
@@ -0,0 +1,21 @@
+int unused_var = 7;
+int used_var = 7;
+
+int
+unused_func (int v)
+{
+  return 3 * unused_var;
+}
+
+int
+__attribute__((noinline))
+used_func (int v)
+{
+  return 2 * used_var;
+}
+
+int
+main (void)
+{
+  return used_func (5);
+}
diff --git a/binutils-2.19/ld/testsuite/ld-gc/gc.exp b/binutils-2.19/ld/testsuite/ld-gc/gc.exp
new file mode 100644
index 0000000..400e989
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-gc/gc.exp
@@ -0,0 +1,81 @@
+# Expect script for ld-gc tests
+#   Copyright 2008
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# These tests require --gc-sections
+if ![check_gc_sections_available] {
+    return
+}
+
+set cflags "-ffunction-sections -fdata-sections"
+set objfile "tmpdir/gc.o"
+
+if { [is_remote host] || [which $CC] != 0 } {
+    ld_compile "$CC -c $CFLAGS $cflags" $srcdir/$subdir/gc.c $objfile
+}
+
+proc test_gc { testname filename linker ldflags} {
+    global nm
+    global srcdir
+    global subdir
+    global nm_output
+    global objfile
+
+    if ![file readable $objfile ] {
+	untested $testname
+	return
+    }
+
+    set outfile "tmpdir/$filename"
+
+    if ![ld_simple_link $linker $outfile "-L$srcdir/$subdir $ldflags $objfile"] {
+	fail $testname
+	return
+    }
+    if ![ld_nm $nm "" $outfile] {
+	unresolved $testname
+	return
+    }
+    if {![info exists nm_output(used_func)] \
+	    || ![info exists nm_output(used_var)]} {
+	send_log "used sections do not exist\n"
+	verbose "used sections do not exist"
+	fail $testname
+	return
+    }
+    #ppc64_elf_gc_mark_hook needs to be taught how to look through
+    #the .toc section to properly mark variable sections for gc.
+    setup_xfail "powerpc64*-*-*"
+    if {[info exists nm_output(unused_func)] \
+	    || [info exists nm_output(unused_var)]} {
+	send_log "unused section still here\n"
+	verbose "unused section still here"
+	fail $testname
+	return
+    }
+    pass $testname
+}
+
+test_gc "Check --gc-section" "gcexe" $ld "--gc-sections -e main"
+test_gc "Check --gc-section/-q" "gcrexe" $ld "--gc-sections -q -e main"
+test_gc "Check --gc-section/-r/-e" "gcrel" $ld "-r --gc-sections -e main"
+test_gc "Check --gc-section/-r/-u" "gcrel" $ld "-r --gc-sections -u used_func"
+
+run_dump_test "noent"
diff --git a/binutils-2.19/ld/testsuite/ld-gc/noent.d b/binutils-2.19/ld/testsuite/ld-gc/noent.d
new file mode 100644
index 0000000..1741a74
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-gc/noent.d
@@ -0,0 +1,3 @@
+# name: --gc-sections -r without -e
+# ld: --gc-sections -r
+# error: gc-sections requires either an entry or an undefined symbol
diff --git a/binutils-2.19/ld/testsuite/ld-gc/noent.s b/binutils-2.19/ld/testsuite/ld-gc/noent.s
new file mode 100644
index 0000000..ea74bf4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-gc/noent.s
@@ -0,0 +1,4 @@
+	.text
+	.globl entry
+entry:
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/gcsection.d b/binutils-2.19/ld/testsuite/ld-h8300/gcsection.d
new file mode 100644
index 0000000..638d985
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/gcsection.d
@@ -0,0 +1,27 @@
+# name: H8300 GCC section test case
+# ld: --gc-sections  -m h8300helf
+# objdump: -d --no-show-raw-insn
+.*:     file format .*-h8300
+
+Disassembly of section .text:
+
+00000100 <_functionWeUse>:
+ 100:	mov.l	er6,@-er7
+ 104:	mov.l	er7,er6
+ 106:	subs	#4,er7
+ 108:	mov.w	r0,@\(0xfffe:16,er6\)
+ 10c:	mov.w	@\(0xfffe:16,er6\),r2
+ 110:	mov.w	r2,r0
+ 112:	adds	#4,er7
+ 114:	mov.l	@er7\+,er6
+ 118:	rts	
+
+0000011a <_start>:
+ 11a:	mov.l	er6,@-er7
+ 11e:	mov.l	er7,er6
+ 120:	mov.w	#0x4b,r0
+ 124:	jsr	@0x100:24
+ 128:	mov.w	r0,r2
+ 12a:	mov.w	r2,r0
+ 12c:	mov.l	@er7\+,er6
+ 130:	rts	
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/gcsection.s b/binutils-2.19/ld/testsuite/ld-h8300/gcsection.s
new file mode 100644
index 0000000..2149ee9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/gcsection.s
@@ -0,0 +1,43 @@
+	.h8300h
+	.section	.text.functionWeUse,"ax",@progbits
+	.align 1
+	.global _functionWeUse
+_functionWeUse:
+	mov.l	er6,@-er7
+	mov.l	er7,er6
+	subs	#4,er7
+	mov.w	r0,@(-2,er6)
+	mov.w	@(-2,er6),r2
+	mov.w	r2,r0
+	adds	#4,er7
+	mov.l	@er7+,er6
+	rts
+	.size	_functionWeUse, .-_functionWeUse
+	.section	.text.functionWeDontUse,"ax",@progbits
+	.align 1
+	.global _functionWeDontUse
+_functionWeDontUse:
+	mov.l	er6,@-er7
+	mov.l	er7,er6
+	subs	#4,er7
+	mov.w	r0,@(-2,er6)
+	mov.w	@(-2,er6),r2
+	mov.w	r2,r0
+	adds	#4,er7
+	mov.l	@er7+,er6
+	rts
+	.size	_functionWeDontUse, .-_functionWeDontUse
+	.section	.text.start,"ax",@progbits
+	.align 1
+	.global _start
+_start:
+	mov.l	er6,@-er7
+	mov.l	er7,er6
+	mov.w	#75,r0
+	jsr	@_functionWeUse
+	mov.w	r0,r2
+	mov.w	r2,r0
+	mov.l	@er7+,er6
+	rts
+	.size	_start, .-_start
+	.end
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/h8300.exp b/binutils-2.19/ld/testsuite/ld-h8300/h8300.exp
new file mode 100644
index 0000000..0f9efcb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/h8300.exp
@@ -0,0 +1,44 @@
+# Expect script for ld-h8300 tests
+# Copyright 2002, 2003, 2004, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Nick Clifton  <nickc@redhat.com>
+#
+
+# Test h8300
+
+if ![istarget h8300-*-*] {
+    return
+}
+
+run_dump_test relax
+
+if {[istarget *-elf]} {
+    run_dump_test relax-2
+    run_dump_test relax-3
+    run_dump_test relax-4
+    run_dump_test relax-5
+    run_dump_test relax-6
+    run_dump_test gcsection	
+} else {
+    run_dump_test relax-3-coff
+    run_dump_test relax-4-coff
+    run_dump_test relax-5-coff
+    run_dump_test relax-6-coff
+}
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax-2.d b/binutils-2.19/ld/testsuite/ld-h8300/relax-2.d
new file mode 100644
index 0000000..963139d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax-2.d
@@ -0,0 +1,11 @@
+# name: H8300 Relaxation Test 2
+# ld: --relax -m h8300helf
+# objdump: -d --no-show-raw-insn
+
+.*:     file format .*-h8300
+
+Disassembly of section .text:
+
+00000100 <_start>:
+ *100:	mov.b	@0x67:8,r0l
+ *102:	mov.b	@0x4321:16,r0l
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax-2.s b/binutils-2.19/ld/testsuite/ld-h8300/relax-2.s
new file mode 100644
index 0000000..aa82dba
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax-2.s
@@ -0,0 +1,8 @@
+	.h8300h
+	.globl	_start
+_start:
+	mov.b	@foo:16,r0l
+	mov.b	@bar:32,r0l
+
+	.equ	foo,0xffff67
+	.equ	bar,0x4321
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax-3-coff.d b/binutils-2.19/ld/testsuite/ld-h8300/relax-3-coff.d
new file mode 100644
index 0000000..0384398
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax-3-coff.d
@@ -0,0 +1,36 @@
+# name: H8300 Relaxation Test 3 (for COFF)
+# source: relax-3.s
+# ld: --relax -m h8300s
+# objdump: -d
+
+.*:     file format .*-h8300
+
+Disassembly of section .text:
+
+00000100 <_start>:
+#
+# Relaxation of aa:16
+#
+.*:	6a 08 00 00.*mov.b	@0x0:16,r0l
+.*:	6a 08 7f ff.*mov.b	@0x7fff:16,r0l
+.*:	6a 08 80 00.*mov.b	@0x8000:16,r0l
+.*:	6a 08 fe ff.*mov.b	@0xfeff:16,r0l
+.*:	28 00      .*mov.b	@0x0:8,r0l
+.*:	28 ff      .*mov.b	@0xff:8,r0l
+#
+# Relaxation of aa:32
+#
+.*:	6a 08 00 00.*mov.b	@0x0:16,r0l
+.*:	6a 08 7f ff.*mov.b	@0x7fff:16,r0l
+.*:	6a 28 00 00.*mov.b	@0x8000:32,r0l
+.*:	80 00 
+.*:	6a 28 00 00.*mov.b	@0xff00:32,r0l
+.*:	ff 00 
+.*:	6a 28 00 ff.*mov.b	@0xffff00:32,r0l
+.*:	ff 00 
+.*:	6a 28 ff ff.*mov.b	@0xffff7fff:32,r0l
+.*:	7f ff 
+.*:	6a 08 80 00.*mov.b	@0x8000:16,r0l
+.*:	6a 08 fe ff.*mov.b	@0xfeff:16,r0l
+.*:	28 00      .*mov.b	@0x0:8,r0l
+.*:	28 ff      .*mov.b	@0xff:8,r0l
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax-3.d b/binutils-2.19/ld/testsuite/ld-h8300/relax-3.d
new file mode 100644
index 0000000..b9eded2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax-3.d
@@ -0,0 +1,35 @@
+# name: H8300 Relaxation Test 3
+# ld: --relax -m h8300self
+# objdump: -d
+
+.*:     file format .*-h8300
+
+Disassembly of section .text:
+
+00000100 <_start>:
+#
+# Relaxation of aa:16
+#
+.*:	6a 08 00 00 	mov.b	@0x0:16,r0l
+.*:	6a 08 7f ff 	mov.b	@0x7fff:16,r0l
+.*:	6a 08 80 00 	mov.b	@0x8000:16,r0l
+.*:	6a 08 fe ff 	mov.b	@0xfeff:16,r0l
+.*:	28 00 *	mov.b	@0x0:8,r0l
+.*:	28 ff *	mov.b	@0xff:8,r0l
+#
+# Relaxation of aa:32
+#
+.*:	6a 08 00 00 	mov.b	@0x0:16,r0l
+.*:	6a 08 7f ff 	mov.b	@0x7fff:16,r0l
+.*:	6a 28 00 00 	mov.b	@0x8000:32,r0l
+.*:	80 00 
+.*:	6a 28 00 00 	mov.b	@0xff00:32,r0l
+.*:	ff 00 
+.*:	6a 28 00 ff 	mov.b	@0xffff00:32,r0l
+.*:	ff 00 
+.*:	6a 28 ff ff 	mov.b	@0xffff7fff:32,r0l
+.*:	7f ff 
+.*:	6a 08 80 00 	mov.b	@0x8000:16,r0l
+.*:	6a 08 fe ff 	mov.b	@0xfeff:16,r0l
+.*:	28 00 *	mov.b	@0x0:8,r0l
+.*:	28 ff *	mov.b	@0xff:8,r0l
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax-3.s b/binutils-2.19/ld/testsuite/ld-h8300/relax-3.s
new file mode 100644
index 0000000..f4a2346
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax-3.s
@@ -0,0 +1,32 @@
+	.h8300s
+	.globl	_start
+_start:
+	# s3-s6 aren't valid 16-bit addresses.
+	mov.b	@s1:16,r0l
+	mov.b	@s2:16,r0l
+	mov.b	@s7:16,r0l
+	mov.b	@s8:16,r0l
+	mov.b	@s9:16,r0l
+	mov.b	@s10:16,r0l
+
+	mov.b	@s1:32,r0l
+	mov.b	@s2:32,r0l
+	mov.b	@s3:32,r0l
+	mov.b	@s4:32,r0l
+	mov.b	@s5:32,r0l
+	mov.b	@s6:32,r0l
+	mov.b	@s7:32,r0l
+	mov.b	@s8:32,r0l
+	mov.b	@s9:32,r0l
+	mov.b	@s10:32,r0l
+
+	.equ	s1,0
+	.equ	s2,0x7fff
+	.equ	s3,0x8000
+	.equ	s4,0xff00
+	.equ	s5,0xffff00
+	.equ	s6,0xffff7fff
+	.equ	s7,0xffff8000
+	.equ	s8,0xfffffeff
+	.equ	s9,0xffffff00
+	.equ	s10,0xffffffff
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax-4-coff.d b/binutils-2.19/ld/testsuite/ld-h8300/relax-4-coff.d
new file mode 100644
index 0000000..d6417ac
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax-4-coff.d
@@ -0,0 +1,76 @@
+# name: H8300 Relaxation Test 4 (for COFF)
+# source: relax-4.s
+# ld: --relax -m h8300s
+# objdump: -d
+
+.*:     file format .*-h8300
+
+Disassembly of section .text:
+
+00000100 <_start>:
+ 100:	f8 03.*mov.b	#0x3,r0l
+ 102:	fa 05.*mov.b	#0x5,r2l
+ 104:	7f ff 60 80.*bset	r0l,@0xff:8
+ 108:	7f 00 60 a0.*bset	r2l,@0x0:8
+ 10c:	7e ff 63 a0.*btst	r2l,@0xff:8
+ 110:	7e 00 63 80.*btst	r0l,@0x0:8
+ 114:	6a 18 00 00.*bset	#0x5,@0x0:16
+ 118:	70 50 
+ 11a:	6a 18 7f ff.*bset	#0x5,@0x7fff:16
+ 11e:	70 50 
+ 120:	6a 18 80 00.*bset	#0x5,@0x8000:16
+ 124:	70 50 
+ 126:	6a 18 fe ff.*bset	#0x5,@0xfeff:16
+ 12a:	70 50 
+ 12c:	7f 00 70 50.*bset	#0x5,@0x0:8
+ 130:	7f ff 70 50.*bset	#0x5,@0xff:8
+ 134:	6a 10 00 00.*band	#0x5,@0x0:16
+ 138:	76 50 
+ 13a:	6a 10 7f ff.*band	#0x5,@0x7fff:16
+ 13e:	76 50 
+ 140:	6a 10 80 00.*band	#0x5,@0x8000:16
+ 144:	76 50 
+ 146:	6a 10 fe ff.*band	#0x5,@0xfeff:16
+ 14a:	76 50 
+ 14c:	7e 00 76 50.*band	#0x5,@0x0:8
+ 150:	7e ff 76 50.*band	#0x5,@0xff:8
+ 154:	7f ff 60 a0.*bset	r2l,@0xff:8
+ 158:	7f 00 60 80.*bset	r0l,@0x0:8
+ 15c:	7e ff 63 80.*btst	r0l,@0xff:8
+ 160:	7e 00 63 a0.*btst	r2l,@0x0:8
+ 164:	6a 18 00 00.*bset	#0x6,@0x0:16
+ 168:	70 60 
+ 16a:	6a 18 7f ff.*bset	#0x6,@0x7fff:16
+ 16e:	70 60 
+ 170:	6a 38 00 00.*bset	#0x6,@0x8000:32
+ 174:	80 00 70 60 
+ 178:	6a 38 00 00.*bset	#0x6,@0xff00:32
+ 17c:	ff 00 70 60 
+ 180:	6a 38 00 ff.*bset	#0x6,@0xffff00:32
+ 184:	ff 00 70 60 
+ 188:	6a 38 ff ff.*bset	#0x6,@0xffff7fff:32
+ 18c:	7f ff 70 60 
+ 190:	6a 18 80 00.*bset	#0x6,@0x8000:16
+ 194:	70 60 
+ 196:	6a 18 fe ff.*bset	#0x6,@0xfeff:16
+ 19a:	70 60 
+ 19c:	7f 00 70 60.*bset	#0x6,@0x0:8
+ 1a0:	7f ff 70 60.*bset	#0x6,@0xff:8
+ 1a4:	6a 10 00 00.*band	#0x6,@0x0:16
+ 1a8:	76 60 
+ 1aa:	6a 10 7f ff.*band	#0x6,@0x7fff:16
+ 1ae:	76 60 
+ 1b0:	6a 30 00 00.*band	#0x6,@0x8000:32
+ 1b4:	80 00 76 60 
+ 1b8:	6a 30 00 00.*band	#0x6,@0xff00:32
+ 1bc:	ff 00 76 60 
+ 1c0:	6a 30 00 ff.*band	#0x6,@0xffff00:32
+ 1c4:	ff 00 76 60 
+ 1c8:	6a 30 ff ff.*band	#0x6,@0xffff7fff:32
+ 1cc:	7f ff 76 60 
+ 1d0:	6a 10 80 00.*band	#0x6,@0x8000:16
+ 1d4:	76 60 
+ 1d6:	6a 10 fe ff.*band	#0x6,@0xfeff:16
+ 1da:	76 60 
+ 1dc:	7e 00 76 60.*band	#0x6,@0x0:8
+ 1e0:	7e ff 76 60.*band	#0x6,@0xff:8
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax-4.d b/binutils-2.19/ld/testsuite/ld-h8300/relax-4.d
new file mode 100644
index 0000000..b8d38ce
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax-4.d
@@ -0,0 +1,51 @@
+# name: H8300 Relaxation Test 4
+# ld: --relax -m h8300self
+# objdump: -d --no-show-raw-insn
+
+.*:     file format .*-h8300
+
+Disassembly of section .text:
+
+00000100 <_start>:
+ 100:	mov.b	#0x3,r0l
+ 102:	mov.b	#0x5,r2l
+ 104:	bset	r0l,@0xff:8
+ 108:	bset	r2l,@0x0:8
+ 10c:	btst	r2l,@0xff:8
+ 110:	btst	r0l,@0x0:8
+ 114:	bset	#0x5,@0x0:16
+ 11a:	bset	#0x5,@0x7fff:16
+ 120:	bset	#0x5,@0x8000:16
+ 126:	bset	#0x5,@0xfeff:16
+ 12c:	bset	#0x5,@0x0:8
+ 130:	bset	#0x5,@0xff:8
+ 134:	band	#0x5,@0x0:16
+ 13a:	band	#0x5,@0x7fff:16
+ 140:	band	#0x5,@0x8000:16
+ 146:	band	#0x5,@0xfeff:16
+ 14c:	band	#0x5,@0x0:8
+ 150:	band	#0x5,@0xff:8
+ 154:	bset	r2l,@0xff:8
+ 158:	bset	r0l,@0x0:8
+ 15c:	btst	r0l,@0xff:8
+ 160:	btst	r2l,@0x0:8
+ 164:	bset	#0x6,@0x0:16
+ 16a:	bset	#0x6,@0x7fff:16
+ 170:	bset	#0x6,@0x8000:32
+ 178:	bset	#0x6,@0xff00:32
+ 180:	bset	#0x6,@0xffff00:32
+ 188:	bset	#0x6,@0xffff7fff:32
+ 190:	bset	#0x6,@0x8000:16
+ 196:	bset	#0x6,@0xfeff:16
+ 19c:	bset	#0x6,@0x0:8
+ 1a0:	bset	#0x6,@0xff:8
+ 1a4:	band	#0x6,@0x0:16
+ 1aa:	band	#0x6,@0x7fff:16
+ 1b0:	band	#0x6,@0x8000:32
+ 1b8:	band	#0x6,@0xff00:32
+ 1c0:	band	#0x6,@0xffff00:32
+ 1c8:	band	#0x6,@0xffff7fff:32
+ 1d0:	band	#0x6,@0x8000:16
+ 1d6:	band	#0x6,@0xfeff:16
+ 1dc:	band	#0x6,@0x0:8
+ 1e0:	band	#0x6,@0xff:8
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax-4.s b/binutils-2.19/ld/testsuite/ld-h8300/relax-4.s
new file mode 100644
index 0000000..32b5b06
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax-4.s
@@ -0,0 +1,72 @@
+; Relaxation is possible for following bit manipulation instructions

+; BAND, BCLR, BIAND, BILD, BIOR, BIST, BIXOR, BLD, BNOT, BOR, BSET, BST, BTST, BXOR

+  	.h8300s

+    	.globl	_start

+    _start:

+    	# s3-s6 aren't valid 16-bit addresses.

+    	mov.b   #0x3,r0l

+   	mov.b   #0x5,r2l

+;

+; Relaxation of aa:16

+;	    	

+   	bset    r0l,@s10:16

+	bset    r2l,@s9:16

+	btst    r2l,@s10:16

+   	btst    r0l,@s9:16

+   	

+   	bset	#5,@s1:16

+   	bset	#5,@s2:16

+   	bset	#5,@s7:16

+   	bset	#5,@s8:16

+   	bset	#5,@s9:16

+   	bset	#5,@s10:16   	   	

+	   	

+   	band	#5,@s1:16

+	band	#5,@s2:16

+	band	#5,@s7:16

+   	band	#5,@s8:16

+   	band	#5,@s9:16

+   	band	#5,@s10:16

+;

+; Relaxation of aa:32

+;

+   	bset    r2l,@s10:32

+   	bset    r0l,@s9:32

+   	btst    r0l,@s10:32

+   	btst    r2l,@s9:32

+   	

+   	bset	#6,@s1:32

+   	bset	#6,@s2:32

+   	bset	#6,@s3:32

+   	bset	#6,@s4:32

+   	bset	#6,@s5:32

+   	bset	#6,@s6:32

+   	bset	#6,@s7:32

+   	bset	#6,@s8:32

+   	bset	#6,@s9:32

+   	bset	#6,@s10:32

+	    

+   	band	#6,@s1:32

+   	band	#6,@s2:32

+   	band	#6,@s3:32

+   	band	#6,@s4:32

+   	band	#6,@s5:32

+   	band	#6,@s6:32

+  	band	#6,@s7:32

+   	band	#6,@s8:32

+   	band	#6,@s9:32

+   	band	#6,@s10:32

+    

+    	.equ	s1,0

+    	.equ	s2,0x7fff

+    	.equ	s3,0x8000

+    	.equ	s4,0xff00

+    	.equ	s5,0xffff00

+    	.equ	s6,0xffff7fff

+    	.equ	s7,0xffff8000

+    	.equ	s8,0xfffffeff

+    	.equ	s9,0xffffff00

+    	.equ	s10,0xffffffff

+    	

+    	.end

+    	

diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax-5-coff.d b/binutils-2.19/ld/testsuite/ld-h8300/relax-5-coff.d
new file mode 100644
index 0000000..eed2ba0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax-5-coff.d
@@ -0,0 +1,50 @@
+# name: H8300 Relaxation Test 5 (for COFF)
+# source: relax-5.s
+# ld: --relax -m h8300s
+# objdump: -d --no-show-raw-insn
+
+.*:     file format .*-h8300
+
+Disassembly of section .text:
+
+00000100 <_start>:
+ 100:.*ldc	@0x0:16,ccr
+ 106:.*ldc	@0x7fff:16,ccr
+ 10c:.*ldc	@0x8000:32,ccr
+ 114:.*ldc	@0xff00:32,ccr
+ 11c:.*ldc	@0xffff00:32,ccr
+ 124:.*ldc	@0xffff7fff:32,ccr
+ 12c:.*ldc	@0x8000:16,ccr
+ 132:.*ldc	@0xfeff:16,ccr
+ 138:.*ldc	@0xff00:16,ccr
+ 13e:.*ldc	@0xffff:16,ccr
+ 144:.*stc	ccr,@0x0:16
+ 14a:.*stc	ccr,@0x7fff:16
+ 150:.*stc	ccr,@0x8000:32
+ 158:.*stc	ccr,@0xff00:32
+ 160:.*stc	ccr,@0xffff00:32
+ 168:.*stc	ccr,@0xffff7fff:32
+ 170:.*stc	ccr,@0x8000:16
+ 176:.*stc	ccr,@0xfeff:16
+ 17c:.*stc	ccr,@0xff00:16
+ 182:.*stc	ccr,@0xffff:16
+ 188:.*ldc	@0x0:16,exr
+ 18e:.*ldc	@0x7fff:16,exr
+ 194:.*ldc	@0x8000:32,exr
+ 19c:.*ldc	@0xff00:32,exr
+ 1a4:.*ldc	@0xffff00:32,exr
+ 1ac:.*ldc	@0xffff7fff:32,exr
+ 1b4:.*ldc	@0x8000:16,exr
+ 1ba:.*ldc	@0xfeff:16,exr
+ 1c0:.*ldc	@0xff00:16,exr
+ 1c6:.*ldc	@0xffff:16,exr
+ 1cc:.*stc	exr,@0x0:16
+ 1d2:.*stc	exr,@0x7fff:16
+ 1d8:.*stc	exr,@0x8000:32
+ 1e0:.*stc	exr,@0xff00:32
+ 1e8:.*stc	exr,@0xffff00:32
+ 1f0:.*stc	exr,@0xffff7fff:32
+ 1f8:.*stc	exr,@0x8000:16
+ 1fe:.*stc	exr,@0xfeff:16
+ 204:.*stc	exr,@0xff00:16
+ 20a:.*stc	exr,@0xffff:16
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax-5.d b/binutils-2.19/ld/testsuite/ld-h8300/relax-5.d
new file mode 100644
index 0000000..01e12a5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax-5.d
@@ -0,0 +1,50 @@
+# name: H8300 Relaxation Test 5
+# source: relax-5.s
+# ld: --relax -m h8300self
+# objdump: -d --no-show-raw-insn
+
+.*:     file format .*-h8300
+
+Disassembly of section .text:
+
+00000100 <_start>:
+ 100:	ldc	@0x0:16,ccr
+ 106:	ldc	@0x7fff:16,ccr
+ 10c:	ldc	@0x8000:32,ccr
+ 114:	ldc	@0xff00:32,ccr
+ 11c:	ldc	@0xffff00:32,ccr
+ 124:	ldc	@0xffff7fff:32,ccr
+ 12c:	ldc	@0x8000:16,ccr
+ 132:	ldc	@0xfeff:16,ccr
+ 138:	ldc	@0xff00:16,ccr
+ 13e:	ldc	@0xffff:16,ccr
+ 144:	stc	ccr,@0x0:16
+ 14a:	stc	ccr,@0x7fff:16
+ 150:	stc	ccr,@0x8000:32
+ 158:	stc	ccr,@0xff00:32
+ 160:	stc	ccr,@0xffff00:32
+ 168:	stc	ccr,@0xffff7fff:32
+ 170:	stc	ccr,@0x8000:16
+ 176:	stc	ccr,@0xfeff:16
+ 17c:	stc	ccr,@0xff00:16
+ 182:	stc	ccr,@0xffff:16
+ 188:	ldc	@0x0:16,exr
+ 18e:	ldc	@0x7fff:16,exr
+ 194:	ldc	@0x8000:32,exr
+ 19c:	ldc	@0xff00:32,exr
+ 1a4:	ldc	@0xffff00:32,exr
+ 1ac:	ldc	@0xffff7fff:32,exr
+ 1b4:	ldc	@0x8000:16,exr
+ 1ba:	ldc	@0xfeff:16,exr
+ 1c0:	ldc	@0xff00:16,exr
+ 1c6:	ldc	@0xffff:16,exr
+ 1cc:	stc	exr,@0x0:16
+ 1d2:	stc	exr,@0x7fff:16
+ 1d8:	stc	exr,@0x8000:32
+ 1e0:	stc	exr,@0xff00:32
+ 1e8:	stc	exr,@0xffff00:32
+ 1f0:	stc	exr,@0xffff7fff:32
+ 1f8:	stc	exr,@0x8000:16
+ 1fe:	stc	exr,@0xfeff:16
+ 204:	stc	exr,@0xff00:16
+ 20a:	stc	exr,@0xffff:16
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax-5.s b/binutils-2.19/ld/testsuite/ld-h8300/relax-5.s
new file mode 100644
index 0000000..b5afedb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax-5.s
@@ -0,0 +1,66 @@
+; Relaxation is possible from @aa:32 to @aa:16 for following instructions
+; ldc.w @@aa:32,ccr 
+; stc.w ccr,@@aa:32
+; ldc.w @aa:32,exr
+; stc.w exr,@aa:32
+	.h8300s
+    	.globl	_start
+;
+; Relaxation of aa:32
+;
+    _start:
+    	ldc  @s1:32,ccr
+	ldc  @s2:32,ccr
+	ldc  @s3:32,ccr
+	ldc  @s4:32,ccr
+	ldc  @s5:32,ccr
+	ldc  @s6:32,ccr
+	ldc  @s7:32,ccr
+	ldc  @s8:32,ccr
+	ldc  @s9:32,ccr
+	ldc  @s10:32,ccr
+
+	stc  ccr,@s1:32
+	stc  ccr,@s2:32
+	stc  ccr,@s3:32
+	stc  ccr,@s4:32
+	stc  ccr,@s5:32
+	stc  ccr,@s6:32
+	stc  ccr,@s7:32
+	stc  ccr,@s8:32
+	stc  ccr,@s9:32
+	stc  ccr,@s10:32
+	
+    	ldc  @s1:32,exr
+	ldc  @s2:32,exr
+	ldc  @s3:32,exr
+	ldc  @s4:32,exr
+	ldc  @s5:32,exr
+	ldc  @s6:32,exr
+	ldc  @s7:32,exr
+	ldc  @s8:32,exr
+	ldc  @s9:32,exr
+	ldc  @s10:32,exr
+
+	stc  exr,@s1:32
+	stc  exr,@s2:32
+	stc  exr,@s3:32
+	stc  exr,@s4:32
+	stc  exr,@s5:32
+	stc  exr,@s6:32
+	stc  exr,@s7:32
+	stc  exr,@s8:32
+	stc  exr,@s9:32
+	stc  exr,@s10:32
+    	
+	.equ	s1,0
+    	.equ	s2,0x7fff
+    	.equ	s3,0x8000
+    	.equ	s4,0xff00
+    	.equ	s5,0xffff00
+    	.equ	s6,0xffff7fff
+    	.equ	s7,0xffff8000
+    	.equ	s8,0xfffffeff
+    	.equ	s9,0xffffff00
+    	.equ	s10,0xffffffff
+    	.end
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax-6-coff.d b/binutils-2.19/ld/testsuite/ld-h8300/relax-6-coff.d
new file mode 100644
index 0000000..b9c1e2f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax-6-coff.d
@@ -0,0 +1,11 @@
+# name: H8300 Relaxation Test 6
+# source: relax-6.s
+# ld: --relax -m h8300s
+# objdump: -d --no-show-raw-insn
+
+.*:     file format .*-h8300
+Disassembly of section .text:
+
+00000100 <_start>:
+ 100:	mov.b	r2l,@0xbd:8
+ 102:	rts	
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax-6.d b/binutils-2.19/ld/testsuite/ld-h8300/relax-6.d
new file mode 100644
index 0000000..023af78
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax-6.d
@@ -0,0 +1,11 @@
+# name: H8300 Relaxation Test 6
+# source: relax-6.s
+# ld: --relax -m h8300self
+# objdump: -d --no-show-raw-insn
+
+.*:     file format .*-h8300
+Disassembly of section .text:
+
+00000100 <_start>:
+ 100:	mov.b	r2l,@0xbd:8
+ 102:	rts	
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax-6.s b/binutils-2.19/ld/testsuite/ld-h8300/relax-6.s
new file mode 100644
index 0000000..fb44b54
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax-6.s
@@ -0,0 +1,5 @@
+	.h8300s
+	.global _start
+_start:
+	mov.b	r2l,@0xFFFFFFBD:32
+	rts
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax.d b/binutils-2.19/ld/testsuite/ld-h8300/relax.d
new file mode 100644
index 0000000..e7315a1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax.d
@@ -0,0 +1,21 @@
+# name: H8300 Relaxation Test
+# ld: --relax
+# objdump: -d
+
+# Based on the test case reported by Kazu Hirata:
+# http://sources.redhat.com/ml/binutils/2002-11/msg00301.html
+
+.*:     file format .*-h8300
+
+Disassembly of section .text:
+
+00000100 <_start>:
+ 100:	0d 00.*mov.w	r0,r0
+ 102:	47 02.*beq	.+2 \(0x106\)
+ 104:	55 02.*bsr	.+2 \(0x108\)
+
+00000106 <.L1>:
+ 106:	54 70.*rts	
+
+00000108 <_bar>:
+ 108:	54 70.*rts	
diff --git a/binutils-2.19/ld/testsuite/ld-h8300/relax.s b/binutils-2.19/ld/testsuite/ld-h8300/relax.s
new file mode 100644
index 0000000..b06f3a9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-h8300/relax.s
@@ -0,0 +1,10 @@
+	.text
+	.global _start
+_start:
+        mov.w   r0,r0
+        beq     .L1
+        jsr     @_bar
+.L1:
+        rts
+_bar:
+        rts
diff --git a/binutils-2.19/ld/testsuite/ld-i386/abs.d b/binutils-2.19/ld/testsuite/ld-i386/abs.d
new file mode 100644
index 0000000..6293515
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/abs.d
@@ -0,0 +1,10 @@
+#name: Absolute non-overflowing relocs
+#source: abs.s
+#source: zero.s
+#ld:
+#objdump: -rs
+
+.*:     file format .*
+
+Contents of section \.text:
+[ 	][0-9a-f]+ c800fff0 c8000110 c9c3.*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/abs.s b/binutils-2.19/ld/testsuite/ld-i386/abs.s
new file mode 100644
index 0000000..2705950
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/abs.s
@@ -0,0 +1,8 @@
+ .text
+ .global _start
+_start:
+	enter	$zero + 0xff00, $zero + 0xf0
+	enter	$zero - 0xff00, $zero - 0xf0
+	leave
+	ret
+ .p2align 4,0x90
diff --git a/binutils-2.19/ld/testsuite/ld-i386/alloc.d b/binutils-2.19/ld/testsuite/ld-i386/alloc.d
new file mode 100644
index 0000000..c2b22f2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/alloc.d
@@ -0,0 +1,4 @@
+#name: Invalid allocated section
+#as: --32
+#ld: -melf_i386 -T alloc.t
+#error: .*section `.foo' can't be allocated in segment 0.*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/alloc.s b/binutils-2.19/ld/testsuite/ld-i386/alloc.s
new file mode 100644
index 0000000..8c4f8fa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/alloc.s
@@ -0,0 +1,6 @@
+	.section .bar,"ax","progbits"
+	.byte 0
+	.section .foo,"aw","progbits"
+	.byte 0
+	.bss
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-i386/alloc.t b/binutils-2.19/ld/testsuite/ld-i386/alloc.t
new file mode 100644
index 0000000..ea7f48c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/alloc.t
@@ -0,0 +1,13 @@
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+PHDRS {
+ text PT_LOAD FLAGS(5); /* R_E */
+}
+SECTIONS
+{
+  . = 0xC0000000 + ((0x100000 + (0x100000 - 1)) & ~(0x100000 - 1));
+  .bar : AT(ADDR(.bar) - 0xC0000000) { *(.bar) } :text
+  .bss : AT(ADDR(.bss) - 0xC0000000) { *(.bss) }
+  .foo 0 : AT(ADDR(.bss) + SIZEOF(.bss) - 0xC0000000) { *(.foo) } :text
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-i386/combreloc.d b/binutils-2.19/ld/testsuite/ld-i386/combreloc.d
new file mode 100644
index 0000000..bbe9134
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/combreloc.d
@@ -0,0 +1,17 @@
+# Test that orphan reloc sections are merged into .rel.dyn with
+# -z combreloc.
+#source: combreloc.s
+#as: --32
+#ld: -shared -melf_i386 -z combreloc
+#readelf: -r
+
+Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name
+[0-9a-f]+  [0-9a-f]+06 R_386_GLOB_DAT    [0-9a-f]+   _start
+[0-9a-f]+  [0-9a-f]+01 R_386_32          [0-9a-f]+   _start
+[0-9a-f]+  [0-9a-f]+01 R_386_32          [0-9a-f]+   _start
+[0-9a-f]+  [0-9a-f]+01 R_386_32          [0-9a-f]+   _start
+
+Relocation section '.rel.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name
+[0-9a-f]+  [0-9a-f]+07 R_386_JUMP_SLOT   [0-9a-f]+   foo
diff --git a/binutils-2.19/ld/testsuite/ld-i386/combreloc.s b/binutils-2.19/ld/testsuite/ld-i386/combreloc.s
new file mode 100644
index 0000000..2a78a7c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/combreloc.s
@@ -0,0 +1,22 @@
+	.text
+	.globl	_start, foo
+	.type	_start,@function
+_start:
+	pushl	%ebp
+	movl	%esp, %ebp
+        pushl	%ebx
+        call	1f
+1:	popl	%ebx
+	addl	$_GLOBAL_OFFSET_TABLE_+[.-1b], %ebx
+	movl	_start@GOT(%ebx), %eax
+	movl	(%eax), %eax
+	call	foo@PLT
+	movl	(%esp), %ebx
+	leave
+foo:	ret
+	.data
+	.long	_start
+	.section "__libc_subfreeres", "aw", @progbits
+	.long	_start
+	.section "__libc_atexit", "aw", @progbits
+	.long	_start
diff --git a/binutils-2.19/ld/testsuite/ld-i386/emit-relocs.d b/binutils-2.19/ld/testsuite/ld-i386/emit-relocs.d
new file mode 100644
index 0000000..0c16b94
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/emit-relocs.d
@@ -0,0 +1,8 @@
+
+Relocation section '\.rel\.plt' at offset .* contains 1 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name
+.*  .*07 R_386_JUMP_SLOT   00000000   foo
+
+Relocation section '\.rel\.text' at offset .* contains 1 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name
+.*  .*04 R_386_PLT32       00000000   foo
diff --git a/binutils-2.19/ld/testsuite/ld-i386/emit-relocs.s b/binutils-2.19/ld/testsuite/ld-i386/emit-relocs.s
new file mode 100644
index 0000000..e609a2e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/emit-relocs.s
@@ -0,0 +1 @@
+	call	foo@plt
diff --git a/binutils-2.19/ld/testsuite/ld-i386/hidden1.d b/binutils-2.19/ld/testsuite/ld-i386/hidden1.d
new file mode 100644
index 0000000..5ace20d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/hidden1.d
@@ -0,0 +1,3 @@
+#as: --32
+#ld: -shared -melf_i386
+#error: .*relocation R_386_GOTOFF against undefined hidden symbol `foo' can not be used when making a shared object
diff --git a/binutils-2.19/ld/testsuite/ld-i386/hidden1.s b/binutils-2.19/ld/testsuite/ld-i386/hidden1.s
new file mode 100644
index 0000000..2c1ce93
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/hidden1.s
@@ -0,0 +1,9 @@
+	.text
+.globl bar
+	.type	bar, @function
+bar:
+	leal	foo@GOTOFF(%ecx), %eax
+	ret
+	.size	bar, .-bar
+	.weak	foo
+	.hidden	foo
diff --git a/binutils-2.19/ld/testsuite/ld-i386/hidden2.d b/binutils-2.19/ld/testsuite/ld-i386/hidden2.d
new file mode 100644
index 0000000..90bc438
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/hidden2.d
@@ -0,0 +1,13 @@
+#as: --32
+#ld: -shared -melf_i386
+#objdump: -drw
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+[a-f0-9]+ <bar>:
+[ 	]*[a-f0-9]+:	e8 cf fe ff ff       	call   0 <bar-0x[a-f0-9]+>
+[ 	]*[a-f0-9]+:	c3                   	ret    
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-i386/hidden2.s b/binutils-2.19/ld/testsuite/ld-i386/hidden2.s
new file mode 100644
index 0000000..03e2ce7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/hidden2.s
@@ -0,0 +1,9 @@
+	.text
+.globl bar
+	.type	bar, @function
+bar:
+	call	foo
+	ret
+	.size	bar, .-bar
+	.weak	foo
+	.hidden	foo
diff --git a/binutils-2.19/ld/testsuite/ld-i386/hidden3.d b/binutils-2.19/ld/testsuite/ld-i386/hidden3.d
new file mode 100644
index 0000000..5ace20d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/hidden3.d
@@ -0,0 +1,3 @@
+#as: --32
+#ld: -shared -melf_i386
+#error: .*relocation R_386_GOTOFF against undefined hidden symbol `foo' can not be used when making a shared object
diff --git a/binutils-2.19/ld/testsuite/ld-i386/hidden3.s b/binutils-2.19/ld/testsuite/ld-i386/hidden3.s
new file mode 100644
index 0000000..221b159
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/hidden3.s
@@ -0,0 +1,8 @@
+	.text
+.globl bar
+	.type	bar, @function
+bar:
+	leal	foo@GOTOFF(%ecx), %eax
+	ret
+	.size	bar, .-bar
+	.hidden	foo
diff --git a/binutils-2.19/ld/testsuite/ld-i386/i386.exp b/binutils-2.19/ld/testsuite/ld-i386/i386.exp
new file mode 100644
index 0000000..6f75f3a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/i386.exp
@@ -0,0 +1,140 @@
+# Expect script for ld-i386 tests
+#   Copyright (C) 2002, 2005, 2006, 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Test i386 linking; all types of relocs.  This tests the assembler and
+# tools like objdump as well as the linker.
+
+if {[istarget "i?86-*-vxworks"]} {
+    set i386tests {
+	{"VxWorks shared library test 1" "-shared -Tvxworks1.ld"
+	 "" {vxworks1-lib.s}
+	 {{readelf --relocs vxworks1-lib.rd} {objdump -dr vxworks1-lib.dd}
+	  {readelf --symbols vxworks1-lib.nd} {readelf -d vxworks1-lib.td}}
+	 "libvxworks1.so"}
+	{"VxWorks executable test 1 (dynamic)" \
+	 "tmpdir/libvxworks1.so -Tvxworks1.ld -q --force-dynamic"
+	 "" {vxworks1.s}
+	 {{readelf --relocs vxworks1.rd} {objdump -dr vxworks1.dd}}
+	 "vxworks1"}
+	{"VxWorks executable test 2 (dynamic)" \
+	 "-Tvxworks1.ld -q --force-dynamic"
+	 "" {vxworks2.s}
+	 {{readelf --segments vxworks2.sd}}
+	 "vxworks2"}
+	{"VxWorks executable test 2 (static)"
+	 "-Tvxworks1.ld"
+	 "" {vxworks2.s}
+	 {{readelf --segments vxworks2-static.sd}}
+	 "vxworks2"}
+    }
+    run_ld_link_tests $i386tests
+    run_dump_test "vxworks1-static"
+}
+
+if { !([istarget "i?86-*-elf*"]		
+       || ([istarget "i?86-*-linux*"]
+	   && ![istarget "*-*-*aout*"]
+	   && ![istarget "*-*-*oldld*"])
+       || [istarget "x86_64-*-linux*"]
+       || [istarget "amd64-*-linux*"]) } {
+    return
+}
+
+# List contains test-items with 3 items followed by 2 lists:
+# 0:name 1:ld options 2:assembler options
+# 3:filenames of assembler files 4: action and options. 5: name of output file
+
+# Actions:
+# objdump: Apply objdump options on result.  Compare with regex (last arg).
+# nm: Apply nm options on result.  Compare with regex (last arg).
+# readelf: Apply readelf options on result.  Compare with regex (last arg).
+
+set i386tests {
+    {"TLS -fpic -shared transitions" "-shared -melf_i386"
+     "--32" {tlspic1.s tlspic2.s}
+     {{readelf -Ssrl tlspic.rd} {objdump -drj.text tlspic.dd}
+      {objdump -sj.got tlspic.sd} {objdump -sj.tdata tlspic.td}}
+      "libtlspic.so"}
+    {"TLS descriptor -fpic -shared transitions" "-shared -melf_i386"
+     "--32" {tlsdesc.s tlspic2.s}
+     {{readelf -Ssrl tlsdesc.rd} {objdump -drj.text tlsdesc.dd}
+      {objdump "-s -j.got -j.got.plt" tlsdesc.sd} {objdump -sj.tdata tlsdesc.td}}
+      "libtlsdesc.so"}
+    {"Helper shared library" "-shared -melf_i386"
+     "--32" {tlslib.s} {} "libtlslib.so"}
+    {"TLS -fpic and -fno-pic exec transitions"
+     "-melf_i386 tmpdir/libtlslib.so" "--32" {tlsbinpic.s tlsbin.s}
+     {{readelf -Ssrl tlsbin.rd} {objdump -drj.text tlsbin.dd}
+      {objdump -sj.got tlsbin.sd} {objdump -sj.tdata tlsbin.td}}
+      "tlsbin"}
+    {"TLS descriptor -fpic and -fno-pic exec transitions"
+     "-melf_i386 tmpdir/libtlslib.so" "--32" {tlsbindesc.s tlsbin.s}
+     {{readelf -Ssrl tlsbindesc.rd} {objdump -drj.text tlsbindesc.dd}
+      {objdump -sj.got tlsbindesc.sd} {objdump -sj.tdata tlsbindesc.td}}
+      "tlsbindesc"}
+    {"TLS -fno-pic -shared" "-shared -melf_i386"
+     "--32" {tlsnopic1.s tlsnopic2.s}
+     {{readelf -Ssrl tlsnopic.rd} {objdump -drj.text tlsnopic.dd}
+      {objdump -sj.got tlsnopic.sd}} "libtlsnopic.so"}
+    {"TLS with global dynamic and descriptors"
+	"-shared -melf_i386" "--32" {tlsgdesc.s}
+     {{readelf -Ssrl tlsgdesc.rd} {objdump -drj.text tlsgdesc.dd}}
+      "libtlsgdesc.so"}
+    {"TLS in debug sections" "-melf_i386"
+     "--32" {tlsg.s}
+     {{objdump -sj.debug_foobar tlsg.sd}} "tlsg"}
+    {"TLS @indntpoff with %eax" "-melf_i386" "--32" {tlsindntpoff.s}
+     {{objdump -drj.text tlsindntpoff.dd}} "tlsindntpoff"}
+    {"Reloc section order" "-shared -melf_i386 -z nocombreloc" "--32"
+     {reloc.s} {{objdump -hw reloc.d}} "reloc.so"}
+    {"Basic --emit-relocs support" "-shared -melf_i386 --emit-relocs" "--32"
+     {emit-relocs.s} {{readelf --relocs emit-relocs.d}} "emit-relocs.so"}
+    {"-z combreloc relocation sections" "-shared -melf_i386 -z combreloc"
+     "--32" {combreloc.s} {{readelf -r combreloc.d}} "combreloc.so"}
+    {"TLS GD->LE transition" "-melf_i386"
+     "--32" {tlsgd1.s}
+     {{objdump -dwr tlsgd1.dd}} "tlsgd1"}
+    {"TLS LD->LE transition" "-melf_i386"
+     "--32" {tlsld1.s}
+     {{objdump -dwr tlsld1.dd}} "tlsld1"}
+    {"TLS IE->LE transition" "-melf_i386"
+     "--32" {tlsie1.s}
+     {{objdump -dwr tlsie1.dd}} "tlsie1"}
+}
+
+run_ld_link_tests $i386tests
+
+run_dump_test "abs"
+run_dump_test "pcrel8"
+run_dump_test "pcrel16"
+run_dump_test "pcrel16abs"
+run_dump_test "alloc"
+run_dump_test "warn1"
+run_dump_test "tlsie2"
+run_dump_test "tlsie3"
+run_dump_test "tlsie4"
+run_dump_test "tlsie5"
+run_dump_test "hidden1"
+run_dump_test "hidden2"
+run_dump_test "hidden3"
+run_dump_test "protected1"
+run_dump_test "protected2"
+run_dump_test "protected3"
diff --git a/binutils-2.19/ld/testsuite/ld-i386/pcrel16.d b/binutils-2.19/ld/testsuite/ld-i386/pcrel16.d
new file mode 100644
index 0000000..3d45afe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/pcrel16.d
@@ -0,0 +1,15 @@
+#name: PCREL16 overflow
+#as: --32
+#ld: -melf_i386 -Ttext 0x0
+#objdump: -drj.text -m i8086
+
+.*: +file format elf32-i386
+
+Disassembly of section .text:
+
+0+ <_start>:
+	...
+     420:	cd 42[ 	]+int    \$0x42
+     422:	ca 02 00[ 	]+lret   \$0x2
+	...
+    f065:	e9 b8 13[ 	]+jmp    420 <_start\+0x420>
diff --git a/binutils-2.19/ld/testsuite/ld-i386/pcrel16.s b/binutils-2.19/ld/testsuite/ld-i386/pcrel16.s
new file mode 100644
index 0000000..d68a6c6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/pcrel16.s
@@ -0,0 +1,9 @@
+	.code16
+	.text
+	.globl _start
+_start:
+	.org 0x420
+	int $0x42
+	lret $2
+	.org 0xf065
+	jmp _start+((0x42) << 4)
diff --git a/binutils-2.19/ld/testsuite/ld-i386/pcrel16abs.d b/binutils-2.19/ld/testsuite/ld-i386/pcrel16abs.d
new file mode 100644
index 0000000..f4bfca5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/pcrel16abs.d
@@ -0,0 +1,12 @@
+#name: PCREL16 absolute reloc
+#as: --32
+#ld: -melf_i386 -Ttext 0xfffffff0
+#objdump: -drj.text -m i8086
+
+.*: +file format elf32-i386
+
+Disassembly of section .text:
+
+f+0 <_start>:
+f+0:	e9 0d e0[ 	]+jmp[ 	]+ffffe000 <SEGMENT_SIZE\+0xfffee000>
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-i386/pcrel16abs.s b/binutils-2.19/ld/testsuite/ld-i386/pcrel16abs.s
new file mode 100644
index 0000000..4bf68a7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/pcrel16abs.s
@@ -0,0 +1,6 @@
+SEGMENT_SIZE = 0x10000
+RVECTOR = 0x00010
+.code16
+ .globl _start
+_start:
+ jmp SEGMENT_SIZE-(0x1f00 +0xf0 +RVECTOR)
diff --git a/binutils-2.19/ld/testsuite/ld-i386/pcrel8.d b/binutils-2.19/ld/testsuite/ld-i386/pcrel8.d
new file mode 100644
index 0000000..208c64e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/pcrel8.d
@@ -0,0 +1,4 @@
+#name: PCREL8 overflow
+#as: --32
+#ld: -melf_i386
+#error: .*relocation truncated to fit: R_386_PC8 .*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/pcrel8.s b/binutils-2.19/ld/testsuite/ld-i386/pcrel8.s
new file mode 100644
index 0000000..e624aaf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/pcrel8.s
@@ -0,0 +1,11 @@
+ .text
+ .code16
+ .global _start, fwd
+_start:
+	jcxz	fwd
+ .rept 10
+	testl $0x12345678, %ss:0x76543210(,%eax,4)
+ .endr
+fwd:
+	leave
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-i386/protected1.d b/binutils-2.19/ld/testsuite/ld-i386/protected1.d
new file mode 100644
index 0000000..a3cb5ce
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/protected1.d
@@ -0,0 +1,3 @@
+#as: --32
+#ld: -shared -melf_i386
+#error: .*relocation R_386_GOTOFF against protected function `foo' can not be used when making a shared object
diff --git a/binutils-2.19/ld/testsuite/ld-i386/protected1.s b/binutils-2.19/ld/testsuite/ld-i386/protected1.s
new file mode 100644
index 0000000..2edaeb2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/protected1.s
@@ -0,0 +1,13 @@
+	.text
+.globl foo
+	.protected	foo
+	.type	foo, @function
+foo:
+	ret
+	.size	foo, .-foo
+.globl bar
+	.type	bar, @function
+bar:
+	leal	foo@GOTOFF(%ecx), %eax
+	ret
+	.size	bar, .-bar
diff --git a/binutils-2.19/ld/testsuite/ld-i386/protected2.d b/binutils-2.19/ld/testsuite/ld-i386/protected2.d
new file mode 100644
index 0000000..ba53e59
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/protected2.d
@@ -0,0 +1,16 @@
+#as: --32
+#ld: -shared -melf_i386
+#objdump: -drw
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+[a-f0-9]+ <foo>:
+[ 	]*[a-f0-9]+:	c3                   	ret    
+
+0+[a-f0-9]+ <bar>:
+[ 	]*[a-f0-9]+:	e8 fa ff ff ff       	call   [a-f0-9]+ <foo>
+[ 	]*[a-f0-9]+:	c3                   	ret    
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-i386/protected2.s b/binutils-2.19/ld/testsuite/ld-i386/protected2.s
new file mode 100644
index 0000000..61e5aec
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/protected2.s
@@ -0,0 +1,13 @@
+	.text
+.globl foo
+	.protected	foo
+	.type	foo, @function
+foo:
+	ret
+	.size	foo, .-foo
+.globl bar
+	.type	bar, @function
+bar:
+	call	foo
+	ret
+	.size	bar, .-bar
diff --git a/binutils-2.19/ld/testsuite/ld-i386/protected3.d b/binutils-2.19/ld/testsuite/ld-i386/protected3.d
new file mode 100644
index 0000000..e42185a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/protected3.d
@@ -0,0 +1,13 @@
+#as: --32
+#ld: -shared -melf_i386
+#objdump: -drw
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+[a-f0-9]+ <bar>:
+[ 	]*[a-f0-9]+:	8b 81 0c 00 00 00    	mov    0x[a-f0-9]+\(%ecx\),%eax
+[ 	]*[a-f0-9]+:	c3                   	ret    
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-i386/protected3.s b/binutils-2.19/ld/testsuite/ld-i386/protected3.s
new file mode 100644
index 0000000..7a605a2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/protected3.s
@@ -0,0 +1,15 @@
+	.protected	foo
+.globl foo
+	.data
+	.align 4
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	1
+	.text
+.globl bar
+	.type	bar, @function
+bar:
+	movl	foo@GOTOFF(%ecx), %eax
+	ret
+	.size	bar, .-bar
diff --git a/binutils-2.19/ld/testsuite/ld-i386/reloc.d b/binutils-2.19/ld/testsuite/ld-i386/reloc.d
new file mode 100644
index 0000000..e559e53
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/reloc.d
@@ -0,0 +1,17 @@
+# Test that orphan reloc sections are placed before .rel.plt even when
+# .rel.plt is the only reloc section.
+#source: reloc.s
+#as: --32
+#ld: -shared -melf_i386 -z nocombreloc
+#objdump: -hw
+
+.*: +file format elf32-i386
+#...
+.*\.relplatypus.*
+#...
+.*\.rel\.plt.*
+# x86 ld doesn't output non-alloc reloc sections to shared libs, so disable
+# the following two lines for the time being.
+# #...
+# .*\.relechidna.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-i386/reloc.s b/binutils-2.19/ld/testsuite/ld-i386/reloc.s
new file mode 100644
index 0000000..0e3ff1d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/reloc.s
@@ -0,0 +1,8 @@
+ .section echidna
+ .long .text
+
+ .section platypus,"ax"
+ .long .text
+
+ .text
+ jmp _start@plt
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsbin.dd b/binutils-2.19/ld/testsuite/ld-i386/tlsbin.dd
new file mode 100644
index 0000000..9cf14a5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsbin.dd
@@ -0,0 +1,464 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: --32
+#ld: -melf_i386 tmpdir/libtlslib.so
+#objdump: -drj.text
+#target: i?86-*-*
+
+# PT_TLS layout is:
+# Offset from	Offset from	Name
+# TCB base	TCB end
+# 0x00		-0xa0		sg1..sg8
+# 0x20		-0x80		sl1..sl8
+# 0x40		-0x60		sh1..sh8
+# 0x60		-0x40		bg1..bg8
+# 0x80		-0x20		bl1..bl8
+
+.*: +file format elf32-i386
+
+Disassembly of section .text:
+
+0+8049000 <fn2>:
+ 8049000:	55[ 	]+push   %ebp
+ 8049001:	89 e5[ 	]+mov    %esp,%ebp
+ 8049003:	53[ 	]+push   %ebx
+ 8049004:	50[ 	]+push   %eax
+ 8049005:	e8 00 00 00 00[ 	]+call   804900a <fn2\+0xa>
+ 804900a:	5b[ 	]+pop    %ebx
+ 804900b:	81 c3 1a 11 00 00[ 	]+add    \$0x111a,%ebx
+ 8049011:	90[ 	]+nop *
+ 8049012:	90[ 	]+nop *
+ 8049013:	90[ 	]+nop *
+ 8049014:	90[ 	]+nop *
+#  GD -> IE because variable is not defined in executable
+ 8049015:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 804901b:	2b 83 f8 ff ff ff[ 	]+sub    -0x8\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sG1
+ 8049021:	90[ 	]+nop *
+ 8049022:	90[ 	]+nop *
+ 8049023:	90[ 	]+nop *
+ 8049024:	90[ 	]+nop *
+#  GD -> IE because variable is not defined in executable where
+#  the variable is referenced through @gottpoff too
+ 8049025:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 804902b:	2b 83 e8 ff ff ff[ 	]+sub    -0x18\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sG2
+ 8049031:	90[ 	]+nop *
+ 8049032:	90[ 	]+nop *
+ 8049033:	90[ 	]+nop *
+ 8049034:	90[ 	]+nop *
+#  GD -> IE because variable is not defined in executable where
+#  the variable is referenced through @gotntpoff too
+ 8049035:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 804903b:	03 83 dc ff ff ff[ 	]+add    -0x24\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	sG3
+ 8049041:	90[ 	]+nop *
+ 8049042:	90[ 	]+nop *
+ 8049043:	90[ 	]+nop *
+ 8049044:	90[ 	]+nop *
+#  GD -> IE because variable is not defined in executable where
+#  the variable is referenced through @gottpoff and @gotntpoff too
+ 8049045:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 804904b:	2b 83 ec ff ff ff[ 	]+sub    -0x14\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sG4
+ 8049051:	90[ 	]+nop *
+ 8049052:	90[ 	]+nop *
+ 8049053:	90[ 	]+nop *
+ 8049054:	90[ 	]+nop *
+#  GD -> LE with global variable defined in executable
+ 8049055:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 804905b:	81 e8 00 10 00 00[ 	]+sub    \$0x1000,%eax
+#							sg1
+ 8049061:	90[ 	]+nop *
+ 8049062:	90[ 	]+nop *
+ 8049063:	90[ 	]+nop *
+ 8049064:	90[ 	]+nop *
+#  GD -> LE with local variable defined in executable
+ 8049065:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 804906b:	81 e8 e0 0f 00 00[ 	]+sub    \$0xfe0,%eax
+#							sl1
+ 8049071:	90[ 	]+nop *
+ 8049072:	90[ 	]+nop *
+ 8049073:	90[ 	]+nop *
+ 8049074:	90[ 	]+nop *
+#  GD -> LE with hidden variable defined in executable
+ 8049075:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 804907b:	81 e8 c0 0f 00 00[ 	]+sub    \$0xfc0,%eax
+#							sh1
+ 8049081:	90[ 	]+nop *
+ 8049082:	90[ 	]+nop *
+ 8049083:	90[ 	]+nop *
+ 8049084:	90[ 	]+nop *
+#  LD -> LE
+ 8049085:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 804908b:	90[ 	]+nop *
+ 804908c:	8d 74 26 00[ 	]+lea    0x0\(%esi,%eiz,1\),%esi
+ 8049090:	90[ 	]+nop *
+ 8049091:	90[ 	]+nop *
+ 8049092:	8d 90 20 f0 ff ff[ 	]+lea    -0xfe0\(%eax\),%edx
+#							sl1
+ 8049098:	90[ 	]+nop *
+ 8049099:	90[ 	]+nop *
+ 804909a:	8d 88 24 f0 ff ff[ 	]+lea    -0xfdc\(%eax\),%ecx
+#							sl2
+ 80490a0:	90[ 	]+nop *
+ 80490a1:	90[ 	]+nop *
+ 80490a2:	90[ 	]+nop *
+ 80490a3:	90[ 	]+nop *
+#  LD -> LE against hidden variables
+ 80490a4:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 80490aa:	90[ 	]+nop *
+ 80490ab:	8d 74 26 00[ 	]+lea    0x0\(%esi,%eiz,1\),%esi
+ 80490af:	90[ 	]+nop *
+ 80490b0:	90[ 	]+nop *
+ 80490b1:	8d 90 40 f0 ff ff[ 	]+lea    -0xfc0\(%eax\),%edx
+#							sh1
+ 80490b7:	90[ 	]+nop *
+ 80490b8:	90[ 	]+nop *
+ 80490b9:	8d 88 44 f0 ff ff[ 	]+lea    -0xfbc\(%eax\),%ecx
+#							sh2
+ 80490bf:	90[ 	]+nop *
+ 80490c0:	90[ 	]+nop *
+ 80490c1:	90[ 	]+nop *
+ 80490c2:	90[ 	]+nop *
+#  @gottpoff IE against global var
+ 80490c3:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ 80490ca:	90[ 	]+nop *
+ 80490cb:	90[ 	]+nop *
+ 80490cc:	2b 8b e8 ff ff ff[ 	]+sub    -0x18\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF32	sG2
+ 80490d2:	90[ 	]+nop *
+ 80490d3:	90[ 	]+nop *
+ 80490d4:	90[ 	]+nop *
+ 80490d5:	90[ 	]+nop *
+#  @gottpoff IE against global var
+ 80490d6:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 80490dc:	90[ 	]+nop *
+ 80490dd:	90[ 	]+nop *
+ 80490de:	2b 83 ec ff ff ff[ 	]+sub    -0x14\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sG4
+ 80490e4:	90[ 	]+nop *
+ 80490e5:	90[ 	]+nop *
+ 80490e6:	90[ 	]+nop *
+ 80490e7:	90[ 	]+nop *
+#  @gotntpoff IE against global var
+ 80490e8:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ 80490ef:	90[ 	]+nop *
+ 80490f0:	90[ 	]+nop *
+ 80490f1:	03 8b dc ff ff ff[ 	]+add    -0x24\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	sG3
+ 80490f7:	90[ 	]+nop *
+ 80490f8:	90[ 	]+nop *
+ 80490f9:	90[ 	]+nop *
+ 80490fa:	90[ 	]+nop *
+#  @gotntpoff IE against global var
+ 80490fb:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 8049101:	90[ 	]+nop *
+ 8049102:	90[ 	]+nop *
+ 8049103:	03 83 f0 ff ff ff[ 	]+add    -0x10\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	sG4
+ 8049109:	90[ 	]+nop *
+ 804910a:	90[ 	]+nop *
+ 804910b:	90[ 	]+nop *
+ 804910c:	90[ 	]+nop *
+#  @gottpoff IE -> LE against global var defined in exec
+ 804910d:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ 8049114:	90[ 	]+nop *
+ 8049115:	90[ 	]+nop *
+ 8049116:	81 e9 00 10 00 00[ 	]+sub    \$0x1000,%ecx
+#							sg1
+ 804911c:	90[ 	]+nop *
+ 804911d:	90[ 	]+nop *
+ 804911e:	90[ 	]+nop *
+ 804911f:	90[ 	]+nop *
+#  @gotntpoff IE -> LE against local var
+ 8049120:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ 8049127:	90[ 	]+nop *
+ 8049128:	90[ 	]+nop *
+ 8049129:	81 c0 20 f0 ff ff[ 	]+add    \$0xfffff020,%eax
+#							sl1
+ 804912f:	90[ 	]+nop *
+ 8049130:	90[ 	]+nop *
+ 8049131:	90[ 	]+nop *
+ 8049132:	90[ 	]+nop *
+#  @gottpoff IE -> LE against hidden var
+ 8049133:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ 804913a:	90[ 	]+nop *
+ 804913b:	90[ 	]+nop *
+ 804913c:	81 e9 c0 0f 00 00[ 	]+sub    \$0xfc0,%ecx
+#							sh1
+ 8049142:	90[ 	]+nop *
+ 8049143:	90[ 	]+nop *
+ 8049144:	90[ 	]+nop *
+ 8049145:	90[ 	]+nop *
+#  Direct access through %gs
+#  @gotntpoff IE against global var
+ 8049146:	8b 8b e0 ff ff ff[ 	]+mov    -0x20\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	sG5
+ 804914c:	90[ 	]+nop *
+ 804914d:	90[ 	]+nop *
+ 804914e:	65 8b 11[ 	]+mov    %gs:\(%ecx\),%edx
+ 8049151:	90[ 	]+nop *
+ 8049152:	90[ 	]+nop *
+ 8049153:	90[ 	]+nop *
+ 8049154:	90[ 	]+nop *
+#  @gotntpoff IE->LE against local var
+ 8049155:	c7 c0 30 f0 ff ff[ 	]+mov    \$0xfffff030,%eax
+#							sl5
+ 804915b:	90[ 	]+nop *
+ 804915c:	90[ 	]+nop *
+ 804915d:	65 8b 10[ 	]+mov    %gs:\(%eax\),%edx
+ 8049160:	90[ 	]+nop *
+ 8049161:	90[ 	]+nop *
+ 8049162:	90[ 	]+nop *
+ 8049163:	90[ 	]+nop *
+#  @gotntpoff IE->LE against hidden var
+ 8049164:	c7 c2 50 f0 ff ff[ 	]+mov    \$0xfffff050,%edx
+#							sh5
+ 804916a:	90[ 	]+nop *
+ 804916b:	90[ 	]+nop *
+ 804916c:	65 8b 12[ 	]+mov    %gs:\(%edx\),%edx
+ 804916f:	90[ 	]+nop *
+ 8049170:	90[ 	]+nop *
+ 8049171:	90[ 	]+nop *
+ 8049172:	90[ 	]+nop *
+#  GD -> IE because variable is not defined in executable
+ 8049173:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 8049179:	2b 83 f8 ff ff ff[ 	]+sub    -0x8\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sG1
+ 804917f:	90[ 	]+nop *
+ 8049180:	90[ 	]+nop *
+ 8049181:	90[ 	]+nop *
+ 8049182:	90[ 	]+nop *
+ 8049183:	8b 5d fc[ 	]+mov    -0x4\(%ebp\),%ebx
+ 8049186:	c9[ 	]+leave *
+ 8049187:	c3[ 	]+ret *
+
+0+8049188 <_start>:
+ 8049188:	55[ 	]+push   %ebp
+ 8049189:	89 e5[ 	]+mov    %esp,%ebp
+ 804918b:	e8 00 00 00 00[ 	]+call   8049190 <_start\+0x8>
+ 8049190:	59[ 	]+pop    %ecx
+ 8049191:	81 c1 94 0f 00 00[ 	]+add    \$0xf94,%ecx
+ 8049197:	90[ 	]+nop *
+ 8049198:	90[ 	]+nop *
+ 8049199:	90[ 	]+nop *
+ 804919a:	90[ 	]+nop *
+#  @gottpoff IE against global var
+ 804919b:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ 80491a2:	90[ 	]+nop *
+ 80491a3:	90[ 	]+nop *
+ 80491a4:	2b 91 f4 ff ff ff[ 	]+sub    -0xc\(%ecx\),%edx
+#				->R_386_TLS_TPOFF32	sG6
+ 80491aa:	90[ 	]+nop *
+ 80491ab:	90[ 	]+nop *
+ 80491ac:	90[ 	]+nop *
+ 80491ad:	90[ 	]+nop *
+#  @indntpoff IE against global var
+ 80491ae:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 80491b4:	90[ 	]+nop *
+ 80491b5:	90[ 	]+nop *
+ 80491b6:	03 05 08 a1 04 08[ 	]+add    0x804a108,%eax
+#				->R_386_TLS_TPOFF	sG7
+ 80491bc:	90[ 	]+nop *
+ 80491bd:	90[ 	]+nop *
+ 80491be:	90[ 	]+nop *
+ 80491bf:	90[ 	]+nop *
+#  @indntpoff direct %gs access IE against global var
+ 80491c0:	8b 15 20 a1 04 08[ 	]+mov    0x804a120,%edx
+#				->R_386_TLS_TPOFF	sG8
+ 80491c6:	90[ 	]+nop *
+ 80491c7:	90[ 	]+nop *
+ 80491c8:	65 8b 02[ 	]+mov    %gs:\(%edx\),%eax
+ 80491cb:	90[ 	]+nop *
+ 80491cc:	90[ 	]+nop *
+ 80491cd:	90[ 	]+nop *
+ 80491ce:	90[ 	]+nop *
+#  @gottpoff IE -> LE against global var defined in exec
+ 80491cf:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ 80491d6:	90[ 	]+nop *
+ 80491d7:	90[ 	]+nop *
+ 80491d8:	81 ea 8c 0f 00 00[ 	]+sub    \$0xf8c,%edx
+#							bg6
+ 80491de:	90[ 	]+nop *
+ 80491df:	90[ 	]+nop *
+ 80491e0:	90[ 	]+nop *
+ 80491e1:	90[ 	]+nop *
+#  @indntpoff IE -> LE against global var defined in exec
+ 80491e2:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 80491e8:	90[ 	]+nop *
+ 80491e9:	90[ 	]+nop *
+ 80491ea:	81 c0 78 f0 ff ff[ 	]+add    \$0xfffff078,%eax
+#							bg7
+ 80491f0:	90[ 	]+nop *
+ 80491f1:	90[ 	]+nop *
+ 80491f2:	90[ 	]+nop *
+ 80491f3:	90[ 	]+nop *
+#  @indntpoff direct %gs access IE -> LE against global var defined
+#  in exec
+ 80491f4:	c7 c2 7c f0 ff ff[ 	]+mov    \$0xfffff07c,%edx
+#							bg8
+ 80491fa:	90[ 	]+nop *
+ 80491fb:	90[ 	]+nop *
+ 80491fc:	65 8b 02[ 	]+mov    %gs:\(%edx\),%eax
+ 80491ff:	90[ 	]+nop *
+ 8049200:	90[ 	]+nop *
+ 8049201:	90[ 	]+nop *
+ 8049202:	90[ 	]+nop *
+#  @gottpoff IE -> LE against local var
+ 8049203:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ 804920a:	90[ 	]+nop *
+ 804920b:	90[ 	]+nop *
+ 804920c:	81 ea 6c 0f 00 00[ 	]+sub    \$0xf6c,%edx
+#							bl6
+ 8049212:	90[ 	]+nop *
+ 8049213:	90[ 	]+nop *
+ 8049214:	90[ 	]+nop *
+ 8049215:	90[ 	]+nop *
+#  @indntpoff IE -> LE against local var
+ 8049216:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 804921c:	90[ 	]+nop *
+ 804921d:	90[ 	]+nop *
+ 804921e:	81 c0 98 f0 ff ff[ 	]+add    \$0xfffff098,%eax
+#							bl7
+ 8049224:	90[ 	]+nop *
+ 8049225:	90[ 	]+nop *
+ 8049226:	90[ 	]+nop *
+ 8049227:	90[ 	]+nop *
+#  @indntpoff direct %gs access IE -> LE against local var
+ 8049228:	c7 c2 9c f0 ff ff[ 	]+mov    \$0xfffff09c,%edx
+#							bl8
+ 804922e:	90[ 	]+nop *
+ 804922f:	90[ 	]+nop *
+ 8049230:	65 8b 02[ 	]+mov    %gs:\(%edx\),%eax
+ 8049233:	90[ 	]+nop *
+ 8049234:	90[ 	]+nop *
+ 8049235:	90[ 	]+nop *
+ 8049236:	90[ 	]+nop *
+#  @gottpoff IE -> LE against hidden but not local var
+ 8049237:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ 804923e:	90[ 	]+nop *
+ 804923f:	90[ 	]+nop *
+ 8049240:	81 ea ac 0f 00 00[ 	]+sub    \$0xfac,%edx
+#							sh6
+ 8049246:	90[ 	]+nop *
+ 8049247:	90[ 	]+nop *
+ 8049248:	90[ 	]+nop *
+ 8049249:	90[ 	]+nop *
+#  @indntpoff IE -> LE against hidden but not local var
+ 804924a:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 8049250:	90[ 	]+nop *
+ 8049251:	90[ 	]+nop *
+ 8049252:	81 c0 58 f0 ff ff[ 	]+add    \$0xfffff058,%eax
+#							sh7
+ 8049258:	90[ 	]+nop *
+ 8049259:	90[ 	]+nop *
+ 804925a:	90[ 	]+nop *
+ 804925b:	90[ 	]+nop *
+#  @indntpoff direct %gs access IE -> LE against hidden but not
+#  local var
+ 804925c:	c7 c2 5c f0 ff ff[ 	]+mov    \$0xfffff05c,%edx
+#							sh8
+ 8049262:	90[ 	]+nop *
+ 8049263:	90[ 	]+nop *
+ 8049264:	65 8b 02[ 	]+mov    %gs:\(%edx\),%eax
+ 8049267:	90[ 	]+nop *
+ 8049268:	90[ 	]+nop *
+ 8049269:	90[ 	]+nop *
+ 804926a:	90[ 	]+nop *
+#  LE @tpoff, global var defined in exec
+ 804926b:	ba 00 10 00 00[ 	]+mov    \$0x1000,%edx
+#							sg1
+ 8049270:	90[ 	]+nop *
+ 8049271:	90[ 	]+nop *
+ 8049272:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 8049278:	90[ 	]+nop *
+ 8049279:	90[ 	]+nop *
+ 804927a:	29 d0[ 	]+sub    %edx,%eax
+ 804927c:	90[ 	]+nop *
+ 804927d:	90[ 	]+nop *
+ 804927e:	90[ 	]+nop *
+ 804927f:	90[ 	]+nop *
+#  LE @tpoff, local var
+ 8049280:	b8 7f 0f 00 00[ 	]+mov    \$0xf7f,%eax
+#							bl1+1
+ 8049285:	90[ 	]+nop *
+ 8049286:	90[ 	]+nop *
+ 8049287:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ 804928e:	90[ 	]+nop *
+ 804928f:	90[ 	]+nop *
+ 8049290:	29 c2[ 	]+sub    %eax,%edx
+ 8049292:	90[ 	]+nop *
+ 8049293:	90[ 	]+nop *
+ 8049294:	90[ 	]+nop *
+ 8049295:	90[ 	]+nop *
+#  LE @tpoff, hidden var defined in exec
+ 8049296:	b8 bd 0f 00 00[ 	]+mov    \$0xfbd,%eax
+#							sh1+3
+ 804929b:	90[ 	]+nop *
+ 804929c:	90[ 	]+nop *
+ 804929d:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ 80492a4:	90[ 	]+nop *
+ 80492a5:	90[ 	]+nop *
+ 80492a6:	29 c2[ 	]+sub    %eax,%edx
+ 80492a8:	90[ 	]+nop *
+ 80492a9:	90[ 	]+nop *
+ 80492aa:	90[ 	]+nop *
+ 80492ab:	90[ 	]+nop *
+#  LE @ntpoff, global var defined in exec
+ 80492ac:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ 80492b2:	90[ 	]+nop *
+ 80492b3:	90[ 	]+nop *
+ 80492b4:	8d 90 04 f0 ff ff[ 	]+lea    -0xffc\(%eax\),%edx
+#							sg2
+ 80492ba:	90[ 	]+nop *
+ 80492bb:	90[ 	]+nop *
+ 80492bc:	90[ 	]+nop *
+ 80492bd:	90[ 	]+nop *
+#  LE @ntpoff, local var, non-canonical sequence
+ 80492be:	b8 86 f0 ff ff[ 	]+mov    \$0xfffff086,%eax
+#							bl2+2
+ 80492c3:	90[ 	]+nop *
+ 80492c4:	90[ 	]+nop *
+ 80492c5:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ 80492cc:	90[ 	]+nop *
+ 80492cd:	90[ 	]+nop *
+ 80492ce:	01 c2[ 	]+add    %eax,%edx
+ 80492d0:	90[ 	]+nop *
+ 80492d1:	90[ 	]+nop *
+ 80492d2:	90[ 	]+nop *
+ 80492d3:	90[ 	]+nop *
+#  LE @ntpoff, hidden var defined in exec, non-canonical sequence
+ 80492d4:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ 80492db:	90[ 	]+nop *
+ 80492dc:	90[ 	]+nop *
+ 80492dd:	81 c2 45 f0 ff ff[ 	]+add    \$0xfffff045,%edx
+#							sh2+1
+ 80492e3:	90[ 	]+nop *
+ 80492e4:	90[ 	]+nop *
+ 80492e5:	90[ 	]+nop *
+ 80492e6:	90[ 	]+nop *
+#  LE @ntpoff, global var defined in exec
+ 80492e7:	65 a1 08 f0 ff ff[ 	]+mov    %gs:0xfffff008,%eax
+#							sg3
+ 80492ed:	90[ 	]+nop *
+ 80492ee:	90[ 	]+nop *
+ 80492ef:	90[ 	]+nop *
+ 80492f0:	90[ 	]+nop *
+#  LE @ntpoff, local var
+ 80492f1:	65 8b 15 8b f0 ff ff[ 	]+mov    %gs:0xfffff08b,%edx
+#							bl3+3
+ 80492f8:	90[ 	]+nop *
+ 80492f9:	90[ 	]+nop *
+ 80492fa:	90[ 	]+nop *
+ 80492fb:	90[ 	]+nop *
+#  LE @ntpoff, hidden var defined in exec
+ 80492fc:	65 8b 15 49 f0 ff ff[ 	]+mov    %gs:0xfffff049,%edx
+#							sh3+1
+ 8049303:	90[ 	]+nop *
+ 8049304:	90[ 	]+nop *
+ 8049305:	90[ 	]+nop *
+ 8049306:	90[ 	]+nop *
+ 8049307:	8b 5d fc[ 	]+mov    -0x4\(%ebp\),%ebx
+ 804930a:	c9[ 	]+leave *
+ 804930b:	c3[ 	]+ret *
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsbin.rd b/binutils-2.19/ld/testsuite/ld-i386/tlsbin.rd
new file mode 100644
index 0000000..56a0deb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsbin.rd
@@ -0,0 +1,160 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: --32
+#ld: -melf_i386 tmpdir/libtlslib.so
+#readelf: -Ssrl
+#target: i?86-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] \.interp +.*
+ +\[[ 0-9]+\] \.hash +.*
+ +\[[ 0-9]+\] \.dynsym +.*
+ +\[[ 0-9]+\] \.dynstr +.*
+ +\[[ 0-9]+\] \.rel.dyn +.*
+ +\[[ 0-9]+\] \.rel.plt +.*
+ +\[[ 0-9]+\] \.plt +.*
+ +\[[ 0-9]+\] \.text +PROGBITS +0+8049000 .*
+ +\[[ 0-9]+\] \.tdata +PROGBITS +0+804a000 [0-9a-f]+ 000060 00 WAT  0   0 4096
+ +\[[ 0-9]+\] \.tbss +NOBITS +[0-9a-f]+ [0-9a-f]+ 000040 00 WAT  0   0  1
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC +0+804a060 .*
+ +\[[ 0-9]+\] \.got +PROGBITS +0+804a100 .*
+ +\[[ 0-9]+\] \.got\.plt +PROGBITS +0+804a124 .*
+ +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x8049188
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  PHDR.*
+  INTERP.*
+.*Requesting program interpreter.*
+  LOAD.*
+  LOAD.*
+  DYNAMIC.*
+  TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+60 0x0+a0 R +0x1000
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 +
+   01 +.interp *
+   02 +.interp .hash .dynsym .dynstr .rel.dyn .rel.plt .plt .text *
+   03 +.tdata .dynamic .got .got.plt *
+   04 +.dynamic *
+   05 +.tdata .tbss *
+
+Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 9 entries:
+ Offset +Info +Type +Sym.Value +Sym. Name
+[0-9a-f ]+R_386_TLS_TPOFF +0+ +sG3
+[0-9a-f ]+R_386_TLS_TPOFF +0+ +sG5
+[0-9a-f ]+R_386_TLS_TPOFF +0+ +sG7
+[0-9a-f ]+R_386_TLS_TPOFF32 0+ +sG2
+[0-9a-f ]+R_386_TLS_TPOFF32 0+ +sG4
+[0-9a-f ]+R_386_TLS_TPOFF +0+ +sG4
+[0-9a-f ]+R_386_TLS_TPOFF32 0+ +sG6
+[0-9a-f ]+R_386_TLS_TPOFF32 0+ +sG1
+[0-9a-f ]+R_386_TLS_TPOFF +0+ +sG8
+
+Relocation section '.rel.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ Offset +Info +Type +Sym.Value  Sym. Name
+[0-9a-f ]+R_386_JUMP_SLOT +[0-9a-f]+ +___tls_get_addr
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value  Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG7
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG2
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG4
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG6
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG1
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG8
+ +[0-9]+: [0-9a-f]+ +0 FUNC +GLOBAL DEFAULT  UND ___tls_get_addr
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value  Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +1 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +2 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +3 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +4 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +5 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +6 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +7 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +8 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +9 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +10 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +11 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +12 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +13 *
+ +[0-9]+: 00000020 +0 TLS +LOCAL  DEFAULT +9 sl1
+ +[0-9]+: 00000024 +0 TLS +LOCAL  DEFAULT +9 sl2
+ +[0-9]+: 00000028 +0 TLS +LOCAL  DEFAULT +9 sl3
+ +[0-9]+: 0000002c +0 TLS +LOCAL  DEFAULT +9 sl4
+ +[0-9]+: 00000030 +0 TLS +LOCAL  DEFAULT +9 sl5
+ +[0-9]+: 00000034 +0 TLS +LOCAL  DEFAULT +9 sl6
+ +[0-9]+: 00000038 +0 TLS +LOCAL  DEFAULT +9 sl7
+ +[0-9]+: 0000003c +0 TLS +LOCAL  DEFAULT +9 sl8
+ +[0-9]+: 00000080 +0 TLS +LOCAL  DEFAULT +10 bl1
+ +[0-9]+: 00000084 +0 TLS +LOCAL  DEFAULT +10 bl2
+ +[0-9]+: 00000088 +0 TLS +LOCAL  DEFAULT +10 bl3
+ +[0-9]+: 0000008c +0 TLS +LOCAL  DEFAULT +10 bl4
+ +[0-9]+: 00000090 +0 TLS +LOCAL  DEFAULT +10 bl5
+ +[0-9]+: 00000094 +0 TLS +LOCAL  DEFAULT +10 bl6
+ +[0-9]+: 00000098 +0 TLS +LOCAL  DEFAULT +10 bl7
+ +[0-9]+: 0000009c +0 TLS +LOCAL  DEFAULT +10 bl8
+ +[0-9]+: 0+804a060 +0 OBJECT  LOCAL +HIDDEN +11 _DYNAMIC
+ +[0-9]+: [0-9a-f]+ +0 OBJECT  LOCAL +HIDDEN +13 _GLOBAL_OFFSET_TABLE_
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG3
+ +[0-9]+: 0000001c +0 TLS +GLOBAL DEFAULT +9 sg8
+ +[0-9]+: 0000007c +0 TLS +GLOBAL DEFAULT +10 bg8
+ +[0-9]+: 00000074 +0 TLS +GLOBAL DEFAULT +10 bg6
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG5
+ +[0-9]+: 00000068 +0 TLS +GLOBAL DEFAULT +10 bg3
+ +[0-9]+: 00000008 +0 TLS +GLOBAL DEFAULT +9 sg3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG7
+ +[0-9]+: 00000048 +0 TLS +GLOBAL HIDDEN +9 sh3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG2
+ +[0-9]+: 0000000c +0 TLS +GLOBAL DEFAULT +9 sg4
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG4
+ +[0-9]+: 00000010 +0 TLS +GLOBAL DEFAULT +9 sg5
+ +[0-9]+: 00000070 +0 TLS +GLOBAL DEFAULT +10 bg5
+ +[0-9]+: 00000058 +0 TLS +GLOBAL HIDDEN +9 sh7
+ +[0-9]+: 0000005c +0 TLS +GLOBAL HIDDEN +9 sh8
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +9 sg1
+ +[0-9]+: 0+8049188 +0 FUNC +GLOBAL DEFAULT +8 _start
+ +[0-9]+: 0000004c +0 TLS +GLOBAL HIDDEN +9 sh4
+ +[0-9]+: 00000078 +0 TLS +GLOBAL DEFAULT +10 bg7
+ +[0-9]+: 00000050 +0 TLS +GLOBAL HIDDEN +9 sh5
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG6
+ +[0-9]+: 0+8049000 +0 FUNC +GLOBAL DEFAULT +8 fn2
+ +[0-9]+: 00000004 +0 TLS +GLOBAL DEFAULT +9 sg2
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG1
+ +[0-9]+: 00000040 +0 TLS +GLOBAL HIDDEN +9 sh1
+ +[0-9]+: 00000014 +0 TLS +GLOBAL DEFAULT +9 sg6
+ +[0-9]+: 00000018 +0 TLS +GLOBAL DEFAULT +9 sg7
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+ +[0-9]+: 00000044 +0 TLS +GLOBAL HIDDEN +9 sh2
+ +[0-9]+: 00000054 +0 TLS +GLOBAL HIDDEN +9 sh6
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG8
+ +[0-9]+: 00000064 +0 TLS +GLOBAL DEFAULT +10 bg2
+ +[0-9]+: 00000060 +0 TLS +GLOBAL DEFAULT +10 bg1
+ +[0-9]+: [0-9a-f]+ +0 FUNC +GLOBAL DEFAULT  UND ___tls_get_addr
+ +[0-9]+: 0000006c +0 TLS +GLOBAL DEFAULT +10 bg4
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsbin.s b/binutils-2.19/ld/testsuite/ld-i386/tlsbin.s
new file mode 100644
index 0000000..db80e09
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsbin.s
@@ -0,0 +1,165 @@
+	.section ".tbss", "awT", @nobits
+	.globl bg1, bg2, bg3, bg4, bg5, bg6, bg7, bg8
+bg1:	.space 4
+bg2:	.space 4
+bg3:	.space 4
+bg4:	.space 4
+bg5:	.space 4
+bg6:	.space 4
+bg7:	.space 4
+bg8:	.space 4
+bl1:	.space 4
+bl2:	.space 4
+bl3:	.space 4
+bl4:	.space 4
+bl5:	.space 4
+bl6:	.space 4
+bl7:	.space 4
+bl8:	.space 4
+	.text
+	.globl	_start
+	.type	_start,@function
+_start:
+	pushl	%ebp
+	movl	%esp, %ebp
+	/* Set up .GOT pointer for non-pic @gottpoff sequences */
+	call	1f
+1:	popl	%ecx
+	addl	$_GLOBAL_OFFSET_TABLE_+[.-1b], %ecx
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against global var  */
+	movl	%gs:0, %edx
+	nop;nop
+	subl	sG6@gottpoff(%ecx), %edx
+	nop;nop;nop;nop
+
+	/* @indntpoff IE against global var  */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	sG7@indntpoff, %eax
+	nop;nop;nop;nop
+
+	/* @indntpoff direct %gs access IE against global var  */
+	movl	sG8@indntpoff, %edx
+	nop;nop
+	movl	%gs:(%edx), %eax
+	nop;nop;nop;nop
+
+	/* @gottpoff IE -> LE against global var defined in exec  */
+	movl	%gs:0, %edx
+	nop;nop
+	subl	bg6@gottpoff(%ecx), %edx
+	nop;nop;nop;nop
+
+	/* @indntpoff IE -> LE against global var defined in exec */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	bg7@indntpoff, %eax
+	nop;nop;nop;nop
+
+	/* @indntpoff direct %gs access IE -> LE against global var defined
+	   in exec  */
+	movl	bg8@indntpoff, %edx
+	nop;nop
+	movl	%gs:(%edx), %eax
+	nop;nop;nop;nop
+
+	/* @gottpoff IE -> LE against local var  */
+	movl	%gs:0, %edx
+	nop;nop
+	subl	bl6@gottpoff(%ecx), %edx
+	nop;nop;nop;nop
+
+	/* @indntpoff IE -> LE against local var  */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	bl7@indntpoff, %eax
+	nop;nop;nop;nop
+
+	/* @indntpoff direct %gs access IE -> LE against local var  */
+	movl	bl8@indntpoff, %edx
+	nop;nop
+	movl	%gs:(%edx), %eax
+	nop;nop;nop;nop
+
+	/* @gottpoff IE -> LE against hidden but not local var  */
+	movl	%gs:0, %edx
+	nop;nop
+	subl	sh6@gottpoff(%ecx), %edx
+	nop;nop;nop;nop
+
+	/* @indntpoff IE -> LE against hidden but not local var  */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	sh7@indntpoff, %eax
+	nop;nop;nop;nop
+
+	/* @indntpoff direct %gs access IE -> LE against hidden but not
+	   local var  */
+	movl	sh8@indntpoff, %edx
+	nop;nop
+	movl	%gs:(%edx), %eax
+	nop;nop;nop;nop
+
+	/* LE @tpoff, global var defined in exec  */
+	movl	$sg1@tpoff, %edx
+	nop;nop
+	movl	%gs:0, %eax
+	nop;nop
+	subl	%edx, %eax
+	nop;nop;nop;nop
+
+	/* LE @tpoff, local var  */
+	movl	$-1+bl1@tpoff, %eax
+	nop;nop
+	movl	%gs:0, %edx
+	nop;nop
+	subl	%eax, %edx
+	nop;nop;nop;nop
+
+	/* LE @tpoff, hidden var defined in exec  */
+	movl	$sh1@tpoff-3, %eax
+	nop;nop
+	movl	%gs:0, %edx
+	nop;nop
+	subl	%eax, %edx
+	nop;nop;nop;nop
+
+	/* LE @ntpoff, global var defined in exec  */
+	movl	%gs:0, %eax
+	nop;nop
+	leal	sg2@ntpoff(%eax), %edx
+	nop;nop;nop;nop
+
+	/* LE @ntpoff, local var, non-canonical sequence  */
+	movl	$2+bl2@ntpoff, %eax
+	nop;nop
+	movl	%gs:0, %edx
+	nop;nop
+	addl	%eax, %edx
+	nop;nop;nop;nop
+
+	/* LE @ntpoff, hidden var defined in exec, non-canonical sequence */
+	movl	%gs:0, %edx
+	nop;nop
+	addl	$sh2@ntpoff+1, %edx
+	nop;nop;nop;nop
+
+	/* Direct %gs access  */
+
+	/* LE @ntpoff, global var defined in exec  */
+	movl	%gs:sg3@ntpoff, %eax
+	nop;nop;nop;nop
+
+	/* LE @ntpoff, local var  */
+	movl	%gs:bl3@ntpoff+3, %edx
+	nop;nop;nop;nop
+
+	/* LE @ntpoff, hidden var defined in exec  */
+	movl	%gs:1+sh3@ntpoff, %edx
+	nop;nop;nop;nop
+
+	movl    -4(%ebp), %ebx
+	leave
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsbin.sd b/binutils-2.19/ld/testsuite/ld-i386/tlsbin.sd
new file mode 100644
index 0000000..2fa7a89
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsbin.sd
@@ -0,0 +1,13 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: --32
+#ld: -melf_i386 tmpdir/libtlslib.so
+#objdump: -sj.got
+#target: i?86-*-*
+
+.*:     file format elf32-i386
+
+Contents of section \.got:
+ 804a100 [0-9a-f]+ 00000000 00000000 [0-9a-f]+  .*
+ 804a110 00000000 00000000 00000000 00000000  .*
+ 804a120 00000000  +.*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsbin.td b/binutils-2.19/ld/testsuite/ld-i386/tlsbin.td
new file mode 100644
index 0000000..bb29455
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsbin.td
@@ -0,0 +1,16 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: --32
+#ld: -melf_i386 tmpdir/libtlslib.so
+#objdump: -sj.tdata
+#target: i?86-*-*
+
+.*:     file format elf32-i386
+
+Contents of section \.tdata:
+ 804a000 11000000 12000000 13000000 14000000  .*
+ 804a010 15000000 16000000 17000000 18000000  .*
+ 804a020 41000000 42000000 43000000 44000000  .*
+ 804a030 45000000 46000000 47000000 48000000  .*
+ 804a040 01010000 02010000 03010000 04010000  .*
+ 804a050 05010000 06010000 07010000 08010000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsbindesc.dd b/binutils-2.19/ld/testsuite/ld-i386/tlsbindesc.dd
new file mode 100644
index 0000000..f77d1c8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsbindesc.dd
@@ -0,0 +1,456 @@
+#source: tlsbindesc.s
+#source: tlsbin.s
+#as: --32
+#ld: -melf_i386 tmpdir/libtlslib.so
+#objdump: -drj.text
+#target: i?86-*-*
+
+# PT_TLS layout is:
+# Offset from	Offset from	Name
+# TCB base	TCB end
+# 0x00		-0xa0		sg1..sg8
+# 0x20		-0x80		sl1..sl8
+# 0x40		-0x60		sh1..sh8
+# 0x60		-0x40		bg1..bg8
+# 0x80		-0x20		bl1..bl8
+
+.*: +file format elf32-i386
+
+Disassembly of section .text:
+
+[0-9a-f]+ <fn2>:
+ [0-9a-f]+:	55[ 	]+push   %ebp
+ [0-9a-f]+:	89 e5[ 	]+mov    %esp,%ebp
+ [0-9a-f]+:	53[ 	]+push   %ebx
+ [0-9a-f]+:	50[ 	]+push   %eax
+ [0-9a-f]+:	e8 00 00 00 00[ 	]+call   [0-9a-f]+ <fn2\+0xa>
+ [0-9a-f]+:	5b[ 	]+pop    %ebx
+ [0-9a-f]+:	81 c3 fa 10 00 00[ 	]+add    \$0x10fa,%ebx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is not defined in executable
+ [0-9a-f]+:	8b 83 f8 ff ff ff[ 	]+mov    -0x8\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sG1
+ [0-9a-f]+:	f7 d8[ 	]+neg    %eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is not defined in executable where
+#  the variable is referenced through @gottpoff too
+ [0-9a-f]+:	8b 83 e8 ff ff ff[ 	]+mov    -0x18\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sG2
+ [0-9a-f]+:	f7 d8[ 	]+neg    %eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is not defined in executable where
+#  the variable is referenced through @gotntpoff too
+ [0-9a-f]+:	8b 83 dc ff ff ff[ 	]+mov    -0x24\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	sG3
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is not defined in executable where
+#  the variable is referenced through @gottpoff and @gotntpoff too
+ [0-9a-f]+:	8b 83 f0 ff ff ff[ 	]+mov    -0x10\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sG4
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> LE with global variable defined in executable
+ [0-9a-f]+:	8d 05 00 f0 ff ff[ 	]+lea    0xfffff000,%eax
+#							sg1
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> LE with local variable defined in executable
+ [0-9a-f]+:	8d 05 20 f0 ff ff[ 	]+lea    0xfffff020,%eax
+#							sl1
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> LE with hidden variable defined in executable
+ [0-9a-f]+:	8d 05 40 f0 ff ff[ 	]+lea    0xfffff040,%eax
+#							sh1
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LD -> LE
+ [0-9a-f]+:	8d 05 00 00 00 00[ 	]+lea    0x0,%eax
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 90 20 f0 ff ff[ 	]+lea    -0xfe0\(%eax\),%edx
+#							sl1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 88 24 f0 ff ff[ 	]+lea    -0xfdc\(%eax\),%ecx
+#							sl2
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LD -> LE against hidden variables
+ [0-9a-f]+:	8d 05 00 00 00 00[ 	]+lea    0x0,%eax
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 90 40 f0 ff ff[ 	]+lea    -0xfc0\(%eax\),%edx
+#							sh1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 88 44 f0 ff ff[ 	]+lea    -0xfbc\(%eax\),%ecx
+#							sh2
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against global var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 8b e8 ff ff ff[ 	]+sub    -0x18\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF32	sG2
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against global var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 83 ec ff ff ff[ 	]+sub    -0x14\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sG4
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against global var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 8b dc ff ff ff[ 	]+add    -0x24\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	sG3
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against global var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 83 f0 ff ff ff[ 	]+add    -0x10\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	sG4
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE -> LE against global var defined in exec
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	81 e9 00 10 00 00[ 	]+sub    \$0x1000,%ecx
+#							sg1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE -> LE against local var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	81 c0 20 f0 ff ff[ 	]+add    \$0xfffff020,%eax
+#							sl1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE -> LE against hidden var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	81 e9 c0 0f 00 00[ 	]+sub    \$0xfc0,%ecx
+#							sh1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  Direct access through %gs
+#  @gotntpoff IE against global var
+ [0-9a-f]+:	8b 8b e0 ff ff ff[ 	]+mov    -0x20\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	sG5
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 11[ 	]+mov    %gs:\(%ecx\),%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE->LE against local var
+ [0-9a-f]+:	c7 c0 30 f0 ff ff[ 	]+mov    \$0xfffff030,%eax
+#							sl5
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 10[ 	]+mov    %gs:\(%eax\),%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE->LE against hidden var
+ [0-9a-f]+:	c7 c2 50 f0 ff ff[ 	]+mov    \$0xfffff050,%edx
+#							sh5
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 12[ 	]+mov    %gs:\(%edx\),%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8b 5d fc[ 	]+mov    -0x4\(%ebp\),%ebx
+ [0-9a-f]+:	c9[ 	]+leave *
+ [0-9a-f]+:	c3[ 	]+ret *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+
+[0-9a-f]+ <_start>:
+ [0-9a-f]+:	55[ 	]+push   %ebp
+ [0-9a-f]+:	89 e5[ 	]+mov    %esp,%ebp
+ [0-9a-f]+:	e8 00 00 00 00[ 	]+call   [0-9a-f]+ <_start\+0x8>
+ [0-9a-f]+:	59[ 	]+pop    %ecx
+ [0-9a-f]+:	81 c1 a4 0f 00 00[ 	]+add    \$0xfa4,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against global var
+ [0-9a-f]+:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 91 f4 ff ff ff[ 	]+sub    -0xc\(%ecx\),%edx
+#				->R_386_TLS_TPOFF32	sG6
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @indntpoff IE against global var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 05 e8 a0 04 08[ 	]+add    0x804a0e8,%eax
+#				->R_386_TLS_TPOFF	sG7
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @indntpoff direct %gs access IE against global var
+ [0-9a-f]+:	8b 15 00 a1 04 08[ 	]+mov    0x804a100,%edx
+#				->R_386_TLS_TPOFF	sG8
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 02[ 	]+mov    %gs:\(%edx\),%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE -> LE against global var defined in exec
+ [0-9a-f]+:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	81 ea 8c 0f 00 00[ 	]+sub    \$0xf8c,%edx
+#							bg6
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @indntpoff IE -> LE against global var defined in exec
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	81 c0 78 f0 ff ff[ 	]+add    \$0xfffff078,%eax
+#							bg7
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @indntpoff direct %gs access IE -> LE against global var defined
+#  in exec
+ [0-9a-f]+:	c7 c2 7c f0 ff ff[ 	]+mov    \$0xfffff07c,%edx
+#							bg8
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 02[ 	]+mov    %gs:\(%edx\),%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE -> LE against local var
+ [0-9a-f]+:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	81 ea 6c 0f 00 00[ 	]+sub    \$0xf6c,%edx
+#							bl6
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @indntpoff IE -> LE against local var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	81 c0 98 f0 ff ff[ 	]+add    \$0xfffff098,%eax
+#							bl7
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @indntpoff direct %gs access IE -> LE against local var
+ [0-9a-f]+:	c7 c2 9c f0 ff ff[ 	]+mov    \$0xfffff09c,%edx
+#							bl8
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 02[ 	]+mov    %gs:\(%edx\),%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE -> LE against hidden but not local var
+ [0-9a-f]+:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	81 ea ac 0f 00 00[ 	]+sub    \$0xfac,%edx
+#							sh6
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @indntpoff IE -> LE against hidden but not local var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	81 c0 58 f0 ff ff[ 	]+add    \$0xfffff058,%eax
+#							sh7
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @indntpoff direct %gs access IE -> LE against hidden but not
+#  local var
+ [0-9a-f]+:	c7 c2 5c f0 ff ff[ 	]+mov    \$0xfffff05c,%edx
+#							sh8
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 02[ 	]+mov    %gs:\(%edx\),%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LE @tpoff, global var defined in exec
+ [0-9a-f]+:	ba 00 10 00 00[ 	]+mov    \$0x1000,%edx
+#							sg1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	29 d0[ 	]+sub    %edx,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LE @tpoff, local var
+ [0-9a-f]+:	b8 7f 0f 00 00[ 	]+mov    \$0xf7f,%eax
+#							bl1+1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	29 c2[ 	]+sub    %eax,%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LE @tpoff, hidden var defined in exec
+ [0-9a-f]+:	b8 bd 0f 00 00[ 	]+mov    \$0xfbd,%eax
+#							sh1+3
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	29 c2[ 	]+sub    %eax,%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LE @ntpoff, global var defined in exec
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 90 04 f0 ff ff[ 	]+lea    -0xffc\(%eax\),%edx
+#							sg2
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LE @ntpoff, local var, non-canonical sequence
+ [0-9a-f]+:	b8 86 f0 ff ff[ 	]+mov    \$0xfffff086,%eax
+#							bl2+2
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	01 c2[ 	]+add    %eax,%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LE @ntpoff, hidden var defined in exec, non-canonical sequence
+ [0-9a-f]+:	65 8b 15 00 00 00 00[ 	]+mov    %gs:0x0,%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	81 c2 45 f0 ff ff[ 	]+add    \$0xfffff045,%edx
+#							sh2+1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LE @ntpoff, global var defined in exec
+ [0-9a-f]+:	65 a1 08 f0 ff ff[ 	]+mov    %gs:0xfffff008,%eax
+#							sg3
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LE @ntpoff, local var
+ [0-9a-f]+:	65 8b 15 8b f0 ff ff[ 	]+mov    %gs:0xfffff08b,%edx
+#							bl3+3
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LE @ntpoff, hidden var defined in exec
+ [0-9a-f]+:	65 8b 15 49 f0 ff ff[ 	]+mov    %gs:0xfffff049,%edx
+#							sh3+1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8b 5d fc[ 	]+mov    -0x4\(%ebp\),%ebx
+ [0-9a-f]+:	c9[ 	]+leave *
+ [0-9a-f]+:	c3[ 	]+ret *
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsbindesc.rd b/binutils-2.19/ld/testsuite/ld-i386/tlsbindesc.rd
new file mode 100644
index 0000000..dd3e65e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsbindesc.rd
@@ -0,0 +1,151 @@
+#source: tlsbindesc.s
+#source: tlsbin.s
+#as: --32
+#ld: -melf_i386 tmpdir/libtlslib.so
+#readelf: -Ssrl
+#target: i?86-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] \.interp +.*
+ +\[[ 0-9]+\] \.hash +.*
+ +\[[ 0-9]+\] \.dynsym +.*
+ +\[[ 0-9]+\] \.dynstr +.*
+ +\[[ 0-9]+\] \.rel.dyn +.*
+ +\[[ 0-9]+\] \.text +PROGBITS +0+8049000 .*
+ +\[[ 0-9]+\] \.tdata +PROGBITS +0+804a000 [0-9a-f]+ 000060 00 WAT  0   0 4096
+ +\[[ 0-9]+\] \.tbss +NOBITS +[0-9a-f]+ [0-9a-f]+ 000040 00 WAT  0   0  1
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC +0+804a060 .*
+ +\[[ 0-9]+\] \.got +PROGBITS +0+804a0e0 .*
+ +\[[ 0-9]+\] \.got\.plt +PROGBITS +0+804a104 .*
+ +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x8049158
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  PHDR.*
+  INTERP.*
+.*Requesting program interpreter.*
+  LOAD.*
+  LOAD.*
+  DYNAMIC.*
+  TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+60 0x0+a0 R +0x1000
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 +
+   01 +.interp *
+   02 +.interp .hash .dynsym .dynstr .rel.dyn .text *
+   03 +.tdata .dynamic .got .got.plt *
+   04 +.dynamic *
+   05 +.tdata .tbss *
+
+Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 9 entries:
+ Offset +Info +Type +Sym.Value +Sym. Name
+0+804a0e0  0000010e R_386_TLS_TPOFF +0+ +sG3
+0+804a0e4  0000020e R_386_TLS_TPOFF +0+ +sG5
+0+804a0e8  0000030e R_386_TLS_TPOFF +0+ +sG7
+0+804a0ec  00000425 R_386_TLS_TPOFF32 0+ +sG2
+0+804a0f0  00000525 R_386_TLS_TPOFF32 0+ +sG4
+0+804a0f4  0000050e R_386_TLS_TPOFF +0+ +sG4
+0+804a0f8  00000725 R_386_TLS_TPOFF32 0+ +sG6
+0+804a0fc  00000825 R_386_TLS_TPOFF32 0+ +sG1
+0+804a100  00000b0e R_386_TLS_TPOFF +0+ +sG8
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value  Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG7
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG2
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG4
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG6
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG1
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG8
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value  Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +1 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +2 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +3 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +4 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +5 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +6 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +7 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +8 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +9 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +10 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +11 *
+ +[0-9]+: 00000020 +0 TLS +LOCAL  DEFAULT +7 sl1
+ +[0-9]+: 00000024 +0 TLS +LOCAL  DEFAULT +7 sl2
+ +[0-9]+: 00000028 +0 TLS +LOCAL  DEFAULT +7 sl3
+ +[0-9]+: 0000002c +0 TLS +LOCAL  DEFAULT +7 sl4
+ +[0-9]+: 00000030 +0 TLS +LOCAL  DEFAULT +7 sl5
+ +[0-9]+: 00000034 +0 TLS +LOCAL  DEFAULT +7 sl6
+ +[0-9]+: 00000038 +0 TLS +LOCAL  DEFAULT +7 sl7
+ +[0-9]+: 0000003c +0 TLS +LOCAL  DEFAULT +7 sl8
+ +[0-9]+: 00000080 +0 TLS +LOCAL  DEFAULT +8 bl1
+ +[0-9]+: 00000084 +0 TLS +LOCAL  DEFAULT +8 bl2
+ +[0-9]+: 00000088 +0 TLS +LOCAL  DEFAULT +8 bl3
+ +[0-9]+: 0000008c +0 TLS +LOCAL  DEFAULT +8 bl4
+ +[0-9]+: 00000090 +0 TLS +LOCAL  DEFAULT +8 bl5
+ +[0-9]+: 00000094 +0 TLS +LOCAL  DEFAULT +8 bl6
+ +[0-9]+: 00000098 +0 TLS +LOCAL  DEFAULT +8 bl7
+ +[0-9]+: 0000009c +0 TLS +LOCAL  DEFAULT +8 bl8
+ +[0-9]+: 00001000 +0 TLS +LOCAL  HIDDEN +7 _TLS_MODULE_BASE_
+ +[0-9]+: 0+804a060 +0 OBJECT  LOCAL  HIDDEN    9 _DYNAMIC
+ +[0-9]+: [0-9a-f]+ +0 OBJECT  LOCAL  HIDDEN   11 _GLOBAL_OFFSET_TABLE_
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG3
+ +[0-9]+: 0000001c +0 TLS +GLOBAL DEFAULT +7 sg8
+ +[0-9]+: 0000007c +0 TLS +GLOBAL DEFAULT +8 bg8
+ +[0-9]+: 00000074 +0 TLS +GLOBAL DEFAULT +8 bg6
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG5
+ +[0-9]+: 00000068 +0 TLS +GLOBAL DEFAULT +8 bg3
+ +[0-9]+: 00000008 +0 TLS +GLOBAL DEFAULT +7 sg3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG7
+ +[0-9]+: 00000048 +0 TLS +GLOBAL HIDDEN +7 sh3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG2
+ +[0-9]+: 0000000c +0 TLS +GLOBAL DEFAULT +7 sg4
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG4
+ +[0-9]+: 00000010 +0 TLS +GLOBAL DEFAULT +7 sg5
+ +[0-9]+: 00000070 +0 TLS +GLOBAL DEFAULT +8 bg5
+ +[0-9]+: 00000058 +0 TLS +GLOBAL HIDDEN +7 sh7
+ +[0-9]+: 0000005c +0 TLS +GLOBAL HIDDEN +7 sh8
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +7 sg1
+ +[0-9]+: 0+8049158 +0 FUNC +GLOBAL DEFAULT +6 _start
+ +[0-9]+: 0000004c +0 TLS +GLOBAL HIDDEN +7 sh4
+ +[0-9]+: 00000078 +0 TLS +GLOBAL DEFAULT +8 bg7
+ +[0-9]+: 00000050 +0 TLS +GLOBAL HIDDEN +7 sh5
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG6
+ +[0-9]+: 0+8049000 +0 FUNC +GLOBAL DEFAULT +6 fn2
+ +[0-9]+: 00000004 +0 TLS +GLOBAL DEFAULT +7 sg2
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG1
+ +[0-9]+: 00000040 +0 TLS +GLOBAL HIDDEN +7 sh1
+ +[0-9]+: 00000014 +0 TLS +GLOBAL DEFAULT +7 sg6
+ +[0-9]+: 00000018 +0 TLS +GLOBAL DEFAULT +7 sg7
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+ +[0-9]+: 00000044 +0 TLS +GLOBAL HIDDEN +7 sh2
+ +[0-9]+: 00000054 +0 TLS +GLOBAL HIDDEN +7 sh6
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG8
+ +[0-9]+: 00000064 +0 TLS +GLOBAL DEFAULT +8 bg2
+ +[0-9]+: 00000060 +0 TLS +GLOBAL DEFAULT +8 bg1
+ +[0-9]+: 0000006c +0 TLS +GLOBAL DEFAULT +8 bg4
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsbindesc.s b/binutils-2.19/ld/testsuite/ld-i386/tlsbindesc.s
new file mode 100644
index 0000000..9094d08
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsbindesc.s
@@ -0,0 +1,167 @@
+	/* Force .got aligned to 4K, so it very likely gets at 0x804a100
+	   (0x60 bytes .tdata and 0xa0 bytes .dynamic)  */
+	.section ".tdata", "awT", @progbits
+	.balign	4096
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+	/* Force .text aligned to 4K, so it very likely gets at 0x8049000.  */
+	.text
+	.balign	4096
+	.globl	fn2
+	.type	fn2,@function
+fn2:
+	pushl	%ebp
+	movl	%esp, %ebp
+	pushl	%ebx
+	pushl	%eax
+	call	1f
+1:	popl	%ebx
+	addl	$_GLOBAL_OFFSET_TABLE_+[.-1b], %ebx
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is not defined in executable */
+	leal	sG1@tlsdesc(%ebx), %eax
+	call	*sG1@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is not defined in executable where
+	   the variable is referenced through @gottpoff too */
+	leal	sG2@tlsdesc(%ebx), %eax
+	call	*sG2@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is not defined in executable where
+	   the variable is referenced through @gotntpoff too */
+	leal	sG3@tlsdesc(%ebx), %eax
+	call	*sG3@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is not defined in executable where
+	   the variable is referenced through @gottpoff and @gotntpoff too */
+	leal	sG4@tlsdesc(%ebx), %eax
+	call	*sG4@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> LE with global variable defined in executable */
+	leal	sg1@tlsdesc(%ebx), %eax
+	call	*sg1@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> LE with local variable defined in executable */
+	leal	sl1@tlsdesc(%ebx), %eax
+	call	*sl1@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> LE with hidden variable defined in executable */
+	leal	sh1@tlsdesc(%ebx), %eax
+	call	*sh1@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* LD -> LE */
+	leal	_TLS_MODULE_BASE_@tlsdesc(%ebx), %eax
+	call	*_TLS_MODULE_BASE_@tlscall(%eax)
+	nop;nop
+	leal	sl1@dtpoff(%eax), %edx
+	nop;nop
+	leal	sl2@dtpoff(%eax), %ecx
+	nop;nop;nop;nop
+
+	/* LD -> LE against hidden variables */
+	leal	_TLS_MODULE_BASE_@tlsdesc(%ebx), %eax
+	call	*_TLS_MODULE_BASE_@tlscall(%eax)
+	nop;nop
+	leal	sh1@dtpoff(%eax), %edx
+	nop;nop
+	leal	sh2@dtpoff(%eax), %ecx
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against global var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sG2@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against global var  */
+	movl	%gs:0, %eax
+	nop;nop
+	subl	sG4@gottpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against global var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	addl	sG3@gotntpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against global var  */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	sG4@gotntpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gottpoff IE -> LE against global var defined in exec */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sg1@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE -> LE against local var */
+	movl	%gs:0, %ecx
+	nop;nop
+	addl	sl1@gotntpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gottpoff IE -> LE against hidden var */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sh1@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* Direct access through %gs  */
+
+	/* @gotntpoff IE against global var  */
+	movl	sG5@gotntpoff(%ebx), %ecx
+	nop;nop
+	movl	%gs:(%ecx), %edx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE->LE against local var  */
+	movl	sl5@gotntpoff(%ebx), %eax
+	nop;nop
+	movl	%gs:(%eax), %edx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE->LE against hidden var  */
+	movl	sh5@gotntpoff(%ebx), %edx
+	nop;nop
+	movl	%gs:(%edx), %edx
+	nop;nop;nop;nop
+
+	movl    -4(%ebp), %ebx
+	leave
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsbindesc.sd b/binutils-2.19/ld/testsuite/ld-i386/tlsbindesc.sd
new file mode 100644
index 0000000..a87f5da
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsbindesc.sd
@@ -0,0 +1,13 @@
+#source: tlsbindesc.s
+#source: tlsbin.s
+#as: --32
+#ld: -melf_i386 tmpdir/libtlslib.so
+#objdump: -sj.got
+#target: i?86-*-*
+
+.*:     file format elf32-i386
+
+Contents of section \.got:
+ 804a0e0 [0-9a-f]+ 00000000 00000000 [0-9a-f]+  .*
+ 804a0f0 00000000 00000000 00000000 00000000  .*
+ 804a100 00000000  +.*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsbindesc.td b/binutils-2.19/ld/testsuite/ld-i386/tlsbindesc.td
new file mode 100644
index 0000000..726df3e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsbindesc.td
@@ -0,0 +1,16 @@
+#source: tlsbindesc.s
+#source: tlsbin.s
+#as: --32
+#ld: -melf_i386 tmpdir/libtlslib.so
+#objdump: -sj.tdata
+#target: i?86-*-*
+
+.*:     file format elf32-i386
+
+Contents of section \.tdata:
+ 804a000 11000000 12000000 13000000 14000000  .*
+ 804a010 15000000 16000000 17000000 18000000  .*
+ 804a020 41000000 42000000 43000000 44000000  .*
+ 804a030 45000000 46000000 47000000 48000000  .*
+ 804a040 01010000 02010000 03010000 04010000  .*
+ 804a050 05010000 06010000 07010000 08010000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsbinpic.s b/binutils-2.19/ld/testsuite/ld-i386/tlsbinpic.s
new file mode 100644
index 0000000..9c8a006
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsbinpic.s
@@ -0,0 +1,172 @@
+	/* Force .got aligned to 4K, so it very likely gets at 0x804a100
+	   (0x60 bytes .tdata and 0xa0 bytes .dynamic)  */
+	.section ".tdata", "awT", @progbits
+	.balign	4096
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+	/* Force .text aligned to 4K, so it very likely gets at 0x8049000.  */
+	.text
+	.balign	4096
+	.globl	fn2
+	.type	fn2,@function
+fn2:
+	pushl	%ebp
+	movl	%esp, %ebp
+	pushl	%ebx
+	pushl	%eax
+	call	1f
+1:	popl	%ebx
+	addl	$_GLOBAL_OFFSET_TABLE_+[.-1b], %ebx
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is not defined in executable */
+	leal	sG1@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is not defined in executable where
+	   the variable is referenced through @gottpoff too */
+	leal	sG2@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is not defined in executable where
+	   the variable is referenced through @gotntpoff too */
+	leal	sG3@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is not defined in executable where
+	   the variable is referenced through @gottpoff and @gotntpoff too */
+	leal	sG4@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> LE with global variable defined in executable */
+	leal	sg1@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> LE with local variable defined in executable */
+	leal	sl1@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> LE with hidden variable defined in executable */
+	leal	sh1@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* LD -> LE */
+	leal	sl1@tlsldm(%ebx), %eax
+	call	___tls_get_addr@PLT
+	nop;nop
+	leal	sl1@dtpoff(%eax), %edx
+	nop;nop
+	leal	sl2@dtpoff(%eax), %ecx
+	nop;nop;nop;nop
+
+	/* LD -> LE against hidden variables */
+	leal	sh1@tlsldm(%ebx), %eax
+	call	___tls_get_addr@PLT
+	nop;nop
+	leal	sh1@dtpoff(%eax), %edx
+	nop;nop
+	leal	sh2@dtpoff(%eax), %ecx
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against global var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sG2@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against global var  */
+	movl	%gs:0, %eax
+	nop;nop
+	subl	sG4@gottpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against global var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	addl	sG3@gotntpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against global var  */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	sG4@gotntpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gottpoff IE -> LE against global var defined in exec */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sg1@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE -> LE against local var */
+	movl	%gs:0, %ecx
+	nop;nop
+	addl	sl1@gotntpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gottpoff IE -> LE against hidden var */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sh1@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* Direct access through %gs  */
+
+	/* @gotntpoff IE against global var  */
+	movl	sG5@gotntpoff(%ebx), %ecx
+	nop;nop
+	movl	%gs:(%ecx), %edx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE->LE against local var  */
+	movl	sl5@gotntpoff(%ebx), %eax
+	nop;nop
+	movl	%gs:(%eax), %edx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE->LE against hidden var  */
+	movl	sh5@gotntpoff(%ebx), %edx
+	nop;nop
+	movl	%gs:(%edx), %edx
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is not defined in executable */
+	leal	sG1@tlsgd(%ebx), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop;nop
+
+	movl    -4(%ebp), %ebx
+	leave
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsdesc.dd b/binutils-2.19/ld/testsuite/ld-i386/tlsdesc.dd
new file mode 100644
index 0000000..bca0090
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsdesc.dd
@@ -0,0 +1,391 @@
+#source: tlsdesc.s
+#source: tlspic2.s
+#as: --32
+#ld: -shared -melf_i386
+#objdump: -drj.text
+#target: i?86-*-*
+
+.*: +file format elf32-i386
+
+Disassembly of section .text:
+
+[0-9a-f]+ <fn1>:
+ [0-9a-f]+:	55[ 	]+push   %ebp
+ [0-9a-f]+:	89 e5[ 	]+mov    %esp,%ebp
+ [0-9a-f]+:	53[ 	]+push   %ebx
+ [0-9a-f]+:	50[ 	]+push   %eax
+ [0-9a-f]+:	e8 00 00 00 00[ 	]+call   [0-9a-f]+ <fn1\+0xa>
+ [0-9a-f]+:	5b[ 	]+pop    %ebx
+ [0-9a-f]+:	81 c3 9a 13 00 00[ 	]+add    \$0x[0-9a-f]+,%ebx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GDesc
+ [0-9a-f]+:	8d 83 24 00 00 00[ 	]+lea    0x24\(%ebx\),%eax
+#				->R_386_TLS_DESC	sg1
+ [0-9a-f]+:	ff 10[ 	]+call   \*\(%eax\)
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is referenced through @gottpoff too
+ [0-9a-f]+:	8b 83 f8 ff ff ff[ 	]+mov    -0x8\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	sg2
+ [0-9a-f]+:	f7 d8[ 	]+neg    %eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is referenced through @gotntpoff too
+ [0-9a-f]+:	8b 83 c4 ff ff ff[ 	]+mov    -0x3c\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sg3
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is referenced through @gottpoff and
+ [0-9a-f]+:	8b 83 d4 ff ff ff[ 	]+mov    -0x2c\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sg4
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD against local variable
+ [0-9a-f]+:	8d 83 0c 00 00 00[ 	]+lea    0xc\(%ebx\),%eax
+#				->R_386_TLS_DESC	sl1
+ [0-9a-f]+:	ff 10[ 	]+call   \*\(%eax\)
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against local variable referenced through @gottpoff too
+ [0-9a-f]+:	8b 83 b0 ff ff ff[ 	]+mov    -0x50\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	sl2
+ [0-9a-f]+:	f7 d8[ 	]+neg    %eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against local variable referenced through @gotntpoff
+ [0-9a-f]+:	8b 83 b4 ff ff ff[ 	]+mov    -0x4c\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sl3
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against local variable referenced through @gottpoff and
+ [0-9a-f]+:	8b 83 bc ff ff ff[ 	]+mov    -0x44\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sl4
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD against hidden and local variable
+ [0-9a-f]+:	8d 83 2c 00 00 00[ 	]+lea    0x2c\(%ebx\),%eax
+#				->R_386_TLS_DESC	sh1
+ [0-9a-f]+:	ff 10[ 	]+call   \*\(%eax\)
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against hidden and local variable referenced through @gottpoff too
+ [0-9a-f]+:	8b 83 fc ff ff ff[ 	]+mov    -0x4\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	sh2
+ [0-9a-f]+:	f7 d8[ 	]+neg    %eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against hidden and local variable referenced through @gotntpoff too
+ [0-9a-f]+:	8b 83 c8 ff ff ff[ 	]+mov    -0x38\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sh3
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against hidden and local variable referenced through @gottpoff and @gotntpoff too
+ [0-9a-f]+:	8b 83 e8 ff ff ff[ 	]+mov    -0x18\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sh4
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD against hidden but not local variable
+ [0-9a-f]+:	8d 83 14 00 00 00[ 	]+lea    0x14\(%ebx\),%eax
+#				->R_386_TLS_DESC	sH1
+ [0-9a-f]+:	ff 10[ 	]+call   \*\(%eax\)
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against hidden but not local variable referenced through
+ [0-9a-f]+:	8b 83 cc ff ff ff[ 	]+mov    -0x34\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	sH2
+ [0-9a-f]+:	f7 d8[ 	]+neg    %eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against hidden but not local variable referenced through
+ [0-9a-f]+:	8b 83 ec ff ff ff[ 	]+mov    -0x14\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sH3
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against hidden but not local variable referenced through
+ [0-9a-f]+:	8b 83 e0 ff ff ff[ 	]+mov    -0x20\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sH4
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LD
+ [0-9a-f]+:	8d 83 1c 00 00 00[ 	]+lea    0x1c\(%ebx\),%eax
+#				->R_386_TLS_DESC	_TLS_MODULE_BASE_
+ [0-9a-f]+:	ff 10[ 	]+call   \*\(%eax\)
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 90 20 00 00 00[ 	]+lea    0x20\(%eax\),%edx
+#							sl1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 88 26 00 00 00[ 	]+lea    0x26\(%eax\),%ecx
+#							sl2+2
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LD against hidden and local variables
+ [0-9a-f]+:	8d 90 40 00 00 00[ 	]+lea    0x40\(%eax\),%edx
+#							sh1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 88 47 00 00 00[ 	]+lea    0x47\(%eax\),%ecx
+#							sh2+3
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LD against hidden but not local variables
+ [0-9a-f]+:	8d 90 60 00 00 00[ 	]+lea    0x60\(%eax\),%edx
+#							sH1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 88 65 00 00 00[ 	]+lea    0x65\(%eax\),%ecx
+#							sH2+1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against global var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 8b f8 ff ff ff[ 	]+sub    -0x8\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF32	sg2
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against global var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 83 d0 ff ff ff[ 	]+sub    -0x30\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sg4
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against global var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 8b c4 ff ff ff[ 	]+add    -0x3c\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	sg3
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against global var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 83 d4 ff ff ff[ 	]+add    -0x2c\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	sg4
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against local var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 8b b0 ff ff ff[ 	]+sub    -0x50\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF32	[0xdcffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against local var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 83 b8 ff ff ff[ 	]+sub    -0x48\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	[0xd4ffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against local var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 8b b4 ff ff ff[ 	]+add    -0x4c\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	[0x28000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against local var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 83 bc ff ff ff[ 	]+add    -0x44\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	[0x2c000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against hidden and local var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 8b fc ff ff ff[ 	]+sub    -0x4\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF32	[0xbcffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against hidden and local var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 83 e4 ff ff ff[ 	]+sub    -0x1c\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	[0xb4ffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against hidden and local var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 8b c8 ff ff ff[ 	]+add    -0x38\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	[0x48000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against hidden and local var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 83 e8 ff ff ff[ 	]+add    -0x18\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	[0x4c000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against hidden but not local var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 8b cc ff ff ff[ 	]+sub    -0x34\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF32	[0x9cffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against hidden but not local var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 83 dc ff ff ff[ 	]+sub    -0x24\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	[0x94ffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against hidden but not local var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 8b ec ff ff ff[ 	]+add    -0x14\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	[0x68000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against hidden but not local var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 83 e0 ff ff ff[ 	]+add    -0x20\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	[0x6c000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  Direct access through %gs
+#  @gotntpoff IE against global var
+ [0-9a-f]+:	8b 8b d8 ff ff ff[ 	]+mov    -0x28\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	sg5
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 11[ 	]+mov    %gs:\(%ecx\),%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against local var
+ [0-9a-f]+:	8b 83 c0 ff ff ff[ 	]+mov    -0x40\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	[0x30000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 10[ 	]+mov    %gs:\(%eax\),%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against hidden and local var
+ [0-9a-f]+:	8b 93 f0 ff ff ff[ 	]+mov    -0x10\(%ebx\),%edx
+#				->R_386_TLS_TPOFF	[0x50000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 12[ 	]+mov    %gs:\(%edx\),%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against hidden but not local var
+ [0-9a-f]+:	8b 8b f4 ff ff ff[ 	]+mov    -0xc\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	[0x70000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 11[ 	]+mov    %gs:\(%ecx\),%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8b 5d fc[ 	]+mov    -0x4\(%ebp\),%ebx
+ [0-9a-f]+:	c9[ 	]+leave *
+ [0-9a-f]+:	c3[ 	]+ret *
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsdesc.rd b/binutils-2.19/ld/testsuite/ld-i386/tlsdesc.rd
new file mode 100644
index 0000000..72c9c09
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsdesc.rd
@@ -0,0 +1,149 @@
+#source: tlsdesc.s
+#source: tlspic2.s
+#as: --32
+#ld: -shared -melf_i386
+#readelf: -Ssrl
+#target: i?86-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] \.hash +.*
+ +\[[ 0-9]+\] \.dynsym +.*
+ +\[[ 0-9]+\] \.dynstr +.*
+ +\[[ 0-9]+\] \.rel.dyn +.*
+ +\[[ 0-9]+\] \.rel.plt +.*
+ +\[[ 0-9]+\] \.text +.*
+ +\[[ 0-9]+\] \.tdata +PROGBITS +[0-9a-f]+ [0-9a-f]+ 000060 00 WAT  0   0  1
+ +\[[ 0-9]+\] \.tbss +NOBITS +[0-9aa-f]+ [0-9a-f]+ 000020 00 WAT  0   0  1
+ +\[[ 0-9]+\] \.dynamic +.*
+ +\[[ 0-9]+\] \.got +.*
+ +\[[ 0-9]+\] \.got.plt +.*
+ +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x[0-9a-f]+
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  LOAD.*
+  LOAD.*
+  DYNAMIC.*
+  TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+60 0x0+80 R +0x1
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 +.hash .dynsym .dynstr .rel.dyn .rel.plt .text *
+   01 +.tdata .dynamic .got .got.plt *
+   02 +.dynamic *
+   03 +.tdata .tbss *
+
+Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 20 entries:
+ Offset +Info +Type +Sym.Value +Sym. Name
+[0-9a-f ]+R_386_TLS_TPOFF32
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF32
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF32
+[0-9a-f ]+R_386_TLS_TPOFF32
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF32
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF32
+[0-9a-f ]+R_386_TLS_TPOFF   0+8   sg3
+[0-9a-f ]+R_386_TLS_TPOFF32 0+c   sg4
+[0-9a-f ]+R_386_TLS_TPOFF   0+c   sg4
+[0-9a-f ]+R_386_TLS_TPOFF   0+10   sg5
+[0-9a-f ]+R_386_TLS_TPOFF32 0+4   sg2
+
+Relocation section '.rel.plt' at offset 0x[0-9a-f]+ contains 5 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name
+[0-9a-f ]+R_386_TLS_DESC * 0+   sg1
+[0-9a-f ]+R_386_TLS_DESC *
+[0-9a-f ]+R_386_TLS_DESC *
+[0-9a-f ]+R_386_TLS_DESC *
+[0-9a-f ]+R_386_TLS_DESC *
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: + Value  Size Type + Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: 0+1c +0 TLS +GLOBAL DEFAULT +7 sg8
+ +[0-9]+: 0+8 +0 TLS +GLOBAL DEFAULT +7 sg3
+ +[0-9]+: 0+c +0 TLS +GLOBAL DEFAULT +7 sg4
+ +[0-9]+: 0+10 +0 TLS +GLOBAL DEFAULT +7 sg5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +7 sg1
+ +[0-9]+: [0-9a-f]+ +0 FUNC +GLOBAL DEFAULT +6 fn1
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+4 +0 TLS +GLOBAL DEFAULT +7 sg2
+ +[0-9]+: 0+14 +0 TLS +GLOBAL DEFAULT +7 sg6
+ +[0-9]+: 0+18 +0 TLS +GLOBAL DEFAULT +7 sg7
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value  Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +1 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +2 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +3 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +4 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +5 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +6 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +7 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +8 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +9 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +10 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +11 *
+ +[0-9]+: 0+20 +0 TLS +LOCAL  DEFAULT +7 sl1
+ +[0-9]+: 0+24 +0 TLS +LOCAL  DEFAULT +7 sl2
+ +[0-9]+: 0+28 +0 TLS +LOCAL  DEFAULT +7 sl3
+ +[0-9]+: 0+2c +0 TLS +LOCAL  DEFAULT +7 sl4
+ +[0-9]+: 0+30 +0 TLS +LOCAL  DEFAULT +7 sl5
+ +[0-9]+: 0+34 +0 TLS +LOCAL  DEFAULT +7 sl6
+ +[0-9]+: 0+38 +0 TLS +LOCAL  DEFAULT +7 sl7
+ +[0-9]+: 0+3c +0 TLS +LOCAL  DEFAULT +7 sl8
+ +[0-9]+: 0+60 +0 TLS +LOCAL  HIDDEN +8 sH1
+ +[0-9]+: 0+ +0 TLS +LOCAL  HIDDEN +7 _TLS_MODULE_BASE_
+ +[0-9]+: [0-9a-f]+ +0 OBJECT  LOCAL  HIDDEN  ABS _DYNAMIC
+ +[0-9]+: 0+48 +0 TLS +LOCAL  HIDDEN +7 sh3
+ +[0-9]+: 0+64 +0 TLS +LOCAL  HIDDEN +8 sH2
+ +[0-9]+: 0+78 +0 TLS +LOCAL  HIDDEN +8 sH7
+ +[0-9]+: 0+58 +0 TLS +LOCAL  HIDDEN +7 sh7
+ +[0-9]+: 0+5c +0 TLS +LOCAL  HIDDEN +7 sh8
+ +[0-9]+: 0+6c +0 TLS +LOCAL  HIDDEN +8 sH4
+ +[0-9]+: 0+4c +0 TLS +LOCAL  HIDDEN +7 sh4
+ +[0-9]+: 0+68 +0 TLS +LOCAL  HIDDEN +8 sH3
+ +[0-9]+: 0+50 +0 TLS +LOCAL  HIDDEN +7 sh5
+ +[0-9]+: 0+70 +0 TLS +LOCAL  HIDDEN +8 sH5
+ +[0-9]+: 0+74 +0 TLS +LOCAL  HIDDEN +8 sH6
+ +[0-9]+: 0+7c +0 TLS +LOCAL  HIDDEN +8 sH8
+ +[0-9]+: 0+40 +0 TLS +LOCAL  HIDDEN +7 sh1
+ +[0-9]+: [0-9a-f]+ +0 OBJECT  LOCAL  HIDDEN  ABS _GLOBAL_OFFSET_TABLE_
+ +[0-9]+: 0+44 +0 TLS +LOCAL  HIDDEN +7 sh2
+ +[0-9]+: 0+54 +0 TLS +LOCAL  HIDDEN +7 sh6
+ +[0-9]+: 0+1c +0 TLS +GLOBAL DEFAULT +7 sg8
+ +[0-9]+: 0+8 +0 TLS +GLOBAL DEFAULT +7 sg3
+ +[0-9]+: 0+c +0 TLS +GLOBAL DEFAULT +7 sg4
+ +[0-9]+: 0+10 +0 TLS +GLOBAL DEFAULT +7 sg5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +7 sg1
+ +[0-9]+: [0-9a-f]+ +0 FUNC +GLOBAL DEFAULT +6 fn1
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+4 +0 TLS +GLOBAL DEFAULT +7 sg2
+ +[0-9]+: 0+14 +0 TLS +GLOBAL DEFAULT +7 sg6
+ +[0-9]+: 0+18 +0 TLS +GLOBAL DEFAULT +7 sg7
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsdesc.s b/binutils-2.19/ld/testsuite/ld-i386/tlsdesc.s
new file mode 100644
index 0000000..8377f64
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsdesc.s
@@ -0,0 +1,276 @@
+	.section ".tdata", "awT", @progbits
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+	.text
+	.globl	fn1
+	.type	fn1,@function
+fn1:
+	pushl	%ebp
+	movl	%esp, %ebp
+	pushl	%ebx
+	pushl	%eax
+	call	1f
+1:	popl	%ebx
+	addl	$_GLOBAL_OFFSET_TABLE_+[.-1b], %ebx
+	nop;nop;nop;nop
+
+	/* GD */
+	leal	sg1@tlsdesc(%ebx), %eax
+	call	*sg1@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is referenced through @gottpoff too */
+	leal	sg2@tlsdesc(%ebx), %eax
+	call	*sg2@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is referenced through @gotntpoff too */
+	leal	sg3@tlsdesc(%ebx), %eax
+	call	*sg3@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is referenced through @gottpoff and
+	   @gotntpoff too */
+	leal	sg4@tlsdesc(%ebx), %eax
+	call	*sg4@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD against local variable */
+	leal	sl1@tlsdesc(%ebx), %eax
+	call	*sl1@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE against local variable referenced through @gottpoff too */
+	leal	sl2@tlsdesc(%ebx), %eax
+	call	*sl2@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE against local variable referenced through @gotntpoff
+	   too */
+	leal	sl3@tlsdesc(%ebx), %eax
+	call	*sl3@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE against local variable referenced through @gottpoff and
+	   @gotntpoff too */
+	leal	sl4@tlsdesc(%ebx), %eax
+	call	*sl4@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD against hidden and local variable */
+	leal	sh1@tlsdesc(%ebx), %eax
+	call	*sh1@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden and local variable referenced through
+	   @gottpoff too */
+	leal	sh2@tlsdesc(%ebx), %eax
+	call	*sh2@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden and local variable referenced through
+	   @gotntpoff too */
+	leal	sh3@tlsdesc(%ebx), %eax
+	call	*sh3@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden and local variable referenced through
+	   @gottpoff and @gotntpoff too */
+	leal	sh4@tlsdesc(%ebx), %eax
+	call	*sh4@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD against hidden but not local variable */
+	leal	sH1@tlsdesc(%ebx), %eax
+	call	*sH1@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden but not local variable referenced through
+	   @gottpoff too */
+	leal	sH2@tlsdesc(%ebx), %eax
+	call	*sH2@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden but not local variable referenced through
+	   @gotntpoff too */
+	leal	sH3@tlsdesc(%ebx), %eax
+	call	*sH3@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden but not local variable referenced through
+	   @gottpoff and @gotntpoff too */
+	leal	sH4@tlsdesc(%ebx), %eax
+	call	*sH4@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* LD */
+	leal	_TLS_MODULE_BASE_@tlsdesc(%ebx), %eax
+	call	*_TLS_MODULE_BASE_@tlscall(%eax)
+	nop;nop
+	leal	sl1@dtpoff(%eax), %edx
+	nop;nop
+	leal	2+sl2@dtpoff(%eax), %ecx
+	nop;nop;nop;nop
+
+	/* LD against hidden and local variables */
+	leal	sh1@dtpoff(%eax), %edx
+	nop;nop
+	leal	sh2@dtpoff+3(%eax), %ecx
+	nop;nop;nop;nop
+
+	/* LD against hidden but not local variables */
+	leal	sH1@dtpoff(%eax), %edx
+	nop;nop
+	leal	sH2@dtpoff+1(%eax), %ecx
+	nop;nop
+
+	/* @gottpoff IE against global var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sg2@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against global var  */
+	movl	%gs:0, %eax
+	nop;nop
+	subl	sg4@gottpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against global var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	addl	sg3@gotntpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against global var  */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	sg4@gotntpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against local var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sl2@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against local var  */
+	movl	%gs:0, %eax
+	nop;nop
+	subl	sl4@gottpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against local var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	addl	sl3@gotntpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against local var  */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	sl4@gotntpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against hidden and local var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sh2@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against hidden and local var  */
+	movl	%gs:0, %eax
+	nop;nop
+	subl	sh4@gottpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against hidden and local var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	addl	sh3@gotntpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against hidden and local var  */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	sh4@gotntpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against hidden but not local var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sH2@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against hidden but not local var  */
+	movl	%gs:0, %eax
+	nop;nop
+	subl	sH4@gottpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against hidden but not local var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	addl	sH3@gotntpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against hidden but not local var  */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	sH4@gotntpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* Direct access through %gs  */
+
+	/* @gotntpoff IE against global var  */
+	movl	sg5@gotntpoff(%ebx), %ecx
+	nop;nop
+	movl	%gs:(%ecx), %edx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against local var  */
+	movl	sl5@gotntpoff(%ebx), %eax
+	nop;nop
+	movl	%gs:(%eax), %edx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against hidden and local var  */
+	movl	sh5@gotntpoff(%ebx), %edx
+	nop;nop
+	movl	%gs:(%edx), %edx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against hidden but not local var  */
+	movl	sH5@gotntpoff(%ebx), %ecx
+	nop;nop
+	movl	%gs:(%ecx), %edx
+	nop;nop;nop;nop
+
+	movl    -4(%ebp), %ebx
+	leave
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsdesc.sd b/binutils-2.19/ld/testsuite/ld-i386/tlsdesc.sd
new file mode 100644
index 0000000..656c409
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsdesc.sd
@@ -0,0 +1,20 @@
+#source: tlsdesc.s
+#source: tlspic2.s
+#as: --32
+#ld: -shared -melf_i386
+#objdump: -s -j.got -j.got.plt
+#target: i?86-*-*
+
+.*:     file format elf32-i386
+
+Contents of section \.got:
+ [0-9a-f]+ dcffffff 28000000 d4ffffff 2c000000  .*
+ [0-9a-f]+ 30000000 00000000 48000000 9cffffff  .*
+ [0-9a-f]+ 00000000 00000000 00000000 94ffffff  .*
+ [0-9a-f]+ 6c000000 b4ffffff 4c000000 68000000  .*
+ [0-9a-f]+ 50000000 70000000 00000000 bcffffff  .*
+Contents of section \.got\.plt:
+ [0-9a-f]+ b0150000 00000000 00000000 00000000  .*
+ [0-9a-f]+ 20000000 00000000 60000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000000  .*
+ [0-9a-f]+ 40000000 +.*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsdesc.td b/binutils-2.19/ld/testsuite/ld-i386/tlsdesc.td
new file mode 100644
index 0000000..f3612b3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsdesc.td
@@ -0,0 +1,16 @@
+#source: tlsdesc.s
+#source: tlspic2.s
+#as: --32
+#ld: -shared -melf_i386
+#objdump: -sj.tdata
+#target: i?86-*-*
+
+.*:     file format elf32-i386
+
+Contents of section \.tdata:
+ [0-9a-f]+ 11000000 12000000 13000000 14000000  .*
+ [0-9a-f]+ 15000000 16000000 17000000 18000000  .*
+ [0-9a-f]+ 41000000 42000000 43000000 44000000  .*
+ [0-9a-f]+ 45000000 46000000 47000000 48000000  .*
+ [0-9a-f]+ 01010000 02010000 03010000 04010000  .*
+ [0-9a-f]+ 05010000 06010000 07010000 08010000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsg.s b/binutils-2.19/ld/testsuite/ld-i386/tlsg.s
new file mode 100644
index 0000000..b8e1a5d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsg.s
@@ -0,0 +1,12 @@
+	.section	.tbss,"awT",@nobits
+	.align 4
+	.skip	24
+	.type	a,@object
+	.size	a,4
+a:
+	.zero	4
+	.text
+	.globl	_start
+_start:
+	.section	.debug_foobar
+	.long	a@dtpoff
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsg.sd b/binutils-2.19/ld/testsuite/ld-i386/tlsg.sd
new file mode 100644
index 0000000..d794762
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsg.sd
@@ -0,0 +1,10 @@
+#source: tlsg.s
+#as: --32
+#ld: -melf_i386
+#objdump: -sj.debug_foobar
+#target: i?86-*-*
+
+.*: +file format elf32-i386
+
+Contents of section .debug_foobar:
+ 0+ 18000000  +.*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsgd1.dd b/binutils-2.19/ld/testsuite/ld-i386/tlsgd1.dd
new file mode 100644
index 0000000..9a33132
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsgd1.dd
@@ -0,0 +1,16 @@
+#source: tlsgd1.s
+#as: --32
+#ld: -melf_i386 tmpdir/tlsgd1
+#objdump: -drw
+#target: i?86-*-linux*
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+[a-f0-9]+ <_start>:
+[ 	]*[a-f0-9]+:	65 a1 00 00 00 00    	mov    %gs:0x0,%eax
+[ 	]*[a-f0-9]+:	81 e8 04 00 00 00    	sub    \$0x4,%eax
+[ 	]*[a-f0-9]+:	65 a1 00 00 00 00    	mov    %gs:0x0,%eax
+[ 	]*[a-f0-9]+:	81 e8 04 00 00 00    	sub    \$0x4,%eax
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsgd1.s b/binutils-2.19/ld/testsuite/ld-i386/tlsgd1.s
new file mode 100644
index 0000000..552ca09
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsgd1.s
@@ -0,0 +1,15 @@
+	.text
+	.globl _start
+_start:
+	leal	foo@TLSGD(,%ebx,1), %eax
+	call	___tls_get_addr
+	leal	foo@TLSGD(%ebx), %eax
+	call	___tls_get_addr
+	nop
+	.globl foo
+	.section	.tdata,"awT",@progbits
+	.align 4
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	100
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsgdesc.dd b/binutils-2.19/ld/testsuite/ld-i386/tlsgdesc.dd
new file mode 100644
index 0000000..25659de
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsgdesc.dd
@@ -0,0 +1,156 @@
+#source: tlsgdesc.s
+#as: --32
+#ld: -shared -melf_i386
+#objdump: -drj.text
+#target: i?86-*-*
+
+.*: +file format elf32-i386
+
+Disassembly of section .text:
+
+[0-9a-f]+ <fc1>:
+ [0-9a-f]+:	55[ 	]+push   %ebp
+ [0-9a-f]+:	89 e5[ 	]+mov    %esp,%ebp
+ [0-9a-f]+:	53[ 	]+push   %ebx
+ [0-9a-f]+:	50[ 	]+push   %eax
+ [0-9a-f]+:	e8 00 00 00 00[ 	]+call   [0-9a-f]+ <.*>
+ [0-9a-f]+:	5b[ 	]+pop    %ebx
+ [0-9a-f]+:	81 c3 be 11 00 00[ 	]+add    \$0x[0-9a-f]+,%ebx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against global var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 8b e0 ff ff ff[ 	]+sub    -0x20\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF32	sG3
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against global var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 8b f0 ff ff ff[ 	]+add    -0x10\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	sG4
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD
+ [0-9a-f]+:	8d 04 1d f8 ff ff ff[ 	]+lea    -0x8\(,%ebx,1\),%eax
+#				->R_386_TLS_DTPMOD32	sG1
+ [0-9a-f]+:	e8 a9 ff ff ff[ 	]+call   [0-9a-f]+ <___tls_get_addr@plt>
+#				->R_386_JUMP_SLOT	___tls_get_addr
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 83 18 00 00 00[ 	]+lea    0x18\(%ebx\),%eax
+#				->R_386_TLS_DESC	sG1
+ [0-9a-f]+:	ff 10[ 	]+call   \*\(%eax\)
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 83 10 00 00 00[ 	]+lea    0x10\(%ebx\),%eax
+#				->R_386_TLS_DESC	sG2
+ [0-9a-f]+:	ff 10[ 	]+call   \*\(%eax\)
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 04 1d e8 ff ff ff[ 	]+lea    -0x18\(,%ebx,1\),%eax
+#				->R_386_TLS_DTPMOD32	sG2
+ [0-9a-f]+:	e8 81 ff ff ff[ 	]+call   [0-9a-f]+ <___tls_get_addr@plt>
+#				->R_386_JUMP_SLOT	___tls_get_addr
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is referenced through @gottpoff too
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	2b 83 e0 ff ff ff[ 	]+sub    -0x20\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sG3
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8b 83 e0 ff ff ff[ 	]+mov    -0x20\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sG3
+ [0-9a-f]+:	f7 d8[ 	]+neg    %eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is referenced through @gotntpoff too
+ [0-9a-f]+:	8b 83 f0 ff ff ff[ 	]+mov    -0x10\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	sG4
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	03 83 f0 ff ff ff[ 	]+add    -0x10\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	sG4
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is referenced through @gotntpoff too
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	03 83 e4 ff ff ff[ 	]+add    -0x1c\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	sG5
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8b 83 e4 ff ff ff[ 	]+mov    -0x1c\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	sG5
+ [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is referenced through @gottpoff too
+ [0-9a-f]+:	8b 83 f4 ff ff ff[ 	]+mov    -0xc\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sG6
+ [0-9a-f]+:	f7 d8[ 	]+neg    %eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	2b 83 f4 ff ff ff[ 	]+sub    -0xc\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sG6
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against global var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 8b e4 ff ff ff[ 	]+add    -0x1c\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	sG5
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against global var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 8b f4 ff ff ff[ 	]+sub    -0xc\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF32	sG6
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8b 5d fc[ 	]+mov    -0x4\(%ebp\),%ebx
+ [0-9a-f]+:	c9[ 	]+leave *
+ [0-9a-f]+:	c3[ 	]+ret *
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsgdesc.rd b/binutils-2.19/ld/testsuite/ld-i386/tlsgdesc.rd
new file mode 100644
index 0000000..d872dca
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsgdesc.rd
@@ -0,0 +1,103 @@
+#source: tlsgdesc.s
+#as: --32
+#ld: -shared -melf_i386
+#readelf: -Ssrl
+#target: i?86-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] \.hash +.*
+ +\[[ 0-9]+\] \.dynsym +.*
+ +\[[ 0-9]+\] \.dynstr +.*
+ +\[[ 0-9]+\] \.rel.dyn +.*
+ +\[[ 0-9]+\] \.rel.plt +.*
+ +\[[ 0-9]+\] \.plt +.*
+ +\[[ 0-9]+\] \.text +.*
+ +\[[ 0-9]+\] \.dynamic +.*
+ +\[[ 0-9]+\] \.got +.*
+ +\[[ 0-9]+\] \.got.plt +.*
+ +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x[0-9a-f]+
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  LOAD.*
+  LOAD.*
+  DYNAMIC.*
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 +.hash .dynsym .dynstr .rel.dyn .rel.plt .plt .text *
+   01 +.dynamic .got .got.plt *
+   02 +.dynamic *
+
+Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 8 entries:
+ Offset +Info +Type +Sym.Value +Sym. Name
+[0-9a-f ]+R_386_TLS_TPOFF32 0+   sG3
+[0-9a-f ]+R_386_TLS_TPOFF   0+   sG5
+[0-9a-f ]+R_386_TLS_DTPMOD3 0+   sG2
+[0-9a-f ]+R_386_TLS_DTPOFF3 0+   sG2
+[0-9a-f ]+R_386_TLS_TPOFF   0+   sG4
+[0-9a-f ]+R_386_TLS_TPOFF32 0+   sG6
+[0-9a-f ]+R_386_TLS_DTPMOD3 0+   sG1
+[0-9a-f ]+R_386_TLS_DTPOFF3 0+   sG1
+
+Relocation section '.rel.plt' at offset 0x[0-9a-f]+ contains 3 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name
+[0-9a-f ]+R_386_JUMP_SLOT   0+   ___tls_get_addr
+[0-9a-f ]+R_386_TLS_DESC    0+   sG1
+[0-9a-f ]+R_386_TLS_DESC    0+   sG2
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: + Value  Size Type + Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG2
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG4
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG6
+ +[0-9]+: [0-9a-f]+ +0 FUNC +GLOBAL DEFAULT +7 fc1
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG1
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+ +[0-9]+: 0+ +0 NOTYPE  GLOBAL DEFAULT  UND ___tls_get_addr
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value  Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +1 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +2 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +3 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +4 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +5 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +6 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +7 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +8 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +9 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +10 *
+ +[0-9]+: [0-9a-f]+ +0 OBJECT  LOCAL  HIDDEN  ABS _DYNAMIC
+ +[0-9]+: [0-9a-f]+ +0 OBJECT  LOCAL  HIDDEN  ABS _GLOBAL_OFFSET_TABLE_
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG2
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG4
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG6
+ +[0-9]+: [0-9a-f]+ +0 FUNC +GLOBAL DEFAULT +7 fc1
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG1
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+ +[0-9]+: 0+ +0 NOTYPE  GLOBAL DEFAULT  UND ___tls_get_addr
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsgdesc.s b/binutils-2.19/ld/testsuite/ld-i386/tlsgdesc.s
new file mode 100644
index 0000000..9502a10
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsgdesc.s
@@ -0,0 +1,100 @@
+	.text
+	.globl	fc1
+	.type	fc1,@function
+fc1:
+	pushl	%ebp
+	movl	%esp, %ebp
+	pushl	%ebx
+	pushl	%eax
+	call	1f
+1:	popl	%ebx
+	addl	$_GLOBAL_OFFSET_TABLE_+[.-1b], %ebx
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against global var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sG3@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against global var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	addl	sG4@gotntpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* GD */
+	leal	sG1@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD */
+	leal	sG1@tlsdesc(%ebx), %eax
+	call	*sG1@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD */
+	leal	sG2@tlsdesc(%ebx), %eax
+	call	*sG2@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD */
+	leal	sG2@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE tpoff */
+	leal	sG3@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE tpoff */
+	leal	sG3@tlsdesc(%ebx), %eax
+	call	*sG3@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE ntpoff */
+	leal	sG4@tlsdesc(%ebx), %eax
+	call	*sG4@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE ntpoff */
+	leal	sG4@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE ntpoff */
+	leal	sG5@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE ntpoff */
+	leal	sG5@tlsdesc(%ebx), %eax
+	call	*sG5@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE tpoff */
+	leal	sG6@tlsdesc(%ebx), %eax
+	call	*sG6@tlscall(%eax)
+	nop;nop;nop;nop
+
+	/* GD -> IE tpoff */
+	leal	sG6@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against global var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	addl	sG5@gotntpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against global var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sG6@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	movl    -4(%ebp), %ebx
+	leave
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsie1.dd b/binutils-2.19/ld/testsuite/ld-i386/tlsie1.dd
new file mode 100644
index 0000000..2cebc70
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsie1.dd
@@ -0,0 +1,18 @@
+#source: tlsie1.s
+#as: --32
+#ld: -melf_i386 tmpdir/tlsld1
+#objdump: -drw
+#target: i?86-*-linux*
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+[a-f0-9]+ <_start>:
+[ 	]*[a-f0-9]+:	81 c1 fc ff ff ff    	add    \$0xfffffffc,%ecx
+[ 	]*[a-f0-9]+:	81 c1 fc ff ff ff    	add    \$0xfffffffc,%ecx
+[ 	]*[a-f0-9]+:	c7 c0 fc ff ff ff    	mov    \$0xfffffffc,%eax
+[ 	]*[a-f0-9]+:	c7 c1 fc ff ff ff    	mov    \$0xfffffffc,%ecx
+[ 	]*[a-f0-9]+:	b8 fc ff ff ff       	mov    \$0xfffffffc,%eax
+[ 	]*[a-f0-9]+:	c7 c1 fc ff ff ff    	mov    \$0xfffffffc,%ecx
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsie1.s b/binutils-2.19/ld/testsuite/ld-i386/tlsie1.s
new file mode 100644
index 0000000..d4ad569
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsie1.s
@@ -0,0 +1,16 @@
+	.text
+	.globl _start
+_start:
+	addl	foo@gotntpoff(%ebx), %ecx
+	addl	foo@indntpoff, %ecx
+	movl	foo@gotntpoff(%ebx), %eax
+	movl	foo@gotntpoff(%ebx), %ecx
+	movl	foo@indntpoff, %eax
+	movl	foo@indntpoff, %ecx
+	.globl foo
+	.section	.tdata,"awT",@progbits
+	.align 4
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	100
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsie2.d b/binutils-2.19/ld/testsuite/ld-i386/tlsie2.d
new file mode 100644
index 0000000..ebb85fd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsie2.d
@@ -0,0 +1,4 @@
+#name: TLS IE->LE transition check (R_386_TLS_GOTIE with %eax)
+#as: --32
+#ld: -melf_i386
+#error: .*TLS transition from R_386_TLS_GOTIE to R_386_TLS_LE_32 against `foo'.*failed.*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsie2.s b/binutils-2.19/ld/testsuite/ld-i386/tlsie2.s
new file mode 100644
index 0000000..72df617
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsie2.s
@@ -0,0 +1,12 @@
+	.text
+	.globl _start
+_start:
+	leal	foo@gotntpoff(%ebx), %eax
+	movl	(%eax), %eax
+	.globl foo
+	.section	.tdata,"awT",@progbits
+	.align 4
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	100
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsie3.d b/binutils-2.19/ld/testsuite/ld-i386/tlsie3.d
new file mode 100644
index 0000000..d993f30
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsie3.d
@@ -0,0 +1,4 @@
+#name: TLS IE->LE transition check (R_386_TLS_GOTIE)
+#as: --32
+#ld: -melf_i386
+#error: .*TLS transition from R_386_TLS_GOTIE to R_386_TLS_LE_32 against `foo'.*failed.*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsie3.s b/binutils-2.19/ld/testsuite/ld-i386/tlsie3.s
new file mode 100644
index 0000000..865156d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsie3.s
@@ -0,0 +1,12 @@
+	.text
+	.globl _start
+_start:
+	leal	foo@gotntpoff(%ebx), %ecx
+	movl	(%ecx), %ecx
+	.globl foo
+	.section	.tdata,"awT",@progbits
+	.align 4
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	100
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsie4.d b/binutils-2.19/ld/testsuite/ld-i386/tlsie4.d
new file mode 100644
index 0000000..3ca8fdd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsie4.d
@@ -0,0 +1,4 @@
+#name: TLS IE->LE transition check (R_386_TLS_IE with %eax)
+#as: --32
+#ld: -melf_i386
+#error: .*TLS transition from R_386_TLS_IE to R_386_TLS_LE_32 against `foo'.*failed.*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsie4.s b/binutils-2.19/ld/testsuite/ld-i386/tlsie4.s
new file mode 100644
index 0000000..3469f29
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsie4.s
@@ -0,0 +1,12 @@
+	.text
+	.globl _start
+_start:
+	leal	foo@indntpoff(%ebx), %eax
+	movl	(%eax), %eax
+	.globl foo
+	.section	.tdata,"awT",@progbits
+	.align 4
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	100
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsie5.d b/binutils-2.19/ld/testsuite/ld-i386/tlsie5.d
new file mode 100644
index 0000000..3febeb1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsie5.d
@@ -0,0 +1,4 @@
+#name: TLS IE->LE transition check (R_386_TLS_IE)
+#as: --32
+#ld: -melf_i386
+#error: .*TLS transition from R_386_TLS_IE to R_386_TLS_LE_32 against `foo'.*failed.*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsie5.s b/binutils-2.19/ld/testsuite/ld-i386/tlsie5.s
new file mode 100644
index 0000000..affee31
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsie5.s
@@ -0,0 +1,12 @@
+	.text
+	.globl _start
+_start:
+	leal	foo@indntpoff, %ecx
+	movl	(%ecx), %ecx
+	.globl foo
+	.section	.tdata,"awT",@progbits
+	.align 4
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	100
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsindntpoff.dd b/binutils-2.19/ld/testsuite/ld-i386/tlsindntpoff.dd
new file mode 100644
index 0000000..db20de1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsindntpoff.dd
@@ -0,0 +1,16 @@
+#source: tlsindntpoff.s
+#as: --32
+#ld: -melf_i386
+#objdump: -drj.text
+#target: i?86-*-*
+
+.*: +file format elf32-i386
+
+Disassembly of section .text:
+
+[0-9a-f]+000 <_start>:
+ [0-9a-f]+000:	39 d8[ 	]+cmp    %ebx,%eax
+ [0-9a-f]+002:	73 08[ 	]+jae    [0-9a-f]+00c <_start\+0xc>
+ [0-9a-f]+004:	b8 fc ff ff ff[ 	]+mov    \$0xfffffffc,%eax
+ [0-9a-f]+009:	65 8b 00[ 	]+mov    %gs:\(%eax\),%eax
+ [0-9a-f]+00c:	c3[ 	]+ret *
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsindntpoff.s b/binutils-2.19/ld/testsuite/ld-i386/tlsindntpoff.s
new file mode 100644
index 0000000..4bc93f6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsindntpoff.s
@@ -0,0 +1,19 @@
+	/* Force .got aligned to 4K, so it very likely gets at 0x804a100
+	   (0x60 bytes .tdata and 0xa0 bytes .dynamic)  */
+	.data
+	.balign	4096
+	.section ".tdata", "awT", @progbits
+	.globl foo
+foo:	.long 27
+
+	/* Force .text aligned to 4K, so it very likely gets at 0x8049000.  */
+	.text
+	.balign	4096
+	.globl	_start
+	.type	_start,@function
+_start:
+	cmp	%ebx, %eax
+	jae	1f
+	movl	foo@indntpoff, %eax
+	movl	%gs:(%eax), %eax
+1:	ret
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsld1.dd b/binutils-2.19/ld/testsuite/ld-i386/tlsld1.dd
new file mode 100644
index 0000000..2ad49ff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsld1.dd
@@ -0,0 +1,15 @@
+#source: tlsld1.s
+#as: --32
+#ld: -melf_i386 tmpdir/tlsld1
+#objdump: -drw
+#target: i?86-*-linux*
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+[a-f0-9]+ <_start>:
+[ 	]*[a-f0-9]+:	65 a1 00 00 00 00    	mov    %gs:0x0,%eax
+[ 	]*[a-f0-9]+:	90                   	nop    
+[ 	]*[a-f0-9]+:	8d 74 26 00          	lea    0x0\(%esi,%eiz,1\),%esi
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsld1.s b/binutils-2.19/ld/testsuite/ld-i386/tlsld1.s
new file mode 100644
index 0000000..5d57e35
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsld1.s
@@ -0,0 +1,12 @@
+	.text
+	.globl _start
+_start:
+	leal	foo@TLSLDM(%ebx), %eax
+	call	___tls_get_addr
+	.globl foo
+	.section	.tdata,"awT",@progbits
+	.align 4
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	100
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlslib.s b/binutils-2.19/ld/testsuite/ld-i386/tlslib.s
new file mode 100644
index 0000000..22e1f8d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlslib.s
@@ -0,0 +1,17 @@
+	.section ".tdata", "awT", @progbits
+	.globl sG1, sG2, sG3, sG4, sG5, sG6, sG7, sG8
+sG1:	.long 513
+sG2:	.long 514
+sG3:	.long 515
+sG4:	.long 516
+sG5:	.long 517
+sG6:	.long 518
+sG7:	.long 519
+sG8:	.long 520
+
+	.text
+	/* Dummy.  */
+	.globl ___tls_get_addr
+	.type   ___tls_get_addr,@function
+___tls_get_addr:
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsnopic.dd b/binutils-2.19/ld/testsuite/ld-i386/tlsnopic.dd
new file mode 100644
index 0000000..a0a8853
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsnopic.dd
@@ -0,0 +1,161 @@
+#source: tlsnopic1.s
+#source: tlsnopic2.s
+#as: --32
+#ld: -shared -melf_i386
+#objdump: -drj.text
+#target: i?86-*-*
+
+.*: +file format elf32-i386
+
+Disassembly of section .text:
+
+0+1000 <fn3>:
+    1000:	55[ 	]+push   %ebp
+    1001:	89 e5[ 	]+mov    %esp,%ebp
+#  @indntpoff IE against global var
+    1003:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+    1009:	90[ 	]+nop *
+    100a:	90[ 	]+nop *
+    100b:	03 05 7c 21 00 00[ 	]+add    0x217c,%eax
+#				->R_386_TLS_TPOFF	sg1
+    1011:	90[ 	]+nop *
+    1012:	90[ 	]+nop *
+    1013:	90[ 	]+nop *
+    1014:	90[ 	]+nop *
+#  @indntpoff direct %gs access IE against global var
+    1015:	8b 15 80 21 00 00[ 	]+mov    0x2180,%edx
+#				->R_386_TLS_TPOFF	sg2
+    101b:	90[ 	]+nop *
+    101c:	90[ 	]+nop *
+    101d:	65 8b 02[ 	]+mov    %gs:\(%edx\),%eax
+    1020:	90[ 	]+nop *
+    1021:	90[ 	]+nop *
+    1022:	90[ 	]+nop *
+    1023:	90[ 	]+nop *
+#  @indntpoff IE against hidden var
+    1024:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+    102a:	90[ 	]+nop *
+    102b:	90[ 	]+nop *
+    102c:	03 05 84 21 00 00[ 	]+add    0x2184,%eax
+#				->R_386_TLS_TPOFF	[0x14000000]
+    1032:	90[ 	]+nop *
+    1033:	90[ 	]+nop *
+    1034:	90[ 	]+nop *
+    1035:	90[ 	]+nop *
+#  @indntpoff direct %gs access IE against hidden var
+    1036:	8b 15 88 21 00 00[ 	]+mov    0x2188,%edx
+#				->R_386_TLS_TPOFF	[0x18000000]
+    103c:	90[ 	]+nop *
+    103d:	90[ 	]+nop *
+    103e:	65 8b 02[ 	]+mov    %gs:\(%edx\),%eax
+    1041:	90[ 	]+nop *
+    1042:	90[ 	]+nop *
+    1043:	90[ 	]+nop *
+    1044:	90[ 	]+nop *
+#  @indntpoff IE against local var
+    1045:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+    104b:	90[ 	]+nop *
+    104c:	90[ 	]+nop *
+    104d:	03 05 74 21 00 00[ 	]+add    0x2174,%eax
+#				->R_386_TLS_TPOFF	[0x00000000]
+    1053:	90[ 	]+nop *
+    1054:	90[ 	]+nop *
+    1055:	90[ 	]+nop *
+    1056:	90[ 	]+nop *
+#  @indntpoff direct %gs access IE against local var
+    1057:	8b 15 78 21 00 00[ 	]+mov    0x2178,%edx
+#				->R_386_TLS_TPOFF	[0x04000000]
+    105d:	90[ 	]+nop *
+    105e:	90[ 	]+nop *
+    105f:	65 8b 02[ 	]+mov    %gs:\(%edx\),%eax
+    1062:	90[ 	]+nop *
+    1063:	90[ 	]+nop *
+    1064:	90[ 	]+nop *
+    1065:	90[ 	]+nop *
+#  LE @tpoff, global var
+    1066:	ba fd ff ff ff[ 	]+mov    \$0xfffffffd,%edx
+#				R_386_TLS_TPOFF32	sg3
+    106b:	90[ 	]+nop *
+    106c:	90[ 	]+nop *
+    106d:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+    1073:	90[ 	]+nop *
+    1074:	90[ 	]+nop *
+    1075:	29 d0[ 	]+sub    %edx,%eax
+    1077:	90[ 	]+nop *
+    1078:	90[ 	]+nop *
+    1079:	90[ 	]+nop *
+    107a:	90[ 	]+nop *
+#  LE @tpoff, local var
+    107b:	b8 f7 ff ff ff[ 	]+mov    \$0xfffffff7,%eax
+#				R_386_TLS_TPOFF32
+    1080:	90[ 	]+nop *
+    1081:	90[ 	]+nop *
+    1082:	65 8b 15 00 00 00 00 	mov    %gs:0x0,%edx
+    1089:	90[ 	]+nop *
+    108a:	90[ 	]+nop *
+    108b:	29 c2[ 	]+sub    %eax,%edx
+    108d:	90[ 	]+nop *
+    108e:	90[ 	]+nop *
+    108f:	90[ 	]+nop *
+    1090:	90[ 	]+nop *
+#  LE @ntpoff, global var
+    1091:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+    1097:	90[ 	]+nop *
+    1098:	90[ 	]+nop *
+    1099:	8d 90 02 00 00 00[ 	]+lea    0x2\(%eax\),%edx
+#				R_386_TLS_TPOFF		sg4
+    109f:	90[ 	]+nop *
+    10a0:	90[ 	]+nop *
+    10a1:	90[ 	]+nop *
+    10a2:	90[ 	]+nop *
+#  LE @ntpoff, hidden var, non-canonical sequence
+    10a3:	b8 1c 00 00 00[ 	]+mov    \$0x1c,%eax
+#				R_386_TLS_TPOFF
+    10a8:	90[ 	]+nop *
+    10a9:	90[ 	]+nop *
+    10aa:	65 8b 15 00 00 00 00 	mov    %gs:0x0,%edx
+    10b1:	90[ 	]+nop *
+    10b2:	90[ 	]+nop *
+    10b3:	01 c2[ 	]+add    %eax,%edx
+    10b5:	90[ 	]+nop *
+    10b6:	90[ 	]+nop *
+    10b7:	90[ 	]+nop *
+    10b8:	90[ 	]+nop *
+#  LE @ntpoff, local var, non-canonical sequence
+    10b9:	65 8b 15 00 00 00 00 	mov    %gs:0x0,%edx
+    10c0:	90[ 	]+nop *
+    10c1:	90[ 	]+nop *
+    10c2:	81 c2 0d 00 00 00[ 	]+add    \$0xd,%edx
+#				R_386_TLS_TPOFF
+    10c8:	90[ 	]+nop *
+    10c9:	90[ 	]+nop *
+    10ca:	90[ 	]+nop *
+    10cb:	90[ 	]+nop *
+#  Direct %gs access
+#  LE @ntpoff, global var
+    10cc:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+#				R_386_TLS_TPOFF		sg5
+    10d2:	90[ 	]+nop *
+    10d3:	90[ 	]+nop *
+    10d4:	90[ 	]+nop *
+    10d5:	90[ 	]+nop *
+#  LE @ntpoff, local var
+    10d6:	65 8b 15 13 00 00 00 	mov    %gs:0x13,%edx
+#				R_386_TLS_TPOFF
+    10dd:	90[ 	]+nop *
+    10de:	90[ 	]+nop *
+    10df:	90[ 	]+nop *
+    10e0:	90[ 	]+nop *
+#  LE @ntpoff, hidden var
+    10e1:	65 8b 15 21 00 00 00 	mov    %gs:0x21,%edx
+#				R_386_TLS_TPOFF
+    10e8:	90[ 	]+nop *
+    10e9:	90[ 	]+nop *
+    10ea:	90[ 	]+nop *
+    10eb:	90[ 	]+nop *
+    10ec:	8b 5d fc[ 	]+mov    -0x4\(%ebp\),%ebx
+    10ef:	c9[ 	]+leave *
+    10f0:	c3[ 	]+ret *
+    10f1:	90[ 	]+nop *
+    10f2:	90[ 	]+nop *
+    10f3:	90[ 	]+nop *
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsnopic.rd b/binutils-2.19/ld/testsuite/ld-i386/tlsnopic.rd
new file mode 100644
index 0000000..b67d02a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsnopic.rd
@@ -0,0 +1,116 @@
+#source: tlsnopic1.s
+#source: tlsnopic2.s
+#as: --32
+#ld: -shared -melf_i386
+#readelf: -Ssrl
+#target: i?86-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] \.hash +.*
+ +\[[ 0-9]+\] \.dynsym +.*
+ +\[[ 0-9]+\] \.dynstr +.*
+ +\[[ 0-9]+\] \.rel.dyn +.*
+ +\[[ 0-9]+\] \.text +PROGBITS +0+1000 .*
+ +\[[ 0-9]+\] \.tbss +NOBITS +[0-9a-f]+ [0-9a-f]+ 000024 00 WAT  0   0  1
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC +0+20f4 .*
+ +\[[ 0-9]+\] \.got +PROGBITS +0+2174 .*
+ +\[[ 0-9]+\] \.got.plt +PROGBITS +0+218c .*
+ +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x1000
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  LOAD.*
+  LOAD.*
+  DYNAMIC.*
+  TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+ 0x0+24 R +0x1
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 +.hash .dynsym .dynstr .rel.dyn .text *
+   01 +.dynamic .got .got.plt *
+   02 +.dynamic *
+   03 +.tbss *
+
+Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 20 entries:
+ Offset +Info +Type +Sym.Value +Sym. Name
+[0-9a-f ]+R_386_RELATIVE +
+[0-9a-f ]+R_386_RELATIVE +
+[0-9a-f ]+R_386_RELATIVE +
+[0-9a-f ]+R_386_RELATIVE +
+[0-9a-f ]+R_386_RELATIVE +
+[0-9a-f ]+R_386_RELATIVE +
+[0-9a-f ]+R_386_TLS_TPOFF32 0+   sg3
+[0-9a-f ]+R_386_TLS_TPOFF32
+[0-9a-f ]+R_386_TLS_TPOFF +
+[0-9a-f ]+R_386_TLS_TPOFF +
+[0-9a-f ]+R_386_TLS_TPOFF +
+[0-9a-f ]+R_386_TLS_TPOFF +
+[0-9a-f ]+R_386_TLS_TPOFF +
+[0-9a-f ]+R_386_TLS_TPOFF +
+[0-9a-f ]+R_386_TLS_TPOFF +
+[0-9a-f ]+R_386_TLS_TPOFF +
+[0-9a-f ]+R_386_TLS_TPOFF   0+   sg4
+[0-9a-f ]+R_386_TLS_TPOFF   0+   sg5
+[0-9a-f ]+R_386_TLS_TPOFF   0+   sg1
+[0-9a-f ]+R_386_TLS_TPOFF   0+   sg2
+
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value  Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sg3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sg4
+ +[0-9]+: 0+1000 +0 FUNC +GLOBAL DEFAULT +5 fn3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sg5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sg1
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sg2
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value  Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +1 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +2 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +3 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +4 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +5 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +6 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +7 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +8 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +9 *
+ +[0-9]+: 0+00 +0 TLS +LOCAL  DEFAULT +6 bl1
+ +[0-9]+: 0+04 +0 TLS +LOCAL  DEFAULT +6 bl2
+ +[0-9]+: 0+08 +0 TLS +LOCAL  DEFAULT +6 bl3
+ +[0-9]+: 0+0c +0 TLS +LOCAL  DEFAULT +6 bl4
+ +[0-9]+: 0+10 +0 TLS +LOCAL  DEFAULT +6 bl5
+ +[0-9]+: [0-9a-f]+ +0 OBJECT  LOCAL  HIDDEN  ABS _DYNAMIC
+ +[0-9]+: 0+1c +0 TLS +LOCAL  HIDDEN +6 sh3
+ +[0-9]+: 0+20 +0 TLS +LOCAL  HIDDEN +6 sh4
+ +[0-9]+: 0+14 +0 TLS +LOCAL  HIDDEN +6 sh1
+ +[0-9]+: 0+218c +0 OBJECT  LOCAL  HIDDEN  ABS _GLOBAL_OFFSET_TABLE_
+ +[0-9]+: 0+18 +0 TLS +LOCAL  HIDDEN +6 sh2
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sg3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sg4
+ +[0-9]+: 0+1000 +0 FUNC +GLOBAL DEFAULT +5 fn3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sg5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sg1
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sg2
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsnopic.sd b/binutils-2.19/ld/testsuite/ld-i386/tlsnopic.sd
new file mode 100644
index 0000000..fdfaacf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsnopic.sd
@@ -0,0 +1,12 @@
+#source: tlsnopic1.s
+#source: tlsnopic2.s
+#as: --32
+#ld: -shared -melf_i386
+#objdump: -sj.got
+#target: i?86-*-*
+
+.*:     file format elf32-i386
+
+Contents of section \.got:
+ 2174 00000000 04000000 00000000 00000000  .*
+ 2184 14000000 18000000  +.*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsnopic1.s b/binutils-2.19/ld/testsuite/ld-i386/tlsnopic1.s
new file mode 100644
index 0000000..80a28bf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsnopic1.s
@@ -0,0 +1,107 @@
+	.section ".data.rel.ro", "aw", @progbits
+	/* Align, so that .got is likely at address 0x2080.  */
+	.balign	4096
+	.section ".tbss", "awT", @nobits
+bl1:	.space 4
+bl2:	.space 4
+bl3:	.space 4
+bl4:	.space 4
+bl5:	.space 4
+	.text
+	/* Align, so that fn3 is likely at address 0x1000.  */
+	.balign	4096
+	.globl	fn3
+	.type	fn3,@function
+fn3:
+	pushl	%ebp
+	movl	%esp, %ebp
+
+	/* @indntpoff IE against global var  */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	sg1@indntpoff, %eax
+	nop;nop;nop;nop
+
+	/* @indntpoff direct %gs access IE against global var  */
+	movl	sg2@indntpoff, %edx
+	nop;nop
+	movl	%gs:(%edx), %eax
+	nop;nop;nop;nop
+
+	/* @indntpoff IE against hidden var */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	sh1@indntpoff, %eax
+	nop;nop;nop;nop
+
+	/* @indntpoff direct %gs access IE against hidden var */
+	movl	sh2@indntpoff, %edx
+	nop;nop
+	movl	%gs:(%edx), %eax
+	nop;nop;nop;nop
+
+	/* @indntpoff IE against local var  */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	bl1@indntpoff, %eax
+	nop;nop;nop;nop
+
+	/* @indntpoff direct %gs access IE against local var  */
+	movl	bl2@indntpoff, %edx
+	nop;nop
+	movl	%gs:(%edx), %eax
+	nop;nop;nop;nop
+
+	/* LE @tpoff, global var  */
+	movl	$-3+sg3@tpoff, %edx
+	nop;nop
+	movl	%gs:0, %eax
+	nop;nop
+	subl	%edx, %eax
+	nop;nop;nop;nop
+
+	/* LE @tpoff, local var  */
+	movl	$-1+bl3@tpoff, %eax
+	nop;nop
+	movl	%gs:0, %edx
+	nop;nop
+	subl	%eax, %edx
+	nop;nop;nop;nop
+
+	/* LE @ntpoff, global var  */
+	movl	%gs:0, %eax
+	nop;nop
+	leal	2+sg4@ntpoff(%eax), %edx
+	nop;nop;nop;nop
+
+	/* LE @ntpoff, hidden var, non-canonical sequence  */
+	movl	$sh3@ntpoff, %eax
+	nop;nop
+	movl	%gs:0, %edx
+	nop;nop
+	addl	%eax, %edx
+	nop;nop;nop;nop
+
+	/* LE @ntpoff, local var, non-canonical sequence */
+	movl	%gs:0, %edx
+	nop;nop
+	addl	$bl4@ntpoff+1, %edx
+	nop;nop;nop;nop
+
+	/* Direct %gs access  */
+
+	/* LE @ntpoff, global var  */
+	movl	%gs:sg5@ntpoff, %eax
+	nop;nop;nop;nop
+
+	/* LE @ntpoff, local var  */
+	movl	%gs:bl5@ntpoff+3, %edx
+	nop;nop;nop;nop
+
+	/* LE @ntpoff, hidden var  */
+	movl	%gs:1+sh4@ntpoff, %edx
+	nop;nop;nop;nop
+
+	movl    -4(%ebp), %ebx
+	leave
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlsnopic2.s b/binutils-2.19/ld/testsuite/ld-i386/tlsnopic2.s
new file mode 100644
index 0000000..d932956
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlsnopic2.s
@@ -0,0 +1,7 @@
+	.section ".tbss", "awT", @nobits
+	.globl sh1, sh2, sh3, sh4
+	.hidden sh1, sh2, sh3, sh4
+sh1:	.space 4
+sh2:	.space 4
+sh3:	.space 4
+sh4:	.space 4
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlspic.dd b/binutils-2.19/ld/testsuite/ld-i386/tlspic.dd
new file mode 100644
index 0000000..dd436d2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlspic.dd
@@ -0,0 +1,411 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: --32
+#ld: -shared -melf_i386
+#objdump: -drj.text
+#target: i?86-*-*
+
+.*: +file format elf32-i386
+
+Disassembly of section .text:
+
+[0-9a-f]+ <fn1>:
+ [0-9a-f]+:	55[ 	]+push   %ebp
+ [0-9a-f]+:	89 e5[ 	]+mov    %esp,%ebp
+ [0-9a-f]+:	53[ 	]+push   %ebx
+ [0-9a-f]+:	50[ 	]+push   %eax
+ [0-9a-f]+:	e8 00 00 00 00[ 	]+call   [0-9a-f]+ <fn1\+0xa>
+ [0-9a-f]+:	5b[ 	]+pop    %ebx
+ [0-9a-f]+:	81 c3 42 14 00 00[ 	]+add    \$0x[0-9a-f]+,%ebx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD
+ [0-9a-f]+:	8d 04 1d d4 ff ff ff[ 	]+lea    -0x2c\(,%ebx,1\),%eax
+#				->R_386_TLS_DTPMOD32	sg1
+ [0-9a-f]+:	e8 cf ff ff ff[ 	]+call   [0-9a-f]+ <___tls_get_addr@plt>
+#				->R_386_JUMP_SLOT	___tls_get_addr
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is referenced through @gottpoff too
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	2b 83 f0 ff ff ff[ 	]+sub    -0x10\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sg2
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is referenced through @gotntpoff too
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	03 83 b4 ff ff ff[ 	]+add    -0x4c\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	sg3
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is referenced through @gottpoff and
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	2b 83 c0 ff ff ff[ 	]+sub    -0x40\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sg4
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD against local variable
+ [0-9a-f]+:	8d 04 1d 88 ff ff ff[ 	]+lea    -0x78\(,%ebx,1\),%eax
+#				->R_386_TLS_DTPMOD32	[0x00000000 0x20000000]
+ [0-9a-f]+:	e8 8f ff ff ff[ 	]+call   [0-9a-f]+ <___tls_get_addr@plt>
+#				->R_386_JUMP_SLOT	___tls_get_addr
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against local variable referenced through @gottpoff too
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	2b 83 90 ff ff ff[ 	]+sub    -0x70\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	[0xdcffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against local variable referenced through @gotntpoff
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	03 83 94 ff ff ff[ 	]+add    -0x6c\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	[0x28000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against local variable referenced through @gottpoff and
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	2b 83 98 ff ff ff[ 	]+sub    -0x68\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	[0xd4ffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD against hidden and local variable
+ [0-9a-f]+:	8d 04 1d f4 ff ff ff[ 	]+lea    -0xc\(,%ebx,1\),%eax
+#				->R_386_TLS_DTPMOD32	[0x00000000 0x40000000]
+ [0-9a-f]+:	e8 4f ff ff ff[ 	]+call   [0-9a-f]+ <___tls_get_addr@plt>
+#				->R_386_JUMP_SLOT	___tls_get_addr
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against hidden and local variable referenced through @gottpoff too
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	2b 83 fc ff ff ff[ 	]+sub    -0x4\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	[0xbcffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against hidden and local variable referenced through @gotntpoff too
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	03 83 b8 ff ff ff[ 	]+add    -0x48\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	[0x48000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against hidden and local variable referenced through @gottpoff and @gotntpoff too
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	2b 83 dc ff ff ff[ 	]+sub    -0x24\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	[0xb4ffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD against hidden but not local variable
+ [0-9a-f]+:	8d 04 1d ac ff ff ff[ 	]+lea    -0x54\(,%ebx,1\),%eax
+#				->R_386_TLS_DTPMOD32	[0x00000000 0x60000000]
+ [0-9a-f]+:	e8 0f ff ff ff[ 	]+call   [0-9a-f]+ <___tls_get_addr@plt>
+#				->R_386_JUMP_SLOT	___tls_get_addr
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against hidden but not local variable referenced through
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	2b 83 bc ff ff ff[ 	]+sub    -0x44\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	[0x9cffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against hidden but not local variable referenced through
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	03 83 e4 ff ff ff[ 	]+add    -0x1c\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	[0x68000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against hidden but not local variable referenced through
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	2b 83 cc ff ff ff[ 	]+sub    -0x34\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	[0x94ffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LD
+ [0-9a-f]+:	8d 83 a4 ff ff ff[ 	]+lea    -0x5c\(%ebx\),%eax
+#				->R_386_TLS_DTPMOD32	[0x00000000 0x00000000]
+ [0-9a-f]+:	e8 d0 fe ff ff[ 	]+call   [0-9a-f]+ <___tls_get_addr@plt>
+#				->R_386_JUMP_SLOT	___tls_get_addr
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 90 20 00 00 00[ 	]+lea    0x20\(%eax\),%edx
+#							sl1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 88 26 00 00 00[ 	]+lea    0x26\(%eax\),%ecx
+#							sl2+2
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LD against hidden and local variables
+ [0-9a-f]+:	8d 83 a4 ff ff ff[ 	]+lea    -0x5c\(%ebx\),%eax
+#				->R_386_TLS_DTPMOD32	[0x00000000 0x00000000]
+ [0-9a-f]+:	e8 b1 fe ff ff[ 	]+call   [0-9a-f]+ <___tls_get_addr@plt>
+#				->R_386_JUMP_SLOT	___tls_get_addr
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 90 40 00 00 00[ 	]+lea    0x40\(%eax\),%edx
+#							sh1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 88 47 00 00 00[ 	]+lea    0x47\(%eax\),%ecx
+#							sh2+3
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  LD against hidden but not local variables
+ [0-9a-f]+:	8d 83 a4 ff ff ff[ 	]+lea    -0x5c\(%ebx\),%eax
+#				->R_386_TLS_DTPMOD32	[0x00000000 0x00000000]
+ [0-9a-f]+:	e8 92 fe ff ff[ 	]+call   [0-9a-f]+ <___tls_get_addr@plt>
+#				->R_386_JUMP_SLOT	___tls_get_addr
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 90 60 00 00 00[ 	]+lea    0x60\(%eax\),%edx
+#							sH1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8d 88 65 00 00 00[ 	]+lea    0x65\(%eax\),%ecx
+#							sH2+1
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against global var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 8b f0 ff ff ff[ 	]+sub    -0x10\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF32	sg2
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against global var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 83 c0 ff ff ff[ 	]+sub    -0x40\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	sg4
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against global var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 8b b4 ff ff ff[ 	]+add    -0x4c\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	sg3
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against global var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 83 c4 ff ff ff[ 	]+add    -0x3c\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	sg4
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against local var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 8b 90 ff ff ff[ 	]+sub    -0x70\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF32	[0xdcffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against local var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 83 98 ff ff ff[ 	]+sub    -0x68\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	[0xd4ffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against local var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 8b 94 ff ff ff[ 	]+add    -0x6c\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	[0x28000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against local var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 83 9c ff ff ff[ 	]+add    -0x64\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	[0x2c000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against hidden and local var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 8b fc ff ff ff[ 	]+sub    -0x4\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF32	[0xbcffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against hidden and local var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 83 dc ff ff ff[ 	]+sub    -0x24\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	[0xb4ffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against hidden and local var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 8b b8 ff ff ff[ 	]+add    -0x48\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	[0x48000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against hidden and local var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 83 e0 ff ff ff[ 	]+add    -0x20\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	[0x4c000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against hidden but not local var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 8b bc ff ff ff[ 	]+sub    -0x44\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF32	[0x9cffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gottpoff IE against hidden but not local var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	2b 83 cc ff ff ff[ 	]+sub    -0x34\(%ebx\),%eax
+#				->R_386_TLS_TPOFF32	[0x94ffffff]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against hidden but not local var
+ [0-9a-f]+:	65 8b 0d 00 00 00 00[ 	]+mov    %gs:0x0,%ecx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 8b e4 ff ff ff[ 	]+add    -0x1c\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	[0x68000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against hidden but not local var
+ [0-9a-f]+:	65 a1 00 00 00 00[ 	]+mov    %gs:0x0,%eax
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	03 83 d0 ff ff ff[ 	]+add    -0x30\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	[0x6c000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  Direct access through %gs
+#  @gotntpoff IE against global var
+ [0-9a-f]+:	8b 8b c8 ff ff ff[ 	]+mov    -0x38\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	sg5
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 11[ 	]+mov    %gs:\(%ecx\),%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against local var
+ [0-9a-f]+:	8b 83 a0 ff ff ff[ 	]+mov    -0x60\(%ebx\),%eax
+#				->R_386_TLS_TPOFF	[0x30000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 10[ 	]+mov    %gs:\(%eax\),%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against hidden and local var
+ [0-9a-f]+:	8b 93 e8 ff ff ff[ 	]+mov    -0x18\(%ebx\),%edx
+#				->R_386_TLS_TPOFF	[0x50000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 12[ 	]+mov    %gs:\(%edx\),%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+#  @gotntpoff IE against hidden but not local var
+ [0-9a-f]+:	8b 8b ec ff ff ff[ 	]+mov    -0x14\(%ebx\),%ecx
+#				->R_386_TLS_TPOFF	[0x70000000]
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	65 8b 11[ 	]+mov    %gs:\(%ecx\),%edx
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	8b 5d fc[ 	]+mov    -0x4\(%ebp\),%ebx
+ [0-9a-f]+:	c9[ 	]+leave *
+ [0-9a-f]+:	c3[ 	]+ret *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
+ [0-9a-f]+:	90[ 	]+nop *
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlspic.rd b/binutils-2.19/ld/testsuite/ld-i386/tlspic.rd
new file mode 100644
index 0000000..ac41442
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlspic.rd
@@ -0,0 +1,154 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: --32
+#ld: -shared -melf_i386
+#readelf: -Ssrl
+#target: i?86-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] \.hash +.*
+ +\[[ 0-9]+\] \.dynsym +.*
+ +\[[ 0-9]+\] \.dynstr +.*
+ +\[[ 0-9]+\] \.rel.dyn +.*
+ +\[[ 0-9]+\] \.rel.plt +.*
+ +\[[ 0-9]+\] \.plt +.*
+ +\[[ 0-9]+\] \.text +.*
+ +\[[ 0-9]+\] \.tdata +PROGBITS +[0-9a-f]+ [0-9a-f]+ 000060 00 WAT  0   0  1
+ +\[[ 0-9]+\] \.tbss +NOBITS +[0-9aa-f]+ [0-9a-f]+ 000020 00 WAT  0   0  1
+ +\[[ 0-9]+\] \.dynamic +.*
+ +\[[ 0-9]+\] \.got +.*
+ +\[[ 0-9]+\] \.got.plt +.*
+ +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x[0-9a-f]+
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  LOAD.*
+  LOAD.*
+  DYNAMIC.*
+  TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+60 0x0+80 R +0x1
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 +.hash .dynsym .dynstr .rel.dyn .rel.plt .plt .text *
+   01 +.tdata .dynamic .got .got.plt *
+   02 +.dynamic *
+   03 +.tdata .tbss *
+
+Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 26 entries:
+ Offset +Info +Type +Sym.Value +Sym. Name
+[0-9a-f ]+R_386_TLS_DTPMOD3
+[0-9a-f ]+R_386_TLS_TPOFF32
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF32
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_DTPMOD3
+[0-9a-f ]+R_386_TLS_DTPMOD3
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF32
+[0-9a-f ]+R_386_TLS_TPOFF32
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF32
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_TPOFF *
+[0-9a-f ]+R_386_TLS_DTPMOD3
+[0-9a-f ]+R_386_TLS_TPOFF32
+[0-9a-f ]+R_386_TLS_TPOFF   0+8   sg3
+[0-9a-f ]+R_386_TLS_TPOFF32 0+c   sg4
+[0-9a-f ]+R_386_TLS_TPOFF   0+c   sg4
+[0-9a-f ]+R_386_TLS_TPOFF   0+10   sg5
+[0-9a-f ]+R_386_TLS_DTPMOD3 0+   sg1
+[0-9a-f ]+R_386_TLS_DTPOFF3 0+   sg1
+[0-9a-f ]+R_386_TLS_TPOFF32 0+4   sg2
+
+Relocation section '.rel.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ Offset +Info +Type +Sym.Value +Sym. Name
+[0-9a-f ]+R_386_JUMP_SLOT   0+   ___tls_get_addr
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value  Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: 0+1c +0 TLS +GLOBAL DEFAULT +8 sg8
+ +[0-9]+: 0+8 +0 TLS +GLOBAL DEFAULT +8 sg3
+ +[0-9]+: 0+c +0 TLS +GLOBAL DEFAULT +8 sg4
+ +[0-9]+: 0+10 +0 TLS +GLOBAL DEFAULT +8 sg5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +8 sg1
+ +[0-9]+: [0-9a-f]+ +0 FUNC +GLOBAL DEFAULT +7 fn1
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+4 +0 TLS +GLOBAL DEFAULT +8 sg2
+ +[0-9]+: 0+14 +0 TLS +GLOBAL DEFAULT +8 sg6
+ +[0-9]+: 0+18 +0 TLS +GLOBAL DEFAULT +8 sg7
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+ +[0-9]+: 0+ +0 NOTYPE  GLOBAL DEFAULT  UND ___tls_get_addr
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value  Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +1 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +2 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +3 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +4 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +5 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +6 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +7 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +8 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +9 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +10 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +11 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +12 *
+ +[0-9]+: 0+20 +0 TLS +LOCAL  DEFAULT +8 sl1
+ +[0-9]+: 0+24 +0 TLS +LOCAL  DEFAULT +8 sl2
+ +[0-9]+: 0+28 +0 TLS +LOCAL  DEFAULT +8 sl3
+ +[0-9]+: 0+2c +0 TLS +LOCAL  DEFAULT +8 sl4
+ +[0-9]+: 0+30 +0 TLS +LOCAL  DEFAULT +8 sl5
+ +[0-9]+: 0+34 +0 TLS +LOCAL  DEFAULT +8 sl6
+ +[0-9]+: 0+38 +0 TLS +LOCAL  DEFAULT +8 sl7
+ +[0-9]+: 0+3c +0 TLS +LOCAL  DEFAULT +8 sl8
+ +[0-9]+: 0+60 +0 TLS +LOCAL  HIDDEN +9 sH1
+ +[0-9]+: [0-9a-f]+ +0 OBJECT  LOCAL  HIDDEN  ABS _DYNAMIC
+ +[0-9]+: 0+48 +0 TLS +LOCAL  HIDDEN +8 sh3
+ +[0-9]+: 0+64 +0 TLS +LOCAL  HIDDEN +9 sH2
+ +[0-9]+: 0+78 +0 TLS +LOCAL  HIDDEN +9 sH7
+ +[0-9]+: 0+58 +0 TLS +LOCAL  HIDDEN +8 sh7
+ +[0-9]+: 0+5c +0 TLS +LOCAL  HIDDEN +8 sh8
+ +[0-9]+: 0+6c +0 TLS +LOCAL  HIDDEN +9 sH4
+ +[0-9]+: 0+4c +0 TLS +LOCAL  HIDDEN +8 sh4
+ +[0-9]+: 0+68 +0 TLS +LOCAL  HIDDEN +9 sH3
+ +[0-9]+: 0+50 +0 TLS +LOCAL  HIDDEN +8 sh5
+ +[0-9]+: 0+70 +0 TLS +LOCAL  HIDDEN +9 sH5
+ +[0-9]+: 0+74 +0 TLS +LOCAL  HIDDEN +9 sH6
+ +[0-9]+: 0+7c +0 TLS +LOCAL  HIDDEN +9 sH8
+ +[0-9]+: 0+40 +0 TLS +LOCAL  HIDDEN +8 sh1
+ +[0-9]+: [0-9a-f]+ +0 OBJECT  LOCAL  HIDDEN  ABS _GLOBAL_OFFSET_TABLE_
+ +[0-9]+: 0+44 +0 TLS +LOCAL  HIDDEN +8 sh2
+ +[0-9]+: 0+54 +0 TLS +LOCAL  HIDDEN +8 sh6
+ +[0-9]+: 0+1c +0 TLS +GLOBAL DEFAULT +8 sg8
+ +[0-9]+: 0+8 +0 TLS +GLOBAL DEFAULT +8 sg3
+ +[0-9]+: 0+c +0 TLS +GLOBAL DEFAULT +8 sg4
+ +[0-9]+: 0+10 +0 TLS +GLOBAL DEFAULT +8 sg5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +8 sg1
+ +[0-9]+: [0-9a-f]+ +0 FUNC +GLOBAL DEFAULT +7 fn1
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+4 +0 TLS +GLOBAL DEFAULT +8 sg2
+ +[0-9]+: 0+14 +0 TLS +GLOBAL DEFAULT +8 sg6
+ +[0-9]+: 0+18 +0 TLS +GLOBAL DEFAULT +8 sg7
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+ +[0-9]+: 0+ +0 NOTYPE  GLOBAL DEFAULT  UND ___tls_get_addr
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlspic.sd b/binutils-2.19/ld/testsuite/ld-i386/tlspic.sd
new file mode 100644
index 0000000..f9c9627
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlspic.sd
@@ -0,0 +1,18 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: --32
+#ld: -shared -melf_i386
+#objdump: -sj.got
+#target: i?86-*-*
+
+.*:     file format elf32-i386
+
+Contents of section \.got:
+ [0-9a-f]+ 00000000 20000000 dcffffff 28000000  .*
+ [0-9a-f]+ d4ffffff 2c000000 30000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 60000000 00000000  .*
+ [0-9a-f]+ 48000000 9cffffff 00000000 00000000  .*
+ [0-9a-f]+ 00000000 94ffffff 6c000000 00000000  .*
+ [0-9a-f]+ 00000000 b4ffffff 4c000000 68000000  .*
+ [0-9a-f]+ 50000000 70000000 00000000 00000000  .*
+ [0-9a-f]+ 40000000 bcffffff  +.*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlspic.td b/binutils-2.19/ld/testsuite/ld-i386/tlspic.td
new file mode 100644
index 0000000..1291584
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlspic.td
@@ -0,0 +1,16 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: --32
+#ld: -shared -melf_i386
+#objdump: -sj.tdata
+#target: i?86-*-*
+
+.*:     file format elf32-i386
+
+Contents of section \.tdata:
+ [0-9a-f]+ 11000000 12000000 13000000 14000000  .*
+ [0-9a-f]+ 15000000 16000000 17000000 18000000  .*
+ [0-9a-f]+ 41000000 42000000 43000000 44000000  .*
+ [0-9a-f]+ 45000000 46000000 47000000 48000000  .*
+ [0-9a-f]+ 01010000 02010000 03010000 04010000  .*
+ [0-9a-f]+ 05010000 06010000 07010000 08010000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlspic1.s b/binutils-2.19/ld/testsuite/ld-i386/tlspic1.s
new file mode 100644
index 0000000..9dcb3b7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlspic1.s
@@ -0,0 +1,282 @@
+	.section ".tdata", "awT", @progbits
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+	.text
+	.globl	fn1
+	.type	fn1,@function
+fn1:
+	pushl	%ebp
+	movl	%esp, %ebp
+	pushl	%ebx
+	pushl	%eax
+	call	1f
+1:	popl	%ebx
+	addl	$_GLOBAL_OFFSET_TABLE_+[.-1b], %ebx
+	nop;nop;nop;nop
+
+	/* GD */
+	leal	sg1@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is referenced through @gottpoff too */
+	leal	sg2@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is referenced through @gotntpoff too */
+	leal	sg3@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is referenced through @gottpoff and
+	   @gotntpoff too */
+	leal	sg4@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD against local variable */
+	leal	sl1@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE against local variable referenced through @gottpoff too */
+	leal	sl2@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE against local variable referenced through @gotntpoff
+	   too */
+	leal	sl3@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE against local variable referenced through @gottpoff and
+	   @gotntpoff too */
+	leal	sl4@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD against hidden and local variable */
+	leal	sh1@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden and local variable referenced through
+	   @gottpoff too */
+	leal	sh2@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden and local variable referenced through
+	   @gotntpoff too */
+	leal	sh3@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden and local variable referenced through
+	   @gottpoff and @gotntpoff too */
+	leal	sh4@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD against hidden but not local variable */
+	leal	sH1@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden but not local variable referenced through
+	   @gottpoff too */
+	leal	sH2@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden but not local variable referenced through
+	   @gotntpoff too */
+	leal	sH3@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden but not local variable referenced through
+	   @gottpoff and @gotntpoff too */
+	leal	sH4@tlsgd(,%ebx,1), %eax
+	call	___tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* LD */
+	leal	sl1@tlsldm(%ebx), %eax
+	call	___tls_get_addr@PLT
+	nop;nop
+	leal	sl1@dtpoff(%eax), %edx
+	nop;nop
+	leal	2+sl2@dtpoff(%eax), %ecx
+	nop;nop;nop;nop
+
+	/* LD against hidden and local variables */
+	leal	sh1@tlsldm(%ebx), %eax
+	call	___tls_get_addr@PLT
+	nop;nop
+	leal	sh1@dtpoff(%eax), %edx
+	nop;nop
+	leal	sh2@dtpoff+3(%eax), %ecx
+	nop;nop;nop;nop
+
+	/* LD against hidden but not local variables */
+	leal	sH1@tlsldm(%ebx), %eax
+	call	___tls_get_addr@PLT
+	nop;nop
+	leal	sH1@dtpoff(%eax), %edx
+	nop;nop
+	leal	sH2@dtpoff+1(%eax), %ecx
+	nop;nop
+
+	/* @gottpoff IE against global var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sg2@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against global var  */
+	movl	%gs:0, %eax
+	nop;nop
+	subl	sg4@gottpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against global var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	addl	sg3@gotntpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against global var  */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	sg4@gotntpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against local var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sl2@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against local var  */
+	movl	%gs:0, %eax
+	nop;nop
+	subl	sl4@gottpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against local var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	addl	sl3@gotntpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against local var  */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	sl4@gotntpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against hidden and local var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sh2@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against hidden and local var  */
+	movl	%gs:0, %eax
+	nop;nop
+	subl	sh4@gottpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against hidden and local var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	addl	sh3@gotntpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against hidden and local var  */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	sh4@gotntpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against hidden but not local var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	subl	sH2@gottpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gottpoff IE against hidden but not local var  */
+	movl	%gs:0, %eax
+	nop;nop
+	subl	sH4@gottpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against hidden but not local var  */
+	movl	%gs:0, %ecx
+	nop;nop
+	addl	sH3@gotntpoff(%ebx), %ecx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against hidden but not local var  */
+	movl	%gs:0, %eax
+	nop;nop
+	addl	sH4@gotntpoff(%ebx), %eax
+	nop;nop;nop;nop
+
+	/* Direct access through %gs  */
+
+	/* @gotntpoff IE against global var  */
+	movl	sg5@gotntpoff(%ebx), %ecx
+	nop;nop
+	movl	%gs:(%ecx), %edx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against local var  */
+	movl	sl5@gotntpoff(%ebx), %eax
+	nop;nop
+	movl	%gs:(%eax), %edx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against hidden and local var  */
+	movl	sh5@gotntpoff(%ebx), %edx
+	nop;nop
+	movl	%gs:(%edx), %edx
+	nop;nop;nop;nop
+
+	/* @gotntpoff IE against hidden but not local var  */
+	movl	sH5@gotntpoff(%ebx), %ecx
+	nop;nop
+	movl	%gs:(%ecx), %edx
+	nop;nop;nop;nop
+
+	movl    -4(%ebp), %ebx
+	leave
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-i386/tlspic2.s b/binutils-2.19/ld/testsuite/ld-i386/tlspic2.s
new file mode 100644
index 0000000..5513f9b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/tlspic2.s
@@ -0,0 +1,11 @@
+	.section ".tbss", "awT", @nobits
+	.globl sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+	.hidden sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+sH1:	.space 4
+sH2:	.space 4
+sH3:	.space 4
+sH4:	.space 4
+sH5:	.space 4
+sH6:	.space 4
+sH7:	.space 4
+sH8:	.space 4
diff --git a/binutils-2.19/ld/testsuite/ld-i386/vxworks1-lib.dd b/binutils-2.19/ld/testsuite/ld-i386/vxworks1-lib.dd
new file mode 100644
index 0000000..8cebf82
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/vxworks1-lib.dd
@@ -0,0 +1,41 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+00080800 <_PROCEDURE_LINKAGE_TABLE_>:
+   80800:	ff b3 04 00 00 00    	pushl  0x4\(%ebx\)
+   80806:	ff a3 08 00 00 00    	jmp    \*0x8\(%ebx\)
+   8080c:	90                   	nop    
+   8080d:	90                   	nop    
+   8080e:	90                   	nop    
+   8080f:	90                   	nop    
+
+00080810 <sexternal@plt>:
+   80810:	ff a3 0c 00 00 00    	jmp    \*0xc\(%ebx\)
+   80816:	68 00 00 00 00       	push   \$0x0
+   8081b:	e9 e0 ff ff ff       	jmp    80800 <_PROCEDURE_LINKAGE_TABLE_>
+
+00080820 <sglobal@plt>:
+   80820:	ff a3 10 00 00 00    	jmp    \*0x10\(%ebx\)
+   80826:	68 08 00 00 00       	push   \$0x8
+   8082b:	e9 d0 ff ff ff       	jmp    80800 <_PROCEDURE_LINKAGE_TABLE_>
+Disassembly of section \.text:
+
+00080c00 <foo>:
+   80c00:	53                   	push   %ebx
+   80c01:	8b 1d 00 00 00 00    	mov    0x0,%ebx
+   80c07:	8b 99 00 00 00 00    	mov    0x0\(%ecx\),%ebx
+   80c0d:	8b 83 14 00 00 00    	mov    0x14\(%ebx\),%eax
+   80c13:	ff 00                	incl   \(%eax\)
+   80c15:	e8 0c 00 00 00       	call   80c26 <slocal>
+   80c1a:	e8 01 fc ff ff       	call   80820 <sglobal@plt>
+   80c1f:	e8 ec fb ff ff       	call   80810 <sexternal@plt>
+   80c24:	5b                   	pop    %ebx
+   80c25:	c3                   	ret    
+
+00080c26 <slocal>:
+   80c26:	c3                   	ret    
+
+00080c27 <sglobal>:
+   80c27:	c3                   	ret    
diff --git a/binutils-2.19/ld/testsuite/ld-i386/vxworks1-lib.nd b/binutils-2.19/ld/testsuite/ld-i386/vxworks1-lib.nd
new file mode 100644
index 0000000..edf3db3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/vxworks1-lib.nd
@@ -0,0 +1,9 @@
+#...
+Symbol table '\.dynsym' .*:
+#...
+.*: 00081400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
+#...
+Symbol table '\.symtab' .*:
+#...
+.*: 00081400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-i386/vxworks1-lib.rd b/binutils-2.19/ld/testsuite/ld-i386/vxworks1-lib.rd
new file mode 100644
index 0000000..61ff293
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/vxworks1-lib.rd
@@ -0,0 +1,12 @@
+
+Relocation section '\.rel\.plt' at offset .* contains 2 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name
+0008140c  .*07 R_386_JUMP_SLOT   00000000   sexternal
+00081410  .*07 R_386_JUMP_SLOT   00080c27   sglobal
+
+Relocation section '\.rel\.dyn' at offset .* contains 4 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name
+00081800  00000008 R_386_RELATIVE *
+00080c03  .*01 R_386_32          00000000   __GOTT_BASE__
+00080c09  .*01 R_386_32          00000000   __GOTT_INDEX__
+00081414  .*06 R_386_GLOB_DAT    00081c00   x
diff --git a/binutils-2.19/ld/testsuite/ld-i386/vxworks1-lib.s b/binutils-2.19/ld/testsuite/ld-i386/vxworks1-lib.s
new file mode 100644
index 0000000..f9f05dc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/vxworks1-lib.s
@@ -0,0 +1,31 @@
+	.text
+	.globl	foo
+	.type	foo, @function
+foo:
+	push	%ebx
+	movl	__GOTT_BASE__, %ebx
+	movl	__GOTT_INDEX__(%ecx), %ebx
+	movl	x@GOT(%ebx), %eax
+	incl	(%eax)
+	call	slocal@plt
+	call	sglobal@plt
+	call	sexternal@plt
+	pop	%ebx
+	ret
+	.size	foo, .-foo
+
+	.type	slocal, @function
+slocal:
+	ret
+	.size	slocal, .-slocal
+
+	.globl	sglobal
+	.type	sglobal, @function
+sglobal:
+	ret
+	.size	sglobal, .-sglobal
+
+	.data
+	.4byte	slocal
+
+	.comm	x,4,4
diff --git a/binutils-2.19/ld/testsuite/ld-i386/vxworks1-lib.td b/binutils-2.19/ld/testsuite/ld-i386/vxworks1-lib.td
new file mode 100644
index 0000000..9f223e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/vxworks1-lib.td
@@ -0,0 +1,3 @@
+#...
+ 0x0+16 \(TEXTREL\) +0x0
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-i386/vxworks1-static.d b/binutils-2.19/ld/testsuite/ld-i386/vxworks1-static.d
new file mode 100644
index 0000000..88c0baf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/vxworks1-static.d
@@ -0,0 +1,4 @@
+#name: VxWorks executable test 1 (static)
+#source: vxworks1.s
+#ld: tmpdir/libvxworks1.so -Tvxworks1.ld
+#error: Dynamic sections created in non-dynamic link
diff --git a/binutils-2.19/ld/testsuite/ld-i386/vxworks1.dd b/binutils-2.19/ld/testsuite/ld-i386/vxworks1.dd
new file mode 100644
index 0000000..33f68f4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/vxworks1.dd
@@ -0,0 +1,38 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+00080800 <_PROCEDURE_LINKAGE_TABLE_>:
+   80800:	ff 35 04 14 08 00    	pushl  0x81404
+			80802: R_386_32	_GLOBAL_OFFSET_TABLE_
+   80806:	ff 25 08 14 08 00    	jmp    \*0x81408
+			80808: R_386_32	_GLOBAL_OFFSET_TABLE_
+   8080c:	90                   	nop    
+   8080d:	90                   	nop    
+   8080e:	90                   	nop    
+   8080f:	90                   	nop    
+
+00080810 <sglobal@plt>:
+   80810:	ff 25 0c 14 08 00    	jmp    \*0x8140c
+			80812: R_386_32	_GLOBAL_OFFSET_TABLE_
+   80816:	68 00 00 00 00       	push   \$0x0
+   8081b:	e9 e0 ff ff ff       	jmp    80800 <_PROCEDURE_LINKAGE_TABLE_>
+
+00080820 <foo@plt>:
+   80820:	ff 25 10 14 08 00    	jmp    \*0x81410
+			80822: R_386_32	_GLOBAL_OFFSET_TABLE_
+   80826:	68 08 00 00 00       	push   \$0x8
+   8082b:	e9 d0 ff ff ff       	jmp    80800 <_PROCEDURE_LINKAGE_TABLE_>
+Disassembly of section \.text:
+
+00080c00 <_start>:
+   80c00:	e8 1b fc ff ff       	call   80820 <foo@plt>
+			80c01: R_386_PLT32	\.plt
+   80c05:	e8 05 00 00 00       	call   80c0f <sexternal>
+			80c06: R_386_PLT32	sexternal
+   80c0a:	e9 01 fc ff ff       	jmp    80810 <sglobal@plt>
+			80c0b: R_386_PLT32	\.plt
+
+00080c0f <sexternal>:
+   80c0f:	c3                   	ret    
diff --git a/binutils-2.19/ld/testsuite/ld-i386/vxworks1.ld b/binutils-2.19/ld/testsuite/ld-i386/vxworks1.ld
new file mode 100644
index 0000000..ed76f18
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/vxworks1.ld
@@ -0,0 +1,30 @@
+SECTIONS
+{
+  . = 0x80000;
+  .interp : { *(.interp) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+
+  . = ALIGN (0x400);
+  .rel.dyn : { *(.rel.dyn) }
+  .rel.plt : { *(.rel.plt) }
+
+  . = ALIGN (0x400);
+  .plt : { *(.plt) }
+
+  . = ALIGN (0x400);
+  .text : { *(.text) }
+
+  . = ALIGN (0x1000);
+  .dynamic : { *(.dynamic) }
+
+  . = ALIGN (0x400);
+  .got : { *(.got.plt) *(.got) }
+
+  . = ALIGN (0x400);
+  .data : { *(.data) }
+
+  . = ALIGN (0x400);
+  .bss : { *(.bss) *(.dynbss) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-i386/vxworks1.rd b/binutils-2.19/ld/testsuite/ld-i386/vxworks1.rd
new file mode 100644
index 0000000..9fd7383
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/vxworks1.rd
@@ -0,0 +1,20 @@
+
+Relocation section '\.rel\.plt' at offset .* contains 2 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name
+0008140c  .*07 R_386_JUMP_SLOT   00000000   sglobal
+00081410  .*07 R_386_JUMP_SLOT   00000000   foo
+
+Relocation section '\.rel\.text' at offset .* contains 3 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name
+00080c01  .*04 R_386_PLT32       00080800   .plt
+00080c06  .*04 R_386_PLT32       00080c0f   sexternal
+00080c0b  .*04 R_386_PLT32       00080800   .plt
+
+Relocation section '\.rel\.plt\.unloaded' at offset .* contains 6 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name
+00080802  .*01 R_386_32          00081400   _GLOBAL_OFFSET_TABLE_
+00080808  .*01 R_386_32          00081400   _GLOBAL_OFFSET_TABLE_
+00080812  .*01 R_386_32          00081400   _GLOBAL_OFFSET_TABLE_
+0008140c  .*01 R_386_32          00080800   _PROCEDURE_LINKAGE_TAB.*
+00080822  .*01 R_386_32          00081400   _GLOBAL_OFFSET_TABLE_
+00081410  .*01 R_386_32          00080800   _PROCEDURE_LINKAGE_TAB.*
diff --git a/binutils-2.19/ld/testsuite/ld-i386/vxworks1.s b/binutils-2.19/ld/testsuite/ld-i386/vxworks1.s
new file mode 100644
index 0000000..5cb68af
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/vxworks1.s
@@ -0,0 +1,14 @@
+	.text
+	.globl	_start
+	.type	_start,@function
+_start:
+	call	foo@plt
+	call	sexternal@plt
+	jmp	sglobal@plt
+	.size	_start, .-_start
+
+	.globl	sexternal
+	.type	sexternal,@function
+sexternal:
+	ret
+	.size	sexternal, .-sexternal
diff --git a/binutils-2.19/ld/testsuite/ld-i386/vxworks2-static.sd b/binutils-2.19/ld/testsuite/ld-i386/vxworks2-static.sd
new file mode 100644
index 0000000..912755b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/vxworks2-static.sd
@@ -0,0 +1,9 @@
+#...
+Elf file type is EXEC \(Executable file\)
+Entry point 0x80000
+#...
+Program Headers:
+  Type .*
+  LOAD .* 0x00080000 0x00080000 .* R E 0x1000
+
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-i386/vxworks2.s b/binutils-2.19/ld/testsuite/ld-i386/vxworks2.s
new file mode 100644
index 0000000..28c8acb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/vxworks2.s
@@ -0,0 +1,5 @@
+	.globl	_start
+	.type	_start,@function
+_start:
+	ret
+	.end	_start
diff --git a/binutils-2.19/ld/testsuite/ld-i386/vxworks2.sd b/binutils-2.19/ld/testsuite/ld-i386/vxworks2.sd
new file mode 100644
index 0000000..5ff87d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/vxworks2.sd
@@ -0,0 +1,13 @@
+#...
+Elf file type is EXEC \(Executable file\)
+Entry point 0x80400
+#...
+Program Headers:
+  Type .*
+  PHDR .*
+#...
+  LOAD .* 0x00080000 0x00080000 .* R E 0x1000
+  LOAD .* 0x00081000 0x00081000 .* RW  0x1000
+  DYNAMIC .*
+
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-i386/warn1.d b/binutils-2.19/ld/testsuite/ld-i386/warn1.d
new file mode 100644
index 0000000..dd541f2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/warn1.d
@@ -0,0 +1,4 @@
+#name: --warn-shared-textrel --fatal-warnings
+#as: --32
+#ld: -shared -melf_i386 --warn-shared-textrel --fatal-warnings
+#error: .*warning: creating a DT_TEXTREL in a shared object.
diff --git a/binutils-2.19/ld/testsuite/ld-i386/warn1.s b/binutils-2.19/ld/testsuite/ld-i386/warn1.s
new file mode 100644
index 0000000..ca3481a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/warn1.s
@@ -0,0 +1,5 @@
+	.text
+	.globl foo
+	.type	foo, @function
+foo:
+	movl	bar, %eax
diff --git a/binutils-2.19/ld/testsuite/ld-i386/zero.s b/binutils-2.19/ld/testsuite/ld-i386/zero.s
new file mode 100644
index 0000000..f716bba
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-i386/zero.s
@@ -0,0 +1,2 @@
+ .global zero
+ .equiv zero, 0
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/ia64.exp b/binutils-2.19/ld/testsuite/ld-ia64/ia64.exp
new file mode 100644
index 0000000..d6e52aa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/ia64.exp
@@ -0,0 +1,64 @@
+# Expect script for ld-ia64 tests
+#   Copyright (C) 2002, 2003, 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Test ia64 linking; all types of relocs.  This tests the assembler and
+# tools like objdump as well as the linker.
+
+if { !([istarget "ia64-*-elf*"]
+       || [istarget "ia64-*-linux*"]) } {
+    return
+}
+
+# List contains test-items with 3 items followed by 2 lists:
+# 0:name 1:ld options 2:assembler options
+# 3:filenames of assembler files 4: action and options. 5: name of output file
+
+# Actions:
+# objdump: Apply objdump options on result.  Compare with regex (last arg).
+# nm: Apply nm options on result.  Compare with regex (last arg).
+# readelf: Apply readelf options on result.  Compare with regex (last arg).
+
+set ia64tests {
+    {"TLS -fpic -shared" "-shared"
+     "-mtune=itanium1" {tlspic1.s tlspic2.s}
+     {{readelf -WSsrl tlspic.rd} {objdump -drj.text tlspic.dd}
+      {objdump -sj.got tlspic.sd} {objdump -sj.tdata tlspic.td}}
+      "libtlspic.so"}
+    {"Helper shared library" "-shared"
+     "" {tlslib.s} {} "libtlslib.so"}
+    {"TLS -fpic and -fno-pic exec"
+     "tmpdir/libtlslib.so" "-mtune=itanium1" {tlsbinpic.s tlsbin.s}
+     {{readelf -WSsrl tlsbin.rd} {objdump -drj.text tlsbin.dd}
+      {objdump -sj.got tlsbin.sd} {objdump -sj.tdata tlsbin.td}}
+      "tlsbin"}
+    {"TLS in debug sections" ""
+     "" {tlsg.s}
+     {{objdump -sj.debug_foobar tlsg.sd}} "tlsg"}
+}
+
+run_ld_link_tests $ia64tests
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach t $test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname $t]
+    run_dump_test [file rootname $t]
+}
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/line.exp b/binutils-2.19/ld/testsuite/ld-ia64/line.exp
new file mode 100644
index 0000000..2ebc7d6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/line.exp
@@ -0,0 +1,57 @@
+# Test that the linker reports undefined symbol line number correctly.
+#
+#   Copyright 2007  Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+if { !([istarget "ia64-*-elf*"]
+       || [istarget "ia64-*-linux*"]) } {
+    return
+}
+
+set testline "undefined line"
+
+if ![ld_assemble $as "-x $srcdir/$subdir/undefined.s" tmpdir/undefined.o] {
+    verbose "Unable to assemble test file!" 1
+    unresolved $testline
+    return
+}
+
+remote_file host delete "tmpdir/undefined"
+
+# Using -e start prevents the SunOS linker from trying to build a
+# shared library.
+send_log "$ld -e start -o tmpdir/undefined tmpdir/undefined.o\n"
+set exec_output [run_host_cmd "$ld" "-e start -o tmpdir/undefined tmpdir/undefined.o"]
+
+send_log "$exec_output\n"
+verbose "$exec_output"
+
+proc checkund { string testname } {
+    global exec_output
+
+    if [string match "*$string*" $exec_output] {
+	pass $testname
+    } else {
+	fail $testname
+    }
+}
+
+set ml "undefined.c:9: undefined reference to `*this_function_is_not_defined'"
+
+checkund $ml $testline
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/link-order.d b/binutils-2.19/ld/testsuite/ld-ia64/link-order.d
new file mode 100644
index 0000000..53a3794
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/link-order.d
@@ -0,0 +1,9 @@
+#source: ../../../binutils/testsuite/binutils-all/link-order.s
+#ld: -r
+#readelf: -S --wide
+
+#...
+  \[[ ]+1\] \.text.*[ \t]+PROGBITS[ \t0-9a-f]+AX.*
+#...
+  \[[ 0-9]+\] \.IA_64.unwind[ \t]+IA_64_UNWIND[ \t0-9a-f]+AL[ \t]+1[ \t]+1[ \t]+8
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/merge1.d b/binutils-2.19/ld/testsuite/ld-ia64/merge1.d
new file mode 100644
index 0000000..39882b8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/merge1.d
@@ -0,0 +1,10 @@
+#source: merge1.s
+#as: -x
+#ld: -shared
+#objdump: -d
+
+#...
+0+1e0 <.text>:
+[ 	]*[a-f0-9]+:	0b 60 80 02 00 24 	\[MMI\]       addl r12=32,r1;;
+[ 	]*[a-f0-9]+:	c0 c0 04 00 48 00 	            addl r12=24,r1
+[ 	]*[a-f0-9]+:	00 00 04 00       	            nop.i 0x0;;
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/merge1.s b/binutils-2.19/ld/testsuite/ld-ia64/merge1.s
new file mode 100644
index 0000000..8998db4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/merge1.s
@@ -0,0 +1,12 @@
+	.section .rodata.str1.8,"aMS", 1
+.LC1:	.string "foo"
+.LC2:	.string "foo"
+	.section .data.rel.local,"aw"
+	.quad .LC2
+	.section .rodata,"a"
+.LC3:	.string "bar"
+	.balign 8
+	.space 0x400000
+	.text
+	addl r12=@ltoffx(.LC1),r1 ;;
+	addl r12=@ltoffx(.LC3),r1 ;;
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/merge2.d b/binutils-2.19/ld/testsuite/ld-ia64/merge2.d
new file mode 100644
index 0000000..dde3d09
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/merge2.d
@@ -0,0 +1,10 @@
+#source: merge2.s
+#as: -x
+#ld: -shared
+#objdump: -d
+
+#...
+0+1e0 <.text>:
+[ 	]*[a-f0-9]+:	0b 60 80 02 00 24 	\[MMI\]       addl r12=32,r1;;
+[ 	]*[a-f0-9]+:	c0 c0 04 00 48 00 	            addl r12=24,r1
+[ 	]*[a-f0-9]+:	00 00 04 00       	            nop.i 0x0;;
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/merge2.s b/binutils-2.19/ld/testsuite/ld-ia64/merge2.s
new file mode 100644
index 0000000..6c85ac2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/merge2.s
@@ -0,0 +1,12 @@
+	.section .rodata.str1.8,"aMS", 1
+.LC2:	.string "foo"
+.LC1:	.string "foo"
+	.section .data.rel.local,"aw"
+	.quad .LC2
+	.section .rodata,"a"
+.LC3:	.string "bar"
+	.balign 8
+	.space 0x400000
+	.text
+	addl r12=@ltoffx(.LC1),r1 ;;
+	addl r12=@ltoffx(.LC3),r1 ;;
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/merge3.d b/binutils-2.19/ld/testsuite/ld-ia64/merge3.d
new file mode 100644
index 0000000..d0163f3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/merge3.d
@@ -0,0 +1,13 @@
+#source: merge3.s
+#as: -x
+#ld: -shared
+#objdump: -d
+
+#...
+0+210 <.text>:
+[ 	]*[a-f0-9]+:	0b 60 80 02 00 24 	\[MMI\]       addl r12=32,r1;;
+[ 	]*[a-f0-9]+:	c0 40 05 00 48 00 	            addl r12=40,r1
+[ 	]*[a-f0-9]+:	00 00 04 00       	            nop.i 0x0;;
+[ 	]*[a-f0-9]+:	01 60 60 02 00 24 	\[MII\]       addl r12=24,r1
+[ 	]*[a-f0-9]+:	00 00 00 02 00 00 	            nop.i 0x0
+[ 	]*[a-f0-9]+:	00 00 04 00       	            nop.i 0x0;;
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/merge3.s b/binutils-2.19/ld/testsuite/ld-ia64/merge3.s
new file mode 100644
index 0000000..2442701
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/merge3.s
@@ -0,0 +1,16 @@
+	.section .rodata.str1.8,"aMS", 1
+.LC1:	.string "foo"
+.LC2:	.string "foo"
+.LC3:	.string "bar"
+.LC4:	.string "bar"
+	.section .data.rel.local,"aw"
+	.quad .LC2
+	.quad .LC3
+	.section .rodata,"a"
+.LC5:	.string "mumble"
+	.balign 8
+	.space 0x400000
+	.text
+	addl r12=@ltoffx(.LC1),r1 ;;
+	addl r12=@ltoffx(.LC4),r1 ;;
+	addl r12=@ltoffx(.LC5),r1 ;;
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/merge4.d b/binutils-2.19/ld/testsuite/ld-ia64/merge4.d
new file mode 100644
index 0000000..0ed5621
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/merge4.d
@@ -0,0 +1,13 @@
+#source: merge4.s
+#as: -x
+#ld: -shared
+#objdump: -d
+
+#...
+0+240 <.text>:
+[ 	]*[a-f0-9]+:	0b 60 80 02 00 24 	\[MMI\]       addl r12=32,r1;;
+[ 	]*[a-f0-9]+:	c0 40 05 00 48 00 	            addl r12=40,r1
+[ 	]*[a-f0-9]+:	00 00 04 00       	            nop.i 0x0;;
+[ 	]*[a-f0-9]+:	0b 60 c0 02 00 24 	\[MMI\]       addl r12=48,r1;;
+[ 	]*[a-f0-9]+:	c0 c0 04 00 48 00 	            addl r12=24,r1
+[ 	]*[a-f0-9]+:	00 00 04 00       	            nop.i 0x0;;
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/merge4.s b/binutils-2.19/ld/testsuite/ld-ia64/merge4.s
new file mode 100644
index 0000000..c23b4d0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/merge4.s
@@ -0,0 +1,21 @@
+	.section .rodata.str1.8,"aMS", 1
+.LC1:	.string "foo"
+.LC2:	.string "foo"
+.LC3:	.string "bar"
+.LC4:	.string "bar"
+.LC5:	.string "baz"
+.LC6:	.string "baz"
+	.section .data.rel.local,"aw"
+	.quad .LC2
+	.quad .LC4
+	.quad .LC5
+	.section .rodata,"a"
+.LC7:	.string "mumble"
+	.balign 8
+	.space 0x400000
+	.text
+	addl r12=@ltoffx(.LC1),r1 ;;
+	addl r12=@ltoffx(.LC3),r1 ;;
+	addl r12=@ltoffx(.LC6),r1 ;;
+	addl r12=@ltoffx(.LC7),r1 ;;
+
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/merge5.d b/binutils-2.19/ld/testsuite/ld-ia64/merge5.d
new file mode 100644
index 0000000..3adfa55
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/merge5.d
@@ -0,0 +1,16 @@
+#source: merge5.s
+#as: -x
+#ld: -shared
+#objdump: -d
+
+#...
+0+270 <.text>:
+[ 	]*[a-f0-9]+:	0b 60 80 02 00 24 	\[MMI\]       addl r12=32,r1;;
+[ 	]*[a-f0-9]+:	c0 40 05 00 48 00 	            addl r12=40,r1
+[ 	]*[a-f0-9]+:	00 00 04 00       	            nop.i 0x0;;
+[ 	]*[a-f0-9]+:	0b 60 a0 02 00 24 	\[MMI\]       addl r12=40,r1;;
+[ 	]*[a-f0-9]+:	c0 c0 05 00 48 00 	            addl r12=56,r1
+[ 	]*[a-f0-9]+:	00 00 04 00       	            nop.i 0x0;;
+[ 	]*[a-f0-9]+:	01 60 60 02 00 24 	\[MII\]       addl r12=24,r1
+[ 	]*[a-f0-9]+:	00 00 00 02 00 00 	            nop.i 0x0
+[ 	]*[a-f0-9]+:	00 00 04 00       	            nop.i 0x0;;
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/merge5.s b/binutils-2.19/ld/testsuite/ld-ia64/merge5.s
new file mode 100644
index 0000000..81428c4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/merge5.s
@@ -0,0 +1,24 @@
+	.section .rodata.str1.8,"aMS", 1
+.LC1:	.string "foo"
+.LC2:	.string "foo"
+.LC3:	.string "bar"
+.LC4:	.string "bar"
+.LC5:	.string "bar"
+.LC6:	.string "bar"
+.LC7:	.string "baz"
+.LC8:	.string "baz"
+	.section .data.rel.local,"aw"
+	.quad .LC2
+	.quad .LC4
+	.quad .LC6
+	.quad .LC7
+	.section .rodata,"a"
+.LC9:	.string "mumble"
+	.balign 8
+	.space 0x400000
+	.text
+	addl r12=@ltoffx(.LC1),r1 ;;
+	addl r12=@ltoffx(.LC3),r1 ;;
+	addl r12=@ltoffx(.LC5),r1 ;;
+	addl r12=@ltoffx(.LC8),r1 ;;
+	addl r12=@ltoffx(.LC9),r1 ;;
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/tlsbin.dd b/binutils-2.19/ld/testsuite/ld-ia64/tlsbin.dd
new file mode 100644
index 0000000..1c5bc2f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/tlsbin.dd
@@ -0,0 +1,74 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as:
+#ld: -shared
+#objdump: -drj.text
+#target: ia64-*-*
+
+.*: +file format elf..-ia64-.*
+
+Disassembly of section .text:
+
+40+1000 <fn2>:
+40+1000:	10 10 15 06 80 05[ 	]+\[MIB\][ 	]+alloc r34=ar.pfs,5,3,0
+40+1006:	10 02 00 62 00 00[ 	]+mov r33=b0
+40+100c:	00 00 00 20[ 	]+nop.b 0x0
+40+1010:	0d 70 .0 0. 00 24[ 	]+\[MFI\][ 	]+addl r14=(24|32|40|48|56|64),r1
+40+1016:	00 00 00 02 00 e0[ 	]+nop.f 0x0
+40+101c:	.1 0. 00 90[ 	]+addl r15=(24|32|40|48|56|64),r1;;
+40+1020:	19 18 01 1c 18 10[ 	]+\[MMB\][ 	]+ld8 r35=\[r14\]
+40+1026:	40 02 3c 30 20 00[ 	]+ld8 r36=\[r15\]
+40+102c:	[0-9a-f 	]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
+40+1030:	0d 70 .0 0. 00 24[ 	]+\[MFI\][ 	]+addl r14=(24|32|40|48|56|64),r1
+40+1036:	00 00 00 02 00 e0[ 	]+nop.f 0x0
+40+103c:	.1 0. 00 90[ 	]+addl r15=(24|32|40|48|56|64),r1;;
+40+1040:	19 18 01 1c 18 10[ 	]+\[MMB\][ 	]+ld8 r35=\[r14\]
+40+1046:	40 02 3c 30 20 00[ 	]+ld8 r36=\[r15\]
+40+104c:	[0-9a-f 	]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
+40+1050:	0d 70 .0 0. 00 24[ 	]+\[MFI\][ 	]+addl r14=(24|32|40|48|56|64),r1
+40+1056:	00 00 00 02 00 80[ 	]+nop.f 0x0
+40+105c:	14 02 00 90[ 	]+mov r36=33;;
+40+1060:	1d 18 01 1c 18 10[ 	]+\[MFB\][ 	]+ld8 r35=\[r14\]
+40+1066:	00 00 00 02 00 00[ 	]+nop.f 0x0
+40+106c:	[0-9a-f 	]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
+40+1070:	0d 70 .0 0. 00 24[ 	]+\[MFI\][ 	]+addl r14=(24|32|40|48|56|64),r1
+40+1076:	00 00 00 02 00 80[ 	]+nop.f 0x0
+40+107c:	04 00 00 84[ 	]+mov r36=r0;;
+40+1080:	1d 18 01 1c 18 10[ 	]+\[MFB\][ 	]+ld8 r35=\[r14\]
+40+1086:	00 00 00 02 00 00[ 	]+nop.f 0x0
+40+108c:	[0-9a-f 	]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
+40+1090:	0b 10 00 10 00 21[ 	]+\[MMI\][ 	]+mov r2=r8;;
+40+1096:	e0 00 0a 00 48 e0[ 	]+addl r14=64,r2
+40+109c:	61 14 00 90[ 	]+addl r15=70,r2;;
+40+10a0:	05 70 2c 11 00 21[ 	]+\[MLX\][ 	]+adds r14=75,r8
+40+10a6:	00 00 00 00 00 e0[ 	]+movl r15=0x4d;;
+40+10ac:	d1 04 00 60 
+40+10b0:	0a 78 3c 10 00 20[ 	]+\[MMI\][ 	]+add r15=r15,r8;;
+40+10b6:	00 00 00 02 00 00[ 	]+nop.m 0x0
+40+10bc:	20 02 aa 00[ 	]+mov.i ar.pfs=r34
+40+10c0:	11 00 00 00 01 00[ 	]+\[MIB\][ 	]+nop.m 0x0
+40+10c6:	00 08 05 80 03 80[ 	]+mov b0=r33
+40+10cc:	08 00 84 00[ 	]+br.ret.sptk.many b0;;
+
+40+10d0 <_start>:
+40+10d0:	0b 70 .0 0. 00 24[ 	]+\[MMI\][ 	]+addl r14=(24|32|40|48|56|64),r1;;
+40+10d6:	e0 00 38 30 20 00[ 	]+ld8 r14=\[r14\]
+40+10dc:	00 00 04 00[ 	]+nop.i 0x0;;
+40+10e0:	0b 70 38 1a 00 20[ 	]+\[MMI\][ 	]+add r14=r14,r13;;
+40+10e6:	e0 .0 0. 00 48 00[ 	]+addl r14=(24|32|40|48|56|64),r1
+40+10ec:	00 00 04 00[ 	]+nop.i 0x0;;
+40+10f0:	0b 70 00 1c 18 10[ 	]+\[MMI\][ 	]+ld8 r14=\[r14\];;
+40+10f6:	e0 70 34 00 40 00[ 	]+add r14=r14,r13
+40+10fc:	00 00 04 00[ 	]+nop.i 0x0;;
+40+1100:	0b 10 00 1a 00 21[ 	]+\[MMI\][ 	]+mov r2=r13;;
+40+1106:	e0 80 08 00 48 e0[ 	]+addl r14=16,r2
+40+110c:	61 11 04 90[ 	]+addl r15=150,r2;;
+40+1110:	05 70 5c 1b 00 21[ 	]+\[MLX\][ 	]+adds r14=87,r13
+40+1116:	00 00 00 00 00 e0[ 	]+movl r15=0x95;;
+40+111c:	51 01 04 60 
+40+1120:	0a 78 3c 1a 00 20[ 	]+\[MMI\][ 	]+add r15=r15,r13;;
+40+1126:	00 00 00 02 00 00[ 	]+nop.m 0x0
+40+112c:	00 00 04 00[ 	]+nop.i 0x0
+40+1130:	1d 00 00 00 01 00[ 	]+\[MFB\][ 	]+nop.m 0x0
+40+1136:	00 00 00 02 00 80[ 	]+nop.f 0x0
+40+113c:	08 00 84 00[ 	]+br.ret.sptk.many b0;;
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/tlsbin.rd b/binutils-2.19/ld/testsuite/ld-ia64/tlsbin.rd
new file mode 100644
index 0000000..7f130a4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/tlsbin.rd
@@ -0,0 +1,136 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as:
+#ld: -shared
+#readelf: -WSsrl
+#target: ia64-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0
+ +\[[ 0-9]+\] .interp +.*
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .rela.IA_64.pltof +.*
+ +\[[ 0-9]+\] .plt +.*
+ +\[[ 0-9]+\] .text +PROGBITS +40+1000 0+1000 0+140 00 +AX +0 +0 4096
+ +\[[ 0-9]+\] .IA_64.unwind_inf +.*
+ +\[[ 0-9]+\] .IA_64.unwind +.*
+ +\[[ 0-9]+\] .tdata +PROGBITS +60+1[0-9a-f]+ 0+1[0-9a-f]+ 0+60 00 WAT +0 +0 +4
+ +\[[ 0-9]+\] .tbss +NOBITS +60+1[0-9a-f]+ 0+1[0-9a-f]+ 0+40 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +60+1[0-9a-f]+ 0+1[0-9a-f]+ 0+150 10 +WA +4 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +60+1318 0+1318 0+48 00 WAp +0 +0 +8
+ +\[[ 0-9]+\] .IA_64.pltoff +.*
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+#...
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x40+10d0
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  PHDR +0x0+40 0x40+40 0x40+40 0x0+188 0x0+188 R E 0x8
+  INTERP +0x0+1c8 0x40+1c8 0x40+1c8 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x1
+.*Requesting program interpreter.*
+  LOAD +0x0+ 0x40+ 0x40+ 0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ R E 0x10000
+  LOAD +0x0+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x0+0[0-9a-f]+ 0x0+0[0-9a-f]+ RW +0x10000
+  DYNAMIC +0x0+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x0+150 0x0+150 RW +0x8
+  TLS +0x0+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x60+1[0-9a-f]+ 0x0+60 0x0+a0 R +0x4
+  IA_64_UNWIND .* R +0x8
+#...
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 3 entries:
+ +Offset +Info +Type +Symbol's Value  Symbol's Name \+ Addend
+[0-9a-f ]+R_IA64_TPREL64LSB +0+ sG2 \+ 0
+[0-9a-f ]+R_IA64_DTPMOD64LSB +0+ sG1 \+ 0
+[0-9a-f ]+R_IA64_DTPREL64LSB +0+ sG1 \+ 0
+
+Relocation section '.rela.IA_64.pltoff' at offset 0x[0-9a-f]+ contains 1 entries:
+ +Offset +Info +Type +Symbol's Value  Symbol's Name \+ Addend
+[0-9a-f ]+R_IA64_IPLTLSB +0+ __tls_get_addr \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* TLS +GLOBAL DEFAULT +UND sG2
+.* FUNC +GLOBAL DEFAULT +UND __tls_get_addr
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +UND sG1
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +1 *
+.* SECTION LOCAL +DEFAULT +2 *
+.* SECTION LOCAL +DEFAULT +3 *
+.* SECTION LOCAL +DEFAULT +4 *
+.* SECTION LOCAL +DEFAULT +5 *
+.* SECTION LOCAL +DEFAULT +6 *
+.* SECTION LOCAL +DEFAULT +7 *
+.* SECTION LOCAL +DEFAULT +8 *
+.* SECTION LOCAL +DEFAULT +9 *
+.* SECTION LOCAL +DEFAULT +10 *
+.* SECTION LOCAL +DEFAULT +11 *
+.* SECTION LOCAL +DEFAULT +12 *
+.* SECTION LOCAL +DEFAULT +13 *
+.* SECTION LOCAL +DEFAULT +14 *
+.* SECTION LOCAL +DEFAULT +15 *
+.* TLS +LOCAL +DEFAULT +11 sl1
+.* TLS +LOCAL +DEFAULT +11 sl2
+.* TLS +LOCAL +DEFAULT +11 sl3
+.* TLS +LOCAL +DEFAULT +11 sl4
+.* TLS +LOCAL +DEFAULT +11 sl5
+.* TLS +LOCAL +DEFAULT +11 sl6
+.* TLS +LOCAL +DEFAULT +11 sl7
+.* TLS +LOCAL +DEFAULT +11 sl8
+.* TLS +LOCAL +DEFAULT +12 bl1
+.* TLS +LOCAL +DEFAULT +12 bl2
+.* TLS +LOCAL +DEFAULT +12 bl3
+.* TLS +LOCAL +DEFAULT +12 bl4
+.* TLS +LOCAL +DEFAULT +12 bl5
+.* TLS +LOCAL +DEFAULT +12 bl6
+.* TLS +LOCAL +DEFAULT +12 bl7
+.* TLS +LOCAL +DEFAULT +12 bl8
+.* OBJECT +LOCAL +HIDDEN +13 _DYNAMIC
+.* OBJECT +LOCAL +HIDDEN +14 _GLOBAL_OFFSET_TABLE_
+.* TLS +GLOBAL DEFAULT +11 sg8
+.* TLS +GLOBAL DEFAULT +12 bg8
+.* TLS +GLOBAL DEFAULT +12 bg6
+.* TLS +GLOBAL DEFAULT +12 bg3
+.* TLS +GLOBAL DEFAULT +11 sg3
+.* TLS +GLOBAL HIDDEN +11 sh3
+.* TLS +GLOBAL DEFAULT +UND sG2
+.* TLS +GLOBAL DEFAULT +11 sg4
+.* TLS +GLOBAL DEFAULT +11 sg5
+.* TLS +GLOBAL DEFAULT +12 bg5
+.* FUNC +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL HIDDEN +11 sh7
+.* TLS +GLOBAL HIDDEN +11 sh8
+.* TLS +GLOBAL DEFAULT +11 sg1
+.* FUNC +GLOBAL DEFAULT +8 _start
+.* TLS +GLOBAL HIDDEN +11 sh4
+.* TLS +GLOBAL DEFAULT +12 bg7
+.* TLS +GLOBAL HIDDEN +11 sh5
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* FUNC +GLOBAL DEFAULT +8 fn2
+.* TLS +GLOBAL DEFAULT +11 sg2
+.* TLS +GLOBAL DEFAULT +UND sG1
+.* TLS +GLOBAL HIDDEN +11 sh1
+.* TLS +GLOBAL DEFAULT +11 sg6
+.* TLS +GLOBAL DEFAULT +11 sg7
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* TLS +GLOBAL HIDDEN +11 sh2
+.* TLS +GLOBAL HIDDEN +11 sh6
+.* TLS +GLOBAL DEFAULT +12 bg2
+.* TLS +GLOBAL DEFAULT +12 bg1
+.* TLS +GLOBAL DEFAULT +12 bg4
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/tlsbin.s b/binutils-2.19/ld/testsuite/ld-ia64/tlsbin.s
new file mode 100644
index 0000000..7b5f34a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/tlsbin.s
@@ -0,0 +1,54 @@
+	.section ".tbss", "awT", @nobits
+	.globl bg1, bg2, bg3, bg4, bg5, bg6, bg7, bg8
+bg1:	.space 4
+bg2:	.space 4
+bg3:	.space 4
+bg4:	.space 4
+bg5:	.space 4
+bg6:	.space 4
+bg7:	.space 4
+bg8:	.space 4
+bl1:	.space 4
+bl2:	.space 4
+bl3:	.space 4
+bl4:	.space 4
+bl5:	.space 4
+bl6:	.space 4
+bl7:	.space 4
+bl8:	.space 4
+	.explicit
+	.pred.safe_across_calls p1-p5,p16-p63
+	.text
+	.globl	_start#
+	.proc	_start#
+_start:
+	/* IE */
+	addl	r14 = @ltoff(@tprel(sG2#)), gp
+	;;
+	ld8	r14 = [r14]
+	;;
+	add	r14 = r14, r13
+	;;
+
+	/* IE against global symbol in exec */
+	addl	r14 = @ltoff(@tprel(bl1#)), gp
+	;;
+	ld8	r14 = [r14]
+	;;
+	add	r14 = r14, r13
+	;;
+
+	/* LE */
+	mov	r2 = r13
+	;;
+	addl	r14 = @tprel(sg1#), r2
+	addl	r15 = @tprel(bl2#) + 2, r2
+	;;
+	adds	r14 = @tprel(sh2#) + 3, r13
+	movl	r15 = @tprel(bl2#) + 1
+	;;
+	add	r15 = r15, r13
+	;;
+
+	br.ret.sptk.many b0
+	.endp	_start#
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/tlsbin.sd b/binutils-2.19/ld/testsuite/ld-ia64/tlsbin.sd
new file mode 100644
index 0000000..411eedb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/tlsbin.sd
@@ -0,0 +1,15 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as:
+#ld: -shared
+#objdump: -sj.got
+#target: ia64-*-*
+
+.*: +file format elf..-ia64-.*
+
+Contents of section .got:
+ (60+)?1318 0+ 0+ 0+ 0+  .*
+ (60+)?1328 0+ 0+ 0+ 0+  .*
+ (60+)?1338 0+ 0+ 0+ 0+  .*
+ (60+)?1348 (00|01|24|90)000000 0+ (00|01|24|90)000000 0+  .*
+ (60+)?1358 (00|01|24|90)000000 0+  .*
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/tlsbin.td b/binutils-2.19/ld/testsuite/ld-ia64/tlsbin.td
new file mode 100644
index 0000000..1e724e7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/tlsbin.td
@@ -0,0 +1,16 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as:
+#ld: -shared
+#objdump: -sj.tdata
+#target: ia64-*-*
+
+.*: +file format elf..-ia64-.*
+
+Contents of section .tdata:
+ (60+)?1[0-9a-f]+ 11000000 12000000 13000000 14000000  .*
+ (60+)?1[0-9a-f]+ 15000000 16000000 17000000 18000000  .*
+ (60+)?1[0-9a-f]+ 41000000 42000000 43000000 44000000  .*
+ (60+)?1[0-9a-f]+ 45000000 46000000 47000000 48000000  .*
+ (60+)?1[0-9a-f]+ 01010000 02010000 03010000 04010000  .*
+ (60+)?1[0-9a-f]+ 05010000 06010000 07010000 08010000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/tlsbinpic.s b/binutils-2.19/ld/testsuite/ld-ia64/tlsbinpic.s
new file mode 100644
index 0000000..f061343
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/tlsbinpic.s
@@ -0,0 +1,97 @@
+	/* Force .data aligned to 4K, so that .got very likely gets at
+	   0x60000000000031b0 (0x60 bytes .tdata and 0x150 bytes
+	   .dynamic).  */
+	.data
+	.balign	4096
+	.section ".tdata", "awT", @progbits
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+	.explicit
+	.pred.safe_across_calls p1-p5,p16-p63
+	/* Force .text aligned to 4K, so it very likely gets at
+	   0x4000000000001000.  */
+	.text
+	.balign	4096
+	.globl	fn2#
+	.proc	fn2#
+fn2:
+	.prologue 12, 33
+	.mib
+	.save	ar.pfs, r34
+	alloc	r34 = ar.pfs, 0, 3, 2, 0
+	.save	rp, r33
+	mov	r33 = b0
+
+	/* GD */
+	addl	r14 = @ltoff(@dtpmod(sG1#)), gp
+	addl	r15 = @ltoff(@dtprel(sG1#)), gp
+	;;
+	ld8	out0 = [r14]
+	ld8	out1 = [r15]
+	br.call.sptk.many b0 = __tls_get_addr#
+	;;
+
+	/* GD against local symbol */
+	addl	r14 = @ltoff(@dtpmod(sl2#)), gp
+	addl	r15 = @ltoff(@dtprel(sl2#)), gp
+	;;
+	ld8	out0 = [r14]
+	ld8	out1 = [r15]
+	br.call.sptk.many b0 = __tls_get_addr#
+	;;
+
+	/* LD */
+	addl	r14 = @ltoff(@dtpmod(sl1#)), gp
+	addl	out1 = @dtprel(sl1#) + 1, r0
+	;;
+	ld8	out0 = [r14]
+	br.call.sptk.many b0 = __tls_get_addr#
+	;;
+
+	/* LD with 4 variables variables */
+	addl	r14 = @ltoff(@dtpmod(sh1#)), gp
+	mov	out1 = r0
+	;;
+	ld8	out0 = [r14]
+	br.call.sptk.many b0 = __tls_get_addr#
+	;;
+	mov	r2 = r8
+	;;
+	addl	r14 = @dtprel(sh1#), r2
+	addl	r15 = @dtprel(sh2#) + 2, r2
+	;;
+	adds	r14 = @dtprel(sh3#) + 3, r8
+	movl	r15 = @dtprel(sh4#) + 1
+	;;
+	add	r15 = r15, r8
+	;;
+
+	mov	ar.pfs = r34
+	mov	b0 = r33
+	br.ret.sptk.many b0
+	.endp	fn2#
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/tlsg.s b/binutils-2.19/ld/testsuite/ld-ia64/tlsg.s
new file mode 100644
index 0000000..fa3fce0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/tlsg.s
@@ -0,0 +1,14 @@
+	.section	.tbss,"awT",@nobits
+	.align 4
+	.skip	24
+	.type	a#,@object
+	.size	a#,4
+a:
+	data4	0
+	.text
+	.globl	_start#
+	.proc	_start#
+_start:
+	.endp	_start#
+	.section	.debug_foobar
+	data8	@dtprel(a#)
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/tlsg.sd b/binutils-2.19/ld/testsuite/ld-ia64/tlsg.sd
new file mode 100644
index 0000000..67bc9cd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/tlsg.sd
@@ -0,0 +1,10 @@
+#source: tlsg.s
+#as:
+#ld:
+#objdump: -sj.debug_foobar
+#target: ia64-*-*
+
+.*: +file format elf..-ia64-.*
+
+Contents of section .debug_foobar:
+ 0+ 18000000 0+  +.*
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/tlslib.s b/binutils-2.19/ld/testsuite/ld-ia64/tlslib.s
new file mode 100644
index 0000000..d0e63fe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/tlslib.s
@@ -0,0 +1,18 @@
+	.section ".tdata", "awT", @progbits
+	.globl sG1, sG2, sG3, sG4, sG5, sG6, sG7, sG8
+sG1:	.long 513
+sG2:	.long 514
+sG3:	.long 515
+sG4:	.long 516
+sG5:	.long 517
+sG6:	.long 518
+sG7:	.long 519
+sG8:	.long 520
+
+	.text
+	/* Dummy.  */
+	.globl	__tls_get_addr#
+	.proc	__tls_get_addr#
+__tls_get_addr:
+	br.ret.sptk.many b0
+	.endp   __tls_get_addr#
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/tlspic.dd b/binutils-2.19/ld/testsuite/ld-ia64/tlspic.dd
new file mode 100644
index 0000000..32850f0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/tlspic.dd
@@ -0,0 +1,64 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as:
+#ld:
+#objdump: -drj.text
+#target: ia64-*-*
+
+.*: +file format elf..-ia64-.*
+
+Disassembly of section .text:
+
+0+1000 <fn1>:
+ +1000:	10 10 15 06 80 05[ 	]+\[MIB\] +alloc r34=ar.pfs,5,3,0
+ +1006:	10 02 00 62 00 00[ 	]+mov r33=b0
+ +100c:	00 00 00 20[ 	]+nop.b 0x0
+ +1010:	0d 70 60 02 00 24[ 	]+\[MFI\] +addl r14=24,r1
+ +1016:	00 00 00 02 00 e0[ 	]+nop.f 0x0
+ +101c:	01 0a 00 90[ 	]+addl r15=32,r1;;
+ +1020:	19 18 01 1c 18 10[ 	]+\[MMB\] +ld8 r35=\[r14\]
+ +1026:	40 02 3c 30 20 00[ 	]+ld8 r36=\[r15\]
+ +102c:	[0-9a-f 	]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
+ +1030:	0d 70 c0 02 00 24[ 	]+\[MFI\] +addl r14=48,r1
+ +1036:	00 00 00 02 00 e0[ 	]+nop.f 0x0
+ +103c:	01 0c 00 90[ 	]+addl r15=64,r1;;
+ +1040:	19 18 01 1c 18 10[ 	]+\[MMB\] +ld8 r35=\[r14\]
+ +1046:	40 02 3c 30 20 00[ 	]+ld8 r36=\[r15\]
+ +104c:	[0-9a-f 	]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
+ +1050:	0d 70 c0 02 00 24[ 	]+\[MFI\] +addl r14=48,r1
+ +1056:	00 00 00 02 00 80[ 	]+nop.f 0x0
+ +105c:	14 02 00 90[ 	]+mov r36=33;;
+ +1060:	1d 18 01 1c 18 10[ 	]+\[MFB\] +ld8 r35=\[r14\]
+ +1066:	00 00 00 02 00 00[ 	]+nop.f 0x0
+ +106c:	[0-9a-f 	]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
+ +1070:	0d 70 c0 02 00 24[ 	]+\[MFI\] +addl r14=48,r1
+ +1076:	00 00 00 02 00 80[ 	]+nop.f 0x0
+ +107c:	04 00 00 84[ 	]+mov r36=r0;;
+ +1080:	1d 18 01 1c 18 10[ 	]+\[MFB\] +ld8 r35=\[r14\]
+ +1086:	00 00 00 02 00 00[ 	]+nop.f 0x0
+ +108c:	[0-9a-f 	]+br.call.sptk.many b0=[0-9a-f]+ <.*>;;
+ +1090:	0b 10 00 10 00 21[ 	]+\[MMI\] +mov r2=r8;;
+ +1096:	e0 00 0a 00 48 e0[ 	]+addl r14=64,r2
+ +109c:	21 16 00 90[ 	]+addl r15=98,r2;;
+ +10a0:	05 70 4c 11 00 21[ 	]+\[MLX\] +adds r14=83,r8
+ +10a6:	00 00 00 00 00 e0[ 	]+movl r15=0x71;;
+ +10ac:	11 07 00 60 
+ +10b0:	0b 78 3c 10 00 20[ 	]+\[MMI\] +add r15=r15,r8;;
+ +10b6:	e0 40 05 00 48 00[ 	]+addl r14=40,r1
+ +10bc:	00 00 04 00[ 	]+nop.i 0x0;;
+ +10c0:	0b 78 00 1c 18 10[ 	]+\[MMI\] +ld8 r15=\[r14\];;
+ +10c6:	e0 78 34 00 40 00[ 	]+add r14=r15,r13
+ +10cc:	00 00 04 00[ 	]+nop.i 0x0;;
+ +10d0:	0d 70 20 03 00 24[ 	]+\[MFI\] +addl r14=72,r1
+ +10d6:	00 00 00 02 00 e0[ 	]+nop.f 0x0
+ +10dc:	81 0b 00 90[ 	]+addl r15=56,r1;;
+ +10e0:	09 70 00 1c 18 10[ 	]+\[MMI\] +ld8 r14=\[r14\]
+ +10e6:	f0 00 3c 30 20 00[ 	]+ld8 r15=\[r15\]
+ +10ec:	00 00 04 00[ 	]+nop.i 0x0;;
+ +10f0:	02 70 38 1a 00 20[ 	]+\[MII\] +add r14=r14,r13
+ +10f6:	f0 78 34 00 40 00[ 	]+add r15=r15,r13;;
+ +10fc:	20 02 aa 00[ 	]+mov.i ar.pfs=r34
+ +1100:	11 00 00 00 01 00[ 	]+\[MIB\] +nop.m 0x0
+ +1106:	00 08 05 80 03 80[ 	]+mov b0=r33
+ +110c:	08 00 84 00[ 	]+br.ret.sptk.many b0;;
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/tlspic.rd b/binutils-2.19/ld/testsuite/ld-ia64/tlspic.rd
new file mode 100644
index 0000000..509e598
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/tlspic.rd
@@ -0,0 +1,131 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as:
+#ld: -shared
+#readelf: -WSsrl
+#target: ia64-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .rela.IA_64.pltof +.*
+ +\[[ 0-9]+\] .plt +.*
+ +\[[ 0-9]+\] .text +PROGBITS +0+1000 0+1000 0+110 00 +AX +0 +0 4096
+ +\[[ 0-9]+\] .IA_64.unwind_inf +.*
+ +\[[ 0-9]+\] .IA_64.unwind +.*
+ +\[[ 0-9]+\] .tdata +PROGBITS +0+11[0-9a-f]+ 0+1[0-9a-f]+ 0+60 00 WAT +0 +0 +4
+ +\[[ 0-9]+\] .tbss +NOBITS +0+11[0-9a-f]+ 0+1[0-9a-f]+ 0+20 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+11[0-9a-f]+ 0+1[0-9a-f]+ 0+140 10 +WA +3 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+112d8 0+12d8 0+50 00 WAp +0 +0 +8
+ +\[[ 0-9]+\] .IA_64.pltoff +.*
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+Key to Flags:
+#...
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x1000
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  LOAD +0x0+ 0x0+ 0x0+ 0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ R E 0x10000
+  LOAD +0x0+1[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+0[0-9a-f]+ 0x0+0[0-9a-f]+ RW +0x10000
+  DYNAMIC +0x0+1[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+140 0x0+140 RW +0x8
+  TLS +0x0+1[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+11[0-9a-f]+ 0x0+60 0x0+80 R +0x4
+  IA_64_UNWIND +0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ 0x0+1[0-9a-f]+ 0x0+18 0x0+18 R +0x8
+#...
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 6 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_IA64_DTPMOD64LSB +0+ sg1 \+ 0
+[0-9a-f ]+R_IA64_DTPREL64LSB +0+ sg1 \+ 0
+[0-9a-f ]+R_IA64_TPREL64LSB +0+4 sg2 \+ 0
+[0-9a-f ]+R_IA64_DTPMOD64LSB +0+
+[0-9a-f ]+R_IA64_TPREL64LSB +0+44
+[0-9a-f ]+R_IA64_TPREL64LSB +0+24
+
+Relocation section '.rela.IA_64.pltoff' at offset 0x[0-9a-f]+ contains 1 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_IA64_IPLTLSB +0+ __tls_get_addr \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* TLS +GLOBAL DEFAULT +10 sg8
+.* TLS +GLOBAL DEFAULT +10 sg3
+.* TLS +GLOBAL DEFAULT +10 sg4
+.* TLS +GLOBAL DEFAULT +10 sg5
+.* NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +10 sg1
+.* FUNC +GLOBAL DEFAULT +7 fn1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +10 sg2
+.* TLS +GLOBAL DEFAULT +10 sg6
+.* TLS +GLOBAL DEFAULT +10 sg7
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +1 *
+.* SECTION LOCAL +DEFAULT +2 *
+.* SECTION LOCAL +DEFAULT +3 *
+.* SECTION LOCAL +DEFAULT +4 *
+.* SECTION LOCAL +DEFAULT +5 *
+.* SECTION LOCAL +DEFAULT +6 *
+.* SECTION LOCAL +DEFAULT +7 *
+.* SECTION LOCAL +DEFAULT +8 *
+.* SECTION LOCAL +DEFAULT +9 *
+.* SECTION LOCAL +DEFAULT +10 *
+.* SECTION LOCAL +DEFAULT +11 *
+.* SECTION LOCAL +DEFAULT +12 *
+.* SECTION LOCAL +DEFAULT +13 *
+.* SECTION LOCAL +DEFAULT +14 *
+.* TLS +LOCAL +DEFAULT +10 sl1
+.* TLS +LOCAL +DEFAULT +10 sl2
+.* TLS +LOCAL +DEFAULT +10 sl3
+.* TLS +LOCAL +DEFAULT +10 sl4
+.* TLS +LOCAL +DEFAULT +10 sl5
+.* TLS +LOCAL +DEFAULT +10 sl6
+.* TLS +LOCAL +DEFAULT +10 sl7
+.* TLS +LOCAL +DEFAULT +10 sl8
+.* TLS +LOCAL +HIDDEN +11 sH1
+.* OBJECT +LOCAL +HIDDEN +ABS _DYNAMIC
+.* TLS +LOCAL +HIDDEN +10 sh3
+.* TLS +LOCAL +HIDDEN +11 sH2
+.* TLS +LOCAL +HIDDEN +11 sH7
+.* TLS +LOCAL +HIDDEN +10 sh7
+.* TLS +LOCAL +HIDDEN +10 sh8
+.* TLS +LOCAL +HIDDEN +11 sH4
+.* TLS +LOCAL +HIDDEN +10 sh4
+.* TLS +LOCAL +HIDDEN +11 sH3
+.* TLS +LOCAL +HIDDEN +10 sh5
+.* TLS +LOCAL +HIDDEN +11 sH5
+.* TLS +LOCAL +HIDDEN +11 sH6
+.* TLS +LOCAL +HIDDEN +11 sH8
+.* TLS +LOCAL +HIDDEN +10 sh1
+.* OBJECT +LOCAL +HIDDEN +ABS _GLOBAL_OFFSET_TABLE_
+.* TLS +LOCAL +HIDDEN +10 sh2
+.* TLS +LOCAL +HIDDEN +10 sh6
+.* TLS +GLOBAL DEFAULT +10 sg8
+.* TLS +GLOBAL DEFAULT +10 sg3
+.* TLS +GLOBAL DEFAULT +10 sg4
+.* TLS +GLOBAL DEFAULT +10 sg5
+.* NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +10 sg1
+.* FUNC +GLOBAL DEFAULT +7 fn1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +10 sg2
+.* TLS +GLOBAL DEFAULT +10 sg6
+.* TLS +GLOBAL DEFAULT +10 sg7
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/tlspic.sd b/binutils-2.19/ld/testsuite/ld-ia64/tlspic.sd
new file mode 100644
index 0000000..7b03a08
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/tlspic.sd
@@ -0,0 +1,15 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as:
+#ld: -shared
+#objdump: -sj.got
+#target: ia64-*-*
+
+.*: +file format elf..-ia64-.*
+
+Contents of section .got:
+ 112d8 0+ 0+ 0+ 0+  .*
+ 112e8 0+ 0+ [0-9a-f]+ [0-9a-f]+  .*
+ 112f8 [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ [0-9a-f]+  .*
+ 11308 [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ [0-9a-f]+  .*
+ 11318 440+ 0+ [0-9a-f]+ [0-9a-f]+  .*
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/tlspic.td b/binutils-2.19/ld/testsuite/ld-ia64/tlspic.td
new file mode 100644
index 0000000..47b5b6c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/tlspic.td
@@ -0,0 +1,16 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as:
+#ld: -shared
+#objdump: -sj.tdata
+#target: ia64-*-*
+
+.*: +file format elf..-ia64-.*
+
+Contents of section .tdata:
+ 11[0-9a-f]+ 11000000 12000000 13000000 14000000  .*
+ 11[0-9a-f]+ 15000000 16000000 17000000 18000000  .*
+ 11[0-9a-f]+ 41000000 42000000 43000000 44000000  .*
+ 11[0-9a-f]+ 45000000 46000000 47000000 48000000  .*
+ 11[0-9a-f]+ 01010000 02010000 03010000 04010000  .*
+ 11[0-9a-f]+ 05010000 06010000 07010000 08010000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/tlspic1.s b/binutils-2.19/ld/testsuite/ld-ia64/tlspic1.s
new file mode 100644
index 0000000..5242d28
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/tlspic1.s
@@ -0,0 +1,114 @@
+	/* Force .data aligned to 4K, so .got very likely gets at 0x13190
+	   (0x60 bytes .tdata and 0x130 bytes .dynamic)  */
+	.data
+	.balign 4096
+	.section ".tdata", "awT", @progbits
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+	.explicit
+	.pred.safe_across_calls p1-p5,p16-p63
+	/* Force .text aligned to 4K, so it very likely gets at 0x1000.  */
+	.text
+	.balign	4096
+	.globl	fn1#
+	.proc	fn1#
+fn1:
+	.prologue 12, 33
+	.mib
+	.save	ar.pfs, r34
+	alloc	r34 = ar.pfs, 0, 3, 2, 0
+	.save	rp, r33
+	mov	r33 = b0
+
+	/* GD */
+	addl	r14 = @ltoff(@dtpmod(sg1#)), gp
+	addl	r15 = @ltoff(@dtprel(sg1#)), gp
+	;;
+	ld8	out0 = [r14]
+	ld8	out1 = [r15]
+	br.call.sptk.many b0 = __tls_get_addr#
+	;;
+
+	/* GD against hidden symbol */
+	addl	r14 = @ltoff(@dtpmod(sh2#)), gp
+	addl	r15 = @ltoff(@dtprel(sh2#)), gp
+	;;
+	ld8	out0 = [r14]
+	ld8	out1 = [r15]
+	br.call.sptk.many b0 = __tls_get_addr#
+	;;
+
+	/* LD */
+	addl	r14 = @ltoff(@dtpmod(sl1#)), gp
+	addl	out1 = @dtprel(sl1#) + 1, r0
+	;;
+	ld8	out0 = [r14]
+	br.call.sptk.many b0 = __tls_get_addr#
+	;;
+
+	/* LD with 4 variables variables */
+	addl	r14 = @ltoff(@dtpmod(sh1#)), gp
+	mov	out1 = r0
+	;;
+	ld8	out0 = [r14]
+	br.call.sptk.many b0 = __tls_get_addr#
+	;;
+	mov	r2 = r8
+	;;
+	addl	r14 = @dtprel(sh1#), r2
+	addl	r15 = @dtprel(sH1#) + 2, r2
+	;;
+	adds	r14 = @dtprel(sh5#) + 3, r8
+	movl	r15 = @dtprel(sH5#) + 1
+	;;
+	add	r15 = r15, r8
+	;;
+
+	/* IE against global */
+	addl	r14 = @ltoff(@tprel(sg2#)), gp
+	;;
+	ld8	r15 = [r14]
+	;;
+	add	r14 = r15, r13
+	;;
+
+	/* IE against local and hidden */
+	addl	r14 = @ltoff(@tprel(sl2#)), gp
+	addl	r15 = @ltoff(@tprel(sh2#)), gp
+	;;
+	ld8	r14 = [r14]
+	ld8	r15 = [r15]
+	;;
+	add	r14 = r14, r13
+	add	r15 = r15, r13
+	;;
+
+	mov	ar.pfs = r34
+	mov	b0 = r33
+	br.ret.sptk.many b0
+	.endp	fn1#
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/tlspic2.s b/binutils-2.19/ld/testsuite/ld-ia64/tlspic2.s
new file mode 100644
index 0000000..5513f9b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/tlspic2.s
@@ -0,0 +1,11 @@
+	.section ".tbss", "awT", @nobits
+	.globl sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+	.hidden sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+sH1:	.space 4
+sH2:	.space 4
+sH3:	.space 4
+sH4:	.space 4
+sH5:	.space 4
+sH6:	.space 4
+sH7:	.space 4
+sH8:	.space 4
diff --git a/binutils-2.19/ld/testsuite/ld-ia64/undefined.s b/binutils-2.19/ld/testsuite/ld-ia64/undefined.s
new file mode 100644
index 0000000..d563c62
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-ia64/undefined.s
@@ -0,0 +1,152 @@
+	.file	"undefined.c"
+	.pred.safe_across_calls p1-p5,p16-p63
+	.section	.debug_abbrev,"",@progbits
+.Ldebug_abbrev0:
+	.section	.debug_info,"",@progbits
+.Ldebug_info0:
+	.section	.debug_line,"",@progbits
+.Ldebug_line0:
+	.text
+.Ltext0:
+	.align 16
+	.global function#
+	.proc function#
+function:
+[.LFB2:]
+	.file 1 "undefined.c"
+	.loc 1 8 0
+	.prologue 12, 32
+	.mii
+	.save ar.pfs, r33
+	alloc r33 = ar.pfs, 0, 3, 0, 0
+	.save rp, r32
+	mov r32 = b0
+	mov r34 = r1
+	.body
+	.loc 1 9 0
+	;;
+	.mib
+	nop 0
+	nop 0
+	br.call.sptk.many b0 = this_function_is_not_defined#
+	.loc 1 10 0
+	;;
+	.loc 1 9 0
+	.mmi
+	nop 0
+	mov r1 = r34
+	.loc 1 10 0
+	mov b0 = r32
+	.mib
+	nop 0
+	mov ar.pfs = r33
+	br.ret.sptk.many b0
+.LFE2:
+	.endp function#
+.Letext0:
+	.section	.debug_info
+	data4.ua	0x4c
+	data2.ua	0x2
+	data4.ua	@secrel(.Ldebug_abbrev0)
+	data1	0x8
+	.uleb128 0x1
+	data4.ua	@secrel(.Ldebug_line0)
+	data8.ua	.Letext0
+	data8.ua	.Ltext0
+	data4.ua	@secrel(.LASF0)
+	data1	0x1
+	data4.ua	@secrel(.LASF1)
+	.uleb128 0x2
+	data1	0x1
+	data4.ua	@secrel(.LASF2)
+	data1	0x1
+	data1	0x8
+	data4.ua	0x48
+	data8.ua	.LFB2
+	data8.ua	.LFE2
+	data1	0x2
+	data1	0x7c
+	.sleb128 16
+	.uleb128 0x3
+	stringz	"int"
+	data1	0x4
+	data1	0x5
+	data1	0x0
+	.section	.debug_abbrev
+	.uleb128 0x1
+	.uleb128 0x11
+	data1	0x1
+	.uleb128 0x10
+	.uleb128 0x6
+	.uleb128 0x12
+	.uleb128 0x1
+	.uleb128 0x11
+	.uleb128 0x1
+	.uleb128 0x25
+	.uleb128 0xe
+	.uleb128 0x13
+	.uleb128 0xb
+	.uleb128 0x3
+	.uleb128 0xe
+	data1	0x0
+	data1	0x0
+	.uleb128 0x2
+	.uleb128 0x2e
+	data1	0x0
+	.uleb128 0x3f
+	.uleb128 0xc
+	.uleb128 0x3
+	.uleb128 0xe
+	.uleb128 0x3a
+	.uleb128 0xb
+	.uleb128 0x3b
+	.uleb128 0xb
+	.uleb128 0x49
+	.uleb128 0x13
+	.uleb128 0x11
+	.uleb128 0x1
+	.uleb128 0x12
+	.uleb128 0x1
+	.uleb128 0x40
+	.uleb128 0xa
+	data1	0x0
+	data1	0x0
+	.uleb128 0x3
+	.uleb128 0x24
+	data1	0x0
+	.uleb128 0x3
+	.uleb128 0x8
+	.uleb128 0xb
+	.uleb128 0xb
+	.uleb128 0x3e
+	.uleb128 0xb
+	data1	0x0
+	data1	0x0
+	data1	0x0
+	.section	.debug_pubnames,"",@progbits
+	data4.ua	0x1b
+	data2.ua	0x2
+	data4.ua	@secrel(.Ldebug_info0)
+	data4.ua	0x50
+	data4.ua	0x29
+	stringz	"function"
+	data4.ua	0x0
+	.section	.debug_aranges,"",@progbits
+	data4.ua	0x2c
+	data2.ua	0x2
+	data4.ua	@secrel(.Ldebug_info0)
+	data1	0x8
+	data1	0x0
+	data2.ua	0x0
+	data2.ua	0x0
+	data8.ua	.Ltext0
+	data8.ua	.Letext0-.Ltext0
+	data8.ua	0x0
+	data8.ua	0x0
+	.section	.debug_str,"MS",@progbits,1
+.LASF0:
+	stringz	"GNU C 4.1.2"
+.LASF1:
+	stringz	"undefined.c"
+.LASF2:
+	stringz	"function"
diff --git a/binutils-2.19/ld/testsuite/ld-libs/lib-1.s b/binutils-2.19/ld/testsuite/ld-libs/lib-1.s
new file mode 100644
index 0000000..7cc5e1d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-libs/lib-1.s
@@ -0,0 +1,2 @@
+	.globl	foo
+	.set	foo,0x2000
diff --git a/binutils-2.19/ld/testsuite/ld-libs/lib-2.d b/binutils-2.19/ld/testsuite/ld-libs/lib-2.d
new file mode 100644
index 0000000..b055417
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-libs/lib-2.d
@@ -0,0 +1,4 @@
+#...
+0+1000 A bar
+0+2000 A foo
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-libs/lib-2.s b/binutils-2.19/ld/testsuite/ld-libs/lib-2.s
new file mode 100644
index 0000000..af749d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-libs/lib-2.s
@@ -0,0 +1,2 @@
+	.globl	bar
+	.set	bar,0x1000
diff --git a/binutils-2.19/ld/testsuite/ld-libs/libs.exp b/binutils-2.19/ld/testsuite/ld-libs/libs.exp
new file mode 100644
index 0000000..6b64d8c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-libs/libs.exp
@@ -0,0 +1,30 @@
+# Expect script for the linker's -l command line option
+#   Copyright (C) 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+file mkdir tmpdir/libtmp
+
+# Check that -l: works.  The first "test" just creates an object file
+# for the second one.
+run_ld_link_tests {
+    {"-l: test (preparation)" "-r" "" {lib-1.s} {} "libtmp/anobject"}
+    {"-l: test" "-r -Ltmpdir/libtmp -l:anobject" "" {lib-2.s}
+     {{nm -C lib-2.d}} "lib-2"}
+}
diff --git a/binutils-2.19/ld/testsuite/ld-linkonce/linkonce.exp b/binutils-2.19/ld/testsuite/ld-linkonce/linkonce.exp
new file mode 100644
index 0000000..11e159e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-linkonce/linkonce.exp
@@ -0,0 +1,46 @@
+# Expect script for ld linkonce tests
+#   Copyright 2001, 2002, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Hans-Peter Nilsson (hp@axis.com)
+#
+
+# Test for ELF here (or really, .gnu.linkonce functionality), so we don't
+# have to qualify on ELF specifically in every .d-file.
+
+if { ![istarget *-*-linux*] \
+     && ![istarget *-*-gnu] \
+     && ![istarget hppa*64*-*-hpux*] \
+     && ![istarget *-*-elf] } {
+    return
+}
+
+if { [istarget *-*-linux*aout*] \
+     || [istarget *-*-linux*oldld*] } {
+    return
+}
+
+load_lib ld-lib.exp
+
+set rd_test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+for { set i 0 } { $i < [llength $rd_test_list] } { incr i } {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname [lindex $rd_test_list $i]]
+    run_dump_test [file rootname [lindex $rd_test_list $i]]
+}
diff --git a/binutils-2.19/ld/testsuite/ld-linkonce/x.s b/binutils-2.19/ld/testsuite/ld-linkonce/x.s
new file mode 100644
index 0000000..d07f73e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-linkonce/x.s
@@ -0,0 +1,47 @@
+;# Main file, x.s, with the program (_start) referring to two
+;# linkonce functions fn and fn2.  The functions fn and fn2 are
+;# supposed to be equivalent of C++ template instantiations; the
+;# main file instantiates fn.
+
+ .text
+ .global _start
+_start:
+ .long fn
+ .long fn2
+
+ .section .gnu.linkonce.t.fn,"ax",@progbits
+ .weak fn
+ .type fn,@function
+fn:
+.La:
+ .long 1
+ .long 2
+.Lb:
+ .size fn,.Lb-.La
+
+ .section .gcc_except_table,"aw",@progbits
+ .long 2
+ .long .La
+ .long .Lb-.La
+
+ .section .eh_frame,"aw",@progbits
+.Lframe1:
+ .long .LECIE1-.LSCIE1
+.LSCIE1:
+ .long 0x0
+ .byte 0x1
+ .byte 0
+ .uleb128 0x1
+ .sleb128 -4
+ .byte 0
+ .p2align 2
+.LECIE1:
+
+.LSFDE1:
+ .long .LEFDE1-.LASFDE1
+.LASFDE1:
+ .long .LASFDE1-.Lframe1
+ .long .La
+ .long .Lb-.La
+ .p2align 2
+.LEFDE1:
diff --git a/binutils-2.19/ld/testsuite/ld-linkonce/y.s b/binutils-2.19/ld/testsuite/ld-linkonce/y.s
new file mode 100644
index 0000000..c1eb511
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-linkonce/y.s
@@ -0,0 +1,64 @@
+;# Library file y.s has linkonce entries for fn and fn2.  Note
+;# that this version of fn has different code, as if compiled
+;# with different optimization flags than the one in x.s (not
+;# important for this test, though).  The reference from
+;# .gcc_except_table to the linkonce-excluded fn2 must be zero, or g++
+;# EH will not work.
+
+ .section .gnu.linkonce.t.fn2,"ax",@progbits
+ .weak fn2
+ .type fn2,@function
+fn2:
+.Lc:
+ .long 3
+.Ld:
+ .size fn2,.Ld-.Lc
+
+ .section .gnu.linkonce.t.fn,"ax",@progbits
+ .weak fn
+ .type fn,@function
+fn:
+.Le:
+ .long 4
+.Lf:
+ .size fn,.Lf-.Le
+
+ .section .gcc_except_table,"aw",@progbits
+ .long 7
+ .long .Lc
+ .long .Ld-.Lc
+
+ .long 0x6066
+ .long .Le
+ .long .Lf-.Le
+
+ .section .eh_frame,"aw",@progbits
+.Lframe1:
+ .long .LECIE1-.LSCIE1
+.LSCIE1:
+ .long 0x0
+ .byte 0x1
+ .byte 0
+ .uleb128 0x1
+ .sleb128 -4
+ .byte 0
+ .p2align 2
+.LECIE1:
+
+.LSFDE1:
+ .long .LEFDE1-.LASFDE1
+.LASFDE1:
+ .long .LASFDE1-.Lframe1
+ .long .Lc
+ .long .Ld-.Lc
+ .p2align 2
+.LEFDE1:
+
+.LSFDE2:
+ .long .LEFDE2-.LASFDE2
+.LASFDE2:
+ .long .LASFDE2-.Lframe1
+ .long .Le
+ .long .Lf-.Le
+ .p2align 2
+.LEFDE2:
diff --git a/binutils-2.19/ld/testsuite/ld-linkonce/zeroeh.ld b/binutils-2.19/ld/testsuite/ld-linkonce/zeroeh.ld
new file mode 100644
index 0000000..b22eaa1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-linkonce/zeroeh.ld
@@ -0,0 +1,5 @@
+SECTIONS {
+ .text 0xa00 : { *(.text); *(.gnu.linkonce.t.*) }
+ .gcc_except_table 0x2000 : { *(.gcc_except_table) }
+ .eh_frame 0x4000 : { *(.eh_frame) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-linkonce/zeroehl32.d b/binutils-2.19/ld/testsuite/ld-linkonce/zeroehl32.d
new file mode 100644
index 0000000..5b51836
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-linkonce/zeroehl32.d
@@ -0,0 +1,21 @@
+#source: x.s
+#source: y.s
+#ld: -Ttext 0xa00 -T zeroeh.ld
+#objdump: -s
+#target: cris-*-elf cris-*-linux* i?86-*-elf i?86-*-linux*
+
+# The word at address 201c, for the linkonce-excluded section, must be zero.
+
+.*:     file format elf32.*
+
+Contents of section \.text:
+ 0a00 080a0000 100a0000 01000000 02000000  .*
+ 0a10 03000000                             .*
+Contents of section \.gcc_except_table:
+ 2000 02000000 080a0000 08000000 07000000  .*
+ 2010 100a0000 04000000 66600000 00000000  .*
+ 2020 04000000                             .*
+Contents of section \.eh_frame:
+ 4000 0c000000 00000000 0100017c 00000000  .*
+ 4010 0c000000 14000000 080a0000 08000000  .*
+ 4020 0c000000 24000000 100a0000 04000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/adj-brset.d b/binutils-2.19/ld/testsuite/ld-m68hc11/adj-brset.d
new file mode 100644
index 0000000..f1788f7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/adj-brset.d
@@ -0,0 +1,32 @@
+#source: adj-brset.s
+#as: -m68hc11
+#ld: --relax
+#objdump: -d --prefix-addresses -r
+#target: m6811-*-* m6812-*-*
+
+.*: +file format elf32\-m68hc11
+
+Disassembly of section .text:
+0+8000 <_start> brclr	140,x \#\$c8 0+804a <L8>
+0+8004 <L1> addd	\*0+4 <_toto>
+0+8006 <L1\+0x2> brclr	20,x \#\$03 0+8004 <L1>
+0+800a <L1\+0x6> brclr	90,x \#\$63 0+801a <L3>
+0+800e <L2> addd	\*0+4 <_toto>
+0+8010 <L2\+0x2> brclr	19,y \#\$04 0+800e <L2>
+0+8015 <L2\+0x7> brclr	91,y \#\$62 0+8024 <L4>
+0+801a <L3> addd	\*0+4 <_toto>
+0+801c <L3\+0x2> brset	18,x \#\$05 0+801a <L3>
+0+8020 <L3\+0x6> brset	92,x \#\$61 0+8030 <L5>
+0+8024 <L4> addd	\*0+4 <_toto>
+0+8026 <L4\+0x2> brset	17,y \#\$06 0+8024 <L4>
+0+802b <L4\+0x7> brset	93,y \#\$60 0+8030 <L5>
+0+8030 <L5> addd	\*0+4 <_toto>
+0+8032 <L5\+0x2> brset	\*0+32 <_table> \#\$07 0+8030 <L5>
+0+8036 <L5\+0x6> brset	\*0+3c <_table\+0xa> \#\$5f 0+8044 <L7>
+0+803a <L6> addd	\*0+4 <_toto>
+0+803c <L6\+0x2> brclr	\*0+33 <_table\+0x1> \#\$08 0+803a <L6>
+0+8040 <L6\+0x6> brset	\*0+3d <_table\+0xb> \#\$5e 0+804a <L8>
+0+8044 <L7> addd	\*0+4 <_toto>
+0+8046 <L7\+0x2> brclr	\*0+33 <_table\+0x1> \#\$08 0+803a <L6>
+0+804a <L8> brclr	140,x \#\$c8 0+8000 <_start>
+0+804e <L8\+0x4> rts
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/adj-brset.s b/binutils-2.19/ld/testsuite/ld-m68hc11/adj-brset.s
new file mode 100644
index 0000000..1aaff41
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/adj-brset.s
@@ -0,0 +1,51 @@
+;;; Test 68HC11 linker relaxation and fixup of brclr/brset branches
+;;; 
+	.sect .text
+	.globl _start
+_start:
+start:
+	brclr	140,x#200,L8	; Branch adjustment covers the whole test
+;;; The 'addd' is relaxed and we win 1 byte.  The next brclr/brset
+;;; branch must be fixed and reduced by 1.  We check for different
+;;; addressing modes because the instruction has different opcode and
+;;; different lengths.
+L1:
+	addd	_toto
+	brclr	20,x,#3,L1
+	brclr	90,x,#99,L3	; Likewise with forward branch
+L2:
+	addd	_toto
+	brclr	19,y,#4,L2
+	brclr	91,y,#98,L4
+L3:
+	addd	_toto
+	brset	18,x,#5,L3
+	brset	92,x,#97,L5
+L4:
+	addd	_toto
+	brset	17,y,#6,L4
+	brset	93,y,#96,L5
+L5:
+	addd	_toto
+	brset	*_table,#7,L5
+	brset	*_table+10,#95,L7
+L6:
+	addd	_toto
+	brclr	*_table+1,#8,L6
+	brset	*_table+11,#94,L8
+L7:
+	addd	_toto
+	brclr	*_table+1,#8,L6
+L8:
+	brclr	140,x#200,_start ; Branch adjustment covers the whole test
+	rts
+
+	.sect	.page0
+_bar:
+	.long	0
+_toto:
+	.long	0
+	.skip	32
+stack:
+	.skip	10
+_table:
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/adj-jump.d b/binutils-2.19/ld/testsuite/ld-m68hc11/adj-jump.d
new file mode 100644
index 0000000..be87524
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/adj-jump.d
@@ -0,0 +1,60 @@
+#source: adj-jump.s
+#as: -m68hc11
+#ld: --relax
+#objdump: -d --prefix-addresses -r
+#target: m6811-*-* m6812-*-*
+
+.*: +file format elf32\-m68hc11
+
+Disassembly of section .text:
+0+8000 <_start> bra	0+8074 <L3>
+	...
+0+8016 <_start\+0x16> bra	0+8074 <L3>
+0+8018 <L1> addd	0,x
+0+801a <L1\+0x2> bne	0+8018 <L1>
+0+801c <L1\+0x4> addd	\*0+4 <_toto>
+0+801e <L1\+0x6> beq	0+8018 <L1>
+0+8020 <L1\+0x8> addd	\*0+5 <_toto\+0x1>
+0+8022 <L1\+0xa> bne	0+8018 <L1>
+0+8024 <L1\+0xc> bgt	0+8018 <L1>
+0+8026 <L1\+0xe> bge	0+8018 <L1>
+0+8028 <L1\+0x10> beq	0+8018 <L1>
+0+802a <L1\+0x12> ble	0+8018 <L1>
+0+802c <L1\+0x14> blt	0+8018 <L1>
+0+802e <L1\+0x16> bhi	0+8018 <L1>
+0+8030 <L1\+0x18> bcc	0+8018 <L1>
+0+8032 <L1\+0x1a> beq	0+8018 <L1>
+0+8034 <L1\+0x1c> bls	0+8018 <L1>
+0+8036 <L1\+0x1e> bcs	0+8018 <L1>
+0+8038 <L1\+0x20> bcs	0+8018 <L1>
+0+803a <L1\+0x22> bmi	0+8018 <L1>
+0+803c <L1\+0x24> bvs	0+8018 <L1>
+0+803e <L1\+0x26> bcc	0+8018 <L1>
+0+8040 <L1\+0x28> bpl	0+8018 <L1>
+0+8042 <L1\+0x2a> bvc	0+8018 <L1>
+0+8044 <L1\+0x2c> bne	0+8018 <L1>
+0+8046 <L1\+0x2e> brn	0+8018 <L1>
+0+8048 <L1\+0x30> bra	0+8018 <L1>
+0+804a <L1\+0x32> addd	\*0+4 <_toto>
+0+804c <L1\+0x34> addd	\*0+4 <_toto>
+0+804e <L1\+0x36> addd	\*0+4 <_toto>
+0+8050 <L1\+0x38> addd	\*0+4 <_toto>
+0+8052 <L1\+0x3a> addd	\*0+4 <_toto>
+0+8054 <L1\+0x3c> addd	\*0+4 <_toto>
+0+8056 <L1\+0x3e> addd	\*0+4 <_toto>
+0+8058 <L1\+0x40> addd	\*0+4 <_toto>
+0+805a <L1\+0x42> addd	\*0+4 <_toto>
+0+805c <L1\+0x44> addd	\*0+4 <_toto>
+0+805e <L1\+0x46> addd	\*0+4 <_toto>
+0+8060 <L1\+0x48> addd	\*0+4 <_toto>
+0+8062 <L1\+0x4a> addd	\*0+4 <_toto>
+0+8064 <L1\+0x4c> addd	\*0+4 <_toto>
+0+8066 <L1\+0x4e> addd	\*0+4 <_toto>
+0+8068 <L2> bra	0+8000 <_start>
+0+806a <L2\+0x2> bne	0+8068 <L2>
+0+806c <L2\+0x4> beq	0+8074 <L3>
+0+806e <L2\+0x6> addd	\*0+4 <_toto>
+0+8070 <L2\+0x8> beq	0+8074 <L3>
+0+8072 <L2\+0xa> addd	\*0+4 <_toto>
+0+8074 <L3> addd	\*0+4 <_toto>
+0+8076 <L3\+0x2> rts
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/adj-jump.s b/binutils-2.19/ld/testsuite/ld-m68hc11/adj-jump.s
new file mode 100644
index 0000000..99b7258
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/adj-jump.s
@@ -0,0 +1,74 @@
+;;; Test 68HC11 linker relaxation and fixup of bcc/bra branches
+;;; 
+	.sect .text
+	.globl _start
+_start:
+	;; Next 'bra' is assembled as a 'jmp'.  It is relaxed to 'bra L3'
+	;; during a second pass of relax.
+	bra	L3
+	.skip	20
+	;; Next 'jmp' must be relaxed to a 'bra' during the first pass.
+	;; The branch offset must then be adjusted by consecutive relax.
+	jmp	L3
+L1:
+	addd	0,x
+	bne	L1		; Branch not adjusted
+	addd	_toto
+	beq	L1		; Backward branch, adjust -1
+	addd	_toto+1
+	jbne	L1		; Backward branch, adjust -2
+	bgt	L1		; All possible backward branchs, adjust -2
+	bge	L1
+	beq	L1
+	ble	L1
+	blt	L1
+	bhi	L1
+	bhs	L1
+	beq	L1
+	bls	L1
+	blo	L1
+	bcs	L1
+	bmi	L1
+	bvs	L1
+	bcc	L1
+	bpl	L1
+	bvc	L1
+	bne	L1
+	brn	L1
+	bra	L1
+	;; Relax several insn to reduce block by 15
+	addd	_toto
+	addd	_toto
+	addd	_toto
+	addd	_toto
+	addd	_toto
+	addd	_toto
+	addd	_toto
+	addd	_toto
+	addd	_toto
+	addd	_toto
+	addd	_toto
+	addd	_toto
+	addd	_toto
+	addd	_toto
+	addd	_toto
+L2:
+	jmp	_start		; -> relax to bra _start
+	bne	L2		; Backward branch, adjust -1
+	beq	L3		; Forward branch, adjust -2
+	addd	_toto
+	beq	L3		; Forward branch, adjust -1
+	addd	_toto
+L3:
+	addd	_toto
+	rts
+
+	.sect	.page0
+_bar:
+	.long	0
+_toto:
+	.long	0
+	.skip	32
+stack:
+	.skip	10
+_table:
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/bug-1403.d b/binutils-2.19/ld/testsuite/ld-m68hc11/bug-1403.d
new file mode 100644
index 0000000..c643cd1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/bug-1403.d
@@ -0,0 +1,12 @@
+#source: bug-1403.s
+#as: -m68hc11
+#ld: --relax
+#objdump: -d --prefix-addresses -r
+#target: m6811-*-* m6812-*-*
+
+.*: +file format elf32-m68hc11
+
+Disassembly of section .text:
+0+8000 <_start> bset	\*0+ <__bss_size> \#\$04
+0+8003 <L1> bra	0+8005 <toto>
+0+8005 <toto> rts
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/bug-1403.s b/binutils-2.19/ld/testsuite/ld-m68hc11/bug-1403.s
new file mode 100644
index 0000000..9c6fc9b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/bug-1403.s
@@ -0,0 +1,20 @@
+;;; Bug #1403:	Branch adjustment to another section not correct when doing linker relaxation
+;;; http://savannah.gnu.org/bugs/?func=detailbug&bug_id=1403&group_id=2424
+;;; 
+	.sect .text
+	.globl _start
+_start:
+	.relax	L1
+	ldx	#table
+	bset	0,x #4
+L1:
+	bra	toto		; bra is assembled as a jmp and relaxed
+
+	.sect .page0
+	.globl table
+table:	.long 0
+
+	.sect	.text.toto
+	.globl	toto
+toto:
+	rts
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/bug-1417.d b/binutils-2.19/ld/testsuite/ld-m68hc11/bug-1417.d
new file mode 100644
index 0000000..84b3ad4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/bug-1417.d
@@ -0,0 +1,15 @@
+#source: bug-1417.s
+#as: -m68hc11
+#ld: --relax
+#objdump: -d --prefix-addresses -r
+#target: m6811-*-* m6812-*-*
+
+.*: +file format elf32-m68hc11
+
+Disassembly of section .text:
+0+8000 <_start> tst	0+ <__bss_size>
+0+8003 <_start\+0x3> bne	0+8007 <L1>
+0+8005 <_start\+0x5> bsr	0+800b <foo>
+0+8007 <L1> bset	\*0+ <__bss_size> \#\$04
+0+800a <L2> rts
+0+800b <foo> rts
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/bug-1417.s b/binutils-2.19/ld/testsuite/ld-m68hc11/bug-1417.s
new file mode 100644
index 0000000..2b3e6a1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/bug-1417.s
@@ -0,0 +1,21 @@
+;;; Bug #1417:	Branch wrong after linker relaxation
+;;; http://savannah.gnu.org/bugs/?func=detailbug&bug_id=1417&group_id=2424
+;;; 
+	.sect .text
+	.globl _start
+_start:
+	tst	table
+	bne	L1		; Branch was adjusted but it must not
+	jsr	foo
+L1:
+	.relax	L2
+	ldx	#table		; Instruction removed
+	bset	0,x #4		; Changed to bset *table #4
+L2:
+	rts
+foo:
+	rts
+
+	.sect .page0
+	.globl table
+table:	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/bug-3331.d b/binutils-2.19/ld/testsuite/ld-m68hc11/bug-3331.d
new file mode 100644
index 0000000..91050bf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/bug-3331.d
@@ -0,0 +1,14 @@
+#source: bug-3331.s
+#as: -m68hc11
+#ld: --relax
+#objdump: -d --prefix-addresses -r
+#target: m6811-*-* m6812-*-*
+
+.*: +file format elf32-m68hc11
+
+Disassembly of section .text:
+0+8000 <_start> ldx	#0+1100 <__data_section_start>
+0+8003 <_start\+0x3> bset	0,x \#\$04
+0+8006 <L1> ldd	\#0+2 <__bss_size\+0x2>
+0+8009 <L1\+0x3> std	\*0+ <__bss_size>
+0+800b <L1\+0x5> rts
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/bug-3331.s b/binutils-2.19/ld/testsuite/ld-m68hc11/bug-3331.s
new file mode 100644
index 0000000..19a3201
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/bug-3331.s
@@ -0,0 +1,23 @@
+;;; Bug #3331:	Invalid group relaxation, bset uses an invalid address
+;;; http://savannah.gnu.org/bugs/?func=detailbug&bug_id=3331&group_id=2424
+;;; 
+	.sect .text
+	.globl _start
+_start:
+	.relax	L1
+	ldx	#foo		;; This relax group must not be changed.
+	bset	0,x #4
+L1:
+	ldd	#2
+	std	table		;; This instruction uses a symbol in page0
+				;; and it triggered the relaxation of the
+				;; previous relax group
+	rts
+
+	.sect .page0
+	.globl table
+table:	.long 0
+
+	.sect .data
+	.globl foo
+foo:	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/far-hc11.d b/binutils-2.19/ld/testsuite/ld-m68hc11/far-hc11.d
new file mode 100644
index 0000000..e380511
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/far-hc11.d
@@ -0,0 +1,73 @@
+#source: far-hc11.s
+#as: -m68hc11
+#ld: -m m68hc11elf
+#objdump: -d --prefix-addresses -r
+#target: m6811-*-* m6812-*-*
+
+.*:     file format elf32-m68hc11
+
+Disassembly of section .text:
+0+8000 <tramp._far_foo> pshb
+0+8001 <tramp._far_foo\+0x1> ldab	\#0
+0+8003 <tramp._far_foo\+0x3> ldy	\#0+6c <_far_foo>
+0+8007 <tramp._far_foo\+0x7> jmp	0+8056 <__far_trampoline>
+0+800a <tramp._far_bar> pshb
+0+800b <tramp._far_bar\+0x1> ldab	\#0
+0+800d <tramp._far_bar\+0x3> ldy	\#0+64 <stack>
+0+8011 <tramp._far_bar\+0x7> jmp	0+8056 <__far_trampoline>
+0+8014 <_start> lds	\#0+64 <stack>
+0+8017 <_start\+0x3> ldx	\#0+abcd <__data_image\+0x2b63>
+0+801a <_start\+0x6> pshx
+0+801b <_start\+0x7> ldd	\#0+1234 <__data_section_start\+0x134>
+0+801e <_start\+0xa> ldx	\#0+5678 <__data_section_start\+0x4578>
+0+8021 <_start\+0xd> jsr	0+800a <tramp._far_bar>
+0+8024 <_start\+0x10> cpx	\#0+1234 <__data_section_start\+0x134>
+0+8027 <_start\+0x13> bne	0+804e <fail>
+0+8029 <_start\+0x15> cpd	\#0+5678 <__data_section_start\+0x4578>
+0+802d <_start\+0x19> bne	0+804e <fail>
+0+802f <_start\+0x1b> pulx
+0+8030 <_start\+0x1c> cpx	\#0+abcd <__data_image\+0x2b63>
+0+8033 <_start\+0x1f> bne	0+804e <fail>
+0+8035 <_start\+0x21> ldd	\#0+8000 <tramp._far_foo>
+0+8038 <_start\+0x24> xgdx
+0+8039 <_start\+0x25> jsr	0,x
+0+803b <_start\+0x27> ldd	\#0+800a <tramp._far_bar>
+0+803e <_start\+0x2a> xgdy
+0+8040 <_start\+0x2c> jsr	0,y
+0+8043 <_start\+0x2f> ldaa	\#0
+0+8045 <_start\+0x31> ldy	\#0+73 <_far_no_tramp>
+0+8049 <_start\+0x35> bsr	0+8066 <__call_a16>
+0+804b <_start\+0x37> clra
+0+804c <_start\+0x38> clrb
+0+804d <_start\+0x39> wai
+0+804e <fail> ldd	\#0+1 <__bss_size\+0x1>
+0+8051 <fail\+0x3> wai
+0+8052 <fail\+0x4> bra	0+8014 <_start>
+0+8054 <__return> ins
+0+8055 <__return\+0x1> rts
+0+8056 <__far_trampoline> psha
+0+8057 <__far_trampoline\+0x1> psha
+0+8058 <__far_trampoline\+0x2> pshx
+0+8059 <__far_trampoline\+0x3> tsx
+0+805a <__far_trampoline\+0x4> ldab	4,x
+0+805c <__far_trampoline\+0x6> ldaa	2,x
+0+805e <__far_trampoline\+0x8> staa	4,x
+0+8060 <__far_trampoline\+0xa> pulx
+0+8061 <__far_trampoline\+0xb> pula
+0+8062 <__far_trampoline\+0xc> pula
+0+8063 <__far_trampoline\+0xd> jmp	0,y
+0+8066 <__call_a16> psha
+0+8067 <__call_a16\+0x1> jmp	0,y
+Disassembly of section .bank1:
+0+64 <_far_bar> jsr	0+6b <local_bank1>
+0+67 <_far_bar\+0x3> xgdx
+0+68 <_far_bar\+0x4> jmp	0+8054 <__return>
+0+6b <local_bank1> rts
+Disassembly of section .bank2:
+0+6c <_far_foo> jsr	0+72 <local_bank2>
+0+6f <_far_foo\+0x3> jmp	0+8054 <__return>
+0+72 <local_bank2> rts
+Disassembly of section .bank3:
+0+73 <_far_no_tramp> jsr	0+79 <local_bank3>
+0+76 <_far_no_tramp\+0x3> jmp	0+8054 <__return>
+0+79 <local_bank3> rts
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/far-hc11.s b/binutils-2.19/ld/testsuite/ld-m68hc11/far-hc11.s
new file mode 100644
index 0000000..e8e63d4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/far-hc11.s
@@ -0,0 +1,105 @@
+;;; Test 68HC11 FAR trampoline generation
+;;; 2 trampolines are generated:
+;;; - one for '_far_bar'
+;;; - one for '_far_foo'
+;;; 'far_no_tramp' does not have any trampoline generated.
+;;;
+	.sect .text
+	.globl _start
+_start:
+start:	
+	lds	#stack
+	ldx	#0xabcd
+	pshx
+	ldd	#0x1234
+	ldx	#0x5678
+	bsr	_far_bar	; Call to trampoline generated code
+	cpx	#0x1234
+	bne	fail		; X and D preserved (swapped by _far_bar)
+	cpd	#0x5678
+	bne	fail
+	pulx
+	cpx	#0xabcd		; Stack parameter preserved
+	bne	fail
+	ldd	#_far_foo	; Get address of trampoline handler
+	xgdx
+	jsr	0,x
+	ldd	#_far_bar	; Likewise (unique trampoline check)
+	xgdy
+	jsr	0,y
+	ldaa	#%page(_far_no_tramp)
+	ldy	#%addr(_far_no_tramp)
+	bsr	__call_a16	; No trampoline generated for _far_no_tramp
+	clra
+	clrb
+	wai
+fail:
+	ldd	#1
+	wai
+	bra	start
+	.global	__return
+__return:
+	ins
+	rts
+
+	.sect .bank1,"ax"
+	.globl _far_bar
+	.far _far_bar		; Must mark symbol as far
+_far_bar:
+	jsr	local_bank1
+	xgdx
+	jmp	__return
+
+local_bank1:
+	rts
+
+	.sect .bank2,"ax"
+	.globl _far_foo
+	.far _far_foo
+_far_foo:
+	jsr	local_bank2
+	jmp	__return
+
+local_bank2:
+	rts
+
+	.sect .bank3,"ax"
+	.globl _far_no_tramp
+	.far _far_no_tramp
+_far_no_tramp:
+	jsr	local_bank3
+	jmp	__return
+
+local_bank3:
+	rts
+
+	.sect .text
+	.globl __far_trampoline
+__far_trampoline:
+	psha				; (2) Save function parameter (high)
+	;; <Read current page in A>
+	psha				; (2)
+	;; <Set currenge page from B>
+	pshx				; (4)
+	tsx				; (3)
+	ldab	4,x			; (4) Restore function parameter (low)
+	ldaa	2,x			; (4) Get saved page number
+	staa	4,x			; (4) Save it below return PC
+	pulx				; (5)
+	pula				; (3)
+	pula				; (3) Restore function parameter (high)
+	jmp	0,y			; (4)
+
+	.globl __call_a16
+__call_a16:
+	;; xgdx				; (3)
+	;; <Read current page in A>	; (3) ldaa _current_page
+	psha				; (2)
+	;; <Set current page from B>	; (4) staa _current_page
+	;; xgdx				; (3)
+	jmp 0,y				; (4)
+
+	.sect .page0
+	.skip 100
+stack:
+
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/far-hc12.d b/binutils-2.19/ld/testsuite/ld-m68hc11/far-hc12.d
new file mode 100644
index 0000000..304ae87
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/far-hc12.d
@@ -0,0 +1,55 @@
+#source: far-hc12.s
+#as: -m68hc12
+#ld: -m m68hc12elf --script $srcdir/$subdir/far-hc12.ld
+#objdump: -d --prefix-addresses -r
+#target: m6811-*-* m6812-*-*
+
+.*:     file format elf32\-m68hc12
+
+Disassembly of section .text:
+0+c000 <tramp\._far_foo> ldy	\#0+8000 <__bank_start>
+0+c003 <tramp\._far_foo\+0x3> call	0+c049 <__far_trampoline> \{0+c049 <__far_trampoline>, 1\}
+0+c007 <tramp\._far_bar> ldy	\#0+8000 <__bank_start>
+0+c00a <tramp\._far_bar\+0x3> call	0+c049 <__far_trampoline> \{0+c049 <__far_trampoline>, 0\}
+0+c00e <_start> lds	\#0+2063 <stack-0x1>
+0+c011 <_start\+0x3> ldx	\#0+abcd <__bank_start\+0x2bcd>
+0+c014 <_start\+0x6> pshx
+0+c015 <_start\+0x7> ldd	\#0+1234 <stack\-0xe30>
+0+c018 <_start\+0xa> ldx	\#0+5678 <__bank_size\+0x1678>
+0+c01b <_start\+0xd> jsr	0+c007 <tramp._far_bar>
+0+c01e <_start\+0x10> cpx	\#0+1234 <stack\-0xe30>
+0+c021 <_start\+0x13> bne	0+c043 <fail>
+0+c023 <_start\+0x15> cpd	\#0+5678 <__bank_size\+0x1678>
+0+c026 <_start\+0x18> bne	0+c043 <fail>
+0+c028 <_start\+0x1a> pulx
+0+c029 <_start\+0x1b> cpx	\#0+abcd <__bank_start\+0x2bcd>
+0+c02c <_start\+0x1e> bne	0+c043 <fail>
+0+c02e <_start\+0x20> ldd	\#0+c000 <tramp._far_foo>
+0+c031 <_start\+0x23> xgdx
+0+c033 <_start\+0x25> jsr	0,X
+0+c035 <_start\+0x27> ldd	\#0+c007 <tramp._far_bar>
+0+c038 <_start\+0x2a> xgdy
+0+c03a <_start\+0x2c> jsr	0,Y
+0+c03c <_start\+0x2e> call	0+18000 <_far_no_tramp> \{0+8000 <__bank_start>, 2\}
+0+c040 <_start\+0x32> clra
+0+c041 <_start\+0x33> clrb
+0+c042 <_start\+0x34> wai
+0+c043 <fail> ldd	\#0+1 <stack\-0x2063>
+0+c046 <fail\+0x3> wai
+0+c047 <fail\+0x4> bra	0+c00e <_start>
+0+c049 <__far_trampoline> movb	0,SP, 2,SP
+0+c04d <__far_trampoline\+0x4> leas	2,SP
+0+c04f <__far_trampoline\+0x6> jmp	0,Y
+Disassembly of section .bank1:
+0+10+ <_far_bar> jsr	0+10006 <local_bank1>
+0+10003 <_far_bar\+0x3> xgdx
+0+10005 <_far_bar\+0x5> rtc
+0+10006 <local_bank1> rts
+Disassembly of section .bank2:
+0+14000 <_far_foo> jsr	0+14004 <local_bank2>
+0+14003 <_far_foo\+0x3> rtc
+0+14004 <local_bank2> rts
+Disassembly of section .bank3:
+0+18000 <_far_no_tramp> jsr	0+18004 <local_bank3>
+0+18003 <_far_no_tramp\+0x3> rtc
+0+18004 <local_bank3> rts
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/far-hc12.ld b/binutils-2.19/ld/testsuite/ld-m68hc11/far-hc12.ld
new file mode 100644
index 0000000..78dffe6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/far-hc12.ld
@@ -0,0 +1,18 @@
+ENTRY(_start)
+SECTIONS {
+  .text 0xc000 : {
+    *(.text)
+  }
+  .bank1 0x10000 : {
+    *(.bank1)
+  }
+  .bank2 0x14000 : {
+    *(.bank2)
+  }
+  .bank3 0x18000 : {
+    *(.bank3)
+  }
+  .bss 0x2000 : {
+    *(.bss)
+  }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/far-hc12.s b/binutils-2.19/ld/testsuite/ld-m68hc11/far-hc12.s
new file mode 100644
index 0000000..0081e38
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/far-hc12.s
@@ -0,0 +1,83 @@
+;;; Test 68HC12 FAR trampoline generation
+;;; 2 trampolines are generated:
+;;; - one for '_far_bar'
+;;; - one for '_far_foo'
+;;; 'far_no_tramp' does not have any trampoline generated.
+;;;
+	.sect .text
+	.globl _start
+_start:
+start:	
+	lds	#stack-1
+	ldx	#0xabcd
+	pshx
+	ldd	#0x1234
+	ldx	#0x5678
+	bsr	_far_bar	; Call to trampoline generated code
+	cpx	#0x1234
+	bne	fail		; X and D preserved (swapped by _far_bar)
+	cpd	#0x5678
+	bne	fail
+	pulx
+	cpx	#0xabcd		; Stack parameter preserved
+	bne	fail
+	ldd	#_far_foo	; Get address of trampoline handler
+	xgdx
+	jsr	0,x
+	ldd	#_far_bar	; Likewise (unique trampoline check)
+	xgdy
+	jsr	0,y
+	call	_far_no_tramp	; No trampoline generated for _far_no_tramp
+	clra
+	clrb
+	wai
+fail:
+	ldd	#1
+	wai
+	bra	start
+
+	.sect .bank1,"ax"
+	.globl _far_bar
+	.far _far_bar		; Must mark symbol as far
+_far_bar:
+	jsr	local_bank1
+	xgdx
+	rtc
+
+local_bank1:
+	rts
+
+	.sect .bank2,"ax"
+	.globl _far_foo
+	.far _far_foo
+_far_foo:
+	jsr	local_bank2
+	rtc
+
+local_bank2:
+	rts
+
+	.sect .bank3,"ax"
+	.globl _far_no_tramp
+	.far _far_no_tramp
+_far_no_tramp:
+	jsr	local_bank3
+	rtc
+
+local_bank3:
+	rts
+
+	.sect .text
+	.globl __far_trampoline
+__far_trampoline:
+	movb	0,sp, 2,sp	; Copy page register below the caller's return
+	leas	2,sp		; address.
+	jmp	0,y		; We have a 'call/rtc' stack layout now
+				; and can jump to the far handler
+				; (whose memory bank is mapped due to the
+				; call to the trampoline).
+
+	.sect .bss
+	.skip 100
+stack:
+
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/link-hc12.s b/binutils-2.19/ld/testsuite/ld-m68hc11/link-hc12.s
new file mode 100644
index 0000000..43b97c5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/link-hc12.s
@@ -0,0 +1,6 @@
+;;; Test 68HCS12 and 68HC12 mixes (compatible case)
+;;;
+	.sect .text
+	.globl main
+main:
+	rts
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/link-hcs12.d b/binutils-2.19/ld/testsuite/ld-m68hc11/link-hcs12.d
new file mode 100644
index 0000000..f243da2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/link-hcs12.d
@@ -0,0 +1,24 @@
+#source: link-hcs12.s -m68hcs12
+#source: link-hc12.s -m68hc12
+#as: -mshort
+#ld: -m m68hc12elf
+#objdump: -p -d --prefix-addresses -r
+#target: m6811-*-* m6812-*-*
+
+.*:     file format elf32\-m68hc12
+
+Program Header:
+    LOAD off    0x0+ vaddr 0x0+1000 paddr 0x0+1000 align 2\*\*12
+         filesz 0x0+100 memsz 0x0+100 flags rw-
+    LOAD off    0x0+1000 vaddr 0x0+8000 paddr 0x0+8000 align 2\*\*12
+         filesz 0x0+6 memsz 0x0+6 flags r-x
+    LOAD off    0x0+1100 vaddr 0x0+1100 paddr 0x0+8006 align 2\*\*12
+         filesz 0x0+ memsz 0x0+ flags rw-
+private flags = 22:\[abi=16\-bit int, 64\-bit double, cpu=HCS12\] \[memory=flat\]
+
+Disassembly of section .text:
+0+8000 <_start> jsr	0+8005 <main>
+0+8003 <_start\+0x3> bra	0+8000 <_start>
+0+8005 <main> rts
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/link-hcs12.s b/binutils-2.19/ld/testsuite/ld-m68hc11/link-hcs12.s
new file mode 100644
index 0000000..868d4cf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/link-hcs12.s
@@ -0,0 +1,7 @@
+;;; Test 68HCS12 and 68HC12 mixes (compatible case)
+;;;
+	.sect .text
+	.globl _start
+_start:
+	bsr	main
+	bra	_start
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/m68hc11.exp b/binutils-2.19/ld/testsuite/ld-m68hc11/m68hc11.exp
new file mode 100644
index 0000000..b45b96a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/m68hc11.exp
@@ -0,0 +1,34 @@
+# Expect script for run_dump_test based ld-m68hc11 tests.
+#   Copyright 2002, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Adapted from ld-sh/rd-sh.exp
+
+# Test 68HC11 relaxing.  This tests the assembler as well as the linker.
+
+if { ![istarget m6811-*-*] && ![istarget m6812-*-*] } {
+    return
+}
+
+set rd_test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach shtest $rd_test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname $shtest]
+    run_dump_test [file rootname $shtest]
+}
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/relax-direct.d b/binutils-2.19/ld/testsuite/ld-m68hc11/relax-direct.d
new file mode 100644
index 0000000..9bd0822
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/relax-direct.d
@@ -0,0 +1,63 @@
+#source: relax-direct.s
+#as: -m68hc11
+#ld: --relax
+#objdump: -d --prefix-addresses -r
+#target: m6811-*-* m6812-*-*
+
+.*: +file format elf32-m68hc11
+
+Disassembly of section .text:
+0+8000 <_start> lds	\*0+28 <stack>
+0+8002 <_start\+0x2> ldd	\*0+ <__bss_size>
+0+8004 <_start\+0x4> beq	0+800f <F1>
+0+8006 <_start\+0x6> bne	0+800b <_start\+0xb>
+0+8008 <_start\+0x8> jmp	0+8138 <F2>
+0+800b <_start\+0xb> std	\*0+ <__bss_size>
+0+800d <_start\+0xd> jsr	\*0+ <__bss_size>
+0+800f <F1> addd	\*0+4 <_toto>
+0+8011 <F1\+0x2> bne	0+8000 <_start>
+0+8013 <F1\+0x4> addd	\*0+cc <_table\+0x9a>
+0+8015 <F1\+0x6> addd	0+114 <_stack_top\+0x1a>
+0+8018 <F1\+0x9> adca	\*0+34 <_table\+0x2>
+0+801a <F1\+0xb> adcb	\*0+35 <_table\+0x3>
+0+801c <F1\+0xd> adda	\*0+36 <_table\+0x4>
+0+801e <F1\+0xf> addb	\*0+37 <_table\+0x5>
+0+8020 <F1\+0x11> addd	\*0+38 <_table\+0x6>
+0+8022 <F1\+0x13> anda	\*0+39 <_table\+0x7>
+0+8024 <F1\+0x15> andb	\*0+3a <_table\+0x8>
+0+8026 <F1\+0x17> cmpa	\*0+3b <_table\+0x9>
+0+8028 <F1\+0x19> cmpb	\*0+3c <_table\+0xa>
+0+802a <F1\+0x1b> cpd	\*0+3d <_table\+0xb>
+0+802d <F1\+0x1e> cpx	\*0+3e <_table\+0xc>
+0+802f <F1\+0x20> cpy	\*0+3f <_table\+0xd>
+0+8032 <F1\+0x23> eora	\*0+40 <_table\+0xe>
+0+8034 <F1\+0x25> eorb	\*0+41 <_table\+0xf>
+0+8036 <F1\+0x27> jsr	\*0+42 <_table\+0x10>
+0+8038 <F1\+0x29> ldaa	\*0+43 <_table\+0x11>
+0+803a <F1\+0x2b> ldab	\*0+44 <_table\+0x12>
+0+803c <F1\+0x2d> ldd	\*0+45 <_table\+0x13>
+0+803e <F1\+0x2f> lds	\*0+46 <_table\+0x14>
+0+8040 <F1\+0x31> ldx	\*0+47 <_table\+0x15>
+0+8042 <F1\+0x33> ldy	\*0+48 <_table\+0x16>
+0+8045 <F1\+0x36> oraa	\*0+49 <_table\+0x17>
+0+8047 <F1\+0x38> orab	\*0+4a <_table\+0x18>
+0+8049 <F1\+0x3a> sbcb	\*0+4b <_table\+0x19>
+0+804b <F1\+0x3c> sbca	\*0+4c <_table\+0x1a>
+0+804d <F1\+0x3e> staa	\*0+4d <_table\+0x1b>
+0+804f <F1\+0x40> stab	\*0+4e <_table\+0x1c>
+0+8051 <F1\+0x42> std	\*0+4f <_table\+0x1d>
+0+8053 <F1\+0x44> sts	\*0+50 <_table\+0x1e>
+0+8055 <F1\+0x46> stx	\*0+51 <_table\+0x1f>
+0+8057 <F1\+0x48> sty	\*0+52 <_table\+0x20>
+0+805a <F1\+0x4b> suba	\*0+53 <_table\+0x21>
+0+805c <F1\+0x4d> subb	\*0+54 <_table\+0x22>
+0+805e <F1\+0x4f> subd	\*0+55 <_table\+0x23>
+0+8060 <F1\+0x51> bne	0+8000 <_start>
+0+8062 <F1\+0x53> bra	0+800f <F1>
+0+8064 <F1\+0x55> rts
+0+8065 <no_relax> addd	0+136 <_stack_top\+0x3c>
+0+8068 <no_relax\+0x3> std	0+122 <_stack_top\+0x28>
+0+806b <no_relax\+0x6> tst	0+5 <_toto\+0x1>
+0+806e <no_relax\+0x9> bne	0+8065 <no_relax>
+	...
+0+8138 <F2> jmp	0+8000 <_start>
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/relax-direct.s b/binutils-2.19/ld/testsuite/ld-m68hc11/relax-direct.s
new file mode 100644
index 0000000..f449772
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/relax-direct.s
@@ -0,0 +1,84 @@
+;;; Test 68HC11 linker relaxation from extended addressing to direct
+;;; addressing modes
+;;; 
+	.sect .text
+	.globl _start
+_start:
+start:	
+	lds	stack
+	ldd	_bar
+	beq	F1
+	beq	F2
+	std	_bar
+	jsr	_bar
+F1:
+	addd	_toto
+	bne	start
+	;; All the following instructions will be relaxed and win 1 byte
+	;; for each.
+	addd	_toto+200
+	addd	stack+256-20
+	adca	_table+2
+	adcb	_table+3
+	adda	_table+4
+	addb	_table+5
+	addd	_table+6
+	anda	_table+7
+	andb	_table+8
+	cmpa	_table+9
+	cmpb	_table+10
+	cpd	_table+11
+	cpx	_table+12
+	cpy	_table+13
+	eora	_table+14
+	eorb	_table+15
+	jsr	_table+16
+	ldaa	_table+17
+	ldab	_table+18
+	ldd	_table+19
+	lds	_table+20
+	ldx	_table+21
+	ldy	_table+22
+	oraa	_table+23
+	orab	_table+24
+	sbcb	_table+25
+	sbca	_table+26
+	staa	_table+27
+	stab	_table+28
+	std	_table+29
+	sts	_table+30
+	stx	_table+31
+	sty	_table+32
+	suba	_table+33
+	subb	_table+34
+	subd	_table+35
+	;; 'bne' is assembled as far branch and must relax to 
+	;; a relative 8-bit branch.
+	bne	_start
+	;; Likewise for next branch
+	bra	F1
+	rts
+
+;;; The following instructions will not be relaxed
+no_relax:
+	addd	_stack_top+60
+	std	_stack_top+40
+	;; 'tst' does not support direct addressing mode.
+	tst	_toto+1
+	bne	no_relax
+	.skip	200
+F2:
+	bra	_start
+
+	.sect	.page0
+_bar:
+	.long	0
+_toto:
+	.long	0
+	.skip	32
+stack:
+	.skip	10
+_table:
+	.skip	200
+_stack_top:
+
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/relax-group.d b/binutils-2.19/ld/testsuite/ld-m68hc11/relax-group.d
new file mode 100644
index 0000000..baf294b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/relax-group.d
@@ -0,0 +1,63 @@
+#source: relax-group.s
+#as: -m68hc11
+#ld: --relax
+#objdump: -d --prefix-addresses -r
+#target: m6811-*-* m6812-*-*
+
+.*: +file format elf32-m68hc11
+
+Disassembly of section .text:
+0+8000 <_start> bset	\*0+ <__bss_size> #\$04
+0+8003 <L1x> bset	\*0+ <__bss_size> #\$04
+0+8006 <L1y> bset	\*0+3 <__bss_size\+0x3> #\$04
+0+8009 <L1y\+0x3> bset	\*0+4 <table4> #\$08
+0+800c <L2x> bset	\*0+3 <__bss_size\+0x3> #\$04
+0+800f <L2x\+0x3> bset	\*0+4 <table4> #\$08
+0+8012 <L2y> bset	\*0+6 <table4\+0x2> #\$04
+0+8015 <L2y\+0x3> bset	\*0+7 <table4\+0x3> #\$08
+0+8018 <L2y\+0x6> bset	\*0+8 <table8> #\$0c
+0+801b <L2y\+0x9> bset	\*0+9 <table8\+0x1> #\$0c
+0+801e <L2y\+0xc> bset	\*0+a <table8\+0x2> #\$0c
+0+8021 <L2y\+0xf> bset	\*0+b <table8\+0x3> #\$0c
+0+8024 <L3x> bset	\*0+6 <table4\+0x2> #\$04
+0+8027 <L3x\+0x3> bset	\*0+7 <table4\+0x3> #\$08
+0+802a <L3x\+0x6> bset	\*0+8 <table8> #\$0c
+0+802d <L3x\+0x9> bset	\*0+9 <table8\+0x1> #\$0c
+0+8030 <L3x\+0xc> bset	\*0+a <table8\+0x2> #\$0c
+0+8033 <L3x\+0xf> bset	\*0+b <table8\+0x3> #\$0c
+0+8036 <L3y> bra	0+8000 <_start>
+0+8038 <L3y\+0x2> ldx	#0+fe <end_table\+0xe8>
+0+803b <L3y\+0x5> bset	\*0+fe <end_table\+0xe8> #\$04
+0+803e <L3y\+0x8> bset	\*0+ff <end_table\+0xe9> #\$08
+0+8041 <L3y\+0xb> bset	2,x #\$0c
+0+8044 <L3y\+0xe> bset	3,x #\$0c
+0+8047 <L3y\+0x11> bset	4,x #\$0c
+0+804a <L3y\+0x14> bset	5,x #\$0c
+0+804d <L4x> ldy	#0+fe <end_table\+0xe8>
+0+8051 <L4x\+0x4> bset	\*0+fe <end_table\+0xe8> #\$04
+0+8054 <L4x\+0x7> bset	\*0+ff <end_table\+0xe9> #\$08
+0+8057 <L4x\+0xa> bset	2,y #\$0c
+0+805b <L4x\+0xe> bset	3,y #\$0c
+0+805f <L4x\+0x12> bset	4,y #\$0c
+0+8063 <L4x\+0x16> bset	5,y #\$0c
+0+8067 <L4y> bclr	\*0+a <table8\+0x2> #\$04
+0+806a <L4y\+0x3> bclr	\*0+b <table8\+0x3> #\$08
+0+806d <L5x> bclr	\*0+1a <end_table\+0x4> #\$04
+0+8070 <L5x\+0x3> bclr	\*0+1b <end_table\+0x5> #\$08
+0+8073 <L5y> brset	\*0+8 <table8> #\$04 0+8073 <L5y>
+0+8077 <L6x> brset	\*0+8 <table8> #\$04 0+8077 <L6x>
+0+807b <L7x> brset	\*0+8 <table8> #\$04 0+8094 <brend>
+0+807f <L8x> brset	\*0+8 <table8> #\$04 0+8094 <brend>
+0+8083 <L8y> brclr	\*0+8 <table8> #\$04 0+8083 <L8y>
+0+8087 <L9x> brclr	\*0+8 <table8> #\$04 0+8087 <L9x>
+0+808b <L9y> brclr	\*0+8 <table8> #\$04 0+8094 <brend>
+0+808f <L10x> brclr	\*0+8 <table8> #\$04 0+8094 <brend>
+0+8093 <L10y> nop
+0+8094 <brend> bset	0,x #\$04
+0+8097 <w2> ldx	#0+ <__bss_size>
+0+809a <w3> ldy	#0+8 <table8>
+0+809e <w4> rts
+0+809f <w5> ldx	#0+ <__bss_size>
+0+80a2 <w5\+0x3> bset	0,x #\$05
+0+80a5 <w5\+0x6> jmp	0+8000 <_start>
+0+80a8 <w5\+0x9> rts
diff --git a/binutils-2.19/ld/testsuite/ld-m68hc11/relax-group.s b/binutils-2.19/ld/testsuite/ld-m68hc11/relax-group.s
new file mode 100644
index 0000000..41c55f5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68hc11/relax-group.s
@@ -0,0 +1,161 @@
+;;; Test 68HC11 linker relaxation (group relax)
+;;; 
+	.sect .text
+	.globl _start
+_start:
+;;;
+;;; The following group of instructions are adjusted.
+;;;
+	.relax	L1x
+	ldx	#table
+	bset	0,x #4
+L1x:
+	.relax	L1y
+	ldy	#table
+	bset	0,y #4
+L1y:
+	.relax	L2x
+	ldx	#table+3
+	bset	0,x #4
+	bset	1,x #8
+L2x:
+	.relax	L2y
+	ldy	#table+3
+	bset	0,y #4
+	bset	1,y #8
+L2y:
+	.relax	L3x
+	ldx	#table+6
+	bset	0,x #4
+	bset	1,x #8
+	bset	2,x #12
+	bset	3,x #12
+	bset	4,x #12
+	bset	5,x #12
+L3x:
+	.relax	L3y
+	ldy	#table+6
+	bset	0,y #4
+	bset	1,y #8
+	bset	2,y #12
+	bset	3,y #12
+	bset	4,y #12
+	bset	5,y #12
+L3y:
+	;; Next branch is always relative.  It must be adjusted while
+	;; above instructions are relaxed.
+	bra	_start
+;;;
+;;; This group has the first two bset insn relaxable while the
+;;; others are not.  The ldx/ldy must not be removed.
+;;; 
+	.relax	L4x
+	ldx	#table+0xfe
+	bset	0,x #4
+	bset	1,x #8
+	bset	2,x #12
+	bset	3,x #12
+	bset	4,x #12
+	bset	5,x #12
+L4x:
+	.relax	L4y
+	ldy	#table+0xfe
+	bset	0,y #4
+	bset	1,y #8
+	bset	2,y #12
+	bset	3,y #12
+	bset	4,y #12
+	bset	5,y #12
+L4y:
+;;;
+;;; Relax group for bclr
+;;; 
+	.relax	L5x
+	ldx	#table+10
+	bclr	0,x #4
+	bclr	1,x #8
+L5x:
+	.relax	L5y
+	ldy	#table+16
+	bclr	10,y #4
+	bclr	11,y #8
+L5y:
+;;;
+;;; Relax group for brset (with backward branch)
+;;; 
+	.relax	L6x
+	ldx	#table+8
+	brset	0,x #4 L5y
+L6x:
+	.relax	L7x
+	ldy	#table+8
+	brset	0,y #4 L6x
+L7x:
+;;;
+;;; Relax group for brset (with forward branch)
+;;; 
+	.relax	L8x
+	ldx	#table+8
+	brset	0,x #4 brend
+L8x:
+	.relax	L8y
+	ldy	#table+8
+	brset	0,y #4 brend
+L8y:
+;;;
+;;; Relax group for brclr (with backward branch)
+;;; 
+	.relax	L9x
+	ldx	#table+8
+	brclr	0,x #4 L8y
+L9x:
+	.relax	L9y
+	ldy	#table+8
+	brclr	0,y #4 L9x
+L9y:
+;;;
+;;; Relax group for brclr (with forward branch)
+;;; 
+	.relax	L10x
+	ldx	#table+8
+	brclr	0,x #4 brend
+L10x:
+	.relax	L10y
+	ldy	#table+8
+	brclr	0,y #4 brend
+L10y:
+	nop
+brend:
+;;;
+;;; The following are wrong use of .relax groups.
+;;;
+	.relax	w1
+w1:
+	.relax	w2
+	bset	0,x #4
+w2:
+	.relax w3
+	ldx	#table
+w3:
+	.relax w4
+	ldy	#table+8
+w4:
+	.relax w5
+	rts
+w5:
+;;;
+;;; Next insn is not in a .relax group
+	ldx	#table
+	bset	0,x #5
+	bra	_start
+	rts
+
+	.sect .page0
+	.globl table
+table:	.long 0
+table4:	.long 0
+table8:	.long 0
+	.skip	10
+end_table:
+	.long 0
+
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/got-1.d b/binutils-2.19/ld/testsuite/ld-m68k/got-1.d
new file mode 100644
index 0000000..e8070e9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/got-1.d
@@ -0,0 +1,19 @@
+#source: got-1.s
+#ld: -shared
+#readelf: -d -r
+
+Dynamic section at offset .* contains 9 entries:
+  Tag        Type                         Name/Value
+ 0x00000004 \(HASH\)                       0x[0-9a-f]+
+ 0x00000005 \(STRTAB\)                     0x[0-9a-f]+
+ 0x00000006 \(SYMTAB\)                     0x[0-9a-f]+
+ 0x0000000a \(STRSZ\)                      [0-9]+ \(bytes\)
+ 0x0000000b \(SYMENT\)                     16 \(bytes\)
+ 0x00000007 \(RELA\)                       0x[0-9a-f]+
+ 0x00000008 \(RELASZ\)                     12 \(bytes\)
+ 0x00000009 \(RELAENT\)                    12 \(bytes\)
+ 0x00000000 \(NULL\)                       0x0
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 1 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name \+ Addend
+[0-9a-f]+  [0-9a-f]+ R_68K_GLOB_DAT    00000000   a \+ 0
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/got-1.s b/binutils-2.19/ld/testsuite/ld-m68k/got-1.s
new file mode 100644
index 0000000..0cf3692
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/got-1.s
@@ -0,0 +1,18 @@
+#NO_APP
+	.file	"got-1.c"
+	.text
+	.align	2
+	.globl	foo
+	.type	foo, @function
+foo:
+	link.w %fp,#0
+	move.l %a5,-(%sp)
+	lea (%pc, _GLOBAL_OFFSET_TABLE_@GOTPC), %a5
+	move.l a@GOT(%a5),%d0
+	move.l %d0,%a0
+	move.l (%a0),%d0
+	move.l (%sp)+,%a5
+	unlk %fp
+	rts
+	.size	foo, .-foo
+	.section	.note.GNU-stack,"",@progbits
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/got-multigot-12-13-14-34-35-ok.d b/binutils-2.19/ld/testsuite/ld-m68k/got-multigot-12-13-14-34-35-ok.d
new file mode 100644
index 0000000..de55032
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/got-multigot-12-13-14-34-35-ok.d
@@ -0,0 +1,18 @@
+#as: -mcpu=5206
+#ld: -shared --got=multigot
+#readelf: -d -r
+
+Dynamic section at offset .* contains 9 entries:
+  Tag        Type                         Name/Value
+ 0x00000004 \(HASH\)                       0x[0-9a-f]+
+ 0x00000005 \(STRTAB\)                     0x[0-9a-f]+
+ 0x00000006 \(SYMTAB\)                     0x[0-9a-f]+
+ 0x0000000a \(STRSZ\)                      [0-9]+ \(bytes\)
+ 0x0000000b \(SYMENT\)                     16 \(bytes\)
+ 0x00000007 \(RELA\)                       0x[0-9a-f]+
+ 0x00000008 \(RELASZ\)                     294960 \(bytes\)
+ 0x00000009 \(RELAENT\)                    12 \(bytes\)
+ 0x00000000 \(NULL\)                       0x0
+
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 24580 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name \+ Addend
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/got-multigot-14-ok.d b/binutils-2.19/ld/testsuite/ld-m68k/got-multigot-14-ok.d
new file mode 100644
index 0000000..dc2e64a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/got-multigot-14-ok.d
@@ -0,0 +1,18 @@
+#as: -mcpu=5206
+#ld: -shared --got=multigot
+#readelf: -d -r
+
+Dynamic section at offset .* contains 9 entries:
+  Tag        Type                         Name/Value
+ 0x00000004 \(HASH\)                       0x[0-9a-f]+
+ 0x00000005 \(STRTAB\)                     0x[0-9a-f]+
+ 0x00000006 \(SYMTAB\)                     0x[0-9a-f]+
+ 0x0000000a \(STRSZ\)                      [0-9]+ \(bytes\)
+ 0x0000000b \(SYMENT\)                     16 \(bytes\)
+ 0x00000007 \(RELA\)                       0x[0-9a-f]+
+ 0x00000008 \(RELASZ\)                     196608 \(bytes\)
+ 0x00000009 \(RELAENT\)                    12 \(bytes\)
+ 0x00000000 \(NULL\)                       0x0
+
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 16384 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name \+ Addend
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/got-multigot-15-er.d b/binutils-2.19/ld/testsuite/ld-m68k/got-multigot-15-er.d
new file mode 100644
index 0000000..58381ae
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/got-multigot-15-er.d
@@ -0,0 +1,3 @@
+#as: -mcpu=5206
+#ld: -shared --got=multigot
+#error: .*GOT overflow.*
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/got-negative-12-13-14-34-ok.d b/binutils-2.19/ld/testsuite/ld-m68k/got-negative-12-13-14-34-ok.d
new file mode 100644
index 0000000..402631c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/got-negative-12-13-14-34-ok.d
@@ -0,0 +1,18 @@
+#as: -mcpu=5206
+#ld: -shared --got=negative
+#readelf: -d -r
+
+Dynamic section at offset .* contains 9 entries:
+  Tag        Type                         Name/Value
+ 0x00000004 \(HASH\)                       0x[0-9a-f]+
+ 0x00000005 \(STRTAB\)                     0x[0-9a-f]+
+ 0x00000006 \(SYMTAB\)                     0x[0-9a-f]+
+ 0x0000000a \(STRSZ\)                      [0-9]+ \(bytes\)
+ 0x0000000b \(SYMENT\)                     16 \(bytes\)
+ 0x00000007 \(RELA\)                       0x[0-9a-f]+
+ 0x00000008 \(RELASZ\)                     196608 \(bytes\)
+ 0x00000009 \(RELAENT\)                    12 \(bytes\)
+ 0x00000000 \(NULL\)                       0x0
+
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 16384 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name \+ Addend
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/got-negative-12-13-14-35-er.d b/binutils-2.19/ld/testsuite/ld-m68k/got-negative-12-13-14-35-er.d
new file mode 100644
index 0000000..4487a8c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/got-negative-12-13-14-35-er.d
@@ -0,0 +1,3 @@
+#as: -mcpu=5206
+#ld: -shared --got=negative
+#error: .*relocation truncated to fit.*
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/got-negative-14-ok.d b/binutils-2.19/ld/testsuite/ld-m68k/got-negative-14-ok.d
new file mode 100644
index 0000000..402631c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/got-negative-14-ok.d
@@ -0,0 +1,18 @@
+#as: -mcpu=5206
+#ld: -shared --got=negative
+#readelf: -d -r
+
+Dynamic section at offset .* contains 9 entries:
+  Tag        Type                         Name/Value
+ 0x00000004 \(HASH\)                       0x[0-9a-f]+
+ 0x00000005 \(STRTAB\)                     0x[0-9a-f]+
+ 0x00000006 \(SYMTAB\)                     0x[0-9a-f]+
+ 0x0000000a \(STRSZ\)                      [0-9]+ \(bytes\)
+ 0x0000000b \(SYMENT\)                     16 \(bytes\)
+ 0x00000007 \(RELA\)                       0x[0-9a-f]+
+ 0x00000008 \(RELASZ\)                     196608 \(bytes\)
+ 0x00000009 \(RELAENT\)                    12 \(bytes\)
+ 0x00000000 \(NULL\)                       0x0
+
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 16384 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name \+ Addend
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/got-negative-15-er.d b/binutils-2.19/ld/testsuite/ld-m68k/got-negative-15-er.d
new file mode 100644
index 0000000..c1b7409
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/got-negative-15-er.d
@@ -0,0 +1,3 @@
+#as: -mcpu=5206
+#ld: -shared --got=negative
+#error: .*GOT overflow.*
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/got-single-12-ok.d b/binutils-2.19/ld/testsuite/ld-m68k/got-single-12-ok.d
new file mode 100644
index 0000000..a7fdeb9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/got-single-12-ok.d
@@ -0,0 +1,18 @@
+#as: -mcpu=5206
+#ld: -shared --got=single
+#readelf: -d -r
+
+Dynamic section at offset .* contains 9 entries:
+  Tag        Type                         Name/Value
+ 0x00000004 \(HASH\)                       0x[0-9a-f]+
+ 0x00000005 \(STRTAB\)                     0x[0-9a-f]+
+ 0x00000006 \(SYMTAB\)                     0x[0-9a-f]+
+ 0x0000000a \(STRSZ\)                      [0-9]+ \(bytes\)
+ 0x0000000b \(SYMENT\)                     16 \(bytes\)
+ 0x00000007 \(RELA\)                       0x[0-9a-f]+
+ 0x00000008 \(RELASZ\)                     98268 \(bytes\)
+ 0x00000009 \(RELAENT\)                    12 \(bytes\)
+ 0x00000000 \(NULL\)                       0x0
+
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 8189 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name \+ Addend
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/got-single-13-er.d b/binutils-2.19/ld/testsuite/ld-m68k/got-single-13-er.d
new file mode 100644
index 0000000..bfca9f8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/got-single-13-er.d
@@ -0,0 +1,3 @@
+#as: -mcpu=5206
+#ld: -shared --got=single
+#error: .*relocation truncated to fit.*
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/got-xgot-12-13-14-15-34-35-ok.d b/binutils-2.19/ld/testsuite/ld-m68k/got-xgot-12-13-14-15-34-35-ok.d
new file mode 100644
index 0000000..dd2c21d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/got-xgot-12-13-14-15-34-35-ok.d
@@ -0,0 +1,18 @@
+#as: -mcpu=5206
+#ld: -shared --got=multigot
+#readelf: -d -r
+
+Dynamic section at offset .* contains 9 entries:
+  Tag        Type                         Name/Value
+ 0x00000004 \(HASH\)                       0x[0-9a-f]+
+ 0x00000005 \(STRTAB\)                     0x[0-9a-f]+
+ 0x00000006 \(SYMTAB\)                     0x[0-9a-f]+
+ 0x0000000a \(STRSZ\)                      [0-9]+ \(bytes\)
+ 0x0000000b \(SYMENT\)                     16 \(bytes\)
+ 0x00000007 \(RELA\)                       0x[0-9a-f]+
+ 0x00000008 \(RELASZ\)                     294972 \(bytes\)
+ 0x00000009 \(RELAENT\)                    12 \(bytes\)
+ 0x00000000 \(NULL\)                       0x0
+
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 24581 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name \+ Addend
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/got-xgot-15-ok.d b/binutils-2.19/ld/testsuite/ld-m68k/got-xgot-15-ok.d
new file mode 100644
index 0000000..bc11849
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/got-xgot-15-ok.d
@@ -0,0 +1,18 @@
+#as: -mcpu=5206
+#ld: -shared --got=multigot
+#readelf: -d -r
+
+Dynamic section at offset .* contains 9 entries:
+  Tag        Type                         Name/Value
+ 0x00000004 \(HASH\)                       0x[0-9a-f]+
+ 0x00000005 \(STRTAB\)                     0x[0-9a-f]+
+ 0x00000006 \(SYMTAB\)                     0x[0-9a-f]+
+ 0x0000000a \(STRSZ\)                      [0-9]+ \(bytes\)
+ 0x0000000b \(SYMENT\)                     16 \(bytes\)
+ 0x00000007 \(RELA\)                       0x[0-9a-f]+
+ 0x00000008 \(RELASZ\)                     196620 \(bytes\)
+ 0x00000009 \(RELAENT\)                    12 \(bytes\)
+ 0x00000000 \(NULL\)                       0x0
+
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 16385 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name \+ Addend
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/isaa-mac.d b/binutils-2.19/ld/testsuite/ld-m68k/isaa-mac.d
new file mode 100644
index 0000000..79b809a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/isaa-mac.d
@@ -0,0 +1,7 @@
+
+.*:     file format elf32-m68k
+
+Program Header:
+#...
+private flags = 12: \[isa A\] \[mac\]
+
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/isaa-mac.s b/binutils-2.19/ld/testsuite/ld-m68k/isaa-mac.s
new file mode 100644
index 0000000..e3ec277
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/isaa-mac.s
@@ -0,0 +1,3 @@
+	.arch isaa,mac
+
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/isaa-nodiv.s b/binutils-2.19/ld/testsuite/ld-m68k/isaa-nodiv.s
new file mode 100644
index 0000000..de327f1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/isaa-nodiv.s
@@ -0,0 +1,3 @@
+	.arch isaa,no-div
+
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/isaa.d b/binutils-2.19/ld/testsuite/ld-m68k/isaa.d
new file mode 100644
index 0000000..48e4fa2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/isaa.d
@@ -0,0 +1,7 @@
+
+.*:     file format elf32-m68k
+
+Program Header:
+#...
+private flags = 2: \[isa A\]
+
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/isaa.s b/binutils-2.19/ld/testsuite/ld-m68k/isaa.s
new file mode 100644
index 0000000..f4675c1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/isaa.s
@@ -0,0 +1,3 @@
+	.arch isaa
+
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/isaaplus.d b/binutils-2.19/ld/testsuite/ld-m68k/isaaplus.d
new file mode 100644
index 0000000..88623ce
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/isaaplus.d
@@ -0,0 +1,7 @@
+
+.*:     file format elf32-m68k
+
+Program Header:
+#...
+private flags = 3: \[isa A\+\]
+
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/isaaplus.s b/binutils-2.19/ld/testsuite/ld-m68k/isaaplus.s
new file mode 100644
index 0000000..5b0a0b8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/isaaplus.s
@@ -0,0 +1,3 @@
+	.arch isaaplus
+
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/isab-float.d b/binutils-2.19/ld/testsuite/ld-m68k/isab-float.d
new file mode 100644
index 0000000..3547ea7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/isab-float.d
@@ -0,0 +1,7 @@
+
+.*:     file format elf32-m68k
+
+Program Header:
+#...
+private flags = 8045: \[cfv4e\] \[isa B\] \[float\]
+
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/isab-float.s b/binutils-2.19/ld/testsuite/ld-m68k/isab-float.s
new file mode 100644
index 0000000..3889d0d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/isab-float.s
@@ -0,0 +1,3 @@
+	.arch isab,float
+
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/isab-nousp.s b/binutils-2.19/ld/testsuite/ld-m68k/isab-nousp.s
new file mode 100644
index 0000000..1e52357
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/isab-nousp.s
@@ -0,0 +1,3 @@
+	.arch isab,no-usp
+
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/isab.d b/binutils-2.19/ld/testsuite/ld-m68k/isab.d
new file mode 100644
index 0000000..c5b0134
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/isab.d
@@ -0,0 +1,7 @@
+
+.*:     file format elf32-m68k
+
+Program Header:
+#...
+private flags = 5: \[isa B\]
+
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/isab.s b/binutils-2.19/ld/testsuite/ld-m68k/isab.s
new file mode 100644
index 0000000..3f93db7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/isab.s
@@ -0,0 +1,3 @@
+	.arch isab
+
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/m68k-got.exp b/binutils-2.19/ld/testsuite/ld-m68k/m68k-got.exp
new file mode 100644
index 0000000..4902eac
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/m68k-got.exp
@@ -0,0 +1,250 @@
+# Expect script for run_dump_test based ld-m68k GOT tests.
+#   Copyright 008 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+if { ![is_elf_format] || ![istarget m68k-*-*] } {
+    return
+}
+
+# 1 - 1
+# 2 - 8189
+# 3 - 8190
+# 4 - 16384
+# 5 - 16385
+
+proc gen_got_test { testname } {
+    global srcdir
+    global subdir
+
+    if [catch { set ofd [open "tmpdir/$testname.s" w] } msg] {
+	perror "$msg"
+	unresolved $testname
+	return
+    }
+
+    switch --  $testname {
+	"got-12" {
+	    set start 1
+	    set count 8189
+	    set xgot 0
+	}
+	"got-13" {
+	    set start 1
+	    set count 8190
+	    set xgot 0
+	}
+	"got-14" {
+	    set start 1
+	    set count 16384
+	    set xgot 0
+	}
+	"got-15" {
+	    set start 1
+	    set count 16385
+	    set xgot 0
+	}
+	"got-34" {
+	    set start 8190
+	    set count 16384
+	    set xgot 0
+	}
+	"got-35" {
+	    set start 8190
+	    set count 16385
+	    set xgot 0
+	}
+	"xgot-15" {
+	    set start 1
+	    set count 16385
+	    set xgot 1
+	}
+    }
+
+    set func [format "sum_%05d_%05d" $start $count]
+    puts $ofd "\t.text"
+    puts $ofd "\t.align	2"
+    puts $ofd "\t.globl $func"
+    puts $ofd "\t.type $func,@function"
+    puts $ofd "$func:"
+    puts $ofd "\tlink.w %fp,#0"
+    puts $ofd "\tmove.l %a5,-(%sp)"
+    puts $ofd "\tmove.l #_GLOBAL_OFFSET_TABLE_@GOTPC, %a5"
+    puts $ofd "\tlea (-6, %pc, %a5), %a5"
+
+    if { $xgot == 1 } {
+	set symbol [format "a%05d" $start]
+	incr start
+	puts $ofd "\tlea $symbol@GOT,%a0"
+	puts $ofd "\tadd.l %a5,%a0"
+	puts $ofd "\tmove.l (%a0),%a0"
+	puts $ofd "\tmove.l (%a0),%d1"
+	for { set i $start } { $i < $count } { incr i } {
+	    set symbol [format "a%05d" $i]
+	    puts $ofd "\tlea $symbol@GOT,%a0"
+	    puts $ofd "\tadd.l %a5,%a0"
+	    puts $ofd "\tmove.l (%a0),%a0"
+	    puts $ofd "\tmove.l (%a0),%d0"
+	    puts $ofd "\tadd.l %d0,%d1"
+	}
+	set symbol [format "a%05d" $count]
+	puts $ofd "\tlea $symbol@GOT,%a0"
+	puts $ofd "\tadd.l %a5,%a0"
+	puts $ofd "\tmove.l (%a0),%a0"
+	puts $ofd "\tmove.l (%a0),%d0"
+	puts $ofd "\tadd.l %d1,%d0"
+    } else {
+	set symbol [format "a%05d" $start]
+	incr start
+	puts $ofd "\tmove.l $symbol@GOT(%a5),%d0"
+	puts $ofd "\tmove.l %d0,%a0"
+	puts $ofd "\tmove.l (%a0),%d1"
+	for { set i $start } { $i < $count } { incr i } {
+	    set symbol [format "a%05d" $i]
+	    puts $ofd "\tmove.l $symbol@GOT(%a5),%d0"
+	    puts $ofd "\tmove.l %d0,%a0"
+	    puts $ofd "\tmove.l (%a0),%d0"
+	    puts $ofd "\tadd.l %d0,%d1"
+	}
+	set symbol [format "a%05d" $count]
+	puts $ofd "\tmove.l $symbol@GOT(%a5),%d0"
+	puts $ofd "\tmove.l %d0,%a0"
+	puts $ofd "\tmove.l (%a0),%d0"
+	puts $ofd "\tadd.l %d1,%d0"
+    }
+
+    puts $ofd "\tmove.l (%sp)+,%a5"
+    puts $ofd "\tunlk %fp"
+    puts $ofd "\trts"
+    puts $ofd "\t.size	$func, .-$func"
+
+    close $ofd
+}
+
+proc got_test { testname } {
+    global srcdir
+    global subdir
+    global objdir
+
+    if [catch { set ifd [open "$srcdir/$subdir/$testname.d" r] } msg] {
+	perror "$msg"
+	unresolved $testname
+	return
+    }
+    if [catch { set ofd [open "tmpdir/$testname.d" w] } msg] {
+	perror "$msg"
+	unresolved $testname
+	return
+    }
+
+    switch --  $testname {
+	"got-single-12-ok" {
+	    puts $ofd "#source: $objdir/tmpdir/got-12.s"
+	    set count 8189
+	}
+	"got-single-13-er" {
+	    puts $ofd "#source: $objdir/tmpdir/got-13.s"
+	    set count 0
+	}
+	"got-negative-14-ok" {
+	    puts $ofd "#source: $objdir/tmpdir/got-14.s"
+	    set count 16384
+	}
+	"got-negative-15-er" {
+	    puts $ofd "#source: $objdir/tmpdir/got-15.s"
+	    set count 0
+	}
+	"got-negative-12-13-14-34-ok" {
+	    puts $ofd "#source: $objdir/tmpdir/got-12.s"
+	    puts $ofd "#source: $objdir/tmpdir/got-13.s"
+	    puts $ofd "#source: $objdir/tmpdir/got-14.s"
+	    puts $ofd "#source: $objdir/tmpdir/got-34.s"
+	    set count 16384
+	}
+	"got-negative-12-13-14-35-er" {
+	    puts $ofd "#source: $objdir/tmpdir/got-12.s"
+	    puts $ofd "#source: $objdir/tmpdir/got-13.s"
+	    puts $ofd "#source: $objdir/tmpdir/got-14.s"
+	    puts $ofd "#source: $objdir/tmpdir/got-35.s"
+	    set count 0
+	}
+	"got-multigot-14-ok" {
+	    puts $ofd "#source: $objdir/tmpdir/got-14.s"
+	    set count 16384
+	}
+	"got-multigot-15-er" {
+	    puts $ofd "#source: $objdir/tmpdir/got-15.s"
+	    set count 0
+	}
+	"got-multigot-12-13-14-34-35-ok" {
+	    puts $ofd "#source: $objdir/tmpdir/got-12.s"
+	    puts $ofd "#source: $objdir/tmpdir/got-13.s"
+	    puts $ofd "#source: $objdir/tmpdir/got-14.s"
+	    puts $ofd "#source: $objdir/tmpdir/got-34.s"
+	    puts $ofd "#source: $objdir/tmpdir/got-35.s"
+	    set count 24580
+	}
+	"got-xgot-15-ok" {
+	    puts $ofd "#source: $objdir/tmpdir/xgot-15.s"
+	    set count 16385
+	}
+	"got-xgot-12-13-14-15-34-35-ok" {
+	    puts $ofd "#source: $objdir/tmpdir/got-12.s"
+	    puts $ofd "#source: $objdir/tmpdir/got-13.s"
+	    puts $ofd "#source: $objdir/tmpdir/got-14.s"
+	    puts $ofd "#source: $objdir/tmpdir/xgot-15.s"
+	    puts $ofd "#source: $objdir/tmpdir/got-34.s"
+	    puts $ofd "#source: $objdir/tmpdir/got-35.s"
+	    set count 24581
+	}
+    }
+
+    while { [gets $ifd line] != -1 } {
+	puts $ofd $line
+    }
+
+    for { set i 0 } { $i < $count } { incr i } {
+	puts $ofd "^\[0-9a-f\]+  \[0-9a-f\]+ R_68K_GLOB_DAT    00000000   a\[0-9\]+ \\\+ 0"
+    }
+
+    close $ifd
+    close $ofd
+    run_dump_test "tmpdir/$testname"
+}
+
+gen_got_test got-12
+gen_got_test got-13
+gen_got_test got-14
+gen_got_test got-15
+gen_got_test got-34
+gen_got_test got-35
+gen_got_test xgot-15
+
+run_dump_test "got-1"
+got_test "got-single-12-ok"
+got_test "got-single-13-er"
+got_test "got-negative-14-ok"
+got_test "got-negative-15-er"
+got_test "got-negative-12-13-14-34-ok"
+got_test "got-negative-12-13-14-35-er"
+got_test "got-multigot-14-ok"
+got_test "got-multigot-15-er"
+got_test "got-multigot-12-13-14-34-35-ok"
+got_test "got-xgot-15-ok"
+got_test "got-xgot-12-13-14-15-34-35-ok"
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/m68k.exp b/binutils-2.19/ld/testsuite/ld-m68k/m68k.exp
new file mode 100644
index 0000000..ccdfda0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/m68k.exp
@@ -0,0 +1,68 @@
+# Expect script for run_dump_test based ld-m68k tests.
+#   Copyright 2006, 2007, 2008 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Test m68k object merging
+
+if { ![is_elf_format] || ![istarget m68k-*-*] } {
+    return
+}
+
+# List contains test-items with 3 items followed by 2 lists:
+# 0:name 1:ld options 2:assembler options
+# 3:filenames of assembler files 4: action and options. 5: name of output file
+
+# Actions:
+# objdump: Apply objdump options on result.  Compare with regex (last arg).
+# nm: Apply nm options on result.  Compare with regex (last arg).
+# readelf: Apply readelf options on result.  Compare with regex (last arg).
+
+set m68k_mergeok_tests {
+    {"merge isa-a isa-a:nodiv" "-T merge.ld" ""
+	{isaa.s isaa-nodiv.s} {{objdump -p isaa.d}} "isaa"}
+    {"merge isa-a isa-b" "-T merge.ld" ""
+	{isaa.s isab.s} {{objdump -p isab.d}} "isab"}
+    {"merge isa-a isa-aplus" "-T merge.ld" ""
+	{isaa.s isaaplus.s} {{objdump -p isaaplus.d}} "isaplus"}
+    {"merge isa-b isa-b:nousp" "-T merge.ld" ""
+	{isab.s isab-nousp.s} {{objdump -p isab.d}} "isab"}
+    {"merge isa-a isa-a:mac" "-T merge.ld" ""
+	{isaa.s isaa-mac.s} {{objdump -p isaa-mac.d}} "isaa-mac"}
+    {"merge isa-b isa-b:float" "-T merge.ld" ""
+	{isab.s isab-float.s} {{objdump -p isab-float.d}} "isab-float"}}
+
+run_ld_link_tests $m68k_mergeok_tests
+
+run_dump_test "merge-error-1a"
+run_dump_test "merge-error-1b"
+run_dump_test "merge-error-1c"
+run_dump_test "merge-error-1d"
+run_dump_test "merge-error-1e"
+run_dump_test "merge-ok-1a"
+run_dump_test "merge-ok-1b"
+run_dump_test "merge-ok-1c"
+
+foreach { id sources } { a { plt1.s } b { plt1-empty.s plt1.s } } {
+    foreach arch { 68020 cpu32 isab isac } {
+	run_ld_link_tests [list \
+	    [list "PLT 1$id ($arch)" "-shared -T plt1.ld" "-m$arch" \
+		 $sources [list [list objdump -dr plt1-$arch.d]] \
+		 plt1-${id}-${arch}.so]]
+    }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1a.d b/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1a.d
new file mode 100644
index 0000000..3629f39
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1a.d
@@ -0,0 +1,4 @@
+#source: merge-error-1a.s -mcpu=cpu32
+#source: merge-error-1b.s -mcpu=68000
+#ld: -r
+#error: ^[^\n]* m68k:68000 [^\n]* incompatible with m68k:cpu32 [^\n]*$
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1a.s b/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1a.s
new file mode 100644
index 0000000..ee48942
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1a.s
@@ -0,0 +1 @@
+	rts
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1b.d b/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1b.d
new file mode 100644
index 0000000..bedd3d6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1b.d
@@ -0,0 +1,4 @@
+#source: merge-error-1a.s -mcpu=cpu32
+#source: merge-error-1b.s -mcpu=5207
+#ld: -r
+#error: ^[^\n]* m68k:isa-aplus:emac [^\n]* incompatible with m68k:cpu32 [^\n]*$
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1b.s b/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1b.s
new file mode 100644
index 0000000..ee48942
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1b.s
@@ -0,0 +1 @@
+	rts
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1c.d b/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1c.d
new file mode 100644
index 0000000..9538e77
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1c.d
@@ -0,0 +1,4 @@
+#source: merge-error-1a.s -march=isaaplus
+#source: merge-error-1b.s -march=isab
+#ld: -r
+#error: ^[^\n]* m68k:isa-b [^\n]* incompatible with m68k:isa-aplus [^\n]*$
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1d.d b/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1d.d
new file mode 100644
index 0000000..4d86771
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1d.d
@@ -0,0 +1,4 @@
+#source: merge-error-1a.s -march=isaa -mmac
+#source: merge-error-1b.s -march=isaa -memac
+#ld: -r
+#error: ^[^\n]* m68k:isa-a:emac [^\n]* incompatible with m68k:isa-a:mac [^\n]*$
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1e.d b/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1e.d
new file mode 100644
index 0000000..969f844
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/merge-error-1e.d
@@ -0,0 +1,4 @@
+#source: merge-error-1a.s -march=isaa -mno-div -mmac
+#source: merge-error-1b.s -march=isaa -mno-div -memac
+#ld: -r
+#error: ^[^\n]* m68k:isa-a:emac [^\n]* is incompatible with m68k:isa-a:mac [^\n]*$
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/merge-ok-1a.d b/binutils-2.19/ld/testsuite/ld-m68k/merge-ok-1a.d
new file mode 100644
index 0000000..96da556
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/merge-ok-1a.d
@@ -0,0 +1,6 @@
+#source: merge-error-1a.s -mcpu=5207
+#source: merge-error-1b.s -mcpu=528x
+#ld: -r
+#objdump: -p
+#...
+private flags = 23: \[isa A\+\] \[emac\]
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/merge-ok-1b.d b/binutils-2.19/ld/testsuite/ld-m68k/merge-ok-1b.d
new file mode 100644
index 0000000..03ae258
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/merge-ok-1b.d
@@ -0,0 +1,6 @@
+#source: merge-error-1a.s -march=isaa -mno-div -mmac
+#source: merge-error-1b.s -march=isaa -mno-div -mfloat
+#ld: -r
+#objdump: -p
+#...
+private flags = 8051: \[cfv4e\] \[isa A\] \[nodiv\] \[float\] \[mac\]
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/merge-ok-1c.d b/binutils-2.19/ld/testsuite/ld-m68k/merge-ok-1c.d
new file mode 100644
index 0000000..81cf5a6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/merge-ok-1c.d
@@ -0,0 +1,6 @@
+#source: merge-error-1a.s -march=cpu32
+#source: merge-error-1b.s -march=cpu32
+#ld: -r
+#objdump: -p
+#...
+private flags = 810000: \[cpu32\]
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/merge.ld b/binutils-2.19/ld/testsuite/ld-m68k/merge.ld
new file mode 100644
index 0000000..ed2acfe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/merge.ld
@@ -0,0 +1,9 @@
+OUTPUT_FORMAT("elf32-m68k", "elf32-m68k",
+              "elf32-m68k")
+OUTPUT_ARCH(m68k)
+ENTRY(_start)
+
+SECTIONS {
+ 
+  .text : {_start = .; *(.text)}
+}
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/plt1-68020.d b/binutils-2.19/ld/testsuite/ld-m68k/plt1-68020.d
new file mode 100644
index 0000000..54463b9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/plt1-68020.d
@@ -0,0 +1,35 @@
+
+.*:     file format elf32-m68k
+
+Disassembly of section \.plt:
+
+00020800 <f.@plt-0x14>:
+   20800:	2f3b 0170 0000 	movel %pc@\(30404 <_GLOBAL_OFFSET_TABLE_\+0x4>\),%sp@-
+   20806:	fc02 
+   20808:	4efb 0171 0000 	jmp %pc@\(30408 <_GLOBAL_OFFSET_TABLE_\+0x8>\)@\(0*\)
+   2080e:	fbfe 
+   20810:	0000 0000      	orib #0,%d0
+
+00020814 <f.@plt>:
+   20814:	4efb 0171 0000 	jmp %pc@\(3040c <_GLOBAL_OFFSET_TABLE_\+0xc>\)@\(0*\)
+   2081a:	fbf6 
+   2081c:	2f3c 0000 0000 	movel #0,%sp@-
+   20822:	60ff ffff ffdc 	bral 20800 <f.@plt-0x14>
+
+00020828 <f.@plt>:
+   20828:	4efb 0171 0000 	jmp %pc@\(30410 <_GLOBAL_OFFSET_TABLE_\+0x10>\)@\(0*\)
+   2082e:	fbe6 
+   20830:	2f3c 0000 000c 	movel #12,%sp@-
+   20836:	60ff ffff ffc8 	bral 20800 <f.@plt-0x14>
+
+0002083c <f.@plt>:
+   2083c:	4efb 0171 0000 	jmp %pc@\(30414 <_GLOBAL_OFFSET_TABLE_\+0x14>\)@\(0*\)
+   20842:	fbd6 
+   20844:	2f3c 0000 0018 	movel #24,%sp@-
+   2084a:	60ff ffff ffb4 	bral 20800 <f.@plt-0x14>
+Disassembly of section \.text:
+
+00020c00 <.*>:
+   20c00:	61ff ffff fc.. 	bsrl 208.. <f1@plt>
+   20c06:	61ff ffff fc.. 	bsrl 208.. <f2@plt>
+   20c0c:	61ff ffff fc.. 	bsrl 208.. <f3@plt>
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/plt1-cpu32.d b/binutils-2.19/ld/testsuite/ld-m68k/plt1-cpu32.d
new file mode 100644
index 0000000..a497740
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/plt1-cpu32.d
@@ -0,0 +1,43 @@
+
+.*:     file format elf32-m68k
+
+Disassembly of section \.plt:
+
+00020800 <f.@plt-0x18>:
+   20800:	2f3b 0170 0000 	movel %pc@\(30404 <_GLOBAL_OFFSET_TABLE_\+0x4>\),%sp@-
+   20806:	fc02 
+   20808:	227b 0170 0000 	moveal %pc@\(30408 <_GLOBAL_OFFSET_TABLE_\+0x8>\),%a1
+   2080e:	fbfe 
+   20810:	4ed1           	jmp %a1@
+   20812:	0000 0000      	orib #0,%d0
+	\.\.\.
+
+00020818 <f.@plt>:
+   20818:	227b 0170 0000 	moveal %pc@\(3040c <_GLOBAL_OFFSET_TABLE_\+0xc>\),%a1
+   2081e:	fbf2 
+   20820:	4ed1           	jmp %a1@
+   20822:	2f3c 0000 0000 	movel #0,%sp@-
+   20828:	60ff ffff ffd6 	bral 20800 <f.@plt-0x18>
+	\.\.\.
+
+00020830 <f.@plt>:
+   20830:	227b 0170 0000 	moveal %pc@\(30410 <_GLOBAL_OFFSET_TABLE_\+0x10>\),%a1
+   20836:	fbde 
+   20838:	4ed1           	jmp %a1@
+   2083a:	2f3c 0000 000c 	movel #12,%sp@-
+   20840:	60ff ffff ffbe 	bral 20800 <f.@plt-0x18>
+	\.\.\.
+
+00020848 <f.@plt>:
+   20848:	227b 0170 0000 	moveal %pc@\(30414 <_GLOBAL_OFFSET_TABLE_\+0x14>\),%a1
+   2084e:	fbca 
+   20850:	4ed1           	jmp %a1@
+   20852:	2f3c 0000 0018 	movel #24,%sp@-
+   20858:	60ff ffff ffa6 	bral 20800 <f.@plt-0x18>
+	\.\.\.
+Disassembly of section \.text:
+
+00020c00 <.*>:
+   20c00:	61ff ffff fc.. 	bsrl 208.. <f1@plt>
+   20c06:	61ff ffff fc.. 	bsrl 208.. <f2@plt>
+   20c0c:	61ff ffff fc.. 	bsrl 208.. <f3@plt>
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/plt1-empty.s b/binutils-2.19/ld/testsuite/ld-m68k/plt1-empty.s
new file mode 100644
index 0000000..a59477d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/plt1-empty.s
@@ -0,0 +1,3 @@
+	.text
+	.globl	foo
+foo:
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/plt1-isab.d b/binutils-2.19/ld/testsuite/ld-m68k/plt1-isab.d
new file mode 100644
index 0000000..a9aeacb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/plt1-isab.d
@@ -0,0 +1,44 @@
+
+.*:     file format elf32-m68k
+
+Disassembly of section \.plt:
+
+00020800 <f.@plt-0x18>:
+# _GLOBAL_OFFSET_TABLE_ + 4 == 0x30404 == 0x20802 + 0xfc02
+   20800:	203c 0000 fc02 	movel #64514,%d0
+   20806:	2f3b 08fa      	movel %pc@\(20802 <f.@plt-0x16>,%d0:l\),%sp@-
+# _GLOBAL_OFFSET_TABLE_ + 8 == 0x30408 == 0x2080c + 0xfbfc
+   2080a:	203c 0000 fbfc 	movel #64508,%d0
+   20810:	207b 08fa      	moveal %pc@\(2080c <f.@plt-0xc>,%d0:l\),%a0
+   20814:	4ed0           	jmp %a0@
+   20816:	4e71           	nop
+
+00020818 <f.@plt>:
+# _GLOBAL_OFFSET_TABLE_ + 12 == 0x3040c == 0x2081a + 0xfbf2
+   20818:	203c 0000 fbf2 	movel #64498,%d0
+   2081e:	207b 08fa      	moveal %pc@\(2081a <f.@plt\+0x2>,%d0:l\),%a0
+   20822:	4ed0           	jmp %a0@
+   20824:	2f3c 0000 0000 	movel #0,%sp@-
+   2082a:	60ff ffff ffd4 	bral 20800 <f.@plt-0x18>
+
+00020830 <f.@plt>:
+# _GLOBAL_OFFSET_TABLE_ + 16 == 0x30410 == 0x20832 + 0xfbde
+   20830:	203c 0000 fbde 	movel #64478,%d0
+   20836:	207b 08fa      	moveal %pc@\(20832 <f.@plt\+0x2>,%d0:l\),%a0
+   2083a:	4ed0           	jmp %a0@
+   2083c:	2f3c 0000 000c 	movel #12,%sp@-
+   20842:	60ff ffff ffbc 	bral 20800 <f.@plt-0x18>
+
+00020848 <f.@plt>:
+# _GLOBAL_OFFSET_TABLE_ + 20 == 0x30414 == 0x2084a + 0xfbca
+   20848:	203c 0000 fbca 	movel #64458,%d0
+   2084e:	207b 08fa      	moveal %pc@\(2084a <f.@plt\+0x2>,%d0:l\),%a0
+   20852:	4ed0           	jmp %a0@
+   20854:	2f3c 0000 0018 	movel #24,%sp@-
+   2085a:	60ff ffff ffa4 	bral 20800 <f.@plt-0x18>
+Disassembly of section \.text:
+
+00020c00 <.*>:
+   20c00:	61ff ffff fc.. 	bsrl 208.. <f1@plt>
+   20c06:	61ff ffff fc.. 	bsrl 208.. <f2@plt>
+   20c0c:	61ff ffff fc.. 	bsrl 208.. <f3@plt>
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/plt1-isac.d b/binutils-2.19/ld/testsuite/ld-m68k/plt1-isac.d
new file mode 100644
index 0000000..ae299ce
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/plt1-isac.d
@@ -0,0 +1,44 @@
+
+.*:     file format elf32-m68k
+
+Disassembly of section \.plt:
+
+00020800 <f.@plt-0x18>:
+# _GLOBAL_OFFSET_TABLE_ + 4 == 0x30404 == 0x20802 + 0xfc02
+   20800:	203c 0000 fc02 	movel #64514,%d0
+   20806:	2ebb 08fa      	movel %pc@\(20802 <f.@plt-0x16>,%d0:l\),%sp@
+# _GLOBAL_OFFSET_TABLE_ + 8 == 0x30408 == 0x2080c + 0xfbfc
+   2080a:	203c 0000 fbfc 	movel #64508,%d0
+   20810:	207b 08fa      	moveal %pc@\(2080c <f.@plt-0xc>,%d0:l\),%a0
+   20814:	4ed0           	jmp %a0@
+   20816:	4e71           	nop
+
+00020818 <f.@plt>:
+# _GLOBAL_OFFSET_TABLE_ + 12 == 0x3040c == 0x2081a + 0xfbf2
+   20818:	203c 0000 fbf2 	movel #64498,%d0
+   2081e:	207b 08fa      	moveal %pc@\(2081a <f.@plt\+0x2>,%d0:l\),%a0
+   20822:	4ed0           	jmp %a0@
+   20824:	2f3c 0000 0000 	movel #0,%sp@-
+   2082a:	61ff ffff ffd4 	bsrl 20800 <f.@plt-0x18>
+
+00020830 <f.@plt>:
+# _GLOBAL_OFFSET_TABLE_ + 16 == 0x30410 == 0x20832 + 0xfbde
+   20830:	203c 0000 fbde 	movel #64478,%d0
+   20836:	207b 08fa      	moveal %pc@\(20832 <f.@plt\+0x2>,%d0:l\),%a0
+   2083a:	4ed0           	jmp %a0@
+   2083c:	2f3c 0000 000c 	movel #12,%sp@-
+   20842:	61ff ffff ffbc 	bsrl 20800 <f.@plt-0x18>
+
+00020848 <f.@plt>:
+# _GLOBAL_OFFSET_TABLE_ + 20 == 0x30414 == 0x2084a + 0xfbca
+   20848:	203c 0000 fbca 	movel #64458,%d0
+   2084e:	207b 08fa      	moveal %pc@\(2084a <f.@plt\+0x2>,%d0:l\),%a0
+   20852:	4ed0           	jmp %a0@
+   20854:	2f3c 0000 0018 	movel #24,%sp@-
+   2085a:	61ff ffff ffa4 	bsrl 20800 <f.@plt-0x18>
+Disassembly of section \.text:
+
+00020c00 <.*>:
+   20c00:	61ff ffff fc.. 	bsrl 208.. <f1@plt>
+   20c06:	61ff ffff fc.. 	bsrl 208.. <f2@plt>
+   20c0c:	61ff ffff fc.. 	bsrl 208.. <f3@plt>
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/plt1.ld b/binutils-2.19/ld/testsuite/ld-m68k/plt1.ld
new file mode 100644
index 0000000..718e2ad
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/plt1.ld
@@ -0,0 +1,23 @@
+SECTIONS
+{
+  . = 0x20000;
+  .interp : { *(.interp) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+
+  . = ALIGN (0x400);
+  .rela.plt : { *(.rela.plt) }
+
+  . = ALIGN (0x400);
+  .plt : { *(.plt) }
+
+  . = ALIGN (0x400);
+  .text : { *(.text) }
+
+  . = ALIGN (0x10000);
+  .dynamic : { *(.dynamic) }
+
+  . = ALIGN (0x400);
+  .got : { *(.got.plt) *(.got) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-m68k/plt1.s b/binutils-2.19/ld/testsuite/ld-m68k/plt1.s
new file mode 100644
index 0000000..855fb19
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-m68k/plt1.s
@@ -0,0 +1,3 @@
+	bsr.l	f1@PLTPC
+	bsr.l	f2@PLTPC
+	bsr.l	f3@PLTPC
diff --git a/binutils-2.19/ld/testsuite/ld-maxq/addend.dd b/binutils-2.19/ld/testsuite/ld-maxq/addend.dd
new file mode 100644
index 0000000..5cd8b32
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-maxq/addend.dd
@@ -0,0 +1,21 @@
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <_main>:
+   0:	78 56 [ 	]*MOVE  56h, #78h
+	...
+
+00000004 <_buf1>:
+   4:	34 12 [ 	]*MOVE  12h, #34h
+	...
+
+00000008 <_start>:
+   8:	3a da [ 	]*NOP 
+   a:	3a da [ 	]*NOP 
+   c:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+   e:	03 09 [ 	]*MOVE  A\[0\], #03h
+  10:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  12:	01 09 [ 	]*MOVE  A\[0\], #01h
+  14:	fa 3d [ 	]*CALL  #fah
+  16:	f8 3d [ 	]*CALL  #f8h
diff --git a/binutils-2.19/ld/testsuite/ld-maxq/addend.s b/binutils-2.19/ld/testsuite/ld-maxq/addend.s
new file mode 100644
index 0000000..a5ca450
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-maxq/addend.s
@@ -0,0 +1,16 @@
+; Addend check testcases 
+; inderpreetb@noida.hcltech.com
+.global _main
+_main:
+_buf0:
+	.long 0x5678
+_buf1:
+	.long 0x1234
+_start:
+	nop
+	nop
+	move A[0], _buf1+2
+	move A[0], _buf1-2
+	call _buf0+8
+	call _buf1+2
+
diff --git a/binutils-2.19/ld/testsuite/ld-maxq/maxq.exp b/binutils-2.19/ld/testsuite/ld-maxq/maxq.exp
new file mode 100644
index 0000000..b47dcd4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-maxq/maxq.exp
@@ -0,0 +1,55 @@
+# Expect script for ld-maxq tests
+#   Copyright (C) 2004, 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by inderpreetb@noida.hcltech.com
+
+# Test maxq linking; all types of relocs.  This tests the assembler and
+# tools like objdump as well as the linker.
+
+if { !([istarget "maxq*-*-*"]  ) } {
+    return
+}
+
+# List contains test-items with 3 items followed by 2 lists:
+# 0:name 1:ld options 2:assembler options
+# 3:filenames of assembler files 4: action and options. 5: name of output file
+
+# Actions:
+# objdump: Apply objdump options on result.  Compare with regex (last arg).
+# nm: Apply nm options on result.  Compare with regex (last arg).
+# readelf: Apply readelf options on result.  Compare with regex (last arg).
+
+set maxqtests {
+{"32-bit Relocation check" "" ""
+{r32-1.s r32-2.s} {{objdump -drw r32.dd}}
+"r32.o" }
+{"maxq addend check" "" ""
+{addend.s} {{objdump -dw addend.dd}}
+"addendo.o" }
+{"16bit relocation test" "" ""
+{paddr.s} {{objdump -Dw paddr.dd}}
+"paddro.o" }
+{"16bit relocation test-1" "" ""
+{paddr1.s} {{objdump -Dw paddr1.dd}}
+"paddro1.o" }
+
+}
+
+run_ld_link_tests $maxqtests
diff --git a/binutils-2.19/ld/testsuite/ld-maxq/paddr.dd b/binutils-2.19/ld/testsuite/ld-maxq/paddr.dd
new file mode 100644
index 0000000..8f5ab48
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-maxq/paddr.dd
@@ -0,0 +1,16 @@
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	12 09 [ 	]*MOVE  A\[0\], #12h
+   2:	3a da [ 	]*NOP 
+   4:	3a da [ 	]*NOP 
+	...
+Disassembly of section .data:
+
+0000a000 <lb>:
+    a000:	23 00 [ 	]*MOVE  00h, #23h
+
+0000a002 <plc>:
+    a002:	00 a0 [ 	]*MOVE  20h, 00h
diff --git a/binutils-2.19/ld/testsuite/ld-maxq/paddr.s b/binutils-2.19/ld/testsuite/ld-maxq/paddr.s
new file mode 100644
index 0000000..693da88
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-maxq/paddr.s
@@ -0,0 +1,14 @@
+.text
+main:
+
+	move A[0], #12h
+	nop	
+	nop
+
+
+
+.data
+
+lb: .word 0x23
+plc: .word lb
+
diff --git a/binutils-2.19/ld/testsuite/ld-maxq/paddr1.dd b/binutils-2.19/ld/testsuite/ld-maxq/paddr1.dd
new file mode 100644
index 0000000..1297b83
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-maxq/paddr1.dd
@@ -0,0 +1,18 @@
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <main>:
+   0:	12 09       	MOVE  A\[0\], #12h
+   2:	3a da       	NOP 
+   4:	3a da       	NOP 
+	...
+Disassembly of section .data:
+
+0000a000 <lb>:
+    a000:	23 00       	MOVE  00h, #23h
+	...
+
+0000a004 <plc>:
+    a004:	00 a0       	MOVE  20h, 00h
+	...
diff --git a/binutils-2.19/ld/testsuite/ld-maxq/paddr1.s b/binutils-2.19/ld/testsuite/ld-maxq/paddr1.s
new file mode 100644
index 0000000..2f3d165
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-maxq/paddr1.s
@@ -0,0 +1,10 @@
+.text
+main:
+
+	move A[0], #12h
+	nop	
+	nop
+.data
+
+lb: .long 0x23
+plc: .long lb
diff --git a/binutils-2.19/ld/testsuite/ld-maxq/r32-1.s b/binutils-2.19/ld/testsuite/ld-maxq/r32-1.s
new file mode 100644
index 0000000..9cf38c1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-maxq/r32-1.s
@@ -0,0 +1,20 @@
+; Test the intersegment relocation
+; Inderpreetb@noida.hcltech.com
+
+.global _start
+.extern _main
+_start:
+	call _main
+	nop
+	nop
+	nop
+	nop
+.global _exit
+_exit:
+	nop
+	nop
+	nop
+.global _abort	
+_abort:
+	nop	
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-maxq/r32-2.s b/binutils-2.19/ld/testsuite/ld-maxq/r32-2.s
new file mode 100644
index 0000000..49bb59e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-maxq/r32-2.s
@@ -0,0 +1,13 @@
+;
+; test the intersegment relocation
+; inderpreetb@noida.hcltech.com
+.extern _start
+.extern _abort
+.extern _exit
+.global _main
+_main:
+	call _exit
+	call _abort
+	ljump _abort
+	ljump _exit
+
diff --git a/binutils-2.19/ld/testsuite/ld-maxq/r32.dd b/binutils-2.19/ld/testsuite/ld-maxq/r32.dd
new file mode 100644
index 0000000..f245ca9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-maxq/r32.dd
@@ -0,0 +1,31 @@
+.*: +file format .*
+
+Disassembly of section .text:
+
+00000000 <_start>:
+   0:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+   2:	0c 3d [ 	]*CALL  #0ch
+   4:	3a da [ 	]*NOP 
+   6:	3a da [ 	]*NOP 
+   8:	3a da [ 	]*NOP 
+   a:	3a da [ 	]*NOP 
+
+0000000c <_exit>:
+   c:	3a da [ 	]*NOP 
+   e:	3a da [ 	]*NOP 
+  10:	3a da [ 	]*NOP 
+
+00000012 <_abort>:
+  12:	3a da [ 	]*NOP 
+  14:	3a da [ 	]*NOP 
+	...
+
+00000018 <_main>:
+  18:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  1a:	06 3d [ 	]*CALL  #06h
+  1c:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  1e:	09 3d [ 	]*CALL  #09h
+  20:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  22:	09 0c [ 	]*JUMP  #09h
+  24:	00 0b [ 	]*MOVE  PFX\[0\], #00h
+  26:	06 0c [ 	]*JUMP  #06h
diff --git a/binutils-2.19/ld/testsuite/ld-mep/mep.exp b/binutils-2.19/ld/testsuite/ld-mep/mep.exp
new file mode 100644
index 0000000..3c54f8f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mep/mep.exp
@@ -0,0 +1,38 @@
+# Expect script for ld-mep tests
+#   Copyright 2002, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by DJ Delorie (dj@redhat.com)
+#
+
+# Test MeP linking for special cases.
+
+if ![istarget mep*-*-*] {
+    return
+}
+
+set testbsrweak "MeP bsr to undefined weak function"
+
+if ![ld_assemble $as "$srcdir/$subdir/mep1.s" tmpdir/mep1.o] {
+    unresolved $testbsrweak
+} else { if ![ld_simple_link $ld tmpdir/mep1 "-T$srcdir/$subdir/mep1.ld tmpdir/mep1.o"] {
+    fail $testbsrweak
+} else {
+    pass $testbsrweak
+} }
diff --git a/binutils-2.19/ld/testsuite/ld-mep/mep1.ld b/binutils-2.19/ld/testsuite/ld-mep/mep1.ld
new file mode 100644
index 0000000..d0a4104
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mep/mep1.ld
@@ -0,0 +1,8 @@
+SECTIONS
+{
+  /* This is beyond the normal range of a PCREL24 (bsr) relocation.  */
+  . = 0x100000;
+  .text1 : { *(.text1) }
+  . = 0x900000;
+  .text2 : { *(.text2) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mep/mep1.s b/binutils-2.19/ld/testsuite/ld-mep/mep1.s
new file mode 100644
index 0000000..ab5414f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mep/mep1.s
@@ -0,0 +1,13 @@
+	.weak	bar
+
+	# This will be in low memory.
+	.section .text1,"ax"
+	bsr	bar
+	jmp	bar
+
+	# This will be in high memory.
+	.section .text2,"ax"
+	# This needs special handling
+	bsr	bar
+	# This shouldn't
+	jmp	bar
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-0.s b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-0.s
new file mode 100644
index 0000000..a143746
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-0.s
@@ -0,0 +1 @@
+.gnu_attribute 4,0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-00.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-00.d
new file mode 100644
index 0000000..cd95356
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-00.d
@@ -0,0 +1,7 @@
+#source: attr-gnu-4-0.s
+#source: attr-gnu-4-0.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#target: mips*-*-*
+
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-01.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-01.d
new file mode 100644
index 0000000..3e68405
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-01.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-0.s
+#source: attr-gnu-4-1.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: Hard float \(-mdouble-float\)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-02.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-02.d
new file mode 100644
index 0000000..0641a85
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-02.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-0.s
+#source: attr-gnu-4-2.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: Hard float \(-msingle-float\)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-03.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-03.d
new file mode 100644
index 0000000..64f03f5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-03.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-0.s
+#source: attr-gnu-4-3.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: Soft float
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-04.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-04.d
new file mode 100644
index 0000000..992ed04
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-04.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-0.s
+#source: attr-gnu-4-4.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: 64-bit float \(-mips32r2 -mfp64\)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-05.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-05.d
new file mode 100644
index 0000000..ebfc6d8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-05.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-0.s
+#source: attr-gnu-4-5.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: \?\?\? \(5\)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-1.s
new file mode 100644
index 0000000..e985a56
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-1.s
@@ -0,0 +1 @@
+.gnu_attribute 4,1
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d
new file mode 100644
index 0000000..d57dd96
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-1.s
+#source: attr-gnu-4-0.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: Hard float \(-mdouble-float\)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-11.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-11.d
new file mode 100644
index 0000000..d694508
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-11.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-1.s
+#source: attr-gnu-4-1.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: Hard float \(-mdouble-float\)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-12.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-12.d
new file mode 100644
index 0000000..3ee6025
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-12.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-1.s
+#source: attr-gnu-4-2.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#warning: Warning: .* uses -msingle-float, .* uses -mdouble-float
+#target: mips*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-13.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-13.d
new file mode 100644
index 0000000..a48c119
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-13.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-1.s
+#source: attr-gnu-4-3.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#warning: Warning: .* uses hard float, .* uses soft float
+#target: mips*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-14.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-14.d
new file mode 100644
index 0000000..e899382
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-14.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-1.s
+#source: attr-gnu-4-4.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#warning: Warning: .* uses -msingle-float, .* uses -mips32r2 -mfp64
+#target: mips*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-15.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-15.d
new file mode 100644
index 0000000..cf32302
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-15.d
@@ -0,0 +1,11 @@
+#source: attr-gnu-4-1.s
+#source: attr-gnu-4-5.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#warning: Warning: .* uses unknown floating point ABI 5
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: Hard float \(-mdouble-float\)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-2.s b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-2.s
new file mode 100644
index 0000000..54ebf4e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-2.s
@@ -0,0 +1 @@
+.gnu_attribute 4,2
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-20.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-20.d
new file mode 100644
index 0000000..7ea84ab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-20.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-2.s
+#source: attr-gnu-4-0.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: Hard float \(-msingle-float\)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-21.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-21.d
new file mode 100644
index 0000000..3f84867
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-21.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-2.s
+#source: attr-gnu-4-1.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#warning: Warning: .* uses -msingle-float, .* uses -mdouble-float
+#target: mips*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-22.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-22.d
new file mode 100644
index 0000000..603e5c1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-22.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-2.s
+#source: attr-gnu-4-2.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: Hard float \(-msingle-float\)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-23.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-23.d
new file mode 100644
index 0000000..c0c14fd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-23.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-2.s
+#source: attr-gnu-4-3.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#warning: Warning: .* uses hard float, .* uses soft float
+#target: mips*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-24.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-24.d
new file mode 100644
index 0000000..09e8175
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-24.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-2.s
+#source: attr-gnu-4-4.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#warning: Warning: .* uses -mips32r2 -mfp64
+#target: mips*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-25.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-25.d
new file mode 100644
index 0000000..7701397
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-25.d
@@ -0,0 +1,11 @@
+#source: attr-gnu-4-2.s
+#source: attr-gnu-4-5.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#warning: Warning: .* uses unknown floating point ABI 5
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: Hard float \(-msingle-float\)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-3.s b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-3.s
new file mode 100644
index 0000000..32e5f5d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-3.s
@@ -0,0 +1 @@
+.gnu_attribute 4,3
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-30.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-30.d
new file mode 100644
index 0000000..d123328
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-30.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-3.s
+#source: attr-gnu-4-0.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: Soft float
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-31.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-31.d
new file mode 100644
index 0000000..6a629e7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-31.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-3.s
+#source: attr-gnu-4-1.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#warning: Warning: .* uses hard float, .* uses soft float
+#target: mips*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-32.d
new file mode 100644
index 0000000..824d467
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-32.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-3.s
+#source: attr-gnu-4-2.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#warning: Warning: .* uses hard float, .* uses soft float
+#target: mips*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-33.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-33.d
new file mode 100644
index 0000000..28d9d31
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-33.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-3.s
+#source: attr-gnu-4-3.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: Soft float
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-34.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-34.d
new file mode 100644
index 0000000..2a9b0f3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-34.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-3.s
+#source: attr-gnu-4-4.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#warning: Warning: .* uses hard float, .* uses soft float
+#target: mips*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-35.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-35.d
new file mode 100644
index 0000000..c3ad25f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-35.d
@@ -0,0 +1,11 @@
+#source: attr-gnu-4-3.s
+#source: attr-gnu-4-5.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#warning: Warning: .* uses unknown floating point ABI 5
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: Soft float
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-4.s b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-4.s
new file mode 100644
index 0000000..3ff129a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-4.s
@@ -0,0 +1 @@
+.gnu_attribute 4,4
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-40.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-40.d
new file mode 100644
index 0000000..f84e95b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-40.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-4.s
+#source: attr-gnu-4-0.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: 64-bit float \(-mips32r2 -mfp64\)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-41.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-41.d
new file mode 100644
index 0000000..71f74a9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-41.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-4.s
+#source: attr-gnu-4-1.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#warning: Warning: .* uses -msingle-float, .* uses -mips32r2 -mfp64
+#target: mips*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-42.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-42.d
new file mode 100644
index 0000000..c095695
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-42.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-4.s
+#source: attr-gnu-4-2.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#warning: Warning: .* uses -mips32r2 -mfp64
+#target: mips*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-43.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-43.d
new file mode 100644
index 0000000..8396e38
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-43.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-4.s
+#source: attr-gnu-4-3.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#warning: Warning: .* uses hard float, .* uses soft float
+#target: mips*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-44.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-44.d
new file mode 100644
index 0000000..6e8cac2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-44.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-4.s
+#source: attr-gnu-4-4.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#readelf: -A
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: 64-bit float \(-mips32r2 -mfp64\)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-45.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-45.d
new file mode 100644
index 0000000..11738c5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-45.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-4.s
+#source: attr-gnu-4-5.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#warning: Warning: .* uses unknown floating point ABI 5
+#target: mips*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_MIPS_ABI_FP: 64-bit float \(-mips32r2 -mfp64\)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-5.s b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-5.s
new file mode 100644
index 0000000..b21ec3b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-5.s
@@ -0,0 +1 @@
+.gnu_attribute 4,5
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-51.d b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-51.d
new file mode 100644
index 0000000..b5f1c22
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/attr-gnu-4-51.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-5.s
+#source: attr-gnu-4-1.s
+#as: -EB -32
+#ld: -r -melf32btsmip
+#warning: Warning: .* uses unknown floating point ABI 5
+#target: mips*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/branch-misc-1.d b/binutils-2.19/ld/testsuite/ld-mips-elf/branch-misc-1.d
new file mode 100644
index 0000000..0cd3701
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/branch-misc-1.d
@@ -0,0 +1,30 @@
+#name: MIPS branch-misc-1
+#source: ../../../gas/testsuite/gas/mips/branch-misc-1.s
+#objdump: --prefix-addresses -tdr --show-raw-insn
+#ld: -Ttext 0x20000000 -e 0x20000000 -N
+
+.*:     file format elf.*mips.*
+
+#...
+
+Disassembly of section \.text:
+	\.\.\.
+	\.\.\.
+	\.\.\.
+0*2000003c <[^>]*> 0411fff0 	bal	0*20000000 <[^>]*>
+0*20000040 <[^>]*> 00000000 	nop
+0*20000044 <[^>]*> 0411fff3 	bal	0*20000014 <[^>]*>
+0*20000048 <[^>]*> 00000000 	nop
+0*2000004c <[^>]*> 0411fff6 	bal	0*20000028 <[^>]*>
+0*20000050 <[^>]*> 00000000 	nop
+0*20000054 <[^>]*> 0411000a 	bal	0*20000080 <[^>]*>
+0*20000058 <[^>]*> 00000000 	nop
+0*2000005c <[^>]*> 0411000d 	bal	0*20000094 <[^>]*>
+0*20000060 <[^>]*> 00000000 	nop
+0*20000064 <[^>]*> 04110010 	bal	0*200000a8 <[^>]*>
+0*20000068 <[^>]*> 00000000 	nop
+	\.\.\.
+	\.\.\.
+	\.\.\.
+	\.\.\.
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/dyn-sec64.d b/binutils-2.19/ld/testsuite/ld-mips-elf/dyn-sec64.d
new file mode 100644
index 0000000..9564c11
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/dyn-sec64.d
@@ -0,0 +1,30 @@
+#name: objdump -p print 64-bit values
+#source: dyn-sec64.s
+#as: -mips3 -EB -64
+#ld: -Tdyn-sec64.ld -shared -melf64btsmip
+#objdump: -p
+
+.*: .* file format .*
+
+Program Header:
+.* LOAD .*
+.*
+.* LOAD .*
+.*
+.* DYNAMIC .*
+.*
+.* NULL .*
+.*
+
+Dynamic Section:
+
+  INIT .* 0x0001234000003000
+  FINI .* 0x0001234000004000
+  HASH .* 0x0001234000001000
+  STRTAB .*
+  SYMTAB .*
+  STRSZ .*
+  SYMENT .*
+  PLTGOT .* 0x0001235000000000
+  REL .* 0x0001234000002000
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/dyn-sec64.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/dyn-sec64.ld
new file mode 100644
index 0000000..bb75d73
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/dyn-sec64.ld
@@ -0,0 +1,23 @@
+SECTIONS
+{
+  . = 0x1234000000000;
+  .dynamic : { *(.dynamic) }
+  . = 0x1234000001000;
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+  . = 0x1234000002000;
+  .rel.dyn : { *(.rel.dyn) }
+
+  . = 0x1234000003000;
+  .init : { *(.init) }
+  . = 0x1234000004000;
+  .fini : { *(.fini) }
+  .text : { *(.text) }
+  .MIPS.stubs : { *(.MIPS.stubs) }
+
+  . = 0x1235000000000;
+  _gp = ALIGN (16) + 0x7ff0;
+  .got : { *(.got) }
+  .data : { *(.data) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/dyn-sec64.s b/binutils-2.19/ld/testsuite/ld-mips-elf/dyn-sec64.s
new file mode 100644
index 0000000..7d634ee
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/dyn-sec64.s
@@ -0,0 +1,19 @@
+        .section .init,"ax",@progbits
+	.globl	_init
+	.ent	_init
+	.type	_init, @function
+_init:
+        ld      $2,%call16(bar)
+	.end	_init
+
+        .section .fini,"ax",@progbits
+	.globl	_fini
+	.ent	_fini
+	.type	_fini, @function
+_fini:
+	.end	_fini
+
+	.data
+foo:
+	.dword	bar
+
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame1-n32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame1-n32.d
new file mode 100644
index 0000000..3924016
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame1-n32.d
@@ -0,0 +1,202 @@
+#name: MIPS eh-frame 1, n32
+#source: eh-frame1.s
+#source: eh-frame1.s
+#as: -EB -n32 --defsym alignment=2 --defsym fill=0x40
+#readelf: --relocs -wf
+#ld: -shared -melf32btsmipn32 -Teh-frame1.ld
+#warning: fde encoding in.*prevents \.eh_frame_hdr table being created.
+
+Relocation section '\.rel\.dyn' .*:
+ *Offset .*
+00000000  [0-9a-f]+ R_MIPS_NONE *
+# Initial PCs for the FDEs attached to CIE 0xbc
+000300dc  [0-9a-f]+ R_MIPS_REL32 *
+000300f0  [0-9a-f]+ R_MIPS_REL32 *
+000301f8  [0-9a-f]+ R_MIPS_REL32 *
+0003020c  [0-9a-f]+ R_MIPS_REL32 *
+0003008b  [0-9a-f]+ R_MIPS_REL32      00000000   foo
+000300d0  [0-9a-f]+ R_MIPS_REL32      00000000   foo
+0003010e  [0-9a-f]+ R_MIPS_REL32      00000000   foo
+The section \.eh_frame contains:
+
+00000000 00000010 00000000 CIE
+  Version:               1
+  Augmentation:          "zR"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     10
+
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+
+00000014 00000010 00000018 FDE cie=00000000 pc=00020000..00020010
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000028 00000010 0000002c FDE cie=00000000 pc=00020010..00020030
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic2 removed
+0000003c 00000010 00000040 FDE cie=00000000 pc=00020030..00020060
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic3 removed
+00000050 00000010 00000054 FDE cie=00000000 pc=00020060..000200a0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic4 removed
+00000064 00000010 00000068 FDE cie=00000000 pc=000200a0..000200f0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000078 00000018 00000000 CIE
+  Version:               1
+  Augmentation:          "zRP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     10 00 00 00 00 00
+
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000094 00000010 00000020 FDE cie=00000078 pc=000200f0..00020100
+  DW_CFA_advance_loc: 0 to 000200f0
+  DW_CFA_advance_loc: 0 to 000200f0
+  DW_CFA_advance_loc: 0 to 000200f0
+
+000000a8 00000010 00000034 FDE cie=00000078 pc=00020100..00020120
+  DW_CFA_advance_loc: 0 to 00020100
+  DW_CFA_advance_loc: 0 to 00020100
+  DW_CFA_advance_loc: 0 to 00020100
+
+000000bc 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     50 00 00 00 00 00 00 00
+
+
+000000d4 00000010 0000001c FDE cie=000000bc pc=00020120..00020130
+  DW_CFA_advance_loc: 0 to 00020120
+  DW_CFA_advance_loc: 0 to 00020120
+  DW_CFA_advance_loc: 0 to 00020120
+
+000000e8 00000010 00000030 FDE cie=000000bc pc=00020130..00020150
+  DW_CFA_advance_loc: 0 to 00020130
+  DW_CFA_advance_loc: 0 to 00020130
+  DW_CFA_advance_loc: 0 to 00020130
+
+000000fc 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zPR"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     00 00 00 00 00 10
+
+  DW_CFA_advance_loc: 0 to 00000000
+
+00000114 00000010 0000001c FDE cie=000000fc pc=00020150..00020160
+  DW_CFA_advance_loc: 0 to 00020150
+  DW_CFA_advance_loc: 0 to 00020150
+  DW_CFA_advance_loc: 0 to 00020150
+
+# FDE for .discard removed
+# zPR2 removed
+00000128 00000010 00000030 FDE cie=000000fc pc=00020160..00020190
+  DW_CFA_advance_loc: 0 to 00020160
+  DW_CFA_advance_loc: 0 to 00020160
+  DW_CFA_advance_loc: 0 to 00020160
+
+0000013c 00000010 00000044 FDE cie=000000fc pc=00020190..000201d0
+  DW_CFA_advance_loc: 0 to 00020190
+  DW_CFA_advance_loc: 0 to 00020190
+  DW_CFA_advance_loc: 0 to 00020190
+
+00000150 00000010 00000154 FDE cie=00000000 pc=000201d0..000201e0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic1 removed, followed by repeat of above
+00000164 00000010 00000168 FDE cie=00000000 pc=000201e0..000201f0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000178 00000010 0000017c FDE cie=00000000 pc=000201f0..00020210
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+0000018c 00000010 00000190 FDE cie=00000000 pc=00020210..00020240
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001a0 00000010 000001a4 FDE cie=00000000 pc=00020240..00020280
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001b4 00000010 000001b8 FDE cie=00000000 pc=00020280..000202d0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001c8 00000010 00000154 FDE cie=00000078 pc=000202d0..000202e0
+  DW_CFA_advance_loc: 0 to 000202d0
+  DW_CFA_advance_loc: 0 to 000202d0
+  DW_CFA_advance_loc: 0 to 000202d0
+
+000001dc 00000010 00000168 FDE cie=00000078 pc=000202e0..00020300
+  DW_CFA_advance_loc: 0 to 000202e0
+  DW_CFA_advance_loc: 0 to 000202e0
+  DW_CFA_advance_loc: 0 to 000202e0
+
+000001f0 00000010 00000138 FDE cie=000000bc pc=00020300..00020310
+  DW_CFA_advance_loc: 0 to 00020300
+  DW_CFA_advance_loc: 0 to 00020300
+  DW_CFA_advance_loc: 0 to 00020300
+
+00000204 00000010 0000014c FDE cie=000000bc pc=00020310..00020330
+  DW_CFA_advance_loc: 0 to 00020310
+  DW_CFA_advance_loc: 0 to 00020310
+  DW_CFA_advance_loc: 0 to 00020310
+
+00000218 00000010 00000120 FDE cie=000000fc pc=00020330..00020340
+  DW_CFA_advance_loc: 0 to 00020330
+  DW_CFA_advance_loc: 0 to 00020330
+  DW_CFA_advance_loc: 0 to 00020330
+
+0000022c 00000010 00000134 FDE cie=000000fc pc=00020340..00020370
+  DW_CFA_advance_loc: 0 to 00020340
+  DW_CFA_advance_loc: 0 to 00020340
+  DW_CFA_advance_loc: 0 to 00020340
+
+00000240 00000010 00000148 FDE cie=000000fc pc=00020370..000203b0
+  DW_CFA_advance_loc: 0 to 00020370
+  DW_CFA_advance_loc: 0 to 00020370
+  DW_CFA_advance_loc: 0 to 00020370
+
+00000254 00000010 00000258 FDE cie=00000000 pc=000203b0..000203c0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame1-n64.d b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame1-n64.d
new file mode 100644
index 0000000..f0925b9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame1-n64.d
@@ -0,0 +1,338 @@
+#name: MIPS eh-frame 1, n64
+#source: eh-frame1.s
+#source: eh-frame1.s
+#as: -EB -64 --defsym alignment=3 --defsym fill=0x40
+#readelf: --relocs -wf
+#ld: -shared -melf64btsmip -Teh-frame1.ld
+#warning: fde encoding in.*prevents \.eh_frame_hdr table being created.
+
+Relocation section '\.rel\.dyn' .*:
+ *Offset .*
+000000000000  [0-9a-f]+ R_MIPS_NONE *
+ *Type2: R_MIPS_NONE *
+ *Type3: R_MIPS_NONE *
+# Initial PCs for the FDEs attached to CIE 0x120
+000000030148  [0-9a-f]+ R_MIPS_REL32 *
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+000000030168  [0-9a-f]+ R_MIPS_REL32 *
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+000000030308  [0-9a-f]+ R_MIPS_REL32 *
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+000000030328  [0-9a-f]+ R_MIPS_REL32 *
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+0000000300cb  [0-9a-f]+ R_MIPS_REL32      0000000000000000 foo
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+000000030138  [0-9a-f]+ R_MIPS_REL32      0000000000000000 foo
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+000000030192  [0-9a-f]+ R_MIPS_REL32      0000000000000000 foo
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+The section \.eh_frame contains:
+
+00000000 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zR"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     10
+
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000018 0000001c 0000001c FDE cie=00000000 pc=00020000..00020010
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000038 0000001c 0000003c FDE cie=00000000 pc=00020010..00020030
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic2 removed
+00000058 0000001c 0000005c FDE cie=00000000 pc=00020030..00020060
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic3 removed
+00000078 0000001c 0000007c FDE cie=00000000 pc=00020060..000200a0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic4 removed
+00000098 0000001c 0000009c FDE cie=00000000 pc=000200a0..000200f0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000b8 00000024 00000000 CIE
+  Version:               1
+  Augmentation:          "zRP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     10 00 00 00 00 00 00 00 00 00
+
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000e0 0000001c 0000002c FDE cie=000000b8 pc=000200f0..00020100
+  DW_CFA_advance_loc: 0 to 000200f0
+  DW_CFA_advance_loc: 0 to 000200f0
+  DW_CFA_advance_loc: 0 to 000200f0
+  DW_CFA_advance_loc: 0 to 000200f0
+  DW_CFA_advance_loc: 0 to 000200f0
+  DW_CFA_advance_loc: 0 to 000200f0
+  DW_CFA_advance_loc: 0 to 000200f0
+
+00000100 0000001c 0000004c FDE cie=000000b8 pc=00020100..00020120
+  DW_CFA_advance_loc: 0 to 00020100
+  DW_CFA_advance_loc: 0 to 00020100
+  DW_CFA_advance_loc: 0 to 00020100
+  DW_CFA_advance_loc: 0 to 00020100
+  DW_CFA_advance_loc: 0 to 00020100
+  DW_CFA_advance_loc: 0 to 00020100
+  DW_CFA_advance_loc: 0 to 00020100
+
+00000120 0000001c 00000000 CIE
+  Version:               1
+  Augmentation:          "zP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+
+00000140 0000001c 00000024 FDE cie=00000120 pc=00020120..00020130
+  DW_CFA_advance_loc: 0 to 00020120
+  DW_CFA_advance_loc: 0 to 00020120
+  DW_CFA_advance_loc: 0 to 00020120
+  DW_CFA_advance_loc: 0 to 00020120
+  DW_CFA_advance_loc: 0 to 00020120
+  DW_CFA_advance_loc: 0 to 00020120
+  DW_CFA_advance_loc: 0 to 00020120
+
+00000160 0000001c 00000044 FDE cie=00000120 pc=00020130..00020150
+  DW_CFA_advance_loc: 0 to 00020130
+  DW_CFA_advance_loc: 0 to 00020130
+  DW_CFA_advance_loc: 0 to 00020130
+  DW_CFA_advance_loc: 0 to 00020130
+  DW_CFA_advance_loc: 0 to 00020130
+  DW_CFA_advance_loc: 0 to 00020130
+  DW_CFA_advance_loc: 0 to 00020130
+
+00000180 0000001c 00000000 CIE
+  Version:               1
+  Augmentation:          "zPR"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     00 00 00 00 00 00 00 00 00 10
+
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+  DW_CFA_advance_loc: 0 to 00000000
+
+000001a0 0000001c 00000024 FDE cie=00000180 pc=00020150..00020160
+  DW_CFA_advance_loc: 0 to 00020150
+  DW_CFA_advance_loc: 0 to 00020150
+  DW_CFA_advance_loc: 0 to 00020150
+  DW_CFA_advance_loc: 0 to 00020150
+  DW_CFA_advance_loc: 0 to 00020150
+  DW_CFA_advance_loc: 0 to 00020150
+  DW_CFA_advance_loc: 0 to 00020150
+
+# FDE for .discard removed
+# zPR2 removed
+000001c0 0000001c 00000044 FDE cie=00000180 pc=00020160..00020190
+  DW_CFA_advance_loc: 0 to 00020160
+  DW_CFA_advance_loc: 0 to 00020160
+  DW_CFA_advance_loc: 0 to 00020160
+  DW_CFA_advance_loc: 0 to 00020160
+  DW_CFA_advance_loc: 0 to 00020160
+  DW_CFA_advance_loc: 0 to 00020160
+  DW_CFA_advance_loc: 0 to 00020160
+
+000001e0 0000001c 00000064 FDE cie=00000180 pc=00020190..000201d0
+  DW_CFA_advance_loc: 0 to 00020190
+  DW_CFA_advance_loc: 0 to 00020190
+  DW_CFA_advance_loc: 0 to 00020190
+  DW_CFA_advance_loc: 0 to 00020190
+  DW_CFA_advance_loc: 0 to 00020190
+  DW_CFA_advance_loc: 0 to 00020190
+  DW_CFA_advance_loc: 0 to 00020190
+
+00000200 0000001c 00000204 FDE cie=00000000 pc=000201d0..000201e0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic1 removed, followed by repeat of above
+00000220 0000001c 00000224 FDE cie=00000000 pc=000201e0..000201f0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000240 0000001c 00000244 FDE cie=00000000 pc=000201f0..00020210
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000260 0000001c 00000264 FDE cie=00000000 pc=00020210..00020240
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000280 0000001c 00000284 FDE cie=00000000 pc=00020240..00020280
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000002a0 0000001c 000002a4 FDE cie=00000000 pc=00020280..000202d0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000002c0 0000001c 0000020c FDE cie=000000b8 pc=000202d0..000202e0
+  DW_CFA_advance_loc: 0 to 000202d0
+  DW_CFA_advance_loc: 0 to 000202d0
+  DW_CFA_advance_loc: 0 to 000202d0
+  DW_CFA_advance_loc: 0 to 000202d0
+  DW_CFA_advance_loc: 0 to 000202d0
+  DW_CFA_advance_loc: 0 to 000202d0
+  DW_CFA_advance_loc: 0 to 000202d0
+
+000002e0 0000001c 0000022c FDE cie=000000b8 pc=000202e0..00020300
+  DW_CFA_advance_loc: 0 to 000202e0
+  DW_CFA_advance_loc: 0 to 000202e0
+  DW_CFA_advance_loc: 0 to 000202e0
+  DW_CFA_advance_loc: 0 to 000202e0
+  DW_CFA_advance_loc: 0 to 000202e0
+  DW_CFA_advance_loc: 0 to 000202e0
+  DW_CFA_advance_loc: 0 to 000202e0
+
+00000300 0000001c 000001e4 FDE cie=00000120 pc=00020300..00020310
+  DW_CFA_advance_loc: 0 to 00020300
+  DW_CFA_advance_loc: 0 to 00020300
+  DW_CFA_advance_loc: 0 to 00020300
+  DW_CFA_advance_loc: 0 to 00020300
+  DW_CFA_advance_loc: 0 to 00020300
+  DW_CFA_advance_loc: 0 to 00020300
+  DW_CFA_advance_loc: 0 to 00020300
+
+00000320 0000001c 00000204 FDE cie=00000120 pc=00020310..00020330
+  DW_CFA_advance_loc: 0 to 00020310
+  DW_CFA_advance_loc: 0 to 00020310
+  DW_CFA_advance_loc: 0 to 00020310
+  DW_CFA_advance_loc: 0 to 00020310
+  DW_CFA_advance_loc: 0 to 00020310
+  DW_CFA_advance_loc: 0 to 00020310
+  DW_CFA_advance_loc: 0 to 00020310
+
+00000340 0000001c 000001c4 FDE cie=00000180 pc=00020330..00020340
+  DW_CFA_advance_loc: 0 to 00020330
+  DW_CFA_advance_loc: 0 to 00020330
+  DW_CFA_advance_loc: 0 to 00020330
+  DW_CFA_advance_loc: 0 to 00020330
+  DW_CFA_advance_loc: 0 to 00020330
+  DW_CFA_advance_loc: 0 to 00020330
+  DW_CFA_advance_loc: 0 to 00020330
+
+00000360 0000001c 000001e4 FDE cie=00000180 pc=00020340..00020370
+  DW_CFA_advance_loc: 0 to 00020340
+  DW_CFA_advance_loc: 0 to 00020340
+  DW_CFA_advance_loc: 0 to 00020340
+  DW_CFA_advance_loc: 0 to 00020340
+  DW_CFA_advance_loc: 0 to 00020340
+  DW_CFA_advance_loc: 0 to 00020340
+  DW_CFA_advance_loc: 0 to 00020340
+
+00000380 0000001c 00000204 FDE cie=00000180 pc=00020370..000203b0
+  DW_CFA_advance_loc: 0 to 00020370
+  DW_CFA_advance_loc: 0 to 00020370
+  DW_CFA_advance_loc: 0 to 00020370
+  DW_CFA_advance_loc: 0 to 00020370
+  DW_CFA_advance_loc: 0 to 00020370
+  DW_CFA_advance_loc: 0 to 00020370
+  DW_CFA_advance_loc: 0 to 00020370
+
+000003a0 0000001c 000003a4 FDE cie=00000000 pc=000203b0..000203c0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame1.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame1.ld
new file mode 100644
index 0000000..93c4972
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame1.ld
@@ -0,0 +1,19 @@
+SECTIONS
+{
+  . = 0x10000;
+  .dynamic : { *(.dynamic) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+  .rel.dyn : { *(.rel.dyn) }
+
+  . = 0x20000;
+  .text : { *(.text) }
+
+  . = 0x30000;
+  .eh_frame : { *(.eh_frame) }
+  .got : { *(.got) }
+  .gcc_compiled_long32 : { *(.gcc_compiled_long32) }
+
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame1.s
new file mode 100644
index 0000000..94ed70d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame1.s
@@ -0,0 +1,152 @@
+#----------------------------------------------------------------------------
+# Macros
+#----------------------------------------------------------------------------
+
+	mask = (1 << alignment) - 1
+
+	# Output VALUE as an unaligned pointer-sized quantity.
+	.macro pbyte value
+	.if alignment == 2
+	.4byte		\value
+	.else
+	.8byte		\value
+	.endif
+	.endm
+
+
+	# Start a new CIE, and emit everything up to the augmentation data.
+	# Use LABEL to mark the start of the entry and AUG as the augmentation
+	# string.
+	.macro start_cie label,aug
+	.section	.eh_frame,"aw",@progbits
+\label:
+	.word		2f-1f		# Length
+1:
+	.word		0		# Identifier
+	.byte		1		# Version
+	.string		"\aug"		# Augmentation
+	.byte		1		# Code alignment
+	.byte		4		# Data alignment
+	.byte		31		# Return address column
+	.endm
+
+
+	# Create a dummy function of SIZE bytes in SECTION and emit the
+	# first four entries of an FDE for it.
+	.macro start_fde cie,section,size
+	.section	\section,"ax",@progbits
+3:
+	.rept		\size / 4
+	nop
+	.endr
+4:
+	.section	.eh_frame,"aw",@progbits
+	.word		2f-1f		# Length
+1:
+	.word		.-\cie		# CIE offset
+	pbyte		3b		# Initial PC
+	pbyte		4b-3b		# Size of code
+	.endm
+
+
+	# Finish a CIE or FDE entry.
+	.macro end_entry
+	.p2align	alignment,fill
+2:
+	.endm
+
+
+	# Start the augmentation data for a CIE that has a 'P' entry
+	# followed by EXTRA bytes.  AUGLEN is the length of augmentation
+	# string (including zero terminator), ENCODING is the encoding to
+	# use for the personality routine and VALUE is the value it
+	# should have.
+	.macro		persaug auglen,extra,encoding,value
+	.if (\encoding & 0xf0) == 0x50
+	.byte		(-(9 + \auglen + 3 + 2) & mask) + 2 + mask + \extra
+	.byte		\encoding
+	.fill		-(9 + \auglen + 3 + 2) & mask,1,0
+	.else
+	.byte		2 + mask + \extra
+	.byte		\encoding
+	.endif
+	pbyte		\value
+	.endm
+
+
+	.macro cie_basic label
+	start_cie	\label,""
+	end_entry
+	.endm
+
+	.macro fde_basic cie,section,size
+	start_fde	\cie,\section,\size
+	end_entry
+	.endm
+
+
+	.macro cie_zP label,encoding,value
+	start_cie	 \label,"zP"
+	persaug		3,0,\encoding,\value
+	end_entry
+	.endm
+
+	.macro fde_zP cie,section,size
+	start_fde	 \cie,\section,\size
+	.byte		 0		# Augmentation length
+	end_entry
+	.endm
+
+
+	.macro cie_zPR label,encoding,value
+	start_cie	 \label,"zPR"
+	persaug		4,1,\encoding,\value
+	.byte		0		# FDE enconding
+	end_entry
+	.endm
+
+	.macro fde_zPR cie,section,size
+	start_fde	\cie,\section,\size
+	.byte		0		# Augmentation length
+	end_entry
+	.endm
+
+#----------------------------------------------------------------------------
+# Test code
+#----------------------------------------------------------------------------
+
+	cie_basic	basic1
+	fde_basic	basic1,.text,0x10
+	fde_basic	basic1,.text,0x20
+
+	cie_basic	basic2
+	fde_basic	basic2,.text,0x30
+
+	cie_basic	basic3
+	fde_basic	basic3,.text,0x40
+
+	cie_basic	basic4
+	fde_basic	basic4,.text,0x50
+
+	cie_zP		zP_unalign1,0x00,foo
+	fde_zP		zP_unalign1,.text,0x10
+	fde_zP		zP_unalign1,.text,0x20
+
+	cie_zP		zP_align1,0x50,foo
+	fde_zP		zP_align1,.text,0x10
+	fde_zP		zP_align1,.text,0x20
+
+	cie_zPR		zPR1,0x00,foo
+	fde_zPR		zPR1,.text,0x10
+	fde_zPR		zPR1,.discard,0x20
+
+	cie_zPR		zPR2,0x00,foo
+	fde_zPR		zPR2,.text,0x30
+	fde_zPR		zPR2,.text,0x40
+
+	cie_basic	basic5
+	fde_basic	basic5,.text,0x10
+
+	.if alignment == 2
+	.section	.gcc_compiled_long32
+	.endif
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame2-n32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame2-n32.d
new file mode 100644
index 0000000..ce2aa1d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame2-n32.d
@@ -0,0 +1,198 @@
+#name: MIPS eh-frame 2, n32
+#source: eh-frame1.s
+#source: eh-frame1.s
+#as: -EB -n32 --defsym alignment=2 --defsym fill=0
+#readelf: --relocs -wf
+#ld: -shared -melf32btsmipn32 -Teh-frame1.ld
+#warning: fde encoding in.*prevents \.eh_frame_hdr table being created.
+
+Relocation section '\.rel\.dyn' .*:
+ *Offset .*
+00000000  [0-9a-f]+ R_MIPS_NONE *
+# Initial PCs for the FDEs attached to CIE 0xb8
+000300d8  [0-9a-f]+ R_MIPS_REL32 *
+000300ec  [0-9a-f]+ R_MIPS_REL32 *
+000301f4  [0-9a-f]+ R_MIPS_REL32 *
+00030208  [0-9a-f]+ R_MIPS_REL32 *
+0003008b  [0-9a-f]+ R_MIPS_REL32      00000000   foo
+000300cc  [0-9a-f]+ R_MIPS_REL32      00000000   foo
+0003010a  [0-9a-f]+ R_MIPS_REL32      00000000   foo
+The section \.eh_frame contains:
+
+00000000 00000010 00000000 CIE
+  Version:               1
+  Augmentation:          "zR"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     10
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000014 00000010 00000018 FDE cie=00000000 pc=00020000..00020010
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000028 00000010 0000002c FDE cie=00000000 pc=00020010..00020030
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic2 removed
+0000003c 00000010 00000040 FDE cie=00000000 pc=00020030..00020060
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic3 removed
+00000050 00000010 00000054 FDE cie=00000000 pc=00020060..000200a0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic4 removed
+00000064 00000010 00000068 FDE cie=00000000 pc=000200a0..000200f0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000078 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zRP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     10 00 00 00 00 00
+
+  DW_CFA_nop
+
+00000090 00000010 0000001c FDE cie=00000078 pc=000200f0..00020100
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000a4 00000010 00000030 FDE cie=00000078 pc=00020100..00020120
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000b8 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     50 00 00 00 00 00 00 00
+
+
+000000d0 00000010 0000001c FDE cie=000000b8 pc=00020120..00020130
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000e4 00000010 00000030 FDE cie=000000b8 pc=00020130..00020150
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000f8 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zPR"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     00 00 00 00 00 10
+
+  DW_CFA_nop
+
+00000110 00000010 0000001c FDE cie=000000f8 pc=00020150..00020160
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# FDE for .discard removed
+# zPR2 removed
+00000124 00000010 00000030 FDE cie=000000f8 pc=00020160..00020190
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000138 00000010 00000044 FDE cie=000000f8 pc=00020190..000201d0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+0000014c 00000010 00000150 FDE cie=00000000 pc=000201d0..000201e0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic1 removed, followed by repeat of above
+00000160 00000010 00000164 FDE cie=00000000 pc=000201e0..000201f0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000174 00000010 00000178 FDE cie=00000000 pc=000201f0..00020210
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000188 00000010 0000018c FDE cie=00000000 pc=00020210..00020240
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+0000019c 00000010 000001a0 FDE cie=00000000 pc=00020240..00020280
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001b0 00000010 000001b4 FDE cie=00000000 pc=00020280..000202d0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001c4 00000010 00000150 FDE cie=00000078 pc=000202d0..000202e0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001d8 00000010 00000164 FDE cie=00000078 pc=000202e0..00020300
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001ec 00000010 00000138 FDE cie=000000b8 pc=00020300..00020310
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000200 00000010 0000014c FDE cie=000000b8 pc=00020310..00020330
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000214 00000010 00000120 FDE cie=000000f8 pc=00020330..00020340
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000228 00000010 00000134 FDE cie=000000f8 pc=00020340..00020370
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+0000023c 00000010 00000148 FDE cie=000000f8 pc=00020370..000203b0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000250 00000010 00000254 FDE cie=00000000 pc=000203b0..000203c0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame2-n64.d b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame2-n64.d
new file mode 100644
index 0000000..50394f5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame2-n64.d
@@ -0,0 +1,330 @@
+#name: MIPS eh-frame 2, n64
+#source: eh-frame1.s
+#source: eh-frame1.s
+#as: -EB -64 --defsym alignment=3 --defsym fill=0
+#readelf: --relocs -wf
+#ld: -shared -melf64btsmip -Teh-frame1.ld
+#warning: fde encoding in.*prevents \.eh_frame_hdr table being created.
+
+Relocation section '\.rel\.dyn' .*:
+ *Offset .*
+000000000000  [0-9a-f]+ R_MIPS_NONE *
+ *Type2: R_MIPS_NONE *
+ *Type3: R_MIPS_NONE *
+# Initial PCs for the FDEs attached to CIE 0x118
+000000030140  [0-9a-f]+ R_MIPS_REL32 *
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+000000030160  [0-9a-f]+ R_MIPS_REL32 *
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+000000030300  [0-9a-f]+ R_MIPS_REL32 *
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+000000030320  [0-9a-f]+ R_MIPS_REL32 *
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+0000000300cb  [0-9a-f]+ R_MIPS_REL32      0000000000000000 foo
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+000000030130  [0-9a-f]+ R_MIPS_REL32      0000000000000000 foo
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+00000003018a  [0-9a-f]+ R_MIPS_REL32      0000000000000000 foo
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+The section \.eh_frame contains:
+
+00000000 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zR"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     10
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000018 0000001c 0000001c FDE cie=00000000 pc=00020000..00020010
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000038 0000001c 0000003c FDE cie=00000000 pc=00020010..00020030
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic2 removed
+00000058 0000001c 0000005c FDE cie=00000000 pc=00020030..00020060
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic3 removed
+00000078 0000001c 0000007c FDE cie=00000000 pc=00020060..000200a0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic4 removed
+00000098 0000001c 0000009c FDE cie=00000000 pc=000200a0..000200f0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000b8 0000001c 00000000 CIE
+  Version:               1
+  Augmentation:          "zRP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     10 00 00 00 00 00 00 00 00 00
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000d8 0000001c 00000024 FDE cie=000000b8 pc=000200f0..00020100
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000f8 0000001c 00000044 FDE cie=000000b8 pc=00020100..00020120
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000118 0000001c 00000000 CIE
+  Version:               1
+  Augmentation:          "zP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     50 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
+
+00000138 0000001c 00000024 FDE cie=00000118 pc=00020120..00020130
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000158 0000001c 00000044 FDE cie=00000118 pc=00020130..00020150
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000178 0000001c 00000000 CIE
+  Version:               1
+  Augmentation:          "zPR"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     00 00 00 00 00 00 00 00 00 10
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000198 0000001c 00000024 FDE cie=00000178 pc=00020150..00020160
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# FDE for .discard removed
+# zPR2 removed
+000001b8 0000001c 00000044 FDE cie=00000178 pc=00020160..00020190
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001d8 0000001c 00000064 FDE cie=00000178 pc=00020190..000201d0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001f8 0000001c 000001fc FDE cie=00000000 pc=000201d0..000201e0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# basic1 removed, followed by repeat of above
+00000218 0000001c 0000021c FDE cie=00000000 pc=000201e0..000201f0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000238 0000001c 0000023c FDE cie=00000000 pc=000201f0..00020210
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000258 0000001c 0000025c FDE cie=00000000 pc=00020210..00020240
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000278 0000001c 0000027c FDE cie=00000000 pc=00020240..00020280
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000298 0000001c 0000029c FDE cie=00000000 pc=00020280..000202d0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000002b8 0000001c 00000204 FDE cie=000000b8 pc=000202d0..000202e0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000002d8 0000001c 00000224 FDE cie=000000b8 pc=000202e0..00020300
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000002f8 0000001c 000001e4 FDE cie=00000118 pc=00020300..00020310
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000318 0000001c 00000204 FDE cie=00000118 pc=00020310..00020330
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000338 0000001c 000001c4 FDE cie=00000178 pc=00020330..00020340
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000358 0000001c 000001e4 FDE cie=00000178 pc=00020340..00020370
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000378 0000001c 00000204 FDE cie=00000178 pc=00020370..000203b0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000398 0000001c 0000039c FDE cie=00000000 pc=000203b0..000203c0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame3.d b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame3.d
new file mode 100644
index 0000000..4c91d2c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame3.d
@@ -0,0 +1,281 @@
+#name: MIPS eh-frame 3
+#source: eh-frame1.s
+#source: eh-frame1.s
+#as: -EB -mips3 -mabi=eabi --defsym alignment=3 --defsym fill=0 --defsym foo=0x1020304050607080
+#readelf: -wf
+#ld: -EB -Teh-frame1.ld
+#
+# This test is for the official LP64 version of EABI64, which uses a
+# combination of 32-bit objects and 64-bit FDE addresses.
+#
+
+The section \.eh_frame contains:
+
+00000000 0000000c 00000000 CIE
+  Version:               1
+  Augmentation:          ""
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000010 00000014 00000014 FDE cie=00000000 pc=00020000..00020010
+
+00000028 00000014 0000002c FDE cie=00000000 pc=00020010..00020030
+
+# basic2 removed
+00000040 00000014 00000044 FDE cie=00000000 pc=00020030..00020060
+
+# basic3 removed
+00000058 00000014 0000005c FDE cie=00000000 pc=00020060..000200a0
+
+# basic4 removed
+00000070 00000014 00000074 FDE cie=00000000 pc=000200a0..000200f0
+
+00000088 0000001c 00000000 CIE
+  Version:               1
+  Augmentation:          "zP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     00 10 20 30 40 50 60 70 80
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000a8 0000001c 00000024 FDE cie=00000088 pc=000200f0..00020100
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000c8 0000001c 00000044 FDE cie=00000088 pc=00020100..00020120
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000e8 0000001c 00000000 CIE
+  Version:               1
+  Augmentation:          "zP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     50 00 00 00 00 00 00 00 10 20 30 40 50 60 70 80
+
+
+00000108 0000001c 00000024 FDE cie=000000e8 pc=00020120..00020130
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000128 0000001c 00000044 FDE cie=000000e8 pc=00020130..00020150
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000148 0000001c 00000000 CIE
+  Version:               1
+  Augmentation:          "zPR"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     00 10 20 30 40 50 60 70 80 00
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000168 0000001c 00000024 FDE cie=00000148 pc=00020150..00020160
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# FDE for .discard removed
+# zPR2 removed
+00000188 0000001c 00000044 FDE cie=00000148 pc=00020160..00020190
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001a8 0000001c 00000064 FDE cie=00000148 pc=00020190..000201d0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001c8 0000000c 00000000 CIE
+  Version:               1
+  Augmentation:          ""
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001d8 00000014 00000014 FDE cie=000001c8 pc=000201d0..000201e0
+
+# basic1 removed, followed by repeat of above
+000001f0 00000014 0000002c FDE cie=000001c8 pc=000201e0..000201f0
+
+00000208 00000014 00000044 FDE cie=000001c8 pc=000201f0..00020210
+
+00000220 00000014 0000005c FDE cie=000001c8 pc=00020210..00020240
+
+00000238 00000014 00000074 FDE cie=000001c8 pc=00020240..00020280
+
+00000250 00000014 0000008c FDE cie=000001c8 pc=00020280..000202d0
+
+00000268 0000001c 00000000 CIE
+  Version:               1
+  Augmentation:          "zP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     00 10 20 30 40 50 60 70 80
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000288 0000001c 00000024 FDE cie=00000268 pc=000202d0..000202e0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000002a8 0000001c 00000044 FDE cie=00000268 pc=000202e0..00020300
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000002c8 0000001c 00000000 CIE
+  Version:               1
+  Augmentation:          "zP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     50 00 00 00 00 00 00 00 10 20 30 40 50 60 70 80
+
+
+000002e8 0000001c 00000024 FDE cie=000002c8 pc=00020300..00020310
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000308 0000001c 00000044 FDE cie=000002c8 pc=00020310..00020330
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000328 0000001c 00000000 CIE
+  Version:               1
+  Augmentation:          "zPR"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     00 10 20 30 40 50 60 70 80 00
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000348 0000001c 00000024 FDE cie=00000328 pc=00020330..00020340
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# FDE for .discard removed
+# zPR2 removed
+00000368 0000001c 00000044 FDE cie=00000328 pc=00020340..00020370
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000388 0000001c 00000064 FDE cie=00000328 pc=00020370..000203b0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000003a8 0000000c 00000000 CIE
+  Version:               1
+  Augmentation:          ""
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000003b8 00000014 00000014 FDE cie=000003a8 pc=000203b0..000203c0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame4.d b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame4.d
new file mode 100644
index 0000000..e04d5fc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/eh-frame4.d
@@ -0,0 +1,208 @@
+#name: MIPS eh-frame 4
+#source: eh-frame1.s
+#source: eh-frame1.s
+#as: -EB -mips3 -mabi=eabi --defsym alignment=2 --defsym fill=0 --defsym foo=0x50607080
+#readelf: -wf
+#ld: -EB -Teh-frame1.ld
+#
+# This test is for the semi-official ILP32 variation of EABI64.
+#
+
+The section \.eh_frame contains:
+
+00000000 0000000c 00000000 CIE
+  Version:               1
+  Augmentation:          ""
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000010 0000000c 00000014 FDE cie=00000000 pc=00020000..00020010
+
+00000020 0000000c 00000024 FDE cie=00000000 pc=00020010..00020030
+
+# basic2 removed
+00000030 0000000c 00000034 FDE cie=00000000 pc=00020030..00020060
+
+# basic3 removed
+00000040 0000000c 00000044 FDE cie=00000000 pc=00020060..000200a0
+
+# basic4 removed
+00000050 0000000c 00000054 FDE cie=00000000 pc=000200a0..000200f0
+
+00000060 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     00 50 60 70 80
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000078 00000010 0000001c FDE cie=00000060 pc=000200f0..00020100
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+0000008c 00000010 00000030 FDE cie=00000060 pc=00020100..00020120
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000a0 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     50 00 00 00 50 60 70 80
+
+
+000000b8 00000010 0000001c FDE cie=000000a0 pc=00020120..00020130
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000cc 00000010 00000030 FDE cie=000000a0 pc=00020130..00020150
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000000e0 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zPR"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     00 50 60 70 80 00
+
+  DW_CFA_nop
+
+000000f8 00000010 0000001c FDE cie=000000e0 pc=00020150..00020160
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# FDE for .discard removed
+# zPR2 removed
+0000010c 00000010 00000030 FDE cie=000000e0 pc=00020160..00020190
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000120 00000010 00000044 FDE cie=000000e0 pc=00020190..000201d0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000134 0000000c 00000000 CIE
+  Version:               1
+  Augmentation:          ""
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000144 0000000c 00000014 FDE cie=00000134 pc=000201d0..000201e0
+
+# basic1 removed, followed by repeat of above
+00000154 0000000c 00000024 FDE cie=00000134 pc=000201e0..000201f0
+
+00000164 0000000c 00000034 FDE cie=00000134 pc=000201f0..00020210
+
+00000174 0000000c 00000044 FDE cie=00000134 pc=00020210..00020240
+
+00000184 0000000c 00000054 FDE cie=00000134 pc=00020240..00020280
+
+00000194 0000000c 00000064 FDE cie=00000134 pc=00020280..000202d0
+
+000001a4 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     00 50 60 70 80
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001bc 00000010 0000001c FDE cie=000001a4 pc=000202d0..000202e0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001d0 00000010 00000030 FDE cie=000001a4 pc=000202e0..00020300
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+000001e4 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zP"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     50 00 00 00 50 60 70 80
+
+
+000001fc 00000010 0000001c FDE cie=000001e4 pc=00020300..00020310
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000210 00000010 00000030 FDE cie=000001e4 pc=00020310..00020330
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000224 00000014 00000000 CIE
+  Version:               1
+  Augmentation:          "zPR"
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+  Augmentation data:     00 50 60 70 80 00
+
+  DW_CFA_nop
+
+0000023c 00000010 0000001c FDE cie=00000224 pc=00020330..00020340
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+# FDE for .discard removed
+# zPR2 removed
+00000250 00000010 00000030 FDE cie=00000224 pc=00020340..00020370
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000264 00000010 00000044 FDE cie=00000224 pc=00020370..000203b0
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000278 0000000c 00000000 CIE
+  Version:               1
+  Augmentation:          ""
+  Code alignment factor: 1
+  Data alignment factor: 4
+  Return address column: 31
+
+  DW_CFA_nop
+  DW_CFA_nop
+  DW_CFA_nop
+
+00000288 0000000c 00000014 FDE cie=00000278 pc=000203b0..000203c0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d
new file mode 100644
index 0000000..d1619d5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d
@@ -0,0 +1,315 @@
+#name: MIPS ELF got reloc n32
+#as: -EB -n32 -KPIC
+#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s
+#ld: -melf32btsmipn32
+#objdump: -D --show-raw-insn
+
+.*: +file format elf32-n.*mips.*
+
+Disassembly of section \.reginfo:
+
+10000098 <\.reginfo>:
+10000098:	92020022 	.*
+	\.\.\.
+100000ac:	100185a0 	.*
+
+Disassembly of section \.text:
+
+100000b0 <fn>:
+100000b0:	8f858064 	lw	a1,-32668\(gp\)
+100000b4:	8f858064 	lw	a1,-32668\(gp\)
+100000b8:	24a5000c 	addiu	a1,a1,12
+100000bc:	8f858064 	lw	a1,-32668\(gp\)
+100000c0:	3c010001 	lui	at,0x1
+100000c4:	3421e240 	ori	at,at,0xe240
+100000c8:	00a12821 	addu	a1,a1,at
+100000cc:	8f858064 	lw	a1,-32668\(gp\)
+100000d0:	00b12821 	addu	a1,a1,s1
+100000d4:	8f858064 	lw	a1,-32668\(gp\)
+100000d8:	24a5000c 	addiu	a1,a1,12
+100000dc:	00b12821 	addu	a1,a1,s1
+100000e0:	8f858064 	lw	a1,-32668\(gp\)
+100000e4:	3c010001 	lui	at,0x1
+100000e8:	3421e240 	ori	at,at,0xe240
+100000ec:	00a12821 	addu	a1,a1,at
+100000f0:	00b12821 	addu	a1,a1,s1
+100000f4:	8f858018 	lw	a1,-32744\(gp\)
+100000f8:	8ca504fc 	lw	a1,1276\(a1\)
+100000fc:	8f858018 	lw	a1,-32744\(gp\)
+10000100:	8ca50508 	lw	a1,1288\(a1\)
+10000104:	8f858018 	lw	a1,-32744\(gp\)
+10000108:	00b12821 	addu	a1,a1,s1
+1000010c:	8ca504fc 	lw	a1,1276\(a1\)
+10000110:	8f858018 	lw	a1,-32744\(gp\)
+10000114:	00b12821 	addu	a1,a1,s1
+10000118:	8ca50508 	lw	a1,1288\(a1\)
+1000011c:	8f818018 	lw	at,-32744\(gp\)
+10000120:	00250821 	addu	at,at,a1
+10000124:	8c25051e 	lw	a1,1310\(at\)
+10000128:	8f818018 	lw	at,-32744\(gp\)
+1000012c:	00250821 	addu	at,at,a1
+10000130:	ac250534 	sw	a1,1332\(at\)
+10000134:	8f818064 	lw	at,-32668\(gp\)
+10000138:	88250000 	lwl	a1,0\(at\)
+1000013c:	98250003 	lwr	a1,3\(at\)
+10000140:	8f818064 	lw	at,-32668\(gp\)
+10000144:	2421000c 	addiu	at,at,12
+10000148:	88250000 	lwl	a1,0\(at\)
+1000014c:	98250003 	lwr	a1,3\(at\)
+10000150:	8f818064 	lw	at,-32668\(gp\)
+10000154:	00310821 	addu	at,at,s1
+10000158:	88250000 	lwl	a1,0\(at\)
+1000015c:	98250003 	lwr	a1,3\(at\)
+10000160:	8f818064 	lw	at,-32668\(gp\)
+10000164:	2421000c 	addiu	at,at,12
+10000168:	00310821 	addu	at,at,s1
+1000016c:	88250000 	lwl	a1,0\(at\)
+10000170:	98250003 	lwr	a1,3\(at\)
+10000174:	8f818064 	lw	at,-32668\(gp\)
+10000178:	24210022 	addiu	at,at,34
+1000017c:	00250821 	addu	at,at,a1
+10000180:	88250000 	lwl	a1,0\(at\)
+10000184:	98250003 	lwr	a1,3\(at\)
+10000188:	8f818064 	lw	at,-32668\(gp\)
+1000018c:	24210038 	addiu	at,at,56
+10000190:	00250821 	addu	at,at,a1
+10000194:	a8250000 	swl	a1,0\(at\)
+10000198:	b8250003 	swr	a1,3\(at\)
+1000019c:	8f85801c 	lw	a1,-32740\(gp\)
+100001a0:	8f858020 	lw	a1,-32736\(gp\)
+100001a4:	8f858024 	lw	a1,-32732\(gp\)
+100001a8:	8f85801c 	lw	a1,-32740\(gp\)
+100001ac:	00b12821 	addu	a1,a1,s1
+100001b0:	8f858020 	lw	a1,-32736\(gp\)
+100001b4:	00b12821 	addu	a1,a1,s1
+100001b8:	8f858024 	lw	a1,-32732\(gp\)
+100001bc:	00b12821 	addu	a1,a1,s1
+100001c0:	8f858018 	lw	a1,-32744\(gp\)
+100001c4:	8ca504fc 	lw	a1,1276\(a1\)
+100001c8:	8f858018 	lw	a1,-32744\(gp\)
+100001cc:	8ca50508 	lw	a1,1288\(a1\)
+100001d0:	8f858018 	lw	a1,-32744\(gp\)
+100001d4:	00b12821 	addu	a1,a1,s1
+100001d8:	8ca504fc 	lw	a1,1276\(a1\)
+100001dc:	8f858018 	lw	a1,-32744\(gp\)
+100001e0:	00b12821 	addu	a1,a1,s1
+100001e4:	8ca50508 	lw	a1,1288\(a1\)
+100001e8:	8f818018 	lw	at,-32744\(gp\)
+100001ec:	00250821 	addu	at,at,a1
+100001f0:	8c25051e 	lw	a1,1310\(at\)
+100001f4:	8f818018 	lw	at,-32744\(gp\)
+100001f8:	00250821 	addu	at,at,a1
+100001fc:	ac250534 	sw	a1,1332\(at\)
+10000200:	8f81801c 	lw	at,-32740\(gp\)
+10000204:	88250000 	lwl	a1,0\(at\)
+10000208:	98250003 	lwr	a1,3\(at\)
+1000020c:	8f818020 	lw	at,-32736\(gp\)
+10000210:	88250000 	lwl	a1,0\(at\)
+10000214:	98250003 	lwr	a1,3\(at\)
+10000218:	8f81801c 	lw	at,-32740\(gp\)
+1000021c:	00310821 	addu	at,at,s1
+10000220:	88250000 	lwl	a1,0\(at\)
+10000224:	98250003 	lwr	a1,3\(at\)
+10000228:	8f818020 	lw	at,-32736\(gp\)
+1000022c:	00310821 	addu	at,at,s1
+10000230:	88250000 	lwl	a1,0\(at\)
+10000234:	98250003 	lwr	a1,3\(at\)
+10000238:	8f818028 	lw	at,-32728\(gp\)
+1000023c:	00250821 	addu	at,at,a1
+10000240:	88250000 	lwl	a1,0\(at\)
+10000244:	98250003 	lwr	a1,3\(at\)
+10000248:	8f81802c 	lw	at,-32724\(gp\)
+1000024c:	00250821 	addu	at,at,a1
+10000250:	a8250000 	swl	a1,0\(at\)
+10000254:	b8250003 	swr	a1,3\(at\)
+10000258:	8f85805c 	lw	a1,-32676\(gp\)
+1000025c:	8f858030 	lw	a1,-32720\(gp\)
+10000260:	8f99805c 	lw	t9,-32676\(gp\)
+10000264:	8f998030 	lw	t9,-32720\(gp\)
+10000268:	8f99805c 	lw	t9,-32676\(gp\)
+1000026c:	0320f809 	jalr	t9
+10000270:	00000000 	nop
+10000274:	8f998030 	lw	t9,-32720\(gp\)
+10000278:	0320f809 	jalr	t9
+1000027c:	00000000 	nop
+10000280:	8f858068 	lw	a1,-32664\(gp\)
+10000284:	8f858068 	lw	a1,-32664\(gp\)
+10000288:	24a5000c 	addiu	a1,a1,12
+1000028c:	8f858068 	lw	a1,-32664\(gp\)
+10000290:	3c010001 	lui	at,0x1
+10000294:	3421e240 	ori	at,at,0xe240
+10000298:	00a12821 	addu	a1,a1,at
+1000029c:	8f858068 	lw	a1,-32664\(gp\)
+100002a0:	00b12821 	addu	a1,a1,s1
+100002a4:	8f858068 	lw	a1,-32664\(gp\)
+100002a8:	24a5000c 	addiu	a1,a1,12
+100002ac:	00b12821 	addu	a1,a1,s1
+100002b0:	8f858068 	lw	a1,-32664\(gp\)
+100002b4:	3c010001 	lui	at,0x1
+100002b8:	3421e240 	ori	at,at,0xe240
+100002bc:	00a12821 	addu	a1,a1,at
+100002c0:	00b12821 	addu	a1,a1,s1
+100002c4:	8f858018 	lw	a1,-32744\(gp\)
+100002c8:	8ca50574 	lw	a1,1396\(a1\)
+100002cc:	8f858018 	lw	a1,-32744\(gp\)
+100002d0:	8ca50580 	lw	a1,1408\(a1\)
+100002d4:	8f858018 	lw	a1,-32744\(gp\)
+100002d8:	00b12821 	addu	a1,a1,s1
+100002dc:	8ca50574 	lw	a1,1396\(a1\)
+100002e0:	8f858018 	lw	a1,-32744\(gp\)
+100002e4:	00b12821 	addu	a1,a1,s1
+100002e8:	8ca50580 	lw	a1,1408\(a1\)
+100002ec:	8f818018 	lw	at,-32744\(gp\)
+100002f0:	00250821 	addu	at,at,a1
+100002f4:	8c250596 	lw	a1,1430\(at\)
+100002f8:	8f818018 	lw	at,-32744\(gp\)
+100002fc:	00250821 	addu	at,at,a1
+10000300:	ac2505ac 	sw	a1,1452\(at\)
+10000304:	8f818068 	lw	at,-32664\(gp\)
+10000308:	88250000 	lwl	a1,0\(at\)
+1000030c:	98250003 	lwr	a1,3\(at\)
+10000310:	8f818068 	lw	at,-32664\(gp\)
+10000314:	2421000c 	addiu	at,at,12
+10000318:	88250000 	lwl	a1,0\(at\)
+1000031c:	98250003 	lwr	a1,3\(at\)
+10000320:	8f818068 	lw	at,-32664\(gp\)
+10000324:	00310821 	addu	at,at,s1
+10000328:	88250000 	lwl	a1,0\(at\)
+1000032c:	98250003 	lwr	a1,3\(at\)
+10000330:	8f818068 	lw	at,-32664\(gp\)
+10000334:	2421000c 	addiu	at,at,12
+10000338:	00310821 	addu	at,at,s1
+1000033c:	88250000 	lwl	a1,0\(at\)
+10000340:	98250003 	lwr	a1,3\(at\)
+10000344:	8f818068 	lw	at,-32664\(gp\)
+10000348:	24210022 	addiu	at,at,34
+1000034c:	00250821 	addu	at,at,a1
+10000350:	88250000 	lwl	a1,0\(at\)
+10000354:	98250003 	lwr	a1,3\(at\)
+10000358:	8f818068 	lw	at,-32664\(gp\)
+1000035c:	24210038 	addiu	at,at,56
+10000360:	00250821 	addu	at,at,a1
+10000364:	a8250000 	swl	a1,0\(at\)
+10000368:	b8250003 	swr	a1,3\(at\)
+1000036c:	8f858034 	lw	a1,-32716\(gp\)
+10000370:	8f858038 	lw	a1,-32712\(gp\)
+10000374:	8f85803c 	lw	a1,-32708\(gp\)
+10000378:	8f858034 	lw	a1,-32716\(gp\)
+1000037c:	00b12821 	addu	a1,a1,s1
+10000380:	8f858038 	lw	a1,-32712\(gp\)
+10000384:	00b12821 	addu	a1,a1,s1
+10000388:	8f85803c 	lw	a1,-32708\(gp\)
+1000038c:	00b12821 	addu	a1,a1,s1
+10000390:	8f858018 	lw	a1,-32744\(gp\)
+10000394:	8ca50574 	lw	a1,1396\(a1\)
+10000398:	8f858018 	lw	a1,-32744\(gp\)
+1000039c:	8ca50580 	lw	a1,1408\(a1\)
+100003a0:	8f858018 	lw	a1,-32744\(gp\)
+100003a4:	00b12821 	addu	a1,a1,s1
+100003a8:	8ca50574 	lw	a1,1396\(a1\)
+100003ac:	8f858018 	lw	a1,-32744\(gp\)
+100003b0:	00b12821 	addu	a1,a1,s1
+100003b4:	8ca50580 	lw	a1,1408\(a1\)
+100003b8:	8f818018 	lw	at,-32744\(gp\)
+100003bc:	00250821 	addu	at,at,a1
+100003c0:	8c250596 	lw	a1,1430\(at\)
+100003c4:	8f818018 	lw	at,-32744\(gp\)
+100003c8:	00250821 	addu	at,at,a1
+100003cc:	ac2505ac 	sw	a1,1452\(at\)
+100003d0:	8f818034 	lw	at,-32716\(gp\)
+100003d4:	88250000 	lwl	a1,0\(at\)
+100003d8:	98250003 	lwr	a1,3\(at\)
+100003dc:	8f818038 	lw	at,-32712\(gp\)
+100003e0:	88250000 	lwl	a1,0\(at\)
+100003e4:	98250003 	lwr	a1,3\(at\)
+100003e8:	8f818034 	lw	at,-32716\(gp\)
+100003ec:	00310821 	addu	at,at,s1
+100003f0:	88250000 	lwl	a1,0\(at\)
+100003f4:	98250003 	lwr	a1,3\(at\)
+100003f8:	8f818038 	lw	at,-32712\(gp\)
+100003fc:	00310821 	addu	at,at,s1
+10000400:	88250000 	lwl	a1,0\(at\)
+10000404:	98250003 	lwr	a1,3\(at\)
+10000408:	8f818040 	lw	at,-32704\(gp\)
+1000040c:	00250821 	addu	at,at,a1
+10000410:	88250000 	lwl	a1,0\(at\)
+10000414:	98250003 	lwr	a1,3\(at\)
+10000418:	8f818044 	lw	at,-32700\(gp\)
+1000041c:	00250821 	addu	at,at,a1
+10000420:	a8250000 	swl	a1,0\(at\)
+10000424:	b8250003 	swr	a1,3\(at\)
+10000428:	8f858060 	lw	a1,-32672\(gp\)
+1000042c:	8f858048 	lw	a1,-32696\(gp\)
+10000430:	8f998060 	lw	t9,-32672\(gp\)
+10000434:	8f998048 	lw	t9,-32696\(gp\)
+10000438:	8f998060 	lw	t9,-32672\(gp\)
+1000043c:	0320f809 	jalr	t9
+10000440:	00000000 	nop
+10000444:	8f998048 	lw	t9,-32696\(gp\)
+10000448:	0320f809 	jalr	t9
+1000044c:	00000000 	nop
+10000450:	1000ff17 	b	100000b0 <fn>
+10000454:	8f858064 	lw	a1,-32668\(gp\)
+10000458:	8f858018 	lw	a1,-32744\(gp\)
+1000045c:	10000015 	b	100004b4 <fn2>
+10000460:	8ca50574 	lw	a1,1396\(a1\)
+10000464:	1000ff12 	b	100000b0 <fn>
+10000468:	8f85801c 	lw	a1,-32740\(gp\)
+1000046c:	8f858038 	lw	a1,-32712\(gp\)
+10000470:	10000010 	b	100004b4 <fn2>
+10000474:	00000000 	nop
+10000478:	8f858024 	lw	a1,-32732\(gp\)
+1000047c:	1000ff0c 	b	100000b0 <fn>
+10000480:	00000000 	nop
+10000484:	8f858018 	lw	a1,-32744\(gp\)
+10000488:	1000000a 	b	100004b4 <fn2>
+1000048c:	8ca50574 	lw	a1,1396\(a1\)
+10000490:	8f858018 	lw	a1,-32744\(gp\)
+10000494:	1000ff06 	b	100000b0 <fn>
+10000498:	8ca50508 	lw	a1,1288\(a1\)
+1000049c:	8f818018 	lw	at,-32744\(gp\)
+100004a0:	00250821 	addu	at,at,a1
+100004a4:	10000003 	b	100004b4 <fn2>
+100004a8:	8c250596 	lw	a1,1430\(at\)
+	\.\.\.
+
+100004b4 <fn2>:
+	\.\.\.
+Disassembly of section \.data:
+
+100104c0 <_fdata>:
+	\.\.\.
+
+100104fc <dg1>:
+	\.\.\.
+
+10010538 <sp2>:
+	\.\.\.
+
+10010574 <dg2>:
+	\.\.\.
+Disassembly of section \.got:
+
+100105b0 <_GLOBAL_OFFSET_TABLE_>:
+100105b0:	00000000 	.*
+100105b4:	80000000 	.*
+100105b8:	10010000 	.*
+100105bc:	100104fc 	.*
+100105c0:	10010508 	.*
+100105c4:	1002e73c 	.*
+100105c8:	1001051e 	.*
+100105cc:	10010534 	.*
+100105d0:	100000b0 	.*
+100105d4:	10010574 	.*
+100105d8:	10010580 	.*
+100105dc:	1002e7b4 	.*
+100105e0:	10010596 	.*
+100105e4:	100105ac 	.*
+100105e8:	100004b4 	.*
+100105ec:	00000000 	.*
+	\.\.\.
+100105fc:	100000b0 	.*
+10010600:	100004b4 	.*
+10010604:	100104fc 	.*
+10010608:	10010574 	.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d b/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d
new file mode 100644
index 0000000..946751e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d
@@ -0,0 +1,334 @@
+#name: MIPS ELF got reloc n64
+#as: -EB -64 -KPIC
+#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s
+#ld: -melf64btsmip
+#objdump: -D --show-raw-insn
+
+.*: +file format elf64-.*mips.*
+
+Disassembly of section \.MIPS\.options:
+
+00000001200000b0 <\.MIPS\.options>:
+   1200000b0:	01280000 	.*
+   1200000b4:	00000000 	.*
+   1200000b8:	92020022 	.*
+	\.\.\.
+   1200000d0:	00000001 	.*
+   1200000d4:	200185d0 	.*
+Disassembly of section \.text:
+
+00000001200000e0 <fn>:
+   1200000e0:	df8580b8 	ld	a1,-32584\(gp\)
+   1200000e4:	df8580b8 	ld	a1,-32584\(gp\)
+   1200000e8:	64a5000c 	daddiu	a1,a1,12
+   1200000ec:	df8580b8 	ld	a1,-32584\(gp\)
+   1200000f0:	3c010001 	lui	at,0x1
+   1200000f4:	3421e240 	ori	at,at,0xe240
+   1200000f8:	00a1282d 	daddu	a1,a1,at
+   1200000fc:	df8580b8 	ld	a1,-32584\(gp\)
+   120000100:	00b1282d 	daddu	a1,a1,s1
+   120000104:	df8580b8 	ld	a1,-32584\(gp\)
+   120000108:	64a5000c 	daddiu	a1,a1,12
+   12000010c:	00b1282d 	daddu	a1,a1,s1
+   120000110:	df8580b8 	ld	a1,-32584\(gp\)
+   120000114:	3c010001 	lui	at,0x1
+   120000118:	3421e240 	ori	at,at,0xe240
+   12000011c:	00a1282d 	daddu	a1,a1,at
+   120000120:	00b1282d 	daddu	a1,a1,s1
+   120000124:	df858020 	ld	a1,-32736\(gp\)
+   120000128:	dca5052c 	ld	a1,1324\(a1\)
+   12000012c:	df858020 	ld	a1,-32736\(gp\)
+   120000130:	dca50538 	ld	a1,1336\(a1\)
+   120000134:	df858020 	ld	a1,-32736\(gp\)
+   120000138:	00b1282d 	daddu	a1,a1,s1
+   12000013c:	dca5052c 	ld	a1,1324\(a1\)
+   120000140:	df858020 	ld	a1,-32736\(gp\)
+   120000144:	00b1282d 	daddu	a1,a1,s1
+   120000148:	dca50538 	ld	a1,1336\(a1\)
+   12000014c:	df818020 	ld	at,-32736\(gp\)
+   120000150:	0025082d 	daddu	at,at,a1
+   120000154:	dc25054e 	ld	a1,1358\(at\)
+   120000158:	df818020 	ld	at,-32736\(gp\)
+   12000015c:	0025082d 	daddu	at,at,a1
+   120000160:	fc250564 	sd	a1,1380\(at\)
+   120000164:	df8180b8 	ld	at,-32584\(gp\)
+   120000168:	88250000 	lwl	a1,0\(at\)
+   12000016c:	98250003 	lwr	a1,3\(at\)
+   120000170:	df8180b8 	ld	at,-32584\(gp\)
+   120000174:	6421000c 	daddiu	at,at,12
+   120000178:	88250000 	lwl	a1,0\(at\)
+   12000017c:	98250003 	lwr	a1,3\(at\)
+   120000180:	df8180b8 	ld	at,-32584\(gp\)
+   120000184:	0031082d 	daddu	at,at,s1
+   120000188:	88250000 	lwl	a1,0\(at\)
+   12000018c:	98250003 	lwr	a1,3\(at\)
+   120000190:	df8180b8 	ld	at,-32584\(gp\)
+   120000194:	6421000c 	daddiu	at,at,12
+   120000198:	0031082d 	daddu	at,at,s1
+   12000019c:	88250000 	lwl	a1,0\(at\)
+   1200001a0:	98250003 	lwr	a1,3\(at\)
+   1200001a4:	df8180b8 	ld	at,-32584\(gp\)
+   1200001a8:	64210022 	daddiu	at,at,34
+   1200001ac:	0025082d 	daddu	at,at,a1
+   1200001b0:	88250000 	lwl	a1,0\(at\)
+   1200001b4:	98250003 	lwr	a1,3\(at\)
+   1200001b8:	df8180b8 	ld	at,-32584\(gp\)
+   1200001bc:	64210038 	daddiu	at,at,56
+   1200001c0:	0025082d 	daddu	at,at,a1
+   1200001c4:	a8250000 	swl	a1,0\(at\)
+   1200001c8:	b8250003 	swr	a1,3\(at\)
+   1200001cc:	df858028 	ld	a1,-32728\(gp\)
+   1200001d0:	df858030 	ld	a1,-32720\(gp\)
+   1200001d4:	df858038 	ld	a1,-32712\(gp\)
+   1200001d8:	df858028 	ld	a1,-32728\(gp\)
+   1200001dc:	00b1282d 	daddu	a1,a1,s1
+   1200001e0:	df858030 	ld	a1,-32720\(gp\)
+   1200001e4:	00b1282d 	daddu	a1,a1,s1
+   1200001e8:	df858038 	ld	a1,-32712\(gp\)
+   1200001ec:	00b1282d 	daddu	a1,a1,s1
+   1200001f0:	df858020 	ld	a1,-32736\(gp\)
+   1200001f4:	dca5052c 	ld	a1,1324\(a1\)
+   1200001f8:	df858020 	ld	a1,-32736\(gp\)
+   1200001fc:	dca50538 	ld	a1,1336\(a1\)
+   120000200:	df858020 	ld	a1,-32736\(gp\)
+   120000204:	00b1282d 	daddu	a1,a1,s1
+   120000208:	dca5052c 	ld	a1,1324\(a1\)
+   12000020c:	df858020 	ld	a1,-32736\(gp\)
+   120000210:	00b1282d 	daddu	a1,a1,s1
+   120000214:	dca50538 	ld	a1,1336\(a1\)
+   120000218:	df818020 	ld	at,-32736\(gp\)
+   12000021c:	0025082d 	daddu	at,at,a1
+   120000220:	dc25054e 	ld	a1,1358\(at\)
+   120000224:	df818020 	ld	at,-32736\(gp\)
+   120000228:	0025082d 	daddu	at,at,a1
+   12000022c:	fc250564 	sd	a1,1380\(at\)
+   120000230:	df818028 	ld	at,-32728\(gp\)
+   120000234:	88250000 	lwl	a1,0\(at\)
+   120000238:	98250003 	lwr	a1,3\(at\)
+   12000023c:	df818030 	ld	at,-32720\(gp\)
+   120000240:	88250000 	lwl	a1,0\(at\)
+   120000244:	98250003 	lwr	a1,3\(at\)
+   120000248:	df818028 	ld	at,-32728\(gp\)
+   12000024c:	0031082d 	daddu	at,at,s1
+   120000250:	88250000 	lwl	a1,0\(at\)
+   120000254:	98250003 	lwr	a1,3\(at\)
+   120000258:	df818030 	ld	at,-32720\(gp\)
+   12000025c:	0031082d 	daddu	at,at,s1
+   120000260:	88250000 	lwl	a1,0\(at\)
+   120000264:	98250003 	lwr	a1,3\(at\)
+   120000268:	df818040 	ld	at,-32704\(gp\)
+   12000026c:	0025082d 	daddu	at,at,a1
+   120000270:	88250000 	lwl	a1,0\(at\)
+   120000274:	98250003 	lwr	a1,3\(at\)
+   120000278:	df818048 	ld	at,-32696\(gp\)
+   12000027c:	0025082d 	daddu	at,at,a1
+   120000280:	a8250000 	swl	a1,0\(at\)
+   120000284:	b8250003 	swr	a1,3\(at\)
+   120000288:	df8580a8 	ld	a1,-32600\(gp\)
+   12000028c:	df858050 	ld	a1,-32688\(gp\)
+   120000290:	df9980a8 	ld	t9,-32600\(gp\)
+   120000294:	df998050 	ld	t9,-32688\(gp\)
+   120000298:	df9980a8 	ld	t9,-32600\(gp\)
+   12000029c:	0320f809 	jalr	t9
+   1200002a0:	00000000 	nop
+   1200002a4:	df998050 	ld	t9,-32688\(gp\)
+   1200002a8:	0320f809 	jalr	t9
+   1200002ac:	00000000 	nop
+   1200002b0:	df8580c0 	ld	a1,-32576\(gp\)
+   1200002b4:	df8580c0 	ld	a1,-32576\(gp\)
+   1200002b8:	64a5000c 	daddiu	a1,a1,12
+   1200002bc:	df8580c0 	ld	a1,-32576\(gp\)
+   1200002c0:	3c010001 	lui	at,0x1
+   1200002c4:	3421e240 	ori	at,at,0xe240
+   1200002c8:	00a1282d 	daddu	a1,a1,at
+   1200002cc:	df8580c0 	ld	a1,-32576\(gp\)
+   1200002d0:	00b1282d 	daddu	a1,a1,s1
+   1200002d4:	df8580c0 	ld	a1,-32576\(gp\)
+   1200002d8:	64a5000c 	daddiu	a1,a1,12
+   1200002dc:	00b1282d 	daddu	a1,a1,s1
+   1200002e0:	df8580c0 	ld	a1,-32576\(gp\)
+   1200002e4:	3c010001 	lui	at,0x1
+   1200002e8:	3421e240 	ori	at,at,0xe240
+   1200002ec:	00a1282d 	daddu	a1,a1,at
+   1200002f0:	00b1282d 	daddu	a1,a1,s1
+   1200002f4:	df858020 	ld	a1,-32736\(gp\)
+   1200002f8:	dca505a4 	ld	a1,1444\(a1\)
+   1200002fc:	df858020 	ld	a1,-32736\(gp\)
+   120000300:	dca505b0 	ld	a1,1456\(a1\)
+   120000304:	df858020 	ld	a1,-32736\(gp\)
+   120000308:	00b1282d 	daddu	a1,a1,s1
+   12000030c:	dca505a4 	ld	a1,1444\(a1\)
+   120000310:	df858020 	ld	a1,-32736\(gp\)
+   120000314:	00b1282d 	daddu	a1,a1,s1
+   120000318:	dca505b0 	ld	a1,1456\(a1\)
+   12000031c:	df818020 	ld	at,-32736\(gp\)
+   120000320:	0025082d 	daddu	at,at,a1
+   120000324:	dc2505c6 	ld	a1,1478\(at\)
+   120000328:	df818020 	ld	at,-32736\(gp\)
+   12000032c:	0025082d 	daddu	at,at,a1
+   120000330:	fc2505dc 	sd	a1,1500\(at\)
+   120000334:	df8180c0 	ld	at,-32576\(gp\)
+   120000338:	88250000 	lwl	a1,0\(at\)
+   12000033c:	98250003 	lwr	a1,3\(at\)
+   120000340:	df8180c0 	ld	at,-32576\(gp\)
+   120000344:	6421000c 	daddiu	at,at,12
+   120000348:	88250000 	lwl	a1,0\(at\)
+   12000034c:	98250003 	lwr	a1,3\(at\)
+   120000350:	df8180c0 	ld	at,-32576\(gp\)
+   120000354:	0031082d 	daddu	at,at,s1
+   120000358:	88250000 	lwl	a1,0\(at\)
+   12000035c:	98250003 	lwr	a1,3\(at\)
+   120000360:	df8180c0 	ld	at,-32576\(gp\)
+   120000364:	6421000c 	daddiu	at,at,12
+   120000368:	0031082d 	daddu	at,at,s1
+   12000036c:	88250000 	lwl	a1,0\(at\)
+   120000370:	98250003 	lwr	a1,3\(at\)
+   120000374:	df8180c0 	ld	at,-32576\(gp\)
+   120000378:	64210022 	daddiu	at,at,34
+   12000037c:	0025082d 	daddu	at,at,a1
+   120000380:	88250000 	lwl	a1,0\(at\)
+   120000384:	98250003 	lwr	a1,3\(at\)
+   120000388:	df8180c0 	ld	at,-32576\(gp\)
+   12000038c:	64210038 	daddiu	at,at,56
+   120000390:	0025082d 	daddu	at,at,a1
+   120000394:	a8250000 	swl	a1,0\(at\)
+   120000398:	b8250003 	swr	a1,3\(at\)
+   12000039c:	df858058 	ld	a1,-32680\(gp\)
+   1200003a0:	df858060 	ld	a1,-32672\(gp\)
+   1200003a4:	df858068 	ld	a1,-32664\(gp\)
+   1200003a8:	df858058 	ld	a1,-32680\(gp\)
+   1200003ac:	00b1282d 	daddu	a1,a1,s1
+   1200003b0:	df858060 	ld	a1,-32672\(gp\)
+   1200003b4:	00b1282d 	daddu	a1,a1,s1
+   1200003b8:	df858068 	ld	a1,-32664\(gp\)
+   1200003bc:	00b1282d 	daddu	a1,a1,s1
+   1200003c0:	df858020 	ld	a1,-32736\(gp\)
+   1200003c4:	dca505a4 	ld	a1,1444\(a1\)
+   1200003c8:	df858020 	ld	a1,-32736\(gp\)
+   1200003cc:	dca505b0 	ld	a1,1456\(a1\)
+   1200003d0:	df858020 	ld	a1,-32736\(gp\)
+   1200003d4:	00b1282d 	daddu	a1,a1,s1
+   1200003d8:	dca505a4 	ld	a1,1444\(a1\)
+   1200003dc:	df858020 	ld	a1,-32736\(gp\)
+   1200003e0:	00b1282d 	daddu	a1,a1,s1
+   1200003e4:	dca505b0 	ld	a1,1456\(a1\)
+   1200003e8:	df818020 	ld	at,-32736\(gp\)
+   1200003ec:	0025082d 	daddu	at,at,a1
+   1200003f0:	dc2505c6 	ld	a1,1478\(at\)
+   1200003f4:	df818020 	ld	at,-32736\(gp\)
+   1200003f8:	0025082d 	daddu	at,at,a1
+   1200003fc:	fc2505dc 	sd	a1,1500\(at\)
+   120000400:	df818058 	ld	at,-32680\(gp\)
+   120000404:	88250000 	lwl	a1,0\(at\)
+   120000408:	98250003 	lwr	a1,3\(at\)
+   12000040c:	df818060 	ld	at,-32672\(gp\)
+   120000410:	88250000 	lwl	a1,0\(at\)
+   120000414:	98250003 	lwr	a1,3\(at\)
+   120000418:	df818058 	ld	at,-32680\(gp\)
+   12000041c:	0031082d 	daddu	at,at,s1
+   120000420:	88250000 	lwl	a1,0\(at\)
+   120000424:	98250003 	lwr	a1,3\(at\)
+   120000428:	df818060 	ld	at,-32672\(gp\)
+   12000042c:	0031082d 	daddu	at,at,s1
+   120000430:	88250000 	lwl	a1,0\(at\)
+   120000434:	98250003 	lwr	a1,3\(at\)
+   120000438:	df818070 	ld	at,-32656\(gp\)
+   12000043c:	0025082d 	daddu	at,at,a1
+   120000440:	88250000 	lwl	a1,0\(at\)
+   120000444:	98250003 	lwr	a1,3\(at\)
+   120000448:	df818078 	ld	at,-32648\(gp\)
+   12000044c:	0025082d 	daddu	at,at,a1
+   120000450:	a8250000 	swl	a1,0\(at\)
+   120000454:	b8250003 	swr	a1,3\(at\)
+   120000458:	df8580b0 	ld	a1,-32592\(gp\)
+   12000045c:	df858080 	ld	a1,-32640\(gp\)
+   120000460:	df9980b0 	ld	t9,-32592\(gp\)
+   120000464:	df998080 	ld	t9,-32640\(gp\)
+   120000468:	df9980b0 	ld	t9,-32592\(gp\)
+   12000046c:	0320f809 	jalr	t9
+   120000470:	00000000 	nop
+   120000474:	df998080 	ld	t9,-32640\(gp\)
+   120000478:	0320f809 	jalr	t9
+   12000047c:	00000000 	nop
+   120000480:	1000ff17 	b	1200000e0 <fn>
+   120000484:	df8580b8 	ld	a1,-32584\(gp\)
+   120000488:	df858020 	ld	a1,-32736\(gp\)
+   12000048c:	10000015 	b	1200004e4 <fn2>
+   120000490:	dca505a4 	ld	a1,1444\(a1\)
+   120000494:	1000ff12 	b	1200000e0 <fn>
+   120000498:	df858028 	ld	a1,-32728\(gp\)
+   12000049c:	df858060 	ld	a1,-32672\(gp\)
+   1200004a0:	10000010 	b	1200004e4 <fn2>
+   1200004a4:	00000000 	nop
+   1200004a8:	df858038 	ld	a1,-32712\(gp\)
+   1200004ac:	1000ff0c 	b	1200000e0 <fn>
+   1200004b0:	00000000 	nop
+   1200004b4:	df858020 	ld	a1,-32736\(gp\)
+   1200004b8:	1000000a 	b	1200004e4 <fn2>
+   1200004bc:	dca505a4 	ld	a1,1444\(a1\)
+   1200004c0:	df858020 	ld	a1,-32736\(gp\)
+   1200004c4:	1000ff06 	b	1200000e0 <fn>
+   1200004c8:	dca50538 	ld	a1,1336\(a1\)
+   1200004cc:	df818020 	ld	at,-32736\(gp\)
+   1200004d0:	0025082d 	daddu	at,at,a1
+   1200004d4:	10000003 	b	1200004e4 <fn2>
+   1200004d8:	dc2505c6 	ld	a1,1478\(at\)
+	\.\.\.
+
+00000001200004e4 <fn2>:
+	\.\.\.
+Disassembly of section \.data:
+
+00000001200104f0 <_fdata>:
+	\.\.\.
+
+000000012001052c <dg1>:
+	\.\.\.
+
+0000000120010568 <sp2>:
+	\.\.\.
+
+00000001200105a4 <dg2>:
+	\.\.\.
+Disassembly of section \.got:
+
+00000001200105e0 <_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+   1200105e8:	80000000 	.*
+   1200105ec:	00000000 	.*
+   1200105f0:	00000001 	.*
+   1200105f4:	20010000 	.*
+   1200105f8:	00000001 	.*
+   1200105fc:	2001052c 	.*
+   120010600:	00000001 	.*
+   120010604:	20010538 	.*
+   120010608:	00000001 	.*
+   12001060c:	2002e76c 	.*
+   120010610:	00000001 	.*
+   120010614:	2001054e 	.*
+   120010618:	00000001 	.*
+   12001061c:	20010564 	.*
+   120010620:	00000001 	.*
+   120010624:	200000e0 	.*
+   120010628:	00000001 	.*
+   12001062c:	200105a4 	.*
+   120010630:	00000001 	.*
+   120010634:	200105b0 	.*
+   120010638:	00000001 	.*
+   12001063c:	2002e7e4 	.*
+   120010640:	00000001 	.*
+   120010644:	200105c6 	.*
+   120010648:	00000001 	.*
+   12001064c:	200105dc 	.*
+   120010650:	00000001 	.*
+   120010654:	200004e4 	.*
+	\.\.\.
+   120010678:	00000001 	.*
+   12001067c:	200000e0 	.*
+   120010680:	00000001 	.*
+   120010684:	200004e4 	.*
+   120010688:	00000001 	.*
+   12001068c:	2001052c 	.*
+   120010690:	00000001 	.*
+   120010694:	200105a4 	.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-got-n64.d b/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-got-n64.d
new file mode 100644
index 0000000..8ebfdf8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-got-n64.d
@@ -0,0 +1,332 @@
+#name: MIPS ELF got reloc n64
+#as: -EB -64 -KPIC
+#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s
+#ld: -melf64btsmip
+#objdump: -D --show-raw-insn
+
+.*: +file format elf64-.*mips.*
+
+Disassembly of section \.MIPS\.options:
+
+00000000100000b0 <\.MIPS\.options>:
+    100000b0:	01280000 	.*
+    100000b4:	00000000 	.*
+    100000b8:	92020022 	.*
+	\.\.\.
+    100000d4:	101085d0 	.*
+Disassembly of section \.text:
+
+00000000100000e0 <fn>:
+    100000e0:	df8580b8 	ld	a1,-32584\(gp\)
+    100000e4:	df8580b8 	ld	a1,-32584\(gp\)
+    100000e8:	64a5000c 	daddiu	a1,a1,12
+    100000ec:	df8580b8 	ld	a1,-32584\(gp\)
+    100000f0:	3c010002 	lui	at,0x2
+    100000f4:	6421e240 	daddiu	at,at,-7616
+    100000f8:	00a1282d 	daddu	a1,a1,at
+    100000fc:	df8580b8 	ld	a1,-32584\(gp\)
+    10000100:	00b1282d 	daddu	a1,a1,s1
+    10000104:	df8580b8 	ld	a1,-32584\(gp\)
+    10000108:	64a5000c 	daddiu	a1,a1,12
+    1000010c:	00b1282d 	daddu	a1,a1,s1
+    10000110:	df8580b8 	ld	a1,-32584\(gp\)
+    10000114:	3c010002 	lui	at,0x2
+    10000118:	6421e240 	daddiu	at,at,-7616
+    1000011c:	00a1282d 	daddu	a1,a1,at
+    10000120:	00b1282d 	daddu	a1,a1,s1
+    10000124:	df8580b8 	ld	a1,-32584\(gp\)
+    10000128:	dca50000 	ld	a1,0\(a1\)
+    1000012c:	df8580b8 	ld	a1,-32584\(gp\)
+    10000130:	dca5000c 	ld	a1,12\(a1\)
+    10000134:	df8580b8 	ld	a1,-32584\(gp\)
+    10000138:	00b1282d 	daddu	a1,a1,s1
+    1000013c:	dca50000 	ld	a1,0\(a1\)
+    10000140:	df8580b8 	ld	a1,-32584\(gp\)
+    10000144:	00b1282d 	daddu	a1,a1,s1
+    10000148:	dca5000c 	ld	a1,12\(a1\)
+    1000014c:	df8180b8 	ld	at,-32584\(gp\)
+    10000150:	0025082d 	daddu	at,at,a1
+    10000154:	dc250022 	ld	a1,34\(at\)
+    10000158:	df8180b8 	ld	at,-32584\(gp\)
+    1000015c:	0025082d 	daddu	at,at,a1
+    10000160:	fc250038 	sd	a1,56\(at\)
+    10000164:	df8180b8 	ld	at,-32584\(gp\)
+    10000168:	88250000 	lwl	a1,0\(at\)
+    1000016c:	98250003 	lwr	a1,3\(at\)
+    10000170:	df8180b8 	ld	at,-32584\(gp\)
+    10000174:	6421000c 	daddiu	at,at,12
+    10000178:	88250000 	lwl	a1,0\(at\)
+    1000017c:	98250003 	lwr	a1,3\(at\)
+    10000180:	df8180b8 	ld	at,-32584\(gp\)
+    10000184:	0031082d 	daddu	at,at,s1
+    10000188:	88250000 	lwl	a1,0\(at\)
+    1000018c:	98250003 	lwr	a1,3\(at\)
+    10000190:	df8180b8 	ld	at,-32584\(gp\)
+    10000194:	6421000c 	daddiu	at,at,12
+    10000198:	0031082d 	daddu	at,at,s1
+    1000019c:	88250000 	lwl	a1,0\(at\)
+    100001a0:	98250003 	lwr	a1,3\(at\)
+    100001a4:	df8180b8 	ld	at,-32584\(gp\)
+    100001a8:	64210022 	daddiu	at,at,34
+    100001ac:	0025082d 	daddu	at,at,a1
+    100001b0:	88250000 	lwl	a1,0\(at\)
+    100001b4:	98250003 	lwr	a1,3\(at\)
+    100001b8:	df8180b8 	ld	at,-32584\(gp\)
+    100001bc:	64210038 	daddiu	at,at,56
+    100001c0:	0025082d 	daddu	at,at,a1
+    100001c4:	a8250000 	swl	a1,0\(at\)
+    100001c8:	b8250003 	swr	a1,3\(at\)
+    100001cc:	df858020 	ld	a1,-32736\(gp\)
+    100001d0:	df858028 	ld	a1,-32728\(gp\)
+    100001d4:	df858030 	ld	a1,-32720\(gp\)
+    100001d8:	df858020 	ld	a1,-32736\(gp\)
+    100001dc:	00b1282d 	daddu	a1,a1,s1
+    100001e0:	df858028 	ld	a1,-32728\(gp\)
+    100001e4:	00b1282d 	daddu	a1,a1,s1
+    100001e8:	df858030 	ld	a1,-32720\(gp\)
+    100001ec:	00b1282d 	daddu	a1,a1,s1
+    100001f0:	df858038 	ld	a1,-32712\(gp\)
+    100001f4:	dca5052c 	ld	a1,1324\(a1\)
+    100001f8:	df858038 	ld	a1,-32712\(gp\)
+    100001fc:	dca50538 	ld	a1,1336\(a1\)
+    10000200:	df858038 	ld	a1,-32712\(gp\)
+    10000204:	00b1282d 	daddu	a1,a1,s1
+    10000208:	dca5052c 	ld	a1,1324\(a1\)
+    1000020c:	df858038 	ld	a1,-32712\(gp\)
+    10000210:	00b1282d 	daddu	a1,a1,s1
+    10000214:	dca50538 	ld	a1,1336\(a1\)
+    10000218:	df818038 	ld	at,-32712\(gp\)
+    1000021c:	0025082d 	daddu	at,at,a1
+    10000220:	dc25054e 	ld	a1,1358\(at\)
+    10000224:	df818038 	ld	at,-32712\(gp\)
+    10000228:	0025082d 	daddu	at,at,a1
+    1000022c:	fc250564 	sd	a1,1380\(at\)
+    10000230:	df818020 	ld	at,-32736\(gp\)
+    10000234:	88250000 	lwl	a1,0\(at\)
+    10000238:	98250003 	lwr	a1,3\(at\)
+    1000023c:	df818028 	ld	at,-32728\(gp\)
+    10000240:	88250000 	lwl	a1,0\(at\)
+    10000244:	98250003 	lwr	a1,3\(at\)
+    10000248:	df818020 	ld	at,-32736\(gp\)
+    1000024c:	0031082d 	daddu	at,at,s1
+    10000250:	88250000 	lwl	a1,0\(at\)
+    10000254:	98250003 	lwr	a1,3\(at\)
+    10000258:	df818028 	ld	at,-32728\(gp\)
+    1000025c:	0031082d 	daddu	at,at,s1
+    10000260:	88250000 	lwl	a1,0\(at\)
+    10000264:	98250003 	lwr	a1,3\(at\)
+    10000268:	df818040 	ld	at,-32704\(gp\)
+    1000026c:	0025082d 	daddu	at,at,a1
+    10000270:	88250000 	lwl	a1,0\(at\)
+    10000274:	98250003 	lwr	a1,3\(at\)
+    10000278:	df818048 	ld	at,-32696\(gp\)
+    1000027c:	0025082d 	daddu	at,at,a1
+    10000280:	a8250000 	swl	a1,0\(at\)
+    10000284:	b8250003 	swr	a1,3\(at\)
+    10000288:	df8580a8 	ld	a1,-32600\(gp\)
+    1000028c:	df858050 	ld	a1,-32688\(gp\)
+    10000290:	df9980a8 	ld	t9,-32600\(gp\)
+    10000294:	df998050 	ld	t9,-32688\(gp\)
+    10000298:	df9980a8 	ld	t9,-32600\(gp\)
+    1000029c:	0320f809 	jalr	t9
+    100002a0:	00000000 	nop
+    100002a4:	df998050 	ld	t9,-32688\(gp\)
+    100002a8:	0320f809 	jalr	t9
+    100002ac:	00000000 	nop
+    100002b0:	df8580c0 	ld	a1,-32576\(gp\)
+    100002b4:	df8580c0 	ld	a1,-32576\(gp\)
+    100002b8:	64a5000c 	daddiu	a1,a1,12
+    100002bc:	df8580c0 	ld	a1,-32576\(gp\)
+    100002c0:	3c010002 	lui	at,0x2
+    100002c4:	6421e240 	daddiu	at,at,-7616
+    100002c8:	00a1282d 	daddu	a1,a1,at
+    100002cc:	df8580c0 	ld	a1,-32576\(gp\)
+    100002d0:	00b1282d 	daddu	a1,a1,s1
+    100002d4:	df8580c0 	ld	a1,-32576\(gp\)
+    100002d8:	64a5000c 	daddiu	a1,a1,12
+    100002dc:	00b1282d 	daddu	a1,a1,s1
+    100002e0:	df8580c0 	ld	a1,-32576\(gp\)
+    100002e4:	3c010002 	lui	at,0x2
+    100002e8:	6421e240 	daddiu	at,at,-7616
+    100002ec:	00a1282d 	daddu	a1,a1,at
+    100002f0:	00b1282d 	daddu	a1,a1,s1
+    100002f4:	df8580c0 	ld	a1,-32576\(gp\)
+    100002f8:	dca50000 	ld	a1,0\(a1\)
+    100002fc:	df8580c0 	ld	a1,-32576\(gp\)
+    10000300:	dca5000c 	ld	a1,12\(a1\)
+    10000304:	df8580c0 	ld	a1,-32576\(gp\)
+    10000308:	00b1282d 	daddu	a1,a1,s1
+    1000030c:	dca50000 	ld	a1,0\(a1\)
+    10000310:	df8580c0 	ld	a1,-32576\(gp\)
+    10000314:	00b1282d 	daddu	a1,a1,s1
+    10000318:	dca5000c 	ld	a1,12\(a1\)
+    1000031c:	df8180c0 	ld	at,-32576\(gp\)
+    10000320:	0025082d 	daddu	at,at,a1
+    10000324:	dc250022 	ld	a1,34\(at\)
+    10000328:	df8180c0 	ld	at,-32576\(gp\)
+    1000032c:	0025082d 	daddu	at,at,a1
+    10000330:	fc250038 	sd	a1,56\(at\)
+    10000334:	df8180c0 	ld	at,-32576\(gp\)
+    10000338:	88250000 	lwl	a1,0\(at\)
+    1000033c:	98250003 	lwr	a1,3\(at\)
+    10000340:	df8180c0 	ld	at,-32576\(gp\)
+    10000344:	6421000c 	daddiu	at,at,12
+    10000348:	88250000 	lwl	a1,0\(at\)
+    1000034c:	98250003 	lwr	a1,3\(at\)
+    10000350:	df8180c0 	ld	at,-32576\(gp\)
+    10000354:	0031082d 	daddu	at,at,s1
+    10000358:	88250000 	lwl	a1,0\(at\)
+    1000035c:	98250003 	lwr	a1,3\(at\)
+    10000360:	df8180c0 	ld	at,-32576\(gp\)
+    10000364:	6421000c 	daddiu	at,at,12
+    10000368:	0031082d 	daddu	at,at,s1
+    1000036c:	88250000 	lwl	a1,0\(at\)
+    10000370:	98250003 	lwr	a1,3\(at\)
+    10000374:	df8180c0 	ld	at,-32576\(gp\)
+    10000378:	64210022 	daddiu	at,at,34
+    1000037c:	0025082d 	daddu	at,at,a1
+    10000380:	88250000 	lwl	a1,0\(at\)
+    10000384:	98250003 	lwr	a1,3\(at\)
+    10000388:	df8180c0 	ld	at,-32576\(gp\)
+    1000038c:	64210038 	daddiu	at,at,56
+    10000390:	0025082d 	daddu	at,at,a1
+    10000394:	a8250000 	swl	a1,0\(at\)
+    10000398:	b8250003 	swr	a1,3\(at\)
+    1000039c:	df858058 	ld	a1,-32680\(gp\)
+    100003a0:	df858060 	ld	a1,-32672\(gp\)
+    100003a4:	df858068 	ld	a1,-32664\(gp\)
+    100003a8:	df858058 	ld	a1,-32680\(gp\)
+    100003ac:	00b1282d 	daddu	a1,a1,s1
+    100003b0:	df858060 	ld	a1,-32672\(gp\)
+    100003b4:	00b1282d 	daddu	a1,a1,s1
+    100003b8:	df858068 	ld	a1,-32664\(gp\)
+    100003bc:	00b1282d 	daddu	a1,a1,s1
+    100003c0:	df858038 	ld	a1,-32712\(gp\)
+    100003c4:	dca505a4 	ld	a1,1444\(a1\)
+    100003c8:	df858038 	ld	a1,-32712\(gp\)
+    100003cc:	dca505b0 	ld	a1,1456\(a1\)
+    100003d0:	df858038 	ld	a1,-32712\(gp\)
+    100003d4:	00b1282d 	daddu	a1,a1,s1
+    100003d8:	dca505a4 	ld	a1,1444\(a1\)
+    100003dc:	df858038 	ld	a1,-32712\(gp\)
+    100003e0:	00b1282d 	daddu	a1,a1,s1
+    100003e4:	dca505b0 	ld	a1,1456\(a1\)
+    100003e8:	df818038 	ld	at,-32712\(gp\)
+    100003ec:	0025082d 	daddu	at,at,a1
+    100003f0:	dc2505c6 	ld	a1,1478\(at\)
+    100003f4:	df818038 	ld	at,-32712\(gp\)
+    100003f8:	0025082d 	daddu	at,at,a1
+    100003fc:	fc2505dc 	sd	a1,1500\(at\)
+    10000400:	df818058 	ld	at,-32680\(gp\)
+    10000404:	88250000 	lwl	a1,0\(at\)
+    10000408:	98250003 	lwr	a1,3\(at\)
+    1000040c:	df818060 	ld	at,-32672\(gp\)
+    10000410:	88250000 	lwl	a1,0\(at\)
+    10000414:	98250003 	lwr	a1,3\(at\)
+    10000418:	df818058 	ld	at,-32680\(gp\)
+    1000041c:	0031082d 	daddu	at,at,s1
+    10000420:	88250000 	lwl	a1,0\(at\)
+    10000424:	98250003 	lwr	a1,3\(at\)
+    10000428:	df818060 	ld	at,-32672\(gp\)
+    1000042c:	0031082d 	daddu	at,at,s1
+    10000430:	88250000 	lwl	a1,0\(at\)
+    10000434:	98250003 	lwr	a1,3\(at\)
+    10000438:	df818070 	ld	at,-32656\(gp\)
+    1000043c:	0025082d 	daddu	at,at,a1
+    10000440:	88250000 	lwl	a1,0\(at\)
+    10000444:	98250003 	lwr	a1,3\(at\)
+    10000448:	df818078 	ld	at,-32648\(gp\)
+    1000044c:	0025082d 	daddu	at,at,a1
+    10000450:	a8250000 	swl	a1,0\(at\)
+    10000454:	b8250003 	swr	a1,3\(at\)
+    10000458:	df8580b0 	ld	a1,-32592\(gp\)
+    1000045c:	df858080 	ld	a1,-32640\(gp\)
+    10000460:	df9980b0 	ld	t9,-32592\(gp\)
+    10000464:	df998080 	ld	t9,-32640\(gp\)
+    10000468:	df9980b0 	ld	t9,-32592\(gp\)
+    1000046c:	0320f809 	jalr	t9
+    10000470:	00000000 	nop
+    10000474:	df998080 	ld	t9,-32640\(gp\)
+    10000478:	0320f809 	jalr	t9
+    1000047c:	00000000 	nop
+    10000480:	1000ff17 	b	100000e0 <fn>
+    10000484:	df8580b8 	ld	a1,-32584\(gp\)
+    10000488:	df8580c0 	ld	a1,-32576\(gp\)
+    1000048c:	10000015 	b	100004e4 <fn2>
+    10000490:	dca50000 	ld	a1,0\(a1\)
+    10000494:	1000ff12 	b	100000e0 <fn>
+    10000498:	df858020 	ld	a1,-32736\(gp\)
+    1000049c:	df858060 	ld	a1,-32672\(gp\)
+    100004a0:	10000010 	b	100004e4 <fn2>
+    100004a4:	00000000 	nop
+    100004a8:	df858030 	ld	a1,-32720\(gp\)
+    100004ac:	1000ff0c 	b	100000e0 <fn>
+    100004b0:	00000000 	nop
+    100004b4:	df858038 	ld	a1,-32712\(gp\)
+    100004b8:	1000000a 	b	100004e4 <fn2>
+    100004bc:	dca505a4 	ld	a1,1444\(a1\)
+    100004c0:	df858038 	ld	a1,-32712\(gp\)
+    100004c4:	1000ff06 	b	100000e0 <fn>
+    100004c8:	dca50538 	ld	a1,1336\(a1\)
+    100004cc:	df818038 	ld	at,-32712\(gp\)
+    100004d0:	0025082d 	daddu	at,at,a1
+    100004d4:	10000003 	b	100004e4 <fn2>
+    100004d8:	dc2505c6 	ld	a1,1478\(at\)
+	\.\.\.
+
+00000000100004e4 <fn2>:
+	\.\.\.
+Disassembly of section \.data:
+
+00000000101004f0 <_fdata>:
+	\.\.\.
+
+000000001010052c <dg1>:
+	\.\.\.
+
+0000000010100568 <sp2>:
+	\.\.\.
+
+00000000101005a4 <dg2>:
+	\.\.\.
+Disassembly of section \.got:
+
+00000000101005e0 <_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+    101005e8:	80000000 	.*
+    101005ec:	00000000 	.*
+    101005f0:	00000000 	.*
+    101005f4:	1010052c 	.*
+    101005f8:	00000000 	.*
+    101005fc:	10100538 	.*
+    10100600:	00000000 	.*
+    10100604:	1011e76c 	.*
+    10100608:	00000000 	.*
+    1010060c:	10100000 	.*
+    10100610:	00000000 	.*
+    10100614:	1010054e 	.*
+    10100618:	00000000 	.*
+    1010061c:	10100564 	.*
+    10100620:	00000000 	.*
+    10100624:	100000e0 	.*
+    10100628:	00000000 	.*
+    1010062c:	101005a4 	.*
+    10100630:	00000000 	.*
+    10100634:	101005b0 	.*
+    10100638:	00000000 	.*
+    1010063c:	1011e7e4 	.*
+    10100640:	00000000 	.*
+    10100644:	101005c6 	.*
+    10100648:	00000000 	.*
+    1010064c:	101005dc 	.*
+    10100650:	00000000 	.*
+    10100654:	100004e4 	.*
+    10100658:	00000000 	.*
+	\.\.\.
+    1010067c:	100000e0 	.*
+    10100680:	00000000 	.*
+    10100684:	100004e4 	.*
+    10100688:	00000000 	.*
+    1010068c:	1010052c 	.*
+    10100690:	00000000 	.*
+    10100694:	101005a4 	.*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d
new file mode 100644
index 0000000..097ec33
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d
@@ -0,0 +1,429 @@
+#name: MIPS ELF xgot reloc n32
+#as: -EB -n32 -KPIC -xgot
+#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s
+#ld: -melf32btsmipn32
+#objdump: -D --show-raw-insn
+
+.*: +file format elf32-n.*mips.*
+
+Disassembly of section \.reginfo:
+
+10000098 <\.reginfo>:
+10000098:	92020022 	.*
+	\.\.\.
+100000ac:	10018790 	.*
+
+Disassembly of section \.text:
+
+100000b0 <fn>:
+100000b0:	3c050000 	lui	a1,0x0
+100000b4:	00bc2821 	addu	a1,a1,gp
+100000b8:	8ca58034 	lw	a1,-32716\(a1\)
+100000bc:	3c050000 	lui	a1,0x0
+100000c0:	00bc2821 	addu	a1,a1,gp
+100000c4:	8ca58034 	lw	a1,-32716\(a1\)
+100000c8:	24a5000c 	addiu	a1,a1,12
+100000cc:	3c050000 	lui	a1,0x0
+100000d0:	00bc2821 	addu	a1,a1,gp
+100000d4:	8ca58034 	lw	a1,-32716\(a1\)
+100000d8:	3c010001 	lui	at,0x1
+100000dc:	3421e240 	ori	at,at,0xe240
+100000e0:	00a12821 	addu	a1,a1,at
+100000e4:	3c050000 	lui	a1,0x0
+100000e8:	00bc2821 	addu	a1,a1,gp
+100000ec:	8ca58034 	lw	a1,-32716\(a1\)
+100000f0:	00b12821 	addu	a1,a1,s1
+100000f4:	3c050000 	lui	a1,0x0
+100000f8:	00bc2821 	addu	a1,a1,gp
+100000fc:	8ca58034 	lw	a1,-32716\(a1\)
+10000100:	24a5000c 	addiu	a1,a1,12
+10000104:	00b12821 	addu	a1,a1,s1
+10000108:	3c050000 	lui	a1,0x0
+1000010c:	00bc2821 	addu	a1,a1,gp
+10000110:	8ca58034 	lw	a1,-32716\(a1\)
+10000114:	3c010001 	lui	at,0x1
+10000118:	3421e240 	ori	at,at,0xe240
+1000011c:	00a12821 	addu	a1,a1,at
+10000120:	00b12821 	addu	a1,a1,s1
+10000124:	3c050000 	lui	a1,0x0
+10000128:	00bc2821 	addu	a1,a1,gp
+1000012c:	8ca58034 	lw	a1,-32716\(a1\)
+10000130:	8ca50000 	lw	a1,0\(a1\)
+10000134:	3c050000 	lui	a1,0x0
+10000138:	00bc2821 	addu	a1,a1,gp
+1000013c:	8ca58034 	lw	a1,-32716\(a1\)
+10000140:	8ca5000c 	lw	a1,12\(a1\)
+10000144:	3c050000 	lui	a1,0x0
+10000148:	00bc2821 	addu	a1,a1,gp
+1000014c:	8ca58034 	lw	a1,-32716\(a1\)
+10000150:	00b12821 	addu	a1,a1,s1
+10000154:	8ca50000 	lw	a1,0\(a1\)
+10000158:	3c050000 	lui	a1,0x0
+1000015c:	00bc2821 	addu	a1,a1,gp
+10000160:	8ca58034 	lw	a1,-32716\(a1\)
+10000164:	00b12821 	addu	a1,a1,s1
+10000168:	8ca5000c 	lw	a1,12\(a1\)
+1000016c:	3c010000 	lui	at,0x0
+10000170:	003c0821 	addu	at,at,gp
+10000174:	8c218034 	lw	at,-32716\(at\)
+10000178:	00250821 	addu	at,at,a1
+1000017c:	8c250022 	lw	a1,34\(at\)
+10000180:	3c010000 	lui	at,0x0
+10000184:	003c0821 	addu	at,at,gp
+10000188:	8c218034 	lw	at,-32716\(at\)
+1000018c:	00250821 	addu	at,at,a1
+10000190:	ac250038 	sw	a1,56\(at\)
+10000194:	3c010000 	lui	at,0x0
+10000198:	003c0821 	addu	at,at,gp
+1000019c:	8c218034 	lw	at,-32716\(at\)
+100001a0:	88250000 	lwl	a1,0\(at\)
+100001a4:	98250003 	lwr	a1,3\(at\)
+100001a8:	3c010000 	lui	at,0x0
+100001ac:	003c0821 	addu	at,at,gp
+100001b0:	8c218034 	lw	at,-32716\(at\)
+100001b4:	2421000c 	addiu	at,at,12
+100001b8:	88250000 	lwl	a1,0\(at\)
+100001bc:	98250003 	lwr	a1,3\(at\)
+100001c0:	3c010000 	lui	at,0x0
+100001c4:	003c0821 	addu	at,at,gp
+100001c8:	8c218034 	lw	at,-32716\(at\)
+100001cc:	00310821 	addu	at,at,s1
+100001d0:	88250000 	lwl	a1,0\(at\)
+100001d4:	98250003 	lwr	a1,3\(at\)
+100001d8:	3c010000 	lui	at,0x0
+100001dc:	003c0821 	addu	at,at,gp
+100001e0:	8c218034 	lw	at,-32716\(at\)
+100001e4:	2421000c 	addiu	at,at,12
+100001e8:	00310821 	addu	at,at,s1
+100001ec:	88250000 	lwl	a1,0\(at\)
+100001f0:	98250003 	lwr	a1,3\(at\)
+100001f4:	3c010000 	lui	at,0x0
+100001f8:	003c0821 	addu	at,at,gp
+100001fc:	8c218034 	lw	at,-32716\(at\)
+10000200:	24210022 	addiu	at,at,34
+10000204:	00250821 	addu	at,at,a1
+10000208:	88250000 	lwl	a1,0\(at\)
+1000020c:	98250003 	lwr	a1,3\(at\)
+10000210:	3c010000 	lui	at,0x0
+10000214:	003c0821 	addu	at,at,gp
+10000218:	8c218034 	lw	at,-32716\(at\)
+1000021c:	24210038 	addiu	at,at,56
+10000220:	00250821 	addu	at,at,a1
+10000224:	a8250000 	swl	a1,0\(at\)
+10000228:	b8250003 	swr	a1,3\(at\)
+1000022c:	8f858018 	lw	a1,-32744\(gp\)
+10000230:	24a506ec 	addiu	a1,a1,1772
+10000234:	8f858018 	lw	a1,-32744\(gp\)
+10000238:	24a506f8 	addiu	a1,a1,1784
+1000023c:	8f85801c 	lw	a1,-32740\(gp\)
+10000240:	24a5e92c 	addiu	a1,a1,-5844
+10000244:	8f858018 	lw	a1,-32744\(gp\)
+10000248:	24a506ec 	addiu	a1,a1,1772
+1000024c:	00b12821 	addu	a1,a1,s1
+10000250:	8f858018 	lw	a1,-32744\(gp\)
+10000254:	24a506f8 	addiu	a1,a1,1784
+10000258:	00b12821 	addu	a1,a1,s1
+1000025c:	8f85801c 	lw	a1,-32740\(gp\)
+10000260:	24a5e92c 	addiu	a1,a1,-5844
+10000264:	00b12821 	addu	a1,a1,s1
+10000268:	8f858018 	lw	a1,-32744\(gp\)
+1000026c:	8ca506ec 	lw	a1,1772\(a1\)
+10000270:	8f858018 	lw	a1,-32744\(gp\)
+10000274:	8ca506f8 	lw	a1,1784\(a1\)
+10000278:	8f858018 	lw	a1,-32744\(gp\)
+1000027c:	00b12821 	addu	a1,a1,s1
+10000280:	8ca506ec 	lw	a1,1772\(a1\)
+10000284:	8f858018 	lw	a1,-32744\(gp\)
+10000288:	00b12821 	addu	a1,a1,s1
+1000028c:	8ca506f8 	lw	a1,1784\(a1\)
+10000290:	8f818018 	lw	at,-32744\(gp\)
+10000294:	00250821 	addu	at,at,a1
+10000298:	8c25070e 	lw	a1,1806\(at\)
+1000029c:	8f818018 	lw	at,-32744\(gp\)
+100002a0:	00250821 	addu	at,at,a1
+100002a4:	ac250724 	sw	a1,1828\(at\)
+100002a8:	8f818018 	lw	at,-32744\(gp\)
+100002ac:	242106ec 	addiu	at,at,1772
+100002b0:	88250000 	lwl	a1,0\(at\)
+100002b4:	98250003 	lwr	a1,3\(at\)
+100002b8:	8f818018 	lw	at,-32744\(gp\)
+100002bc:	242106f8 	addiu	at,at,1784
+100002c0:	88250000 	lwl	a1,0\(at\)
+100002c4:	98250003 	lwr	a1,3\(at\)
+100002c8:	8f818018 	lw	at,-32744\(gp\)
+100002cc:	242106ec 	addiu	at,at,1772
+100002d0:	00310821 	addu	at,at,s1
+100002d4:	88250000 	lwl	a1,0\(at\)
+100002d8:	98250003 	lwr	a1,3\(at\)
+100002dc:	8f818018 	lw	at,-32744\(gp\)
+100002e0:	242106f8 	addiu	at,at,1784
+100002e4:	00310821 	addu	at,at,s1
+100002e8:	88250000 	lwl	a1,0\(at\)
+100002ec:	98250003 	lwr	a1,3\(at\)
+100002f0:	8f818018 	lw	at,-32744\(gp\)
+100002f4:	2421070e 	addiu	at,at,1806
+100002f8:	00250821 	addu	at,at,a1
+100002fc:	88250000 	lwl	a1,0\(at\)
+10000300:	98250003 	lwr	a1,3\(at\)
+10000304:	8f818018 	lw	at,-32744\(gp\)
+10000308:	24210724 	addiu	at,at,1828
+1000030c:	00250821 	addu	at,at,a1
+10000310:	a8250000 	swl	a1,0\(at\)
+10000314:	b8250003 	swr	a1,3\(at\)
+10000318:	3c050000 	lui	a1,0x0
+1000031c:	00bc2821 	addu	a1,a1,gp
+10000320:	8ca5802c 	lw	a1,-32724\(a1\)
+10000324:	8f858020 	lw	a1,-32736\(gp\)
+10000328:	24a500b0 	addiu	a1,a1,176
+1000032c:	3c190000 	lui	t9,0x0
+10000330:	033cc821 	addu	t9,t9,gp
+10000334:	8f39802c 	lw	t9,-32724\(t9\)
+10000338:	8f998020 	lw	t9,-32736\(gp\)
+1000033c:	273900b0 	addiu	t9,t9,176
+10000340:	3c190000 	lui	t9,0x0
+10000344:	033cc821 	addu	t9,t9,gp
+10000348:	8f39802c 	lw	t9,-32724\(t9\)
+1000034c:	0320f809 	jalr	t9
+10000350:	00000000 	nop
+10000354:	8f998020 	lw	t9,-32736\(gp\)
+10000358:	273900b0 	addiu	t9,t9,176
+1000035c:	0320f809 	jalr	t9
+10000360:	00000000 	nop
+10000364:	3c050000 	lui	a1,0x0
+10000368:	00bc2821 	addu	a1,a1,gp
+1000036c:	8ca58038 	lw	a1,-32712\(a1\)
+10000370:	3c050000 	lui	a1,0x0
+10000374:	00bc2821 	addu	a1,a1,gp
+10000378:	8ca58038 	lw	a1,-32712\(a1\)
+1000037c:	24a5000c 	addiu	a1,a1,12
+10000380:	3c050000 	lui	a1,0x0
+10000384:	00bc2821 	addu	a1,a1,gp
+10000388:	8ca58038 	lw	a1,-32712\(a1\)
+1000038c:	3c010001 	lui	at,0x1
+10000390:	3421e240 	ori	at,at,0xe240
+10000394:	00a12821 	addu	a1,a1,at
+10000398:	3c050000 	lui	a1,0x0
+1000039c:	00bc2821 	addu	a1,a1,gp
+100003a0:	8ca58038 	lw	a1,-32712\(a1\)
+100003a4:	00b12821 	addu	a1,a1,s1
+100003a8:	3c050000 	lui	a1,0x0
+100003ac:	00bc2821 	addu	a1,a1,gp
+100003b0:	8ca58038 	lw	a1,-32712\(a1\)
+100003b4:	24a5000c 	addiu	a1,a1,12
+100003b8:	00b12821 	addu	a1,a1,s1
+100003bc:	3c050000 	lui	a1,0x0
+100003c0:	00bc2821 	addu	a1,a1,gp
+100003c4:	8ca58038 	lw	a1,-32712\(a1\)
+100003c8:	3c010001 	lui	at,0x1
+100003cc:	3421e240 	ori	at,at,0xe240
+100003d0:	00a12821 	addu	a1,a1,at
+100003d4:	00b12821 	addu	a1,a1,s1
+100003d8:	3c050000 	lui	a1,0x0
+100003dc:	00bc2821 	addu	a1,a1,gp
+100003e0:	8ca58038 	lw	a1,-32712\(a1\)
+100003e4:	8ca50000 	lw	a1,0\(a1\)
+100003e8:	3c050000 	lui	a1,0x0
+100003ec:	00bc2821 	addu	a1,a1,gp
+100003f0:	8ca58038 	lw	a1,-32712\(a1\)
+100003f4:	8ca5000c 	lw	a1,12\(a1\)
+100003f8:	3c050000 	lui	a1,0x0
+100003fc:	00bc2821 	addu	a1,a1,gp
+10000400:	8ca58038 	lw	a1,-32712\(a1\)
+10000404:	00b12821 	addu	a1,a1,s1
+10000408:	8ca50000 	lw	a1,0\(a1\)
+1000040c:	3c050000 	lui	a1,0x0
+10000410:	00bc2821 	addu	a1,a1,gp
+10000414:	8ca58038 	lw	a1,-32712\(a1\)
+10000418:	00b12821 	addu	a1,a1,s1
+1000041c:	8ca5000c 	lw	a1,12\(a1\)
+10000420:	3c010000 	lui	at,0x0
+10000424:	003c0821 	addu	at,at,gp
+10000428:	8c218038 	lw	at,-32712\(at\)
+1000042c:	00250821 	addu	at,at,a1
+10000430:	8c250022 	lw	a1,34\(at\)
+10000434:	3c010000 	lui	at,0x0
+10000438:	003c0821 	addu	at,at,gp
+1000043c:	8c218038 	lw	at,-32712\(at\)
+10000440:	00250821 	addu	at,at,a1
+10000444:	ac250038 	sw	a1,56\(at\)
+10000448:	3c010000 	lui	at,0x0
+1000044c:	003c0821 	addu	at,at,gp
+10000450:	8c218038 	lw	at,-32712\(at\)
+10000454:	88250000 	lwl	a1,0\(at\)
+10000458:	98250003 	lwr	a1,3\(at\)
+1000045c:	3c010000 	lui	at,0x0
+10000460:	003c0821 	addu	at,at,gp
+10000464:	8c218038 	lw	at,-32712\(at\)
+10000468:	2421000c 	addiu	at,at,12
+1000046c:	88250000 	lwl	a1,0\(at\)
+10000470:	98250003 	lwr	a1,3\(at\)
+10000474:	3c010000 	lui	at,0x0
+10000478:	003c0821 	addu	at,at,gp
+1000047c:	8c218038 	lw	at,-32712\(at\)
+10000480:	00310821 	addu	at,at,s1
+10000484:	88250000 	lwl	a1,0\(at\)
+10000488:	98250003 	lwr	a1,3\(at\)
+1000048c:	3c010000 	lui	at,0x0
+10000490:	003c0821 	addu	at,at,gp
+10000494:	8c218038 	lw	at,-32712\(at\)
+10000498:	2421000c 	addiu	at,at,12
+1000049c:	00310821 	addu	at,at,s1
+100004a0:	88250000 	lwl	a1,0\(at\)
+100004a4:	98250003 	lwr	a1,3\(at\)
+100004a8:	3c010000 	lui	at,0x0
+100004ac:	003c0821 	addu	at,at,gp
+100004b0:	8c218038 	lw	at,-32712\(at\)
+100004b4:	24210022 	addiu	at,at,34
+100004b8:	00250821 	addu	at,at,a1
+100004bc:	88250000 	lwl	a1,0\(at\)
+100004c0:	98250003 	lwr	a1,3\(at\)
+100004c4:	3c010000 	lui	at,0x0
+100004c8:	003c0821 	addu	at,at,gp
+100004cc:	8c218038 	lw	at,-32712\(at\)
+100004d0:	24210038 	addiu	at,at,56
+100004d4:	00250821 	addu	at,at,a1
+100004d8:	a8250000 	swl	a1,0\(at\)
+100004dc:	b8250003 	swr	a1,3\(at\)
+100004e0:	8f858018 	lw	a1,-32744\(gp\)
+100004e4:	24a50764 	addiu	a1,a1,1892
+100004e8:	8f858018 	lw	a1,-32744\(gp\)
+100004ec:	24a50770 	addiu	a1,a1,1904
+100004f0:	8f85801c 	lw	a1,-32740\(gp\)
+100004f4:	24a5e9a4 	addiu	a1,a1,-5724
+100004f8:	8f858018 	lw	a1,-32744\(gp\)
+100004fc:	24a50764 	addiu	a1,a1,1892
+10000500:	00b12821 	addu	a1,a1,s1
+10000504:	8f858018 	lw	a1,-32744\(gp\)
+10000508:	24a50770 	addiu	a1,a1,1904
+1000050c:	00b12821 	addu	a1,a1,s1
+10000510:	8f85801c 	lw	a1,-32740\(gp\)
+10000514:	24a5e9a4 	addiu	a1,a1,-5724
+10000518:	00b12821 	addu	a1,a1,s1
+1000051c:	8f858018 	lw	a1,-32744\(gp\)
+10000520:	8ca50764 	lw	a1,1892\(a1\)
+10000524:	8f858018 	lw	a1,-32744\(gp\)
+10000528:	8ca50770 	lw	a1,1904\(a1\)
+1000052c:	8f858018 	lw	a1,-32744\(gp\)
+10000530:	00b12821 	addu	a1,a1,s1
+10000534:	8ca50764 	lw	a1,1892\(a1\)
+10000538:	8f858018 	lw	a1,-32744\(gp\)
+1000053c:	00b12821 	addu	a1,a1,s1
+10000540:	8ca50770 	lw	a1,1904\(a1\)
+10000544:	8f818018 	lw	at,-32744\(gp\)
+10000548:	00250821 	addu	at,at,a1
+1000054c:	8c250786 	lw	a1,1926\(at\)
+10000550:	8f818018 	lw	at,-32744\(gp\)
+10000554:	00250821 	addu	at,at,a1
+10000558:	ac25079c 	sw	a1,1948\(at\)
+1000055c:	8f818018 	lw	at,-32744\(gp\)
+10000560:	24210764 	addiu	at,at,1892
+10000564:	88250000 	lwl	a1,0\(at\)
+10000568:	98250003 	lwr	a1,3\(at\)
+1000056c:	8f818018 	lw	at,-32744\(gp\)
+10000570:	24210770 	addiu	at,at,1904
+10000574:	88250000 	lwl	a1,0\(at\)
+10000578:	98250003 	lwr	a1,3\(at\)
+1000057c:	8f818018 	lw	at,-32744\(gp\)
+10000580:	24210764 	addiu	at,at,1892
+10000584:	00310821 	addu	at,at,s1
+10000588:	88250000 	lwl	a1,0\(at\)
+1000058c:	98250003 	lwr	a1,3\(at\)
+10000590:	8f818018 	lw	at,-32744\(gp\)
+10000594:	24210770 	addiu	at,at,1904
+10000598:	00310821 	addu	at,at,s1
+1000059c:	88250000 	lwl	a1,0\(at\)
+100005a0:	98250003 	lwr	a1,3\(at\)
+100005a4:	8f818018 	lw	at,-32744\(gp\)
+100005a8:	24210786 	addiu	at,at,1926
+100005ac:	00250821 	addu	at,at,a1
+100005b0:	88250000 	lwl	a1,0\(at\)
+100005b4:	98250003 	lwr	a1,3\(at\)
+100005b8:	8f818018 	lw	at,-32744\(gp\)
+100005bc:	2421079c 	addiu	at,at,1948
+100005c0:	00250821 	addu	at,at,a1
+100005c4:	a8250000 	swl	a1,0\(at\)
+100005c8:	b8250003 	swr	a1,3\(at\)
+100005cc:	3c050000 	lui	a1,0x0
+100005d0:	00bc2821 	addu	a1,a1,gp
+100005d4:	8ca58030 	lw	a1,-32720\(a1\)
+100005d8:	8f858020 	lw	a1,-32736\(gp\)
+100005dc:	24a506b0 	addiu	a1,a1,1712
+100005e0:	3c190000 	lui	t9,0x0
+100005e4:	033cc821 	addu	t9,t9,gp
+100005e8:	8f398030 	lw	t9,-32720\(t9\)
+100005ec:	8f998020 	lw	t9,-32736\(gp\)
+100005f0:	273906b0 	addiu	t9,t9,1712
+100005f4:	3c190000 	lui	t9,0x0
+100005f8:	033cc821 	addu	t9,t9,gp
+100005fc:	8f398030 	lw	t9,-32720\(t9\)
+10000600:	0320f809 	jalr	t9
+10000604:	00000000 	nop
+10000608:	8f998020 	lw	t9,-32736\(gp\)
+1000060c:	273906b0 	addiu	t9,t9,1712
+10000610:	0320f809 	jalr	t9
+10000614:	00000000 	nop
+10000618:	3c050000 	lui	a1,0x0
+1000061c:	00bc2821 	addu	a1,a1,gp
+10000620:	8ca58034 	lw	a1,-32716\(a1\)
+10000624:	1000fea2 	b	100000b0 <fn>
+10000628:	00000000 	nop
+1000062c:	3c050000 	lui	a1,0x0
+10000630:	00bc2821 	addu	a1,a1,gp
+10000634:	8ca58038 	lw	a1,-32712\(a1\)
+10000638:	8ca50000 	lw	a1,0\(a1\)
+1000063c:	1000001c 	b	100006b0 <fn2>
+10000640:	00000000 	nop
+10000644:	8f858018 	lw	a1,-32744\(gp\)
+10000648:	24a506ec 	addiu	a1,a1,1772
+1000064c:	1000fe98 	b	100000b0 <fn>
+10000650:	00000000 	nop
+10000654:	8f858018 	lw	a1,-32744\(gp\)
+10000658:	24a50770 	addiu	a1,a1,1904
+1000065c:	10000014 	b	100006b0 <fn2>
+10000660:	00000000 	nop
+10000664:	8f85801c 	lw	a1,-32740\(gp\)
+10000668:	24a5e92c 	addiu	a1,a1,-5844
+1000066c:	1000fe90 	b	100000b0 <fn>
+10000670:	00000000 	nop
+10000674:	8f858018 	lw	a1,-32744\(gp\)
+10000678:	8ca50764 	lw	a1,1892\(a1\)
+1000067c:	1000000c 	b	100006b0 <fn2>
+10000680:	00000000 	nop
+10000684:	8f858018 	lw	a1,-32744\(gp\)
+10000688:	8ca506f8 	lw	a1,1784\(a1\)
+1000068c:	1000fe88 	b	100000b0 <fn>
+10000690:	00000000 	nop
+10000694:	8f818018 	lw	at,-32744\(gp\)
+10000698:	00250821 	addu	at,at,a1
+1000069c:	8c250786 	lw	a1,1926\(at\)
+100006a0:	10000003 	b	100006b0 <fn2>
+100006a4:	00000000 	nop
+	\.\.\.
+Disassembly of section \.data:
+
+100106b0 <_fdata>:
+	\.\.\.
+
+100106ec <dg1>:
+	\.\.\.
+
+10010728 <sp2>:
+	\.\.\.
+
+10010764 <dg2>:
+	\.\.\.
+Disassembly of section \.got:
+
+100107a0 <_GLOBAL_OFFSET_TABLE_>:
+100107a0:	00000000 	.*
+100107a4:	80000000 	.*
+100107a8:	10010000 	.*
+100107ac:	10030000 	.*
+100107b0:	10000000 	.*
+100107b4:	00000000 	.*
+100107b8:	00000000 	.*
+100107bc:	100000b0 	.*
+100107c0:	100006b0 	.*
+100107c4:	100106ec 	.*
+100107c8:	10010764 	.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d b/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d
new file mode 100644
index 0000000..4eb41a6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d
@@ -0,0 +1,438 @@
+#name: MIPS ELF xgot reloc n64
+#as: -EB -64 -KPIC -xgot
+#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s
+#ld: -melf64btsmip
+#objdump: -D --show-raw-insn
+
+.*: +file format elf64-.*mips.*
+
+Disassembly of section \.MIPS\.options:
+
+00000001200000b0 <\.MIPS\.options>:
+   1200000b0:	01280000 	.*
+   1200000b4:	00000000 	.*
+   1200000b8:	92020022 	.*
+	\.\.\.
+   1200000d0:	00000001 	.*
+   1200000d4:	200187c0 	.*
+Disassembly of section \.text:
+
+00000001200000e0 <fn>:
+   1200000e0:	3c050000 	lui	a1,0x0
+   1200000e4:	00bc282d 	daddu	a1,a1,gp
+   1200000e8:	dca58058 	ld	a1,-32680\(a1\)
+   1200000ec:	3c050000 	lui	a1,0x0
+   1200000f0:	00bc282d 	daddu	a1,a1,gp
+   1200000f4:	dca58058 	ld	a1,-32680\(a1\)
+   1200000f8:	64a5000c 	daddiu	a1,a1,12
+   1200000fc:	3c050000 	lui	a1,0x0
+   120000100:	00bc282d 	daddu	a1,a1,gp
+   120000104:	dca58058 	ld	a1,-32680\(a1\)
+   120000108:	3c010001 	lui	at,0x1
+   12000010c:	3421e240 	ori	at,at,0xe240
+   120000110:	00a1282d 	daddu	a1,a1,at
+   120000114:	3c050000 	lui	a1,0x0
+   120000118:	00bc282d 	daddu	a1,a1,gp
+   12000011c:	dca58058 	ld	a1,-32680\(a1\)
+   120000120:	00b1282d 	daddu	a1,a1,s1
+   120000124:	3c050000 	lui	a1,0x0
+   120000128:	00bc282d 	daddu	a1,a1,gp
+   12000012c:	dca58058 	ld	a1,-32680\(a1\)
+   120000130:	64a5000c 	daddiu	a1,a1,12
+   120000134:	00b1282d 	daddu	a1,a1,s1
+   120000138:	3c050000 	lui	a1,0x0
+   12000013c:	00bc282d 	daddu	a1,a1,gp
+   120000140:	dca58058 	ld	a1,-32680\(a1\)
+   120000144:	3c010001 	lui	at,0x1
+   120000148:	3421e240 	ori	at,at,0xe240
+   12000014c:	00a1282d 	daddu	a1,a1,at
+   120000150:	00b1282d 	daddu	a1,a1,s1
+   120000154:	3c050000 	lui	a1,0x0
+   120000158:	00bc282d 	daddu	a1,a1,gp
+   12000015c:	dca58058 	ld	a1,-32680\(a1\)
+   120000160:	dca50000 	ld	a1,0\(a1\)
+   120000164:	3c050000 	lui	a1,0x0
+   120000168:	00bc282d 	daddu	a1,a1,gp
+   12000016c:	dca58058 	ld	a1,-32680\(a1\)
+   120000170:	dca5000c 	ld	a1,12\(a1\)
+   120000174:	3c050000 	lui	a1,0x0
+   120000178:	00bc282d 	daddu	a1,a1,gp
+   12000017c:	dca58058 	ld	a1,-32680\(a1\)
+   120000180:	00b1282d 	daddu	a1,a1,s1
+   120000184:	dca50000 	ld	a1,0\(a1\)
+   120000188:	3c050000 	lui	a1,0x0
+   12000018c:	00bc282d 	daddu	a1,a1,gp
+   120000190:	dca58058 	ld	a1,-32680\(a1\)
+   120000194:	00b1282d 	daddu	a1,a1,s1
+   120000198:	dca5000c 	ld	a1,12\(a1\)
+   12000019c:	3c010000 	lui	at,0x0
+   1200001a0:	003c082d 	daddu	at,at,gp
+   1200001a4:	dc218058 	ld	at,-32680\(at\)
+   1200001a8:	0025082d 	daddu	at,at,a1
+   1200001ac:	dc250022 	ld	a1,34\(at\)
+   1200001b0:	3c010000 	lui	at,0x0
+   1200001b4:	003c082d 	daddu	at,at,gp
+   1200001b8:	dc218058 	ld	at,-32680\(at\)
+   1200001bc:	0025082d 	daddu	at,at,a1
+   1200001c0:	fc250038 	sd	a1,56\(at\)
+   1200001c4:	3c010000 	lui	at,0x0
+   1200001c8:	003c082d 	daddu	at,at,gp
+   1200001cc:	dc218058 	ld	at,-32680\(at\)
+   1200001d0:	88250000 	lwl	a1,0\(at\)
+   1200001d4:	98250003 	lwr	a1,3\(at\)
+   1200001d8:	3c010000 	lui	at,0x0
+   1200001dc:	003c082d 	daddu	at,at,gp
+   1200001e0:	dc218058 	ld	at,-32680\(at\)
+   1200001e4:	6421000c 	daddiu	at,at,12
+   1200001e8:	88250000 	lwl	a1,0\(at\)
+   1200001ec:	98250003 	lwr	a1,3\(at\)
+   1200001f0:	3c010000 	lui	at,0x0
+   1200001f4:	003c082d 	daddu	at,at,gp
+   1200001f8:	dc218058 	ld	at,-32680\(at\)
+   1200001fc:	0031082d 	daddu	at,at,s1
+   120000200:	88250000 	lwl	a1,0\(at\)
+   120000204:	98250003 	lwr	a1,3\(at\)
+   120000208:	3c010000 	lui	at,0x0
+   12000020c:	003c082d 	daddu	at,at,gp
+   120000210:	dc218058 	ld	at,-32680\(at\)
+   120000214:	6421000c 	daddiu	at,at,12
+   120000218:	0031082d 	daddu	at,at,s1
+   12000021c:	88250000 	lwl	a1,0\(at\)
+   120000220:	98250003 	lwr	a1,3\(at\)
+   120000224:	3c010000 	lui	at,0x0
+   120000228:	003c082d 	daddu	at,at,gp
+   12000022c:	dc218058 	ld	at,-32680\(at\)
+   120000230:	64210022 	daddiu	at,at,34
+   120000234:	0025082d 	daddu	at,at,a1
+   120000238:	88250000 	lwl	a1,0\(at\)
+   12000023c:	98250003 	lwr	a1,3\(at\)
+   120000240:	3c010000 	lui	at,0x0
+   120000244:	003c082d 	daddu	at,at,gp
+   120000248:	dc218058 	ld	at,-32680\(at\)
+   12000024c:	64210038 	daddiu	at,at,56
+   120000250:	0025082d 	daddu	at,at,a1
+   120000254:	a8250000 	swl	a1,0\(at\)
+   120000258:	b8250003 	swr	a1,3\(at\)
+   12000025c:	df858020 	ld	a1,-32736\(gp\)
+   120000260:	64a5071c 	daddiu	a1,a1,1820
+   120000264:	df858020 	ld	a1,-32736\(gp\)
+   120000268:	64a50728 	daddiu	a1,a1,1832
+   12000026c:	df858028 	ld	a1,-32728\(gp\)
+   120000270:	64a5e95c 	daddiu	a1,a1,-5796
+   120000274:	df858020 	ld	a1,-32736\(gp\)
+   120000278:	64a5071c 	daddiu	a1,a1,1820
+   12000027c:	00b1282d 	daddu	a1,a1,s1
+   120000280:	df858020 	ld	a1,-32736\(gp\)
+   120000284:	64a50728 	daddiu	a1,a1,1832
+   120000288:	00b1282d 	daddu	a1,a1,s1
+   12000028c:	df858028 	ld	a1,-32728\(gp\)
+   120000290:	64a5e95c 	daddiu	a1,a1,-5796
+   120000294:	00b1282d 	daddu	a1,a1,s1
+   120000298:	df858020 	ld	a1,-32736\(gp\)
+   12000029c:	dca5071c 	ld	a1,1820\(a1\)
+   1200002a0:	df858020 	ld	a1,-32736\(gp\)
+   1200002a4:	dca50728 	ld	a1,1832\(a1\)
+   1200002a8:	df858020 	ld	a1,-32736\(gp\)
+   1200002ac:	00b1282d 	daddu	a1,a1,s1
+   1200002b0:	dca5071c 	ld	a1,1820\(a1\)
+   1200002b4:	df858020 	ld	a1,-32736\(gp\)
+   1200002b8:	00b1282d 	daddu	a1,a1,s1
+   1200002bc:	dca50728 	ld	a1,1832\(a1\)
+   1200002c0:	df818020 	ld	at,-32736\(gp\)
+   1200002c4:	0025082d 	daddu	at,at,a1
+   1200002c8:	dc25073e 	ld	a1,1854\(at\)
+   1200002cc:	df818020 	ld	at,-32736\(gp\)
+   1200002d0:	0025082d 	daddu	at,at,a1
+   1200002d4:	fc250754 	sd	a1,1876\(at\)
+   1200002d8:	df818020 	ld	at,-32736\(gp\)
+   1200002dc:	6421071c 	daddiu	at,at,1820
+   1200002e0:	88250000 	lwl	a1,0\(at\)
+   1200002e4:	98250003 	lwr	a1,3\(at\)
+   1200002e8:	df818020 	ld	at,-32736\(gp\)
+   1200002ec:	64210728 	daddiu	at,at,1832
+   1200002f0:	88250000 	lwl	a1,0\(at\)
+   1200002f4:	98250003 	lwr	a1,3\(at\)
+   1200002f8:	df818020 	ld	at,-32736\(gp\)
+   1200002fc:	6421071c 	daddiu	at,at,1820
+   120000300:	0031082d 	daddu	at,at,s1
+   120000304:	88250000 	lwl	a1,0\(at\)
+   120000308:	98250003 	lwr	a1,3\(at\)
+   12000030c:	df818020 	ld	at,-32736\(gp\)
+   120000310:	64210728 	daddiu	at,at,1832
+   120000314:	0031082d 	daddu	at,at,s1
+   120000318:	88250000 	lwl	a1,0\(at\)
+   12000031c:	98250003 	lwr	a1,3\(at\)
+   120000320:	df818020 	ld	at,-32736\(gp\)
+   120000324:	6421073e 	daddiu	at,at,1854
+   120000328:	0025082d 	daddu	at,at,a1
+   12000032c:	88250000 	lwl	a1,0\(at\)
+   120000330:	98250003 	lwr	a1,3\(at\)
+   120000334:	df818020 	ld	at,-32736\(gp\)
+   120000338:	64210754 	daddiu	at,at,1876
+   12000033c:	0025082d 	daddu	at,at,a1
+   120000340:	a8250000 	swl	a1,0\(at\)
+   120000344:	b8250003 	swr	a1,3\(at\)
+   120000348:	3c050000 	lui	a1,0x0
+   12000034c:	00bc282d 	daddu	a1,a1,gp
+   120000350:	dca58048 	ld	a1,-32696\(a1\)
+   120000354:	df858030 	ld	a1,-32720\(gp\)
+   120000358:	64a500e0 	daddiu	a1,a1,224
+   12000035c:	3c190000 	lui	t9,0x0
+   120000360:	033cc82d 	daddu	t9,t9,gp
+   120000364:	df398048 	ld	t9,-32696\(t9\)
+   120000368:	df998030 	ld	t9,-32720\(gp\)
+   12000036c:	673900e0 	daddiu	t9,t9,224
+   120000370:	3c190000 	lui	t9,0x0
+   120000374:	033cc82d 	daddu	t9,t9,gp
+   120000378:	df398048 	ld	t9,-32696\(t9\)
+   12000037c:	0320f809 	jalr	t9
+   120000380:	00000000 	nop
+   120000384:	df998030 	ld	t9,-32720\(gp\)
+   120000388:	673900e0 	daddiu	t9,t9,224
+   12000038c:	0320f809 	jalr	t9
+   120000390:	00000000 	nop
+   120000394:	3c050000 	lui	a1,0x0
+   120000398:	00bc282d 	daddu	a1,a1,gp
+   12000039c:	dca58060 	ld	a1,-32672\(a1\)
+   1200003a0:	3c050000 	lui	a1,0x0
+   1200003a4:	00bc282d 	daddu	a1,a1,gp
+   1200003a8:	dca58060 	ld	a1,-32672\(a1\)
+   1200003ac:	64a5000c 	daddiu	a1,a1,12
+   1200003b0:	3c050000 	lui	a1,0x0
+   1200003b4:	00bc282d 	daddu	a1,a1,gp
+   1200003b8:	dca58060 	ld	a1,-32672\(a1\)
+   1200003bc:	3c010001 	lui	at,0x1
+   1200003c0:	3421e240 	ori	at,at,0xe240
+   1200003c4:	00a1282d 	daddu	a1,a1,at
+   1200003c8:	3c050000 	lui	a1,0x0
+   1200003cc:	00bc282d 	daddu	a1,a1,gp
+   1200003d0:	dca58060 	ld	a1,-32672\(a1\)
+   1200003d4:	00b1282d 	daddu	a1,a1,s1
+   1200003d8:	3c050000 	lui	a1,0x0
+   1200003dc:	00bc282d 	daddu	a1,a1,gp
+   1200003e0:	dca58060 	ld	a1,-32672\(a1\)
+   1200003e4:	64a5000c 	daddiu	a1,a1,12
+   1200003e8:	00b1282d 	daddu	a1,a1,s1
+   1200003ec:	3c050000 	lui	a1,0x0
+   1200003f0:	00bc282d 	daddu	a1,a1,gp
+   1200003f4:	dca58060 	ld	a1,-32672\(a1\)
+   1200003f8:	3c010001 	lui	at,0x1
+   1200003fc:	3421e240 	ori	at,at,0xe240
+   120000400:	00a1282d 	daddu	a1,a1,at
+   120000404:	00b1282d 	daddu	a1,a1,s1
+   120000408:	3c050000 	lui	a1,0x0
+   12000040c:	00bc282d 	daddu	a1,a1,gp
+   120000410:	dca58060 	ld	a1,-32672\(a1\)
+   120000414:	dca50000 	ld	a1,0\(a1\)
+   120000418:	3c050000 	lui	a1,0x0
+   12000041c:	00bc282d 	daddu	a1,a1,gp
+   120000420:	dca58060 	ld	a1,-32672\(a1\)
+   120000424:	dca5000c 	ld	a1,12\(a1\)
+   120000428:	3c050000 	lui	a1,0x0
+   12000042c:	00bc282d 	daddu	a1,a1,gp
+   120000430:	dca58060 	ld	a1,-32672\(a1\)
+   120000434:	00b1282d 	daddu	a1,a1,s1
+   120000438:	dca50000 	ld	a1,0\(a1\)
+   12000043c:	3c050000 	lui	a1,0x0
+   120000440:	00bc282d 	daddu	a1,a1,gp
+   120000444:	dca58060 	ld	a1,-32672\(a1\)
+   120000448:	00b1282d 	daddu	a1,a1,s1
+   12000044c:	dca5000c 	ld	a1,12\(a1\)
+   120000450:	3c010000 	lui	at,0x0
+   120000454:	003c082d 	daddu	at,at,gp
+   120000458:	dc218060 	ld	at,-32672\(at\)
+   12000045c:	0025082d 	daddu	at,at,a1
+   120000460:	dc250022 	ld	a1,34\(at\)
+   120000464:	3c010000 	lui	at,0x0
+   120000468:	003c082d 	daddu	at,at,gp
+   12000046c:	dc218060 	ld	at,-32672\(at\)
+   120000470:	0025082d 	daddu	at,at,a1
+   120000474:	fc250038 	sd	a1,56\(at\)
+   120000478:	3c010000 	lui	at,0x0
+   12000047c:	003c082d 	daddu	at,at,gp
+   120000480:	dc218060 	ld	at,-32672\(at\)
+   120000484:	88250000 	lwl	a1,0\(at\)
+   120000488:	98250003 	lwr	a1,3\(at\)
+   12000048c:	3c010000 	lui	at,0x0
+   120000490:	003c082d 	daddu	at,at,gp
+   120000494:	dc218060 	ld	at,-32672\(at\)
+   120000498:	6421000c 	daddiu	at,at,12
+   12000049c:	88250000 	lwl	a1,0\(at\)
+   1200004a0:	98250003 	lwr	a1,3\(at\)
+   1200004a4:	3c010000 	lui	at,0x0
+   1200004a8:	003c082d 	daddu	at,at,gp
+   1200004ac:	dc218060 	ld	at,-32672\(at\)
+   1200004b0:	0031082d 	daddu	at,at,s1
+   1200004b4:	88250000 	lwl	a1,0\(at\)
+   1200004b8:	98250003 	lwr	a1,3\(at\)
+   1200004bc:	3c010000 	lui	at,0x0
+   1200004c0:	003c082d 	daddu	at,at,gp
+   1200004c4:	dc218060 	ld	at,-32672\(at\)
+   1200004c8:	6421000c 	daddiu	at,at,12
+   1200004cc:	0031082d 	daddu	at,at,s1
+   1200004d0:	88250000 	lwl	a1,0\(at\)
+   1200004d4:	98250003 	lwr	a1,3\(at\)
+   1200004d8:	3c010000 	lui	at,0x0
+   1200004dc:	003c082d 	daddu	at,at,gp
+   1200004e0:	dc218060 	ld	at,-32672\(at\)
+   1200004e4:	64210022 	daddiu	at,at,34
+   1200004e8:	0025082d 	daddu	at,at,a1
+   1200004ec:	88250000 	lwl	a1,0\(at\)
+   1200004f0:	98250003 	lwr	a1,3\(at\)
+   1200004f4:	3c010000 	lui	at,0x0
+   1200004f8:	003c082d 	daddu	at,at,gp
+   1200004fc:	dc218060 	ld	at,-32672\(at\)
+   120000500:	64210038 	daddiu	at,at,56
+   120000504:	0025082d 	daddu	at,at,a1
+   120000508:	a8250000 	swl	a1,0\(at\)
+   12000050c:	b8250003 	swr	a1,3\(at\)
+   120000510:	df858020 	ld	a1,-32736\(gp\)
+   120000514:	64a50794 	daddiu	a1,a1,1940
+   120000518:	df858020 	ld	a1,-32736\(gp\)
+   12000051c:	64a507a0 	daddiu	a1,a1,1952
+   120000520:	df858028 	ld	a1,-32728\(gp\)
+   120000524:	64a5e9d4 	daddiu	a1,a1,-5676
+   120000528:	df858020 	ld	a1,-32736\(gp\)
+   12000052c:	64a50794 	daddiu	a1,a1,1940
+   120000530:	00b1282d 	daddu	a1,a1,s1
+   120000534:	df858020 	ld	a1,-32736\(gp\)
+   120000538:	64a507a0 	daddiu	a1,a1,1952
+   12000053c:	00b1282d 	daddu	a1,a1,s1
+   120000540:	df858028 	ld	a1,-32728\(gp\)
+   120000544:	64a5e9d4 	daddiu	a1,a1,-5676
+   120000548:	00b1282d 	daddu	a1,a1,s1
+   12000054c:	df858020 	ld	a1,-32736\(gp\)
+   120000550:	dca50794 	ld	a1,1940\(a1\)
+   120000554:	df858020 	ld	a1,-32736\(gp\)
+   120000558:	dca507a0 	ld	a1,1952\(a1\)
+   12000055c:	df858020 	ld	a1,-32736\(gp\)
+   120000560:	00b1282d 	daddu	a1,a1,s1
+   120000564:	dca50794 	ld	a1,1940\(a1\)
+   120000568:	df858020 	ld	a1,-32736\(gp\)
+   12000056c:	00b1282d 	daddu	a1,a1,s1
+   120000570:	dca507a0 	ld	a1,1952\(a1\)
+   120000574:	df818020 	ld	at,-32736\(gp\)
+   120000578:	0025082d 	daddu	at,at,a1
+   12000057c:	dc2507b6 	ld	a1,1974\(at\)
+   120000580:	df818020 	ld	at,-32736\(gp\)
+   120000584:	0025082d 	daddu	at,at,a1
+   120000588:	fc2507cc 	sd	a1,1996\(at\)
+   12000058c:	df818020 	ld	at,-32736\(gp\)
+   120000590:	64210794 	daddiu	at,at,1940
+   120000594:	88250000 	lwl	a1,0\(at\)
+   120000598:	98250003 	lwr	a1,3\(at\)
+   12000059c:	df818020 	ld	at,-32736\(gp\)
+   1200005a0:	642107a0 	daddiu	at,at,1952
+   1200005a4:	88250000 	lwl	a1,0\(at\)
+   1200005a8:	98250003 	lwr	a1,3\(at\)
+   1200005ac:	df818020 	ld	at,-32736\(gp\)
+   1200005b0:	64210794 	daddiu	at,at,1940
+   1200005b4:	0031082d 	daddu	at,at,s1
+   1200005b8:	88250000 	lwl	a1,0\(at\)
+   1200005bc:	98250003 	lwr	a1,3\(at\)
+   1200005c0:	df818020 	ld	at,-32736\(gp\)
+   1200005c4:	642107a0 	daddiu	at,at,1952
+   1200005c8:	0031082d 	daddu	at,at,s1
+   1200005cc:	88250000 	lwl	a1,0\(at\)
+   1200005d0:	98250003 	lwr	a1,3\(at\)
+   1200005d4:	df818020 	ld	at,-32736\(gp\)
+   1200005d8:	642107b6 	daddiu	at,at,1974
+   1200005dc:	0025082d 	daddu	at,at,a1
+   1200005e0:	88250000 	lwl	a1,0\(at\)
+   1200005e4:	98250003 	lwr	a1,3\(at\)
+   1200005e8:	df818020 	ld	at,-32736\(gp\)
+   1200005ec:	642107cc 	daddiu	at,at,1996
+   1200005f0:	0025082d 	daddu	at,at,a1
+   1200005f4:	a8250000 	swl	a1,0\(at\)
+   1200005f8:	b8250003 	swr	a1,3\(at\)
+   1200005fc:	3c050000 	lui	a1,0x0
+   120000600:	00bc282d 	daddu	a1,a1,gp
+   120000604:	dca58050 	ld	a1,-32688\(a1\)
+   120000608:	df858030 	ld	a1,-32720\(gp\)
+   12000060c:	64a506e0 	daddiu	a1,a1,1760
+   120000610:	3c190000 	lui	t9,0x0
+   120000614:	033cc82d 	daddu	t9,t9,gp
+   120000618:	df398050 	ld	t9,-32688\(t9\)
+   12000061c:	df998030 	ld	t9,-32720\(gp\)
+   120000620:	673906e0 	daddiu	t9,t9,1760
+   120000624:	3c190000 	lui	t9,0x0
+   120000628:	033cc82d 	daddu	t9,t9,gp
+   12000062c:	df398050 	ld	t9,-32688\(t9\)
+   120000630:	0320f809 	jalr	t9
+   120000634:	00000000 	nop
+   120000638:	df998030 	ld	t9,-32720\(gp\)
+   12000063c:	673906e0 	daddiu	t9,t9,1760
+   120000640:	0320f809 	jalr	t9
+   120000644:	00000000 	nop
+   120000648:	3c050000 	lui	a1,0x0
+   12000064c:	00bc282d 	daddu	a1,a1,gp
+   120000650:	dca58058 	ld	a1,-32680\(a1\)
+   120000654:	1000fea2 	b	1200000e0 <fn>
+   120000658:	00000000 	nop
+   12000065c:	3c050000 	lui	a1,0x0
+   120000660:	00bc282d 	daddu	a1,a1,gp
+   120000664:	dca58060 	ld	a1,-32672\(a1\)
+   120000668:	dca50000 	ld	a1,0\(a1\)
+   12000066c:	1000001c 	b	1200006e0 <fn2>
+   120000670:	00000000 	nop
+   120000674:	df858020 	ld	a1,-32736\(gp\)
+   120000678:	64a5071c 	daddiu	a1,a1,1820
+   12000067c:	1000fe98 	b	1200000e0 <fn>
+   120000680:	00000000 	nop
+   120000684:	df858020 	ld	a1,-32736\(gp\)
+   120000688:	64a507a0 	daddiu	a1,a1,1952
+   12000068c:	10000014 	b	1200006e0 <fn2>
+   120000690:	00000000 	nop
+   120000694:	df858028 	ld	a1,-32728\(gp\)
+   120000698:	64a5e95c 	daddiu	a1,a1,-5796
+   12000069c:	1000fe90 	b	1200000e0 <fn>
+   1200006a0:	00000000 	nop
+   1200006a4:	df858020 	ld	a1,-32736\(gp\)
+   1200006a8:	dca50794 	ld	a1,1940\(a1\)
+   1200006ac:	1000000c 	b	1200006e0 <fn2>
+   1200006b0:	00000000 	nop
+   1200006b4:	df858020 	ld	a1,-32736\(gp\)
+   1200006b8:	dca50728 	ld	a1,1832\(a1\)
+   1200006bc:	1000fe88 	b	1200000e0 <fn>
+   1200006c0:	00000000 	nop
+   1200006c4:	df818020 	ld	at,-32736\(gp\)
+   1200006c8:	0025082d 	daddu	at,at,a1
+   1200006cc:	dc2507b6 	ld	a1,1974\(at\)
+   1200006d0:	10000003 	b	1200006e0 <fn2>
+   1200006d4:	00000000 	nop
+	\.\.\.
+Disassembly of section \.data:
+
+00000001200106e0 <_fdata>:
+	\.\.\.
+
+000000012001071c <dg1>:
+	\.\.\.
+
+0000000120010758 <sp2>:
+	\.\.\.
+
+0000000120010794 <dg2>:
+	\.\.\.
+Disassembly of section \.got:
+
+00000001200107d0 <_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+   1200107d8:	80000000 	.*
+   1200107dc:	00000000 	.*
+   1200107e0:	00000001 	.*
+   1200107e4:	20010000 	.*
+   1200107e8:	00000001 	.*
+   1200107ec:	20030000 	.*
+   1200107f0:	00000001 	.*
+   1200107f4:	20000000 	.*
+	\.\.\.
+   120010808:	00000001 	.*
+   12001080c:	200000e0 	.*
+   120010810:	00000001 	.*
+   120010814:	200006e0 	.*
+   120010818:	00000001 	.*
+   12001081c:	2001071c 	.*
+   120010820:	00000001 	.*
+   120010824:	20010794 	.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d b/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d
new file mode 100644
index 0000000..0111f78
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d
@@ -0,0 +1,436 @@
+#name: MIPS ELF xgot reloc n64
+#as: -EB -64 -KPIC -xgot
+#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s
+#ld: -melf64btsmip
+#objdump: -D --show-raw-insn
+
+.*: +file format elf64-.*mips.*
+
+Disassembly of section \.MIPS\.options:
+
+00000000100000b0 <\.MIPS\.options>:
+    100000b0:	01280000 	.*
+    100000b4:	00000000 	.*
+    100000b8:	92020022 	.*
+	\.\.\.
+    100000d4:	101087c0 	.*
+Disassembly of section \.text:
+
+00000000100000e0 <fn>:
+    100000e0:	3c050000 	lui	a1,0x0
+    100000e4:	00bc282d 	daddu	a1,a1,gp
+    100000e8:	dca58058 	ld	a1,-32680\(a1\)
+    100000ec:	3c050000 	lui	a1,0x0
+    100000f0:	00bc282d 	daddu	a1,a1,gp
+    100000f4:	dca58058 	ld	a1,-32680\(a1\)
+    100000f8:	64a5000c 	daddiu	a1,a1,12
+    100000fc:	3c050000 	lui	a1,0x0
+    10000100:	00bc282d 	daddu	a1,a1,gp
+    10000104:	dca58058 	ld	a1,-32680\(a1\)
+    10000108:	3c010002 	lui	at,0x2
+    1000010c:	6421e240 	daddiu	at,at,-7616
+    10000110:	00a1282d 	daddu	a1,a1,at
+    10000114:	3c050000 	lui	a1,0x0
+    10000118:	00bc282d 	daddu	a1,a1,gp
+    1000011c:	dca58058 	ld	a1,-32680\(a1\)
+    10000120:	00b1282d 	daddu	a1,a1,s1
+    10000124:	3c050000 	lui	a1,0x0
+    10000128:	00bc282d 	daddu	a1,a1,gp
+    1000012c:	dca58058 	ld	a1,-32680\(a1\)
+    10000130:	64a5000c 	daddiu	a1,a1,12
+    10000134:	00b1282d 	daddu	a1,a1,s1
+    10000138:	3c050000 	lui	a1,0x0
+    1000013c:	00bc282d 	daddu	a1,a1,gp
+    10000140:	dca58058 	ld	a1,-32680\(a1\)
+    10000144:	3c010002 	lui	at,0x2
+    10000148:	6421e240 	daddiu	at,at,-7616
+    1000014c:	00a1282d 	daddu	a1,a1,at
+    10000150:	00b1282d 	daddu	a1,a1,s1
+    10000154:	3c050000 	lui	a1,0x0
+    10000158:	00bc282d 	daddu	a1,a1,gp
+    1000015c:	dca58058 	ld	a1,-32680\(a1\)
+    10000160:	dca50000 	ld	a1,0\(a1\)
+    10000164:	3c050000 	lui	a1,0x0
+    10000168:	00bc282d 	daddu	a1,a1,gp
+    1000016c:	dca58058 	ld	a1,-32680\(a1\)
+    10000170:	dca5000c 	ld	a1,12\(a1\)
+    10000174:	3c050000 	lui	a1,0x0
+    10000178:	00bc282d 	daddu	a1,a1,gp
+    1000017c:	dca58058 	ld	a1,-32680\(a1\)
+    10000180:	00b1282d 	daddu	a1,a1,s1
+    10000184:	dca50000 	ld	a1,0\(a1\)
+    10000188:	3c050000 	lui	a1,0x0
+    1000018c:	00bc282d 	daddu	a1,a1,gp
+    10000190:	dca58058 	ld	a1,-32680\(a1\)
+    10000194:	00b1282d 	daddu	a1,a1,s1
+    10000198:	dca5000c 	ld	a1,12\(a1\)
+    1000019c:	3c010000 	lui	at,0x0
+    100001a0:	003c082d 	daddu	at,at,gp
+    100001a4:	dc218058 	ld	at,-32680\(at\)
+    100001a8:	0025082d 	daddu	at,at,a1
+    100001ac:	dc250022 	ld	a1,34\(at\)
+    100001b0:	3c010000 	lui	at,0x0
+    100001b4:	003c082d 	daddu	at,at,gp
+    100001b8:	dc218058 	ld	at,-32680\(at\)
+    100001bc:	0025082d 	daddu	at,at,a1
+    100001c0:	fc250038 	sd	a1,56\(at\)
+    100001c4:	3c010000 	lui	at,0x0
+    100001c8:	003c082d 	daddu	at,at,gp
+    100001cc:	dc218058 	ld	at,-32680\(at\)
+    100001d0:	88250000 	lwl	a1,0\(at\)
+    100001d4:	98250003 	lwr	a1,3\(at\)
+    100001d8:	3c010000 	lui	at,0x0
+    100001dc:	003c082d 	daddu	at,at,gp
+    100001e0:	dc218058 	ld	at,-32680\(at\)
+    100001e4:	6421000c 	daddiu	at,at,12
+    100001e8:	88250000 	lwl	a1,0\(at\)
+    100001ec:	98250003 	lwr	a1,3\(at\)
+    100001f0:	3c010000 	lui	at,0x0
+    100001f4:	003c082d 	daddu	at,at,gp
+    100001f8:	dc218058 	ld	at,-32680\(at\)
+    100001fc:	0031082d 	daddu	at,at,s1
+    10000200:	88250000 	lwl	a1,0\(at\)
+    10000204:	98250003 	lwr	a1,3\(at\)
+    10000208:	3c010000 	lui	at,0x0
+    1000020c:	003c082d 	daddu	at,at,gp
+    10000210:	dc218058 	ld	at,-32680\(at\)
+    10000214:	6421000c 	daddiu	at,at,12
+    10000218:	0031082d 	daddu	at,at,s1
+    1000021c:	88250000 	lwl	a1,0\(at\)
+    10000220:	98250003 	lwr	a1,3\(at\)
+    10000224:	3c010000 	lui	at,0x0
+    10000228:	003c082d 	daddu	at,at,gp
+    1000022c:	dc218058 	ld	at,-32680\(at\)
+    10000230:	64210022 	daddiu	at,at,34
+    10000234:	0025082d 	daddu	at,at,a1
+    10000238:	88250000 	lwl	a1,0\(at\)
+    1000023c:	98250003 	lwr	a1,3\(at\)
+    10000240:	3c010000 	lui	at,0x0
+    10000244:	003c082d 	daddu	at,at,gp
+    10000248:	dc218058 	ld	at,-32680\(at\)
+    1000024c:	64210038 	daddiu	at,at,56
+    10000250:	0025082d 	daddu	at,at,a1
+    10000254:	a8250000 	swl	a1,0\(at\)
+    10000258:	b8250003 	swr	a1,3\(at\)
+    1000025c:	df858020 	ld	a1,-32736\(gp\)
+    10000260:	64a5071c 	daddiu	a1,a1,1820
+    10000264:	df858020 	ld	a1,-32736\(gp\)
+    10000268:	64a50728 	daddiu	a1,a1,1832
+    1000026c:	df858028 	ld	a1,-32728\(gp\)
+    10000270:	64a5e95c 	daddiu	a1,a1,-5796
+    10000274:	df858020 	ld	a1,-32736\(gp\)
+    10000278:	64a5071c 	daddiu	a1,a1,1820
+    1000027c:	00b1282d 	daddu	a1,a1,s1
+    10000280:	df858020 	ld	a1,-32736\(gp\)
+    10000284:	64a50728 	daddiu	a1,a1,1832
+    10000288:	00b1282d 	daddu	a1,a1,s1
+    1000028c:	df858028 	ld	a1,-32728\(gp\)
+    10000290:	64a5e95c 	daddiu	a1,a1,-5796
+    10000294:	00b1282d 	daddu	a1,a1,s1
+    10000298:	df858020 	ld	a1,-32736\(gp\)
+    1000029c:	dca5071c 	ld	a1,1820\(a1\)
+    100002a0:	df858020 	ld	a1,-32736\(gp\)
+    100002a4:	dca50728 	ld	a1,1832\(a1\)
+    100002a8:	df858020 	ld	a1,-32736\(gp\)
+    100002ac:	00b1282d 	daddu	a1,a1,s1
+    100002b0:	dca5071c 	ld	a1,1820\(a1\)
+    100002b4:	df858020 	ld	a1,-32736\(gp\)
+    100002b8:	00b1282d 	daddu	a1,a1,s1
+    100002bc:	dca50728 	ld	a1,1832\(a1\)
+    100002c0:	df818020 	ld	at,-32736\(gp\)
+    100002c4:	0025082d 	daddu	at,at,a1
+    100002c8:	dc25073e 	ld	a1,1854\(at\)
+    100002cc:	df818020 	ld	at,-32736\(gp\)
+    100002d0:	0025082d 	daddu	at,at,a1
+    100002d4:	fc250754 	sd	a1,1876\(at\)
+    100002d8:	df818020 	ld	at,-32736\(gp\)
+    100002dc:	6421071c 	daddiu	at,at,1820
+    100002e0:	88250000 	lwl	a1,0\(at\)
+    100002e4:	98250003 	lwr	a1,3\(at\)
+    100002e8:	df818020 	ld	at,-32736\(gp\)
+    100002ec:	64210728 	daddiu	at,at,1832
+    100002f0:	88250000 	lwl	a1,0\(at\)
+    100002f4:	98250003 	lwr	a1,3\(at\)
+    100002f8:	df818020 	ld	at,-32736\(gp\)
+    100002fc:	6421071c 	daddiu	at,at,1820
+    10000300:	0031082d 	daddu	at,at,s1
+    10000304:	88250000 	lwl	a1,0\(at\)
+    10000308:	98250003 	lwr	a1,3\(at\)
+    1000030c:	df818020 	ld	at,-32736\(gp\)
+    10000310:	64210728 	daddiu	at,at,1832
+    10000314:	0031082d 	daddu	at,at,s1
+    10000318:	88250000 	lwl	a1,0\(at\)
+    1000031c:	98250003 	lwr	a1,3\(at\)
+    10000320:	df818020 	ld	at,-32736\(gp\)
+    10000324:	6421073e 	daddiu	at,at,1854
+    10000328:	0025082d 	daddu	at,at,a1
+    1000032c:	88250000 	lwl	a1,0\(at\)
+    10000330:	98250003 	lwr	a1,3\(at\)
+    10000334:	df818020 	ld	at,-32736\(gp\)
+    10000338:	64210754 	daddiu	at,at,1876
+    1000033c:	0025082d 	daddu	at,at,a1
+    10000340:	a8250000 	swl	a1,0\(at\)
+    10000344:	b8250003 	swr	a1,3\(at\)
+    10000348:	3c050000 	lui	a1,0x0
+    1000034c:	00bc282d 	daddu	a1,a1,gp
+    10000350:	dca58048 	ld	a1,-32696\(a1\)
+    10000354:	df858030 	ld	a1,-32720\(gp\)
+    10000358:	64a500e0 	daddiu	a1,a1,224
+    1000035c:	3c190000 	lui	t9,0x0
+    10000360:	033cc82d 	daddu	t9,t9,gp
+    10000364:	df398048 	ld	t9,-32696\(t9\)
+    10000368:	df998030 	ld	t9,-32720\(gp\)
+    1000036c:	673900e0 	daddiu	t9,t9,224
+    10000370:	3c190000 	lui	t9,0x0
+    10000374:	033cc82d 	daddu	t9,t9,gp
+    10000378:	df398048 	ld	t9,-32696\(t9\)
+    1000037c:	0320f809 	jalr	t9
+    10000380:	00000000 	nop
+    10000384:	df998030 	ld	t9,-32720\(gp\)
+    10000388:	673900e0 	daddiu	t9,t9,224
+    1000038c:	0320f809 	jalr	t9
+    10000390:	00000000 	nop
+    10000394:	3c050000 	lui	a1,0x0
+    10000398:	00bc282d 	daddu	a1,a1,gp
+    1000039c:	dca58060 	ld	a1,-32672\(a1\)
+    100003a0:	3c050000 	lui	a1,0x0
+    100003a4:	00bc282d 	daddu	a1,a1,gp
+    100003a8:	dca58060 	ld	a1,-32672\(a1\)
+    100003ac:	64a5000c 	daddiu	a1,a1,12
+    100003b0:	3c050000 	lui	a1,0x0
+    100003b4:	00bc282d 	daddu	a1,a1,gp
+    100003b8:	dca58060 	ld	a1,-32672\(a1\)
+    100003bc:	3c010002 	lui	at,0x2
+    100003c0:	6421e240 	daddiu	at,at,-7616
+    100003c4:	00a1282d 	daddu	a1,a1,at
+    100003c8:	3c050000 	lui	a1,0x0
+    100003cc:	00bc282d 	daddu	a1,a1,gp
+    100003d0:	dca58060 	ld	a1,-32672\(a1\)
+    100003d4:	00b1282d 	daddu	a1,a1,s1
+    100003d8:	3c050000 	lui	a1,0x0
+    100003dc:	00bc282d 	daddu	a1,a1,gp
+    100003e0:	dca58060 	ld	a1,-32672\(a1\)
+    100003e4:	64a5000c 	daddiu	a1,a1,12
+    100003e8:	00b1282d 	daddu	a1,a1,s1
+    100003ec:	3c050000 	lui	a1,0x0
+    100003f0:	00bc282d 	daddu	a1,a1,gp
+    100003f4:	dca58060 	ld	a1,-32672\(a1\)
+    100003f8:	3c010002 	lui	at,0x2
+    100003fc:	6421e240 	daddiu	at,at,-7616
+    10000400:	00a1282d 	daddu	a1,a1,at
+    10000404:	00b1282d 	daddu	a1,a1,s1
+    10000408:	3c050000 	lui	a1,0x0
+    1000040c:	00bc282d 	daddu	a1,a1,gp
+    10000410:	dca58060 	ld	a1,-32672\(a1\)
+    10000414:	dca50000 	ld	a1,0\(a1\)
+    10000418:	3c050000 	lui	a1,0x0
+    1000041c:	00bc282d 	daddu	a1,a1,gp
+    10000420:	dca58060 	ld	a1,-32672\(a1\)
+    10000424:	dca5000c 	ld	a1,12\(a1\)
+    10000428:	3c050000 	lui	a1,0x0
+    1000042c:	00bc282d 	daddu	a1,a1,gp
+    10000430:	dca58060 	ld	a1,-32672\(a1\)
+    10000434:	00b1282d 	daddu	a1,a1,s1
+    10000438:	dca50000 	ld	a1,0\(a1\)
+    1000043c:	3c050000 	lui	a1,0x0
+    10000440:	00bc282d 	daddu	a1,a1,gp
+    10000444:	dca58060 	ld	a1,-32672\(a1\)
+    10000448:	00b1282d 	daddu	a1,a1,s1
+    1000044c:	dca5000c 	ld	a1,12\(a1\)
+    10000450:	3c010000 	lui	at,0x0
+    10000454:	003c082d 	daddu	at,at,gp
+    10000458:	dc218060 	ld	at,-32672\(at\)
+    1000045c:	0025082d 	daddu	at,at,a1
+    10000460:	dc250022 	ld	a1,34\(at\)
+    10000464:	3c010000 	lui	at,0x0
+    10000468:	003c082d 	daddu	at,at,gp
+    1000046c:	dc218060 	ld	at,-32672\(at\)
+    10000470:	0025082d 	daddu	at,at,a1
+    10000474:	fc250038 	sd	a1,56\(at\)
+    10000478:	3c010000 	lui	at,0x0
+    1000047c:	003c082d 	daddu	at,at,gp
+    10000480:	dc218060 	ld	at,-32672\(at\)
+    10000484:	88250000 	lwl	a1,0\(at\)
+    10000488:	98250003 	lwr	a1,3\(at\)
+    1000048c:	3c010000 	lui	at,0x0
+    10000490:	003c082d 	daddu	at,at,gp
+    10000494:	dc218060 	ld	at,-32672\(at\)
+    10000498:	6421000c 	daddiu	at,at,12
+    1000049c:	88250000 	lwl	a1,0\(at\)
+    100004a0:	98250003 	lwr	a1,3\(at\)
+    100004a4:	3c010000 	lui	at,0x0
+    100004a8:	003c082d 	daddu	at,at,gp
+    100004ac:	dc218060 	ld	at,-32672\(at\)
+    100004b0:	0031082d 	daddu	at,at,s1
+    100004b4:	88250000 	lwl	a1,0\(at\)
+    100004b8:	98250003 	lwr	a1,3\(at\)
+    100004bc:	3c010000 	lui	at,0x0
+    100004c0:	003c082d 	daddu	at,at,gp
+    100004c4:	dc218060 	ld	at,-32672\(at\)
+    100004c8:	6421000c 	daddiu	at,at,12
+    100004cc:	0031082d 	daddu	at,at,s1
+    100004d0:	88250000 	lwl	a1,0\(at\)
+    100004d4:	98250003 	lwr	a1,3\(at\)
+    100004d8:	3c010000 	lui	at,0x0
+    100004dc:	003c082d 	daddu	at,at,gp
+    100004e0:	dc218060 	ld	at,-32672\(at\)
+    100004e4:	64210022 	daddiu	at,at,34
+    100004e8:	0025082d 	daddu	at,at,a1
+    100004ec:	88250000 	lwl	a1,0\(at\)
+    100004f0:	98250003 	lwr	a1,3\(at\)
+    100004f4:	3c010000 	lui	at,0x0
+    100004f8:	003c082d 	daddu	at,at,gp
+    100004fc:	dc218060 	ld	at,-32672\(at\)
+    10000500:	64210038 	daddiu	at,at,56
+    10000504:	0025082d 	daddu	at,at,a1
+    10000508:	a8250000 	swl	a1,0\(at\)
+    1000050c:	b8250003 	swr	a1,3\(at\)
+    10000510:	df858020 	ld	a1,-32736\(gp\)
+    10000514:	64a50794 	daddiu	a1,a1,1940
+    10000518:	df858020 	ld	a1,-32736\(gp\)
+    1000051c:	64a507a0 	daddiu	a1,a1,1952
+    10000520:	df858028 	ld	a1,-32728\(gp\)
+    10000524:	64a5e9d4 	daddiu	a1,a1,-5676
+    10000528:	df858020 	ld	a1,-32736\(gp\)
+    1000052c:	64a50794 	daddiu	a1,a1,1940
+    10000530:	00b1282d 	daddu	a1,a1,s1
+    10000534:	df858020 	ld	a1,-32736\(gp\)
+    10000538:	64a507a0 	daddiu	a1,a1,1952
+    1000053c:	00b1282d 	daddu	a1,a1,s1
+    10000540:	df858028 	ld	a1,-32728\(gp\)
+    10000544:	64a5e9d4 	daddiu	a1,a1,-5676
+    10000548:	00b1282d 	daddu	a1,a1,s1
+    1000054c:	df858020 	ld	a1,-32736\(gp\)
+    10000550:	dca50794 	ld	a1,1940\(a1\)
+    10000554:	df858020 	ld	a1,-32736\(gp\)
+    10000558:	dca507a0 	ld	a1,1952\(a1\)
+    1000055c:	df858020 	ld	a1,-32736\(gp\)
+    10000560:	00b1282d 	daddu	a1,a1,s1
+    10000564:	dca50794 	ld	a1,1940\(a1\)
+    10000568:	df858020 	ld	a1,-32736\(gp\)
+    1000056c:	00b1282d 	daddu	a1,a1,s1
+    10000570:	dca507a0 	ld	a1,1952\(a1\)
+    10000574:	df818020 	ld	at,-32736\(gp\)
+    10000578:	0025082d 	daddu	at,at,a1
+    1000057c:	dc250794 	ld	a1,1940\(at\)
+    10000580:	df818020 	ld	at,-32736\(gp\)
+    10000584:	0025082d 	daddu	at,at,a1
+    10000588:	fc2507cc 	sd	a1,1996\(at\)
+    1000058c:	df818020 	ld	at,-32736\(gp\)
+    10000590:	64210794 	daddiu	at,at,1940
+    10000594:	88250000 	lwl	a1,0\(at\)
+    10000598:	98250003 	lwr	a1,3\(at\)
+    1000059c:	df818020 	ld	at,-32736\(gp\)
+    100005a0:	642107a0 	daddiu	at,at,1952
+    100005a4:	88250000 	lwl	a1,0\(at\)
+    100005a8:	98250003 	lwr	a1,3\(at\)
+    100005ac:	df818020 	ld	at,-32736\(gp\)
+    100005b0:	64210794 	daddiu	at,at,1940
+    100005b4:	0031082d 	daddu	at,at,s1
+    100005b8:	88250000 	lwl	a1,0\(at\)
+    100005bc:	98250003 	lwr	a1,3\(at\)
+    100005c0:	df818020 	ld	at,-32736\(gp\)
+    100005c4:	642107a0 	daddiu	at,at,1952
+    100005c8:	0031082d 	daddu	at,at,s1
+    100005cc:	88250000 	lwl	a1,0\(at\)
+    100005d0:	98250003 	lwr	a1,3\(at\)
+    100005d4:	df818020 	ld	at,-32736\(gp\)
+    100005d8:	642107b6 	daddiu	at,at,1974
+    100005dc:	0025082d 	daddu	at,at,a1
+    100005e0:	88250000 	lwl	a1,0\(at\)
+    100005e4:	98250003 	lwr	a1,3\(at\)
+    100005e8:	df818020 	ld	at,-32736\(gp\)
+    100005ec:	642107cc 	daddiu	at,at,1996
+    100005f0:	0025082d 	daddu	at,at,a1
+    100005f4:	a8250000 	swl	a1,0\(at\)
+    100005f8:	b8250003 	swr	a1,3\(at\)
+    100005fc:	3c050000 	lui	a1,0x0
+    10000600:	00bc282d 	daddu	a1,a1,gp
+    10000604:	dca58050 	ld	a1,-32688\(a1\)
+    10000608:	df858030 	ld	a1,-32720\(gp\)
+    1000060c:	64a506e0 	daddiu	a1,a1,1760
+    10000610:	3c190000 	lui	t9,0x0
+    10000614:	033cc82d 	daddu	t9,t9,gp
+    10000618:	df398050 	ld	t9,-32688\(t9\)
+    1000061c:	df998030 	ld	t9,-32720\(gp\)
+    10000620:	673906e0 	daddiu	t9,t9,1760
+    10000624:	3c190000 	lui	t9,0x0
+    10000628:	033cc82d 	daddu	t9,t9,gp
+    1000062c:	df398050 	ld	t9,-32688\(t9\)
+    10000630:	0320f809 	jalr	t9
+    10000634:	00000000 	nop
+    10000638:	df998030 	ld	t9,-32720\(gp\)
+    1000063c:	673906e0 	daddiu	t9,t9,1760
+    10000640:	0320f809 	jalr	t9
+    10000644:	00000000 	nop
+    10000648:	3c050000 	lui	a1,0x0
+    1000064c:	00bc282d 	daddu	a1,a1,gp
+    10000650:	dca58058 	ld	a1,-32680\(a1\)
+    10000654:	1000fea2 	b	100000e0 <fn>
+    10000658:	00000000 	nop
+    1000065c:	3c050000 	lui	a1,0x0
+    10000660:	00bc282d 	daddu	a1,a1,gp
+    10000664:	dca58060 	ld	a1,-32672\(a1\)
+    10000668:	dca50000 	ld	a1,0\(a1\)
+    1000066c:	1000001c 	b	100006e0 <fn2>
+    10000670:	00000000 	nop
+    10000674:	df858020 	ld	a1,-32736\(gp\)
+    10000678:	64a5071c 	daddiu	a1,a1,1820
+    1000067c:	1000fe98 	b	100000e0 <fn>
+    10000680:	00000000 	nop
+    10000684:	df858020 	ld	a1,-32736\(gp\)
+    10000688:	64a507a0 	daddiu	a1,a1,1952
+    1000068c:	10000014 	b	100006e0 <fn2>
+    10000690:	00000000 	nop
+    10000694:	df858028 	ld	a1,-32728\(gp\)
+    10000698:	64a5e95c 	daddiu	a1,a1,-5796
+    1000069c:	1000fe90 	b	100000e0 <fn>
+    100006a0:	00000000 	nop
+    100006a4:	df858020 	ld	a1,-32736\(gp\)
+    100006a8:	dca50794 	ld	a1,1940\(a1\)
+    100006ac:	1000000c 	b	100006e0 <fn2>
+    100006b0:	00000000 	nop
+    100006b4:	df858020 	ld	a1,-32736\(gp\)
+    100006b8:	dca50728 	ld	a1,1832\(a1\)
+    100006bc:	1000fe88 	b	100000e0 <fn>
+    100006c0:	00000000 	nop
+    100006c4:	df818020 	ld	at,-32736\(gp\)
+    100006c8:	0025082d 	daddu	at,at,a1
+    100006cc:	dc2507b6 	ld	a1,1974\(at\)
+    100006d0:	10000003 	b	100006e0 <fn2>
+    100006d4:	00000000 	nop
+	\.\.\.
+Disassembly of section \.data:
+
+00000000101006e0 <_fdata>:
+	\.\.\.
+
+000000001010071c <dg1>:
+	\.\.\.
+
+0000000010100758 <sp2>:
+	\.\.\.
+
+0000000010100794 <dg2>:
+	\.\.\.
+Disassembly of section \.got:
+
+00000000101007d0 <_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+    101007d8:	80000000 	.*
+    101007dc:	00000000 	.*
+    101007e0:	00000000 	.*
+    101007e4:	10100000 	.*
+    101007e8:	00000000 	.*
+    101007ec:	10120000 	.*
+    101007f0:	00000000 	.*
+    101007f4:	10000000 	.*
+    101007f8:	00000000 	.*
+	\.\.\.
+    1010080c:	100000e0 	.*
+    10100810:	00000000 	.*
+    10100814:	100006e0 	.*
+    10100818:	00000000 	.*
+    1010081c:	1010071c 	.*
+    10100820:	00000000 	.*
+    10100824:	10100794 	.*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/emit-relocs-1.d b/binutils-2.19/ld/testsuite/ld-mips-elf/emit-relocs-1.d
new file mode 100644
index 0000000..520d401
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/emit-relocs-1.d
@@ -0,0 +1,37 @@
+#name: Emit relocs 1
+#source: emit-relocs-1a.s -mabi=n32 -EB
+#source: emit-relocs-1b.s -mabi=n32 -EB
+#ld: -q -T emit-relocs-1.ld -melf32btsmipn32
+#objdump: -sr
+
+.*:     file format .*
+
+RELOCATION RECORDS FOR \[\.data\]:
+OFFSET   TYPE              VALUE *
+00000000 R_MIPS_32         \.data
+00000004 R_MIPS_32         \.data\+0x00001000
+00000008 R_MIPS_32         \.merge1\+0x00000002
+0000000c R_MIPS_32         \.merge2
+00000010 R_MIPS_32         \.merge3
+00000014 R_MIPS_32         \.merge3\+0x00000004
+00000020 R_MIPS_32         \.data\+0x00000020
+00000024 R_MIPS_32         \.data\+0x00001020
+00000028 R_MIPS_32         \.merge1
+0000002c R_MIPS_32         \.merge2\+0x00000002
+00000030 R_MIPS_32         \.merge3\+0x00000008
+00000034 R_MIPS_32         \.merge3\+0x00000004
+
+
+Contents of section \.text:
+ 80000 03e00008 00000000 00000000 00000000  .*
+Contents of section \.merge1:
+ 80400 666c7574 74657200                    flutter.*
+Contents of section \.merge2:
+ 80800 74617374 696e6700                    tasting.*
+Contents of section \.merge3:
+ 80c00 00000100 00000200 00000300           .*
+Contents of section \.data:
+ 81000 00081000 00082000 00080402 00080800  .*
+ 81010 00080c00 00080c04 00000000 00000000  .*
+ 81020 00081020 00082020 00080400 00080802  .*
+ 81030 00080c08 00080c04 .*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/emit-relocs-1.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/emit-relocs-1.ld
new file mode 100644
index 0000000..1879ef4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/emit-relocs-1.ld
@@ -0,0 +1,20 @@
+ENTRY(_start)
+SECTIONS
+{
+  . = 0x80000;
+  .text : { *(.text) }
+
+  . = ALIGN (0x400);
+  .merge1 : { *(.merge1) }
+
+  . = ALIGN (0x400);
+  .merge2 : { *(.merge2) }
+
+  . = ALIGN (0x400);
+  .merge3 : { *(.merge3) }
+
+  . = ALIGN (0x400);
+  .data : { *(.data) }
+
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/emit-relocs-1a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/emit-relocs-1a.s
new file mode 100644
index 0000000..9176f97
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/emit-relocs-1a.s
@@ -0,0 +1,22 @@
+	.text
+	.globl	_start
+_start:
+	jr	$31
+
+	.section .merge1,"aMS",@progbits,1
+A:	.string	"utter"
+
+	.section .merge2,"aMS",@progbits,1
+B:	.string "tasting"
+
+	.section .merge3,"aM",@progbits,4
+C:	.4byte	0x100
+D:	.4byte	0x200
+
+	.data
+E:	.4byte	E
+	.4byte	E + 0x1000
+	.4byte	A
+	.4byte	B
+	.4byte	C
+	.4byte	D
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/emit-relocs-1b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/emit-relocs-1b.s
new file mode 100644
index 0000000..0e88c14
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/emit-relocs-1b.s
@@ -0,0 +1,17 @@
+	.section .merge1,"aMS",@progbits,1
+A:	.string	"flutter"
+
+	.section .merge2,"aMS",@progbits,1
+B:	.string "sting"
+
+	.section .merge3,"aM",@progbits,4
+C:	.4byte	0x300
+D:	.4byte	0x200
+
+	.data
+E:	.4byte	E
+	.4byte	E + 0x1000
+	.4byte	A
+	.4byte	B
+	.4byte	C
+	.4byte	D
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-1.d b/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-1.d
new file mode 100644
index 0000000..b14adff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-1.d
@@ -0,0 +1,25 @@
+#name: GOT dump (readelf -A) test 1
+#source: got-dump-1.s
+#as: -mips3
+#ld: -Tgot-dump-1.ld -shared
+#readelf: -A
+
+Primary GOT:
+ Canonical gp value: 00068000
+
+ Reserved entries:
+   Address     Access  Initial Purpose
+  00060010 -32752\(gp\) 00000000 Lazy resolver
+  00060014 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+ Local entries:
+   Address     Access  Initial
+  00060018 -32744\(gp\) 00060000
+  0006001c -32740\(gp\) 00060004
+
+ Global entries:
+   Address     Access  Initial Sym.Val. Type    Ndx Name
+  00060020 -32736\(gp\) 00050020 00050020 FUNC    UND extern
+  00060024 -32732\(gp\) 00050000 00050000 FUNC      7 glob
+  00060028 -32728\(gp\) 00000000 00000000 NOTYPE  UND undef
+
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-1.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-1.ld
new file mode 100644
index 0000000..4fe5c1a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-1.ld
@@ -0,0 +1,19 @@
+SECTIONS
+{
+  . = 0x40000;
+  .reginfo : { *(.reginfo) }
+  .dynamic : { *(.dynamic) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+  .rel.dyn : { *(.rel.dyn) }
+
+  . = 0x50000;
+  .text : { *(.text) }
+  .MIPS.stubs : { *(.MIPS.stubs) }
+
+  . = 0x60000;
+  .data : { *(.data) }
+  _gp = ALIGN (16) + 0x7ff0;
+  .got : { *(.got) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-1.s
new file mode 100644
index 0000000..d6c318e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-1.s
@@ -0,0 +1,22 @@
+	.global	glob
+	.ent	glob
+glob:
+	lw	$4,%got(local)($28)
+	addiu	$4,$4,%lo(local)
+	lw	$4,%got(hidden)($28)
+	lw	$4,%call16(glob)($28)
+	lw	$4,%call16(extern)($28)
+	.end	glob
+
+	.data
+	.type	local,%object
+	.size	local,4
+local:
+	.word	undef
+
+	.globl	hidden
+	.hidden	hidden
+	.type	hidden,%object
+	.size	hidden,4
+hidden:
+	.word	0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-2.d b/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-2.d
new file mode 100644
index 0000000..56cc0b3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-2.d
@@ -0,0 +1,25 @@
+#name: GOT dump (readelf -A) test 2
+#source: got-dump-2.s
+#as: -mips3 -EB -64
+#ld: -Tgot-dump-2.ld -shared -melf64btsmip
+#readelf: -A
+
+Primary GOT:
+ Canonical gp value: 0001236000008000
+
+ Reserved entries:
+           Address     Access          Initial Purpose
+  0001236000000010 -32752\(gp\) 0000000000000000 Lazy resolver
+  0001236000000018 -32744\(gp\) 8000000000000000 Module pointer \(GNU extension\)
+
+ Local entries:
+           Address     Access          Initial
+  0001236000000020 -32736\(gp\) 0001236000000000
+  0001236000000028 -32728\(gp\) 0001236000000008
+
+ Global entries:
+           Address     Access          Initial         Sym.Val. Type    Ndx Name
+  0001236000000030 -32720\(gp\) 0001235000000020 0001235000000020 FUNC    UND extern
+  0001236000000038 -32712\(gp\) 0001235000000000 0001235000000000 FUNC      7 glob
+  0001236000000040 -32704\(gp\) 0000000000000000 0000000000000000 NOTYPE  UND undef
+
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-2.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-2.ld
new file mode 100644
index 0000000..cab0f4b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-2.ld
@@ -0,0 +1,18 @@
+SECTIONS
+{
+  . = 0x1234000000000;
+  .dynamic : { *(.dynamic) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+  .rel.dyn : { *(.rel.dyn) }
+
+  . = 0x1235000000000;
+  .text : { *(.text) }
+  .MIPS.stubs : { *(.MIPS.stubs) }
+
+  . = 0x1236000000000;
+  .data : { *(.data) }
+  _gp = ALIGN (16) + 0x7ff0;
+  .got : { *(.got) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-2.s b/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-2.s
new file mode 100644
index 0000000..5a237fe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-dump-2.s
@@ -0,0 +1,22 @@
+	.global	glob
+	.ent	glob
+glob:
+	ld	$4,%got_page(local)($28)
+	daddiu	$4,$4,%got_ofst(local)
+	ld	$4,%got_disp(hidden)($28)
+	ld	$4,%call16(glob)($28)
+	ld	$4,%call16(extern)($28)
+	.end	glob
+
+	.data
+	.type	local,%object
+	.size	local,8
+local:
+	.dword	undef
+
+	.globl	hidden
+	.hidden	hidden
+	.type	hidden,%object
+	.size	hidden,8
+hidden:
+	.dword	0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-1.d b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-1.d
new file mode 100644
index 0000000..6f4cfd3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-1.d
@@ -0,0 +1,10 @@
+#name: GOT page test 1
+#source: got-page-1.s
+#ld: -T got-page-1.ld -shared
+#readelf: -d
+#
+# There should be 10 page entries and 2 reserved entries
+#
+#...
+.* \(MIPS_LOCAL_GOTNO\) *12
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-1.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-1.ld
new file mode 100644
index 0000000..fe2afe6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-1.ld
@@ -0,0 +1,31 @@
+SECTIONS
+{
+  . = 0x80000;
+  .interp : { *(.interp) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+
+  . = ALIGN (0x400);
+  .rel.dyn : { *(.rel.dyn) }
+
+  . = ALIGN (0x400);
+  .MIPS.stubs : { *(.MIPS.stubs) }
+
+  . = ALIGN (0x400);
+  .text : { *(.text) }
+
+  . = ALIGN (0x10000);
+  _gp = . + 0x7ff0;
+  .got : { *(.got) }
+
+  . = ALIGN (0x400);
+  .bss : { *(.bss .bss.*) }
+
+  /DISCARD/ : { *(.reginfo) }
+}
+
+VERSION
+{
+  { local: *; };
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-1.s
new file mode 100644
index 0000000..976a522
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-1.s
@@ -0,0 +1,46 @@
+	# See below.
+	lw	$4,%got(foo+0x120000)($gp)
+	addiu	$4,$4,%lo(foo+0x120000)
+
+	# 2 pages
+	lw	$4,%got(foo-0x8000)($gp)
+	addiu	$4,$4,%lo(foo-0x8000)
+	lw	$4,%got(foo+0x800)($gp)
+	addiu	$4,$4,%lo(foo+0x8000)
+
+	# 2 pages
+	lw	$4,%got(foo-0x1000000)($gp)
+	addiu	$4,$4,%lo(foo-0x1000000)
+	lw	$4,%got(foo-0xffffff)($gp)
+	addiu	$4,$4,%lo(foo-0xffffff)
+
+	# 1 page
+	lw	$4,%got(foo+0x120000)($gp)
+	addiu	$4,$4,%lo(foo+0x120000)
+
+	# 5 pages
+	lw	$4,%got(bar)($gp)
+	addiu	$4,$4,%lo(bar)
+	lw	$4,%got(bar+0x20000)($gp)
+	addiu	$4,$4,%lo(bar+0x20000)
+	lw	$4,%got(bar+0x40000)($gp)
+	addiu	$4,$4,%lo(bar+0x40000)
+	lw	$4,%got(bar+0x30000)($gp)
+	addiu	$4,$4,%lo(bar+0x30000)
+	lw	$4,%got(bar+0x10000)($gp)
+	addiu	$4,$4,%lo(bar+0x10000)
+	lw	$4,%got(bar+0x38000)($gp)
+	addiu	$4,$4,%lo(bar+0x38000)
+	lw	$4,%got(bar+0x14000)($gp)
+	addiu	$4,$4,%lo(bar+0x14000)
+	lw	$4,%got(bar+0x2c000)($gp)
+	addiu	$4,$4,%lo(bar+0x2c000)
+	lw	$4,%got(bar+0x02000)($gp)
+	addiu	$4,$4,%lo(bar+0x02000)
+
+	.section .bss.foo,"aw",@nobits
+	.fill	0x800000
+foo:	.fill	0x800000
+
+	.section .bss.bar,"aw",@nobits
+bar:	.fill	0xc00000
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-2.d b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-2.d
new file mode 100644
index 0000000..ad198d0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-2.d
@@ -0,0 +1,11 @@
+#name: GOT page test 2
+#source: got-page-2.s
+#as: -EB -n32
+#ld: -T got-page-1.ld -shared -melf32btsmipn32
+#readelf: -d
+#
+# There should be 10 page entries and 2 reserved entries
+#
+#...
+.* \(MIPS_LOCAL_GOTNO\) *12
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-2.s b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-2.s
new file mode 100644
index 0000000..9482570
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-2.s
@@ -0,0 +1,46 @@
+	# See below.
+	lw	$4,%got_page(foo+0x120000)($gp)
+	addiu	$4,$4,%got_ofst(foo+0x120000)
+
+	# 2 pages
+	lw	$4,%got_page(foo-0x8000)($gp)
+	addiu	$4,$4,%got_ofst(foo-0x8000)
+	lw	$4,%got_page(foo+0x800)($gp)
+	addiu	$4,$4,%got_ofst(foo+0x8000)
+
+	# 2 pages
+	lw	$4,%got_page(foo-0x1000000)($gp)
+	addiu	$4,$4,%got_ofst(foo-0x1000000)
+	lw	$4,%got_page(foo-0xffffff)($gp)
+	addiu	$4,$4,%got_ofst(foo-0xffffff)
+
+	# 1 page
+	lw	$4,%got_page(foo+0x120000)($gp)
+	addiu	$4,$4,%got_ofst(foo+0x120000)
+
+	# 5 pages
+	lw	$4,%got_page(bar)($gp)
+	addiu	$4,$4,%got_ofst(bar)
+	lw	$4,%got_page(bar+0x20000)($gp)
+	addiu	$4,$4,%got_ofst(bar+0x20000)
+	lw	$4,%got_page(bar+0x40000)($gp)
+	addiu	$4,$4,%got_ofst(bar+0x40000)
+	lw	$4,%got_page(bar+0x30000)($gp)
+	addiu	$4,$4,%got_ofst(bar+0x30000)
+	lw	$4,%got_page(bar+0x10000)($gp)
+	addiu	$4,$4,%got_ofst(bar+0x10000)
+	lw	$4,%got_page(bar+0x38000)($gp)
+	addiu	$4,$4,%got_ofst(bar+0x38000)
+	lw	$4,%got_page(bar+0x14000)($gp)
+	addiu	$4,$4,%got_ofst(bar+0x14000)
+	lw	$4,%got_page(bar+0x2c000)($gp)
+	addiu	$4,$4,%got_ofst(bar+0x2c000)
+	lw	$4,%got_page(bar+0x02000)($gp)
+	addiu	$4,$4,%got_ofst(bar+0x02000)
+
+	.section .bss.foo,"aw",@nobits
+	.fill	0x800000
+foo:	.fill	0x800000
+
+	.section .bss.bar,"aw",@nobits
+bar:	.fill	0xc00000
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-3.d b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-3.d
new file mode 100644
index 0000000..913b0c9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-3.d
@@ -0,0 +1,26 @@
+#name: GOT page test 3
+#source: got-page-3a.s
+#source: got-page-3b.s
+#source: got-page-3c.s
+#as: -mips3
+#ld: -T got-page-1.ld -shared
+#objdump: -dr
+#
+# got-page-3a.s and got-page-3b.s should get assigned the same GOT,
+# with a page estimate of 10.  Thus the first page entry has offset
+# -32744 (-32768 + 0x8000 - ELF_MIPS_GP_OFFSET + MIPS_RESERVED_GOTNO)
+# and the first global entry has an offset -32744 + 40 == -32704.
+#
+# got-page-3c.s should get its own GOT, and needs no page entries.
+# The first global symbol should therefore be at offset -32744.
+#
+#...
+.*	lw	a0,-32744\(gp\)
+.*	addiu	a0,a0,.*
+#...
+.*	lw	a1,-32704\(gp\)
+#...
+.* <f3>:
+#...
+.*	lw	a1,-32744\(gp\)
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-3a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-3a.s
new file mode 100644
index 0000000..c0d4633
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-3a.s
@@ -0,0 +1,58 @@
+	.macro	makeref,sym
+	lw	$5,%got(\sym\@)($gp)
+	.endm
+
+	.globl	f1
+	.ent	f1
+f1:
+	# See below.
+	lw	$4,%got(foo+0x120000)($gp)
+	addiu	$4,$4,%lo(foo+0x120000)
+
+	# 2 pages
+	lw	$4,%got(foo-0x8000)($gp)
+	addiu	$4,$4,%lo(foo-0x8000)
+	lw	$4,%got(foo+0x800)($gp)
+	addiu	$4,$4,%lo(foo+0x8000)
+
+	# 2 pages
+	lw	$4,%got(foo-0x1000000)($gp)
+	addiu	$4,$4,%lo(foo-0x1000000)
+	lw	$4,%got(foo-0xffffff)($gp)
+	addiu	$4,$4,%lo(foo-0xffffff)
+
+	# 1 page
+	lw	$4,%got(foo+0x120000)($gp)
+	addiu	$4,$4,%lo(foo+0x120000)
+
+	# 5 pages
+	lw	$4,%got(bar)($gp)
+	addiu	$4,$4,%lo(bar)
+	lw	$4,%got(bar+0x20000)($gp)
+	addiu	$4,$4,%lo(bar+0x20000)
+	lw	$4,%got(bar+0x40000)($gp)
+	addiu	$4,$4,%lo(bar+0x40000)
+	lw	$4,%got(bar+0x30000)($gp)
+	addiu	$4,$4,%lo(bar+0x30000)
+	lw	$4,%got(bar+0x10000)($gp)
+	addiu	$4,$4,%lo(bar+0x10000)
+	lw	$4,%got(bar+0x38000)($gp)
+	addiu	$4,$4,%lo(bar+0x38000)
+	lw	$4,%got(bar+0x14000)($gp)
+	addiu	$4,$4,%lo(bar+0x14000)
+	lw	$4,%got(bar+0x2c000)($gp)
+	addiu	$4,$4,%lo(bar+0x2c000)
+	lw	$4,%got(bar+0x02000)($gp)
+	addiu	$4,$4,%lo(bar+0x02000)
+	.end	f1
+
+	.rept	8000
+	makeref	foo
+	.endr
+
+	.section .bss.foo,"aw",@nobits
+	.fill	0x800000
+foo:	.fill	0x800000
+
+	.section .bss.bar,"aw",@nobits
+bar:	.fill	0xc00000
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-3b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-3b.s
new file mode 100644
index 0000000..6b399db
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-3b.s
@@ -0,0 +1,11 @@
+	.macro	makeref,sym
+	lw	$5,%got(\sym\@)($gp)
+	.endm
+
+	.globl	f2
+	.ent	f2
+f2:
+	.rept	8000
+	makeref	bar
+	.endr
+	.end	f2
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-3c.s b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-3c.s
new file mode 100644
index 0000000..cd7656c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-page-3c.s
@@ -0,0 +1,11 @@
+	.macro	makeref,sym
+	lw	$5,%got(\sym\@)($gp)
+	.endm
+
+	.globl	f3
+	.ent	f3
+f3:
+	.rept	8000
+	makeref	frob
+	.endr
+	.end	f3
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1.dd
new file mode 100644
index 0000000..98cda95
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1.dd
@@ -0,0 +1,6 @@
+# There must be one global GOT symbol.  Its index doesn't matter.
+#...
+ 0x70000011 \(MIPS_SYMTABNO\) * 4
+#...
+ 0x70000013 \(MIPS_GOTSYM\) * 0x3
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1.rd b/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1.rd
new file mode 100644
index 0000000..d99ead1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1.rd
@@ -0,0 +1,6 @@
+
+Relocation section '\.rel\.dyn' at offset .* contains 2 entries:
+ *Offset * Info * Type * Sym\.Value * Sym\. Name
+00000000 * 00000000 * R_MIPS_NONE *
+# This index must be the same as DT_MIPS_GOTsYM.
+[^ ]+ * 00000303 * R_MIPS_REL32 * [^ ]+ * foo
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1.sd b/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1.sd
new file mode 100644
index 0000000..9c3a8c0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1.sd
@@ -0,0 +1,6 @@
+# foo@@V2 must have index DT_MIPS_GOTSYM
+#...
+ *3: .* 4 * OBJECT * GLOBAL * DEFAULT * [0-9]+ * foo@@V2
+
+Symbol table '\.symtab' contains .*:
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1.ver b/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1.ver
new file mode 100644
index 0000000..defa8e9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1.ver
@@ -0,0 +1 @@
+V2 { global: foo; local: *; };
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1a.s
new file mode 100644
index 0000000..b9959ff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1a.s
@@ -0,0 +1,2 @@
+	.abicalls
+	.word	foo
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1b.s
new file mode 100644
index 0000000..dd308b4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/got-vers-1b.s
@@ -0,0 +1,7 @@
+	.abicalls
+	.symver	foo2,foo@@V2
+	.global	foo2
+	.data
+	.type	foo2,%object
+	.size	foo2,4
+foo2:	.word	0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/hash1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/hash1.s
new file mode 100644
index 0000000..4e7fe2f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/hash1.s
@@ -0,0 +1 @@
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/hash1a.d b/binutils-2.19/ld/testsuite/ld-mips-elf/hash1a.d
new file mode 100644
index 0000000..f3adaa8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/hash1a.d
@@ -0,0 +1,4 @@
+#source: hash1.s
+#ld: -shared --hash-style=sysv
+#objdump: -dr
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/hash1b.d b/binutils-2.19/ld/testsuite/ld-mips-elf/hash1b.d
new file mode 100644
index 0000000..5af9037
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/hash1b.d
@@ -0,0 +1,3 @@
+#source: hash1.s
+#ld: -shared --hash-style=both
+#error: .gnu.hash is incompatible with the MIPS ABI
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/hash1c.d b/binutils-2.19/ld/testsuite/ld-mips-elf/hash1c.d
new file mode 100644
index 0000000..09bff3c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/hash1c.d
@@ -0,0 +1,3 @@
+#source: hash1.s
+#ld: -shared --hash-style=gnu
+#error: .gnu.hash is incompatible with the MIPS ABI
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/jalbal.d b/binutils-2.19/ld/testsuite/ld-mips-elf/jalbal.d
new file mode 100644
index 0000000..49cda75
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/jalbal.d
@@ -0,0 +1,24 @@
+#name: jal to bal
+#source: jalbal.s
+#as: -EB -n32 -march=rm9000
+#ld: -EB -e s1 -Ttext 0x200000a0
+#objdump: -d
+
+.*file format elf.*mips.*
+
+Disassembly of section \.text:
+
+.* <s1>:
+.*	0c00802a 	jal	.*200200a8 <s3>
+.*	00000000 	nop
+.*	04117fff 	bal	.*200200a8 <s3>
+
+.* <s2>:
+.*	\.\.\.
+
+.* <s3>:
+.*	04118000 	bal	.*200000ac <s2>
+.*	00000000 	nop
+.*	0c00002b 	jal	.*200000ac <s2>
+.*	00000000 	nop
+.*	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/jalbal.s b/binutils-2.19/ld/testsuite/ld-mips-elf/jalbal.s
new file mode 100644
index 0000000..4273b9f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/jalbal.s
@@ -0,0 +1,18 @@
+# Test that jal gets converted to bal on the RM9000 when it is in range.
+	.text
+	.global	s1
+	.type	s1,@function
+	.set	noreorder
+s1:
+	jal	s3
+	nop
+	jal	s3
+s2:
+	nop
+	.space	0x1fff8
+s3:
+	jal	s2
+	nop
+	jal	s2
+	nop
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/jaloverflow-2.d b/binutils-2.19/ld/testsuite/ld-mips-elf/jaloverflow-2.d
new file mode 100644
index 0000000..b40f428
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/jaloverflow-2.d
@@ -0,0 +1,8 @@
+#name: JAL overflow 2
+#source: jaloverflow-2.s
+#as:
+#ld: -Ttext=0x20000000 -e start
+#objdump: -dr
+#...
+0*20000000:	0c000000.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/jaloverflow-2.s b/binutils-2.19/ld/testsuite/ld-mips-elf/jaloverflow-2.s
new file mode 100644
index 0000000..71acf29
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/jaloverflow-2.s
@@ -0,0 +1,7 @@
+# jal relocs against undefined weak symbols should not be treated as
+# overflowing
+
+	.globl	start
+	.weak	foo
+start:
+	jal	foo
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/jaloverflow.d b/binutils-2.19/ld/testsuite/ld-mips-elf/jaloverflow.d
new file mode 100644
index 0000000..b77afe6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/jaloverflow.d
@@ -0,0 +1,11 @@
+#name: JAL overflow
+#source: jaloverflow.s
+#as:
+#ld: -Ttext=0xffffff0 -e start
+#error: .*relocation truncated to fit.*
+
+# This tests whether we correctly detect overflow in the jal
+# instruction.  jal is a bit weird since the upper four bits of the
+# destination address are taken from the source address.  So overflow
+# occurs if the source and destination address do not have the same
+# most significant four bits.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/jaloverflow.s b/binutils-2.19/ld/testsuite/ld-mips-elf/jaloverflow.s
new file mode 100644
index 0000000..4dd98b8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/jaloverflow.s
@@ -0,0 +1,12 @@
+# This file gets linked to start at 0xffffff0, so the call is an overflow.
+	.text
+	.global start
+	.set	noreorder
+start:
+	nop
+	nop
+	nop
+	nop
+	jal	start
+	nop
+	.type start, @function
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/jr.s b/binutils-2.19/ld/testsuite/ld-mips-elf/jr.s
new file mode 100644
index 0000000..df487d8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/jr.s
@@ -0,0 +1 @@
+	jr	$31
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips-dyn.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/mips-dyn.ld
new file mode 100644
index 0000000..8f734d2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips-dyn.ld
@@ -0,0 +1,223 @@
+/* Script for -z combreloc: combine and sort reloc sections */
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips",
+	      "elf32-tradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(__start)
+SEARCH_DIR("=/usr/local/lib"); SEARCH_DIR("=/lib"); SEARCH_DIR("=/usr/lib");
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  PROVIDE (__executable_start = 0x0400000); . = 0x0400000 + SIZEOF_HEADERS;
+  .interp         : { *(.interp) }
+  .reginfo        : { *(.reginfo) }
+  .dynamic        : { *(.dynamic) }
+  .hash           : { *(.hash) }
+  .dynsym         : { *(.dynsym) }
+  .dynstr         : { *(.dynstr) }
+  .gnu.version    : { *(.gnu.version) }
+  .gnu.version_d  : { *(.gnu.version_d) }
+  .gnu.version_r  : { *(.gnu.version_r) }
+  .rel.dyn        :
+    {
+      *(.rel.init)
+      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
+      *(.rel.fini)
+      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
+      *(.rel.data.rel.ro*)
+      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
+      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
+      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
+      *(.rel.ctors)
+      *(.rel.dtors)
+      *(.rel.got)
+      *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
+      *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
+      *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
+      *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
+      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
+    }
+  .rela.dyn       :
+    {
+      *(.rela.init)
+      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+      *(.rela.fini)
+      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+      *(.rela.ctors)
+      *(.rela.dtors)
+      *(.rela.got)
+      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+    }
+  .rel.plt        : { *(.rel.plt) }
+  .rela.plt       : { *(.rela.plt) }
+  .init           :
+  {
+    KEEP (*(.init))
+  } =0
+  .plt            : { *(.plt) }
+  .text           :
+  {
+    _ftext = . ;
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.mips16.fn.*) *(.mips16.call.*)
+  } =0
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } =0
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
+  .rodata1        : { *(.rodata1) }
+  .sdata2         : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }
+  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
+  .eh_frame_hdr : { *(.eh_frame_hdr) }
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = 0x10000000;
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  . = ALIGN(32 / 8);
+  PROVIDE (__preinit_array_start = .);
+  .preinit_array     : { KEEP (*(.preinit_array)) }
+  PROVIDE (__preinit_array_end = .);
+  PROVIDE (__init_array_start = .);
+  .init_array     : { KEEP (*(.init_array)) }
+  PROVIDE (__init_array_end = .);
+  PROVIDE (__fini_array_start = .);
+  .fini_array     : { KEEP (*(.fini_array)) }
+  PROVIDE (__fini_array_end = .);
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  }
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  }
+  .jcr            : { KEEP (*(.jcr)) }
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }
+  .data           :
+  {
+    _fdata = . ;
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  }
+  .data1          : { *(.data1) }
+  _gp = ALIGN(16) + 0x7ff0;
+  .got            : { *(.got.plt) *(.got) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata          :
+  {
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+  .lit8           : { *(.lit8) }
+  .lit4           : { *(.lit4) }
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  _fbss = .;
+  .sbss           :
+  {
+    PROVIDE (__sbss_start = .);
+    PROVIDE (___sbss_start = .);
+    *(.dynsbss)
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+    PROVIDE (__sbss_end = .);
+    PROVIDE (___sbss_end = .);
+  }
+  .bss            :
+  {
+   *(.dynbss)
+   *(.bss .bss.* .gnu.linkonce.b.*)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   . = ALIGN(32 / 8);
+  }
+  . = ALIGN(32 / 8);
+  _end = .;
+  PROVIDE (end = .);
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
+  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips-elf-flags.exp b/binutils-2.19/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
new file mode 100644
index 0000000..7ff2938
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips-elf-flags.exp
@@ -0,0 +1,166 @@
+#   Copyright 2003, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+if {![istarget mips*-*-*] || ![is_elf_format]} {
+    return
+}
+
+global ldemul
+if {[istarget mips*-*-irix6*]} {
+    set ldemul "-melf32bsmip"
+} elseif {[istarget mips*el-*-linux*]} {
+    set ldemul "-melf32ltsmip"
+} elseif {[istarget mips*-*-linux*]} {
+    set ldemul "-melf32btsmip"
+} else {
+    set ldemul ""
+}
+
+# Assemble jr.s using each of the argument lists in ARGLIST.  Return the
+# list of object files on success and an empty list on failure.
+proc assemble_for_flags {arglist} {
+    global as srcdir subdir
+
+    set objs {}
+    set index 1
+
+    foreach args $arglist {
+	set obj "tmpdir/mips-flags-${index}.o"
+	if {![ld_assemble $as "$args $srcdir/$subdir/jr.s" $obj]} {
+	    return ""
+	}
+	lappend objs $obj
+	incr index
+    }
+    return $objs
+}
+
+# Assemble a file using each set of arguments in ARGLIST.  Check that
+# the objects can be linked together and that the readelf output
+# includes each flag named in FLAGS.
+proc good_combination {arglist flags} {
+    global ld ldemul READELF
+
+    set finalobj "tmpdir/mips-flags.o"
+    set testname "MIPS compatible objects: $arglist"
+    set objs [assemble_for_flags $arglist]
+
+    if {$objs == ""} {
+	unresolved $testname
+    } elseif {![ld_simple_link "$ld $ldemul" $finalobj "-r $objs"]} {
+	fail $testname
+    } else {
+	catch "exec $READELF --headers $finalobj" output
+	if {![regexp "Flags: *(\[^\n\]*)" $output full gotflags]} {
+	    unresolved $testname
+	} else {
+	    set failed 0
+
+	    # GOTFLAGS is a list of flags separated by ", ".
+	    # Convert it to a tcl list.
+	    regsub -all ", " $gotflags "," gotflags
+	    set gotflags [split $gotflags ","]
+
+	    foreach flag $flags {
+		if {[lsearch -exact $gotflags $flag] < 0} {
+		    set failed 1
+		}
+	    }
+	    if {$failed} {
+		fail $testname
+	    } else {
+		pass $testname
+	    }
+	}
+    }
+}
+
+# Like good_combination, but check that the objects can't be linked
+# together successfully and that the output includes MESSAGE.
+proc bad_combination {arglist message} {
+    global link_output ld ldemul
+
+    set finalobj "tmpdir/mips-flags.o"
+    set testname "MIPS incompatible objects: $arglist"
+    set objs [assemble_for_flags $arglist]
+
+    if {$objs == ""} {
+	unresolved $testname
+    } elseif {[ld_simple_link "$ld $ldemul" $finalobj "-r $objs"]
+	      || [string first $message $link_output] < 0} {
+	fail $testname
+    } else {
+	pass $testname
+    }
+}
+
+# Routines to check for various kinds of incompatibility.
+
+proc abi_conflict {arglist firstabi secondabi} {
+    bad_combination $arglist \
+      "linking $secondabi module with previous $firstabi modules"
+}
+
+proc isa_conflict {arglist firstisa secondisa} {
+    bad_combination $arglist \
+      "linking mips:$secondisa module with previous mips:$firstisa modules"
+}
+
+proc regsize_conflict {arglist} {
+    bad_combination $arglist \
+      "linking 32-bit code with 64-bit code"
+}
+
+abi_conflict { "-mabi=eabi -mgp32" "-mips4 -mabi=32" } EABI32 O32
+abi_conflict { "-mips4 -mabi=o64" "-mips3 -mabi=eabi" } O64 EABI64
+
+isa_conflict { "-march=vr5500 -32" "-march=sb1 -32" } 5500 sb1
+isa_conflict { "-march=vr5400 -32" "-march=4120 -32" } 5400 4120
+isa_conflict { "-march=r3900 -32" "-march=r6000 -32" } 3900 6000
+isa_conflict { "-march=r4010 -32" "-march=r4650 -32" } 4010 4650
+isa_conflict { "-mips3 -mgp32 -32" "-mips32 -32" } 4000 isa32
+isa_conflict { "-march=sb1 -mgp32 -32" "-mips32r2 -32" } sb1 isa32r2
+isa_conflict { "-march=sb1 -32" "-mips64r2 -32" } sb1 isa64r2
+
+regsize_conflict { "-mips4 -mgp64 -mabi=o64" "-mips2 -32" }
+regsize_conflict { "-mips4 -mabi=o64" "-mips4 -mabi=32" }
+regsize_conflict { "-mips4 -mabi=eabi -mgp32" "-mips4 -mabi=eabi -mgp64" }
+regsize_conflict { "-march=vr5000 -mgp64 -mabi=o64" "-march=vr5000 -mgp32 -32" }
+regsize_conflict { "-mips32 -32" "-mips64 -mabi=o64" }
+regsize_conflict { "-mips32r2 -32" "-mips64 -mabi=o64" }
+regsize_conflict { "-mips32r2 -32" "-mips64r2 -mabi=o64" }
+
+good_combination { "-mips4 -mgp32 -32" "-mips2 -32" } { mips4 o32 }
+good_combination { "-mips4 -mabi=32" "-mips2 -32" } { mips4 o32 }
+good_combination { "-mips2 -32" "-mips4 -mabi=32" } { mips4 o32 }
+good_combination { "-mips2 -mabi=eabi" "-mips4 -mabi=eabi -mgp32" } { mips4 eabi32 }
+good_combination { "-mips2 -32" "-mips32 -32" "-mips32r2 -32" } { mips32r2 }
+good_combination { "-mips1 -32" "-mips32r2 -32" "-mips32 -32" } { mips32r2 }
+
+good_combination { "-march=vr4100 -32" "-march=vr4120 -32" } { 4120 }
+good_combination { "-march=vr5400 -32" "-march=vr5500 -32" "-mips4 -32" } { 5500 }
+good_combination { "-mips3 -32" "-mips4 -32" "-march=sb1 -32" "-mips5 -32" } { sb1 }
+good_combination { "-mips1 -32" "-march=3900 -32" } { 3900 }
+good_combination { "-mips3 -32" "-mips64r2 -32" "-mips64 -32" } { mips64r2 }
+
+good_combination { "-march=vr4120 -mabi=32" "-mips3 -mabi=32" } { 4120 o32 }
+good_combination { "-march=sb1 -mgp32 -32" "-march=4000 -mgp32 -32" } { sb1 o32 }
+good_combination { "-mips32 -mabi=32" "-march=sb1 -mabi=32" } { sb1 o32 }
+good_combination { "-mips64r2 -mabi=32" "-mips32 -mabi=32" } { mips64r2 o32 }
+good_combination { "-mips5 -mabi=o64" "-mips64r2 -mabi=o64" } { mips64r2 o64 }
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips-elf.exp b/binutils-2.19/ld/testsuite/ld-mips-elf/mips-elf.exp
new file mode 100644
index 0000000..fa098b1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips-elf.exp
@@ -0,0 +1,504 @@
+# Expect script for MIPS ELF linker tests
+#   Copyright 2002, 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+if {[istarget "mips*-*-vxworks"]} {
+    set mipsvxtests {
+	{"VxWorks shared library test 1" "-shared -Tvxworks1.ld"
+	 "-mips2" {vxworks1-lib.s}
+	 {{readelf --relocs vxworks1-lib.rd} {objdump -dr vxworks1-lib.dd}
+	  {readelf --symbols vxworks1-lib.nd} {readelf -d vxworks1-lib.td}}
+	 "libvxworks1.so"}
+	{"VxWorks executable test 1 (dynamic)" \
+	 "tmpdir/libvxworks1.so -Tvxworks1.ld -q --force-dynamic"
+	 "-mips2" {vxworks1.s}
+	 {{readelf --relocs vxworks1.rd} {objdump -dr vxworks1.dd}}
+	 "vxworks1"}
+	{"VxWorks executable test 2 (dynamic)" \
+	 "-Tvxworks1.ld -q --force-dynamic"
+	 "-mips2" {vxworks2.s}
+	 {{readelf --segments vxworks2.sd}}
+	 "vxworks2"}
+	{"VxWorks executable test 2 (static)"
+	 "-Tvxworks1.ld"
+	 "-mips2" {vxworks2.s}
+	 {{readelf --segments vxworks2-static.sd}}
+	 "vxworks2"}
+    }
+    run_ld_link_tests $mipsvxtests
+    run_dump_test "vxworks1-static"
+    run_dump_test "vxworks-forced-local-1"
+    return
+}
+
+if {![istarget mips*-*-*] || ![is_elf_format]} {
+    return
+}
+
+set has_newabi [expr [istarget *-*-irix6*] || [istarget mips64*-*-linux*]]
+set linux_gnu [expr [istarget mips*-*-linux*]]
+set embedded_elf [expr [istarget mips*-*-elf]]
+
+if { $linux_gnu } {
+    run_ld_link_tests [list \
+	[list "Dummy shared library for MIPS16 PIC test 1" \
+	      "-shared -melf32btsmip" \
+	      "-EB -32" { mips16-pic-1-dummy.s } \
+	      {} \
+	      "mips16-pic-1-dummy.so"] \
+	[list "MIPS16 PIC test 1" \
+	      "-melf32btsmip -T mips16-pic-1.ld tmpdir/mips16-pic-1-dummy.so" \
+	      "-EB -32 -I $srcdir/$subdir" { mips16-pic-1a.s mips16-pic-1b.s } \
+	      { { objdump { -dr -j.text } mips16-pic-1.dd }
+		{ readelf -A mips16-pic-1.gd } } \
+	      "mips16-pic-1"] \
+	[list "MIPS16 PIC test 2" \
+	      "-melf32btsmip -T mips16-pic-1.ld -shared" \
+	      "-EB -32 -I $srcdir/$subdir" { mips16-pic-2a.s mips16-pic-2b.s } \
+	      { { objdump { -dr -j.text } mips16-pic-2.dd } \
+		{ readelf -A mips16-pic-2.gd } \
+	        { readelf --symbols mips16-pic-2.nd } \
+		{ readelf --relocs mips16-pic-2.rd } \
+		{ readelf -d mips16-pic-2.ad } } \
+	     "mips16-pic-2"] \
+	[list "MIPS16 PIC test 3" \
+	      "-melf32btsmip -T mips16-pic-1.ld tmpdir/mips16-pic-1-dummy.so" \
+	      "-EB -32 -I $srcdir/$subdir" { mips16-pic-3a.s mips16-pic-3b.s } \
+	      { { objdump -dr mips16-pic-3.dd } \
+		{ readelf --relocs mips16-pic-3.rd } \
+		{ readelf -A mips16-pic-3.gd } } \
+	      "mips16-pic-3"] \
+	[list "MIPS16 PIC test 4 (shared library)" \
+	      "-shared -melf32btsmip -T mips16-pic-1.ld --version-script mips16-pic-4.ver" \
+	      "-EB -32" { mips16-pic-4a.s mips16-pic-4b.s } \
+	      { { objdump -dr mips16-pic-4a.dd } \
+		{ readelf --symbols mips16-pic-4a.nd } \
+		{ readelf -A mips16-pic-4a.gd } } \
+	      "mips16-pic-4.so"] \
+	[list "MIPS16 PIC test 4 (executable)" \
+	      "-melf32btsmip -T mips16-pic-1.ld tmpdir/mips16-pic-4.so" \
+	      "-EB -32" { mips16-pic-4c.s } \
+	      { { objdump -dr mips16-pic-4b.dd } } \
+	      "mips16-pic-4"]]
+}
+
+if { [istarget mips64*-linux-gnu] } {
+    set o32_as_flags "-32 -EB"
+    set o32_ld_flags "-melf32btsmip"
+} else {
+    set o32_as_flags ""
+    set o32_ld_flags ""
+}
+
+# Check MIPS16 markings being passed through link.
+run_dump_test "mips16-1"
+
+# MIPS branch offset final link checking.
+run_dump_test "branch-misc-1"
+
+# Test multi-got link.  We only do this on GNU/Linux because it requires
+# the "traditional" emulations.
+if { $linux_gnu } {
+    run_dump_test "multi-got-1"
+    run_dump_test "multi-got-no-shared"
+    run_dump_test "multi-got-hidden-1"
+    run_dump_test "multi-got-hidden-2"
+}
+
+# Test __gnu_local_gp accesses
+if { $linux_gnu } {
+    run_dump_test "no-shared-1-o32"
+    if { $has_newabi } {
+	run_dump_test "no-shared-1-n32"
+	run_dump_test "no-shared-1-n64"
+    }
+}
+
+if $has_newabi {
+    run_dump_test "elf-rel-got-n32"
+    run_dump_test "elf-rel-xgot-n32"
+    if { $linux_gnu } {
+	run_dump_test "elf-rel-got-n64-linux"
+	run_dump_test "elf-rel-xgot-n64-linux"
+    } else {
+	run_dump_test "elf-rel-got-n64"
+	run_dump_test "elf-rel-xgot-n64"
+    }
+
+    run_dump_test "relax-jalr-n32"
+    run_dump_test "relax-jalr-n32-shared"
+    run_dump_test "relax-jalr-n64"
+    run_dump_test "relax-jalr-n64-shared"
+}
+
+if { $linux_gnu } {
+    run_dump_test "rel32-o32"
+    run_dump_test "rel32-n32"
+    run_dump_test "rel64"
+    # The first test checks that a mixed PIC/non-PIC relocatable link
+    # will not introduce any stubs itself, but will flag PIC functions
+    # for the final link.
+    #
+    # The second test checks that we insert stubs for calls from
+    # non-PIC functions to PIC functions when linking the original
+    # two objects together.
+    #
+    # The third test checks that we do the same when linking the
+    # result of the first link (with no other source files).
+    run_ld_link_tests {
+	{"PIC and non-PIC test 1 (relocatable)" "-r -melf32btsmip"
+	 "-32 -EB -mips2" {pic-and-nonpic-1a.s pic-and-nonpic-1b.s}
+	 {{objdump -dr pic-and-nonpic-1-rel.dd}
+	  {readelf --symbols pic-and-nonpic-1-rel.nd}}
+	 "pic-and-nonpic-1-rel.o"}
+	{"PIC and non-PIC test 1 (static 1)"
+	 "-melf32btsmip -Tpic-and-nonpic-1.ld"
+	 "-32 -EB -mips2" {pic-and-nonpic-1a.s pic-and-nonpic-1b.s}
+	 {{objdump -dr pic-and-nonpic-1.dd}
+	  {readelf --symbols pic-and-nonpic-1.nd}}
+	 "pic-and-nonpic-1-static1.o"}
+	{"PIC and non-PIC test 1 (static 2)"
+	 "-melf32btsmip -Tpic-and-nonpic-1.ld tmpdir/pic-and-nonpic-1-rel.o"
+	 "" {}
+	 {{objdump -dr pic-and-nonpic-1.dd}
+	  {readelf --symbols pic-and-nonpic-1.nd}}
+	 "pic-and-nonpic-1-static2.o"}
+    }
+    run_dump_test "pic-and-nonpic-2"
+    run_ld_link_tests {
+	{"PIC and non-PIC test 3 (shared library)"
+	 "-melf32btsmip -shared -Tpic-and-nonpic-3a.ld"
+	 "-32 -EB -mips2" {pic-and-nonpic-3a.s}
+	 {{readelf --segments pic-and-nonpic-3a.sd}
+	  {readelf -A pic-and-nonpic-3a.gd}
+	  {objdump -dr pic-and-nonpic-3a.dd}}
+	 "pic-and-nonpic-3a.so"}
+	{"PIC and non-PIC test 3 (executable)"
+	 "-melf32btsmip -Tpic-and-nonpic-3b.ld tmpdir/pic-and-nonpic-3a.so"
+	 "-32 -EB -mips2" {pic-and-nonpic-3b.s}
+	 {{readelf --segments pic-and-nonpic-3b.sd}
+	  {objdump -dr pic-and-nonpic-3b.dd}
+	  {objdump {-s -j.got.plt} pic-and-nonpic-3b.pd}
+	  {readelf -A pic-and-nonpic-3b.gd}
+	  {readelf --relocs pic-and-nonpic-3b.rd}
+	  {readelf --symbols pic-and-nonpic-3b.nd}
+	  {readelf -d pic-and-nonpic-3b.ad}}
+	 "pic-and-nonpic-3b"}
+    }
+    run_dump_test "pic-and-nonpic-3-error"
+    run_ld_link_tests {
+	{"PIC and non-PIC test 4 (shared library)"
+	 "-melf32btsmip -shared -Tpic-and-nonpic-3a.ld"
+	 "-32 -EB -mips2" {pic-and-nonpic-4a.s}
+	 {}
+	 "pic-and-nonpic-4a.so"}
+	{"PIC and non-PIC test 4 (executable)"
+	 "-melf32btsmip -Tpic-and-nonpic-4b.ld tmpdir/pic-and-nonpic-4a.so"
+	 "-32 -EB -mips2" {pic-and-nonpic-4b.s}
+	 {{readelf --segments pic-and-nonpic-4b.sd}
+	  {objdump -dr pic-and-nonpic-4b.dd}
+	  {objdump {-s -j.got -j.data} pic-and-nonpic-4b.gd}
+	  {readelf --relocs pic-and-nonpic-4b.rd}
+	  {readelf --symbols pic-and-nonpic-4b.nd}
+	  {readelf -d pic-and-nonpic-4b.ad}}
+	 "pic-and-nonpic-4b"}
+    }
+    run_dump_test "pic-and-nonpic-4-error"
+    run_ld_link_tests {
+	{"PIC and non-PIC test 5 (executable)"
+	 "-melf32btsmip -Tpic-and-nonpic-5b.ld tmpdir/pic-and-nonpic-3a.so tmpdir/pic-and-nonpic-4a.so"
+	 "-32 -EB -mips2" {pic-and-nonpic-5a.s pic-and-nonpic-5b.s}
+	 {{readelf --segments pic-and-nonpic-5b.sd}
+	  {objdump -dr pic-and-nonpic-5b.dd}
+	  {objdump {-s -j.got.plt -j.data} pic-and-nonpic-5b.pd}
+	  {readelf -A pic-and-nonpic-5b.gd}
+	  {readelf --relocs pic-and-nonpic-5b.rd}
+	  {readelf --symbols pic-and-nonpic-5b.nd}
+	  {readelf -d pic-and-nonpic-5b.ad}}
+	 "pic-and-nonpic-5b"}
+    }
+    set abis { o32 -32 elf32btsmip }
+    if $has_newabi {
+	lappend abis n32 -n32 elf32btsmipn32
+	lappend abis n64 -64 elf64btsmip
+    }
+    foreach { abi flag emul } $abis {
+	run_ld_link_tests [list \
+	    [list "PIC and non-PIC test 6 ($abi shared library)" \
+		 "-m$emul -shared -Tpic-and-nonpic-3a.ld" \
+		 "$flag -EB -mips3" \
+		 [list "pic-and-nonpic-6-${abi}a.s"] {} \
+		 "pic-and-nonpic-6-${abi}.so"] \
+	    [list "PIC and non-PIC test 6 ($abi executable)" \
+		 "-m$emul -Tpic-and-nonpic-6.ld tmpdir/pic-and-nonpic-6-${abi}.so" \
+		 "$flag -EB -mips3" \
+		 [list "pic-and-nonpic-6-${abi}b.s" \
+		      "pic-and-nonpic-6-${abi}c.s"] \
+		 [list "readelf {--wide --segments} pic-and-nonpic-6-${abi}.sd" \
+		      "objdump -dr pic-and-nonpic-6-${abi}.dd" \
+		      "objdump {-s -j.got.plt} pic-and-nonpic-6-${abi}.pd" \
+		      "readelf -A pic-and-nonpic-6-${abi}.gd" \
+		      "readelf --relocs pic-and-nonpic-6-${abi}.rd" \
+		      "readelf --symbols pic-and-nonpic-6-${abi}.nd" \
+		      "readelf -d pic-and-nonpic-6-${abi}.ad"] \
+		 "pic-and-nonpic-6-${abi}"]]
+    }
+}
+
+if { $embedded_elf } {
+    run_dump_test "region1"
+}
+
+if $embedded_elf {
+    # This could work on other targets too, but would need the appropriate
+    # ld -m switch.
+    run_dump_test "reloc-1-rel"
+}
+if $has_newabi {
+    run_dump_test "reloc-1-n32"
+    if $linux_gnu {
+	# Uses a linux-specific ld -m switch
+	run_dump_test "reloc-1-n64"
+    }
+}
+run_dump_test "reloc-2"
+run_dump_test "reloc-merge-lo16"
+run_dump_test "reloc-3"
+if {$has_newabi} {
+    run_dump_test "reloc-3-n32"
+}
+run_dump_test "reloc-4"
+run_dump_test "reloc-5"
+
+if {$has_newabi && $linux_gnu} {
+    run_dump_test "eh-frame1-n32"
+    run_dump_test "eh-frame1-n64"
+    run_dump_test "eh-frame2-n32"
+    run_dump_test "eh-frame2-n64"
+}
+if {$embedded_elf} {
+    run_dump_test "eh-frame3"
+    run_dump_test "eh-frame4"
+}
+
+run_dump_test "jaloverflow"
+run_dump_test "jaloverflow-2"
+if {$has_newabi} {
+    run_dump_test "jalbal"
+}
+
+run_dump_test "mips16-hilo"
+if {$has_newabi} {
+    run_dump_test "mips16-hilo-n32"
+}
+
+if { $linux_gnu } {
+    run_dump_test "textrel-1"
+    run_dump_test "got-page-1"
+    if $has_newabi {
+	run_dump_test "got-page-2"
+	run_dump_test "dyn-sec64"
+    }
+    run_dump_test "got-page-3"
+    run_dump_test "got-dump-1"
+    if $has_newabi {
+	run_dump_test "got-dump-2"
+    }
+    run_dump_test "reloc-estimate-1"
+}
+
+if $has_newabi {
+    run_dump_test "emit-relocs-1"
+}
+
+run_dump_test "hash1a"
+run_dump_test "hash1b"
+run_dump_test "hash1c"
+
+if {[istarget mips*-*-linux*]} {
+     # The number of symbols that are always included in the symbol table
+     # for these tests.  The 4 are:
+     #
+     #     the null symbol entry
+     #     the .MIPS.stubs section symbol
+     #     _gp
+     #     _GLOBAL_OFFSET_TABLE_
+     set base_syms 4
+     foreach dynsym { 7fff 8000 fff0 10000 2fe80 } {
+	 run_ld_link_tests \
+	     [list [list \
+			"Stub for dynsym 0x$dynsym" \
+			"-shared -melf32btsmip -T stub-dynsym-1.ld" \
+			[concat \
+			     "-EB -march=mips1 -32 -KPIC" \
+			     "--defsym base_syms=$base_syms" \
+			     "--defsym dynsym=0x$dynsym"] \
+			[list "stub-dynsym-1.s"] \
+			[list [list \
+				   "objdump" "-dz" \
+				   "stub-dynsym-1-$dynsym.d"]] \
+			"stub-dynsym-1-$dynsym"]]
+     }
+ }
+
+# For tests which may involve multiple files, use run_ld_link_tests.
+
+# List contains test-items with 3 items followed by 2 lists:
+# 0:name 1:ld options 2:assembler options
+# 3:filenames of assembler files 4: action and options. 5: name of output file
+
+# Actions:
+# objdump: Apply objdump options on result.  Compare with regex (last arg).
+# nm: Apply nm options on result.  Compare with regex (last arg).
+# readelf: Apply readelf options on result.  Compare with regex (last arg).
+
+set mips_tls_tests {
+    {"Static executable with TLS" "-static -melf32btsmip -T mips-dyn.ld"
+     "-EB -march=mips1 -32 -KPIC" {tlsbin-o32.s}
+     {{objdump {-dr -m mips:isa32r2} tlsbin-o32.d} {objdump -srj.got tlsbin-o32.got}}
+     "tls-static-o32"}
+    {"Shared library with TLS" "-shared -melf32btsmip -T mips-lib.ld"
+     "-EB -march=mips1 -32 -KPIC" {tlslib-o32.s}
+     {{objdump {-dr -m mips:isa32r2} tlslib-o32.d} {objdump -Rsj.got tlslib-o32.got}}
+     "tlslib-o32.so"}
+    {"Dynamic executable with TLS"
+     "-melf32btsmip -T mips-dyn.ld tmpdir/tlslib-o32.so"
+     "-EB -march=mips1 -32 -KPIC" {tlsdyn-o32.s}
+     {{objdump {-dr -m mips:isa32r2} tlsdyn-o32.d} {objdump -Rsj.got tlsdyn-o32.got}}
+     "tls-dynamic-o32"}
+    {"Shared library with multiple GOTs and TLS"
+     "-shared -melf32btsmip -T mips-lib.ld"
+     "-EB -march=mips1 -32 -KPIC" {tls-multi-got-1-1.s tls-multi-got-1-2.s}
+     {{readelf {-d -r} tls-multi-got-1.r}
+      {objdump {-dr -m mips:isa32r2} tls-multi-got-1.d}
+      {objdump -Rsj.got tls-multi-got-1.got}}
+     "tlslib-multi.so"}
+    {"Shared library with TLS and versioning"
+     "-shared -melf32btsmip -T mips-lib.ld --version-script tlslib.ver"
+     "-EB -march=mips1 -32 -KPIC" {tlslib-o32.s}
+     {{objdump {-dr -m mips:isa32r2} tlslib-o32.d} {objdump -Rsj.got tlslib-o32-ver.got}}
+     "tlslib-o32-ver.so"}
+    {"Dynamic executable with TLS and versioning"
+     "-melf32btsmip -T mips-dyn.ld tmpdir/tlslib-o32-ver.so"
+     "-EB -march=mips1 -32 -KPIC" {tlsdyn-o32.s tlsdyn-o32-2.s}
+     {{objdump {-dr -m mips:isa32r2} tlsdyn-o32-1.d} {objdump -Rsj.got tlsdyn-o32-1.got}}
+     "tls-dynamic-o32-ver"}
+    {"Dynamic executable with TLS and versioning (order 2)"
+     "-melf32btsmip -T mips-dyn.ld tmpdir/tlsdyn-o32.o tmpdir/tlslib-o32-ver.so tmpdir/tlsdyn-o32-2.o"
+     "-EB -march=mips1 -32 -KPIC" {}
+     {{objdump {-dr -m mips:isa32r2} tlsdyn-o32-2.d} {objdump -Rsj.got tlsdyn-o32-2.got}}
+     "tls-dynamic-o32-ver-2"}
+    {"Dynamic executable with TLS and versioning (order 3)"
+     "-melf32btsmip -T mips-dyn.ld tmpdir/tlsdyn-o32-2.o tmpdir/tlslib-o32-ver.so tmpdir/tlsdyn-o32.o"
+     "-EB -march=mips1 -32 -KPIC" {}
+     {{objdump {-dr -m mips:isa32r2} tlsdyn-o32-3.d} {objdump -Rsj.got tlsdyn-o32-3.got}}
+     "tls-dynamic-o32-ver-3"}
+    {"Shared library with TLS and hidden symbols"
+     "-shared -melf32btsmip -T mips-lib.ld --version-script tlslib-hidden.ver"
+     "-EB -march=mips1 -32 -KPIC" {tlslib-o32.s}
+     {{objdump {-dr -m mips:isa32r2} tlslib-o32.d} {objdump -Rsj.got tlslib-o32-hidden.got}}
+     "tlslib-o32-hidden.so"}
+    {"Shared library with TLS and hidden symbols (2)"
+     "-shared -melf32btsmip -T mips-lib.ld"
+     "-EB -march=mips1 -32 -KPIC" {tls-hidden2a.s tls-hidden2b.s}
+     {{objdump -drj.text tls-hidden2.d} {objdump -sj.got tls-hidden2-got.d}}
+     "tls-hidden2.so"}
+    {"Shared library with TLS and hidden symbols (3)"
+     "-shared -melf32btsmip -T tls-hidden3.ld"
+     "-EB -march=mips2 -32 -KPIC" {tls-hidden3a.s tls-hidden3b.s}
+     {{objdump -dj.text tls-hidden3.d} {objdump -sj.got tls-hidden3.got}
+      {readelf --relocs tls-hidden3.r}}
+     "tls-hidden3.so"}
+    {"Shared library with TLS and hidden symbols (4)"
+     "-shared -melf32btsmip -T tls-hidden3.ld"
+     "-EB -march=mips2 -32 -KPIC" {tls-hidden4a.s tls-hidden4b.s}
+     {{objdump -sj.got tls-hidden4.got} {readelf --relocs tls-hidden4.r}}
+     "tls-hidden4.so"}
+}
+
+if {[istarget mips*-*-linux*]} {
+    run_ld_link_tests $mips_tls_tests
+}
+
+set mips16_call_global_test [list \
+    [list "Global calls from mips16" \
+	 "$o32_ld_flags" \
+	 "$o32_as_flags -mips32r2" \
+	 {mips16-call-global-1.s mips16-call-global-2.s mips16-call-global-3.s} \
+	 {{objdump -dr mips16-call-global.d}} \
+	 "mips16-call-global"]]
+
+run_ld_link_tests $mips16_call_global_test
+
+set mips16_intermix_test [list \
+    [list "Intermixing mips32 and mips16 functions" \
+	 "$o32_ld_flags" \
+	 "$o32_as_flags -mips32r2" \
+	 {mips16-intermix-1.s mips16-intermix-2.s} \
+	 {{objdump -t mips16-intermix.d}} \
+	 "mips16-intermix"]]
+
+run_ld_link_tests $mips16_intermix_test
+
+run_dump_test "mips16-local-stubs-1"
+
+run_dump_test "attr-gnu-4-00"
+run_dump_test "attr-gnu-4-01"
+run_dump_test "attr-gnu-4-02"
+run_dump_test "attr-gnu-4-03"
+run_dump_test "attr-gnu-4-04"
+run_dump_test "attr-gnu-4-05"
+run_dump_test "attr-gnu-4-10"
+run_dump_test "attr-gnu-4-11"
+run_dump_test "attr-gnu-4-12"
+run_dump_test "attr-gnu-4-13"
+run_dump_test "attr-gnu-4-14"
+run_dump_test "attr-gnu-4-15"
+run_dump_test "attr-gnu-4-20"
+run_dump_test "attr-gnu-4-21"
+run_dump_test "attr-gnu-4-22"
+run_dump_test "attr-gnu-4-23"
+run_dump_test "attr-gnu-4-24"
+run_dump_test "attr-gnu-4-25"
+run_dump_test "attr-gnu-4-30"
+run_dump_test "attr-gnu-4-31"
+run_dump_test "attr-gnu-4-32"
+run_dump_test "attr-gnu-4-33"
+run_dump_test "attr-gnu-4-34"
+run_dump_test "attr-gnu-4-35"
+run_dump_test "attr-gnu-4-40"
+run_dump_test "attr-gnu-4-41"
+run_dump_test "attr-gnu-4-42"
+run_dump_test "attr-gnu-4-43"
+run_dump_test "attr-gnu-4-44"
+run_dump_test "attr-gnu-4-45"
+run_dump_test "attr-gnu-4-51"
+
+if { $linux_gnu } {
+    run_ld_link_tests {
+	{"GOT and versioning 1"
+	 "-shared -melf32btsmip --version-script got-vers-1.ver"
+	 "-EB -mips2 -32" {got-vers-1a.s got-vers-1b.s}
+	 {{readelf -d got-vers-1.dd}
+	  {readelf --symbols got-vers-1.sd}
+	  {readelf --relocs got-vers-1.rd}}
+	 "got-vers-1.so"}
+    }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips-lib.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/mips-lib.ld
new file mode 100644
index 0000000..10b4140
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips-lib.ld
@@ -0,0 +1,218 @@
+/* Script for --shared -z combreloc: shared library, combine & sort relocs */
+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips",
+	      "elf32-tradlittlemips")
+OUTPUT_ARCH(mips)
+ENTRY(__start)
+SEARCH_DIR("=/usr/local/lib"); SEARCH_DIR("=/lib"); SEARCH_DIR("=/usr/lib");
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = 0 + SIZEOF_HEADERS;
+  .reginfo        : { *(.reginfo) }
+  .dynamic        : { *(.dynamic) }
+  .hash           : { *(.hash) }
+  .dynsym         : { *(.dynsym) }
+  .dynstr         : { *(.dynstr) }
+  .gnu.version    : { *(.gnu.version) }
+  .gnu.version_d  : { *(.gnu.version_d) }
+  .gnu.version_r  : { *(.gnu.version_r) }
+  .rel.dyn        :
+    {
+      *(.rel.init)
+      *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*)
+      *(.rel.fini)
+      *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*)
+      *(.rel.data.rel.ro*)
+      *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*)
+      *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*)
+      *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*)
+      *(.rel.ctors)
+      *(.rel.dtors)
+      *(.rel.got)
+      *(.rel.sdata .rel.sdata.* .rel.gnu.linkonce.s.*)
+      *(.rel.sbss .rel.sbss.* .rel.gnu.linkonce.sb.*)
+      *(.rel.sdata2 .rel.sdata2.* .rel.gnu.linkonce.s2.*)
+      *(.rel.sbss2 .rel.sbss2.* .rel.gnu.linkonce.sb2.*)
+      *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*)
+    }
+  .rela.dyn       :
+    {
+      *(.rela.init)
+      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+      *(.rela.fini)
+      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+      *(.rela.ctors)
+      *(.rela.dtors)
+      *(.rela.got)
+      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+    }
+  .rel.plt        : { *(.rel.plt) }
+  .rela.plt       : { *(.rela.plt) }
+  .init           :
+  {
+    KEEP (*(.init))
+  } =0
+  .plt            : { *(.plt) }
+  .text           :
+  {
+    _ftext = . ;
+    *(.text .stub .text.* .gnu.linkonce.t.*)
+    KEEP (*(.text.*personality*))
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.mips16.fn.*) *(.mips16.call.*)
+  } =0
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } =0
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+  .rodata         : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
+  .rodata1        : { *(.rodata1) }
+  .eh_frame_hdr : { *(.eh_frame_hdr) }
+  .eh_frame       : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN (0x40000) - ((0x40000 - .) & (0x40000 - 1)); . = DATA_SEGMENT_ALIGN (0x40000, 0x1000);
+  /* Exception handling  */
+  .eh_frame       : ONLY_IF_RW { KEEP (*(.eh_frame)) }
+  .gcc_except_table   : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) }
+  /* Thread Local Storage sections  */
+  .tdata	  : { *(.tdata .tdata.* .gnu.linkonce.td.*) }
+  .tbss		  : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) }
+  /* Ensure the __preinit_array_start label is properly aligned.  We
+     could instead move the label definition inside the section, but
+     the linker would then create the section even if it turns out to
+     be empty, which isn't pretty.  */
+  . = ALIGN(32 / 8);
+  .preinit_array     : { KEEP (*(.preinit_array)) }
+  .init_array     : { KEEP (*(.init_array)) }
+  .fini_array     : { KEEP (*(.fini_array)) }
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin*.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  }
+  .dtors          :
+  {
+    KEEP (*crtbegin*.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  }
+  .jcr            : { KEEP (*(.jcr)) }
+  .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) }
+  . = DATA_SEGMENT_RELRO_END (0, .);
+  .data           :
+  {
+    _fdata = . ;
+    *(.data .data.* .gnu.linkonce.d.*)
+    KEEP (*(.gnu.linkonce.d.*personality*))
+    SORT(CONSTRUCTORS)
+  }
+  .data1          : { *(.data1) }
+  _gp = ALIGN(16) + 0x7ff0;
+  .got            : { *(.got.plt) *(.got) }
+  .sdata2         : { *(.sdata2 .sdata2.* .gnu.linkonce.s2.*) }
+  .sbss2          : { *(.sbss2 .sbss2.* .gnu.linkonce.sb2.*) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata          :
+  {
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+  .lit8           : { *(.lit8) }
+  .lit4           : { *(.lit4) }
+  _edata = .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  _fbss = .;
+  .sbss           :
+  {
+    PROVIDE (__sbss_start = .);
+    PROVIDE (___sbss_start = .);
+    *(.dynsbss)
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+    PROVIDE (__sbss_end = .);
+    PROVIDE (___sbss_end = .);
+  }
+  .bss            :
+  {
+   *(.dynbss)
+   *(.bss .bss.* .gnu.linkonce.b.*)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   . = ALIGN(32 / 8);
+  }
+  . = ALIGN(32 / 8);
+  _end = .;
+  PROVIDE (end = .);
+  . = DATA_SEGMENT_END (.);
+  /* Stabs debugging sections.  */
+  .stab          0 : { *(.stab) }
+  .stabstr       0 : { *(.stabstr) }
+  .stab.excl     0 : { *(.stab.excl) }
+  .stab.exclstr  0 : { *(.stab.exclstr) }
+  .stab.index    0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment       0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) }
+  .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) }
+  /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-1.d b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-1.d
new file mode 100644
index 0000000..77d1316
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-1.d
@@ -0,0 +1,9 @@
+#source: mips16-1a.s -no-mips16
+#source: mips16-1b.s -mips16
+#ld: -r
+#objdump: -pd
+
+.*:.*file format.*mips.*
+private flags = [0-9a-f]*[4-7c-f]......: .*[[,]mips16[],].*
+
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-1a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-1a.s
new file mode 100644
index 0000000..a361a65
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-1a.s
@@ -0,0 +1,2 @@
+	.text
+foo1:	jr $31
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-1b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-1b.s
new file mode 100644
index 0000000..11e36f7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-1b.s
@@ -0,0 +1,2 @@
+	.text
+foo2:	jr $31
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-call-global-1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-call-global-1.s
new file mode 100644
index 0000000..1e60bcc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-call-global-1.s
@@ -0,0 +1,12 @@
+	.set	mips16
+
+	.globl	__start
+	.ent	__start
+__start:
+	.frame	$sp,24,$31
+	save	24,$31
+	jal	x+8
+	jal	y+8
+	restore	24,$31
+	j	$31
+	.end	__start
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-call-global-2.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-call-global-2.s
new file mode 100644
index 0000000..2843fcd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-call-global-2.s
@@ -0,0 +1,8 @@
+	.set	mips16
+
+	.globl	x
+	.ent	x
+	.type	x,@function
+x:
+	jr	$31
+	.end	x
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-call-global-3.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-call-global-3.s
new file mode 100644
index 0000000..5113c5d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-call-global-3.s
@@ -0,0 +1,16 @@
+	.set	nomips16
+
+	.globl	y
+	.ent	y
+	.type	y,@function
+y:
+	jr	$31
+	.end	y
+
+	.ent	z
+	.type	z,@function
+z:
+	jr	$31
+	.end	z
+
+	.space 8
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-call-global.d b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-call-global.d
new file mode 100644
index 0000000..051ebcd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-call-global.d
@@ -0,0 +1,39 @@
+
+.*:     file format elf.*mips
+
+Disassembly of section .text:
+
+.*0090 <__start>:
+.*0090:	64c3      	save	24,ra
+.*0092:	1a00 002e 	jal	.*00b8 <x\+0x8>
+.*0096:	6500      	nop
+.*0098:	1e00 0032 	jalx	.*00c8 <z>
+.*009c:	6500      	nop
+.*009e:	6443      	restore	24,ra
+.*00a0:	e8a0      	jrc	ra
+.*00a2:	6500      	nop
+.*00a4:	6500      	nop
+.*00a6:	6500      	nop
+.*00a8:	6500      	nop
+.*00aa:	6500      	nop
+.*00ac:	6500      	nop
+.*00ae:	6500      	nop
+
+.*00b0 <x>:
+.*00b0:	e8a0      	jrc	ra
+.*00b2:	6500      	nop
+.*00b4:	6500      	nop
+.*00b6:	6500      	nop
+.*00b8:	6500      	nop
+.*00ba:	6500      	nop
+.*00bc:	6500      	nop
+.*00be:	6500      	nop
+
+.*00c0 <y>:
+.*00c0:	03e00008 	jr	ra
+.*00c4:	00000000 	nop
+
+.*00c8 <z>:
+.*00c8:	03e00008 	jr	ra
+.*00cc:	00000000 	nop
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-hilo-n32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-hilo-n32.d
new file mode 100644
index 0000000..28c2b61
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-hilo-n32.d
@@ -0,0 +1,338 @@
+#name: R_MIPS16_HI16 and R_MIPS16_LO16 relocs n32
+#source: ../../../gas/testsuite/gas/mips/mips16-hilo.s
+#source: mips16-hilo.s
+#as: -march=mips64 -mabi=n32 -EB
+#objdump: -mmips:16 --prefix-addresses -tdr --show-raw-insn
+#ld: -Tmips16-hilo.ld -e 0x500000 -N -melf32btsmipn32
+
+.*:     file format elf.*mips.*
+
+#...
+
+Disassembly of section .text:
+0+500000 <[^>]*> 6c00      	li	a0,0
+0+500002 <[^>]*> f400 3480 	sll	a0,16
+0+500006 <[^>]*> 4c00      	addiu	a0,0
+0+500008 <[^>]*> f060 6c05 	li	a0,101
+0+50000c <[^>]*> f400 3480 	sll	a0,16
+0+500010 <[^>]*> f328 4c00 	addiu	a0,17184
+0+500014 <[^>]*> f060 6c05 	li	a0,101
+0+500018 <[^>]*> f400 3480 	sll	a0,16
+0+50001c <[^>]*> f328 4c04 	addiu	a0,17188
+0+500020 <[^>]*> f060 6c05 	li	a0,101
+0+500024 <[^>]*> f400 3480 	sll	a0,16
+0+500028 <[^>]*> f328 4c10 	addiu	a0,17200
+0+50002c <[^>]*> f060 6c05 	li	a0,101
+0+500030 <[^>]*> f400 3480 	sll	a0,16
+0+500034 <[^>]*> f728 4c00 	addiu	a0,18208
+0+500038 <[^>]*> f060 6c16 	li	a0,118
+0+50003c <[^>]*> f400 3480 	sll	a0,16
+0+500040 <[^>]*> f02b 4c00 	addiu	a0,22560
+0+500044 <[^>]*> f060 6c16 	li	a0,118
+0+500048 <[^>]*> f400 3480 	sll	a0,16
+0+50004c <[^>]*> f40b 4c09 	addiu	a0,23561
+0+500050 <[^>]*> f060 6c16 	li	a0,118
+0+500054 <[^>]*> f400 3480 	sll	a0,16
+0+500058 <[^>]*> f42a 4c10 	addiu	a0,21552
+0+50005c <[^>]*> f060 6c16 	li	a0,118
+0+500060 <[^>]*> f400 3480 	sll	a0,16
+0+500064 <[^>]*> f40b 4c08 	addiu	a0,23560
+0+500068 <[^>]*> 6c00      	li	a0,0
+0+50006a <[^>]*> f400 3480 	sll	a0,16
+0+50006e <[^>]*> 4c01      	addiu	a0,1
+0+500070 <[^>]*> f060 6c05 	li	a0,101
+0+500074 <[^>]*> f400 3480 	sll	a0,16
+0+500078 <[^>]*> f328 4c01 	addiu	a0,17185
+0+50007c <[^>]*> f060 6c05 	li	a0,101
+0+500080 <[^>]*> f400 3480 	sll	a0,16
+0+500084 <[^>]*> f328 4c05 	addiu	a0,17189
+0+500088 <[^>]*> f060 6c05 	li	a0,101
+0+50008c <[^>]*> f400 3480 	sll	a0,16
+0+500090 <[^>]*> f328 4c11 	addiu	a0,17201
+0+500094 <[^>]*> f060 6c05 	li	a0,101
+0+500098 <[^>]*> f400 3480 	sll	a0,16
+0+50009c <[^>]*> f728 4c01 	addiu	a0,18209
+0+5000a0 <[^>]*> f060 6c16 	li	a0,118
+0+5000a4 <[^>]*> f400 3480 	sll	a0,16
+0+5000a8 <[^>]*> f02b 4c01 	addiu	a0,22561
+0+5000ac <[^>]*> f060 6c16 	li	a0,118
+0+5000b0 <[^>]*> f400 3480 	sll	a0,16
+0+5000b4 <[^>]*> f40b 4c0a 	addiu	a0,23562
+0+5000b8 <[^>]*> f060 6c16 	li	a0,118
+0+5000bc <[^>]*> f400 3480 	sll	a0,16
+0+5000c0 <[^>]*> f42a 4c11 	addiu	a0,21553
+0+5000c4 <[^>]*> f060 6c16 	li	a0,118
+0+5000c8 <[^>]*> f400 3480 	sll	a0,16
+0+5000cc <[^>]*> f40b 4c09 	addiu	a0,23561
+0+5000d0 <[^>]*> 6c01      	li	a0,1
+0+5000d2 <[^>]*> f400 3480 	sll	a0,16
+0+5000d6 <[^>]*> f010 4c00 	addiu	a0,-32768
+0+5000da <[^>]*> f060 6c06 	li	a0,102
+0+5000de <[^>]*> f400 3480 	sll	a0,16
+0+5000e2 <[^>]*> f338 4c00 	addiu	a0,-15584
+0+5000e6 <[^>]*> f060 6c06 	li	a0,102
+0+5000ea <[^>]*> f400 3480 	sll	a0,16
+0+5000ee <[^>]*> f338 4c04 	addiu	a0,-15580
+0+5000f2 <[^>]*> f060 6c06 	li	a0,102
+0+5000f6 <[^>]*> f400 3480 	sll	a0,16
+0+5000fa <[^>]*> f338 4c10 	addiu	a0,-15568
+0+5000fe <[^>]*> f060 6c06 	li	a0,102
+0+500102 <[^>]*> f400 3480 	sll	a0,16
+0+500106 <[^>]*> f738 4c00 	addiu	a0,-14560
+0+50010a <[^>]*> f060 6c17 	li	a0,119
+0+50010e <[^>]*> f400 3480 	sll	a0,16
+0+500112 <[^>]*> f03b 4c00 	addiu	a0,-10208
+0+500116 <[^>]*> f060 6c17 	li	a0,119
+0+50011a <[^>]*> f400 3480 	sll	a0,16
+0+50011e <[^>]*> f41b 4c09 	addiu	a0,-9207
+0+500122 <[^>]*> f060 6c17 	li	a0,119
+0+500126 <[^>]*> f400 3480 	sll	a0,16
+0+50012a <[^>]*> f43a 4c10 	addiu	a0,-11216
+0+50012e <[^>]*> f060 6c17 	li	a0,119
+0+500132 <[^>]*> f400 3480 	sll	a0,16
+0+500136 <[^>]*> f41b 4c08 	addiu	a0,-9208
+0+50013a <[^>]*> 6c00      	li	a0,0
+0+50013c <[^>]*> f400 3480 	sll	a0,16
+0+500140 <[^>]*> f010 4c00 	addiu	a0,-32768
+0+500144 <[^>]*> f060 6c05 	li	a0,101
+0+500148 <[^>]*> f400 3480 	sll	a0,16
+0+50014c <[^>]*> f338 4c00 	addiu	a0,-15584
+0+500150 <[^>]*> f060 6c05 	li	a0,101
+0+500154 <[^>]*> f400 3480 	sll	a0,16
+0+500158 <[^>]*> f338 4c04 	addiu	a0,-15580
+0+50015c <[^>]*> f060 6c05 	li	a0,101
+0+500160 <[^>]*> f400 3480 	sll	a0,16
+0+500164 <[^>]*> f338 4c10 	addiu	a0,-15568
+0+500168 <[^>]*> f060 6c05 	li	a0,101
+0+50016c <[^>]*> f400 3480 	sll	a0,16
+0+500170 <[^>]*> f738 4c00 	addiu	a0,-14560
+0+500174 <[^>]*> f060 6c16 	li	a0,118
+0+500178 <[^>]*> f400 3480 	sll	a0,16
+0+50017c <[^>]*> f03b 4c00 	addiu	a0,-10208
+0+500180 <[^>]*> f060 6c16 	li	a0,118
+0+500184 <[^>]*> f400 3480 	sll	a0,16
+0+500188 <[^>]*> f41b 4c09 	addiu	a0,-9207
+0+50018c <[^>]*> f060 6c16 	li	a0,118
+0+500190 <[^>]*> f400 3480 	sll	a0,16
+0+500194 <[^>]*> f43a 4c10 	addiu	a0,-11216
+0+500198 <[^>]*> f060 6c16 	li	a0,118
+0+50019c <[^>]*> f400 3480 	sll	a0,16
+0+5001a0 <[^>]*> f41b 4c08 	addiu	a0,-9208
+0+5001a4 <[^>]*> 6c01      	li	a0,1
+0+5001a6 <[^>]*> f400 3480 	sll	a0,16
+0+5001aa <[^>]*> 4c00      	addiu	a0,0
+0+5001ac <[^>]*> f060 6c06 	li	a0,102
+0+5001b0 <[^>]*> f400 3480 	sll	a0,16
+0+5001b4 <[^>]*> f328 4c00 	addiu	a0,17184
+0+5001b8 <[^>]*> f060 6c06 	li	a0,102
+0+5001bc <[^>]*> f400 3480 	sll	a0,16
+0+5001c0 <[^>]*> f328 4c04 	addiu	a0,17188
+0+5001c4 <[^>]*> f060 6c06 	li	a0,102
+0+5001c8 <[^>]*> f400 3480 	sll	a0,16
+0+5001cc <[^>]*> f328 4c10 	addiu	a0,17200
+0+5001d0 <[^>]*> f060 6c06 	li	a0,102
+0+5001d4 <[^>]*> f400 3480 	sll	a0,16
+0+5001d8 <[^>]*> f728 4c00 	addiu	a0,18208
+0+5001dc <[^>]*> f060 6c17 	li	a0,119
+0+5001e0 <[^>]*> f400 3480 	sll	a0,16
+0+5001e4 <[^>]*> f02b 4c00 	addiu	a0,22560
+0+5001e8 <[^>]*> f060 6c17 	li	a0,119
+0+5001ec <[^>]*> f400 3480 	sll	a0,16
+0+5001f0 <[^>]*> f40b 4c09 	addiu	a0,23561
+0+5001f4 <[^>]*> f060 6c17 	li	a0,119
+0+5001f8 <[^>]*> f400 3480 	sll	a0,16
+0+5001fc <[^>]*> f42a 4c10 	addiu	a0,21552
+0+500200 <[^>]*> f060 6c17 	li	a0,119
+0+500204 <[^>]*> f400 3480 	sll	a0,16
+0+500208 <[^>]*> f40b 4c08 	addiu	a0,23560
+0+50020c <[^>]*> 6c02      	li	a0,2
+0+50020e <[^>]*> f400 3480 	sll	a0,16
+0+500212 <[^>]*> f5b4 4c05 	addiu	a0,-23131
+0+500216 <[^>]*> f060 6c07 	li	a0,103
+0+50021a <[^>]*> f400 3480 	sll	a0,16
+0+50021e <[^>]*> f0dd 4c05 	addiu	a0,-5947
+0+500222 <[^>]*> f060 6c07 	li	a0,103
+0+500226 <[^>]*> f400 3480 	sll	a0,16
+0+50022a <[^>]*> f0dd 4c09 	addiu	a0,-5943
+0+50022e <[^>]*> f060 6c07 	li	a0,103
+0+500232 <[^>]*> f400 3480 	sll	a0,16
+0+500236 <[^>]*> f0dd 4c15 	addiu	a0,-5931
+0+50023a <[^>]*> f060 6c07 	li	a0,103
+0+50023e <[^>]*> f400 3480 	sll	a0,16
+0+500242 <[^>]*> f4dd 4c05 	addiu	a0,-4923
+0+500246 <[^>]*> f060 6c18 	li	a0,120
+0+50024a <[^>]*> f400 3480 	sll	a0,16
+0+50024e <[^>]*> f5df 4c05 	addiu	a0,-571
+0+500252 <[^>]*> f060 6c18 	li	a0,120
+0+500256 <[^>]*> f400 3480 	sll	a0,16
+0+50025a <[^>]*> f1a0 4c0e 	addiu	a0,430
+0+50025e <[^>]*> f060 6c18 	li	a0,120
+0+500262 <[^>]*> f400 3480 	sll	a0,16
+0+500266 <[^>]*> f1df 4c15 	addiu	a0,-1579
+0+50026a <[^>]*> f060 6c18 	li	a0,120
+0+50026e <[^>]*> f400 3480 	sll	a0,16
+0+500272 <[^>]*> f1a0 4c0d 	addiu	a0,429
+0+500276 <[^>]*> 6d00      	li	a1,0
+0+500278 <[^>]*> f400 35a0 	sll	a1,16
+0+50027c <[^>]*> 9d80      	lw	a0,0\(a1\)
+0+50027e <[^>]*> f060 6d05 	li	a1,101
+0+500282 <[^>]*> f400 35a0 	sll	a1,16
+0+500286 <[^>]*> f060 9d85 	lw	a0,101\(a1\)
+0+50028a <[^>]*> f060 6d05 	li	a1,101
+0+50028e <[^>]*> f400 35a0 	sll	a1,16
+0+500292 <[^>]*> f060 9d85 	lw	a0,101\(a1\)
+0+500296 <[^>]*> f060 6d05 	li	a1,101
+0+50029a <[^>]*> f400 35a0 	sll	a1,16
+0+50029e <[^>]*> f328 9d90 	lw	a0,17200\(a1\)
+0+5002a2 <[^>]*> f060 6d05 	li	a1,101
+0+5002a6 <[^>]*> f400 35a0 	sll	a1,16
+0+5002aa <[^>]*> f728 9d80 	lw	a0,18208\(a1\)
+0+5002ae <[^>]*> f060 6d16 	li	a1,118
+0+5002b2 <[^>]*> f400 35a0 	sll	a1,16
+0+5002b6 <[^>]*> f02b 9d80 	lw	a0,22560\(a1\)
+0+5002ba <[^>]*> f060 6d16 	li	a1,118
+0+5002be <[^>]*> f400 35a0 	sll	a1,16
+0+5002c2 <[^>]*> f40b 9d89 	lw	a0,23561\(a1\)
+0+5002c6 <[^>]*> f060 6d16 	li	a1,118
+0+5002ca <[^>]*> f400 35a0 	sll	a1,16
+0+5002ce <[^>]*> f42a 9d90 	lw	a0,21552\(a1\)
+0+5002d2 <[^>]*> f060 6d16 	li	a1,118
+0+5002d6 <[^>]*> f400 35a0 	sll	a1,16
+0+5002da <[^>]*> f40b 9d88 	lw	a0,23560\(a1\)
+0+5002de <[^>]*> 6d00      	li	a1,0
+0+5002e0 <[^>]*> f400 35a0 	sll	a1,16
+0+5002e4 <[^>]*> f000 9d81 	lw	a0,1\(a1\)
+0+5002e8 <[^>]*> f060 6d05 	li	a1,101
+0+5002ec <[^>]*> f400 35a0 	sll	a1,16
+0+5002f0 <[^>]*> f328 9d81 	lw	a0,17185\(a1\)
+0+5002f4 <[^>]*> f060 6d05 	li	a1,101
+0+5002f8 <[^>]*> f400 35a0 	sll	a1,16
+0+5002fc <[^>]*> f328 9d85 	lw	a0,17189\(a1\)
+0+500300 <[^>]*> f060 6d05 	li	a1,101
+0+500304 <[^>]*> f400 35a0 	sll	a1,16
+0+500308 <[^>]*> f328 9d91 	lw	a0,17201\(a1\)
+0+50030c <[^>]*> f060 6d05 	li	a1,101
+0+500310 <[^>]*> f400 35a0 	sll	a1,16
+0+500314 <[^>]*> f728 9d81 	lw	a0,18209\(a1\)
+0+500318 <[^>]*> f060 6d16 	li	a1,118
+0+50031c <[^>]*> f400 35a0 	sll	a1,16
+0+500320 <[^>]*> f02b 9d81 	lw	a0,22561\(a1\)
+0+500324 <[^>]*> f060 6d16 	li	a1,118
+0+500328 <[^>]*> f400 35a0 	sll	a1,16
+0+50032c <[^>]*> f40b 9d8a 	lw	a0,23562\(a1\)
+0+500330 <[^>]*> f060 6d16 	li	a1,118
+0+500334 <[^>]*> f400 35a0 	sll	a1,16
+0+500338 <[^>]*> f42a 9d91 	lw	a0,21553\(a1\)
+0+50033c <[^>]*> f060 6d16 	li	a1,118
+0+500340 <[^>]*> f400 35a0 	sll	a1,16
+0+500344 <[^>]*> f40b 9d89 	lw	a0,23561\(a1\)
+0+500348 <[^>]*> 6d01      	li	a1,1
+0+50034a <[^>]*> f400 35a0 	sll	a1,16
+0+50034e <[^>]*> f010 9d80 	lw	a0,-32768\(a1\)
+0+500352 <[^>]*> f060 6d06 	li	a1,102
+0+500356 <[^>]*> f400 35a0 	sll	a1,16
+0+50035a <[^>]*> f338 9d80 	lw	a0,-15584\(a1\)
+0+50035e <[^>]*> f060 6d06 	li	a1,102
+0+500362 <[^>]*> f400 35a0 	sll	a1,16
+0+500366 <[^>]*> f338 9d84 	lw	a0,-15580\(a1\)
+0+50036a <[^>]*> f060 6d06 	li	a1,102
+0+50036e <[^>]*> f400 35a0 	sll	a1,16
+0+500372 <[^>]*> f338 9d90 	lw	a0,-15568\(a1\)
+0+500376 <[^>]*> f060 6d06 	li	a1,102
+0+50037a <[^>]*> f400 35a0 	sll	a1,16
+0+50037e <[^>]*> f738 9d80 	lw	a0,-14560\(a1\)
+0+500382 <[^>]*> f060 6d17 	li	a1,119
+0+500386 <[^>]*> f400 35a0 	sll	a1,16
+0+50038a <[^>]*> f03b 9d80 	lw	a0,-10208\(a1\)
+0+50038e <[^>]*> f060 6d17 	li	a1,119
+0+500392 <[^>]*> f400 35a0 	sll	a1,16
+0+500396 <[^>]*> f41b 9d89 	lw	a0,-9207\(a1\)
+0+50039a <[^>]*> f060 6d17 	li	a1,119
+0+50039e <[^>]*> f400 35a0 	sll	a1,16
+0+5003a2 <[^>]*> f43a 9d90 	lw	a0,-11216\(a1\)
+0+5003a6 <[^>]*> f060 6d17 	li	a1,119
+0+5003aa <[^>]*> f400 35a0 	sll	a1,16
+0+5003ae <[^>]*> f41b 9d88 	lw	a0,-9208\(a1\)
+0+5003b2 <[^>]*> 6d00      	li	a1,0
+0+5003b4 <[^>]*> f400 35a0 	sll	a1,16
+0+5003b8 <[^>]*> f010 9d80 	lw	a0,-32768\(a1\)
+0+5003bc <[^>]*> f060 6d05 	li	a1,101
+0+5003c0 <[^>]*> f400 35a0 	sll	a1,16
+0+5003c4 <[^>]*> f338 9d80 	lw	a0,-15584\(a1\)
+0+5003c8 <[^>]*> f060 6d05 	li	a1,101
+0+5003cc <[^>]*> f400 35a0 	sll	a1,16
+0+5003d0 <[^>]*> f338 9d84 	lw	a0,-15580\(a1\)
+0+5003d4 <[^>]*> f060 6d05 	li	a1,101
+0+5003d8 <[^>]*> f400 35a0 	sll	a1,16
+0+5003dc <[^>]*> f338 9d90 	lw	a0,-15568\(a1\)
+0+5003e0 <[^>]*> f060 6d05 	li	a1,101
+0+5003e4 <[^>]*> f400 35a0 	sll	a1,16
+0+5003e8 <[^>]*> f738 9d80 	lw	a0,-14560\(a1\)
+0+5003ec <[^>]*> f060 6d16 	li	a1,118
+0+5003f0 <[^>]*> f400 35a0 	sll	a1,16
+0+5003f4 <[^>]*> f03b 9d80 	lw	a0,-10208\(a1\)
+0+5003f8 <[^>]*> f060 6d16 	li	a1,118
+0+5003fc <[^>]*> f400 35a0 	sll	a1,16
+0+500400 <[^>]*> f41b 9d89 	lw	a0,-9207\(a1\)
+0+500404 <[^>]*> f060 6d16 	li	a1,118
+0+500408 <[^>]*> f400 35a0 	sll	a1,16
+0+50040c <[^>]*> f43a 9d90 	lw	a0,-11216\(a1\)
+0+500410 <[^>]*> f060 6d16 	li	a1,118
+0+500414 <[^>]*> f400 35a0 	sll	a1,16
+0+500418 <[^>]*> f41b 9d88 	lw	a0,-9208\(a1\)
+0+50041c <[^>]*> 6d01      	li	a1,1
+0+50041e <[^>]*> f400 35a0 	sll	a1,16
+0+500422 <[^>]*> 9d80      	lw	a0,0\(a1\)
+0+500424 <[^>]*> f060 6d06 	li	a1,102
+0+500428 <[^>]*> f400 35a0 	sll	a1,16
+0+50042c <[^>]*> f328 9d80 	lw	a0,17184\(a1\)
+0+500430 <[^>]*> f060 6d06 	li	a1,102
+0+500434 <[^>]*> f400 35a0 	sll	a1,16
+0+500438 <[^>]*> f328 9d84 	lw	a0,17188\(a1\)
+0+50043c <[^>]*> f060 6d06 	li	a1,102
+0+500440 <[^>]*> f400 35a0 	sll	a1,16
+0+500444 <[^>]*> f328 9d90 	lw	a0,17200\(a1\)
+0+500448 <[^>]*> f060 6d06 	li	a1,102
+0+50044c <[^>]*> f400 35a0 	sll	a1,16
+0+500450 <[^>]*> f728 9d80 	lw	a0,18208\(a1\)
+0+500454 <[^>]*> f060 6d17 	li	a1,119
+0+500458 <[^>]*> f400 35a0 	sll	a1,16
+0+50045c <[^>]*> f02b 9d80 	lw	a0,22560\(a1\)
+0+500460 <[^>]*> f060 6d17 	li	a1,119
+0+500464 <[^>]*> f400 35a0 	sll	a1,16
+0+500468 <[^>]*> f40b 9d89 	lw	a0,23561\(a1\)
+0+50046c <[^>]*> f060 6d17 	li	a1,119
+0+500470 <[^>]*> f400 35a0 	sll	a1,16
+0+500474 <[^>]*> f42a 9d90 	lw	a0,21552\(a1\)
+0+500478 <[^>]*> f060 6d17 	li	a1,119
+0+50047c <[^>]*> f400 35a0 	sll	a1,16
+0+500480 <[^>]*> f40b 9d88 	lw	a0,23560\(a1\)
+0+500484 <[^>]*> 6d02      	li	a1,2
+0+500486 <[^>]*> f400 35a0 	sll	a1,16
+0+50048a <[^>]*> f5b4 9d85 	lw	a0,-23131\(a1\)
+0+50048e <[^>]*> f060 6d07 	li	a1,103
+0+500492 <[^>]*> f400 35a0 	sll	a1,16
+0+500496 <[^>]*> f0dd 9d85 	lw	a0,-5947\(a1\)
+0+50049a <[^>]*> f060 6d07 	li	a1,103
+0+50049e <[^>]*> f400 35a0 	sll	a1,16
+0+5004a2 <[^>]*> f0dd 9d89 	lw	a0,-5943\(a1\)
+0+5004a6 <[^>]*> f060 6d07 	li	a1,103
+0+5004aa <[^>]*> f400 35a0 	sll	a1,16
+0+5004ae <[^>]*> f0dd 9d95 	lw	a0,-5931\(a1\)
+0+5004b2 <[^>]*> f060 6d07 	li	a1,103
+0+5004b6 <[^>]*> f400 35a0 	sll	a1,16
+0+5004ba <[^>]*> f4dd 9d85 	lw	a0,-4923\(a1\)
+0+5004be <[^>]*> f060 6d18 	li	a1,120
+0+5004c2 <[^>]*> f400 35a0 	sll	a1,16
+0+5004c6 <[^>]*> f5df 9d85 	lw	a0,-571\(a1\)
+0+5004ca <[^>]*> f060 6d18 	li	a1,120
+0+5004ce <[^>]*> f400 35a0 	sll	a1,16
+0+5004d2 <[^>]*> f1a0 9d8e 	lw	a0,430\(a1\)
+0+5004d6 <[^>]*> f060 6d18 	li	a1,120
+0+5004da <[^>]*> f400 35a0 	sll	a1,16
+0+5004de <[^>]*> f1df 9d95 	lw	a0,-1579\(a1\)
+0+5004e2 <[^>]*> f060 6d18 	li	a1,120
+0+5004e6 <[^>]*> f400 35a0 	sll	a1,16
+0+5004ea <[^>]*> f1a0 9d8d 	lw	a0,429\(a1\)
+0+5004ee <[^>]*> 6500      	nop
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-hilo.d b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-hilo.d
new file mode 100644
index 0000000..5600983
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-hilo.d
@@ -0,0 +1,337 @@
+#name: R_MIPS16_HI16 and R_MIPS16_LO16 relocs
+#source: ../../../gas/testsuite/gas/mips/mips16-hilo.s
+#source: mips16-hilo.s
+#objdump: -mmips:16 --prefix-addresses -tdr --show-raw-insn
+#ld: -Tmips16-hilo.ld -e 0x500000 -N
+
+.*:     file format elf.*mips.*
+
+#...
+
+Disassembly of section .text:
+0+500000 <[^>]*> 6c00      	li	a0,0
+0+500002 <[^>]*> f400 3480 	sll	a0,16
+0+500006 <[^>]*> 4c00      	addiu	a0,0
+0+500008 <[^>]*> f060 6c05 	li	a0,101
+0+50000c <[^>]*> f400 3480 	sll	a0,16
+0+500010 <[^>]*> f328 4c00 	addiu	a0,17184
+0+500014 <[^>]*> f060 6c05 	li	a0,101
+0+500018 <[^>]*> f400 3480 	sll	a0,16
+0+50001c <[^>]*> f328 4c04 	addiu	a0,17188
+0+500020 <[^>]*> f060 6c05 	li	a0,101
+0+500024 <[^>]*> f400 3480 	sll	a0,16
+0+500028 <[^>]*> f328 4c10 	addiu	a0,17200
+0+50002c <[^>]*> f060 6c05 	li	a0,101
+0+500030 <[^>]*> f400 3480 	sll	a0,16
+0+500034 <[^>]*> f728 4c00 	addiu	a0,18208
+0+500038 <[^>]*> f060 6c16 	li	a0,118
+0+50003c <[^>]*> f400 3480 	sll	a0,16
+0+500040 <[^>]*> f02b 4c00 	addiu	a0,22560
+0+500044 <[^>]*> f060 6c16 	li	a0,118
+0+500048 <[^>]*> f400 3480 	sll	a0,16
+0+50004c <[^>]*> f40b 4c09 	addiu	a0,23561
+0+500050 <[^>]*> f060 6c16 	li	a0,118
+0+500054 <[^>]*> f400 3480 	sll	a0,16
+0+500058 <[^>]*> f42a 4c10 	addiu	a0,21552
+0+50005c <[^>]*> f060 6c16 	li	a0,118
+0+500060 <[^>]*> f400 3480 	sll	a0,16
+0+500064 <[^>]*> f40b 4c08 	addiu	a0,23560
+0+500068 <[^>]*> 6c00      	li	a0,0
+0+50006a <[^>]*> f400 3480 	sll	a0,16
+0+50006e <[^>]*> 4c01      	addiu	a0,1
+0+500070 <[^>]*> f060 6c05 	li	a0,101
+0+500074 <[^>]*> f400 3480 	sll	a0,16
+0+500078 <[^>]*> f328 4c01 	addiu	a0,17185
+0+50007c <[^>]*> f060 6c05 	li	a0,101
+0+500080 <[^>]*> f400 3480 	sll	a0,16
+0+500084 <[^>]*> f328 4c05 	addiu	a0,17189
+0+500088 <[^>]*> f060 6c05 	li	a0,101
+0+50008c <[^>]*> f400 3480 	sll	a0,16
+0+500090 <[^>]*> f328 4c11 	addiu	a0,17201
+0+500094 <[^>]*> f060 6c05 	li	a0,101
+0+500098 <[^>]*> f400 3480 	sll	a0,16
+0+50009c <[^>]*> f728 4c01 	addiu	a0,18209
+0+5000a0 <[^>]*> f060 6c16 	li	a0,118
+0+5000a4 <[^>]*> f400 3480 	sll	a0,16
+0+5000a8 <[^>]*> f02b 4c01 	addiu	a0,22561
+0+5000ac <[^>]*> f060 6c16 	li	a0,118
+0+5000b0 <[^>]*> f400 3480 	sll	a0,16
+0+5000b4 <[^>]*> f40b 4c0a 	addiu	a0,23562
+0+5000b8 <[^>]*> f060 6c16 	li	a0,118
+0+5000bc <[^>]*> f400 3480 	sll	a0,16
+0+5000c0 <[^>]*> f42a 4c11 	addiu	a0,21553
+0+5000c4 <[^>]*> f060 6c16 	li	a0,118
+0+5000c8 <[^>]*> f400 3480 	sll	a0,16
+0+5000cc <[^>]*> f40b 4c09 	addiu	a0,23561
+0+5000d0 <[^>]*> 6c01      	li	a0,1
+0+5000d2 <[^>]*> f400 3480 	sll	a0,16
+0+5000d6 <[^>]*> f010 4c00 	addiu	a0,-32768
+0+5000da <[^>]*> f060 6c06 	li	a0,102
+0+5000de <[^>]*> f400 3480 	sll	a0,16
+0+5000e2 <[^>]*> f338 4c00 	addiu	a0,-15584
+0+5000e6 <[^>]*> f060 6c06 	li	a0,102
+0+5000ea <[^>]*> f400 3480 	sll	a0,16
+0+5000ee <[^>]*> f338 4c04 	addiu	a0,-15580
+0+5000f2 <[^>]*> f060 6c06 	li	a0,102
+0+5000f6 <[^>]*> f400 3480 	sll	a0,16
+0+5000fa <[^>]*> f338 4c10 	addiu	a0,-15568
+0+5000fe <[^>]*> f060 6c06 	li	a0,102
+0+500102 <[^>]*> f400 3480 	sll	a0,16
+0+500106 <[^>]*> f738 4c00 	addiu	a0,-14560
+0+50010a <[^>]*> f060 6c17 	li	a0,119
+0+50010e <[^>]*> f400 3480 	sll	a0,16
+0+500112 <[^>]*> f03b 4c00 	addiu	a0,-10208
+0+500116 <[^>]*> f060 6c17 	li	a0,119
+0+50011a <[^>]*> f400 3480 	sll	a0,16
+0+50011e <[^>]*> f41b 4c09 	addiu	a0,-9207
+0+500122 <[^>]*> f060 6c17 	li	a0,119
+0+500126 <[^>]*> f400 3480 	sll	a0,16
+0+50012a <[^>]*> f43a 4c10 	addiu	a0,-11216
+0+50012e <[^>]*> f060 6c17 	li	a0,119
+0+500132 <[^>]*> f400 3480 	sll	a0,16
+0+500136 <[^>]*> f41b 4c08 	addiu	a0,-9208
+0+50013a <[^>]*> 6c00      	li	a0,0
+0+50013c <[^>]*> f400 3480 	sll	a0,16
+0+500140 <[^>]*> f010 4c00 	addiu	a0,-32768
+0+500144 <[^>]*> f060 6c05 	li	a0,101
+0+500148 <[^>]*> f400 3480 	sll	a0,16
+0+50014c <[^>]*> f338 4c00 	addiu	a0,-15584
+0+500150 <[^>]*> f060 6c05 	li	a0,101
+0+500154 <[^>]*> f400 3480 	sll	a0,16
+0+500158 <[^>]*> f338 4c04 	addiu	a0,-15580
+0+50015c <[^>]*> f060 6c05 	li	a0,101
+0+500160 <[^>]*> f400 3480 	sll	a0,16
+0+500164 <[^>]*> f338 4c10 	addiu	a0,-15568
+0+500168 <[^>]*> f060 6c05 	li	a0,101
+0+50016c <[^>]*> f400 3480 	sll	a0,16
+0+500170 <[^>]*> f738 4c00 	addiu	a0,-14560
+0+500174 <[^>]*> f060 6c16 	li	a0,118
+0+500178 <[^>]*> f400 3480 	sll	a0,16
+0+50017c <[^>]*> f03b 4c00 	addiu	a0,-10208
+0+500180 <[^>]*> f060 6c16 	li	a0,118
+0+500184 <[^>]*> f400 3480 	sll	a0,16
+0+500188 <[^>]*> f41b 4c09 	addiu	a0,-9207
+0+50018c <[^>]*> f060 6c16 	li	a0,118
+0+500190 <[^>]*> f400 3480 	sll	a0,16
+0+500194 <[^>]*> f43a 4c10 	addiu	a0,-11216
+0+500198 <[^>]*> f060 6c16 	li	a0,118
+0+50019c <[^>]*> f400 3480 	sll	a0,16
+0+5001a0 <[^>]*> f41b 4c08 	addiu	a0,-9208
+0+5001a4 <[^>]*> 6c01      	li	a0,1
+0+5001a6 <[^>]*> f400 3480 	sll	a0,16
+0+5001aa <[^>]*> 4c00      	addiu	a0,0
+0+5001ac <[^>]*> f060 6c06 	li	a0,102
+0+5001b0 <[^>]*> f400 3480 	sll	a0,16
+0+5001b4 <[^>]*> f328 4c00 	addiu	a0,17184
+0+5001b8 <[^>]*> f060 6c06 	li	a0,102
+0+5001bc <[^>]*> f400 3480 	sll	a0,16
+0+5001c0 <[^>]*> f328 4c04 	addiu	a0,17188
+0+5001c4 <[^>]*> f060 6c06 	li	a0,102
+0+5001c8 <[^>]*> f400 3480 	sll	a0,16
+0+5001cc <[^>]*> f328 4c10 	addiu	a0,17200
+0+5001d0 <[^>]*> f060 6c06 	li	a0,102
+0+5001d4 <[^>]*> f400 3480 	sll	a0,16
+0+5001d8 <[^>]*> f728 4c00 	addiu	a0,18208
+0+5001dc <[^>]*> f060 6c17 	li	a0,119
+0+5001e0 <[^>]*> f400 3480 	sll	a0,16
+0+5001e4 <[^>]*> f02b 4c00 	addiu	a0,22560
+0+5001e8 <[^>]*> f060 6c17 	li	a0,119
+0+5001ec <[^>]*> f400 3480 	sll	a0,16
+0+5001f0 <[^>]*> f40b 4c09 	addiu	a0,23561
+0+5001f4 <[^>]*> f060 6c17 	li	a0,119
+0+5001f8 <[^>]*> f400 3480 	sll	a0,16
+0+5001fc <[^>]*> f42a 4c10 	addiu	a0,21552
+0+500200 <[^>]*> f060 6c17 	li	a0,119
+0+500204 <[^>]*> f400 3480 	sll	a0,16
+0+500208 <[^>]*> f40b 4c08 	addiu	a0,23560
+0+50020c <[^>]*> 6c02      	li	a0,2
+0+50020e <[^>]*> f400 3480 	sll	a0,16
+0+500212 <[^>]*> f5b4 4c05 	addiu	a0,-23131
+0+500216 <[^>]*> f060 6c07 	li	a0,103
+0+50021a <[^>]*> f400 3480 	sll	a0,16
+0+50021e <[^>]*> f0dd 4c05 	addiu	a0,-5947
+0+500222 <[^>]*> f060 6c07 	li	a0,103
+0+500226 <[^>]*> f400 3480 	sll	a0,16
+0+50022a <[^>]*> f0dd 4c09 	addiu	a0,-5943
+0+50022e <[^>]*> f060 6c07 	li	a0,103
+0+500232 <[^>]*> f400 3480 	sll	a0,16
+0+500236 <[^>]*> f0dd 4c15 	addiu	a0,-5931
+0+50023a <[^>]*> f060 6c07 	li	a0,103
+0+50023e <[^>]*> f400 3480 	sll	a0,16
+0+500242 <[^>]*> f4dd 4c05 	addiu	a0,-4923
+0+500246 <[^>]*> f060 6c18 	li	a0,120
+0+50024a <[^>]*> f400 3480 	sll	a0,16
+0+50024e <[^>]*> f5df 4c05 	addiu	a0,-571
+0+500252 <[^>]*> f060 6c18 	li	a0,120
+0+500256 <[^>]*> f400 3480 	sll	a0,16
+0+50025a <[^>]*> f1a0 4c0e 	addiu	a0,430
+0+50025e <[^>]*> f060 6c18 	li	a0,120
+0+500262 <[^>]*> f400 3480 	sll	a0,16
+0+500266 <[^>]*> f1df 4c15 	addiu	a0,-1579
+0+50026a <[^>]*> f060 6c18 	li	a0,120
+0+50026e <[^>]*> f400 3480 	sll	a0,16
+0+500272 <[^>]*> f1a0 4c0d 	addiu	a0,429
+0+500276 <[^>]*> 6d00      	li	a1,0
+0+500278 <[^>]*> f400 35a0 	sll	a1,16
+0+50027c <[^>]*> 9d80      	lw	a0,0\(a1\)
+0+50027e <[^>]*> f060 6d05 	li	a1,101
+0+500282 <[^>]*> f400 35a0 	sll	a1,16
+0+500286 <[^>]*> f060 9d85 	lw	a0,101\(a1\)
+0+50028a <[^>]*> f060 6d05 	li	a1,101
+0+50028e <[^>]*> f400 35a0 	sll	a1,16
+0+500292 <[^>]*> f060 9d85 	lw	a0,101\(a1\)
+0+500296 <[^>]*> f060 6d05 	li	a1,101
+0+50029a <[^>]*> f400 35a0 	sll	a1,16
+0+50029e <[^>]*> f328 9d90 	lw	a0,17200\(a1\)
+0+5002a2 <[^>]*> f060 6d05 	li	a1,101
+0+5002a6 <[^>]*> f400 35a0 	sll	a1,16
+0+5002aa <[^>]*> f728 9d80 	lw	a0,18208\(a1\)
+0+5002ae <[^>]*> f060 6d16 	li	a1,118
+0+5002b2 <[^>]*> f400 35a0 	sll	a1,16
+0+5002b6 <[^>]*> f02b 9d80 	lw	a0,22560\(a1\)
+0+5002ba <[^>]*> f060 6d16 	li	a1,118
+0+5002be <[^>]*> f400 35a0 	sll	a1,16
+0+5002c2 <[^>]*> f40b 9d89 	lw	a0,23561\(a1\)
+0+5002c6 <[^>]*> f060 6d16 	li	a1,118
+0+5002ca <[^>]*> f400 35a0 	sll	a1,16
+0+5002ce <[^>]*> f42a 9d90 	lw	a0,21552\(a1\)
+0+5002d2 <[^>]*> f060 6d16 	li	a1,118
+0+5002d6 <[^>]*> f400 35a0 	sll	a1,16
+0+5002da <[^>]*> f40b 9d88 	lw	a0,23560\(a1\)
+0+5002de <[^>]*> 6d00      	li	a1,0
+0+5002e0 <[^>]*> f400 35a0 	sll	a1,16
+0+5002e4 <[^>]*> f000 9d81 	lw	a0,1\(a1\)
+0+5002e8 <[^>]*> f060 6d05 	li	a1,101
+0+5002ec <[^>]*> f400 35a0 	sll	a1,16
+0+5002f0 <[^>]*> f328 9d81 	lw	a0,17185\(a1\)
+0+5002f4 <[^>]*> f060 6d05 	li	a1,101
+0+5002f8 <[^>]*> f400 35a0 	sll	a1,16
+0+5002fc <[^>]*> f328 9d85 	lw	a0,17189\(a1\)
+0+500300 <[^>]*> f060 6d05 	li	a1,101
+0+500304 <[^>]*> f400 35a0 	sll	a1,16
+0+500308 <[^>]*> f328 9d91 	lw	a0,17201\(a1\)
+0+50030c <[^>]*> f060 6d05 	li	a1,101
+0+500310 <[^>]*> f400 35a0 	sll	a1,16
+0+500314 <[^>]*> f728 9d81 	lw	a0,18209\(a1\)
+0+500318 <[^>]*> f060 6d16 	li	a1,118
+0+50031c <[^>]*> f400 35a0 	sll	a1,16
+0+500320 <[^>]*> f02b 9d81 	lw	a0,22561\(a1\)
+0+500324 <[^>]*> f060 6d16 	li	a1,118
+0+500328 <[^>]*> f400 35a0 	sll	a1,16
+0+50032c <[^>]*> f40b 9d8a 	lw	a0,23562\(a1\)
+0+500330 <[^>]*> f060 6d16 	li	a1,118
+0+500334 <[^>]*> f400 35a0 	sll	a1,16
+0+500338 <[^>]*> f42a 9d91 	lw	a0,21553\(a1\)
+0+50033c <[^>]*> f060 6d16 	li	a1,118
+0+500340 <[^>]*> f400 35a0 	sll	a1,16
+0+500344 <[^>]*> f40b 9d89 	lw	a0,23561\(a1\)
+0+500348 <[^>]*> 6d01      	li	a1,1
+0+50034a <[^>]*> f400 35a0 	sll	a1,16
+0+50034e <[^>]*> f010 9d80 	lw	a0,-32768\(a1\)
+0+500352 <[^>]*> f060 6d06 	li	a1,102
+0+500356 <[^>]*> f400 35a0 	sll	a1,16
+0+50035a <[^>]*> f338 9d80 	lw	a0,-15584\(a1\)
+0+50035e <[^>]*> f060 6d06 	li	a1,102
+0+500362 <[^>]*> f400 35a0 	sll	a1,16
+0+500366 <[^>]*> f338 9d84 	lw	a0,-15580\(a1\)
+0+50036a <[^>]*> f060 6d06 	li	a1,102
+0+50036e <[^>]*> f400 35a0 	sll	a1,16
+0+500372 <[^>]*> f338 9d90 	lw	a0,-15568\(a1\)
+0+500376 <[^>]*> f060 6d06 	li	a1,102
+0+50037a <[^>]*> f400 35a0 	sll	a1,16
+0+50037e <[^>]*> f738 9d80 	lw	a0,-14560\(a1\)
+0+500382 <[^>]*> f060 6d17 	li	a1,119
+0+500386 <[^>]*> f400 35a0 	sll	a1,16
+0+50038a <[^>]*> f03b 9d80 	lw	a0,-10208\(a1\)
+0+50038e <[^>]*> f060 6d17 	li	a1,119
+0+500392 <[^>]*> f400 35a0 	sll	a1,16
+0+500396 <[^>]*> f41b 9d89 	lw	a0,-9207\(a1\)
+0+50039a <[^>]*> f060 6d17 	li	a1,119
+0+50039e <[^>]*> f400 35a0 	sll	a1,16
+0+5003a2 <[^>]*> f43a 9d90 	lw	a0,-11216\(a1\)
+0+5003a6 <[^>]*> f060 6d17 	li	a1,119
+0+5003aa <[^>]*> f400 35a0 	sll	a1,16
+0+5003ae <[^>]*> f41b 9d88 	lw	a0,-9208\(a1\)
+0+5003b2 <[^>]*> 6d00      	li	a1,0
+0+5003b4 <[^>]*> f400 35a0 	sll	a1,16
+0+5003b8 <[^>]*> f010 9d80 	lw	a0,-32768\(a1\)
+0+5003bc <[^>]*> f060 6d05 	li	a1,101
+0+5003c0 <[^>]*> f400 35a0 	sll	a1,16
+0+5003c4 <[^>]*> f338 9d80 	lw	a0,-15584\(a1\)
+0+5003c8 <[^>]*> f060 6d05 	li	a1,101
+0+5003cc <[^>]*> f400 35a0 	sll	a1,16
+0+5003d0 <[^>]*> f338 9d84 	lw	a0,-15580\(a1\)
+0+5003d4 <[^>]*> f060 6d05 	li	a1,101
+0+5003d8 <[^>]*> f400 35a0 	sll	a1,16
+0+5003dc <[^>]*> f338 9d90 	lw	a0,-15568\(a1\)
+0+5003e0 <[^>]*> f060 6d05 	li	a1,101
+0+5003e4 <[^>]*> f400 35a0 	sll	a1,16
+0+5003e8 <[^>]*> f738 9d80 	lw	a0,-14560\(a1\)
+0+5003ec <[^>]*> f060 6d16 	li	a1,118
+0+5003f0 <[^>]*> f400 35a0 	sll	a1,16
+0+5003f4 <[^>]*> f03b 9d80 	lw	a0,-10208\(a1\)
+0+5003f8 <[^>]*> f060 6d16 	li	a1,118
+0+5003fc <[^>]*> f400 35a0 	sll	a1,16
+0+500400 <[^>]*> f41b 9d89 	lw	a0,-9207\(a1\)
+0+500404 <[^>]*> f060 6d16 	li	a1,118
+0+500408 <[^>]*> f400 35a0 	sll	a1,16
+0+50040c <[^>]*> f43a 9d90 	lw	a0,-11216\(a1\)
+0+500410 <[^>]*> f060 6d16 	li	a1,118
+0+500414 <[^>]*> f400 35a0 	sll	a1,16
+0+500418 <[^>]*> f41b 9d88 	lw	a0,-9208\(a1\)
+0+50041c <[^>]*> 6d01      	li	a1,1
+0+50041e <[^>]*> f400 35a0 	sll	a1,16
+0+500422 <[^>]*> 9d80      	lw	a0,0\(a1\)
+0+500424 <[^>]*> f060 6d06 	li	a1,102
+0+500428 <[^>]*> f400 35a0 	sll	a1,16
+0+50042c <[^>]*> f328 9d80 	lw	a0,17184\(a1\)
+0+500430 <[^>]*> f060 6d06 	li	a1,102
+0+500434 <[^>]*> f400 35a0 	sll	a1,16
+0+500438 <[^>]*> f328 9d84 	lw	a0,17188\(a1\)
+0+50043c <[^>]*> f060 6d06 	li	a1,102
+0+500440 <[^>]*> f400 35a0 	sll	a1,16
+0+500444 <[^>]*> f328 9d90 	lw	a0,17200\(a1\)
+0+500448 <[^>]*> f060 6d06 	li	a1,102
+0+50044c <[^>]*> f400 35a0 	sll	a1,16
+0+500450 <[^>]*> f728 9d80 	lw	a0,18208\(a1\)
+0+500454 <[^>]*> f060 6d17 	li	a1,119
+0+500458 <[^>]*> f400 35a0 	sll	a1,16
+0+50045c <[^>]*> f02b 9d80 	lw	a0,22560\(a1\)
+0+500460 <[^>]*> f060 6d17 	li	a1,119
+0+500464 <[^>]*> f400 35a0 	sll	a1,16
+0+500468 <[^>]*> f40b 9d89 	lw	a0,23561\(a1\)
+0+50046c <[^>]*> f060 6d17 	li	a1,119
+0+500470 <[^>]*> f400 35a0 	sll	a1,16
+0+500474 <[^>]*> f42a 9d90 	lw	a0,21552\(a1\)
+0+500478 <[^>]*> f060 6d17 	li	a1,119
+0+50047c <[^>]*> f400 35a0 	sll	a1,16
+0+500480 <[^>]*> f40b 9d88 	lw	a0,23560\(a1\)
+0+500484 <[^>]*> 6d02      	li	a1,2
+0+500486 <[^>]*> f400 35a0 	sll	a1,16
+0+50048a <[^>]*> f5b4 9d85 	lw	a0,-23131\(a1\)
+0+50048e <[^>]*> f060 6d07 	li	a1,103
+0+500492 <[^>]*> f400 35a0 	sll	a1,16
+0+500496 <[^>]*> f0dd 9d85 	lw	a0,-5947\(a1\)
+0+50049a <[^>]*> f060 6d07 	li	a1,103
+0+50049e <[^>]*> f400 35a0 	sll	a1,16
+0+5004a2 <[^>]*> f0dd 9d89 	lw	a0,-5943\(a1\)
+0+5004a6 <[^>]*> f060 6d07 	li	a1,103
+0+5004aa <[^>]*> f400 35a0 	sll	a1,16
+0+5004ae <[^>]*> f0dd 9d95 	lw	a0,-5931\(a1\)
+0+5004b2 <[^>]*> f060 6d07 	li	a1,103
+0+5004b6 <[^>]*> f400 35a0 	sll	a1,16
+0+5004ba <[^>]*> f4dd 9d85 	lw	a0,-4923\(a1\)
+0+5004be <[^>]*> f060 6d18 	li	a1,120
+0+5004c2 <[^>]*> f400 35a0 	sll	a1,16
+0+5004c6 <[^>]*> f5df 9d85 	lw	a0,-571\(a1\)
+0+5004ca <[^>]*> f060 6d18 	li	a1,120
+0+5004ce <[^>]*> f400 35a0 	sll	a1,16
+0+5004d2 <[^>]*> f1a0 9d8e 	lw	a0,430\(a1\)
+0+5004d6 <[^>]*> f060 6d18 	li	a1,120
+0+5004da <[^>]*> f400 35a0 	sll	a1,16
+0+5004de <[^>]*> f1df 9d95 	lw	a0,-1579\(a1\)
+0+5004e2 <[^>]*> f060 6d18 	li	a1,120
+0+5004e6 <[^>]*> f400 35a0 	sll	a1,16
+0+5004ea <[^>]*> f1a0 9d8d 	lw	a0,429\(a1\)
+0+5004ee <[^>]*> 6500      	nop
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-hilo.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-hilo.ld
new file mode 100644
index 0000000..1b54352
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-hilo.ld
@@ -0,0 +1,12 @@
+SECTIONS
+{
+  . = 0x0500000;
+  .text : { *(.text) }
+  . = 0x0654320;
+  .data : { *(.data) }
+  .sdata : { *(.sdata) }
+  . = 0x0765430;
+  .bss : { *(.bss) *(COMMON) }
+  .sbss : { *(.sbss) *(.scommon) }
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-hilo.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-hilo.s
new file mode 100644
index 0000000..79ac2fb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-hilo.s
@@ -0,0 +1,14 @@
+	.data
+	.globl	big_external_data_label
+big_external_data_label:
+	.fill	1000
+
+# align section end to 16-byte boundary for easier testing on multiple targets
+	.p2align 4
+
+	.globl	small_external_data_label
+small_external_data_label:
+	.fill	1
+
+# align section end to 16-byte boundary for easier testing on multiple targets
+	.p2align 4
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-intermix-1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-intermix-1.s
new file mode 100644
index 0000000..c596619
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-intermix-1.s
@@ -0,0 +1,104 @@
+	.text
+	.align	2
+	.globl	__start
+	.set	nomips16
+	.ent	__start
+__start:
+	.frame	$sp,56,$31		# vars= 0, regs= 3/2, args= 24, gp= 0
+	.mask	0x80030000,-24
+	.fmask	0x00f00000,-8
+	.set	noreorder
+	.set	nomacro
+	
+	addiu	$sp,$sp,-56
+	sw	$31,32($sp)
+	sw	$17,28($sp)
+	sw	$16,24($sp)
+	sdc1	$f22,48($sp)
+	sdc1	$f20,40($sp)
+	jal	m32_l
+	move	$4,$17
+
+	move	$4,$17
+	jal	m16_l
+	move	$16,$2
+
+	addu	$16,$16,$2
+	jal	m32_d
+	mov.d	$f12,$f22
+
+	addu	$16,$16,$2
+	jal	m16_d
+	mov.d	$f12,$f22
+
+	move	$4,$17
+	mfc1	$7,$f22
+	mfc1	$6,$f23
+	jal	m32_ld
+	addu	$16,$16,$2
+
+	move	$4,$17
+	mfc1	$7,$f22
+	mfc1	$6,$f23
+	jal	m16_ld
+	addu	$16,$16,$2
+
+	move	$6,$17
+	mov.d	$f12,$f22
+	jal	m32_dl
+	addu	$16,$16,$2
+
+	move	$6,$17
+	mov.d	$f12,$f22
+	jal	m16_dl
+	addu	$16,$16,$2
+
+	move	$6,$17
+	move	$7,$17
+	sdc1	$f22,16($sp)
+	mov.d	$f12,$f22
+	jal	m32_dlld
+	addu	$16,$16,$2
+
+	move	$6,$17
+	move	$7,$17
+	mov.d	$f12,$f22
+	sdc1	$f22,16($sp)
+	jal	m16_dlld
+	addu	$16,$16,$2
+
+	move	$4,$17
+	jal	m32_d_l
+	addu	$16,$16,$2
+
+	move	$4,$17
+	jal	m16_d_l
+	mov.d	$f20,$f0
+
+	move	$4,$17
+	mfc1	$7,$f22
+	mfc1	$6,$f23
+	jal	f32
+	add.d	$f20,$f20,$f0
+
+	move	$4,$17
+	add.d	$f20,$f20,$f0
+	mfc1	$7,$f22
+	jal	f16
+	mfc1	$6,$f23
+
+	add.d	$f20,$f20,$f0
+	lw	$31,32($sp)
+	trunc.w.d $f0,$f20
+	lw	$17,28($sp)
+	mfc1	$3,$f0
+	addu	$2,$3,$16
+	lw	$16,24($sp)
+	ldc1	$f22,48($sp)
+	ldc1	$f20,40($sp)
+	j	$31
+	addiu	$sp,$sp,56
+
+	.set	macro
+	.set	reorder
+	.end	__start
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-intermix-2.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-intermix-2.s
new file mode 100644
index 0000000..472f0c9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-intermix-2.s
@@ -0,0 +1,2631 @@
+	.text
+	.align	2
+	.globl	m32_l
+	.set	nomips16
+	.ent	m32_l
+m32_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	move	$2,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_l
+
+	.align	2
+	.globl	m16_l
+	.set	mips16
+	.ent	m16_l
+m16_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	j	$31
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	.end	m16_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static_l
+m32_static_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	move	$2,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static_l
+m16_static_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	j	$31
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	.end	m16_static_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static1_l
+m32_static1_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	move	$2,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static1_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static1_l
+m16_static1_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	j	$31
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	.end	m16_static1_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static32_l
+m32_static32_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	move	$2,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static32_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static32_l
+m16_static32_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	j	$31
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	.end	m16_static32_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static16_l
+m32_static16_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	move	$2,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static16_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static16_l
+m16_static16_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	j	$31
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	.end	m16_static16_l
+
+	.align	2
+	.globl	m32_d
+	.set	nomips16
+	.ent	m32_d
+m32_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f12,$f12
+	j	$31
+	mfc1	$2,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_d
+
+	.align	2
+	.globl	m16_d
+	.set	mips16
+	.ent	m16_d
+m16_d:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	#jal	__mips16_fixdfsi
+	restore	24,$31
+	j	$31
+	.end	m16_d
+	# Stub function for m16_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_d
+__fn_stub_m16_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static_d
+m32_static_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f12,$f12
+	j	$31
+	mfc1	$2,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static_d
+m16_static_d:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	#jal	__mips16_fixdfsi
+	restore	24,$31
+	j	$31
+	.end	m16_static_d
+	# Stub function for m16_static_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static_d
+__fn_stub_m16_static_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static1_d
+m32_static1_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f12,$f12
+	j	$31
+	mfc1	$2,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static1_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static1_d
+m16_static1_d:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	#jal	__mips16_fixdfsi
+	restore	24,$31
+	j	$31
+	.end	m16_static1_d
+	# Stub function for m16_static1_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static1_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static1_d
+__fn_stub_m16_static1_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static1_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static1_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static32_d
+m32_static32_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f12,$f12
+	j	$31
+	mfc1	$2,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static32_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static32_d
+m16_static32_d:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	#jal	__mips16_fixdfsi
+	restore	24,$31
+	j	$31
+	.end	m16_static32_d
+	# Stub function for m16_static32_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static32_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static32_d
+__fn_stub_m16_static32_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static32_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static32_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static16_d
+m32_static16_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f12,$f12
+	j	$31
+	mfc1	$2,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static16_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static16_d
+m16_static16_d:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	#jal	__mips16_fixdfsi
+	restore	24,$31
+	j	$31
+	.end	m16_static16_d
+	# Stub function for m16_static16_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static16_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static16_d
+__fn_stub_m16_static16_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static16_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static16_d
+	.previous
+
+	.align	2
+	.globl	m32_ld
+	.set	nomips16
+	.ent	m32_ld
+m32_ld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$7,$f2
+	mtc1	$6,$f3
+	trunc.w.d $f0,$f2
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_ld
+
+	.align	2
+	.globl	m16_ld
+	.set	mips16
+	.ent	m16_ld
+m16_ld:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	move	$16,$4
+	move	$5,$7
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	move	$4,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_ld
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static_ld
+m32_static_ld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$7,$f2
+	mtc1	$6,$f3
+	trunc.w.d $f0,$f2
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static_ld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static_ld
+m16_static_ld:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	move	$16,$4
+	move	$5,$7
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	move	$4,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static_ld
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static1_ld
+m32_static1_ld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$7,$f2
+	mtc1	$6,$f3
+	trunc.w.d $f0,$f2
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static1_ld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static1_ld
+m16_static1_ld:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	move	$16,$4
+	move	$5,$7
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	move	$4,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static1_ld
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static32_ld
+m32_static32_ld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$7,$f2
+	mtc1	$6,$f3
+	trunc.w.d $f0,$f2
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static32_ld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static32_ld
+m16_static32_ld:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	move	$16,$4
+	move	$5,$7
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	move	$4,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static32_ld
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static16_ld
+m32_static16_ld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$7,$f2
+	mtc1	$6,$f3
+	trunc.w.d $f0,$f2
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$4
+
+	.set	macro
+	.set	reorder
+	.end	m32_static16_ld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static16_ld
+m16_static16_ld:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	move	$16,$4
+	move	$5,$7
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	move	$4,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static16_ld
+
+	.align	2
+	.globl	m32_dl
+	.set	nomips16
+	.ent	m32_dl
+m32_dl:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f0,$f12
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$6
+
+	.set	macro
+	.set	reorder
+	.end	m32_dl
+
+	.align	2
+	.globl	m16_dl
+	.set	mips16
+	.ent	m16_dl
+m16_dl:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	move	$16,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_dl
+	# Stub function for m16_dl (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_dl,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_dl
+__fn_stub_m16_dl:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_dl
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static_dl
+m32_static_dl:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f0,$f12
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$6
+
+	.set	macro
+	.set	reorder
+	.end	m32_static_dl
+
+	.align	2
+	.set	mips16
+	.ent	m16_static_dl
+m16_static_dl:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	move	$16,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static_dl
+	# Stub function for m16_static_dl (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static_dl,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static_dl
+__fn_stub_m16_static_dl:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static_dl
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static1_dl
+m32_static1_dl:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f0,$f12
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$6
+
+	.set	macro
+	.set	reorder
+	.end	m32_static1_dl
+
+	.align	2
+	.set	mips16
+	.ent	m16_static1_dl
+m16_static1_dl:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	move	$16,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static1_dl
+	# Stub function for m16_static1_dl (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static1_dl,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static1_dl
+__fn_stub_m16_static1_dl:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static1_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static1_dl
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static32_dl
+m32_static32_dl:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f0,$f12
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$6
+
+	.set	macro
+	.set	reorder
+	.end	m32_static32_dl
+
+	.align	2
+	.set	mips16
+	.ent	m16_static32_dl
+m16_static32_dl:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	move	$16,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static32_dl
+	# Stub function for m16_static32_dl (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static32_dl,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static32_dl
+__fn_stub_m16_static32_dl:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static32_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static32_dl
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static16_dl
+m32_static16_dl:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f0,$f12
+	mfc1	$24,$f0
+	j	$31
+	addu	$2,$24,$6
+
+	.set	macro
+	.set	reorder
+	.end	m32_static16_dl
+
+	.align	2
+	.set	mips16
+	.ent	m16_static16_dl
+m16_static16_dl:
+	.frame	$sp,24,$31		# vars= 0, regs= 2/0, args= 16, gp= 0
+	.mask	0x80010000,-4
+	.fmask	0x00000000,0
+	save	24,$16,$31
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	move	$16,$6
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16
+	restore	24,$16,$31
+	j	$31
+	.end	m16_static16_dl
+	# Stub function for m16_static16_dl (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static16_dl,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static16_dl
+__fn_stub_m16_static16_dl:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static16_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static16_dl
+	.previous
+
+	.align	2
+	.globl	m32_dlld
+	.set	nomips16
+	.ent	m32_dlld
+m32_dlld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f1,$f12
+	mfc1	$4,$f1
+	addu	$3,$4,$6
+	addu	$2,$3,$7
+	ldc1	$f0,16($sp)
+	trunc.w.d $f2,$f0
+	mfc1	$24,$f2
+	j	$31
+	addu	$2,$2,$24
+
+	.set	macro
+	.set	reorder
+	.end	m32_dlld
+
+	.align	2
+	.globl	m16_dlld
+	.set	mips16
+	.ent	m16_dlld
+m16_dlld:
+	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
+	.mask	0x80030000,-4
+	.fmask	0x00000000,0
+	save	32,$16,$17,$31
+	move	$16,$6
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	move	$17,$7
+	.set	macro
+	.set	reorder
+
+	lw	$5,52($sp)
+	lw	$4,48($sp)
+	addu	$16,$2,$16
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	addu	$16,$17
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16,$2
+	restore	32,$16,$17,$31
+	j	$31
+	.end	m16_dlld
+	# Stub function for m16_dlld (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_dlld,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_dlld
+__fn_stub_m16_dlld:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_dlld
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static_dlld
+m32_static_dlld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f1,$f12
+	mfc1	$4,$f1
+	addu	$3,$4,$6
+	addu	$2,$3,$7
+	ldc1	$f0,16($sp)
+	trunc.w.d $f2,$f0
+	mfc1	$24,$f2
+	j	$31
+	addu	$2,$2,$24
+
+	.set	macro
+	.set	reorder
+	.end	m32_static_dlld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static_dlld
+m16_static_dlld:
+	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
+	.mask	0x80030000,-4
+	.fmask	0x00000000,0
+	save	32,$16,$17,$31
+	move	$16,$6
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	move	$17,$7
+	.set	macro
+	.set	reorder
+
+	lw	$5,52($sp)
+	lw	$4,48($sp)
+	addu	$16,$2,$16
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	addu	$16,$17
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16,$2
+	restore	32,$16,$17,$31
+	j	$31
+	.end	m16_static_dlld
+	# Stub function for m16_static_dlld (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static_dlld,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static_dlld
+__fn_stub_m16_static_dlld:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static_dlld
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static1_dlld
+m32_static1_dlld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f1,$f12
+	mfc1	$4,$f1
+	addu	$3,$4,$6
+	addu	$2,$3,$7
+	ldc1	$f0,16($sp)
+	trunc.w.d $f2,$f0
+	mfc1	$24,$f2
+	j	$31
+	addu	$2,$2,$24
+
+	.set	macro
+	.set	reorder
+	.end	m32_static1_dlld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static1_dlld
+m16_static1_dlld:
+	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
+	.mask	0x80030000,-4
+	.fmask	0x00000000,0
+	save	32,$16,$17,$31
+	move	$16,$6
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	move	$17,$7
+	.set	macro
+	.set	reorder
+
+	lw	$5,52($sp)
+	lw	$4,48($sp)
+	addu	$16,$2,$16
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	addu	$16,$17
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16,$2
+	restore	32,$16,$17,$31
+	j	$31
+	.end	m16_static1_dlld
+	# Stub function for m16_static1_dlld (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static1_dlld,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static1_dlld
+__fn_stub_m16_static1_dlld:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static1_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static1_dlld
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static32_dlld
+m32_static32_dlld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f1,$f12
+	mfc1	$4,$f1
+	addu	$3,$4,$6
+	addu	$2,$3,$7
+	ldc1	$f0,16($sp)
+	trunc.w.d $f2,$f0
+	mfc1	$24,$f2
+	j	$31
+	addu	$2,$2,$24
+
+	.set	macro
+	.set	reorder
+	.end	m32_static32_dlld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static32_dlld
+m16_static32_dlld:
+	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
+	.mask	0x80030000,-4
+	.fmask	0x00000000,0
+	save	32,$16,$17,$31
+	move	$16,$6
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	move	$17,$7
+	.set	macro
+	.set	reorder
+
+	lw	$5,52($sp)
+	lw	$4,48($sp)
+	addu	$16,$2,$16
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	addu	$16,$17
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16,$2
+	restore	32,$16,$17,$31
+	j	$31
+	.end	m16_static32_dlld
+	# Stub function for m16_static32_dlld (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static32_dlld,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static32_dlld
+__fn_stub_m16_static32_dlld:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static32_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static32_dlld
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static16_dlld
+m32_static16_dlld:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	trunc.w.d $f1,$f12
+	mfc1	$4,$f1
+	addu	$3,$4,$6
+	addu	$2,$3,$7
+	ldc1	$f0,16($sp)
+	trunc.w.d $f2,$f0
+	mfc1	$24,$f2
+	j	$31
+	addu	$2,$2,$24
+
+	.set	macro
+	.set	reorder
+	.end	m32_static16_dlld
+
+	.align	2
+	.set	mips16
+	.ent	m16_static16_dlld
+m16_static16_dlld:
+	.frame	$sp,32,$31		# vars= 0, regs= 3/0, args= 16, gp= 0
+	.mask	0x80030000,-4
+	.fmask	0x00000000,0
+	save	32,$16,$17,$31
+	move	$16,$6
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	move	$17,$7
+	.set	macro
+	.set	reorder
+
+	lw	$5,52($sp)
+	lw	$4,48($sp)
+	addu	$16,$2,$16
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_fixdfsi
+	addu	$16,$17
+	.set	macro
+	.set	reorder
+
+	addu	$2,$16,$2
+	restore	32,$16,$17,$31
+	j	$31
+	.end	m16_static16_dlld
+	# Stub function for m16_static16_dlld (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static16_dlld,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static16_dlld
+__fn_stub_m16_static16_dlld:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static16_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static16_dlld
+	.previous
+
+	.align	2
+	.globl	m32_d_l
+	.set	nomips16
+	.ent	m32_d_l
+m32_d_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$4,$f2
+	j	$31
+	cvt.d.w	$f0,$f2
+
+	.set	macro
+	.set	reorder
+	.end	m32_d_l
+
+	.align	2
+	.globl	m16_d_l
+	.set	mips16
+	.ent	m16_d_l
+m16_d_l:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	#jal	__mips16_floatsidf
+	#jal	__mips16_ret_df
+	restore	24,$31
+	j	$31
+	.end	m16_d_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static_d_l
+m32_static_d_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$4,$f2
+	j	$31
+	cvt.d.w	$f0,$f2
+
+	.set	macro
+	.set	reorder
+	.end	m32_static_d_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static_d_l
+m16_static_d_l:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	#jal	__mips16_floatsidf
+	#jal	__mips16_ret_df
+	restore	24,$31
+	j	$31
+	.end	m16_static_d_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static1_d_l
+m32_static1_d_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$4,$f2
+	j	$31
+	cvt.d.w	$f0,$f2
+
+	.set	macro
+	.set	reorder
+	.end	m32_static1_d_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static1_d_l
+m16_static1_d_l:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	#jal	__mips16_floatsidf
+	#jal	__mips16_ret_df
+	restore	24,$31
+	j	$31
+	.end	m16_static1_d_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static32_d_l
+m32_static32_d_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$4,$f2
+	j	$31
+	cvt.d.w	$f0,$f2
+
+	.set	macro
+	.set	reorder
+	.end	m32_static32_d_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static32_d_l
+m16_static32_d_l:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	#jal	__mips16_floatsidf
+	#jal	__mips16_ret_df
+	restore	24,$31
+	j	$31
+	.end	m16_static32_d_l
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static16_d_l
+m32_static16_d_l:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	mtc1	$4,$f2
+	j	$31
+	cvt.d.w	$f0,$f2
+
+	.set	macro
+	.set	reorder
+	.end	m32_static16_d_l
+
+	.align	2
+	.set	mips16
+	.ent	m16_static16_d_l
+m16_static16_d_l:
+	.frame	$sp,24,$31		# vars= 0, regs= 1/0, args= 16, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	24,$31
+	#jal	__mips16_floatsidf
+	#jal	__mips16_ret_df
+	restore	24,$31
+	j	$31
+	.end	m16_static16_d_l
+
+	.align	2
+	.globl	m32_d_d
+	.set	nomips16
+	.ent	m32_d_d
+m32_d_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	mov.d	$f0,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_d_d
+
+	.align	2
+	.globl	m16_d_d
+	.set	mips16
+	.ent	m16_d_d
+m16_d_d:
+	.frame	$sp,8,$31		# vars= 0, regs= 1/0, args= 0, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	8,$31
+	move	$3,$5
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_ret_df
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	restore	8,$31
+	j	$31
+	.end	m16_d_d
+	# Stub function for m16_d_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_d_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_d_d
+__fn_stub_m16_d_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_d_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_d_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static_d_d
+m32_static_d_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	mov.d	$f0,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static_d_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static_d_d
+m16_static_d_d:
+	.frame	$sp,8,$31		# vars= 0, regs= 1/0, args= 0, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	8,$31
+	move	$3,$5
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_ret_df
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	restore	8,$31
+	j	$31
+	.end	m16_static_d_d
+	# Stub function for m16_static_d_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static_d_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static_d_d
+__fn_stub_m16_static_d_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static_d_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static_d_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static1_d_d
+m32_static1_d_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	mov.d	$f0,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static1_d_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static1_d_d
+m16_static1_d_d:
+	.frame	$sp,8,$31		# vars= 0, regs= 1/0, args= 0, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	8,$31
+	move	$3,$5
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_ret_df
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	restore	8,$31
+	j	$31
+	.end	m16_static1_d_d
+	# Stub function for m16_static1_d_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static1_d_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static1_d_d
+__fn_stub_m16_static1_d_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static1_d_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static1_d_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static32_d_d
+m32_static32_d_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	mov.d	$f0,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static32_d_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static32_d_d
+m16_static32_d_d:
+	.frame	$sp,8,$31		# vars= 0, regs= 1/0, args= 0, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	8,$31
+	move	$3,$5
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_ret_df
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	restore	8,$31
+	j	$31
+	.end	m16_static32_d_d
+	# Stub function for m16_static32_d_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static32_d_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static32_d_d
+__fn_stub_m16_static32_d_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static32_d_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static32_d_d
+	.previous
+
+	.align	2
+	.set	nomips16
+	.ent	m32_static16_d_d
+m32_static16_d_d:
+	.frame	$sp,0,$31		# vars= 0, regs= 0/0, args= 0, gp= 0
+	.mask	0x00000000,0
+	.fmask	0x00000000,0
+	.set	noreorder
+	.set	nomacro
+	
+	j	$31
+	mov.d	$f0,$f12
+
+	.set	macro
+	.set	reorder
+	.end	m32_static16_d_d
+
+	.align	2
+	.set	mips16
+	.ent	m16_static16_d_d
+m16_static16_d_d:
+	.frame	$sp,8,$31		# vars= 0, regs= 1/0, args= 0, gp= 0
+	.mask	0x80000000,-4
+	.fmask	0x00000000,0
+	save	8,$31
+	move	$3,$5
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_ret_df
+	move	$2,$4
+	.set	macro
+	.set	reorder
+
+	restore	8,$31
+	j	$31
+	.end	m16_static16_d_d
+	# Stub function for m16_static16_d_d (double)
+	.set	nomips16
+	.section	.mips16.fn.m16_static16_d_d,"ax",@progbits
+	.align	2
+	.ent	__fn_stub_m16_static16_d_d
+__fn_stub_m16_static16_d_d:
+	.set	noreorder
+	mfc1	$4,$f13
+	mfc1	$5,$f12
+	.set	noat
+	la	$1,m16_static16_d_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__fn_stub_m16_static16_d_d
+	.previous
+
+	.align	2
+	.globl	f32
+	.set	nomips16
+	.ent	f32
+f32:
+	.frame	$sp,64,$31		# vars= 0, regs= 3/3, args= 24, gp= 0
+	.mask	0x80030000,-32
+	.fmask	0x03f00000,-8
+	.set	noreorder
+	.set	nomacro
+	
+	addiu	$sp,$sp,-64
+	sw	$17,28($sp)
+	move	$17,$4
+	sw	$31,32($sp)
+	sdc1	$f24,56($sp)
+	sw	$16,24($sp)
+	sdc1	$f22,48($sp)
+	sdc1	$f20,40($sp)
+	mtc1	$7,$f22
+	jal	m32_static1_l
+	mtc1	$6,$f23
+
+	move	$4,$17
+	jal	m16_static1_l
+	move	$16,$2
+
+	addu	$16,$16,$2
+	jal	m32_static1_d
+	mov.d	$f12,$f22
+
+	addu	$16,$16,$2
+	jal	m16_static1_d
+	mov.d	$f12,$f22
+
+	move	$4,$17
+	mfc1	$7,$f22
+	mfc1	$6,$f23
+	jal	m32_static1_ld
+	addu	$16,$16,$2
+
+	move	$4,$17
+	mfc1	$7,$f22
+	mfc1	$6,$f23
+	jal	m16_static1_ld
+	addu	$16,$16,$2
+
+	move	$6,$17
+	mov.d	$f12,$f22
+	jal	m32_static1_dl
+	addu	$16,$16,$2
+
+	move	$6,$17
+	mov.d	$f12,$f22
+	jal	m16_static1_dl
+	addu	$16,$16,$2
+
+	move	$6,$17
+	move	$7,$17
+	sdc1	$f22,16($sp)
+	mov.d	$f12,$f22
+	jal	m32_static1_dlld
+	addu	$16,$16,$2
+
+	move	$6,$17
+	move	$7,$17
+	mov.d	$f12,$f22
+	sdc1	$f22,16($sp)
+	jal	m16_static1_dlld
+	addu	$16,$16,$2
+
+	move	$4,$17
+	jal	m32_static1_d_l
+	addu	$16,$16,$2
+
+	move	$4,$17
+	jal	m16_static1_d_l
+	mov.d	$f20,$f0
+
+	add.d	$f20,$f20,$f0
+	jal	m32_static1_d_d
+	mov.d	$f12,$f22
+
+	add.d	$f20,$f20,$f0
+	jal	m16_static1_d_d
+	mov.d	$f12,$f22
+
+	move	$4,$17
+	jal	m32_static32_l
+	add.d	$f20,$f20,$f0
+
+	move	$4,$17
+	jal	m16_static32_l
+	addu	$16,$16,$2
+
+	addu	$16,$16,$2
+	jal	m32_static32_d
+	mov.d	$f12,$f22
+
+	addu	$16,$16,$2
+	jal	m16_static32_d
+	mov.d	$f12,$f22
+
+	move	$4,$17
+	mfc1	$7,$f22
+	mfc1	$6,$f23
+	jal	m32_static32_ld
+	addu	$16,$16,$2
+
+	move	$4,$17
+	mfc1	$7,$f22
+	mfc1	$6,$f23
+	jal	m16_static32_ld
+	addu	$16,$16,$2
+
+	move	$6,$17
+	mov.d	$f12,$f22
+	jal	m32_static32_dl
+	addu	$16,$16,$2
+
+	move	$6,$17
+	mov.d	$f12,$f22
+	jal	m16_static32_dl
+	addu	$16,$16,$2
+
+	move	$6,$17
+	move	$7,$17
+	sdc1	$f22,16($sp)
+	mov.d	$f12,$f22
+	jal	m32_static32_dlld
+	addu	$16,$16,$2
+
+	move	$6,$17
+	move	$7,$17
+	mov.d	$f12,$f22
+	sdc1	$f22,16($sp)
+	jal	m16_static32_dlld
+	addu	$16,$16,$2
+
+	move	$4,$17
+	jal	m32_static32_d_l
+	addu	$16,$16,$2
+
+	move	$4,$17
+	jal	m16_static32_d_l
+	add.d	$f20,$f20,$f0
+
+	add.d	$f20,$f20,$f0
+	jal	m32_static32_d_d
+	mov.d	$f12,$f22
+
+	mtc1	$16,$f24
+	add.d	$f20,$f20,$f0
+	jal	m16_static32_d_d
+	mov.d	$f12,$f22
+
+	lw	$31,32($sp)
+	lw	$17,28($sp)
+	lw	$16,24($sp)
+	add.d	$f20,$f20,$f0
+	ldc1	$f22,48($sp)
+	cvt.d.w	$f0,$f24
+	ldc1	$f24,56($sp)
+	add.d	$f0,$f0,$f20
+	ldc1	$f20,40($sp)
+	j	$31
+	addiu	$sp,$sp,64
+
+	.set	macro
+	.set	reorder
+	.end	f32
+
+	# Stub function to call m32_static1_d (double)
+	.set	nomips16
+	.section	.mips16.call.m32_static1_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m32_static1_d
+__call_stub_m32_static1_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m32_static1_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m32_static1_d
+	.previous
+
+	# Stub function to call m16_static1_d (double)
+	.set	nomips16
+	.section	.mips16.call.m16_static1_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m16_static1_d
+__call_stub_m16_static1_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m16_static1_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m16_static1_d
+	.previous
+
+	# Stub function to call m32_static1_dl (double)
+	.set	nomips16
+	.section	.mips16.call.m32_static1_dl,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m32_static1_dl
+__call_stub_m32_static1_dl:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m32_static1_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m32_static1_dl
+	.previous
+
+	# Stub function to call m16_static1_dl (double)
+	.set	nomips16
+	.section	.mips16.call.m16_static1_dl,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m16_static1_dl
+__call_stub_m16_static1_dl:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m16_static1_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m16_static1_dl
+	.previous
+
+	# Stub function to call m32_static1_dlld (double)
+	.set	nomips16
+	.section	.mips16.call.m32_static1_dlld,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m32_static1_dlld
+__call_stub_m32_static1_dlld:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m32_static1_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m32_static1_dlld
+	.previous
+
+	# Stub function to call m16_static1_dlld (double)
+	.set	nomips16
+	.section	.mips16.call.m16_static1_dlld,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m16_static1_dlld
+__call_stub_m16_static1_dlld:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m16_static1_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m16_static1_dlld
+	.previous
+
+	# Stub function to call double m32_static1_d_l ()
+	.set	nomips16
+	.section	.mips16.call.fp.m32_static1_d_l,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m32_static1_d_l
+__call_stub_fp_m32_static1_d_l:
+	.set	noreorder
+	move	$18,$31
+	jal	m32_static1_d_l
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m32_static1_d_l
+	.previous
+
+	# Stub function to call double m16_static1_d_l ()
+	.set	nomips16
+	.section	.mips16.call.fp.m16_static1_d_l,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m16_static1_d_l
+__call_stub_fp_m16_static1_d_l:
+	.set	noreorder
+	move	$18,$31
+	jal	m16_static1_d_l
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m16_static1_d_l
+	.previous
+
+	# Stub function to call double m32_static1_d_d (double)
+	.set	nomips16
+	.section	.mips16.call.fp.m32_static1_d_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m32_static1_d_d
+__call_stub_fp_m32_static1_d_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	move	$18,$31
+	jal	m32_static1_d_d
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m32_static1_d_d
+	.previous
+
+	# Stub function to call double m16_static1_d_d (double)
+	.set	nomips16
+	.section	.mips16.call.fp.m16_static1_d_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m16_static1_d_d
+__call_stub_fp_m16_static1_d_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	move	$18,$31
+	jal	m16_static1_d_d
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m16_static1_d_d
+	.previous
+
+	# Stub function to call m32_static16_d (double)
+	.set	nomips16
+	.section	.mips16.call.m32_static16_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m32_static16_d
+__call_stub_m32_static16_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m32_static16_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m32_static16_d
+	.previous
+
+	# Stub function to call m16_static16_d (double)
+	.set	nomips16
+	.section	.mips16.call.m16_static16_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m16_static16_d
+__call_stub_m16_static16_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m16_static16_d
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m16_static16_d
+	.previous
+
+	# Stub function to call m32_static16_dl (double)
+	.set	nomips16
+	.section	.mips16.call.m32_static16_dl,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m32_static16_dl
+__call_stub_m32_static16_dl:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m32_static16_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m32_static16_dl
+	.previous
+
+	# Stub function to call m16_static16_dl (double)
+	.set	nomips16
+	.section	.mips16.call.m16_static16_dl,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m16_static16_dl
+__call_stub_m16_static16_dl:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m16_static16_dl
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m16_static16_dl
+	.previous
+
+	# Stub function to call m32_static16_dlld (double)
+	.set	nomips16
+	.section	.mips16.call.m32_static16_dlld,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m32_static16_dlld
+__call_stub_m32_static16_dlld:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m32_static16_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m32_static16_dlld
+	.previous
+
+	# Stub function to call m16_static16_dlld (double)
+	.set	nomips16
+	.section	.mips16.call.m16_static16_dlld,"ax",@progbits
+	.align	2
+	.ent	__call_stub_m16_static16_dlld
+__call_stub_m16_static16_dlld:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	.set	noat
+	la	$1,m16_static16_dlld
+	jr	$1
+	.set	at
+	nop
+	.set	reorder
+	.end	__call_stub_m16_static16_dlld
+	.previous
+
+	# Stub function to call double m32_static16_d_l ()
+	.set	nomips16
+	.section	.mips16.call.fp.m32_static16_d_l,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m32_static16_d_l
+__call_stub_fp_m32_static16_d_l:
+	.set	noreorder
+	move	$18,$31
+	jal	m32_static16_d_l
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m32_static16_d_l
+	.previous
+
+	# Stub function to call double m16_static16_d_l ()
+	.set	nomips16
+	.section	.mips16.call.fp.m16_static16_d_l,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m16_static16_d_l
+__call_stub_fp_m16_static16_d_l:
+	.set	noreorder
+	move	$18,$31
+	jal	m16_static16_d_l
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m16_static16_d_l
+	.previous
+
+	# Stub function to call double m32_static16_d_d (double)
+	.set	nomips16
+	.section	.mips16.call.fp.m32_static16_d_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m32_static16_d_d
+__call_stub_fp_m32_static16_d_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	move	$18,$31
+	jal	m32_static16_d_d
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m32_static16_d_d
+	.previous
+
+	# Stub function to call double m16_static16_d_d (double)
+	.set	nomips16
+	.section	.mips16.call.fp.m16_static16_d_d,"ax",@progbits
+	.align	2
+	.ent	__call_stub_fp_m16_static16_d_d
+__call_stub_fp_m16_static16_d_d:
+	.set	noreorder
+	mtc1	$4,$f13
+	mtc1	$5,$f12
+	move	$18,$31
+	jal	m16_static16_d_d
+	nop
+	mfc1	$2,$f1
+	mfc1	$3,$f0
+	j	$18
+	nop
+	.set	reorder
+	.end	__call_stub_fp_m16_static16_d_d
+	.previous
+
+	.align	2
+	.globl	f16
+	.set	mips16
+	.ent	f16
+f16:
+	.frame	$sp,104,$31		# vars= 64, regs= 4/0, args= 24, gp= 0
+	.mask	0x80070000,-4
+	.fmask	0x00000000,0
+	save	104,$16,$17,$18,$31
+	move	$17,$4
+	sw	$7,116($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static1_l
+	sw	$6,112($sp)
+	.set	macro
+	.set	reorder
+
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static1_l
+	move	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static1_d
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static1_d
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$7,116($sp)
+	lw	$6,112($sp)
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static1_ld
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$7,116($sp)
+	lw	$6,112($sp)
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static1_ld
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	move	$6,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static1_dl
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	move	$6,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static1_dl
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$3,116($sp)
+	lw	$6,112($sp)
+	sw	$3,20($sp)
+	move	$5,$3
+	sw	$6,16($sp)
+	move	$4,$6
+	move	$7,$17
+	move	$6,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static1_dlld
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	addu	$16,$2
+	lw	$7,112($sp)
+	lw	$2,116($sp)
+	move	$6,$17
+	move	$5,$2
+	sw	$7,16($sp)
+	move	$4,$7
+	sw	$2,20($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static1_dlld
+	move	$7,$17
+	.set	macro
+	.set	reorder
+
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static1_d_l
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	move	$4,$17
+	sw	$3,28($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static1_d_l
+	sw	$2,24($sp)
+	.set	macro
+	.set	reorder
+
+	lw	$5,28($sp)
+	lw	$4,24($sp)
+	move	$7,$3
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_adddf3
+	move	$6,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	sw	$3,36($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static1_d_d
+	sw	$2,32($sp)
+	.set	macro
+	.set	reorder
+
+	lw	$5,36($sp)
+	lw	$4,32($sp)
+	move	$7,$3
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_adddf3
+	move	$6,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	sw	$3,44($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static1_d_d
+	sw	$2,40($sp)
+	.set	macro
+	.set	reorder
+
+	lw	$5,44($sp)
+	lw	$4,40($sp)
+	move	$7,$3
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_adddf3
+	move	$6,$2
+	.set	macro
+	.set	reorder
+
+	move	$4,$17
+	sw	$3,52($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static16_l
+	sw	$2,48($sp)
+	.set	macro
+	.set	reorder
+
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static16_l
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static16_d
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static16_d
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$7,116($sp)
+	lw	$6,112($sp)
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static16_ld
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$7,116($sp)
+	lw	$6,112($sp)
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static16_ld
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	move	$6,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static16_dl
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	move	$6,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static16_dl
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$4,116($sp)
+	lw	$6,112($sp)
+	sw	$4,20($sp)
+	sw	$6,16($sp)
+	move	$5,$4
+	move	$7,$17
+	move	$4,$6
+	move	$6,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static16_dlld
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	addu	$16,$2
+	lw	$3,116($sp)
+	lw	$2,112($sp)
+	move	$6,$17
+	move	$7,$17
+	sw	$3,20($sp)
+	move	$5,$3
+	sw	$2,16($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static16_dlld
+	move	$4,$2
+	.set	macro
+	.set	reorder
+
+	move	$4,$17
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static16_d_l
+	addu	$16,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,52($sp)
+	lw	$4,48($sp)
+	move	$7,$3
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_adddf3
+	move	$6,$2
+	.set	macro
+	.set	reorder
+
+	move	$4,$17
+	sw	$3,60($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static16_d_l
+	sw	$2,56($sp)
+	.set	macro
+	.set	reorder
+
+	lw	$5,60($sp)
+	lw	$4,56($sp)
+	move	$7,$3
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_adddf3
+	move	$6,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	sw	$3,68($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m32_static16_d_d
+	sw	$2,64($sp)
+	.set	macro
+	.set	reorder
+
+	lw	$5,68($sp)
+	lw	$4,64($sp)
+	move	$7,$3
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_adddf3
+	move	$6,$2
+	.set	macro
+	.set	reorder
+
+	lw	$5,116($sp)
+	lw	$4,112($sp)
+	sw	$3,76($sp)
+	.set	noreorder
+	.set	nomacro
+	jal	m16_static16_d_d
+	sw	$2,72($sp)
+	.set	macro
+	.set	reorder
+
+	lw	$5,76($sp)
+	lw	$4,72($sp)
+	move	$7,$3
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_adddf3
+	move	$6,$2
+	.set	macro
+	.set	reorder
+
+	move	$4,$16
+	sw	$3,84($sp)
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_floatsidf
+	sw	$2,80($sp)
+	.set	macro
+	.set	reorder
+
+	lw	$7,84($sp)
+	lw	$6,80($sp)
+	move	$5,$3
+	.set	noreorder
+	.set	nomacro
+	#jal	__mips16_adddf3
+	move	$4,$2
+	.set	macro
+	.set	reorder
+
+	#jal	__mips16_ret_df
+	restore	104,$16,$17,$18,$31
+	j	$31
+	.end	f16
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-intermix.d b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-intermix.d
new file mode 100644
index 0000000..cc8c1fe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-intermix.d
@@ -0,0 +1,126 @@
+
+.*: +file format elf.*mips
+
+SYMBOL TABLE:
+#...
+.* l     F .text	0+[0-9a-f]+ m32_static_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static_l
+.* l     F .text	0+[0-9a-f]+ m32_static1_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_l
+.* l     F .text	0+[0-9a-f]+ m32_static32_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_l
+.* l     F .text	0+[0-9a-f]+ m32_static16_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_l
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_d
+.* l     F .text	0+[0-9a-f]+ m32_static_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static_d
+.* l     F .text	0+[0-9a-f]+ m32_static1_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_d
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static1_d
+.* l     F .text	0+[0-9a-f]+ m32_static32_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_d
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static32_d
+.* l     F .text	0+[0-9a-f]+ m32_static16_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_d
+.* l     F .text	0+[0-9a-f]+ m32_static_ld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static_ld
+.* l     F .text	0+[0-9a-f]+ m32_static1_ld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_ld
+.* l     F .text	0+[0-9a-f]+ m32_static32_ld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_ld
+.* l     F .text	0+[0-9a-f]+ m32_static16_ld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_ld
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_dl
+.* l     F .text	0+[0-9a-f]+ m32_static_dl
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static_dl
+.* l     F .text	0+[0-9a-f]+ m32_static1_dl
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_dl
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static1_dl
+.* l     F .text	0+[0-9a-f]+ m32_static32_dl
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_dl
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static32_dl
+.* l     F .text	0+[0-9a-f]+ m32_static16_dl
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_dl
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_dlld
+.* l     F .text	0+[0-9a-f]+ m32_static_dlld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static_dlld
+.* l     F .text	0+[0-9a-f]+ m32_static1_dlld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_dlld
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static1_dlld
+.* l     F .text	0+[0-9a-f]+ m32_static32_dlld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_dlld
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static32_dlld
+.* l     F .text	0+[0-9a-f]+ m32_static16_dlld
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_dlld
+.* l     F .text	0+[0-9a-f]+ m32_static_d_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static_d_l
+.* l     F .text	0+[0-9a-f]+ m32_static1_d_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_d_l
+.* l     F .text	0+[0-9a-f]+ m32_static32_d_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_d_l
+.* l     F .text	0+[0-9a-f]+ m32_static16_d_l
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_d_l
+# ??? We aren't yet able to get rid of the symbol table entry for
+# __fn_stub_m16_d_d, or its .pdr entry.
+.* l     F .text	0+[0-9a-f]+ *
+.* l     F .text	0+[0-9a-f]+ m32_static_d_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static_d_d
+.* l     F .text	0+[0-9a-f]+ m32_static1_d_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static1_d_d
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static1_d_d
+.* l     F .text	0+[0-9a-f]+ m32_static32_d_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static32_d_d
+.* l     F .text	0+[0-9a-f]+ __fn_stub_m16_static32_d_d
+.* l     F .text	0+[0-9a-f]+ m32_static16_d_d
+.* l     F .text	0+[0-9a-f]+ 0xf0 m16_static16_d_d
+#...
+.* l     F .text	0+[0-9a-f]+ __call_stub_m32_static1_d
+.* l     F .text	0+[0-9a-f]+ __call_stub_m16_static1_d
+.* l     F .text	0+[0-9a-f]+ __call_stub_m32_static1_dl
+.* l     F .text	0+[0-9a-f]+ __call_stub_m16_static1_dl
+.* l     F .text	0+[0-9a-f]+ __call_stub_m32_static1_dlld
+.* l     F .text	0+[0-9a-f]+ __call_stub_m16_static1_dlld
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m32_static1_d_l
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m16_static1_d_l
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m32_static1_d_d
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m16_static1_d_d
+.* l     F .text	0+[0-9a-f]+ __call_stub_m32_static16_d
+.* l     F .text	0+[0-9a-f]+ __call_stub_m16_static16_d
+.* l     F .text	0+[0-9a-f]+ __call_stub_m32_static16_dl
+.* l     F .text	0+[0-9a-f]+ __call_stub_m16_static16_dl
+.* l     F .text	0+[0-9a-f]+ __call_stub_m32_static16_dlld
+.* l     F .text	0+[0-9a-f]+ __call_stub_m16_static16_dlld
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m32_static16_d_l
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m16_static16_d_l
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m32_static16_d_d
+.* l     F .text	0+[0-9a-f]+ __call_stub_fp_m16_static16_d_d
+#...
+.* g     F .text	0+[0-9a-f]+ m32_ld
+#...
+.* g     F .text	0+[0-9a-f]+ m32_d_l
+.* g     F .text	0+[0-9a-f]+ 0xf0 m16_d_d
+.* g     F .text	0+[0-9a-f]+ 0xf0 m16_d
+#...
+.* g     F .text	0+[0-9a-f]+ 0xf0 f16
+#...
+.* g     F .text	0+[0-9a-f]+ m32_d
+#...
+.* g     F .text	0+[0-9a-f]+ 0xf0 m16_dl
+#...
+.* g     F .text	0+[0-9a-f]+ f32
+#...
+.* g     F .text	0+[0-9a-f]+ 0xf0 m16_l
+#...
+.* g     F .text	0+[0-9a-f]+ 0xf0 m16_ld
+#...
+.* g     F .text	0+[0-9a-f]+ 0xf0 m16_dlld
+.* g     F .text	0+[0-9a-f]+ m32_d_d
+#...
+.* g     F .text	0+[0-9a-f]+ m32_dl
+#...
+.* g     F .text	0+[0-9a-f]+ m32_dlld
+#...
+.* g     F .text	0+[0-9a-f]+ 0xf0 m16_d_l
+#...
+.* g     F .text	0+[0-9a-f]+ m32_l
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-local-stubs-1.d b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-local-stubs-1.d
new file mode 100644
index 0000000..1ffa1d1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-local-stubs-1.d
@@ -0,0 +1,107 @@
+#name: MIPS16 interlinking for local functions 1
+#source: mips16-local-stubs-1.s
+#as: -mips4
+#ld: -Ttext 0x20000000 -e caller1
+#objdump: -dr
+#...
+Disassembly of section \.text:
+
+20000000 <f1>:
+20000000:	03e00008 	jr	ra
+20000004:	00000000 	nop
+
+20000008 <g1>:
+20000008:	03e00008 	jr	ra
+2000000c:	00000000 	nop
+
+20000010 <h1>:
+20000010:	e820      	jr	ra
+20000012:	6500      	nop
+
+20000014 <f2>:
+20000014:	03e00008 	jr	ra
+20000018:	00000000 	nop
+
+2000001c <g2>:
+2000001c:	03e00008 	jr	ra
+20000020:	00000000 	nop
+
+20000024 <h2>:
+20000024:	e820      	jr	ra
+20000026:	6500      	nop
+
+20000028 <f3>:
+20000028:	03e00008 	jr	ra
+2000002c:	00000000 	nop
+
+20000030 <g3>:
+20000030:	03e00008 	jr	ra
+20000034:	00000000 	nop
+
+20000038 <h3>:
+20000038:	e820      	jr	ra
+2000003a:	6500      	nop
+
+2000003c <caller1>:
+2000003c:	0c000000 	jal	20000000 <f1>
+20000040:	00000000 	nop
+20000044:	0c000005 	jal	20000014 <f2>
+20000048:	00000000 	nop
+2000004c:	0c000002 	jal	20000008 <g1>
+20000050:	00000000 	nop
+20000054:	0c000007 	jal	2000001c <g2>
+20000058:	00000000 	nop
+2000005c:	0c000024 	jal	20000090 <stub_for_h1>
+20000060:	00000000 	nop
+20000064:	0c000028 	jal	200000a0 <stub_for_h2>
+20000068:	00000000 	nop
+
+2000006c <caller2>:
+2000006c:	1c00 002c 	jalx	200000b0 <stub_for_f1>
+20000070:	6500      	nop
+20000072:	1c00 0034 	jalx	200000d0 <stub_for_f2>
+20000076:	6500      	nop
+20000078:	1c00 0030 	jalx	200000c0 <stub_for_g1>
+2000007c:	6500      	nop
+2000007e:	1c00 0038 	jalx	200000e0 <stub_for_g2>
+20000082:	6500      	nop
+20000084:	1800 0004 	jal	20000010 <h1>
+20000088:	6500      	nop
+2000008a:	1800 0009 	jal	20000024 <h2>
+2000008e:	6500      	nop
+
+20000090 <stub_for_h1>:
+20000090:	3c012000 	lui	at,0x2000
+20000094:	24210011 	addiu	at,at,17
+20000098:	00200008 	jr	at
+2000009c:	00000000 	nop
+
+200000a0 <stub_for_h2>:
+200000a0:	3c012000 	lui	at,0x2000
+200000a4:	24210025 	addiu	at,at,37
+200000a8:	00200008 	jr	at
+200000ac:	00000000 	nop
+
+200000b0 <stub_for_f1>:
+200000b0:	3c012000 	lui	at,0x2000
+200000b4:	24210000 	addiu	at,at,0
+200000b8:	00200008 	jr	at
+200000bc:	00000000 	nop
+
+200000c0 <stub_for_g1>:
+200000c0:	3c012000 	lui	at,0x2000
+200000c4:	24210008 	addiu	at,at,8
+200000c8:	00200008 	jr	at
+200000cc:	00000000 	nop
+
+200000d0 <stub_for_f2>:
+200000d0:	3c012000 	lui	at,0x2000
+200000d4:	24210014 	addiu	at,at,20
+200000d8:	00200008 	jr	at
+200000dc:	00000000 	nop
+
+200000e0 <stub_for_g2>:
+200000e0:	3c012000 	lui	at,0x2000
+200000e4:	2421001c 	addiu	at,at,28
+200000e8:	00200008 	jr	at
+200000ec:	00000000 	nop
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-local-stubs-1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-local-stubs-1.s
new file mode 100644
index 0000000..9904402
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-local-stubs-1.s
@@ -0,0 +1,49 @@
+	.macro	makestub,type,func,section
+	.text
+	.set	\type
+	.type	\func,@function
+	.ent	\func
+\func:
+	jr	$31
+	.end	\func
+
+	.section \section,"ax",@progbits
+	.set	nomips16
+	.type	stub_for_\func,@function
+	.ent	stub_for_\func
+stub_for_\func:
+	.set	noat
+	la	$1,\func
+	jr	$1
+	.set	at
+	.end	stub_for_\func
+	.endm
+
+	.macro	makestubs,id
+	makestub nomips16,f\id,.mips16.call.F\id
+	makestub nomips16,g\id,.mips16.call.fp.G\id
+	makestub mips16,h\id,.mips16.fn.H\id
+	.endm
+
+	.macro	makecaller,type,func
+	.text
+	.set	\type
+	.globl	\func
+	.type	\func,@function
+	.ent	\func
+\func:
+	jal	f1
+	jal	f2
+	jal	g1
+	jal	g2
+	jal	h1
+	jal	h2
+	.end	\func
+	.endm
+
+	makestubs 1
+	makestubs 2
+	makestubs 3
+
+	makecaller nomips16,caller1
+	makecaller mips16,caller2
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1-dummy.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1-dummy.s
new file mode 100644
index 0000000..6ee56e0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1-dummy.s
@@ -0,0 +1,15 @@
+	.abicalls
+	nop
+
+	.macro	dummyfn,name
+	.global	\name
+	.ent	\name
+\name:
+	jr	$31
+	.end	\name
+	.endm
+
+	dummyfn	extern1
+	dummyfn	extern2
+	dummyfn	extern3
+	dummyfn	extern4
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1.dd
new file mode 100644
index 0000000..c853733
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1.dd
@@ -0,0 +1,1227 @@
+
+.*
+
+
+Disassembly of section \.text:
+
+00040400 <a_unused1>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040404 <b_unused1>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040408 <callpic_unused1_mips16>:
+.*:	[^\t]*	li	v0,1
+.*:	[^\t]*	la	v1,47ff0 <.*>
+.*:	[^\t]*	sll	v0,16
+.*:	[^\t]*	addu	v0,v1
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	addiu	sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+# 0x40400: a_unused1
+.*:	[^\t]*	lw	v0,-32744\(v0\)
+.*:	[^\t]*	addiu	v0,1025
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+# 0x40404: b_unused2
+.*:	[^\t]*	lw	v0,-32744\(v0\)
+.*:	[^\t]*	addiu	v0,1029
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,32
+
+00040444 <a_unused2>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040448 <b_unused2>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+0004044c <jals_unused2_mips16>:
+.*:	[^\t]*	jal	.* <a_unused2>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <b_unused2>
+.*:	[^\t]*	nop
+
+00040458 <a_unused3>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+0004045c <b_unused3>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040460 <a_unused4>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040464 <b_unused4>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040468 <callpic_unused4_mips16>:
+.*:	[^\t]*	li	v0,1
+.*:	[^\t]*	la	v1,47ff0 <.*>
+.*:	[^\t]*	sll	v0,16
+.*:	[^\t]*	addu	v0,v1
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	addiu	sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+.*:	[^\t]*	lw	v0,-32740\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32736\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,32
+
+0004049c <a_unused5>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404a0 <b_unused5>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404a4 <jals_unused5_mips16>:
+.*:	[^\t]*	jal	.* <a_unused5>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <b_unused5>
+.*:	[^\t]*	nop
+
+000404b0 <a_unused6>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404b4 <b_unused6>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404b8 <a_unused7>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404bc <b_unused7>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404c0 <a_unused8>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404c4 <b_unused8>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404c8 <a_unused9>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404cc <b_unused9>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404d0 <jals_unused9_mips16>:
+.*:	[^\t]*	jal	.* <a_unused9>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <b_unused9>
+.*:	[^\t]*	nop
+
+000404dc <a_unused10>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404e0 <b_unused10>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404e4 <a_unused11>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404e8 <b_unused11>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404ec <a_used1>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404f0 <b_used1>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000404f4 <callpic_used1_nomips16>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+.*:	[^\t]*	move	v0,gp
+.*:	[^\t]*	addiu	sp,sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+# 0x40b10: __fn_a_used1
+.*:	[^\t]*	lw	v0,-32744\(v0\)
+.*:	[^\t]*	addiu	v0,v0,2832
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+# 0x40b24: __fn_b_used1
+.*:	[^\t]*	lw	v0,-32744\(v0\)
+.*:	[^\t]*	addiu	v0,v0,2852
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,sp,32
+
+0004054c <a_used2>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040550 <b_used2>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040554 <jals_used2_nomips16>:
+.*:	[^\t]*	jal	.* <__fn_a_used2>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <__fn_b_used2>
+.*:	[^\t]*	nop
+
+00040564 <a_used3>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040568 <b_used3>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+0004056c <callpic_used3_nomips16>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+.*:	[^\t]*	move	v0,gp
+.*:	[^\t]*	addiu	sp,sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+# 0x40b80: __fn_a_used3
+.*:	[^\t]*	lw	v0,-32744\(v0\)
+.*:	[^\t]*	addiu	v0,v0,2944
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+# 0x40b94: __fn_b_used3
+.*:	[^\t]*	lw	v0,-32744\(v0\)
+.*:	[^\t]*	addiu	v0,v0,2964
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,sp,32
+
+000405c4 <callpic_used3_mips16>:
+.*:	[^\t]*	li	v0,1
+.*:	[^\t]*	la	v1,47ff0 <.*>
+.*:	[^\t]*	sll	v0,16
+.*:	[^\t]*	addu	v0,v1
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	addiu	sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+# 0x40564: a_used3
+.*:	[^\t]*	lw	v0,-32744\(v0\)
+.*:	[^\t]*	addiu	v0,1381
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+# 0x40568: b_used3
+.*:	[^\t]*	lw	v0,-32744\(v0\)
+.*:	[^\t]*	addiu	v0,1385
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,32
+
+00040600 <a_used4>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040604 <b_used4>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040608 <jals_used4_nomips16>:
+.*:	[^\t]*	jal	.* <__fn_a_used4>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <__fn_b_used4>
+.*:	[^\t]*	nop
+
+00040618 <jals_used4_mips16>:
+.*:	[^\t]*	jal	.* <a_used4>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <b_used4>
+.*:	[^\t]*	nop
+
+00040624 <a_used5>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040628 <b_used5>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+0004062c <jals_used5_nomips16>:
+.*:	[^\t]*	jal	.* <__fn_a_used5>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <__fn_b_used5>
+.*:	[^\t]*	nop
+
+0004063c <callpic_used5_mips16>:
+.*:	[^\t]*	li	v0,1
+.*:	[^\t]*	la	v1,47ff0 <.*>
+.*:	[^\t]*	sll	v0,16
+.*:	[^\t]*	addu	v0,v1
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	addiu	sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+# 0x40624: a_used5
+.*:	[^\t]*	lw	v0,-32744\(v0\)
+.*:	[^\t]*	addiu	v0,1573
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+# 0x40628: b_used5
+.*:	[^\t]*	lw	v0,-32744\(v0\)
+.*:	[^\t]*	addiu	v0,1577
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,32
+
+00040678 <a_used6>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+0004067c <b_used6>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040680 <callpic_used6_nomips16>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+.*:	[^\t]*	move	v0,gp
+.*:	[^\t]*	addiu	sp,sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+.*:	[^\t]*	lw	v0,-32732\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32728\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,sp,32
+
+000406d0 <a_used7>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000406d4 <b_used7>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000406d8 <jals_used7_nomips16>:
+.*:	[^\t]*	jal	.* <__fn_a_used7>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <__fn_b_used7>
+.*:	[^\t]*	nop
+
+000406e8 <a_used8>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000406ec <b_used8>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000406f0 <a_used9>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000406f4 <b_used9>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000406f8 <a_used10>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000406fc <b_used10>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040700 <callpic_used10_nomips16>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+.*:	[^\t]*	move	v0,gp
+.*:	[^\t]*	addiu	sp,sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+.*:	[^\t]*	lw	v0,-32724\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32720\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,sp,32
+
+00040750 <callpic_used10_mips16>:
+.*:	[^\t]*	li	v0,1
+.*:	[^\t]*	la	v1,47ff0 <.*>
+.*:	[^\t]*	sll	v0,16
+.*:	[^\t]*	addu	v0,v1
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	addiu	sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+.*:	[^\t]*	lw	v0,-32724\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32720\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,32
+
+00040784 <a_used11>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040788 <b_used11>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+0004078c <jals_used11_nomips16>:
+.*:	[^\t]*	jal	.* <__fn_a_used11>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <__fn_b_used11>
+.*:	[^\t]*	nop
+
+0004079c <jals_used11_mips16>:
+.*:	[^\t]*	jal	.* <a_used11>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <b_used11>
+.*:	[^\t]*	nop
+
+000407a8 <a_used12>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000407ac <b_used12>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000407b0 <jals_used12_nomips16>:
+.*:	[^\t]*	jal	.* <__fn_a_used12>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <__fn_b_used12>
+.*:	[^\t]*	nop
+
+000407c0 <callpic_used12_mips16>:
+.*:	[^\t]*	li	v0,1
+.*:	[^\t]*	la	v1,47ff0 <.*>
+.*:	[^\t]*	sll	v0,16
+.*:	[^\t]*	addu	v0,v1
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	addiu	sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+.*:	[^\t]*	lw	v0,-32716\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32712\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,32
+
+000407f4 <.mips16.a_used13>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000407f8 <.mips16.b_used13>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000407fc <callpic_used13_nomips16>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+.*:	[^\t]*	move	v0,gp
+.*:	[^\t]*	addiu	sp,sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+.*:	[^\t]*	lw	v0,-32660\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32632\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,sp,32
+
+0004084c <a_used14>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040850 <b_used14>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040854 <jals_used14_nomips16>:
+.*:	[^\t]*	jal	.* <__fn_a_used14>
+.*:	[^\t]*	nop
+ .*:	[^\t]*	jal	.* <__fn_b_used14>
+.*:	[^\t]*	nop
+
+00040864 <.mips16.a_used15>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040868 <.mips16.b_used15>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+0004086c <a_used16>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040870 <b_used16>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040874 <.mips16.a_used17>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040878 <.mips16.b_used17>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+0004087c <callpic_used17_nomips16>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+.*:	[^\t]*	move	v0,gp
+.*:	[^\t]*	addiu	sp,sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+.*:	[^\t]*	lw	v0,-32676\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32656\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,sp,32
+
+000408cc <callpic_used17_mips16>:
+.*:	[^\t]*	li	v0,1
+.*:	[^\t]*	la	v1,47ff0 <.*>
+.*:	[^\t]*	sll	v0,16
+.*:	[^\t]*	addu	v0,v1
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	addiu	sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+.*:	[^\t]*	lw	v0,-32676\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32656\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,32
+
+00040900 <a_used18>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040904 <b_used18>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040908 <jals_used18_nomips16>:
+.*:	[^\t]*	jal	.* <__fn_a_used18>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <__fn_b_used18>
+.*:	[^\t]*	nop
+
+00040918 <jals_used18_mips16>:
+.*:	[^\t]*	jal	.* <a_used18>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <b_used18>
+.*:	[^\t]*	nop
+
+00040924 <.mips16.a_used19>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040928 <.mips16.b_used19>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+0004092c <jals_used19_nomips16>:
+.*:	[^\t]*	jal	.* <a_used19>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <b_used19>
+.*:	[^\t]*	nop
+
+0004093c <callpic_used19_mips16>:
+.*:	[^\t]*	li	v0,1
+.*:	[^\t]*	la	v1,47ff0 <.*>
+.*:	[^\t]*	sll	v0,16
+.*:	[^\t]*	addu	v0,v1
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	addiu	sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+.*:	[^\t]*	lw	v0,-32644\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32672\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,32
+
+00040970 <.mips16.a_used20>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040974 <.mips16.b_used20>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040978 <callpic_used20_mips16>:
+.*:	[^\t]*	li	v0,1
+.*:	[^\t]*	la	v1,47ff0 <.*>
+.*:	[^\t]*	sll	v0,16
+.*:	[^\t]*	addu	v0,v1
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	addiu	sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+.*:	[^\t]*	lw	v0,-32668\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32652\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,32
+
+000409ac <.mips16.a_used21>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+000409b0 <.mips16.b_used21>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+#...
+
+000409c0 <callpic_unused6_mips16>:
+.*:	[^\t]*	li	v0,1
+.*:	[^\t]*	la	v1,47ff0 <.*>
+.*:	[^\t]*	sll	v0,16
+.*:	[^\t]*	addu	v0,v1
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	addiu	sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+.*:	[^\t]*	lw	v0,-32708\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32704\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,32
+
+000409f4 <jals_unused7_mips16>:
+.*:	[^\t]*	jal	.* <a_unused7>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <b_unused7>
+.*:	[^\t]*	nop
+
+00040a00 <jals_unused10_mips16>:
+.*:	[^\t]*	jal	.* <a_unused10>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <b_unused10>
+.*:	[^\t]*	nop
+
+00040a0c <callpic_used8_nomips16>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+.*:	[^\t]*	move	v0,gp
+.*:	[^\t]*	addiu	sp,sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+.*:	[^\t]*	lw	v0,-32700\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32696\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,sp,32
+
+00040a5c <jals_used9_nomips16>:
+.*:	[^\t]*	jal	.* <__fn_a_used9>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <__fn_b_used9>
+.*:	[^\t]*	nop
+
+00040a6c <callpic_used15_nomips16>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+.*:	[^\t]*	move	v0,gp
+.*:	[^\t]*	addiu	sp,sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+.*:	[^\t]*	lw	v0,-32664\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32640\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,sp,32
+
+00040abc <jals_used16_nomips16>:
+.*:	[^\t]*	jal	.* <__fn_a_used16>
+.*:	[^\t]*	nop
+.*:	[^\t]*	jal	.* <__fn_b_used16>
+.*:	[^\t]*	nop
+
+00040acc <callpic_used21_mips16>:
+.*:	[^\t]*	li	v0,1
+.*:	[^\t]*	la	v1,47ff0 <.*>
+.*:	[^\t]*	sll	v0,16
+.*:	[^\t]*	addu	v0,v1
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	addiu	sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+.*:	[^\t]*	lw	v0,-32648\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32636\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,32
+
+00040b00 <__start>:
+	\.\.\.
+
+00040b10 <__fn_a_used1>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040b24 <__fn_b_used1>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x404f0: b_used1
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1265
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040b48 <__fn_a_used2>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040b5c <__fn_b_used2>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x40550: b_used2
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1361
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040b80 <__fn_a_used3>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040b94 <__fn_b_used3>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x40568: b_used3
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1385
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040bb8 <__fn_a_used4>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040bcc <__fn_b_used4>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x40604: b_used4
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1541
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040bf0 <__fn_a_used5>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040c04 <__fn_b_used5>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x40628: b_used5
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1577
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040c28 <__fn_a_used6>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040c3c <__fn_b_used6>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x4067c: b_used6
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1661
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040c60 <__fn_a_used7>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040c74 <__fn_b_used7>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x406d4: b_used7
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1749
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040c98 <__fn_a_used8>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040cac <__fn_b_used8>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x406ec: b_used8
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1773
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040cd0 <__fn_a_used9>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040ce4 <__fn_b_used9>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x406f4: b_used9
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1781
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040d08 <__fn_a_used10>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040d1c <__fn_b_used10>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x406fc: b_used10
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1789
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040d40 <__fn_a_used11>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040d54 <__fn_b_used11>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x40788: b_used11
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1929
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040d78 <__fn_a_used12>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040d8c <__fn_b_used12>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x407ac: b_used12
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1965
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040db0 <a_used13>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040dc4 <b_used13>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x407f8: .mips16.b_used13
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,2041
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040de8 <__fn_a_used14>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040dfc <__fn_b_used14>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x40850: b_used14
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,2129
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040e20 <a_used15>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040e34 <b_used15>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x40628: .mips16.b_used15
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,2153
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040e58 <__fn_a_used16>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040e6c <__fn_b_used16>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x40870: b_used16
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,2161
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040e90 <a_used17>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040ea4 <b_used17>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x40878: .mips16.b_used17
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,2169
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040ec8 <__fn_a_used18>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040edc <__fn_b_used18>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x40904: b_used18
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,2309
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040f00 <a_used19>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040f14 <b_used19>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x40928: .mips16.b_used19
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,2345
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040f38 <a_used20>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040f4c <b_used20>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x40974: .mips16.b_used20
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,2421
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040f70 <a_used21>:
+.*:	[^\t]*	lui	v0,.*
+.*:	[^\t]*	addiu	v0,v0,.*
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040f84 <b_used21>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 0x409b0: .mips16.b_used21
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,2481
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1.gd b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1.gd
new file mode 100644
index 0000000..874a319
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1.gd
@@ -0,0 +1,57 @@
+
+Primary GOT:
+ Canonical gp value: 00057ff0
+
+ Reserved entries:
+   Address     Access  Initial Purpose
+  00050000 -32752\(gp\) 00000000 Lazy resolver
+  00050004 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+ Local entries:
+   Address     Access  Initial
+# GOT page entry
+  00050008 -32744\(gp\) 00040000
+# a_unused4
+  0005000c -32740\(gp\) 00040461
+# b_unused4
+  00050010 -32736\(gp\) 00040465
+# __fn_a_used6
+  00050014 -32732\(gp\) 00040c28
+# __fn_b_used6
+  00050018 -32728\(gp\) 00040c3c
+# __fn_a_used10
+  0005001c -32724\(gp\) 00040d08
+# __fn_b_used10
+  00050020 -32720\(gp\) 00040d1c
+# __fn_a_used12
+  00050024 -32716\(gp\) 00040d78
+# __fn_b_used12
+  00050028 -32712\(gp\) 00040d8c
+# a_unused6
+  0005002c -32708\(gp\) 000404b1
+# b_unused6
+  00050030 -32704\(gp\) 000404b5
+# __fn_a_used8
+  00050034 -32700\(gp\) 00040c98
+# __fn_b_used8
+  00050038 -32696\(gp\) 00040cac
+  0005003c -32692\(gp\) 00000000
+  00050040 -32688\(gp\) 00000000
+  00050044 -32684\(gp\) 00000000
+  00050048 -32680\(gp\) 00000000
+
+ Global entries:
+   Address     Access  Initial Sym\.Val\. Type    Ndx Name
+  0005004c -32676\(gp\) 00040e90 00040e90 FUNC      7 a_used17
+  00050050 -32672\(gp\) 00040f14 00040f14 FUNC      7 b_used19
+  00050054 -32668\(gp\) 00040f38 00040f38 FUNC      7 a_used20
+  00050058 -32664\(gp\) 00040e20 00040e20 FUNC      7 a_used15
+  0005005c -32660\(gp\) 00040db0 00040db0 FUNC      7 a_used13
+  00050060 -32656\(gp\) 00040ea4 00040ea4 FUNC      7 b_used17
+  00050064 -32652\(gp\) 00040f4c 00040f4c FUNC      7 b_used20
+  00050068 -32648\(gp\) 00040f70 00040f70 FUNC      7 a_used21
+  0005006c -32644\(gp\) 00040f00 00040f00 FUNC      7 a_used19
+  00050070 -32640\(gp\) 00040e34 00040e34 FUNC      7 b_used15
+  00050074 -32636\(gp\) 00040f84 00040f84 FUNC      7 b_used21
+  00050078 -32632\(gp\) 00040dc4 00040dc4 FUNC      7 b_used13
+
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1.inc b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1.inc
new file mode 100644
index 0000000..9268a07
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1.inc
@@ -0,0 +1,147 @@
+	# Declare a function called NAME and an __fn_NAME stub for it.
+	# Make the stub use la_TYPE to load the the target address into $2.
+	.macro	stub,name,type
+	.set	nomips16
+	.section .mips16.fn.\name, "ax", @progbits
+	.ent	__fn_\name
+__fn_\name:
+	la_\type \name
+	mfc1	$4,$f12
+	jr	$2
+	nop
+	.end	__fn_\name
+
+	.set	mips16
+	.text
+	.ent	\name
+\name:
+__fn_local_\name:
+	jr	$31
+	nop
+	.end	\name
+	.endm
+
+	# Like stub, but ensure NAME is a local symbol.
+	.macro	lstub,name,type
+	stub	\name, \type
+	.equ	local_\name,1
+	.endm
+
+	# Like stub, but ensure NAME is a hidden symbol.
+	.macro	hstub,name,type
+	.globl	\name
+	.hidden	\name
+	stub	\name, \type
+	.endm
+
+	# Like lstub, but make the MIPS16 function global rather than local.
+	.macro	gstub,name,type
+	.globl	\name
+	stub	\name, \type
+	.endm
+
+	# Use an absolute sequence to load NAME into a register.
+	.macro	la_noshared,name
+	lui	$2,%hi(\name)
+	addiu	$2,$2,%lo(\name)
+	.endm
+
+	# Use the normal PIC sequence to load __fn_local_NAME into $2
+	# and emit a dummy relocation against NAME.  This macro is always
+	# used at the start of a function.
+	.macro	la_shared,name
+	.reloc	0,R_MIPS_NONE,\name
+	.cpload	$25
+	la	$2,__fn_local_\name
+	.endm
+
+	# Use TYPE (either LSTUB, HSTUB or GSTUB) to define functions
+	# called a_NAME and b_NAME.  The former uses absolute accesses
+	# and the latter uses PIC accesses.
+	.macro	decl,name,type
+	\type	a_\name, noshared
+	\type	b_\name, shared
+	.endm
+
+	# Emit the MIPS16 PIC sequence for setting $28 from $25.
+	# Make the value of $25 available in $2 as well.
+	.macro	cpload_mips16
+	li	$2,%hi(_gp_disp)
+	addiu	$3,$pc,%lo(_gp_disp)
+	sll	$2,16
+	addu	$2,$2,$3
+	move	$28,$2
+	.endm
+
+	# Likewise, but for non-MIPS16 code.
+	.macro	cpload_nomips16
+	.cpload	$25
+	move	$2,$28
+	.endm
+
+	# Start a PIC function in ISA mode MODE, which is either "mips16"
+	# or "nomips16".
+	.macro	pic_prologue,mode
+	cpload_\mode
+	addiu	$sp,$sp,-32
+	sw	$2,16($sp)
+	sw	$31,20($sp)
+	.endm
+
+	# Use a PIC function to call NAME.
+	.macro	pic_call,name,mode
+	.ifdef	local_\name
+	.ifc	\mode,mips16
+	lw	$2,%got(__fn_local_\name)($2)
+	addiu	$2,%lo(__fn_local_\name)
+	.else
+	lw	$2,%got(\name)($2)
+	addiu	$2,%lo(\name)
+	.endif
+	.else
+	lw	$2,%call16(\name)($2)
+	.endif
+	jalr	$2
+	move	$25,$2
+	lw	$2,16($sp)
+	move	$28,$2
+	.endm
+
+	# Finish a PIC function started by pic_prologue.
+	.macro	pic_epilogue
+	lw	$2,20($sp)
+	jr	$2
+	addiu	$sp,$sp,32
+	.endm
+
+	# Use PIC %call16 sequences to call a_NAME and b_NAME.
+	# MODE selects the ISA mode of the code: either "mips16"
+	# or "nomips16".
+	.macro	callpic,name,mode
+	.text
+	.set	\mode
+	.ent	callpic_\name\()_\mode
+callpic_\name\()_\mode:
+	pic_prologue \mode
+	pic_call     a_\name,\mode
+	pic_call     b_\name,\mode
+	pic_epilogue
+	.end	callpic_\name\()_\mode
+	.endm
+
+	# Use absolute jals to call a_NAME and b_NAME.  MODE selects the
+	# ISA mode of the code: either "mips16" or "nomips16".
+	.macro	jals,name,mode
+	.text
+	.set	\mode
+	.ent	jals_\name\()_\mode
+jals_\name\()_\mode:
+	.option	pic0
+	jal	a_\name
+	nop
+
+	jal	b_\name
+	nop
+	.option	pic2
+	.end	jals_\name\()_\mode
+	.endm
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1.ld
new file mode 100644
index 0000000..91f1464
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1.ld
@@ -0,0 +1,22 @@
+SECTIONS
+{
+  . = 0x40000;
+  .interp : { *(.interp) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+  .dynamic : { *(.dynamic) }
+  .reginfo : { *(.reginfo) }
+  .hash : { *(.hash) }
+  . = ALIGN (0x400);
+  .text : { *(.text) *(.mips16.*) }
+  .MIPS.stubs : { *(.MIPS.stubs) }
+  . = ALIGN (0x400);
+  .rel.plt : { *(.rel.plt) }
+  .rel.dyn : { *(.rel.dyn) }
+  . = 0x50000;
+  _gp = . + 0x7ff0;
+  .got : { *(.got) }
+  . = 0x50400;
+  .data : { *(.data) }
+  .rld_map : { *(.rld_map) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1a.s
new file mode 100644
index 0000000..14ea93c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1a.s
@@ -0,0 +1,144 @@
+	.abicalls
+	.set	noreorder
+	.include "mips16-pic-1.inc"
+
+	# Test local stubs that are only used by MIPS16 PIC calls in this file.
+	decl	unused1,lstub
+	callpic	unused1,mips16
+
+	# Test local stubs that are only used by MIPS16 jals in this file.
+	decl	unused2,lstub
+	jals	unused2,mips16
+
+	# Test local stubs that aren't called at all.
+	decl	unused3,lstub
+
+	# Test hidden stubs that are called by MIPS16 PIC calls in this file.
+	decl	unused4,hstub
+	callpic	unused4,mips16
+
+	# Test hidden stubs that are called by MIPS16 jals in this file.
+	decl	unused5,hstub
+	jals	unused5,mips16
+
+	# Test hidden stubs that are called by MIPS16 PIC calls in another file.
+	decl	unused6,hstub
+
+	# Test hidden stubs that are called by MIPS16 jals in another file.
+	decl	unused7,hstub
+
+	# Test hidden stubs that aren't called at all.
+	decl	unused8,hstub
+
+	# Test global stubs that are called by MIPS16 jals in this file.
+	decl	unused9,gstub
+	jals	unused9,mips16
+
+	# Test global stubs that are called by MIPS16 jals in another file.
+	decl	unused10,gstub
+
+	# Test global stubs that aren't called at all.
+	decl	unused11,gstub
+
+	# Test local stubs that are used by non-MIPS16 PIC calls in this file.
+	decl	used1,lstub
+	callpic	used1,nomips16
+
+	# Test local stubs that are used by non-MIPS16 jals in this file.
+	decl	used2,lstub
+	jals	used2,nomips16
+
+	# Test local stubs that are used by both MIPS16 and non-MIPS16 PIC
+	# calls in this file.
+	decl	used3,lstub
+	callpic	used3,nomips16
+	callpic	used3,mips16
+
+	# Test local stubs that are used by both MIPS16 and non-MIPS16 jals
+	# in this file.
+	decl	used4,lstub
+	jals	used4,nomips16
+	jals	used4,mips16
+
+	# Test local stubs that are used by a combination of MIPS16 PIC calls
+	# and non-MIPS16 jals in this file.
+	decl	used5,lstub
+	jals	used5,nomips16
+	callpic	used5,mips16
+
+	# Test hidden stubs that are used by non-MIPS16 PIC calls in this file.
+	decl	used6,hstub
+	callpic	used6,nomips16
+
+	# Test hidden stubs that are used by non-MIPS16 jals in this file.
+	decl	used7,hstub
+	jals	used7,nomips16
+
+	# Test hidden stubs that are used by non-MIPS16 PIC calls in another
+	# file.
+	decl	used8,hstub
+
+	# Test hidden stubs that are used by non-MIPS16 jals in another
+	# file.
+	decl	used9,hstub
+
+	# Test hidden stubs that are used by both MIPS16 and non-MIPS16 PIC
+	# calls in this file.
+	decl	used10,hstub
+	callpic	used10,nomips16
+	callpic	used10,mips16
+
+	# Test hidden stubs that are used by both MIPS16 and non-MIPS16 jals
+	# in this file.
+	decl	used11,hstub
+	jals	used11,nomips16
+	jals	used11,mips16
+
+	# Test hidden stubs that are used by a combination of MIPS16 PIC calls
+	# and non-MIPS16 jals in this file.
+	decl	used12,hstub
+	jals	used12,nomips16
+	callpic	used12,mips16
+
+	# Test global stubs that are used by non-MIPS16 PIC calls in this file.
+	decl	used13,gstub
+	callpic	used13,nomips16
+
+	# Test global stubs that are used by non-MIPS16 jals in this file.
+	decl	used14,gstub
+	jals	used14,nomips16
+
+	# Test global stubs that are used by non-MIPS16 PIC calls in another
+	# file.
+	decl	used15,gstub
+
+	# Test global stubs that are used by non-MIPS16 jals in another file.
+	decl	used16,gstub
+
+	# Test global stubs that are used by both MIPS16 and non-MIPS16 PIC
+	# calls in this file.
+	decl	used17,gstub
+	callpic	used17,nomips16
+	callpic	used17,mips16
+
+	# Test global stubs that are used by both MIPS16 and non-MIPS16 jals
+	# in this file.
+	decl	used18,gstub
+	jals	used18,nomips16
+	jals	used18,mips16
+
+	# Test global stubs that are used by a combination of MIPS16 PIC calls
+	# and non-MIPS16 jals in this file.
+	decl	used19,gstub
+	jals	used19,nomips16
+	callpic	used19,mips16
+
+	# Test global stubs that are used by MIPS16 PIC calls in this file.
+	# We currently force all targets of call16 relocations to be dynamic,
+	# and the stub must be the definition of the dynamic symbol.
+	decl	used20,gstub
+	callpic	used20,mips16
+
+	# Test global stubs that are used by MIPS16 PIC calls in another file.
+	# Needed for the same reason as used21.
+	decl	used21,gstub
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1b.s
new file mode 100644
index 0000000..9a17072
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-1b.s
@@ -0,0 +1,19 @@
+	.abicalls
+	.set	noreorder
+	.include "mips16-pic-1.inc"
+
+	callpic	unused6,mips16
+	jals	unused7,mips16
+	jals	unused10,mips16
+	callpic	used8,nomips16
+	jals	used9,nomips16
+	callpic	used15,nomips16
+	jals	used16,nomips16
+	callpic	used21,mips16
+
+	.globl	__start
+	.ent	__start
+	.set	nomips16
+__start:
+	nop
+	.end	__start
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2.ad b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2.ad
new file mode 100644
index 0000000..95c53e5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2.ad
@@ -0,0 +1,6 @@
+# [MIPS_GOTSYM, MIPS_SYMTABNO) covers used4...used7.
+#...
+ .* \(MIPS_SYMTABNO\) * 10
+#...
+ .* \(MIPS_GOTSYM\) * 0x6
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2.dd
new file mode 100644
index 0000000..7052057
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2.dd
@@ -0,0 +1,208 @@
+
+.*
+
+
+Disassembly of section \.text:
+
+00040400 <unused1>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040404 <unused2>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040408 <unused3>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+0004040c <unused4>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040410 <unused5>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040414 <used1>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040418 <used2>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+0004041c <used3>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040420 <\.mips16\.used4>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040424 <\.mips16\.used5>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040428 <\.mips16\.used6>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+0004042c <\.mips16\.used7>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040430 <\.mips16\.used8>:
+.*:	[^\t]*	jr	ra
+.*:	[^\t]*	nop
+
+00040434 <foo>:
+.*:	[^\t]*	li	v0,1
+.*:	[^\t]*	la	v1,47ff0 <.*>
+.*:	[^\t]*	sll	v0,16
+.*:	[^\t]*	addu	v0,v1
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	addiu	sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+# 40400: unused1
+.*:	[^\t]*	lw	v0,-32744\(v0\)
+.*:	[^\t]*	addiu	v0,1025
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32740\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32716\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,32
+#...
+
+00040480 <bar>:
+.*:	[^\t]*	li	v0,1
+.*:	[^\t]*	la	v1,47ff0 <.*>
+.*:	[^\t]*	sll	v0,16
+.*:	[^\t]*	addu	v0,v1
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	addiu	sp,-32
+.*:	[^\t]*	sw	v0,16\(sp\)
+.*:	[^\t]*	sw	ra,20\(sp\)
+.*:	[^\t]*	lw	v0,-32736\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,-32712\(v0\)
+.*:	[^\t]*	jalr	v0
+.*:	[^\t]*	move	t9,v0
+.*:	[^\t]*	lw	v0,16\(sp\)
+.*:	[^\t]*	move	gp,v0
+.*:	[^\t]*	lw	v0,20\(sp\)
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	addiu	sp,32
+#...
+
+000404c0 <__fn_used1>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 40414: used1
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1045
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+000404e4 <__fn_used2>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 40418: used2
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1049
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040508 <__fn_used3>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 4041c: used3
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1053
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+0004052c <used4>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 40420: used4
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1057
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040550 <used5>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 40424: used5
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1061
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040574 <used6>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 40428: used6
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1065
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+00040598 <used7>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 4042c: used7
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1069
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
+
+000405bc <used8>:
+.*:	[^\t]*	lui	gp,.*
+.*:	[^\t]*	addiu	gp,gp,.*
+.*:	[^\t]*	addu	gp,gp,t9
+# 40430: used8
+.*:	[^\t]*	lw	v0,-32744\(gp\)
+.*:	[^\t]*	nop
+.*:	[^\t]*	addiu	v0,v0,1073
+.*:	[^\t]*	mfc1	a0,\$f12
+.*:	[^\t]*	jr	v0
+.*:	[^\t]*	nop
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2.gd b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2.gd
new file mode 100644
index 0000000..d8d1451
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2.gd
@@ -0,0 +1,26 @@
+
+Primary GOT:
+ Canonical gp value: 00057ff0
+
+ Reserved entries:
+   Address     Access  Initial Purpose
+  00050000 -32752\(gp\) 00000000 Lazy resolver
+  00050004 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+ Local entries:
+   Address     Access  Initial
+  00050008 -32744\(gp\) 00040000
+  0005000c -32740\(gp\) 00040409
+  00050010 -32736\(gp\) 0004040d
+  00050014 -32732\(gp\) 00000000
+  00050018 -32728\(gp\) 00000000
+  0005001c -32724\(gp\) 00000000
+  00050020 -32720\(gp\) 00000000
+
+ Global entries:
+   Address     Access  Initial Sym\.Val\. Type    Ndx Name
+  00050024 -32716\(gp\) 00040574 00040574 FUNC      6 used6
+  00050028 -32712\(gp\) 00040598 00040598 FUNC      6 used7
+  0005002c -32708\(gp\) 00040550 00040550 FUNC      6 used5
+  00050030 -32704\(gp\) 0004052c 0004052c FUNC      6 used4
+
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2.nd b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2.nd
new file mode 100644
index 0000000..a2b67b6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2.nd
@@ -0,0 +1,10 @@
+# used8 should come before MIPS_GOTSYM.
+#...
+     4: 000405bc    36 FUNC    GLOBAL DEFAULT .* used8
+     5: .* _GLOBAL_OFFSET_TABLE_
+     6: 00040574    36 FUNC    GLOBAL DEFAULT .* used6
+     7: 00040598    36 FUNC    GLOBAL DEFAULT .* used7
+     8: 00040550    36 FUNC    GLOBAL DEFAULT .* used5
+     9: 0004052c    36 FUNC    GLOBAL DEFAULT .* used4
+
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2.rd b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2.rd
new file mode 100644
index 0000000..09a97b7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2.rd
@@ -0,0 +1,9 @@
+
+Relocation section '\.rel\.dyn' .*:
+.*
+0+00000 * [0-9]+ * R_MIPS_NONE *
+0+50400 * [0-9]+ * R_MIPS_REL32 *
+0+50404 * [0-9]+ * R_MIPS_REL32 *
+0+50410 * [0-9]+ * R_MIPS_REL32 *
+0+50414 * [0-9]+ * R_MIPS_REL32 * 00040550 * used5
+0+50408 * [0-9]+ * R_MIPS_REL32 * 0004052c * used4
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2a.s
new file mode 100644
index 0000000..08a1269
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2a.s
@@ -0,0 +1,63 @@
+	.abicalls
+	.set	noreorder
+	.include "mips16-pic-1.inc"
+
+	# Test local stubs that are only used by MIPS16 PIC calls in this file.
+	lstub	unused1,shared
+
+	# Test local stubs that aren't called at all.
+	lstub	unused2,shared
+
+	# Test hidden stubs that are called by MIPS16 PIC calls in this file.
+	hstub	unused3,shared
+
+	# Test hidden stubs that are called by MIPS16 PIC calls in another file.
+	hstub	unused4,shared
+
+	# Test hidden stubs that aren't called at all.
+	hstub	unused5,shared
+
+
+	# Test local stubs that are referenced by absolute relocations
+	# in this file.
+	lstub	used1,shared
+
+	# Test hidden stubs that are referenced by absolute relocations
+	# in this file.
+	hstub	used2,shared
+
+	# Test hidden stubs that are referenced by absolute relocations
+	# in another file.
+	hstub	used3,shared
+
+	# Test global stubs that are referenced by absolute relocations
+	# in this file.
+	gstub	used4,shared
+
+	# Test global stubs that are referenced by absolute relocations
+	# in another file.
+	gstub	used5,shared
+
+	# Test global stubs that are called by MIPS16 PIC calls in this file.
+	gstub	used6,shared
+
+	# Test global stubs that are called by MIPS16 PIC calls in another file.
+	gstub	used7,shared
+
+	# Test global stubs that aren't referenced at all.
+	gstub	used8,shared
+
+	.set	mips16
+	.ent	foo
+foo:
+	pic_prologue mips16
+	pic_call     unused1,mips16
+	pic_call     unused3,mips16
+	pic_call     used6,mips16
+	pic_epilogue
+	.end	foo
+
+	.data
+	.word	used1
+	.word	used2
+	.word	used4
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2b.s
new file mode 100644
index 0000000..2a66b5a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-2b.s
@@ -0,0 +1,16 @@
+	.abicalls
+	.set	noreorder
+	.include "mips16-pic-1.inc"
+
+	.set	mips16
+	.ent	bar
+bar:
+	pic_prologue mips16
+	pic_call     unused4,mips16
+	pic_call     used7,mips16
+	pic_epilogue
+	.end	bar
+
+	.data
+	.word	used3
+	.word	used5
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3.dd
new file mode 100644
index 0000000..93ba085
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3.dd
@@ -0,0 +1,265 @@
+
+.*
+
+
+Disassembly of section \.text:
+
+00040400 <unused1>:
+.*:	e820      	jr	ra
+.*:	6500      	nop
+
+00040404 <unused2>:
+.*:	e820      	jr	ra
+.*:	6500      	nop
+
+00040408 <unused3>:
+.*:	e820      	jr	ra
+.*:	6500      	nop
+
+0004040c <unused4>:
+.*:	e820      	jr	ra
+.*:	6500      	nop
+
+00040410 <used1>:
+.*:	03e00008 	jr	ra
+.*:	00000000 	nop
+
+00040418 <used2>:
+.*:	03e00008 	jr	ra
+.*:	00000000 	nop
+
+00040420 <used3>:
+.*:	03e00008 	jr	ra
+.*:	00000000 	nop
+
+00040428 <used4>:
+.*:	03e00008 	jr	ra
+.*:	00000000 	nop
+
+00040430 <used5>:
+.*:	03e00008 	jr	ra
+.*:	00000000 	nop
+
+00040438 <used6>:
+.*:	03e00008 	jr	ra
+.*:	00000000 	nop
+
+00040440 <used7>:
+.*:	03e00008 	jr	ra
+.*:	00000000 	nop
+
+00040448 <used8>:
+.*:	03e00008 	jr	ra
+.*:	00000000 	nop
+
+00040450 <used9>:
+.*:	03e00008 	jr	ra
+.*:	00000000 	nop
+
+00040458 <used10>:
+.*:	03e00008 	jr	ra
+.*:	00000000 	nop
+
+00040460 <test_unused1>:
+.*:	.*	jal	.* <unused1>
+
+00040464 <test_used1>:
+.*:	.*	jalx	.* <__call_used1>
+
+00040468 <test_used3>:
+.*:	.*	jalx	.* <__call_used3>
+
+0004046c <test_used7>:
+.*:	.*	jalx	.* <__call_used7>
+
+00040470 <test_extern1>:
+.*:	.*	jalx	.* <__call_extern1>
+
+00040474 <test_unused2>:
+.*:	.*	jal	.* <unused2>
+
+00040478 <test_used2>:
+.*:	.*	jalx	.* <__call_fp_used2>
+
+0004047c <test_used4>:
+.*:	.*	jalx	.* <__call_fp_used4>
+
+00040480 <test_used8>:
+.*:	.*	jalx	.* <__call_fp_used8>
+
+00040484 <test_extern2>:
+.*:	.*	jalx	.* <__call_fp_extern2>
+#...
+
+00040490 <test_unused3>:
+.*:	.*	jal	.* <unused3>
+
+00040494 <test_used5>:
+.*:	.*	jalx	.* <__call_used5>
+
+00040498 <test_used9>:
+.*:	.*	jalx	.* <__call_used9>
+
+0004049c <test_extern3>:
+.*:	.*	jalx	.* <__call_extern3>
+
+000404a0 <test_unused4>:
+.*:	.*	jal	.* <unused4>
+
+000404a4 <test_used6>:
+.*:	.*	jalx	.* <__call_fp_used6>
+
+000404a8 <test_used10>:
+.*:	.*	jalx	.* <__call_fp_used10>
+
+000404ac <test_extern4>:
+.*:	.*	jalx	.* <__call_fp_extern4>
+
+000404b0 <__call_used1>:
+.*:	3c190004 	lui	t9,.*
+.*:	27390410 	addiu	t9,t9,.*
+.*:	03200008 	jr	t9
+.*:	44846000 	mtc1	a0,\$f12
+
+000404c0 <__call_used3>:
+.*:	3c190004 	lui	t9,.*
+.*:	27390420 	addiu	t9,t9,.*
+.*:	03200008 	jr	t9
+.*:	44846000 	mtc1	a0,\$f12
+
+000404d0 <__call_used7>:
+.*:	3c190004 	lui	t9,.*
+.*:	27390440 	addiu	t9,t9,.*
+.*:	03200008 	jr	t9
+.*:	44846000 	mtc1	a0,\$f12
+
+000404e0 <__call_extern1>:
+.*:	3c190004 	lui	t9,.*
+.*:	27390650 	addiu	t9,t9,.*
+.*:	03200008 	jr	t9
+.*:	44846000 	mtc1	a0,\$f12
+
+000404f0 <__call_fp_used2>:
+.*:	03e09021 	move	s2,ra
+.*:	3c190004 	lui	t9,.*
+.*:	27390418 	addiu	t9,t9,.*
+.*:	0320f809 	jalr	t9
+.*:	44846000 	mtc1	a0,\$f12
+.*:	44020000 	mfc1	v0,\$f0
+.*:	02400008 	jr	s2
+.*:	00000000 	nop
+
+00040510 <__call_fp_used4>:
+.*:	03e09021 	move	s2,ra
+.*:	3c190004 	lui	t9,.*
+.*:	27390428 	addiu	t9,t9,.*
+.*:	0320f809 	jalr	t9
+.*:	44846000 	mtc1	a0,\$f12
+.*:	44020000 	mfc1	v0,\$f0
+.*:	02400008 	jr	s2
+.*:	00000000 	nop
+
+00040530 <__call_fp_used8>:
+.*:	03e09021 	move	s2,ra
+.*:	3c190004 	lui	t9,.*
+.*:	27390448 	addiu	t9,t9,.*
+.*:	0320f809 	jalr	t9
+.*:	44846000 	mtc1	a0,\$f12
+.*:	44020000 	mfc1	v0,\$f0
+.*:	02400008 	jr	s2
+.*:	00000000 	nop
+
+00040550 <__call_fp_extern2>:
+.*:	03e09021 	move	s2,ra
+.*:	3c190004 	lui	t9,.*
+.*:	27390630 	addiu	t9,t9,.*
+.*:	0320f809 	jalr	t9
+.*:	44846000 	mtc1	a0,\$f12
+.*:	44020000 	mfc1	v0,\$f0
+.*:	02400008 	jr	s2
+.*:	00000000 	nop
+
+00040570 <__call_used5>:
+.*:	3c190004 	lui	t9,.*
+.*:	27390430 	addiu	t9,t9,.*
+.*:	03200008 	jr	t9
+.*:	44846000 	mtc1	a0,\$f12
+
+00040580 <__call_used9>:
+.*:	3c190004 	lui	t9,.*
+.*:	27390450 	addiu	t9,t9,.*
+.*:	03200008 	jr	t9
+.*:	44846000 	mtc1	a0,\$f12
+
+00040590 <__call_extern3>:
+.*:	3c190004 	lui	t9,.*
+.*:	27390620 	addiu	t9,t9,.*
+.*:	03200008 	jr	t9
+.*:	44846000 	mtc1	a0,\$f12
+
+000405a0 <__call_fp_used6>:
+.*:	03e09021 	move	s2,ra
+.*:	3c190004 	lui	t9,.*
+.*:	27390438 	addiu	t9,t9,.*
+.*:	0320f809 	jalr	t9
+.*:	44846000 	mtc1	a0,\$f12
+.*:	44020000 	mfc1	v0,\$f0
+.*:	02400008 	jr	s2
+.*:	00000000 	nop
+
+000405c0 <__call_fp_used10>:
+.*:	03e09021 	move	s2,ra
+.*:	3c190004 	lui	t9,.*
+.*:	27390458 	addiu	t9,t9,.*
+.*:	0320f809 	jalr	t9
+.*:	44846000 	mtc1	a0,\$f12
+.*:	44020000 	mfc1	v0,\$f0
+.*:	02400008 	jr	s2
+.*:	00000000 	nop
+
+000405e0 <__call_fp_extern4>:
+.*:	03e09021 	move	s2,ra
+.*:	3c190004 	lui	t9,.*
+.*:	27390640 	addiu	t9,t9,.*
+.*:	0320f809 	jalr	t9
+.*:	44846000 	mtc1	a0,\$f12
+.*:	44020000 	mfc1	v0,\$f0
+.*:	02400008 	jr	s2
+.*:	00000000 	nop
+
+Disassembly of section \.plt:
+
+00040600 <.*>:
+.*:	3c1c0005 	lui	gp,0x5
+.*:	8f990400 	lw	t9,1024\(gp\)
+.*:	279c0400 	addiu	gp,gp,1024
+.*:	031cc023 	subu	t8,t8,gp
+.*:	03e07821 	move	t7,ra
+.*:	0018c082 	srl	t8,t8,0x2
+.*:	0320f809 	jalr	t9
+.*:	2718fffe 	addiu	t8,t8,-2
+
+00040620 <extern3@plt>:
+.*:	3c0f0005 	lui	t7,0x5
+.*:	8df90408 	lw	t9,1032\(t7\)
+.*:	25f80408 	addiu	t8,t7,1032
+.*:	03200008 	jr	t9
+
+00040630 <extern2@plt>:
+.*:	3c0f0005 	lui	t7,0x5
+.*:	8df9040c 	lw	t9,1036\(t7\)
+.*:	25f8040c 	addiu	t8,t7,1036
+.*:	03200008 	jr	t9
+
+00040640 <extern4@plt>:
+.*:	3c0f0005 	lui	t7,0x5
+.*:	8df90410 	lw	t9,1040\(t7\)
+.*:	25f80410 	addiu	t8,t7,1040
+.*:	03200008 	jr	t9
+
+00040650 <extern1@plt>:
+.*:	3c0f0005 	lui	t7,0x5
+.*:	8df90414 	lw	t9,1044\(t7\)
+.*:	25f80414 	addiu	t8,t7,1044
+.*:	03200008 	jr	t9
+.*:	00000000 	nop
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3.gd b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3.gd
new file mode 100644
index 0000000..9297fe6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3.gd
@@ -0,0 +1,23 @@
+
+Primary GOT:
+ Canonical gp value: 00057ff0
+
+ Reserved entries:
+   Address     Access  Initial Purpose
+  00050000 -32752\(gp\) 00000000 Lazy resolver
+  00050004 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+
+PLT GOT:
+
+ Reserved entries:
+   Address  Initial Purpose
+  00050400 00000000 PLT lazy resolver
+  00050404 00000000 Module pointer
+
+ Entries:
+   Address  Initial Sym.Val. Type    Ndx Name
+  00050408 00040600 00040620 FUNC    UND extern3
+  0005040c 00040600 00040630 FUNC    UND extern2
+  00050410 00040600 00040640 FUNC    UND extern4
+  00050414 00040600 00040650 FUNC    UND extern1
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3.inc b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3.inc
new file mode 100644
index 0000000..9611611
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3.inc
@@ -0,0 +1,59 @@
+	.macro	test_call,name
+	.set	mips16
+	.text
+	.ent	test_\name
+test_\name:
+	jal	\name
+	.end	test_\name
+	.endm
+
+	.macro	call_stub,name
+	.set	nomips16
+	.section .mips16.call.\name, "ax", @progbits
+	.ent	__call_\name
+__call_\name:
+	la	$25,\name
+	jr	$25
+	mtc1	$4,$f12
+	.end	__call_\name
+
+	test_call \name
+	.endm
+
+	.macro	call_fp_stub,name
+	.set	nomips16
+	.section .mips16.call.fp.\name, "ax", @progbits
+	.ent	__call_fp_\name
+__call_fp_\name:
+	move	$18,$31
+	la	$25,\name
+	jalr	$25
+	mtc1	$4,$f12
+	mfc1	$2,$f0
+	jr	$18
+	nop
+	.end	__call_fp_\name
+
+	test_call \name
+	.endm
+
+	.macro	lstub,name,mode
+	.set	\mode
+	.text
+	.ent	\name
+\name:
+	jr	$31
+	nop
+	.end	\name
+	.endm
+
+	.macro	hstub,name,mode
+	.globl	\name
+	.hidden	\name
+	lstub	\name, \mode
+	.endm
+
+	.macro	gstub,name,mode
+	.globl	\name
+	lstub	\name, \mode
+	.endm
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3.rd b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3.rd
new file mode 100644
index 0000000..6293cf7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3.rd
@@ -0,0 +1,7 @@
+
+Relocation section '\.rel\.plt' at offset .* contains 4 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name
+00050408  .*7f R_MIPS_JUMP_SLOT  00040620   extern3
+0005040c  .*7f R_MIPS_JUMP_SLOT  00040630   extern2
+00050410  .*7f R_MIPS_JUMP_SLOT  00040640   extern4
+00050414  .*7f R_MIPS_JUMP_SLOT  00040650   extern1
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3a.s
new file mode 100644
index 0000000..bbe3a67
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3a.s
@@ -0,0 +1,59 @@
+	.abicalls
+	.option	pic0
+	.set	noreorder
+	.include "mips16-pic-3.inc"
+
+	# For symbols called by a .call stub in this file.
+	hstub	unused1,mips16
+
+	# For symbols called by a .call.fp stub in this file.
+	hstub	unused2,mips16
+
+	# For symbols called by a .call stub in another file.
+	hstub	unused3,mips16
+
+	# For symbols called by a .call.fp stub in another file.
+	hstub	unused4,mips16
+
+
+	# For symbols called by a .call stub in this file.
+	lstub	used1,nomips16
+
+	# For symbols called by a .call.fp stub in this file.
+	lstub	used2,nomips16
+
+	# For symbols called by a .call stub in this file.
+	hstub	used3,nomips16
+
+	# For symbols called by a .call.fp stub in this file.
+	hstub	used4,nomips16
+
+	# For symbols called by a .call stub in another file.
+	hstub	used5,nomips16
+
+	# For symbols called by a .call.fp stub in another file.
+	hstub	used6,nomips16
+
+	# For symbols called by a .call stub in this file.
+	gstub	used7,nomips16
+
+	# For symbols called by a .call.fp stub in this file.
+	gstub	used8,nomips16
+
+	# For symbols called by a .call stub in another file.
+	gstub	used9,nomips16
+
+	# For symbols called by a .call.fp stub in another file.
+	gstub	used10,nomips16
+
+	call_stub unused1
+	call_stub used1
+	call_stub used3
+	call_stub used7
+	call_stub extern1
+
+	call_fp_stub unused2
+	call_fp_stub used2
+	call_fp_stub used4
+	call_fp_stub used8
+	call_fp_stub extern2
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3b.s
new file mode 100644
index 0000000..3003145
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-3b.s
@@ -0,0 +1,14 @@
+	.abicalls
+	.option	pic0
+	.set	noreorder
+	.include "mips16-pic-3.inc"
+
+	call_stub unused3
+	call_stub used5
+	call_stub used9
+	call_stub extern3
+
+	call_fp_stub unused4
+	call_fp_stub used6
+	call_fp_stub used10
+	call_fp_stub extern4
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4.ver b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4.ver
new file mode 100644
index 0000000..fc7b185
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4.ver
@@ -0,0 +1,8 @@
+V1 {
+  global:
+    f1;
+    f2;
+    f3;
+  local:
+    *;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4a.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4a.dd
new file mode 100644
index 0000000..d4e4f22
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4a.dd
@@ -0,0 +1,23 @@
+
+.*
+
+
+Disassembly of section \.text:
+
+00040400 <f2>:
+.*	jr	ra
+.*	nop
+
+00040408 <f3>:
+.*	jr	ra
+.*	nop
+
+00040410 <_f1>:
+.*	jr	ra
+.*	nop
+#...
+
+00040420 <f1@@V1>:
+.*	lw	t9,-32744\(gp\)
+.*	jr	t9
+.*	mfc1	a0,\$f12
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4a.gd b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4a.gd
new file mode 100644
index 0000000..1ab835e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4a.gd
@@ -0,0 +1,13 @@
+
+Primary GOT:
+ Canonical gp value: 00057ff0
+
+ Reserved entries:
+   Address     Access  Initial Purpose
+  00050000 -32752\(gp\) 00000000 Lazy resolver
+  00050004 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+ Local entries:
+   Address     Access  Initial
+  00050008 -32744\(gp\) 00040411
+
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4a.nd b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4a.nd
new file mode 100644
index 0000000..6eca610
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4a.nd
@@ -0,0 +1,10 @@
+
+Symbol table '\.dynsym' contains 6 entries:
+   Num:    Value  Size Type    Bind   Vis      Ndx Name
+     0: 00000000     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 00040400     0 SECTION LOCAL  DEFAULT   .* 
+     2: 00040420    12 FUNC    GLOBAL DEFAULT   .* f1@@V1
+     3: 00000000     0 OBJECT  GLOBAL DEFAULT  ABS V1
+     4: 00040408     8 FUNC    GLOBAL DEFAULT   .* f3@@V1
+     5: 00040400     8 FUNC    GLOBAL DEFAULT   .* f2@@V1
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4a.s
new file mode 100644
index 0000000..812d9d7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4a.s
@@ -0,0 +1,33 @@
+	.abicalls
+	.set	noreorder
+
+	# Define a stub for f1, which is defined in another file.
+	#
+	# (It's questionable whether defining the stub and real function
+	# in separate files is really valid or useful.  However, if we
+	# accept it without error, we should do something useful with it.)
+
+	.section .mips16.fn.f1, "ax", @progbits
+	.ent	__fn
+__fn:
+	.reloc	0,R_MIPS_NONE,f1
+	la	$25,_f1
+	jr	$25
+	mfc1	$4,$f12
+	.end	__fn
+
+	# Define dummy functions for the executable to call.
+
+	.macro	dummy,name
+	.text
+	.global	\name
+	.type	\name,@function
+	.ent	\name
+\name:
+	jr	$31
+	nop
+	.end	\name
+	.endm
+
+	dummy	f2
+	dummy	f3
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4b.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4b.dd
new file mode 100644
index 0000000..ddc55c3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4b.dd
@@ -0,0 +1,35 @@
+
+.*
+
+
+Disassembly of section \.text:
+
+00040400 <__start>:
+.*	jalx	40410 <__call>
+.*	nop
+.*	jalx	40420 <__call_fp>
+.*	nop
+#...
+
+00040410 <__call>:
+.*0004 	lui	t9,.*
+.*0460 	addiu	t9,t9,.*
+.*	jr	t9
+.*	nop
+
+00040420 <__call_fp>:
+.*0004 	lui	t9,.*
+.*0470 	addiu	t9,t9,.*
+.*	jr	t9
+.*	nop
+
+Disassembly of section \.plt:
+
+00040440 <_PROCEDURE_LINKAGE_TABLE_>:
+#...
+
+00040460 <f2@plt>:
+#...
+
+00040470 <f3@plt>:
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4b.s
new file mode 100644
index 0000000..9cb5cb4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4b.s
@@ -0,0 +1,15 @@
+	.abicalls
+	.set	noreorder
+
+	# Define a MIPS16 function f1@@V1.
+
+	.global	_f1
+	.symver	_f1,f1@@V1
+
+	.set	mips16
+	.type	_f1,@function
+	.ent	_f1
+_f1:
+	jr	$31
+	nop
+	.end	_f1
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4c.s b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4c.s
new file mode 100644
index 0000000..338d378
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/mips16-pic-4c.s
@@ -0,0 +1,38 @@
+	.abicalls
+	.option	pic0
+	.set	noreorder
+
+	# Create a call stub for f2.  We pretend that f2 takes floating-point
+	# arguments but doesn't return a floating-point value.
+
+	.section .mips16.call.f2, "ax", @progbits
+	.ent	__call
+__call:
+	la	$25,f2
+	jr	$25
+	nop
+	.end	__call
+
+	# Create a call stub for f3.  We pretend that f3 returns a
+	# floating-point value.
+
+	.section .mips16.call.fp.f3, "ax", @progbits
+	.ent	__call_fp
+__call_fp:
+	la	$25,f3
+	jr	$25
+	nop
+	.end	__call_fp
+
+	# Make sure that f2 and f3 are called from MIPS16 code.
+	.set	mips16
+	.text
+	.global	__start
+	.type	__start,@function
+	.ent	__start
+__start:
+	jal	f2
+	nop
+	jal	f3
+	nop
+	.end	__start
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-1-1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-1-1.s
new file mode 100644
index 0000000..8f70ee1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-1-1.s
@@ -0,0 +1,16384 @@
+.globl sym_1_1
+sym_1_1: la $2, sym_1_1
+.globl sym_1_2
+sym_1_2: la $2, sym_1_2
+.globl sym_1_3
+sym_1_3: la $2, sym_1_3
+.globl sym_1_4
+sym_1_4: la $2, sym_1_4
+.globl sym_1_5
+sym_1_5: la $2, sym_1_5
+.globl sym_1_6
+sym_1_6: la $2, sym_1_6
+.globl sym_1_7
+sym_1_7: la $2, sym_1_7
+.globl sym_1_8
+sym_1_8: la $2, sym_1_8
+.globl sym_1_9
+sym_1_9: la $2, sym_1_9
+.globl sym_1_10
+sym_1_10: la $2, sym_1_10
+.globl sym_1_11
+sym_1_11: la $2, sym_1_11
+.globl sym_1_12
+sym_1_12: la $2, sym_1_12
+.globl sym_1_13
+sym_1_13: la $2, sym_1_13
+.globl sym_1_14
+sym_1_14: la $2, sym_1_14
+.globl sym_1_15
+sym_1_15: la $2, sym_1_15
+.globl sym_1_16
+sym_1_16: la $2, sym_1_16
+.globl sym_1_17
+sym_1_17: la $2, sym_1_17
+.globl sym_1_18
+sym_1_18: la $2, sym_1_18
+.globl sym_1_19
+sym_1_19: la $2, sym_1_19
+.globl sym_1_20
+sym_1_20: la $2, sym_1_20
+.globl sym_1_21
+sym_1_21: la $2, sym_1_21
+.globl sym_1_22
+sym_1_22: la $2, sym_1_22
+.globl sym_1_23
+sym_1_23: la $2, sym_1_23
+.globl sym_1_24
+sym_1_24: la $2, sym_1_24
+.globl sym_1_25
+sym_1_25: la $2, sym_1_25
+.globl sym_1_26
+sym_1_26: la $2, sym_1_26
+.globl sym_1_27
+sym_1_27: la $2, sym_1_27
+.globl sym_1_28
+sym_1_28: la $2, sym_1_28
+.globl sym_1_29
+sym_1_29: la $2, sym_1_29
+.globl sym_1_30
+sym_1_30: la $2, sym_1_30
+.globl sym_1_31
+sym_1_31: la $2, sym_1_31
+.globl sym_1_32
+sym_1_32: la $2, sym_1_32
+.globl sym_1_33
+sym_1_33: la $2, sym_1_33
+.globl sym_1_34
+sym_1_34: la $2, sym_1_34
+.globl sym_1_35
+sym_1_35: la $2, sym_1_35
+.globl sym_1_36
+sym_1_36: la $2, sym_1_36
+.globl sym_1_37
+sym_1_37: la $2, sym_1_37
+.globl sym_1_38
+sym_1_38: la $2, sym_1_38
+.globl sym_1_39
+sym_1_39: la $2, sym_1_39
+.globl sym_1_40
+sym_1_40: la $2, sym_1_40
+.globl sym_1_41
+sym_1_41: la $2, sym_1_41
+.globl sym_1_42
+sym_1_42: la $2, sym_1_42
+.globl sym_1_43
+sym_1_43: la $2, sym_1_43
+.globl sym_1_44
+sym_1_44: la $2, sym_1_44
+.globl sym_1_45
+sym_1_45: la $2, sym_1_45
+.globl sym_1_46
+sym_1_46: la $2, sym_1_46
+.globl sym_1_47
+sym_1_47: la $2, sym_1_47
+.globl sym_1_48
+sym_1_48: la $2, sym_1_48
+.globl sym_1_49
+sym_1_49: la $2, sym_1_49
+.globl sym_1_50
+sym_1_50: la $2, sym_1_50
+.globl sym_1_51
+sym_1_51: la $2, sym_1_51
+.globl sym_1_52
+sym_1_52: la $2, sym_1_52
+.globl sym_1_53
+sym_1_53: la $2, sym_1_53
+.globl sym_1_54
+sym_1_54: la $2, sym_1_54
+.globl sym_1_55
+sym_1_55: la $2, sym_1_55
+.globl sym_1_56
+sym_1_56: la $2, sym_1_56
+.globl sym_1_57
+sym_1_57: la $2, sym_1_57
+.globl sym_1_58
+sym_1_58: la $2, sym_1_58
+.globl sym_1_59
+sym_1_59: la $2, sym_1_59
+.globl sym_1_60
+sym_1_60: la $2, sym_1_60
+.globl sym_1_61
+sym_1_61: la $2, sym_1_61
+.globl sym_1_62
+sym_1_62: la $2, sym_1_62
+.globl sym_1_63
+sym_1_63: la $2, sym_1_63
+.globl sym_1_64
+sym_1_64: la $2, sym_1_64
+.globl sym_1_65
+sym_1_65: la $2, sym_1_65
+.globl sym_1_66
+sym_1_66: la $2, sym_1_66
+.globl sym_1_67
+sym_1_67: la $2, sym_1_67
+.globl sym_1_68
+sym_1_68: la $2, sym_1_68
+.globl sym_1_69
+sym_1_69: la $2, sym_1_69
+.globl sym_1_70
+sym_1_70: la $2, sym_1_70
+.globl sym_1_71
+sym_1_71: la $2, sym_1_71
+.globl sym_1_72
+sym_1_72: la $2, sym_1_72
+.globl sym_1_73
+sym_1_73: la $2, sym_1_73
+.globl sym_1_74
+sym_1_74: la $2, sym_1_74
+.globl sym_1_75
+sym_1_75: la $2, sym_1_75
+.globl sym_1_76
+sym_1_76: la $2, sym_1_76
+.globl sym_1_77
+sym_1_77: la $2, sym_1_77
+.globl sym_1_78
+sym_1_78: la $2, sym_1_78
+.globl sym_1_79
+sym_1_79: la $2, sym_1_79
+.globl sym_1_80
+sym_1_80: la $2, sym_1_80
+.globl sym_1_81
+sym_1_81: la $2, sym_1_81
+.globl sym_1_82
+sym_1_82: la $2, sym_1_82
+.globl sym_1_83
+sym_1_83: la $2, sym_1_83
+.globl sym_1_84
+sym_1_84: la $2, sym_1_84
+.globl sym_1_85
+sym_1_85: la $2, sym_1_85
+.globl sym_1_86
+sym_1_86: la $2, sym_1_86
+.globl sym_1_87
+sym_1_87: la $2, sym_1_87
+.globl sym_1_88
+sym_1_88: la $2, sym_1_88
+.globl sym_1_89
+sym_1_89: la $2, sym_1_89
+.globl sym_1_90
+sym_1_90: la $2, sym_1_90
+.globl sym_1_91
+sym_1_91: la $2, sym_1_91
+.globl sym_1_92
+sym_1_92: la $2, sym_1_92
+.globl sym_1_93
+sym_1_93: la $2, sym_1_93
+.globl sym_1_94
+sym_1_94: la $2, sym_1_94
+.globl sym_1_95
+sym_1_95: la $2, sym_1_95
+.globl sym_1_96
+sym_1_96: la $2, sym_1_96
+.globl sym_1_97
+sym_1_97: la $2, sym_1_97
+.globl sym_1_98
+sym_1_98: la $2, sym_1_98
+.globl sym_1_99
+sym_1_99: la $2, sym_1_99
+.globl sym_1_100
+sym_1_100: la $2, sym_1_100
+.globl sym_1_101
+sym_1_101: la $2, sym_1_101
+.globl sym_1_102
+sym_1_102: la $2, sym_1_102
+.globl sym_1_103
+sym_1_103: la $2, sym_1_103
+.globl sym_1_104
+sym_1_104: la $2, sym_1_104
+.globl sym_1_105
+sym_1_105: la $2, sym_1_105
+.globl sym_1_106
+sym_1_106: la $2, sym_1_106
+.globl sym_1_107
+sym_1_107: la $2, sym_1_107
+.globl sym_1_108
+sym_1_108: la $2, sym_1_108
+.globl sym_1_109
+sym_1_109: la $2, sym_1_109
+.globl sym_1_110
+sym_1_110: la $2, sym_1_110
+.globl sym_1_111
+sym_1_111: la $2, sym_1_111
+.globl sym_1_112
+sym_1_112: la $2, sym_1_112
+.globl sym_1_113
+sym_1_113: la $2, sym_1_113
+.globl sym_1_114
+sym_1_114: la $2, sym_1_114
+.globl sym_1_115
+sym_1_115: la $2, sym_1_115
+.globl sym_1_116
+sym_1_116: la $2, sym_1_116
+.globl sym_1_117
+sym_1_117: la $2, sym_1_117
+.globl sym_1_118
+sym_1_118: la $2, sym_1_118
+.globl sym_1_119
+sym_1_119: la $2, sym_1_119
+.globl sym_1_120
+sym_1_120: la $2, sym_1_120
+.globl sym_1_121
+sym_1_121: la $2, sym_1_121
+.globl sym_1_122
+sym_1_122: la $2, sym_1_122
+.globl sym_1_123
+sym_1_123: la $2, sym_1_123
+.globl sym_1_124
+sym_1_124: la $2, sym_1_124
+.globl sym_1_125
+sym_1_125: la $2, sym_1_125
+.globl sym_1_126
+sym_1_126: la $2, sym_1_126
+.globl sym_1_127
+sym_1_127: la $2, sym_1_127
+.globl sym_1_128
+sym_1_128: la $2, sym_1_128
+.globl sym_1_129
+sym_1_129: la $2, sym_1_129
+.globl sym_1_130
+sym_1_130: la $2, sym_1_130
+.globl sym_1_131
+sym_1_131: la $2, sym_1_131
+.globl sym_1_132
+sym_1_132: la $2, sym_1_132
+.globl sym_1_133
+sym_1_133: la $2, sym_1_133
+.globl sym_1_134
+sym_1_134: la $2, sym_1_134
+.globl sym_1_135
+sym_1_135: la $2, sym_1_135
+.globl sym_1_136
+sym_1_136: la $2, sym_1_136
+.globl sym_1_137
+sym_1_137: la $2, sym_1_137
+.globl sym_1_138
+sym_1_138: la $2, sym_1_138
+.globl sym_1_139
+sym_1_139: la $2, sym_1_139
+.globl sym_1_140
+sym_1_140: la $2, sym_1_140
+.globl sym_1_141
+sym_1_141: la $2, sym_1_141
+.globl sym_1_142
+sym_1_142: la $2, sym_1_142
+.globl sym_1_143
+sym_1_143: la $2, sym_1_143
+.globl sym_1_144
+sym_1_144: la $2, sym_1_144
+.globl sym_1_145
+sym_1_145: la $2, sym_1_145
+.globl sym_1_146
+sym_1_146: la $2, sym_1_146
+.globl sym_1_147
+sym_1_147: la $2, sym_1_147
+.globl sym_1_148
+sym_1_148: la $2, sym_1_148
+.globl sym_1_149
+sym_1_149: la $2, sym_1_149
+.globl sym_1_150
+sym_1_150: la $2, sym_1_150
+.globl sym_1_151
+sym_1_151: la $2, sym_1_151
+.globl sym_1_152
+sym_1_152: la $2, sym_1_152
+.globl sym_1_153
+sym_1_153: la $2, sym_1_153
+.globl sym_1_154
+sym_1_154: la $2, sym_1_154
+.globl sym_1_155
+sym_1_155: la $2, sym_1_155
+.globl sym_1_156
+sym_1_156: la $2, sym_1_156
+.globl sym_1_157
+sym_1_157: la $2, sym_1_157
+.globl sym_1_158
+sym_1_158: la $2, sym_1_158
+.globl sym_1_159
+sym_1_159: la $2, sym_1_159
+.globl sym_1_160
+sym_1_160: la $2, sym_1_160
+.globl sym_1_161
+sym_1_161: la $2, sym_1_161
+.globl sym_1_162
+sym_1_162: la $2, sym_1_162
+.globl sym_1_163
+sym_1_163: la $2, sym_1_163
+.globl sym_1_164
+sym_1_164: la $2, sym_1_164
+.globl sym_1_165
+sym_1_165: la $2, sym_1_165
+.globl sym_1_166
+sym_1_166: la $2, sym_1_166
+.globl sym_1_167
+sym_1_167: la $2, sym_1_167
+.globl sym_1_168
+sym_1_168: la $2, sym_1_168
+.globl sym_1_169
+sym_1_169: la $2, sym_1_169
+.globl sym_1_170
+sym_1_170: la $2, sym_1_170
+.globl sym_1_171
+sym_1_171: la $2, sym_1_171
+.globl sym_1_172
+sym_1_172: la $2, sym_1_172
+.globl sym_1_173
+sym_1_173: la $2, sym_1_173
+.globl sym_1_174
+sym_1_174: la $2, sym_1_174
+.globl sym_1_175
+sym_1_175: la $2, sym_1_175
+.globl sym_1_176
+sym_1_176: la $2, sym_1_176
+.globl sym_1_177
+sym_1_177: la $2, sym_1_177
+.globl sym_1_178
+sym_1_178: la $2, sym_1_178
+.globl sym_1_179
+sym_1_179: la $2, sym_1_179
+.globl sym_1_180
+sym_1_180: la $2, sym_1_180
+.globl sym_1_181
+sym_1_181: la $2, sym_1_181
+.globl sym_1_182
+sym_1_182: la $2, sym_1_182
+.globl sym_1_183
+sym_1_183: la $2, sym_1_183
+.globl sym_1_184
+sym_1_184: la $2, sym_1_184
+.globl sym_1_185
+sym_1_185: la $2, sym_1_185
+.globl sym_1_186
+sym_1_186: la $2, sym_1_186
+.globl sym_1_187
+sym_1_187: la $2, sym_1_187
+.globl sym_1_188
+sym_1_188: la $2, sym_1_188
+.globl sym_1_189
+sym_1_189: la $2, sym_1_189
+.globl sym_1_190
+sym_1_190: la $2, sym_1_190
+.globl sym_1_191
+sym_1_191: la $2, sym_1_191
+.globl sym_1_192
+sym_1_192: la $2, sym_1_192
+.globl sym_1_193
+sym_1_193: la $2, sym_1_193
+.globl sym_1_194
+sym_1_194: la $2, sym_1_194
+.globl sym_1_195
+sym_1_195: la $2, sym_1_195
+.globl sym_1_196
+sym_1_196: la $2, sym_1_196
+.globl sym_1_197
+sym_1_197: la $2, sym_1_197
+.globl sym_1_198
+sym_1_198: la $2, sym_1_198
+.globl sym_1_199
+sym_1_199: la $2, sym_1_199
+.globl sym_1_200
+sym_1_200: la $2, sym_1_200
+.globl sym_1_201
+sym_1_201: la $2, sym_1_201
+.globl sym_1_202
+sym_1_202: la $2, sym_1_202
+.globl sym_1_203
+sym_1_203: la $2, sym_1_203
+.globl sym_1_204
+sym_1_204: la $2, sym_1_204
+.globl sym_1_205
+sym_1_205: la $2, sym_1_205
+.globl sym_1_206
+sym_1_206: la $2, sym_1_206
+.globl sym_1_207
+sym_1_207: la $2, sym_1_207
+.globl sym_1_208
+sym_1_208: la $2, sym_1_208
+.globl sym_1_209
+sym_1_209: la $2, sym_1_209
+.globl sym_1_210
+sym_1_210: la $2, sym_1_210
+.globl sym_1_211
+sym_1_211: la $2, sym_1_211
+.globl sym_1_212
+sym_1_212: la $2, sym_1_212
+.globl sym_1_213
+sym_1_213: la $2, sym_1_213
+.globl sym_1_214
+sym_1_214: la $2, sym_1_214
+.globl sym_1_215
+sym_1_215: la $2, sym_1_215
+.globl sym_1_216
+sym_1_216: la $2, sym_1_216
+.globl sym_1_217
+sym_1_217: la $2, sym_1_217
+.globl sym_1_218
+sym_1_218: la $2, sym_1_218
+.globl sym_1_219
+sym_1_219: la $2, sym_1_219
+.globl sym_1_220
+sym_1_220: la $2, sym_1_220
+.globl sym_1_221
+sym_1_221: la $2, sym_1_221
+.globl sym_1_222
+sym_1_222: la $2, sym_1_222
+.globl sym_1_223
+sym_1_223: la $2, sym_1_223
+.globl sym_1_224
+sym_1_224: la $2, sym_1_224
+.globl sym_1_225
+sym_1_225: la $2, sym_1_225
+.globl sym_1_226
+sym_1_226: la $2, sym_1_226
+.globl sym_1_227
+sym_1_227: la $2, sym_1_227
+.globl sym_1_228
+sym_1_228: la $2, sym_1_228
+.globl sym_1_229
+sym_1_229: la $2, sym_1_229
+.globl sym_1_230
+sym_1_230: la $2, sym_1_230
+.globl sym_1_231
+sym_1_231: la $2, sym_1_231
+.globl sym_1_232
+sym_1_232: la $2, sym_1_232
+.globl sym_1_233
+sym_1_233: la $2, sym_1_233
+.globl sym_1_234
+sym_1_234: la $2, sym_1_234
+.globl sym_1_235
+sym_1_235: la $2, sym_1_235
+.globl sym_1_236
+sym_1_236: la $2, sym_1_236
+.globl sym_1_237
+sym_1_237: la $2, sym_1_237
+.globl sym_1_238
+sym_1_238: la $2, sym_1_238
+.globl sym_1_239
+sym_1_239: la $2, sym_1_239
+.globl sym_1_240
+sym_1_240: la $2, sym_1_240
+.globl sym_1_241
+sym_1_241: la $2, sym_1_241
+.globl sym_1_242
+sym_1_242: la $2, sym_1_242
+.globl sym_1_243
+sym_1_243: la $2, sym_1_243
+.globl sym_1_244
+sym_1_244: la $2, sym_1_244
+.globl sym_1_245
+sym_1_245: la $2, sym_1_245
+.globl sym_1_246
+sym_1_246: la $2, sym_1_246
+.globl sym_1_247
+sym_1_247: la $2, sym_1_247
+.globl sym_1_248
+sym_1_248: la $2, sym_1_248
+.globl sym_1_249
+sym_1_249: la $2, sym_1_249
+.globl sym_1_250
+sym_1_250: la $2, sym_1_250
+.globl sym_1_251
+sym_1_251: la $2, sym_1_251
+.globl sym_1_252
+sym_1_252: la $2, sym_1_252
+.globl sym_1_253
+sym_1_253: la $2, sym_1_253
+.globl sym_1_254
+sym_1_254: la $2, sym_1_254
+.globl sym_1_255
+sym_1_255: la $2, sym_1_255
+.globl sym_1_256
+sym_1_256: la $2, sym_1_256
+.globl sym_1_257
+sym_1_257: la $2, sym_1_257
+.globl sym_1_258
+sym_1_258: la $2, sym_1_258
+.globl sym_1_259
+sym_1_259: la $2, sym_1_259
+.globl sym_1_260
+sym_1_260: la $2, sym_1_260
+.globl sym_1_261
+sym_1_261: la $2, sym_1_261
+.globl sym_1_262
+sym_1_262: la $2, sym_1_262
+.globl sym_1_263
+sym_1_263: la $2, sym_1_263
+.globl sym_1_264
+sym_1_264: la $2, sym_1_264
+.globl sym_1_265
+sym_1_265: la $2, sym_1_265
+.globl sym_1_266
+sym_1_266: la $2, sym_1_266
+.globl sym_1_267
+sym_1_267: la $2, sym_1_267
+.globl sym_1_268
+sym_1_268: la $2, sym_1_268
+.globl sym_1_269
+sym_1_269: la $2, sym_1_269
+.globl sym_1_270
+sym_1_270: la $2, sym_1_270
+.globl sym_1_271
+sym_1_271: la $2, sym_1_271
+.globl sym_1_272
+sym_1_272: la $2, sym_1_272
+.globl sym_1_273
+sym_1_273: la $2, sym_1_273
+.globl sym_1_274
+sym_1_274: la $2, sym_1_274
+.globl sym_1_275
+sym_1_275: la $2, sym_1_275
+.globl sym_1_276
+sym_1_276: la $2, sym_1_276
+.globl sym_1_277
+sym_1_277: la $2, sym_1_277
+.globl sym_1_278
+sym_1_278: la $2, sym_1_278
+.globl sym_1_279
+sym_1_279: la $2, sym_1_279
+.globl sym_1_280
+sym_1_280: la $2, sym_1_280
+.globl sym_1_281
+sym_1_281: la $2, sym_1_281
+.globl sym_1_282
+sym_1_282: la $2, sym_1_282
+.globl sym_1_283
+sym_1_283: la $2, sym_1_283
+.globl sym_1_284
+sym_1_284: la $2, sym_1_284
+.globl sym_1_285
+sym_1_285: la $2, sym_1_285
+.globl sym_1_286
+sym_1_286: la $2, sym_1_286
+.globl sym_1_287
+sym_1_287: la $2, sym_1_287
+.globl sym_1_288
+sym_1_288: la $2, sym_1_288
+.globl sym_1_289
+sym_1_289: la $2, sym_1_289
+.globl sym_1_290
+sym_1_290: la $2, sym_1_290
+.globl sym_1_291
+sym_1_291: la $2, sym_1_291
+.globl sym_1_292
+sym_1_292: la $2, sym_1_292
+.globl sym_1_293
+sym_1_293: la $2, sym_1_293
+.globl sym_1_294
+sym_1_294: la $2, sym_1_294
+.globl sym_1_295
+sym_1_295: la $2, sym_1_295
+.globl sym_1_296
+sym_1_296: la $2, sym_1_296
+.globl sym_1_297
+sym_1_297: la $2, sym_1_297
+.globl sym_1_298
+sym_1_298: la $2, sym_1_298
+.globl sym_1_299
+sym_1_299: la $2, sym_1_299
+.globl sym_1_300
+sym_1_300: la $2, sym_1_300
+.globl sym_1_301
+sym_1_301: la $2, sym_1_301
+.globl sym_1_302
+sym_1_302: la $2, sym_1_302
+.globl sym_1_303
+sym_1_303: la $2, sym_1_303
+.globl sym_1_304
+sym_1_304: la $2, sym_1_304
+.globl sym_1_305
+sym_1_305: la $2, sym_1_305
+.globl sym_1_306
+sym_1_306: la $2, sym_1_306
+.globl sym_1_307
+sym_1_307: la $2, sym_1_307
+.globl sym_1_308
+sym_1_308: la $2, sym_1_308
+.globl sym_1_309
+sym_1_309: la $2, sym_1_309
+.globl sym_1_310
+sym_1_310: la $2, sym_1_310
+.globl sym_1_311
+sym_1_311: la $2, sym_1_311
+.globl sym_1_312
+sym_1_312: la $2, sym_1_312
+.globl sym_1_313
+sym_1_313: la $2, sym_1_313
+.globl sym_1_314
+sym_1_314: la $2, sym_1_314
+.globl sym_1_315
+sym_1_315: la $2, sym_1_315
+.globl sym_1_316
+sym_1_316: la $2, sym_1_316
+.globl sym_1_317
+sym_1_317: la $2, sym_1_317
+.globl sym_1_318
+sym_1_318: la $2, sym_1_318
+.globl sym_1_319
+sym_1_319: la $2, sym_1_319
+.globl sym_1_320
+sym_1_320: la $2, sym_1_320
+.globl sym_1_321
+sym_1_321: la $2, sym_1_321
+.globl sym_1_322
+sym_1_322: la $2, sym_1_322
+.globl sym_1_323
+sym_1_323: la $2, sym_1_323
+.globl sym_1_324
+sym_1_324: la $2, sym_1_324
+.globl sym_1_325
+sym_1_325: la $2, sym_1_325
+.globl sym_1_326
+sym_1_326: la $2, sym_1_326
+.globl sym_1_327
+sym_1_327: la $2, sym_1_327
+.globl sym_1_328
+sym_1_328: la $2, sym_1_328
+.globl sym_1_329
+sym_1_329: la $2, sym_1_329
+.globl sym_1_330
+sym_1_330: la $2, sym_1_330
+.globl sym_1_331
+sym_1_331: la $2, sym_1_331
+.globl sym_1_332
+sym_1_332: la $2, sym_1_332
+.globl sym_1_333
+sym_1_333: la $2, sym_1_333
+.globl sym_1_334
+sym_1_334: la $2, sym_1_334
+.globl sym_1_335
+sym_1_335: la $2, sym_1_335
+.globl sym_1_336
+sym_1_336: la $2, sym_1_336
+.globl sym_1_337
+sym_1_337: la $2, sym_1_337
+.globl sym_1_338
+sym_1_338: la $2, sym_1_338
+.globl sym_1_339
+sym_1_339: la $2, sym_1_339
+.globl sym_1_340
+sym_1_340: la $2, sym_1_340
+.globl sym_1_341
+sym_1_341: la $2, sym_1_341
+.globl sym_1_342
+sym_1_342: la $2, sym_1_342
+.globl sym_1_343
+sym_1_343: la $2, sym_1_343
+.globl sym_1_344
+sym_1_344: la $2, sym_1_344
+.globl sym_1_345
+sym_1_345: la $2, sym_1_345
+.globl sym_1_346
+sym_1_346: la $2, sym_1_346
+.globl sym_1_347
+sym_1_347: la $2, sym_1_347
+.globl sym_1_348
+sym_1_348: la $2, sym_1_348
+.globl sym_1_349
+sym_1_349: la $2, sym_1_349
+.globl sym_1_350
+sym_1_350: la $2, sym_1_350
+.globl sym_1_351
+sym_1_351: la $2, sym_1_351
+.globl sym_1_352
+sym_1_352: la $2, sym_1_352
+.globl sym_1_353
+sym_1_353: la $2, sym_1_353
+.globl sym_1_354
+sym_1_354: la $2, sym_1_354
+.globl sym_1_355
+sym_1_355: la $2, sym_1_355
+.globl sym_1_356
+sym_1_356: la $2, sym_1_356
+.globl sym_1_357
+sym_1_357: la $2, sym_1_357
+.globl sym_1_358
+sym_1_358: la $2, sym_1_358
+.globl sym_1_359
+sym_1_359: la $2, sym_1_359
+.globl sym_1_360
+sym_1_360: la $2, sym_1_360
+.globl sym_1_361
+sym_1_361: la $2, sym_1_361
+.globl sym_1_362
+sym_1_362: la $2, sym_1_362
+.globl sym_1_363
+sym_1_363: la $2, sym_1_363
+.globl sym_1_364
+sym_1_364: la $2, sym_1_364
+.globl sym_1_365
+sym_1_365: la $2, sym_1_365
+.globl sym_1_366
+sym_1_366: la $2, sym_1_366
+.globl sym_1_367
+sym_1_367: la $2, sym_1_367
+.globl sym_1_368
+sym_1_368: la $2, sym_1_368
+.globl sym_1_369
+sym_1_369: la $2, sym_1_369
+.globl sym_1_370
+sym_1_370: la $2, sym_1_370
+.globl sym_1_371
+sym_1_371: la $2, sym_1_371
+.globl sym_1_372
+sym_1_372: la $2, sym_1_372
+.globl sym_1_373
+sym_1_373: la $2, sym_1_373
+.globl sym_1_374
+sym_1_374: la $2, sym_1_374
+.globl sym_1_375
+sym_1_375: la $2, sym_1_375
+.globl sym_1_376
+sym_1_376: la $2, sym_1_376
+.globl sym_1_377
+sym_1_377: la $2, sym_1_377
+.globl sym_1_378
+sym_1_378: la $2, sym_1_378
+.globl sym_1_379
+sym_1_379: la $2, sym_1_379
+.globl sym_1_380
+sym_1_380: la $2, sym_1_380
+.globl sym_1_381
+sym_1_381: la $2, sym_1_381
+.globl sym_1_382
+sym_1_382: la $2, sym_1_382
+.globl sym_1_383
+sym_1_383: la $2, sym_1_383
+.globl sym_1_384
+sym_1_384: la $2, sym_1_384
+.globl sym_1_385
+sym_1_385: la $2, sym_1_385
+.globl sym_1_386
+sym_1_386: la $2, sym_1_386
+.globl sym_1_387
+sym_1_387: la $2, sym_1_387
+.globl sym_1_388
+sym_1_388: la $2, sym_1_388
+.globl sym_1_389
+sym_1_389: la $2, sym_1_389
+.globl sym_1_390
+sym_1_390: la $2, sym_1_390
+.globl sym_1_391
+sym_1_391: la $2, sym_1_391
+.globl sym_1_392
+sym_1_392: la $2, sym_1_392
+.globl sym_1_393
+sym_1_393: la $2, sym_1_393
+.globl sym_1_394
+sym_1_394: la $2, sym_1_394
+.globl sym_1_395
+sym_1_395: la $2, sym_1_395
+.globl sym_1_396
+sym_1_396: la $2, sym_1_396
+.globl sym_1_397
+sym_1_397: la $2, sym_1_397
+.globl sym_1_398
+sym_1_398: la $2, sym_1_398
+.globl sym_1_399
+sym_1_399: la $2, sym_1_399
+.globl sym_1_400
+sym_1_400: la $2, sym_1_400
+.globl sym_1_401
+sym_1_401: la $2, sym_1_401
+.globl sym_1_402
+sym_1_402: la $2, sym_1_402
+.globl sym_1_403
+sym_1_403: la $2, sym_1_403
+.globl sym_1_404
+sym_1_404: la $2, sym_1_404
+.globl sym_1_405
+sym_1_405: la $2, sym_1_405
+.globl sym_1_406
+sym_1_406: la $2, sym_1_406
+.globl sym_1_407
+sym_1_407: la $2, sym_1_407
+.globl sym_1_408
+sym_1_408: la $2, sym_1_408
+.globl sym_1_409
+sym_1_409: la $2, sym_1_409
+.globl sym_1_410
+sym_1_410: la $2, sym_1_410
+.globl sym_1_411
+sym_1_411: la $2, sym_1_411
+.globl sym_1_412
+sym_1_412: la $2, sym_1_412
+.globl sym_1_413
+sym_1_413: la $2, sym_1_413
+.globl sym_1_414
+sym_1_414: la $2, sym_1_414
+.globl sym_1_415
+sym_1_415: la $2, sym_1_415
+.globl sym_1_416
+sym_1_416: la $2, sym_1_416
+.globl sym_1_417
+sym_1_417: la $2, sym_1_417
+.globl sym_1_418
+sym_1_418: la $2, sym_1_418
+.globl sym_1_419
+sym_1_419: la $2, sym_1_419
+.globl sym_1_420
+sym_1_420: la $2, sym_1_420
+.globl sym_1_421
+sym_1_421: la $2, sym_1_421
+.globl sym_1_422
+sym_1_422: la $2, sym_1_422
+.globl sym_1_423
+sym_1_423: la $2, sym_1_423
+.globl sym_1_424
+sym_1_424: la $2, sym_1_424
+.globl sym_1_425
+sym_1_425: la $2, sym_1_425
+.globl sym_1_426
+sym_1_426: la $2, sym_1_426
+.globl sym_1_427
+sym_1_427: la $2, sym_1_427
+.globl sym_1_428
+sym_1_428: la $2, sym_1_428
+.globl sym_1_429
+sym_1_429: la $2, sym_1_429
+.globl sym_1_430
+sym_1_430: la $2, sym_1_430
+.globl sym_1_431
+sym_1_431: la $2, sym_1_431
+.globl sym_1_432
+sym_1_432: la $2, sym_1_432
+.globl sym_1_433
+sym_1_433: la $2, sym_1_433
+.globl sym_1_434
+sym_1_434: la $2, sym_1_434
+.globl sym_1_435
+sym_1_435: la $2, sym_1_435
+.globl sym_1_436
+sym_1_436: la $2, sym_1_436
+.globl sym_1_437
+sym_1_437: la $2, sym_1_437
+.globl sym_1_438
+sym_1_438: la $2, sym_1_438
+.globl sym_1_439
+sym_1_439: la $2, sym_1_439
+.globl sym_1_440
+sym_1_440: la $2, sym_1_440
+.globl sym_1_441
+sym_1_441: la $2, sym_1_441
+.globl sym_1_442
+sym_1_442: la $2, sym_1_442
+.globl sym_1_443
+sym_1_443: la $2, sym_1_443
+.globl sym_1_444
+sym_1_444: la $2, sym_1_444
+.globl sym_1_445
+sym_1_445: la $2, sym_1_445
+.globl sym_1_446
+sym_1_446: la $2, sym_1_446
+.globl sym_1_447
+sym_1_447: la $2, sym_1_447
+.globl sym_1_448
+sym_1_448: la $2, sym_1_448
+.globl sym_1_449
+sym_1_449: la $2, sym_1_449
+.globl sym_1_450
+sym_1_450: la $2, sym_1_450
+.globl sym_1_451
+sym_1_451: la $2, sym_1_451
+.globl sym_1_452
+sym_1_452: la $2, sym_1_452
+.globl sym_1_453
+sym_1_453: la $2, sym_1_453
+.globl sym_1_454
+sym_1_454: la $2, sym_1_454
+.globl sym_1_455
+sym_1_455: la $2, sym_1_455
+.globl sym_1_456
+sym_1_456: la $2, sym_1_456
+.globl sym_1_457
+sym_1_457: la $2, sym_1_457
+.globl sym_1_458
+sym_1_458: la $2, sym_1_458
+.globl sym_1_459
+sym_1_459: la $2, sym_1_459
+.globl sym_1_460
+sym_1_460: la $2, sym_1_460
+.globl sym_1_461
+sym_1_461: la $2, sym_1_461
+.globl sym_1_462
+sym_1_462: la $2, sym_1_462
+.globl sym_1_463
+sym_1_463: la $2, sym_1_463
+.globl sym_1_464
+sym_1_464: la $2, sym_1_464
+.globl sym_1_465
+sym_1_465: la $2, sym_1_465
+.globl sym_1_466
+sym_1_466: la $2, sym_1_466
+.globl sym_1_467
+sym_1_467: la $2, sym_1_467
+.globl sym_1_468
+sym_1_468: la $2, sym_1_468
+.globl sym_1_469
+sym_1_469: la $2, sym_1_469
+.globl sym_1_470
+sym_1_470: la $2, sym_1_470
+.globl sym_1_471
+sym_1_471: la $2, sym_1_471
+.globl sym_1_472
+sym_1_472: la $2, sym_1_472
+.globl sym_1_473
+sym_1_473: la $2, sym_1_473
+.globl sym_1_474
+sym_1_474: la $2, sym_1_474
+.globl sym_1_475
+sym_1_475: la $2, sym_1_475
+.globl sym_1_476
+sym_1_476: la $2, sym_1_476
+.globl sym_1_477
+sym_1_477: la $2, sym_1_477
+.globl sym_1_478
+sym_1_478: la $2, sym_1_478
+.globl sym_1_479
+sym_1_479: la $2, sym_1_479
+.globl sym_1_480
+sym_1_480: la $2, sym_1_480
+.globl sym_1_481
+sym_1_481: la $2, sym_1_481
+.globl sym_1_482
+sym_1_482: la $2, sym_1_482
+.globl sym_1_483
+sym_1_483: la $2, sym_1_483
+.globl sym_1_484
+sym_1_484: la $2, sym_1_484
+.globl sym_1_485
+sym_1_485: la $2, sym_1_485
+.globl sym_1_486
+sym_1_486: la $2, sym_1_486
+.globl sym_1_487
+sym_1_487: la $2, sym_1_487
+.globl sym_1_488
+sym_1_488: la $2, sym_1_488
+.globl sym_1_489
+sym_1_489: la $2, sym_1_489
+.globl sym_1_490
+sym_1_490: la $2, sym_1_490
+.globl sym_1_491
+sym_1_491: la $2, sym_1_491
+.globl sym_1_492
+sym_1_492: la $2, sym_1_492
+.globl sym_1_493
+sym_1_493: la $2, sym_1_493
+.globl sym_1_494
+sym_1_494: la $2, sym_1_494
+.globl sym_1_495
+sym_1_495: la $2, sym_1_495
+.globl sym_1_496
+sym_1_496: la $2, sym_1_496
+.globl sym_1_497
+sym_1_497: la $2, sym_1_497
+.globl sym_1_498
+sym_1_498: la $2, sym_1_498
+.globl sym_1_499
+sym_1_499: la $2, sym_1_499
+.globl sym_1_500
+sym_1_500: la $2, sym_1_500
+.globl sym_1_501
+sym_1_501: la $2, sym_1_501
+.globl sym_1_502
+sym_1_502: la $2, sym_1_502
+.globl sym_1_503
+sym_1_503: la $2, sym_1_503
+.globl sym_1_504
+sym_1_504: la $2, sym_1_504
+.globl sym_1_505
+sym_1_505: la $2, sym_1_505
+.globl sym_1_506
+sym_1_506: la $2, sym_1_506
+.globl sym_1_507
+sym_1_507: la $2, sym_1_507
+.globl sym_1_508
+sym_1_508: la $2, sym_1_508
+.globl sym_1_509
+sym_1_509: la $2, sym_1_509
+.globl sym_1_510
+sym_1_510: la $2, sym_1_510
+.globl sym_1_511
+sym_1_511: la $2, sym_1_511
+.globl sym_1_512
+sym_1_512: la $2, sym_1_512
+.globl sym_1_513
+sym_1_513: la $2, sym_1_513
+.globl sym_1_514
+sym_1_514: la $2, sym_1_514
+.globl sym_1_515
+sym_1_515: la $2, sym_1_515
+.globl sym_1_516
+sym_1_516: la $2, sym_1_516
+.globl sym_1_517
+sym_1_517: la $2, sym_1_517
+.globl sym_1_518
+sym_1_518: la $2, sym_1_518
+.globl sym_1_519
+sym_1_519: la $2, sym_1_519
+.globl sym_1_520
+sym_1_520: la $2, sym_1_520
+.globl sym_1_521
+sym_1_521: la $2, sym_1_521
+.globl sym_1_522
+sym_1_522: la $2, sym_1_522
+.globl sym_1_523
+sym_1_523: la $2, sym_1_523
+.globl sym_1_524
+sym_1_524: la $2, sym_1_524
+.globl sym_1_525
+sym_1_525: la $2, sym_1_525
+.globl sym_1_526
+sym_1_526: la $2, sym_1_526
+.globl sym_1_527
+sym_1_527: la $2, sym_1_527
+.globl sym_1_528
+sym_1_528: la $2, sym_1_528
+.globl sym_1_529
+sym_1_529: la $2, sym_1_529
+.globl sym_1_530
+sym_1_530: la $2, sym_1_530
+.globl sym_1_531
+sym_1_531: la $2, sym_1_531
+.globl sym_1_532
+sym_1_532: la $2, sym_1_532
+.globl sym_1_533
+sym_1_533: la $2, sym_1_533
+.globl sym_1_534
+sym_1_534: la $2, sym_1_534
+.globl sym_1_535
+sym_1_535: la $2, sym_1_535
+.globl sym_1_536
+sym_1_536: la $2, sym_1_536
+.globl sym_1_537
+sym_1_537: la $2, sym_1_537
+.globl sym_1_538
+sym_1_538: la $2, sym_1_538
+.globl sym_1_539
+sym_1_539: la $2, sym_1_539
+.globl sym_1_540
+sym_1_540: la $2, sym_1_540
+.globl sym_1_541
+sym_1_541: la $2, sym_1_541
+.globl sym_1_542
+sym_1_542: la $2, sym_1_542
+.globl sym_1_543
+sym_1_543: la $2, sym_1_543
+.globl sym_1_544
+sym_1_544: la $2, sym_1_544
+.globl sym_1_545
+sym_1_545: la $2, sym_1_545
+.globl sym_1_546
+sym_1_546: la $2, sym_1_546
+.globl sym_1_547
+sym_1_547: la $2, sym_1_547
+.globl sym_1_548
+sym_1_548: la $2, sym_1_548
+.globl sym_1_549
+sym_1_549: la $2, sym_1_549
+.globl sym_1_550
+sym_1_550: la $2, sym_1_550
+.globl sym_1_551
+sym_1_551: la $2, sym_1_551
+.globl sym_1_552
+sym_1_552: la $2, sym_1_552
+.globl sym_1_553
+sym_1_553: la $2, sym_1_553
+.globl sym_1_554
+sym_1_554: la $2, sym_1_554
+.globl sym_1_555
+sym_1_555: la $2, sym_1_555
+.globl sym_1_556
+sym_1_556: la $2, sym_1_556
+.globl sym_1_557
+sym_1_557: la $2, sym_1_557
+.globl sym_1_558
+sym_1_558: la $2, sym_1_558
+.globl sym_1_559
+sym_1_559: la $2, sym_1_559
+.globl sym_1_560
+sym_1_560: la $2, sym_1_560
+.globl sym_1_561
+sym_1_561: la $2, sym_1_561
+.globl sym_1_562
+sym_1_562: la $2, sym_1_562
+.globl sym_1_563
+sym_1_563: la $2, sym_1_563
+.globl sym_1_564
+sym_1_564: la $2, sym_1_564
+.globl sym_1_565
+sym_1_565: la $2, sym_1_565
+.globl sym_1_566
+sym_1_566: la $2, sym_1_566
+.globl sym_1_567
+sym_1_567: la $2, sym_1_567
+.globl sym_1_568
+sym_1_568: la $2, sym_1_568
+.globl sym_1_569
+sym_1_569: la $2, sym_1_569
+.globl sym_1_570
+sym_1_570: la $2, sym_1_570
+.globl sym_1_571
+sym_1_571: la $2, sym_1_571
+.globl sym_1_572
+sym_1_572: la $2, sym_1_572
+.globl sym_1_573
+sym_1_573: la $2, sym_1_573
+.globl sym_1_574
+sym_1_574: la $2, sym_1_574
+.globl sym_1_575
+sym_1_575: la $2, sym_1_575
+.globl sym_1_576
+sym_1_576: la $2, sym_1_576
+.globl sym_1_577
+sym_1_577: la $2, sym_1_577
+.globl sym_1_578
+sym_1_578: la $2, sym_1_578
+.globl sym_1_579
+sym_1_579: la $2, sym_1_579
+.globl sym_1_580
+sym_1_580: la $2, sym_1_580
+.globl sym_1_581
+sym_1_581: la $2, sym_1_581
+.globl sym_1_582
+sym_1_582: la $2, sym_1_582
+.globl sym_1_583
+sym_1_583: la $2, sym_1_583
+.globl sym_1_584
+sym_1_584: la $2, sym_1_584
+.globl sym_1_585
+sym_1_585: la $2, sym_1_585
+.globl sym_1_586
+sym_1_586: la $2, sym_1_586
+.globl sym_1_587
+sym_1_587: la $2, sym_1_587
+.globl sym_1_588
+sym_1_588: la $2, sym_1_588
+.globl sym_1_589
+sym_1_589: la $2, sym_1_589
+.globl sym_1_590
+sym_1_590: la $2, sym_1_590
+.globl sym_1_591
+sym_1_591: la $2, sym_1_591
+.globl sym_1_592
+sym_1_592: la $2, sym_1_592
+.globl sym_1_593
+sym_1_593: la $2, sym_1_593
+.globl sym_1_594
+sym_1_594: la $2, sym_1_594
+.globl sym_1_595
+sym_1_595: la $2, sym_1_595
+.globl sym_1_596
+sym_1_596: la $2, sym_1_596
+.globl sym_1_597
+sym_1_597: la $2, sym_1_597
+.globl sym_1_598
+sym_1_598: la $2, sym_1_598
+.globl sym_1_599
+sym_1_599: la $2, sym_1_599
+.globl sym_1_600
+sym_1_600: la $2, sym_1_600
+.globl sym_1_601
+sym_1_601: la $2, sym_1_601
+.globl sym_1_602
+sym_1_602: la $2, sym_1_602
+.globl sym_1_603
+sym_1_603: la $2, sym_1_603
+.globl sym_1_604
+sym_1_604: la $2, sym_1_604
+.globl sym_1_605
+sym_1_605: la $2, sym_1_605
+.globl sym_1_606
+sym_1_606: la $2, sym_1_606
+.globl sym_1_607
+sym_1_607: la $2, sym_1_607
+.globl sym_1_608
+sym_1_608: la $2, sym_1_608
+.globl sym_1_609
+sym_1_609: la $2, sym_1_609
+.globl sym_1_610
+sym_1_610: la $2, sym_1_610
+.globl sym_1_611
+sym_1_611: la $2, sym_1_611
+.globl sym_1_612
+sym_1_612: la $2, sym_1_612
+.globl sym_1_613
+sym_1_613: la $2, sym_1_613
+.globl sym_1_614
+sym_1_614: la $2, sym_1_614
+.globl sym_1_615
+sym_1_615: la $2, sym_1_615
+.globl sym_1_616
+sym_1_616: la $2, sym_1_616
+.globl sym_1_617
+sym_1_617: la $2, sym_1_617
+.globl sym_1_618
+sym_1_618: la $2, sym_1_618
+.globl sym_1_619
+sym_1_619: la $2, sym_1_619
+.globl sym_1_620
+sym_1_620: la $2, sym_1_620
+.globl sym_1_621
+sym_1_621: la $2, sym_1_621
+.globl sym_1_622
+sym_1_622: la $2, sym_1_622
+.globl sym_1_623
+sym_1_623: la $2, sym_1_623
+.globl sym_1_624
+sym_1_624: la $2, sym_1_624
+.globl sym_1_625
+sym_1_625: la $2, sym_1_625
+.globl sym_1_626
+sym_1_626: la $2, sym_1_626
+.globl sym_1_627
+sym_1_627: la $2, sym_1_627
+.globl sym_1_628
+sym_1_628: la $2, sym_1_628
+.globl sym_1_629
+sym_1_629: la $2, sym_1_629
+.globl sym_1_630
+sym_1_630: la $2, sym_1_630
+.globl sym_1_631
+sym_1_631: la $2, sym_1_631
+.globl sym_1_632
+sym_1_632: la $2, sym_1_632
+.globl sym_1_633
+sym_1_633: la $2, sym_1_633
+.globl sym_1_634
+sym_1_634: la $2, sym_1_634
+.globl sym_1_635
+sym_1_635: la $2, sym_1_635
+.globl sym_1_636
+sym_1_636: la $2, sym_1_636
+.globl sym_1_637
+sym_1_637: la $2, sym_1_637
+.globl sym_1_638
+sym_1_638: la $2, sym_1_638
+.globl sym_1_639
+sym_1_639: la $2, sym_1_639
+.globl sym_1_640
+sym_1_640: la $2, sym_1_640
+.globl sym_1_641
+sym_1_641: la $2, sym_1_641
+.globl sym_1_642
+sym_1_642: la $2, sym_1_642
+.globl sym_1_643
+sym_1_643: la $2, sym_1_643
+.globl sym_1_644
+sym_1_644: la $2, sym_1_644
+.globl sym_1_645
+sym_1_645: la $2, sym_1_645
+.globl sym_1_646
+sym_1_646: la $2, sym_1_646
+.globl sym_1_647
+sym_1_647: la $2, sym_1_647
+.globl sym_1_648
+sym_1_648: la $2, sym_1_648
+.globl sym_1_649
+sym_1_649: la $2, sym_1_649
+.globl sym_1_650
+sym_1_650: la $2, sym_1_650
+.globl sym_1_651
+sym_1_651: la $2, sym_1_651
+.globl sym_1_652
+sym_1_652: la $2, sym_1_652
+.globl sym_1_653
+sym_1_653: la $2, sym_1_653
+.globl sym_1_654
+sym_1_654: la $2, sym_1_654
+.globl sym_1_655
+sym_1_655: la $2, sym_1_655
+.globl sym_1_656
+sym_1_656: la $2, sym_1_656
+.globl sym_1_657
+sym_1_657: la $2, sym_1_657
+.globl sym_1_658
+sym_1_658: la $2, sym_1_658
+.globl sym_1_659
+sym_1_659: la $2, sym_1_659
+.globl sym_1_660
+sym_1_660: la $2, sym_1_660
+.globl sym_1_661
+sym_1_661: la $2, sym_1_661
+.globl sym_1_662
+sym_1_662: la $2, sym_1_662
+.globl sym_1_663
+sym_1_663: la $2, sym_1_663
+.globl sym_1_664
+sym_1_664: la $2, sym_1_664
+.globl sym_1_665
+sym_1_665: la $2, sym_1_665
+.globl sym_1_666
+sym_1_666: la $2, sym_1_666
+.globl sym_1_667
+sym_1_667: la $2, sym_1_667
+.globl sym_1_668
+sym_1_668: la $2, sym_1_668
+.globl sym_1_669
+sym_1_669: la $2, sym_1_669
+.globl sym_1_670
+sym_1_670: la $2, sym_1_670
+.globl sym_1_671
+sym_1_671: la $2, sym_1_671
+.globl sym_1_672
+sym_1_672: la $2, sym_1_672
+.globl sym_1_673
+sym_1_673: la $2, sym_1_673
+.globl sym_1_674
+sym_1_674: la $2, sym_1_674
+.globl sym_1_675
+sym_1_675: la $2, sym_1_675
+.globl sym_1_676
+sym_1_676: la $2, sym_1_676
+.globl sym_1_677
+sym_1_677: la $2, sym_1_677
+.globl sym_1_678
+sym_1_678: la $2, sym_1_678
+.globl sym_1_679
+sym_1_679: la $2, sym_1_679
+.globl sym_1_680
+sym_1_680: la $2, sym_1_680
+.globl sym_1_681
+sym_1_681: la $2, sym_1_681
+.globl sym_1_682
+sym_1_682: la $2, sym_1_682
+.globl sym_1_683
+sym_1_683: la $2, sym_1_683
+.globl sym_1_684
+sym_1_684: la $2, sym_1_684
+.globl sym_1_685
+sym_1_685: la $2, sym_1_685
+.globl sym_1_686
+sym_1_686: la $2, sym_1_686
+.globl sym_1_687
+sym_1_687: la $2, sym_1_687
+.globl sym_1_688
+sym_1_688: la $2, sym_1_688
+.globl sym_1_689
+sym_1_689: la $2, sym_1_689
+.globl sym_1_690
+sym_1_690: la $2, sym_1_690
+.globl sym_1_691
+sym_1_691: la $2, sym_1_691
+.globl sym_1_692
+sym_1_692: la $2, sym_1_692
+.globl sym_1_693
+sym_1_693: la $2, sym_1_693
+.globl sym_1_694
+sym_1_694: la $2, sym_1_694
+.globl sym_1_695
+sym_1_695: la $2, sym_1_695
+.globl sym_1_696
+sym_1_696: la $2, sym_1_696
+.globl sym_1_697
+sym_1_697: la $2, sym_1_697
+.globl sym_1_698
+sym_1_698: la $2, sym_1_698
+.globl sym_1_699
+sym_1_699: la $2, sym_1_699
+.globl sym_1_700
+sym_1_700: la $2, sym_1_700
+.globl sym_1_701
+sym_1_701: la $2, sym_1_701
+.globl sym_1_702
+sym_1_702: la $2, sym_1_702
+.globl sym_1_703
+sym_1_703: la $2, sym_1_703
+.globl sym_1_704
+sym_1_704: la $2, sym_1_704
+.globl sym_1_705
+sym_1_705: la $2, sym_1_705
+.globl sym_1_706
+sym_1_706: la $2, sym_1_706
+.globl sym_1_707
+sym_1_707: la $2, sym_1_707
+.globl sym_1_708
+sym_1_708: la $2, sym_1_708
+.globl sym_1_709
+sym_1_709: la $2, sym_1_709
+.globl sym_1_710
+sym_1_710: la $2, sym_1_710
+.globl sym_1_711
+sym_1_711: la $2, sym_1_711
+.globl sym_1_712
+sym_1_712: la $2, sym_1_712
+.globl sym_1_713
+sym_1_713: la $2, sym_1_713
+.globl sym_1_714
+sym_1_714: la $2, sym_1_714
+.globl sym_1_715
+sym_1_715: la $2, sym_1_715
+.globl sym_1_716
+sym_1_716: la $2, sym_1_716
+.globl sym_1_717
+sym_1_717: la $2, sym_1_717
+.globl sym_1_718
+sym_1_718: la $2, sym_1_718
+.globl sym_1_719
+sym_1_719: la $2, sym_1_719
+.globl sym_1_720
+sym_1_720: la $2, sym_1_720
+.globl sym_1_721
+sym_1_721: la $2, sym_1_721
+.globl sym_1_722
+sym_1_722: la $2, sym_1_722
+.globl sym_1_723
+sym_1_723: la $2, sym_1_723
+.globl sym_1_724
+sym_1_724: la $2, sym_1_724
+.globl sym_1_725
+sym_1_725: la $2, sym_1_725
+.globl sym_1_726
+sym_1_726: la $2, sym_1_726
+.globl sym_1_727
+sym_1_727: la $2, sym_1_727
+.globl sym_1_728
+sym_1_728: la $2, sym_1_728
+.globl sym_1_729
+sym_1_729: la $2, sym_1_729
+.globl sym_1_730
+sym_1_730: la $2, sym_1_730
+.globl sym_1_731
+sym_1_731: la $2, sym_1_731
+.globl sym_1_732
+sym_1_732: la $2, sym_1_732
+.globl sym_1_733
+sym_1_733: la $2, sym_1_733
+.globl sym_1_734
+sym_1_734: la $2, sym_1_734
+.globl sym_1_735
+sym_1_735: la $2, sym_1_735
+.globl sym_1_736
+sym_1_736: la $2, sym_1_736
+.globl sym_1_737
+sym_1_737: la $2, sym_1_737
+.globl sym_1_738
+sym_1_738: la $2, sym_1_738
+.globl sym_1_739
+sym_1_739: la $2, sym_1_739
+.globl sym_1_740
+sym_1_740: la $2, sym_1_740
+.globl sym_1_741
+sym_1_741: la $2, sym_1_741
+.globl sym_1_742
+sym_1_742: la $2, sym_1_742
+.globl sym_1_743
+sym_1_743: la $2, sym_1_743
+.globl sym_1_744
+sym_1_744: la $2, sym_1_744
+.globl sym_1_745
+sym_1_745: la $2, sym_1_745
+.globl sym_1_746
+sym_1_746: la $2, sym_1_746
+.globl sym_1_747
+sym_1_747: la $2, sym_1_747
+.globl sym_1_748
+sym_1_748: la $2, sym_1_748
+.globl sym_1_749
+sym_1_749: la $2, sym_1_749
+.globl sym_1_750
+sym_1_750: la $2, sym_1_750
+.globl sym_1_751
+sym_1_751: la $2, sym_1_751
+.globl sym_1_752
+sym_1_752: la $2, sym_1_752
+.globl sym_1_753
+sym_1_753: la $2, sym_1_753
+.globl sym_1_754
+sym_1_754: la $2, sym_1_754
+.globl sym_1_755
+sym_1_755: la $2, sym_1_755
+.globl sym_1_756
+sym_1_756: la $2, sym_1_756
+.globl sym_1_757
+sym_1_757: la $2, sym_1_757
+.globl sym_1_758
+sym_1_758: la $2, sym_1_758
+.globl sym_1_759
+sym_1_759: la $2, sym_1_759
+.globl sym_1_760
+sym_1_760: la $2, sym_1_760
+.globl sym_1_761
+sym_1_761: la $2, sym_1_761
+.globl sym_1_762
+sym_1_762: la $2, sym_1_762
+.globl sym_1_763
+sym_1_763: la $2, sym_1_763
+.globl sym_1_764
+sym_1_764: la $2, sym_1_764
+.globl sym_1_765
+sym_1_765: la $2, sym_1_765
+.globl sym_1_766
+sym_1_766: la $2, sym_1_766
+.globl sym_1_767
+sym_1_767: la $2, sym_1_767
+.globl sym_1_768
+sym_1_768: la $2, sym_1_768
+.globl sym_1_769
+sym_1_769: la $2, sym_1_769
+.globl sym_1_770
+sym_1_770: la $2, sym_1_770
+.globl sym_1_771
+sym_1_771: la $2, sym_1_771
+.globl sym_1_772
+sym_1_772: la $2, sym_1_772
+.globl sym_1_773
+sym_1_773: la $2, sym_1_773
+.globl sym_1_774
+sym_1_774: la $2, sym_1_774
+.globl sym_1_775
+sym_1_775: la $2, sym_1_775
+.globl sym_1_776
+sym_1_776: la $2, sym_1_776
+.globl sym_1_777
+sym_1_777: la $2, sym_1_777
+.globl sym_1_778
+sym_1_778: la $2, sym_1_778
+.globl sym_1_779
+sym_1_779: la $2, sym_1_779
+.globl sym_1_780
+sym_1_780: la $2, sym_1_780
+.globl sym_1_781
+sym_1_781: la $2, sym_1_781
+.globl sym_1_782
+sym_1_782: la $2, sym_1_782
+.globl sym_1_783
+sym_1_783: la $2, sym_1_783
+.globl sym_1_784
+sym_1_784: la $2, sym_1_784
+.globl sym_1_785
+sym_1_785: la $2, sym_1_785
+.globl sym_1_786
+sym_1_786: la $2, sym_1_786
+.globl sym_1_787
+sym_1_787: la $2, sym_1_787
+.globl sym_1_788
+sym_1_788: la $2, sym_1_788
+.globl sym_1_789
+sym_1_789: la $2, sym_1_789
+.globl sym_1_790
+sym_1_790: la $2, sym_1_790
+.globl sym_1_791
+sym_1_791: la $2, sym_1_791
+.globl sym_1_792
+sym_1_792: la $2, sym_1_792
+.globl sym_1_793
+sym_1_793: la $2, sym_1_793
+.globl sym_1_794
+sym_1_794: la $2, sym_1_794
+.globl sym_1_795
+sym_1_795: la $2, sym_1_795
+.globl sym_1_796
+sym_1_796: la $2, sym_1_796
+.globl sym_1_797
+sym_1_797: la $2, sym_1_797
+.globl sym_1_798
+sym_1_798: la $2, sym_1_798
+.globl sym_1_799
+sym_1_799: la $2, sym_1_799
+.globl sym_1_800
+sym_1_800: la $2, sym_1_800
+.globl sym_1_801
+sym_1_801: la $2, sym_1_801
+.globl sym_1_802
+sym_1_802: la $2, sym_1_802
+.globl sym_1_803
+sym_1_803: la $2, sym_1_803
+.globl sym_1_804
+sym_1_804: la $2, sym_1_804
+.globl sym_1_805
+sym_1_805: la $2, sym_1_805
+.globl sym_1_806
+sym_1_806: la $2, sym_1_806
+.globl sym_1_807
+sym_1_807: la $2, sym_1_807
+.globl sym_1_808
+sym_1_808: la $2, sym_1_808
+.globl sym_1_809
+sym_1_809: la $2, sym_1_809
+.globl sym_1_810
+sym_1_810: la $2, sym_1_810
+.globl sym_1_811
+sym_1_811: la $2, sym_1_811
+.globl sym_1_812
+sym_1_812: la $2, sym_1_812
+.globl sym_1_813
+sym_1_813: la $2, sym_1_813
+.globl sym_1_814
+sym_1_814: la $2, sym_1_814
+.globl sym_1_815
+sym_1_815: la $2, sym_1_815
+.globl sym_1_816
+sym_1_816: la $2, sym_1_816
+.globl sym_1_817
+sym_1_817: la $2, sym_1_817
+.globl sym_1_818
+sym_1_818: la $2, sym_1_818
+.globl sym_1_819
+sym_1_819: la $2, sym_1_819
+.globl sym_1_820
+sym_1_820: la $2, sym_1_820
+.globl sym_1_821
+sym_1_821: la $2, sym_1_821
+.globl sym_1_822
+sym_1_822: la $2, sym_1_822
+.globl sym_1_823
+sym_1_823: la $2, sym_1_823
+.globl sym_1_824
+sym_1_824: la $2, sym_1_824
+.globl sym_1_825
+sym_1_825: la $2, sym_1_825
+.globl sym_1_826
+sym_1_826: la $2, sym_1_826
+.globl sym_1_827
+sym_1_827: la $2, sym_1_827
+.globl sym_1_828
+sym_1_828: la $2, sym_1_828
+.globl sym_1_829
+sym_1_829: la $2, sym_1_829
+.globl sym_1_830
+sym_1_830: la $2, sym_1_830
+.globl sym_1_831
+sym_1_831: la $2, sym_1_831
+.globl sym_1_832
+sym_1_832: la $2, sym_1_832
+.globl sym_1_833
+sym_1_833: la $2, sym_1_833
+.globl sym_1_834
+sym_1_834: la $2, sym_1_834
+.globl sym_1_835
+sym_1_835: la $2, sym_1_835
+.globl sym_1_836
+sym_1_836: la $2, sym_1_836
+.globl sym_1_837
+sym_1_837: la $2, sym_1_837
+.globl sym_1_838
+sym_1_838: la $2, sym_1_838
+.globl sym_1_839
+sym_1_839: la $2, sym_1_839
+.globl sym_1_840
+sym_1_840: la $2, sym_1_840
+.globl sym_1_841
+sym_1_841: la $2, sym_1_841
+.globl sym_1_842
+sym_1_842: la $2, sym_1_842
+.globl sym_1_843
+sym_1_843: la $2, sym_1_843
+.globl sym_1_844
+sym_1_844: la $2, sym_1_844
+.globl sym_1_845
+sym_1_845: la $2, sym_1_845
+.globl sym_1_846
+sym_1_846: la $2, sym_1_846
+.globl sym_1_847
+sym_1_847: la $2, sym_1_847
+.globl sym_1_848
+sym_1_848: la $2, sym_1_848
+.globl sym_1_849
+sym_1_849: la $2, sym_1_849
+.globl sym_1_850
+sym_1_850: la $2, sym_1_850
+.globl sym_1_851
+sym_1_851: la $2, sym_1_851
+.globl sym_1_852
+sym_1_852: la $2, sym_1_852
+.globl sym_1_853
+sym_1_853: la $2, sym_1_853
+.globl sym_1_854
+sym_1_854: la $2, sym_1_854
+.globl sym_1_855
+sym_1_855: la $2, sym_1_855
+.globl sym_1_856
+sym_1_856: la $2, sym_1_856
+.globl sym_1_857
+sym_1_857: la $2, sym_1_857
+.globl sym_1_858
+sym_1_858: la $2, sym_1_858
+.globl sym_1_859
+sym_1_859: la $2, sym_1_859
+.globl sym_1_860
+sym_1_860: la $2, sym_1_860
+.globl sym_1_861
+sym_1_861: la $2, sym_1_861
+.globl sym_1_862
+sym_1_862: la $2, sym_1_862
+.globl sym_1_863
+sym_1_863: la $2, sym_1_863
+.globl sym_1_864
+sym_1_864: la $2, sym_1_864
+.globl sym_1_865
+sym_1_865: la $2, sym_1_865
+.globl sym_1_866
+sym_1_866: la $2, sym_1_866
+.globl sym_1_867
+sym_1_867: la $2, sym_1_867
+.globl sym_1_868
+sym_1_868: la $2, sym_1_868
+.globl sym_1_869
+sym_1_869: la $2, sym_1_869
+.globl sym_1_870
+sym_1_870: la $2, sym_1_870
+.globl sym_1_871
+sym_1_871: la $2, sym_1_871
+.globl sym_1_872
+sym_1_872: la $2, sym_1_872
+.globl sym_1_873
+sym_1_873: la $2, sym_1_873
+.globl sym_1_874
+sym_1_874: la $2, sym_1_874
+.globl sym_1_875
+sym_1_875: la $2, sym_1_875
+.globl sym_1_876
+sym_1_876: la $2, sym_1_876
+.globl sym_1_877
+sym_1_877: la $2, sym_1_877
+.globl sym_1_878
+sym_1_878: la $2, sym_1_878
+.globl sym_1_879
+sym_1_879: la $2, sym_1_879
+.globl sym_1_880
+sym_1_880: la $2, sym_1_880
+.globl sym_1_881
+sym_1_881: la $2, sym_1_881
+.globl sym_1_882
+sym_1_882: la $2, sym_1_882
+.globl sym_1_883
+sym_1_883: la $2, sym_1_883
+.globl sym_1_884
+sym_1_884: la $2, sym_1_884
+.globl sym_1_885
+sym_1_885: la $2, sym_1_885
+.globl sym_1_886
+sym_1_886: la $2, sym_1_886
+.globl sym_1_887
+sym_1_887: la $2, sym_1_887
+.globl sym_1_888
+sym_1_888: la $2, sym_1_888
+.globl sym_1_889
+sym_1_889: la $2, sym_1_889
+.globl sym_1_890
+sym_1_890: la $2, sym_1_890
+.globl sym_1_891
+sym_1_891: la $2, sym_1_891
+.globl sym_1_892
+sym_1_892: la $2, sym_1_892
+.globl sym_1_893
+sym_1_893: la $2, sym_1_893
+.globl sym_1_894
+sym_1_894: la $2, sym_1_894
+.globl sym_1_895
+sym_1_895: la $2, sym_1_895
+.globl sym_1_896
+sym_1_896: la $2, sym_1_896
+.globl sym_1_897
+sym_1_897: la $2, sym_1_897
+.globl sym_1_898
+sym_1_898: la $2, sym_1_898
+.globl sym_1_899
+sym_1_899: la $2, sym_1_899
+.globl sym_1_900
+sym_1_900: la $2, sym_1_900
+.globl sym_1_901
+sym_1_901: la $2, sym_1_901
+.globl sym_1_902
+sym_1_902: la $2, sym_1_902
+.globl sym_1_903
+sym_1_903: la $2, sym_1_903
+.globl sym_1_904
+sym_1_904: la $2, sym_1_904
+.globl sym_1_905
+sym_1_905: la $2, sym_1_905
+.globl sym_1_906
+sym_1_906: la $2, sym_1_906
+.globl sym_1_907
+sym_1_907: la $2, sym_1_907
+.globl sym_1_908
+sym_1_908: la $2, sym_1_908
+.globl sym_1_909
+sym_1_909: la $2, sym_1_909
+.globl sym_1_910
+sym_1_910: la $2, sym_1_910
+.globl sym_1_911
+sym_1_911: la $2, sym_1_911
+.globl sym_1_912
+sym_1_912: la $2, sym_1_912
+.globl sym_1_913
+sym_1_913: la $2, sym_1_913
+.globl sym_1_914
+sym_1_914: la $2, sym_1_914
+.globl sym_1_915
+sym_1_915: la $2, sym_1_915
+.globl sym_1_916
+sym_1_916: la $2, sym_1_916
+.globl sym_1_917
+sym_1_917: la $2, sym_1_917
+.globl sym_1_918
+sym_1_918: la $2, sym_1_918
+.globl sym_1_919
+sym_1_919: la $2, sym_1_919
+.globl sym_1_920
+sym_1_920: la $2, sym_1_920
+.globl sym_1_921
+sym_1_921: la $2, sym_1_921
+.globl sym_1_922
+sym_1_922: la $2, sym_1_922
+.globl sym_1_923
+sym_1_923: la $2, sym_1_923
+.globl sym_1_924
+sym_1_924: la $2, sym_1_924
+.globl sym_1_925
+sym_1_925: la $2, sym_1_925
+.globl sym_1_926
+sym_1_926: la $2, sym_1_926
+.globl sym_1_927
+sym_1_927: la $2, sym_1_927
+.globl sym_1_928
+sym_1_928: la $2, sym_1_928
+.globl sym_1_929
+sym_1_929: la $2, sym_1_929
+.globl sym_1_930
+sym_1_930: la $2, sym_1_930
+.globl sym_1_931
+sym_1_931: la $2, sym_1_931
+.globl sym_1_932
+sym_1_932: la $2, sym_1_932
+.globl sym_1_933
+sym_1_933: la $2, sym_1_933
+.globl sym_1_934
+sym_1_934: la $2, sym_1_934
+.globl sym_1_935
+sym_1_935: la $2, sym_1_935
+.globl sym_1_936
+sym_1_936: la $2, sym_1_936
+.globl sym_1_937
+sym_1_937: la $2, sym_1_937
+.globl sym_1_938
+sym_1_938: la $2, sym_1_938
+.globl sym_1_939
+sym_1_939: la $2, sym_1_939
+.globl sym_1_940
+sym_1_940: la $2, sym_1_940
+.globl sym_1_941
+sym_1_941: la $2, sym_1_941
+.globl sym_1_942
+sym_1_942: la $2, sym_1_942
+.globl sym_1_943
+sym_1_943: la $2, sym_1_943
+.globl sym_1_944
+sym_1_944: la $2, sym_1_944
+.globl sym_1_945
+sym_1_945: la $2, sym_1_945
+.globl sym_1_946
+sym_1_946: la $2, sym_1_946
+.globl sym_1_947
+sym_1_947: la $2, sym_1_947
+.globl sym_1_948
+sym_1_948: la $2, sym_1_948
+.globl sym_1_949
+sym_1_949: la $2, sym_1_949
+.globl sym_1_950
+sym_1_950: la $2, sym_1_950
+.globl sym_1_951
+sym_1_951: la $2, sym_1_951
+.globl sym_1_952
+sym_1_952: la $2, sym_1_952
+.globl sym_1_953
+sym_1_953: la $2, sym_1_953
+.globl sym_1_954
+sym_1_954: la $2, sym_1_954
+.globl sym_1_955
+sym_1_955: la $2, sym_1_955
+.globl sym_1_956
+sym_1_956: la $2, sym_1_956
+.globl sym_1_957
+sym_1_957: la $2, sym_1_957
+.globl sym_1_958
+sym_1_958: la $2, sym_1_958
+.globl sym_1_959
+sym_1_959: la $2, sym_1_959
+.globl sym_1_960
+sym_1_960: la $2, sym_1_960
+.globl sym_1_961
+sym_1_961: la $2, sym_1_961
+.globl sym_1_962
+sym_1_962: la $2, sym_1_962
+.globl sym_1_963
+sym_1_963: la $2, sym_1_963
+.globl sym_1_964
+sym_1_964: la $2, sym_1_964
+.globl sym_1_965
+sym_1_965: la $2, sym_1_965
+.globl sym_1_966
+sym_1_966: la $2, sym_1_966
+.globl sym_1_967
+sym_1_967: la $2, sym_1_967
+.globl sym_1_968
+sym_1_968: la $2, sym_1_968
+.globl sym_1_969
+sym_1_969: la $2, sym_1_969
+.globl sym_1_970
+sym_1_970: la $2, sym_1_970
+.globl sym_1_971
+sym_1_971: la $2, sym_1_971
+.globl sym_1_972
+sym_1_972: la $2, sym_1_972
+.globl sym_1_973
+sym_1_973: la $2, sym_1_973
+.globl sym_1_974
+sym_1_974: la $2, sym_1_974
+.globl sym_1_975
+sym_1_975: la $2, sym_1_975
+.globl sym_1_976
+sym_1_976: la $2, sym_1_976
+.globl sym_1_977
+sym_1_977: la $2, sym_1_977
+.globl sym_1_978
+sym_1_978: la $2, sym_1_978
+.globl sym_1_979
+sym_1_979: la $2, sym_1_979
+.globl sym_1_980
+sym_1_980: la $2, sym_1_980
+.globl sym_1_981
+sym_1_981: la $2, sym_1_981
+.globl sym_1_982
+sym_1_982: la $2, sym_1_982
+.globl sym_1_983
+sym_1_983: la $2, sym_1_983
+.globl sym_1_984
+sym_1_984: la $2, sym_1_984
+.globl sym_1_985
+sym_1_985: la $2, sym_1_985
+.globl sym_1_986
+sym_1_986: la $2, sym_1_986
+.globl sym_1_987
+sym_1_987: la $2, sym_1_987
+.globl sym_1_988
+sym_1_988: la $2, sym_1_988
+.globl sym_1_989
+sym_1_989: la $2, sym_1_989
+.globl sym_1_990
+sym_1_990: la $2, sym_1_990
+.globl sym_1_991
+sym_1_991: la $2, sym_1_991
+.globl sym_1_992
+sym_1_992: la $2, sym_1_992
+.globl sym_1_993
+sym_1_993: la $2, sym_1_993
+.globl sym_1_994
+sym_1_994: la $2, sym_1_994
+.globl sym_1_995
+sym_1_995: la $2, sym_1_995
+.globl sym_1_996
+sym_1_996: la $2, sym_1_996
+.globl sym_1_997
+sym_1_997: la $2, sym_1_997
+.globl sym_1_998
+sym_1_998: la $2, sym_1_998
+.globl sym_1_999
+sym_1_999: la $2, sym_1_999
+.globl sym_1_1000
+sym_1_1000: la $2, sym_1_1000
+.globl sym_1_1001
+sym_1_1001: la $2, sym_1_1001
+.globl sym_1_1002
+sym_1_1002: la $2, sym_1_1002
+.globl sym_1_1003
+sym_1_1003: la $2, sym_1_1003
+.globl sym_1_1004
+sym_1_1004: la $2, sym_1_1004
+.globl sym_1_1005
+sym_1_1005: la $2, sym_1_1005
+.globl sym_1_1006
+sym_1_1006: la $2, sym_1_1006
+.globl sym_1_1007
+sym_1_1007: la $2, sym_1_1007
+.globl sym_1_1008
+sym_1_1008: la $2, sym_1_1008
+.globl sym_1_1009
+sym_1_1009: la $2, sym_1_1009
+.globl sym_1_1010
+sym_1_1010: la $2, sym_1_1010
+.globl sym_1_1011
+sym_1_1011: la $2, sym_1_1011
+.globl sym_1_1012
+sym_1_1012: la $2, sym_1_1012
+.globl sym_1_1013
+sym_1_1013: la $2, sym_1_1013
+.globl sym_1_1014
+sym_1_1014: la $2, sym_1_1014
+.globl sym_1_1015
+sym_1_1015: la $2, sym_1_1015
+.globl sym_1_1016
+sym_1_1016: la $2, sym_1_1016
+.globl sym_1_1017
+sym_1_1017: la $2, sym_1_1017
+.globl sym_1_1018
+sym_1_1018: la $2, sym_1_1018
+.globl sym_1_1019
+sym_1_1019: la $2, sym_1_1019
+.globl sym_1_1020
+sym_1_1020: la $2, sym_1_1020
+.globl sym_1_1021
+sym_1_1021: la $2, sym_1_1021
+.globl sym_1_1022
+sym_1_1022: la $2, sym_1_1022
+.globl sym_1_1023
+sym_1_1023: la $2, sym_1_1023
+.globl sym_1_1024
+sym_1_1024: la $2, sym_1_1024
+.globl sym_1_1025
+sym_1_1025: la $2, sym_1_1025
+.globl sym_1_1026
+sym_1_1026: la $2, sym_1_1026
+.globl sym_1_1027
+sym_1_1027: la $2, sym_1_1027
+.globl sym_1_1028
+sym_1_1028: la $2, sym_1_1028
+.globl sym_1_1029
+sym_1_1029: la $2, sym_1_1029
+.globl sym_1_1030
+sym_1_1030: la $2, sym_1_1030
+.globl sym_1_1031
+sym_1_1031: la $2, sym_1_1031
+.globl sym_1_1032
+sym_1_1032: la $2, sym_1_1032
+.globl sym_1_1033
+sym_1_1033: la $2, sym_1_1033
+.globl sym_1_1034
+sym_1_1034: la $2, sym_1_1034
+.globl sym_1_1035
+sym_1_1035: la $2, sym_1_1035
+.globl sym_1_1036
+sym_1_1036: la $2, sym_1_1036
+.globl sym_1_1037
+sym_1_1037: la $2, sym_1_1037
+.globl sym_1_1038
+sym_1_1038: la $2, sym_1_1038
+.globl sym_1_1039
+sym_1_1039: la $2, sym_1_1039
+.globl sym_1_1040
+sym_1_1040: la $2, sym_1_1040
+.globl sym_1_1041
+sym_1_1041: la $2, sym_1_1041
+.globl sym_1_1042
+sym_1_1042: la $2, sym_1_1042
+.globl sym_1_1043
+sym_1_1043: la $2, sym_1_1043
+.globl sym_1_1044
+sym_1_1044: la $2, sym_1_1044
+.globl sym_1_1045
+sym_1_1045: la $2, sym_1_1045
+.globl sym_1_1046
+sym_1_1046: la $2, sym_1_1046
+.globl sym_1_1047
+sym_1_1047: la $2, sym_1_1047
+.globl sym_1_1048
+sym_1_1048: la $2, sym_1_1048
+.globl sym_1_1049
+sym_1_1049: la $2, sym_1_1049
+.globl sym_1_1050
+sym_1_1050: la $2, sym_1_1050
+.globl sym_1_1051
+sym_1_1051: la $2, sym_1_1051
+.globl sym_1_1052
+sym_1_1052: la $2, sym_1_1052
+.globl sym_1_1053
+sym_1_1053: la $2, sym_1_1053
+.globl sym_1_1054
+sym_1_1054: la $2, sym_1_1054
+.globl sym_1_1055
+sym_1_1055: la $2, sym_1_1055
+.globl sym_1_1056
+sym_1_1056: la $2, sym_1_1056
+.globl sym_1_1057
+sym_1_1057: la $2, sym_1_1057
+.globl sym_1_1058
+sym_1_1058: la $2, sym_1_1058
+.globl sym_1_1059
+sym_1_1059: la $2, sym_1_1059
+.globl sym_1_1060
+sym_1_1060: la $2, sym_1_1060
+.globl sym_1_1061
+sym_1_1061: la $2, sym_1_1061
+.globl sym_1_1062
+sym_1_1062: la $2, sym_1_1062
+.globl sym_1_1063
+sym_1_1063: la $2, sym_1_1063
+.globl sym_1_1064
+sym_1_1064: la $2, sym_1_1064
+.globl sym_1_1065
+sym_1_1065: la $2, sym_1_1065
+.globl sym_1_1066
+sym_1_1066: la $2, sym_1_1066
+.globl sym_1_1067
+sym_1_1067: la $2, sym_1_1067
+.globl sym_1_1068
+sym_1_1068: la $2, sym_1_1068
+.globl sym_1_1069
+sym_1_1069: la $2, sym_1_1069
+.globl sym_1_1070
+sym_1_1070: la $2, sym_1_1070
+.globl sym_1_1071
+sym_1_1071: la $2, sym_1_1071
+.globl sym_1_1072
+sym_1_1072: la $2, sym_1_1072
+.globl sym_1_1073
+sym_1_1073: la $2, sym_1_1073
+.globl sym_1_1074
+sym_1_1074: la $2, sym_1_1074
+.globl sym_1_1075
+sym_1_1075: la $2, sym_1_1075
+.globl sym_1_1076
+sym_1_1076: la $2, sym_1_1076
+.globl sym_1_1077
+sym_1_1077: la $2, sym_1_1077
+.globl sym_1_1078
+sym_1_1078: la $2, sym_1_1078
+.globl sym_1_1079
+sym_1_1079: la $2, sym_1_1079
+.globl sym_1_1080
+sym_1_1080: la $2, sym_1_1080
+.globl sym_1_1081
+sym_1_1081: la $2, sym_1_1081
+.globl sym_1_1082
+sym_1_1082: la $2, sym_1_1082
+.globl sym_1_1083
+sym_1_1083: la $2, sym_1_1083
+.globl sym_1_1084
+sym_1_1084: la $2, sym_1_1084
+.globl sym_1_1085
+sym_1_1085: la $2, sym_1_1085
+.globl sym_1_1086
+sym_1_1086: la $2, sym_1_1086
+.globl sym_1_1087
+sym_1_1087: la $2, sym_1_1087
+.globl sym_1_1088
+sym_1_1088: la $2, sym_1_1088
+.globl sym_1_1089
+sym_1_1089: la $2, sym_1_1089
+.globl sym_1_1090
+sym_1_1090: la $2, sym_1_1090
+.globl sym_1_1091
+sym_1_1091: la $2, sym_1_1091
+.globl sym_1_1092
+sym_1_1092: la $2, sym_1_1092
+.globl sym_1_1093
+sym_1_1093: la $2, sym_1_1093
+.globl sym_1_1094
+sym_1_1094: la $2, sym_1_1094
+.globl sym_1_1095
+sym_1_1095: la $2, sym_1_1095
+.globl sym_1_1096
+sym_1_1096: la $2, sym_1_1096
+.globl sym_1_1097
+sym_1_1097: la $2, sym_1_1097
+.globl sym_1_1098
+sym_1_1098: la $2, sym_1_1098
+.globl sym_1_1099
+sym_1_1099: la $2, sym_1_1099
+.globl sym_1_1100
+sym_1_1100: la $2, sym_1_1100
+.globl sym_1_1101
+sym_1_1101: la $2, sym_1_1101
+.globl sym_1_1102
+sym_1_1102: la $2, sym_1_1102
+.globl sym_1_1103
+sym_1_1103: la $2, sym_1_1103
+.globl sym_1_1104
+sym_1_1104: la $2, sym_1_1104
+.globl sym_1_1105
+sym_1_1105: la $2, sym_1_1105
+.globl sym_1_1106
+sym_1_1106: la $2, sym_1_1106
+.globl sym_1_1107
+sym_1_1107: la $2, sym_1_1107
+.globl sym_1_1108
+sym_1_1108: la $2, sym_1_1108
+.globl sym_1_1109
+sym_1_1109: la $2, sym_1_1109
+.globl sym_1_1110
+sym_1_1110: la $2, sym_1_1110
+.globl sym_1_1111
+sym_1_1111: la $2, sym_1_1111
+.globl sym_1_1112
+sym_1_1112: la $2, sym_1_1112
+.globl sym_1_1113
+sym_1_1113: la $2, sym_1_1113
+.globl sym_1_1114
+sym_1_1114: la $2, sym_1_1114
+.globl sym_1_1115
+sym_1_1115: la $2, sym_1_1115
+.globl sym_1_1116
+sym_1_1116: la $2, sym_1_1116
+.globl sym_1_1117
+sym_1_1117: la $2, sym_1_1117
+.globl sym_1_1118
+sym_1_1118: la $2, sym_1_1118
+.globl sym_1_1119
+sym_1_1119: la $2, sym_1_1119
+.globl sym_1_1120
+sym_1_1120: la $2, sym_1_1120
+.globl sym_1_1121
+sym_1_1121: la $2, sym_1_1121
+.globl sym_1_1122
+sym_1_1122: la $2, sym_1_1122
+.globl sym_1_1123
+sym_1_1123: la $2, sym_1_1123
+.globl sym_1_1124
+sym_1_1124: la $2, sym_1_1124
+.globl sym_1_1125
+sym_1_1125: la $2, sym_1_1125
+.globl sym_1_1126
+sym_1_1126: la $2, sym_1_1126
+.globl sym_1_1127
+sym_1_1127: la $2, sym_1_1127
+.globl sym_1_1128
+sym_1_1128: la $2, sym_1_1128
+.globl sym_1_1129
+sym_1_1129: la $2, sym_1_1129
+.globl sym_1_1130
+sym_1_1130: la $2, sym_1_1130
+.globl sym_1_1131
+sym_1_1131: la $2, sym_1_1131
+.globl sym_1_1132
+sym_1_1132: la $2, sym_1_1132
+.globl sym_1_1133
+sym_1_1133: la $2, sym_1_1133
+.globl sym_1_1134
+sym_1_1134: la $2, sym_1_1134
+.globl sym_1_1135
+sym_1_1135: la $2, sym_1_1135
+.globl sym_1_1136
+sym_1_1136: la $2, sym_1_1136
+.globl sym_1_1137
+sym_1_1137: la $2, sym_1_1137
+.globl sym_1_1138
+sym_1_1138: la $2, sym_1_1138
+.globl sym_1_1139
+sym_1_1139: la $2, sym_1_1139
+.globl sym_1_1140
+sym_1_1140: la $2, sym_1_1140
+.globl sym_1_1141
+sym_1_1141: la $2, sym_1_1141
+.globl sym_1_1142
+sym_1_1142: la $2, sym_1_1142
+.globl sym_1_1143
+sym_1_1143: la $2, sym_1_1143
+.globl sym_1_1144
+sym_1_1144: la $2, sym_1_1144
+.globl sym_1_1145
+sym_1_1145: la $2, sym_1_1145
+.globl sym_1_1146
+sym_1_1146: la $2, sym_1_1146
+.globl sym_1_1147
+sym_1_1147: la $2, sym_1_1147
+.globl sym_1_1148
+sym_1_1148: la $2, sym_1_1148
+.globl sym_1_1149
+sym_1_1149: la $2, sym_1_1149
+.globl sym_1_1150
+sym_1_1150: la $2, sym_1_1150
+.globl sym_1_1151
+sym_1_1151: la $2, sym_1_1151
+.globl sym_1_1152
+sym_1_1152: la $2, sym_1_1152
+.globl sym_1_1153
+sym_1_1153: la $2, sym_1_1153
+.globl sym_1_1154
+sym_1_1154: la $2, sym_1_1154
+.globl sym_1_1155
+sym_1_1155: la $2, sym_1_1155
+.globl sym_1_1156
+sym_1_1156: la $2, sym_1_1156
+.globl sym_1_1157
+sym_1_1157: la $2, sym_1_1157
+.globl sym_1_1158
+sym_1_1158: la $2, sym_1_1158
+.globl sym_1_1159
+sym_1_1159: la $2, sym_1_1159
+.globl sym_1_1160
+sym_1_1160: la $2, sym_1_1160
+.globl sym_1_1161
+sym_1_1161: la $2, sym_1_1161
+.globl sym_1_1162
+sym_1_1162: la $2, sym_1_1162
+.globl sym_1_1163
+sym_1_1163: la $2, sym_1_1163
+.globl sym_1_1164
+sym_1_1164: la $2, sym_1_1164
+.globl sym_1_1165
+sym_1_1165: la $2, sym_1_1165
+.globl sym_1_1166
+sym_1_1166: la $2, sym_1_1166
+.globl sym_1_1167
+sym_1_1167: la $2, sym_1_1167
+.globl sym_1_1168
+sym_1_1168: la $2, sym_1_1168
+.globl sym_1_1169
+sym_1_1169: la $2, sym_1_1169
+.globl sym_1_1170
+sym_1_1170: la $2, sym_1_1170
+.globl sym_1_1171
+sym_1_1171: la $2, sym_1_1171
+.globl sym_1_1172
+sym_1_1172: la $2, sym_1_1172
+.globl sym_1_1173
+sym_1_1173: la $2, sym_1_1173
+.globl sym_1_1174
+sym_1_1174: la $2, sym_1_1174
+.globl sym_1_1175
+sym_1_1175: la $2, sym_1_1175
+.globl sym_1_1176
+sym_1_1176: la $2, sym_1_1176
+.globl sym_1_1177
+sym_1_1177: la $2, sym_1_1177
+.globl sym_1_1178
+sym_1_1178: la $2, sym_1_1178
+.globl sym_1_1179
+sym_1_1179: la $2, sym_1_1179
+.globl sym_1_1180
+sym_1_1180: la $2, sym_1_1180
+.globl sym_1_1181
+sym_1_1181: la $2, sym_1_1181
+.globl sym_1_1182
+sym_1_1182: la $2, sym_1_1182
+.globl sym_1_1183
+sym_1_1183: la $2, sym_1_1183
+.globl sym_1_1184
+sym_1_1184: la $2, sym_1_1184
+.globl sym_1_1185
+sym_1_1185: la $2, sym_1_1185
+.globl sym_1_1186
+sym_1_1186: la $2, sym_1_1186
+.globl sym_1_1187
+sym_1_1187: la $2, sym_1_1187
+.globl sym_1_1188
+sym_1_1188: la $2, sym_1_1188
+.globl sym_1_1189
+sym_1_1189: la $2, sym_1_1189
+.globl sym_1_1190
+sym_1_1190: la $2, sym_1_1190
+.globl sym_1_1191
+sym_1_1191: la $2, sym_1_1191
+.globl sym_1_1192
+sym_1_1192: la $2, sym_1_1192
+.globl sym_1_1193
+sym_1_1193: la $2, sym_1_1193
+.globl sym_1_1194
+sym_1_1194: la $2, sym_1_1194
+.globl sym_1_1195
+sym_1_1195: la $2, sym_1_1195
+.globl sym_1_1196
+sym_1_1196: la $2, sym_1_1196
+.globl sym_1_1197
+sym_1_1197: la $2, sym_1_1197
+.globl sym_1_1198
+sym_1_1198: la $2, sym_1_1198
+.globl sym_1_1199
+sym_1_1199: la $2, sym_1_1199
+.globl sym_1_1200
+sym_1_1200: la $2, sym_1_1200
+.globl sym_1_1201
+sym_1_1201: la $2, sym_1_1201
+.globl sym_1_1202
+sym_1_1202: la $2, sym_1_1202
+.globl sym_1_1203
+sym_1_1203: la $2, sym_1_1203
+.globl sym_1_1204
+sym_1_1204: la $2, sym_1_1204
+.globl sym_1_1205
+sym_1_1205: la $2, sym_1_1205
+.globl sym_1_1206
+sym_1_1206: la $2, sym_1_1206
+.globl sym_1_1207
+sym_1_1207: la $2, sym_1_1207
+.globl sym_1_1208
+sym_1_1208: la $2, sym_1_1208
+.globl sym_1_1209
+sym_1_1209: la $2, sym_1_1209
+.globl sym_1_1210
+sym_1_1210: la $2, sym_1_1210
+.globl sym_1_1211
+sym_1_1211: la $2, sym_1_1211
+.globl sym_1_1212
+sym_1_1212: la $2, sym_1_1212
+.globl sym_1_1213
+sym_1_1213: la $2, sym_1_1213
+.globl sym_1_1214
+sym_1_1214: la $2, sym_1_1214
+.globl sym_1_1215
+sym_1_1215: la $2, sym_1_1215
+.globl sym_1_1216
+sym_1_1216: la $2, sym_1_1216
+.globl sym_1_1217
+sym_1_1217: la $2, sym_1_1217
+.globl sym_1_1218
+sym_1_1218: la $2, sym_1_1218
+.globl sym_1_1219
+sym_1_1219: la $2, sym_1_1219
+.globl sym_1_1220
+sym_1_1220: la $2, sym_1_1220
+.globl sym_1_1221
+sym_1_1221: la $2, sym_1_1221
+.globl sym_1_1222
+sym_1_1222: la $2, sym_1_1222
+.globl sym_1_1223
+sym_1_1223: la $2, sym_1_1223
+.globl sym_1_1224
+sym_1_1224: la $2, sym_1_1224
+.globl sym_1_1225
+sym_1_1225: la $2, sym_1_1225
+.globl sym_1_1226
+sym_1_1226: la $2, sym_1_1226
+.globl sym_1_1227
+sym_1_1227: la $2, sym_1_1227
+.globl sym_1_1228
+sym_1_1228: la $2, sym_1_1228
+.globl sym_1_1229
+sym_1_1229: la $2, sym_1_1229
+.globl sym_1_1230
+sym_1_1230: la $2, sym_1_1230
+.globl sym_1_1231
+sym_1_1231: la $2, sym_1_1231
+.globl sym_1_1232
+sym_1_1232: la $2, sym_1_1232
+.globl sym_1_1233
+sym_1_1233: la $2, sym_1_1233
+.globl sym_1_1234
+sym_1_1234: la $2, sym_1_1234
+.globl sym_1_1235
+sym_1_1235: la $2, sym_1_1235
+.globl sym_1_1236
+sym_1_1236: la $2, sym_1_1236
+.globl sym_1_1237
+sym_1_1237: la $2, sym_1_1237
+.globl sym_1_1238
+sym_1_1238: la $2, sym_1_1238
+.globl sym_1_1239
+sym_1_1239: la $2, sym_1_1239
+.globl sym_1_1240
+sym_1_1240: la $2, sym_1_1240
+.globl sym_1_1241
+sym_1_1241: la $2, sym_1_1241
+.globl sym_1_1242
+sym_1_1242: la $2, sym_1_1242
+.globl sym_1_1243
+sym_1_1243: la $2, sym_1_1243
+.globl sym_1_1244
+sym_1_1244: la $2, sym_1_1244
+.globl sym_1_1245
+sym_1_1245: la $2, sym_1_1245
+.globl sym_1_1246
+sym_1_1246: la $2, sym_1_1246
+.globl sym_1_1247
+sym_1_1247: la $2, sym_1_1247
+.globl sym_1_1248
+sym_1_1248: la $2, sym_1_1248
+.globl sym_1_1249
+sym_1_1249: la $2, sym_1_1249
+.globl sym_1_1250
+sym_1_1250: la $2, sym_1_1250
+.globl sym_1_1251
+sym_1_1251: la $2, sym_1_1251
+.globl sym_1_1252
+sym_1_1252: la $2, sym_1_1252
+.globl sym_1_1253
+sym_1_1253: la $2, sym_1_1253
+.globl sym_1_1254
+sym_1_1254: la $2, sym_1_1254
+.globl sym_1_1255
+sym_1_1255: la $2, sym_1_1255
+.globl sym_1_1256
+sym_1_1256: la $2, sym_1_1256
+.globl sym_1_1257
+sym_1_1257: la $2, sym_1_1257
+.globl sym_1_1258
+sym_1_1258: la $2, sym_1_1258
+.globl sym_1_1259
+sym_1_1259: la $2, sym_1_1259
+.globl sym_1_1260
+sym_1_1260: la $2, sym_1_1260
+.globl sym_1_1261
+sym_1_1261: la $2, sym_1_1261
+.globl sym_1_1262
+sym_1_1262: la $2, sym_1_1262
+.globl sym_1_1263
+sym_1_1263: la $2, sym_1_1263
+.globl sym_1_1264
+sym_1_1264: la $2, sym_1_1264
+.globl sym_1_1265
+sym_1_1265: la $2, sym_1_1265
+.globl sym_1_1266
+sym_1_1266: la $2, sym_1_1266
+.globl sym_1_1267
+sym_1_1267: la $2, sym_1_1267
+.globl sym_1_1268
+sym_1_1268: la $2, sym_1_1268
+.globl sym_1_1269
+sym_1_1269: la $2, sym_1_1269
+.globl sym_1_1270
+sym_1_1270: la $2, sym_1_1270
+.globl sym_1_1271
+sym_1_1271: la $2, sym_1_1271
+.globl sym_1_1272
+sym_1_1272: la $2, sym_1_1272
+.globl sym_1_1273
+sym_1_1273: la $2, sym_1_1273
+.globl sym_1_1274
+sym_1_1274: la $2, sym_1_1274
+.globl sym_1_1275
+sym_1_1275: la $2, sym_1_1275
+.globl sym_1_1276
+sym_1_1276: la $2, sym_1_1276
+.globl sym_1_1277
+sym_1_1277: la $2, sym_1_1277
+.globl sym_1_1278
+sym_1_1278: la $2, sym_1_1278
+.globl sym_1_1279
+sym_1_1279: la $2, sym_1_1279
+.globl sym_1_1280
+sym_1_1280: la $2, sym_1_1280
+.globl sym_1_1281
+sym_1_1281: la $2, sym_1_1281
+.globl sym_1_1282
+sym_1_1282: la $2, sym_1_1282
+.globl sym_1_1283
+sym_1_1283: la $2, sym_1_1283
+.globl sym_1_1284
+sym_1_1284: la $2, sym_1_1284
+.globl sym_1_1285
+sym_1_1285: la $2, sym_1_1285
+.globl sym_1_1286
+sym_1_1286: la $2, sym_1_1286
+.globl sym_1_1287
+sym_1_1287: la $2, sym_1_1287
+.globl sym_1_1288
+sym_1_1288: la $2, sym_1_1288
+.globl sym_1_1289
+sym_1_1289: la $2, sym_1_1289
+.globl sym_1_1290
+sym_1_1290: la $2, sym_1_1290
+.globl sym_1_1291
+sym_1_1291: la $2, sym_1_1291
+.globl sym_1_1292
+sym_1_1292: la $2, sym_1_1292
+.globl sym_1_1293
+sym_1_1293: la $2, sym_1_1293
+.globl sym_1_1294
+sym_1_1294: la $2, sym_1_1294
+.globl sym_1_1295
+sym_1_1295: la $2, sym_1_1295
+.globl sym_1_1296
+sym_1_1296: la $2, sym_1_1296
+.globl sym_1_1297
+sym_1_1297: la $2, sym_1_1297
+.globl sym_1_1298
+sym_1_1298: la $2, sym_1_1298
+.globl sym_1_1299
+sym_1_1299: la $2, sym_1_1299
+.globl sym_1_1300
+sym_1_1300: la $2, sym_1_1300
+.globl sym_1_1301
+sym_1_1301: la $2, sym_1_1301
+.globl sym_1_1302
+sym_1_1302: la $2, sym_1_1302
+.globl sym_1_1303
+sym_1_1303: la $2, sym_1_1303
+.globl sym_1_1304
+sym_1_1304: la $2, sym_1_1304
+.globl sym_1_1305
+sym_1_1305: la $2, sym_1_1305
+.globl sym_1_1306
+sym_1_1306: la $2, sym_1_1306
+.globl sym_1_1307
+sym_1_1307: la $2, sym_1_1307
+.globl sym_1_1308
+sym_1_1308: la $2, sym_1_1308
+.globl sym_1_1309
+sym_1_1309: la $2, sym_1_1309
+.globl sym_1_1310
+sym_1_1310: la $2, sym_1_1310
+.globl sym_1_1311
+sym_1_1311: la $2, sym_1_1311
+.globl sym_1_1312
+sym_1_1312: la $2, sym_1_1312
+.globl sym_1_1313
+sym_1_1313: la $2, sym_1_1313
+.globl sym_1_1314
+sym_1_1314: la $2, sym_1_1314
+.globl sym_1_1315
+sym_1_1315: la $2, sym_1_1315
+.globl sym_1_1316
+sym_1_1316: la $2, sym_1_1316
+.globl sym_1_1317
+sym_1_1317: la $2, sym_1_1317
+.globl sym_1_1318
+sym_1_1318: la $2, sym_1_1318
+.globl sym_1_1319
+sym_1_1319: la $2, sym_1_1319
+.globl sym_1_1320
+sym_1_1320: la $2, sym_1_1320
+.globl sym_1_1321
+sym_1_1321: la $2, sym_1_1321
+.globl sym_1_1322
+sym_1_1322: la $2, sym_1_1322
+.globl sym_1_1323
+sym_1_1323: la $2, sym_1_1323
+.globl sym_1_1324
+sym_1_1324: la $2, sym_1_1324
+.globl sym_1_1325
+sym_1_1325: la $2, sym_1_1325
+.globl sym_1_1326
+sym_1_1326: la $2, sym_1_1326
+.globl sym_1_1327
+sym_1_1327: la $2, sym_1_1327
+.globl sym_1_1328
+sym_1_1328: la $2, sym_1_1328
+.globl sym_1_1329
+sym_1_1329: la $2, sym_1_1329
+.globl sym_1_1330
+sym_1_1330: la $2, sym_1_1330
+.globl sym_1_1331
+sym_1_1331: la $2, sym_1_1331
+.globl sym_1_1332
+sym_1_1332: la $2, sym_1_1332
+.globl sym_1_1333
+sym_1_1333: la $2, sym_1_1333
+.globl sym_1_1334
+sym_1_1334: la $2, sym_1_1334
+.globl sym_1_1335
+sym_1_1335: la $2, sym_1_1335
+.globl sym_1_1336
+sym_1_1336: la $2, sym_1_1336
+.globl sym_1_1337
+sym_1_1337: la $2, sym_1_1337
+.globl sym_1_1338
+sym_1_1338: la $2, sym_1_1338
+.globl sym_1_1339
+sym_1_1339: la $2, sym_1_1339
+.globl sym_1_1340
+sym_1_1340: la $2, sym_1_1340
+.globl sym_1_1341
+sym_1_1341: la $2, sym_1_1341
+.globl sym_1_1342
+sym_1_1342: la $2, sym_1_1342
+.globl sym_1_1343
+sym_1_1343: la $2, sym_1_1343
+.globl sym_1_1344
+sym_1_1344: la $2, sym_1_1344
+.globl sym_1_1345
+sym_1_1345: la $2, sym_1_1345
+.globl sym_1_1346
+sym_1_1346: la $2, sym_1_1346
+.globl sym_1_1347
+sym_1_1347: la $2, sym_1_1347
+.globl sym_1_1348
+sym_1_1348: la $2, sym_1_1348
+.globl sym_1_1349
+sym_1_1349: la $2, sym_1_1349
+.globl sym_1_1350
+sym_1_1350: la $2, sym_1_1350
+.globl sym_1_1351
+sym_1_1351: la $2, sym_1_1351
+.globl sym_1_1352
+sym_1_1352: la $2, sym_1_1352
+.globl sym_1_1353
+sym_1_1353: la $2, sym_1_1353
+.globl sym_1_1354
+sym_1_1354: la $2, sym_1_1354
+.globl sym_1_1355
+sym_1_1355: la $2, sym_1_1355
+.globl sym_1_1356
+sym_1_1356: la $2, sym_1_1356
+.globl sym_1_1357
+sym_1_1357: la $2, sym_1_1357
+.globl sym_1_1358
+sym_1_1358: la $2, sym_1_1358
+.globl sym_1_1359
+sym_1_1359: la $2, sym_1_1359
+.globl sym_1_1360
+sym_1_1360: la $2, sym_1_1360
+.globl sym_1_1361
+sym_1_1361: la $2, sym_1_1361
+.globl sym_1_1362
+sym_1_1362: la $2, sym_1_1362
+.globl sym_1_1363
+sym_1_1363: la $2, sym_1_1363
+.globl sym_1_1364
+sym_1_1364: la $2, sym_1_1364
+.globl sym_1_1365
+sym_1_1365: la $2, sym_1_1365
+.globl sym_1_1366
+sym_1_1366: la $2, sym_1_1366
+.globl sym_1_1367
+sym_1_1367: la $2, sym_1_1367
+.globl sym_1_1368
+sym_1_1368: la $2, sym_1_1368
+.globl sym_1_1369
+sym_1_1369: la $2, sym_1_1369
+.globl sym_1_1370
+sym_1_1370: la $2, sym_1_1370
+.globl sym_1_1371
+sym_1_1371: la $2, sym_1_1371
+.globl sym_1_1372
+sym_1_1372: la $2, sym_1_1372
+.globl sym_1_1373
+sym_1_1373: la $2, sym_1_1373
+.globl sym_1_1374
+sym_1_1374: la $2, sym_1_1374
+.globl sym_1_1375
+sym_1_1375: la $2, sym_1_1375
+.globl sym_1_1376
+sym_1_1376: la $2, sym_1_1376
+.globl sym_1_1377
+sym_1_1377: la $2, sym_1_1377
+.globl sym_1_1378
+sym_1_1378: la $2, sym_1_1378
+.globl sym_1_1379
+sym_1_1379: la $2, sym_1_1379
+.globl sym_1_1380
+sym_1_1380: la $2, sym_1_1380
+.globl sym_1_1381
+sym_1_1381: la $2, sym_1_1381
+.globl sym_1_1382
+sym_1_1382: la $2, sym_1_1382
+.globl sym_1_1383
+sym_1_1383: la $2, sym_1_1383
+.globl sym_1_1384
+sym_1_1384: la $2, sym_1_1384
+.globl sym_1_1385
+sym_1_1385: la $2, sym_1_1385
+.globl sym_1_1386
+sym_1_1386: la $2, sym_1_1386
+.globl sym_1_1387
+sym_1_1387: la $2, sym_1_1387
+.globl sym_1_1388
+sym_1_1388: la $2, sym_1_1388
+.globl sym_1_1389
+sym_1_1389: la $2, sym_1_1389
+.globl sym_1_1390
+sym_1_1390: la $2, sym_1_1390
+.globl sym_1_1391
+sym_1_1391: la $2, sym_1_1391
+.globl sym_1_1392
+sym_1_1392: la $2, sym_1_1392
+.globl sym_1_1393
+sym_1_1393: la $2, sym_1_1393
+.globl sym_1_1394
+sym_1_1394: la $2, sym_1_1394
+.globl sym_1_1395
+sym_1_1395: la $2, sym_1_1395
+.globl sym_1_1396
+sym_1_1396: la $2, sym_1_1396
+.globl sym_1_1397
+sym_1_1397: la $2, sym_1_1397
+.globl sym_1_1398
+sym_1_1398: la $2, sym_1_1398
+.globl sym_1_1399
+sym_1_1399: la $2, sym_1_1399
+.globl sym_1_1400
+sym_1_1400: la $2, sym_1_1400
+.globl sym_1_1401
+sym_1_1401: la $2, sym_1_1401
+.globl sym_1_1402
+sym_1_1402: la $2, sym_1_1402
+.globl sym_1_1403
+sym_1_1403: la $2, sym_1_1403
+.globl sym_1_1404
+sym_1_1404: la $2, sym_1_1404
+.globl sym_1_1405
+sym_1_1405: la $2, sym_1_1405
+.globl sym_1_1406
+sym_1_1406: la $2, sym_1_1406
+.globl sym_1_1407
+sym_1_1407: la $2, sym_1_1407
+.globl sym_1_1408
+sym_1_1408: la $2, sym_1_1408
+.globl sym_1_1409
+sym_1_1409: la $2, sym_1_1409
+.globl sym_1_1410
+sym_1_1410: la $2, sym_1_1410
+.globl sym_1_1411
+sym_1_1411: la $2, sym_1_1411
+.globl sym_1_1412
+sym_1_1412: la $2, sym_1_1412
+.globl sym_1_1413
+sym_1_1413: la $2, sym_1_1413
+.globl sym_1_1414
+sym_1_1414: la $2, sym_1_1414
+.globl sym_1_1415
+sym_1_1415: la $2, sym_1_1415
+.globl sym_1_1416
+sym_1_1416: la $2, sym_1_1416
+.globl sym_1_1417
+sym_1_1417: la $2, sym_1_1417
+.globl sym_1_1418
+sym_1_1418: la $2, sym_1_1418
+.globl sym_1_1419
+sym_1_1419: la $2, sym_1_1419
+.globl sym_1_1420
+sym_1_1420: la $2, sym_1_1420
+.globl sym_1_1421
+sym_1_1421: la $2, sym_1_1421
+.globl sym_1_1422
+sym_1_1422: la $2, sym_1_1422
+.globl sym_1_1423
+sym_1_1423: la $2, sym_1_1423
+.globl sym_1_1424
+sym_1_1424: la $2, sym_1_1424
+.globl sym_1_1425
+sym_1_1425: la $2, sym_1_1425
+.globl sym_1_1426
+sym_1_1426: la $2, sym_1_1426
+.globl sym_1_1427
+sym_1_1427: la $2, sym_1_1427
+.globl sym_1_1428
+sym_1_1428: la $2, sym_1_1428
+.globl sym_1_1429
+sym_1_1429: la $2, sym_1_1429
+.globl sym_1_1430
+sym_1_1430: la $2, sym_1_1430
+.globl sym_1_1431
+sym_1_1431: la $2, sym_1_1431
+.globl sym_1_1432
+sym_1_1432: la $2, sym_1_1432
+.globl sym_1_1433
+sym_1_1433: la $2, sym_1_1433
+.globl sym_1_1434
+sym_1_1434: la $2, sym_1_1434
+.globl sym_1_1435
+sym_1_1435: la $2, sym_1_1435
+.globl sym_1_1436
+sym_1_1436: la $2, sym_1_1436
+.globl sym_1_1437
+sym_1_1437: la $2, sym_1_1437
+.globl sym_1_1438
+sym_1_1438: la $2, sym_1_1438
+.globl sym_1_1439
+sym_1_1439: la $2, sym_1_1439
+.globl sym_1_1440
+sym_1_1440: la $2, sym_1_1440
+.globl sym_1_1441
+sym_1_1441: la $2, sym_1_1441
+.globl sym_1_1442
+sym_1_1442: la $2, sym_1_1442
+.globl sym_1_1443
+sym_1_1443: la $2, sym_1_1443
+.globl sym_1_1444
+sym_1_1444: la $2, sym_1_1444
+.globl sym_1_1445
+sym_1_1445: la $2, sym_1_1445
+.globl sym_1_1446
+sym_1_1446: la $2, sym_1_1446
+.globl sym_1_1447
+sym_1_1447: la $2, sym_1_1447
+.globl sym_1_1448
+sym_1_1448: la $2, sym_1_1448
+.globl sym_1_1449
+sym_1_1449: la $2, sym_1_1449
+.globl sym_1_1450
+sym_1_1450: la $2, sym_1_1450
+.globl sym_1_1451
+sym_1_1451: la $2, sym_1_1451
+.globl sym_1_1452
+sym_1_1452: la $2, sym_1_1452
+.globl sym_1_1453
+sym_1_1453: la $2, sym_1_1453
+.globl sym_1_1454
+sym_1_1454: la $2, sym_1_1454
+.globl sym_1_1455
+sym_1_1455: la $2, sym_1_1455
+.globl sym_1_1456
+sym_1_1456: la $2, sym_1_1456
+.globl sym_1_1457
+sym_1_1457: la $2, sym_1_1457
+.globl sym_1_1458
+sym_1_1458: la $2, sym_1_1458
+.globl sym_1_1459
+sym_1_1459: la $2, sym_1_1459
+.globl sym_1_1460
+sym_1_1460: la $2, sym_1_1460
+.globl sym_1_1461
+sym_1_1461: la $2, sym_1_1461
+.globl sym_1_1462
+sym_1_1462: la $2, sym_1_1462
+.globl sym_1_1463
+sym_1_1463: la $2, sym_1_1463
+.globl sym_1_1464
+sym_1_1464: la $2, sym_1_1464
+.globl sym_1_1465
+sym_1_1465: la $2, sym_1_1465
+.globl sym_1_1466
+sym_1_1466: la $2, sym_1_1466
+.globl sym_1_1467
+sym_1_1467: la $2, sym_1_1467
+.globl sym_1_1468
+sym_1_1468: la $2, sym_1_1468
+.globl sym_1_1469
+sym_1_1469: la $2, sym_1_1469
+.globl sym_1_1470
+sym_1_1470: la $2, sym_1_1470
+.globl sym_1_1471
+sym_1_1471: la $2, sym_1_1471
+.globl sym_1_1472
+sym_1_1472: la $2, sym_1_1472
+.globl sym_1_1473
+sym_1_1473: la $2, sym_1_1473
+.globl sym_1_1474
+sym_1_1474: la $2, sym_1_1474
+.globl sym_1_1475
+sym_1_1475: la $2, sym_1_1475
+.globl sym_1_1476
+sym_1_1476: la $2, sym_1_1476
+.globl sym_1_1477
+sym_1_1477: la $2, sym_1_1477
+.globl sym_1_1478
+sym_1_1478: la $2, sym_1_1478
+.globl sym_1_1479
+sym_1_1479: la $2, sym_1_1479
+.globl sym_1_1480
+sym_1_1480: la $2, sym_1_1480
+.globl sym_1_1481
+sym_1_1481: la $2, sym_1_1481
+.globl sym_1_1482
+sym_1_1482: la $2, sym_1_1482
+.globl sym_1_1483
+sym_1_1483: la $2, sym_1_1483
+.globl sym_1_1484
+sym_1_1484: la $2, sym_1_1484
+.globl sym_1_1485
+sym_1_1485: la $2, sym_1_1485
+.globl sym_1_1486
+sym_1_1486: la $2, sym_1_1486
+.globl sym_1_1487
+sym_1_1487: la $2, sym_1_1487
+.globl sym_1_1488
+sym_1_1488: la $2, sym_1_1488
+.globl sym_1_1489
+sym_1_1489: la $2, sym_1_1489
+.globl sym_1_1490
+sym_1_1490: la $2, sym_1_1490
+.globl sym_1_1491
+sym_1_1491: la $2, sym_1_1491
+.globl sym_1_1492
+sym_1_1492: la $2, sym_1_1492
+.globl sym_1_1493
+sym_1_1493: la $2, sym_1_1493
+.globl sym_1_1494
+sym_1_1494: la $2, sym_1_1494
+.globl sym_1_1495
+sym_1_1495: la $2, sym_1_1495
+.globl sym_1_1496
+sym_1_1496: la $2, sym_1_1496
+.globl sym_1_1497
+sym_1_1497: la $2, sym_1_1497
+.globl sym_1_1498
+sym_1_1498: la $2, sym_1_1498
+.globl sym_1_1499
+sym_1_1499: la $2, sym_1_1499
+.globl sym_1_1500
+sym_1_1500: la $2, sym_1_1500
+.globl sym_1_1501
+sym_1_1501: la $2, sym_1_1501
+.globl sym_1_1502
+sym_1_1502: la $2, sym_1_1502
+.globl sym_1_1503
+sym_1_1503: la $2, sym_1_1503
+.globl sym_1_1504
+sym_1_1504: la $2, sym_1_1504
+.globl sym_1_1505
+sym_1_1505: la $2, sym_1_1505
+.globl sym_1_1506
+sym_1_1506: la $2, sym_1_1506
+.globl sym_1_1507
+sym_1_1507: la $2, sym_1_1507
+.globl sym_1_1508
+sym_1_1508: la $2, sym_1_1508
+.globl sym_1_1509
+sym_1_1509: la $2, sym_1_1509
+.globl sym_1_1510
+sym_1_1510: la $2, sym_1_1510
+.globl sym_1_1511
+sym_1_1511: la $2, sym_1_1511
+.globl sym_1_1512
+sym_1_1512: la $2, sym_1_1512
+.globl sym_1_1513
+sym_1_1513: la $2, sym_1_1513
+.globl sym_1_1514
+sym_1_1514: la $2, sym_1_1514
+.globl sym_1_1515
+sym_1_1515: la $2, sym_1_1515
+.globl sym_1_1516
+sym_1_1516: la $2, sym_1_1516
+.globl sym_1_1517
+sym_1_1517: la $2, sym_1_1517
+.globl sym_1_1518
+sym_1_1518: la $2, sym_1_1518
+.globl sym_1_1519
+sym_1_1519: la $2, sym_1_1519
+.globl sym_1_1520
+sym_1_1520: la $2, sym_1_1520
+.globl sym_1_1521
+sym_1_1521: la $2, sym_1_1521
+.globl sym_1_1522
+sym_1_1522: la $2, sym_1_1522
+.globl sym_1_1523
+sym_1_1523: la $2, sym_1_1523
+.globl sym_1_1524
+sym_1_1524: la $2, sym_1_1524
+.globl sym_1_1525
+sym_1_1525: la $2, sym_1_1525
+.globl sym_1_1526
+sym_1_1526: la $2, sym_1_1526
+.globl sym_1_1527
+sym_1_1527: la $2, sym_1_1527
+.globl sym_1_1528
+sym_1_1528: la $2, sym_1_1528
+.globl sym_1_1529
+sym_1_1529: la $2, sym_1_1529
+.globl sym_1_1530
+sym_1_1530: la $2, sym_1_1530
+.globl sym_1_1531
+sym_1_1531: la $2, sym_1_1531
+.globl sym_1_1532
+sym_1_1532: la $2, sym_1_1532
+.globl sym_1_1533
+sym_1_1533: la $2, sym_1_1533
+.globl sym_1_1534
+sym_1_1534: la $2, sym_1_1534
+.globl sym_1_1535
+sym_1_1535: la $2, sym_1_1535
+.globl sym_1_1536
+sym_1_1536: la $2, sym_1_1536
+.globl sym_1_1537
+sym_1_1537: la $2, sym_1_1537
+.globl sym_1_1538
+sym_1_1538: la $2, sym_1_1538
+.globl sym_1_1539
+sym_1_1539: la $2, sym_1_1539
+.globl sym_1_1540
+sym_1_1540: la $2, sym_1_1540
+.globl sym_1_1541
+sym_1_1541: la $2, sym_1_1541
+.globl sym_1_1542
+sym_1_1542: la $2, sym_1_1542
+.globl sym_1_1543
+sym_1_1543: la $2, sym_1_1543
+.globl sym_1_1544
+sym_1_1544: la $2, sym_1_1544
+.globl sym_1_1545
+sym_1_1545: la $2, sym_1_1545
+.globl sym_1_1546
+sym_1_1546: la $2, sym_1_1546
+.globl sym_1_1547
+sym_1_1547: la $2, sym_1_1547
+.globl sym_1_1548
+sym_1_1548: la $2, sym_1_1548
+.globl sym_1_1549
+sym_1_1549: la $2, sym_1_1549
+.globl sym_1_1550
+sym_1_1550: la $2, sym_1_1550
+.globl sym_1_1551
+sym_1_1551: la $2, sym_1_1551
+.globl sym_1_1552
+sym_1_1552: la $2, sym_1_1552
+.globl sym_1_1553
+sym_1_1553: la $2, sym_1_1553
+.globl sym_1_1554
+sym_1_1554: la $2, sym_1_1554
+.globl sym_1_1555
+sym_1_1555: la $2, sym_1_1555
+.globl sym_1_1556
+sym_1_1556: la $2, sym_1_1556
+.globl sym_1_1557
+sym_1_1557: la $2, sym_1_1557
+.globl sym_1_1558
+sym_1_1558: la $2, sym_1_1558
+.globl sym_1_1559
+sym_1_1559: la $2, sym_1_1559
+.globl sym_1_1560
+sym_1_1560: la $2, sym_1_1560
+.globl sym_1_1561
+sym_1_1561: la $2, sym_1_1561
+.globl sym_1_1562
+sym_1_1562: la $2, sym_1_1562
+.globl sym_1_1563
+sym_1_1563: la $2, sym_1_1563
+.globl sym_1_1564
+sym_1_1564: la $2, sym_1_1564
+.globl sym_1_1565
+sym_1_1565: la $2, sym_1_1565
+.globl sym_1_1566
+sym_1_1566: la $2, sym_1_1566
+.globl sym_1_1567
+sym_1_1567: la $2, sym_1_1567
+.globl sym_1_1568
+sym_1_1568: la $2, sym_1_1568
+.globl sym_1_1569
+sym_1_1569: la $2, sym_1_1569
+.globl sym_1_1570
+sym_1_1570: la $2, sym_1_1570
+.globl sym_1_1571
+sym_1_1571: la $2, sym_1_1571
+.globl sym_1_1572
+sym_1_1572: la $2, sym_1_1572
+.globl sym_1_1573
+sym_1_1573: la $2, sym_1_1573
+.globl sym_1_1574
+sym_1_1574: la $2, sym_1_1574
+.globl sym_1_1575
+sym_1_1575: la $2, sym_1_1575
+.globl sym_1_1576
+sym_1_1576: la $2, sym_1_1576
+.globl sym_1_1577
+sym_1_1577: la $2, sym_1_1577
+.globl sym_1_1578
+sym_1_1578: la $2, sym_1_1578
+.globl sym_1_1579
+sym_1_1579: la $2, sym_1_1579
+.globl sym_1_1580
+sym_1_1580: la $2, sym_1_1580
+.globl sym_1_1581
+sym_1_1581: la $2, sym_1_1581
+.globl sym_1_1582
+sym_1_1582: la $2, sym_1_1582
+.globl sym_1_1583
+sym_1_1583: la $2, sym_1_1583
+.globl sym_1_1584
+sym_1_1584: la $2, sym_1_1584
+.globl sym_1_1585
+sym_1_1585: la $2, sym_1_1585
+.globl sym_1_1586
+sym_1_1586: la $2, sym_1_1586
+.globl sym_1_1587
+sym_1_1587: la $2, sym_1_1587
+.globl sym_1_1588
+sym_1_1588: la $2, sym_1_1588
+.globl sym_1_1589
+sym_1_1589: la $2, sym_1_1589
+.globl sym_1_1590
+sym_1_1590: la $2, sym_1_1590
+.globl sym_1_1591
+sym_1_1591: la $2, sym_1_1591
+.globl sym_1_1592
+sym_1_1592: la $2, sym_1_1592
+.globl sym_1_1593
+sym_1_1593: la $2, sym_1_1593
+.globl sym_1_1594
+sym_1_1594: la $2, sym_1_1594
+.globl sym_1_1595
+sym_1_1595: la $2, sym_1_1595
+.globl sym_1_1596
+sym_1_1596: la $2, sym_1_1596
+.globl sym_1_1597
+sym_1_1597: la $2, sym_1_1597
+.globl sym_1_1598
+sym_1_1598: la $2, sym_1_1598
+.globl sym_1_1599
+sym_1_1599: la $2, sym_1_1599
+.globl sym_1_1600
+sym_1_1600: la $2, sym_1_1600
+.globl sym_1_1601
+sym_1_1601: la $2, sym_1_1601
+.globl sym_1_1602
+sym_1_1602: la $2, sym_1_1602
+.globl sym_1_1603
+sym_1_1603: la $2, sym_1_1603
+.globl sym_1_1604
+sym_1_1604: la $2, sym_1_1604
+.globl sym_1_1605
+sym_1_1605: la $2, sym_1_1605
+.globl sym_1_1606
+sym_1_1606: la $2, sym_1_1606
+.globl sym_1_1607
+sym_1_1607: la $2, sym_1_1607
+.globl sym_1_1608
+sym_1_1608: la $2, sym_1_1608
+.globl sym_1_1609
+sym_1_1609: la $2, sym_1_1609
+.globl sym_1_1610
+sym_1_1610: la $2, sym_1_1610
+.globl sym_1_1611
+sym_1_1611: la $2, sym_1_1611
+.globl sym_1_1612
+sym_1_1612: la $2, sym_1_1612
+.globl sym_1_1613
+sym_1_1613: la $2, sym_1_1613
+.globl sym_1_1614
+sym_1_1614: la $2, sym_1_1614
+.globl sym_1_1615
+sym_1_1615: la $2, sym_1_1615
+.globl sym_1_1616
+sym_1_1616: la $2, sym_1_1616
+.globl sym_1_1617
+sym_1_1617: la $2, sym_1_1617
+.globl sym_1_1618
+sym_1_1618: la $2, sym_1_1618
+.globl sym_1_1619
+sym_1_1619: la $2, sym_1_1619
+.globl sym_1_1620
+sym_1_1620: la $2, sym_1_1620
+.globl sym_1_1621
+sym_1_1621: la $2, sym_1_1621
+.globl sym_1_1622
+sym_1_1622: la $2, sym_1_1622
+.globl sym_1_1623
+sym_1_1623: la $2, sym_1_1623
+.globl sym_1_1624
+sym_1_1624: la $2, sym_1_1624
+.globl sym_1_1625
+sym_1_1625: la $2, sym_1_1625
+.globl sym_1_1626
+sym_1_1626: la $2, sym_1_1626
+.globl sym_1_1627
+sym_1_1627: la $2, sym_1_1627
+.globl sym_1_1628
+sym_1_1628: la $2, sym_1_1628
+.globl sym_1_1629
+sym_1_1629: la $2, sym_1_1629
+.globl sym_1_1630
+sym_1_1630: la $2, sym_1_1630
+.globl sym_1_1631
+sym_1_1631: la $2, sym_1_1631
+.globl sym_1_1632
+sym_1_1632: la $2, sym_1_1632
+.globl sym_1_1633
+sym_1_1633: la $2, sym_1_1633
+.globl sym_1_1634
+sym_1_1634: la $2, sym_1_1634
+.globl sym_1_1635
+sym_1_1635: la $2, sym_1_1635
+.globl sym_1_1636
+sym_1_1636: la $2, sym_1_1636
+.globl sym_1_1637
+sym_1_1637: la $2, sym_1_1637
+.globl sym_1_1638
+sym_1_1638: la $2, sym_1_1638
+.globl sym_1_1639
+sym_1_1639: la $2, sym_1_1639
+.globl sym_1_1640
+sym_1_1640: la $2, sym_1_1640
+.globl sym_1_1641
+sym_1_1641: la $2, sym_1_1641
+.globl sym_1_1642
+sym_1_1642: la $2, sym_1_1642
+.globl sym_1_1643
+sym_1_1643: la $2, sym_1_1643
+.globl sym_1_1644
+sym_1_1644: la $2, sym_1_1644
+.globl sym_1_1645
+sym_1_1645: la $2, sym_1_1645
+.globl sym_1_1646
+sym_1_1646: la $2, sym_1_1646
+.globl sym_1_1647
+sym_1_1647: la $2, sym_1_1647
+.globl sym_1_1648
+sym_1_1648: la $2, sym_1_1648
+.globl sym_1_1649
+sym_1_1649: la $2, sym_1_1649
+.globl sym_1_1650
+sym_1_1650: la $2, sym_1_1650
+.globl sym_1_1651
+sym_1_1651: la $2, sym_1_1651
+.globl sym_1_1652
+sym_1_1652: la $2, sym_1_1652
+.globl sym_1_1653
+sym_1_1653: la $2, sym_1_1653
+.globl sym_1_1654
+sym_1_1654: la $2, sym_1_1654
+.globl sym_1_1655
+sym_1_1655: la $2, sym_1_1655
+.globl sym_1_1656
+sym_1_1656: la $2, sym_1_1656
+.globl sym_1_1657
+sym_1_1657: la $2, sym_1_1657
+.globl sym_1_1658
+sym_1_1658: la $2, sym_1_1658
+.globl sym_1_1659
+sym_1_1659: la $2, sym_1_1659
+.globl sym_1_1660
+sym_1_1660: la $2, sym_1_1660
+.globl sym_1_1661
+sym_1_1661: la $2, sym_1_1661
+.globl sym_1_1662
+sym_1_1662: la $2, sym_1_1662
+.globl sym_1_1663
+sym_1_1663: la $2, sym_1_1663
+.globl sym_1_1664
+sym_1_1664: la $2, sym_1_1664
+.globl sym_1_1665
+sym_1_1665: la $2, sym_1_1665
+.globl sym_1_1666
+sym_1_1666: la $2, sym_1_1666
+.globl sym_1_1667
+sym_1_1667: la $2, sym_1_1667
+.globl sym_1_1668
+sym_1_1668: la $2, sym_1_1668
+.globl sym_1_1669
+sym_1_1669: la $2, sym_1_1669
+.globl sym_1_1670
+sym_1_1670: la $2, sym_1_1670
+.globl sym_1_1671
+sym_1_1671: la $2, sym_1_1671
+.globl sym_1_1672
+sym_1_1672: la $2, sym_1_1672
+.globl sym_1_1673
+sym_1_1673: la $2, sym_1_1673
+.globl sym_1_1674
+sym_1_1674: la $2, sym_1_1674
+.globl sym_1_1675
+sym_1_1675: la $2, sym_1_1675
+.globl sym_1_1676
+sym_1_1676: la $2, sym_1_1676
+.globl sym_1_1677
+sym_1_1677: la $2, sym_1_1677
+.globl sym_1_1678
+sym_1_1678: la $2, sym_1_1678
+.globl sym_1_1679
+sym_1_1679: la $2, sym_1_1679
+.globl sym_1_1680
+sym_1_1680: la $2, sym_1_1680
+.globl sym_1_1681
+sym_1_1681: la $2, sym_1_1681
+.globl sym_1_1682
+sym_1_1682: la $2, sym_1_1682
+.globl sym_1_1683
+sym_1_1683: la $2, sym_1_1683
+.globl sym_1_1684
+sym_1_1684: la $2, sym_1_1684
+.globl sym_1_1685
+sym_1_1685: la $2, sym_1_1685
+.globl sym_1_1686
+sym_1_1686: la $2, sym_1_1686
+.globl sym_1_1687
+sym_1_1687: la $2, sym_1_1687
+.globl sym_1_1688
+sym_1_1688: la $2, sym_1_1688
+.globl sym_1_1689
+sym_1_1689: la $2, sym_1_1689
+.globl sym_1_1690
+sym_1_1690: la $2, sym_1_1690
+.globl sym_1_1691
+sym_1_1691: la $2, sym_1_1691
+.globl sym_1_1692
+sym_1_1692: la $2, sym_1_1692
+.globl sym_1_1693
+sym_1_1693: la $2, sym_1_1693
+.globl sym_1_1694
+sym_1_1694: la $2, sym_1_1694
+.globl sym_1_1695
+sym_1_1695: la $2, sym_1_1695
+.globl sym_1_1696
+sym_1_1696: la $2, sym_1_1696
+.globl sym_1_1697
+sym_1_1697: la $2, sym_1_1697
+.globl sym_1_1698
+sym_1_1698: la $2, sym_1_1698
+.globl sym_1_1699
+sym_1_1699: la $2, sym_1_1699
+.globl sym_1_1700
+sym_1_1700: la $2, sym_1_1700
+.globl sym_1_1701
+sym_1_1701: la $2, sym_1_1701
+.globl sym_1_1702
+sym_1_1702: la $2, sym_1_1702
+.globl sym_1_1703
+sym_1_1703: la $2, sym_1_1703
+.globl sym_1_1704
+sym_1_1704: la $2, sym_1_1704
+.globl sym_1_1705
+sym_1_1705: la $2, sym_1_1705
+.globl sym_1_1706
+sym_1_1706: la $2, sym_1_1706
+.globl sym_1_1707
+sym_1_1707: la $2, sym_1_1707
+.globl sym_1_1708
+sym_1_1708: la $2, sym_1_1708
+.globl sym_1_1709
+sym_1_1709: la $2, sym_1_1709
+.globl sym_1_1710
+sym_1_1710: la $2, sym_1_1710
+.globl sym_1_1711
+sym_1_1711: la $2, sym_1_1711
+.globl sym_1_1712
+sym_1_1712: la $2, sym_1_1712
+.globl sym_1_1713
+sym_1_1713: la $2, sym_1_1713
+.globl sym_1_1714
+sym_1_1714: la $2, sym_1_1714
+.globl sym_1_1715
+sym_1_1715: la $2, sym_1_1715
+.globl sym_1_1716
+sym_1_1716: la $2, sym_1_1716
+.globl sym_1_1717
+sym_1_1717: la $2, sym_1_1717
+.globl sym_1_1718
+sym_1_1718: la $2, sym_1_1718
+.globl sym_1_1719
+sym_1_1719: la $2, sym_1_1719
+.globl sym_1_1720
+sym_1_1720: la $2, sym_1_1720
+.globl sym_1_1721
+sym_1_1721: la $2, sym_1_1721
+.globl sym_1_1722
+sym_1_1722: la $2, sym_1_1722
+.globl sym_1_1723
+sym_1_1723: la $2, sym_1_1723
+.globl sym_1_1724
+sym_1_1724: la $2, sym_1_1724
+.globl sym_1_1725
+sym_1_1725: la $2, sym_1_1725
+.globl sym_1_1726
+sym_1_1726: la $2, sym_1_1726
+.globl sym_1_1727
+sym_1_1727: la $2, sym_1_1727
+.globl sym_1_1728
+sym_1_1728: la $2, sym_1_1728
+.globl sym_1_1729
+sym_1_1729: la $2, sym_1_1729
+.globl sym_1_1730
+sym_1_1730: la $2, sym_1_1730
+.globl sym_1_1731
+sym_1_1731: la $2, sym_1_1731
+.globl sym_1_1732
+sym_1_1732: la $2, sym_1_1732
+.globl sym_1_1733
+sym_1_1733: la $2, sym_1_1733
+.globl sym_1_1734
+sym_1_1734: la $2, sym_1_1734
+.globl sym_1_1735
+sym_1_1735: la $2, sym_1_1735
+.globl sym_1_1736
+sym_1_1736: la $2, sym_1_1736
+.globl sym_1_1737
+sym_1_1737: la $2, sym_1_1737
+.globl sym_1_1738
+sym_1_1738: la $2, sym_1_1738
+.globl sym_1_1739
+sym_1_1739: la $2, sym_1_1739
+.globl sym_1_1740
+sym_1_1740: la $2, sym_1_1740
+.globl sym_1_1741
+sym_1_1741: la $2, sym_1_1741
+.globl sym_1_1742
+sym_1_1742: la $2, sym_1_1742
+.globl sym_1_1743
+sym_1_1743: la $2, sym_1_1743
+.globl sym_1_1744
+sym_1_1744: la $2, sym_1_1744
+.globl sym_1_1745
+sym_1_1745: la $2, sym_1_1745
+.globl sym_1_1746
+sym_1_1746: la $2, sym_1_1746
+.globl sym_1_1747
+sym_1_1747: la $2, sym_1_1747
+.globl sym_1_1748
+sym_1_1748: la $2, sym_1_1748
+.globl sym_1_1749
+sym_1_1749: la $2, sym_1_1749
+.globl sym_1_1750
+sym_1_1750: la $2, sym_1_1750
+.globl sym_1_1751
+sym_1_1751: la $2, sym_1_1751
+.globl sym_1_1752
+sym_1_1752: la $2, sym_1_1752
+.globl sym_1_1753
+sym_1_1753: la $2, sym_1_1753
+.globl sym_1_1754
+sym_1_1754: la $2, sym_1_1754
+.globl sym_1_1755
+sym_1_1755: la $2, sym_1_1755
+.globl sym_1_1756
+sym_1_1756: la $2, sym_1_1756
+.globl sym_1_1757
+sym_1_1757: la $2, sym_1_1757
+.globl sym_1_1758
+sym_1_1758: la $2, sym_1_1758
+.globl sym_1_1759
+sym_1_1759: la $2, sym_1_1759
+.globl sym_1_1760
+sym_1_1760: la $2, sym_1_1760
+.globl sym_1_1761
+sym_1_1761: la $2, sym_1_1761
+.globl sym_1_1762
+sym_1_1762: la $2, sym_1_1762
+.globl sym_1_1763
+sym_1_1763: la $2, sym_1_1763
+.globl sym_1_1764
+sym_1_1764: la $2, sym_1_1764
+.globl sym_1_1765
+sym_1_1765: la $2, sym_1_1765
+.globl sym_1_1766
+sym_1_1766: la $2, sym_1_1766
+.globl sym_1_1767
+sym_1_1767: la $2, sym_1_1767
+.globl sym_1_1768
+sym_1_1768: la $2, sym_1_1768
+.globl sym_1_1769
+sym_1_1769: la $2, sym_1_1769
+.globl sym_1_1770
+sym_1_1770: la $2, sym_1_1770
+.globl sym_1_1771
+sym_1_1771: la $2, sym_1_1771
+.globl sym_1_1772
+sym_1_1772: la $2, sym_1_1772
+.globl sym_1_1773
+sym_1_1773: la $2, sym_1_1773
+.globl sym_1_1774
+sym_1_1774: la $2, sym_1_1774
+.globl sym_1_1775
+sym_1_1775: la $2, sym_1_1775
+.globl sym_1_1776
+sym_1_1776: la $2, sym_1_1776
+.globl sym_1_1777
+sym_1_1777: la $2, sym_1_1777
+.globl sym_1_1778
+sym_1_1778: la $2, sym_1_1778
+.globl sym_1_1779
+sym_1_1779: la $2, sym_1_1779
+.globl sym_1_1780
+sym_1_1780: la $2, sym_1_1780
+.globl sym_1_1781
+sym_1_1781: la $2, sym_1_1781
+.globl sym_1_1782
+sym_1_1782: la $2, sym_1_1782
+.globl sym_1_1783
+sym_1_1783: la $2, sym_1_1783
+.globl sym_1_1784
+sym_1_1784: la $2, sym_1_1784
+.globl sym_1_1785
+sym_1_1785: la $2, sym_1_1785
+.globl sym_1_1786
+sym_1_1786: la $2, sym_1_1786
+.globl sym_1_1787
+sym_1_1787: la $2, sym_1_1787
+.globl sym_1_1788
+sym_1_1788: la $2, sym_1_1788
+.globl sym_1_1789
+sym_1_1789: la $2, sym_1_1789
+.globl sym_1_1790
+sym_1_1790: la $2, sym_1_1790
+.globl sym_1_1791
+sym_1_1791: la $2, sym_1_1791
+.globl sym_1_1792
+sym_1_1792: la $2, sym_1_1792
+.globl sym_1_1793
+sym_1_1793: la $2, sym_1_1793
+.globl sym_1_1794
+sym_1_1794: la $2, sym_1_1794
+.globl sym_1_1795
+sym_1_1795: la $2, sym_1_1795
+.globl sym_1_1796
+sym_1_1796: la $2, sym_1_1796
+.globl sym_1_1797
+sym_1_1797: la $2, sym_1_1797
+.globl sym_1_1798
+sym_1_1798: la $2, sym_1_1798
+.globl sym_1_1799
+sym_1_1799: la $2, sym_1_1799
+.globl sym_1_1800
+sym_1_1800: la $2, sym_1_1800
+.globl sym_1_1801
+sym_1_1801: la $2, sym_1_1801
+.globl sym_1_1802
+sym_1_1802: la $2, sym_1_1802
+.globl sym_1_1803
+sym_1_1803: la $2, sym_1_1803
+.globl sym_1_1804
+sym_1_1804: la $2, sym_1_1804
+.globl sym_1_1805
+sym_1_1805: la $2, sym_1_1805
+.globl sym_1_1806
+sym_1_1806: la $2, sym_1_1806
+.globl sym_1_1807
+sym_1_1807: la $2, sym_1_1807
+.globl sym_1_1808
+sym_1_1808: la $2, sym_1_1808
+.globl sym_1_1809
+sym_1_1809: la $2, sym_1_1809
+.globl sym_1_1810
+sym_1_1810: la $2, sym_1_1810
+.globl sym_1_1811
+sym_1_1811: la $2, sym_1_1811
+.globl sym_1_1812
+sym_1_1812: la $2, sym_1_1812
+.globl sym_1_1813
+sym_1_1813: la $2, sym_1_1813
+.globl sym_1_1814
+sym_1_1814: la $2, sym_1_1814
+.globl sym_1_1815
+sym_1_1815: la $2, sym_1_1815
+.globl sym_1_1816
+sym_1_1816: la $2, sym_1_1816
+.globl sym_1_1817
+sym_1_1817: la $2, sym_1_1817
+.globl sym_1_1818
+sym_1_1818: la $2, sym_1_1818
+.globl sym_1_1819
+sym_1_1819: la $2, sym_1_1819
+.globl sym_1_1820
+sym_1_1820: la $2, sym_1_1820
+.globl sym_1_1821
+sym_1_1821: la $2, sym_1_1821
+.globl sym_1_1822
+sym_1_1822: la $2, sym_1_1822
+.globl sym_1_1823
+sym_1_1823: la $2, sym_1_1823
+.globl sym_1_1824
+sym_1_1824: la $2, sym_1_1824
+.globl sym_1_1825
+sym_1_1825: la $2, sym_1_1825
+.globl sym_1_1826
+sym_1_1826: la $2, sym_1_1826
+.globl sym_1_1827
+sym_1_1827: la $2, sym_1_1827
+.globl sym_1_1828
+sym_1_1828: la $2, sym_1_1828
+.globl sym_1_1829
+sym_1_1829: la $2, sym_1_1829
+.globl sym_1_1830
+sym_1_1830: la $2, sym_1_1830
+.globl sym_1_1831
+sym_1_1831: la $2, sym_1_1831
+.globl sym_1_1832
+sym_1_1832: la $2, sym_1_1832
+.globl sym_1_1833
+sym_1_1833: la $2, sym_1_1833
+.globl sym_1_1834
+sym_1_1834: la $2, sym_1_1834
+.globl sym_1_1835
+sym_1_1835: la $2, sym_1_1835
+.globl sym_1_1836
+sym_1_1836: la $2, sym_1_1836
+.globl sym_1_1837
+sym_1_1837: la $2, sym_1_1837
+.globl sym_1_1838
+sym_1_1838: la $2, sym_1_1838
+.globl sym_1_1839
+sym_1_1839: la $2, sym_1_1839
+.globl sym_1_1840
+sym_1_1840: la $2, sym_1_1840
+.globl sym_1_1841
+sym_1_1841: la $2, sym_1_1841
+.globl sym_1_1842
+sym_1_1842: la $2, sym_1_1842
+.globl sym_1_1843
+sym_1_1843: la $2, sym_1_1843
+.globl sym_1_1844
+sym_1_1844: la $2, sym_1_1844
+.globl sym_1_1845
+sym_1_1845: la $2, sym_1_1845
+.globl sym_1_1846
+sym_1_1846: la $2, sym_1_1846
+.globl sym_1_1847
+sym_1_1847: la $2, sym_1_1847
+.globl sym_1_1848
+sym_1_1848: la $2, sym_1_1848
+.globl sym_1_1849
+sym_1_1849: la $2, sym_1_1849
+.globl sym_1_1850
+sym_1_1850: la $2, sym_1_1850
+.globl sym_1_1851
+sym_1_1851: la $2, sym_1_1851
+.globl sym_1_1852
+sym_1_1852: la $2, sym_1_1852
+.globl sym_1_1853
+sym_1_1853: la $2, sym_1_1853
+.globl sym_1_1854
+sym_1_1854: la $2, sym_1_1854
+.globl sym_1_1855
+sym_1_1855: la $2, sym_1_1855
+.globl sym_1_1856
+sym_1_1856: la $2, sym_1_1856
+.globl sym_1_1857
+sym_1_1857: la $2, sym_1_1857
+.globl sym_1_1858
+sym_1_1858: la $2, sym_1_1858
+.globl sym_1_1859
+sym_1_1859: la $2, sym_1_1859
+.globl sym_1_1860
+sym_1_1860: la $2, sym_1_1860
+.globl sym_1_1861
+sym_1_1861: la $2, sym_1_1861
+.globl sym_1_1862
+sym_1_1862: la $2, sym_1_1862
+.globl sym_1_1863
+sym_1_1863: la $2, sym_1_1863
+.globl sym_1_1864
+sym_1_1864: la $2, sym_1_1864
+.globl sym_1_1865
+sym_1_1865: la $2, sym_1_1865
+.globl sym_1_1866
+sym_1_1866: la $2, sym_1_1866
+.globl sym_1_1867
+sym_1_1867: la $2, sym_1_1867
+.globl sym_1_1868
+sym_1_1868: la $2, sym_1_1868
+.globl sym_1_1869
+sym_1_1869: la $2, sym_1_1869
+.globl sym_1_1870
+sym_1_1870: la $2, sym_1_1870
+.globl sym_1_1871
+sym_1_1871: la $2, sym_1_1871
+.globl sym_1_1872
+sym_1_1872: la $2, sym_1_1872
+.globl sym_1_1873
+sym_1_1873: la $2, sym_1_1873
+.globl sym_1_1874
+sym_1_1874: la $2, sym_1_1874
+.globl sym_1_1875
+sym_1_1875: la $2, sym_1_1875
+.globl sym_1_1876
+sym_1_1876: la $2, sym_1_1876
+.globl sym_1_1877
+sym_1_1877: la $2, sym_1_1877
+.globl sym_1_1878
+sym_1_1878: la $2, sym_1_1878
+.globl sym_1_1879
+sym_1_1879: la $2, sym_1_1879
+.globl sym_1_1880
+sym_1_1880: la $2, sym_1_1880
+.globl sym_1_1881
+sym_1_1881: la $2, sym_1_1881
+.globl sym_1_1882
+sym_1_1882: la $2, sym_1_1882
+.globl sym_1_1883
+sym_1_1883: la $2, sym_1_1883
+.globl sym_1_1884
+sym_1_1884: la $2, sym_1_1884
+.globl sym_1_1885
+sym_1_1885: la $2, sym_1_1885
+.globl sym_1_1886
+sym_1_1886: la $2, sym_1_1886
+.globl sym_1_1887
+sym_1_1887: la $2, sym_1_1887
+.globl sym_1_1888
+sym_1_1888: la $2, sym_1_1888
+.globl sym_1_1889
+sym_1_1889: la $2, sym_1_1889
+.globl sym_1_1890
+sym_1_1890: la $2, sym_1_1890
+.globl sym_1_1891
+sym_1_1891: la $2, sym_1_1891
+.globl sym_1_1892
+sym_1_1892: la $2, sym_1_1892
+.globl sym_1_1893
+sym_1_1893: la $2, sym_1_1893
+.globl sym_1_1894
+sym_1_1894: la $2, sym_1_1894
+.globl sym_1_1895
+sym_1_1895: la $2, sym_1_1895
+.globl sym_1_1896
+sym_1_1896: la $2, sym_1_1896
+.globl sym_1_1897
+sym_1_1897: la $2, sym_1_1897
+.globl sym_1_1898
+sym_1_1898: la $2, sym_1_1898
+.globl sym_1_1899
+sym_1_1899: la $2, sym_1_1899
+.globl sym_1_1900
+sym_1_1900: la $2, sym_1_1900
+.globl sym_1_1901
+sym_1_1901: la $2, sym_1_1901
+.globl sym_1_1902
+sym_1_1902: la $2, sym_1_1902
+.globl sym_1_1903
+sym_1_1903: la $2, sym_1_1903
+.globl sym_1_1904
+sym_1_1904: la $2, sym_1_1904
+.globl sym_1_1905
+sym_1_1905: la $2, sym_1_1905
+.globl sym_1_1906
+sym_1_1906: la $2, sym_1_1906
+.globl sym_1_1907
+sym_1_1907: la $2, sym_1_1907
+.globl sym_1_1908
+sym_1_1908: la $2, sym_1_1908
+.globl sym_1_1909
+sym_1_1909: la $2, sym_1_1909
+.globl sym_1_1910
+sym_1_1910: la $2, sym_1_1910
+.globl sym_1_1911
+sym_1_1911: la $2, sym_1_1911
+.globl sym_1_1912
+sym_1_1912: la $2, sym_1_1912
+.globl sym_1_1913
+sym_1_1913: la $2, sym_1_1913
+.globl sym_1_1914
+sym_1_1914: la $2, sym_1_1914
+.globl sym_1_1915
+sym_1_1915: la $2, sym_1_1915
+.globl sym_1_1916
+sym_1_1916: la $2, sym_1_1916
+.globl sym_1_1917
+sym_1_1917: la $2, sym_1_1917
+.globl sym_1_1918
+sym_1_1918: la $2, sym_1_1918
+.globl sym_1_1919
+sym_1_1919: la $2, sym_1_1919
+.globl sym_1_1920
+sym_1_1920: la $2, sym_1_1920
+.globl sym_1_1921
+sym_1_1921: la $2, sym_1_1921
+.globl sym_1_1922
+sym_1_1922: la $2, sym_1_1922
+.globl sym_1_1923
+sym_1_1923: la $2, sym_1_1923
+.globl sym_1_1924
+sym_1_1924: la $2, sym_1_1924
+.globl sym_1_1925
+sym_1_1925: la $2, sym_1_1925
+.globl sym_1_1926
+sym_1_1926: la $2, sym_1_1926
+.globl sym_1_1927
+sym_1_1927: la $2, sym_1_1927
+.globl sym_1_1928
+sym_1_1928: la $2, sym_1_1928
+.globl sym_1_1929
+sym_1_1929: la $2, sym_1_1929
+.globl sym_1_1930
+sym_1_1930: la $2, sym_1_1930
+.globl sym_1_1931
+sym_1_1931: la $2, sym_1_1931
+.globl sym_1_1932
+sym_1_1932: la $2, sym_1_1932
+.globl sym_1_1933
+sym_1_1933: la $2, sym_1_1933
+.globl sym_1_1934
+sym_1_1934: la $2, sym_1_1934
+.globl sym_1_1935
+sym_1_1935: la $2, sym_1_1935
+.globl sym_1_1936
+sym_1_1936: la $2, sym_1_1936
+.globl sym_1_1937
+sym_1_1937: la $2, sym_1_1937
+.globl sym_1_1938
+sym_1_1938: la $2, sym_1_1938
+.globl sym_1_1939
+sym_1_1939: la $2, sym_1_1939
+.globl sym_1_1940
+sym_1_1940: la $2, sym_1_1940
+.globl sym_1_1941
+sym_1_1941: la $2, sym_1_1941
+.globl sym_1_1942
+sym_1_1942: la $2, sym_1_1942
+.globl sym_1_1943
+sym_1_1943: la $2, sym_1_1943
+.globl sym_1_1944
+sym_1_1944: la $2, sym_1_1944
+.globl sym_1_1945
+sym_1_1945: la $2, sym_1_1945
+.globl sym_1_1946
+sym_1_1946: la $2, sym_1_1946
+.globl sym_1_1947
+sym_1_1947: la $2, sym_1_1947
+.globl sym_1_1948
+sym_1_1948: la $2, sym_1_1948
+.globl sym_1_1949
+sym_1_1949: la $2, sym_1_1949
+.globl sym_1_1950
+sym_1_1950: la $2, sym_1_1950
+.globl sym_1_1951
+sym_1_1951: la $2, sym_1_1951
+.globl sym_1_1952
+sym_1_1952: la $2, sym_1_1952
+.globl sym_1_1953
+sym_1_1953: la $2, sym_1_1953
+.globl sym_1_1954
+sym_1_1954: la $2, sym_1_1954
+.globl sym_1_1955
+sym_1_1955: la $2, sym_1_1955
+.globl sym_1_1956
+sym_1_1956: la $2, sym_1_1956
+.globl sym_1_1957
+sym_1_1957: la $2, sym_1_1957
+.globl sym_1_1958
+sym_1_1958: la $2, sym_1_1958
+.globl sym_1_1959
+sym_1_1959: la $2, sym_1_1959
+.globl sym_1_1960
+sym_1_1960: la $2, sym_1_1960
+.globl sym_1_1961
+sym_1_1961: la $2, sym_1_1961
+.globl sym_1_1962
+sym_1_1962: la $2, sym_1_1962
+.globl sym_1_1963
+sym_1_1963: la $2, sym_1_1963
+.globl sym_1_1964
+sym_1_1964: la $2, sym_1_1964
+.globl sym_1_1965
+sym_1_1965: la $2, sym_1_1965
+.globl sym_1_1966
+sym_1_1966: la $2, sym_1_1966
+.globl sym_1_1967
+sym_1_1967: la $2, sym_1_1967
+.globl sym_1_1968
+sym_1_1968: la $2, sym_1_1968
+.globl sym_1_1969
+sym_1_1969: la $2, sym_1_1969
+.globl sym_1_1970
+sym_1_1970: la $2, sym_1_1970
+.globl sym_1_1971
+sym_1_1971: la $2, sym_1_1971
+.globl sym_1_1972
+sym_1_1972: la $2, sym_1_1972
+.globl sym_1_1973
+sym_1_1973: la $2, sym_1_1973
+.globl sym_1_1974
+sym_1_1974: la $2, sym_1_1974
+.globl sym_1_1975
+sym_1_1975: la $2, sym_1_1975
+.globl sym_1_1976
+sym_1_1976: la $2, sym_1_1976
+.globl sym_1_1977
+sym_1_1977: la $2, sym_1_1977
+.globl sym_1_1978
+sym_1_1978: la $2, sym_1_1978
+.globl sym_1_1979
+sym_1_1979: la $2, sym_1_1979
+.globl sym_1_1980
+sym_1_1980: la $2, sym_1_1980
+.globl sym_1_1981
+sym_1_1981: la $2, sym_1_1981
+.globl sym_1_1982
+sym_1_1982: la $2, sym_1_1982
+.globl sym_1_1983
+sym_1_1983: la $2, sym_1_1983
+.globl sym_1_1984
+sym_1_1984: la $2, sym_1_1984
+.globl sym_1_1985
+sym_1_1985: la $2, sym_1_1985
+.globl sym_1_1986
+sym_1_1986: la $2, sym_1_1986
+.globl sym_1_1987
+sym_1_1987: la $2, sym_1_1987
+.globl sym_1_1988
+sym_1_1988: la $2, sym_1_1988
+.globl sym_1_1989
+sym_1_1989: la $2, sym_1_1989
+.globl sym_1_1990
+sym_1_1990: la $2, sym_1_1990
+.globl sym_1_1991
+sym_1_1991: la $2, sym_1_1991
+.globl sym_1_1992
+sym_1_1992: la $2, sym_1_1992
+.globl sym_1_1993
+sym_1_1993: la $2, sym_1_1993
+.globl sym_1_1994
+sym_1_1994: la $2, sym_1_1994
+.globl sym_1_1995
+sym_1_1995: la $2, sym_1_1995
+.globl sym_1_1996
+sym_1_1996: la $2, sym_1_1996
+.globl sym_1_1997
+sym_1_1997: la $2, sym_1_1997
+.globl sym_1_1998
+sym_1_1998: la $2, sym_1_1998
+.globl sym_1_1999
+sym_1_1999: la $2, sym_1_1999
+.globl sym_1_2000
+sym_1_2000: la $2, sym_1_2000
+.globl sym_1_2001
+sym_1_2001: la $2, sym_1_2001
+.globl sym_1_2002
+sym_1_2002: la $2, sym_1_2002
+.globl sym_1_2003
+sym_1_2003: la $2, sym_1_2003
+.globl sym_1_2004
+sym_1_2004: la $2, sym_1_2004
+.globl sym_1_2005
+sym_1_2005: la $2, sym_1_2005
+.globl sym_1_2006
+sym_1_2006: la $2, sym_1_2006
+.globl sym_1_2007
+sym_1_2007: la $2, sym_1_2007
+.globl sym_1_2008
+sym_1_2008: la $2, sym_1_2008
+.globl sym_1_2009
+sym_1_2009: la $2, sym_1_2009
+.globl sym_1_2010
+sym_1_2010: la $2, sym_1_2010
+.globl sym_1_2011
+sym_1_2011: la $2, sym_1_2011
+.globl sym_1_2012
+sym_1_2012: la $2, sym_1_2012
+.globl sym_1_2013
+sym_1_2013: la $2, sym_1_2013
+.globl sym_1_2014
+sym_1_2014: la $2, sym_1_2014
+.globl sym_1_2015
+sym_1_2015: la $2, sym_1_2015
+.globl sym_1_2016
+sym_1_2016: la $2, sym_1_2016
+.globl sym_1_2017
+sym_1_2017: la $2, sym_1_2017
+.globl sym_1_2018
+sym_1_2018: la $2, sym_1_2018
+.globl sym_1_2019
+sym_1_2019: la $2, sym_1_2019
+.globl sym_1_2020
+sym_1_2020: la $2, sym_1_2020
+.globl sym_1_2021
+sym_1_2021: la $2, sym_1_2021
+.globl sym_1_2022
+sym_1_2022: la $2, sym_1_2022
+.globl sym_1_2023
+sym_1_2023: la $2, sym_1_2023
+.globl sym_1_2024
+sym_1_2024: la $2, sym_1_2024
+.globl sym_1_2025
+sym_1_2025: la $2, sym_1_2025
+.globl sym_1_2026
+sym_1_2026: la $2, sym_1_2026
+.globl sym_1_2027
+sym_1_2027: la $2, sym_1_2027
+.globl sym_1_2028
+sym_1_2028: la $2, sym_1_2028
+.globl sym_1_2029
+sym_1_2029: la $2, sym_1_2029
+.globl sym_1_2030
+sym_1_2030: la $2, sym_1_2030
+.globl sym_1_2031
+sym_1_2031: la $2, sym_1_2031
+.globl sym_1_2032
+sym_1_2032: la $2, sym_1_2032
+.globl sym_1_2033
+sym_1_2033: la $2, sym_1_2033
+.globl sym_1_2034
+sym_1_2034: la $2, sym_1_2034
+.globl sym_1_2035
+sym_1_2035: la $2, sym_1_2035
+.globl sym_1_2036
+sym_1_2036: la $2, sym_1_2036
+.globl sym_1_2037
+sym_1_2037: la $2, sym_1_2037
+.globl sym_1_2038
+sym_1_2038: la $2, sym_1_2038
+.globl sym_1_2039
+sym_1_2039: la $2, sym_1_2039
+.globl sym_1_2040
+sym_1_2040: la $2, sym_1_2040
+.globl sym_1_2041
+sym_1_2041: la $2, sym_1_2041
+.globl sym_1_2042
+sym_1_2042: la $2, sym_1_2042
+.globl sym_1_2043
+sym_1_2043: la $2, sym_1_2043
+.globl sym_1_2044
+sym_1_2044: la $2, sym_1_2044
+.globl sym_1_2045
+sym_1_2045: la $2, sym_1_2045
+.globl sym_1_2046
+sym_1_2046: la $2, sym_1_2046
+.globl sym_1_2047
+sym_1_2047: la $2, sym_1_2047
+.globl sym_1_2048
+sym_1_2048: la $2, sym_1_2048
+.globl sym_1_2049
+sym_1_2049: la $2, sym_1_2049
+.globl sym_1_2050
+sym_1_2050: la $2, sym_1_2050
+.globl sym_1_2051
+sym_1_2051: la $2, sym_1_2051
+.globl sym_1_2052
+sym_1_2052: la $2, sym_1_2052
+.globl sym_1_2053
+sym_1_2053: la $2, sym_1_2053
+.globl sym_1_2054
+sym_1_2054: la $2, sym_1_2054
+.globl sym_1_2055
+sym_1_2055: la $2, sym_1_2055
+.globl sym_1_2056
+sym_1_2056: la $2, sym_1_2056
+.globl sym_1_2057
+sym_1_2057: la $2, sym_1_2057
+.globl sym_1_2058
+sym_1_2058: la $2, sym_1_2058
+.globl sym_1_2059
+sym_1_2059: la $2, sym_1_2059
+.globl sym_1_2060
+sym_1_2060: la $2, sym_1_2060
+.globl sym_1_2061
+sym_1_2061: la $2, sym_1_2061
+.globl sym_1_2062
+sym_1_2062: la $2, sym_1_2062
+.globl sym_1_2063
+sym_1_2063: la $2, sym_1_2063
+.globl sym_1_2064
+sym_1_2064: la $2, sym_1_2064
+.globl sym_1_2065
+sym_1_2065: la $2, sym_1_2065
+.globl sym_1_2066
+sym_1_2066: la $2, sym_1_2066
+.globl sym_1_2067
+sym_1_2067: la $2, sym_1_2067
+.globl sym_1_2068
+sym_1_2068: la $2, sym_1_2068
+.globl sym_1_2069
+sym_1_2069: la $2, sym_1_2069
+.globl sym_1_2070
+sym_1_2070: la $2, sym_1_2070
+.globl sym_1_2071
+sym_1_2071: la $2, sym_1_2071
+.globl sym_1_2072
+sym_1_2072: la $2, sym_1_2072
+.globl sym_1_2073
+sym_1_2073: la $2, sym_1_2073
+.globl sym_1_2074
+sym_1_2074: la $2, sym_1_2074
+.globl sym_1_2075
+sym_1_2075: la $2, sym_1_2075
+.globl sym_1_2076
+sym_1_2076: la $2, sym_1_2076
+.globl sym_1_2077
+sym_1_2077: la $2, sym_1_2077
+.globl sym_1_2078
+sym_1_2078: la $2, sym_1_2078
+.globl sym_1_2079
+sym_1_2079: la $2, sym_1_2079
+.globl sym_1_2080
+sym_1_2080: la $2, sym_1_2080
+.globl sym_1_2081
+sym_1_2081: la $2, sym_1_2081
+.globl sym_1_2082
+sym_1_2082: la $2, sym_1_2082
+.globl sym_1_2083
+sym_1_2083: la $2, sym_1_2083
+.globl sym_1_2084
+sym_1_2084: la $2, sym_1_2084
+.globl sym_1_2085
+sym_1_2085: la $2, sym_1_2085
+.globl sym_1_2086
+sym_1_2086: la $2, sym_1_2086
+.globl sym_1_2087
+sym_1_2087: la $2, sym_1_2087
+.globl sym_1_2088
+sym_1_2088: la $2, sym_1_2088
+.globl sym_1_2089
+sym_1_2089: la $2, sym_1_2089
+.globl sym_1_2090
+sym_1_2090: la $2, sym_1_2090
+.globl sym_1_2091
+sym_1_2091: la $2, sym_1_2091
+.globl sym_1_2092
+sym_1_2092: la $2, sym_1_2092
+.globl sym_1_2093
+sym_1_2093: la $2, sym_1_2093
+.globl sym_1_2094
+sym_1_2094: la $2, sym_1_2094
+.globl sym_1_2095
+sym_1_2095: la $2, sym_1_2095
+.globl sym_1_2096
+sym_1_2096: la $2, sym_1_2096
+.globl sym_1_2097
+sym_1_2097: la $2, sym_1_2097
+.globl sym_1_2098
+sym_1_2098: la $2, sym_1_2098
+.globl sym_1_2099
+sym_1_2099: la $2, sym_1_2099
+.globl sym_1_2100
+sym_1_2100: la $2, sym_1_2100
+.globl sym_1_2101
+sym_1_2101: la $2, sym_1_2101
+.globl sym_1_2102
+sym_1_2102: la $2, sym_1_2102
+.globl sym_1_2103
+sym_1_2103: la $2, sym_1_2103
+.globl sym_1_2104
+sym_1_2104: la $2, sym_1_2104
+.globl sym_1_2105
+sym_1_2105: la $2, sym_1_2105
+.globl sym_1_2106
+sym_1_2106: la $2, sym_1_2106
+.globl sym_1_2107
+sym_1_2107: la $2, sym_1_2107
+.globl sym_1_2108
+sym_1_2108: la $2, sym_1_2108
+.globl sym_1_2109
+sym_1_2109: la $2, sym_1_2109
+.globl sym_1_2110
+sym_1_2110: la $2, sym_1_2110
+.globl sym_1_2111
+sym_1_2111: la $2, sym_1_2111
+.globl sym_1_2112
+sym_1_2112: la $2, sym_1_2112
+.globl sym_1_2113
+sym_1_2113: la $2, sym_1_2113
+.globl sym_1_2114
+sym_1_2114: la $2, sym_1_2114
+.globl sym_1_2115
+sym_1_2115: la $2, sym_1_2115
+.globl sym_1_2116
+sym_1_2116: la $2, sym_1_2116
+.globl sym_1_2117
+sym_1_2117: la $2, sym_1_2117
+.globl sym_1_2118
+sym_1_2118: la $2, sym_1_2118
+.globl sym_1_2119
+sym_1_2119: la $2, sym_1_2119
+.globl sym_1_2120
+sym_1_2120: la $2, sym_1_2120
+.globl sym_1_2121
+sym_1_2121: la $2, sym_1_2121
+.globl sym_1_2122
+sym_1_2122: la $2, sym_1_2122
+.globl sym_1_2123
+sym_1_2123: la $2, sym_1_2123
+.globl sym_1_2124
+sym_1_2124: la $2, sym_1_2124
+.globl sym_1_2125
+sym_1_2125: la $2, sym_1_2125
+.globl sym_1_2126
+sym_1_2126: la $2, sym_1_2126
+.globl sym_1_2127
+sym_1_2127: la $2, sym_1_2127
+.globl sym_1_2128
+sym_1_2128: la $2, sym_1_2128
+.globl sym_1_2129
+sym_1_2129: la $2, sym_1_2129
+.globl sym_1_2130
+sym_1_2130: la $2, sym_1_2130
+.globl sym_1_2131
+sym_1_2131: la $2, sym_1_2131
+.globl sym_1_2132
+sym_1_2132: la $2, sym_1_2132
+.globl sym_1_2133
+sym_1_2133: la $2, sym_1_2133
+.globl sym_1_2134
+sym_1_2134: la $2, sym_1_2134
+.globl sym_1_2135
+sym_1_2135: la $2, sym_1_2135
+.globl sym_1_2136
+sym_1_2136: la $2, sym_1_2136
+.globl sym_1_2137
+sym_1_2137: la $2, sym_1_2137
+.globl sym_1_2138
+sym_1_2138: la $2, sym_1_2138
+.globl sym_1_2139
+sym_1_2139: la $2, sym_1_2139
+.globl sym_1_2140
+sym_1_2140: la $2, sym_1_2140
+.globl sym_1_2141
+sym_1_2141: la $2, sym_1_2141
+.globl sym_1_2142
+sym_1_2142: la $2, sym_1_2142
+.globl sym_1_2143
+sym_1_2143: la $2, sym_1_2143
+.globl sym_1_2144
+sym_1_2144: la $2, sym_1_2144
+.globl sym_1_2145
+sym_1_2145: la $2, sym_1_2145
+.globl sym_1_2146
+sym_1_2146: la $2, sym_1_2146
+.globl sym_1_2147
+sym_1_2147: la $2, sym_1_2147
+.globl sym_1_2148
+sym_1_2148: la $2, sym_1_2148
+.globl sym_1_2149
+sym_1_2149: la $2, sym_1_2149
+.globl sym_1_2150
+sym_1_2150: la $2, sym_1_2150
+.globl sym_1_2151
+sym_1_2151: la $2, sym_1_2151
+.globl sym_1_2152
+sym_1_2152: la $2, sym_1_2152
+.globl sym_1_2153
+sym_1_2153: la $2, sym_1_2153
+.globl sym_1_2154
+sym_1_2154: la $2, sym_1_2154
+.globl sym_1_2155
+sym_1_2155: la $2, sym_1_2155
+.globl sym_1_2156
+sym_1_2156: la $2, sym_1_2156
+.globl sym_1_2157
+sym_1_2157: la $2, sym_1_2157
+.globl sym_1_2158
+sym_1_2158: la $2, sym_1_2158
+.globl sym_1_2159
+sym_1_2159: la $2, sym_1_2159
+.globl sym_1_2160
+sym_1_2160: la $2, sym_1_2160
+.globl sym_1_2161
+sym_1_2161: la $2, sym_1_2161
+.globl sym_1_2162
+sym_1_2162: la $2, sym_1_2162
+.globl sym_1_2163
+sym_1_2163: la $2, sym_1_2163
+.globl sym_1_2164
+sym_1_2164: la $2, sym_1_2164
+.globl sym_1_2165
+sym_1_2165: la $2, sym_1_2165
+.globl sym_1_2166
+sym_1_2166: la $2, sym_1_2166
+.globl sym_1_2167
+sym_1_2167: la $2, sym_1_2167
+.globl sym_1_2168
+sym_1_2168: la $2, sym_1_2168
+.globl sym_1_2169
+sym_1_2169: la $2, sym_1_2169
+.globl sym_1_2170
+sym_1_2170: la $2, sym_1_2170
+.globl sym_1_2171
+sym_1_2171: la $2, sym_1_2171
+.globl sym_1_2172
+sym_1_2172: la $2, sym_1_2172
+.globl sym_1_2173
+sym_1_2173: la $2, sym_1_2173
+.globl sym_1_2174
+sym_1_2174: la $2, sym_1_2174
+.globl sym_1_2175
+sym_1_2175: la $2, sym_1_2175
+.globl sym_1_2176
+sym_1_2176: la $2, sym_1_2176
+.globl sym_1_2177
+sym_1_2177: la $2, sym_1_2177
+.globl sym_1_2178
+sym_1_2178: la $2, sym_1_2178
+.globl sym_1_2179
+sym_1_2179: la $2, sym_1_2179
+.globl sym_1_2180
+sym_1_2180: la $2, sym_1_2180
+.globl sym_1_2181
+sym_1_2181: la $2, sym_1_2181
+.globl sym_1_2182
+sym_1_2182: la $2, sym_1_2182
+.globl sym_1_2183
+sym_1_2183: la $2, sym_1_2183
+.globl sym_1_2184
+sym_1_2184: la $2, sym_1_2184
+.globl sym_1_2185
+sym_1_2185: la $2, sym_1_2185
+.globl sym_1_2186
+sym_1_2186: la $2, sym_1_2186
+.globl sym_1_2187
+sym_1_2187: la $2, sym_1_2187
+.globl sym_1_2188
+sym_1_2188: la $2, sym_1_2188
+.globl sym_1_2189
+sym_1_2189: la $2, sym_1_2189
+.globl sym_1_2190
+sym_1_2190: la $2, sym_1_2190
+.globl sym_1_2191
+sym_1_2191: la $2, sym_1_2191
+.globl sym_1_2192
+sym_1_2192: la $2, sym_1_2192
+.globl sym_1_2193
+sym_1_2193: la $2, sym_1_2193
+.globl sym_1_2194
+sym_1_2194: la $2, sym_1_2194
+.globl sym_1_2195
+sym_1_2195: la $2, sym_1_2195
+.globl sym_1_2196
+sym_1_2196: la $2, sym_1_2196
+.globl sym_1_2197
+sym_1_2197: la $2, sym_1_2197
+.globl sym_1_2198
+sym_1_2198: la $2, sym_1_2198
+.globl sym_1_2199
+sym_1_2199: la $2, sym_1_2199
+.globl sym_1_2200
+sym_1_2200: la $2, sym_1_2200
+.globl sym_1_2201
+sym_1_2201: la $2, sym_1_2201
+.globl sym_1_2202
+sym_1_2202: la $2, sym_1_2202
+.globl sym_1_2203
+sym_1_2203: la $2, sym_1_2203
+.globl sym_1_2204
+sym_1_2204: la $2, sym_1_2204
+.globl sym_1_2205
+sym_1_2205: la $2, sym_1_2205
+.globl sym_1_2206
+sym_1_2206: la $2, sym_1_2206
+.globl sym_1_2207
+sym_1_2207: la $2, sym_1_2207
+.globl sym_1_2208
+sym_1_2208: la $2, sym_1_2208
+.globl sym_1_2209
+sym_1_2209: la $2, sym_1_2209
+.globl sym_1_2210
+sym_1_2210: la $2, sym_1_2210
+.globl sym_1_2211
+sym_1_2211: la $2, sym_1_2211
+.globl sym_1_2212
+sym_1_2212: la $2, sym_1_2212
+.globl sym_1_2213
+sym_1_2213: la $2, sym_1_2213
+.globl sym_1_2214
+sym_1_2214: la $2, sym_1_2214
+.globl sym_1_2215
+sym_1_2215: la $2, sym_1_2215
+.globl sym_1_2216
+sym_1_2216: la $2, sym_1_2216
+.globl sym_1_2217
+sym_1_2217: la $2, sym_1_2217
+.globl sym_1_2218
+sym_1_2218: la $2, sym_1_2218
+.globl sym_1_2219
+sym_1_2219: la $2, sym_1_2219
+.globl sym_1_2220
+sym_1_2220: la $2, sym_1_2220
+.globl sym_1_2221
+sym_1_2221: la $2, sym_1_2221
+.globl sym_1_2222
+sym_1_2222: la $2, sym_1_2222
+.globl sym_1_2223
+sym_1_2223: la $2, sym_1_2223
+.globl sym_1_2224
+sym_1_2224: la $2, sym_1_2224
+.globl sym_1_2225
+sym_1_2225: la $2, sym_1_2225
+.globl sym_1_2226
+sym_1_2226: la $2, sym_1_2226
+.globl sym_1_2227
+sym_1_2227: la $2, sym_1_2227
+.globl sym_1_2228
+sym_1_2228: la $2, sym_1_2228
+.globl sym_1_2229
+sym_1_2229: la $2, sym_1_2229
+.globl sym_1_2230
+sym_1_2230: la $2, sym_1_2230
+.globl sym_1_2231
+sym_1_2231: la $2, sym_1_2231
+.globl sym_1_2232
+sym_1_2232: la $2, sym_1_2232
+.globl sym_1_2233
+sym_1_2233: la $2, sym_1_2233
+.globl sym_1_2234
+sym_1_2234: la $2, sym_1_2234
+.globl sym_1_2235
+sym_1_2235: la $2, sym_1_2235
+.globl sym_1_2236
+sym_1_2236: la $2, sym_1_2236
+.globl sym_1_2237
+sym_1_2237: la $2, sym_1_2237
+.globl sym_1_2238
+sym_1_2238: la $2, sym_1_2238
+.globl sym_1_2239
+sym_1_2239: la $2, sym_1_2239
+.globl sym_1_2240
+sym_1_2240: la $2, sym_1_2240
+.globl sym_1_2241
+sym_1_2241: la $2, sym_1_2241
+.globl sym_1_2242
+sym_1_2242: la $2, sym_1_2242
+.globl sym_1_2243
+sym_1_2243: la $2, sym_1_2243
+.globl sym_1_2244
+sym_1_2244: la $2, sym_1_2244
+.globl sym_1_2245
+sym_1_2245: la $2, sym_1_2245
+.globl sym_1_2246
+sym_1_2246: la $2, sym_1_2246
+.globl sym_1_2247
+sym_1_2247: la $2, sym_1_2247
+.globl sym_1_2248
+sym_1_2248: la $2, sym_1_2248
+.globl sym_1_2249
+sym_1_2249: la $2, sym_1_2249
+.globl sym_1_2250
+sym_1_2250: la $2, sym_1_2250
+.globl sym_1_2251
+sym_1_2251: la $2, sym_1_2251
+.globl sym_1_2252
+sym_1_2252: la $2, sym_1_2252
+.globl sym_1_2253
+sym_1_2253: la $2, sym_1_2253
+.globl sym_1_2254
+sym_1_2254: la $2, sym_1_2254
+.globl sym_1_2255
+sym_1_2255: la $2, sym_1_2255
+.globl sym_1_2256
+sym_1_2256: la $2, sym_1_2256
+.globl sym_1_2257
+sym_1_2257: la $2, sym_1_2257
+.globl sym_1_2258
+sym_1_2258: la $2, sym_1_2258
+.globl sym_1_2259
+sym_1_2259: la $2, sym_1_2259
+.globl sym_1_2260
+sym_1_2260: la $2, sym_1_2260
+.globl sym_1_2261
+sym_1_2261: la $2, sym_1_2261
+.globl sym_1_2262
+sym_1_2262: la $2, sym_1_2262
+.globl sym_1_2263
+sym_1_2263: la $2, sym_1_2263
+.globl sym_1_2264
+sym_1_2264: la $2, sym_1_2264
+.globl sym_1_2265
+sym_1_2265: la $2, sym_1_2265
+.globl sym_1_2266
+sym_1_2266: la $2, sym_1_2266
+.globl sym_1_2267
+sym_1_2267: la $2, sym_1_2267
+.globl sym_1_2268
+sym_1_2268: la $2, sym_1_2268
+.globl sym_1_2269
+sym_1_2269: la $2, sym_1_2269
+.globl sym_1_2270
+sym_1_2270: la $2, sym_1_2270
+.globl sym_1_2271
+sym_1_2271: la $2, sym_1_2271
+.globl sym_1_2272
+sym_1_2272: la $2, sym_1_2272
+.globl sym_1_2273
+sym_1_2273: la $2, sym_1_2273
+.globl sym_1_2274
+sym_1_2274: la $2, sym_1_2274
+.globl sym_1_2275
+sym_1_2275: la $2, sym_1_2275
+.globl sym_1_2276
+sym_1_2276: la $2, sym_1_2276
+.globl sym_1_2277
+sym_1_2277: la $2, sym_1_2277
+.globl sym_1_2278
+sym_1_2278: la $2, sym_1_2278
+.globl sym_1_2279
+sym_1_2279: la $2, sym_1_2279
+.globl sym_1_2280
+sym_1_2280: la $2, sym_1_2280
+.globl sym_1_2281
+sym_1_2281: la $2, sym_1_2281
+.globl sym_1_2282
+sym_1_2282: la $2, sym_1_2282
+.globl sym_1_2283
+sym_1_2283: la $2, sym_1_2283
+.globl sym_1_2284
+sym_1_2284: la $2, sym_1_2284
+.globl sym_1_2285
+sym_1_2285: la $2, sym_1_2285
+.globl sym_1_2286
+sym_1_2286: la $2, sym_1_2286
+.globl sym_1_2287
+sym_1_2287: la $2, sym_1_2287
+.globl sym_1_2288
+sym_1_2288: la $2, sym_1_2288
+.globl sym_1_2289
+sym_1_2289: la $2, sym_1_2289
+.globl sym_1_2290
+sym_1_2290: la $2, sym_1_2290
+.globl sym_1_2291
+sym_1_2291: la $2, sym_1_2291
+.globl sym_1_2292
+sym_1_2292: la $2, sym_1_2292
+.globl sym_1_2293
+sym_1_2293: la $2, sym_1_2293
+.globl sym_1_2294
+sym_1_2294: la $2, sym_1_2294
+.globl sym_1_2295
+sym_1_2295: la $2, sym_1_2295
+.globl sym_1_2296
+sym_1_2296: la $2, sym_1_2296
+.globl sym_1_2297
+sym_1_2297: la $2, sym_1_2297
+.globl sym_1_2298
+sym_1_2298: la $2, sym_1_2298
+.globl sym_1_2299
+sym_1_2299: la $2, sym_1_2299
+.globl sym_1_2300
+sym_1_2300: la $2, sym_1_2300
+.globl sym_1_2301
+sym_1_2301: la $2, sym_1_2301
+.globl sym_1_2302
+sym_1_2302: la $2, sym_1_2302
+.globl sym_1_2303
+sym_1_2303: la $2, sym_1_2303
+.globl sym_1_2304
+sym_1_2304: la $2, sym_1_2304
+.globl sym_1_2305
+sym_1_2305: la $2, sym_1_2305
+.globl sym_1_2306
+sym_1_2306: la $2, sym_1_2306
+.globl sym_1_2307
+sym_1_2307: la $2, sym_1_2307
+.globl sym_1_2308
+sym_1_2308: la $2, sym_1_2308
+.globl sym_1_2309
+sym_1_2309: la $2, sym_1_2309
+.globl sym_1_2310
+sym_1_2310: la $2, sym_1_2310
+.globl sym_1_2311
+sym_1_2311: la $2, sym_1_2311
+.globl sym_1_2312
+sym_1_2312: la $2, sym_1_2312
+.globl sym_1_2313
+sym_1_2313: la $2, sym_1_2313
+.globl sym_1_2314
+sym_1_2314: la $2, sym_1_2314
+.globl sym_1_2315
+sym_1_2315: la $2, sym_1_2315
+.globl sym_1_2316
+sym_1_2316: la $2, sym_1_2316
+.globl sym_1_2317
+sym_1_2317: la $2, sym_1_2317
+.globl sym_1_2318
+sym_1_2318: la $2, sym_1_2318
+.globl sym_1_2319
+sym_1_2319: la $2, sym_1_2319
+.globl sym_1_2320
+sym_1_2320: la $2, sym_1_2320
+.globl sym_1_2321
+sym_1_2321: la $2, sym_1_2321
+.globl sym_1_2322
+sym_1_2322: la $2, sym_1_2322
+.globl sym_1_2323
+sym_1_2323: la $2, sym_1_2323
+.globl sym_1_2324
+sym_1_2324: la $2, sym_1_2324
+.globl sym_1_2325
+sym_1_2325: la $2, sym_1_2325
+.globl sym_1_2326
+sym_1_2326: la $2, sym_1_2326
+.globl sym_1_2327
+sym_1_2327: la $2, sym_1_2327
+.globl sym_1_2328
+sym_1_2328: la $2, sym_1_2328
+.globl sym_1_2329
+sym_1_2329: la $2, sym_1_2329
+.globl sym_1_2330
+sym_1_2330: la $2, sym_1_2330
+.globl sym_1_2331
+sym_1_2331: la $2, sym_1_2331
+.globl sym_1_2332
+sym_1_2332: la $2, sym_1_2332
+.globl sym_1_2333
+sym_1_2333: la $2, sym_1_2333
+.globl sym_1_2334
+sym_1_2334: la $2, sym_1_2334
+.globl sym_1_2335
+sym_1_2335: la $2, sym_1_2335
+.globl sym_1_2336
+sym_1_2336: la $2, sym_1_2336
+.globl sym_1_2337
+sym_1_2337: la $2, sym_1_2337
+.globl sym_1_2338
+sym_1_2338: la $2, sym_1_2338
+.globl sym_1_2339
+sym_1_2339: la $2, sym_1_2339
+.globl sym_1_2340
+sym_1_2340: la $2, sym_1_2340
+.globl sym_1_2341
+sym_1_2341: la $2, sym_1_2341
+.globl sym_1_2342
+sym_1_2342: la $2, sym_1_2342
+.globl sym_1_2343
+sym_1_2343: la $2, sym_1_2343
+.globl sym_1_2344
+sym_1_2344: la $2, sym_1_2344
+.globl sym_1_2345
+sym_1_2345: la $2, sym_1_2345
+.globl sym_1_2346
+sym_1_2346: la $2, sym_1_2346
+.globl sym_1_2347
+sym_1_2347: la $2, sym_1_2347
+.globl sym_1_2348
+sym_1_2348: la $2, sym_1_2348
+.globl sym_1_2349
+sym_1_2349: la $2, sym_1_2349
+.globl sym_1_2350
+sym_1_2350: la $2, sym_1_2350
+.globl sym_1_2351
+sym_1_2351: la $2, sym_1_2351
+.globl sym_1_2352
+sym_1_2352: la $2, sym_1_2352
+.globl sym_1_2353
+sym_1_2353: la $2, sym_1_2353
+.globl sym_1_2354
+sym_1_2354: la $2, sym_1_2354
+.globl sym_1_2355
+sym_1_2355: la $2, sym_1_2355
+.globl sym_1_2356
+sym_1_2356: la $2, sym_1_2356
+.globl sym_1_2357
+sym_1_2357: la $2, sym_1_2357
+.globl sym_1_2358
+sym_1_2358: la $2, sym_1_2358
+.globl sym_1_2359
+sym_1_2359: la $2, sym_1_2359
+.globl sym_1_2360
+sym_1_2360: la $2, sym_1_2360
+.globl sym_1_2361
+sym_1_2361: la $2, sym_1_2361
+.globl sym_1_2362
+sym_1_2362: la $2, sym_1_2362
+.globl sym_1_2363
+sym_1_2363: la $2, sym_1_2363
+.globl sym_1_2364
+sym_1_2364: la $2, sym_1_2364
+.globl sym_1_2365
+sym_1_2365: la $2, sym_1_2365
+.globl sym_1_2366
+sym_1_2366: la $2, sym_1_2366
+.globl sym_1_2367
+sym_1_2367: la $2, sym_1_2367
+.globl sym_1_2368
+sym_1_2368: la $2, sym_1_2368
+.globl sym_1_2369
+sym_1_2369: la $2, sym_1_2369
+.globl sym_1_2370
+sym_1_2370: la $2, sym_1_2370
+.globl sym_1_2371
+sym_1_2371: la $2, sym_1_2371
+.globl sym_1_2372
+sym_1_2372: la $2, sym_1_2372
+.globl sym_1_2373
+sym_1_2373: la $2, sym_1_2373
+.globl sym_1_2374
+sym_1_2374: la $2, sym_1_2374
+.globl sym_1_2375
+sym_1_2375: la $2, sym_1_2375
+.globl sym_1_2376
+sym_1_2376: la $2, sym_1_2376
+.globl sym_1_2377
+sym_1_2377: la $2, sym_1_2377
+.globl sym_1_2378
+sym_1_2378: la $2, sym_1_2378
+.globl sym_1_2379
+sym_1_2379: la $2, sym_1_2379
+.globl sym_1_2380
+sym_1_2380: la $2, sym_1_2380
+.globl sym_1_2381
+sym_1_2381: la $2, sym_1_2381
+.globl sym_1_2382
+sym_1_2382: la $2, sym_1_2382
+.globl sym_1_2383
+sym_1_2383: la $2, sym_1_2383
+.globl sym_1_2384
+sym_1_2384: la $2, sym_1_2384
+.globl sym_1_2385
+sym_1_2385: la $2, sym_1_2385
+.globl sym_1_2386
+sym_1_2386: la $2, sym_1_2386
+.globl sym_1_2387
+sym_1_2387: la $2, sym_1_2387
+.globl sym_1_2388
+sym_1_2388: la $2, sym_1_2388
+.globl sym_1_2389
+sym_1_2389: la $2, sym_1_2389
+.globl sym_1_2390
+sym_1_2390: la $2, sym_1_2390
+.globl sym_1_2391
+sym_1_2391: la $2, sym_1_2391
+.globl sym_1_2392
+sym_1_2392: la $2, sym_1_2392
+.globl sym_1_2393
+sym_1_2393: la $2, sym_1_2393
+.globl sym_1_2394
+sym_1_2394: la $2, sym_1_2394
+.globl sym_1_2395
+sym_1_2395: la $2, sym_1_2395
+.globl sym_1_2396
+sym_1_2396: la $2, sym_1_2396
+.globl sym_1_2397
+sym_1_2397: la $2, sym_1_2397
+.globl sym_1_2398
+sym_1_2398: la $2, sym_1_2398
+.globl sym_1_2399
+sym_1_2399: la $2, sym_1_2399
+.globl sym_1_2400
+sym_1_2400: la $2, sym_1_2400
+.globl sym_1_2401
+sym_1_2401: la $2, sym_1_2401
+.globl sym_1_2402
+sym_1_2402: la $2, sym_1_2402
+.globl sym_1_2403
+sym_1_2403: la $2, sym_1_2403
+.globl sym_1_2404
+sym_1_2404: la $2, sym_1_2404
+.globl sym_1_2405
+sym_1_2405: la $2, sym_1_2405
+.globl sym_1_2406
+sym_1_2406: la $2, sym_1_2406
+.globl sym_1_2407
+sym_1_2407: la $2, sym_1_2407
+.globl sym_1_2408
+sym_1_2408: la $2, sym_1_2408
+.globl sym_1_2409
+sym_1_2409: la $2, sym_1_2409
+.globl sym_1_2410
+sym_1_2410: la $2, sym_1_2410
+.globl sym_1_2411
+sym_1_2411: la $2, sym_1_2411
+.globl sym_1_2412
+sym_1_2412: la $2, sym_1_2412
+.globl sym_1_2413
+sym_1_2413: la $2, sym_1_2413
+.globl sym_1_2414
+sym_1_2414: la $2, sym_1_2414
+.globl sym_1_2415
+sym_1_2415: la $2, sym_1_2415
+.globl sym_1_2416
+sym_1_2416: la $2, sym_1_2416
+.globl sym_1_2417
+sym_1_2417: la $2, sym_1_2417
+.globl sym_1_2418
+sym_1_2418: la $2, sym_1_2418
+.globl sym_1_2419
+sym_1_2419: la $2, sym_1_2419
+.globl sym_1_2420
+sym_1_2420: la $2, sym_1_2420
+.globl sym_1_2421
+sym_1_2421: la $2, sym_1_2421
+.globl sym_1_2422
+sym_1_2422: la $2, sym_1_2422
+.globl sym_1_2423
+sym_1_2423: la $2, sym_1_2423
+.globl sym_1_2424
+sym_1_2424: la $2, sym_1_2424
+.globl sym_1_2425
+sym_1_2425: la $2, sym_1_2425
+.globl sym_1_2426
+sym_1_2426: la $2, sym_1_2426
+.globl sym_1_2427
+sym_1_2427: la $2, sym_1_2427
+.globl sym_1_2428
+sym_1_2428: la $2, sym_1_2428
+.globl sym_1_2429
+sym_1_2429: la $2, sym_1_2429
+.globl sym_1_2430
+sym_1_2430: la $2, sym_1_2430
+.globl sym_1_2431
+sym_1_2431: la $2, sym_1_2431
+.globl sym_1_2432
+sym_1_2432: la $2, sym_1_2432
+.globl sym_1_2433
+sym_1_2433: la $2, sym_1_2433
+.globl sym_1_2434
+sym_1_2434: la $2, sym_1_2434
+.globl sym_1_2435
+sym_1_2435: la $2, sym_1_2435
+.globl sym_1_2436
+sym_1_2436: la $2, sym_1_2436
+.globl sym_1_2437
+sym_1_2437: la $2, sym_1_2437
+.globl sym_1_2438
+sym_1_2438: la $2, sym_1_2438
+.globl sym_1_2439
+sym_1_2439: la $2, sym_1_2439
+.globl sym_1_2440
+sym_1_2440: la $2, sym_1_2440
+.globl sym_1_2441
+sym_1_2441: la $2, sym_1_2441
+.globl sym_1_2442
+sym_1_2442: la $2, sym_1_2442
+.globl sym_1_2443
+sym_1_2443: la $2, sym_1_2443
+.globl sym_1_2444
+sym_1_2444: la $2, sym_1_2444
+.globl sym_1_2445
+sym_1_2445: la $2, sym_1_2445
+.globl sym_1_2446
+sym_1_2446: la $2, sym_1_2446
+.globl sym_1_2447
+sym_1_2447: la $2, sym_1_2447
+.globl sym_1_2448
+sym_1_2448: la $2, sym_1_2448
+.globl sym_1_2449
+sym_1_2449: la $2, sym_1_2449
+.globl sym_1_2450
+sym_1_2450: la $2, sym_1_2450
+.globl sym_1_2451
+sym_1_2451: la $2, sym_1_2451
+.globl sym_1_2452
+sym_1_2452: la $2, sym_1_2452
+.globl sym_1_2453
+sym_1_2453: la $2, sym_1_2453
+.globl sym_1_2454
+sym_1_2454: la $2, sym_1_2454
+.globl sym_1_2455
+sym_1_2455: la $2, sym_1_2455
+.globl sym_1_2456
+sym_1_2456: la $2, sym_1_2456
+.globl sym_1_2457
+sym_1_2457: la $2, sym_1_2457
+.globl sym_1_2458
+sym_1_2458: la $2, sym_1_2458
+.globl sym_1_2459
+sym_1_2459: la $2, sym_1_2459
+.globl sym_1_2460
+sym_1_2460: la $2, sym_1_2460
+.globl sym_1_2461
+sym_1_2461: la $2, sym_1_2461
+.globl sym_1_2462
+sym_1_2462: la $2, sym_1_2462
+.globl sym_1_2463
+sym_1_2463: la $2, sym_1_2463
+.globl sym_1_2464
+sym_1_2464: la $2, sym_1_2464
+.globl sym_1_2465
+sym_1_2465: la $2, sym_1_2465
+.globl sym_1_2466
+sym_1_2466: la $2, sym_1_2466
+.globl sym_1_2467
+sym_1_2467: la $2, sym_1_2467
+.globl sym_1_2468
+sym_1_2468: la $2, sym_1_2468
+.globl sym_1_2469
+sym_1_2469: la $2, sym_1_2469
+.globl sym_1_2470
+sym_1_2470: la $2, sym_1_2470
+.globl sym_1_2471
+sym_1_2471: la $2, sym_1_2471
+.globl sym_1_2472
+sym_1_2472: la $2, sym_1_2472
+.globl sym_1_2473
+sym_1_2473: la $2, sym_1_2473
+.globl sym_1_2474
+sym_1_2474: la $2, sym_1_2474
+.globl sym_1_2475
+sym_1_2475: la $2, sym_1_2475
+.globl sym_1_2476
+sym_1_2476: la $2, sym_1_2476
+.globl sym_1_2477
+sym_1_2477: la $2, sym_1_2477
+.globl sym_1_2478
+sym_1_2478: la $2, sym_1_2478
+.globl sym_1_2479
+sym_1_2479: la $2, sym_1_2479
+.globl sym_1_2480
+sym_1_2480: la $2, sym_1_2480
+.globl sym_1_2481
+sym_1_2481: la $2, sym_1_2481
+.globl sym_1_2482
+sym_1_2482: la $2, sym_1_2482
+.globl sym_1_2483
+sym_1_2483: la $2, sym_1_2483
+.globl sym_1_2484
+sym_1_2484: la $2, sym_1_2484
+.globl sym_1_2485
+sym_1_2485: la $2, sym_1_2485
+.globl sym_1_2486
+sym_1_2486: la $2, sym_1_2486
+.globl sym_1_2487
+sym_1_2487: la $2, sym_1_2487
+.globl sym_1_2488
+sym_1_2488: la $2, sym_1_2488
+.globl sym_1_2489
+sym_1_2489: la $2, sym_1_2489
+.globl sym_1_2490
+sym_1_2490: la $2, sym_1_2490
+.globl sym_1_2491
+sym_1_2491: la $2, sym_1_2491
+.globl sym_1_2492
+sym_1_2492: la $2, sym_1_2492
+.globl sym_1_2493
+sym_1_2493: la $2, sym_1_2493
+.globl sym_1_2494
+sym_1_2494: la $2, sym_1_2494
+.globl sym_1_2495
+sym_1_2495: la $2, sym_1_2495
+.globl sym_1_2496
+sym_1_2496: la $2, sym_1_2496
+.globl sym_1_2497
+sym_1_2497: la $2, sym_1_2497
+.globl sym_1_2498
+sym_1_2498: la $2, sym_1_2498
+.globl sym_1_2499
+sym_1_2499: la $2, sym_1_2499
+.globl sym_1_2500
+sym_1_2500: la $2, sym_1_2500
+.globl sym_1_2501
+sym_1_2501: la $2, sym_1_2501
+.globl sym_1_2502
+sym_1_2502: la $2, sym_1_2502
+.globl sym_1_2503
+sym_1_2503: la $2, sym_1_2503
+.globl sym_1_2504
+sym_1_2504: la $2, sym_1_2504
+.globl sym_1_2505
+sym_1_2505: la $2, sym_1_2505
+.globl sym_1_2506
+sym_1_2506: la $2, sym_1_2506
+.globl sym_1_2507
+sym_1_2507: la $2, sym_1_2507
+.globl sym_1_2508
+sym_1_2508: la $2, sym_1_2508
+.globl sym_1_2509
+sym_1_2509: la $2, sym_1_2509
+.globl sym_1_2510
+sym_1_2510: la $2, sym_1_2510
+.globl sym_1_2511
+sym_1_2511: la $2, sym_1_2511
+.globl sym_1_2512
+sym_1_2512: la $2, sym_1_2512
+.globl sym_1_2513
+sym_1_2513: la $2, sym_1_2513
+.globl sym_1_2514
+sym_1_2514: la $2, sym_1_2514
+.globl sym_1_2515
+sym_1_2515: la $2, sym_1_2515
+.globl sym_1_2516
+sym_1_2516: la $2, sym_1_2516
+.globl sym_1_2517
+sym_1_2517: la $2, sym_1_2517
+.globl sym_1_2518
+sym_1_2518: la $2, sym_1_2518
+.globl sym_1_2519
+sym_1_2519: la $2, sym_1_2519
+.globl sym_1_2520
+sym_1_2520: la $2, sym_1_2520
+.globl sym_1_2521
+sym_1_2521: la $2, sym_1_2521
+.globl sym_1_2522
+sym_1_2522: la $2, sym_1_2522
+.globl sym_1_2523
+sym_1_2523: la $2, sym_1_2523
+.globl sym_1_2524
+sym_1_2524: la $2, sym_1_2524
+.globl sym_1_2525
+sym_1_2525: la $2, sym_1_2525
+.globl sym_1_2526
+sym_1_2526: la $2, sym_1_2526
+.globl sym_1_2527
+sym_1_2527: la $2, sym_1_2527
+.globl sym_1_2528
+sym_1_2528: la $2, sym_1_2528
+.globl sym_1_2529
+sym_1_2529: la $2, sym_1_2529
+.globl sym_1_2530
+sym_1_2530: la $2, sym_1_2530
+.globl sym_1_2531
+sym_1_2531: la $2, sym_1_2531
+.globl sym_1_2532
+sym_1_2532: la $2, sym_1_2532
+.globl sym_1_2533
+sym_1_2533: la $2, sym_1_2533
+.globl sym_1_2534
+sym_1_2534: la $2, sym_1_2534
+.globl sym_1_2535
+sym_1_2535: la $2, sym_1_2535
+.globl sym_1_2536
+sym_1_2536: la $2, sym_1_2536
+.globl sym_1_2537
+sym_1_2537: la $2, sym_1_2537
+.globl sym_1_2538
+sym_1_2538: la $2, sym_1_2538
+.globl sym_1_2539
+sym_1_2539: la $2, sym_1_2539
+.globl sym_1_2540
+sym_1_2540: la $2, sym_1_2540
+.globl sym_1_2541
+sym_1_2541: la $2, sym_1_2541
+.globl sym_1_2542
+sym_1_2542: la $2, sym_1_2542
+.globl sym_1_2543
+sym_1_2543: la $2, sym_1_2543
+.globl sym_1_2544
+sym_1_2544: la $2, sym_1_2544
+.globl sym_1_2545
+sym_1_2545: la $2, sym_1_2545
+.globl sym_1_2546
+sym_1_2546: la $2, sym_1_2546
+.globl sym_1_2547
+sym_1_2547: la $2, sym_1_2547
+.globl sym_1_2548
+sym_1_2548: la $2, sym_1_2548
+.globl sym_1_2549
+sym_1_2549: la $2, sym_1_2549
+.globl sym_1_2550
+sym_1_2550: la $2, sym_1_2550
+.globl sym_1_2551
+sym_1_2551: la $2, sym_1_2551
+.globl sym_1_2552
+sym_1_2552: la $2, sym_1_2552
+.globl sym_1_2553
+sym_1_2553: la $2, sym_1_2553
+.globl sym_1_2554
+sym_1_2554: la $2, sym_1_2554
+.globl sym_1_2555
+sym_1_2555: la $2, sym_1_2555
+.globl sym_1_2556
+sym_1_2556: la $2, sym_1_2556
+.globl sym_1_2557
+sym_1_2557: la $2, sym_1_2557
+.globl sym_1_2558
+sym_1_2558: la $2, sym_1_2558
+.globl sym_1_2559
+sym_1_2559: la $2, sym_1_2559
+.globl sym_1_2560
+sym_1_2560: la $2, sym_1_2560
+.globl sym_1_2561
+sym_1_2561: la $2, sym_1_2561
+.globl sym_1_2562
+sym_1_2562: la $2, sym_1_2562
+.globl sym_1_2563
+sym_1_2563: la $2, sym_1_2563
+.globl sym_1_2564
+sym_1_2564: la $2, sym_1_2564
+.globl sym_1_2565
+sym_1_2565: la $2, sym_1_2565
+.globl sym_1_2566
+sym_1_2566: la $2, sym_1_2566
+.globl sym_1_2567
+sym_1_2567: la $2, sym_1_2567
+.globl sym_1_2568
+sym_1_2568: la $2, sym_1_2568
+.globl sym_1_2569
+sym_1_2569: la $2, sym_1_2569
+.globl sym_1_2570
+sym_1_2570: la $2, sym_1_2570
+.globl sym_1_2571
+sym_1_2571: la $2, sym_1_2571
+.globl sym_1_2572
+sym_1_2572: la $2, sym_1_2572
+.globl sym_1_2573
+sym_1_2573: la $2, sym_1_2573
+.globl sym_1_2574
+sym_1_2574: la $2, sym_1_2574
+.globl sym_1_2575
+sym_1_2575: la $2, sym_1_2575
+.globl sym_1_2576
+sym_1_2576: la $2, sym_1_2576
+.globl sym_1_2577
+sym_1_2577: la $2, sym_1_2577
+.globl sym_1_2578
+sym_1_2578: la $2, sym_1_2578
+.globl sym_1_2579
+sym_1_2579: la $2, sym_1_2579
+.globl sym_1_2580
+sym_1_2580: la $2, sym_1_2580
+.globl sym_1_2581
+sym_1_2581: la $2, sym_1_2581
+.globl sym_1_2582
+sym_1_2582: la $2, sym_1_2582
+.globl sym_1_2583
+sym_1_2583: la $2, sym_1_2583
+.globl sym_1_2584
+sym_1_2584: la $2, sym_1_2584
+.globl sym_1_2585
+sym_1_2585: la $2, sym_1_2585
+.globl sym_1_2586
+sym_1_2586: la $2, sym_1_2586
+.globl sym_1_2587
+sym_1_2587: la $2, sym_1_2587
+.globl sym_1_2588
+sym_1_2588: la $2, sym_1_2588
+.globl sym_1_2589
+sym_1_2589: la $2, sym_1_2589
+.globl sym_1_2590
+sym_1_2590: la $2, sym_1_2590
+.globl sym_1_2591
+sym_1_2591: la $2, sym_1_2591
+.globl sym_1_2592
+sym_1_2592: la $2, sym_1_2592
+.globl sym_1_2593
+sym_1_2593: la $2, sym_1_2593
+.globl sym_1_2594
+sym_1_2594: la $2, sym_1_2594
+.globl sym_1_2595
+sym_1_2595: la $2, sym_1_2595
+.globl sym_1_2596
+sym_1_2596: la $2, sym_1_2596
+.globl sym_1_2597
+sym_1_2597: la $2, sym_1_2597
+.globl sym_1_2598
+sym_1_2598: la $2, sym_1_2598
+.globl sym_1_2599
+sym_1_2599: la $2, sym_1_2599
+.globl sym_1_2600
+sym_1_2600: la $2, sym_1_2600
+.globl sym_1_2601
+sym_1_2601: la $2, sym_1_2601
+.globl sym_1_2602
+sym_1_2602: la $2, sym_1_2602
+.globl sym_1_2603
+sym_1_2603: la $2, sym_1_2603
+.globl sym_1_2604
+sym_1_2604: la $2, sym_1_2604
+.globl sym_1_2605
+sym_1_2605: la $2, sym_1_2605
+.globl sym_1_2606
+sym_1_2606: la $2, sym_1_2606
+.globl sym_1_2607
+sym_1_2607: la $2, sym_1_2607
+.globl sym_1_2608
+sym_1_2608: la $2, sym_1_2608
+.globl sym_1_2609
+sym_1_2609: la $2, sym_1_2609
+.globl sym_1_2610
+sym_1_2610: la $2, sym_1_2610
+.globl sym_1_2611
+sym_1_2611: la $2, sym_1_2611
+.globl sym_1_2612
+sym_1_2612: la $2, sym_1_2612
+.globl sym_1_2613
+sym_1_2613: la $2, sym_1_2613
+.globl sym_1_2614
+sym_1_2614: la $2, sym_1_2614
+.globl sym_1_2615
+sym_1_2615: la $2, sym_1_2615
+.globl sym_1_2616
+sym_1_2616: la $2, sym_1_2616
+.globl sym_1_2617
+sym_1_2617: la $2, sym_1_2617
+.globl sym_1_2618
+sym_1_2618: la $2, sym_1_2618
+.globl sym_1_2619
+sym_1_2619: la $2, sym_1_2619
+.globl sym_1_2620
+sym_1_2620: la $2, sym_1_2620
+.globl sym_1_2621
+sym_1_2621: la $2, sym_1_2621
+.globl sym_1_2622
+sym_1_2622: la $2, sym_1_2622
+.globl sym_1_2623
+sym_1_2623: la $2, sym_1_2623
+.globl sym_1_2624
+sym_1_2624: la $2, sym_1_2624
+.globl sym_1_2625
+sym_1_2625: la $2, sym_1_2625
+.globl sym_1_2626
+sym_1_2626: la $2, sym_1_2626
+.globl sym_1_2627
+sym_1_2627: la $2, sym_1_2627
+.globl sym_1_2628
+sym_1_2628: la $2, sym_1_2628
+.globl sym_1_2629
+sym_1_2629: la $2, sym_1_2629
+.globl sym_1_2630
+sym_1_2630: la $2, sym_1_2630
+.globl sym_1_2631
+sym_1_2631: la $2, sym_1_2631
+.globl sym_1_2632
+sym_1_2632: la $2, sym_1_2632
+.globl sym_1_2633
+sym_1_2633: la $2, sym_1_2633
+.globl sym_1_2634
+sym_1_2634: la $2, sym_1_2634
+.globl sym_1_2635
+sym_1_2635: la $2, sym_1_2635
+.globl sym_1_2636
+sym_1_2636: la $2, sym_1_2636
+.globl sym_1_2637
+sym_1_2637: la $2, sym_1_2637
+.globl sym_1_2638
+sym_1_2638: la $2, sym_1_2638
+.globl sym_1_2639
+sym_1_2639: la $2, sym_1_2639
+.globl sym_1_2640
+sym_1_2640: la $2, sym_1_2640
+.globl sym_1_2641
+sym_1_2641: la $2, sym_1_2641
+.globl sym_1_2642
+sym_1_2642: la $2, sym_1_2642
+.globl sym_1_2643
+sym_1_2643: la $2, sym_1_2643
+.globl sym_1_2644
+sym_1_2644: la $2, sym_1_2644
+.globl sym_1_2645
+sym_1_2645: la $2, sym_1_2645
+.globl sym_1_2646
+sym_1_2646: la $2, sym_1_2646
+.globl sym_1_2647
+sym_1_2647: la $2, sym_1_2647
+.globl sym_1_2648
+sym_1_2648: la $2, sym_1_2648
+.globl sym_1_2649
+sym_1_2649: la $2, sym_1_2649
+.globl sym_1_2650
+sym_1_2650: la $2, sym_1_2650
+.globl sym_1_2651
+sym_1_2651: la $2, sym_1_2651
+.globl sym_1_2652
+sym_1_2652: la $2, sym_1_2652
+.globl sym_1_2653
+sym_1_2653: la $2, sym_1_2653
+.globl sym_1_2654
+sym_1_2654: la $2, sym_1_2654
+.globl sym_1_2655
+sym_1_2655: la $2, sym_1_2655
+.globl sym_1_2656
+sym_1_2656: la $2, sym_1_2656
+.globl sym_1_2657
+sym_1_2657: la $2, sym_1_2657
+.globl sym_1_2658
+sym_1_2658: la $2, sym_1_2658
+.globl sym_1_2659
+sym_1_2659: la $2, sym_1_2659
+.globl sym_1_2660
+sym_1_2660: la $2, sym_1_2660
+.globl sym_1_2661
+sym_1_2661: la $2, sym_1_2661
+.globl sym_1_2662
+sym_1_2662: la $2, sym_1_2662
+.globl sym_1_2663
+sym_1_2663: la $2, sym_1_2663
+.globl sym_1_2664
+sym_1_2664: la $2, sym_1_2664
+.globl sym_1_2665
+sym_1_2665: la $2, sym_1_2665
+.globl sym_1_2666
+sym_1_2666: la $2, sym_1_2666
+.globl sym_1_2667
+sym_1_2667: la $2, sym_1_2667
+.globl sym_1_2668
+sym_1_2668: la $2, sym_1_2668
+.globl sym_1_2669
+sym_1_2669: la $2, sym_1_2669
+.globl sym_1_2670
+sym_1_2670: la $2, sym_1_2670
+.globl sym_1_2671
+sym_1_2671: la $2, sym_1_2671
+.globl sym_1_2672
+sym_1_2672: la $2, sym_1_2672
+.globl sym_1_2673
+sym_1_2673: la $2, sym_1_2673
+.globl sym_1_2674
+sym_1_2674: la $2, sym_1_2674
+.globl sym_1_2675
+sym_1_2675: la $2, sym_1_2675
+.globl sym_1_2676
+sym_1_2676: la $2, sym_1_2676
+.globl sym_1_2677
+sym_1_2677: la $2, sym_1_2677
+.globl sym_1_2678
+sym_1_2678: la $2, sym_1_2678
+.globl sym_1_2679
+sym_1_2679: la $2, sym_1_2679
+.globl sym_1_2680
+sym_1_2680: la $2, sym_1_2680
+.globl sym_1_2681
+sym_1_2681: la $2, sym_1_2681
+.globl sym_1_2682
+sym_1_2682: la $2, sym_1_2682
+.globl sym_1_2683
+sym_1_2683: la $2, sym_1_2683
+.globl sym_1_2684
+sym_1_2684: la $2, sym_1_2684
+.globl sym_1_2685
+sym_1_2685: la $2, sym_1_2685
+.globl sym_1_2686
+sym_1_2686: la $2, sym_1_2686
+.globl sym_1_2687
+sym_1_2687: la $2, sym_1_2687
+.globl sym_1_2688
+sym_1_2688: la $2, sym_1_2688
+.globl sym_1_2689
+sym_1_2689: la $2, sym_1_2689
+.globl sym_1_2690
+sym_1_2690: la $2, sym_1_2690
+.globl sym_1_2691
+sym_1_2691: la $2, sym_1_2691
+.globl sym_1_2692
+sym_1_2692: la $2, sym_1_2692
+.globl sym_1_2693
+sym_1_2693: la $2, sym_1_2693
+.globl sym_1_2694
+sym_1_2694: la $2, sym_1_2694
+.globl sym_1_2695
+sym_1_2695: la $2, sym_1_2695
+.globl sym_1_2696
+sym_1_2696: la $2, sym_1_2696
+.globl sym_1_2697
+sym_1_2697: la $2, sym_1_2697
+.globl sym_1_2698
+sym_1_2698: la $2, sym_1_2698
+.globl sym_1_2699
+sym_1_2699: la $2, sym_1_2699
+.globl sym_1_2700
+sym_1_2700: la $2, sym_1_2700
+.globl sym_1_2701
+sym_1_2701: la $2, sym_1_2701
+.globl sym_1_2702
+sym_1_2702: la $2, sym_1_2702
+.globl sym_1_2703
+sym_1_2703: la $2, sym_1_2703
+.globl sym_1_2704
+sym_1_2704: la $2, sym_1_2704
+.globl sym_1_2705
+sym_1_2705: la $2, sym_1_2705
+.globl sym_1_2706
+sym_1_2706: la $2, sym_1_2706
+.globl sym_1_2707
+sym_1_2707: la $2, sym_1_2707
+.globl sym_1_2708
+sym_1_2708: la $2, sym_1_2708
+.globl sym_1_2709
+sym_1_2709: la $2, sym_1_2709
+.globl sym_1_2710
+sym_1_2710: la $2, sym_1_2710
+.globl sym_1_2711
+sym_1_2711: la $2, sym_1_2711
+.globl sym_1_2712
+sym_1_2712: la $2, sym_1_2712
+.globl sym_1_2713
+sym_1_2713: la $2, sym_1_2713
+.globl sym_1_2714
+sym_1_2714: la $2, sym_1_2714
+.globl sym_1_2715
+sym_1_2715: la $2, sym_1_2715
+.globl sym_1_2716
+sym_1_2716: la $2, sym_1_2716
+.globl sym_1_2717
+sym_1_2717: la $2, sym_1_2717
+.globl sym_1_2718
+sym_1_2718: la $2, sym_1_2718
+.globl sym_1_2719
+sym_1_2719: la $2, sym_1_2719
+.globl sym_1_2720
+sym_1_2720: la $2, sym_1_2720
+.globl sym_1_2721
+sym_1_2721: la $2, sym_1_2721
+.globl sym_1_2722
+sym_1_2722: la $2, sym_1_2722
+.globl sym_1_2723
+sym_1_2723: la $2, sym_1_2723
+.globl sym_1_2724
+sym_1_2724: la $2, sym_1_2724
+.globl sym_1_2725
+sym_1_2725: la $2, sym_1_2725
+.globl sym_1_2726
+sym_1_2726: la $2, sym_1_2726
+.globl sym_1_2727
+sym_1_2727: la $2, sym_1_2727
+.globl sym_1_2728
+sym_1_2728: la $2, sym_1_2728
+.globl sym_1_2729
+sym_1_2729: la $2, sym_1_2729
+.globl sym_1_2730
+sym_1_2730: la $2, sym_1_2730
+.globl sym_1_2731
+sym_1_2731: la $2, sym_1_2731
+.globl sym_1_2732
+sym_1_2732: la $2, sym_1_2732
+.globl sym_1_2733
+sym_1_2733: la $2, sym_1_2733
+.globl sym_1_2734
+sym_1_2734: la $2, sym_1_2734
+.globl sym_1_2735
+sym_1_2735: la $2, sym_1_2735
+.globl sym_1_2736
+sym_1_2736: la $2, sym_1_2736
+.globl sym_1_2737
+sym_1_2737: la $2, sym_1_2737
+.globl sym_1_2738
+sym_1_2738: la $2, sym_1_2738
+.globl sym_1_2739
+sym_1_2739: la $2, sym_1_2739
+.globl sym_1_2740
+sym_1_2740: la $2, sym_1_2740
+.globl sym_1_2741
+sym_1_2741: la $2, sym_1_2741
+.globl sym_1_2742
+sym_1_2742: la $2, sym_1_2742
+.globl sym_1_2743
+sym_1_2743: la $2, sym_1_2743
+.globl sym_1_2744
+sym_1_2744: la $2, sym_1_2744
+.globl sym_1_2745
+sym_1_2745: la $2, sym_1_2745
+.globl sym_1_2746
+sym_1_2746: la $2, sym_1_2746
+.globl sym_1_2747
+sym_1_2747: la $2, sym_1_2747
+.globl sym_1_2748
+sym_1_2748: la $2, sym_1_2748
+.globl sym_1_2749
+sym_1_2749: la $2, sym_1_2749
+.globl sym_1_2750
+sym_1_2750: la $2, sym_1_2750
+.globl sym_1_2751
+sym_1_2751: la $2, sym_1_2751
+.globl sym_1_2752
+sym_1_2752: la $2, sym_1_2752
+.globl sym_1_2753
+sym_1_2753: la $2, sym_1_2753
+.globl sym_1_2754
+sym_1_2754: la $2, sym_1_2754
+.globl sym_1_2755
+sym_1_2755: la $2, sym_1_2755
+.globl sym_1_2756
+sym_1_2756: la $2, sym_1_2756
+.globl sym_1_2757
+sym_1_2757: la $2, sym_1_2757
+.globl sym_1_2758
+sym_1_2758: la $2, sym_1_2758
+.globl sym_1_2759
+sym_1_2759: la $2, sym_1_2759
+.globl sym_1_2760
+sym_1_2760: la $2, sym_1_2760
+.globl sym_1_2761
+sym_1_2761: la $2, sym_1_2761
+.globl sym_1_2762
+sym_1_2762: la $2, sym_1_2762
+.globl sym_1_2763
+sym_1_2763: la $2, sym_1_2763
+.globl sym_1_2764
+sym_1_2764: la $2, sym_1_2764
+.globl sym_1_2765
+sym_1_2765: la $2, sym_1_2765
+.globl sym_1_2766
+sym_1_2766: la $2, sym_1_2766
+.globl sym_1_2767
+sym_1_2767: la $2, sym_1_2767
+.globl sym_1_2768
+sym_1_2768: la $2, sym_1_2768
+.globl sym_1_2769
+sym_1_2769: la $2, sym_1_2769
+.globl sym_1_2770
+sym_1_2770: la $2, sym_1_2770
+.globl sym_1_2771
+sym_1_2771: la $2, sym_1_2771
+.globl sym_1_2772
+sym_1_2772: la $2, sym_1_2772
+.globl sym_1_2773
+sym_1_2773: la $2, sym_1_2773
+.globl sym_1_2774
+sym_1_2774: la $2, sym_1_2774
+.globl sym_1_2775
+sym_1_2775: la $2, sym_1_2775
+.globl sym_1_2776
+sym_1_2776: la $2, sym_1_2776
+.globl sym_1_2777
+sym_1_2777: la $2, sym_1_2777
+.globl sym_1_2778
+sym_1_2778: la $2, sym_1_2778
+.globl sym_1_2779
+sym_1_2779: la $2, sym_1_2779
+.globl sym_1_2780
+sym_1_2780: la $2, sym_1_2780
+.globl sym_1_2781
+sym_1_2781: la $2, sym_1_2781
+.globl sym_1_2782
+sym_1_2782: la $2, sym_1_2782
+.globl sym_1_2783
+sym_1_2783: la $2, sym_1_2783
+.globl sym_1_2784
+sym_1_2784: la $2, sym_1_2784
+.globl sym_1_2785
+sym_1_2785: la $2, sym_1_2785
+.globl sym_1_2786
+sym_1_2786: la $2, sym_1_2786
+.globl sym_1_2787
+sym_1_2787: la $2, sym_1_2787
+.globl sym_1_2788
+sym_1_2788: la $2, sym_1_2788
+.globl sym_1_2789
+sym_1_2789: la $2, sym_1_2789
+.globl sym_1_2790
+sym_1_2790: la $2, sym_1_2790
+.globl sym_1_2791
+sym_1_2791: la $2, sym_1_2791
+.globl sym_1_2792
+sym_1_2792: la $2, sym_1_2792
+.globl sym_1_2793
+sym_1_2793: la $2, sym_1_2793
+.globl sym_1_2794
+sym_1_2794: la $2, sym_1_2794
+.globl sym_1_2795
+sym_1_2795: la $2, sym_1_2795
+.globl sym_1_2796
+sym_1_2796: la $2, sym_1_2796
+.globl sym_1_2797
+sym_1_2797: la $2, sym_1_2797
+.globl sym_1_2798
+sym_1_2798: la $2, sym_1_2798
+.globl sym_1_2799
+sym_1_2799: la $2, sym_1_2799
+.globl sym_1_2800
+sym_1_2800: la $2, sym_1_2800
+.globl sym_1_2801
+sym_1_2801: la $2, sym_1_2801
+.globl sym_1_2802
+sym_1_2802: la $2, sym_1_2802
+.globl sym_1_2803
+sym_1_2803: la $2, sym_1_2803
+.globl sym_1_2804
+sym_1_2804: la $2, sym_1_2804
+.globl sym_1_2805
+sym_1_2805: la $2, sym_1_2805
+.globl sym_1_2806
+sym_1_2806: la $2, sym_1_2806
+.globl sym_1_2807
+sym_1_2807: la $2, sym_1_2807
+.globl sym_1_2808
+sym_1_2808: la $2, sym_1_2808
+.globl sym_1_2809
+sym_1_2809: la $2, sym_1_2809
+.globl sym_1_2810
+sym_1_2810: la $2, sym_1_2810
+.globl sym_1_2811
+sym_1_2811: la $2, sym_1_2811
+.globl sym_1_2812
+sym_1_2812: la $2, sym_1_2812
+.globl sym_1_2813
+sym_1_2813: la $2, sym_1_2813
+.globl sym_1_2814
+sym_1_2814: la $2, sym_1_2814
+.globl sym_1_2815
+sym_1_2815: la $2, sym_1_2815
+.globl sym_1_2816
+sym_1_2816: la $2, sym_1_2816
+.globl sym_1_2817
+sym_1_2817: la $2, sym_1_2817
+.globl sym_1_2818
+sym_1_2818: la $2, sym_1_2818
+.globl sym_1_2819
+sym_1_2819: la $2, sym_1_2819
+.globl sym_1_2820
+sym_1_2820: la $2, sym_1_2820
+.globl sym_1_2821
+sym_1_2821: la $2, sym_1_2821
+.globl sym_1_2822
+sym_1_2822: la $2, sym_1_2822
+.globl sym_1_2823
+sym_1_2823: la $2, sym_1_2823
+.globl sym_1_2824
+sym_1_2824: la $2, sym_1_2824
+.globl sym_1_2825
+sym_1_2825: la $2, sym_1_2825
+.globl sym_1_2826
+sym_1_2826: la $2, sym_1_2826
+.globl sym_1_2827
+sym_1_2827: la $2, sym_1_2827
+.globl sym_1_2828
+sym_1_2828: la $2, sym_1_2828
+.globl sym_1_2829
+sym_1_2829: la $2, sym_1_2829
+.globl sym_1_2830
+sym_1_2830: la $2, sym_1_2830
+.globl sym_1_2831
+sym_1_2831: la $2, sym_1_2831
+.globl sym_1_2832
+sym_1_2832: la $2, sym_1_2832
+.globl sym_1_2833
+sym_1_2833: la $2, sym_1_2833
+.globl sym_1_2834
+sym_1_2834: la $2, sym_1_2834
+.globl sym_1_2835
+sym_1_2835: la $2, sym_1_2835
+.globl sym_1_2836
+sym_1_2836: la $2, sym_1_2836
+.globl sym_1_2837
+sym_1_2837: la $2, sym_1_2837
+.globl sym_1_2838
+sym_1_2838: la $2, sym_1_2838
+.globl sym_1_2839
+sym_1_2839: la $2, sym_1_2839
+.globl sym_1_2840
+sym_1_2840: la $2, sym_1_2840
+.globl sym_1_2841
+sym_1_2841: la $2, sym_1_2841
+.globl sym_1_2842
+sym_1_2842: la $2, sym_1_2842
+.globl sym_1_2843
+sym_1_2843: la $2, sym_1_2843
+.globl sym_1_2844
+sym_1_2844: la $2, sym_1_2844
+.globl sym_1_2845
+sym_1_2845: la $2, sym_1_2845
+.globl sym_1_2846
+sym_1_2846: la $2, sym_1_2846
+.globl sym_1_2847
+sym_1_2847: la $2, sym_1_2847
+.globl sym_1_2848
+sym_1_2848: la $2, sym_1_2848
+.globl sym_1_2849
+sym_1_2849: la $2, sym_1_2849
+.globl sym_1_2850
+sym_1_2850: la $2, sym_1_2850
+.globl sym_1_2851
+sym_1_2851: la $2, sym_1_2851
+.globl sym_1_2852
+sym_1_2852: la $2, sym_1_2852
+.globl sym_1_2853
+sym_1_2853: la $2, sym_1_2853
+.globl sym_1_2854
+sym_1_2854: la $2, sym_1_2854
+.globl sym_1_2855
+sym_1_2855: la $2, sym_1_2855
+.globl sym_1_2856
+sym_1_2856: la $2, sym_1_2856
+.globl sym_1_2857
+sym_1_2857: la $2, sym_1_2857
+.globl sym_1_2858
+sym_1_2858: la $2, sym_1_2858
+.globl sym_1_2859
+sym_1_2859: la $2, sym_1_2859
+.globl sym_1_2860
+sym_1_2860: la $2, sym_1_2860
+.globl sym_1_2861
+sym_1_2861: la $2, sym_1_2861
+.globl sym_1_2862
+sym_1_2862: la $2, sym_1_2862
+.globl sym_1_2863
+sym_1_2863: la $2, sym_1_2863
+.globl sym_1_2864
+sym_1_2864: la $2, sym_1_2864
+.globl sym_1_2865
+sym_1_2865: la $2, sym_1_2865
+.globl sym_1_2866
+sym_1_2866: la $2, sym_1_2866
+.globl sym_1_2867
+sym_1_2867: la $2, sym_1_2867
+.globl sym_1_2868
+sym_1_2868: la $2, sym_1_2868
+.globl sym_1_2869
+sym_1_2869: la $2, sym_1_2869
+.globl sym_1_2870
+sym_1_2870: la $2, sym_1_2870
+.globl sym_1_2871
+sym_1_2871: la $2, sym_1_2871
+.globl sym_1_2872
+sym_1_2872: la $2, sym_1_2872
+.globl sym_1_2873
+sym_1_2873: la $2, sym_1_2873
+.globl sym_1_2874
+sym_1_2874: la $2, sym_1_2874
+.globl sym_1_2875
+sym_1_2875: la $2, sym_1_2875
+.globl sym_1_2876
+sym_1_2876: la $2, sym_1_2876
+.globl sym_1_2877
+sym_1_2877: la $2, sym_1_2877
+.globl sym_1_2878
+sym_1_2878: la $2, sym_1_2878
+.globl sym_1_2879
+sym_1_2879: la $2, sym_1_2879
+.globl sym_1_2880
+sym_1_2880: la $2, sym_1_2880
+.globl sym_1_2881
+sym_1_2881: la $2, sym_1_2881
+.globl sym_1_2882
+sym_1_2882: la $2, sym_1_2882
+.globl sym_1_2883
+sym_1_2883: la $2, sym_1_2883
+.globl sym_1_2884
+sym_1_2884: la $2, sym_1_2884
+.globl sym_1_2885
+sym_1_2885: la $2, sym_1_2885
+.globl sym_1_2886
+sym_1_2886: la $2, sym_1_2886
+.globl sym_1_2887
+sym_1_2887: la $2, sym_1_2887
+.globl sym_1_2888
+sym_1_2888: la $2, sym_1_2888
+.globl sym_1_2889
+sym_1_2889: la $2, sym_1_2889
+.globl sym_1_2890
+sym_1_2890: la $2, sym_1_2890
+.globl sym_1_2891
+sym_1_2891: la $2, sym_1_2891
+.globl sym_1_2892
+sym_1_2892: la $2, sym_1_2892
+.globl sym_1_2893
+sym_1_2893: la $2, sym_1_2893
+.globl sym_1_2894
+sym_1_2894: la $2, sym_1_2894
+.globl sym_1_2895
+sym_1_2895: la $2, sym_1_2895
+.globl sym_1_2896
+sym_1_2896: la $2, sym_1_2896
+.globl sym_1_2897
+sym_1_2897: la $2, sym_1_2897
+.globl sym_1_2898
+sym_1_2898: la $2, sym_1_2898
+.globl sym_1_2899
+sym_1_2899: la $2, sym_1_2899
+.globl sym_1_2900
+sym_1_2900: la $2, sym_1_2900
+.globl sym_1_2901
+sym_1_2901: la $2, sym_1_2901
+.globl sym_1_2902
+sym_1_2902: la $2, sym_1_2902
+.globl sym_1_2903
+sym_1_2903: la $2, sym_1_2903
+.globl sym_1_2904
+sym_1_2904: la $2, sym_1_2904
+.globl sym_1_2905
+sym_1_2905: la $2, sym_1_2905
+.globl sym_1_2906
+sym_1_2906: la $2, sym_1_2906
+.globl sym_1_2907
+sym_1_2907: la $2, sym_1_2907
+.globl sym_1_2908
+sym_1_2908: la $2, sym_1_2908
+.globl sym_1_2909
+sym_1_2909: la $2, sym_1_2909
+.globl sym_1_2910
+sym_1_2910: la $2, sym_1_2910
+.globl sym_1_2911
+sym_1_2911: la $2, sym_1_2911
+.globl sym_1_2912
+sym_1_2912: la $2, sym_1_2912
+.globl sym_1_2913
+sym_1_2913: la $2, sym_1_2913
+.globl sym_1_2914
+sym_1_2914: la $2, sym_1_2914
+.globl sym_1_2915
+sym_1_2915: la $2, sym_1_2915
+.globl sym_1_2916
+sym_1_2916: la $2, sym_1_2916
+.globl sym_1_2917
+sym_1_2917: la $2, sym_1_2917
+.globl sym_1_2918
+sym_1_2918: la $2, sym_1_2918
+.globl sym_1_2919
+sym_1_2919: la $2, sym_1_2919
+.globl sym_1_2920
+sym_1_2920: la $2, sym_1_2920
+.globl sym_1_2921
+sym_1_2921: la $2, sym_1_2921
+.globl sym_1_2922
+sym_1_2922: la $2, sym_1_2922
+.globl sym_1_2923
+sym_1_2923: la $2, sym_1_2923
+.globl sym_1_2924
+sym_1_2924: la $2, sym_1_2924
+.globl sym_1_2925
+sym_1_2925: la $2, sym_1_2925
+.globl sym_1_2926
+sym_1_2926: la $2, sym_1_2926
+.globl sym_1_2927
+sym_1_2927: la $2, sym_1_2927
+.globl sym_1_2928
+sym_1_2928: la $2, sym_1_2928
+.globl sym_1_2929
+sym_1_2929: la $2, sym_1_2929
+.globl sym_1_2930
+sym_1_2930: la $2, sym_1_2930
+.globl sym_1_2931
+sym_1_2931: la $2, sym_1_2931
+.globl sym_1_2932
+sym_1_2932: la $2, sym_1_2932
+.globl sym_1_2933
+sym_1_2933: la $2, sym_1_2933
+.globl sym_1_2934
+sym_1_2934: la $2, sym_1_2934
+.globl sym_1_2935
+sym_1_2935: la $2, sym_1_2935
+.globl sym_1_2936
+sym_1_2936: la $2, sym_1_2936
+.globl sym_1_2937
+sym_1_2937: la $2, sym_1_2937
+.globl sym_1_2938
+sym_1_2938: la $2, sym_1_2938
+.globl sym_1_2939
+sym_1_2939: la $2, sym_1_2939
+.globl sym_1_2940
+sym_1_2940: la $2, sym_1_2940
+.globl sym_1_2941
+sym_1_2941: la $2, sym_1_2941
+.globl sym_1_2942
+sym_1_2942: la $2, sym_1_2942
+.globl sym_1_2943
+sym_1_2943: la $2, sym_1_2943
+.globl sym_1_2944
+sym_1_2944: la $2, sym_1_2944
+.globl sym_1_2945
+sym_1_2945: la $2, sym_1_2945
+.globl sym_1_2946
+sym_1_2946: la $2, sym_1_2946
+.globl sym_1_2947
+sym_1_2947: la $2, sym_1_2947
+.globl sym_1_2948
+sym_1_2948: la $2, sym_1_2948
+.globl sym_1_2949
+sym_1_2949: la $2, sym_1_2949
+.globl sym_1_2950
+sym_1_2950: la $2, sym_1_2950
+.globl sym_1_2951
+sym_1_2951: la $2, sym_1_2951
+.globl sym_1_2952
+sym_1_2952: la $2, sym_1_2952
+.globl sym_1_2953
+sym_1_2953: la $2, sym_1_2953
+.globl sym_1_2954
+sym_1_2954: la $2, sym_1_2954
+.globl sym_1_2955
+sym_1_2955: la $2, sym_1_2955
+.globl sym_1_2956
+sym_1_2956: la $2, sym_1_2956
+.globl sym_1_2957
+sym_1_2957: la $2, sym_1_2957
+.globl sym_1_2958
+sym_1_2958: la $2, sym_1_2958
+.globl sym_1_2959
+sym_1_2959: la $2, sym_1_2959
+.globl sym_1_2960
+sym_1_2960: la $2, sym_1_2960
+.globl sym_1_2961
+sym_1_2961: la $2, sym_1_2961
+.globl sym_1_2962
+sym_1_2962: la $2, sym_1_2962
+.globl sym_1_2963
+sym_1_2963: la $2, sym_1_2963
+.globl sym_1_2964
+sym_1_2964: la $2, sym_1_2964
+.globl sym_1_2965
+sym_1_2965: la $2, sym_1_2965
+.globl sym_1_2966
+sym_1_2966: la $2, sym_1_2966
+.globl sym_1_2967
+sym_1_2967: la $2, sym_1_2967
+.globl sym_1_2968
+sym_1_2968: la $2, sym_1_2968
+.globl sym_1_2969
+sym_1_2969: la $2, sym_1_2969
+.globl sym_1_2970
+sym_1_2970: la $2, sym_1_2970
+.globl sym_1_2971
+sym_1_2971: la $2, sym_1_2971
+.globl sym_1_2972
+sym_1_2972: la $2, sym_1_2972
+.globl sym_1_2973
+sym_1_2973: la $2, sym_1_2973
+.globl sym_1_2974
+sym_1_2974: la $2, sym_1_2974
+.globl sym_1_2975
+sym_1_2975: la $2, sym_1_2975
+.globl sym_1_2976
+sym_1_2976: la $2, sym_1_2976
+.globl sym_1_2977
+sym_1_2977: la $2, sym_1_2977
+.globl sym_1_2978
+sym_1_2978: la $2, sym_1_2978
+.globl sym_1_2979
+sym_1_2979: la $2, sym_1_2979
+.globl sym_1_2980
+sym_1_2980: la $2, sym_1_2980
+.globl sym_1_2981
+sym_1_2981: la $2, sym_1_2981
+.globl sym_1_2982
+sym_1_2982: la $2, sym_1_2982
+.globl sym_1_2983
+sym_1_2983: la $2, sym_1_2983
+.globl sym_1_2984
+sym_1_2984: la $2, sym_1_2984
+.globl sym_1_2985
+sym_1_2985: la $2, sym_1_2985
+.globl sym_1_2986
+sym_1_2986: la $2, sym_1_2986
+.globl sym_1_2987
+sym_1_2987: la $2, sym_1_2987
+.globl sym_1_2988
+sym_1_2988: la $2, sym_1_2988
+.globl sym_1_2989
+sym_1_2989: la $2, sym_1_2989
+.globl sym_1_2990
+sym_1_2990: la $2, sym_1_2990
+.globl sym_1_2991
+sym_1_2991: la $2, sym_1_2991
+.globl sym_1_2992
+sym_1_2992: la $2, sym_1_2992
+.globl sym_1_2993
+sym_1_2993: la $2, sym_1_2993
+.globl sym_1_2994
+sym_1_2994: la $2, sym_1_2994
+.globl sym_1_2995
+sym_1_2995: la $2, sym_1_2995
+.globl sym_1_2996
+sym_1_2996: la $2, sym_1_2996
+.globl sym_1_2997
+sym_1_2997: la $2, sym_1_2997
+.globl sym_1_2998
+sym_1_2998: la $2, sym_1_2998
+.globl sym_1_2999
+sym_1_2999: la $2, sym_1_2999
+.globl sym_1_3000
+sym_1_3000: la $2, sym_1_3000
+.globl sym_1_3001
+sym_1_3001: la $2, sym_1_3001
+.globl sym_1_3002
+sym_1_3002: la $2, sym_1_3002
+.globl sym_1_3003
+sym_1_3003: la $2, sym_1_3003
+.globl sym_1_3004
+sym_1_3004: la $2, sym_1_3004
+.globl sym_1_3005
+sym_1_3005: la $2, sym_1_3005
+.globl sym_1_3006
+sym_1_3006: la $2, sym_1_3006
+.globl sym_1_3007
+sym_1_3007: la $2, sym_1_3007
+.globl sym_1_3008
+sym_1_3008: la $2, sym_1_3008
+.globl sym_1_3009
+sym_1_3009: la $2, sym_1_3009
+.globl sym_1_3010
+sym_1_3010: la $2, sym_1_3010
+.globl sym_1_3011
+sym_1_3011: la $2, sym_1_3011
+.globl sym_1_3012
+sym_1_3012: la $2, sym_1_3012
+.globl sym_1_3013
+sym_1_3013: la $2, sym_1_3013
+.globl sym_1_3014
+sym_1_3014: la $2, sym_1_3014
+.globl sym_1_3015
+sym_1_3015: la $2, sym_1_3015
+.globl sym_1_3016
+sym_1_3016: la $2, sym_1_3016
+.globl sym_1_3017
+sym_1_3017: la $2, sym_1_3017
+.globl sym_1_3018
+sym_1_3018: la $2, sym_1_3018
+.globl sym_1_3019
+sym_1_3019: la $2, sym_1_3019
+.globl sym_1_3020
+sym_1_3020: la $2, sym_1_3020
+.globl sym_1_3021
+sym_1_3021: la $2, sym_1_3021
+.globl sym_1_3022
+sym_1_3022: la $2, sym_1_3022
+.globl sym_1_3023
+sym_1_3023: la $2, sym_1_3023
+.globl sym_1_3024
+sym_1_3024: la $2, sym_1_3024
+.globl sym_1_3025
+sym_1_3025: la $2, sym_1_3025
+.globl sym_1_3026
+sym_1_3026: la $2, sym_1_3026
+.globl sym_1_3027
+sym_1_3027: la $2, sym_1_3027
+.globl sym_1_3028
+sym_1_3028: la $2, sym_1_3028
+.globl sym_1_3029
+sym_1_3029: la $2, sym_1_3029
+.globl sym_1_3030
+sym_1_3030: la $2, sym_1_3030
+.globl sym_1_3031
+sym_1_3031: la $2, sym_1_3031
+.globl sym_1_3032
+sym_1_3032: la $2, sym_1_3032
+.globl sym_1_3033
+sym_1_3033: la $2, sym_1_3033
+.globl sym_1_3034
+sym_1_3034: la $2, sym_1_3034
+.globl sym_1_3035
+sym_1_3035: la $2, sym_1_3035
+.globl sym_1_3036
+sym_1_3036: la $2, sym_1_3036
+.globl sym_1_3037
+sym_1_3037: la $2, sym_1_3037
+.globl sym_1_3038
+sym_1_3038: la $2, sym_1_3038
+.globl sym_1_3039
+sym_1_3039: la $2, sym_1_3039
+.globl sym_1_3040
+sym_1_3040: la $2, sym_1_3040
+.globl sym_1_3041
+sym_1_3041: la $2, sym_1_3041
+.globl sym_1_3042
+sym_1_3042: la $2, sym_1_3042
+.globl sym_1_3043
+sym_1_3043: la $2, sym_1_3043
+.globl sym_1_3044
+sym_1_3044: la $2, sym_1_3044
+.globl sym_1_3045
+sym_1_3045: la $2, sym_1_3045
+.globl sym_1_3046
+sym_1_3046: la $2, sym_1_3046
+.globl sym_1_3047
+sym_1_3047: la $2, sym_1_3047
+.globl sym_1_3048
+sym_1_3048: la $2, sym_1_3048
+.globl sym_1_3049
+sym_1_3049: la $2, sym_1_3049
+.globl sym_1_3050
+sym_1_3050: la $2, sym_1_3050
+.globl sym_1_3051
+sym_1_3051: la $2, sym_1_3051
+.globl sym_1_3052
+sym_1_3052: la $2, sym_1_3052
+.globl sym_1_3053
+sym_1_3053: la $2, sym_1_3053
+.globl sym_1_3054
+sym_1_3054: la $2, sym_1_3054
+.globl sym_1_3055
+sym_1_3055: la $2, sym_1_3055
+.globl sym_1_3056
+sym_1_3056: la $2, sym_1_3056
+.globl sym_1_3057
+sym_1_3057: la $2, sym_1_3057
+.globl sym_1_3058
+sym_1_3058: la $2, sym_1_3058
+.globl sym_1_3059
+sym_1_3059: la $2, sym_1_3059
+.globl sym_1_3060
+sym_1_3060: la $2, sym_1_3060
+.globl sym_1_3061
+sym_1_3061: la $2, sym_1_3061
+.globl sym_1_3062
+sym_1_3062: la $2, sym_1_3062
+.globl sym_1_3063
+sym_1_3063: la $2, sym_1_3063
+.globl sym_1_3064
+sym_1_3064: la $2, sym_1_3064
+.globl sym_1_3065
+sym_1_3065: la $2, sym_1_3065
+.globl sym_1_3066
+sym_1_3066: la $2, sym_1_3066
+.globl sym_1_3067
+sym_1_3067: la $2, sym_1_3067
+.globl sym_1_3068
+sym_1_3068: la $2, sym_1_3068
+.globl sym_1_3069
+sym_1_3069: la $2, sym_1_3069
+.globl sym_1_3070
+sym_1_3070: la $2, sym_1_3070
+.globl sym_1_3071
+sym_1_3071: la $2, sym_1_3071
+.globl sym_1_3072
+sym_1_3072: la $2, sym_1_3072
+.globl sym_1_3073
+sym_1_3073: la $2, sym_1_3073
+.globl sym_1_3074
+sym_1_3074: la $2, sym_1_3074
+.globl sym_1_3075
+sym_1_3075: la $2, sym_1_3075
+.globl sym_1_3076
+sym_1_3076: la $2, sym_1_3076
+.globl sym_1_3077
+sym_1_3077: la $2, sym_1_3077
+.globl sym_1_3078
+sym_1_3078: la $2, sym_1_3078
+.globl sym_1_3079
+sym_1_3079: la $2, sym_1_3079
+.globl sym_1_3080
+sym_1_3080: la $2, sym_1_3080
+.globl sym_1_3081
+sym_1_3081: la $2, sym_1_3081
+.globl sym_1_3082
+sym_1_3082: la $2, sym_1_3082
+.globl sym_1_3083
+sym_1_3083: la $2, sym_1_3083
+.globl sym_1_3084
+sym_1_3084: la $2, sym_1_3084
+.globl sym_1_3085
+sym_1_3085: la $2, sym_1_3085
+.globl sym_1_3086
+sym_1_3086: la $2, sym_1_3086
+.globl sym_1_3087
+sym_1_3087: la $2, sym_1_3087
+.globl sym_1_3088
+sym_1_3088: la $2, sym_1_3088
+.globl sym_1_3089
+sym_1_3089: la $2, sym_1_3089
+.globl sym_1_3090
+sym_1_3090: la $2, sym_1_3090
+.globl sym_1_3091
+sym_1_3091: la $2, sym_1_3091
+.globl sym_1_3092
+sym_1_3092: la $2, sym_1_3092
+.globl sym_1_3093
+sym_1_3093: la $2, sym_1_3093
+.globl sym_1_3094
+sym_1_3094: la $2, sym_1_3094
+.globl sym_1_3095
+sym_1_3095: la $2, sym_1_3095
+.globl sym_1_3096
+sym_1_3096: la $2, sym_1_3096
+.globl sym_1_3097
+sym_1_3097: la $2, sym_1_3097
+.globl sym_1_3098
+sym_1_3098: la $2, sym_1_3098
+.globl sym_1_3099
+sym_1_3099: la $2, sym_1_3099
+.globl sym_1_3100
+sym_1_3100: la $2, sym_1_3100
+.globl sym_1_3101
+sym_1_3101: la $2, sym_1_3101
+.globl sym_1_3102
+sym_1_3102: la $2, sym_1_3102
+.globl sym_1_3103
+sym_1_3103: la $2, sym_1_3103
+.globl sym_1_3104
+sym_1_3104: la $2, sym_1_3104
+.globl sym_1_3105
+sym_1_3105: la $2, sym_1_3105
+.globl sym_1_3106
+sym_1_3106: la $2, sym_1_3106
+.globl sym_1_3107
+sym_1_3107: la $2, sym_1_3107
+.globl sym_1_3108
+sym_1_3108: la $2, sym_1_3108
+.globl sym_1_3109
+sym_1_3109: la $2, sym_1_3109
+.globl sym_1_3110
+sym_1_3110: la $2, sym_1_3110
+.globl sym_1_3111
+sym_1_3111: la $2, sym_1_3111
+.globl sym_1_3112
+sym_1_3112: la $2, sym_1_3112
+.globl sym_1_3113
+sym_1_3113: la $2, sym_1_3113
+.globl sym_1_3114
+sym_1_3114: la $2, sym_1_3114
+.globl sym_1_3115
+sym_1_3115: la $2, sym_1_3115
+.globl sym_1_3116
+sym_1_3116: la $2, sym_1_3116
+.globl sym_1_3117
+sym_1_3117: la $2, sym_1_3117
+.globl sym_1_3118
+sym_1_3118: la $2, sym_1_3118
+.globl sym_1_3119
+sym_1_3119: la $2, sym_1_3119
+.globl sym_1_3120
+sym_1_3120: la $2, sym_1_3120
+.globl sym_1_3121
+sym_1_3121: la $2, sym_1_3121
+.globl sym_1_3122
+sym_1_3122: la $2, sym_1_3122
+.globl sym_1_3123
+sym_1_3123: la $2, sym_1_3123
+.globl sym_1_3124
+sym_1_3124: la $2, sym_1_3124
+.globl sym_1_3125
+sym_1_3125: la $2, sym_1_3125
+.globl sym_1_3126
+sym_1_3126: la $2, sym_1_3126
+.globl sym_1_3127
+sym_1_3127: la $2, sym_1_3127
+.globl sym_1_3128
+sym_1_3128: la $2, sym_1_3128
+.globl sym_1_3129
+sym_1_3129: la $2, sym_1_3129
+.globl sym_1_3130
+sym_1_3130: la $2, sym_1_3130
+.globl sym_1_3131
+sym_1_3131: la $2, sym_1_3131
+.globl sym_1_3132
+sym_1_3132: la $2, sym_1_3132
+.globl sym_1_3133
+sym_1_3133: la $2, sym_1_3133
+.globl sym_1_3134
+sym_1_3134: la $2, sym_1_3134
+.globl sym_1_3135
+sym_1_3135: la $2, sym_1_3135
+.globl sym_1_3136
+sym_1_3136: la $2, sym_1_3136
+.globl sym_1_3137
+sym_1_3137: la $2, sym_1_3137
+.globl sym_1_3138
+sym_1_3138: la $2, sym_1_3138
+.globl sym_1_3139
+sym_1_3139: la $2, sym_1_3139
+.globl sym_1_3140
+sym_1_3140: la $2, sym_1_3140
+.globl sym_1_3141
+sym_1_3141: la $2, sym_1_3141
+.globl sym_1_3142
+sym_1_3142: la $2, sym_1_3142
+.globl sym_1_3143
+sym_1_3143: la $2, sym_1_3143
+.globl sym_1_3144
+sym_1_3144: la $2, sym_1_3144
+.globl sym_1_3145
+sym_1_3145: la $2, sym_1_3145
+.globl sym_1_3146
+sym_1_3146: la $2, sym_1_3146
+.globl sym_1_3147
+sym_1_3147: la $2, sym_1_3147
+.globl sym_1_3148
+sym_1_3148: la $2, sym_1_3148
+.globl sym_1_3149
+sym_1_3149: la $2, sym_1_3149
+.globl sym_1_3150
+sym_1_3150: la $2, sym_1_3150
+.globl sym_1_3151
+sym_1_3151: la $2, sym_1_3151
+.globl sym_1_3152
+sym_1_3152: la $2, sym_1_3152
+.globl sym_1_3153
+sym_1_3153: la $2, sym_1_3153
+.globl sym_1_3154
+sym_1_3154: la $2, sym_1_3154
+.globl sym_1_3155
+sym_1_3155: la $2, sym_1_3155
+.globl sym_1_3156
+sym_1_3156: la $2, sym_1_3156
+.globl sym_1_3157
+sym_1_3157: la $2, sym_1_3157
+.globl sym_1_3158
+sym_1_3158: la $2, sym_1_3158
+.globl sym_1_3159
+sym_1_3159: la $2, sym_1_3159
+.globl sym_1_3160
+sym_1_3160: la $2, sym_1_3160
+.globl sym_1_3161
+sym_1_3161: la $2, sym_1_3161
+.globl sym_1_3162
+sym_1_3162: la $2, sym_1_3162
+.globl sym_1_3163
+sym_1_3163: la $2, sym_1_3163
+.globl sym_1_3164
+sym_1_3164: la $2, sym_1_3164
+.globl sym_1_3165
+sym_1_3165: la $2, sym_1_3165
+.globl sym_1_3166
+sym_1_3166: la $2, sym_1_3166
+.globl sym_1_3167
+sym_1_3167: la $2, sym_1_3167
+.globl sym_1_3168
+sym_1_3168: la $2, sym_1_3168
+.globl sym_1_3169
+sym_1_3169: la $2, sym_1_3169
+.globl sym_1_3170
+sym_1_3170: la $2, sym_1_3170
+.globl sym_1_3171
+sym_1_3171: la $2, sym_1_3171
+.globl sym_1_3172
+sym_1_3172: la $2, sym_1_3172
+.globl sym_1_3173
+sym_1_3173: la $2, sym_1_3173
+.globl sym_1_3174
+sym_1_3174: la $2, sym_1_3174
+.globl sym_1_3175
+sym_1_3175: la $2, sym_1_3175
+.globl sym_1_3176
+sym_1_3176: la $2, sym_1_3176
+.globl sym_1_3177
+sym_1_3177: la $2, sym_1_3177
+.globl sym_1_3178
+sym_1_3178: la $2, sym_1_3178
+.globl sym_1_3179
+sym_1_3179: la $2, sym_1_3179
+.globl sym_1_3180
+sym_1_3180: la $2, sym_1_3180
+.globl sym_1_3181
+sym_1_3181: la $2, sym_1_3181
+.globl sym_1_3182
+sym_1_3182: la $2, sym_1_3182
+.globl sym_1_3183
+sym_1_3183: la $2, sym_1_3183
+.globl sym_1_3184
+sym_1_3184: la $2, sym_1_3184
+.globl sym_1_3185
+sym_1_3185: la $2, sym_1_3185
+.globl sym_1_3186
+sym_1_3186: la $2, sym_1_3186
+.globl sym_1_3187
+sym_1_3187: la $2, sym_1_3187
+.globl sym_1_3188
+sym_1_3188: la $2, sym_1_3188
+.globl sym_1_3189
+sym_1_3189: la $2, sym_1_3189
+.globl sym_1_3190
+sym_1_3190: la $2, sym_1_3190
+.globl sym_1_3191
+sym_1_3191: la $2, sym_1_3191
+.globl sym_1_3192
+sym_1_3192: la $2, sym_1_3192
+.globl sym_1_3193
+sym_1_3193: la $2, sym_1_3193
+.globl sym_1_3194
+sym_1_3194: la $2, sym_1_3194
+.globl sym_1_3195
+sym_1_3195: la $2, sym_1_3195
+.globl sym_1_3196
+sym_1_3196: la $2, sym_1_3196
+.globl sym_1_3197
+sym_1_3197: la $2, sym_1_3197
+.globl sym_1_3198
+sym_1_3198: la $2, sym_1_3198
+.globl sym_1_3199
+sym_1_3199: la $2, sym_1_3199
+.globl sym_1_3200
+sym_1_3200: la $2, sym_1_3200
+.globl sym_1_3201
+sym_1_3201: la $2, sym_1_3201
+.globl sym_1_3202
+sym_1_3202: la $2, sym_1_3202
+.globl sym_1_3203
+sym_1_3203: la $2, sym_1_3203
+.globl sym_1_3204
+sym_1_3204: la $2, sym_1_3204
+.globl sym_1_3205
+sym_1_3205: la $2, sym_1_3205
+.globl sym_1_3206
+sym_1_3206: la $2, sym_1_3206
+.globl sym_1_3207
+sym_1_3207: la $2, sym_1_3207
+.globl sym_1_3208
+sym_1_3208: la $2, sym_1_3208
+.globl sym_1_3209
+sym_1_3209: la $2, sym_1_3209
+.globl sym_1_3210
+sym_1_3210: la $2, sym_1_3210
+.globl sym_1_3211
+sym_1_3211: la $2, sym_1_3211
+.globl sym_1_3212
+sym_1_3212: la $2, sym_1_3212
+.globl sym_1_3213
+sym_1_3213: la $2, sym_1_3213
+.globl sym_1_3214
+sym_1_3214: la $2, sym_1_3214
+.globl sym_1_3215
+sym_1_3215: la $2, sym_1_3215
+.globl sym_1_3216
+sym_1_3216: la $2, sym_1_3216
+.globl sym_1_3217
+sym_1_3217: la $2, sym_1_3217
+.globl sym_1_3218
+sym_1_3218: la $2, sym_1_3218
+.globl sym_1_3219
+sym_1_3219: la $2, sym_1_3219
+.globl sym_1_3220
+sym_1_3220: la $2, sym_1_3220
+.globl sym_1_3221
+sym_1_3221: la $2, sym_1_3221
+.globl sym_1_3222
+sym_1_3222: la $2, sym_1_3222
+.globl sym_1_3223
+sym_1_3223: la $2, sym_1_3223
+.globl sym_1_3224
+sym_1_3224: la $2, sym_1_3224
+.globl sym_1_3225
+sym_1_3225: la $2, sym_1_3225
+.globl sym_1_3226
+sym_1_3226: la $2, sym_1_3226
+.globl sym_1_3227
+sym_1_3227: la $2, sym_1_3227
+.globl sym_1_3228
+sym_1_3228: la $2, sym_1_3228
+.globl sym_1_3229
+sym_1_3229: la $2, sym_1_3229
+.globl sym_1_3230
+sym_1_3230: la $2, sym_1_3230
+.globl sym_1_3231
+sym_1_3231: la $2, sym_1_3231
+.globl sym_1_3232
+sym_1_3232: la $2, sym_1_3232
+.globl sym_1_3233
+sym_1_3233: la $2, sym_1_3233
+.globl sym_1_3234
+sym_1_3234: la $2, sym_1_3234
+.globl sym_1_3235
+sym_1_3235: la $2, sym_1_3235
+.globl sym_1_3236
+sym_1_3236: la $2, sym_1_3236
+.globl sym_1_3237
+sym_1_3237: la $2, sym_1_3237
+.globl sym_1_3238
+sym_1_3238: la $2, sym_1_3238
+.globl sym_1_3239
+sym_1_3239: la $2, sym_1_3239
+.globl sym_1_3240
+sym_1_3240: la $2, sym_1_3240
+.globl sym_1_3241
+sym_1_3241: la $2, sym_1_3241
+.globl sym_1_3242
+sym_1_3242: la $2, sym_1_3242
+.globl sym_1_3243
+sym_1_3243: la $2, sym_1_3243
+.globl sym_1_3244
+sym_1_3244: la $2, sym_1_3244
+.globl sym_1_3245
+sym_1_3245: la $2, sym_1_3245
+.globl sym_1_3246
+sym_1_3246: la $2, sym_1_3246
+.globl sym_1_3247
+sym_1_3247: la $2, sym_1_3247
+.globl sym_1_3248
+sym_1_3248: la $2, sym_1_3248
+.globl sym_1_3249
+sym_1_3249: la $2, sym_1_3249
+.globl sym_1_3250
+sym_1_3250: la $2, sym_1_3250
+.globl sym_1_3251
+sym_1_3251: la $2, sym_1_3251
+.globl sym_1_3252
+sym_1_3252: la $2, sym_1_3252
+.globl sym_1_3253
+sym_1_3253: la $2, sym_1_3253
+.globl sym_1_3254
+sym_1_3254: la $2, sym_1_3254
+.globl sym_1_3255
+sym_1_3255: la $2, sym_1_3255
+.globl sym_1_3256
+sym_1_3256: la $2, sym_1_3256
+.globl sym_1_3257
+sym_1_3257: la $2, sym_1_3257
+.globl sym_1_3258
+sym_1_3258: la $2, sym_1_3258
+.globl sym_1_3259
+sym_1_3259: la $2, sym_1_3259
+.globl sym_1_3260
+sym_1_3260: la $2, sym_1_3260
+.globl sym_1_3261
+sym_1_3261: la $2, sym_1_3261
+.globl sym_1_3262
+sym_1_3262: la $2, sym_1_3262
+.globl sym_1_3263
+sym_1_3263: la $2, sym_1_3263
+.globl sym_1_3264
+sym_1_3264: la $2, sym_1_3264
+.globl sym_1_3265
+sym_1_3265: la $2, sym_1_3265
+.globl sym_1_3266
+sym_1_3266: la $2, sym_1_3266
+.globl sym_1_3267
+sym_1_3267: la $2, sym_1_3267
+.globl sym_1_3268
+sym_1_3268: la $2, sym_1_3268
+.globl sym_1_3269
+sym_1_3269: la $2, sym_1_3269
+.globl sym_1_3270
+sym_1_3270: la $2, sym_1_3270
+.globl sym_1_3271
+sym_1_3271: la $2, sym_1_3271
+.globl sym_1_3272
+sym_1_3272: la $2, sym_1_3272
+.globl sym_1_3273
+sym_1_3273: la $2, sym_1_3273
+.globl sym_1_3274
+sym_1_3274: la $2, sym_1_3274
+.globl sym_1_3275
+sym_1_3275: la $2, sym_1_3275
+.globl sym_1_3276
+sym_1_3276: la $2, sym_1_3276
+.globl sym_1_3277
+sym_1_3277: la $2, sym_1_3277
+.globl sym_1_3278
+sym_1_3278: la $2, sym_1_3278
+.globl sym_1_3279
+sym_1_3279: la $2, sym_1_3279
+.globl sym_1_3280
+sym_1_3280: la $2, sym_1_3280
+.globl sym_1_3281
+sym_1_3281: la $2, sym_1_3281
+.globl sym_1_3282
+sym_1_3282: la $2, sym_1_3282
+.globl sym_1_3283
+sym_1_3283: la $2, sym_1_3283
+.globl sym_1_3284
+sym_1_3284: la $2, sym_1_3284
+.globl sym_1_3285
+sym_1_3285: la $2, sym_1_3285
+.globl sym_1_3286
+sym_1_3286: la $2, sym_1_3286
+.globl sym_1_3287
+sym_1_3287: la $2, sym_1_3287
+.globl sym_1_3288
+sym_1_3288: la $2, sym_1_3288
+.globl sym_1_3289
+sym_1_3289: la $2, sym_1_3289
+.globl sym_1_3290
+sym_1_3290: la $2, sym_1_3290
+.globl sym_1_3291
+sym_1_3291: la $2, sym_1_3291
+.globl sym_1_3292
+sym_1_3292: la $2, sym_1_3292
+.globl sym_1_3293
+sym_1_3293: la $2, sym_1_3293
+.globl sym_1_3294
+sym_1_3294: la $2, sym_1_3294
+.globl sym_1_3295
+sym_1_3295: la $2, sym_1_3295
+.globl sym_1_3296
+sym_1_3296: la $2, sym_1_3296
+.globl sym_1_3297
+sym_1_3297: la $2, sym_1_3297
+.globl sym_1_3298
+sym_1_3298: la $2, sym_1_3298
+.globl sym_1_3299
+sym_1_3299: la $2, sym_1_3299
+.globl sym_1_3300
+sym_1_3300: la $2, sym_1_3300
+.globl sym_1_3301
+sym_1_3301: la $2, sym_1_3301
+.globl sym_1_3302
+sym_1_3302: la $2, sym_1_3302
+.globl sym_1_3303
+sym_1_3303: la $2, sym_1_3303
+.globl sym_1_3304
+sym_1_3304: la $2, sym_1_3304
+.globl sym_1_3305
+sym_1_3305: la $2, sym_1_3305
+.globl sym_1_3306
+sym_1_3306: la $2, sym_1_3306
+.globl sym_1_3307
+sym_1_3307: la $2, sym_1_3307
+.globl sym_1_3308
+sym_1_3308: la $2, sym_1_3308
+.globl sym_1_3309
+sym_1_3309: la $2, sym_1_3309
+.globl sym_1_3310
+sym_1_3310: la $2, sym_1_3310
+.globl sym_1_3311
+sym_1_3311: la $2, sym_1_3311
+.globl sym_1_3312
+sym_1_3312: la $2, sym_1_3312
+.globl sym_1_3313
+sym_1_3313: la $2, sym_1_3313
+.globl sym_1_3314
+sym_1_3314: la $2, sym_1_3314
+.globl sym_1_3315
+sym_1_3315: la $2, sym_1_3315
+.globl sym_1_3316
+sym_1_3316: la $2, sym_1_3316
+.globl sym_1_3317
+sym_1_3317: la $2, sym_1_3317
+.globl sym_1_3318
+sym_1_3318: la $2, sym_1_3318
+.globl sym_1_3319
+sym_1_3319: la $2, sym_1_3319
+.globl sym_1_3320
+sym_1_3320: la $2, sym_1_3320
+.globl sym_1_3321
+sym_1_3321: la $2, sym_1_3321
+.globl sym_1_3322
+sym_1_3322: la $2, sym_1_3322
+.globl sym_1_3323
+sym_1_3323: la $2, sym_1_3323
+.globl sym_1_3324
+sym_1_3324: la $2, sym_1_3324
+.globl sym_1_3325
+sym_1_3325: la $2, sym_1_3325
+.globl sym_1_3326
+sym_1_3326: la $2, sym_1_3326
+.globl sym_1_3327
+sym_1_3327: la $2, sym_1_3327
+.globl sym_1_3328
+sym_1_3328: la $2, sym_1_3328
+.globl sym_1_3329
+sym_1_3329: la $2, sym_1_3329
+.globl sym_1_3330
+sym_1_3330: la $2, sym_1_3330
+.globl sym_1_3331
+sym_1_3331: la $2, sym_1_3331
+.globl sym_1_3332
+sym_1_3332: la $2, sym_1_3332
+.globl sym_1_3333
+sym_1_3333: la $2, sym_1_3333
+.globl sym_1_3334
+sym_1_3334: la $2, sym_1_3334
+.globl sym_1_3335
+sym_1_3335: la $2, sym_1_3335
+.globl sym_1_3336
+sym_1_3336: la $2, sym_1_3336
+.globl sym_1_3337
+sym_1_3337: la $2, sym_1_3337
+.globl sym_1_3338
+sym_1_3338: la $2, sym_1_3338
+.globl sym_1_3339
+sym_1_3339: la $2, sym_1_3339
+.globl sym_1_3340
+sym_1_3340: la $2, sym_1_3340
+.globl sym_1_3341
+sym_1_3341: la $2, sym_1_3341
+.globl sym_1_3342
+sym_1_3342: la $2, sym_1_3342
+.globl sym_1_3343
+sym_1_3343: la $2, sym_1_3343
+.globl sym_1_3344
+sym_1_3344: la $2, sym_1_3344
+.globl sym_1_3345
+sym_1_3345: la $2, sym_1_3345
+.globl sym_1_3346
+sym_1_3346: la $2, sym_1_3346
+.globl sym_1_3347
+sym_1_3347: la $2, sym_1_3347
+.globl sym_1_3348
+sym_1_3348: la $2, sym_1_3348
+.globl sym_1_3349
+sym_1_3349: la $2, sym_1_3349
+.globl sym_1_3350
+sym_1_3350: la $2, sym_1_3350
+.globl sym_1_3351
+sym_1_3351: la $2, sym_1_3351
+.globl sym_1_3352
+sym_1_3352: la $2, sym_1_3352
+.globl sym_1_3353
+sym_1_3353: la $2, sym_1_3353
+.globl sym_1_3354
+sym_1_3354: la $2, sym_1_3354
+.globl sym_1_3355
+sym_1_3355: la $2, sym_1_3355
+.globl sym_1_3356
+sym_1_3356: la $2, sym_1_3356
+.globl sym_1_3357
+sym_1_3357: la $2, sym_1_3357
+.globl sym_1_3358
+sym_1_3358: la $2, sym_1_3358
+.globl sym_1_3359
+sym_1_3359: la $2, sym_1_3359
+.globl sym_1_3360
+sym_1_3360: la $2, sym_1_3360
+.globl sym_1_3361
+sym_1_3361: la $2, sym_1_3361
+.globl sym_1_3362
+sym_1_3362: la $2, sym_1_3362
+.globl sym_1_3363
+sym_1_3363: la $2, sym_1_3363
+.globl sym_1_3364
+sym_1_3364: la $2, sym_1_3364
+.globl sym_1_3365
+sym_1_3365: la $2, sym_1_3365
+.globl sym_1_3366
+sym_1_3366: la $2, sym_1_3366
+.globl sym_1_3367
+sym_1_3367: la $2, sym_1_3367
+.globl sym_1_3368
+sym_1_3368: la $2, sym_1_3368
+.globl sym_1_3369
+sym_1_3369: la $2, sym_1_3369
+.globl sym_1_3370
+sym_1_3370: la $2, sym_1_3370
+.globl sym_1_3371
+sym_1_3371: la $2, sym_1_3371
+.globl sym_1_3372
+sym_1_3372: la $2, sym_1_3372
+.globl sym_1_3373
+sym_1_3373: la $2, sym_1_3373
+.globl sym_1_3374
+sym_1_3374: la $2, sym_1_3374
+.globl sym_1_3375
+sym_1_3375: la $2, sym_1_3375
+.globl sym_1_3376
+sym_1_3376: la $2, sym_1_3376
+.globl sym_1_3377
+sym_1_3377: la $2, sym_1_3377
+.globl sym_1_3378
+sym_1_3378: la $2, sym_1_3378
+.globl sym_1_3379
+sym_1_3379: la $2, sym_1_3379
+.globl sym_1_3380
+sym_1_3380: la $2, sym_1_3380
+.globl sym_1_3381
+sym_1_3381: la $2, sym_1_3381
+.globl sym_1_3382
+sym_1_3382: la $2, sym_1_3382
+.globl sym_1_3383
+sym_1_3383: la $2, sym_1_3383
+.globl sym_1_3384
+sym_1_3384: la $2, sym_1_3384
+.globl sym_1_3385
+sym_1_3385: la $2, sym_1_3385
+.globl sym_1_3386
+sym_1_3386: la $2, sym_1_3386
+.globl sym_1_3387
+sym_1_3387: la $2, sym_1_3387
+.globl sym_1_3388
+sym_1_3388: la $2, sym_1_3388
+.globl sym_1_3389
+sym_1_3389: la $2, sym_1_3389
+.globl sym_1_3390
+sym_1_3390: la $2, sym_1_3390
+.globl sym_1_3391
+sym_1_3391: la $2, sym_1_3391
+.globl sym_1_3392
+sym_1_3392: la $2, sym_1_3392
+.globl sym_1_3393
+sym_1_3393: la $2, sym_1_3393
+.globl sym_1_3394
+sym_1_3394: la $2, sym_1_3394
+.globl sym_1_3395
+sym_1_3395: la $2, sym_1_3395
+.globl sym_1_3396
+sym_1_3396: la $2, sym_1_3396
+.globl sym_1_3397
+sym_1_3397: la $2, sym_1_3397
+.globl sym_1_3398
+sym_1_3398: la $2, sym_1_3398
+.globl sym_1_3399
+sym_1_3399: la $2, sym_1_3399
+.globl sym_1_3400
+sym_1_3400: la $2, sym_1_3400
+.globl sym_1_3401
+sym_1_3401: la $2, sym_1_3401
+.globl sym_1_3402
+sym_1_3402: la $2, sym_1_3402
+.globl sym_1_3403
+sym_1_3403: la $2, sym_1_3403
+.globl sym_1_3404
+sym_1_3404: la $2, sym_1_3404
+.globl sym_1_3405
+sym_1_3405: la $2, sym_1_3405
+.globl sym_1_3406
+sym_1_3406: la $2, sym_1_3406
+.globl sym_1_3407
+sym_1_3407: la $2, sym_1_3407
+.globl sym_1_3408
+sym_1_3408: la $2, sym_1_3408
+.globl sym_1_3409
+sym_1_3409: la $2, sym_1_3409
+.globl sym_1_3410
+sym_1_3410: la $2, sym_1_3410
+.globl sym_1_3411
+sym_1_3411: la $2, sym_1_3411
+.globl sym_1_3412
+sym_1_3412: la $2, sym_1_3412
+.globl sym_1_3413
+sym_1_3413: la $2, sym_1_3413
+.globl sym_1_3414
+sym_1_3414: la $2, sym_1_3414
+.globl sym_1_3415
+sym_1_3415: la $2, sym_1_3415
+.globl sym_1_3416
+sym_1_3416: la $2, sym_1_3416
+.globl sym_1_3417
+sym_1_3417: la $2, sym_1_3417
+.globl sym_1_3418
+sym_1_3418: la $2, sym_1_3418
+.globl sym_1_3419
+sym_1_3419: la $2, sym_1_3419
+.globl sym_1_3420
+sym_1_3420: la $2, sym_1_3420
+.globl sym_1_3421
+sym_1_3421: la $2, sym_1_3421
+.globl sym_1_3422
+sym_1_3422: la $2, sym_1_3422
+.globl sym_1_3423
+sym_1_3423: la $2, sym_1_3423
+.globl sym_1_3424
+sym_1_3424: la $2, sym_1_3424
+.globl sym_1_3425
+sym_1_3425: la $2, sym_1_3425
+.globl sym_1_3426
+sym_1_3426: la $2, sym_1_3426
+.globl sym_1_3427
+sym_1_3427: la $2, sym_1_3427
+.globl sym_1_3428
+sym_1_3428: la $2, sym_1_3428
+.globl sym_1_3429
+sym_1_3429: la $2, sym_1_3429
+.globl sym_1_3430
+sym_1_3430: la $2, sym_1_3430
+.globl sym_1_3431
+sym_1_3431: la $2, sym_1_3431
+.globl sym_1_3432
+sym_1_3432: la $2, sym_1_3432
+.globl sym_1_3433
+sym_1_3433: la $2, sym_1_3433
+.globl sym_1_3434
+sym_1_3434: la $2, sym_1_3434
+.globl sym_1_3435
+sym_1_3435: la $2, sym_1_3435
+.globl sym_1_3436
+sym_1_3436: la $2, sym_1_3436
+.globl sym_1_3437
+sym_1_3437: la $2, sym_1_3437
+.globl sym_1_3438
+sym_1_3438: la $2, sym_1_3438
+.globl sym_1_3439
+sym_1_3439: la $2, sym_1_3439
+.globl sym_1_3440
+sym_1_3440: la $2, sym_1_3440
+.globl sym_1_3441
+sym_1_3441: la $2, sym_1_3441
+.globl sym_1_3442
+sym_1_3442: la $2, sym_1_3442
+.globl sym_1_3443
+sym_1_3443: la $2, sym_1_3443
+.globl sym_1_3444
+sym_1_3444: la $2, sym_1_3444
+.globl sym_1_3445
+sym_1_3445: la $2, sym_1_3445
+.globl sym_1_3446
+sym_1_3446: la $2, sym_1_3446
+.globl sym_1_3447
+sym_1_3447: la $2, sym_1_3447
+.globl sym_1_3448
+sym_1_3448: la $2, sym_1_3448
+.globl sym_1_3449
+sym_1_3449: la $2, sym_1_3449
+.globl sym_1_3450
+sym_1_3450: la $2, sym_1_3450
+.globl sym_1_3451
+sym_1_3451: la $2, sym_1_3451
+.globl sym_1_3452
+sym_1_3452: la $2, sym_1_3452
+.globl sym_1_3453
+sym_1_3453: la $2, sym_1_3453
+.globl sym_1_3454
+sym_1_3454: la $2, sym_1_3454
+.globl sym_1_3455
+sym_1_3455: la $2, sym_1_3455
+.globl sym_1_3456
+sym_1_3456: la $2, sym_1_3456
+.globl sym_1_3457
+sym_1_3457: la $2, sym_1_3457
+.globl sym_1_3458
+sym_1_3458: la $2, sym_1_3458
+.globl sym_1_3459
+sym_1_3459: la $2, sym_1_3459
+.globl sym_1_3460
+sym_1_3460: la $2, sym_1_3460
+.globl sym_1_3461
+sym_1_3461: la $2, sym_1_3461
+.globl sym_1_3462
+sym_1_3462: la $2, sym_1_3462
+.globl sym_1_3463
+sym_1_3463: la $2, sym_1_3463
+.globl sym_1_3464
+sym_1_3464: la $2, sym_1_3464
+.globl sym_1_3465
+sym_1_3465: la $2, sym_1_3465
+.globl sym_1_3466
+sym_1_3466: la $2, sym_1_3466
+.globl sym_1_3467
+sym_1_3467: la $2, sym_1_3467
+.globl sym_1_3468
+sym_1_3468: la $2, sym_1_3468
+.globl sym_1_3469
+sym_1_3469: la $2, sym_1_3469
+.globl sym_1_3470
+sym_1_3470: la $2, sym_1_3470
+.globl sym_1_3471
+sym_1_3471: la $2, sym_1_3471
+.globl sym_1_3472
+sym_1_3472: la $2, sym_1_3472
+.globl sym_1_3473
+sym_1_3473: la $2, sym_1_3473
+.globl sym_1_3474
+sym_1_3474: la $2, sym_1_3474
+.globl sym_1_3475
+sym_1_3475: la $2, sym_1_3475
+.globl sym_1_3476
+sym_1_3476: la $2, sym_1_3476
+.globl sym_1_3477
+sym_1_3477: la $2, sym_1_3477
+.globl sym_1_3478
+sym_1_3478: la $2, sym_1_3478
+.globl sym_1_3479
+sym_1_3479: la $2, sym_1_3479
+.globl sym_1_3480
+sym_1_3480: la $2, sym_1_3480
+.globl sym_1_3481
+sym_1_3481: la $2, sym_1_3481
+.globl sym_1_3482
+sym_1_3482: la $2, sym_1_3482
+.globl sym_1_3483
+sym_1_3483: la $2, sym_1_3483
+.globl sym_1_3484
+sym_1_3484: la $2, sym_1_3484
+.globl sym_1_3485
+sym_1_3485: la $2, sym_1_3485
+.globl sym_1_3486
+sym_1_3486: la $2, sym_1_3486
+.globl sym_1_3487
+sym_1_3487: la $2, sym_1_3487
+.globl sym_1_3488
+sym_1_3488: la $2, sym_1_3488
+.globl sym_1_3489
+sym_1_3489: la $2, sym_1_3489
+.globl sym_1_3490
+sym_1_3490: la $2, sym_1_3490
+.globl sym_1_3491
+sym_1_3491: la $2, sym_1_3491
+.globl sym_1_3492
+sym_1_3492: la $2, sym_1_3492
+.globl sym_1_3493
+sym_1_3493: la $2, sym_1_3493
+.globl sym_1_3494
+sym_1_3494: la $2, sym_1_3494
+.globl sym_1_3495
+sym_1_3495: la $2, sym_1_3495
+.globl sym_1_3496
+sym_1_3496: la $2, sym_1_3496
+.globl sym_1_3497
+sym_1_3497: la $2, sym_1_3497
+.globl sym_1_3498
+sym_1_3498: la $2, sym_1_3498
+.globl sym_1_3499
+sym_1_3499: la $2, sym_1_3499
+.globl sym_1_3500
+sym_1_3500: la $2, sym_1_3500
+.globl sym_1_3501
+sym_1_3501: la $2, sym_1_3501
+.globl sym_1_3502
+sym_1_3502: la $2, sym_1_3502
+.globl sym_1_3503
+sym_1_3503: la $2, sym_1_3503
+.globl sym_1_3504
+sym_1_3504: la $2, sym_1_3504
+.globl sym_1_3505
+sym_1_3505: la $2, sym_1_3505
+.globl sym_1_3506
+sym_1_3506: la $2, sym_1_3506
+.globl sym_1_3507
+sym_1_3507: la $2, sym_1_3507
+.globl sym_1_3508
+sym_1_3508: la $2, sym_1_3508
+.globl sym_1_3509
+sym_1_3509: la $2, sym_1_3509
+.globl sym_1_3510
+sym_1_3510: la $2, sym_1_3510
+.globl sym_1_3511
+sym_1_3511: la $2, sym_1_3511
+.globl sym_1_3512
+sym_1_3512: la $2, sym_1_3512
+.globl sym_1_3513
+sym_1_3513: la $2, sym_1_3513
+.globl sym_1_3514
+sym_1_3514: la $2, sym_1_3514
+.globl sym_1_3515
+sym_1_3515: la $2, sym_1_3515
+.globl sym_1_3516
+sym_1_3516: la $2, sym_1_3516
+.globl sym_1_3517
+sym_1_3517: la $2, sym_1_3517
+.globl sym_1_3518
+sym_1_3518: la $2, sym_1_3518
+.globl sym_1_3519
+sym_1_3519: la $2, sym_1_3519
+.globl sym_1_3520
+sym_1_3520: la $2, sym_1_3520
+.globl sym_1_3521
+sym_1_3521: la $2, sym_1_3521
+.globl sym_1_3522
+sym_1_3522: la $2, sym_1_3522
+.globl sym_1_3523
+sym_1_3523: la $2, sym_1_3523
+.globl sym_1_3524
+sym_1_3524: la $2, sym_1_3524
+.globl sym_1_3525
+sym_1_3525: la $2, sym_1_3525
+.globl sym_1_3526
+sym_1_3526: la $2, sym_1_3526
+.globl sym_1_3527
+sym_1_3527: la $2, sym_1_3527
+.globl sym_1_3528
+sym_1_3528: la $2, sym_1_3528
+.globl sym_1_3529
+sym_1_3529: la $2, sym_1_3529
+.globl sym_1_3530
+sym_1_3530: la $2, sym_1_3530
+.globl sym_1_3531
+sym_1_3531: la $2, sym_1_3531
+.globl sym_1_3532
+sym_1_3532: la $2, sym_1_3532
+.globl sym_1_3533
+sym_1_3533: la $2, sym_1_3533
+.globl sym_1_3534
+sym_1_3534: la $2, sym_1_3534
+.globl sym_1_3535
+sym_1_3535: la $2, sym_1_3535
+.globl sym_1_3536
+sym_1_3536: la $2, sym_1_3536
+.globl sym_1_3537
+sym_1_3537: la $2, sym_1_3537
+.globl sym_1_3538
+sym_1_3538: la $2, sym_1_3538
+.globl sym_1_3539
+sym_1_3539: la $2, sym_1_3539
+.globl sym_1_3540
+sym_1_3540: la $2, sym_1_3540
+.globl sym_1_3541
+sym_1_3541: la $2, sym_1_3541
+.globl sym_1_3542
+sym_1_3542: la $2, sym_1_3542
+.globl sym_1_3543
+sym_1_3543: la $2, sym_1_3543
+.globl sym_1_3544
+sym_1_3544: la $2, sym_1_3544
+.globl sym_1_3545
+sym_1_3545: la $2, sym_1_3545
+.globl sym_1_3546
+sym_1_3546: la $2, sym_1_3546
+.globl sym_1_3547
+sym_1_3547: la $2, sym_1_3547
+.globl sym_1_3548
+sym_1_3548: la $2, sym_1_3548
+.globl sym_1_3549
+sym_1_3549: la $2, sym_1_3549
+.globl sym_1_3550
+sym_1_3550: la $2, sym_1_3550
+.globl sym_1_3551
+sym_1_3551: la $2, sym_1_3551
+.globl sym_1_3552
+sym_1_3552: la $2, sym_1_3552
+.globl sym_1_3553
+sym_1_3553: la $2, sym_1_3553
+.globl sym_1_3554
+sym_1_3554: la $2, sym_1_3554
+.globl sym_1_3555
+sym_1_3555: la $2, sym_1_3555
+.globl sym_1_3556
+sym_1_3556: la $2, sym_1_3556
+.globl sym_1_3557
+sym_1_3557: la $2, sym_1_3557
+.globl sym_1_3558
+sym_1_3558: la $2, sym_1_3558
+.globl sym_1_3559
+sym_1_3559: la $2, sym_1_3559
+.globl sym_1_3560
+sym_1_3560: la $2, sym_1_3560
+.globl sym_1_3561
+sym_1_3561: la $2, sym_1_3561
+.globl sym_1_3562
+sym_1_3562: la $2, sym_1_3562
+.globl sym_1_3563
+sym_1_3563: la $2, sym_1_3563
+.globl sym_1_3564
+sym_1_3564: la $2, sym_1_3564
+.globl sym_1_3565
+sym_1_3565: la $2, sym_1_3565
+.globl sym_1_3566
+sym_1_3566: la $2, sym_1_3566
+.globl sym_1_3567
+sym_1_3567: la $2, sym_1_3567
+.globl sym_1_3568
+sym_1_3568: la $2, sym_1_3568
+.globl sym_1_3569
+sym_1_3569: la $2, sym_1_3569
+.globl sym_1_3570
+sym_1_3570: la $2, sym_1_3570
+.globl sym_1_3571
+sym_1_3571: la $2, sym_1_3571
+.globl sym_1_3572
+sym_1_3572: la $2, sym_1_3572
+.globl sym_1_3573
+sym_1_3573: la $2, sym_1_3573
+.globl sym_1_3574
+sym_1_3574: la $2, sym_1_3574
+.globl sym_1_3575
+sym_1_3575: la $2, sym_1_3575
+.globl sym_1_3576
+sym_1_3576: la $2, sym_1_3576
+.globl sym_1_3577
+sym_1_3577: la $2, sym_1_3577
+.globl sym_1_3578
+sym_1_3578: la $2, sym_1_3578
+.globl sym_1_3579
+sym_1_3579: la $2, sym_1_3579
+.globl sym_1_3580
+sym_1_3580: la $2, sym_1_3580
+.globl sym_1_3581
+sym_1_3581: la $2, sym_1_3581
+.globl sym_1_3582
+sym_1_3582: la $2, sym_1_3582
+.globl sym_1_3583
+sym_1_3583: la $2, sym_1_3583
+.globl sym_1_3584
+sym_1_3584: la $2, sym_1_3584
+.globl sym_1_3585
+sym_1_3585: la $2, sym_1_3585
+.globl sym_1_3586
+sym_1_3586: la $2, sym_1_3586
+.globl sym_1_3587
+sym_1_3587: la $2, sym_1_3587
+.globl sym_1_3588
+sym_1_3588: la $2, sym_1_3588
+.globl sym_1_3589
+sym_1_3589: la $2, sym_1_3589
+.globl sym_1_3590
+sym_1_3590: la $2, sym_1_3590
+.globl sym_1_3591
+sym_1_3591: la $2, sym_1_3591
+.globl sym_1_3592
+sym_1_3592: la $2, sym_1_3592
+.globl sym_1_3593
+sym_1_3593: la $2, sym_1_3593
+.globl sym_1_3594
+sym_1_3594: la $2, sym_1_3594
+.globl sym_1_3595
+sym_1_3595: la $2, sym_1_3595
+.globl sym_1_3596
+sym_1_3596: la $2, sym_1_3596
+.globl sym_1_3597
+sym_1_3597: la $2, sym_1_3597
+.globl sym_1_3598
+sym_1_3598: la $2, sym_1_3598
+.globl sym_1_3599
+sym_1_3599: la $2, sym_1_3599
+.globl sym_1_3600
+sym_1_3600: la $2, sym_1_3600
+.globl sym_1_3601
+sym_1_3601: la $2, sym_1_3601
+.globl sym_1_3602
+sym_1_3602: la $2, sym_1_3602
+.globl sym_1_3603
+sym_1_3603: la $2, sym_1_3603
+.globl sym_1_3604
+sym_1_3604: la $2, sym_1_3604
+.globl sym_1_3605
+sym_1_3605: la $2, sym_1_3605
+.globl sym_1_3606
+sym_1_3606: la $2, sym_1_3606
+.globl sym_1_3607
+sym_1_3607: la $2, sym_1_3607
+.globl sym_1_3608
+sym_1_3608: la $2, sym_1_3608
+.globl sym_1_3609
+sym_1_3609: la $2, sym_1_3609
+.globl sym_1_3610
+sym_1_3610: la $2, sym_1_3610
+.globl sym_1_3611
+sym_1_3611: la $2, sym_1_3611
+.globl sym_1_3612
+sym_1_3612: la $2, sym_1_3612
+.globl sym_1_3613
+sym_1_3613: la $2, sym_1_3613
+.globl sym_1_3614
+sym_1_3614: la $2, sym_1_3614
+.globl sym_1_3615
+sym_1_3615: la $2, sym_1_3615
+.globl sym_1_3616
+sym_1_3616: la $2, sym_1_3616
+.globl sym_1_3617
+sym_1_3617: la $2, sym_1_3617
+.globl sym_1_3618
+sym_1_3618: la $2, sym_1_3618
+.globl sym_1_3619
+sym_1_3619: la $2, sym_1_3619
+.globl sym_1_3620
+sym_1_3620: la $2, sym_1_3620
+.globl sym_1_3621
+sym_1_3621: la $2, sym_1_3621
+.globl sym_1_3622
+sym_1_3622: la $2, sym_1_3622
+.globl sym_1_3623
+sym_1_3623: la $2, sym_1_3623
+.globl sym_1_3624
+sym_1_3624: la $2, sym_1_3624
+.globl sym_1_3625
+sym_1_3625: la $2, sym_1_3625
+.globl sym_1_3626
+sym_1_3626: la $2, sym_1_3626
+.globl sym_1_3627
+sym_1_3627: la $2, sym_1_3627
+.globl sym_1_3628
+sym_1_3628: la $2, sym_1_3628
+.globl sym_1_3629
+sym_1_3629: la $2, sym_1_3629
+.globl sym_1_3630
+sym_1_3630: la $2, sym_1_3630
+.globl sym_1_3631
+sym_1_3631: la $2, sym_1_3631
+.globl sym_1_3632
+sym_1_3632: la $2, sym_1_3632
+.globl sym_1_3633
+sym_1_3633: la $2, sym_1_3633
+.globl sym_1_3634
+sym_1_3634: la $2, sym_1_3634
+.globl sym_1_3635
+sym_1_3635: la $2, sym_1_3635
+.globl sym_1_3636
+sym_1_3636: la $2, sym_1_3636
+.globl sym_1_3637
+sym_1_3637: la $2, sym_1_3637
+.globl sym_1_3638
+sym_1_3638: la $2, sym_1_3638
+.globl sym_1_3639
+sym_1_3639: la $2, sym_1_3639
+.globl sym_1_3640
+sym_1_3640: la $2, sym_1_3640
+.globl sym_1_3641
+sym_1_3641: la $2, sym_1_3641
+.globl sym_1_3642
+sym_1_3642: la $2, sym_1_3642
+.globl sym_1_3643
+sym_1_3643: la $2, sym_1_3643
+.globl sym_1_3644
+sym_1_3644: la $2, sym_1_3644
+.globl sym_1_3645
+sym_1_3645: la $2, sym_1_3645
+.globl sym_1_3646
+sym_1_3646: la $2, sym_1_3646
+.globl sym_1_3647
+sym_1_3647: la $2, sym_1_3647
+.globl sym_1_3648
+sym_1_3648: la $2, sym_1_3648
+.globl sym_1_3649
+sym_1_3649: la $2, sym_1_3649
+.globl sym_1_3650
+sym_1_3650: la $2, sym_1_3650
+.globl sym_1_3651
+sym_1_3651: la $2, sym_1_3651
+.globl sym_1_3652
+sym_1_3652: la $2, sym_1_3652
+.globl sym_1_3653
+sym_1_3653: la $2, sym_1_3653
+.globl sym_1_3654
+sym_1_3654: la $2, sym_1_3654
+.globl sym_1_3655
+sym_1_3655: la $2, sym_1_3655
+.globl sym_1_3656
+sym_1_3656: la $2, sym_1_3656
+.globl sym_1_3657
+sym_1_3657: la $2, sym_1_3657
+.globl sym_1_3658
+sym_1_3658: la $2, sym_1_3658
+.globl sym_1_3659
+sym_1_3659: la $2, sym_1_3659
+.globl sym_1_3660
+sym_1_3660: la $2, sym_1_3660
+.globl sym_1_3661
+sym_1_3661: la $2, sym_1_3661
+.globl sym_1_3662
+sym_1_3662: la $2, sym_1_3662
+.globl sym_1_3663
+sym_1_3663: la $2, sym_1_3663
+.globl sym_1_3664
+sym_1_3664: la $2, sym_1_3664
+.globl sym_1_3665
+sym_1_3665: la $2, sym_1_3665
+.globl sym_1_3666
+sym_1_3666: la $2, sym_1_3666
+.globl sym_1_3667
+sym_1_3667: la $2, sym_1_3667
+.globl sym_1_3668
+sym_1_3668: la $2, sym_1_3668
+.globl sym_1_3669
+sym_1_3669: la $2, sym_1_3669
+.globl sym_1_3670
+sym_1_3670: la $2, sym_1_3670
+.globl sym_1_3671
+sym_1_3671: la $2, sym_1_3671
+.globl sym_1_3672
+sym_1_3672: la $2, sym_1_3672
+.globl sym_1_3673
+sym_1_3673: la $2, sym_1_3673
+.globl sym_1_3674
+sym_1_3674: la $2, sym_1_3674
+.globl sym_1_3675
+sym_1_3675: la $2, sym_1_3675
+.globl sym_1_3676
+sym_1_3676: la $2, sym_1_3676
+.globl sym_1_3677
+sym_1_3677: la $2, sym_1_3677
+.globl sym_1_3678
+sym_1_3678: la $2, sym_1_3678
+.globl sym_1_3679
+sym_1_3679: la $2, sym_1_3679
+.globl sym_1_3680
+sym_1_3680: la $2, sym_1_3680
+.globl sym_1_3681
+sym_1_3681: la $2, sym_1_3681
+.globl sym_1_3682
+sym_1_3682: la $2, sym_1_3682
+.globl sym_1_3683
+sym_1_3683: la $2, sym_1_3683
+.globl sym_1_3684
+sym_1_3684: la $2, sym_1_3684
+.globl sym_1_3685
+sym_1_3685: la $2, sym_1_3685
+.globl sym_1_3686
+sym_1_3686: la $2, sym_1_3686
+.globl sym_1_3687
+sym_1_3687: la $2, sym_1_3687
+.globl sym_1_3688
+sym_1_3688: la $2, sym_1_3688
+.globl sym_1_3689
+sym_1_3689: la $2, sym_1_3689
+.globl sym_1_3690
+sym_1_3690: la $2, sym_1_3690
+.globl sym_1_3691
+sym_1_3691: la $2, sym_1_3691
+.globl sym_1_3692
+sym_1_3692: la $2, sym_1_3692
+.globl sym_1_3693
+sym_1_3693: la $2, sym_1_3693
+.globl sym_1_3694
+sym_1_3694: la $2, sym_1_3694
+.globl sym_1_3695
+sym_1_3695: la $2, sym_1_3695
+.globl sym_1_3696
+sym_1_3696: la $2, sym_1_3696
+.globl sym_1_3697
+sym_1_3697: la $2, sym_1_3697
+.globl sym_1_3698
+sym_1_3698: la $2, sym_1_3698
+.globl sym_1_3699
+sym_1_3699: la $2, sym_1_3699
+.globl sym_1_3700
+sym_1_3700: la $2, sym_1_3700
+.globl sym_1_3701
+sym_1_3701: la $2, sym_1_3701
+.globl sym_1_3702
+sym_1_3702: la $2, sym_1_3702
+.globl sym_1_3703
+sym_1_3703: la $2, sym_1_3703
+.globl sym_1_3704
+sym_1_3704: la $2, sym_1_3704
+.globl sym_1_3705
+sym_1_3705: la $2, sym_1_3705
+.globl sym_1_3706
+sym_1_3706: la $2, sym_1_3706
+.globl sym_1_3707
+sym_1_3707: la $2, sym_1_3707
+.globl sym_1_3708
+sym_1_3708: la $2, sym_1_3708
+.globl sym_1_3709
+sym_1_3709: la $2, sym_1_3709
+.globl sym_1_3710
+sym_1_3710: la $2, sym_1_3710
+.globl sym_1_3711
+sym_1_3711: la $2, sym_1_3711
+.globl sym_1_3712
+sym_1_3712: la $2, sym_1_3712
+.globl sym_1_3713
+sym_1_3713: la $2, sym_1_3713
+.globl sym_1_3714
+sym_1_3714: la $2, sym_1_3714
+.globl sym_1_3715
+sym_1_3715: la $2, sym_1_3715
+.globl sym_1_3716
+sym_1_3716: la $2, sym_1_3716
+.globl sym_1_3717
+sym_1_3717: la $2, sym_1_3717
+.globl sym_1_3718
+sym_1_3718: la $2, sym_1_3718
+.globl sym_1_3719
+sym_1_3719: la $2, sym_1_3719
+.globl sym_1_3720
+sym_1_3720: la $2, sym_1_3720
+.globl sym_1_3721
+sym_1_3721: la $2, sym_1_3721
+.globl sym_1_3722
+sym_1_3722: la $2, sym_1_3722
+.globl sym_1_3723
+sym_1_3723: la $2, sym_1_3723
+.globl sym_1_3724
+sym_1_3724: la $2, sym_1_3724
+.globl sym_1_3725
+sym_1_3725: la $2, sym_1_3725
+.globl sym_1_3726
+sym_1_3726: la $2, sym_1_3726
+.globl sym_1_3727
+sym_1_3727: la $2, sym_1_3727
+.globl sym_1_3728
+sym_1_3728: la $2, sym_1_3728
+.globl sym_1_3729
+sym_1_3729: la $2, sym_1_3729
+.globl sym_1_3730
+sym_1_3730: la $2, sym_1_3730
+.globl sym_1_3731
+sym_1_3731: la $2, sym_1_3731
+.globl sym_1_3732
+sym_1_3732: la $2, sym_1_3732
+.globl sym_1_3733
+sym_1_3733: la $2, sym_1_3733
+.globl sym_1_3734
+sym_1_3734: la $2, sym_1_3734
+.globl sym_1_3735
+sym_1_3735: la $2, sym_1_3735
+.globl sym_1_3736
+sym_1_3736: la $2, sym_1_3736
+.globl sym_1_3737
+sym_1_3737: la $2, sym_1_3737
+.globl sym_1_3738
+sym_1_3738: la $2, sym_1_3738
+.globl sym_1_3739
+sym_1_3739: la $2, sym_1_3739
+.globl sym_1_3740
+sym_1_3740: la $2, sym_1_3740
+.globl sym_1_3741
+sym_1_3741: la $2, sym_1_3741
+.globl sym_1_3742
+sym_1_3742: la $2, sym_1_3742
+.globl sym_1_3743
+sym_1_3743: la $2, sym_1_3743
+.globl sym_1_3744
+sym_1_3744: la $2, sym_1_3744
+.globl sym_1_3745
+sym_1_3745: la $2, sym_1_3745
+.globl sym_1_3746
+sym_1_3746: la $2, sym_1_3746
+.globl sym_1_3747
+sym_1_3747: la $2, sym_1_3747
+.globl sym_1_3748
+sym_1_3748: la $2, sym_1_3748
+.globl sym_1_3749
+sym_1_3749: la $2, sym_1_3749
+.globl sym_1_3750
+sym_1_3750: la $2, sym_1_3750
+.globl sym_1_3751
+sym_1_3751: la $2, sym_1_3751
+.globl sym_1_3752
+sym_1_3752: la $2, sym_1_3752
+.globl sym_1_3753
+sym_1_3753: la $2, sym_1_3753
+.globl sym_1_3754
+sym_1_3754: la $2, sym_1_3754
+.globl sym_1_3755
+sym_1_3755: la $2, sym_1_3755
+.globl sym_1_3756
+sym_1_3756: la $2, sym_1_3756
+.globl sym_1_3757
+sym_1_3757: la $2, sym_1_3757
+.globl sym_1_3758
+sym_1_3758: la $2, sym_1_3758
+.globl sym_1_3759
+sym_1_3759: la $2, sym_1_3759
+.globl sym_1_3760
+sym_1_3760: la $2, sym_1_3760
+.globl sym_1_3761
+sym_1_3761: la $2, sym_1_3761
+.globl sym_1_3762
+sym_1_3762: la $2, sym_1_3762
+.globl sym_1_3763
+sym_1_3763: la $2, sym_1_3763
+.globl sym_1_3764
+sym_1_3764: la $2, sym_1_3764
+.globl sym_1_3765
+sym_1_3765: la $2, sym_1_3765
+.globl sym_1_3766
+sym_1_3766: la $2, sym_1_3766
+.globl sym_1_3767
+sym_1_3767: la $2, sym_1_3767
+.globl sym_1_3768
+sym_1_3768: la $2, sym_1_3768
+.globl sym_1_3769
+sym_1_3769: la $2, sym_1_3769
+.globl sym_1_3770
+sym_1_3770: la $2, sym_1_3770
+.globl sym_1_3771
+sym_1_3771: la $2, sym_1_3771
+.globl sym_1_3772
+sym_1_3772: la $2, sym_1_3772
+.globl sym_1_3773
+sym_1_3773: la $2, sym_1_3773
+.globl sym_1_3774
+sym_1_3774: la $2, sym_1_3774
+.globl sym_1_3775
+sym_1_3775: la $2, sym_1_3775
+.globl sym_1_3776
+sym_1_3776: la $2, sym_1_3776
+.globl sym_1_3777
+sym_1_3777: la $2, sym_1_3777
+.globl sym_1_3778
+sym_1_3778: la $2, sym_1_3778
+.globl sym_1_3779
+sym_1_3779: la $2, sym_1_3779
+.globl sym_1_3780
+sym_1_3780: la $2, sym_1_3780
+.globl sym_1_3781
+sym_1_3781: la $2, sym_1_3781
+.globl sym_1_3782
+sym_1_3782: la $2, sym_1_3782
+.globl sym_1_3783
+sym_1_3783: la $2, sym_1_3783
+.globl sym_1_3784
+sym_1_3784: la $2, sym_1_3784
+.globl sym_1_3785
+sym_1_3785: la $2, sym_1_3785
+.globl sym_1_3786
+sym_1_3786: la $2, sym_1_3786
+.globl sym_1_3787
+sym_1_3787: la $2, sym_1_3787
+.globl sym_1_3788
+sym_1_3788: la $2, sym_1_3788
+.globl sym_1_3789
+sym_1_3789: la $2, sym_1_3789
+.globl sym_1_3790
+sym_1_3790: la $2, sym_1_3790
+.globl sym_1_3791
+sym_1_3791: la $2, sym_1_3791
+.globl sym_1_3792
+sym_1_3792: la $2, sym_1_3792
+.globl sym_1_3793
+sym_1_3793: la $2, sym_1_3793
+.globl sym_1_3794
+sym_1_3794: la $2, sym_1_3794
+.globl sym_1_3795
+sym_1_3795: la $2, sym_1_3795
+.globl sym_1_3796
+sym_1_3796: la $2, sym_1_3796
+.globl sym_1_3797
+sym_1_3797: la $2, sym_1_3797
+.globl sym_1_3798
+sym_1_3798: la $2, sym_1_3798
+.globl sym_1_3799
+sym_1_3799: la $2, sym_1_3799
+.globl sym_1_3800
+sym_1_3800: la $2, sym_1_3800
+.globl sym_1_3801
+sym_1_3801: la $2, sym_1_3801
+.globl sym_1_3802
+sym_1_3802: la $2, sym_1_3802
+.globl sym_1_3803
+sym_1_3803: la $2, sym_1_3803
+.globl sym_1_3804
+sym_1_3804: la $2, sym_1_3804
+.globl sym_1_3805
+sym_1_3805: la $2, sym_1_3805
+.globl sym_1_3806
+sym_1_3806: la $2, sym_1_3806
+.globl sym_1_3807
+sym_1_3807: la $2, sym_1_3807
+.globl sym_1_3808
+sym_1_3808: la $2, sym_1_3808
+.globl sym_1_3809
+sym_1_3809: la $2, sym_1_3809
+.globl sym_1_3810
+sym_1_3810: la $2, sym_1_3810
+.globl sym_1_3811
+sym_1_3811: la $2, sym_1_3811
+.globl sym_1_3812
+sym_1_3812: la $2, sym_1_3812
+.globl sym_1_3813
+sym_1_3813: la $2, sym_1_3813
+.globl sym_1_3814
+sym_1_3814: la $2, sym_1_3814
+.globl sym_1_3815
+sym_1_3815: la $2, sym_1_3815
+.globl sym_1_3816
+sym_1_3816: la $2, sym_1_3816
+.globl sym_1_3817
+sym_1_3817: la $2, sym_1_3817
+.globl sym_1_3818
+sym_1_3818: la $2, sym_1_3818
+.globl sym_1_3819
+sym_1_3819: la $2, sym_1_3819
+.globl sym_1_3820
+sym_1_3820: la $2, sym_1_3820
+.globl sym_1_3821
+sym_1_3821: la $2, sym_1_3821
+.globl sym_1_3822
+sym_1_3822: la $2, sym_1_3822
+.globl sym_1_3823
+sym_1_3823: la $2, sym_1_3823
+.globl sym_1_3824
+sym_1_3824: la $2, sym_1_3824
+.globl sym_1_3825
+sym_1_3825: la $2, sym_1_3825
+.globl sym_1_3826
+sym_1_3826: la $2, sym_1_3826
+.globl sym_1_3827
+sym_1_3827: la $2, sym_1_3827
+.globl sym_1_3828
+sym_1_3828: la $2, sym_1_3828
+.globl sym_1_3829
+sym_1_3829: la $2, sym_1_3829
+.globl sym_1_3830
+sym_1_3830: la $2, sym_1_3830
+.globl sym_1_3831
+sym_1_3831: la $2, sym_1_3831
+.globl sym_1_3832
+sym_1_3832: la $2, sym_1_3832
+.globl sym_1_3833
+sym_1_3833: la $2, sym_1_3833
+.globl sym_1_3834
+sym_1_3834: la $2, sym_1_3834
+.globl sym_1_3835
+sym_1_3835: la $2, sym_1_3835
+.globl sym_1_3836
+sym_1_3836: la $2, sym_1_3836
+.globl sym_1_3837
+sym_1_3837: la $2, sym_1_3837
+.globl sym_1_3838
+sym_1_3838: la $2, sym_1_3838
+.globl sym_1_3839
+sym_1_3839: la $2, sym_1_3839
+.globl sym_1_3840
+sym_1_3840: la $2, sym_1_3840
+.globl sym_1_3841
+sym_1_3841: la $2, sym_1_3841
+.globl sym_1_3842
+sym_1_3842: la $2, sym_1_3842
+.globl sym_1_3843
+sym_1_3843: la $2, sym_1_3843
+.globl sym_1_3844
+sym_1_3844: la $2, sym_1_3844
+.globl sym_1_3845
+sym_1_3845: la $2, sym_1_3845
+.globl sym_1_3846
+sym_1_3846: la $2, sym_1_3846
+.globl sym_1_3847
+sym_1_3847: la $2, sym_1_3847
+.globl sym_1_3848
+sym_1_3848: la $2, sym_1_3848
+.globl sym_1_3849
+sym_1_3849: la $2, sym_1_3849
+.globl sym_1_3850
+sym_1_3850: la $2, sym_1_3850
+.globl sym_1_3851
+sym_1_3851: la $2, sym_1_3851
+.globl sym_1_3852
+sym_1_3852: la $2, sym_1_3852
+.globl sym_1_3853
+sym_1_3853: la $2, sym_1_3853
+.globl sym_1_3854
+sym_1_3854: la $2, sym_1_3854
+.globl sym_1_3855
+sym_1_3855: la $2, sym_1_3855
+.globl sym_1_3856
+sym_1_3856: la $2, sym_1_3856
+.globl sym_1_3857
+sym_1_3857: la $2, sym_1_3857
+.globl sym_1_3858
+sym_1_3858: la $2, sym_1_3858
+.globl sym_1_3859
+sym_1_3859: la $2, sym_1_3859
+.globl sym_1_3860
+sym_1_3860: la $2, sym_1_3860
+.globl sym_1_3861
+sym_1_3861: la $2, sym_1_3861
+.globl sym_1_3862
+sym_1_3862: la $2, sym_1_3862
+.globl sym_1_3863
+sym_1_3863: la $2, sym_1_3863
+.globl sym_1_3864
+sym_1_3864: la $2, sym_1_3864
+.globl sym_1_3865
+sym_1_3865: la $2, sym_1_3865
+.globl sym_1_3866
+sym_1_3866: la $2, sym_1_3866
+.globl sym_1_3867
+sym_1_3867: la $2, sym_1_3867
+.globl sym_1_3868
+sym_1_3868: la $2, sym_1_3868
+.globl sym_1_3869
+sym_1_3869: la $2, sym_1_3869
+.globl sym_1_3870
+sym_1_3870: la $2, sym_1_3870
+.globl sym_1_3871
+sym_1_3871: la $2, sym_1_3871
+.globl sym_1_3872
+sym_1_3872: la $2, sym_1_3872
+.globl sym_1_3873
+sym_1_3873: la $2, sym_1_3873
+.globl sym_1_3874
+sym_1_3874: la $2, sym_1_3874
+.globl sym_1_3875
+sym_1_3875: la $2, sym_1_3875
+.globl sym_1_3876
+sym_1_3876: la $2, sym_1_3876
+.globl sym_1_3877
+sym_1_3877: la $2, sym_1_3877
+.globl sym_1_3878
+sym_1_3878: la $2, sym_1_3878
+.globl sym_1_3879
+sym_1_3879: la $2, sym_1_3879
+.globl sym_1_3880
+sym_1_3880: la $2, sym_1_3880
+.globl sym_1_3881
+sym_1_3881: la $2, sym_1_3881
+.globl sym_1_3882
+sym_1_3882: la $2, sym_1_3882
+.globl sym_1_3883
+sym_1_3883: la $2, sym_1_3883
+.globl sym_1_3884
+sym_1_3884: la $2, sym_1_3884
+.globl sym_1_3885
+sym_1_3885: la $2, sym_1_3885
+.globl sym_1_3886
+sym_1_3886: la $2, sym_1_3886
+.globl sym_1_3887
+sym_1_3887: la $2, sym_1_3887
+.globl sym_1_3888
+sym_1_3888: la $2, sym_1_3888
+.globl sym_1_3889
+sym_1_3889: la $2, sym_1_3889
+.globl sym_1_3890
+sym_1_3890: la $2, sym_1_3890
+.globl sym_1_3891
+sym_1_3891: la $2, sym_1_3891
+.globl sym_1_3892
+sym_1_3892: la $2, sym_1_3892
+.globl sym_1_3893
+sym_1_3893: la $2, sym_1_3893
+.globl sym_1_3894
+sym_1_3894: la $2, sym_1_3894
+.globl sym_1_3895
+sym_1_3895: la $2, sym_1_3895
+.globl sym_1_3896
+sym_1_3896: la $2, sym_1_3896
+.globl sym_1_3897
+sym_1_3897: la $2, sym_1_3897
+.globl sym_1_3898
+sym_1_3898: la $2, sym_1_3898
+.globl sym_1_3899
+sym_1_3899: la $2, sym_1_3899
+.globl sym_1_3900
+sym_1_3900: la $2, sym_1_3900
+.globl sym_1_3901
+sym_1_3901: la $2, sym_1_3901
+.globl sym_1_3902
+sym_1_3902: la $2, sym_1_3902
+.globl sym_1_3903
+sym_1_3903: la $2, sym_1_3903
+.globl sym_1_3904
+sym_1_3904: la $2, sym_1_3904
+.globl sym_1_3905
+sym_1_3905: la $2, sym_1_3905
+.globl sym_1_3906
+sym_1_3906: la $2, sym_1_3906
+.globl sym_1_3907
+sym_1_3907: la $2, sym_1_3907
+.globl sym_1_3908
+sym_1_3908: la $2, sym_1_3908
+.globl sym_1_3909
+sym_1_3909: la $2, sym_1_3909
+.globl sym_1_3910
+sym_1_3910: la $2, sym_1_3910
+.globl sym_1_3911
+sym_1_3911: la $2, sym_1_3911
+.globl sym_1_3912
+sym_1_3912: la $2, sym_1_3912
+.globl sym_1_3913
+sym_1_3913: la $2, sym_1_3913
+.globl sym_1_3914
+sym_1_3914: la $2, sym_1_3914
+.globl sym_1_3915
+sym_1_3915: la $2, sym_1_3915
+.globl sym_1_3916
+sym_1_3916: la $2, sym_1_3916
+.globl sym_1_3917
+sym_1_3917: la $2, sym_1_3917
+.globl sym_1_3918
+sym_1_3918: la $2, sym_1_3918
+.globl sym_1_3919
+sym_1_3919: la $2, sym_1_3919
+.globl sym_1_3920
+sym_1_3920: la $2, sym_1_3920
+.globl sym_1_3921
+sym_1_3921: la $2, sym_1_3921
+.globl sym_1_3922
+sym_1_3922: la $2, sym_1_3922
+.globl sym_1_3923
+sym_1_3923: la $2, sym_1_3923
+.globl sym_1_3924
+sym_1_3924: la $2, sym_1_3924
+.globl sym_1_3925
+sym_1_3925: la $2, sym_1_3925
+.globl sym_1_3926
+sym_1_3926: la $2, sym_1_3926
+.globl sym_1_3927
+sym_1_3927: la $2, sym_1_3927
+.globl sym_1_3928
+sym_1_3928: la $2, sym_1_3928
+.globl sym_1_3929
+sym_1_3929: la $2, sym_1_3929
+.globl sym_1_3930
+sym_1_3930: la $2, sym_1_3930
+.globl sym_1_3931
+sym_1_3931: la $2, sym_1_3931
+.globl sym_1_3932
+sym_1_3932: la $2, sym_1_3932
+.globl sym_1_3933
+sym_1_3933: la $2, sym_1_3933
+.globl sym_1_3934
+sym_1_3934: la $2, sym_1_3934
+.globl sym_1_3935
+sym_1_3935: la $2, sym_1_3935
+.globl sym_1_3936
+sym_1_3936: la $2, sym_1_3936
+.globl sym_1_3937
+sym_1_3937: la $2, sym_1_3937
+.globl sym_1_3938
+sym_1_3938: la $2, sym_1_3938
+.globl sym_1_3939
+sym_1_3939: la $2, sym_1_3939
+.globl sym_1_3940
+sym_1_3940: la $2, sym_1_3940
+.globl sym_1_3941
+sym_1_3941: la $2, sym_1_3941
+.globl sym_1_3942
+sym_1_3942: la $2, sym_1_3942
+.globl sym_1_3943
+sym_1_3943: la $2, sym_1_3943
+.globl sym_1_3944
+sym_1_3944: la $2, sym_1_3944
+.globl sym_1_3945
+sym_1_3945: la $2, sym_1_3945
+.globl sym_1_3946
+sym_1_3946: la $2, sym_1_3946
+.globl sym_1_3947
+sym_1_3947: la $2, sym_1_3947
+.globl sym_1_3948
+sym_1_3948: la $2, sym_1_3948
+.globl sym_1_3949
+sym_1_3949: la $2, sym_1_3949
+.globl sym_1_3950
+sym_1_3950: la $2, sym_1_3950
+.globl sym_1_3951
+sym_1_3951: la $2, sym_1_3951
+.globl sym_1_3952
+sym_1_3952: la $2, sym_1_3952
+.globl sym_1_3953
+sym_1_3953: la $2, sym_1_3953
+.globl sym_1_3954
+sym_1_3954: la $2, sym_1_3954
+.globl sym_1_3955
+sym_1_3955: la $2, sym_1_3955
+.globl sym_1_3956
+sym_1_3956: la $2, sym_1_3956
+.globl sym_1_3957
+sym_1_3957: la $2, sym_1_3957
+.globl sym_1_3958
+sym_1_3958: la $2, sym_1_3958
+.globl sym_1_3959
+sym_1_3959: la $2, sym_1_3959
+.globl sym_1_3960
+sym_1_3960: la $2, sym_1_3960
+.globl sym_1_3961
+sym_1_3961: la $2, sym_1_3961
+.globl sym_1_3962
+sym_1_3962: la $2, sym_1_3962
+.globl sym_1_3963
+sym_1_3963: la $2, sym_1_3963
+.globl sym_1_3964
+sym_1_3964: la $2, sym_1_3964
+.globl sym_1_3965
+sym_1_3965: la $2, sym_1_3965
+.globl sym_1_3966
+sym_1_3966: la $2, sym_1_3966
+.globl sym_1_3967
+sym_1_3967: la $2, sym_1_3967
+.globl sym_1_3968
+sym_1_3968: la $2, sym_1_3968
+.globl sym_1_3969
+sym_1_3969: la $2, sym_1_3969
+.globl sym_1_3970
+sym_1_3970: la $2, sym_1_3970
+.globl sym_1_3971
+sym_1_3971: la $2, sym_1_3971
+.globl sym_1_3972
+sym_1_3972: la $2, sym_1_3972
+.globl sym_1_3973
+sym_1_3973: la $2, sym_1_3973
+.globl sym_1_3974
+sym_1_3974: la $2, sym_1_3974
+.globl sym_1_3975
+sym_1_3975: la $2, sym_1_3975
+.globl sym_1_3976
+sym_1_3976: la $2, sym_1_3976
+.globl sym_1_3977
+sym_1_3977: la $2, sym_1_3977
+.globl sym_1_3978
+sym_1_3978: la $2, sym_1_3978
+.globl sym_1_3979
+sym_1_3979: la $2, sym_1_3979
+.globl sym_1_3980
+sym_1_3980: la $2, sym_1_3980
+.globl sym_1_3981
+sym_1_3981: la $2, sym_1_3981
+.globl sym_1_3982
+sym_1_3982: la $2, sym_1_3982
+.globl sym_1_3983
+sym_1_3983: la $2, sym_1_3983
+.globl sym_1_3984
+sym_1_3984: la $2, sym_1_3984
+.globl sym_1_3985
+sym_1_3985: la $2, sym_1_3985
+.globl sym_1_3986
+sym_1_3986: la $2, sym_1_3986
+.globl sym_1_3987
+sym_1_3987: la $2, sym_1_3987
+.globl sym_1_3988
+sym_1_3988: la $2, sym_1_3988
+.globl sym_1_3989
+sym_1_3989: la $2, sym_1_3989
+.globl sym_1_3990
+sym_1_3990: la $2, sym_1_3990
+.globl sym_1_3991
+sym_1_3991: la $2, sym_1_3991
+.globl sym_1_3992
+sym_1_3992: la $2, sym_1_3992
+.globl sym_1_3993
+sym_1_3993: la $2, sym_1_3993
+.globl sym_1_3994
+sym_1_3994: la $2, sym_1_3994
+.globl sym_1_3995
+sym_1_3995: la $2, sym_1_3995
+.globl sym_1_3996
+sym_1_3996: la $2, sym_1_3996
+.globl sym_1_3997
+sym_1_3997: la $2, sym_1_3997
+.globl sym_1_3998
+sym_1_3998: la $2, sym_1_3998
+.globl sym_1_3999
+sym_1_3999: la $2, sym_1_3999
+.globl sym_1_4000
+sym_1_4000: la $2, sym_1_4000
+.globl sym_1_4001
+sym_1_4001: la $2, sym_1_4001
+.globl sym_1_4002
+sym_1_4002: la $2, sym_1_4002
+.globl sym_1_4003
+sym_1_4003: la $2, sym_1_4003
+.globl sym_1_4004
+sym_1_4004: la $2, sym_1_4004
+.globl sym_1_4005
+sym_1_4005: la $2, sym_1_4005
+.globl sym_1_4006
+sym_1_4006: la $2, sym_1_4006
+.globl sym_1_4007
+sym_1_4007: la $2, sym_1_4007
+.globl sym_1_4008
+sym_1_4008: la $2, sym_1_4008
+.globl sym_1_4009
+sym_1_4009: la $2, sym_1_4009
+.globl sym_1_4010
+sym_1_4010: la $2, sym_1_4010
+.globl sym_1_4011
+sym_1_4011: la $2, sym_1_4011
+.globl sym_1_4012
+sym_1_4012: la $2, sym_1_4012
+.globl sym_1_4013
+sym_1_4013: la $2, sym_1_4013
+.globl sym_1_4014
+sym_1_4014: la $2, sym_1_4014
+.globl sym_1_4015
+sym_1_4015: la $2, sym_1_4015
+.globl sym_1_4016
+sym_1_4016: la $2, sym_1_4016
+.globl sym_1_4017
+sym_1_4017: la $2, sym_1_4017
+.globl sym_1_4018
+sym_1_4018: la $2, sym_1_4018
+.globl sym_1_4019
+sym_1_4019: la $2, sym_1_4019
+.globl sym_1_4020
+sym_1_4020: la $2, sym_1_4020
+.globl sym_1_4021
+sym_1_4021: la $2, sym_1_4021
+.globl sym_1_4022
+sym_1_4022: la $2, sym_1_4022
+.globl sym_1_4023
+sym_1_4023: la $2, sym_1_4023
+.globl sym_1_4024
+sym_1_4024: la $2, sym_1_4024
+.globl sym_1_4025
+sym_1_4025: la $2, sym_1_4025
+.globl sym_1_4026
+sym_1_4026: la $2, sym_1_4026
+.globl sym_1_4027
+sym_1_4027: la $2, sym_1_4027
+.globl sym_1_4028
+sym_1_4028: la $2, sym_1_4028
+.globl sym_1_4029
+sym_1_4029: la $2, sym_1_4029
+.globl sym_1_4030
+sym_1_4030: la $2, sym_1_4030
+.globl sym_1_4031
+sym_1_4031: la $2, sym_1_4031
+.globl sym_1_4032
+sym_1_4032: la $2, sym_1_4032
+.globl sym_1_4033
+sym_1_4033: la $2, sym_1_4033
+.globl sym_1_4034
+sym_1_4034: la $2, sym_1_4034
+.globl sym_1_4035
+sym_1_4035: la $2, sym_1_4035
+.globl sym_1_4036
+sym_1_4036: la $2, sym_1_4036
+.globl sym_1_4037
+sym_1_4037: la $2, sym_1_4037
+.globl sym_1_4038
+sym_1_4038: la $2, sym_1_4038
+.globl sym_1_4039
+sym_1_4039: la $2, sym_1_4039
+.globl sym_1_4040
+sym_1_4040: la $2, sym_1_4040
+.globl sym_1_4041
+sym_1_4041: la $2, sym_1_4041
+.globl sym_1_4042
+sym_1_4042: la $2, sym_1_4042
+.globl sym_1_4043
+sym_1_4043: la $2, sym_1_4043
+.globl sym_1_4044
+sym_1_4044: la $2, sym_1_4044
+.globl sym_1_4045
+sym_1_4045: la $2, sym_1_4045
+.globl sym_1_4046
+sym_1_4046: la $2, sym_1_4046
+.globl sym_1_4047
+sym_1_4047: la $2, sym_1_4047
+.globl sym_1_4048
+sym_1_4048: la $2, sym_1_4048
+.globl sym_1_4049
+sym_1_4049: la $2, sym_1_4049
+.globl sym_1_4050
+sym_1_4050: la $2, sym_1_4050
+.globl sym_1_4051
+sym_1_4051: la $2, sym_1_4051
+.globl sym_1_4052
+sym_1_4052: la $2, sym_1_4052
+.globl sym_1_4053
+sym_1_4053: la $2, sym_1_4053
+.globl sym_1_4054
+sym_1_4054: la $2, sym_1_4054
+.globl sym_1_4055
+sym_1_4055: la $2, sym_1_4055
+.globl sym_1_4056
+sym_1_4056: la $2, sym_1_4056
+.globl sym_1_4057
+sym_1_4057: la $2, sym_1_4057
+.globl sym_1_4058
+sym_1_4058: la $2, sym_1_4058
+.globl sym_1_4059
+sym_1_4059: la $2, sym_1_4059
+.globl sym_1_4060
+sym_1_4060: la $2, sym_1_4060
+.globl sym_1_4061
+sym_1_4061: la $2, sym_1_4061
+.globl sym_1_4062
+sym_1_4062: la $2, sym_1_4062
+.globl sym_1_4063
+sym_1_4063: la $2, sym_1_4063
+.globl sym_1_4064
+sym_1_4064: la $2, sym_1_4064
+.globl sym_1_4065
+sym_1_4065: la $2, sym_1_4065
+.globl sym_1_4066
+sym_1_4066: la $2, sym_1_4066
+.globl sym_1_4067
+sym_1_4067: la $2, sym_1_4067
+.globl sym_1_4068
+sym_1_4068: la $2, sym_1_4068
+.globl sym_1_4069
+sym_1_4069: la $2, sym_1_4069
+.globl sym_1_4070
+sym_1_4070: la $2, sym_1_4070
+.globl sym_1_4071
+sym_1_4071: la $2, sym_1_4071
+.globl sym_1_4072
+sym_1_4072: la $2, sym_1_4072
+.globl sym_1_4073
+sym_1_4073: la $2, sym_1_4073
+.globl sym_1_4074
+sym_1_4074: la $2, sym_1_4074
+.globl sym_1_4075
+sym_1_4075: la $2, sym_1_4075
+.globl sym_1_4076
+sym_1_4076: la $2, sym_1_4076
+.globl sym_1_4077
+sym_1_4077: la $2, sym_1_4077
+.globl sym_1_4078
+sym_1_4078: la $2, sym_1_4078
+.globl sym_1_4079
+sym_1_4079: la $2, sym_1_4079
+.globl sym_1_4080
+sym_1_4080: la $2, sym_1_4080
+.globl sym_1_4081
+sym_1_4081: la $2, sym_1_4081
+.globl sym_1_4082
+sym_1_4082: la $2, sym_1_4082
+.globl sym_1_4083
+sym_1_4083: la $2, sym_1_4083
+.globl sym_1_4084
+sym_1_4084: la $2, sym_1_4084
+.globl sym_1_4085
+sym_1_4085: la $2, sym_1_4085
+.globl sym_1_4086
+sym_1_4086: la $2, sym_1_4086
+.globl sym_1_4087
+sym_1_4087: la $2, sym_1_4087
+.globl sym_1_4088
+sym_1_4088: la $2, sym_1_4088
+.globl sym_1_4089
+sym_1_4089: la $2, sym_1_4089
+.globl sym_1_4090
+sym_1_4090: la $2, sym_1_4090
+.globl sym_1_4091
+sym_1_4091: la $2, sym_1_4091
+.globl sym_1_4092
+sym_1_4092: la $2, sym_1_4092
+.globl sym_1_4093
+sym_1_4093: la $2, sym_1_4093
+.globl sym_1_4094
+sym_1_4094: la $2, sym_1_4094
+.globl sym_1_4095
+sym_1_4095: la $2, sym_1_4095
+.globl sym_1_4096
+sym_1_4096: la $2, sym_1_4096
+.globl sym_1_4097
+sym_1_4097: la $2, sym_1_4097
+.globl sym_1_4098
+sym_1_4098: la $2, sym_1_4098
+.globl sym_1_4099
+sym_1_4099: la $2, sym_1_4099
+.globl sym_1_4100
+sym_1_4100: la $2, sym_1_4100
+.globl sym_1_4101
+sym_1_4101: la $2, sym_1_4101
+.globl sym_1_4102
+sym_1_4102: la $2, sym_1_4102
+.globl sym_1_4103
+sym_1_4103: la $2, sym_1_4103
+.globl sym_1_4104
+sym_1_4104: la $2, sym_1_4104
+.globl sym_1_4105
+sym_1_4105: la $2, sym_1_4105
+.globl sym_1_4106
+sym_1_4106: la $2, sym_1_4106
+.globl sym_1_4107
+sym_1_4107: la $2, sym_1_4107
+.globl sym_1_4108
+sym_1_4108: la $2, sym_1_4108
+.globl sym_1_4109
+sym_1_4109: la $2, sym_1_4109
+.globl sym_1_4110
+sym_1_4110: la $2, sym_1_4110
+.globl sym_1_4111
+sym_1_4111: la $2, sym_1_4111
+.globl sym_1_4112
+sym_1_4112: la $2, sym_1_4112
+.globl sym_1_4113
+sym_1_4113: la $2, sym_1_4113
+.globl sym_1_4114
+sym_1_4114: la $2, sym_1_4114
+.globl sym_1_4115
+sym_1_4115: la $2, sym_1_4115
+.globl sym_1_4116
+sym_1_4116: la $2, sym_1_4116
+.globl sym_1_4117
+sym_1_4117: la $2, sym_1_4117
+.globl sym_1_4118
+sym_1_4118: la $2, sym_1_4118
+.globl sym_1_4119
+sym_1_4119: la $2, sym_1_4119
+.globl sym_1_4120
+sym_1_4120: la $2, sym_1_4120
+.globl sym_1_4121
+sym_1_4121: la $2, sym_1_4121
+.globl sym_1_4122
+sym_1_4122: la $2, sym_1_4122
+.globl sym_1_4123
+sym_1_4123: la $2, sym_1_4123
+.globl sym_1_4124
+sym_1_4124: la $2, sym_1_4124
+.globl sym_1_4125
+sym_1_4125: la $2, sym_1_4125
+.globl sym_1_4126
+sym_1_4126: la $2, sym_1_4126
+.globl sym_1_4127
+sym_1_4127: la $2, sym_1_4127
+.globl sym_1_4128
+sym_1_4128: la $2, sym_1_4128
+.globl sym_1_4129
+sym_1_4129: la $2, sym_1_4129
+.globl sym_1_4130
+sym_1_4130: la $2, sym_1_4130
+.globl sym_1_4131
+sym_1_4131: la $2, sym_1_4131
+.globl sym_1_4132
+sym_1_4132: la $2, sym_1_4132
+.globl sym_1_4133
+sym_1_4133: la $2, sym_1_4133
+.globl sym_1_4134
+sym_1_4134: la $2, sym_1_4134
+.globl sym_1_4135
+sym_1_4135: la $2, sym_1_4135
+.globl sym_1_4136
+sym_1_4136: la $2, sym_1_4136
+.globl sym_1_4137
+sym_1_4137: la $2, sym_1_4137
+.globl sym_1_4138
+sym_1_4138: la $2, sym_1_4138
+.globl sym_1_4139
+sym_1_4139: la $2, sym_1_4139
+.globl sym_1_4140
+sym_1_4140: la $2, sym_1_4140
+.globl sym_1_4141
+sym_1_4141: la $2, sym_1_4141
+.globl sym_1_4142
+sym_1_4142: la $2, sym_1_4142
+.globl sym_1_4143
+sym_1_4143: la $2, sym_1_4143
+.globl sym_1_4144
+sym_1_4144: la $2, sym_1_4144
+.globl sym_1_4145
+sym_1_4145: la $2, sym_1_4145
+.globl sym_1_4146
+sym_1_4146: la $2, sym_1_4146
+.globl sym_1_4147
+sym_1_4147: la $2, sym_1_4147
+.globl sym_1_4148
+sym_1_4148: la $2, sym_1_4148
+.globl sym_1_4149
+sym_1_4149: la $2, sym_1_4149
+.globl sym_1_4150
+sym_1_4150: la $2, sym_1_4150
+.globl sym_1_4151
+sym_1_4151: la $2, sym_1_4151
+.globl sym_1_4152
+sym_1_4152: la $2, sym_1_4152
+.globl sym_1_4153
+sym_1_4153: la $2, sym_1_4153
+.globl sym_1_4154
+sym_1_4154: la $2, sym_1_4154
+.globl sym_1_4155
+sym_1_4155: la $2, sym_1_4155
+.globl sym_1_4156
+sym_1_4156: la $2, sym_1_4156
+.globl sym_1_4157
+sym_1_4157: la $2, sym_1_4157
+.globl sym_1_4158
+sym_1_4158: la $2, sym_1_4158
+.globl sym_1_4159
+sym_1_4159: la $2, sym_1_4159
+.globl sym_1_4160
+sym_1_4160: la $2, sym_1_4160
+.globl sym_1_4161
+sym_1_4161: la $2, sym_1_4161
+.globl sym_1_4162
+sym_1_4162: la $2, sym_1_4162
+.globl sym_1_4163
+sym_1_4163: la $2, sym_1_4163
+.globl sym_1_4164
+sym_1_4164: la $2, sym_1_4164
+.globl sym_1_4165
+sym_1_4165: la $2, sym_1_4165
+.globl sym_1_4166
+sym_1_4166: la $2, sym_1_4166
+.globl sym_1_4167
+sym_1_4167: la $2, sym_1_4167
+.globl sym_1_4168
+sym_1_4168: la $2, sym_1_4168
+.globl sym_1_4169
+sym_1_4169: la $2, sym_1_4169
+.globl sym_1_4170
+sym_1_4170: la $2, sym_1_4170
+.globl sym_1_4171
+sym_1_4171: la $2, sym_1_4171
+.globl sym_1_4172
+sym_1_4172: la $2, sym_1_4172
+.globl sym_1_4173
+sym_1_4173: la $2, sym_1_4173
+.globl sym_1_4174
+sym_1_4174: la $2, sym_1_4174
+.globl sym_1_4175
+sym_1_4175: la $2, sym_1_4175
+.globl sym_1_4176
+sym_1_4176: la $2, sym_1_4176
+.globl sym_1_4177
+sym_1_4177: la $2, sym_1_4177
+.globl sym_1_4178
+sym_1_4178: la $2, sym_1_4178
+.globl sym_1_4179
+sym_1_4179: la $2, sym_1_4179
+.globl sym_1_4180
+sym_1_4180: la $2, sym_1_4180
+.globl sym_1_4181
+sym_1_4181: la $2, sym_1_4181
+.globl sym_1_4182
+sym_1_4182: la $2, sym_1_4182
+.globl sym_1_4183
+sym_1_4183: la $2, sym_1_4183
+.globl sym_1_4184
+sym_1_4184: la $2, sym_1_4184
+.globl sym_1_4185
+sym_1_4185: la $2, sym_1_4185
+.globl sym_1_4186
+sym_1_4186: la $2, sym_1_4186
+.globl sym_1_4187
+sym_1_4187: la $2, sym_1_4187
+.globl sym_1_4188
+sym_1_4188: la $2, sym_1_4188
+.globl sym_1_4189
+sym_1_4189: la $2, sym_1_4189
+.globl sym_1_4190
+sym_1_4190: la $2, sym_1_4190
+.globl sym_1_4191
+sym_1_4191: la $2, sym_1_4191
+.globl sym_1_4192
+sym_1_4192: la $2, sym_1_4192
+.globl sym_1_4193
+sym_1_4193: la $2, sym_1_4193
+.globl sym_1_4194
+sym_1_4194: la $2, sym_1_4194
+.globl sym_1_4195
+sym_1_4195: la $2, sym_1_4195
+.globl sym_1_4196
+sym_1_4196: la $2, sym_1_4196
+.globl sym_1_4197
+sym_1_4197: la $2, sym_1_4197
+.globl sym_1_4198
+sym_1_4198: la $2, sym_1_4198
+.globl sym_1_4199
+sym_1_4199: la $2, sym_1_4199
+.globl sym_1_4200
+sym_1_4200: la $2, sym_1_4200
+.globl sym_1_4201
+sym_1_4201: la $2, sym_1_4201
+.globl sym_1_4202
+sym_1_4202: la $2, sym_1_4202
+.globl sym_1_4203
+sym_1_4203: la $2, sym_1_4203
+.globl sym_1_4204
+sym_1_4204: la $2, sym_1_4204
+.globl sym_1_4205
+sym_1_4205: la $2, sym_1_4205
+.globl sym_1_4206
+sym_1_4206: la $2, sym_1_4206
+.globl sym_1_4207
+sym_1_4207: la $2, sym_1_4207
+.globl sym_1_4208
+sym_1_4208: la $2, sym_1_4208
+.globl sym_1_4209
+sym_1_4209: la $2, sym_1_4209
+.globl sym_1_4210
+sym_1_4210: la $2, sym_1_4210
+.globl sym_1_4211
+sym_1_4211: la $2, sym_1_4211
+.globl sym_1_4212
+sym_1_4212: la $2, sym_1_4212
+.globl sym_1_4213
+sym_1_4213: la $2, sym_1_4213
+.globl sym_1_4214
+sym_1_4214: la $2, sym_1_4214
+.globl sym_1_4215
+sym_1_4215: la $2, sym_1_4215
+.globl sym_1_4216
+sym_1_4216: la $2, sym_1_4216
+.globl sym_1_4217
+sym_1_4217: la $2, sym_1_4217
+.globl sym_1_4218
+sym_1_4218: la $2, sym_1_4218
+.globl sym_1_4219
+sym_1_4219: la $2, sym_1_4219
+.globl sym_1_4220
+sym_1_4220: la $2, sym_1_4220
+.globl sym_1_4221
+sym_1_4221: la $2, sym_1_4221
+.globl sym_1_4222
+sym_1_4222: la $2, sym_1_4222
+.globl sym_1_4223
+sym_1_4223: la $2, sym_1_4223
+.globl sym_1_4224
+sym_1_4224: la $2, sym_1_4224
+.globl sym_1_4225
+sym_1_4225: la $2, sym_1_4225
+.globl sym_1_4226
+sym_1_4226: la $2, sym_1_4226
+.globl sym_1_4227
+sym_1_4227: la $2, sym_1_4227
+.globl sym_1_4228
+sym_1_4228: la $2, sym_1_4228
+.globl sym_1_4229
+sym_1_4229: la $2, sym_1_4229
+.globl sym_1_4230
+sym_1_4230: la $2, sym_1_4230
+.globl sym_1_4231
+sym_1_4231: la $2, sym_1_4231
+.globl sym_1_4232
+sym_1_4232: la $2, sym_1_4232
+.globl sym_1_4233
+sym_1_4233: la $2, sym_1_4233
+.globl sym_1_4234
+sym_1_4234: la $2, sym_1_4234
+.globl sym_1_4235
+sym_1_4235: la $2, sym_1_4235
+.globl sym_1_4236
+sym_1_4236: la $2, sym_1_4236
+.globl sym_1_4237
+sym_1_4237: la $2, sym_1_4237
+.globl sym_1_4238
+sym_1_4238: la $2, sym_1_4238
+.globl sym_1_4239
+sym_1_4239: la $2, sym_1_4239
+.globl sym_1_4240
+sym_1_4240: la $2, sym_1_4240
+.globl sym_1_4241
+sym_1_4241: la $2, sym_1_4241
+.globl sym_1_4242
+sym_1_4242: la $2, sym_1_4242
+.globl sym_1_4243
+sym_1_4243: la $2, sym_1_4243
+.globl sym_1_4244
+sym_1_4244: la $2, sym_1_4244
+.globl sym_1_4245
+sym_1_4245: la $2, sym_1_4245
+.globl sym_1_4246
+sym_1_4246: la $2, sym_1_4246
+.globl sym_1_4247
+sym_1_4247: la $2, sym_1_4247
+.globl sym_1_4248
+sym_1_4248: la $2, sym_1_4248
+.globl sym_1_4249
+sym_1_4249: la $2, sym_1_4249
+.globl sym_1_4250
+sym_1_4250: la $2, sym_1_4250
+.globl sym_1_4251
+sym_1_4251: la $2, sym_1_4251
+.globl sym_1_4252
+sym_1_4252: la $2, sym_1_4252
+.globl sym_1_4253
+sym_1_4253: la $2, sym_1_4253
+.globl sym_1_4254
+sym_1_4254: la $2, sym_1_4254
+.globl sym_1_4255
+sym_1_4255: la $2, sym_1_4255
+.globl sym_1_4256
+sym_1_4256: la $2, sym_1_4256
+.globl sym_1_4257
+sym_1_4257: la $2, sym_1_4257
+.globl sym_1_4258
+sym_1_4258: la $2, sym_1_4258
+.globl sym_1_4259
+sym_1_4259: la $2, sym_1_4259
+.globl sym_1_4260
+sym_1_4260: la $2, sym_1_4260
+.globl sym_1_4261
+sym_1_4261: la $2, sym_1_4261
+.globl sym_1_4262
+sym_1_4262: la $2, sym_1_4262
+.globl sym_1_4263
+sym_1_4263: la $2, sym_1_4263
+.globl sym_1_4264
+sym_1_4264: la $2, sym_1_4264
+.globl sym_1_4265
+sym_1_4265: la $2, sym_1_4265
+.globl sym_1_4266
+sym_1_4266: la $2, sym_1_4266
+.globl sym_1_4267
+sym_1_4267: la $2, sym_1_4267
+.globl sym_1_4268
+sym_1_4268: la $2, sym_1_4268
+.globl sym_1_4269
+sym_1_4269: la $2, sym_1_4269
+.globl sym_1_4270
+sym_1_4270: la $2, sym_1_4270
+.globl sym_1_4271
+sym_1_4271: la $2, sym_1_4271
+.globl sym_1_4272
+sym_1_4272: la $2, sym_1_4272
+.globl sym_1_4273
+sym_1_4273: la $2, sym_1_4273
+.globl sym_1_4274
+sym_1_4274: la $2, sym_1_4274
+.globl sym_1_4275
+sym_1_4275: la $2, sym_1_4275
+.globl sym_1_4276
+sym_1_4276: la $2, sym_1_4276
+.globl sym_1_4277
+sym_1_4277: la $2, sym_1_4277
+.globl sym_1_4278
+sym_1_4278: la $2, sym_1_4278
+.globl sym_1_4279
+sym_1_4279: la $2, sym_1_4279
+.globl sym_1_4280
+sym_1_4280: la $2, sym_1_4280
+.globl sym_1_4281
+sym_1_4281: la $2, sym_1_4281
+.globl sym_1_4282
+sym_1_4282: la $2, sym_1_4282
+.globl sym_1_4283
+sym_1_4283: la $2, sym_1_4283
+.globl sym_1_4284
+sym_1_4284: la $2, sym_1_4284
+.globl sym_1_4285
+sym_1_4285: la $2, sym_1_4285
+.globl sym_1_4286
+sym_1_4286: la $2, sym_1_4286
+.globl sym_1_4287
+sym_1_4287: la $2, sym_1_4287
+.globl sym_1_4288
+sym_1_4288: la $2, sym_1_4288
+.globl sym_1_4289
+sym_1_4289: la $2, sym_1_4289
+.globl sym_1_4290
+sym_1_4290: la $2, sym_1_4290
+.globl sym_1_4291
+sym_1_4291: la $2, sym_1_4291
+.globl sym_1_4292
+sym_1_4292: la $2, sym_1_4292
+.globl sym_1_4293
+sym_1_4293: la $2, sym_1_4293
+.globl sym_1_4294
+sym_1_4294: la $2, sym_1_4294
+.globl sym_1_4295
+sym_1_4295: la $2, sym_1_4295
+.globl sym_1_4296
+sym_1_4296: la $2, sym_1_4296
+.globl sym_1_4297
+sym_1_4297: la $2, sym_1_4297
+.globl sym_1_4298
+sym_1_4298: la $2, sym_1_4298
+.globl sym_1_4299
+sym_1_4299: la $2, sym_1_4299
+.globl sym_1_4300
+sym_1_4300: la $2, sym_1_4300
+.globl sym_1_4301
+sym_1_4301: la $2, sym_1_4301
+.globl sym_1_4302
+sym_1_4302: la $2, sym_1_4302
+.globl sym_1_4303
+sym_1_4303: la $2, sym_1_4303
+.globl sym_1_4304
+sym_1_4304: la $2, sym_1_4304
+.globl sym_1_4305
+sym_1_4305: la $2, sym_1_4305
+.globl sym_1_4306
+sym_1_4306: la $2, sym_1_4306
+.globl sym_1_4307
+sym_1_4307: la $2, sym_1_4307
+.globl sym_1_4308
+sym_1_4308: la $2, sym_1_4308
+.globl sym_1_4309
+sym_1_4309: la $2, sym_1_4309
+.globl sym_1_4310
+sym_1_4310: la $2, sym_1_4310
+.globl sym_1_4311
+sym_1_4311: la $2, sym_1_4311
+.globl sym_1_4312
+sym_1_4312: la $2, sym_1_4312
+.globl sym_1_4313
+sym_1_4313: la $2, sym_1_4313
+.globl sym_1_4314
+sym_1_4314: la $2, sym_1_4314
+.globl sym_1_4315
+sym_1_4315: la $2, sym_1_4315
+.globl sym_1_4316
+sym_1_4316: la $2, sym_1_4316
+.globl sym_1_4317
+sym_1_4317: la $2, sym_1_4317
+.globl sym_1_4318
+sym_1_4318: la $2, sym_1_4318
+.globl sym_1_4319
+sym_1_4319: la $2, sym_1_4319
+.globl sym_1_4320
+sym_1_4320: la $2, sym_1_4320
+.globl sym_1_4321
+sym_1_4321: la $2, sym_1_4321
+.globl sym_1_4322
+sym_1_4322: la $2, sym_1_4322
+.globl sym_1_4323
+sym_1_4323: la $2, sym_1_4323
+.globl sym_1_4324
+sym_1_4324: la $2, sym_1_4324
+.globl sym_1_4325
+sym_1_4325: la $2, sym_1_4325
+.globl sym_1_4326
+sym_1_4326: la $2, sym_1_4326
+.globl sym_1_4327
+sym_1_4327: la $2, sym_1_4327
+.globl sym_1_4328
+sym_1_4328: la $2, sym_1_4328
+.globl sym_1_4329
+sym_1_4329: la $2, sym_1_4329
+.globl sym_1_4330
+sym_1_4330: la $2, sym_1_4330
+.globl sym_1_4331
+sym_1_4331: la $2, sym_1_4331
+.globl sym_1_4332
+sym_1_4332: la $2, sym_1_4332
+.globl sym_1_4333
+sym_1_4333: la $2, sym_1_4333
+.globl sym_1_4334
+sym_1_4334: la $2, sym_1_4334
+.globl sym_1_4335
+sym_1_4335: la $2, sym_1_4335
+.globl sym_1_4336
+sym_1_4336: la $2, sym_1_4336
+.globl sym_1_4337
+sym_1_4337: la $2, sym_1_4337
+.globl sym_1_4338
+sym_1_4338: la $2, sym_1_4338
+.globl sym_1_4339
+sym_1_4339: la $2, sym_1_4339
+.globl sym_1_4340
+sym_1_4340: la $2, sym_1_4340
+.globl sym_1_4341
+sym_1_4341: la $2, sym_1_4341
+.globl sym_1_4342
+sym_1_4342: la $2, sym_1_4342
+.globl sym_1_4343
+sym_1_4343: la $2, sym_1_4343
+.globl sym_1_4344
+sym_1_4344: la $2, sym_1_4344
+.globl sym_1_4345
+sym_1_4345: la $2, sym_1_4345
+.globl sym_1_4346
+sym_1_4346: la $2, sym_1_4346
+.globl sym_1_4347
+sym_1_4347: la $2, sym_1_4347
+.globl sym_1_4348
+sym_1_4348: la $2, sym_1_4348
+.globl sym_1_4349
+sym_1_4349: la $2, sym_1_4349
+.globl sym_1_4350
+sym_1_4350: la $2, sym_1_4350
+.globl sym_1_4351
+sym_1_4351: la $2, sym_1_4351
+.globl sym_1_4352
+sym_1_4352: la $2, sym_1_4352
+.globl sym_1_4353
+sym_1_4353: la $2, sym_1_4353
+.globl sym_1_4354
+sym_1_4354: la $2, sym_1_4354
+.globl sym_1_4355
+sym_1_4355: la $2, sym_1_4355
+.globl sym_1_4356
+sym_1_4356: la $2, sym_1_4356
+.globl sym_1_4357
+sym_1_4357: la $2, sym_1_4357
+.globl sym_1_4358
+sym_1_4358: la $2, sym_1_4358
+.globl sym_1_4359
+sym_1_4359: la $2, sym_1_4359
+.globl sym_1_4360
+sym_1_4360: la $2, sym_1_4360
+.globl sym_1_4361
+sym_1_4361: la $2, sym_1_4361
+.globl sym_1_4362
+sym_1_4362: la $2, sym_1_4362
+.globl sym_1_4363
+sym_1_4363: la $2, sym_1_4363
+.globl sym_1_4364
+sym_1_4364: la $2, sym_1_4364
+.globl sym_1_4365
+sym_1_4365: la $2, sym_1_4365
+.globl sym_1_4366
+sym_1_4366: la $2, sym_1_4366
+.globl sym_1_4367
+sym_1_4367: la $2, sym_1_4367
+.globl sym_1_4368
+sym_1_4368: la $2, sym_1_4368
+.globl sym_1_4369
+sym_1_4369: la $2, sym_1_4369
+.globl sym_1_4370
+sym_1_4370: la $2, sym_1_4370
+.globl sym_1_4371
+sym_1_4371: la $2, sym_1_4371
+.globl sym_1_4372
+sym_1_4372: la $2, sym_1_4372
+.globl sym_1_4373
+sym_1_4373: la $2, sym_1_4373
+.globl sym_1_4374
+sym_1_4374: la $2, sym_1_4374
+.globl sym_1_4375
+sym_1_4375: la $2, sym_1_4375
+.globl sym_1_4376
+sym_1_4376: la $2, sym_1_4376
+.globl sym_1_4377
+sym_1_4377: la $2, sym_1_4377
+.globl sym_1_4378
+sym_1_4378: la $2, sym_1_4378
+.globl sym_1_4379
+sym_1_4379: la $2, sym_1_4379
+.globl sym_1_4380
+sym_1_4380: la $2, sym_1_4380
+.globl sym_1_4381
+sym_1_4381: la $2, sym_1_4381
+.globl sym_1_4382
+sym_1_4382: la $2, sym_1_4382
+.globl sym_1_4383
+sym_1_4383: la $2, sym_1_4383
+.globl sym_1_4384
+sym_1_4384: la $2, sym_1_4384
+.globl sym_1_4385
+sym_1_4385: la $2, sym_1_4385
+.globl sym_1_4386
+sym_1_4386: la $2, sym_1_4386
+.globl sym_1_4387
+sym_1_4387: la $2, sym_1_4387
+.globl sym_1_4388
+sym_1_4388: la $2, sym_1_4388
+.globl sym_1_4389
+sym_1_4389: la $2, sym_1_4389
+.globl sym_1_4390
+sym_1_4390: la $2, sym_1_4390
+.globl sym_1_4391
+sym_1_4391: la $2, sym_1_4391
+.globl sym_1_4392
+sym_1_4392: la $2, sym_1_4392
+.globl sym_1_4393
+sym_1_4393: la $2, sym_1_4393
+.globl sym_1_4394
+sym_1_4394: la $2, sym_1_4394
+.globl sym_1_4395
+sym_1_4395: la $2, sym_1_4395
+.globl sym_1_4396
+sym_1_4396: la $2, sym_1_4396
+.globl sym_1_4397
+sym_1_4397: la $2, sym_1_4397
+.globl sym_1_4398
+sym_1_4398: la $2, sym_1_4398
+.globl sym_1_4399
+sym_1_4399: la $2, sym_1_4399
+.globl sym_1_4400
+sym_1_4400: la $2, sym_1_4400
+.globl sym_1_4401
+sym_1_4401: la $2, sym_1_4401
+.globl sym_1_4402
+sym_1_4402: la $2, sym_1_4402
+.globl sym_1_4403
+sym_1_4403: la $2, sym_1_4403
+.globl sym_1_4404
+sym_1_4404: la $2, sym_1_4404
+.globl sym_1_4405
+sym_1_4405: la $2, sym_1_4405
+.globl sym_1_4406
+sym_1_4406: la $2, sym_1_4406
+.globl sym_1_4407
+sym_1_4407: la $2, sym_1_4407
+.globl sym_1_4408
+sym_1_4408: la $2, sym_1_4408
+.globl sym_1_4409
+sym_1_4409: la $2, sym_1_4409
+.globl sym_1_4410
+sym_1_4410: la $2, sym_1_4410
+.globl sym_1_4411
+sym_1_4411: la $2, sym_1_4411
+.globl sym_1_4412
+sym_1_4412: la $2, sym_1_4412
+.globl sym_1_4413
+sym_1_4413: la $2, sym_1_4413
+.globl sym_1_4414
+sym_1_4414: la $2, sym_1_4414
+.globl sym_1_4415
+sym_1_4415: la $2, sym_1_4415
+.globl sym_1_4416
+sym_1_4416: la $2, sym_1_4416
+.globl sym_1_4417
+sym_1_4417: la $2, sym_1_4417
+.globl sym_1_4418
+sym_1_4418: la $2, sym_1_4418
+.globl sym_1_4419
+sym_1_4419: la $2, sym_1_4419
+.globl sym_1_4420
+sym_1_4420: la $2, sym_1_4420
+.globl sym_1_4421
+sym_1_4421: la $2, sym_1_4421
+.globl sym_1_4422
+sym_1_4422: la $2, sym_1_4422
+.globl sym_1_4423
+sym_1_4423: la $2, sym_1_4423
+.globl sym_1_4424
+sym_1_4424: la $2, sym_1_4424
+.globl sym_1_4425
+sym_1_4425: la $2, sym_1_4425
+.globl sym_1_4426
+sym_1_4426: la $2, sym_1_4426
+.globl sym_1_4427
+sym_1_4427: la $2, sym_1_4427
+.globl sym_1_4428
+sym_1_4428: la $2, sym_1_4428
+.globl sym_1_4429
+sym_1_4429: la $2, sym_1_4429
+.globl sym_1_4430
+sym_1_4430: la $2, sym_1_4430
+.globl sym_1_4431
+sym_1_4431: la $2, sym_1_4431
+.globl sym_1_4432
+sym_1_4432: la $2, sym_1_4432
+.globl sym_1_4433
+sym_1_4433: la $2, sym_1_4433
+.globl sym_1_4434
+sym_1_4434: la $2, sym_1_4434
+.globl sym_1_4435
+sym_1_4435: la $2, sym_1_4435
+.globl sym_1_4436
+sym_1_4436: la $2, sym_1_4436
+.globl sym_1_4437
+sym_1_4437: la $2, sym_1_4437
+.globl sym_1_4438
+sym_1_4438: la $2, sym_1_4438
+.globl sym_1_4439
+sym_1_4439: la $2, sym_1_4439
+.globl sym_1_4440
+sym_1_4440: la $2, sym_1_4440
+.globl sym_1_4441
+sym_1_4441: la $2, sym_1_4441
+.globl sym_1_4442
+sym_1_4442: la $2, sym_1_4442
+.globl sym_1_4443
+sym_1_4443: la $2, sym_1_4443
+.globl sym_1_4444
+sym_1_4444: la $2, sym_1_4444
+.globl sym_1_4445
+sym_1_4445: la $2, sym_1_4445
+.globl sym_1_4446
+sym_1_4446: la $2, sym_1_4446
+.globl sym_1_4447
+sym_1_4447: la $2, sym_1_4447
+.globl sym_1_4448
+sym_1_4448: la $2, sym_1_4448
+.globl sym_1_4449
+sym_1_4449: la $2, sym_1_4449
+.globl sym_1_4450
+sym_1_4450: la $2, sym_1_4450
+.globl sym_1_4451
+sym_1_4451: la $2, sym_1_4451
+.globl sym_1_4452
+sym_1_4452: la $2, sym_1_4452
+.globl sym_1_4453
+sym_1_4453: la $2, sym_1_4453
+.globl sym_1_4454
+sym_1_4454: la $2, sym_1_4454
+.globl sym_1_4455
+sym_1_4455: la $2, sym_1_4455
+.globl sym_1_4456
+sym_1_4456: la $2, sym_1_4456
+.globl sym_1_4457
+sym_1_4457: la $2, sym_1_4457
+.globl sym_1_4458
+sym_1_4458: la $2, sym_1_4458
+.globl sym_1_4459
+sym_1_4459: la $2, sym_1_4459
+.globl sym_1_4460
+sym_1_4460: la $2, sym_1_4460
+.globl sym_1_4461
+sym_1_4461: la $2, sym_1_4461
+.globl sym_1_4462
+sym_1_4462: la $2, sym_1_4462
+.globl sym_1_4463
+sym_1_4463: la $2, sym_1_4463
+.globl sym_1_4464
+sym_1_4464: la $2, sym_1_4464
+.globl sym_1_4465
+sym_1_4465: la $2, sym_1_4465
+.globl sym_1_4466
+sym_1_4466: la $2, sym_1_4466
+.globl sym_1_4467
+sym_1_4467: la $2, sym_1_4467
+.globl sym_1_4468
+sym_1_4468: la $2, sym_1_4468
+.globl sym_1_4469
+sym_1_4469: la $2, sym_1_4469
+.globl sym_1_4470
+sym_1_4470: la $2, sym_1_4470
+.globl sym_1_4471
+sym_1_4471: la $2, sym_1_4471
+.globl sym_1_4472
+sym_1_4472: la $2, sym_1_4472
+.globl sym_1_4473
+sym_1_4473: la $2, sym_1_4473
+.globl sym_1_4474
+sym_1_4474: la $2, sym_1_4474
+.globl sym_1_4475
+sym_1_4475: la $2, sym_1_4475
+.globl sym_1_4476
+sym_1_4476: la $2, sym_1_4476
+.globl sym_1_4477
+sym_1_4477: la $2, sym_1_4477
+.globl sym_1_4478
+sym_1_4478: la $2, sym_1_4478
+.globl sym_1_4479
+sym_1_4479: la $2, sym_1_4479
+.globl sym_1_4480
+sym_1_4480: la $2, sym_1_4480
+.globl sym_1_4481
+sym_1_4481: la $2, sym_1_4481
+.globl sym_1_4482
+sym_1_4482: la $2, sym_1_4482
+.globl sym_1_4483
+sym_1_4483: la $2, sym_1_4483
+.globl sym_1_4484
+sym_1_4484: la $2, sym_1_4484
+.globl sym_1_4485
+sym_1_4485: la $2, sym_1_4485
+.globl sym_1_4486
+sym_1_4486: la $2, sym_1_4486
+.globl sym_1_4487
+sym_1_4487: la $2, sym_1_4487
+.globl sym_1_4488
+sym_1_4488: la $2, sym_1_4488
+.globl sym_1_4489
+sym_1_4489: la $2, sym_1_4489
+.globl sym_1_4490
+sym_1_4490: la $2, sym_1_4490
+.globl sym_1_4491
+sym_1_4491: la $2, sym_1_4491
+.globl sym_1_4492
+sym_1_4492: la $2, sym_1_4492
+.globl sym_1_4493
+sym_1_4493: la $2, sym_1_4493
+.globl sym_1_4494
+sym_1_4494: la $2, sym_1_4494
+.globl sym_1_4495
+sym_1_4495: la $2, sym_1_4495
+.globl sym_1_4496
+sym_1_4496: la $2, sym_1_4496
+.globl sym_1_4497
+sym_1_4497: la $2, sym_1_4497
+.globl sym_1_4498
+sym_1_4498: la $2, sym_1_4498
+.globl sym_1_4499
+sym_1_4499: la $2, sym_1_4499
+.globl sym_1_4500
+sym_1_4500: la $2, sym_1_4500
+.globl sym_1_4501
+sym_1_4501: la $2, sym_1_4501
+.globl sym_1_4502
+sym_1_4502: la $2, sym_1_4502
+.globl sym_1_4503
+sym_1_4503: la $2, sym_1_4503
+.globl sym_1_4504
+sym_1_4504: la $2, sym_1_4504
+.globl sym_1_4505
+sym_1_4505: la $2, sym_1_4505
+.globl sym_1_4506
+sym_1_4506: la $2, sym_1_4506
+.globl sym_1_4507
+sym_1_4507: la $2, sym_1_4507
+.globl sym_1_4508
+sym_1_4508: la $2, sym_1_4508
+.globl sym_1_4509
+sym_1_4509: la $2, sym_1_4509
+.globl sym_1_4510
+sym_1_4510: la $2, sym_1_4510
+.globl sym_1_4511
+sym_1_4511: la $2, sym_1_4511
+.globl sym_1_4512
+sym_1_4512: la $2, sym_1_4512
+.globl sym_1_4513
+sym_1_4513: la $2, sym_1_4513
+.globl sym_1_4514
+sym_1_4514: la $2, sym_1_4514
+.globl sym_1_4515
+sym_1_4515: la $2, sym_1_4515
+.globl sym_1_4516
+sym_1_4516: la $2, sym_1_4516
+.globl sym_1_4517
+sym_1_4517: la $2, sym_1_4517
+.globl sym_1_4518
+sym_1_4518: la $2, sym_1_4518
+.globl sym_1_4519
+sym_1_4519: la $2, sym_1_4519
+.globl sym_1_4520
+sym_1_4520: la $2, sym_1_4520
+.globl sym_1_4521
+sym_1_4521: la $2, sym_1_4521
+.globl sym_1_4522
+sym_1_4522: la $2, sym_1_4522
+.globl sym_1_4523
+sym_1_4523: la $2, sym_1_4523
+.globl sym_1_4524
+sym_1_4524: la $2, sym_1_4524
+.globl sym_1_4525
+sym_1_4525: la $2, sym_1_4525
+.globl sym_1_4526
+sym_1_4526: la $2, sym_1_4526
+.globl sym_1_4527
+sym_1_4527: la $2, sym_1_4527
+.globl sym_1_4528
+sym_1_4528: la $2, sym_1_4528
+.globl sym_1_4529
+sym_1_4529: la $2, sym_1_4529
+.globl sym_1_4530
+sym_1_4530: la $2, sym_1_4530
+.globl sym_1_4531
+sym_1_4531: la $2, sym_1_4531
+.globl sym_1_4532
+sym_1_4532: la $2, sym_1_4532
+.globl sym_1_4533
+sym_1_4533: la $2, sym_1_4533
+.globl sym_1_4534
+sym_1_4534: la $2, sym_1_4534
+.globl sym_1_4535
+sym_1_4535: la $2, sym_1_4535
+.globl sym_1_4536
+sym_1_4536: la $2, sym_1_4536
+.globl sym_1_4537
+sym_1_4537: la $2, sym_1_4537
+.globl sym_1_4538
+sym_1_4538: la $2, sym_1_4538
+.globl sym_1_4539
+sym_1_4539: la $2, sym_1_4539
+.globl sym_1_4540
+sym_1_4540: la $2, sym_1_4540
+.globl sym_1_4541
+sym_1_4541: la $2, sym_1_4541
+.globl sym_1_4542
+sym_1_4542: la $2, sym_1_4542
+.globl sym_1_4543
+sym_1_4543: la $2, sym_1_4543
+.globl sym_1_4544
+sym_1_4544: la $2, sym_1_4544
+.globl sym_1_4545
+sym_1_4545: la $2, sym_1_4545
+.globl sym_1_4546
+sym_1_4546: la $2, sym_1_4546
+.globl sym_1_4547
+sym_1_4547: la $2, sym_1_4547
+.globl sym_1_4548
+sym_1_4548: la $2, sym_1_4548
+.globl sym_1_4549
+sym_1_4549: la $2, sym_1_4549
+.globl sym_1_4550
+sym_1_4550: la $2, sym_1_4550
+.globl sym_1_4551
+sym_1_4551: la $2, sym_1_4551
+.globl sym_1_4552
+sym_1_4552: la $2, sym_1_4552
+.globl sym_1_4553
+sym_1_4553: la $2, sym_1_4553
+.globl sym_1_4554
+sym_1_4554: la $2, sym_1_4554
+.globl sym_1_4555
+sym_1_4555: la $2, sym_1_4555
+.globl sym_1_4556
+sym_1_4556: la $2, sym_1_4556
+.globl sym_1_4557
+sym_1_4557: la $2, sym_1_4557
+.globl sym_1_4558
+sym_1_4558: la $2, sym_1_4558
+.globl sym_1_4559
+sym_1_4559: la $2, sym_1_4559
+.globl sym_1_4560
+sym_1_4560: la $2, sym_1_4560
+.globl sym_1_4561
+sym_1_4561: la $2, sym_1_4561
+.globl sym_1_4562
+sym_1_4562: la $2, sym_1_4562
+.globl sym_1_4563
+sym_1_4563: la $2, sym_1_4563
+.globl sym_1_4564
+sym_1_4564: la $2, sym_1_4564
+.globl sym_1_4565
+sym_1_4565: la $2, sym_1_4565
+.globl sym_1_4566
+sym_1_4566: la $2, sym_1_4566
+.globl sym_1_4567
+sym_1_4567: la $2, sym_1_4567
+.globl sym_1_4568
+sym_1_4568: la $2, sym_1_4568
+.globl sym_1_4569
+sym_1_4569: la $2, sym_1_4569
+.globl sym_1_4570
+sym_1_4570: la $2, sym_1_4570
+.globl sym_1_4571
+sym_1_4571: la $2, sym_1_4571
+.globl sym_1_4572
+sym_1_4572: la $2, sym_1_4572
+.globl sym_1_4573
+sym_1_4573: la $2, sym_1_4573
+.globl sym_1_4574
+sym_1_4574: la $2, sym_1_4574
+.globl sym_1_4575
+sym_1_4575: la $2, sym_1_4575
+.globl sym_1_4576
+sym_1_4576: la $2, sym_1_4576
+.globl sym_1_4577
+sym_1_4577: la $2, sym_1_4577
+.globl sym_1_4578
+sym_1_4578: la $2, sym_1_4578
+.globl sym_1_4579
+sym_1_4579: la $2, sym_1_4579
+.globl sym_1_4580
+sym_1_4580: la $2, sym_1_4580
+.globl sym_1_4581
+sym_1_4581: la $2, sym_1_4581
+.globl sym_1_4582
+sym_1_4582: la $2, sym_1_4582
+.globl sym_1_4583
+sym_1_4583: la $2, sym_1_4583
+.globl sym_1_4584
+sym_1_4584: la $2, sym_1_4584
+.globl sym_1_4585
+sym_1_4585: la $2, sym_1_4585
+.globl sym_1_4586
+sym_1_4586: la $2, sym_1_4586
+.globl sym_1_4587
+sym_1_4587: la $2, sym_1_4587
+.globl sym_1_4588
+sym_1_4588: la $2, sym_1_4588
+.globl sym_1_4589
+sym_1_4589: la $2, sym_1_4589
+.globl sym_1_4590
+sym_1_4590: la $2, sym_1_4590
+.globl sym_1_4591
+sym_1_4591: la $2, sym_1_4591
+.globl sym_1_4592
+sym_1_4592: la $2, sym_1_4592
+.globl sym_1_4593
+sym_1_4593: la $2, sym_1_4593
+.globl sym_1_4594
+sym_1_4594: la $2, sym_1_4594
+.globl sym_1_4595
+sym_1_4595: la $2, sym_1_4595
+.globl sym_1_4596
+sym_1_4596: la $2, sym_1_4596
+.globl sym_1_4597
+sym_1_4597: la $2, sym_1_4597
+.globl sym_1_4598
+sym_1_4598: la $2, sym_1_4598
+.globl sym_1_4599
+sym_1_4599: la $2, sym_1_4599
+.globl sym_1_4600
+sym_1_4600: la $2, sym_1_4600
+.globl sym_1_4601
+sym_1_4601: la $2, sym_1_4601
+.globl sym_1_4602
+sym_1_4602: la $2, sym_1_4602
+.globl sym_1_4603
+sym_1_4603: la $2, sym_1_4603
+.globl sym_1_4604
+sym_1_4604: la $2, sym_1_4604
+.globl sym_1_4605
+sym_1_4605: la $2, sym_1_4605
+.globl sym_1_4606
+sym_1_4606: la $2, sym_1_4606
+.globl sym_1_4607
+sym_1_4607: la $2, sym_1_4607
+.globl sym_1_4608
+sym_1_4608: la $2, sym_1_4608
+.globl sym_1_4609
+sym_1_4609: la $2, sym_1_4609
+.globl sym_1_4610
+sym_1_4610: la $2, sym_1_4610
+.globl sym_1_4611
+sym_1_4611: la $2, sym_1_4611
+.globl sym_1_4612
+sym_1_4612: la $2, sym_1_4612
+.globl sym_1_4613
+sym_1_4613: la $2, sym_1_4613
+.globl sym_1_4614
+sym_1_4614: la $2, sym_1_4614
+.globl sym_1_4615
+sym_1_4615: la $2, sym_1_4615
+.globl sym_1_4616
+sym_1_4616: la $2, sym_1_4616
+.globl sym_1_4617
+sym_1_4617: la $2, sym_1_4617
+.globl sym_1_4618
+sym_1_4618: la $2, sym_1_4618
+.globl sym_1_4619
+sym_1_4619: la $2, sym_1_4619
+.globl sym_1_4620
+sym_1_4620: la $2, sym_1_4620
+.globl sym_1_4621
+sym_1_4621: la $2, sym_1_4621
+.globl sym_1_4622
+sym_1_4622: la $2, sym_1_4622
+.globl sym_1_4623
+sym_1_4623: la $2, sym_1_4623
+.globl sym_1_4624
+sym_1_4624: la $2, sym_1_4624
+.globl sym_1_4625
+sym_1_4625: la $2, sym_1_4625
+.globl sym_1_4626
+sym_1_4626: la $2, sym_1_4626
+.globl sym_1_4627
+sym_1_4627: la $2, sym_1_4627
+.globl sym_1_4628
+sym_1_4628: la $2, sym_1_4628
+.globl sym_1_4629
+sym_1_4629: la $2, sym_1_4629
+.globl sym_1_4630
+sym_1_4630: la $2, sym_1_4630
+.globl sym_1_4631
+sym_1_4631: la $2, sym_1_4631
+.globl sym_1_4632
+sym_1_4632: la $2, sym_1_4632
+.globl sym_1_4633
+sym_1_4633: la $2, sym_1_4633
+.globl sym_1_4634
+sym_1_4634: la $2, sym_1_4634
+.globl sym_1_4635
+sym_1_4635: la $2, sym_1_4635
+.globl sym_1_4636
+sym_1_4636: la $2, sym_1_4636
+.globl sym_1_4637
+sym_1_4637: la $2, sym_1_4637
+.globl sym_1_4638
+sym_1_4638: la $2, sym_1_4638
+.globl sym_1_4639
+sym_1_4639: la $2, sym_1_4639
+.globl sym_1_4640
+sym_1_4640: la $2, sym_1_4640
+.globl sym_1_4641
+sym_1_4641: la $2, sym_1_4641
+.globl sym_1_4642
+sym_1_4642: la $2, sym_1_4642
+.globl sym_1_4643
+sym_1_4643: la $2, sym_1_4643
+.globl sym_1_4644
+sym_1_4644: la $2, sym_1_4644
+.globl sym_1_4645
+sym_1_4645: la $2, sym_1_4645
+.globl sym_1_4646
+sym_1_4646: la $2, sym_1_4646
+.globl sym_1_4647
+sym_1_4647: la $2, sym_1_4647
+.globl sym_1_4648
+sym_1_4648: la $2, sym_1_4648
+.globl sym_1_4649
+sym_1_4649: la $2, sym_1_4649
+.globl sym_1_4650
+sym_1_4650: la $2, sym_1_4650
+.globl sym_1_4651
+sym_1_4651: la $2, sym_1_4651
+.globl sym_1_4652
+sym_1_4652: la $2, sym_1_4652
+.globl sym_1_4653
+sym_1_4653: la $2, sym_1_4653
+.globl sym_1_4654
+sym_1_4654: la $2, sym_1_4654
+.globl sym_1_4655
+sym_1_4655: la $2, sym_1_4655
+.globl sym_1_4656
+sym_1_4656: la $2, sym_1_4656
+.globl sym_1_4657
+sym_1_4657: la $2, sym_1_4657
+.globl sym_1_4658
+sym_1_4658: la $2, sym_1_4658
+.globl sym_1_4659
+sym_1_4659: la $2, sym_1_4659
+.globl sym_1_4660
+sym_1_4660: la $2, sym_1_4660
+.globl sym_1_4661
+sym_1_4661: la $2, sym_1_4661
+.globl sym_1_4662
+sym_1_4662: la $2, sym_1_4662
+.globl sym_1_4663
+sym_1_4663: la $2, sym_1_4663
+.globl sym_1_4664
+sym_1_4664: la $2, sym_1_4664
+.globl sym_1_4665
+sym_1_4665: la $2, sym_1_4665
+.globl sym_1_4666
+sym_1_4666: la $2, sym_1_4666
+.globl sym_1_4667
+sym_1_4667: la $2, sym_1_4667
+.globl sym_1_4668
+sym_1_4668: la $2, sym_1_4668
+.globl sym_1_4669
+sym_1_4669: la $2, sym_1_4669
+.globl sym_1_4670
+sym_1_4670: la $2, sym_1_4670
+.globl sym_1_4671
+sym_1_4671: la $2, sym_1_4671
+.globl sym_1_4672
+sym_1_4672: la $2, sym_1_4672
+.globl sym_1_4673
+sym_1_4673: la $2, sym_1_4673
+.globl sym_1_4674
+sym_1_4674: la $2, sym_1_4674
+.globl sym_1_4675
+sym_1_4675: la $2, sym_1_4675
+.globl sym_1_4676
+sym_1_4676: la $2, sym_1_4676
+.globl sym_1_4677
+sym_1_4677: la $2, sym_1_4677
+.globl sym_1_4678
+sym_1_4678: la $2, sym_1_4678
+.globl sym_1_4679
+sym_1_4679: la $2, sym_1_4679
+.globl sym_1_4680
+sym_1_4680: la $2, sym_1_4680
+.globl sym_1_4681
+sym_1_4681: la $2, sym_1_4681
+.globl sym_1_4682
+sym_1_4682: la $2, sym_1_4682
+.globl sym_1_4683
+sym_1_4683: la $2, sym_1_4683
+.globl sym_1_4684
+sym_1_4684: la $2, sym_1_4684
+.globl sym_1_4685
+sym_1_4685: la $2, sym_1_4685
+.globl sym_1_4686
+sym_1_4686: la $2, sym_1_4686
+.globl sym_1_4687
+sym_1_4687: la $2, sym_1_4687
+.globl sym_1_4688
+sym_1_4688: la $2, sym_1_4688
+.globl sym_1_4689
+sym_1_4689: la $2, sym_1_4689
+.globl sym_1_4690
+sym_1_4690: la $2, sym_1_4690
+.globl sym_1_4691
+sym_1_4691: la $2, sym_1_4691
+.globl sym_1_4692
+sym_1_4692: la $2, sym_1_4692
+.globl sym_1_4693
+sym_1_4693: la $2, sym_1_4693
+.globl sym_1_4694
+sym_1_4694: la $2, sym_1_4694
+.globl sym_1_4695
+sym_1_4695: la $2, sym_1_4695
+.globl sym_1_4696
+sym_1_4696: la $2, sym_1_4696
+.globl sym_1_4697
+sym_1_4697: la $2, sym_1_4697
+.globl sym_1_4698
+sym_1_4698: la $2, sym_1_4698
+.globl sym_1_4699
+sym_1_4699: la $2, sym_1_4699
+.globl sym_1_4700
+sym_1_4700: la $2, sym_1_4700
+.globl sym_1_4701
+sym_1_4701: la $2, sym_1_4701
+.globl sym_1_4702
+sym_1_4702: la $2, sym_1_4702
+.globl sym_1_4703
+sym_1_4703: la $2, sym_1_4703
+.globl sym_1_4704
+sym_1_4704: la $2, sym_1_4704
+.globl sym_1_4705
+sym_1_4705: la $2, sym_1_4705
+.globl sym_1_4706
+sym_1_4706: la $2, sym_1_4706
+.globl sym_1_4707
+sym_1_4707: la $2, sym_1_4707
+.globl sym_1_4708
+sym_1_4708: la $2, sym_1_4708
+.globl sym_1_4709
+sym_1_4709: la $2, sym_1_4709
+.globl sym_1_4710
+sym_1_4710: la $2, sym_1_4710
+.globl sym_1_4711
+sym_1_4711: la $2, sym_1_4711
+.globl sym_1_4712
+sym_1_4712: la $2, sym_1_4712
+.globl sym_1_4713
+sym_1_4713: la $2, sym_1_4713
+.globl sym_1_4714
+sym_1_4714: la $2, sym_1_4714
+.globl sym_1_4715
+sym_1_4715: la $2, sym_1_4715
+.globl sym_1_4716
+sym_1_4716: la $2, sym_1_4716
+.globl sym_1_4717
+sym_1_4717: la $2, sym_1_4717
+.globl sym_1_4718
+sym_1_4718: la $2, sym_1_4718
+.globl sym_1_4719
+sym_1_4719: la $2, sym_1_4719
+.globl sym_1_4720
+sym_1_4720: la $2, sym_1_4720
+.globl sym_1_4721
+sym_1_4721: la $2, sym_1_4721
+.globl sym_1_4722
+sym_1_4722: la $2, sym_1_4722
+.globl sym_1_4723
+sym_1_4723: la $2, sym_1_4723
+.globl sym_1_4724
+sym_1_4724: la $2, sym_1_4724
+.globl sym_1_4725
+sym_1_4725: la $2, sym_1_4725
+.globl sym_1_4726
+sym_1_4726: la $2, sym_1_4726
+.globl sym_1_4727
+sym_1_4727: la $2, sym_1_4727
+.globl sym_1_4728
+sym_1_4728: la $2, sym_1_4728
+.globl sym_1_4729
+sym_1_4729: la $2, sym_1_4729
+.globl sym_1_4730
+sym_1_4730: la $2, sym_1_4730
+.globl sym_1_4731
+sym_1_4731: la $2, sym_1_4731
+.globl sym_1_4732
+sym_1_4732: la $2, sym_1_4732
+.globl sym_1_4733
+sym_1_4733: la $2, sym_1_4733
+.globl sym_1_4734
+sym_1_4734: la $2, sym_1_4734
+.globl sym_1_4735
+sym_1_4735: la $2, sym_1_4735
+.globl sym_1_4736
+sym_1_4736: la $2, sym_1_4736
+.globl sym_1_4737
+sym_1_4737: la $2, sym_1_4737
+.globl sym_1_4738
+sym_1_4738: la $2, sym_1_4738
+.globl sym_1_4739
+sym_1_4739: la $2, sym_1_4739
+.globl sym_1_4740
+sym_1_4740: la $2, sym_1_4740
+.globl sym_1_4741
+sym_1_4741: la $2, sym_1_4741
+.globl sym_1_4742
+sym_1_4742: la $2, sym_1_4742
+.globl sym_1_4743
+sym_1_4743: la $2, sym_1_4743
+.globl sym_1_4744
+sym_1_4744: la $2, sym_1_4744
+.globl sym_1_4745
+sym_1_4745: la $2, sym_1_4745
+.globl sym_1_4746
+sym_1_4746: la $2, sym_1_4746
+.globl sym_1_4747
+sym_1_4747: la $2, sym_1_4747
+.globl sym_1_4748
+sym_1_4748: la $2, sym_1_4748
+.globl sym_1_4749
+sym_1_4749: la $2, sym_1_4749
+.globl sym_1_4750
+sym_1_4750: la $2, sym_1_4750
+.globl sym_1_4751
+sym_1_4751: la $2, sym_1_4751
+.globl sym_1_4752
+sym_1_4752: la $2, sym_1_4752
+.globl sym_1_4753
+sym_1_4753: la $2, sym_1_4753
+.globl sym_1_4754
+sym_1_4754: la $2, sym_1_4754
+.globl sym_1_4755
+sym_1_4755: la $2, sym_1_4755
+.globl sym_1_4756
+sym_1_4756: la $2, sym_1_4756
+.globl sym_1_4757
+sym_1_4757: la $2, sym_1_4757
+.globl sym_1_4758
+sym_1_4758: la $2, sym_1_4758
+.globl sym_1_4759
+sym_1_4759: la $2, sym_1_4759
+.globl sym_1_4760
+sym_1_4760: la $2, sym_1_4760
+.globl sym_1_4761
+sym_1_4761: la $2, sym_1_4761
+.globl sym_1_4762
+sym_1_4762: la $2, sym_1_4762
+.globl sym_1_4763
+sym_1_4763: la $2, sym_1_4763
+.globl sym_1_4764
+sym_1_4764: la $2, sym_1_4764
+.globl sym_1_4765
+sym_1_4765: la $2, sym_1_4765
+.globl sym_1_4766
+sym_1_4766: la $2, sym_1_4766
+.globl sym_1_4767
+sym_1_4767: la $2, sym_1_4767
+.globl sym_1_4768
+sym_1_4768: la $2, sym_1_4768
+.globl sym_1_4769
+sym_1_4769: la $2, sym_1_4769
+.globl sym_1_4770
+sym_1_4770: la $2, sym_1_4770
+.globl sym_1_4771
+sym_1_4771: la $2, sym_1_4771
+.globl sym_1_4772
+sym_1_4772: la $2, sym_1_4772
+.globl sym_1_4773
+sym_1_4773: la $2, sym_1_4773
+.globl sym_1_4774
+sym_1_4774: la $2, sym_1_4774
+.globl sym_1_4775
+sym_1_4775: la $2, sym_1_4775
+.globl sym_1_4776
+sym_1_4776: la $2, sym_1_4776
+.globl sym_1_4777
+sym_1_4777: la $2, sym_1_4777
+.globl sym_1_4778
+sym_1_4778: la $2, sym_1_4778
+.globl sym_1_4779
+sym_1_4779: la $2, sym_1_4779
+.globl sym_1_4780
+sym_1_4780: la $2, sym_1_4780
+.globl sym_1_4781
+sym_1_4781: la $2, sym_1_4781
+.globl sym_1_4782
+sym_1_4782: la $2, sym_1_4782
+.globl sym_1_4783
+sym_1_4783: la $2, sym_1_4783
+.globl sym_1_4784
+sym_1_4784: la $2, sym_1_4784
+.globl sym_1_4785
+sym_1_4785: la $2, sym_1_4785
+.globl sym_1_4786
+sym_1_4786: la $2, sym_1_4786
+.globl sym_1_4787
+sym_1_4787: la $2, sym_1_4787
+.globl sym_1_4788
+sym_1_4788: la $2, sym_1_4788
+.globl sym_1_4789
+sym_1_4789: la $2, sym_1_4789
+.globl sym_1_4790
+sym_1_4790: la $2, sym_1_4790
+.globl sym_1_4791
+sym_1_4791: la $2, sym_1_4791
+.globl sym_1_4792
+sym_1_4792: la $2, sym_1_4792
+.globl sym_1_4793
+sym_1_4793: la $2, sym_1_4793
+.globl sym_1_4794
+sym_1_4794: la $2, sym_1_4794
+.globl sym_1_4795
+sym_1_4795: la $2, sym_1_4795
+.globl sym_1_4796
+sym_1_4796: la $2, sym_1_4796
+.globl sym_1_4797
+sym_1_4797: la $2, sym_1_4797
+.globl sym_1_4798
+sym_1_4798: la $2, sym_1_4798
+.globl sym_1_4799
+sym_1_4799: la $2, sym_1_4799
+.globl sym_1_4800
+sym_1_4800: la $2, sym_1_4800
+.globl sym_1_4801
+sym_1_4801: la $2, sym_1_4801
+.globl sym_1_4802
+sym_1_4802: la $2, sym_1_4802
+.globl sym_1_4803
+sym_1_4803: la $2, sym_1_4803
+.globl sym_1_4804
+sym_1_4804: la $2, sym_1_4804
+.globl sym_1_4805
+sym_1_4805: la $2, sym_1_4805
+.globl sym_1_4806
+sym_1_4806: la $2, sym_1_4806
+.globl sym_1_4807
+sym_1_4807: la $2, sym_1_4807
+.globl sym_1_4808
+sym_1_4808: la $2, sym_1_4808
+.globl sym_1_4809
+sym_1_4809: la $2, sym_1_4809
+.globl sym_1_4810
+sym_1_4810: la $2, sym_1_4810
+.globl sym_1_4811
+sym_1_4811: la $2, sym_1_4811
+.globl sym_1_4812
+sym_1_4812: la $2, sym_1_4812
+.globl sym_1_4813
+sym_1_4813: la $2, sym_1_4813
+.globl sym_1_4814
+sym_1_4814: la $2, sym_1_4814
+.globl sym_1_4815
+sym_1_4815: la $2, sym_1_4815
+.globl sym_1_4816
+sym_1_4816: la $2, sym_1_4816
+.globl sym_1_4817
+sym_1_4817: la $2, sym_1_4817
+.globl sym_1_4818
+sym_1_4818: la $2, sym_1_4818
+.globl sym_1_4819
+sym_1_4819: la $2, sym_1_4819
+.globl sym_1_4820
+sym_1_4820: la $2, sym_1_4820
+.globl sym_1_4821
+sym_1_4821: la $2, sym_1_4821
+.globl sym_1_4822
+sym_1_4822: la $2, sym_1_4822
+.globl sym_1_4823
+sym_1_4823: la $2, sym_1_4823
+.globl sym_1_4824
+sym_1_4824: la $2, sym_1_4824
+.globl sym_1_4825
+sym_1_4825: la $2, sym_1_4825
+.globl sym_1_4826
+sym_1_4826: la $2, sym_1_4826
+.globl sym_1_4827
+sym_1_4827: la $2, sym_1_4827
+.globl sym_1_4828
+sym_1_4828: la $2, sym_1_4828
+.globl sym_1_4829
+sym_1_4829: la $2, sym_1_4829
+.globl sym_1_4830
+sym_1_4830: la $2, sym_1_4830
+.globl sym_1_4831
+sym_1_4831: la $2, sym_1_4831
+.globl sym_1_4832
+sym_1_4832: la $2, sym_1_4832
+.globl sym_1_4833
+sym_1_4833: la $2, sym_1_4833
+.globl sym_1_4834
+sym_1_4834: la $2, sym_1_4834
+.globl sym_1_4835
+sym_1_4835: la $2, sym_1_4835
+.globl sym_1_4836
+sym_1_4836: la $2, sym_1_4836
+.globl sym_1_4837
+sym_1_4837: la $2, sym_1_4837
+.globl sym_1_4838
+sym_1_4838: la $2, sym_1_4838
+.globl sym_1_4839
+sym_1_4839: la $2, sym_1_4839
+.globl sym_1_4840
+sym_1_4840: la $2, sym_1_4840
+.globl sym_1_4841
+sym_1_4841: la $2, sym_1_4841
+.globl sym_1_4842
+sym_1_4842: la $2, sym_1_4842
+.globl sym_1_4843
+sym_1_4843: la $2, sym_1_4843
+.globl sym_1_4844
+sym_1_4844: la $2, sym_1_4844
+.globl sym_1_4845
+sym_1_4845: la $2, sym_1_4845
+.globl sym_1_4846
+sym_1_4846: la $2, sym_1_4846
+.globl sym_1_4847
+sym_1_4847: la $2, sym_1_4847
+.globl sym_1_4848
+sym_1_4848: la $2, sym_1_4848
+.globl sym_1_4849
+sym_1_4849: la $2, sym_1_4849
+.globl sym_1_4850
+sym_1_4850: la $2, sym_1_4850
+.globl sym_1_4851
+sym_1_4851: la $2, sym_1_4851
+.globl sym_1_4852
+sym_1_4852: la $2, sym_1_4852
+.globl sym_1_4853
+sym_1_4853: la $2, sym_1_4853
+.globl sym_1_4854
+sym_1_4854: la $2, sym_1_4854
+.globl sym_1_4855
+sym_1_4855: la $2, sym_1_4855
+.globl sym_1_4856
+sym_1_4856: la $2, sym_1_4856
+.globl sym_1_4857
+sym_1_4857: la $2, sym_1_4857
+.globl sym_1_4858
+sym_1_4858: la $2, sym_1_4858
+.globl sym_1_4859
+sym_1_4859: la $2, sym_1_4859
+.globl sym_1_4860
+sym_1_4860: la $2, sym_1_4860
+.globl sym_1_4861
+sym_1_4861: la $2, sym_1_4861
+.globl sym_1_4862
+sym_1_4862: la $2, sym_1_4862
+.globl sym_1_4863
+sym_1_4863: la $2, sym_1_4863
+.globl sym_1_4864
+sym_1_4864: la $2, sym_1_4864
+.globl sym_1_4865
+sym_1_4865: la $2, sym_1_4865
+.globl sym_1_4866
+sym_1_4866: la $2, sym_1_4866
+.globl sym_1_4867
+sym_1_4867: la $2, sym_1_4867
+.globl sym_1_4868
+sym_1_4868: la $2, sym_1_4868
+.globl sym_1_4869
+sym_1_4869: la $2, sym_1_4869
+.globl sym_1_4870
+sym_1_4870: la $2, sym_1_4870
+.globl sym_1_4871
+sym_1_4871: la $2, sym_1_4871
+.globl sym_1_4872
+sym_1_4872: la $2, sym_1_4872
+.globl sym_1_4873
+sym_1_4873: la $2, sym_1_4873
+.globl sym_1_4874
+sym_1_4874: la $2, sym_1_4874
+.globl sym_1_4875
+sym_1_4875: la $2, sym_1_4875
+.globl sym_1_4876
+sym_1_4876: la $2, sym_1_4876
+.globl sym_1_4877
+sym_1_4877: la $2, sym_1_4877
+.globl sym_1_4878
+sym_1_4878: la $2, sym_1_4878
+.globl sym_1_4879
+sym_1_4879: la $2, sym_1_4879
+.globl sym_1_4880
+sym_1_4880: la $2, sym_1_4880
+.globl sym_1_4881
+sym_1_4881: la $2, sym_1_4881
+.globl sym_1_4882
+sym_1_4882: la $2, sym_1_4882
+.globl sym_1_4883
+sym_1_4883: la $2, sym_1_4883
+.globl sym_1_4884
+sym_1_4884: la $2, sym_1_4884
+.globl sym_1_4885
+sym_1_4885: la $2, sym_1_4885
+.globl sym_1_4886
+sym_1_4886: la $2, sym_1_4886
+.globl sym_1_4887
+sym_1_4887: la $2, sym_1_4887
+.globl sym_1_4888
+sym_1_4888: la $2, sym_1_4888
+.globl sym_1_4889
+sym_1_4889: la $2, sym_1_4889
+.globl sym_1_4890
+sym_1_4890: la $2, sym_1_4890
+.globl sym_1_4891
+sym_1_4891: la $2, sym_1_4891
+.globl sym_1_4892
+sym_1_4892: la $2, sym_1_4892
+.globl sym_1_4893
+sym_1_4893: la $2, sym_1_4893
+.globl sym_1_4894
+sym_1_4894: la $2, sym_1_4894
+.globl sym_1_4895
+sym_1_4895: la $2, sym_1_4895
+.globl sym_1_4896
+sym_1_4896: la $2, sym_1_4896
+.globl sym_1_4897
+sym_1_4897: la $2, sym_1_4897
+.globl sym_1_4898
+sym_1_4898: la $2, sym_1_4898
+.globl sym_1_4899
+sym_1_4899: la $2, sym_1_4899
+.globl sym_1_4900
+sym_1_4900: la $2, sym_1_4900
+.globl sym_1_4901
+sym_1_4901: la $2, sym_1_4901
+.globl sym_1_4902
+sym_1_4902: la $2, sym_1_4902
+.globl sym_1_4903
+sym_1_4903: la $2, sym_1_4903
+.globl sym_1_4904
+sym_1_4904: la $2, sym_1_4904
+.globl sym_1_4905
+sym_1_4905: la $2, sym_1_4905
+.globl sym_1_4906
+sym_1_4906: la $2, sym_1_4906
+.globl sym_1_4907
+sym_1_4907: la $2, sym_1_4907
+.globl sym_1_4908
+sym_1_4908: la $2, sym_1_4908
+.globl sym_1_4909
+sym_1_4909: la $2, sym_1_4909
+.globl sym_1_4910
+sym_1_4910: la $2, sym_1_4910
+.globl sym_1_4911
+sym_1_4911: la $2, sym_1_4911
+.globl sym_1_4912
+sym_1_4912: la $2, sym_1_4912
+.globl sym_1_4913
+sym_1_4913: la $2, sym_1_4913
+.globl sym_1_4914
+sym_1_4914: la $2, sym_1_4914
+.globl sym_1_4915
+sym_1_4915: la $2, sym_1_4915
+.globl sym_1_4916
+sym_1_4916: la $2, sym_1_4916
+.globl sym_1_4917
+sym_1_4917: la $2, sym_1_4917
+.globl sym_1_4918
+sym_1_4918: la $2, sym_1_4918
+.globl sym_1_4919
+sym_1_4919: la $2, sym_1_4919
+.globl sym_1_4920
+sym_1_4920: la $2, sym_1_4920
+.globl sym_1_4921
+sym_1_4921: la $2, sym_1_4921
+.globl sym_1_4922
+sym_1_4922: la $2, sym_1_4922
+.globl sym_1_4923
+sym_1_4923: la $2, sym_1_4923
+.globl sym_1_4924
+sym_1_4924: la $2, sym_1_4924
+.globl sym_1_4925
+sym_1_4925: la $2, sym_1_4925
+.globl sym_1_4926
+sym_1_4926: la $2, sym_1_4926
+.globl sym_1_4927
+sym_1_4927: la $2, sym_1_4927
+.globl sym_1_4928
+sym_1_4928: la $2, sym_1_4928
+.globl sym_1_4929
+sym_1_4929: la $2, sym_1_4929
+.globl sym_1_4930
+sym_1_4930: la $2, sym_1_4930
+.globl sym_1_4931
+sym_1_4931: la $2, sym_1_4931
+.globl sym_1_4932
+sym_1_4932: la $2, sym_1_4932
+.globl sym_1_4933
+sym_1_4933: la $2, sym_1_4933
+.globl sym_1_4934
+sym_1_4934: la $2, sym_1_4934
+.globl sym_1_4935
+sym_1_4935: la $2, sym_1_4935
+.globl sym_1_4936
+sym_1_4936: la $2, sym_1_4936
+.globl sym_1_4937
+sym_1_4937: la $2, sym_1_4937
+.globl sym_1_4938
+sym_1_4938: la $2, sym_1_4938
+.globl sym_1_4939
+sym_1_4939: la $2, sym_1_4939
+.globl sym_1_4940
+sym_1_4940: la $2, sym_1_4940
+.globl sym_1_4941
+sym_1_4941: la $2, sym_1_4941
+.globl sym_1_4942
+sym_1_4942: la $2, sym_1_4942
+.globl sym_1_4943
+sym_1_4943: la $2, sym_1_4943
+.globl sym_1_4944
+sym_1_4944: la $2, sym_1_4944
+.globl sym_1_4945
+sym_1_4945: la $2, sym_1_4945
+.globl sym_1_4946
+sym_1_4946: la $2, sym_1_4946
+.globl sym_1_4947
+sym_1_4947: la $2, sym_1_4947
+.globl sym_1_4948
+sym_1_4948: la $2, sym_1_4948
+.globl sym_1_4949
+sym_1_4949: la $2, sym_1_4949
+.globl sym_1_4950
+sym_1_4950: la $2, sym_1_4950
+.globl sym_1_4951
+sym_1_4951: la $2, sym_1_4951
+.globl sym_1_4952
+sym_1_4952: la $2, sym_1_4952
+.globl sym_1_4953
+sym_1_4953: la $2, sym_1_4953
+.globl sym_1_4954
+sym_1_4954: la $2, sym_1_4954
+.globl sym_1_4955
+sym_1_4955: la $2, sym_1_4955
+.globl sym_1_4956
+sym_1_4956: la $2, sym_1_4956
+.globl sym_1_4957
+sym_1_4957: la $2, sym_1_4957
+.globl sym_1_4958
+sym_1_4958: la $2, sym_1_4958
+.globl sym_1_4959
+sym_1_4959: la $2, sym_1_4959
+.globl sym_1_4960
+sym_1_4960: la $2, sym_1_4960
+.globl sym_1_4961
+sym_1_4961: la $2, sym_1_4961
+.globl sym_1_4962
+sym_1_4962: la $2, sym_1_4962
+.globl sym_1_4963
+sym_1_4963: la $2, sym_1_4963
+.globl sym_1_4964
+sym_1_4964: la $2, sym_1_4964
+.globl sym_1_4965
+sym_1_4965: la $2, sym_1_4965
+.globl sym_1_4966
+sym_1_4966: la $2, sym_1_4966
+.globl sym_1_4967
+sym_1_4967: la $2, sym_1_4967
+.globl sym_1_4968
+sym_1_4968: la $2, sym_1_4968
+.globl sym_1_4969
+sym_1_4969: la $2, sym_1_4969
+.globl sym_1_4970
+sym_1_4970: la $2, sym_1_4970
+.globl sym_1_4971
+sym_1_4971: la $2, sym_1_4971
+.globl sym_1_4972
+sym_1_4972: la $2, sym_1_4972
+.globl sym_1_4973
+sym_1_4973: la $2, sym_1_4973
+.globl sym_1_4974
+sym_1_4974: la $2, sym_1_4974
+.globl sym_1_4975
+sym_1_4975: la $2, sym_1_4975
+.globl sym_1_4976
+sym_1_4976: la $2, sym_1_4976
+.globl sym_1_4977
+sym_1_4977: la $2, sym_1_4977
+.globl sym_1_4978
+sym_1_4978: la $2, sym_1_4978
+.globl sym_1_4979
+sym_1_4979: la $2, sym_1_4979
+.globl sym_1_4980
+sym_1_4980: la $2, sym_1_4980
+.globl sym_1_4981
+sym_1_4981: la $2, sym_1_4981
+.globl sym_1_4982
+sym_1_4982: la $2, sym_1_4982
+.globl sym_1_4983
+sym_1_4983: la $2, sym_1_4983
+.globl sym_1_4984
+sym_1_4984: la $2, sym_1_4984
+.globl sym_1_4985
+sym_1_4985: la $2, sym_1_4985
+.globl sym_1_4986
+sym_1_4986: la $2, sym_1_4986
+.globl sym_1_4987
+sym_1_4987: la $2, sym_1_4987
+.globl sym_1_4988
+sym_1_4988: la $2, sym_1_4988
+.globl sym_1_4989
+sym_1_4989: la $2, sym_1_4989
+.globl sym_1_4990
+sym_1_4990: la $2, sym_1_4990
+.globl sym_1_4991
+sym_1_4991: la $2, sym_1_4991
+.globl sym_1_4992
+sym_1_4992: la $2, sym_1_4992
+.globl sym_1_4993
+sym_1_4993: la $2, sym_1_4993
+.globl sym_1_4994
+sym_1_4994: la $2, sym_1_4994
+.globl sym_1_4995
+sym_1_4995: la $2, sym_1_4995
+.globl sym_1_4996
+sym_1_4996: la $2, sym_1_4996
+.globl sym_1_4997
+sym_1_4997: la $2, sym_1_4997
+.globl sym_1_4998
+sym_1_4998: la $2, sym_1_4998
+.globl sym_1_4999
+sym_1_4999: la $2, sym_1_4999
+.globl sym_1_5000
+sym_1_5000: la $2, sym_1_5000
+.globl sym_1_5001
+sym_1_5001: la $2, sym_1_5001
+.globl sym_1_5002
+sym_1_5002: la $2, sym_1_5002
+.globl sym_1_5003
+sym_1_5003: la $2, sym_1_5003
+.globl sym_1_5004
+sym_1_5004: la $2, sym_1_5004
+.globl sym_1_5005
+sym_1_5005: la $2, sym_1_5005
+.globl sym_1_5006
+sym_1_5006: la $2, sym_1_5006
+.globl sym_1_5007
+sym_1_5007: la $2, sym_1_5007
+.globl sym_1_5008
+sym_1_5008: la $2, sym_1_5008
+.globl sym_1_5009
+sym_1_5009: la $2, sym_1_5009
+.globl sym_1_5010
+sym_1_5010: la $2, sym_1_5010
+.globl sym_1_5011
+sym_1_5011: la $2, sym_1_5011
+.globl sym_1_5012
+sym_1_5012: la $2, sym_1_5012
+.globl sym_1_5013
+sym_1_5013: la $2, sym_1_5013
+.globl sym_1_5014
+sym_1_5014: la $2, sym_1_5014
+.globl sym_1_5015
+sym_1_5015: la $2, sym_1_5015
+.globl sym_1_5016
+sym_1_5016: la $2, sym_1_5016
+.globl sym_1_5017
+sym_1_5017: la $2, sym_1_5017
+.globl sym_1_5018
+sym_1_5018: la $2, sym_1_5018
+.globl sym_1_5019
+sym_1_5019: la $2, sym_1_5019
+.globl sym_1_5020
+sym_1_5020: la $2, sym_1_5020
+.globl sym_1_5021
+sym_1_5021: la $2, sym_1_5021
+.globl sym_1_5022
+sym_1_5022: la $2, sym_1_5022
+.globl sym_1_5023
+sym_1_5023: la $2, sym_1_5023
+.globl sym_1_5024
+sym_1_5024: la $2, sym_1_5024
+.globl sym_1_5025
+sym_1_5025: la $2, sym_1_5025
+.globl sym_1_5026
+sym_1_5026: la $2, sym_1_5026
+.globl sym_1_5027
+sym_1_5027: la $2, sym_1_5027
+.globl sym_1_5028
+sym_1_5028: la $2, sym_1_5028
+.globl sym_1_5029
+sym_1_5029: la $2, sym_1_5029
+.globl sym_1_5030
+sym_1_5030: la $2, sym_1_5030
+.globl sym_1_5031
+sym_1_5031: la $2, sym_1_5031
+.globl sym_1_5032
+sym_1_5032: la $2, sym_1_5032
+.globl sym_1_5033
+sym_1_5033: la $2, sym_1_5033
+.globl sym_1_5034
+sym_1_5034: la $2, sym_1_5034
+.globl sym_1_5035
+sym_1_5035: la $2, sym_1_5035
+.globl sym_1_5036
+sym_1_5036: la $2, sym_1_5036
+.globl sym_1_5037
+sym_1_5037: la $2, sym_1_5037
+.globl sym_1_5038
+sym_1_5038: la $2, sym_1_5038
+.globl sym_1_5039
+sym_1_5039: la $2, sym_1_5039
+.globl sym_1_5040
+sym_1_5040: la $2, sym_1_5040
+.globl sym_1_5041
+sym_1_5041: la $2, sym_1_5041
+.globl sym_1_5042
+sym_1_5042: la $2, sym_1_5042
+.globl sym_1_5043
+sym_1_5043: la $2, sym_1_5043
+.globl sym_1_5044
+sym_1_5044: la $2, sym_1_5044
+.globl sym_1_5045
+sym_1_5045: la $2, sym_1_5045
+.globl sym_1_5046
+sym_1_5046: la $2, sym_1_5046
+.globl sym_1_5047
+sym_1_5047: la $2, sym_1_5047
+.globl sym_1_5048
+sym_1_5048: la $2, sym_1_5048
+.globl sym_1_5049
+sym_1_5049: la $2, sym_1_5049
+.globl sym_1_5050
+sym_1_5050: la $2, sym_1_5050
+.globl sym_1_5051
+sym_1_5051: la $2, sym_1_5051
+.globl sym_1_5052
+sym_1_5052: la $2, sym_1_5052
+.globl sym_1_5053
+sym_1_5053: la $2, sym_1_5053
+.globl sym_1_5054
+sym_1_5054: la $2, sym_1_5054
+.globl sym_1_5055
+sym_1_5055: la $2, sym_1_5055
+.globl sym_1_5056
+sym_1_5056: la $2, sym_1_5056
+.globl sym_1_5057
+sym_1_5057: la $2, sym_1_5057
+.globl sym_1_5058
+sym_1_5058: la $2, sym_1_5058
+.globl sym_1_5059
+sym_1_5059: la $2, sym_1_5059
+.globl sym_1_5060
+sym_1_5060: la $2, sym_1_5060
+.globl sym_1_5061
+sym_1_5061: la $2, sym_1_5061
+.globl sym_1_5062
+sym_1_5062: la $2, sym_1_5062
+.globl sym_1_5063
+sym_1_5063: la $2, sym_1_5063
+.globl sym_1_5064
+sym_1_5064: la $2, sym_1_5064
+.globl sym_1_5065
+sym_1_5065: la $2, sym_1_5065
+.globl sym_1_5066
+sym_1_5066: la $2, sym_1_5066
+.globl sym_1_5067
+sym_1_5067: la $2, sym_1_5067
+.globl sym_1_5068
+sym_1_5068: la $2, sym_1_5068
+.globl sym_1_5069
+sym_1_5069: la $2, sym_1_5069
+.globl sym_1_5070
+sym_1_5070: la $2, sym_1_5070
+.globl sym_1_5071
+sym_1_5071: la $2, sym_1_5071
+.globl sym_1_5072
+sym_1_5072: la $2, sym_1_5072
+.globl sym_1_5073
+sym_1_5073: la $2, sym_1_5073
+.globl sym_1_5074
+sym_1_5074: la $2, sym_1_5074
+.globl sym_1_5075
+sym_1_5075: la $2, sym_1_5075
+.globl sym_1_5076
+sym_1_5076: la $2, sym_1_5076
+.globl sym_1_5077
+sym_1_5077: la $2, sym_1_5077
+.globl sym_1_5078
+sym_1_5078: la $2, sym_1_5078
+.globl sym_1_5079
+sym_1_5079: la $2, sym_1_5079
+.globl sym_1_5080
+sym_1_5080: la $2, sym_1_5080
+.globl sym_1_5081
+sym_1_5081: la $2, sym_1_5081
+.globl sym_1_5082
+sym_1_5082: la $2, sym_1_5082
+.globl sym_1_5083
+sym_1_5083: la $2, sym_1_5083
+.globl sym_1_5084
+sym_1_5084: la $2, sym_1_5084
+.globl sym_1_5085
+sym_1_5085: la $2, sym_1_5085
+.globl sym_1_5086
+sym_1_5086: la $2, sym_1_5086
+.globl sym_1_5087
+sym_1_5087: la $2, sym_1_5087
+.globl sym_1_5088
+sym_1_5088: la $2, sym_1_5088
+.globl sym_1_5089
+sym_1_5089: la $2, sym_1_5089
+.globl sym_1_5090
+sym_1_5090: la $2, sym_1_5090
+.globl sym_1_5091
+sym_1_5091: la $2, sym_1_5091
+.globl sym_1_5092
+sym_1_5092: la $2, sym_1_5092
+.globl sym_1_5093
+sym_1_5093: la $2, sym_1_5093
+.globl sym_1_5094
+sym_1_5094: la $2, sym_1_5094
+.globl sym_1_5095
+sym_1_5095: la $2, sym_1_5095
+.globl sym_1_5096
+sym_1_5096: la $2, sym_1_5096
+.globl sym_1_5097
+sym_1_5097: la $2, sym_1_5097
+.globl sym_1_5098
+sym_1_5098: la $2, sym_1_5098
+.globl sym_1_5099
+sym_1_5099: la $2, sym_1_5099
+.globl sym_1_5100
+sym_1_5100: la $2, sym_1_5100
+.globl sym_1_5101
+sym_1_5101: la $2, sym_1_5101
+.globl sym_1_5102
+sym_1_5102: la $2, sym_1_5102
+.globl sym_1_5103
+sym_1_5103: la $2, sym_1_5103
+.globl sym_1_5104
+sym_1_5104: la $2, sym_1_5104
+.globl sym_1_5105
+sym_1_5105: la $2, sym_1_5105
+.globl sym_1_5106
+sym_1_5106: la $2, sym_1_5106
+.globl sym_1_5107
+sym_1_5107: la $2, sym_1_5107
+.globl sym_1_5108
+sym_1_5108: la $2, sym_1_5108
+.globl sym_1_5109
+sym_1_5109: la $2, sym_1_5109
+.globl sym_1_5110
+sym_1_5110: la $2, sym_1_5110
+.globl sym_1_5111
+sym_1_5111: la $2, sym_1_5111
+.globl sym_1_5112
+sym_1_5112: la $2, sym_1_5112
+.globl sym_1_5113
+sym_1_5113: la $2, sym_1_5113
+.globl sym_1_5114
+sym_1_5114: la $2, sym_1_5114
+.globl sym_1_5115
+sym_1_5115: la $2, sym_1_5115
+.globl sym_1_5116
+sym_1_5116: la $2, sym_1_5116
+.globl sym_1_5117
+sym_1_5117: la $2, sym_1_5117
+.globl sym_1_5118
+sym_1_5118: la $2, sym_1_5118
+.globl sym_1_5119
+sym_1_5119: la $2, sym_1_5119
+.globl sym_1_5120
+sym_1_5120: la $2, sym_1_5120
+.globl sym_1_5121
+sym_1_5121: la $2, sym_1_5121
+.globl sym_1_5122
+sym_1_5122: la $2, sym_1_5122
+.globl sym_1_5123
+sym_1_5123: la $2, sym_1_5123
+.globl sym_1_5124
+sym_1_5124: la $2, sym_1_5124
+.globl sym_1_5125
+sym_1_5125: la $2, sym_1_5125
+.globl sym_1_5126
+sym_1_5126: la $2, sym_1_5126
+.globl sym_1_5127
+sym_1_5127: la $2, sym_1_5127
+.globl sym_1_5128
+sym_1_5128: la $2, sym_1_5128
+.globl sym_1_5129
+sym_1_5129: la $2, sym_1_5129
+.globl sym_1_5130
+sym_1_5130: la $2, sym_1_5130
+.globl sym_1_5131
+sym_1_5131: la $2, sym_1_5131
+.globl sym_1_5132
+sym_1_5132: la $2, sym_1_5132
+.globl sym_1_5133
+sym_1_5133: la $2, sym_1_5133
+.globl sym_1_5134
+sym_1_5134: la $2, sym_1_5134
+.globl sym_1_5135
+sym_1_5135: la $2, sym_1_5135
+.globl sym_1_5136
+sym_1_5136: la $2, sym_1_5136
+.globl sym_1_5137
+sym_1_5137: la $2, sym_1_5137
+.globl sym_1_5138
+sym_1_5138: la $2, sym_1_5138
+.globl sym_1_5139
+sym_1_5139: la $2, sym_1_5139
+.globl sym_1_5140
+sym_1_5140: la $2, sym_1_5140
+.globl sym_1_5141
+sym_1_5141: la $2, sym_1_5141
+.globl sym_1_5142
+sym_1_5142: la $2, sym_1_5142
+.globl sym_1_5143
+sym_1_5143: la $2, sym_1_5143
+.globl sym_1_5144
+sym_1_5144: la $2, sym_1_5144
+.globl sym_1_5145
+sym_1_5145: la $2, sym_1_5145
+.globl sym_1_5146
+sym_1_5146: la $2, sym_1_5146
+.globl sym_1_5147
+sym_1_5147: la $2, sym_1_5147
+.globl sym_1_5148
+sym_1_5148: la $2, sym_1_5148
+.globl sym_1_5149
+sym_1_5149: la $2, sym_1_5149
+.globl sym_1_5150
+sym_1_5150: la $2, sym_1_5150
+.globl sym_1_5151
+sym_1_5151: la $2, sym_1_5151
+.globl sym_1_5152
+sym_1_5152: la $2, sym_1_5152
+.globl sym_1_5153
+sym_1_5153: la $2, sym_1_5153
+.globl sym_1_5154
+sym_1_5154: la $2, sym_1_5154
+.globl sym_1_5155
+sym_1_5155: la $2, sym_1_5155
+.globl sym_1_5156
+sym_1_5156: la $2, sym_1_5156
+.globl sym_1_5157
+sym_1_5157: la $2, sym_1_5157
+.globl sym_1_5158
+sym_1_5158: la $2, sym_1_5158
+.globl sym_1_5159
+sym_1_5159: la $2, sym_1_5159
+.globl sym_1_5160
+sym_1_5160: la $2, sym_1_5160
+.globl sym_1_5161
+sym_1_5161: la $2, sym_1_5161
+.globl sym_1_5162
+sym_1_5162: la $2, sym_1_5162
+.globl sym_1_5163
+sym_1_5163: la $2, sym_1_5163
+.globl sym_1_5164
+sym_1_5164: la $2, sym_1_5164
+.globl sym_1_5165
+sym_1_5165: la $2, sym_1_5165
+.globl sym_1_5166
+sym_1_5166: la $2, sym_1_5166
+.globl sym_1_5167
+sym_1_5167: la $2, sym_1_5167
+.globl sym_1_5168
+sym_1_5168: la $2, sym_1_5168
+.globl sym_1_5169
+sym_1_5169: la $2, sym_1_5169
+.globl sym_1_5170
+sym_1_5170: la $2, sym_1_5170
+.globl sym_1_5171
+sym_1_5171: la $2, sym_1_5171
+.globl sym_1_5172
+sym_1_5172: la $2, sym_1_5172
+.globl sym_1_5173
+sym_1_5173: la $2, sym_1_5173
+.globl sym_1_5174
+sym_1_5174: la $2, sym_1_5174
+.globl sym_1_5175
+sym_1_5175: la $2, sym_1_5175
+.globl sym_1_5176
+sym_1_5176: la $2, sym_1_5176
+.globl sym_1_5177
+sym_1_5177: la $2, sym_1_5177
+.globl sym_1_5178
+sym_1_5178: la $2, sym_1_5178
+.globl sym_1_5179
+sym_1_5179: la $2, sym_1_5179
+.globl sym_1_5180
+sym_1_5180: la $2, sym_1_5180
+.globl sym_1_5181
+sym_1_5181: la $2, sym_1_5181
+.globl sym_1_5182
+sym_1_5182: la $2, sym_1_5182
+.globl sym_1_5183
+sym_1_5183: la $2, sym_1_5183
+.globl sym_1_5184
+sym_1_5184: la $2, sym_1_5184
+.globl sym_1_5185
+sym_1_5185: la $2, sym_1_5185
+.globl sym_1_5186
+sym_1_5186: la $2, sym_1_5186
+.globl sym_1_5187
+sym_1_5187: la $2, sym_1_5187
+.globl sym_1_5188
+sym_1_5188: la $2, sym_1_5188
+.globl sym_1_5189
+sym_1_5189: la $2, sym_1_5189
+.globl sym_1_5190
+sym_1_5190: la $2, sym_1_5190
+.globl sym_1_5191
+sym_1_5191: la $2, sym_1_5191
+.globl sym_1_5192
+sym_1_5192: la $2, sym_1_5192
+.globl sym_1_5193
+sym_1_5193: la $2, sym_1_5193
+.globl sym_1_5194
+sym_1_5194: la $2, sym_1_5194
+.globl sym_1_5195
+sym_1_5195: la $2, sym_1_5195
+.globl sym_1_5196
+sym_1_5196: la $2, sym_1_5196
+.globl sym_1_5197
+sym_1_5197: la $2, sym_1_5197
+.globl sym_1_5198
+sym_1_5198: la $2, sym_1_5198
+.globl sym_1_5199
+sym_1_5199: la $2, sym_1_5199
+.globl sym_1_5200
+sym_1_5200: la $2, sym_1_5200
+.globl sym_1_5201
+sym_1_5201: la $2, sym_1_5201
+.globl sym_1_5202
+sym_1_5202: la $2, sym_1_5202
+.globl sym_1_5203
+sym_1_5203: la $2, sym_1_5203
+.globl sym_1_5204
+sym_1_5204: la $2, sym_1_5204
+.globl sym_1_5205
+sym_1_5205: la $2, sym_1_5205
+.globl sym_1_5206
+sym_1_5206: la $2, sym_1_5206
+.globl sym_1_5207
+sym_1_5207: la $2, sym_1_5207
+.globl sym_1_5208
+sym_1_5208: la $2, sym_1_5208
+.globl sym_1_5209
+sym_1_5209: la $2, sym_1_5209
+.globl sym_1_5210
+sym_1_5210: la $2, sym_1_5210
+.globl sym_1_5211
+sym_1_5211: la $2, sym_1_5211
+.globl sym_1_5212
+sym_1_5212: la $2, sym_1_5212
+.globl sym_1_5213
+sym_1_5213: la $2, sym_1_5213
+.globl sym_1_5214
+sym_1_5214: la $2, sym_1_5214
+.globl sym_1_5215
+sym_1_5215: la $2, sym_1_5215
+.globl sym_1_5216
+sym_1_5216: la $2, sym_1_5216
+.globl sym_1_5217
+sym_1_5217: la $2, sym_1_5217
+.globl sym_1_5218
+sym_1_5218: la $2, sym_1_5218
+.globl sym_1_5219
+sym_1_5219: la $2, sym_1_5219
+.globl sym_1_5220
+sym_1_5220: la $2, sym_1_5220
+.globl sym_1_5221
+sym_1_5221: la $2, sym_1_5221
+.globl sym_1_5222
+sym_1_5222: la $2, sym_1_5222
+.globl sym_1_5223
+sym_1_5223: la $2, sym_1_5223
+.globl sym_1_5224
+sym_1_5224: la $2, sym_1_5224
+.globl sym_1_5225
+sym_1_5225: la $2, sym_1_5225
+.globl sym_1_5226
+sym_1_5226: la $2, sym_1_5226
+.globl sym_1_5227
+sym_1_5227: la $2, sym_1_5227
+.globl sym_1_5228
+sym_1_5228: la $2, sym_1_5228
+.globl sym_1_5229
+sym_1_5229: la $2, sym_1_5229
+.globl sym_1_5230
+sym_1_5230: la $2, sym_1_5230
+.globl sym_1_5231
+sym_1_5231: la $2, sym_1_5231
+.globl sym_1_5232
+sym_1_5232: la $2, sym_1_5232
+.globl sym_1_5233
+sym_1_5233: la $2, sym_1_5233
+.globl sym_1_5234
+sym_1_5234: la $2, sym_1_5234
+.globl sym_1_5235
+sym_1_5235: la $2, sym_1_5235
+.globl sym_1_5236
+sym_1_5236: la $2, sym_1_5236
+.globl sym_1_5237
+sym_1_5237: la $2, sym_1_5237
+.globl sym_1_5238
+sym_1_5238: la $2, sym_1_5238
+.globl sym_1_5239
+sym_1_5239: la $2, sym_1_5239
+.globl sym_1_5240
+sym_1_5240: la $2, sym_1_5240
+.globl sym_1_5241
+sym_1_5241: la $2, sym_1_5241
+.globl sym_1_5242
+sym_1_5242: la $2, sym_1_5242
+.globl sym_1_5243
+sym_1_5243: la $2, sym_1_5243
+.globl sym_1_5244
+sym_1_5244: la $2, sym_1_5244
+.globl sym_1_5245
+sym_1_5245: la $2, sym_1_5245
+.globl sym_1_5246
+sym_1_5246: la $2, sym_1_5246
+.globl sym_1_5247
+sym_1_5247: la $2, sym_1_5247
+.globl sym_1_5248
+sym_1_5248: la $2, sym_1_5248
+.globl sym_1_5249
+sym_1_5249: la $2, sym_1_5249
+.globl sym_1_5250
+sym_1_5250: la $2, sym_1_5250
+.globl sym_1_5251
+sym_1_5251: la $2, sym_1_5251
+.globl sym_1_5252
+sym_1_5252: la $2, sym_1_5252
+.globl sym_1_5253
+sym_1_5253: la $2, sym_1_5253
+.globl sym_1_5254
+sym_1_5254: la $2, sym_1_5254
+.globl sym_1_5255
+sym_1_5255: la $2, sym_1_5255
+.globl sym_1_5256
+sym_1_5256: la $2, sym_1_5256
+.globl sym_1_5257
+sym_1_5257: la $2, sym_1_5257
+.globl sym_1_5258
+sym_1_5258: la $2, sym_1_5258
+.globl sym_1_5259
+sym_1_5259: la $2, sym_1_5259
+.globl sym_1_5260
+sym_1_5260: la $2, sym_1_5260
+.globl sym_1_5261
+sym_1_5261: la $2, sym_1_5261
+.globl sym_1_5262
+sym_1_5262: la $2, sym_1_5262
+.globl sym_1_5263
+sym_1_5263: la $2, sym_1_5263
+.globl sym_1_5264
+sym_1_5264: la $2, sym_1_5264
+.globl sym_1_5265
+sym_1_5265: la $2, sym_1_5265
+.globl sym_1_5266
+sym_1_5266: la $2, sym_1_5266
+.globl sym_1_5267
+sym_1_5267: la $2, sym_1_5267
+.globl sym_1_5268
+sym_1_5268: la $2, sym_1_5268
+.globl sym_1_5269
+sym_1_5269: la $2, sym_1_5269
+.globl sym_1_5270
+sym_1_5270: la $2, sym_1_5270
+.globl sym_1_5271
+sym_1_5271: la $2, sym_1_5271
+.globl sym_1_5272
+sym_1_5272: la $2, sym_1_5272
+.globl sym_1_5273
+sym_1_5273: la $2, sym_1_5273
+.globl sym_1_5274
+sym_1_5274: la $2, sym_1_5274
+.globl sym_1_5275
+sym_1_5275: la $2, sym_1_5275
+.globl sym_1_5276
+sym_1_5276: la $2, sym_1_5276
+.globl sym_1_5277
+sym_1_5277: la $2, sym_1_5277
+.globl sym_1_5278
+sym_1_5278: la $2, sym_1_5278
+.globl sym_1_5279
+sym_1_5279: la $2, sym_1_5279
+.globl sym_1_5280
+sym_1_5280: la $2, sym_1_5280
+.globl sym_1_5281
+sym_1_5281: la $2, sym_1_5281
+.globl sym_1_5282
+sym_1_5282: la $2, sym_1_5282
+.globl sym_1_5283
+sym_1_5283: la $2, sym_1_5283
+.globl sym_1_5284
+sym_1_5284: la $2, sym_1_5284
+.globl sym_1_5285
+sym_1_5285: la $2, sym_1_5285
+.globl sym_1_5286
+sym_1_5286: la $2, sym_1_5286
+.globl sym_1_5287
+sym_1_5287: la $2, sym_1_5287
+.globl sym_1_5288
+sym_1_5288: la $2, sym_1_5288
+.globl sym_1_5289
+sym_1_5289: la $2, sym_1_5289
+.globl sym_1_5290
+sym_1_5290: la $2, sym_1_5290
+.globl sym_1_5291
+sym_1_5291: la $2, sym_1_5291
+.globl sym_1_5292
+sym_1_5292: la $2, sym_1_5292
+.globl sym_1_5293
+sym_1_5293: la $2, sym_1_5293
+.globl sym_1_5294
+sym_1_5294: la $2, sym_1_5294
+.globl sym_1_5295
+sym_1_5295: la $2, sym_1_5295
+.globl sym_1_5296
+sym_1_5296: la $2, sym_1_5296
+.globl sym_1_5297
+sym_1_5297: la $2, sym_1_5297
+.globl sym_1_5298
+sym_1_5298: la $2, sym_1_5298
+.globl sym_1_5299
+sym_1_5299: la $2, sym_1_5299
+.globl sym_1_5300
+sym_1_5300: la $2, sym_1_5300
+.globl sym_1_5301
+sym_1_5301: la $2, sym_1_5301
+.globl sym_1_5302
+sym_1_5302: la $2, sym_1_5302
+.globl sym_1_5303
+sym_1_5303: la $2, sym_1_5303
+.globl sym_1_5304
+sym_1_5304: la $2, sym_1_5304
+.globl sym_1_5305
+sym_1_5305: la $2, sym_1_5305
+.globl sym_1_5306
+sym_1_5306: la $2, sym_1_5306
+.globl sym_1_5307
+sym_1_5307: la $2, sym_1_5307
+.globl sym_1_5308
+sym_1_5308: la $2, sym_1_5308
+.globl sym_1_5309
+sym_1_5309: la $2, sym_1_5309
+.globl sym_1_5310
+sym_1_5310: la $2, sym_1_5310
+.globl sym_1_5311
+sym_1_5311: la $2, sym_1_5311
+.globl sym_1_5312
+sym_1_5312: la $2, sym_1_5312
+.globl sym_1_5313
+sym_1_5313: la $2, sym_1_5313
+.globl sym_1_5314
+sym_1_5314: la $2, sym_1_5314
+.globl sym_1_5315
+sym_1_5315: la $2, sym_1_5315
+.globl sym_1_5316
+sym_1_5316: la $2, sym_1_5316
+.globl sym_1_5317
+sym_1_5317: la $2, sym_1_5317
+.globl sym_1_5318
+sym_1_5318: la $2, sym_1_5318
+.globl sym_1_5319
+sym_1_5319: la $2, sym_1_5319
+.globl sym_1_5320
+sym_1_5320: la $2, sym_1_5320
+.globl sym_1_5321
+sym_1_5321: la $2, sym_1_5321
+.globl sym_1_5322
+sym_1_5322: la $2, sym_1_5322
+.globl sym_1_5323
+sym_1_5323: la $2, sym_1_5323
+.globl sym_1_5324
+sym_1_5324: la $2, sym_1_5324
+.globl sym_1_5325
+sym_1_5325: la $2, sym_1_5325
+.globl sym_1_5326
+sym_1_5326: la $2, sym_1_5326
+.globl sym_1_5327
+sym_1_5327: la $2, sym_1_5327
+.globl sym_1_5328
+sym_1_5328: la $2, sym_1_5328
+.globl sym_1_5329
+sym_1_5329: la $2, sym_1_5329
+.globl sym_1_5330
+sym_1_5330: la $2, sym_1_5330
+.globl sym_1_5331
+sym_1_5331: la $2, sym_1_5331
+.globl sym_1_5332
+sym_1_5332: la $2, sym_1_5332
+.globl sym_1_5333
+sym_1_5333: la $2, sym_1_5333
+.globl sym_1_5334
+sym_1_5334: la $2, sym_1_5334
+.globl sym_1_5335
+sym_1_5335: la $2, sym_1_5335
+.globl sym_1_5336
+sym_1_5336: la $2, sym_1_5336
+.globl sym_1_5337
+sym_1_5337: la $2, sym_1_5337
+.globl sym_1_5338
+sym_1_5338: la $2, sym_1_5338
+.globl sym_1_5339
+sym_1_5339: la $2, sym_1_5339
+.globl sym_1_5340
+sym_1_5340: la $2, sym_1_5340
+.globl sym_1_5341
+sym_1_5341: la $2, sym_1_5341
+.globl sym_1_5342
+sym_1_5342: la $2, sym_1_5342
+.globl sym_1_5343
+sym_1_5343: la $2, sym_1_5343
+.globl sym_1_5344
+sym_1_5344: la $2, sym_1_5344
+.globl sym_1_5345
+sym_1_5345: la $2, sym_1_5345
+.globl sym_1_5346
+sym_1_5346: la $2, sym_1_5346
+.globl sym_1_5347
+sym_1_5347: la $2, sym_1_5347
+.globl sym_1_5348
+sym_1_5348: la $2, sym_1_5348
+.globl sym_1_5349
+sym_1_5349: la $2, sym_1_5349
+.globl sym_1_5350
+sym_1_5350: la $2, sym_1_5350
+.globl sym_1_5351
+sym_1_5351: la $2, sym_1_5351
+.globl sym_1_5352
+sym_1_5352: la $2, sym_1_5352
+.globl sym_1_5353
+sym_1_5353: la $2, sym_1_5353
+.globl sym_1_5354
+sym_1_5354: la $2, sym_1_5354
+.globl sym_1_5355
+sym_1_5355: la $2, sym_1_5355
+.globl sym_1_5356
+sym_1_5356: la $2, sym_1_5356
+.globl sym_1_5357
+sym_1_5357: la $2, sym_1_5357
+.globl sym_1_5358
+sym_1_5358: la $2, sym_1_5358
+.globl sym_1_5359
+sym_1_5359: la $2, sym_1_5359
+.globl sym_1_5360
+sym_1_5360: la $2, sym_1_5360
+.globl sym_1_5361
+sym_1_5361: la $2, sym_1_5361
+.globl sym_1_5362
+sym_1_5362: la $2, sym_1_5362
+.globl sym_1_5363
+sym_1_5363: la $2, sym_1_5363
+.globl sym_1_5364
+sym_1_5364: la $2, sym_1_5364
+.globl sym_1_5365
+sym_1_5365: la $2, sym_1_5365
+.globl sym_1_5366
+sym_1_5366: la $2, sym_1_5366
+.globl sym_1_5367
+sym_1_5367: la $2, sym_1_5367
+.globl sym_1_5368
+sym_1_5368: la $2, sym_1_5368
+.globl sym_1_5369
+sym_1_5369: la $2, sym_1_5369
+.globl sym_1_5370
+sym_1_5370: la $2, sym_1_5370
+.globl sym_1_5371
+sym_1_5371: la $2, sym_1_5371
+.globl sym_1_5372
+sym_1_5372: la $2, sym_1_5372
+.globl sym_1_5373
+sym_1_5373: la $2, sym_1_5373
+.globl sym_1_5374
+sym_1_5374: la $2, sym_1_5374
+.globl sym_1_5375
+sym_1_5375: la $2, sym_1_5375
+.globl sym_1_5376
+sym_1_5376: la $2, sym_1_5376
+.globl sym_1_5377
+sym_1_5377: la $2, sym_1_5377
+.globl sym_1_5378
+sym_1_5378: la $2, sym_1_5378
+.globl sym_1_5379
+sym_1_5379: la $2, sym_1_5379
+.globl sym_1_5380
+sym_1_5380: la $2, sym_1_5380
+.globl sym_1_5381
+sym_1_5381: la $2, sym_1_5381
+.globl sym_1_5382
+sym_1_5382: la $2, sym_1_5382
+.globl sym_1_5383
+sym_1_5383: la $2, sym_1_5383
+.globl sym_1_5384
+sym_1_5384: la $2, sym_1_5384
+.globl sym_1_5385
+sym_1_5385: la $2, sym_1_5385
+.globl sym_1_5386
+sym_1_5386: la $2, sym_1_5386
+.globl sym_1_5387
+sym_1_5387: la $2, sym_1_5387
+.globl sym_1_5388
+sym_1_5388: la $2, sym_1_5388
+.globl sym_1_5389
+sym_1_5389: la $2, sym_1_5389
+.globl sym_1_5390
+sym_1_5390: la $2, sym_1_5390
+.globl sym_1_5391
+sym_1_5391: la $2, sym_1_5391
+.globl sym_1_5392
+sym_1_5392: la $2, sym_1_5392
+.globl sym_1_5393
+sym_1_5393: la $2, sym_1_5393
+.globl sym_1_5394
+sym_1_5394: la $2, sym_1_5394
+.globl sym_1_5395
+sym_1_5395: la $2, sym_1_5395
+.globl sym_1_5396
+sym_1_5396: la $2, sym_1_5396
+.globl sym_1_5397
+sym_1_5397: la $2, sym_1_5397
+.globl sym_1_5398
+sym_1_5398: la $2, sym_1_5398
+.globl sym_1_5399
+sym_1_5399: la $2, sym_1_5399
+.globl sym_1_5400
+sym_1_5400: la $2, sym_1_5400
+.globl sym_1_5401
+sym_1_5401: la $2, sym_1_5401
+.globl sym_1_5402
+sym_1_5402: la $2, sym_1_5402
+.globl sym_1_5403
+sym_1_5403: la $2, sym_1_5403
+.globl sym_1_5404
+sym_1_5404: la $2, sym_1_5404
+.globl sym_1_5405
+sym_1_5405: la $2, sym_1_5405
+.globl sym_1_5406
+sym_1_5406: la $2, sym_1_5406
+.globl sym_1_5407
+sym_1_5407: la $2, sym_1_5407
+.globl sym_1_5408
+sym_1_5408: la $2, sym_1_5408
+.globl sym_1_5409
+sym_1_5409: la $2, sym_1_5409
+.globl sym_1_5410
+sym_1_5410: la $2, sym_1_5410
+.globl sym_1_5411
+sym_1_5411: la $2, sym_1_5411
+.globl sym_1_5412
+sym_1_5412: la $2, sym_1_5412
+.globl sym_1_5413
+sym_1_5413: la $2, sym_1_5413
+.globl sym_1_5414
+sym_1_5414: la $2, sym_1_5414
+.globl sym_1_5415
+sym_1_5415: la $2, sym_1_5415
+.globl sym_1_5416
+sym_1_5416: la $2, sym_1_5416
+.globl sym_1_5417
+sym_1_5417: la $2, sym_1_5417
+.globl sym_1_5418
+sym_1_5418: la $2, sym_1_5418
+.globl sym_1_5419
+sym_1_5419: la $2, sym_1_5419
+.globl sym_1_5420
+sym_1_5420: la $2, sym_1_5420
+.globl sym_1_5421
+sym_1_5421: la $2, sym_1_5421
+.globl sym_1_5422
+sym_1_5422: la $2, sym_1_5422
+.globl sym_1_5423
+sym_1_5423: la $2, sym_1_5423
+.globl sym_1_5424
+sym_1_5424: la $2, sym_1_5424
+.globl sym_1_5425
+sym_1_5425: la $2, sym_1_5425
+.globl sym_1_5426
+sym_1_5426: la $2, sym_1_5426
+.globl sym_1_5427
+sym_1_5427: la $2, sym_1_5427
+.globl sym_1_5428
+sym_1_5428: la $2, sym_1_5428
+.globl sym_1_5429
+sym_1_5429: la $2, sym_1_5429
+.globl sym_1_5430
+sym_1_5430: la $2, sym_1_5430
+.globl sym_1_5431
+sym_1_5431: la $2, sym_1_5431
+.globl sym_1_5432
+sym_1_5432: la $2, sym_1_5432
+.globl sym_1_5433
+sym_1_5433: la $2, sym_1_5433
+.globl sym_1_5434
+sym_1_5434: la $2, sym_1_5434
+.globl sym_1_5435
+sym_1_5435: la $2, sym_1_5435
+.globl sym_1_5436
+sym_1_5436: la $2, sym_1_5436
+.globl sym_1_5437
+sym_1_5437: la $2, sym_1_5437
+.globl sym_1_5438
+sym_1_5438: la $2, sym_1_5438
+.globl sym_1_5439
+sym_1_5439: la $2, sym_1_5439
+.globl sym_1_5440
+sym_1_5440: la $2, sym_1_5440
+.globl sym_1_5441
+sym_1_5441: la $2, sym_1_5441
+.globl sym_1_5442
+sym_1_5442: la $2, sym_1_5442
+.globl sym_1_5443
+sym_1_5443: la $2, sym_1_5443
+.globl sym_1_5444
+sym_1_5444: la $2, sym_1_5444
+.globl sym_1_5445
+sym_1_5445: la $2, sym_1_5445
+.globl sym_1_5446
+sym_1_5446: la $2, sym_1_5446
+.globl sym_1_5447
+sym_1_5447: la $2, sym_1_5447
+.globl sym_1_5448
+sym_1_5448: la $2, sym_1_5448
+.globl sym_1_5449
+sym_1_5449: la $2, sym_1_5449
+.globl sym_1_5450
+sym_1_5450: la $2, sym_1_5450
+.globl sym_1_5451
+sym_1_5451: la $2, sym_1_5451
+.globl sym_1_5452
+sym_1_5452: la $2, sym_1_5452
+.globl sym_1_5453
+sym_1_5453: la $2, sym_1_5453
+.globl sym_1_5454
+sym_1_5454: la $2, sym_1_5454
+.globl sym_1_5455
+sym_1_5455: la $2, sym_1_5455
+.globl sym_1_5456
+sym_1_5456: la $2, sym_1_5456
+.globl sym_1_5457
+sym_1_5457: la $2, sym_1_5457
+.globl sym_1_5458
+sym_1_5458: la $2, sym_1_5458
+.globl sym_1_5459
+sym_1_5459: la $2, sym_1_5459
+.globl sym_1_5460
+sym_1_5460: la $2, sym_1_5460
+.globl sym_1_5461
+sym_1_5461: la $2, sym_1_5461
+.globl sym_1_5462
+sym_1_5462: la $2, sym_1_5462
+.globl sym_1_5463
+sym_1_5463: la $2, sym_1_5463
+.globl sym_1_5464
+sym_1_5464: la $2, sym_1_5464
+.globl sym_1_5465
+sym_1_5465: la $2, sym_1_5465
+.globl sym_1_5466
+sym_1_5466: la $2, sym_1_5466
+.globl sym_1_5467
+sym_1_5467: la $2, sym_1_5467
+.globl sym_1_5468
+sym_1_5468: la $2, sym_1_5468
+.globl sym_1_5469
+sym_1_5469: la $2, sym_1_5469
+.globl sym_1_5470
+sym_1_5470: la $2, sym_1_5470
+.globl sym_1_5471
+sym_1_5471: la $2, sym_1_5471
+.globl sym_1_5472
+sym_1_5472: la $2, sym_1_5472
+.globl sym_1_5473
+sym_1_5473: la $2, sym_1_5473
+.globl sym_1_5474
+sym_1_5474: la $2, sym_1_5474
+.globl sym_1_5475
+sym_1_5475: la $2, sym_1_5475
+.globl sym_1_5476
+sym_1_5476: la $2, sym_1_5476
+.globl sym_1_5477
+sym_1_5477: la $2, sym_1_5477
+.globl sym_1_5478
+sym_1_5478: la $2, sym_1_5478
+.globl sym_1_5479
+sym_1_5479: la $2, sym_1_5479
+.globl sym_1_5480
+sym_1_5480: la $2, sym_1_5480
+.globl sym_1_5481
+sym_1_5481: la $2, sym_1_5481
+.globl sym_1_5482
+sym_1_5482: la $2, sym_1_5482
+.globl sym_1_5483
+sym_1_5483: la $2, sym_1_5483
+.globl sym_1_5484
+sym_1_5484: la $2, sym_1_5484
+.globl sym_1_5485
+sym_1_5485: la $2, sym_1_5485
+.globl sym_1_5486
+sym_1_5486: la $2, sym_1_5486
+.globl sym_1_5487
+sym_1_5487: la $2, sym_1_5487
+.globl sym_1_5488
+sym_1_5488: la $2, sym_1_5488
+.globl sym_1_5489
+sym_1_5489: la $2, sym_1_5489
+.globl sym_1_5490
+sym_1_5490: la $2, sym_1_5490
+.globl sym_1_5491
+sym_1_5491: la $2, sym_1_5491
+.globl sym_1_5492
+sym_1_5492: la $2, sym_1_5492
+.globl sym_1_5493
+sym_1_5493: la $2, sym_1_5493
+.globl sym_1_5494
+sym_1_5494: la $2, sym_1_5494
+.globl sym_1_5495
+sym_1_5495: la $2, sym_1_5495
+.globl sym_1_5496
+sym_1_5496: la $2, sym_1_5496
+.globl sym_1_5497
+sym_1_5497: la $2, sym_1_5497
+.globl sym_1_5498
+sym_1_5498: la $2, sym_1_5498
+.globl sym_1_5499
+sym_1_5499: la $2, sym_1_5499
+.globl sym_1_5500
+sym_1_5500: la $2, sym_1_5500
+.globl sym_1_5501
+sym_1_5501: la $2, sym_1_5501
+.globl sym_1_5502
+sym_1_5502: la $2, sym_1_5502
+.globl sym_1_5503
+sym_1_5503: la $2, sym_1_5503
+.globl sym_1_5504
+sym_1_5504: la $2, sym_1_5504
+.globl sym_1_5505
+sym_1_5505: la $2, sym_1_5505
+.globl sym_1_5506
+sym_1_5506: la $2, sym_1_5506
+.globl sym_1_5507
+sym_1_5507: la $2, sym_1_5507
+.globl sym_1_5508
+sym_1_5508: la $2, sym_1_5508
+.globl sym_1_5509
+sym_1_5509: la $2, sym_1_5509
+.globl sym_1_5510
+sym_1_5510: la $2, sym_1_5510
+.globl sym_1_5511
+sym_1_5511: la $2, sym_1_5511
+.globl sym_1_5512
+sym_1_5512: la $2, sym_1_5512
+.globl sym_1_5513
+sym_1_5513: la $2, sym_1_5513
+.globl sym_1_5514
+sym_1_5514: la $2, sym_1_5514
+.globl sym_1_5515
+sym_1_5515: la $2, sym_1_5515
+.globl sym_1_5516
+sym_1_5516: la $2, sym_1_5516
+.globl sym_1_5517
+sym_1_5517: la $2, sym_1_5517
+.globl sym_1_5518
+sym_1_5518: la $2, sym_1_5518
+.globl sym_1_5519
+sym_1_5519: la $2, sym_1_5519
+.globl sym_1_5520
+sym_1_5520: la $2, sym_1_5520
+.globl sym_1_5521
+sym_1_5521: la $2, sym_1_5521
+.globl sym_1_5522
+sym_1_5522: la $2, sym_1_5522
+.globl sym_1_5523
+sym_1_5523: la $2, sym_1_5523
+.globl sym_1_5524
+sym_1_5524: la $2, sym_1_5524
+.globl sym_1_5525
+sym_1_5525: la $2, sym_1_5525
+.globl sym_1_5526
+sym_1_5526: la $2, sym_1_5526
+.globl sym_1_5527
+sym_1_5527: la $2, sym_1_5527
+.globl sym_1_5528
+sym_1_5528: la $2, sym_1_5528
+.globl sym_1_5529
+sym_1_5529: la $2, sym_1_5529
+.globl sym_1_5530
+sym_1_5530: la $2, sym_1_5530
+.globl sym_1_5531
+sym_1_5531: la $2, sym_1_5531
+.globl sym_1_5532
+sym_1_5532: la $2, sym_1_5532
+.globl sym_1_5533
+sym_1_5533: la $2, sym_1_5533
+.globl sym_1_5534
+sym_1_5534: la $2, sym_1_5534
+.globl sym_1_5535
+sym_1_5535: la $2, sym_1_5535
+.globl sym_1_5536
+sym_1_5536: la $2, sym_1_5536
+.globl sym_1_5537
+sym_1_5537: la $2, sym_1_5537
+.globl sym_1_5538
+sym_1_5538: la $2, sym_1_5538
+.globl sym_1_5539
+sym_1_5539: la $2, sym_1_5539
+.globl sym_1_5540
+sym_1_5540: la $2, sym_1_5540
+.globl sym_1_5541
+sym_1_5541: la $2, sym_1_5541
+.globl sym_1_5542
+sym_1_5542: la $2, sym_1_5542
+.globl sym_1_5543
+sym_1_5543: la $2, sym_1_5543
+.globl sym_1_5544
+sym_1_5544: la $2, sym_1_5544
+.globl sym_1_5545
+sym_1_5545: la $2, sym_1_5545
+.globl sym_1_5546
+sym_1_5546: la $2, sym_1_5546
+.globl sym_1_5547
+sym_1_5547: la $2, sym_1_5547
+.globl sym_1_5548
+sym_1_5548: la $2, sym_1_5548
+.globl sym_1_5549
+sym_1_5549: la $2, sym_1_5549
+.globl sym_1_5550
+sym_1_5550: la $2, sym_1_5550
+.globl sym_1_5551
+sym_1_5551: la $2, sym_1_5551
+.globl sym_1_5552
+sym_1_5552: la $2, sym_1_5552
+.globl sym_1_5553
+sym_1_5553: la $2, sym_1_5553
+.globl sym_1_5554
+sym_1_5554: la $2, sym_1_5554
+.globl sym_1_5555
+sym_1_5555: la $2, sym_1_5555
+.globl sym_1_5556
+sym_1_5556: la $2, sym_1_5556
+.globl sym_1_5557
+sym_1_5557: la $2, sym_1_5557
+.globl sym_1_5558
+sym_1_5558: la $2, sym_1_5558
+.globl sym_1_5559
+sym_1_5559: la $2, sym_1_5559
+.globl sym_1_5560
+sym_1_5560: la $2, sym_1_5560
+.globl sym_1_5561
+sym_1_5561: la $2, sym_1_5561
+.globl sym_1_5562
+sym_1_5562: la $2, sym_1_5562
+.globl sym_1_5563
+sym_1_5563: la $2, sym_1_5563
+.globl sym_1_5564
+sym_1_5564: la $2, sym_1_5564
+.globl sym_1_5565
+sym_1_5565: la $2, sym_1_5565
+.globl sym_1_5566
+sym_1_5566: la $2, sym_1_5566
+.globl sym_1_5567
+sym_1_5567: la $2, sym_1_5567
+.globl sym_1_5568
+sym_1_5568: la $2, sym_1_5568
+.globl sym_1_5569
+sym_1_5569: la $2, sym_1_5569
+.globl sym_1_5570
+sym_1_5570: la $2, sym_1_5570
+.globl sym_1_5571
+sym_1_5571: la $2, sym_1_5571
+.globl sym_1_5572
+sym_1_5572: la $2, sym_1_5572
+.globl sym_1_5573
+sym_1_5573: la $2, sym_1_5573
+.globl sym_1_5574
+sym_1_5574: la $2, sym_1_5574
+.globl sym_1_5575
+sym_1_5575: la $2, sym_1_5575
+.globl sym_1_5576
+sym_1_5576: la $2, sym_1_5576
+.globl sym_1_5577
+sym_1_5577: la $2, sym_1_5577
+.globl sym_1_5578
+sym_1_5578: la $2, sym_1_5578
+.globl sym_1_5579
+sym_1_5579: la $2, sym_1_5579
+.globl sym_1_5580
+sym_1_5580: la $2, sym_1_5580
+.globl sym_1_5581
+sym_1_5581: la $2, sym_1_5581
+.globl sym_1_5582
+sym_1_5582: la $2, sym_1_5582
+.globl sym_1_5583
+sym_1_5583: la $2, sym_1_5583
+.globl sym_1_5584
+sym_1_5584: la $2, sym_1_5584
+.globl sym_1_5585
+sym_1_5585: la $2, sym_1_5585
+.globl sym_1_5586
+sym_1_5586: la $2, sym_1_5586
+.globl sym_1_5587
+sym_1_5587: la $2, sym_1_5587
+.globl sym_1_5588
+sym_1_5588: la $2, sym_1_5588
+.globl sym_1_5589
+sym_1_5589: la $2, sym_1_5589
+.globl sym_1_5590
+sym_1_5590: la $2, sym_1_5590
+.globl sym_1_5591
+sym_1_5591: la $2, sym_1_5591
+.globl sym_1_5592
+sym_1_5592: la $2, sym_1_5592
+.globl sym_1_5593
+sym_1_5593: la $2, sym_1_5593
+.globl sym_1_5594
+sym_1_5594: la $2, sym_1_5594
+.globl sym_1_5595
+sym_1_5595: la $2, sym_1_5595
+.globl sym_1_5596
+sym_1_5596: la $2, sym_1_5596
+.globl sym_1_5597
+sym_1_5597: la $2, sym_1_5597
+.globl sym_1_5598
+sym_1_5598: la $2, sym_1_5598
+.globl sym_1_5599
+sym_1_5599: la $2, sym_1_5599
+.globl sym_1_5600
+sym_1_5600: la $2, sym_1_5600
+.globl sym_1_5601
+sym_1_5601: la $2, sym_1_5601
+.globl sym_1_5602
+sym_1_5602: la $2, sym_1_5602
+.globl sym_1_5603
+sym_1_5603: la $2, sym_1_5603
+.globl sym_1_5604
+sym_1_5604: la $2, sym_1_5604
+.globl sym_1_5605
+sym_1_5605: la $2, sym_1_5605
+.globl sym_1_5606
+sym_1_5606: la $2, sym_1_5606
+.globl sym_1_5607
+sym_1_5607: la $2, sym_1_5607
+.globl sym_1_5608
+sym_1_5608: la $2, sym_1_5608
+.globl sym_1_5609
+sym_1_5609: la $2, sym_1_5609
+.globl sym_1_5610
+sym_1_5610: la $2, sym_1_5610
+.globl sym_1_5611
+sym_1_5611: la $2, sym_1_5611
+.globl sym_1_5612
+sym_1_5612: la $2, sym_1_5612
+.globl sym_1_5613
+sym_1_5613: la $2, sym_1_5613
+.globl sym_1_5614
+sym_1_5614: la $2, sym_1_5614
+.globl sym_1_5615
+sym_1_5615: la $2, sym_1_5615
+.globl sym_1_5616
+sym_1_5616: la $2, sym_1_5616
+.globl sym_1_5617
+sym_1_5617: la $2, sym_1_5617
+.globl sym_1_5618
+sym_1_5618: la $2, sym_1_5618
+.globl sym_1_5619
+sym_1_5619: la $2, sym_1_5619
+.globl sym_1_5620
+sym_1_5620: la $2, sym_1_5620
+.globl sym_1_5621
+sym_1_5621: la $2, sym_1_5621
+.globl sym_1_5622
+sym_1_5622: la $2, sym_1_5622
+.globl sym_1_5623
+sym_1_5623: la $2, sym_1_5623
+.globl sym_1_5624
+sym_1_5624: la $2, sym_1_5624
+.globl sym_1_5625
+sym_1_5625: la $2, sym_1_5625
+.globl sym_1_5626
+sym_1_5626: la $2, sym_1_5626
+.globl sym_1_5627
+sym_1_5627: la $2, sym_1_5627
+.globl sym_1_5628
+sym_1_5628: la $2, sym_1_5628
+.globl sym_1_5629
+sym_1_5629: la $2, sym_1_5629
+.globl sym_1_5630
+sym_1_5630: la $2, sym_1_5630
+.globl sym_1_5631
+sym_1_5631: la $2, sym_1_5631
+.globl sym_1_5632
+sym_1_5632: la $2, sym_1_5632
+.globl sym_1_5633
+sym_1_5633: la $2, sym_1_5633
+.globl sym_1_5634
+sym_1_5634: la $2, sym_1_5634
+.globl sym_1_5635
+sym_1_5635: la $2, sym_1_5635
+.globl sym_1_5636
+sym_1_5636: la $2, sym_1_5636
+.globl sym_1_5637
+sym_1_5637: la $2, sym_1_5637
+.globl sym_1_5638
+sym_1_5638: la $2, sym_1_5638
+.globl sym_1_5639
+sym_1_5639: la $2, sym_1_5639
+.globl sym_1_5640
+sym_1_5640: la $2, sym_1_5640
+.globl sym_1_5641
+sym_1_5641: la $2, sym_1_5641
+.globl sym_1_5642
+sym_1_5642: la $2, sym_1_5642
+.globl sym_1_5643
+sym_1_5643: la $2, sym_1_5643
+.globl sym_1_5644
+sym_1_5644: la $2, sym_1_5644
+.globl sym_1_5645
+sym_1_5645: la $2, sym_1_5645
+.globl sym_1_5646
+sym_1_5646: la $2, sym_1_5646
+.globl sym_1_5647
+sym_1_5647: la $2, sym_1_5647
+.globl sym_1_5648
+sym_1_5648: la $2, sym_1_5648
+.globl sym_1_5649
+sym_1_5649: la $2, sym_1_5649
+.globl sym_1_5650
+sym_1_5650: la $2, sym_1_5650
+.globl sym_1_5651
+sym_1_5651: la $2, sym_1_5651
+.globl sym_1_5652
+sym_1_5652: la $2, sym_1_5652
+.globl sym_1_5653
+sym_1_5653: la $2, sym_1_5653
+.globl sym_1_5654
+sym_1_5654: la $2, sym_1_5654
+.globl sym_1_5655
+sym_1_5655: la $2, sym_1_5655
+.globl sym_1_5656
+sym_1_5656: la $2, sym_1_5656
+.globl sym_1_5657
+sym_1_5657: la $2, sym_1_5657
+.globl sym_1_5658
+sym_1_5658: la $2, sym_1_5658
+.globl sym_1_5659
+sym_1_5659: la $2, sym_1_5659
+.globl sym_1_5660
+sym_1_5660: la $2, sym_1_5660
+.globl sym_1_5661
+sym_1_5661: la $2, sym_1_5661
+.globl sym_1_5662
+sym_1_5662: la $2, sym_1_5662
+.globl sym_1_5663
+sym_1_5663: la $2, sym_1_5663
+.globl sym_1_5664
+sym_1_5664: la $2, sym_1_5664
+.globl sym_1_5665
+sym_1_5665: la $2, sym_1_5665
+.globl sym_1_5666
+sym_1_5666: la $2, sym_1_5666
+.globl sym_1_5667
+sym_1_5667: la $2, sym_1_5667
+.globl sym_1_5668
+sym_1_5668: la $2, sym_1_5668
+.globl sym_1_5669
+sym_1_5669: la $2, sym_1_5669
+.globl sym_1_5670
+sym_1_5670: la $2, sym_1_5670
+.globl sym_1_5671
+sym_1_5671: la $2, sym_1_5671
+.globl sym_1_5672
+sym_1_5672: la $2, sym_1_5672
+.globl sym_1_5673
+sym_1_5673: la $2, sym_1_5673
+.globl sym_1_5674
+sym_1_5674: la $2, sym_1_5674
+.globl sym_1_5675
+sym_1_5675: la $2, sym_1_5675
+.globl sym_1_5676
+sym_1_5676: la $2, sym_1_5676
+.globl sym_1_5677
+sym_1_5677: la $2, sym_1_5677
+.globl sym_1_5678
+sym_1_5678: la $2, sym_1_5678
+.globl sym_1_5679
+sym_1_5679: la $2, sym_1_5679
+.globl sym_1_5680
+sym_1_5680: la $2, sym_1_5680
+.globl sym_1_5681
+sym_1_5681: la $2, sym_1_5681
+.globl sym_1_5682
+sym_1_5682: la $2, sym_1_5682
+.globl sym_1_5683
+sym_1_5683: la $2, sym_1_5683
+.globl sym_1_5684
+sym_1_5684: la $2, sym_1_5684
+.globl sym_1_5685
+sym_1_5685: la $2, sym_1_5685
+.globl sym_1_5686
+sym_1_5686: la $2, sym_1_5686
+.globl sym_1_5687
+sym_1_5687: la $2, sym_1_5687
+.globl sym_1_5688
+sym_1_5688: la $2, sym_1_5688
+.globl sym_1_5689
+sym_1_5689: la $2, sym_1_5689
+.globl sym_1_5690
+sym_1_5690: la $2, sym_1_5690
+.globl sym_1_5691
+sym_1_5691: la $2, sym_1_5691
+.globl sym_1_5692
+sym_1_5692: la $2, sym_1_5692
+.globl sym_1_5693
+sym_1_5693: la $2, sym_1_5693
+.globl sym_1_5694
+sym_1_5694: la $2, sym_1_5694
+.globl sym_1_5695
+sym_1_5695: la $2, sym_1_5695
+.globl sym_1_5696
+sym_1_5696: la $2, sym_1_5696
+.globl sym_1_5697
+sym_1_5697: la $2, sym_1_5697
+.globl sym_1_5698
+sym_1_5698: la $2, sym_1_5698
+.globl sym_1_5699
+sym_1_5699: la $2, sym_1_5699
+.globl sym_1_5700
+sym_1_5700: la $2, sym_1_5700
+.globl sym_1_5701
+sym_1_5701: la $2, sym_1_5701
+.globl sym_1_5702
+sym_1_5702: la $2, sym_1_5702
+.globl sym_1_5703
+sym_1_5703: la $2, sym_1_5703
+.globl sym_1_5704
+sym_1_5704: la $2, sym_1_5704
+.globl sym_1_5705
+sym_1_5705: la $2, sym_1_5705
+.globl sym_1_5706
+sym_1_5706: la $2, sym_1_5706
+.globl sym_1_5707
+sym_1_5707: la $2, sym_1_5707
+.globl sym_1_5708
+sym_1_5708: la $2, sym_1_5708
+.globl sym_1_5709
+sym_1_5709: la $2, sym_1_5709
+.globl sym_1_5710
+sym_1_5710: la $2, sym_1_5710
+.globl sym_1_5711
+sym_1_5711: la $2, sym_1_5711
+.globl sym_1_5712
+sym_1_5712: la $2, sym_1_5712
+.globl sym_1_5713
+sym_1_5713: la $2, sym_1_5713
+.globl sym_1_5714
+sym_1_5714: la $2, sym_1_5714
+.globl sym_1_5715
+sym_1_5715: la $2, sym_1_5715
+.globl sym_1_5716
+sym_1_5716: la $2, sym_1_5716
+.globl sym_1_5717
+sym_1_5717: la $2, sym_1_5717
+.globl sym_1_5718
+sym_1_5718: la $2, sym_1_5718
+.globl sym_1_5719
+sym_1_5719: la $2, sym_1_5719
+.globl sym_1_5720
+sym_1_5720: la $2, sym_1_5720
+.globl sym_1_5721
+sym_1_5721: la $2, sym_1_5721
+.globl sym_1_5722
+sym_1_5722: la $2, sym_1_5722
+.globl sym_1_5723
+sym_1_5723: la $2, sym_1_5723
+.globl sym_1_5724
+sym_1_5724: la $2, sym_1_5724
+.globl sym_1_5725
+sym_1_5725: la $2, sym_1_5725
+.globl sym_1_5726
+sym_1_5726: la $2, sym_1_5726
+.globl sym_1_5727
+sym_1_5727: la $2, sym_1_5727
+.globl sym_1_5728
+sym_1_5728: la $2, sym_1_5728
+.globl sym_1_5729
+sym_1_5729: la $2, sym_1_5729
+.globl sym_1_5730
+sym_1_5730: la $2, sym_1_5730
+.globl sym_1_5731
+sym_1_5731: la $2, sym_1_5731
+.globl sym_1_5732
+sym_1_5732: la $2, sym_1_5732
+.globl sym_1_5733
+sym_1_5733: la $2, sym_1_5733
+.globl sym_1_5734
+sym_1_5734: la $2, sym_1_5734
+.globl sym_1_5735
+sym_1_5735: la $2, sym_1_5735
+.globl sym_1_5736
+sym_1_5736: la $2, sym_1_5736
+.globl sym_1_5737
+sym_1_5737: la $2, sym_1_5737
+.globl sym_1_5738
+sym_1_5738: la $2, sym_1_5738
+.globl sym_1_5739
+sym_1_5739: la $2, sym_1_5739
+.globl sym_1_5740
+sym_1_5740: la $2, sym_1_5740
+.globl sym_1_5741
+sym_1_5741: la $2, sym_1_5741
+.globl sym_1_5742
+sym_1_5742: la $2, sym_1_5742
+.globl sym_1_5743
+sym_1_5743: la $2, sym_1_5743
+.globl sym_1_5744
+sym_1_5744: la $2, sym_1_5744
+.globl sym_1_5745
+sym_1_5745: la $2, sym_1_5745
+.globl sym_1_5746
+sym_1_5746: la $2, sym_1_5746
+.globl sym_1_5747
+sym_1_5747: la $2, sym_1_5747
+.globl sym_1_5748
+sym_1_5748: la $2, sym_1_5748
+.globl sym_1_5749
+sym_1_5749: la $2, sym_1_5749
+.globl sym_1_5750
+sym_1_5750: la $2, sym_1_5750
+.globl sym_1_5751
+sym_1_5751: la $2, sym_1_5751
+.globl sym_1_5752
+sym_1_5752: la $2, sym_1_5752
+.globl sym_1_5753
+sym_1_5753: la $2, sym_1_5753
+.globl sym_1_5754
+sym_1_5754: la $2, sym_1_5754
+.globl sym_1_5755
+sym_1_5755: la $2, sym_1_5755
+.globl sym_1_5756
+sym_1_5756: la $2, sym_1_5756
+.globl sym_1_5757
+sym_1_5757: la $2, sym_1_5757
+.globl sym_1_5758
+sym_1_5758: la $2, sym_1_5758
+.globl sym_1_5759
+sym_1_5759: la $2, sym_1_5759
+.globl sym_1_5760
+sym_1_5760: la $2, sym_1_5760
+.globl sym_1_5761
+sym_1_5761: la $2, sym_1_5761
+.globl sym_1_5762
+sym_1_5762: la $2, sym_1_5762
+.globl sym_1_5763
+sym_1_5763: la $2, sym_1_5763
+.globl sym_1_5764
+sym_1_5764: la $2, sym_1_5764
+.globl sym_1_5765
+sym_1_5765: la $2, sym_1_5765
+.globl sym_1_5766
+sym_1_5766: la $2, sym_1_5766
+.globl sym_1_5767
+sym_1_5767: la $2, sym_1_5767
+.globl sym_1_5768
+sym_1_5768: la $2, sym_1_5768
+.globl sym_1_5769
+sym_1_5769: la $2, sym_1_5769
+.globl sym_1_5770
+sym_1_5770: la $2, sym_1_5770
+.globl sym_1_5771
+sym_1_5771: la $2, sym_1_5771
+.globl sym_1_5772
+sym_1_5772: la $2, sym_1_5772
+.globl sym_1_5773
+sym_1_5773: la $2, sym_1_5773
+.globl sym_1_5774
+sym_1_5774: la $2, sym_1_5774
+.globl sym_1_5775
+sym_1_5775: la $2, sym_1_5775
+.globl sym_1_5776
+sym_1_5776: la $2, sym_1_5776
+.globl sym_1_5777
+sym_1_5777: la $2, sym_1_5777
+.globl sym_1_5778
+sym_1_5778: la $2, sym_1_5778
+.globl sym_1_5779
+sym_1_5779: la $2, sym_1_5779
+.globl sym_1_5780
+sym_1_5780: la $2, sym_1_5780
+.globl sym_1_5781
+sym_1_5781: la $2, sym_1_5781
+.globl sym_1_5782
+sym_1_5782: la $2, sym_1_5782
+.globl sym_1_5783
+sym_1_5783: la $2, sym_1_5783
+.globl sym_1_5784
+sym_1_5784: la $2, sym_1_5784
+.globl sym_1_5785
+sym_1_5785: la $2, sym_1_5785
+.globl sym_1_5786
+sym_1_5786: la $2, sym_1_5786
+.globl sym_1_5787
+sym_1_5787: la $2, sym_1_5787
+.globl sym_1_5788
+sym_1_5788: la $2, sym_1_5788
+.globl sym_1_5789
+sym_1_5789: la $2, sym_1_5789
+.globl sym_1_5790
+sym_1_5790: la $2, sym_1_5790
+.globl sym_1_5791
+sym_1_5791: la $2, sym_1_5791
+.globl sym_1_5792
+sym_1_5792: la $2, sym_1_5792
+.globl sym_1_5793
+sym_1_5793: la $2, sym_1_5793
+.globl sym_1_5794
+sym_1_5794: la $2, sym_1_5794
+.globl sym_1_5795
+sym_1_5795: la $2, sym_1_5795
+.globl sym_1_5796
+sym_1_5796: la $2, sym_1_5796
+.globl sym_1_5797
+sym_1_5797: la $2, sym_1_5797
+.globl sym_1_5798
+sym_1_5798: la $2, sym_1_5798
+.globl sym_1_5799
+sym_1_5799: la $2, sym_1_5799
+.globl sym_1_5800
+sym_1_5800: la $2, sym_1_5800
+.globl sym_1_5801
+sym_1_5801: la $2, sym_1_5801
+.globl sym_1_5802
+sym_1_5802: la $2, sym_1_5802
+.globl sym_1_5803
+sym_1_5803: la $2, sym_1_5803
+.globl sym_1_5804
+sym_1_5804: la $2, sym_1_5804
+.globl sym_1_5805
+sym_1_5805: la $2, sym_1_5805
+.globl sym_1_5806
+sym_1_5806: la $2, sym_1_5806
+.globl sym_1_5807
+sym_1_5807: la $2, sym_1_5807
+.globl sym_1_5808
+sym_1_5808: la $2, sym_1_5808
+.globl sym_1_5809
+sym_1_5809: la $2, sym_1_5809
+.globl sym_1_5810
+sym_1_5810: la $2, sym_1_5810
+.globl sym_1_5811
+sym_1_5811: la $2, sym_1_5811
+.globl sym_1_5812
+sym_1_5812: la $2, sym_1_5812
+.globl sym_1_5813
+sym_1_5813: la $2, sym_1_5813
+.globl sym_1_5814
+sym_1_5814: la $2, sym_1_5814
+.globl sym_1_5815
+sym_1_5815: la $2, sym_1_5815
+.globl sym_1_5816
+sym_1_5816: la $2, sym_1_5816
+.globl sym_1_5817
+sym_1_5817: la $2, sym_1_5817
+.globl sym_1_5818
+sym_1_5818: la $2, sym_1_5818
+.globl sym_1_5819
+sym_1_5819: la $2, sym_1_5819
+.globl sym_1_5820
+sym_1_5820: la $2, sym_1_5820
+.globl sym_1_5821
+sym_1_5821: la $2, sym_1_5821
+.globl sym_1_5822
+sym_1_5822: la $2, sym_1_5822
+.globl sym_1_5823
+sym_1_5823: la $2, sym_1_5823
+.globl sym_1_5824
+sym_1_5824: la $2, sym_1_5824
+.globl sym_1_5825
+sym_1_5825: la $2, sym_1_5825
+.globl sym_1_5826
+sym_1_5826: la $2, sym_1_5826
+.globl sym_1_5827
+sym_1_5827: la $2, sym_1_5827
+.globl sym_1_5828
+sym_1_5828: la $2, sym_1_5828
+.globl sym_1_5829
+sym_1_5829: la $2, sym_1_5829
+.globl sym_1_5830
+sym_1_5830: la $2, sym_1_5830
+.globl sym_1_5831
+sym_1_5831: la $2, sym_1_5831
+.globl sym_1_5832
+sym_1_5832: la $2, sym_1_5832
+.globl sym_1_5833
+sym_1_5833: la $2, sym_1_5833
+.globl sym_1_5834
+sym_1_5834: la $2, sym_1_5834
+.globl sym_1_5835
+sym_1_5835: la $2, sym_1_5835
+.globl sym_1_5836
+sym_1_5836: la $2, sym_1_5836
+.globl sym_1_5837
+sym_1_5837: la $2, sym_1_5837
+.globl sym_1_5838
+sym_1_5838: la $2, sym_1_5838
+.globl sym_1_5839
+sym_1_5839: la $2, sym_1_5839
+.globl sym_1_5840
+sym_1_5840: la $2, sym_1_5840
+.globl sym_1_5841
+sym_1_5841: la $2, sym_1_5841
+.globl sym_1_5842
+sym_1_5842: la $2, sym_1_5842
+.globl sym_1_5843
+sym_1_5843: la $2, sym_1_5843
+.globl sym_1_5844
+sym_1_5844: la $2, sym_1_5844
+.globl sym_1_5845
+sym_1_5845: la $2, sym_1_5845
+.globl sym_1_5846
+sym_1_5846: la $2, sym_1_5846
+.globl sym_1_5847
+sym_1_5847: la $2, sym_1_5847
+.globl sym_1_5848
+sym_1_5848: la $2, sym_1_5848
+.globl sym_1_5849
+sym_1_5849: la $2, sym_1_5849
+.globl sym_1_5850
+sym_1_5850: la $2, sym_1_5850
+.globl sym_1_5851
+sym_1_5851: la $2, sym_1_5851
+.globl sym_1_5852
+sym_1_5852: la $2, sym_1_5852
+.globl sym_1_5853
+sym_1_5853: la $2, sym_1_5853
+.globl sym_1_5854
+sym_1_5854: la $2, sym_1_5854
+.globl sym_1_5855
+sym_1_5855: la $2, sym_1_5855
+.globl sym_1_5856
+sym_1_5856: la $2, sym_1_5856
+.globl sym_1_5857
+sym_1_5857: la $2, sym_1_5857
+.globl sym_1_5858
+sym_1_5858: la $2, sym_1_5858
+.globl sym_1_5859
+sym_1_5859: la $2, sym_1_5859
+.globl sym_1_5860
+sym_1_5860: la $2, sym_1_5860
+.globl sym_1_5861
+sym_1_5861: la $2, sym_1_5861
+.globl sym_1_5862
+sym_1_5862: la $2, sym_1_5862
+.globl sym_1_5863
+sym_1_5863: la $2, sym_1_5863
+.globl sym_1_5864
+sym_1_5864: la $2, sym_1_5864
+.globl sym_1_5865
+sym_1_5865: la $2, sym_1_5865
+.globl sym_1_5866
+sym_1_5866: la $2, sym_1_5866
+.globl sym_1_5867
+sym_1_5867: la $2, sym_1_5867
+.globl sym_1_5868
+sym_1_5868: la $2, sym_1_5868
+.globl sym_1_5869
+sym_1_5869: la $2, sym_1_5869
+.globl sym_1_5870
+sym_1_5870: la $2, sym_1_5870
+.globl sym_1_5871
+sym_1_5871: la $2, sym_1_5871
+.globl sym_1_5872
+sym_1_5872: la $2, sym_1_5872
+.globl sym_1_5873
+sym_1_5873: la $2, sym_1_5873
+.globl sym_1_5874
+sym_1_5874: la $2, sym_1_5874
+.globl sym_1_5875
+sym_1_5875: la $2, sym_1_5875
+.globl sym_1_5876
+sym_1_5876: la $2, sym_1_5876
+.globl sym_1_5877
+sym_1_5877: la $2, sym_1_5877
+.globl sym_1_5878
+sym_1_5878: la $2, sym_1_5878
+.globl sym_1_5879
+sym_1_5879: la $2, sym_1_5879
+.globl sym_1_5880
+sym_1_5880: la $2, sym_1_5880
+.globl sym_1_5881
+sym_1_5881: la $2, sym_1_5881
+.globl sym_1_5882
+sym_1_5882: la $2, sym_1_5882
+.globl sym_1_5883
+sym_1_5883: la $2, sym_1_5883
+.globl sym_1_5884
+sym_1_5884: la $2, sym_1_5884
+.globl sym_1_5885
+sym_1_5885: la $2, sym_1_5885
+.globl sym_1_5886
+sym_1_5886: la $2, sym_1_5886
+.globl sym_1_5887
+sym_1_5887: la $2, sym_1_5887
+.globl sym_1_5888
+sym_1_5888: la $2, sym_1_5888
+.globl sym_1_5889
+sym_1_5889: la $2, sym_1_5889
+.globl sym_1_5890
+sym_1_5890: la $2, sym_1_5890
+.globl sym_1_5891
+sym_1_5891: la $2, sym_1_5891
+.globl sym_1_5892
+sym_1_5892: la $2, sym_1_5892
+.globl sym_1_5893
+sym_1_5893: la $2, sym_1_5893
+.globl sym_1_5894
+sym_1_5894: la $2, sym_1_5894
+.globl sym_1_5895
+sym_1_5895: la $2, sym_1_5895
+.globl sym_1_5896
+sym_1_5896: la $2, sym_1_5896
+.globl sym_1_5897
+sym_1_5897: la $2, sym_1_5897
+.globl sym_1_5898
+sym_1_5898: la $2, sym_1_5898
+.globl sym_1_5899
+sym_1_5899: la $2, sym_1_5899
+.globl sym_1_5900
+sym_1_5900: la $2, sym_1_5900
+.globl sym_1_5901
+sym_1_5901: la $2, sym_1_5901
+.globl sym_1_5902
+sym_1_5902: la $2, sym_1_5902
+.globl sym_1_5903
+sym_1_5903: la $2, sym_1_5903
+.globl sym_1_5904
+sym_1_5904: la $2, sym_1_5904
+.globl sym_1_5905
+sym_1_5905: la $2, sym_1_5905
+.globl sym_1_5906
+sym_1_5906: la $2, sym_1_5906
+.globl sym_1_5907
+sym_1_5907: la $2, sym_1_5907
+.globl sym_1_5908
+sym_1_5908: la $2, sym_1_5908
+.globl sym_1_5909
+sym_1_5909: la $2, sym_1_5909
+.globl sym_1_5910
+sym_1_5910: la $2, sym_1_5910
+.globl sym_1_5911
+sym_1_5911: la $2, sym_1_5911
+.globl sym_1_5912
+sym_1_5912: la $2, sym_1_5912
+.globl sym_1_5913
+sym_1_5913: la $2, sym_1_5913
+.globl sym_1_5914
+sym_1_5914: la $2, sym_1_5914
+.globl sym_1_5915
+sym_1_5915: la $2, sym_1_5915
+.globl sym_1_5916
+sym_1_5916: la $2, sym_1_5916
+.globl sym_1_5917
+sym_1_5917: la $2, sym_1_5917
+.globl sym_1_5918
+sym_1_5918: la $2, sym_1_5918
+.globl sym_1_5919
+sym_1_5919: la $2, sym_1_5919
+.globl sym_1_5920
+sym_1_5920: la $2, sym_1_5920
+.globl sym_1_5921
+sym_1_5921: la $2, sym_1_5921
+.globl sym_1_5922
+sym_1_5922: la $2, sym_1_5922
+.globl sym_1_5923
+sym_1_5923: la $2, sym_1_5923
+.globl sym_1_5924
+sym_1_5924: la $2, sym_1_5924
+.globl sym_1_5925
+sym_1_5925: la $2, sym_1_5925
+.globl sym_1_5926
+sym_1_5926: la $2, sym_1_5926
+.globl sym_1_5927
+sym_1_5927: la $2, sym_1_5927
+.globl sym_1_5928
+sym_1_5928: la $2, sym_1_5928
+.globl sym_1_5929
+sym_1_5929: la $2, sym_1_5929
+.globl sym_1_5930
+sym_1_5930: la $2, sym_1_5930
+.globl sym_1_5931
+sym_1_5931: la $2, sym_1_5931
+.globl sym_1_5932
+sym_1_5932: la $2, sym_1_5932
+.globl sym_1_5933
+sym_1_5933: la $2, sym_1_5933
+.globl sym_1_5934
+sym_1_5934: la $2, sym_1_5934
+.globl sym_1_5935
+sym_1_5935: la $2, sym_1_5935
+.globl sym_1_5936
+sym_1_5936: la $2, sym_1_5936
+.globl sym_1_5937
+sym_1_5937: la $2, sym_1_5937
+.globl sym_1_5938
+sym_1_5938: la $2, sym_1_5938
+.globl sym_1_5939
+sym_1_5939: la $2, sym_1_5939
+.globl sym_1_5940
+sym_1_5940: la $2, sym_1_5940
+.globl sym_1_5941
+sym_1_5941: la $2, sym_1_5941
+.globl sym_1_5942
+sym_1_5942: la $2, sym_1_5942
+.globl sym_1_5943
+sym_1_5943: la $2, sym_1_5943
+.globl sym_1_5944
+sym_1_5944: la $2, sym_1_5944
+.globl sym_1_5945
+sym_1_5945: la $2, sym_1_5945
+.globl sym_1_5946
+sym_1_5946: la $2, sym_1_5946
+.globl sym_1_5947
+sym_1_5947: la $2, sym_1_5947
+.globl sym_1_5948
+sym_1_5948: la $2, sym_1_5948
+.globl sym_1_5949
+sym_1_5949: la $2, sym_1_5949
+.globl sym_1_5950
+sym_1_5950: la $2, sym_1_5950
+.globl sym_1_5951
+sym_1_5951: la $2, sym_1_5951
+.globl sym_1_5952
+sym_1_5952: la $2, sym_1_5952
+.globl sym_1_5953
+sym_1_5953: la $2, sym_1_5953
+.globl sym_1_5954
+sym_1_5954: la $2, sym_1_5954
+.globl sym_1_5955
+sym_1_5955: la $2, sym_1_5955
+.globl sym_1_5956
+sym_1_5956: la $2, sym_1_5956
+.globl sym_1_5957
+sym_1_5957: la $2, sym_1_5957
+.globl sym_1_5958
+sym_1_5958: la $2, sym_1_5958
+.globl sym_1_5959
+sym_1_5959: la $2, sym_1_5959
+.globl sym_1_5960
+sym_1_5960: la $2, sym_1_5960
+.globl sym_1_5961
+sym_1_5961: la $2, sym_1_5961
+.globl sym_1_5962
+sym_1_5962: la $2, sym_1_5962
+.globl sym_1_5963
+sym_1_5963: la $2, sym_1_5963
+.globl sym_1_5964
+sym_1_5964: la $2, sym_1_5964
+.globl sym_1_5965
+sym_1_5965: la $2, sym_1_5965
+.globl sym_1_5966
+sym_1_5966: la $2, sym_1_5966
+.globl sym_1_5967
+sym_1_5967: la $2, sym_1_5967
+.globl sym_1_5968
+sym_1_5968: la $2, sym_1_5968
+.globl sym_1_5969
+sym_1_5969: la $2, sym_1_5969
+.globl sym_1_5970
+sym_1_5970: la $2, sym_1_5970
+.globl sym_1_5971
+sym_1_5971: la $2, sym_1_5971
+.globl sym_1_5972
+sym_1_5972: la $2, sym_1_5972
+.globl sym_1_5973
+sym_1_5973: la $2, sym_1_5973
+.globl sym_1_5974
+sym_1_5974: la $2, sym_1_5974
+.globl sym_1_5975
+sym_1_5975: la $2, sym_1_5975
+.globl sym_1_5976
+sym_1_5976: la $2, sym_1_5976
+.globl sym_1_5977
+sym_1_5977: la $2, sym_1_5977
+.globl sym_1_5978
+sym_1_5978: la $2, sym_1_5978
+.globl sym_1_5979
+sym_1_5979: la $2, sym_1_5979
+.globl sym_1_5980
+sym_1_5980: la $2, sym_1_5980
+.globl sym_1_5981
+sym_1_5981: la $2, sym_1_5981
+.globl sym_1_5982
+sym_1_5982: la $2, sym_1_5982
+.globl sym_1_5983
+sym_1_5983: la $2, sym_1_5983
+.globl sym_1_5984
+sym_1_5984: la $2, sym_1_5984
+.globl sym_1_5985
+sym_1_5985: la $2, sym_1_5985
+.globl sym_1_5986
+sym_1_5986: la $2, sym_1_5986
+.globl sym_1_5987
+sym_1_5987: la $2, sym_1_5987
+.globl sym_1_5988
+sym_1_5988: la $2, sym_1_5988
+.globl sym_1_5989
+sym_1_5989: la $2, sym_1_5989
+.globl sym_1_5990
+sym_1_5990: la $2, sym_1_5990
+.globl sym_1_5991
+sym_1_5991: la $2, sym_1_5991
+.globl sym_1_5992
+sym_1_5992: la $2, sym_1_5992
+.globl sym_1_5993
+sym_1_5993: la $2, sym_1_5993
+.globl sym_1_5994
+sym_1_5994: la $2, sym_1_5994
+.globl sym_1_5995
+sym_1_5995: la $2, sym_1_5995
+.globl sym_1_5996
+sym_1_5996: la $2, sym_1_5996
+.globl sym_1_5997
+sym_1_5997: la $2, sym_1_5997
+.globl sym_1_5998
+sym_1_5998: la $2, sym_1_5998
+.globl sym_1_5999
+sym_1_5999: la $2, sym_1_5999
+.globl sym_1_6000
+sym_1_6000: la $2, sym_1_6000
+.globl sym_1_6001
+sym_1_6001: la $2, sym_1_6001
+.globl sym_1_6002
+sym_1_6002: la $2, sym_1_6002
+.globl sym_1_6003
+sym_1_6003: la $2, sym_1_6003
+.globl sym_1_6004
+sym_1_6004: la $2, sym_1_6004
+.globl sym_1_6005
+sym_1_6005: la $2, sym_1_6005
+.globl sym_1_6006
+sym_1_6006: la $2, sym_1_6006
+.globl sym_1_6007
+sym_1_6007: la $2, sym_1_6007
+.globl sym_1_6008
+sym_1_6008: la $2, sym_1_6008
+.globl sym_1_6009
+sym_1_6009: la $2, sym_1_6009
+.globl sym_1_6010
+sym_1_6010: la $2, sym_1_6010
+.globl sym_1_6011
+sym_1_6011: la $2, sym_1_6011
+.globl sym_1_6012
+sym_1_6012: la $2, sym_1_6012
+.globl sym_1_6013
+sym_1_6013: la $2, sym_1_6013
+.globl sym_1_6014
+sym_1_6014: la $2, sym_1_6014
+.globl sym_1_6015
+sym_1_6015: la $2, sym_1_6015
+.globl sym_1_6016
+sym_1_6016: la $2, sym_1_6016
+.globl sym_1_6017
+sym_1_6017: la $2, sym_1_6017
+.globl sym_1_6018
+sym_1_6018: la $2, sym_1_6018
+.globl sym_1_6019
+sym_1_6019: la $2, sym_1_6019
+.globl sym_1_6020
+sym_1_6020: la $2, sym_1_6020
+.globl sym_1_6021
+sym_1_6021: la $2, sym_1_6021
+.globl sym_1_6022
+sym_1_6022: la $2, sym_1_6022
+.globl sym_1_6023
+sym_1_6023: la $2, sym_1_6023
+.globl sym_1_6024
+sym_1_6024: la $2, sym_1_6024
+.globl sym_1_6025
+sym_1_6025: la $2, sym_1_6025
+.globl sym_1_6026
+sym_1_6026: la $2, sym_1_6026
+.globl sym_1_6027
+sym_1_6027: la $2, sym_1_6027
+.globl sym_1_6028
+sym_1_6028: la $2, sym_1_6028
+.globl sym_1_6029
+sym_1_6029: la $2, sym_1_6029
+.globl sym_1_6030
+sym_1_6030: la $2, sym_1_6030
+.globl sym_1_6031
+sym_1_6031: la $2, sym_1_6031
+.globl sym_1_6032
+sym_1_6032: la $2, sym_1_6032
+.globl sym_1_6033
+sym_1_6033: la $2, sym_1_6033
+.globl sym_1_6034
+sym_1_6034: la $2, sym_1_6034
+.globl sym_1_6035
+sym_1_6035: la $2, sym_1_6035
+.globl sym_1_6036
+sym_1_6036: la $2, sym_1_6036
+.globl sym_1_6037
+sym_1_6037: la $2, sym_1_6037
+.globl sym_1_6038
+sym_1_6038: la $2, sym_1_6038
+.globl sym_1_6039
+sym_1_6039: la $2, sym_1_6039
+.globl sym_1_6040
+sym_1_6040: la $2, sym_1_6040
+.globl sym_1_6041
+sym_1_6041: la $2, sym_1_6041
+.globl sym_1_6042
+sym_1_6042: la $2, sym_1_6042
+.globl sym_1_6043
+sym_1_6043: la $2, sym_1_6043
+.globl sym_1_6044
+sym_1_6044: la $2, sym_1_6044
+.globl sym_1_6045
+sym_1_6045: la $2, sym_1_6045
+.globl sym_1_6046
+sym_1_6046: la $2, sym_1_6046
+.globl sym_1_6047
+sym_1_6047: la $2, sym_1_6047
+.globl sym_1_6048
+sym_1_6048: la $2, sym_1_6048
+.globl sym_1_6049
+sym_1_6049: la $2, sym_1_6049
+.globl sym_1_6050
+sym_1_6050: la $2, sym_1_6050
+.globl sym_1_6051
+sym_1_6051: la $2, sym_1_6051
+.globl sym_1_6052
+sym_1_6052: la $2, sym_1_6052
+.globl sym_1_6053
+sym_1_6053: la $2, sym_1_6053
+.globl sym_1_6054
+sym_1_6054: la $2, sym_1_6054
+.globl sym_1_6055
+sym_1_6055: la $2, sym_1_6055
+.globl sym_1_6056
+sym_1_6056: la $2, sym_1_6056
+.globl sym_1_6057
+sym_1_6057: la $2, sym_1_6057
+.globl sym_1_6058
+sym_1_6058: la $2, sym_1_6058
+.globl sym_1_6059
+sym_1_6059: la $2, sym_1_6059
+.globl sym_1_6060
+sym_1_6060: la $2, sym_1_6060
+.globl sym_1_6061
+sym_1_6061: la $2, sym_1_6061
+.globl sym_1_6062
+sym_1_6062: la $2, sym_1_6062
+.globl sym_1_6063
+sym_1_6063: la $2, sym_1_6063
+.globl sym_1_6064
+sym_1_6064: la $2, sym_1_6064
+.globl sym_1_6065
+sym_1_6065: la $2, sym_1_6065
+.globl sym_1_6066
+sym_1_6066: la $2, sym_1_6066
+.globl sym_1_6067
+sym_1_6067: la $2, sym_1_6067
+.globl sym_1_6068
+sym_1_6068: la $2, sym_1_6068
+.globl sym_1_6069
+sym_1_6069: la $2, sym_1_6069
+.globl sym_1_6070
+sym_1_6070: la $2, sym_1_6070
+.globl sym_1_6071
+sym_1_6071: la $2, sym_1_6071
+.globl sym_1_6072
+sym_1_6072: la $2, sym_1_6072
+.globl sym_1_6073
+sym_1_6073: la $2, sym_1_6073
+.globl sym_1_6074
+sym_1_6074: la $2, sym_1_6074
+.globl sym_1_6075
+sym_1_6075: la $2, sym_1_6075
+.globl sym_1_6076
+sym_1_6076: la $2, sym_1_6076
+.globl sym_1_6077
+sym_1_6077: la $2, sym_1_6077
+.globl sym_1_6078
+sym_1_6078: la $2, sym_1_6078
+.globl sym_1_6079
+sym_1_6079: la $2, sym_1_6079
+.globl sym_1_6080
+sym_1_6080: la $2, sym_1_6080
+.globl sym_1_6081
+sym_1_6081: la $2, sym_1_6081
+.globl sym_1_6082
+sym_1_6082: la $2, sym_1_6082
+.globl sym_1_6083
+sym_1_6083: la $2, sym_1_6083
+.globl sym_1_6084
+sym_1_6084: la $2, sym_1_6084
+.globl sym_1_6085
+sym_1_6085: la $2, sym_1_6085
+.globl sym_1_6086
+sym_1_6086: la $2, sym_1_6086
+.globl sym_1_6087
+sym_1_6087: la $2, sym_1_6087
+.globl sym_1_6088
+sym_1_6088: la $2, sym_1_6088
+.globl sym_1_6089
+sym_1_6089: la $2, sym_1_6089
+.globl sym_1_6090
+sym_1_6090: la $2, sym_1_6090
+.globl sym_1_6091
+sym_1_6091: la $2, sym_1_6091
+.globl sym_1_6092
+sym_1_6092: la $2, sym_1_6092
+.globl sym_1_6093
+sym_1_6093: la $2, sym_1_6093
+.globl sym_1_6094
+sym_1_6094: la $2, sym_1_6094
+.globl sym_1_6095
+sym_1_6095: la $2, sym_1_6095
+.globl sym_1_6096
+sym_1_6096: la $2, sym_1_6096
+.globl sym_1_6097
+sym_1_6097: la $2, sym_1_6097
+.globl sym_1_6098
+sym_1_6098: la $2, sym_1_6098
+.globl sym_1_6099
+sym_1_6099: la $2, sym_1_6099
+.globl sym_1_6100
+sym_1_6100: la $2, sym_1_6100
+.globl sym_1_6101
+sym_1_6101: la $2, sym_1_6101
+.globl sym_1_6102
+sym_1_6102: la $2, sym_1_6102
+.globl sym_1_6103
+sym_1_6103: la $2, sym_1_6103
+.globl sym_1_6104
+sym_1_6104: la $2, sym_1_6104
+.globl sym_1_6105
+sym_1_6105: la $2, sym_1_6105
+.globl sym_1_6106
+sym_1_6106: la $2, sym_1_6106
+.globl sym_1_6107
+sym_1_6107: la $2, sym_1_6107
+.globl sym_1_6108
+sym_1_6108: la $2, sym_1_6108
+.globl sym_1_6109
+sym_1_6109: la $2, sym_1_6109
+.globl sym_1_6110
+sym_1_6110: la $2, sym_1_6110
+.globl sym_1_6111
+sym_1_6111: la $2, sym_1_6111
+.globl sym_1_6112
+sym_1_6112: la $2, sym_1_6112
+.globl sym_1_6113
+sym_1_6113: la $2, sym_1_6113
+.globl sym_1_6114
+sym_1_6114: la $2, sym_1_6114
+.globl sym_1_6115
+sym_1_6115: la $2, sym_1_6115
+.globl sym_1_6116
+sym_1_6116: la $2, sym_1_6116
+.globl sym_1_6117
+sym_1_6117: la $2, sym_1_6117
+.globl sym_1_6118
+sym_1_6118: la $2, sym_1_6118
+.globl sym_1_6119
+sym_1_6119: la $2, sym_1_6119
+.globl sym_1_6120
+sym_1_6120: la $2, sym_1_6120
+.globl sym_1_6121
+sym_1_6121: la $2, sym_1_6121
+.globl sym_1_6122
+sym_1_6122: la $2, sym_1_6122
+.globl sym_1_6123
+sym_1_6123: la $2, sym_1_6123
+.globl sym_1_6124
+sym_1_6124: la $2, sym_1_6124
+.globl sym_1_6125
+sym_1_6125: la $2, sym_1_6125
+.globl sym_1_6126
+sym_1_6126: la $2, sym_1_6126
+.globl sym_1_6127
+sym_1_6127: la $2, sym_1_6127
+.globl sym_1_6128
+sym_1_6128: la $2, sym_1_6128
+.globl sym_1_6129
+sym_1_6129: la $2, sym_1_6129
+.globl sym_1_6130
+sym_1_6130: la $2, sym_1_6130
+.globl sym_1_6131
+sym_1_6131: la $2, sym_1_6131
+.globl sym_1_6132
+sym_1_6132: la $2, sym_1_6132
+.globl sym_1_6133
+sym_1_6133: la $2, sym_1_6133
+.globl sym_1_6134
+sym_1_6134: la $2, sym_1_6134
+.globl sym_1_6135
+sym_1_6135: la $2, sym_1_6135
+.globl sym_1_6136
+sym_1_6136: la $2, sym_1_6136
+.globl sym_1_6137
+sym_1_6137: la $2, sym_1_6137
+.globl sym_1_6138
+sym_1_6138: la $2, sym_1_6138
+.globl sym_1_6139
+sym_1_6139: la $2, sym_1_6139
+.globl sym_1_6140
+sym_1_6140: la $2, sym_1_6140
+.globl sym_1_6141
+sym_1_6141: la $2, sym_1_6141
+.globl sym_1_6142
+sym_1_6142: la $2, sym_1_6142
+.globl sym_1_6143
+sym_1_6143: la $2, sym_1_6143
+.globl sym_1_6144
+sym_1_6144: la $2, sym_1_6144
+.globl sym_1_6145
+sym_1_6145: la $2, sym_1_6145
+.globl sym_1_6146
+sym_1_6146: la $2, sym_1_6146
+.globl sym_1_6147
+sym_1_6147: la $2, sym_1_6147
+.globl sym_1_6148
+sym_1_6148: la $2, sym_1_6148
+.globl sym_1_6149
+sym_1_6149: la $2, sym_1_6149
+.globl sym_1_6150
+sym_1_6150: la $2, sym_1_6150
+.globl sym_1_6151
+sym_1_6151: la $2, sym_1_6151
+.globl sym_1_6152
+sym_1_6152: la $2, sym_1_6152
+.globl sym_1_6153
+sym_1_6153: la $2, sym_1_6153
+.globl sym_1_6154
+sym_1_6154: la $2, sym_1_6154
+.globl sym_1_6155
+sym_1_6155: la $2, sym_1_6155
+.globl sym_1_6156
+sym_1_6156: la $2, sym_1_6156
+.globl sym_1_6157
+sym_1_6157: la $2, sym_1_6157
+.globl sym_1_6158
+sym_1_6158: la $2, sym_1_6158
+.globl sym_1_6159
+sym_1_6159: la $2, sym_1_6159
+.globl sym_1_6160
+sym_1_6160: la $2, sym_1_6160
+.globl sym_1_6161
+sym_1_6161: la $2, sym_1_6161
+.globl sym_1_6162
+sym_1_6162: la $2, sym_1_6162
+.globl sym_1_6163
+sym_1_6163: la $2, sym_1_6163
+.globl sym_1_6164
+sym_1_6164: la $2, sym_1_6164
+.globl sym_1_6165
+sym_1_6165: la $2, sym_1_6165
+.globl sym_1_6166
+sym_1_6166: la $2, sym_1_6166
+.globl sym_1_6167
+sym_1_6167: la $2, sym_1_6167
+.globl sym_1_6168
+sym_1_6168: la $2, sym_1_6168
+.globl sym_1_6169
+sym_1_6169: la $2, sym_1_6169
+.globl sym_1_6170
+sym_1_6170: la $2, sym_1_6170
+.globl sym_1_6171
+sym_1_6171: la $2, sym_1_6171
+.globl sym_1_6172
+sym_1_6172: la $2, sym_1_6172
+.globl sym_1_6173
+sym_1_6173: la $2, sym_1_6173
+.globl sym_1_6174
+sym_1_6174: la $2, sym_1_6174
+.globl sym_1_6175
+sym_1_6175: la $2, sym_1_6175
+.globl sym_1_6176
+sym_1_6176: la $2, sym_1_6176
+.globl sym_1_6177
+sym_1_6177: la $2, sym_1_6177
+.globl sym_1_6178
+sym_1_6178: la $2, sym_1_6178
+.globl sym_1_6179
+sym_1_6179: la $2, sym_1_6179
+.globl sym_1_6180
+sym_1_6180: la $2, sym_1_6180
+.globl sym_1_6181
+sym_1_6181: la $2, sym_1_6181
+.globl sym_1_6182
+sym_1_6182: la $2, sym_1_6182
+.globl sym_1_6183
+sym_1_6183: la $2, sym_1_6183
+.globl sym_1_6184
+sym_1_6184: la $2, sym_1_6184
+.globl sym_1_6185
+sym_1_6185: la $2, sym_1_6185
+.globl sym_1_6186
+sym_1_6186: la $2, sym_1_6186
+.globl sym_1_6187
+sym_1_6187: la $2, sym_1_6187
+.globl sym_1_6188
+sym_1_6188: la $2, sym_1_6188
+.globl sym_1_6189
+sym_1_6189: la $2, sym_1_6189
+.globl sym_1_6190
+sym_1_6190: la $2, sym_1_6190
+.globl sym_1_6191
+sym_1_6191: la $2, sym_1_6191
+.globl sym_1_6192
+sym_1_6192: la $2, sym_1_6192
+.globl sym_1_6193
+sym_1_6193: la $2, sym_1_6193
+.globl sym_1_6194
+sym_1_6194: la $2, sym_1_6194
+.globl sym_1_6195
+sym_1_6195: la $2, sym_1_6195
+.globl sym_1_6196
+sym_1_6196: la $2, sym_1_6196
+.globl sym_1_6197
+sym_1_6197: la $2, sym_1_6197
+.globl sym_1_6198
+sym_1_6198: la $2, sym_1_6198
+.globl sym_1_6199
+sym_1_6199: la $2, sym_1_6199
+.globl sym_1_6200
+sym_1_6200: la $2, sym_1_6200
+.globl sym_1_6201
+sym_1_6201: la $2, sym_1_6201
+.globl sym_1_6202
+sym_1_6202: la $2, sym_1_6202
+.globl sym_1_6203
+sym_1_6203: la $2, sym_1_6203
+.globl sym_1_6204
+sym_1_6204: la $2, sym_1_6204
+.globl sym_1_6205
+sym_1_6205: la $2, sym_1_6205
+.globl sym_1_6206
+sym_1_6206: la $2, sym_1_6206
+.globl sym_1_6207
+sym_1_6207: la $2, sym_1_6207
+.globl sym_1_6208
+sym_1_6208: la $2, sym_1_6208
+.globl sym_1_6209
+sym_1_6209: la $2, sym_1_6209
+.globl sym_1_6210
+sym_1_6210: la $2, sym_1_6210
+.globl sym_1_6211
+sym_1_6211: la $2, sym_1_6211
+.globl sym_1_6212
+sym_1_6212: la $2, sym_1_6212
+.globl sym_1_6213
+sym_1_6213: la $2, sym_1_6213
+.globl sym_1_6214
+sym_1_6214: la $2, sym_1_6214
+.globl sym_1_6215
+sym_1_6215: la $2, sym_1_6215
+.globl sym_1_6216
+sym_1_6216: la $2, sym_1_6216
+.globl sym_1_6217
+sym_1_6217: la $2, sym_1_6217
+.globl sym_1_6218
+sym_1_6218: la $2, sym_1_6218
+.globl sym_1_6219
+sym_1_6219: la $2, sym_1_6219
+.globl sym_1_6220
+sym_1_6220: la $2, sym_1_6220
+.globl sym_1_6221
+sym_1_6221: la $2, sym_1_6221
+.globl sym_1_6222
+sym_1_6222: la $2, sym_1_6222
+.globl sym_1_6223
+sym_1_6223: la $2, sym_1_6223
+.globl sym_1_6224
+sym_1_6224: la $2, sym_1_6224
+.globl sym_1_6225
+sym_1_6225: la $2, sym_1_6225
+.globl sym_1_6226
+sym_1_6226: la $2, sym_1_6226
+.globl sym_1_6227
+sym_1_6227: la $2, sym_1_6227
+.globl sym_1_6228
+sym_1_6228: la $2, sym_1_6228
+.globl sym_1_6229
+sym_1_6229: la $2, sym_1_6229
+.globl sym_1_6230
+sym_1_6230: la $2, sym_1_6230
+.globl sym_1_6231
+sym_1_6231: la $2, sym_1_6231
+.globl sym_1_6232
+sym_1_6232: la $2, sym_1_6232
+.globl sym_1_6233
+sym_1_6233: la $2, sym_1_6233
+.globl sym_1_6234
+sym_1_6234: la $2, sym_1_6234
+.globl sym_1_6235
+sym_1_6235: la $2, sym_1_6235
+.globl sym_1_6236
+sym_1_6236: la $2, sym_1_6236
+.globl sym_1_6237
+sym_1_6237: la $2, sym_1_6237
+.globl sym_1_6238
+sym_1_6238: la $2, sym_1_6238
+.globl sym_1_6239
+sym_1_6239: la $2, sym_1_6239
+.globl sym_1_6240
+sym_1_6240: la $2, sym_1_6240
+.globl sym_1_6241
+sym_1_6241: la $2, sym_1_6241
+.globl sym_1_6242
+sym_1_6242: la $2, sym_1_6242
+.globl sym_1_6243
+sym_1_6243: la $2, sym_1_6243
+.globl sym_1_6244
+sym_1_6244: la $2, sym_1_6244
+.globl sym_1_6245
+sym_1_6245: la $2, sym_1_6245
+.globl sym_1_6246
+sym_1_6246: la $2, sym_1_6246
+.globl sym_1_6247
+sym_1_6247: la $2, sym_1_6247
+.globl sym_1_6248
+sym_1_6248: la $2, sym_1_6248
+.globl sym_1_6249
+sym_1_6249: la $2, sym_1_6249
+.globl sym_1_6250
+sym_1_6250: la $2, sym_1_6250
+.globl sym_1_6251
+sym_1_6251: la $2, sym_1_6251
+.globl sym_1_6252
+sym_1_6252: la $2, sym_1_6252
+.globl sym_1_6253
+sym_1_6253: la $2, sym_1_6253
+.globl sym_1_6254
+sym_1_6254: la $2, sym_1_6254
+.globl sym_1_6255
+sym_1_6255: la $2, sym_1_6255
+.globl sym_1_6256
+sym_1_6256: la $2, sym_1_6256
+.globl sym_1_6257
+sym_1_6257: la $2, sym_1_6257
+.globl sym_1_6258
+sym_1_6258: la $2, sym_1_6258
+.globl sym_1_6259
+sym_1_6259: la $2, sym_1_6259
+.globl sym_1_6260
+sym_1_6260: la $2, sym_1_6260
+.globl sym_1_6261
+sym_1_6261: la $2, sym_1_6261
+.globl sym_1_6262
+sym_1_6262: la $2, sym_1_6262
+.globl sym_1_6263
+sym_1_6263: la $2, sym_1_6263
+.globl sym_1_6264
+sym_1_6264: la $2, sym_1_6264
+.globl sym_1_6265
+sym_1_6265: la $2, sym_1_6265
+.globl sym_1_6266
+sym_1_6266: la $2, sym_1_6266
+.globl sym_1_6267
+sym_1_6267: la $2, sym_1_6267
+.globl sym_1_6268
+sym_1_6268: la $2, sym_1_6268
+.globl sym_1_6269
+sym_1_6269: la $2, sym_1_6269
+.globl sym_1_6270
+sym_1_6270: la $2, sym_1_6270
+.globl sym_1_6271
+sym_1_6271: la $2, sym_1_6271
+.globl sym_1_6272
+sym_1_6272: la $2, sym_1_6272
+.globl sym_1_6273
+sym_1_6273: la $2, sym_1_6273
+.globl sym_1_6274
+sym_1_6274: la $2, sym_1_6274
+.globl sym_1_6275
+sym_1_6275: la $2, sym_1_6275
+.globl sym_1_6276
+sym_1_6276: la $2, sym_1_6276
+.globl sym_1_6277
+sym_1_6277: la $2, sym_1_6277
+.globl sym_1_6278
+sym_1_6278: la $2, sym_1_6278
+.globl sym_1_6279
+sym_1_6279: la $2, sym_1_6279
+.globl sym_1_6280
+sym_1_6280: la $2, sym_1_6280
+.globl sym_1_6281
+sym_1_6281: la $2, sym_1_6281
+.globl sym_1_6282
+sym_1_6282: la $2, sym_1_6282
+.globl sym_1_6283
+sym_1_6283: la $2, sym_1_6283
+.globl sym_1_6284
+sym_1_6284: la $2, sym_1_6284
+.globl sym_1_6285
+sym_1_6285: la $2, sym_1_6285
+.globl sym_1_6286
+sym_1_6286: la $2, sym_1_6286
+.globl sym_1_6287
+sym_1_6287: la $2, sym_1_6287
+.globl sym_1_6288
+sym_1_6288: la $2, sym_1_6288
+.globl sym_1_6289
+sym_1_6289: la $2, sym_1_6289
+.globl sym_1_6290
+sym_1_6290: la $2, sym_1_6290
+.globl sym_1_6291
+sym_1_6291: la $2, sym_1_6291
+.globl sym_1_6292
+sym_1_6292: la $2, sym_1_6292
+.globl sym_1_6293
+sym_1_6293: la $2, sym_1_6293
+.globl sym_1_6294
+sym_1_6294: la $2, sym_1_6294
+.globl sym_1_6295
+sym_1_6295: la $2, sym_1_6295
+.globl sym_1_6296
+sym_1_6296: la $2, sym_1_6296
+.globl sym_1_6297
+sym_1_6297: la $2, sym_1_6297
+.globl sym_1_6298
+sym_1_6298: la $2, sym_1_6298
+.globl sym_1_6299
+sym_1_6299: la $2, sym_1_6299
+.globl sym_1_6300
+sym_1_6300: la $2, sym_1_6300
+.globl sym_1_6301
+sym_1_6301: la $2, sym_1_6301
+.globl sym_1_6302
+sym_1_6302: la $2, sym_1_6302
+.globl sym_1_6303
+sym_1_6303: la $2, sym_1_6303
+.globl sym_1_6304
+sym_1_6304: la $2, sym_1_6304
+.globl sym_1_6305
+sym_1_6305: la $2, sym_1_6305
+.globl sym_1_6306
+sym_1_6306: la $2, sym_1_6306
+.globl sym_1_6307
+sym_1_6307: la $2, sym_1_6307
+.globl sym_1_6308
+sym_1_6308: la $2, sym_1_6308
+.globl sym_1_6309
+sym_1_6309: la $2, sym_1_6309
+.globl sym_1_6310
+sym_1_6310: la $2, sym_1_6310
+.globl sym_1_6311
+sym_1_6311: la $2, sym_1_6311
+.globl sym_1_6312
+sym_1_6312: la $2, sym_1_6312
+.globl sym_1_6313
+sym_1_6313: la $2, sym_1_6313
+.globl sym_1_6314
+sym_1_6314: la $2, sym_1_6314
+.globl sym_1_6315
+sym_1_6315: la $2, sym_1_6315
+.globl sym_1_6316
+sym_1_6316: la $2, sym_1_6316
+.globl sym_1_6317
+sym_1_6317: la $2, sym_1_6317
+.globl sym_1_6318
+sym_1_6318: la $2, sym_1_6318
+.globl sym_1_6319
+sym_1_6319: la $2, sym_1_6319
+.globl sym_1_6320
+sym_1_6320: la $2, sym_1_6320
+.globl sym_1_6321
+sym_1_6321: la $2, sym_1_6321
+.globl sym_1_6322
+sym_1_6322: la $2, sym_1_6322
+.globl sym_1_6323
+sym_1_6323: la $2, sym_1_6323
+.globl sym_1_6324
+sym_1_6324: la $2, sym_1_6324
+.globl sym_1_6325
+sym_1_6325: la $2, sym_1_6325
+.globl sym_1_6326
+sym_1_6326: la $2, sym_1_6326
+.globl sym_1_6327
+sym_1_6327: la $2, sym_1_6327
+.globl sym_1_6328
+sym_1_6328: la $2, sym_1_6328
+.globl sym_1_6329
+sym_1_6329: la $2, sym_1_6329
+.globl sym_1_6330
+sym_1_6330: la $2, sym_1_6330
+.globl sym_1_6331
+sym_1_6331: la $2, sym_1_6331
+.globl sym_1_6332
+sym_1_6332: la $2, sym_1_6332
+.globl sym_1_6333
+sym_1_6333: la $2, sym_1_6333
+.globl sym_1_6334
+sym_1_6334: la $2, sym_1_6334
+.globl sym_1_6335
+sym_1_6335: la $2, sym_1_6335
+.globl sym_1_6336
+sym_1_6336: la $2, sym_1_6336
+.globl sym_1_6337
+sym_1_6337: la $2, sym_1_6337
+.globl sym_1_6338
+sym_1_6338: la $2, sym_1_6338
+.globl sym_1_6339
+sym_1_6339: la $2, sym_1_6339
+.globl sym_1_6340
+sym_1_6340: la $2, sym_1_6340
+.globl sym_1_6341
+sym_1_6341: la $2, sym_1_6341
+.globl sym_1_6342
+sym_1_6342: la $2, sym_1_6342
+.globl sym_1_6343
+sym_1_6343: la $2, sym_1_6343
+.globl sym_1_6344
+sym_1_6344: la $2, sym_1_6344
+.globl sym_1_6345
+sym_1_6345: la $2, sym_1_6345
+.globl sym_1_6346
+sym_1_6346: la $2, sym_1_6346
+.globl sym_1_6347
+sym_1_6347: la $2, sym_1_6347
+.globl sym_1_6348
+sym_1_6348: la $2, sym_1_6348
+.globl sym_1_6349
+sym_1_6349: la $2, sym_1_6349
+.globl sym_1_6350
+sym_1_6350: la $2, sym_1_6350
+.globl sym_1_6351
+sym_1_6351: la $2, sym_1_6351
+.globl sym_1_6352
+sym_1_6352: la $2, sym_1_6352
+.globl sym_1_6353
+sym_1_6353: la $2, sym_1_6353
+.globl sym_1_6354
+sym_1_6354: la $2, sym_1_6354
+.globl sym_1_6355
+sym_1_6355: la $2, sym_1_6355
+.globl sym_1_6356
+sym_1_6356: la $2, sym_1_6356
+.globl sym_1_6357
+sym_1_6357: la $2, sym_1_6357
+.globl sym_1_6358
+sym_1_6358: la $2, sym_1_6358
+.globl sym_1_6359
+sym_1_6359: la $2, sym_1_6359
+.globl sym_1_6360
+sym_1_6360: la $2, sym_1_6360
+.globl sym_1_6361
+sym_1_6361: la $2, sym_1_6361
+.globl sym_1_6362
+sym_1_6362: la $2, sym_1_6362
+.globl sym_1_6363
+sym_1_6363: la $2, sym_1_6363
+.globl sym_1_6364
+sym_1_6364: la $2, sym_1_6364
+.globl sym_1_6365
+sym_1_6365: la $2, sym_1_6365
+.globl sym_1_6366
+sym_1_6366: la $2, sym_1_6366
+.globl sym_1_6367
+sym_1_6367: la $2, sym_1_6367
+.globl sym_1_6368
+sym_1_6368: la $2, sym_1_6368
+.globl sym_1_6369
+sym_1_6369: la $2, sym_1_6369
+.globl sym_1_6370
+sym_1_6370: la $2, sym_1_6370
+.globl sym_1_6371
+sym_1_6371: la $2, sym_1_6371
+.globl sym_1_6372
+sym_1_6372: la $2, sym_1_6372
+.globl sym_1_6373
+sym_1_6373: la $2, sym_1_6373
+.globl sym_1_6374
+sym_1_6374: la $2, sym_1_6374
+.globl sym_1_6375
+sym_1_6375: la $2, sym_1_6375
+.globl sym_1_6376
+sym_1_6376: la $2, sym_1_6376
+.globl sym_1_6377
+sym_1_6377: la $2, sym_1_6377
+.globl sym_1_6378
+sym_1_6378: la $2, sym_1_6378
+.globl sym_1_6379
+sym_1_6379: la $2, sym_1_6379
+.globl sym_1_6380
+sym_1_6380: la $2, sym_1_6380
+.globl sym_1_6381
+sym_1_6381: la $2, sym_1_6381
+.globl sym_1_6382
+sym_1_6382: la $2, sym_1_6382
+.globl sym_1_6383
+sym_1_6383: la $2, sym_1_6383
+.globl sym_1_6384
+sym_1_6384: la $2, sym_1_6384
+.globl sym_1_6385
+sym_1_6385: la $2, sym_1_6385
+.globl sym_1_6386
+sym_1_6386: la $2, sym_1_6386
+.globl sym_1_6387
+sym_1_6387: la $2, sym_1_6387
+.globl sym_1_6388
+sym_1_6388: la $2, sym_1_6388
+.globl sym_1_6389
+sym_1_6389: la $2, sym_1_6389
+.globl sym_1_6390
+sym_1_6390: la $2, sym_1_6390
+.globl sym_1_6391
+sym_1_6391: la $2, sym_1_6391
+.globl sym_1_6392
+sym_1_6392: la $2, sym_1_6392
+.globl sym_1_6393
+sym_1_6393: la $2, sym_1_6393
+.globl sym_1_6394
+sym_1_6394: la $2, sym_1_6394
+.globl sym_1_6395
+sym_1_6395: la $2, sym_1_6395
+.globl sym_1_6396
+sym_1_6396: la $2, sym_1_6396
+.globl sym_1_6397
+sym_1_6397: la $2, sym_1_6397
+.globl sym_1_6398
+sym_1_6398: la $2, sym_1_6398
+.globl sym_1_6399
+sym_1_6399: la $2, sym_1_6399
+.globl sym_1_6400
+sym_1_6400: la $2, sym_1_6400
+.globl sym_1_6401
+sym_1_6401: la $2, sym_1_6401
+.globl sym_1_6402
+sym_1_6402: la $2, sym_1_6402
+.globl sym_1_6403
+sym_1_6403: la $2, sym_1_6403
+.globl sym_1_6404
+sym_1_6404: la $2, sym_1_6404
+.globl sym_1_6405
+sym_1_6405: la $2, sym_1_6405
+.globl sym_1_6406
+sym_1_6406: la $2, sym_1_6406
+.globl sym_1_6407
+sym_1_6407: la $2, sym_1_6407
+.globl sym_1_6408
+sym_1_6408: la $2, sym_1_6408
+.globl sym_1_6409
+sym_1_6409: la $2, sym_1_6409
+.globl sym_1_6410
+sym_1_6410: la $2, sym_1_6410
+.globl sym_1_6411
+sym_1_6411: la $2, sym_1_6411
+.globl sym_1_6412
+sym_1_6412: la $2, sym_1_6412
+.globl sym_1_6413
+sym_1_6413: la $2, sym_1_6413
+.globl sym_1_6414
+sym_1_6414: la $2, sym_1_6414
+.globl sym_1_6415
+sym_1_6415: la $2, sym_1_6415
+.globl sym_1_6416
+sym_1_6416: la $2, sym_1_6416
+.globl sym_1_6417
+sym_1_6417: la $2, sym_1_6417
+.globl sym_1_6418
+sym_1_6418: la $2, sym_1_6418
+.globl sym_1_6419
+sym_1_6419: la $2, sym_1_6419
+.globl sym_1_6420
+sym_1_6420: la $2, sym_1_6420
+.globl sym_1_6421
+sym_1_6421: la $2, sym_1_6421
+.globl sym_1_6422
+sym_1_6422: la $2, sym_1_6422
+.globl sym_1_6423
+sym_1_6423: la $2, sym_1_6423
+.globl sym_1_6424
+sym_1_6424: la $2, sym_1_6424
+.globl sym_1_6425
+sym_1_6425: la $2, sym_1_6425
+.globl sym_1_6426
+sym_1_6426: la $2, sym_1_6426
+.globl sym_1_6427
+sym_1_6427: la $2, sym_1_6427
+.globl sym_1_6428
+sym_1_6428: la $2, sym_1_6428
+.globl sym_1_6429
+sym_1_6429: la $2, sym_1_6429
+.globl sym_1_6430
+sym_1_6430: la $2, sym_1_6430
+.globl sym_1_6431
+sym_1_6431: la $2, sym_1_6431
+.globl sym_1_6432
+sym_1_6432: la $2, sym_1_6432
+.globl sym_1_6433
+sym_1_6433: la $2, sym_1_6433
+.globl sym_1_6434
+sym_1_6434: la $2, sym_1_6434
+.globl sym_1_6435
+sym_1_6435: la $2, sym_1_6435
+.globl sym_1_6436
+sym_1_6436: la $2, sym_1_6436
+.globl sym_1_6437
+sym_1_6437: la $2, sym_1_6437
+.globl sym_1_6438
+sym_1_6438: la $2, sym_1_6438
+.globl sym_1_6439
+sym_1_6439: la $2, sym_1_6439
+.globl sym_1_6440
+sym_1_6440: la $2, sym_1_6440
+.globl sym_1_6441
+sym_1_6441: la $2, sym_1_6441
+.globl sym_1_6442
+sym_1_6442: la $2, sym_1_6442
+.globl sym_1_6443
+sym_1_6443: la $2, sym_1_6443
+.globl sym_1_6444
+sym_1_6444: la $2, sym_1_6444
+.globl sym_1_6445
+sym_1_6445: la $2, sym_1_6445
+.globl sym_1_6446
+sym_1_6446: la $2, sym_1_6446
+.globl sym_1_6447
+sym_1_6447: la $2, sym_1_6447
+.globl sym_1_6448
+sym_1_6448: la $2, sym_1_6448
+.globl sym_1_6449
+sym_1_6449: la $2, sym_1_6449
+.globl sym_1_6450
+sym_1_6450: la $2, sym_1_6450
+.globl sym_1_6451
+sym_1_6451: la $2, sym_1_6451
+.globl sym_1_6452
+sym_1_6452: la $2, sym_1_6452
+.globl sym_1_6453
+sym_1_6453: la $2, sym_1_6453
+.globl sym_1_6454
+sym_1_6454: la $2, sym_1_6454
+.globl sym_1_6455
+sym_1_6455: la $2, sym_1_6455
+.globl sym_1_6456
+sym_1_6456: la $2, sym_1_6456
+.globl sym_1_6457
+sym_1_6457: la $2, sym_1_6457
+.globl sym_1_6458
+sym_1_6458: la $2, sym_1_6458
+.globl sym_1_6459
+sym_1_6459: la $2, sym_1_6459
+.globl sym_1_6460
+sym_1_6460: la $2, sym_1_6460
+.globl sym_1_6461
+sym_1_6461: la $2, sym_1_6461
+.globl sym_1_6462
+sym_1_6462: la $2, sym_1_6462
+.globl sym_1_6463
+sym_1_6463: la $2, sym_1_6463
+.globl sym_1_6464
+sym_1_6464: la $2, sym_1_6464
+.globl sym_1_6465
+sym_1_6465: la $2, sym_1_6465
+.globl sym_1_6466
+sym_1_6466: la $2, sym_1_6466
+.globl sym_1_6467
+sym_1_6467: la $2, sym_1_6467
+.globl sym_1_6468
+sym_1_6468: la $2, sym_1_6468
+.globl sym_1_6469
+sym_1_6469: la $2, sym_1_6469
+.globl sym_1_6470
+sym_1_6470: la $2, sym_1_6470
+.globl sym_1_6471
+sym_1_6471: la $2, sym_1_6471
+.globl sym_1_6472
+sym_1_6472: la $2, sym_1_6472
+.globl sym_1_6473
+sym_1_6473: la $2, sym_1_6473
+.globl sym_1_6474
+sym_1_6474: la $2, sym_1_6474
+.globl sym_1_6475
+sym_1_6475: la $2, sym_1_6475
+.globl sym_1_6476
+sym_1_6476: la $2, sym_1_6476
+.globl sym_1_6477
+sym_1_6477: la $2, sym_1_6477
+.globl sym_1_6478
+sym_1_6478: la $2, sym_1_6478
+.globl sym_1_6479
+sym_1_6479: la $2, sym_1_6479
+.globl sym_1_6480
+sym_1_6480: la $2, sym_1_6480
+.globl sym_1_6481
+sym_1_6481: la $2, sym_1_6481
+.globl sym_1_6482
+sym_1_6482: la $2, sym_1_6482
+.globl sym_1_6483
+sym_1_6483: la $2, sym_1_6483
+.globl sym_1_6484
+sym_1_6484: la $2, sym_1_6484
+.globl sym_1_6485
+sym_1_6485: la $2, sym_1_6485
+.globl sym_1_6486
+sym_1_6486: la $2, sym_1_6486
+.globl sym_1_6487
+sym_1_6487: la $2, sym_1_6487
+.globl sym_1_6488
+sym_1_6488: la $2, sym_1_6488
+.globl sym_1_6489
+sym_1_6489: la $2, sym_1_6489
+.globl sym_1_6490
+sym_1_6490: la $2, sym_1_6490
+.globl sym_1_6491
+sym_1_6491: la $2, sym_1_6491
+.globl sym_1_6492
+sym_1_6492: la $2, sym_1_6492
+.globl sym_1_6493
+sym_1_6493: la $2, sym_1_6493
+.globl sym_1_6494
+sym_1_6494: la $2, sym_1_6494
+.globl sym_1_6495
+sym_1_6495: la $2, sym_1_6495
+.globl sym_1_6496
+sym_1_6496: la $2, sym_1_6496
+.globl sym_1_6497
+sym_1_6497: la $2, sym_1_6497
+.globl sym_1_6498
+sym_1_6498: la $2, sym_1_6498
+.globl sym_1_6499
+sym_1_6499: la $2, sym_1_6499
+.globl sym_1_6500
+sym_1_6500: la $2, sym_1_6500
+.globl sym_1_6501
+sym_1_6501: la $2, sym_1_6501
+.globl sym_1_6502
+sym_1_6502: la $2, sym_1_6502
+.globl sym_1_6503
+sym_1_6503: la $2, sym_1_6503
+.globl sym_1_6504
+sym_1_6504: la $2, sym_1_6504
+.globl sym_1_6505
+sym_1_6505: la $2, sym_1_6505
+.globl sym_1_6506
+sym_1_6506: la $2, sym_1_6506
+.globl sym_1_6507
+sym_1_6507: la $2, sym_1_6507
+.globl sym_1_6508
+sym_1_6508: la $2, sym_1_6508
+.globl sym_1_6509
+sym_1_6509: la $2, sym_1_6509
+.globl sym_1_6510
+sym_1_6510: la $2, sym_1_6510
+.globl sym_1_6511
+sym_1_6511: la $2, sym_1_6511
+.globl sym_1_6512
+sym_1_6512: la $2, sym_1_6512
+.globl sym_1_6513
+sym_1_6513: la $2, sym_1_6513
+.globl sym_1_6514
+sym_1_6514: la $2, sym_1_6514
+.globl sym_1_6515
+sym_1_6515: la $2, sym_1_6515
+.globl sym_1_6516
+sym_1_6516: la $2, sym_1_6516
+.globl sym_1_6517
+sym_1_6517: la $2, sym_1_6517
+.globl sym_1_6518
+sym_1_6518: la $2, sym_1_6518
+.globl sym_1_6519
+sym_1_6519: la $2, sym_1_6519
+.globl sym_1_6520
+sym_1_6520: la $2, sym_1_6520
+.globl sym_1_6521
+sym_1_6521: la $2, sym_1_6521
+.globl sym_1_6522
+sym_1_6522: la $2, sym_1_6522
+.globl sym_1_6523
+sym_1_6523: la $2, sym_1_6523
+.globl sym_1_6524
+sym_1_6524: la $2, sym_1_6524
+.globl sym_1_6525
+sym_1_6525: la $2, sym_1_6525
+.globl sym_1_6526
+sym_1_6526: la $2, sym_1_6526
+.globl sym_1_6527
+sym_1_6527: la $2, sym_1_6527
+.globl sym_1_6528
+sym_1_6528: la $2, sym_1_6528
+.globl sym_1_6529
+sym_1_6529: la $2, sym_1_6529
+.globl sym_1_6530
+sym_1_6530: la $2, sym_1_6530
+.globl sym_1_6531
+sym_1_6531: la $2, sym_1_6531
+.globl sym_1_6532
+sym_1_6532: la $2, sym_1_6532
+.globl sym_1_6533
+sym_1_6533: la $2, sym_1_6533
+.globl sym_1_6534
+sym_1_6534: la $2, sym_1_6534
+.globl sym_1_6535
+sym_1_6535: la $2, sym_1_6535
+.globl sym_1_6536
+sym_1_6536: la $2, sym_1_6536
+.globl sym_1_6537
+sym_1_6537: la $2, sym_1_6537
+.globl sym_1_6538
+sym_1_6538: la $2, sym_1_6538
+.globl sym_1_6539
+sym_1_6539: la $2, sym_1_6539
+.globl sym_1_6540
+sym_1_6540: la $2, sym_1_6540
+.globl sym_1_6541
+sym_1_6541: la $2, sym_1_6541
+.globl sym_1_6542
+sym_1_6542: la $2, sym_1_6542
+.globl sym_1_6543
+sym_1_6543: la $2, sym_1_6543
+.globl sym_1_6544
+sym_1_6544: la $2, sym_1_6544
+.globl sym_1_6545
+sym_1_6545: la $2, sym_1_6545
+.globl sym_1_6546
+sym_1_6546: la $2, sym_1_6546
+.globl sym_1_6547
+sym_1_6547: la $2, sym_1_6547
+.globl sym_1_6548
+sym_1_6548: la $2, sym_1_6548
+.globl sym_1_6549
+sym_1_6549: la $2, sym_1_6549
+.globl sym_1_6550
+sym_1_6550: la $2, sym_1_6550
+.globl sym_1_6551
+sym_1_6551: la $2, sym_1_6551
+.globl sym_1_6552
+sym_1_6552: la $2, sym_1_6552
+.globl sym_1_6553
+sym_1_6553: la $2, sym_1_6553
+.globl sym_1_6554
+sym_1_6554: la $2, sym_1_6554
+.globl sym_1_6555
+sym_1_6555: la $2, sym_1_6555
+.globl sym_1_6556
+sym_1_6556: la $2, sym_1_6556
+.globl sym_1_6557
+sym_1_6557: la $2, sym_1_6557
+.globl sym_1_6558
+sym_1_6558: la $2, sym_1_6558
+.globl sym_1_6559
+sym_1_6559: la $2, sym_1_6559
+.globl sym_1_6560
+sym_1_6560: la $2, sym_1_6560
+.globl sym_1_6561
+sym_1_6561: la $2, sym_1_6561
+.globl sym_1_6562
+sym_1_6562: la $2, sym_1_6562
+.globl sym_1_6563
+sym_1_6563: la $2, sym_1_6563
+.globl sym_1_6564
+sym_1_6564: la $2, sym_1_6564
+.globl sym_1_6565
+sym_1_6565: la $2, sym_1_6565
+.globl sym_1_6566
+sym_1_6566: la $2, sym_1_6566
+.globl sym_1_6567
+sym_1_6567: la $2, sym_1_6567
+.globl sym_1_6568
+sym_1_6568: la $2, sym_1_6568
+.globl sym_1_6569
+sym_1_6569: la $2, sym_1_6569
+.globl sym_1_6570
+sym_1_6570: la $2, sym_1_6570
+.globl sym_1_6571
+sym_1_6571: la $2, sym_1_6571
+.globl sym_1_6572
+sym_1_6572: la $2, sym_1_6572
+.globl sym_1_6573
+sym_1_6573: la $2, sym_1_6573
+.globl sym_1_6574
+sym_1_6574: la $2, sym_1_6574
+.globl sym_1_6575
+sym_1_6575: la $2, sym_1_6575
+.globl sym_1_6576
+sym_1_6576: la $2, sym_1_6576
+.globl sym_1_6577
+sym_1_6577: la $2, sym_1_6577
+.globl sym_1_6578
+sym_1_6578: la $2, sym_1_6578
+.globl sym_1_6579
+sym_1_6579: la $2, sym_1_6579
+.globl sym_1_6580
+sym_1_6580: la $2, sym_1_6580
+.globl sym_1_6581
+sym_1_6581: la $2, sym_1_6581
+.globl sym_1_6582
+sym_1_6582: la $2, sym_1_6582
+.globl sym_1_6583
+sym_1_6583: la $2, sym_1_6583
+.globl sym_1_6584
+sym_1_6584: la $2, sym_1_6584
+.globl sym_1_6585
+sym_1_6585: la $2, sym_1_6585
+.globl sym_1_6586
+sym_1_6586: la $2, sym_1_6586
+.globl sym_1_6587
+sym_1_6587: la $2, sym_1_6587
+.globl sym_1_6588
+sym_1_6588: la $2, sym_1_6588
+.globl sym_1_6589
+sym_1_6589: la $2, sym_1_6589
+.globl sym_1_6590
+sym_1_6590: la $2, sym_1_6590
+.globl sym_1_6591
+sym_1_6591: la $2, sym_1_6591
+.globl sym_1_6592
+sym_1_6592: la $2, sym_1_6592
+.globl sym_1_6593
+sym_1_6593: la $2, sym_1_6593
+.globl sym_1_6594
+sym_1_6594: la $2, sym_1_6594
+.globl sym_1_6595
+sym_1_6595: la $2, sym_1_6595
+.globl sym_1_6596
+sym_1_6596: la $2, sym_1_6596
+.globl sym_1_6597
+sym_1_6597: la $2, sym_1_6597
+.globl sym_1_6598
+sym_1_6598: la $2, sym_1_6598
+.globl sym_1_6599
+sym_1_6599: la $2, sym_1_6599
+.globl sym_1_6600
+sym_1_6600: la $2, sym_1_6600
+.globl sym_1_6601
+sym_1_6601: la $2, sym_1_6601
+.globl sym_1_6602
+sym_1_6602: la $2, sym_1_6602
+.globl sym_1_6603
+sym_1_6603: la $2, sym_1_6603
+.globl sym_1_6604
+sym_1_6604: la $2, sym_1_6604
+.globl sym_1_6605
+sym_1_6605: la $2, sym_1_6605
+.globl sym_1_6606
+sym_1_6606: la $2, sym_1_6606
+.globl sym_1_6607
+sym_1_6607: la $2, sym_1_6607
+.globl sym_1_6608
+sym_1_6608: la $2, sym_1_6608
+.globl sym_1_6609
+sym_1_6609: la $2, sym_1_6609
+.globl sym_1_6610
+sym_1_6610: la $2, sym_1_6610
+.globl sym_1_6611
+sym_1_6611: la $2, sym_1_6611
+.globl sym_1_6612
+sym_1_6612: la $2, sym_1_6612
+.globl sym_1_6613
+sym_1_6613: la $2, sym_1_6613
+.globl sym_1_6614
+sym_1_6614: la $2, sym_1_6614
+.globl sym_1_6615
+sym_1_6615: la $2, sym_1_6615
+.globl sym_1_6616
+sym_1_6616: la $2, sym_1_6616
+.globl sym_1_6617
+sym_1_6617: la $2, sym_1_6617
+.globl sym_1_6618
+sym_1_6618: la $2, sym_1_6618
+.globl sym_1_6619
+sym_1_6619: la $2, sym_1_6619
+.globl sym_1_6620
+sym_1_6620: la $2, sym_1_6620
+.globl sym_1_6621
+sym_1_6621: la $2, sym_1_6621
+.globl sym_1_6622
+sym_1_6622: la $2, sym_1_6622
+.globl sym_1_6623
+sym_1_6623: la $2, sym_1_6623
+.globl sym_1_6624
+sym_1_6624: la $2, sym_1_6624
+.globl sym_1_6625
+sym_1_6625: la $2, sym_1_6625
+.globl sym_1_6626
+sym_1_6626: la $2, sym_1_6626
+.globl sym_1_6627
+sym_1_6627: la $2, sym_1_6627
+.globl sym_1_6628
+sym_1_6628: la $2, sym_1_6628
+.globl sym_1_6629
+sym_1_6629: la $2, sym_1_6629
+.globl sym_1_6630
+sym_1_6630: la $2, sym_1_6630
+.globl sym_1_6631
+sym_1_6631: la $2, sym_1_6631
+.globl sym_1_6632
+sym_1_6632: la $2, sym_1_6632
+.globl sym_1_6633
+sym_1_6633: la $2, sym_1_6633
+.globl sym_1_6634
+sym_1_6634: la $2, sym_1_6634
+.globl sym_1_6635
+sym_1_6635: la $2, sym_1_6635
+.globl sym_1_6636
+sym_1_6636: la $2, sym_1_6636
+.globl sym_1_6637
+sym_1_6637: la $2, sym_1_6637
+.globl sym_1_6638
+sym_1_6638: la $2, sym_1_6638
+.globl sym_1_6639
+sym_1_6639: la $2, sym_1_6639
+.globl sym_1_6640
+sym_1_6640: la $2, sym_1_6640
+.globl sym_1_6641
+sym_1_6641: la $2, sym_1_6641
+.globl sym_1_6642
+sym_1_6642: la $2, sym_1_6642
+.globl sym_1_6643
+sym_1_6643: la $2, sym_1_6643
+.globl sym_1_6644
+sym_1_6644: la $2, sym_1_6644
+.globl sym_1_6645
+sym_1_6645: la $2, sym_1_6645
+.globl sym_1_6646
+sym_1_6646: la $2, sym_1_6646
+.globl sym_1_6647
+sym_1_6647: la $2, sym_1_6647
+.globl sym_1_6648
+sym_1_6648: la $2, sym_1_6648
+.globl sym_1_6649
+sym_1_6649: la $2, sym_1_6649
+.globl sym_1_6650
+sym_1_6650: la $2, sym_1_6650
+.globl sym_1_6651
+sym_1_6651: la $2, sym_1_6651
+.globl sym_1_6652
+sym_1_6652: la $2, sym_1_6652
+.globl sym_1_6653
+sym_1_6653: la $2, sym_1_6653
+.globl sym_1_6654
+sym_1_6654: la $2, sym_1_6654
+.globl sym_1_6655
+sym_1_6655: la $2, sym_1_6655
+.globl sym_1_6656
+sym_1_6656: la $2, sym_1_6656
+.globl sym_1_6657
+sym_1_6657: la $2, sym_1_6657
+.globl sym_1_6658
+sym_1_6658: la $2, sym_1_6658
+.globl sym_1_6659
+sym_1_6659: la $2, sym_1_6659
+.globl sym_1_6660
+sym_1_6660: la $2, sym_1_6660
+.globl sym_1_6661
+sym_1_6661: la $2, sym_1_6661
+.globl sym_1_6662
+sym_1_6662: la $2, sym_1_6662
+.globl sym_1_6663
+sym_1_6663: la $2, sym_1_6663
+.globl sym_1_6664
+sym_1_6664: la $2, sym_1_6664
+.globl sym_1_6665
+sym_1_6665: la $2, sym_1_6665
+.globl sym_1_6666
+sym_1_6666: la $2, sym_1_6666
+.globl sym_1_6667
+sym_1_6667: la $2, sym_1_6667
+.globl sym_1_6668
+sym_1_6668: la $2, sym_1_6668
+.globl sym_1_6669
+sym_1_6669: la $2, sym_1_6669
+.globl sym_1_6670
+sym_1_6670: la $2, sym_1_6670
+.globl sym_1_6671
+sym_1_6671: la $2, sym_1_6671
+.globl sym_1_6672
+sym_1_6672: la $2, sym_1_6672
+.globl sym_1_6673
+sym_1_6673: la $2, sym_1_6673
+.globl sym_1_6674
+sym_1_6674: la $2, sym_1_6674
+.globl sym_1_6675
+sym_1_6675: la $2, sym_1_6675
+.globl sym_1_6676
+sym_1_6676: la $2, sym_1_6676
+.globl sym_1_6677
+sym_1_6677: la $2, sym_1_6677
+.globl sym_1_6678
+sym_1_6678: la $2, sym_1_6678
+.globl sym_1_6679
+sym_1_6679: la $2, sym_1_6679
+.globl sym_1_6680
+sym_1_6680: la $2, sym_1_6680
+.globl sym_1_6681
+sym_1_6681: la $2, sym_1_6681
+.globl sym_1_6682
+sym_1_6682: la $2, sym_1_6682
+.globl sym_1_6683
+sym_1_6683: la $2, sym_1_6683
+.globl sym_1_6684
+sym_1_6684: la $2, sym_1_6684
+.globl sym_1_6685
+sym_1_6685: la $2, sym_1_6685
+.globl sym_1_6686
+sym_1_6686: la $2, sym_1_6686
+.globl sym_1_6687
+sym_1_6687: la $2, sym_1_6687
+.globl sym_1_6688
+sym_1_6688: la $2, sym_1_6688
+.globl sym_1_6689
+sym_1_6689: la $2, sym_1_6689
+.globl sym_1_6690
+sym_1_6690: la $2, sym_1_6690
+.globl sym_1_6691
+sym_1_6691: la $2, sym_1_6691
+.globl sym_1_6692
+sym_1_6692: la $2, sym_1_6692
+.globl sym_1_6693
+sym_1_6693: la $2, sym_1_6693
+.globl sym_1_6694
+sym_1_6694: la $2, sym_1_6694
+.globl sym_1_6695
+sym_1_6695: la $2, sym_1_6695
+.globl sym_1_6696
+sym_1_6696: la $2, sym_1_6696
+.globl sym_1_6697
+sym_1_6697: la $2, sym_1_6697
+.globl sym_1_6698
+sym_1_6698: la $2, sym_1_6698
+.globl sym_1_6699
+sym_1_6699: la $2, sym_1_6699
+.globl sym_1_6700
+sym_1_6700: la $2, sym_1_6700
+.globl sym_1_6701
+sym_1_6701: la $2, sym_1_6701
+.globl sym_1_6702
+sym_1_6702: la $2, sym_1_6702
+.globl sym_1_6703
+sym_1_6703: la $2, sym_1_6703
+.globl sym_1_6704
+sym_1_6704: la $2, sym_1_6704
+.globl sym_1_6705
+sym_1_6705: la $2, sym_1_6705
+.globl sym_1_6706
+sym_1_6706: la $2, sym_1_6706
+.globl sym_1_6707
+sym_1_6707: la $2, sym_1_6707
+.globl sym_1_6708
+sym_1_6708: la $2, sym_1_6708
+.globl sym_1_6709
+sym_1_6709: la $2, sym_1_6709
+.globl sym_1_6710
+sym_1_6710: la $2, sym_1_6710
+.globl sym_1_6711
+sym_1_6711: la $2, sym_1_6711
+.globl sym_1_6712
+sym_1_6712: la $2, sym_1_6712
+.globl sym_1_6713
+sym_1_6713: la $2, sym_1_6713
+.globl sym_1_6714
+sym_1_6714: la $2, sym_1_6714
+.globl sym_1_6715
+sym_1_6715: la $2, sym_1_6715
+.globl sym_1_6716
+sym_1_6716: la $2, sym_1_6716
+.globl sym_1_6717
+sym_1_6717: la $2, sym_1_6717
+.globl sym_1_6718
+sym_1_6718: la $2, sym_1_6718
+.globl sym_1_6719
+sym_1_6719: la $2, sym_1_6719
+.globl sym_1_6720
+sym_1_6720: la $2, sym_1_6720
+.globl sym_1_6721
+sym_1_6721: la $2, sym_1_6721
+.globl sym_1_6722
+sym_1_6722: la $2, sym_1_6722
+.globl sym_1_6723
+sym_1_6723: la $2, sym_1_6723
+.globl sym_1_6724
+sym_1_6724: la $2, sym_1_6724
+.globl sym_1_6725
+sym_1_6725: la $2, sym_1_6725
+.globl sym_1_6726
+sym_1_6726: la $2, sym_1_6726
+.globl sym_1_6727
+sym_1_6727: la $2, sym_1_6727
+.globl sym_1_6728
+sym_1_6728: la $2, sym_1_6728
+.globl sym_1_6729
+sym_1_6729: la $2, sym_1_6729
+.globl sym_1_6730
+sym_1_6730: la $2, sym_1_6730
+.globl sym_1_6731
+sym_1_6731: la $2, sym_1_6731
+.globl sym_1_6732
+sym_1_6732: la $2, sym_1_6732
+.globl sym_1_6733
+sym_1_6733: la $2, sym_1_6733
+.globl sym_1_6734
+sym_1_6734: la $2, sym_1_6734
+.globl sym_1_6735
+sym_1_6735: la $2, sym_1_6735
+.globl sym_1_6736
+sym_1_6736: la $2, sym_1_6736
+.globl sym_1_6737
+sym_1_6737: la $2, sym_1_6737
+.globl sym_1_6738
+sym_1_6738: la $2, sym_1_6738
+.globl sym_1_6739
+sym_1_6739: la $2, sym_1_6739
+.globl sym_1_6740
+sym_1_6740: la $2, sym_1_6740
+.globl sym_1_6741
+sym_1_6741: la $2, sym_1_6741
+.globl sym_1_6742
+sym_1_6742: la $2, sym_1_6742
+.globl sym_1_6743
+sym_1_6743: la $2, sym_1_6743
+.globl sym_1_6744
+sym_1_6744: la $2, sym_1_6744
+.globl sym_1_6745
+sym_1_6745: la $2, sym_1_6745
+.globl sym_1_6746
+sym_1_6746: la $2, sym_1_6746
+.globl sym_1_6747
+sym_1_6747: la $2, sym_1_6747
+.globl sym_1_6748
+sym_1_6748: la $2, sym_1_6748
+.globl sym_1_6749
+sym_1_6749: la $2, sym_1_6749
+.globl sym_1_6750
+sym_1_6750: la $2, sym_1_6750
+.globl sym_1_6751
+sym_1_6751: la $2, sym_1_6751
+.globl sym_1_6752
+sym_1_6752: la $2, sym_1_6752
+.globl sym_1_6753
+sym_1_6753: la $2, sym_1_6753
+.globl sym_1_6754
+sym_1_6754: la $2, sym_1_6754
+.globl sym_1_6755
+sym_1_6755: la $2, sym_1_6755
+.globl sym_1_6756
+sym_1_6756: la $2, sym_1_6756
+.globl sym_1_6757
+sym_1_6757: la $2, sym_1_6757
+.globl sym_1_6758
+sym_1_6758: la $2, sym_1_6758
+.globl sym_1_6759
+sym_1_6759: la $2, sym_1_6759
+.globl sym_1_6760
+sym_1_6760: la $2, sym_1_6760
+.globl sym_1_6761
+sym_1_6761: la $2, sym_1_6761
+.globl sym_1_6762
+sym_1_6762: la $2, sym_1_6762
+.globl sym_1_6763
+sym_1_6763: la $2, sym_1_6763
+.globl sym_1_6764
+sym_1_6764: la $2, sym_1_6764
+.globl sym_1_6765
+sym_1_6765: la $2, sym_1_6765
+.globl sym_1_6766
+sym_1_6766: la $2, sym_1_6766
+.globl sym_1_6767
+sym_1_6767: la $2, sym_1_6767
+.globl sym_1_6768
+sym_1_6768: la $2, sym_1_6768
+.globl sym_1_6769
+sym_1_6769: la $2, sym_1_6769
+.globl sym_1_6770
+sym_1_6770: la $2, sym_1_6770
+.globl sym_1_6771
+sym_1_6771: la $2, sym_1_6771
+.globl sym_1_6772
+sym_1_6772: la $2, sym_1_6772
+.globl sym_1_6773
+sym_1_6773: la $2, sym_1_6773
+.globl sym_1_6774
+sym_1_6774: la $2, sym_1_6774
+.globl sym_1_6775
+sym_1_6775: la $2, sym_1_6775
+.globl sym_1_6776
+sym_1_6776: la $2, sym_1_6776
+.globl sym_1_6777
+sym_1_6777: la $2, sym_1_6777
+.globl sym_1_6778
+sym_1_6778: la $2, sym_1_6778
+.globl sym_1_6779
+sym_1_6779: la $2, sym_1_6779
+.globl sym_1_6780
+sym_1_6780: la $2, sym_1_6780
+.globl sym_1_6781
+sym_1_6781: la $2, sym_1_6781
+.globl sym_1_6782
+sym_1_6782: la $2, sym_1_6782
+.globl sym_1_6783
+sym_1_6783: la $2, sym_1_6783
+.globl sym_1_6784
+sym_1_6784: la $2, sym_1_6784
+.globl sym_1_6785
+sym_1_6785: la $2, sym_1_6785
+.globl sym_1_6786
+sym_1_6786: la $2, sym_1_6786
+.globl sym_1_6787
+sym_1_6787: la $2, sym_1_6787
+.globl sym_1_6788
+sym_1_6788: la $2, sym_1_6788
+.globl sym_1_6789
+sym_1_6789: la $2, sym_1_6789
+.globl sym_1_6790
+sym_1_6790: la $2, sym_1_6790
+.globl sym_1_6791
+sym_1_6791: la $2, sym_1_6791
+.globl sym_1_6792
+sym_1_6792: la $2, sym_1_6792
+.globl sym_1_6793
+sym_1_6793: la $2, sym_1_6793
+.globl sym_1_6794
+sym_1_6794: la $2, sym_1_6794
+.globl sym_1_6795
+sym_1_6795: la $2, sym_1_6795
+.globl sym_1_6796
+sym_1_6796: la $2, sym_1_6796
+.globl sym_1_6797
+sym_1_6797: la $2, sym_1_6797
+.globl sym_1_6798
+sym_1_6798: la $2, sym_1_6798
+.globl sym_1_6799
+sym_1_6799: la $2, sym_1_6799
+.globl sym_1_6800
+sym_1_6800: la $2, sym_1_6800
+.globl sym_1_6801
+sym_1_6801: la $2, sym_1_6801
+.globl sym_1_6802
+sym_1_6802: la $2, sym_1_6802
+.globl sym_1_6803
+sym_1_6803: la $2, sym_1_6803
+.globl sym_1_6804
+sym_1_6804: la $2, sym_1_6804
+.globl sym_1_6805
+sym_1_6805: la $2, sym_1_6805
+.globl sym_1_6806
+sym_1_6806: la $2, sym_1_6806
+.globl sym_1_6807
+sym_1_6807: la $2, sym_1_6807
+.globl sym_1_6808
+sym_1_6808: la $2, sym_1_6808
+.globl sym_1_6809
+sym_1_6809: la $2, sym_1_6809
+.globl sym_1_6810
+sym_1_6810: la $2, sym_1_6810
+.globl sym_1_6811
+sym_1_6811: la $2, sym_1_6811
+.globl sym_1_6812
+sym_1_6812: la $2, sym_1_6812
+.globl sym_1_6813
+sym_1_6813: la $2, sym_1_6813
+.globl sym_1_6814
+sym_1_6814: la $2, sym_1_6814
+.globl sym_1_6815
+sym_1_6815: la $2, sym_1_6815
+.globl sym_1_6816
+sym_1_6816: la $2, sym_1_6816
+.globl sym_1_6817
+sym_1_6817: la $2, sym_1_6817
+.globl sym_1_6818
+sym_1_6818: la $2, sym_1_6818
+.globl sym_1_6819
+sym_1_6819: la $2, sym_1_6819
+.globl sym_1_6820
+sym_1_6820: la $2, sym_1_6820
+.globl sym_1_6821
+sym_1_6821: la $2, sym_1_6821
+.globl sym_1_6822
+sym_1_6822: la $2, sym_1_6822
+.globl sym_1_6823
+sym_1_6823: la $2, sym_1_6823
+.globl sym_1_6824
+sym_1_6824: la $2, sym_1_6824
+.globl sym_1_6825
+sym_1_6825: la $2, sym_1_6825
+.globl sym_1_6826
+sym_1_6826: la $2, sym_1_6826
+.globl sym_1_6827
+sym_1_6827: la $2, sym_1_6827
+.globl sym_1_6828
+sym_1_6828: la $2, sym_1_6828
+.globl sym_1_6829
+sym_1_6829: la $2, sym_1_6829
+.globl sym_1_6830
+sym_1_6830: la $2, sym_1_6830
+.globl sym_1_6831
+sym_1_6831: la $2, sym_1_6831
+.globl sym_1_6832
+sym_1_6832: la $2, sym_1_6832
+.globl sym_1_6833
+sym_1_6833: la $2, sym_1_6833
+.globl sym_1_6834
+sym_1_6834: la $2, sym_1_6834
+.globl sym_1_6835
+sym_1_6835: la $2, sym_1_6835
+.globl sym_1_6836
+sym_1_6836: la $2, sym_1_6836
+.globl sym_1_6837
+sym_1_6837: la $2, sym_1_6837
+.globl sym_1_6838
+sym_1_6838: la $2, sym_1_6838
+.globl sym_1_6839
+sym_1_6839: la $2, sym_1_6839
+.globl sym_1_6840
+sym_1_6840: la $2, sym_1_6840
+.globl sym_1_6841
+sym_1_6841: la $2, sym_1_6841
+.globl sym_1_6842
+sym_1_6842: la $2, sym_1_6842
+.globl sym_1_6843
+sym_1_6843: la $2, sym_1_6843
+.globl sym_1_6844
+sym_1_6844: la $2, sym_1_6844
+.globl sym_1_6845
+sym_1_6845: la $2, sym_1_6845
+.globl sym_1_6846
+sym_1_6846: la $2, sym_1_6846
+.globl sym_1_6847
+sym_1_6847: la $2, sym_1_6847
+.globl sym_1_6848
+sym_1_6848: la $2, sym_1_6848
+.globl sym_1_6849
+sym_1_6849: la $2, sym_1_6849
+.globl sym_1_6850
+sym_1_6850: la $2, sym_1_6850
+.globl sym_1_6851
+sym_1_6851: la $2, sym_1_6851
+.globl sym_1_6852
+sym_1_6852: la $2, sym_1_6852
+.globl sym_1_6853
+sym_1_6853: la $2, sym_1_6853
+.globl sym_1_6854
+sym_1_6854: la $2, sym_1_6854
+.globl sym_1_6855
+sym_1_6855: la $2, sym_1_6855
+.globl sym_1_6856
+sym_1_6856: la $2, sym_1_6856
+.globl sym_1_6857
+sym_1_6857: la $2, sym_1_6857
+.globl sym_1_6858
+sym_1_6858: la $2, sym_1_6858
+.globl sym_1_6859
+sym_1_6859: la $2, sym_1_6859
+.globl sym_1_6860
+sym_1_6860: la $2, sym_1_6860
+.globl sym_1_6861
+sym_1_6861: la $2, sym_1_6861
+.globl sym_1_6862
+sym_1_6862: la $2, sym_1_6862
+.globl sym_1_6863
+sym_1_6863: la $2, sym_1_6863
+.globl sym_1_6864
+sym_1_6864: la $2, sym_1_6864
+.globl sym_1_6865
+sym_1_6865: la $2, sym_1_6865
+.globl sym_1_6866
+sym_1_6866: la $2, sym_1_6866
+.globl sym_1_6867
+sym_1_6867: la $2, sym_1_6867
+.globl sym_1_6868
+sym_1_6868: la $2, sym_1_6868
+.globl sym_1_6869
+sym_1_6869: la $2, sym_1_6869
+.globl sym_1_6870
+sym_1_6870: la $2, sym_1_6870
+.globl sym_1_6871
+sym_1_6871: la $2, sym_1_6871
+.globl sym_1_6872
+sym_1_6872: la $2, sym_1_6872
+.globl sym_1_6873
+sym_1_6873: la $2, sym_1_6873
+.globl sym_1_6874
+sym_1_6874: la $2, sym_1_6874
+.globl sym_1_6875
+sym_1_6875: la $2, sym_1_6875
+.globl sym_1_6876
+sym_1_6876: la $2, sym_1_6876
+.globl sym_1_6877
+sym_1_6877: la $2, sym_1_6877
+.globl sym_1_6878
+sym_1_6878: la $2, sym_1_6878
+.globl sym_1_6879
+sym_1_6879: la $2, sym_1_6879
+.globl sym_1_6880
+sym_1_6880: la $2, sym_1_6880
+.globl sym_1_6881
+sym_1_6881: la $2, sym_1_6881
+.globl sym_1_6882
+sym_1_6882: la $2, sym_1_6882
+.globl sym_1_6883
+sym_1_6883: la $2, sym_1_6883
+.globl sym_1_6884
+sym_1_6884: la $2, sym_1_6884
+.globl sym_1_6885
+sym_1_6885: la $2, sym_1_6885
+.globl sym_1_6886
+sym_1_6886: la $2, sym_1_6886
+.globl sym_1_6887
+sym_1_6887: la $2, sym_1_6887
+.globl sym_1_6888
+sym_1_6888: la $2, sym_1_6888
+.globl sym_1_6889
+sym_1_6889: la $2, sym_1_6889
+.globl sym_1_6890
+sym_1_6890: la $2, sym_1_6890
+.globl sym_1_6891
+sym_1_6891: la $2, sym_1_6891
+.globl sym_1_6892
+sym_1_6892: la $2, sym_1_6892
+.globl sym_1_6893
+sym_1_6893: la $2, sym_1_6893
+.globl sym_1_6894
+sym_1_6894: la $2, sym_1_6894
+.globl sym_1_6895
+sym_1_6895: la $2, sym_1_6895
+.globl sym_1_6896
+sym_1_6896: la $2, sym_1_6896
+.globl sym_1_6897
+sym_1_6897: la $2, sym_1_6897
+.globl sym_1_6898
+sym_1_6898: la $2, sym_1_6898
+.globl sym_1_6899
+sym_1_6899: la $2, sym_1_6899
+.globl sym_1_6900
+sym_1_6900: la $2, sym_1_6900
+.globl sym_1_6901
+sym_1_6901: la $2, sym_1_6901
+.globl sym_1_6902
+sym_1_6902: la $2, sym_1_6902
+.globl sym_1_6903
+sym_1_6903: la $2, sym_1_6903
+.globl sym_1_6904
+sym_1_6904: la $2, sym_1_6904
+.globl sym_1_6905
+sym_1_6905: la $2, sym_1_6905
+.globl sym_1_6906
+sym_1_6906: la $2, sym_1_6906
+.globl sym_1_6907
+sym_1_6907: la $2, sym_1_6907
+.globl sym_1_6908
+sym_1_6908: la $2, sym_1_6908
+.globl sym_1_6909
+sym_1_6909: la $2, sym_1_6909
+.globl sym_1_6910
+sym_1_6910: la $2, sym_1_6910
+.globl sym_1_6911
+sym_1_6911: la $2, sym_1_6911
+.globl sym_1_6912
+sym_1_6912: la $2, sym_1_6912
+.globl sym_1_6913
+sym_1_6913: la $2, sym_1_6913
+.globl sym_1_6914
+sym_1_6914: la $2, sym_1_6914
+.globl sym_1_6915
+sym_1_6915: la $2, sym_1_6915
+.globl sym_1_6916
+sym_1_6916: la $2, sym_1_6916
+.globl sym_1_6917
+sym_1_6917: la $2, sym_1_6917
+.globl sym_1_6918
+sym_1_6918: la $2, sym_1_6918
+.globl sym_1_6919
+sym_1_6919: la $2, sym_1_6919
+.globl sym_1_6920
+sym_1_6920: la $2, sym_1_6920
+.globl sym_1_6921
+sym_1_6921: la $2, sym_1_6921
+.globl sym_1_6922
+sym_1_6922: la $2, sym_1_6922
+.globl sym_1_6923
+sym_1_6923: la $2, sym_1_6923
+.globl sym_1_6924
+sym_1_6924: la $2, sym_1_6924
+.globl sym_1_6925
+sym_1_6925: la $2, sym_1_6925
+.globl sym_1_6926
+sym_1_6926: la $2, sym_1_6926
+.globl sym_1_6927
+sym_1_6927: la $2, sym_1_6927
+.globl sym_1_6928
+sym_1_6928: la $2, sym_1_6928
+.globl sym_1_6929
+sym_1_6929: la $2, sym_1_6929
+.globl sym_1_6930
+sym_1_6930: la $2, sym_1_6930
+.globl sym_1_6931
+sym_1_6931: la $2, sym_1_6931
+.globl sym_1_6932
+sym_1_6932: la $2, sym_1_6932
+.globl sym_1_6933
+sym_1_6933: la $2, sym_1_6933
+.globl sym_1_6934
+sym_1_6934: la $2, sym_1_6934
+.globl sym_1_6935
+sym_1_6935: la $2, sym_1_6935
+.globl sym_1_6936
+sym_1_6936: la $2, sym_1_6936
+.globl sym_1_6937
+sym_1_6937: la $2, sym_1_6937
+.globl sym_1_6938
+sym_1_6938: la $2, sym_1_6938
+.globl sym_1_6939
+sym_1_6939: la $2, sym_1_6939
+.globl sym_1_6940
+sym_1_6940: la $2, sym_1_6940
+.globl sym_1_6941
+sym_1_6941: la $2, sym_1_6941
+.globl sym_1_6942
+sym_1_6942: la $2, sym_1_6942
+.globl sym_1_6943
+sym_1_6943: la $2, sym_1_6943
+.globl sym_1_6944
+sym_1_6944: la $2, sym_1_6944
+.globl sym_1_6945
+sym_1_6945: la $2, sym_1_6945
+.globl sym_1_6946
+sym_1_6946: la $2, sym_1_6946
+.globl sym_1_6947
+sym_1_6947: la $2, sym_1_6947
+.globl sym_1_6948
+sym_1_6948: la $2, sym_1_6948
+.globl sym_1_6949
+sym_1_6949: la $2, sym_1_6949
+.globl sym_1_6950
+sym_1_6950: la $2, sym_1_6950
+.globl sym_1_6951
+sym_1_6951: la $2, sym_1_6951
+.globl sym_1_6952
+sym_1_6952: la $2, sym_1_6952
+.globl sym_1_6953
+sym_1_6953: la $2, sym_1_6953
+.globl sym_1_6954
+sym_1_6954: la $2, sym_1_6954
+.globl sym_1_6955
+sym_1_6955: la $2, sym_1_6955
+.globl sym_1_6956
+sym_1_6956: la $2, sym_1_6956
+.globl sym_1_6957
+sym_1_6957: la $2, sym_1_6957
+.globl sym_1_6958
+sym_1_6958: la $2, sym_1_6958
+.globl sym_1_6959
+sym_1_6959: la $2, sym_1_6959
+.globl sym_1_6960
+sym_1_6960: la $2, sym_1_6960
+.globl sym_1_6961
+sym_1_6961: la $2, sym_1_6961
+.globl sym_1_6962
+sym_1_6962: la $2, sym_1_6962
+.globl sym_1_6963
+sym_1_6963: la $2, sym_1_6963
+.globl sym_1_6964
+sym_1_6964: la $2, sym_1_6964
+.globl sym_1_6965
+sym_1_6965: la $2, sym_1_6965
+.globl sym_1_6966
+sym_1_6966: la $2, sym_1_6966
+.globl sym_1_6967
+sym_1_6967: la $2, sym_1_6967
+.globl sym_1_6968
+sym_1_6968: la $2, sym_1_6968
+.globl sym_1_6969
+sym_1_6969: la $2, sym_1_6969
+.globl sym_1_6970
+sym_1_6970: la $2, sym_1_6970
+.globl sym_1_6971
+sym_1_6971: la $2, sym_1_6971
+.globl sym_1_6972
+sym_1_6972: la $2, sym_1_6972
+.globl sym_1_6973
+sym_1_6973: la $2, sym_1_6973
+.globl sym_1_6974
+sym_1_6974: la $2, sym_1_6974
+.globl sym_1_6975
+sym_1_6975: la $2, sym_1_6975
+.globl sym_1_6976
+sym_1_6976: la $2, sym_1_6976
+.globl sym_1_6977
+sym_1_6977: la $2, sym_1_6977
+.globl sym_1_6978
+sym_1_6978: la $2, sym_1_6978
+.globl sym_1_6979
+sym_1_6979: la $2, sym_1_6979
+.globl sym_1_6980
+sym_1_6980: la $2, sym_1_6980
+.globl sym_1_6981
+sym_1_6981: la $2, sym_1_6981
+.globl sym_1_6982
+sym_1_6982: la $2, sym_1_6982
+.globl sym_1_6983
+sym_1_6983: la $2, sym_1_6983
+.globl sym_1_6984
+sym_1_6984: la $2, sym_1_6984
+.globl sym_1_6985
+sym_1_6985: la $2, sym_1_6985
+.globl sym_1_6986
+sym_1_6986: la $2, sym_1_6986
+.globl sym_1_6987
+sym_1_6987: la $2, sym_1_6987
+.globl sym_1_6988
+sym_1_6988: la $2, sym_1_6988
+.globl sym_1_6989
+sym_1_6989: la $2, sym_1_6989
+.globl sym_1_6990
+sym_1_6990: la $2, sym_1_6990
+.globl sym_1_6991
+sym_1_6991: la $2, sym_1_6991
+.globl sym_1_6992
+sym_1_6992: la $2, sym_1_6992
+.globl sym_1_6993
+sym_1_6993: la $2, sym_1_6993
+.globl sym_1_6994
+sym_1_6994: la $2, sym_1_6994
+.globl sym_1_6995
+sym_1_6995: la $2, sym_1_6995
+.globl sym_1_6996
+sym_1_6996: la $2, sym_1_6996
+.globl sym_1_6997
+sym_1_6997: la $2, sym_1_6997
+.globl sym_1_6998
+sym_1_6998: la $2, sym_1_6998
+.globl sym_1_6999
+sym_1_6999: la $2, sym_1_6999
+.globl sym_1_7000
+sym_1_7000: la $2, sym_1_7000
+.globl sym_1_7001
+sym_1_7001: la $2, sym_1_7001
+.globl sym_1_7002
+sym_1_7002: la $2, sym_1_7002
+.globl sym_1_7003
+sym_1_7003: la $2, sym_1_7003
+.globl sym_1_7004
+sym_1_7004: la $2, sym_1_7004
+.globl sym_1_7005
+sym_1_7005: la $2, sym_1_7005
+.globl sym_1_7006
+sym_1_7006: la $2, sym_1_7006
+.globl sym_1_7007
+sym_1_7007: la $2, sym_1_7007
+.globl sym_1_7008
+sym_1_7008: la $2, sym_1_7008
+.globl sym_1_7009
+sym_1_7009: la $2, sym_1_7009
+.globl sym_1_7010
+sym_1_7010: la $2, sym_1_7010
+.globl sym_1_7011
+sym_1_7011: la $2, sym_1_7011
+.globl sym_1_7012
+sym_1_7012: la $2, sym_1_7012
+.globl sym_1_7013
+sym_1_7013: la $2, sym_1_7013
+.globl sym_1_7014
+sym_1_7014: la $2, sym_1_7014
+.globl sym_1_7015
+sym_1_7015: la $2, sym_1_7015
+.globl sym_1_7016
+sym_1_7016: la $2, sym_1_7016
+.globl sym_1_7017
+sym_1_7017: la $2, sym_1_7017
+.globl sym_1_7018
+sym_1_7018: la $2, sym_1_7018
+.globl sym_1_7019
+sym_1_7019: la $2, sym_1_7019
+.globl sym_1_7020
+sym_1_7020: la $2, sym_1_7020
+.globl sym_1_7021
+sym_1_7021: la $2, sym_1_7021
+.globl sym_1_7022
+sym_1_7022: la $2, sym_1_7022
+.globl sym_1_7023
+sym_1_7023: la $2, sym_1_7023
+.globl sym_1_7024
+sym_1_7024: la $2, sym_1_7024
+.globl sym_1_7025
+sym_1_7025: la $2, sym_1_7025
+.globl sym_1_7026
+sym_1_7026: la $2, sym_1_7026
+.globl sym_1_7027
+sym_1_7027: la $2, sym_1_7027
+.globl sym_1_7028
+sym_1_7028: la $2, sym_1_7028
+.globl sym_1_7029
+sym_1_7029: la $2, sym_1_7029
+.globl sym_1_7030
+sym_1_7030: la $2, sym_1_7030
+.globl sym_1_7031
+sym_1_7031: la $2, sym_1_7031
+.globl sym_1_7032
+sym_1_7032: la $2, sym_1_7032
+.globl sym_1_7033
+sym_1_7033: la $2, sym_1_7033
+.globl sym_1_7034
+sym_1_7034: la $2, sym_1_7034
+.globl sym_1_7035
+sym_1_7035: la $2, sym_1_7035
+.globl sym_1_7036
+sym_1_7036: la $2, sym_1_7036
+.globl sym_1_7037
+sym_1_7037: la $2, sym_1_7037
+.globl sym_1_7038
+sym_1_7038: la $2, sym_1_7038
+.globl sym_1_7039
+sym_1_7039: la $2, sym_1_7039
+.globl sym_1_7040
+sym_1_7040: la $2, sym_1_7040
+.globl sym_1_7041
+sym_1_7041: la $2, sym_1_7041
+.globl sym_1_7042
+sym_1_7042: la $2, sym_1_7042
+.globl sym_1_7043
+sym_1_7043: la $2, sym_1_7043
+.globl sym_1_7044
+sym_1_7044: la $2, sym_1_7044
+.globl sym_1_7045
+sym_1_7045: la $2, sym_1_7045
+.globl sym_1_7046
+sym_1_7046: la $2, sym_1_7046
+.globl sym_1_7047
+sym_1_7047: la $2, sym_1_7047
+.globl sym_1_7048
+sym_1_7048: la $2, sym_1_7048
+.globl sym_1_7049
+sym_1_7049: la $2, sym_1_7049
+.globl sym_1_7050
+sym_1_7050: la $2, sym_1_7050
+.globl sym_1_7051
+sym_1_7051: la $2, sym_1_7051
+.globl sym_1_7052
+sym_1_7052: la $2, sym_1_7052
+.globl sym_1_7053
+sym_1_7053: la $2, sym_1_7053
+.globl sym_1_7054
+sym_1_7054: la $2, sym_1_7054
+.globl sym_1_7055
+sym_1_7055: la $2, sym_1_7055
+.globl sym_1_7056
+sym_1_7056: la $2, sym_1_7056
+.globl sym_1_7057
+sym_1_7057: la $2, sym_1_7057
+.globl sym_1_7058
+sym_1_7058: la $2, sym_1_7058
+.globl sym_1_7059
+sym_1_7059: la $2, sym_1_7059
+.globl sym_1_7060
+sym_1_7060: la $2, sym_1_7060
+.globl sym_1_7061
+sym_1_7061: la $2, sym_1_7061
+.globl sym_1_7062
+sym_1_7062: la $2, sym_1_7062
+.globl sym_1_7063
+sym_1_7063: la $2, sym_1_7063
+.globl sym_1_7064
+sym_1_7064: la $2, sym_1_7064
+.globl sym_1_7065
+sym_1_7065: la $2, sym_1_7065
+.globl sym_1_7066
+sym_1_7066: la $2, sym_1_7066
+.globl sym_1_7067
+sym_1_7067: la $2, sym_1_7067
+.globl sym_1_7068
+sym_1_7068: la $2, sym_1_7068
+.globl sym_1_7069
+sym_1_7069: la $2, sym_1_7069
+.globl sym_1_7070
+sym_1_7070: la $2, sym_1_7070
+.globl sym_1_7071
+sym_1_7071: la $2, sym_1_7071
+.globl sym_1_7072
+sym_1_7072: la $2, sym_1_7072
+.globl sym_1_7073
+sym_1_7073: la $2, sym_1_7073
+.globl sym_1_7074
+sym_1_7074: la $2, sym_1_7074
+.globl sym_1_7075
+sym_1_7075: la $2, sym_1_7075
+.globl sym_1_7076
+sym_1_7076: la $2, sym_1_7076
+.globl sym_1_7077
+sym_1_7077: la $2, sym_1_7077
+.globl sym_1_7078
+sym_1_7078: la $2, sym_1_7078
+.globl sym_1_7079
+sym_1_7079: la $2, sym_1_7079
+.globl sym_1_7080
+sym_1_7080: la $2, sym_1_7080
+.globl sym_1_7081
+sym_1_7081: la $2, sym_1_7081
+.globl sym_1_7082
+sym_1_7082: la $2, sym_1_7082
+.globl sym_1_7083
+sym_1_7083: la $2, sym_1_7083
+.globl sym_1_7084
+sym_1_7084: la $2, sym_1_7084
+.globl sym_1_7085
+sym_1_7085: la $2, sym_1_7085
+.globl sym_1_7086
+sym_1_7086: la $2, sym_1_7086
+.globl sym_1_7087
+sym_1_7087: la $2, sym_1_7087
+.globl sym_1_7088
+sym_1_7088: la $2, sym_1_7088
+.globl sym_1_7089
+sym_1_7089: la $2, sym_1_7089
+.globl sym_1_7090
+sym_1_7090: la $2, sym_1_7090
+.globl sym_1_7091
+sym_1_7091: la $2, sym_1_7091
+.globl sym_1_7092
+sym_1_7092: la $2, sym_1_7092
+.globl sym_1_7093
+sym_1_7093: la $2, sym_1_7093
+.globl sym_1_7094
+sym_1_7094: la $2, sym_1_7094
+.globl sym_1_7095
+sym_1_7095: la $2, sym_1_7095
+.globl sym_1_7096
+sym_1_7096: la $2, sym_1_7096
+.globl sym_1_7097
+sym_1_7097: la $2, sym_1_7097
+.globl sym_1_7098
+sym_1_7098: la $2, sym_1_7098
+.globl sym_1_7099
+sym_1_7099: la $2, sym_1_7099
+.globl sym_1_7100
+sym_1_7100: la $2, sym_1_7100
+.globl sym_1_7101
+sym_1_7101: la $2, sym_1_7101
+.globl sym_1_7102
+sym_1_7102: la $2, sym_1_7102
+.globl sym_1_7103
+sym_1_7103: la $2, sym_1_7103
+.globl sym_1_7104
+sym_1_7104: la $2, sym_1_7104
+.globl sym_1_7105
+sym_1_7105: la $2, sym_1_7105
+.globl sym_1_7106
+sym_1_7106: la $2, sym_1_7106
+.globl sym_1_7107
+sym_1_7107: la $2, sym_1_7107
+.globl sym_1_7108
+sym_1_7108: la $2, sym_1_7108
+.globl sym_1_7109
+sym_1_7109: la $2, sym_1_7109
+.globl sym_1_7110
+sym_1_7110: la $2, sym_1_7110
+.globl sym_1_7111
+sym_1_7111: la $2, sym_1_7111
+.globl sym_1_7112
+sym_1_7112: la $2, sym_1_7112
+.globl sym_1_7113
+sym_1_7113: la $2, sym_1_7113
+.globl sym_1_7114
+sym_1_7114: la $2, sym_1_7114
+.globl sym_1_7115
+sym_1_7115: la $2, sym_1_7115
+.globl sym_1_7116
+sym_1_7116: la $2, sym_1_7116
+.globl sym_1_7117
+sym_1_7117: la $2, sym_1_7117
+.globl sym_1_7118
+sym_1_7118: la $2, sym_1_7118
+.globl sym_1_7119
+sym_1_7119: la $2, sym_1_7119
+.globl sym_1_7120
+sym_1_7120: la $2, sym_1_7120
+.globl sym_1_7121
+sym_1_7121: la $2, sym_1_7121
+.globl sym_1_7122
+sym_1_7122: la $2, sym_1_7122
+.globl sym_1_7123
+sym_1_7123: la $2, sym_1_7123
+.globl sym_1_7124
+sym_1_7124: la $2, sym_1_7124
+.globl sym_1_7125
+sym_1_7125: la $2, sym_1_7125
+.globl sym_1_7126
+sym_1_7126: la $2, sym_1_7126
+.globl sym_1_7127
+sym_1_7127: la $2, sym_1_7127
+.globl sym_1_7128
+sym_1_7128: la $2, sym_1_7128
+.globl sym_1_7129
+sym_1_7129: la $2, sym_1_7129
+.globl sym_1_7130
+sym_1_7130: la $2, sym_1_7130
+.globl sym_1_7131
+sym_1_7131: la $2, sym_1_7131
+.globl sym_1_7132
+sym_1_7132: la $2, sym_1_7132
+.globl sym_1_7133
+sym_1_7133: la $2, sym_1_7133
+.globl sym_1_7134
+sym_1_7134: la $2, sym_1_7134
+.globl sym_1_7135
+sym_1_7135: la $2, sym_1_7135
+.globl sym_1_7136
+sym_1_7136: la $2, sym_1_7136
+.globl sym_1_7137
+sym_1_7137: la $2, sym_1_7137
+.globl sym_1_7138
+sym_1_7138: la $2, sym_1_7138
+.globl sym_1_7139
+sym_1_7139: la $2, sym_1_7139
+.globl sym_1_7140
+sym_1_7140: la $2, sym_1_7140
+.globl sym_1_7141
+sym_1_7141: la $2, sym_1_7141
+.globl sym_1_7142
+sym_1_7142: la $2, sym_1_7142
+.globl sym_1_7143
+sym_1_7143: la $2, sym_1_7143
+.globl sym_1_7144
+sym_1_7144: la $2, sym_1_7144
+.globl sym_1_7145
+sym_1_7145: la $2, sym_1_7145
+.globl sym_1_7146
+sym_1_7146: la $2, sym_1_7146
+.globl sym_1_7147
+sym_1_7147: la $2, sym_1_7147
+.globl sym_1_7148
+sym_1_7148: la $2, sym_1_7148
+.globl sym_1_7149
+sym_1_7149: la $2, sym_1_7149
+.globl sym_1_7150
+sym_1_7150: la $2, sym_1_7150
+.globl sym_1_7151
+sym_1_7151: la $2, sym_1_7151
+.globl sym_1_7152
+sym_1_7152: la $2, sym_1_7152
+.globl sym_1_7153
+sym_1_7153: la $2, sym_1_7153
+.globl sym_1_7154
+sym_1_7154: la $2, sym_1_7154
+.globl sym_1_7155
+sym_1_7155: la $2, sym_1_7155
+.globl sym_1_7156
+sym_1_7156: la $2, sym_1_7156
+.globl sym_1_7157
+sym_1_7157: la $2, sym_1_7157
+.globl sym_1_7158
+sym_1_7158: la $2, sym_1_7158
+.globl sym_1_7159
+sym_1_7159: la $2, sym_1_7159
+.globl sym_1_7160
+sym_1_7160: la $2, sym_1_7160
+.globl sym_1_7161
+sym_1_7161: la $2, sym_1_7161
+.globl sym_1_7162
+sym_1_7162: la $2, sym_1_7162
+.globl sym_1_7163
+sym_1_7163: la $2, sym_1_7163
+.globl sym_1_7164
+sym_1_7164: la $2, sym_1_7164
+.globl sym_1_7165
+sym_1_7165: la $2, sym_1_7165
+.globl sym_1_7166
+sym_1_7166: la $2, sym_1_7166
+.globl sym_1_7167
+sym_1_7167: la $2, sym_1_7167
+.globl sym_1_7168
+sym_1_7168: la $2, sym_1_7168
+.globl sym_1_7169
+sym_1_7169: la $2, sym_1_7169
+.globl sym_1_7170
+sym_1_7170: la $2, sym_1_7170
+.globl sym_1_7171
+sym_1_7171: la $2, sym_1_7171
+.globl sym_1_7172
+sym_1_7172: la $2, sym_1_7172
+.globl sym_1_7173
+sym_1_7173: la $2, sym_1_7173
+.globl sym_1_7174
+sym_1_7174: la $2, sym_1_7174
+.globl sym_1_7175
+sym_1_7175: la $2, sym_1_7175
+.globl sym_1_7176
+sym_1_7176: la $2, sym_1_7176
+.globl sym_1_7177
+sym_1_7177: la $2, sym_1_7177
+.globl sym_1_7178
+sym_1_7178: la $2, sym_1_7178
+.globl sym_1_7179
+sym_1_7179: la $2, sym_1_7179
+.globl sym_1_7180
+sym_1_7180: la $2, sym_1_7180
+.globl sym_1_7181
+sym_1_7181: la $2, sym_1_7181
+.globl sym_1_7182
+sym_1_7182: la $2, sym_1_7182
+.globl sym_1_7183
+sym_1_7183: la $2, sym_1_7183
+.globl sym_1_7184
+sym_1_7184: la $2, sym_1_7184
+.globl sym_1_7185
+sym_1_7185: la $2, sym_1_7185
+.globl sym_1_7186
+sym_1_7186: la $2, sym_1_7186
+.globl sym_1_7187
+sym_1_7187: la $2, sym_1_7187
+.globl sym_1_7188
+sym_1_7188: la $2, sym_1_7188
+.globl sym_1_7189
+sym_1_7189: la $2, sym_1_7189
+.globl sym_1_7190
+sym_1_7190: la $2, sym_1_7190
+.globl sym_1_7191
+sym_1_7191: la $2, sym_1_7191
+.globl sym_1_7192
+sym_1_7192: la $2, sym_1_7192
+.globl sym_1_7193
+sym_1_7193: la $2, sym_1_7193
+.globl sym_1_7194
+sym_1_7194: la $2, sym_1_7194
+.globl sym_1_7195
+sym_1_7195: la $2, sym_1_7195
+.globl sym_1_7196
+sym_1_7196: la $2, sym_1_7196
+.globl sym_1_7197
+sym_1_7197: la $2, sym_1_7197
+.globl sym_1_7198
+sym_1_7198: la $2, sym_1_7198
+.globl sym_1_7199
+sym_1_7199: la $2, sym_1_7199
+.globl sym_1_7200
+sym_1_7200: la $2, sym_1_7200
+.globl sym_1_7201
+sym_1_7201: la $2, sym_1_7201
+.globl sym_1_7202
+sym_1_7202: la $2, sym_1_7202
+.globl sym_1_7203
+sym_1_7203: la $2, sym_1_7203
+.globl sym_1_7204
+sym_1_7204: la $2, sym_1_7204
+.globl sym_1_7205
+sym_1_7205: la $2, sym_1_7205
+.globl sym_1_7206
+sym_1_7206: la $2, sym_1_7206
+.globl sym_1_7207
+sym_1_7207: la $2, sym_1_7207
+.globl sym_1_7208
+sym_1_7208: la $2, sym_1_7208
+.globl sym_1_7209
+sym_1_7209: la $2, sym_1_7209
+.globl sym_1_7210
+sym_1_7210: la $2, sym_1_7210
+.globl sym_1_7211
+sym_1_7211: la $2, sym_1_7211
+.globl sym_1_7212
+sym_1_7212: la $2, sym_1_7212
+.globl sym_1_7213
+sym_1_7213: la $2, sym_1_7213
+.globl sym_1_7214
+sym_1_7214: la $2, sym_1_7214
+.globl sym_1_7215
+sym_1_7215: la $2, sym_1_7215
+.globl sym_1_7216
+sym_1_7216: la $2, sym_1_7216
+.globl sym_1_7217
+sym_1_7217: la $2, sym_1_7217
+.globl sym_1_7218
+sym_1_7218: la $2, sym_1_7218
+.globl sym_1_7219
+sym_1_7219: la $2, sym_1_7219
+.globl sym_1_7220
+sym_1_7220: la $2, sym_1_7220
+.globl sym_1_7221
+sym_1_7221: la $2, sym_1_7221
+.globl sym_1_7222
+sym_1_7222: la $2, sym_1_7222
+.globl sym_1_7223
+sym_1_7223: la $2, sym_1_7223
+.globl sym_1_7224
+sym_1_7224: la $2, sym_1_7224
+.globl sym_1_7225
+sym_1_7225: la $2, sym_1_7225
+.globl sym_1_7226
+sym_1_7226: la $2, sym_1_7226
+.globl sym_1_7227
+sym_1_7227: la $2, sym_1_7227
+.globl sym_1_7228
+sym_1_7228: la $2, sym_1_7228
+.globl sym_1_7229
+sym_1_7229: la $2, sym_1_7229
+.globl sym_1_7230
+sym_1_7230: la $2, sym_1_7230
+.globl sym_1_7231
+sym_1_7231: la $2, sym_1_7231
+.globl sym_1_7232
+sym_1_7232: la $2, sym_1_7232
+.globl sym_1_7233
+sym_1_7233: la $2, sym_1_7233
+.globl sym_1_7234
+sym_1_7234: la $2, sym_1_7234
+.globl sym_1_7235
+sym_1_7235: la $2, sym_1_7235
+.globl sym_1_7236
+sym_1_7236: la $2, sym_1_7236
+.globl sym_1_7237
+sym_1_7237: la $2, sym_1_7237
+.globl sym_1_7238
+sym_1_7238: la $2, sym_1_7238
+.globl sym_1_7239
+sym_1_7239: la $2, sym_1_7239
+.globl sym_1_7240
+sym_1_7240: la $2, sym_1_7240
+.globl sym_1_7241
+sym_1_7241: la $2, sym_1_7241
+.globl sym_1_7242
+sym_1_7242: la $2, sym_1_7242
+.globl sym_1_7243
+sym_1_7243: la $2, sym_1_7243
+.globl sym_1_7244
+sym_1_7244: la $2, sym_1_7244
+.globl sym_1_7245
+sym_1_7245: la $2, sym_1_7245
+.globl sym_1_7246
+sym_1_7246: la $2, sym_1_7246
+.globl sym_1_7247
+sym_1_7247: la $2, sym_1_7247
+.globl sym_1_7248
+sym_1_7248: la $2, sym_1_7248
+.globl sym_1_7249
+sym_1_7249: la $2, sym_1_7249
+.globl sym_1_7250
+sym_1_7250: la $2, sym_1_7250
+.globl sym_1_7251
+sym_1_7251: la $2, sym_1_7251
+.globl sym_1_7252
+sym_1_7252: la $2, sym_1_7252
+.globl sym_1_7253
+sym_1_7253: la $2, sym_1_7253
+.globl sym_1_7254
+sym_1_7254: la $2, sym_1_7254
+.globl sym_1_7255
+sym_1_7255: la $2, sym_1_7255
+.globl sym_1_7256
+sym_1_7256: la $2, sym_1_7256
+.globl sym_1_7257
+sym_1_7257: la $2, sym_1_7257
+.globl sym_1_7258
+sym_1_7258: la $2, sym_1_7258
+.globl sym_1_7259
+sym_1_7259: la $2, sym_1_7259
+.globl sym_1_7260
+sym_1_7260: la $2, sym_1_7260
+.globl sym_1_7261
+sym_1_7261: la $2, sym_1_7261
+.globl sym_1_7262
+sym_1_7262: la $2, sym_1_7262
+.globl sym_1_7263
+sym_1_7263: la $2, sym_1_7263
+.globl sym_1_7264
+sym_1_7264: la $2, sym_1_7264
+.globl sym_1_7265
+sym_1_7265: la $2, sym_1_7265
+.globl sym_1_7266
+sym_1_7266: la $2, sym_1_7266
+.globl sym_1_7267
+sym_1_7267: la $2, sym_1_7267
+.globl sym_1_7268
+sym_1_7268: la $2, sym_1_7268
+.globl sym_1_7269
+sym_1_7269: la $2, sym_1_7269
+.globl sym_1_7270
+sym_1_7270: la $2, sym_1_7270
+.globl sym_1_7271
+sym_1_7271: la $2, sym_1_7271
+.globl sym_1_7272
+sym_1_7272: la $2, sym_1_7272
+.globl sym_1_7273
+sym_1_7273: la $2, sym_1_7273
+.globl sym_1_7274
+sym_1_7274: la $2, sym_1_7274
+.globl sym_1_7275
+sym_1_7275: la $2, sym_1_7275
+.globl sym_1_7276
+sym_1_7276: la $2, sym_1_7276
+.globl sym_1_7277
+sym_1_7277: la $2, sym_1_7277
+.globl sym_1_7278
+sym_1_7278: la $2, sym_1_7278
+.globl sym_1_7279
+sym_1_7279: la $2, sym_1_7279
+.globl sym_1_7280
+sym_1_7280: la $2, sym_1_7280
+.globl sym_1_7281
+sym_1_7281: la $2, sym_1_7281
+.globl sym_1_7282
+sym_1_7282: la $2, sym_1_7282
+.globl sym_1_7283
+sym_1_7283: la $2, sym_1_7283
+.globl sym_1_7284
+sym_1_7284: la $2, sym_1_7284
+.globl sym_1_7285
+sym_1_7285: la $2, sym_1_7285
+.globl sym_1_7286
+sym_1_7286: la $2, sym_1_7286
+.globl sym_1_7287
+sym_1_7287: la $2, sym_1_7287
+.globl sym_1_7288
+sym_1_7288: la $2, sym_1_7288
+.globl sym_1_7289
+sym_1_7289: la $2, sym_1_7289
+.globl sym_1_7290
+sym_1_7290: la $2, sym_1_7290
+.globl sym_1_7291
+sym_1_7291: la $2, sym_1_7291
+.globl sym_1_7292
+sym_1_7292: la $2, sym_1_7292
+.globl sym_1_7293
+sym_1_7293: la $2, sym_1_7293
+.globl sym_1_7294
+sym_1_7294: la $2, sym_1_7294
+.globl sym_1_7295
+sym_1_7295: la $2, sym_1_7295
+.globl sym_1_7296
+sym_1_7296: la $2, sym_1_7296
+.globl sym_1_7297
+sym_1_7297: la $2, sym_1_7297
+.globl sym_1_7298
+sym_1_7298: la $2, sym_1_7298
+.globl sym_1_7299
+sym_1_7299: la $2, sym_1_7299
+.globl sym_1_7300
+sym_1_7300: la $2, sym_1_7300
+.globl sym_1_7301
+sym_1_7301: la $2, sym_1_7301
+.globl sym_1_7302
+sym_1_7302: la $2, sym_1_7302
+.globl sym_1_7303
+sym_1_7303: la $2, sym_1_7303
+.globl sym_1_7304
+sym_1_7304: la $2, sym_1_7304
+.globl sym_1_7305
+sym_1_7305: la $2, sym_1_7305
+.globl sym_1_7306
+sym_1_7306: la $2, sym_1_7306
+.globl sym_1_7307
+sym_1_7307: la $2, sym_1_7307
+.globl sym_1_7308
+sym_1_7308: la $2, sym_1_7308
+.globl sym_1_7309
+sym_1_7309: la $2, sym_1_7309
+.globl sym_1_7310
+sym_1_7310: la $2, sym_1_7310
+.globl sym_1_7311
+sym_1_7311: la $2, sym_1_7311
+.globl sym_1_7312
+sym_1_7312: la $2, sym_1_7312
+.globl sym_1_7313
+sym_1_7313: la $2, sym_1_7313
+.globl sym_1_7314
+sym_1_7314: la $2, sym_1_7314
+.globl sym_1_7315
+sym_1_7315: la $2, sym_1_7315
+.globl sym_1_7316
+sym_1_7316: la $2, sym_1_7316
+.globl sym_1_7317
+sym_1_7317: la $2, sym_1_7317
+.globl sym_1_7318
+sym_1_7318: la $2, sym_1_7318
+.globl sym_1_7319
+sym_1_7319: la $2, sym_1_7319
+.globl sym_1_7320
+sym_1_7320: la $2, sym_1_7320
+.globl sym_1_7321
+sym_1_7321: la $2, sym_1_7321
+.globl sym_1_7322
+sym_1_7322: la $2, sym_1_7322
+.globl sym_1_7323
+sym_1_7323: la $2, sym_1_7323
+.globl sym_1_7324
+sym_1_7324: la $2, sym_1_7324
+.globl sym_1_7325
+sym_1_7325: la $2, sym_1_7325
+.globl sym_1_7326
+sym_1_7326: la $2, sym_1_7326
+.globl sym_1_7327
+sym_1_7327: la $2, sym_1_7327
+.globl sym_1_7328
+sym_1_7328: la $2, sym_1_7328
+.globl sym_1_7329
+sym_1_7329: la $2, sym_1_7329
+.globl sym_1_7330
+sym_1_7330: la $2, sym_1_7330
+.globl sym_1_7331
+sym_1_7331: la $2, sym_1_7331
+.globl sym_1_7332
+sym_1_7332: la $2, sym_1_7332
+.globl sym_1_7333
+sym_1_7333: la $2, sym_1_7333
+.globl sym_1_7334
+sym_1_7334: la $2, sym_1_7334
+.globl sym_1_7335
+sym_1_7335: la $2, sym_1_7335
+.globl sym_1_7336
+sym_1_7336: la $2, sym_1_7336
+.globl sym_1_7337
+sym_1_7337: la $2, sym_1_7337
+.globl sym_1_7338
+sym_1_7338: la $2, sym_1_7338
+.globl sym_1_7339
+sym_1_7339: la $2, sym_1_7339
+.globl sym_1_7340
+sym_1_7340: la $2, sym_1_7340
+.globl sym_1_7341
+sym_1_7341: la $2, sym_1_7341
+.globl sym_1_7342
+sym_1_7342: la $2, sym_1_7342
+.globl sym_1_7343
+sym_1_7343: la $2, sym_1_7343
+.globl sym_1_7344
+sym_1_7344: la $2, sym_1_7344
+.globl sym_1_7345
+sym_1_7345: la $2, sym_1_7345
+.globl sym_1_7346
+sym_1_7346: la $2, sym_1_7346
+.globl sym_1_7347
+sym_1_7347: la $2, sym_1_7347
+.globl sym_1_7348
+sym_1_7348: la $2, sym_1_7348
+.globl sym_1_7349
+sym_1_7349: la $2, sym_1_7349
+.globl sym_1_7350
+sym_1_7350: la $2, sym_1_7350
+.globl sym_1_7351
+sym_1_7351: la $2, sym_1_7351
+.globl sym_1_7352
+sym_1_7352: la $2, sym_1_7352
+.globl sym_1_7353
+sym_1_7353: la $2, sym_1_7353
+.globl sym_1_7354
+sym_1_7354: la $2, sym_1_7354
+.globl sym_1_7355
+sym_1_7355: la $2, sym_1_7355
+.globl sym_1_7356
+sym_1_7356: la $2, sym_1_7356
+.globl sym_1_7357
+sym_1_7357: la $2, sym_1_7357
+.globl sym_1_7358
+sym_1_7358: la $2, sym_1_7358
+.globl sym_1_7359
+sym_1_7359: la $2, sym_1_7359
+.globl sym_1_7360
+sym_1_7360: la $2, sym_1_7360
+.globl sym_1_7361
+sym_1_7361: la $2, sym_1_7361
+.globl sym_1_7362
+sym_1_7362: la $2, sym_1_7362
+.globl sym_1_7363
+sym_1_7363: la $2, sym_1_7363
+.globl sym_1_7364
+sym_1_7364: la $2, sym_1_7364
+.globl sym_1_7365
+sym_1_7365: la $2, sym_1_7365
+.globl sym_1_7366
+sym_1_7366: la $2, sym_1_7366
+.globl sym_1_7367
+sym_1_7367: la $2, sym_1_7367
+.globl sym_1_7368
+sym_1_7368: la $2, sym_1_7368
+.globl sym_1_7369
+sym_1_7369: la $2, sym_1_7369
+.globl sym_1_7370
+sym_1_7370: la $2, sym_1_7370
+.globl sym_1_7371
+sym_1_7371: la $2, sym_1_7371
+.globl sym_1_7372
+sym_1_7372: la $2, sym_1_7372
+.globl sym_1_7373
+sym_1_7373: la $2, sym_1_7373
+.globl sym_1_7374
+sym_1_7374: la $2, sym_1_7374
+.globl sym_1_7375
+sym_1_7375: la $2, sym_1_7375
+.globl sym_1_7376
+sym_1_7376: la $2, sym_1_7376
+.globl sym_1_7377
+sym_1_7377: la $2, sym_1_7377
+.globl sym_1_7378
+sym_1_7378: la $2, sym_1_7378
+.globl sym_1_7379
+sym_1_7379: la $2, sym_1_7379
+.globl sym_1_7380
+sym_1_7380: la $2, sym_1_7380
+.globl sym_1_7381
+sym_1_7381: la $2, sym_1_7381
+.globl sym_1_7382
+sym_1_7382: la $2, sym_1_7382
+.globl sym_1_7383
+sym_1_7383: la $2, sym_1_7383
+.globl sym_1_7384
+sym_1_7384: la $2, sym_1_7384
+.globl sym_1_7385
+sym_1_7385: la $2, sym_1_7385
+.globl sym_1_7386
+sym_1_7386: la $2, sym_1_7386
+.globl sym_1_7387
+sym_1_7387: la $2, sym_1_7387
+.globl sym_1_7388
+sym_1_7388: la $2, sym_1_7388
+.globl sym_1_7389
+sym_1_7389: la $2, sym_1_7389
+.globl sym_1_7390
+sym_1_7390: la $2, sym_1_7390
+.globl sym_1_7391
+sym_1_7391: la $2, sym_1_7391
+.globl sym_1_7392
+sym_1_7392: la $2, sym_1_7392
+.globl sym_1_7393
+sym_1_7393: la $2, sym_1_7393
+.globl sym_1_7394
+sym_1_7394: la $2, sym_1_7394
+.globl sym_1_7395
+sym_1_7395: la $2, sym_1_7395
+.globl sym_1_7396
+sym_1_7396: la $2, sym_1_7396
+.globl sym_1_7397
+sym_1_7397: la $2, sym_1_7397
+.globl sym_1_7398
+sym_1_7398: la $2, sym_1_7398
+.globl sym_1_7399
+sym_1_7399: la $2, sym_1_7399
+.globl sym_1_7400
+sym_1_7400: la $2, sym_1_7400
+.globl sym_1_7401
+sym_1_7401: la $2, sym_1_7401
+.globl sym_1_7402
+sym_1_7402: la $2, sym_1_7402
+.globl sym_1_7403
+sym_1_7403: la $2, sym_1_7403
+.globl sym_1_7404
+sym_1_7404: la $2, sym_1_7404
+.globl sym_1_7405
+sym_1_7405: la $2, sym_1_7405
+.globl sym_1_7406
+sym_1_7406: la $2, sym_1_7406
+.globl sym_1_7407
+sym_1_7407: la $2, sym_1_7407
+.globl sym_1_7408
+sym_1_7408: la $2, sym_1_7408
+.globl sym_1_7409
+sym_1_7409: la $2, sym_1_7409
+.globl sym_1_7410
+sym_1_7410: la $2, sym_1_7410
+.globl sym_1_7411
+sym_1_7411: la $2, sym_1_7411
+.globl sym_1_7412
+sym_1_7412: la $2, sym_1_7412
+.globl sym_1_7413
+sym_1_7413: la $2, sym_1_7413
+.globl sym_1_7414
+sym_1_7414: la $2, sym_1_7414
+.globl sym_1_7415
+sym_1_7415: la $2, sym_1_7415
+.globl sym_1_7416
+sym_1_7416: la $2, sym_1_7416
+.globl sym_1_7417
+sym_1_7417: la $2, sym_1_7417
+.globl sym_1_7418
+sym_1_7418: la $2, sym_1_7418
+.globl sym_1_7419
+sym_1_7419: la $2, sym_1_7419
+.globl sym_1_7420
+sym_1_7420: la $2, sym_1_7420
+.globl sym_1_7421
+sym_1_7421: la $2, sym_1_7421
+.globl sym_1_7422
+sym_1_7422: la $2, sym_1_7422
+.globl sym_1_7423
+sym_1_7423: la $2, sym_1_7423
+.globl sym_1_7424
+sym_1_7424: la $2, sym_1_7424
+.globl sym_1_7425
+sym_1_7425: la $2, sym_1_7425
+.globl sym_1_7426
+sym_1_7426: la $2, sym_1_7426
+.globl sym_1_7427
+sym_1_7427: la $2, sym_1_7427
+.globl sym_1_7428
+sym_1_7428: la $2, sym_1_7428
+.globl sym_1_7429
+sym_1_7429: la $2, sym_1_7429
+.globl sym_1_7430
+sym_1_7430: la $2, sym_1_7430
+.globl sym_1_7431
+sym_1_7431: la $2, sym_1_7431
+.globl sym_1_7432
+sym_1_7432: la $2, sym_1_7432
+.globl sym_1_7433
+sym_1_7433: la $2, sym_1_7433
+.globl sym_1_7434
+sym_1_7434: la $2, sym_1_7434
+.globl sym_1_7435
+sym_1_7435: la $2, sym_1_7435
+.globl sym_1_7436
+sym_1_7436: la $2, sym_1_7436
+.globl sym_1_7437
+sym_1_7437: la $2, sym_1_7437
+.globl sym_1_7438
+sym_1_7438: la $2, sym_1_7438
+.globl sym_1_7439
+sym_1_7439: la $2, sym_1_7439
+.globl sym_1_7440
+sym_1_7440: la $2, sym_1_7440
+.globl sym_1_7441
+sym_1_7441: la $2, sym_1_7441
+.globl sym_1_7442
+sym_1_7442: la $2, sym_1_7442
+.globl sym_1_7443
+sym_1_7443: la $2, sym_1_7443
+.globl sym_1_7444
+sym_1_7444: la $2, sym_1_7444
+.globl sym_1_7445
+sym_1_7445: la $2, sym_1_7445
+.globl sym_1_7446
+sym_1_7446: la $2, sym_1_7446
+.globl sym_1_7447
+sym_1_7447: la $2, sym_1_7447
+.globl sym_1_7448
+sym_1_7448: la $2, sym_1_7448
+.globl sym_1_7449
+sym_1_7449: la $2, sym_1_7449
+.globl sym_1_7450
+sym_1_7450: la $2, sym_1_7450
+.globl sym_1_7451
+sym_1_7451: la $2, sym_1_7451
+.globl sym_1_7452
+sym_1_7452: la $2, sym_1_7452
+.globl sym_1_7453
+sym_1_7453: la $2, sym_1_7453
+.globl sym_1_7454
+sym_1_7454: la $2, sym_1_7454
+.globl sym_1_7455
+sym_1_7455: la $2, sym_1_7455
+.globl sym_1_7456
+sym_1_7456: la $2, sym_1_7456
+.globl sym_1_7457
+sym_1_7457: la $2, sym_1_7457
+.globl sym_1_7458
+sym_1_7458: la $2, sym_1_7458
+.globl sym_1_7459
+sym_1_7459: la $2, sym_1_7459
+.globl sym_1_7460
+sym_1_7460: la $2, sym_1_7460
+.globl sym_1_7461
+sym_1_7461: la $2, sym_1_7461
+.globl sym_1_7462
+sym_1_7462: la $2, sym_1_7462
+.globl sym_1_7463
+sym_1_7463: la $2, sym_1_7463
+.globl sym_1_7464
+sym_1_7464: la $2, sym_1_7464
+.globl sym_1_7465
+sym_1_7465: la $2, sym_1_7465
+.globl sym_1_7466
+sym_1_7466: la $2, sym_1_7466
+.globl sym_1_7467
+sym_1_7467: la $2, sym_1_7467
+.globl sym_1_7468
+sym_1_7468: la $2, sym_1_7468
+.globl sym_1_7469
+sym_1_7469: la $2, sym_1_7469
+.globl sym_1_7470
+sym_1_7470: la $2, sym_1_7470
+.globl sym_1_7471
+sym_1_7471: la $2, sym_1_7471
+.globl sym_1_7472
+sym_1_7472: la $2, sym_1_7472
+.globl sym_1_7473
+sym_1_7473: la $2, sym_1_7473
+.globl sym_1_7474
+sym_1_7474: la $2, sym_1_7474
+.globl sym_1_7475
+sym_1_7475: la $2, sym_1_7475
+.globl sym_1_7476
+sym_1_7476: la $2, sym_1_7476
+.globl sym_1_7477
+sym_1_7477: la $2, sym_1_7477
+.globl sym_1_7478
+sym_1_7478: la $2, sym_1_7478
+.globl sym_1_7479
+sym_1_7479: la $2, sym_1_7479
+.globl sym_1_7480
+sym_1_7480: la $2, sym_1_7480
+.globl sym_1_7481
+sym_1_7481: la $2, sym_1_7481
+.globl sym_1_7482
+sym_1_7482: la $2, sym_1_7482
+.globl sym_1_7483
+sym_1_7483: la $2, sym_1_7483
+.globl sym_1_7484
+sym_1_7484: la $2, sym_1_7484
+.globl sym_1_7485
+sym_1_7485: la $2, sym_1_7485
+.globl sym_1_7486
+sym_1_7486: la $2, sym_1_7486
+.globl sym_1_7487
+sym_1_7487: la $2, sym_1_7487
+.globl sym_1_7488
+sym_1_7488: la $2, sym_1_7488
+.globl sym_1_7489
+sym_1_7489: la $2, sym_1_7489
+.globl sym_1_7490
+sym_1_7490: la $2, sym_1_7490
+.globl sym_1_7491
+sym_1_7491: la $2, sym_1_7491
+.globl sym_1_7492
+sym_1_7492: la $2, sym_1_7492
+.globl sym_1_7493
+sym_1_7493: la $2, sym_1_7493
+.globl sym_1_7494
+sym_1_7494: la $2, sym_1_7494
+.globl sym_1_7495
+sym_1_7495: la $2, sym_1_7495
+.globl sym_1_7496
+sym_1_7496: la $2, sym_1_7496
+.globl sym_1_7497
+sym_1_7497: la $2, sym_1_7497
+.globl sym_1_7498
+sym_1_7498: la $2, sym_1_7498
+.globl sym_1_7499
+sym_1_7499: la $2, sym_1_7499
+.globl sym_1_7500
+sym_1_7500: la $2, sym_1_7500
+.globl sym_1_7501
+sym_1_7501: la $2, sym_1_7501
+.globl sym_1_7502
+sym_1_7502: la $2, sym_1_7502
+.globl sym_1_7503
+sym_1_7503: la $2, sym_1_7503
+.globl sym_1_7504
+sym_1_7504: la $2, sym_1_7504
+.globl sym_1_7505
+sym_1_7505: la $2, sym_1_7505
+.globl sym_1_7506
+sym_1_7506: la $2, sym_1_7506
+.globl sym_1_7507
+sym_1_7507: la $2, sym_1_7507
+.globl sym_1_7508
+sym_1_7508: la $2, sym_1_7508
+.globl sym_1_7509
+sym_1_7509: la $2, sym_1_7509
+.globl sym_1_7510
+sym_1_7510: la $2, sym_1_7510
+.globl sym_1_7511
+sym_1_7511: la $2, sym_1_7511
+.globl sym_1_7512
+sym_1_7512: la $2, sym_1_7512
+.globl sym_1_7513
+sym_1_7513: la $2, sym_1_7513
+.globl sym_1_7514
+sym_1_7514: la $2, sym_1_7514
+.globl sym_1_7515
+sym_1_7515: la $2, sym_1_7515
+.globl sym_1_7516
+sym_1_7516: la $2, sym_1_7516
+.globl sym_1_7517
+sym_1_7517: la $2, sym_1_7517
+.globl sym_1_7518
+sym_1_7518: la $2, sym_1_7518
+.globl sym_1_7519
+sym_1_7519: la $2, sym_1_7519
+.globl sym_1_7520
+sym_1_7520: la $2, sym_1_7520
+.globl sym_1_7521
+sym_1_7521: la $2, sym_1_7521
+.globl sym_1_7522
+sym_1_7522: la $2, sym_1_7522
+.globl sym_1_7523
+sym_1_7523: la $2, sym_1_7523
+.globl sym_1_7524
+sym_1_7524: la $2, sym_1_7524
+.globl sym_1_7525
+sym_1_7525: la $2, sym_1_7525
+.globl sym_1_7526
+sym_1_7526: la $2, sym_1_7526
+.globl sym_1_7527
+sym_1_7527: la $2, sym_1_7527
+.globl sym_1_7528
+sym_1_7528: la $2, sym_1_7528
+.globl sym_1_7529
+sym_1_7529: la $2, sym_1_7529
+.globl sym_1_7530
+sym_1_7530: la $2, sym_1_7530
+.globl sym_1_7531
+sym_1_7531: la $2, sym_1_7531
+.globl sym_1_7532
+sym_1_7532: la $2, sym_1_7532
+.globl sym_1_7533
+sym_1_7533: la $2, sym_1_7533
+.globl sym_1_7534
+sym_1_7534: la $2, sym_1_7534
+.globl sym_1_7535
+sym_1_7535: la $2, sym_1_7535
+.globl sym_1_7536
+sym_1_7536: la $2, sym_1_7536
+.globl sym_1_7537
+sym_1_7537: la $2, sym_1_7537
+.globl sym_1_7538
+sym_1_7538: la $2, sym_1_7538
+.globl sym_1_7539
+sym_1_7539: la $2, sym_1_7539
+.globl sym_1_7540
+sym_1_7540: la $2, sym_1_7540
+.globl sym_1_7541
+sym_1_7541: la $2, sym_1_7541
+.globl sym_1_7542
+sym_1_7542: la $2, sym_1_7542
+.globl sym_1_7543
+sym_1_7543: la $2, sym_1_7543
+.globl sym_1_7544
+sym_1_7544: la $2, sym_1_7544
+.globl sym_1_7545
+sym_1_7545: la $2, sym_1_7545
+.globl sym_1_7546
+sym_1_7546: la $2, sym_1_7546
+.globl sym_1_7547
+sym_1_7547: la $2, sym_1_7547
+.globl sym_1_7548
+sym_1_7548: la $2, sym_1_7548
+.globl sym_1_7549
+sym_1_7549: la $2, sym_1_7549
+.globl sym_1_7550
+sym_1_7550: la $2, sym_1_7550
+.globl sym_1_7551
+sym_1_7551: la $2, sym_1_7551
+.globl sym_1_7552
+sym_1_7552: la $2, sym_1_7552
+.globl sym_1_7553
+sym_1_7553: la $2, sym_1_7553
+.globl sym_1_7554
+sym_1_7554: la $2, sym_1_7554
+.globl sym_1_7555
+sym_1_7555: la $2, sym_1_7555
+.globl sym_1_7556
+sym_1_7556: la $2, sym_1_7556
+.globl sym_1_7557
+sym_1_7557: la $2, sym_1_7557
+.globl sym_1_7558
+sym_1_7558: la $2, sym_1_7558
+.globl sym_1_7559
+sym_1_7559: la $2, sym_1_7559
+.globl sym_1_7560
+sym_1_7560: la $2, sym_1_7560
+.globl sym_1_7561
+sym_1_7561: la $2, sym_1_7561
+.globl sym_1_7562
+sym_1_7562: la $2, sym_1_7562
+.globl sym_1_7563
+sym_1_7563: la $2, sym_1_7563
+.globl sym_1_7564
+sym_1_7564: la $2, sym_1_7564
+.globl sym_1_7565
+sym_1_7565: la $2, sym_1_7565
+.globl sym_1_7566
+sym_1_7566: la $2, sym_1_7566
+.globl sym_1_7567
+sym_1_7567: la $2, sym_1_7567
+.globl sym_1_7568
+sym_1_7568: la $2, sym_1_7568
+.globl sym_1_7569
+sym_1_7569: la $2, sym_1_7569
+.globl sym_1_7570
+sym_1_7570: la $2, sym_1_7570
+.globl sym_1_7571
+sym_1_7571: la $2, sym_1_7571
+.globl sym_1_7572
+sym_1_7572: la $2, sym_1_7572
+.globl sym_1_7573
+sym_1_7573: la $2, sym_1_7573
+.globl sym_1_7574
+sym_1_7574: la $2, sym_1_7574
+.globl sym_1_7575
+sym_1_7575: la $2, sym_1_7575
+.globl sym_1_7576
+sym_1_7576: la $2, sym_1_7576
+.globl sym_1_7577
+sym_1_7577: la $2, sym_1_7577
+.globl sym_1_7578
+sym_1_7578: la $2, sym_1_7578
+.globl sym_1_7579
+sym_1_7579: la $2, sym_1_7579
+.globl sym_1_7580
+sym_1_7580: la $2, sym_1_7580
+.globl sym_1_7581
+sym_1_7581: la $2, sym_1_7581
+.globl sym_1_7582
+sym_1_7582: la $2, sym_1_7582
+.globl sym_1_7583
+sym_1_7583: la $2, sym_1_7583
+.globl sym_1_7584
+sym_1_7584: la $2, sym_1_7584
+.globl sym_1_7585
+sym_1_7585: la $2, sym_1_7585
+.globl sym_1_7586
+sym_1_7586: la $2, sym_1_7586
+.globl sym_1_7587
+sym_1_7587: la $2, sym_1_7587
+.globl sym_1_7588
+sym_1_7588: la $2, sym_1_7588
+.globl sym_1_7589
+sym_1_7589: la $2, sym_1_7589
+.globl sym_1_7590
+sym_1_7590: la $2, sym_1_7590
+.globl sym_1_7591
+sym_1_7591: la $2, sym_1_7591
+.globl sym_1_7592
+sym_1_7592: la $2, sym_1_7592
+.globl sym_1_7593
+sym_1_7593: la $2, sym_1_7593
+.globl sym_1_7594
+sym_1_7594: la $2, sym_1_7594
+.globl sym_1_7595
+sym_1_7595: la $2, sym_1_7595
+.globl sym_1_7596
+sym_1_7596: la $2, sym_1_7596
+.globl sym_1_7597
+sym_1_7597: la $2, sym_1_7597
+.globl sym_1_7598
+sym_1_7598: la $2, sym_1_7598
+.globl sym_1_7599
+sym_1_7599: la $2, sym_1_7599
+.globl sym_1_7600
+sym_1_7600: la $2, sym_1_7600
+.globl sym_1_7601
+sym_1_7601: la $2, sym_1_7601
+.globl sym_1_7602
+sym_1_7602: la $2, sym_1_7602
+.globl sym_1_7603
+sym_1_7603: la $2, sym_1_7603
+.globl sym_1_7604
+sym_1_7604: la $2, sym_1_7604
+.globl sym_1_7605
+sym_1_7605: la $2, sym_1_7605
+.globl sym_1_7606
+sym_1_7606: la $2, sym_1_7606
+.globl sym_1_7607
+sym_1_7607: la $2, sym_1_7607
+.globl sym_1_7608
+sym_1_7608: la $2, sym_1_7608
+.globl sym_1_7609
+sym_1_7609: la $2, sym_1_7609
+.globl sym_1_7610
+sym_1_7610: la $2, sym_1_7610
+.globl sym_1_7611
+sym_1_7611: la $2, sym_1_7611
+.globl sym_1_7612
+sym_1_7612: la $2, sym_1_7612
+.globl sym_1_7613
+sym_1_7613: la $2, sym_1_7613
+.globl sym_1_7614
+sym_1_7614: la $2, sym_1_7614
+.globl sym_1_7615
+sym_1_7615: la $2, sym_1_7615
+.globl sym_1_7616
+sym_1_7616: la $2, sym_1_7616
+.globl sym_1_7617
+sym_1_7617: la $2, sym_1_7617
+.globl sym_1_7618
+sym_1_7618: la $2, sym_1_7618
+.globl sym_1_7619
+sym_1_7619: la $2, sym_1_7619
+.globl sym_1_7620
+sym_1_7620: la $2, sym_1_7620
+.globl sym_1_7621
+sym_1_7621: la $2, sym_1_7621
+.globl sym_1_7622
+sym_1_7622: la $2, sym_1_7622
+.globl sym_1_7623
+sym_1_7623: la $2, sym_1_7623
+.globl sym_1_7624
+sym_1_7624: la $2, sym_1_7624
+.globl sym_1_7625
+sym_1_7625: la $2, sym_1_7625
+.globl sym_1_7626
+sym_1_7626: la $2, sym_1_7626
+.globl sym_1_7627
+sym_1_7627: la $2, sym_1_7627
+.globl sym_1_7628
+sym_1_7628: la $2, sym_1_7628
+.globl sym_1_7629
+sym_1_7629: la $2, sym_1_7629
+.globl sym_1_7630
+sym_1_7630: la $2, sym_1_7630
+.globl sym_1_7631
+sym_1_7631: la $2, sym_1_7631
+.globl sym_1_7632
+sym_1_7632: la $2, sym_1_7632
+.globl sym_1_7633
+sym_1_7633: la $2, sym_1_7633
+.globl sym_1_7634
+sym_1_7634: la $2, sym_1_7634
+.globl sym_1_7635
+sym_1_7635: la $2, sym_1_7635
+.globl sym_1_7636
+sym_1_7636: la $2, sym_1_7636
+.globl sym_1_7637
+sym_1_7637: la $2, sym_1_7637
+.globl sym_1_7638
+sym_1_7638: la $2, sym_1_7638
+.globl sym_1_7639
+sym_1_7639: la $2, sym_1_7639
+.globl sym_1_7640
+sym_1_7640: la $2, sym_1_7640
+.globl sym_1_7641
+sym_1_7641: la $2, sym_1_7641
+.globl sym_1_7642
+sym_1_7642: la $2, sym_1_7642
+.globl sym_1_7643
+sym_1_7643: la $2, sym_1_7643
+.globl sym_1_7644
+sym_1_7644: la $2, sym_1_7644
+.globl sym_1_7645
+sym_1_7645: la $2, sym_1_7645
+.globl sym_1_7646
+sym_1_7646: la $2, sym_1_7646
+.globl sym_1_7647
+sym_1_7647: la $2, sym_1_7647
+.globl sym_1_7648
+sym_1_7648: la $2, sym_1_7648
+.globl sym_1_7649
+sym_1_7649: la $2, sym_1_7649
+.globl sym_1_7650
+sym_1_7650: la $2, sym_1_7650
+.globl sym_1_7651
+sym_1_7651: la $2, sym_1_7651
+.globl sym_1_7652
+sym_1_7652: la $2, sym_1_7652
+.globl sym_1_7653
+sym_1_7653: la $2, sym_1_7653
+.globl sym_1_7654
+sym_1_7654: la $2, sym_1_7654
+.globl sym_1_7655
+sym_1_7655: la $2, sym_1_7655
+.globl sym_1_7656
+sym_1_7656: la $2, sym_1_7656
+.globl sym_1_7657
+sym_1_7657: la $2, sym_1_7657
+.globl sym_1_7658
+sym_1_7658: la $2, sym_1_7658
+.globl sym_1_7659
+sym_1_7659: la $2, sym_1_7659
+.globl sym_1_7660
+sym_1_7660: la $2, sym_1_7660
+.globl sym_1_7661
+sym_1_7661: la $2, sym_1_7661
+.globl sym_1_7662
+sym_1_7662: la $2, sym_1_7662
+.globl sym_1_7663
+sym_1_7663: la $2, sym_1_7663
+.globl sym_1_7664
+sym_1_7664: la $2, sym_1_7664
+.globl sym_1_7665
+sym_1_7665: la $2, sym_1_7665
+.globl sym_1_7666
+sym_1_7666: la $2, sym_1_7666
+.globl sym_1_7667
+sym_1_7667: la $2, sym_1_7667
+.globl sym_1_7668
+sym_1_7668: la $2, sym_1_7668
+.globl sym_1_7669
+sym_1_7669: la $2, sym_1_7669
+.globl sym_1_7670
+sym_1_7670: la $2, sym_1_7670
+.globl sym_1_7671
+sym_1_7671: la $2, sym_1_7671
+.globl sym_1_7672
+sym_1_7672: la $2, sym_1_7672
+.globl sym_1_7673
+sym_1_7673: la $2, sym_1_7673
+.globl sym_1_7674
+sym_1_7674: la $2, sym_1_7674
+.globl sym_1_7675
+sym_1_7675: la $2, sym_1_7675
+.globl sym_1_7676
+sym_1_7676: la $2, sym_1_7676
+.globl sym_1_7677
+sym_1_7677: la $2, sym_1_7677
+.globl sym_1_7678
+sym_1_7678: la $2, sym_1_7678
+.globl sym_1_7679
+sym_1_7679: la $2, sym_1_7679
+.globl sym_1_7680
+sym_1_7680: la $2, sym_1_7680
+.globl sym_1_7681
+sym_1_7681: la $2, sym_1_7681
+.globl sym_1_7682
+sym_1_7682: la $2, sym_1_7682
+.globl sym_1_7683
+sym_1_7683: la $2, sym_1_7683
+.globl sym_1_7684
+sym_1_7684: la $2, sym_1_7684
+.globl sym_1_7685
+sym_1_7685: la $2, sym_1_7685
+.globl sym_1_7686
+sym_1_7686: la $2, sym_1_7686
+.globl sym_1_7687
+sym_1_7687: la $2, sym_1_7687
+.globl sym_1_7688
+sym_1_7688: la $2, sym_1_7688
+.globl sym_1_7689
+sym_1_7689: la $2, sym_1_7689
+.globl sym_1_7690
+sym_1_7690: la $2, sym_1_7690
+.globl sym_1_7691
+sym_1_7691: la $2, sym_1_7691
+.globl sym_1_7692
+sym_1_7692: la $2, sym_1_7692
+.globl sym_1_7693
+sym_1_7693: la $2, sym_1_7693
+.globl sym_1_7694
+sym_1_7694: la $2, sym_1_7694
+.globl sym_1_7695
+sym_1_7695: la $2, sym_1_7695
+.globl sym_1_7696
+sym_1_7696: la $2, sym_1_7696
+.globl sym_1_7697
+sym_1_7697: la $2, sym_1_7697
+.globl sym_1_7698
+sym_1_7698: la $2, sym_1_7698
+.globl sym_1_7699
+sym_1_7699: la $2, sym_1_7699
+.globl sym_1_7700
+sym_1_7700: la $2, sym_1_7700
+.globl sym_1_7701
+sym_1_7701: la $2, sym_1_7701
+.globl sym_1_7702
+sym_1_7702: la $2, sym_1_7702
+.globl sym_1_7703
+sym_1_7703: la $2, sym_1_7703
+.globl sym_1_7704
+sym_1_7704: la $2, sym_1_7704
+.globl sym_1_7705
+sym_1_7705: la $2, sym_1_7705
+.globl sym_1_7706
+sym_1_7706: la $2, sym_1_7706
+.globl sym_1_7707
+sym_1_7707: la $2, sym_1_7707
+.globl sym_1_7708
+sym_1_7708: la $2, sym_1_7708
+.globl sym_1_7709
+sym_1_7709: la $2, sym_1_7709
+.globl sym_1_7710
+sym_1_7710: la $2, sym_1_7710
+.globl sym_1_7711
+sym_1_7711: la $2, sym_1_7711
+.globl sym_1_7712
+sym_1_7712: la $2, sym_1_7712
+.globl sym_1_7713
+sym_1_7713: la $2, sym_1_7713
+.globl sym_1_7714
+sym_1_7714: la $2, sym_1_7714
+.globl sym_1_7715
+sym_1_7715: la $2, sym_1_7715
+.globl sym_1_7716
+sym_1_7716: la $2, sym_1_7716
+.globl sym_1_7717
+sym_1_7717: la $2, sym_1_7717
+.globl sym_1_7718
+sym_1_7718: la $2, sym_1_7718
+.globl sym_1_7719
+sym_1_7719: la $2, sym_1_7719
+.globl sym_1_7720
+sym_1_7720: la $2, sym_1_7720
+.globl sym_1_7721
+sym_1_7721: la $2, sym_1_7721
+.globl sym_1_7722
+sym_1_7722: la $2, sym_1_7722
+.globl sym_1_7723
+sym_1_7723: la $2, sym_1_7723
+.globl sym_1_7724
+sym_1_7724: la $2, sym_1_7724
+.globl sym_1_7725
+sym_1_7725: la $2, sym_1_7725
+.globl sym_1_7726
+sym_1_7726: la $2, sym_1_7726
+.globl sym_1_7727
+sym_1_7727: la $2, sym_1_7727
+.globl sym_1_7728
+sym_1_7728: la $2, sym_1_7728
+.globl sym_1_7729
+sym_1_7729: la $2, sym_1_7729
+.globl sym_1_7730
+sym_1_7730: la $2, sym_1_7730
+.globl sym_1_7731
+sym_1_7731: la $2, sym_1_7731
+.globl sym_1_7732
+sym_1_7732: la $2, sym_1_7732
+.globl sym_1_7733
+sym_1_7733: la $2, sym_1_7733
+.globl sym_1_7734
+sym_1_7734: la $2, sym_1_7734
+.globl sym_1_7735
+sym_1_7735: la $2, sym_1_7735
+.globl sym_1_7736
+sym_1_7736: la $2, sym_1_7736
+.globl sym_1_7737
+sym_1_7737: la $2, sym_1_7737
+.globl sym_1_7738
+sym_1_7738: la $2, sym_1_7738
+.globl sym_1_7739
+sym_1_7739: la $2, sym_1_7739
+.globl sym_1_7740
+sym_1_7740: la $2, sym_1_7740
+.globl sym_1_7741
+sym_1_7741: la $2, sym_1_7741
+.globl sym_1_7742
+sym_1_7742: la $2, sym_1_7742
+.globl sym_1_7743
+sym_1_7743: la $2, sym_1_7743
+.globl sym_1_7744
+sym_1_7744: la $2, sym_1_7744
+.globl sym_1_7745
+sym_1_7745: la $2, sym_1_7745
+.globl sym_1_7746
+sym_1_7746: la $2, sym_1_7746
+.globl sym_1_7747
+sym_1_7747: la $2, sym_1_7747
+.globl sym_1_7748
+sym_1_7748: la $2, sym_1_7748
+.globl sym_1_7749
+sym_1_7749: la $2, sym_1_7749
+.globl sym_1_7750
+sym_1_7750: la $2, sym_1_7750
+.globl sym_1_7751
+sym_1_7751: la $2, sym_1_7751
+.globl sym_1_7752
+sym_1_7752: la $2, sym_1_7752
+.globl sym_1_7753
+sym_1_7753: la $2, sym_1_7753
+.globl sym_1_7754
+sym_1_7754: la $2, sym_1_7754
+.globl sym_1_7755
+sym_1_7755: la $2, sym_1_7755
+.globl sym_1_7756
+sym_1_7756: la $2, sym_1_7756
+.globl sym_1_7757
+sym_1_7757: la $2, sym_1_7757
+.globl sym_1_7758
+sym_1_7758: la $2, sym_1_7758
+.globl sym_1_7759
+sym_1_7759: la $2, sym_1_7759
+.globl sym_1_7760
+sym_1_7760: la $2, sym_1_7760
+.globl sym_1_7761
+sym_1_7761: la $2, sym_1_7761
+.globl sym_1_7762
+sym_1_7762: la $2, sym_1_7762
+.globl sym_1_7763
+sym_1_7763: la $2, sym_1_7763
+.globl sym_1_7764
+sym_1_7764: la $2, sym_1_7764
+.globl sym_1_7765
+sym_1_7765: la $2, sym_1_7765
+.globl sym_1_7766
+sym_1_7766: la $2, sym_1_7766
+.globl sym_1_7767
+sym_1_7767: la $2, sym_1_7767
+.globl sym_1_7768
+sym_1_7768: la $2, sym_1_7768
+.globl sym_1_7769
+sym_1_7769: la $2, sym_1_7769
+.globl sym_1_7770
+sym_1_7770: la $2, sym_1_7770
+.globl sym_1_7771
+sym_1_7771: la $2, sym_1_7771
+.globl sym_1_7772
+sym_1_7772: la $2, sym_1_7772
+.globl sym_1_7773
+sym_1_7773: la $2, sym_1_7773
+.globl sym_1_7774
+sym_1_7774: la $2, sym_1_7774
+.globl sym_1_7775
+sym_1_7775: la $2, sym_1_7775
+.globl sym_1_7776
+sym_1_7776: la $2, sym_1_7776
+.globl sym_1_7777
+sym_1_7777: la $2, sym_1_7777
+.globl sym_1_7778
+sym_1_7778: la $2, sym_1_7778
+.globl sym_1_7779
+sym_1_7779: la $2, sym_1_7779
+.globl sym_1_7780
+sym_1_7780: la $2, sym_1_7780
+.globl sym_1_7781
+sym_1_7781: la $2, sym_1_7781
+.globl sym_1_7782
+sym_1_7782: la $2, sym_1_7782
+.globl sym_1_7783
+sym_1_7783: la $2, sym_1_7783
+.globl sym_1_7784
+sym_1_7784: la $2, sym_1_7784
+.globl sym_1_7785
+sym_1_7785: la $2, sym_1_7785
+.globl sym_1_7786
+sym_1_7786: la $2, sym_1_7786
+.globl sym_1_7787
+sym_1_7787: la $2, sym_1_7787
+.globl sym_1_7788
+sym_1_7788: la $2, sym_1_7788
+.globl sym_1_7789
+sym_1_7789: la $2, sym_1_7789
+.globl sym_1_7790
+sym_1_7790: la $2, sym_1_7790
+.globl sym_1_7791
+sym_1_7791: la $2, sym_1_7791
+.globl sym_1_7792
+sym_1_7792: la $2, sym_1_7792
+.globl sym_1_7793
+sym_1_7793: la $2, sym_1_7793
+.globl sym_1_7794
+sym_1_7794: la $2, sym_1_7794
+.globl sym_1_7795
+sym_1_7795: la $2, sym_1_7795
+.globl sym_1_7796
+sym_1_7796: la $2, sym_1_7796
+.globl sym_1_7797
+sym_1_7797: la $2, sym_1_7797
+.globl sym_1_7798
+sym_1_7798: la $2, sym_1_7798
+.globl sym_1_7799
+sym_1_7799: la $2, sym_1_7799
+.globl sym_1_7800
+sym_1_7800: la $2, sym_1_7800
+.globl sym_1_7801
+sym_1_7801: la $2, sym_1_7801
+.globl sym_1_7802
+sym_1_7802: la $2, sym_1_7802
+.globl sym_1_7803
+sym_1_7803: la $2, sym_1_7803
+.globl sym_1_7804
+sym_1_7804: la $2, sym_1_7804
+.globl sym_1_7805
+sym_1_7805: la $2, sym_1_7805
+.globl sym_1_7806
+sym_1_7806: la $2, sym_1_7806
+.globl sym_1_7807
+sym_1_7807: la $2, sym_1_7807
+.globl sym_1_7808
+sym_1_7808: la $2, sym_1_7808
+.globl sym_1_7809
+sym_1_7809: la $2, sym_1_7809
+.globl sym_1_7810
+sym_1_7810: la $2, sym_1_7810
+.globl sym_1_7811
+sym_1_7811: la $2, sym_1_7811
+.globl sym_1_7812
+sym_1_7812: la $2, sym_1_7812
+.globl sym_1_7813
+sym_1_7813: la $2, sym_1_7813
+.globl sym_1_7814
+sym_1_7814: la $2, sym_1_7814
+.globl sym_1_7815
+sym_1_7815: la $2, sym_1_7815
+.globl sym_1_7816
+sym_1_7816: la $2, sym_1_7816
+.globl sym_1_7817
+sym_1_7817: la $2, sym_1_7817
+.globl sym_1_7818
+sym_1_7818: la $2, sym_1_7818
+.globl sym_1_7819
+sym_1_7819: la $2, sym_1_7819
+.globl sym_1_7820
+sym_1_7820: la $2, sym_1_7820
+.globl sym_1_7821
+sym_1_7821: la $2, sym_1_7821
+.globl sym_1_7822
+sym_1_7822: la $2, sym_1_7822
+.globl sym_1_7823
+sym_1_7823: la $2, sym_1_7823
+.globl sym_1_7824
+sym_1_7824: la $2, sym_1_7824
+.globl sym_1_7825
+sym_1_7825: la $2, sym_1_7825
+.globl sym_1_7826
+sym_1_7826: la $2, sym_1_7826
+.globl sym_1_7827
+sym_1_7827: la $2, sym_1_7827
+.globl sym_1_7828
+sym_1_7828: la $2, sym_1_7828
+.globl sym_1_7829
+sym_1_7829: la $2, sym_1_7829
+.globl sym_1_7830
+sym_1_7830: la $2, sym_1_7830
+.globl sym_1_7831
+sym_1_7831: la $2, sym_1_7831
+.globl sym_1_7832
+sym_1_7832: la $2, sym_1_7832
+.globl sym_1_7833
+sym_1_7833: la $2, sym_1_7833
+.globl sym_1_7834
+sym_1_7834: la $2, sym_1_7834
+.globl sym_1_7835
+sym_1_7835: la $2, sym_1_7835
+.globl sym_1_7836
+sym_1_7836: la $2, sym_1_7836
+.globl sym_1_7837
+sym_1_7837: la $2, sym_1_7837
+.globl sym_1_7838
+sym_1_7838: la $2, sym_1_7838
+.globl sym_1_7839
+sym_1_7839: la $2, sym_1_7839
+.globl sym_1_7840
+sym_1_7840: la $2, sym_1_7840
+.globl sym_1_7841
+sym_1_7841: la $2, sym_1_7841
+.globl sym_1_7842
+sym_1_7842: la $2, sym_1_7842
+.globl sym_1_7843
+sym_1_7843: la $2, sym_1_7843
+.globl sym_1_7844
+sym_1_7844: la $2, sym_1_7844
+.globl sym_1_7845
+sym_1_7845: la $2, sym_1_7845
+.globl sym_1_7846
+sym_1_7846: la $2, sym_1_7846
+.globl sym_1_7847
+sym_1_7847: la $2, sym_1_7847
+.globl sym_1_7848
+sym_1_7848: la $2, sym_1_7848
+.globl sym_1_7849
+sym_1_7849: la $2, sym_1_7849
+.globl sym_1_7850
+sym_1_7850: la $2, sym_1_7850
+.globl sym_1_7851
+sym_1_7851: la $2, sym_1_7851
+.globl sym_1_7852
+sym_1_7852: la $2, sym_1_7852
+.globl sym_1_7853
+sym_1_7853: la $2, sym_1_7853
+.globl sym_1_7854
+sym_1_7854: la $2, sym_1_7854
+.globl sym_1_7855
+sym_1_7855: la $2, sym_1_7855
+.globl sym_1_7856
+sym_1_7856: la $2, sym_1_7856
+.globl sym_1_7857
+sym_1_7857: la $2, sym_1_7857
+.globl sym_1_7858
+sym_1_7858: la $2, sym_1_7858
+.globl sym_1_7859
+sym_1_7859: la $2, sym_1_7859
+.globl sym_1_7860
+sym_1_7860: la $2, sym_1_7860
+.globl sym_1_7861
+sym_1_7861: la $2, sym_1_7861
+.globl sym_1_7862
+sym_1_7862: la $2, sym_1_7862
+.globl sym_1_7863
+sym_1_7863: la $2, sym_1_7863
+.globl sym_1_7864
+sym_1_7864: la $2, sym_1_7864
+.globl sym_1_7865
+sym_1_7865: la $2, sym_1_7865
+.globl sym_1_7866
+sym_1_7866: la $2, sym_1_7866
+.globl sym_1_7867
+sym_1_7867: la $2, sym_1_7867
+.globl sym_1_7868
+sym_1_7868: la $2, sym_1_7868
+.globl sym_1_7869
+sym_1_7869: la $2, sym_1_7869
+.globl sym_1_7870
+sym_1_7870: la $2, sym_1_7870
+.globl sym_1_7871
+sym_1_7871: la $2, sym_1_7871
+.globl sym_1_7872
+sym_1_7872: la $2, sym_1_7872
+.globl sym_1_7873
+sym_1_7873: la $2, sym_1_7873
+.globl sym_1_7874
+sym_1_7874: la $2, sym_1_7874
+.globl sym_1_7875
+sym_1_7875: la $2, sym_1_7875
+.globl sym_1_7876
+sym_1_7876: la $2, sym_1_7876
+.globl sym_1_7877
+sym_1_7877: la $2, sym_1_7877
+.globl sym_1_7878
+sym_1_7878: la $2, sym_1_7878
+.globl sym_1_7879
+sym_1_7879: la $2, sym_1_7879
+.globl sym_1_7880
+sym_1_7880: la $2, sym_1_7880
+.globl sym_1_7881
+sym_1_7881: la $2, sym_1_7881
+.globl sym_1_7882
+sym_1_7882: la $2, sym_1_7882
+.globl sym_1_7883
+sym_1_7883: la $2, sym_1_7883
+.globl sym_1_7884
+sym_1_7884: la $2, sym_1_7884
+.globl sym_1_7885
+sym_1_7885: la $2, sym_1_7885
+.globl sym_1_7886
+sym_1_7886: la $2, sym_1_7886
+.globl sym_1_7887
+sym_1_7887: la $2, sym_1_7887
+.globl sym_1_7888
+sym_1_7888: la $2, sym_1_7888
+.globl sym_1_7889
+sym_1_7889: la $2, sym_1_7889
+.globl sym_1_7890
+sym_1_7890: la $2, sym_1_7890
+.globl sym_1_7891
+sym_1_7891: la $2, sym_1_7891
+.globl sym_1_7892
+sym_1_7892: la $2, sym_1_7892
+.globl sym_1_7893
+sym_1_7893: la $2, sym_1_7893
+.globl sym_1_7894
+sym_1_7894: la $2, sym_1_7894
+.globl sym_1_7895
+sym_1_7895: la $2, sym_1_7895
+.globl sym_1_7896
+sym_1_7896: la $2, sym_1_7896
+.globl sym_1_7897
+sym_1_7897: la $2, sym_1_7897
+.globl sym_1_7898
+sym_1_7898: la $2, sym_1_7898
+.globl sym_1_7899
+sym_1_7899: la $2, sym_1_7899
+.globl sym_1_7900
+sym_1_7900: la $2, sym_1_7900
+.globl sym_1_7901
+sym_1_7901: la $2, sym_1_7901
+.globl sym_1_7902
+sym_1_7902: la $2, sym_1_7902
+.globl sym_1_7903
+sym_1_7903: la $2, sym_1_7903
+.globl sym_1_7904
+sym_1_7904: la $2, sym_1_7904
+.globl sym_1_7905
+sym_1_7905: la $2, sym_1_7905
+.globl sym_1_7906
+sym_1_7906: la $2, sym_1_7906
+.globl sym_1_7907
+sym_1_7907: la $2, sym_1_7907
+.globl sym_1_7908
+sym_1_7908: la $2, sym_1_7908
+.globl sym_1_7909
+sym_1_7909: la $2, sym_1_7909
+.globl sym_1_7910
+sym_1_7910: la $2, sym_1_7910
+.globl sym_1_7911
+sym_1_7911: la $2, sym_1_7911
+.globl sym_1_7912
+sym_1_7912: la $2, sym_1_7912
+.globl sym_1_7913
+sym_1_7913: la $2, sym_1_7913
+.globl sym_1_7914
+sym_1_7914: la $2, sym_1_7914
+.globl sym_1_7915
+sym_1_7915: la $2, sym_1_7915
+.globl sym_1_7916
+sym_1_7916: la $2, sym_1_7916
+.globl sym_1_7917
+sym_1_7917: la $2, sym_1_7917
+.globl sym_1_7918
+sym_1_7918: la $2, sym_1_7918
+.globl sym_1_7919
+sym_1_7919: la $2, sym_1_7919
+.globl sym_1_7920
+sym_1_7920: la $2, sym_1_7920
+.globl sym_1_7921
+sym_1_7921: la $2, sym_1_7921
+.globl sym_1_7922
+sym_1_7922: la $2, sym_1_7922
+.globl sym_1_7923
+sym_1_7923: la $2, sym_1_7923
+.globl sym_1_7924
+sym_1_7924: la $2, sym_1_7924
+.globl sym_1_7925
+sym_1_7925: la $2, sym_1_7925
+.globl sym_1_7926
+sym_1_7926: la $2, sym_1_7926
+.globl sym_1_7927
+sym_1_7927: la $2, sym_1_7927
+.globl sym_1_7928
+sym_1_7928: la $2, sym_1_7928
+.globl sym_1_7929
+sym_1_7929: la $2, sym_1_7929
+.globl sym_1_7930
+sym_1_7930: la $2, sym_1_7930
+.globl sym_1_7931
+sym_1_7931: la $2, sym_1_7931
+.globl sym_1_7932
+sym_1_7932: la $2, sym_1_7932
+.globl sym_1_7933
+sym_1_7933: la $2, sym_1_7933
+.globl sym_1_7934
+sym_1_7934: la $2, sym_1_7934
+.globl sym_1_7935
+sym_1_7935: la $2, sym_1_7935
+.globl sym_1_7936
+sym_1_7936: la $2, sym_1_7936
+.globl sym_1_7937
+sym_1_7937: la $2, sym_1_7937
+.globl sym_1_7938
+sym_1_7938: la $2, sym_1_7938
+.globl sym_1_7939
+sym_1_7939: la $2, sym_1_7939
+.globl sym_1_7940
+sym_1_7940: la $2, sym_1_7940
+.globl sym_1_7941
+sym_1_7941: la $2, sym_1_7941
+.globl sym_1_7942
+sym_1_7942: la $2, sym_1_7942
+.globl sym_1_7943
+sym_1_7943: la $2, sym_1_7943
+.globl sym_1_7944
+sym_1_7944: la $2, sym_1_7944
+.globl sym_1_7945
+sym_1_7945: la $2, sym_1_7945
+.globl sym_1_7946
+sym_1_7946: la $2, sym_1_7946
+.globl sym_1_7947
+sym_1_7947: la $2, sym_1_7947
+.globl sym_1_7948
+sym_1_7948: la $2, sym_1_7948
+.globl sym_1_7949
+sym_1_7949: la $2, sym_1_7949
+.globl sym_1_7950
+sym_1_7950: la $2, sym_1_7950
+.globl sym_1_7951
+sym_1_7951: la $2, sym_1_7951
+.globl sym_1_7952
+sym_1_7952: la $2, sym_1_7952
+.globl sym_1_7953
+sym_1_7953: la $2, sym_1_7953
+.globl sym_1_7954
+sym_1_7954: la $2, sym_1_7954
+.globl sym_1_7955
+sym_1_7955: la $2, sym_1_7955
+.globl sym_1_7956
+sym_1_7956: la $2, sym_1_7956
+.globl sym_1_7957
+sym_1_7957: la $2, sym_1_7957
+.globl sym_1_7958
+sym_1_7958: la $2, sym_1_7958
+.globl sym_1_7959
+sym_1_7959: la $2, sym_1_7959
+.globl sym_1_7960
+sym_1_7960: la $2, sym_1_7960
+.globl sym_1_7961
+sym_1_7961: la $2, sym_1_7961
+.globl sym_1_7962
+sym_1_7962: la $2, sym_1_7962
+.globl sym_1_7963
+sym_1_7963: la $2, sym_1_7963
+.globl sym_1_7964
+sym_1_7964: la $2, sym_1_7964
+.globl sym_1_7965
+sym_1_7965: la $2, sym_1_7965
+.globl sym_1_7966
+sym_1_7966: la $2, sym_1_7966
+.globl sym_1_7967
+sym_1_7967: la $2, sym_1_7967
+.globl sym_1_7968
+sym_1_7968: la $2, sym_1_7968
+.globl sym_1_7969
+sym_1_7969: la $2, sym_1_7969
+.globl sym_1_7970
+sym_1_7970: la $2, sym_1_7970
+.globl sym_1_7971
+sym_1_7971: la $2, sym_1_7971
+.globl sym_1_7972
+sym_1_7972: la $2, sym_1_7972
+.globl sym_1_7973
+sym_1_7973: la $2, sym_1_7973
+.globl sym_1_7974
+sym_1_7974: la $2, sym_1_7974
+.globl sym_1_7975
+sym_1_7975: la $2, sym_1_7975
+.globl sym_1_7976
+sym_1_7976: la $2, sym_1_7976
+.globl sym_1_7977
+sym_1_7977: la $2, sym_1_7977
+.globl sym_1_7978
+sym_1_7978: la $2, sym_1_7978
+.globl sym_1_7979
+sym_1_7979: la $2, sym_1_7979
+.globl sym_1_7980
+sym_1_7980: la $2, sym_1_7980
+.globl sym_1_7981
+sym_1_7981: la $2, sym_1_7981
+.globl sym_1_7982
+sym_1_7982: la $2, sym_1_7982
+.globl sym_1_7983
+sym_1_7983: la $2, sym_1_7983
+.globl sym_1_7984
+sym_1_7984: la $2, sym_1_7984
+.globl sym_1_7985
+sym_1_7985: la $2, sym_1_7985
+.globl sym_1_7986
+sym_1_7986: la $2, sym_1_7986
+.globl sym_1_7987
+sym_1_7987: la $2, sym_1_7987
+.globl sym_1_7988
+sym_1_7988: la $2, sym_1_7988
+.globl sym_1_7989
+sym_1_7989: la $2, sym_1_7989
+.globl sym_1_7990
+sym_1_7990: la $2, sym_1_7990
+.globl sym_1_7991
+sym_1_7991: la $2, sym_1_7991
+.globl sym_1_7992
+sym_1_7992: la $2, sym_1_7992
+.globl sym_1_7993
+sym_1_7993: la $2, sym_1_7993
+.globl sym_1_7994
+sym_1_7994: la $2, sym_1_7994
+.globl sym_1_7995
+sym_1_7995: la $2, sym_1_7995
+.globl sym_1_7996
+sym_1_7996: la $2, sym_1_7996
+.globl sym_1_7997
+sym_1_7997: la $2, sym_1_7997
+.globl sym_1_7998
+sym_1_7998: la $2, sym_1_7998
+.globl sym_1_7999
+sym_1_7999: la $2, sym_1_7999
+.globl sym_1_8000
+sym_1_8000: la $2, sym_1_8000
+.globl sym_1_8001
+sym_1_8001: la $2, sym_1_8001
+.globl sym_1_8002
+sym_1_8002: la $2, sym_1_8002
+.globl sym_1_8003
+sym_1_8003: la $2, sym_1_8003
+.globl sym_1_8004
+sym_1_8004: la $2, sym_1_8004
+.globl sym_1_8005
+sym_1_8005: la $2, sym_1_8005
+.globl sym_1_8006
+sym_1_8006: la $2, sym_1_8006
+.globl sym_1_8007
+sym_1_8007: la $2, sym_1_8007
+.globl sym_1_8008
+sym_1_8008: la $2, sym_1_8008
+.globl sym_1_8009
+sym_1_8009: la $2, sym_1_8009
+.globl sym_1_8010
+sym_1_8010: la $2, sym_1_8010
+.globl sym_1_8011
+sym_1_8011: la $2, sym_1_8011
+.globl sym_1_8012
+sym_1_8012: la $2, sym_1_8012
+.globl sym_1_8013
+sym_1_8013: la $2, sym_1_8013
+.globl sym_1_8014
+sym_1_8014: la $2, sym_1_8014
+.globl sym_1_8015
+sym_1_8015: la $2, sym_1_8015
+.globl sym_1_8016
+sym_1_8016: la $2, sym_1_8016
+.globl sym_1_8017
+sym_1_8017: la $2, sym_1_8017
+.globl sym_1_8018
+sym_1_8018: la $2, sym_1_8018
+.globl sym_1_8019
+sym_1_8019: la $2, sym_1_8019
+.globl sym_1_8020
+sym_1_8020: la $2, sym_1_8020
+.globl sym_1_8021
+sym_1_8021: la $2, sym_1_8021
+.globl sym_1_8022
+sym_1_8022: la $2, sym_1_8022
+.globl sym_1_8023
+sym_1_8023: la $2, sym_1_8023
+.globl sym_1_8024
+sym_1_8024: la $2, sym_1_8024
+.globl sym_1_8025
+sym_1_8025: la $2, sym_1_8025
+.globl sym_1_8026
+sym_1_8026: la $2, sym_1_8026
+.globl sym_1_8027
+sym_1_8027: la $2, sym_1_8027
+.globl sym_1_8028
+sym_1_8028: la $2, sym_1_8028
+.globl sym_1_8029
+sym_1_8029: la $2, sym_1_8029
+.globl sym_1_8030
+sym_1_8030: la $2, sym_1_8030
+.globl sym_1_8031
+sym_1_8031: la $2, sym_1_8031
+.globl sym_1_8032
+sym_1_8032: la $2, sym_1_8032
+.globl sym_1_8033
+sym_1_8033: la $2, sym_1_8033
+.globl sym_1_8034
+sym_1_8034: la $2, sym_1_8034
+.globl sym_1_8035
+sym_1_8035: la $2, sym_1_8035
+.globl sym_1_8036
+sym_1_8036: la $2, sym_1_8036
+.globl sym_1_8037
+sym_1_8037: la $2, sym_1_8037
+.globl sym_1_8038
+sym_1_8038: la $2, sym_1_8038
+.globl sym_1_8039
+sym_1_8039: la $2, sym_1_8039
+.globl sym_1_8040
+sym_1_8040: la $2, sym_1_8040
+.globl sym_1_8041
+sym_1_8041: la $2, sym_1_8041
+.globl sym_1_8042
+sym_1_8042: la $2, sym_1_8042
+.globl sym_1_8043
+sym_1_8043: la $2, sym_1_8043
+.globl sym_1_8044
+sym_1_8044: la $2, sym_1_8044
+.globl sym_1_8045
+sym_1_8045: la $2, sym_1_8045
+.globl sym_1_8046
+sym_1_8046: la $2, sym_1_8046
+.globl sym_1_8047
+sym_1_8047: la $2, sym_1_8047
+.globl sym_1_8048
+sym_1_8048: la $2, sym_1_8048
+.globl sym_1_8049
+sym_1_8049: la $2, sym_1_8049
+.globl sym_1_8050
+sym_1_8050: la $2, sym_1_8050
+.globl sym_1_8051
+sym_1_8051: la $2, sym_1_8051
+.globl sym_1_8052
+sym_1_8052: la $2, sym_1_8052
+.globl sym_1_8053
+sym_1_8053: la $2, sym_1_8053
+.globl sym_1_8054
+sym_1_8054: la $2, sym_1_8054
+.globl sym_1_8055
+sym_1_8055: la $2, sym_1_8055
+.globl sym_1_8056
+sym_1_8056: la $2, sym_1_8056
+.globl sym_1_8057
+sym_1_8057: la $2, sym_1_8057
+.globl sym_1_8058
+sym_1_8058: la $2, sym_1_8058
+.globl sym_1_8059
+sym_1_8059: la $2, sym_1_8059
+.globl sym_1_8060
+sym_1_8060: la $2, sym_1_8060
+.globl sym_1_8061
+sym_1_8061: la $2, sym_1_8061
+.globl sym_1_8062
+sym_1_8062: la $2, sym_1_8062
+.globl sym_1_8063
+sym_1_8063: la $2, sym_1_8063
+.globl sym_1_8064
+sym_1_8064: la $2, sym_1_8064
+.globl sym_1_8065
+sym_1_8065: la $2, sym_1_8065
+.globl sym_1_8066
+sym_1_8066: la $2, sym_1_8066
+.globl sym_1_8067
+sym_1_8067: la $2, sym_1_8067
+.globl sym_1_8068
+sym_1_8068: la $2, sym_1_8068
+.globl sym_1_8069
+sym_1_8069: la $2, sym_1_8069
+.globl sym_1_8070
+sym_1_8070: la $2, sym_1_8070
+.globl sym_1_8071
+sym_1_8071: la $2, sym_1_8071
+.globl sym_1_8072
+sym_1_8072: la $2, sym_1_8072
+.globl sym_1_8073
+sym_1_8073: la $2, sym_1_8073
+.globl sym_1_8074
+sym_1_8074: la $2, sym_1_8074
+.globl sym_1_8075
+sym_1_8075: la $2, sym_1_8075
+.globl sym_1_8076
+sym_1_8076: la $2, sym_1_8076
+.globl sym_1_8077
+sym_1_8077: la $2, sym_1_8077
+.globl sym_1_8078
+sym_1_8078: la $2, sym_1_8078
+.globl sym_1_8079
+sym_1_8079: la $2, sym_1_8079
+.globl sym_1_8080
+sym_1_8080: la $2, sym_1_8080
+.globl sym_1_8081
+sym_1_8081: la $2, sym_1_8081
+.globl sym_1_8082
+sym_1_8082: la $2, sym_1_8082
+.globl sym_1_8083
+sym_1_8083: la $2, sym_1_8083
+.globl sym_1_8084
+sym_1_8084: la $2, sym_1_8084
+.globl sym_1_8085
+sym_1_8085: la $2, sym_1_8085
+.globl sym_1_8086
+sym_1_8086: la $2, sym_1_8086
+.globl sym_1_8087
+sym_1_8087: la $2, sym_1_8087
+.globl sym_1_8088
+sym_1_8088: la $2, sym_1_8088
+.globl sym_1_8089
+sym_1_8089: la $2, sym_1_8089
+.globl sym_1_8090
+sym_1_8090: la $2, sym_1_8090
+.globl sym_1_8091
+sym_1_8091: la $2, sym_1_8091
+.globl sym_1_8092
+sym_1_8092: la $2, sym_1_8092
+.globl sym_1_8093
+sym_1_8093: la $2, sym_1_8093
+.globl sym_1_8094
+sym_1_8094: la $2, sym_1_8094
+.globl sym_1_8095
+sym_1_8095: la $2, sym_1_8095
+.globl sym_1_8096
+sym_1_8096: la $2, sym_1_8096
+.globl sym_1_8097
+sym_1_8097: la $2, sym_1_8097
+.globl sym_1_8098
+sym_1_8098: la $2, sym_1_8098
+.globl sym_1_8099
+sym_1_8099: la $2, sym_1_8099
+.globl sym_1_8100
+sym_1_8100: la $2, sym_1_8100
+.globl sym_1_8101
+sym_1_8101: la $2, sym_1_8101
+.globl sym_1_8102
+sym_1_8102: la $2, sym_1_8102
+.globl sym_1_8103
+sym_1_8103: la $2, sym_1_8103
+.globl sym_1_8104
+sym_1_8104: la $2, sym_1_8104
+.globl sym_1_8105
+sym_1_8105: la $2, sym_1_8105
+.globl sym_1_8106
+sym_1_8106: la $2, sym_1_8106
+.globl sym_1_8107
+sym_1_8107: la $2, sym_1_8107
+.globl sym_1_8108
+sym_1_8108: la $2, sym_1_8108
+.globl sym_1_8109
+sym_1_8109: la $2, sym_1_8109
+.globl sym_1_8110
+sym_1_8110: la $2, sym_1_8110
+.globl sym_1_8111
+sym_1_8111: la $2, sym_1_8111
+.globl sym_1_8112
+sym_1_8112: la $2, sym_1_8112
+.globl sym_1_8113
+sym_1_8113: la $2, sym_1_8113
+.globl sym_1_8114
+sym_1_8114: la $2, sym_1_8114
+.globl sym_1_8115
+sym_1_8115: la $2, sym_1_8115
+.globl sym_1_8116
+sym_1_8116: la $2, sym_1_8116
+.globl sym_1_8117
+sym_1_8117: la $2, sym_1_8117
+.globl sym_1_8118
+sym_1_8118: la $2, sym_1_8118
+.globl sym_1_8119
+sym_1_8119: la $2, sym_1_8119
+.globl sym_1_8120
+sym_1_8120: la $2, sym_1_8120
+.globl sym_1_8121
+sym_1_8121: la $2, sym_1_8121
+.globl sym_1_8122
+sym_1_8122: la $2, sym_1_8122
+.globl sym_1_8123
+sym_1_8123: la $2, sym_1_8123
+.globl sym_1_8124
+sym_1_8124: la $2, sym_1_8124
+.globl sym_1_8125
+sym_1_8125: la $2, sym_1_8125
+.globl sym_1_8126
+sym_1_8126: la $2, sym_1_8126
+.globl sym_1_8127
+sym_1_8127: la $2, sym_1_8127
+.globl sym_1_8128
+sym_1_8128: la $2, sym_1_8128
+.globl sym_1_8129
+sym_1_8129: la $2, sym_1_8129
+.globl sym_1_8130
+sym_1_8130: la $2, sym_1_8130
+.globl sym_1_8131
+sym_1_8131: la $2, sym_1_8131
+.globl sym_1_8132
+sym_1_8132: la $2, sym_1_8132
+.globl sym_1_8133
+sym_1_8133: la $2, sym_1_8133
+.globl sym_1_8134
+sym_1_8134: la $2, sym_1_8134
+.globl sym_1_8135
+sym_1_8135: la $2, sym_1_8135
+.globl sym_1_8136
+sym_1_8136: la $2, sym_1_8136
+.globl sym_1_8137
+sym_1_8137: la $2, sym_1_8137
+.globl sym_1_8138
+sym_1_8138: la $2, sym_1_8138
+.globl sym_1_8139
+sym_1_8139: la $2, sym_1_8139
+.globl sym_1_8140
+sym_1_8140: la $2, sym_1_8140
+.globl sym_1_8141
+sym_1_8141: la $2, sym_1_8141
+.globl sym_1_8142
+sym_1_8142: la $2, sym_1_8142
+.globl sym_1_8143
+sym_1_8143: la $2, sym_1_8143
+.globl sym_1_8144
+sym_1_8144: la $2, sym_1_8144
+.globl sym_1_8145
+sym_1_8145: la $2, sym_1_8145
+.globl sym_1_8146
+sym_1_8146: la $2, sym_1_8146
+.globl sym_1_8147
+sym_1_8147: la $2, sym_1_8147
+.globl sym_1_8148
+sym_1_8148: la $2, sym_1_8148
+.globl sym_1_8149
+sym_1_8149: la $2, sym_1_8149
+.globl sym_1_8150
+sym_1_8150: la $2, sym_1_8150
+.globl sym_1_8151
+sym_1_8151: la $2, sym_1_8151
+.globl sym_1_8152
+sym_1_8152: la $2, sym_1_8152
+.globl sym_1_8153
+sym_1_8153: la $2, sym_1_8153
+.globl sym_1_8154
+sym_1_8154: la $2, sym_1_8154
+.globl sym_1_8155
+sym_1_8155: la $2, sym_1_8155
+.globl sym_1_8156
+sym_1_8156: la $2, sym_1_8156
+.globl sym_1_8157
+sym_1_8157: la $2, sym_1_8157
+.globl sym_1_8158
+sym_1_8158: la $2, sym_1_8158
+.globl sym_1_8159
+sym_1_8159: la $2, sym_1_8159
+.globl sym_1_8160
+sym_1_8160: la $2, sym_1_8160
+.globl sym_1_8161
+sym_1_8161: la $2, sym_1_8161
+.globl sym_1_8162
+sym_1_8162: la $2, sym_1_8162
+.globl sym_1_8163
+sym_1_8163: la $2, sym_1_8163
+.globl sym_1_8164
+sym_1_8164: la $2, sym_1_8164
+.globl sym_1_8165
+sym_1_8165: la $2, sym_1_8165
+.globl sym_1_8166
+sym_1_8166: la $2, sym_1_8166
+.globl sym_1_8167
+sym_1_8167: la $2, sym_1_8167
+.globl sym_1_8168
+sym_1_8168: la $2, sym_1_8168
+.globl sym_1_8169
+sym_1_8169: la $2, sym_1_8169
+.globl sym_1_8170
+sym_1_8170: la $2, sym_1_8170
+.globl sym_1_8171
+sym_1_8171: la $2, sym_1_8171
+.globl sym_1_8172
+sym_1_8172: la $2, sym_1_8172
+.globl sym_1_8173
+sym_1_8173: la $2, sym_1_8173
+.globl sym_1_8174
+sym_1_8174: la $2, sym_1_8174
+.globl sym_1_8175
+sym_1_8175: la $2, sym_1_8175
+.globl sym_1_8176
+sym_1_8176: la $2, sym_1_8176
+.globl sym_1_8177
+sym_1_8177: la $2, sym_1_8177
+.globl sym_1_8178
+sym_1_8178: la $2, sym_1_8178
+.globl sym_1_8179
+sym_1_8179: la $2, sym_1_8179
+.globl sym_1_8180
+sym_1_8180: la $2, sym_1_8180
+.globl sym_1_8181
+sym_1_8181: la $2, sym_1_8181
+.globl sym_1_8182
+sym_1_8182: la $2, sym_1_8182
+.globl sym_1_8183
+sym_1_8183: la $2, sym_1_8183
+.globl sym_1_8184
+sym_1_8184: la $2, sym_1_8184
+.globl sym_1_8185
+sym_1_8185: la $2, sym_1_8185
+.globl sym_1_8186
+sym_1_8186: la $2, sym_1_8186
+.globl sym_1_8187
+sym_1_8187: la $2, sym_1_8187
+.globl sym_1_8188
+sym_1_8188: la $2, sym_1_8188
+.globl sym_1_8189
+sym_1_8189: la $2, sym_1_8189
+.globl sym_1_8190
+sym_1_8190: la $2, sym_1_8190
+.globl sym_1_8191
+sym_1_8191: la $2, sym_1_8191
+.globl sym_1_8192
+sym_1_8192: la $2, sym_1_8192
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-1-2.s b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-1-2.s
new file mode 100644
index 0000000..8904b03
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-1-2.s
@@ -0,0 +1,16384 @@
+.globl sym_2_1
+sym_2_1: la $2, sym_2_1
+.globl sym_2_2
+sym_2_2: la $2, sym_2_2
+.globl sym_2_3
+sym_2_3: la $2, sym_2_3
+.globl sym_2_4
+sym_2_4: la $2, sym_2_4
+.globl sym_2_5
+sym_2_5: la $2, sym_2_5
+.globl sym_2_6
+sym_2_6: la $2, sym_2_6
+.globl sym_2_7
+sym_2_7: la $2, sym_2_7
+.globl sym_2_8
+sym_2_8: la $2, sym_2_8
+.globl sym_2_9
+sym_2_9: la $2, sym_2_9
+.globl sym_2_10
+sym_2_10: la $2, sym_2_10
+.globl sym_2_11
+sym_2_11: la $2, sym_2_11
+.globl sym_2_12
+sym_2_12: la $2, sym_2_12
+.globl sym_2_13
+sym_2_13: la $2, sym_2_13
+.globl sym_2_14
+sym_2_14: la $2, sym_2_14
+.globl sym_2_15
+sym_2_15: la $2, sym_2_15
+.globl sym_2_16
+sym_2_16: la $2, sym_2_16
+.globl sym_2_17
+sym_2_17: la $2, sym_2_17
+.globl sym_2_18
+sym_2_18: la $2, sym_2_18
+.globl sym_2_19
+sym_2_19: la $2, sym_2_19
+.globl sym_2_20
+sym_2_20: la $2, sym_2_20
+.globl sym_2_21
+sym_2_21: la $2, sym_2_21
+.globl sym_2_22
+sym_2_22: la $2, sym_2_22
+.globl sym_2_23
+sym_2_23: la $2, sym_2_23
+.globl sym_2_24
+sym_2_24: la $2, sym_2_24
+.globl sym_2_25
+sym_2_25: la $2, sym_2_25
+.globl sym_2_26
+sym_2_26: la $2, sym_2_26
+.globl sym_2_27
+sym_2_27: la $2, sym_2_27
+.globl sym_2_28
+sym_2_28: la $2, sym_2_28
+.globl sym_2_29
+sym_2_29: la $2, sym_2_29
+.globl sym_2_30
+sym_2_30: la $2, sym_2_30
+.globl sym_2_31
+sym_2_31: la $2, sym_2_31
+.globl sym_2_32
+sym_2_32: la $2, sym_2_32
+.globl sym_2_33
+sym_2_33: la $2, sym_2_33
+.globl sym_2_34
+sym_2_34: la $2, sym_2_34
+.globl sym_2_35
+sym_2_35: la $2, sym_2_35
+.globl sym_2_36
+sym_2_36: la $2, sym_2_36
+.globl sym_2_37
+sym_2_37: la $2, sym_2_37
+.globl sym_2_38
+sym_2_38: la $2, sym_2_38
+.globl sym_2_39
+sym_2_39: la $2, sym_2_39
+.globl sym_2_40
+sym_2_40: la $2, sym_2_40
+.globl sym_2_41
+sym_2_41: la $2, sym_2_41
+.globl sym_2_42
+sym_2_42: la $2, sym_2_42
+.globl sym_2_43
+sym_2_43: la $2, sym_2_43
+.globl sym_2_44
+sym_2_44: la $2, sym_2_44
+.globl sym_2_45
+sym_2_45: la $2, sym_2_45
+.globl sym_2_46
+sym_2_46: la $2, sym_2_46
+.globl sym_2_47
+sym_2_47: la $2, sym_2_47
+.globl sym_2_48
+sym_2_48: la $2, sym_2_48
+.globl sym_2_49
+sym_2_49: la $2, sym_2_49
+.globl sym_2_50
+sym_2_50: la $2, sym_2_50
+.globl sym_2_51
+sym_2_51: la $2, sym_2_51
+.globl sym_2_52
+sym_2_52: la $2, sym_2_52
+.globl sym_2_53
+sym_2_53: la $2, sym_2_53
+.globl sym_2_54
+sym_2_54: la $2, sym_2_54
+.globl sym_2_55
+sym_2_55: la $2, sym_2_55
+.globl sym_2_56
+sym_2_56: la $2, sym_2_56
+.globl sym_2_57
+sym_2_57: la $2, sym_2_57
+.globl sym_2_58
+sym_2_58: la $2, sym_2_58
+.globl sym_2_59
+sym_2_59: la $2, sym_2_59
+.globl sym_2_60
+sym_2_60: la $2, sym_2_60
+.globl sym_2_61
+sym_2_61: la $2, sym_2_61
+.globl sym_2_62
+sym_2_62: la $2, sym_2_62
+.globl sym_2_63
+sym_2_63: la $2, sym_2_63
+.globl sym_2_64
+sym_2_64: la $2, sym_2_64
+.globl sym_2_65
+sym_2_65: la $2, sym_2_65
+.globl sym_2_66
+sym_2_66: la $2, sym_2_66
+.globl sym_2_67
+sym_2_67: la $2, sym_2_67
+.globl sym_2_68
+sym_2_68: la $2, sym_2_68
+.globl sym_2_69
+sym_2_69: la $2, sym_2_69
+.globl sym_2_70
+sym_2_70: la $2, sym_2_70
+.globl sym_2_71
+sym_2_71: la $2, sym_2_71
+.globl sym_2_72
+sym_2_72: la $2, sym_2_72
+.globl sym_2_73
+sym_2_73: la $2, sym_2_73
+.globl sym_2_74
+sym_2_74: la $2, sym_2_74
+.globl sym_2_75
+sym_2_75: la $2, sym_2_75
+.globl sym_2_76
+sym_2_76: la $2, sym_2_76
+.globl sym_2_77
+sym_2_77: la $2, sym_2_77
+.globl sym_2_78
+sym_2_78: la $2, sym_2_78
+.globl sym_2_79
+sym_2_79: la $2, sym_2_79
+.globl sym_2_80
+sym_2_80: la $2, sym_2_80
+.globl sym_2_81
+sym_2_81: la $2, sym_2_81
+.globl sym_2_82
+sym_2_82: la $2, sym_2_82
+.globl sym_2_83
+sym_2_83: la $2, sym_2_83
+.globl sym_2_84
+sym_2_84: la $2, sym_2_84
+.globl sym_2_85
+sym_2_85: la $2, sym_2_85
+.globl sym_2_86
+sym_2_86: la $2, sym_2_86
+.globl sym_2_87
+sym_2_87: la $2, sym_2_87
+.globl sym_2_88
+sym_2_88: la $2, sym_2_88
+.globl sym_2_89
+sym_2_89: la $2, sym_2_89
+.globl sym_2_90
+sym_2_90: la $2, sym_2_90
+.globl sym_2_91
+sym_2_91: la $2, sym_2_91
+.globl sym_2_92
+sym_2_92: la $2, sym_2_92
+.globl sym_2_93
+sym_2_93: la $2, sym_2_93
+.globl sym_2_94
+sym_2_94: la $2, sym_2_94
+.globl sym_2_95
+sym_2_95: la $2, sym_2_95
+.globl sym_2_96
+sym_2_96: la $2, sym_2_96
+.globl sym_2_97
+sym_2_97: la $2, sym_2_97
+.globl sym_2_98
+sym_2_98: la $2, sym_2_98
+.globl sym_2_99
+sym_2_99: la $2, sym_2_99
+.globl sym_2_100
+sym_2_100: la $2, sym_2_100
+.globl sym_2_101
+sym_2_101: la $2, sym_2_101
+.globl sym_2_102
+sym_2_102: la $2, sym_2_102
+.globl sym_2_103
+sym_2_103: la $2, sym_2_103
+.globl sym_2_104
+sym_2_104: la $2, sym_2_104
+.globl sym_2_105
+sym_2_105: la $2, sym_2_105
+.globl sym_2_106
+sym_2_106: la $2, sym_2_106
+.globl sym_2_107
+sym_2_107: la $2, sym_2_107
+.globl sym_2_108
+sym_2_108: la $2, sym_2_108
+.globl sym_2_109
+sym_2_109: la $2, sym_2_109
+.globl sym_2_110
+sym_2_110: la $2, sym_2_110
+.globl sym_2_111
+sym_2_111: la $2, sym_2_111
+.globl sym_2_112
+sym_2_112: la $2, sym_2_112
+.globl sym_2_113
+sym_2_113: la $2, sym_2_113
+.globl sym_2_114
+sym_2_114: la $2, sym_2_114
+.globl sym_2_115
+sym_2_115: la $2, sym_2_115
+.globl sym_2_116
+sym_2_116: la $2, sym_2_116
+.globl sym_2_117
+sym_2_117: la $2, sym_2_117
+.globl sym_2_118
+sym_2_118: la $2, sym_2_118
+.globl sym_2_119
+sym_2_119: la $2, sym_2_119
+.globl sym_2_120
+sym_2_120: la $2, sym_2_120
+.globl sym_2_121
+sym_2_121: la $2, sym_2_121
+.globl sym_2_122
+sym_2_122: la $2, sym_2_122
+.globl sym_2_123
+sym_2_123: la $2, sym_2_123
+.globl sym_2_124
+sym_2_124: la $2, sym_2_124
+.globl sym_2_125
+sym_2_125: la $2, sym_2_125
+.globl sym_2_126
+sym_2_126: la $2, sym_2_126
+.globl sym_2_127
+sym_2_127: la $2, sym_2_127
+.globl sym_2_128
+sym_2_128: la $2, sym_2_128
+.globl sym_2_129
+sym_2_129: la $2, sym_2_129
+.globl sym_2_130
+sym_2_130: la $2, sym_2_130
+.globl sym_2_131
+sym_2_131: la $2, sym_2_131
+.globl sym_2_132
+sym_2_132: la $2, sym_2_132
+.globl sym_2_133
+sym_2_133: la $2, sym_2_133
+.globl sym_2_134
+sym_2_134: la $2, sym_2_134
+.globl sym_2_135
+sym_2_135: la $2, sym_2_135
+.globl sym_2_136
+sym_2_136: la $2, sym_2_136
+.globl sym_2_137
+sym_2_137: la $2, sym_2_137
+.globl sym_2_138
+sym_2_138: la $2, sym_2_138
+.globl sym_2_139
+sym_2_139: la $2, sym_2_139
+.globl sym_2_140
+sym_2_140: la $2, sym_2_140
+.globl sym_2_141
+sym_2_141: la $2, sym_2_141
+.globl sym_2_142
+sym_2_142: la $2, sym_2_142
+.globl sym_2_143
+sym_2_143: la $2, sym_2_143
+.globl sym_2_144
+sym_2_144: la $2, sym_2_144
+.globl sym_2_145
+sym_2_145: la $2, sym_2_145
+.globl sym_2_146
+sym_2_146: la $2, sym_2_146
+.globl sym_2_147
+sym_2_147: la $2, sym_2_147
+.globl sym_2_148
+sym_2_148: la $2, sym_2_148
+.globl sym_2_149
+sym_2_149: la $2, sym_2_149
+.globl sym_2_150
+sym_2_150: la $2, sym_2_150
+.globl sym_2_151
+sym_2_151: la $2, sym_2_151
+.globl sym_2_152
+sym_2_152: la $2, sym_2_152
+.globl sym_2_153
+sym_2_153: la $2, sym_2_153
+.globl sym_2_154
+sym_2_154: la $2, sym_2_154
+.globl sym_2_155
+sym_2_155: la $2, sym_2_155
+.globl sym_2_156
+sym_2_156: la $2, sym_2_156
+.globl sym_2_157
+sym_2_157: la $2, sym_2_157
+.globl sym_2_158
+sym_2_158: la $2, sym_2_158
+.globl sym_2_159
+sym_2_159: la $2, sym_2_159
+.globl sym_2_160
+sym_2_160: la $2, sym_2_160
+.globl sym_2_161
+sym_2_161: la $2, sym_2_161
+.globl sym_2_162
+sym_2_162: la $2, sym_2_162
+.globl sym_2_163
+sym_2_163: la $2, sym_2_163
+.globl sym_2_164
+sym_2_164: la $2, sym_2_164
+.globl sym_2_165
+sym_2_165: la $2, sym_2_165
+.globl sym_2_166
+sym_2_166: la $2, sym_2_166
+.globl sym_2_167
+sym_2_167: la $2, sym_2_167
+.globl sym_2_168
+sym_2_168: la $2, sym_2_168
+.globl sym_2_169
+sym_2_169: la $2, sym_2_169
+.globl sym_2_170
+sym_2_170: la $2, sym_2_170
+.globl sym_2_171
+sym_2_171: la $2, sym_2_171
+.globl sym_2_172
+sym_2_172: la $2, sym_2_172
+.globl sym_2_173
+sym_2_173: la $2, sym_2_173
+.globl sym_2_174
+sym_2_174: la $2, sym_2_174
+.globl sym_2_175
+sym_2_175: la $2, sym_2_175
+.globl sym_2_176
+sym_2_176: la $2, sym_2_176
+.globl sym_2_177
+sym_2_177: la $2, sym_2_177
+.globl sym_2_178
+sym_2_178: la $2, sym_2_178
+.globl sym_2_179
+sym_2_179: la $2, sym_2_179
+.globl sym_2_180
+sym_2_180: la $2, sym_2_180
+.globl sym_2_181
+sym_2_181: la $2, sym_2_181
+.globl sym_2_182
+sym_2_182: la $2, sym_2_182
+.globl sym_2_183
+sym_2_183: la $2, sym_2_183
+.globl sym_2_184
+sym_2_184: la $2, sym_2_184
+.globl sym_2_185
+sym_2_185: la $2, sym_2_185
+.globl sym_2_186
+sym_2_186: la $2, sym_2_186
+.globl sym_2_187
+sym_2_187: la $2, sym_2_187
+.globl sym_2_188
+sym_2_188: la $2, sym_2_188
+.globl sym_2_189
+sym_2_189: la $2, sym_2_189
+.globl sym_2_190
+sym_2_190: la $2, sym_2_190
+.globl sym_2_191
+sym_2_191: la $2, sym_2_191
+.globl sym_2_192
+sym_2_192: la $2, sym_2_192
+.globl sym_2_193
+sym_2_193: la $2, sym_2_193
+.globl sym_2_194
+sym_2_194: la $2, sym_2_194
+.globl sym_2_195
+sym_2_195: la $2, sym_2_195
+.globl sym_2_196
+sym_2_196: la $2, sym_2_196
+.globl sym_2_197
+sym_2_197: la $2, sym_2_197
+.globl sym_2_198
+sym_2_198: la $2, sym_2_198
+.globl sym_2_199
+sym_2_199: la $2, sym_2_199
+.globl sym_2_200
+sym_2_200: la $2, sym_2_200
+.globl sym_2_201
+sym_2_201: la $2, sym_2_201
+.globl sym_2_202
+sym_2_202: la $2, sym_2_202
+.globl sym_2_203
+sym_2_203: la $2, sym_2_203
+.globl sym_2_204
+sym_2_204: la $2, sym_2_204
+.globl sym_2_205
+sym_2_205: la $2, sym_2_205
+.globl sym_2_206
+sym_2_206: la $2, sym_2_206
+.globl sym_2_207
+sym_2_207: la $2, sym_2_207
+.globl sym_2_208
+sym_2_208: la $2, sym_2_208
+.globl sym_2_209
+sym_2_209: la $2, sym_2_209
+.globl sym_2_210
+sym_2_210: la $2, sym_2_210
+.globl sym_2_211
+sym_2_211: la $2, sym_2_211
+.globl sym_2_212
+sym_2_212: la $2, sym_2_212
+.globl sym_2_213
+sym_2_213: la $2, sym_2_213
+.globl sym_2_214
+sym_2_214: la $2, sym_2_214
+.globl sym_2_215
+sym_2_215: la $2, sym_2_215
+.globl sym_2_216
+sym_2_216: la $2, sym_2_216
+.globl sym_2_217
+sym_2_217: la $2, sym_2_217
+.globl sym_2_218
+sym_2_218: la $2, sym_2_218
+.globl sym_2_219
+sym_2_219: la $2, sym_2_219
+.globl sym_2_220
+sym_2_220: la $2, sym_2_220
+.globl sym_2_221
+sym_2_221: la $2, sym_2_221
+.globl sym_2_222
+sym_2_222: la $2, sym_2_222
+.globl sym_2_223
+sym_2_223: la $2, sym_2_223
+.globl sym_2_224
+sym_2_224: la $2, sym_2_224
+.globl sym_2_225
+sym_2_225: la $2, sym_2_225
+.globl sym_2_226
+sym_2_226: la $2, sym_2_226
+.globl sym_2_227
+sym_2_227: la $2, sym_2_227
+.globl sym_2_228
+sym_2_228: la $2, sym_2_228
+.globl sym_2_229
+sym_2_229: la $2, sym_2_229
+.globl sym_2_230
+sym_2_230: la $2, sym_2_230
+.globl sym_2_231
+sym_2_231: la $2, sym_2_231
+.globl sym_2_232
+sym_2_232: la $2, sym_2_232
+.globl sym_2_233
+sym_2_233: la $2, sym_2_233
+.globl sym_2_234
+sym_2_234: la $2, sym_2_234
+.globl sym_2_235
+sym_2_235: la $2, sym_2_235
+.globl sym_2_236
+sym_2_236: la $2, sym_2_236
+.globl sym_2_237
+sym_2_237: la $2, sym_2_237
+.globl sym_2_238
+sym_2_238: la $2, sym_2_238
+.globl sym_2_239
+sym_2_239: la $2, sym_2_239
+.globl sym_2_240
+sym_2_240: la $2, sym_2_240
+.globl sym_2_241
+sym_2_241: la $2, sym_2_241
+.globl sym_2_242
+sym_2_242: la $2, sym_2_242
+.globl sym_2_243
+sym_2_243: la $2, sym_2_243
+.globl sym_2_244
+sym_2_244: la $2, sym_2_244
+.globl sym_2_245
+sym_2_245: la $2, sym_2_245
+.globl sym_2_246
+sym_2_246: la $2, sym_2_246
+.globl sym_2_247
+sym_2_247: la $2, sym_2_247
+.globl sym_2_248
+sym_2_248: la $2, sym_2_248
+.globl sym_2_249
+sym_2_249: la $2, sym_2_249
+.globl sym_2_250
+sym_2_250: la $2, sym_2_250
+.globl sym_2_251
+sym_2_251: la $2, sym_2_251
+.globl sym_2_252
+sym_2_252: la $2, sym_2_252
+.globl sym_2_253
+sym_2_253: la $2, sym_2_253
+.globl sym_2_254
+sym_2_254: la $2, sym_2_254
+.globl sym_2_255
+sym_2_255: la $2, sym_2_255
+.globl sym_2_256
+sym_2_256: la $2, sym_2_256
+.globl sym_2_257
+sym_2_257: la $2, sym_2_257
+.globl sym_2_258
+sym_2_258: la $2, sym_2_258
+.globl sym_2_259
+sym_2_259: la $2, sym_2_259
+.globl sym_2_260
+sym_2_260: la $2, sym_2_260
+.globl sym_2_261
+sym_2_261: la $2, sym_2_261
+.globl sym_2_262
+sym_2_262: la $2, sym_2_262
+.globl sym_2_263
+sym_2_263: la $2, sym_2_263
+.globl sym_2_264
+sym_2_264: la $2, sym_2_264
+.globl sym_2_265
+sym_2_265: la $2, sym_2_265
+.globl sym_2_266
+sym_2_266: la $2, sym_2_266
+.globl sym_2_267
+sym_2_267: la $2, sym_2_267
+.globl sym_2_268
+sym_2_268: la $2, sym_2_268
+.globl sym_2_269
+sym_2_269: la $2, sym_2_269
+.globl sym_2_270
+sym_2_270: la $2, sym_2_270
+.globl sym_2_271
+sym_2_271: la $2, sym_2_271
+.globl sym_2_272
+sym_2_272: la $2, sym_2_272
+.globl sym_2_273
+sym_2_273: la $2, sym_2_273
+.globl sym_2_274
+sym_2_274: la $2, sym_2_274
+.globl sym_2_275
+sym_2_275: la $2, sym_2_275
+.globl sym_2_276
+sym_2_276: la $2, sym_2_276
+.globl sym_2_277
+sym_2_277: la $2, sym_2_277
+.globl sym_2_278
+sym_2_278: la $2, sym_2_278
+.globl sym_2_279
+sym_2_279: la $2, sym_2_279
+.globl sym_2_280
+sym_2_280: la $2, sym_2_280
+.globl sym_2_281
+sym_2_281: la $2, sym_2_281
+.globl sym_2_282
+sym_2_282: la $2, sym_2_282
+.globl sym_2_283
+sym_2_283: la $2, sym_2_283
+.globl sym_2_284
+sym_2_284: la $2, sym_2_284
+.globl sym_2_285
+sym_2_285: la $2, sym_2_285
+.globl sym_2_286
+sym_2_286: la $2, sym_2_286
+.globl sym_2_287
+sym_2_287: la $2, sym_2_287
+.globl sym_2_288
+sym_2_288: la $2, sym_2_288
+.globl sym_2_289
+sym_2_289: la $2, sym_2_289
+.globl sym_2_290
+sym_2_290: la $2, sym_2_290
+.globl sym_2_291
+sym_2_291: la $2, sym_2_291
+.globl sym_2_292
+sym_2_292: la $2, sym_2_292
+.globl sym_2_293
+sym_2_293: la $2, sym_2_293
+.globl sym_2_294
+sym_2_294: la $2, sym_2_294
+.globl sym_2_295
+sym_2_295: la $2, sym_2_295
+.globl sym_2_296
+sym_2_296: la $2, sym_2_296
+.globl sym_2_297
+sym_2_297: la $2, sym_2_297
+.globl sym_2_298
+sym_2_298: la $2, sym_2_298
+.globl sym_2_299
+sym_2_299: la $2, sym_2_299
+.globl sym_2_300
+sym_2_300: la $2, sym_2_300
+.globl sym_2_301
+sym_2_301: la $2, sym_2_301
+.globl sym_2_302
+sym_2_302: la $2, sym_2_302
+.globl sym_2_303
+sym_2_303: la $2, sym_2_303
+.globl sym_2_304
+sym_2_304: la $2, sym_2_304
+.globl sym_2_305
+sym_2_305: la $2, sym_2_305
+.globl sym_2_306
+sym_2_306: la $2, sym_2_306
+.globl sym_2_307
+sym_2_307: la $2, sym_2_307
+.globl sym_2_308
+sym_2_308: la $2, sym_2_308
+.globl sym_2_309
+sym_2_309: la $2, sym_2_309
+.globl sym_2_310
+sym_2_310: la $2, sym_2_310
+.globl sym_2_311
+sym_2_311: la $2, sym_2_311
+.globl sym_2_312
+sym_2_312: la $2, sym_2_312
+.globl sym_2_313
+sym_2_313: la $2, sym_2_313
+.globl sym_2_314
+sym_2_314: la $2, sym_2_314
+.globl sym_2_315
+sym_2_315: la $2, sym_2_315
+.globl sym_2_316
+sym_2_316: la $2, sym_2_316
+.globl sym_2_317
+sym_2_317: la $2, sym_2_317
+.globl sym_2_318
+sym_2_318: la $2, sym_2_318
+.globl sym_2_319
+sym_2_319: la $2, sym_2_319
+.globl sym_2_320
+sym_2_320: la $2, sym_2_320
+.globl sym_2_321
+sym_2_321: la $2, sym_2_321
+.globl sym_2_322
+sym_2_322: la $2, sym_2_322
+.globl sym_2_323
+sym_2_323: la $2, sym_2_323
+.globl sym_2_324
+sym_2_324: la $2, sym_2_324
+.globl sym_2_325
+sym_2_325: la $2, sym_2_325
+.globl sym_2_326
+sym_2_326: la $2, sym_2_326
+.globl sym_2_327
+sym_2_327: la $2, sym_2_327
+.globl sym_2_328
+sym_2_328: la $2, sym_2_328
+.globl sym_2_329
+sym_2_329: la $2, sym_2_329
+.globl sym_2_330
+sym_2_330: la $2, sym_2_330
+.globl sym_2_331
+sym_2_331: la $2, sym_2_331
+.globl sym_2_332
+sym_2_332: la $2, sym_2_332
+.globl sym_2_333
+sym_2_333: la $2, sym_2_333
+.globl sym_2_334
+sym_2_334: la $2, sym_2_334
+.globl sym_2_335
+sym_2_335: la $2, sym_2_335
+.globl sym_2_336
+sym_2_336: la $2, sym_2_336
+.globl sym_2_337
+sym_2_337: la $2, sym_2_337
+.globl sym_2_338
+sym_2_338: la $2, sym_2_338
+.globl sym_2_339
+sym_2_339: la $2, sym_2_339
+.globl sym_2_340
+sym_2_340: la $2, sym_2_340
+.globl sym_2_341
+sym_2_341: la $2, sym_2_341
+.globl sym_2_342
+sym_2_342: la $2, sym_2_342
+.globl sym_2_343
+sym_2_343: la $2, sym_2_343
+.globl sym_2_344
+sym_2_344: la $2, sym_2_344
+.globl sym_2_345
+sym_2_345: la $2, sym_2_345
+.globl sym_2_346
+sym_2_346: la $2, sym_2_346
+.globl sym_2_347
+sym_2_347: la $2, sym_2_347
+.globl sym_2_348
+sym_2_348: la $2, sym_2_348
+.globl sym_2_349
+sym_2_349: la $2, sym_2_349
+.globl sym_2_350
+sym_2_350: la $2, sym_2_350
+.globl sym_2_351
+sym_2_351: la $2, sym_2_351
+.globl sym_2_352
+sym_2_352: la $2, sym_2_352
+.globl sym_2_353
+sym_2_353: la $2, sym_2_353
+.globl sym_2_354
+sym_2_354: la $2, sym_2_354
+.globl sym_2_355
+sym_2_355: la $2, sym_2_355
+.globl sym_2_356
+sym_2_356: la $2, sym_2_356
+.globl sym_2_357
+sym_2_357: la $2, sym_2_357
+.globl sym_2_358
+sym_2_358: la $2, sym_2_358
+.globl sym_2_359
+sym_2_359: la $2, sym_2_359
+.globl sym_2_360
+sym_2_360: la $2, sym_2_360
+.globl sym_2_361
+sym_2_361: la $2, sym_2_361
+.globl sym_2_362
+sym_2_362: la $2, sym_2_362
+.globl sym_2_363
+sym_2_363: la $2, sym_2_363
+.globl sym_2_364
+sym_2_364: la $2, sym_2_364
+.globl sym_2_365
+sym_2_365: la $2, sym_2_365
+.globl sym_2_366
+sym_2_366: la $2, sym_2_366
+.globl sym_2_367
+sym_2_367: la $2, sym_2_367
+.globl sym_2_368
+sym_2_368: la $2, sym_2_368
+.globl sym_2_369
+sym_2_369: la $2, sym_2_369
+.globl sym_2_370
+sym_2_370: la $2, sym_2_370
+.globl sym_2_371
+sym_2_371: la $2, sym_2_371
+.globl sym_2_372
+sym_2_372: la $2, sym_2_372
+.globl sym_2_373
+sym_2_373: la $2, sym_2_373
+.globl sym_2_374
+sym_2_374: la $2, sym_2_374
+.globl sym_2_375
+sym_2_375: la $2, sym_2_375
+.globl sym_2_376
+sym_2_376: la $2, sym_2_376
+.globl sym_2_377
+sym_2_377: la $2, sym_2_377
+.globl sym_2_378
+sym_2_378: la $2, sym_2_378
+.globl sym_2_379
+sym_2_379: la $2, sym_2_379
+.globl sym_2_380
+sym_2_380: la $2, sym_2_380
+.globl sym_2_381
+sym_2_381: la $2, sym_2_381
+.globl sym_2_382
+sym_2_382: la $2, sym_2_382
+.globl sym_2_383
+sym_2_383: la $2, sym_2_383
+.globl sym_2_384
+sym_2_384: la $2, sym_2_384
+.globl sym_2_385
+sym_2_385: la $2, sym_2_385
+.globl sym_2_386
+sym_2_386: la $2, sym_2_386
+.globl sym_2_387
+sym_2_387: la $2, sym_2_387
+.globl sym_2_388
+sym_2_388: la $2, sym_2_388
+.globl sym_2_389
+sym_2_389: la $2, sym_2_389
+.globl sym_2_390
+sym_2_390: la $2, sym_2_390
+.globl sym_2_391
+sym_2_391: la $2, sym_2_391
+.globl sym_2_392
+sym_2_392: la $2, sym_2_392
+.globl sym_2_393
+sym_2_393: la $2, sym_2_393
+.globl sym_2_394
+sym_2_394: la $2, sym_2_394
+.globl sym_2_395
+sym_2_395: la $2, sym_2_395
+.globl sym_2_396
+sym_2_396: la $2, sym_2_396
+.globl sym_2_397
+sym_2_397: la $2, sym_2_397
+.globl sym_2_398
+sym_2_398: la $2, sym_2_398
+.globl sym_2_399
+sym_2_399: la $2, sym_2_399
+.globl sym_2_400
+sym_2_400: la $2, sym_2_400
+.globl sym_2_401
+sym_2_401: la $2, sym_2_401
+.globl sym_2_402
+sym_2_402: la $2, sym_2_402
+.globl sym_2_403
+sym_2_403: la $2, sym_2_403
+.globl sym_2_404
+sym_2_404: la $2, sym_2_404
+.globl sym_2_405
+sym_2_405: la $2, sym_2_405
+.globl sym_2_406
+sym_2_406: la $2, sym_2_406
+.globl sym_2_407
+sym_2_407: la $2, sym_2_407
+.globl sym_2_408
+sym_2_408: la $2, sym_2_408
+.globl sym_2_409
+sym_2_409: la $2, sym_2_409
+.globl sym_2_410
+sym_2_410: la $2, sym_2_410
+.globl sym_2_411
+sym_2_411: la $2, sym_2_411
+.globl sym_2_412
+sym_2_412: la $2, sym_2_412
+.globl sym_2_413
+sym_2_413: la $2, sym_2_413
+.globl sym_2_414
+sym_2_414: la $2, sym_2_414
+.globl sym_2_415
+sym_2_415: la $2, sym_2_415
+.globl sym_2_416
+sym_2_416: la $2, sym_2_416
+.globl sym_2_417
+sym_2_417: la $2, sym_2_417
+.globl sym_2_418
+sym_2_418: la $2, sym_2_418
+.globl sym_2_419
+sym_2_419: la $2, sym_2_419
+.globl sym_2_420
+sym_2_420: la $2, sym_2_420
+.globl sym_2_421
+sym_2_421: la $2, sym_2_421
+.globl sym_2_422
+sym_2_422: la $2, sym_2_422
+.globl sym_2_423
+sym_2_423: la $2, sym_2_423
+.globl sym_2_424
+sym_2_424: la $2, sym_2_424
+.globl sym_2_425
+sym_2_425: la $2, sym_2_425
+.globl sym_2_426
+sym_2_426: la $2, sym_2_426
+.globl sym_2_427
+sym_2_427: la $2, sym_2_427
+.globl sym_2_428
+sym_2_428: la $2, sym_2_428
+.globl sym_2_429
+sym_2_429: la $2, sym_2_429
+.globl sym_2_430
+sym_2_430: la $2, sym_2_430
+.globl sym_2_431
+sym_2_431: la $2, sym_2_431
+.globl sym_2_432
+sym_2_432: la $2, sym_2_432
+.globl sym_2_433
+sym_2_433: la $2, sym_2_433
+.globl sym_2_434
+sym_2_434: la $2, sym_2_434
+.globl sym_2_435
+sym_2_435: la $2, sym_2_435
+.globl sym_2_436
+sym_2_436: la $2, sym_2_436
+.globl sym_2_437
+sym_2_437: la $2, sym_2_437
+.globl sym_2_438
+sym_2_438: la $2, sym_2_438
+.globl sym_2_439
+sym_2_439: la $2, sym_2_439
+.globl sym_2_440
+sym_2_440: la $2, sym_2_440
+.globl sym_2_441
+sym_2_441: la $2, sym_2_441
+.globl sym_2_442
+sym_2_442: la $2, sym_2_442
+.globl sym_2_443
+sym_2_443: la $2, sym_2_443
+.globl sym_2_444
+sym_2_444: la $2, sym_2_444
+.globl sym_2_445
+sym_2_445: la $2, sym_2_445
+.globl sym_2_446
+sym_2_446: la $2, sym_2_446
+.globl sym_2_447
+sym_2_447: la $2, sym_2_447
+.globl sym_2_448
+sym_2_448: la $2, sym_2_448
+.globl sym_2_449
+sym_2_449: la $2, sym_2_449
+.globl sym_2_450
+sym_2_450: la $2, sym_2_450
+.globl sym_2_451
+sym_2_451: la $2, sym_2_451
+.globl sym_2_452
+sym_2_452: la $2, sym_2_452
+.globl sym_2_453
+sym_2_453: la $2, sym_2_453
+.globl sym_2_454
+sym_2_454: la $2, sym_2_454
+.globl sym_2_455
+sym_2_455: la $2, sym_2_455
+.globl sym_2_456
+sym_2_456: la $2, sym_2_456
+.globl sym_2_457
+sym_2_457: la $2, sym_2_457
+.globl sym_2_458
+sym_2_458: la $2, sym_2_458
+.globl sym_2_459
+sym_2_459: la $2, sym_2_459
+.globl sym_2_460
+sym_2_460: la $2, sym_2_460
+.globl sym_2_461
+sym_2_461: la $2, sym_2_461
+.globl sym_2_462
+sym_2_462: la $2, sym_2_462
+.globl sym_2_463
+sym_2_463: la $2, sym_2_463
+.globl sym_2_464
+sym_2_464: la $2, sym_2_464
+.globl sym_2_465
+sym_2_465: la $2, sym_2_465
+.globl sym_2_466
+sym_2_466: la $2, sym_2_466
+.globl sym_2_467
+sym_2_467: la $2, sym_2_467
+.globl sym_2_468
+sym_2_468: la $2, sym_2_468
+.globl sym_2_469
+sym_2_469: la $2, sym_2_469
+.globl sym_2_470
+sym_2_470: la $2, sym_2_470
+.globl sym_2_471
+sym_2_471: la $2, sym_2_471
+.globl sym_2_472
+sym_2_472: la $2, sym_2_472
+.globl sym_2_473
+sym_2_473: la $2, sym_2_473
+.globl sym_2_474
+sym_2_474: la $2, sym_2_474
+.globl sym_2_475
+sym_2_475: la $2, sym_2_475
+.globl sym_2_476
+sym_2_476: la $2, sym_2_476
+.globl sym_2_477
+sym_2_477: la $2, sym_2_477
+.globl sym_2_478
+sym_2_478: la $2, sym_2_478
+.globl sym_2_479
+sym_2_479: la $2, sym_2_479
+.globl sym_2_480
+sym_2_480: la $2, sym_2_480
+.globl sym_2_481
+sym_2_481: la $2, sym_2_481
+.globl sym_2_482
+sym_2_482: la $2, sym_2_482
+.globl sym_2_483
+sym_2_483: la $2, sym_2_483
+.globl sym_2_484
+sym_2_484: la $2, sym_2_484
+.globl sym_2_485
+sym_2_485: la $2, sym_2_485
+.globl sym_2_486
+sym_2_486: la $2, sym_2_486
+.globl sym_2_487
+sym_2_487: la $2, sym_2_487
+.globl sym_2_488
+sym_2_488: la $2, sym_2_488
+.globl sym_2_489
+sym_2_489: la $2, sym_2_489
+.globl sym_2_490
+sym_2_490: la $2, sym_2_490
+.globl sym_2_491
+sym_2_491: la $2, sym_2_491
+.globl sym_2_492
+sym_2_492: la $2, sym_2_492
+.globl sym_2_493
+sym_2_493: la $2, sym_2_493
+.globl sym_2_494
+sym_2_494: la $2, sym_2_494
+.globl sym_2_495
+sym_2_495: la $2, sym_2_495
+.globl sym_2_496
+sym_2_496: la $2, sym_2_496
+.globl sym_2_497
+sym_2_497: la $2, sym_2_497
+.globl sym_2_498
+sym_2_498: la $2, sym_2_498
+.globl sym_2_499
+sym_2_499: la $2, sym_2_499
+.globl sym_2_500
+sym_2_500: la $2, sym_2_500
+.globl sym_2_501
+sym_2_501: la $2, sym_2_501
+.globl sym_2_502
+sym_2_502: la $2, sym_2_502
+.globl sym_2_503
+sym_2_503: la $2, sym_2_503
+.globl sym_2_504
+sym_2_504: la $2, sym_2_504
+.globl sym_2_505
+sym_2_505: la $2, sym_2_505
+.globl sym_2_506
+sym_2_506: la $2, sym_2_506
+.globl sym_2_507
+sym_2_507: la $2, sym_2_507
+.globl sym_2_508
+sym_2_508: la $2, sym_2_508
+.globl sym_2_509
+sym_2_509: la $2, sym_2_509
+.globl sym_2_510
+sym_2_510: la $2, sym_2_510
+.globl sym_2_511
+sym_2_511: la $2, sym_2_511
+.globl sym_2_512
+sym_2_512: la $2, sym_2_512
+.globl sym_2_513
+sym_2_513: la $2, sym_2_513
+.globl sym_2_514
+sym_2_514: la $2, sym_2_514
+.globl sym_2_515
+sym_2_515: la $2, sym_2_515
+.globl sym_2_516
+sym_2_516: la $2, sym_2_516
+.globl sym_2_517
+sym_2_517: la $2, sym_2_517
+.globl sym_2_518
+sym_2_518: la $2, sym_2_518
+.globl sym_2_519
+sym_2_519: la $2, sym_2_519
+.globl sym_2_520
+sym_2_520: la $2, sym_2_520
+.globl sym_2_521
+sym_2_521: la $2, sym_2_521
+.globl sym_2_522
+sym_2_522: la $2, sym_2_522
+.globl sym_2_523
+sym_2_523: la $2, sym_2_523
+.globl sym_2_524
+sym_2_524: la $2, sym_2_524
+.globl sym_2_525
+sym_2_525: la $2, sym_2_525
+.globl sym_2_526
+sym_2_526: la $2, sym_2_526
+.globl sym_2_527
+sym_2_527: la $2, sym_2_527
+.globl sym_2_528
+sym_2_528: la $2, sym_2_528
+.globl sym_2_529
+sym_2_529: la $2, sym_2_529
+.globl sym_2_530
+sym_2_530: la $2, sym_2_530
+.globl sym_2_531
+sym_2_531: la $2, sym_2_531
+.globl sym_2_532
+sym_2_532: la $2, sym_2_532
+.globl sym_2_533
+sym_2_533: la $2, sym_2_533
+.globl sym_2_534
+sym_2_534: la $2, sym_2_534
+.globl sym_2_535
+sym_2_535: la $2, sym_2_535
+.globl sym_2_536
+sym_2_536: la $2, sym_2_536
+.globl sym_2_537
+sym_2_537: la $2, sym_2_537
+.globl sym_2_538
+sym_2_538: la $2, sym_2_538
+.globl sym_2_539
+sym_2_539: la $2, sym_2_539
+.globl sym_2_540
+sym_2_540: la $2, sym_2_540
+.globl sym_2_541
+sym_2_541: la $2, sym_2_541
+.globl sym_2_542
+sym_2_542: la $2, sym_2_542
+.globl sym_2_543
+sym_2_543: la $2, sym_2_543
+.globl sym_2_544
+sym_2_544: la $2, sym_2_544
+.globl sym_2_545
+sym_2_545: la $2, sym_2_545
+.globl sym_2_546
+sym_2_546: la $2, sym_2_546
+.globl sym_2_547
+sym_2_547: la $2, sym_2_547
+.globl sym_2_548
+sym_2_548: la $2, sym_2_548
+.globl sym_2_549
+sym_2_549: la $2, sym_2_549
+.globl sym_2_550
+sym_2_550: la $2, sym_2_550
+.globl sym_2_551
+sym_2_551: la $2, sym_2_551
+.globl sym_2_552
+sym_2_552: la $2, sym_2_552
+.globl sym_2_553
+sym_2_553: la $2, sym_2_553
+.globl sym_2_554
+sym_2_554: la $2, sym_2_554
+.globl sym_2_555
+sym_2_555: la $2, sym_2_555
+.globl sym_2_556
+sym_2_556: la $2, sym_2_556
+.globl sym_2_557
+sym_2_557: la $2, sym_2_557
+.globl sym_2_558
+sym_2_558: la $2, sym_2_558
+.globl sym_2_559
+sym_2_559: la $2, sym_2_559
+.globl sym_2_560
+sym_2_560: la $2, sym_2_560
+.globl sym_2_561
+sym_2_561: la $2, sym_2_561
+.globl sym_2_562
+sym_2_562: la $2, sym_2_562
+.globl sym_2_563
+sym_2_563: la $2, sym_2_563
+.globl sym_2_564
+sym_2_564: la $2, sym_2_564
+.globl sym_2_565
+sym_2_565: la $2, sym_2_565
+.globl sym_2_566
+sym_2_566: la $2, sym_2_566
+.globl sym_2_567
+sym_2_567: la $2, sym_2_567
+.globl sym_2_568
+sym_2_568: la $2, sym_2_568
+.globl sym_2_569
+sym_2_569: la $2, sym_2_569
+.globl sym_2_570
+sym_2_570: la $2, sym_2_570
+.globl sym_2_571
+sym_2_571: la $2, sym_2_571
+.globl sym_2_572
+sym_2_572: la $2, sym_2_572
+.globl sym_2_573
+sym_2_573: la $2, sym_2_573
+.globl sym_2_574
+sym_2_574: la $2, sym_2_574
+.globl sym_2_575
+sym_2_575: la $2, sym_2_575
+.globl sym_2_576
+sym_2_576: la $2, sym_2_576
+.globl sym_2_577
+sym_2_577: la $2, sym_2_577
+.globl sym_2_578
+sym_2_578: la $2, sym_2_578
+.globl sym_2_579
+sym_2_579: la $2, sym_2_579
+.globl sym_2_580
+sym_2_580: la $2, sym_2_580
+.globl sym_2_581
+sym_2_581: la $2, sym_2_581
+.globl sym_2_582
+sym_2_582: la $2, sym_2_582
+.globl sym_2_583
+sym_2_583: la $2, sym_2_583
+.globl sym_2_584
+sym_2_584: la $2, sym_2_584
+.globl sym_2_585
+sym_2_585: la $2, sym_2_585
+.globl sym_2_586
+sym_2_586: la $2, sym_2_586
+.globl sym_2_587
+sym_2_587: la $2, sym_2_587
+.globl sym_2_588
+sym_2_588: la $2, sym_2_588
+.globl sym_2_589
+sym_2_589: la $2, sym_2_589
+.globl sym_2_590
+sym_2_590: la $2, sym_2_590
+.globl sym_2_591
+sym_2_591: la $2, sym_2_591
+.globl sym_2_592
+sym_2_592: la $2, sym_2_592
+.globl sym_2_593
+sym_2_593: la $2, sym_2_593
+.globl sym_2_594
+sym_2_594: la $2, sym_2_594
+.globl sym_2_595
+sym_2_595: la $2, sym_2_595
+.globl sym_2_596
+sym_2_596: la $2, sym_2_596
+.globl sym_2_597
+sym_2_597: la $2, sym_2_597
+.globl sym_2_598
+sym_2_598: la $2, sym_2_598
+.globl sym_2_599
+sym_2_599: la $2, sym_2_599
+.globl sym_2_600
+sym_2_600: la $2, sym_2_600
+.globl sym_2_601
+sym_2_601: la $2, sym_2_601
+.globl sym_2_602
+sym_2_602: la $2, sym_2_602
+.globl sym_2_603
+sym_2_603: la $2, sym_2_603
+.globl sym_2_604
+sym_2_604: la $2, sym_2_604
+.globl sym_2_605
+sym_2_605: la $2, sym_2_605
+.globl sym_2_606
+sym_2_606: la $2, sym_2_606
+.globl sym_2_607
+sym_2_607: la $2, sym_2_607
+.globl sym_2_608
+sym_2_608: la $2, sym_2_608
+.globl sym_2_609
+sym_2_609: la $2, sym_2_609
+.globl sym_2_610
+sym_2_610: la $2, sym_2_610
+.globl sym_2_611
+sym_2_611: la $2, sym_2_611
+.globl sym_2_612
+sym_2_612: la $2, sym_2_612
+.globl sym_2_613
+sym_2_613: la $2, sym_2_613
+.globl sym_2_614
+sym_2_614: la $2, sym_2_614
+.globl sym_2_615
+sym_2_615: la $2, sym_2_615
+.globl sym_2_616
+sym_2_616: la $2, sym_2_616
+.globl sym_2_617
+sym_2_617: la $2, sym_2_617
+.globl sym_2_618
+sym_2_618: la $2, sym_2_618
+.globl sym_2_619
+sym_2_619: la $2, sym_2_619
+.globl sym_2_620
+sym_2_620: la $2, sym_2_620
+.globl sym_2_621
+sym_2_621: la $2, sym_2_621
+.globl sym_2_622
+sym_2_622: la $2, sym_2_622
+.globl sym_2_623
+sym_2_623: la $2, sym_2_623
+.globl sym_2_624
+sym_2_624: la $2, sym_2_624
+.globl sym_2_625
+sym_2_625: la $2, sym_2_625
+.globl sym_2_626
+sym_2_626: la $2, sym_2_626
+.globl sym_2_627
+sym_2_627: la $2, sym_2_627
+.globl sym_2_628
+sym_2_628: la $2, sym_2_628
+.globl sym_2_629
+sym_2_629: la $2, sym_2_629
+.globl sym_2_630
+sym_2_630: la $2, sym_2_630
+.globl sym_2_631
+sym_2_631: la $2, sym_2_631
+.globl sym_2_632
+sym_2_632: la $2, sym_2_632
+.globl sym_2_633
+sym_2_633: la $2, sym_2_633
+.globl sym_2_634
+sym_2_634: la $2, sym_2_634
+.globl sym_2_635
+sym_2_635: la $2, sym_2_635
+.globl sym_2_636
+sym_2_636: la $2, sym_2_636
+.globl sym_2_637
+sym_2_637: la $2, sym_2_637
+.globl sym_2_638
+sym_2_638: la $2, sym_2_638
+.globl sym_2_639
+sym_2_639: la $2, sym_2_639
+.globl sym_2_640
+sym_2_640: la $2, sym_2_640
+.globl sym_2_641
+sym_2_641: la $2, sym_2_641
+.globl sym_2_642
+sym_2_642: la $2, sym_2_642
+.globl sym_2_643
+sym_2_643: la $2, sym_2_643
+.globl sym_2_644
+sym_2_644: la $2, sym_2_644
+.globl sym_2_645
+sym_2_645: la $2, sym_2_645
+.globl sym_2_646
+sym_2_646: la $2, sym_2_646
+.globl sym_2_647
+sym_2_647: la $2, sym_2_647
+.globl sym_2_648
+sym_2_648: la $2, sym_2_648
+.globl sym_2_649
+sym_2_649: la $2, sym_2_649
+.globl sym_2_650
+sym_2_650: la $2, sym_2_650
+.globl sym_2_651
+sym_2_651: la $2, sym_2_651
+.globl sym_2_652
+sym_2_652: la $2, sym_2_652
+.globl sym_2_653
+sym_2_653: la $2, sym_2_653
+.globl sym_2_654
+sym_2_654: la $2, sym_2_654
+.globl sym_2_655
+sym_2_655: la $2, sym_2_655
+.globl sym_2_656
+sym_2_656: la $2, sym_2_656
+.globl sym_2_657
+sym_2_657: la $2, sym_2_657
+.globl sym_2_658
+sym_2_658: la $2, sym_2_658
+.globl sym_2_659
+sym_2_659: la $2, sym_2_659
+.globl sym_2_660
+sym_2_660: la $2, sym_2_660
+.globl sym_2_661
+sym_2_661: la $2, sym_2_661
+.globl sym_2_662
+sym_2_662: la $2, sym_2_662
+.globl sym_2_663
+sym_2_663: la $2, sym_2_663
+.globl sym_2_664
+sym_2_664: la $2, sym_2_664
+.globl sym_2_665
+sym_2_665: la $2, sym_2_665
+.globl sym_2_666
+sym_2_666: la $2, sym_2_666
+.globl sym_2_667
+sym_2_667: la $2, sym_2_667
+.globl sym_2_668
+sym_2_668: la $2, sym_2_668
+.globl sym_2_669
+sym_2_669: la $2, sym_2_669
+.globl sym_2_670
+sym_2_670: la $2, sym_2_670
+.globl sym_2_671
+sym_2_671: la $2, sym_2_671
+.globl sym_2_672
+sym_2_672: la $2, sym_2_672
+.globl sym_2_673
+sym_2_673: la $2, sym_2_673
+.globl sym_2_674
+sym_2_674: la $2, sym_2_674
+.globl sym_2_675
+sym_2_675: la $2, sym_2_675
+.globl sym_2_676
+sym_2_676: la $2, sym_2_676
+.globl sym_2_677
+sym_2_677: la $2, sym_2_677
+.globl sym_2_678
+sym_2_678: la $2, sym_2_678
+.globl sym_2_679
+sym_2_679: la $2, sym_2_679
+.globl sym_2_680
+sym_2_680: la $2, sym_2_680
+.globl sym_2_681
+sym_2_681: la $2, sym_2_681
+.globl sym_2_682
+sym_2_682: la $2, sym_2_682
+.globl sym_2_683
+sym_2_683: la $2, sym_2_683
+.globl sym_2_684
+sym_2_684: la $2, sym_2_684
+.globl sym_2_685
+sym_2_685: la $2, sym_2_685
+.globl sym_2_686
+sym_2_686: la $2, sym_2_686
+.globl sym_2_687
+sym_2_687: la $2, sym_2_687
+.globl sym_2_688
+sym_2_688: la $2, sym_2_688
+.globl sym_2_689
+sym_2_689: la $2, sym_2_689
+.globl sym_2_690
+sym_2_690: la $2, sym_2_690
+.globl sym_2_691
+sym_2_691: la $2, sym_2_691
+.globl sym_2_692
+sym_2_692: la $2, sym_2_692
+.globl sym_2_693
+sym_2_693: la $2, sym_2_693
+.globl sym_2_694
+sym_2_694: la $2, sym_2_694
+.globl sym_2_695
+sym_2_695: la $2, sym_2_695
+.globl sym_2_696
+sym_2_696: la $2, sym_2_696
+.globl sym_2_697
+sym_2_697: la $2, sym_2_697
+.globl sym_2_698
+sym_2_698: la $2, sym_2_698
+.globl sym_2_699
+sym_2_699: la $2, sym_2_699
+.globl sym_2_700
+sym_2_700: la $2, sym_2_700
+.globl sym_2_701
+sym_2_701: la $2, sym_2_701
+.globl sym_2_702
+sym_2_702: la $2, sym_2_702
+.globl sym_2_703
+sym_2_703: la $2, sym_2_703
+.globl sym_2_704
+sym_2_704: la $2, sym_2_704
+.globl sym_2_705
+sym_2_705: la $2, sym_2_705
+.globl sym_2_706
+sym_2_706: la $2, sym_2_706
+.globl sym_2_707
+sym_2_707: la $2, sym_2_707
+.globl sym_2_708
+sym_2_708: la $2, sym_2_708
+.globl sym_2_709
+sym_2_709: la $2, sym_2_709
+.globl sym_2_710
+sym_2_710: la $2, sym_2_710
+.globl sym_2_711
+sym_2_711: la $2, sym_2_711
+.globl sym_2_712
+sym_2_712: la $2, sym_2_712
+.globl sym_2_713
+sym_2_713: la $2, sym_2_713
+.globl sym_2_714
+sym_2_714: la $2, sym_2_714
+.globl sym_2_715
+sym_2_715: la $2, sym_2_715
+.globl sym_2_716
+sym_2_716: la $2, sym_2_716
+.globl sym_2_717
+sym_2_717: la $2, sym_2_717
+.globl sym_2_718
+sym_2_718: la $2, sym_2_718
+.globl sym_2_719
+sym_2_719: la $2, sym_2_719
+.globl sym_2_720
+sym_2_720: la $2, sym_2_720
+.globl sym_2_721
+sym_2_721: la $2, sym_2_721
+.globl sym_2_722
+sym_2_722: la $2, sym_2_722
+.globl sym_2_723
+sym_2_723: la $2, sym_2_723
+.globl sym_2_724
+sym_2_724: la $2, sym_2_724
+.globl sym_2_725
+sym_2_725: la $2, sym_2_725
+.globl sym_2_726
+sym_2_726: la $2, sym_2_726
+.globl sym_2_727
+sym_2_727: la $2, sym_2_727
+.globl sym_2_728
+sym_2_728: la $2, sym_2_728
+.globl sym_2_729
+sym_2_729: la $2, sym_2_729
+.globl sym_2_730
+sym_2_730: la $2, sym_2_730
+.globl sym_2_731
+sym_2_731: la $2, sym_2_731
+.globl sym_2_732
+sym_2_732: la $2, sym_2_732
+.globl sym_2_733
+sym_2_733: la $2, sym_2_733
+.globl sym_2_734
+sym_2_734: la $2, sym_2_734
+.globl sym_2_735
+sym_2_735: la $2, sym_2_735
+.globl sym_2_736
+sym_2_736: la $2, sym_2_736
+.globl sym_2_737
+sym_2_737: la $2, sym_2_737
+.globl sym_2_738
+sym_2_738: la $2, sym_2_738
+.globl sym_2_739
+sym_2_739: la $2, sym_2_739
+.globl sym_2_740
+sym_2_740: la $2, sym_2_740
+.globl sym_2_741
+sym_2_741: la $2, sym_2_741
+.globl sym_2_742
+sym_2_742: la $2, sym_2_742
+.globl sym_2_743
+sym_2_743: la $2, sym_2_743
+.globl sym_2_744
+sym_2_744: la $2, sym_2_744
+.globl sym_2_745
+sym_2_745: la $2, sym_2_745
+.globl sym_2_746
+sym_2_746: la $2, sym_2_746
+.globl sym_2_747
+sym_2_747: la $2, sym_2_747
+.globl sym_2_748
+sym_2_748: la $2, sym_2_748
+.globl sym_2_749
+sym_2_749: la $2, sym_2_749
+.globl sym_2_750
+sym_2_750: la $2, sym_2_750
+.globl sym_2_751
+sym_2_751: la $2, sym_2_751
+.globl sym_2_752
+sym_2_752: la $2, sym_2_752
+.globl sym_2_753
+sym_2_753: la $2, sym_2_753
+.globl sym_2_754
+sym_2_754: la $2, sym_2_754
+.globl sym_2_755
+sym_2_755: la $2, sym_2_755
+.globl sym_2_756
+sym_2_756: la $2, sym_2_756
+.globl sym_2_757
+sym_2_757: la $2, sym_2_757
+.globl sym_2_758
+sym_2_758: la $2, sym_2_758
+.globl sym_2_759
+sym_2_759: la $2, sym_2_759
+.globl sym_2_760
+sym_2_760: la $2, sym_2_760
+.globl sym_2_761
+sym_2_761: la $2, sym_2_761
+.globl sym_2_762
+sym_2_762: la $2, sym_2_762
+.globl sym_2_763
+sym_2_763: la $2, sym_2_763
+.globl sym_2_764
+sym_2_764: la $2, sym_2_764
+.globl sym_2_765
+sym_2_765: la $2, sym_2_765
+.globl sym_2_766
+sym_2_766: la $2, sym_2_766
+.globl sym_2_767
+sym_2_767: la $2, sym_2_767
+.globl sym_2_768
+sym_2_768: la $2, sym_2_768
+.globl sym_2_769
+sym_2_769: la $2, sym_2_769
+.globl sym_2_770
+sym_2_770: la $2, sym_2_770
+.globl sym_2_771
+sym_2_771: la $2, sym_2_771
+.globl sym_2_772
+sym_2_772: la $2, sym_2_772
+.globl sym_2_773
+sym_2_773: la $2, sym_2_773
+.globl sym_2_774
+sym_2_774: la $2, sym_2_774
+.globl sym_2_775
+sym_2_775: la $2, sym_2_775
+.globl sym_2_776
+sym_2_776: la $2, sym_2_776
+.globl sym_2_777
+sym_2_777: la $2, sym_2_777
+.globl sym_2_778
+sym_2_778: la $2, sym_2_778
+.globl sym_2_779
+sym_2_779: la $2, sym_2_779
+.globl sym_2_780
+sym_2_780: la $2, sym_2_780
+.globl sym_2_781
+sym_2_781: la $2, sym_2_781
+.globl sym_2_782
+sym_2_782: la $2, sym_2_782
+.globl sym_2_783
+sym_2_783: la $2, sym_2_783
+.globl sym_2_784
+sym_2_784: la $2, sym_2_784
+.globl sym_2_785
+sym_2_785: la $2, sym_2_785
+.globl sym_2_786
+sym_2_786: la $2, sym_2_786
+.globl sym_2_787
+sym_2_787: la $2, sym_2_787
+.globl sym_2_788
+sym_2_788: la $2, sym_2_788
+.globl sym_2_789
+sym_2_789: la $2, sym_2_789
+.globl sym_2_790
+sym_2_790: la $2, sym_2_790
+.globl sym_2_791
+sym_2_791: la $2, sym_2_791
+.globl sym_2_792
+sym_2_792: la $2, sym_2_792
+.globl sym_2_793
+sym_2_793: la $2, sym_2_793
+.globl sym_2_794
+sym_2_794: la $2, sym_2_794
+.globl sym_2_795
+sym_2_795: la $2, sym_2_795
+.globl sym_2_796
+sym_2_796: la $2, sym_2_796
+.globl sym_2_797
+sym_2_797: la $2, sym_2_797
+.globl sym_2_798
+sym_2_798: la $2, sym_2_798
+.globl sym_2_799
+sym_2_799: la $2, sym_2_799
+.globl sym_2_800
+sym_2_800: la $2, sym_2_800
+.globl sym_2_801
+sym_2_801: la $2, sym_2_801
+.globl sym_2_802
+sym_2_802: la $2, sym_2_802
+.globl sym_2_803
+sym_2_803: la $2, sym_2_803
+.globl sym_2_804
+sym_2_804: la $2, sym_2_804
+.globl sym_2_805
+sym_2_805: la $2, sym_2_805
+.globl sym_2_806
+sym_2_806: la $2, sym_2_806
+.globl sym_2_807
+sym_2_807: la $2, sym_2_807
+.globl sym_2_808
+sym_2_808: la $2, sym_2_808
+.globl sym_2_809
+sym_2_809: la $2, sym_2_809
+.globl sym_2_810
+sym_2_810: la $2, sym_2_810
+.globl sym_2_811
+sym_2_811: la $2, sym_2_811
+.globl sym_2_812
+sym_2_812: la $2, sym_2_812
+.globl sym_2_813
+sym_2_813: la $2, sym_2_813
+.globl sym_2_814
+sym_2_814: la $2, sym_2_814
+.globl sym_2_815
+sym_2_815: la $2, sym_2_815
+.globl sym_2_816
+sym_2_816: la $2, sym_2_816
+.globl sym_2_817
+sym_2_817: la $2, sym_2_817
+.globl sym_2_818
+sym_2_818: la $2, sym_2_818
+.globl sym_2_819
+sym_2_819: la $2, sym_2_819
+.globl sym_2_820
+sym_2_820: la $2, sym_2_820
+.globl sym_2_821
+sym_2_821: la $2, sym_2_821
+.globl sym_2_822
+sym_2_822: la $2, sym_2_822
+.globl sym_2_823
+sym_2_823: la $2, sym_2_823
+.globl sym_2_824
+sym_2_824: la $2, sym_2_824
+.globl sym_2_825
+sym_2_825: la $2, sym_2_825
+.globl sym_2_826
+sym_2_826: la $2, sym_2_826
+.globl sym_2_827
+sym_2_827: la $2, sym_2_827
+.globl sym_2_828
+sym_2_828: la $2, sym_2_828
+.globl sym_2_829
+sym_2_829: la $2, sym_2_829
+.globl sym_2_830
+sym_2_830: la $2, sym_2_830
+.globl sym_2_831
+sym_2_831: la $2, sym_2_831
+.globl sym_2_832
+sym_2_832: la $2, sym_2_832
+.globl sym_2_833
+sym_2_833: la $2, sym_2_833
+.globl sym_2_834
+sym_2_834: la $2, sym_2_834
+.globl sym_2_835
+sym_2_835: la $2, sym_2_835
+.globl sym_2_836
+sym_2_836: la $2, sym_2_836
+.globl sym_2_837
+sym_2_837: la $2, sym_2_837
+.globl sym_2_838
+sym_2_838: la $2, sym_2_838
+.globl sym_2_839
+sym_2_839: la $2, sym_2_839
+.globl sym_2_840
+sym_2_840: la $2, sym_2_840
+.globl sym_2_841
+sym_2_841: la $2, sym_2_841
+.globl sym_2_842
+sym_2_842: la $2, sym_2_842
+.globl sym_2_843
+sym_2_843: la $2, sym_2_843
+.globl sym_2_844
+sym_2_844: la $2, sym_2_844
+.globl sym_2_845
+sym_2_845: la $2, sym_2_845
+.globl sym_2_846
+sym_2_846: la $2, sym_2_846
+.globl sym_2_847
+sym_2_847: la $2, sym_2_847
+.globl sym_2_848
+sym_2_848: la $2, sym_2_848
+.globl sym_2_849
+sym_2_849: la $2, sym_2_849
+.globl sym_2_850
+sym_2_850: la $2, sym_2_850
+.globl sym_2_851
+sym_2_851: la $2, sym_2_851
+.globl sym_2_852
+sym_2_852: la $2, sym_2_852
+.globl sym_2_853
+sym_2_853: la $2, sym_2_853
+.globl sym_2_854
+sym_2_854: la $2, sym_2_854
+.globl sym_2_855
+sym_2_855: la $2, sym_2_855
+.globl sym_2_856
+sym_2_856: la $2, sym_2_856
+.globl sym_2_857
+sym_2_857: la $2, sym_2_857
+.globl sym_2_858
+sym_2_858: la $2, sym_2_858
+.globl sym_2_859
+sym_2_859: la $2, sym_2_859
+.globl sym_2_860
+sym_2_860: la $2, sym_2_860
+.globl sym_2_861
+sym_2_861: la $2, sym_2_861
+.globl sym_2_862
+sym_2_862: la $2, sym_2_862
+.globl sym_2_863
+sym_2_863: la $2, sym_2_863
+.globl sym_2_864
+sym_2_864: la $2, sym_2_864
+.globl sym_2_865
+sym_2_865: la $2, sym_2_865
+.globl sym_2_866
+sym_2_866: la $2, sym_2_866
+.globl sym_2_867
+sym_2_867: la $2, sym_2_867
+.globl sym_2_868
+sym_2_868: la $2, sym_2_868
+.globl sym_2_869
+sym_2_869: la $2, sym_2_869
+.globl sym_2_870
+sym_2_870: la $2, sym_2_870
+.globl sym_2_871
+sym_2_871: la $2, sym_2_871
+.globl sym_2_872
+sym_2_872: la $2, sym_2_872
+.globl sym_2_873
+sym_2_873: la $2, sym_2_873
+.globl sym_2_874
+sym_2_874: la $2, sym_2_874
+.globl sym_2_875
+sym_2_875: la $2, sym_2_875
+.globl sym_2_876
+sym_2_876: la $2, sym_2_876
+.globl sym_2_877
+sym_2_877: la $2, sym_2_877
+.globl sym_2_878
+sym_2_878: la $2, sym_2_878
+.globl sym_2_879
+sym_2_879: la $2, sym_2_879
+.globl sym_2_880
+sym_2_880: la $2, sym_2_880
+.globl sym_2_881
+sym_2_881: la $2, sym_2_881
+.globl sym_2_882
+sym_2_882: la $2, sym_2_882
+.globl sym_2_883
+sym_2_883: la $2, sym_2_883
+.globl sym_2_884
+sym_2_884: la $2, sym_2_884
+.globl sym_2_885
+sym_2_885: la $2, sym_2_885
+.globl sym_2_886
+sym_2_886: la $2, sym_2_886
+.globl sym_2_887
+sym_2_887: la $2, sym_2_887
+.globl sym_2_888
+sym_2_888: la $2, sym_2_888
+.globl sym_2_889
+sym_2_889: la $2, sym_2_889
+.globl sym_2_890
+sym_2_890: la $2, sym_2_890
+.globl sym_2_891
+sym_2_891: la $2, sym_2_891
+.globl sym_2_892
+sym_2_892: la $2, sym_2_892
+.globl sym_2_893
+sym_2_893: la $2, sym_2_893
+.globl sym_2_894
+sym_2_894: la $2, sym_2_894
+.globl sym_2_895
+sym_2_895: la $2, sym_2_895
+.globl sym_2_896
+sym_2_896: la $2, sym_2_896
+.globl sym_2_897
+sym_2_897: la $2, sym_2_897
+.globl sym_2_898
+sym_2_898: la $2, sym_2_898
+.globl sym_2_899
+sym_2_899: la $2, sym_2_899
+.globl sym_2_900
+sym_2_900: la $2, sym_2_900
+.globl sym_2_901
+sym_2_901: la $2, sym_2_901
+.globl sym_2_902
+sym_2_902: la $2, sym_2_902
+.globl sym_2_903
+sym_2_903: la $2, sym_2_903
+.globl sym_2_904
+sym_2_904: la $2, sym_2_904
+.globl sym_2_905
+sym_2_905: la $2, sym_2_905
+.globl sym_2_906
+sym_2_906: la $2, sym_2_906
+.globl sym_2_907
+sym_2_907: la $2, sym_2_907
+.globl sym_2_908
+sym_2_908: la $2, sym_2_908
+.globl sym_2_909
+sym_2_909: la $2, sym_2_909
+.globl sym_2_910
+sym_2_910: la $2, sym_2_910
+.globl sym_2_911
+sym_2_911: la $2, sym_2_911
+.globl sym_2_912
+sym_2_912: la $2, sym_2_912
+.globl sym_2_913
+sym_2_913: la $2, sym_2_913
+.globl sym_2_914
+sym_2_914: la $2, sym_2_914
+.globl sym_2_915
+sym_2_915: la $2, sym_2_915
+.globl sym_2_916
+sym_2_916: la $2, sym_2_916
+.globl sym_2_917
+sym_2_917: la $2, sym_2_917
+.globl sym_2_918
+sym_2_918: la $2, sym_2_918
+.globl sym_2_919
+sym_2_919: la $2, sym_2_919
+.globl sym_2_920
+sym_2_920: la $2, sym_2_920
+.globl sym_2_921
+sym_2_921: la $2, sym_2_921
+.globl sym_2_922
+sym_2_922: la $2, sym_2_922
+.globl sym_2_923
+sym_2_923: la $2, sym_2_923
+.globl sym_2_924
+sym_2_924: la $2, sym_2_924
+.globl sym_2_925
+sym_2_925: la $2, sym_2_925
+.globl sym_2_926
+sym_2_926: la $2, sym_2_926
+.globl sym_2_927
+sym_2_927: la $2, sym_2_927
+.globl sym_2_928
+sym_2_928: la $2, sym_2_928
+.globl sym_2_929
+sym_2_929: la $2, sym_2_929
+.globl sym_2_930
+sym_2_930: la $2, sym_2_930
+.globl sym_2_931
+sym_2_931: la $2, sym_2_931
+.globl sym_2_932
+sym_2_932: la $2, sym_2_932
+.globl sym_2_933
+sym_2_933: la $2, sym_2_933
+.globl sym_2_934
+sym_2_934: la $2, sym_2_934
+.globl sym_2_935
+sym_2_935: la $2, sym_2_935
+.globl sym_2_936
+sym_2_936: la $2, sym_2_936
+.globl sym_2_937
+sym_2_937: la $2, sym_2_937
+.globl sym_2_938
+sym_2_938: la $2, sym_2_938
+.globl sym_2_939
+sym_2_939: la $2, sym_2_939
+.globl sym_2_940
+sym_2_940: la $2, sym_2_940
+.globl sym_2_941
+sym_2_941: la $2, sym_2_941
+.globl sym_2_942
+sym_2_942: la $2, sym_2_942
+.globl sym_2_943
+sym_2_943: la $2, sym_2_943
+.globl sym_2_944
+sym_2_944: la $2, sym_2_944
+.globl sym_2_945
+sym_2_945: la $2, sym_2_945
+.globl sym_2_946
+sym_2_946: la $2, sym_2_946
+.globl sym_2_947
+sym_2_947: la $2, sym_2_947
+.globl sym_2_948
+sym_2_948: la $2, sym_2_948
+.globl sym_2_949
+sym_2_949: la $2, sym_2_949
+.globl sym_2_950
+sym_2_950: la $2, sym_2_950
+.globl sym_2_951
+sym_2_951: la $2, sym_2_951
+.globl sym_2_952
+sym_2_952: la $2, sym_2_952
+.globl sym_2_953
+sym_2_953: la $2, sym_2_953
+.globl sym_2_954
+sym_2_954: la $2, sym_2_954
+.globl sym_2_955
+sym_2_955: la $2, sym_2_955
+.globl sym_2_956
+sym_2_956: la $2, sym_2_956
+.globl sym_2_957
+sym_2_957: la $2, sym_2_957
+.globl sym_2_958
+sym_2_958: la $2, sym_2_958
+.globl sym_2_959
+sym_2_959: la $2, sym_2_959
+.globl sym_2_960
+sym_2_960: la $2, sym_2_960
+.globl sym_2_961
+sym_2_961: la $2, sym_2_961
+.globl sym_2_962
+sym_2_962: la $2, sym_2_962
+.globl sym_2_963
+sym_2_963: la $2, sym_2_963
+.globl sym_2_964
+sym_2_964: la $2, sym_2_964
+.globl sym_2_965
+sym_2_965: la $2, sym_2_965
+.globl sym_2_966
+sym_2_966: la $2, sym_2_966
+.globl sym_2_967
+sym_2_967: la $2, sym_2_967
+.globl sym_2_968
+sym_2_968: la $2, sym_2_968
+.globl sym_2_969
+sym_2_969: la $2, sym_2_969
+.globl sym_2_970
+sym_2_970: la $2, sym_2_970
+.globl sym_2_971
+sym_2_971: la $2, sym_2_971
+.globl sym_2_972
+sym_2_972: la $2, sym_2_972
+.globl sym_2_973
+sym_2_973: la $2, sym_2_973
+.globl sym_2_974
+sym_2_974: la $2, sym_2_974
+.globl sym_2_975
+sym_2_975: la $2, sym_2_975
+.globl sym_2_976
+sym_2_976: la $2, sym_2_976
+.globl sym_2_977
+sym_2_977: la $2, sym_2_977
+.globl sym_2_978
+sym_2_978: la $2, sym_2_978
+.globl sym_2_979
+sym_2_979: la $2, sym_2_979
+.globl sym_2_980
+sym_2_980: la $2, sym_2_980
+.globl sym_2_981
+sym_2_981: la $2, sym_2_981
+.globl sym_2_982
+sym_2_982: la $2, sym_2_982
+.globl sym_2_983
+sym_2_983: la $2, sym_2_983
+.globl sym_2_984
+sym_2_984: la $2, sym_2_984
+.globl sym_2_985
+sym_2_985: la $2, sym_2_985
+.globl sym_2_986
+sym_2_986: la $2, sym_2_986
+.globl sym_2_987
+sym_2_987: la $2, sym_2_987
+.globl sym_2_988
+sym_2_988: la $2, sym_2_988
+.globl sym_2_989
+sym_2_989: la $2, sym_2_989
+.globl sym_2_990
+sym_2_990: la $2, sym_2_990
+.globl sym_2_991
+sym_2_991: la $2, sym_2_991
+.globl sym_2_992
+sym_2_992: la $2, sym_2_992
+.globl sym_2_993
+sym_2_993: la $2, sym_2_993
+.globl sym_2_994
+sym_2_994: la $2, sym_2_994
+.globl sym_2_995
+sym_2_995: la $2, sym_2_995
+.globl sym_2_996
+sym_2_996: la $2, sym_2_996
+.globl sym_2_997
+sym_2_997: la $2, sym_2_997
+.globl sym_2_998
+sym_2_998: la $2, sym_2_998
+.globl sym_2_999
+sym_2_999: la $2, sym_2_999
+.globl sym_2_1000
+sym_2_1000: la $2, sym_2_1000
+.globl sym_2_1001
+sym_2_1001: la $2, sym_2_1001
+.globl sym_2_1002
+sym_2_1002: la $2, sym_2_1002
+.globl sym_2_1003
+sym_2_1003: la $2, sym_2_1003
+.globl sym_2_1004
+sym_2_1004: la $2, sym_2_1004
+.globl sym_2_1005
+sym_2_1005: la $2, sym_2_1005
+.globl sym_2_1006
+sym_2_1006: la $2, sym_2_1006
+.globl sym_2_1007
+sym_2_1007: la $2, sym_2_1007
+.globl sym_2_1008
+sym_2_1008: la $2, sym_2_1008
+.globl sym_2_1009
+sym_2_1009: la $2, sym_2_1009
+.globl sym_2_1010
+sym_2_1010: la $2, sym_2_1010
+.globl sym_2_1011
+sym_2_1011: la $2, sym_2_1011
+.globl sym_2_1012
+sym_2_1012: la $2, sym_2_1012
+.globl sym_2_1013
+sym_2_1013: la $2, sym_2_1013
+.globl sym_2_1014
+sym_2_1014: la $2, sym_2_1014
+.globl sym_2_1015
+sym_2_1015: la $2, sym_2_1015
+.globl sym_2_1016
+sym_2_1016: la $2, sym_2_1016
+.globl sym_2_1017
+sym_2_1017: la $2, sym_2_1017
+.globl sym_2_1018
+sym_2_1018: la $2, sym_2_1018
+.globl sym_2_1019
+sym_2_1019: la $2, sym_2_1019
+.globl sym_2_1020
+sym_2_1020: la $2, sym_2_1020
+.globl sym_2_1021
+sym_2_1021: la $2, sym_2_1021
+.globl sym_2_1022
+sym_2_1022: la $2, sym_2_1022
+.globl sym_2_1023
+sym_2_1023: la $2, sym_2_1023
+.globl sym_2_1024
+sym_2_1024: la $2, sym_2_1024
+.globl sym_2_1025
+sym_2_1025: la $2, sym_2_1025
+.globl sym_2_1026
+sym_2_1026: la $2, sym_2_1026
+.globl sym_2_1027
+sym_2_1027: la $2, sym_2_1027
+.globl sym_2_1028
+sym_2_1028: la $2, sym_2_1028
+.globl sym_2_1029
+sym_2_1029: la $2, sym_2_1029
+.globl sym_2_1030
+sym_2_1030: la $2, sym_2_1030
+.globl sym_2_1031
+sym_2_1031: la $2, sym_2_1031
+.globl sym_2_1032
+sym_2_1032: la $2, sym_2_1032
+.globl sym_2_1033
+sym_2_1033: la $2, sym_2_1033
+.globl sym_2_1034
+sym_2_1034: la $2, sym_2_1034
+.globl sym_2_1035
+sym_2_1035: la $2, sym_2_1035
+.globl sym_2_1036
+sym_2_1036: la $2, sym_2_1036
+.globl sym_2_1037
+sym_2_1037: la $2, sym_2_1037
+.globl sym_2_1038
+sym_2_1038: la $2, sym_2_1038
+.globl sym_2_1039
+sym_2_1039: la $2, sym_2_1039
+.globl sym_2_1040
+sym_2_1040: la $2, sym_2_1040
+.globl sym_2_1041
+sym_2_1041: la $2, sym_2_1041
+.globl sym_2_1042
+sym_2_1042: la $2, sym_2_1042
+.globl sym_2_1043
+sym_2_1043: la $2, sym_2_1043
+.globl sym_2_1044
+sym_2_1044: la $2, sym_2_1044
+.globl sym_2_1045
+sym_2_1045: la $2, sym_2_1045
+.globl sym_2_1046
+sym_2_1046: la $2, sym_2_1046
+.globl sym_2_1047
+sym_2_1047: la $2, sym_2_1047
+.globl sym_2_1048
+sym_2_1048: la $2, sym_2_1048
+.globl sym_2_1049
+sym_2_1049: la $2, sym_2_1049
+.globl sym_2_1050
+sym_2_1050: la $2, sym_2_1050
+.globl sym_2_1051
+sym_2_1051: la $2, sym_2_1051
+.globl sym_2_1052
+sym_2_1052: la $2, sym_2_1052
+.globl sym_2_1053
+sym_2_1053: la $2, sym_2_1053
+.globl sym_2_1054
+sym_2_1054: la $2, sym_2_1054
+.globl sym_2_1055
+sym_2_1055: la $2, sym_2_1055
+.globl sym_2_1056
+sym_2_1056: la $2, sym_2_1056
+.globl sym_2_1057
+sym_2_1057: la $2, sym_2_1057
+.globl sym_2_1058
+sym_2_1058: la $2, sym_2_1058
+.globl sym_2_1059
+sym_2_1059: la $2, sym_2_1059
+.globl sym_2_1060
+sym_2_1060: la $2, sym_2_1060
+.globl sym_2_1061
+sym_2_1061: la $2, sym_2_1061
+.globl sym_2_1062
+sym_2_1062: la $2, sym_2_1062
+.globl sym_2_1063
+sym_2_1063: la $2, sym_2_1063
+.globl sym_2_1064
+sym_2_1064: la $2, sym_2_1064
+.globl sym_2_1065
+sym_2_1065: la $2, sym_2_1065
+.globl sym_2_1066
+sym_2_1066: la $2, sym_2_1066
+.globl sym_2_1067
+sym_2_1067: la $2, sym_2_1067
+.globl sym_2_1068
+sym_2_1068: la $2, sym_2_1068
+.globl sym_2_1069
+sym_2_1069: la $2, sym_2_1069
+.globl sym_2_1070
+sym_2_1070: la $2, sym_2_1070
+.globl sym_2_1071
+sym_2_1071: la $2, sym_2_1071
+.globl sym_2_1072
+sym_2_1072: la $2, sym_2_1072
+.globl sym_2_1073
+sym_2_1073: la $2, sym_2_1073
+.globl sym_2_1074
+sym_2_1074: la $2, sym_2_1074
+.globl sym_2_1075
+sym_2_1075: la $2, sym_2_1075
+.globl sym_2_1076
+sym_2_1076: la $2, sym_2_1076
+.globl sym_2_1077
+sym_2_1077: la $2, sym_2_1077
+.globl sym_2_1078
+sym_2_1078: la $2, sym_2_1078
+.globl sym_2_1079
+sym_2_1079: la $2, sym_2_1079
+.globl sym_2_1080
+sym_2_1080: la $2, sym_2_1080
+.globl sym_2_1081
+sym_2_1081: la $2, sym_2_1081
+.globl sym_2_1082
+sym_2_1082: la $2, sym_2_1082
+.globl sym_2_1083
+sym_2_1083: la $2, sym_2_1083
+.globl sym_2_1084
+sym_2_1084: la $2, sym_2_1084
+.globl sym_2_1085
+sym_2_1085: la $2, sym_2_1085
+.globl sym_2_1086
+sym_2_1086: la $2, sym_2_1086
+.globl sym_2_1087
+sym_2_1087: la $2, sym_2_1087
+.globl sym_2_1088
+sym_2_1088: la $2, sym_2_1088
+.globl sym_2_1089
+sym_2_1089: la $2, sym_2_1089
+.globl sym_2_1090
+sym_2_1090: la $2, sym_2_1090
+.globl sym_2_1091
+sym_2_1091: la $2, sym_2_1091
+.globl sym_2_1092
+sym_2_1092: la $2, sym_2_1092
+.globl sym_2_1093
+sym_2_1093: la $2, sym_2_1093
+.globl sym_2_1094
+sym_2_1094: la $2, sym_2_1094
+.globl sym_2_1095
+sym_2_1095: la $2, sym_2_1095
+.globl sym_2_1096
+sym_2_1096: la $2, sym_2_1096
+.globl sym_2_1097
+sym_2_1097: la $2, sym_2_1097
+.globl sym_2_1098
+sym_2_1098: la $2, sym_2_1098
+.globl sym_2_1099
+sym_2_1099: la $2, sym_2_1099
+.globl sym_2_1100
+sym_2_1100: la $2, sym_2_1100
+.globl sym_2_1101
+sym_2_1101: la $2, sym_2_1101
+.globl sym_2_1102
+sym_2_1102: la $2, sym_2_1102
+.globl sym_2_1103
+sym_2_1103: la $2, sym_2_1103
+.globl sym_2_1104
+sym_2_1104: la $2, sym_2_1104
+.globl sym_2_1105
+sym_2_1105: la $2, sym_2_1105
+.globl sym_2_1106
+sym_2_1106: la $2, sym_2_1106
+.globl sym_2_1107
+sym_2_1107: la $2, sym_2_1107
+.globl sym_2_1108
+sym_2_1108: la $2, sym_2_1108
+.globl sym_2_1109
+sym_2_1109: la $2, sym_2_1109
+.globl sym_2_1110
+sym_2_1110: la $2, sym_2_1110
+.globl sym_2_1111
+sym_2_1111: la $2, sym_2_1111
+.globl sym_2_1112
+sym_2_1112: la $2, sym_2_1112
+.globl sym_2_1113
+sym_2_1113: la $2, sym_2_1113
+.globl sym_2_1114
+sym_2_1114: la $2, sym_2_1114
+.globl sym_2_1115
+sym_2_1115: la $2, sym_2_1115
+.globl sym_2_1116
+sym_2_1116: la $2, sym_2_1116
+.globl sym_2_1117
+sym_2_1117: la $2, sym_2_1117
+.globl sym_2_1118
+sym_2_1118: la $2, sym_2_1118
+.globl sym_2_1119
+sym_2_1119: la $2, sym_2_1119
+.globl sym_2_1120
+sym_2_1120: la $2, sym_2_1120
+.globl sym_2_1121
+sym_2_1121: la $2, sym_2_1121
+.globl sym_2_1122
+sym_2_1122: la $2, sym_2_1122
+.globl sym_2_1123
+sym_2_1123: la $2, sym_2_1123
+.globl sym_2_1124
+sym_2_1124: la $2, sym_2_1124
+.globl sym_2_1125
+sym_2_1125: la $2, sym_2_1125
+.globl sym_2_1126
+sym_2_1126: la $2, sym_2_1126
+.globl sym_2_1127
+sym_2_1127: la $2, sym_2_1127
+.globl sym_2_1128
+sym_2_1128: la $2, sym_2_1128
+.globl sym_2_1129
+sym_2_1129: la $2, sym_2_1129
+.globl sym_2_1130
+sym_2_1130: la $2, sym_2_1130
+.globl sym_2_1131
+sym_2_1131: la $2, sym_2_1131
+.globl sym_2_1132
+sym_2_1132: la $2, sym_2_1132
+.globl sym_2_1133
+sym_2_1133: la $2, sym_2_1133
+.globl sym_2_1134
+sym_2_1134: la $2, sym_2_1134
+.globl sym_2_1135
+sym_2_1135: la $2, sym_2_1135
+.globl sym_2_1136
+sym_2_1136: la $2, sym_2_1136
+.globl sym_2_1137
+sym_2_1137: la $2, sym_2_1137
+.globl sym_2_1138
+sym_2_1138: la $2, sym_2_1138
+.globl sym_2_1139
+sym_2_1139: la $2, sym_2_1139
+.globl sym_2_1140
+sym_2_1140: la $2, sym_2_1140
+.globl sym_2_1141
+sym_2_1141: la $2, sym_2_1141
+.globl sym_2_1142
+sym_2_1142: la $2, sym_2_1142
+.globl sym_2_1143
+sym_2_1143: la $2, sym_2_1143
+.globl sym_2_1144
+sym_2_1144: la $2, sym_2_1144
+.globl sym_2_1145
+sym_2_1145: la $2, sym_2_1145
+.globl sym_2_1146
+sym_2_1146: la $2, sym_2_1146
+.globl sym_2_1147
+sym_2_1147: la $2, sym_2_1147
+.globl sym_2_1148
+sym_2_1148: la $2, sym_2_1148
+.globl sym_2_1149
+sym_2_1149: la $2, sym_2_1149
+.globl sym_2_1150
+sym_2_1150: la $2, sym_2_1150
+.globl sym_2_1151
+sym_2_1151: la $2, sym_2_1151
+.globl sym_2_1152
+sym_2_1152: la $2, sym_2_1152
+.globl sym_2_1153
+sym_2_1153: la $2, sym_2_1153
+.globl sym_2_1154
+sym_2_1154: la $2, sym_2_1154
+.globl sym_2_1155
+sym_2_1155: la $2, sym_2_1155
+.globl sym_2_1156
+sym_2_1156: la $2, sym_2_1156
+.globl sym_2_1157
+sym_2_1157: la $2, sym_2_1157
+.globl sym_2_1158
+sym_2_1158: la $2, sym_2_1158
+.globl sym_2_1159
+sym_2_1159: la $2, sym_2_1159
+.globl sym_2_1160
+sym_2_1160: la $2, sym_2_1160
+.globl sym_2_1161
+sym_2_1161: la $2, sym_2_1161
+.globl sym_2_1162
+sym_2_1162: la $2, sym_2_1162
+.globl sym_2_1163
+sym_2_1163: la $2, sym_2_1163
+.globl sym_2_1164
+sym_2_1164: la $2, sym_2_1164
+.globl sym_2_1165
+sym_2_1165: la $2, sym_2_1165
+.globl sym_2_1166
+sym_2_1166: la $2, sym_2_1166
+.globl sym_2_1167
+sym_2_1167: la $2, sym_2_1167
+.globl sym_2_1168
+sym_2_1168: la $2, sym_2_1168
+.globl sym_2_1169
+sym_2_1169: la $2, sym_2_1169
+.globl sym_2_1170
+sym_2_1170: la $2, sym_2_1170
+.globl sym_2_1171
+sym_2_1171: la $2, sym_2_1171
+.globl sym_2_1172
+sym_2_1172: la $2, sym_2_1172
+.globl sym_2_1173
+sym_2_1173: la $2, sym_2_1173
+.globl sym_2_1174
+sym_2_1174: la $2, sym_2_1174
+.globl sym_2_1175
+sym_2_1175: la $2, sym_2_1175
+.globl sym_2_1176
+sym_2_1176: la $2, sym_2_1176
+.globl sym_2_1177
+sym_2_1177: la $2, sym_2_1177
+.globl sym_2_1178
+sym_2_1178: la $2, sym_2_1178
+.globl sym_2_1179
+sym_2_1179: la $2, sym_2_1179
+.globl sym_2_1180
+sym_2_1180: la $2, sym_2_1180
+.globl sym_2_1181
+sym_2_1181: la $2, sym_2_1181
+.globl sym_2_1182
+sym_2_1182: la $2, sym_2_1182
+.globl sym_2_1183
+sym_2_1183: la $2, sym_2_1183
+.globl sym_2_1184
+sym_2_1184: la $2, sym_2_1184
+.globl sym_2_1185
+sym_2_1185: la $2, sym_2_1185
+.globl sym_2_1186
+sym_2_1186: la $2, sym_2_1186
+.globl sym_2_1187
+sym_2_1187: la $2, sym_2_1187
+.globl sym_2_1188
+sym_2_1188: la $2, sym_2_1188
+.globl sym_2_1189
+sym_2_1189: la $2, sym_2_1189
+.globl sym_2_1190
+sym_2_1190: la $2, sym_2_1190
+.globl sym_2_1191
+sym_2_1191: la $2, sym_2_1191
+.globl sym_2_1192
+sym_2_1192: la $2, sym_2_1192
+.globl sym_2_1193
+sym_2_1193: la $2, sym_2_1193
+.globl sym_2_1194
+sym_2_1194: la $2, sym_2_1194
+.globl sym_2_1195
+sym_2_1195: la $2, sym_2_1195
+.globl sym_2_1196
+sym_2_1196: la $2, sym_2_1196
+.globl sym_2_1197
+sym_2_1197: la $2, sym_2_1197
+.globl sym_2_1198
+sym_2_1198: la $2, sym_2_1198
+.globl sym_2_1199
+sym_2_1199: la $2, sym_2_1199
+.globl sym_2_1200
+sym_2_1200: la $2, sym_2_1200
+.globl sym_2_1201
+sym_2_1201: la $2, sym_2_1201
+.globl sym_2_1202
+sym_2_1202: la $2, sym_2_1202
+.globl sym_2_1203
+sym_2_1203: la $2, sym_2_1203
+.globl sym_2_1204
+sym_2_1204: la $2, sym_2_1204
+.globl sym_2_1205
+sym_2_1205: la $2, sym_2_1205
+.globl sym_2_1206
+sym_2_1206: la $2, sym_2_1206
+.globl sym_2_1207
+sym_2_1207: la $2, sym_2_1207
+.globl sym_2_1208
+sym_2_1208: la $2, sym_2_1208
+.globl sym_2_1209
+sym_2_1209: la $2, sym_2_1209
+.globl sym_2_1210
+sym_2_1210: la $2, sym_2_1210
+.globl sym_2_1211
+sym_2_1211: la $2, sym_2_1211
+.globl sym_2_1212
+sym_2_1212: la $2, sym_2_1212
+.globl sym_2_1213
+sym_2_1213: la $2, sym_2_1213
+.globl sym_2_1214
+sym_2_1214: la $2, sym_2_1214
+.globl sym_2_1215
+sym_2_1215: la $2, sym_2_1215
+.globl sym_2_1216
+sym_2_1216: la $2, sym_2_1216
+.globl sym_2_1217
+sym_2_1217: la $2, sym_2_1217
+.globl sym_2_1218
+sym_2_1218: la $2, sym_2_1218
+.globl sym_2_1219
+sym_2_1219: la $2, sym_2_1219
+.globl sym_2_1220
+sym_2_1220: la $2, sym_2_1220
+.globl sym_2_1221
+sym_2_1221: la $2, sym_2_1221
+.globl sym_2_1222
+sym_2_1222: la $2, sym_2_1222
+.globl sym_2_1223
+sym_2_1223: la $2, sym_2_1223
+.globl sym_2_1224
+sym_2_1224: la $2, sym_2_1224
+.globl sym_2_1225
+sym_2_1225: la $2, sym_2_1225
+.globl sym_2_1226
+sym_2_1226: la $2, sym_2_1226
+.globl sym_2_1227
+sym_2_1227: la $2, sym_2_1227
+.globl sym_2_1228
+sym_2_1228: la $2, sym_2_1228
+.globl sym_2_1229
+sym_2_1229: la $2, sym_2_1229
+.globl sym_2_1230
+sym_2_1230: la $2, sym_2_1230
+.globl sym_2_1231
+sym_2_1231: la $2, sym_2_1231
+.globl sym_2_1232
+sym_2_1232: la $2, sym_2_1232
+.globl sym_2_1233
+sym_2_1233: la $2, sym_2_1233
+.globl sym_2_1234
+sym_2_1234: la $2, sym_2_1234
+.globl sym_2_1235
+sym_2_1235: la $2, sym_2_1235
+.globl sym_2_1236
+sym_2_1236: la $2, sym_2_1236
+.globl sym_2_1237
+sym_2_1237: la $2, sym_2_1237
+.globl sym_2_1238
+sym_2_1238: la $2, sym_2_1238
+.globl sym_2_1239
+sym_2_1239: la $2, sym_2_1239
+.globl sym_2_1240
+sym_2_1240: la $2, sym_2_1240
+.globl sym_2_1241
+sym_2_1241: la $2, sym_2_1241
+.globl sym_2_1242
+sym_2_1242: la $2, sym_2_1242
+.globl sym_2_1243
+sym_2_1243: la $2, sym_2_1243
+.globl sym_2_1244
+sym_2_1244: la $2, sym_2_1244
+.globl sym_2_1245
+sym_2_1245: la $2, sym_2_1245
+.globl sym_2_1246
+sym_2_1246: la $2, sym_2_1246
+.globl sym_2_1247
+sym_2_1247: la $2, sym_2_1247
+.globl sym_2_1248
+sym_2_1248: la $2, sym_2_1248
+.globl sym_2_1249
+sym_2_1249: la $2, sym_2_1249
+.globl sym_2_1250
+sym_2_1250: la $2, sym_2_1250
+.globl sym_2_1251
+sym_2_1251: la $2, sym_2_1251
+.globl sym_2_1252
+sym_2_1252: la $2, sym_2_1252
+.globl sym_2_1253
+sym_2_1253: la $2, sym_2_1253
+.globl sym_2_1254
+sym_2_1254: la $2, sym_2_1254
+.globl sym_2_1255
+sym_2_1255: la $2, sym_2_1255
+.globl sym_2_1256
+sym_2_1256: la $2, sym_2_1256
+.globl sym_2_1257
+sym_2_1257: la $2, sym_2_1257
+.globl sym_2_1258
+sym_2_1258: la $2, sym_2_1258
+.globl sym_2_1259
+sym_2_1259: la $2, sym_2_1259
+.globl sym_2_1260
+sym_2_1260: la $2, sym_2_1260
+.globl sym_2_1261
+sym_2_1261: la $2, sym_2_1261
+.globl sym_2_1262
+sym_2_1262: la $2, sym_2_1262
+.globl sym_2_1263
+sym_2_1263: la $2, sym_2_1263
+.globl sym_2_1264
+sym_2_1264: la $2, sym_2_1264
+.globl sym_2_1265
+sym_2_1265: la $2, sym_2_1265
+.globl sym_2_1266
+sym_2_1266: la $2, sym_2_1266
+.globl sym_2_1267
+sym_2_1267: la $2, sym_2_1267
+.globl sym_2_1268
+sym_2_1268: la $2, sym_2_1268
+.globl sym_2_1269
+sym_2_1269: la $2, sym_2_1269
+.globl sym_2_1270
+sym_2_1270: la $2, sym_2_1270
+.globl sym_2_1271
+sym_2_1271: la $2, sym_2_1271
+.globl sym_2_1272
+sym_2_1272: la $2, sym_2_1272
+.globl sym_2_1273
+sym_2_1273: la $2, sym_2_1273
+.globl sym_2_1274
+sym_2_1274: la $2, sym_2_1274
+.globl sym_2_1275
+sym_2_1275: la $2, sym_2_1275
+.globl sym_2_1276
+sym_2_1276: la $2, sym_2_1276
+.globl sym_2_1277
+sym_2_1277: la $2, sym_2_1277
+.globl sym_2_1278
+sym_2_1278: la $2, sym_2_1278
+.globl sym_2_1279
+sym_2_1279: la $2, sym_2_1279
+.globl sym_2_1280
+sym_2_1280: la $2, sym_2_1280
+.globl sym_2_1281
+sym_2_1281: la $2, sym_2_1281
+.globl sym_2_1282
+sym_2_1282: la $2, sym_2_1282
+.globl sym_2_1283
+sym_2_1283: la $2, sym_2_1283
+.globl sym_2_1284
+sym_2_1284: la $2, sym_2_1284
+.globl sym_2_1285
+sym_2_1285: la $2, sym_2_1285
+.globl sym_2_1286
+sym_2_1286: la $2, sym_2_1286
+.globl sym_2_1287
+sym_2_1287: la $2, sym_2_1287
+.globl sym_2_1288
+sym_2_1288: la $2, sym_2_1288
+.globl sym_2_1289
+sym_2_1289: la $2, sym_2_1289
+.globl sym_2_1290
+sym_2_1290: la $2, sym_2_1290
+.globl sym_2_1291
+sym_2_1291: la $2, sym_2_1291
+.globl sym_2_1292
+sym_2_1292: la $2, sym_2_1292
+.globl sym_2_1293
+sym_2_1293: la $2, sym_2_1293
+.globl sym_2_1294
+sym_2_1294: la $2, sym_2_1294
+.globl sym_2_1295
+sym_2_1295: la $2, sym_2_1295
+.globl sym_2_1296
+sym_2_1296: la $2, sym_2_1296
+.globl sym_2_1297
+sym_2_1297: la $2, sym_2_1297
+.globl sym_2_1298
+sym_2_1298: la $2, sym_2_1298
+.globl sym_2_1299
+sym_2_1299: la $2, sym_2_1299
+.globl sym_2_1300
+sym_2_1300: la $2, sym_2_1300
+.globl sym_2_1301
+sym_2_1301: la $2, sym_2_1301
+.globl sym_2_1302
+sym_2_1302: la $2, sym_2_1302
+.globl sym_2_1303
+sym_2_1303: la $2, sym_2_1303
+.globl sym_2_1304
+sym_2_1304: la $2, sym_2_1304
+.globl sym_2_1305
+sym_2_1305: la $2, sym_2_1305
+.globl sym_2_1306
+sym_2_1306: la $2, sym_2_1306
+.globl sym_2_1307
+sym_2_1307: la $2, sym_2_1307
+.globl sym_2_1308
+sym_2_1308: la $2, sym_2_1308
+.globl sym_2_1309
+sym_2_1309: la $2, sym_2_1309
+.globl sym_2_1310
+sym_2_1310: la $2, sym_2_1310
+.globl sym_2_1311
+sym_2_1311: la $2, sym_2_1311
+.globl sym_2_1312
+sym_2_1312: la $2, sym_2_1312
+.globl sym_2_1313
+sym_2_1313: la $2, sym_2_1313
+.globl sym_2_1314
+sym_2_1314: la $2, sym_2_1314
+.globl sym_2_1315
+sym_2_1315: la $2, sym_2_1315
+.globl sym_2_1316
+sym_2_1316: la $2, sym_2_1316
+.globl sym_2_1317
+sym_2_1317: la $2, sym_2_1317
+.globl sym_2_1318
+sym_2_1318: la $2, sym_2_1318
+.globl sym_2_1319
+sym_2_1319: la $2, sym_2_1319
+.globl sym_2_1320
+sym_2_1320: la $2, sym_2_1320
+.globl sym_2_1321
+sym_2_1321: la $2, sym_2_1321
+.globl sym_2_1322
+sym_2_1322: la $2, sym_2_1322
+.globl sym_2_1323
+sym_2_1323: la $2, sym_2_1323
+.globl sym_2_1324
+sym_2_1324: la $2, sym_2_1324
+.globl sym_2_1325
+sym_2_1325: la $2, sym_2_1325
+.globl sym_2_1326
+sym_2_1326: la $2, sym_2_1326
+.globl sym_2_1327
+sym_2_1327: la $2, sym_2_1327
+.globl sym_2_1328
+sym_2_1328: la $2, sym_2_1328
+.globl sym_2_1329
+sym_2_1329: la $2, sym_2_1329
+.globl sym_2_1330
+sym_2_1330: la $2, sym_2_1330
+.globl sym_2_1331
+sym_2_1331: la $2, sym_2_1331
+.globl sym_2_1332
+sym_2_1332: la $2, sym_2_1332
+.globl sym_2_1333
+sym_2_1333: la $2, sym_2_1333
+.globl sym_2_1334
+sym_2_1334: la $2, sym_2_1334
+.globl sym_2_1335
+sym_2_1335: la $2, sym_2_1335
+.globl sym_2_1336
+sym_2_1336: la $2, sym_2_1336
+.globl sym_2_1337
+sym_2_1337: la $2, sym_2_1337
+.globl sym_2_1338
+sym_2_1338: la $2, sym_2_1338
+.globl sym_2_1339
+sym_2_1339: la $2, sym_2_1339
+.globl sym_2_1340
+sym_2_1340: la $2, sym_2_1340
+.globl sym_2_1341
+sym_2_1341: la $2, sym_2_1341
+.globl sym_2_1342
+sym_2_1342: la $2, sym_2_1342
+.globl sym_2_1343
+sym_2_1343: la $2, sym_2_1343
+.globl sym_2_1344
+sym_2_1344: la $2, sym_2_1344
+.globl sym_2_1345
+sym_2_1345: la $2, sym_2_1345
+.globl sym_2_1346
+sym_2_1346: la $2, sym_2_1346
+.globl sym_2_1347
+sym_2_1347: la $2, sym_2_1347
+.globl sym_2_1348
+sym_2_1348: la $2, sym_2_1348
+.globl sym_2_1349
+sym_2_1349: la $2, sym_2_1349
+.globl sym_2_1350
+sym_2_1350: la $2, sym_2_1350
+.globl sym_2_1351
+sym_2_1351: la $2, sym_2_1351
+.globl sym_2_1352
+sym_2_1352: la $2, sym_2_1352
+.globl sym_2_1353
+sym_2_1353: la $2, sym_2_1353
+.globl sym_2_1354
+sym_2_1354: la $2, sym_2_1354
+.globl sym_2_1355
+sym_2_1355: la $2, sym_2_1355
+.globl sym_2_1356
+sym_2_1356: la $2, sym_2_1356
+.globl sym_2_1357
+sym_2_1357: la $2, sym_2_1357
+.globl sym_2_1358
+sym_2_1358: la $2, sym_2_1358
+.globl sym_2_1359
+sym_2_1359: la $2, sym_2_1359
+.globl sym_2_1360
+sym_2_1360: la $2, sym_2_1360
+.globl sym_2_1361
+sym_2_1361: la $2, sym_2_1361
+.globl sym_2_1362
+sym_2_1362: la $2, sym_2_1362
+.globl sym_2_1363
+sym_2_1363: la $2, sym_2_1363
+.globl sym_2_1364
+sym_2_1364: la $2, sym_2_1364
+.globl sym_2_1365
+sym_2_1365: la $2, sym_2_1365
+.globl sym_2_1366
+sym_2_1366: la $2, sym_2_1366
+.globl sym_2_1367
+sym_2_1367: la $2, sym_2_1367
+.globl sym_2_1368
+sym_2_1368: la $2, sym_2_1368
+.globl sym_2_1369
+sym_2_1369: la $2, sym_2_1369
+.globl sym_2_1370
+sym_2_1370: la $2, sym_2_1370
+.globl sym_2_1371
+sym_2_1371: la $2, sym_2_1371
+.globl sym_2_1372
+sym_2_1372: la $2, sym_2_1372
+.globl sym_2_1373
+sym_2_1373: la $2, sym_2_1373
+.globl sym_2_1374
+sym_2_1374: la $2, sym_2_1374
+.globl sym_2_1375
+sym_2_1375: la $2, sym_2_1375
+.globl sym_2_1376
+sym_2_1376: la $2, sym_2_1376
+.globl sym_2_1377
+sym_2_1377: la $2, sym_2_1377
+.globl sym_2_1378
+sym_2_1378: la $2, sym_2_1378
+.globl sym_2_1379
+sym_2_1379: la $2, sym_2_1379
+.globl sym_2_1380
+sym_2_1380: la $2, sym_2_1380
+.globl sym_2_1381
+sym_2_1381: la $2, sym_2_1381
+.globl sym_2_1382
+sym_2_1382: la $2, sym_2_1382
+.globl sym_2_1383
+sym_2_1383: la $2, sym_2_1383
+.globl sym_2_1384
+sym_2_1384: la $2, sym_2_1384
+.globl sym_2_1385
+sym_2_1385: la $2, sym_2_1385
+.globl sym_2_1386
+sym_2_1386: la $2, sym_2_1386
+.globl sym_2_1387
+sym_2_1387: la $2, sym_2_1387
+.globl sym_2_1388
+sym_2_1388: la $2, sym_2_1388
+.globl sym_2_1389
+sym_2_1389: la $2, sym_2_1389
+.globl sym_2_1390
+sym_2_1390: la $2, sym_2_1390
+.globl sym_2_1391
+sym_2_1391: la $2, sym_2_1391
+.globl sym_2_1392
+sym_2_1392: la $2, sym_2_1392
+.globl sym_2_1393
+sym_2_1393: la $2, sym_2_1393
+.globl sym_2_1394
+sym_2_1394: la $2, sym_2_1394
+.globl sym_2_1395
+sym_2_1395: la $2, sym_2_1395
+.globl sym_2_1396
+sym_2_1396: la $2, sym_2_1396
+.globl sym_2_1397
+sym_2_1397: la $2, sym_2_1397
+.globl sym_2_1398
+sym_2_1398: la $2, sym_2_1398
+.globl sym_2_1399
+sym_2_1399: la $2, sym_2_1399
+.globl sym_2_1400
+sym_2_1400: la $2, sym_2_1400
+.globl sym_2_1401
+sym_2_1401: la $2, sym_2_1401
+.globl sym_2_1402
+sym_2_1402: la $2, sym_2_1402
+.globl sym_2_1403
+sym_2_1403: la $2, sym_2_1403
+.globl sym_2_1404
+sym_2_1404: la $2, sym_2_1404
+.globl sym_2_1405
+sym_2_1405: la $2, sym_2_1405
+.globl sym_2_1406
+sym_2_1406: la $2, sym_2_1406
+.globl sym_2_1407
+sym_2_1407: la $2, sym_2_1407
+.globl sym_2_1408
+sym_2_1408: la $2, sym_2_1408
+.globl sym_2_1409
+sym_2_1409: la $2, sym_2_1409
+.globl sym_2_1410
+sym_2_1410: la $2, sym_2_1410
+.globl sym_2_1411
+sym_2_1411: la $2, sym_2_1411
+.globl sym_2_1412
+sym_2_1412: la $2, sym_2_1412
+.globl sym_2_1413
+sym_2_1413: la $2, sym_2_1413
+.globl sym_2_1414
+sym_2_1414: la $2, sym_2_1414
+.globl sym_2_1415
+sym_2_1415: la $2, sym_2_1415
+.globl sym_2_1416
+sym_2_1416: la $2, sym_2_1416
+.globl sym_2_1417
+sym_2_1417: la $2, sym_2_1417
+.globl sym_2_1418
+sym_2_1418: la $2, sym_2_1418
+.globl sym_2_1419
+sym_2_1419: la $2, sym_2_1419
+.globl sym_2_1420
+sym_2_1420: la $2, sym_2_1420
+.globl sym_2_1421
+sym_2_1421: la $2, sym_2_1421
+.globl sym_2_1422
+sym_2_1422: la $2, sym_2_1422
+.globl sym_2_1423
+sym_2_1423: la $2, sym_2_1423
+.globl sym_2_1424
+sym_2_1424: la $2, sym_2_1424
+.globl sym_2_1425
+sym_2_1425: la $2, sym_2_1425
+.globl sym_2_1426
+sym_2_1426: la $2, sym_2_1426
+.globl sym_2_1427
+sym_2_1427: la $2, sym_2_1427
+.globl sym_2_1428
+sym_2_1428: la $2, sym_2_1428
+.globl sym_2_1429
+sym_2_1429: la $2, sym_2_1429
+.globl sym_2_1430
+sym_2_1430: la $2, sym_2_1430
+.globl sym_2_1431
+sym_2_1431: la $2, sym_2_1431
+.globl sym_2_1432
+sym_2_1432: la $2, sym_2_1432
+.globl sym_2_1433
+sym_2_1433: la $2, sym_2_1433
+.globl sym_2_1434
+sym_2_1434: la $2, sym_2_1434
+.globl sym_2_1435
+sym_2_1435: la $2, sym_2_1435
+.globl sym_2_1436
+sym_2_1436: la $2, sym_2_1436
+.globl sym_2_1437
+sym_2_1437: la $2, sym_2_1437
+.globl sym_2_1438
+sym_2_1438: la $2, sym_2_1438
+.globl sym_2_1439
+sym_2_1439: la $2, sym_2_1439
+.globl sym_2_1440
+sym_2_1440: la $2, sym_2_1440
+.globl sym_2_1441
+sym_2_1441: la $2, sym_2_1441
+.globl sym_2_1442
+sym_2_1442: la $2, sym_2_1442
+.globl sym_2_1443
+sym_2_1443: la $2, sym_2_1443
+.globl sym_2_1444
+sym_2_1444: la $2, sym_2_1444
+.globl sym_2_1445
+sym_2_1445: la $2, sym_2_1445
+.globl sym_2_1446
+sym_2_1446: la $2, sym_2_1446
+.globl sym_2_1447
+sym_2_1447: la $2, sym_2_1447
+.globl sym_2_1448
+sym_2_1448: la $2, sym_2_1448
+.globl sym_2_1449
+sym_2_1449: la $2, sym_2_1449
+.globl sym_2_1450
+sym_2_1450: la $2, sym_2_1450
+.globl sym_2_1451
+sym_2_1451: la $2, sym_2_1451
+.globl sym_2_1452
+sym_2_1452: la $2, sym_2_1452
+.globl sym_2_1453
+sym_2_1453: la $2, sym_2_1453
+.globl sym_2_1454
+sym_2_1454: la $2, sym_2_1454
+.globl sym_2_1455
+sym_2_1455: la $2, sym_2_1455
+.globl sym_2_1456
+sym_2_1456: la $2, sym_2_1456
+.globl sym_2_1457
+sym_2_1457: la $2, sym_2_1457
+.globl sym_2_1458
+sym_2_1458: la $2, sym_2_1458
+.globl sym_2_1459
+sym_2_1459: la $2, sym_2_1459
+.globl sym_2_1460
+sym_2_1460: la $2, sym_2_1460
+.globl sym_2_1461
+sym_2_1461: la $2, sym_2_1461
+.globl sym_2_1462
+sym_2_1462: la $2, sym_2_1462
+.globl sym_2_1463
+sym_2_1463: la $2, sym_2_1463
+.globl sym_2_1464
+sym_2_1464: la $2, sym_2_1464
+.globl sym_2_1465
+sym_2_1465: la $2, sym_2_1465
+.globl sym_2_1466
+sym_2_1466: la $2, sym_2_1466
+.globl sym_2_1467
+sym_2_1467: la $2, sym_2_1467
+.globl sym_2_1468
+sym_2_1468: la $2, sym_2_1468
+.globl sym_2_1469
+sym_2_1469: la $2, sym_2_1469
+.globl sym_2_1470
+sym_2_1470: la $2, sym_2_1470
+.globl sym_2_1471
+sym_2_1471: la $2, sym_2_1471
+.globl sym_2_1472
+sym_2_1472: la $2, sym_2_1472
+.globl sym_2_1473
+sym_2_1473: la $2, sym_2_1473
+.globl sym_2_1474
+sym_2_1474: la $2, sym_2_1474
+.globl sym_2_1475
+sym_2_1475: la $2, sym_2_1475
+.globl sym_2_1476
+sym_2_1476: la $2, sym_2_1476
+.globl sym_2_1477
+sym_2_1477: la $2, sym_2_1477
+.globl sym_2_1478
+sym_2_1478: la $2, sym_2_1478
+.globl sym_2_1479
+sym_2_1479: la $2, sym_2_1479
+.globl sym_2_1480
+sym_2_1480: la $2, sym_2_1480
+.globl sym_2_1481
+sym_2_1481: la $2, sym_2_1481
+.globl sym_2_1482
+sym_2_1482: la $2, sym_2_1482
+.globl sym_2_1483
+sym_2_1483: la $2, sym_2_1483
+.globl sym_2_1484
+sym_2_1484: la $2, sym_2_1484
+.globl sym_2_1485
+sym_2_1485: la $2, sym_2_1485
+.globl sym_2_1486
+sym_2_1486: la $2, sym_2_1486
+.globl sym_2_1487
+sym_2_1487: la $2, sym_2_1487
+.globl sym_2_1488
+sym_2_1488: la $2, sym_2_1488
+.globl sym_2_1489
+sym_2_1489: la $2, sym_2_1489
+.globl sym_2_1490
+sym_2_1490: la $2, sym_2_1490
+.globl sym_2_1491
+sym_2_1491: la $2, sym_2_1491
+.globl sym_2_1492
+sym_2_1492: la $2, sym_2_1492
+.globl sym_2_1493
+sym_2_1493: la $2, sym_2_1493
+.globl sym_2_1494
+sym_2_1494: la $2, sym_2_1494
+.globl sym_2_1495
+sym_2_1495: la $2, sym_2_1495
+.globl sym_2_1496
+sym_2_1496: la $2, sym_2_1496
+.globl sym_2_1497
+sym_2_1497: la $2, sym_2_1497
+.globl sym_2_1498
+sym_2_1498: la $2, sym_2_1498
+.globl sym_2_1499
+sym_2_1499: la $2, sym_2_1499
+.globl sym_2_1500
+sym_2_1500: la $2, sym_2_1500
+.globl sym_2_1501
+sym_2_1501: la $2, sym_2_1501
+.globl sym_2_1502
+sym_2_1502: la $2, sym_2_1502
+.globl sym_2_1503
+sym_2_1503: la $2, sym_2_1503
+.globl sym_2_1504
+sym_2_1504: la $2, sym_2_1504
+.globl sym_2_1505
+sym_2_1505: la $2, sym_2_1505
+.globl sym_2_1506
+sym_2_1506: la $2, sym_2_1506
+.globl sym_2_1507
+sym_2_1507: la $2, sym_2_1507
+.globl sym_2_1508
+sym_2_1508: la $2, sym_2_1508
+.globl sym_2_1509
+sym_2_1509: la $2, sym_2_1509
+.globl sym_2_1510
+sym_2_1510: la $2, sym_2_1510
+.globl sym_2_1511
+sym_2_1511: la $2, sym_2_1511
+.globl sym_2_1512
+sym_2_1512: la $2, sym_2_1512
+.globl sym_2_1513
+sym_2_1513: la $2, sym_2_1513
+.globl sym_2_1514
+sym_2_1514: la $2, sym_2_1514
+.globl sym_2_1515
+sym_2_1515: la $2, sym_2_1515
+.globl sym_2_1516
+sym_2_1516: la $2, sym_2_1516
+.globl sym_2_1517
+sym_2_1517: la $2, sym_2_1517
+.globl sym_2_1518
+sym_2_1518: la $2, sym_2_1518
+.globl sym_2_1519
+sym_2_1519: la $2, sym_2_1519
+.globl sym_2_1520
+sym_2_1520: la $2, sym_2_1520
+.globl sym_2_1521
+sym_2_1521: la $2, sym_2_1521
+.globl sym_2_1522
+sym_2_1522: la $2, sym_2_1522
+.globl sym_2_1523
+sym_2_1523: la $2, sym_2_1523
+.globl sym_2_1524
+sym_2_1524: la $2, sym_2_1524
+.globl sym_2_1525
+sym_2_1525: la $2, sym_2_1525
+.globl sym_2_1526
+sym_2_1526: la $2, sym_2_1526
+.globl sym_2_1527
+sym_2_1527: la $2, sym_2_1527
+.globl sym_2_1528
+sym_2_1528: la $2, sym_2_1528
+.globl sym_2_1529
+sym_2_1529: la $2, sym_2_1529
+.globl sym_2_1530
+sym_2_1530: la $2, sym_2_1530
+.globl sym_2_1531
+sym_2_1531: la $2, sym_2_1531
+.globl sym_2_1532
+sym_2_1532: la $2, sym_2_1532
+.globl sym_2_1533
+sym_2_1533: la $2, sym_2_1533
+.globl sym_2_1534
+sym_2_1534: la $2, sym_2_1534
+.globl sym_2_1535
+sym_2_1535: la $2, sym_2_1535
+.globl sym_2_1536
+sym_2_1536: la $2, sym_2_1536
+.globl sym_2_1537
+sym_2_1537: la $2, sym_2_1537
+.globl sym_2_1538
+sym_2_1538: la $2, sym_2_1538
+.globl sym_2_1539
+sym_2_1539: la $2, sym_2_1539
+.globl sym_2_1540
+sym_2_1540: la $2, sym_2_1540
+.globl sym_2_1541
+sym_2_1541: la $2, sym_2_1541
+.globl sym_2_1542
+sym_2_1542: la $2, sym_2_1542
+.globl sym_2_1543
+sym_2_1543: la $2, sym_2_1543
+.globl sym_2_1544
+sym_2_1544: la $2, sym_2_1544
+.globl sym_2_1545
+sym_2_1545: la $2, sym_2_1545
+.globl sym_2_1546
+sym_2_1546: la $2, sym_2_1546
+.globl sym_2_1547
+sym_2_1547: la $2, sym_2_1547
+.globl sym_2_1548
+sym_2_1548: la $2, sym_2_1548
+.globl sym_2_1549
+sym_2_1549: la $2, sym_2_1549
+.globl sym_2_1550
+sym_2_1550: la $2, sym_2_1550
+.globl sym_2_1551
+sym_2_1551: la $2, sym_2_1551
+.globl sym_2_1552
+sym_2_1552: la $2, sym_2_1552
+.globl sym_2_1553
+sym_2_1553: la $2, sym_2_1553
+.globl sym_2_1554
+sym_2_1554: la $2, sym_2_1554
+.globl sym_2_1555
+sym_2_1555: la $2, sym_2_1555
+.globl sym_2_1556
+sym_2_1556: la $2, sym_2_1556
+.globl sym_2_1557
+sym_2_1557: la $2, sym_2_1557
+.globl sym_2_1558
+sym_2_1558: la $2, sym_2_1558
+.globl sym_2_1559
+sym_2_1559: la $2, sym_2_1559
+.globl sym_2_1560
+sym_2_1560: la $2, sym_2_1560
+.globl sym_2_1561
+sym_2_1561: la $2, sym_2_1561
+.globl sym_2_1562
+sym_2_1562: la $2, sym_2_1562
+.globl sym_2_1563
+sym_2_1563: la $2, sym_2_1563
+.globl sym_2_1564
+sym_2_1564: la $2, sym_2_1564
+.globl sym_2_1565
+sym_2_1565: la $2, sym_2_1565
+.globl sym_2_1566
+sym_2_1566: la $2, sym_2_1566
+.globl sym_2_1567
+sym_2_1567: la $2, sym_2_1567
+.globl sym_2_1568
+sym_2_1568: la $2, sym_2_1568
+.globl sym_2_1569
+sym_2_1569: la $2, sym_2_1569
+.globl sym_2_1570
+sym_2_1570: la $2, sym_2_1570
+.globl sym_2_1571
+sym_2_1571: la $2, sym_2_1571
+.globl sym_2_1572
+sym_2_1572: la $2, sym_2_1572
+.globl sym_2_1573
+sym_2_1573: la $2, sym_2_1573
+.globl sym_2_1574
+sym_2_1574: la $2, sym_2_1574
+.globl sym_2_1575
+sym_2_1575: la $2, sym_2_1575
+.globl sym_2_1576
+sym_2_1576: la $2, sym_2_1576
+.globl sym_2_1577
+sym_2_1577: la $2, sym_2_1577
+.globl sym_2_1578
+sym_2_1578: la $2, sym_2_1578
+.globl sym_2_1579
+sym_2_1579: la $2, sym_2_1579
+.globl sym_2_1580
+sym_2_1580: la $2, sym_2_1580
+.globl sym_2_1581
+sym_2_1581: la $2, sym_2_1581
+.globl sym_2_1582
+sym_2_1582: la $2, sym_2_1582
+.globl sym_2_1583
+sym_2_1583: la $2, sym_2_1583
+.globl sym_2_1584
+sym_2_1584: la $2, sym_2_1584
+.globl sym_2_1585
+sym_2_1585: la $2, sym_2_1585
+.globl sym_2_1586
+sym_2_1586: la $2, sym_2_1586
+.globl sym_2_1587
+sym_2_1587: la $2, sym_2_1587
+.globl sym_2_1588
+sym_2_1588: la $2, sym_2_1588
+.globl sym_2_1589
+sym_2_1589: la $2, sym_2_1589
+.globl sym_2_1590
+sym_2_1590: la $2, sym_2_1590
+.globl sym_2_1591
+sym_2_1591: la $2, sym_2_1591
+.globl sym_2_1592
+sym_2_1592: la $2, sym_2_1592
+.globl sym_2_1593
+sym_2_1593: la $2, sym_2_1593
+.globl sym_2_1594
+sym_2_1594: la $2, sym_2_1594
+.globl sym_2_1595
+sym_2_1595: la $2, sym_2_1595
+.globl sym_2_1596
+sym_2_1596: la $2, sym_2_1596
+.globl sym_2_1597
+sym_2_1597: la $2, sym_2_1597
+.globl sym_2_1598
+sym_2_1598: la $2, sym_2_1598
+.globl sym_2_1599
+sym_2_1599: la $2, sym_2_1599
+.globl sym_2_1600
+sym_2_1600: la $2, sym_2_1600
+.globl sym_2_1601
+sym_2_1601: la $2, sym_2_1601
+.globl sym_2_1602
+sym_2_1602: la $2, sym_2_1602
+.globl sym_2_1603
+sym_2_1603: la $2, sym_2_1603
+.globl sym_2_1604
+sym_2_1604: la $2, sym_2_1604
+.globl sym_2_1605
+sym_2_1605: la $2, sym_2_1605
+.globl sym_2_1606
+sym_2_1606: la $2, sym_2_1606
+.globl sym_2_1607
+sym_2_1607: la $2, sym_2_1607
+.globl sym_2_1608
+sym_2_1608: la $2, sym_2_1608
+.globl sym_2_1609
+sym_2_1609: la $2, sym_2_1609
+.globl sym_2_1610
+sym_2_1610: la $2, sym_2_1610
+.globl sym_2_1611
+sym_2_1611: la $2, sym_2_1611
+.globl sym_2_1612
+sym_2_1612: la $2, sym_2_1612
+.globl sym_2_1613
+sym_2_1613: la $2, sym_2_1613
+.globl sym_2_1614
+sym_2_1614: la $2, sym_2_1614
+.globl sym_2_1615
+sym_2_1615: la $2, sym_2_1615
+.globl sym_2_1616
+sym_2_1616: la $2, sym_2_1616
+.globl sym_2_1617
+sym_2_1617: la $2, sym_2_1617
+.globl sym_2_1618
+sym_2_1618: la $2, sym_2_1618
+.globl sym_2_1619
+sym_2_1619: la $2, sym_2_1619
+.globl sym_2_1620
+sym_2_1620: la $2, sym_2_1620
+.globl sym_2_1621
+sym_2_1621: la $2, sym_2_1621
+.globl sym_2_1622
+sym_2_1622: la $2, sym_2_1622
+.globl sym_2_1623
+sym_2_1623: la $2, sym_2_1623
+.globl sym_2_1624
+sym_2_1624: la $2, sym_2_1624
+.globl sym_2_1625
+sym_2_1625: la $2, sym_2_1625
+.globl sym_2_1626
+sym_2_1626: la $2, sym_2_1626
+.globl sym_2_1627
+sym_2_1627: la $2, sym_2_1627
+.globl sym_2_1628
+sym_2_1628: la $2, sym_2_1628
+.globl sym_2_1629
+sym_2_1629: la $2, sym_2_1629
+.globl sym_2_1630
+sym_2_1630: la $2, sym_2_1630
+.globl sym_2_1631
+sym_2_1631: la $2, sym_2_1631
+.globl sym_2_1632
+sym_2_1632: la $2, sym_2_1632
+.globl sym_2_1633
+sym_2_1633: la $2, sym_2_1633
+.globl sym_2_1634
+sym_2_1634: la $2, sym_2_1634
+.globl sym_2_1635
+sym_2_1635: la $2, sym_2_1635
+.globl sym_2_1636
+sym_2_1636: la $2, sym_2_1636
+.globl sym_2_1637
+sym_2_1637: la $2, sym_2_1637
+.globl sym_2_1638
+sym_2_1638: la $2, sym_2_1638
+.globl sym_2_1639
+sym_2_1639: la $2, sym_2_1639
+.globl sym_2_1640
+sym_2_1640: la $2, sym_2_1640
+.globl sym_2_1641
+sym_2_1641: la $2, sym_2_1641
+.globl sym_2_1642
+sym_2_1642: la $2, sym_2_1642
+.globl sym_2_1643
+sym_2_1643: la $2, sym_2_1643
+.globl sym_2_1644
+sym_2_1644: la $2, sym_2_1644
+.globl sym_2_1645
+sym_2_1645: la $2, sym_2_1645
+.globl sym_2_1646
+sym_2_1646: la $2, sym_2_1646
+.globl sym_2_1647
+sym_2_1647: la $2, sym_2_1647
+.globl sym_2_1648
+sym_2_1648: la $2, sym_2_1648
+.globl sym_2_1649
+sym_2_1649: la $2, sym_2_1649
+.globl sym_2_1650
+sym_2_1650: la $2, sym_2_1650
+.globl sym_2_1651
+sym_2_1651: la $2, sym_2_1651
+.globl sym_2_1652
+sym_2_1652: la $2, sym_2_1652
+.globl sym_2_1653
+sym_2_1653: la $2, sym_2_1653
+.globl sym_2_1654
+sym_2_1654: la $2, sym_2_1654
+.globl sym_2_1655
+sym_2_1655: la $2, sym_2_1655
+.globl sym_2_1656
+sym_2_1656: la $2, sym_2_1656
+.globl sym_2_1657
+sym_2_1657: la $2, sym_2_1657
+.globl sym_2_1658
+sym_2_1658: la $2, sym_2_1658
+.globl sym_2_1659
+sym_2_1659: la $2, sym_2_1659
+.globl sym_2_1660
+sym_2_1660: la $2, sym_2_1660
+.globl sym_2_1661
+sym_2_1661: la $2, sym_2_1661
+.globl sym_2_1662
+sym_2_1662: la $2, sym_2_1662
+.globl sym_2_1663
+sym_2_1663: la $2, sym_2_1663
+.globl sym_2_1664
+sym_2_1664: la $2, sym_2_1664
+.globl sym_2_1665
+sym_2_1665: la $2, sym_2_1665
+.globl sym_2_1666
+sym_2_1666: la $2, sym_2_1666
+.globl sym_2_1667
+sym_2_1667: la $2, sym_2_1667
+.globl sym_2_1668
+sym_2_1668: la $2, sym_2_1668
+.globl sym_2_1669
+sym_2_1669: la $2, sym_2_1669
+.globl sym_2_1670
+sym_2_1670: la $2, sym_2_1670
+.globl sym_2_1671
+sym_2_1671: la $2, sym_2_1671
+.globl sym_2_1672
+sym_2_1672: la $2, sym_2_1672
+.globl sym_2_1673
+sym_2_1673: la $2, sym_2_1673
+.globl sym_2_1674
+sym_2_1674: la $2, sym_2_1674
+.globl sym_2_1675
+sym_2_1675: la $2, sym_2_1675
+.globl sym_2_1676
+sym_2_1676: la $2, sym_2_1676
+.globl sym_2_1677
+sym_2_1677: la $2, sym_2_1677
+.globl sym_2_1678
+sym_2_1678: la $2, sym_2_1678
+.globl sym_2_1679
+sym_2_1679: la $2, sym_2_1679
+.globl sym_2_1680
+sym_2_1680: la $2, sym_2_1680
+.globl sym_2_1681
+sym_2_1681: la $2, sym_2_1681
+.globl sym_2_1682
+sym_2_1682: la $2, sym_2_1682
+.globl sym_2_1683
+sym_2_1683: la $2, sym_2_1683
+.globl sym_2_1684
+sym_2_1684: la $2, sym_2_1684
+.globl sym_2_1685
+sym_2_1685: la $2, sym_2_1685
+.globl sym_2_1686
+sym_2_1686: la $2, sym_2_1686
+.globl sym_2_1687
+sym_2_1687: la $2, sym_2_1687
+.globl sym_2_1688
+sym_2_1688: la $2, sym_2_1688
+.globl sym_2_1689
+sym_2_1689: la $2, sym_2_1689
+.globl sym_2_1690
+sym_2_1690: la $2, sym_2_1690
+.globl sym_2_1691
+sym_2_1691: la $2, sym_2_1691
+.globl sym_2_1692
+sym_2_1692: la $2, sym_2_1692
+.globl sym_2_1693
+sym_2_1693: la $2, sym_2_1693
+.globl sym_2_1694
+sym_2_1694: la $2, sym_2_1694
+.globl sym_2_1695
+sym_2_1695: la $2, sym_2_1695
+.globl sym_2_1696
+sym_2_1696: la $2, sym_2_1696
+.globl sym_2_1697
+sym_2_1697: la $2, sym_2_1697
+.globl sym_2_1698
+sym_2_1698: la $2, sym_2_1698
+.globl sym_2_1699
+sym_2_1699: la $2, sym_2_1699
+.globl sym_2_1700
+sym_2_1700: la $2, sym_2_1700
+.globl sym_2_1701
+sym_2_1701: la $2, sym_2_1701
+.globl sym_2_1702
+sym_2_1702: la $2, sym_2_1702
+.globl sym_2_1703
+sym_2_1703: la $2, sym_2_1703
+.globl sym_2_1704
+sym_2_1704: la $2, sym_2_1704
+.globl sym_2_1705
+sym_2_1705: la $2, sym_2_1705
+.globl sym_2_1706
+sym_2_1706: la $2, sym_2_1706
+.globl sym_2_1707
+sym_2_1707: la $2, sym_2_1707
+.globl sym_2_1708
+sym_2_1708: la $2, sym_2_1708
+.globl sym_2_1709
+sym_2_1709: la $2, sym_2_1709
+.globl sym_2_1710
+sym_2_1710: la $2, sym_2_1710
+.globl sym_2_1711
+sym_2_1711: la $2, sym_2_1711
+.globl sym_2_1712
+sym_2_1712: la $2, sym_2_1712
+.globl sym_2_1713
+sym_2_1713: la $2, sym_2_1713
+.globl sym_2_1714
+sym_2_1714: la $2, sym_2_1714
+.globl sym_2_1715
+sym_2_1715: la $2, sym_2_1715
+.globl sym_2_1716
+sym_2_1716: la $2, sym_2_1716
+.globl sym_2_1717
+sym_2_1717: la $2, sym_2_1717
+.globl sym_2_1718
+sym_2_1718: la $2, sym_2_1718
+.globl sym_2_1719
+sym_2_1719: la $2, sym_2_1719
+.globl sym_2_1720
+sym_2_1720: la $2, sym_2_1720
+.globl sym_2_1721
+sym_2_1721: la $2, sym_2_1721
+.globl sym_2_1722
+sym_2_1722: la $2, sym_2_1722
+.globl sym_2_1723
+sym_2_1723: la $2, sym_2_1723
+.globl sym_2_1724
+sym_2_1724: la $2, sym_2_1724
+.globl sym_2_1725
+sym_2_1725: la $2, sym_2_1725
+.globl sym_2_1726
+sym_2_1726: la $2, sym_2_1726
+.globl sym_2_1727
+sym_2_1727: la $2, sym_2_1727
+.globl sym_2_1728
+sym_2_1728: la $2, sym_2_1728
+.globl sym_2_1729
+sym_2_1729: la $2, sym_2_1729
+.globl sym_2_1730
+sym_2_1730: la $2, sym_2_1730
+.globl sym_2_1731
+sym_2_1731: la $2, sym_2_1731
+.globl sym_2_1732
+sym_2_1732: la $2, sym_2_1732
+.globl sym_2_1733
+sym_2_1733: la $2, sym_2_1733
+.globl sym_2_1734
+sym_2_1734: la $2, sym_2_1734
+.globl sym_2_1735
+sym_2_1735: la $2, sym_2_1735
+.globl sym_2_1736
+sym_2_1736: la $2, sym_2_1736
+.globl sym_2_1737
+sym_2_1737: la $2, sym_2_1737
+.globl sym_2_1738
+sym_2_1738: la $2, sym_2_1738
+.globl sym_2_1739
+sym_2_1739: la $2, sym_2_1739
+.globl sym_2_1740
+sym_2_1740: la $2, sym_2_1740
+.globl sym_2_1741
+sym_2_1741: la $2, sym_2_1741
+.globl sym_2_1742
+sym_2_1742: la $2, sym_2_1742
+.globl sym_2_1743
+sym_2_1743: la $2, sym_2_1743
+.globl sym_2_1744
+sym_2_1744: la $2, sym_2_1744
+.globl sym_2_1745
+sym_2_1745: la $2, sym_2_1745
+.globl sym_2_1746
+sym_2_1746: la $2, sym_2_1746
+.globl sym_2_1747
+sym_2_1747: la $2, sym_2_1747
+.globl sym_2_1748
+sym_2_1748: la $2, sym_2_1748
+.globl sym_2_1749
+sym_2_1749: la $2, sym_2_1749
+.globl sym_2_1750
+sym_2_1750: la $2, sym_2_1750
+.globl sym_2_1751
+sym_2_1751: la $2, sym_2_1751
+.globl sym_2_1752
+sym_2_1752: la $2, sym_2_1752
+.globl sym_2_1753
+sym_2_1753: la $2, sym_2_1753
+.globl sym_2_1754
+sym_2_1754: la $2, sym_2_1754
+.globl sym_2_1755
+sym_2_1755: la $2, sym_2_1755
+.globl sym_2_1756
+sym_2_1756: la $2, sym_2_1756
+.globl sym_2_1757
+sym_2_1757: la $2, sym_2_1757
+.globl sym_2_1758
+sym_2_1758: la $2, sym_2_1758
+.globl sym_2_1759
+sym_2_1759: la $2, sym_2_1759
+.globl sym_2_1760
+sym_2_1760: la $2, sym_2_1760
+.globl sym_2_1761
+sym_2_1761: la $2, sym_2_1761
+.globl sym_2_1762
+sym_2_1762: la $2, sym_2_1762
+.globl sym_2_1763
+sym_2_1763: la $2, sym_2_1763
+.globl sym_2_1764
+sym_2_1764: la $2, sym_2_1764
+.globl sym_2_1765
+sym_2_1765: la $2, sym_2_1765
+.globl sym_2_1766
+sym_2_1766: la $2, sym_2_1766
+.globl sym_2_1767
+sym_2_1767: la $2, sym_2_1767
+.globl sym_2_1768
+sym_2_1768: la $2, sym_2_1768
+.globl sym_2_1769
+sym_2_1769: la $2, sym_2_1769
+.globl sym_2_1770
+sym_2_1770: la $2, sym_2_1770
+.globl sym_2_1771
+sym_2_1771: la $2, sym_2_1771
+.globl sym_2_1772
+sym_2_1772: la $2, sym_2_1772
+.globl sym_2_1773
+sym_2_1773: la $2, sym_2_1773
+.globl sym_2_1774
+sym_2_1774: la $2, sym_2_1774
+.globl sym_2_1775
+sym_2_1775: la $2, sym_2_1775
+.globl sym_2_1776
+sym_2_1776: la $2, sym_2_1776
+.globl sym_2_1777
+sym_2_1777: la $2, sym_2_1777
+.globl sym_2_1778
+sym_2_1778: la $2, sym_2_1778
+.globl sym_2_1779
+sym_2_1779: la $2, sym_2_1779
+.globl sym_2_1780
+sym_2_1780: la $2, sym_2_1780
+.globl sym_2_1781
+sym_2_1781: la $2, sym_2_1781
+.globl sym_2_1782
+sym_2_1782: la $2, sym_2_1782
+.globl sym_2_1783
+sym_2_1783: la $2, sym_2_1783
+.globl sym_2_1784
+sym_2_1784: la $2, sym_2_1784
+.globl sym_2_1785
+sym_2_1785: la $2, sym_2_1785
+.globl sym_2_1786
+sym_2_1786: la $2, sym_2_1786
+.globl sym_2_1787
+sym_2_1787: la $2, sym_2_1787
+.globl sym_2_1788
+sym_2_1788: la $2, sym_2_1788
+.globl sym_2_1789
+sym_2_1789: la $2, sym_2_1789
+.globl sym_2_1790
+sym_2_1790: la $2, sym_2_1790
+.globl sym_2_1791
+sym_2_1791: la $2, sym_2_1791
+.globl sym_2_1792
+sym_2_1792: la $2, sym_2_1792
+.globl sym_2_1793
+sym_2_1793: la $2, sym_2_1793
+.globl sym_2_1794
+sym_2_1794: la $2, sym_2_1794
+.globl sym_2_1795
+sym_2_1795: la $2, sym_2_1795
+.globl sym_2_1796
+sym_2_1796: la $2, sym_2_1796
+.globl sym_2_1797
+sym_2_1797: la $2, sym_2_1797
+.globl sym_2_1798
+sym_2_1798: la $2, sym_2_1798
+.globl sym_2_1799
+sym_2_1799: la $2, sym_2_1799
+.globl sym_2_1800
+sym_2_1800: la $2, sym_2_1800
+.globl sym_2_1801
+sym_2_1801: la $2, sym_2_1801
+.globl sym_2_1802
+sym_2_1802: la $2, sym_2_1802
+.globl sym_2_1803
+sym_2_1803: la $2, sym_2_1803
+.globl sym_2_1804
+sym_2_1804: la $2, sym_2_1804
+.globl sym_2_1805
+sym_2_1805: la $2, sym_2_1805
+.globl sym_2_1806
+sym_2_1806: la $2, sym_2_1806
+.globl sym_2_1807
+sym_2_1807: la $2, sym_2_1807
+.globl sym_2_1808
+sym_2_1808: la $2, sym_2_1808
+.globl sym_2_1809
+sym_2_1809: la $2, sym_2_1809
+.globl sym_2_1810
+sym_2_1810: la $2, sym_2_1810
+.globl sym_2_1811
+sym_2_1811: la $2, sym_2_1811
+.globl sym_2_1812
+sym_2_1812: la $2, sym_2_1812
+.globl sym_2_1813
+sym_2_1813: la $2, sym_2_1813
+.globl sym_2_1814
+sym_2_1814: la $2, sym_2_1814
+.globl sym_2_1815
+sym_2_1815: la $2, sym_2_1815
+.globl sym_2_1816
+sym_2_1816: la $2, sym_2_1816
+.globl sym_2_1817
+sym_2_1817: la $2, sym_2_1817
+.globl sym_2_1818
+sym_2_1818: la $2, sym_2_1818
+.globl sym_2_1819
+sym_2_1819: la $2, sym_2_1819
+.globl sym_2_1820
+sym_2_1820: la $2, sym_2_1820
+.globl sym_2_1821
+sym_2_1821: la $2, sym_2_1821
+.globl sym_2_1822
+sym_2_1822: la $2, sym_2_1822
+.globl sym_2_1823
+sym_2_1823: la $2, sym_2_1823
+.globl sym_2_1824
+sym_2_1824: la $2, sym_2_1824
+.globl sym_2_1825
+sym_2_1825: la $2, sym_2_1825
+.globl sym_2_1826
+sym_2_1826: la $2, sym_2_1826
+.globl sym_2_1827
+sym_2_1827: la $2, sym_2_1827
+.globl sym_2_1828
+sym_2_1828: la $2, sym_2_1828
+.globl sym_2_1829
+sym_2_1829: la $2, sym_2_1829
+.globl sym_2_1830
+sym_2_1830: la $2, sym_2_1830
+.globl sym_2_1831
+sym_2_1831: la $2, sym_2_1831
+.globl sym_2_1832
+sym_2_1832: la $2, sym_2_1832
+.globl sym_2_1833
+sym_2_1833: la $2, sym_2_1833
+.globl sym_2_1834
+sym_2_1834: la $2, sym_2_1834
+.globl sym_2_1835
+sym_2_1835: la $2, sym_2_1835
+.globl sym_2_1836
+sym_2_1836: la $2, sym_2_1836
+.globl sym_2_1837
+sym_2_1837: la $2, sym_2_1837
+.globl sym_2_1838
+sym_2_1838: la $2, sym_2_1838
+.globl sym_2_1839
+sym_2_1839: la $2, sym_2_1839
+.globl sym_2_1840
+sym_2_1840: la $2, sym_2_1840
+.globl sym_2_1841
+sym_2_1841: la $2, sym_2_1841
+.globl sym_2_1842
+sym_2_1842: la $2, sym_2_1842
+.globl sym_2_1843
+sym_2_1843: la $2, sym_2_1843
+.globl sym_2_1844
+sym_2_1844: la $2, sym_2_1844
+.globl sym_2_1845
+sym_2_1845: la $2, sym_2_1845
+.globl sym_2_1846
+sym_2_1846: la $2, sym_2_1846
+.globl sym_2_1847
+sym_2_1847: la $2, sym_2_1847
+.globl sym_2_1848
+sym_2_1848: la $2, sym_2_1848
+.globl sym_2_1849
+sym_2_1849: la $2, sym_2_1849
+.globl sym_2_1850
+sym_2_1850: la $2, sym_2_1850
+.globl sym_2_1851
+sym_2_1851: la $2, sym_2_1851
+.globl sym_2_1852
+sym_2_1852: la $2, sym_2_1852
+.globl sym_2_1853
+sym_2_1853: la $2, sym_2_1853
+.globl sym_2_1854
+sym_2_1854: la $2, sym_2_1854
+.globl sym_2_1855
+sym_2_1855: la $2, sym_2_1855
+.globl sym_2_1856
+sym_2_1856: la $2, sym_2_1856
+.globl sym_2_1857
+sym_2_1857: la $2, sym_2_1857
+.globl sym_2_1858
+sym_2_1858: la $2, sym_2_1858
+.globl sym_2_1859
+sym_2_1859: la $2, sym_2_1859
+.globl sym_2_1860
+sym_2_1860: la $2, sym_2_1860
+.globl sym_2_1861
+sym_2_1861: la $2, sym_2_1861
+.globl sym_2_1862
+sym_2_1862: la $2, sym_2_1862
+.globl sym_2_1863
+sym_2_1863: la $2, sym_2_1863
+.globl sym_2_1864
+sym_2_1864: la $2, sym_2_1864
+.globl sym_2_1865
+sym_2_1865: la $2, sym_2_1865
+.globl sym_2_1866
+sym_2_1866: la $2, sym_2_1866
+.globl sym_2_1867
+sym_2_1867: la $2, sym_2_1867
+.globl sym_2_1868
+sym_2_1868: la $2, sym_2_1868
+.globl sym_2_1869
+sym_2_1869: la $2, sym_2_1869
+.globl sym_2_1870
+sym_2_1870: la $2, sym_2_1870
+.globl sym_2_1871
+sym_2_1871: la $2, sym_2_1871
+.globl sym_2_1872
+sym_2_1872: la $2, sym_2_1872
+.globl sym_2_1873
+sym_2_1873: la $2, sym_2_1873
+.globl sym_2_1874
+sym_2_1874: la $2, sym_2_1874
+.globl sym_2_1875
+sym_2_1875: la $2, sym_2_1875
+.globl sym_2_1876
+sym_2_1876: la $2, sym_2_1876
+.globl sym_2_1877
+sym_2_1877: la $2, sym_2_1877
+.globl sym_2_1878
+sym_2_1878: la $2, sym_2_1878
+.globl sym_2_1879
+sym_2_1879: la $2, sym_2_1879
+.globl sym_2_1880
+sym_2_1880: la $2, sym_2_1880
+.globl sym_2_1881
+sym_2_1881: la $2, sym_2_1881
+.globl sym_2_1882
+sym_2_1882: la $2, sym_2_1882
+.globl sym_2_1883
+sym_2_1883: la $2, sym_2_1883
+.globl sym_2_1884
+sym_2_1884: la $2, sym_2_1884
+.globl sym_2_1885
+sym_2_1885: la $2, sym_2_1885
+.globl sym_2_1886
+sym_2_1886: la $2, sym_2_1886
+.globl sym_2_1887
+sym_2_1887: la $2, sym_2_1887
+.globl sym_2_1888
+sym_2_1888: la $2, sym_2_1888
+.globl sym_2_1889
+sym_2_1889: la $2, sym_2_1889
+.globl sym_2_1890
+sym_2_1890: la $2, sym_2_1890
+.globl sym_2_1891
+sym_2_1891: la $2, sym_2_1891
+.globl sym_2_1892
+sym_2_1892: la $2, sym_2_1892
+.globl sym_2_1893
+sym_2_1893: la $2, sym_2_1893
+.globl sym_2_1894
+sym_2_1894: la $2, sym_2_1894
+.globl sym_2_1895
+sym_2_1895: la $2, sym_2_1895
+.globl sym_2_1896
+sym_2_1896: la $2, sym_2_1896
+.globl sym_2_1897
+sym_2_1897: la $2, sym_2_1897
+.globl sym_2_1898
+sym_2_1898: la $2, sym_2_1898
+.globl sym_2_1899
+sym_2_1899: la $2, sym_2_1899
+.globl sym_2_1900
+sym_2_1900: la $2, sym_2_1900
+.globl sym_2_1901
+sym_2_1901: la $2, sym_2_1901
+.globl sym_2_1902
+sym_2_1902: la $2, sym_2_1902
+.globl sym_2_1903
+sym_2_1903: la $2, sym_2_1903
+.globl sym_2_1904
+sym_2_1904: la $2, sym_2_1904
+.globl sym_2_1905
+sym_2_1905: la $2, sym_2_1905
+.globl sym_2_1906
+sym_2_1906: la $2, sym_2_1906
+.globl sym_2_1907
+sym_2_1907: la $2, sym_2_1907
+.globl sym_2_1908
+sym_2_1908: la $2, sym_2_1908
+.globl sym_2_1909
+sym_2_1909: la $2, sym_2_1909
+.globl sym_2_1910
+sym_2_1910: la $2, sym_2_1910
+.globl sym_2_1911
+sym_2_1911: la $2, sym_2_1911
+.globl sym_2_1912
+sym_2_1912: la $2, sym_2_1912
+.globl sym_2_1913
+sym_2_1913: la $2, sym_2_1913
+.globl sym_2_1914
+sym_2_1914: la $2, sym_2_1914
+.globl sym_2_1915
+sym_2_1915: la $2, sym_2_1915
+.globl sym_2_1916
+sym_2_1916: la $2, sym_2_1916
+.globl sym_2_1917
+sym_2_1917: la $2, sym_2_1917
+.globl sym_2_1918
+sym_2_1918: la $2, sym_2_1918
+.globl sym_2_1919
+sym_2_1919: la $2, sym_2_1919
+.globl sym_2_1920
+sym_2_1920: la $2, sym_2_1920
+.globl sym_2_1921
+sym_2_1921: la $2, sym_2_1921
+.globl sym_2_1922
+sym_2_1922: la $2, sym_2_1922
+.globl sym_2_1923
+sym_2_1923: la $2, sym_2_1923
+.globl sym_2_1924
+sym_2_1924: la $2, sym_2_1924
+.globl sym_2_1925
+sym_2_1925: la $2, sym_2_1925
+.globl sym_2_1926
+sym_2_1926: la $2, sym_2_1926
+.globl sym_2_1927
+sym_2_1927: la $2, sym_2_1927
+.globl sym_2_1928
+sym_2_1928: la $2, sym_2_1928
+.globl sym_2_1929
+sym_2_1929: la $2, sym_2_1929
+.globl sym_2_1930
+sym_2_1930: la $2, sym_2_1930
+.globl sym_2_1931
+sym_2_1931: la $2, sym_2_1931
+.globl sym_2_1932
+sym_2_1932: la $2, sym_2_1932
+.globl sym_2_1933
+sym_2_1933: la $2, sym_2_1933
+.globl sym_2_1934
+sym_2_1934: la $2, sym_2_1934
+.globl sym_2_1935
+sym_2_1935: la $2, sym_2_1935
+.globl sym_2_1936
+sym_2_1936: la $2, sym_2_1936
+.globl sym_2_1937
+sym_2_1937: la $2, sym_2_1937
+.globl sym_2_1938
+sym_2_1938: la $2, sym_2_1938
+.globl sym_2_1939
+sym_2_1939: la $2, sym_2_1939
+.globl sym_2_1940
+sym_2_1940: la $2, sym_2_1940
+.globl sym_2_1941
+sym_2_1941: la $2, sym_2_1941
+.globl sym_2_1942
+sym_2_1942: la $2, sym_2_1942
+.globl sym_2_1943
+sym_2_1943: la $2, sym_2_1943
+.globl sym_2_1944
+sym_2_1944: la $2, sym_2_1944
+.globl sym_2_1945
+sym_2_1945: la $2, sym_2_1945
+.globl sym_2_1946
+sym_2_1946: la $2, sym_2_1946
+.globl sym_2_1947
+sym_2_1947: la $2, sym_2_1947
+.globl sym_2_1948
+sym_2_1948: la $2, sym_2_1948
+.globl sym_2_1949
+sym_2_1949: la $2, sym_2_1949
+.globl sym_2_1950
+sym_2_1950: la $2, sym_2_1950
+.globl sym_2_1951
+sym_2_1951: la $2, sym_2_1951
+.globl sym_2_1952
+sym_2_1952: la $2, sym_2_1952
+.globl sym_2_1953
+sym_2_1953: la $2, sym_2_1953
+.globl sym_2_1954
+sym_2_1954: la $2, sym_2_1954
+.globl sym_2_1955
+sym_2_1955: la $2, sym_2_1955
+.globl sym_2_1956
+sym_2_1956: la $2, sym_2_1956
+.globl sym_2_1957
+sym_2_1957: la $2, sym_2_1957
+.globl sym_2_1958
+sym_2_1958: la $2, sym_2_1958
+.globl sym_2_1959
+sym_2_1959: la $2, sym_2_1959
+.globl sym_2_1960
+sym_2_1960: la $2, sym_2_1960
+.globl sym_2_1961
+sym_2_1961: la $2, sym_2_1961
+.globl sym_2_1962
+sym_2_1962: la $2, sym_2_1962
+.globl sym_2_1963
+sym_2_1963: la $2, sym_2_1963
+.globl sym_2_1964
+sym_2_1964: la $2, sym_2_1964
+.globl sym_2_1965
+sym_2_1965: la $2, sym_2_1965
+.globl sym_2_1966
+sym_2_1966: la $2, sym_2_1966
+.globl sym_2_1967
+sym_2_1967: la $2, sym_2_1967
+.globl sym_2_1968
+sym_2_1968: la $2, sym_2_1968
+.globl sym_2_1969
+sym_2_1969: la $2, sym_2_1969
+.globl sym_2_1970
+sym_2_1970: la $2, sym_2_1970
+.globl sym_2_1971
+sym_2_1971: la $2, sym_2_1971
+.globl sym_2_1972
+sym_2_1972: la $2, sym_2_1972
+.globl sym_2_1973
+sym_2_1973: la $2, sym_2_1973
+.globl sym_2_1974
+sym_2_1974: la $2, sym_2_1974
+.globl sym_2_1975
+sym_2_1975: la $2, sym_2_1975
+.globl sym_2_1976
+sym_2_1976: la $2, sym_2_1976
+.globl sym_2_1977
+sym_2_1977: la $2, sym_2_1977
+.globl sym_2_1978
+sym_2_1978: la $2, sym_2_1978
+.globl sym_2_1979
+sym_2_1979: la $2, sym_2_1979
+.globl sym_2_1980
+sym_2_1980: la $2, sym_2_1980
+.globl sym_2_1981
+sym_2_1981: la $2, sym_2_1981
+.globl sym_2_1982
+sym_2_1982: la $2, sym_2_1982
+.globl sym_2_1983
+sym_2_1983: la $2, sym_2_1983
+.globl sym_2_1984
+sym_2_1984: la $2, sym_2_1984
+.globl sym_2_1985
+sym_2_1985: la $2, sym_2_1985
+.globl sym_2_1986
+sym_2_1986: la $2, sym_2_1986
+.globl sym_2_1987
+sym_2_1987: la $2, sym_2_1987
+.globl sym_2_1988
+sym_2_1988: la $2, sym_2_1988
+.globl sym_2_1989
+sym_2_1989: la $2, sym_2_1989
+.globl sym_2_1990
+sym_2_1990: la $2, sym_2_1990
+.globl sym_2_1991
+sym_2_1991: la $2, sym_2_1991
+.globl sym_2_1992
+sym_2_1992: la $2, sym_2_1992
+.globl sym_2_1993
+sym_2_1993: la $2, sym_2_1993
+.globl sym_2_1994
+sym_2_1994: la $2, sym_2_1994
+.globl sym_2_1995
+sym_2_1995: la $2, sym_2_1995
+.globl sym_2_1996
+sym_2_1996: la $2, sym_2_1996
+.globl sym_2_1997
+sym_2_1997: la $2, sym_2_1997
+.globl sym_2_1998
+sym_2_1998: la $2, sym_2_1998
+.globl sym_2_1999
+sym_2_1999: la $2, sym_2_1999
+.globl sym_2_2000
+sym_2_2000: la $2, sym_2_2000
+.globl sym_2_2001
+sym_2_2001: la $2, sym_2_2001
+.globl sym_2_2002
+sym_2_2002: la $2, sym_2_2002
+.globl sym_2_2003
+sym_2_2003: la $2, sym_2_2003
+.globl sym_2_2004
+sym_2_2004: la $2, sym_2_2004
+.globl sym_2_2005
+sym_2_2005: la $2, sym_2_2005
+.globl sym_2_2006
+sym_2_2006: la $2, sym_2_2006
+.globl sym_2_2007
+sym_2_2007: la $2, sym_2_2007
+.globl sym_2_2008
+sym_2_2008: la $2, sym_2_2008
+.globl sym_2_2009
+sym_2_2009: la $2, sym_2_2009
+.globl sym_2_2010
+sym_2_2010: la $2, sym_2_2010
+.globl sym_2_2011
+sym_2_2011: la $2, sym_2_2011
+.globl sym_2_2012
+sym_2_2012: la $2, sym_2_2012
+.globl sym_2_2013
+sym_2_2013: la $2, sym_2_2013
+.globl sym_2_2014
+sym_2_2014: la $2, sym_2_2014
+.globl sym_2_2015
+sym_2_2015: la $2, sym_2_2015
+.globl sym_2_2016
+sym_2_2016: la $2, sym_2_2016
+.globl sym_2_2017
+sym_2_2017: la $2, sym_2_2017
+.globl sym_2_2018
+sym_2_2018: la $2, sym_2_2018
+.globl sym_2_2019
+sym_2_2019: la $2, sym_2_2019
+.globl sym_2_2020
+sym_2_2020: la $2, sym_2_2020
+.globl sym_2_2021
+sym_2_2021: la $2, sym_2_2021
+.globl sym_2_2022
+sym_2_2022: la $2, sym_2_2022
+.globl sym_2_2023
+sym_2_2023: la $2, sym_2_2023
+.globl sym_2_2024
+sym_2_2024: la $2, sym_2_2024
+.globl sym_2_2025
+sym_2_2025: la $2, sym_2_2025
+.globl sym_2_2026
+sym_2_2026: la $2, sym_2_2026
+.globl sym_2_2027
+sym_2_2027: la $2, sym_2_2027
+.globl sym_2_2028
+sym_2_2028: la $2, sym_2_2028
+.globl sym_2_2029
+sym_2_2029: la $2, sym_2_2029
+.globl sym_2_2030
+sym_2_2030: la $2, sym_2_2030
+.globl sym_2_2031
+sym_2_2031: la $2, sym_2_2031
+.globl sym_2_2032
+sym_2_2032: la $2, sym_2_2032
+.globl sym_2_2033
+sym_2_2033: la $2, sym_2_2033
+.globl sym_2_2034
+sym_2_2034: la $2, sym_2_2034
+.globl sym_2_2035
+sym_2_2035: la $2, sym_2_2035
+.globl sym_2_2036
+sym_2_2036: la $2, sym_2_2036
+.globl sym_2_2037
+sym_2_2037: la $2, sym_2_2037
+.globl sym_2_2038
+sym_2_2038: la $2, sym_2_2038
+.globl sym_2_2039
+sym_2_2039: la $2, sym_2_2039
+.globl sym_2_2040
+sym_2_2040: la $2, sym_2_2040
+.globl sym_2_2041
+sym_2_2041: la $2, sym_2_2041
+.globl sym_2_2042
+sym_2_2042: la $2, sym_2_2042
+.globl sym_2_2043
+sym_2_2043: la $2, sym_2_2043
+.globl sym_2_2044
+sym_2_2044: la $2, sym_2_2044
+.globl sym_2_2045
+sym_2_2045: la $2, sym_2_2045
+.globl sym_2_2046
+sym_2_2046: la $2, sym_2_2046
+.globl sym_2_2047
+sym_2_2047: la $2, sym_2_2047
+.globl sym_2_2048
+sym_2_2048: la $2, sym_2_2048
+.globl sym_2_2049
+sym_2_2049: la $2, sym_2_2049
+.globl sym_2_2050
+sym_2_2050: la $2, sym_2_2050
+.globl sym_2_2051
+sym_2_2051: la $2, sym_2_2051
+.globl sym_2_2052
+sym_2_2052: la $2, sym_2_2052
+.globl sym_2_2053
+sym_2_2053: la $2, sym_2_2053
+.globl sym_2_2054
+sym_2_2054: la $2, sym_2_2054
+.globl sym_2_2055
+sym_2_2055: la $2, sym_2_2055
+.globl sym_2_2056
+sym_2_2056: la $2, sym_2_2056
+.globl sym_2_2057
+sym_2_2057: la $2, sym_2_2057
+.globl sym_2_2058
+sym_2_2058: la $2, sym_2_2058
+.globl sym_2_2059
+sym_2_2059: la $2, sym_2_2059
+.globl sym_2_2060
+sym_2_2060: la $2, sym_2_2060
+.globl sym_2_2061
+sym_2_2061: la $2, sym_2_2061
+.globl sym_2_2062
+sym_2_2062: la $2, sym_2_2062
+.globl sym_2_2063
+sym_2_2063: la $2, sym_2_2063
+.globl sym_2_2064
+sym_2_2064: la $2, sym_2_2064
+.globl sym_2_2065
+sym_2_2065: la $2, sym_2_2065
+.globl sym_2_2066
+sym_2_2066: la $2, sym_2_2066
+.globl sym_2_2067
+sym_2_2067: la $2, sym_2_2067
+.globl sym_2_2068
+sym_2_2068: la $2, sym_2_2068
+.globl sym_2_2069
+sym_2_2069: la $2, sym_2_2069
+.globl sym_2_2070
+sym_2_2070: la $2, sym_2_2070
+.globl sym_2_2071
+sym_2_2071: la $2, sym_2_2071
+.globl sym_2_2072
+sym_2_2072: la $2, sym_2_2072
+.globl sym_2_2073
+sym_2_2073: la $2, sym_2_2073
+.globl sym_2_2074
+sym_2_2074: la $2, sym_2_2074
+.globl sym_2_2075
+sym_2_2075: la $2, sym_2_2075
+.globl sym_2_2076
+sym_2_2076: la $2, sym_2_2076
+.globl sym_2_2077
+sym_2_2077: la $2, sym_2_2077
+.globl sym_2_2078
+sym_2_2078: la $2, sym_2_2078
+.globl sym_2_2079
+sym_2_2079: la $2, sym_2_2079
+.globl sym_2_2080
+sym_2_2080: la $2, sym_2_2080
+.globl sym_2_2081
+sym_2_2081: la $2, sym_2_2081
+.globl sym_2_2082
+sym_2_2082: la $2, sym_2_2082
+.globl sym_2_2083
+sym_2_2083: la $2, sym_2_2083
+.globl sym_2_2084
+sym_2_2084: la $2, sym_2_2084
+.globl sym_2_2085
+sym_2_2085: la $2, sym_2_2085
+.globl sym_2_2086
+sym_2_2086: la $2, sym_2_2086
+.globl sym_2_2087
+sym_2_2087: la $2, sym_2_2087
+.globl sym_2_2088
+sym_2_2088: la $2, sym_2_2088
+.globl sym_2_2089
+sym_2_2089: la $2, sym_2_2089
+.globl sym_2_2090
+sym_2_2090: la $2, sym_2_2090
+.globl sym_2_2091
+sym_2_2091: la $2, sym_2_2091
+.globl sym_2_2092
+sym_2_2092: la $2, sym_2_2092
+.globl sym_2_2093
+sym_2_2093: la $2, sym_2_2093
+.globl sym_2_2094
+sym_2_2094: la $2, sym_2_2094
+.globl sym_2_2095
+sym_2_2095: la $2, sym_2_2095
+.globl sym_2_2096
+sym_2_2096: la $2, sym_2_2096
+.globl sym_2_2097
+sym_2_2097: la $2, sym_2_2097
+.globl sym_2_2098
+sym_2_2098: la $2, sym_2_2098
+.globl sym_2_2099
+sym_2_2099: la $2, sym_2_2099
+.globl sym_2_2100
+sym_2_2100: la $2, sym_2_2100
+.globl sym_2_2101
+sym_2_2101: la $2, sym_2_2101
+.globl sym_2_2102
+sym_2_2102: la $2, sym_2_2102
+.globl sym_2_2103
+sym_2_2103: la $2, sym_2_2103
+.globl sym_2_2104
+sym_2_2104: la $2, sym_2_2104
+.globl sym_2_2105
+sym_2_2105: la $2, sym_2_2105
+.globl sym_2_2106
+sym_2_2106: la $2, sym_2_2106
+.globl sym_2_2107
+sym_2_2107: la $2, sym_2_2107
+.globl sym_2_2108
+sym_2_2108: la $2, sym_2_2108
+.globl sym_2_2109
+sym_2_2109: la $2, sym_2_2109
+.globl sym_2_2110
+sym_2_2110: la $2, sym_2_2110
+.globl sym_2_2111
+sym_2_2111: la $2, sym_2_2111
+.globl sym_2_2112
+sym_2_2112: la $2, sym_2_2112
+.globl sym_2_2113
+sym_2_2113: la $2, sym_2_2113
+.globl sym_2_2114
+sym_2_2114: la $2, sym_2_2114
+.globl sym_2_2115
+sym_2_2115: la $2, sym_2_2115
+.globl sym_2_2116
+sym_2_2116: la $2, sym_2_2116
+.globl sym_2_2117
+sym_2_2117: la $2, sym_2_2117
+.globl sym_2_2118
+sym_2_2118: la $2, sym_2_2118
+.globl sym_2_2119
+sym_2_2119: la $2, sym_2_2119
+.globl sym_2_2120
+sym_2_2120: la $2, sym_2_2120
+.globl sym_2_2121
+sym_2_2121: la $2, sym_2_2121
+.globl sym_2_2122
+sym_2_2122: la $2, sym_2_2122
+.globl sym_2_2123
+sym_2_2123: la $2, sym_2_2123
+.globl sym_2_2124
+sym_2_2124: la $2, sym_2_2124
+.globl sym_2_2125
+sym_2_2125: la $2, sym_2_2125
+.globl sym_2_2126
+sym_2_2126: la $2, sym_2_2126
+.globl sym_2_2127
+sym_2_2127: la $2, sym_2_2127
+.globl sym_2_2128
+sym_2_2128: la $2, sym_2_2128
+.globl sym_2_2129
+sym_2_2129: la $2, sym_2_2129
+.globl sym_2_2130
+sym_2_2130: la $2, sym_2_2130
+.globl sym_2_2131
+sym_2_2131: la $2, sym_2_2131
+.globl sym_2_2132
+sym_2_2132: la $2, sym_2_2132
+.globl sym_2_2133
+sym_2_2133: la $2, sym_2_2133
+.globl sym_2_2134
+sym_2_2134: la $2, sym_2_2134
+.globl sym_2_2135
+sym_2_2135: la $2, sym_2_2135
+.globl sym_2_2136
+sym_2_2136: la $2, sym_2_2136
+.globl sym_2_2137
+sym_2_2137: la $2, sym_2_2137
+.globl sym_2_2138
+sym_2_2138: la $2, sym_2_2138
+.globl sym_2_2139
+sym_2_2139: la $2, sym_2_2139
+.globl sym_2_2140
+sym_2_2140: la $2, sym_2_2140
+.globl sym_2_2141
+sym_2_2141: la $2, sym_2_2141
+.globl sym_2_2142
+sym_2_2142: la $2, sym_2_2142
+.globl sym_2_2143
+sym_2_2143: la $2, sym_2_2143
+.globl sym_2_2144
+sym_2_2144: la $2, sym_2_2144
+.globl sym_2_2145
+sym_2_2145: la $2, sym_2_2145
+.globl sym_2_2146
+sym_2_2146: la $2, sym_2_2146
+.globl sym_2_2147
+sym_2_2147: la $2, sym_2_2147
+.globl sym_2_2148
+sym_2_2148: la $2, sym_2_2148
+.globl sym_2_2149
+sym_2_2149: la $2, sym_2_2149
+.globl sym_2_2150
+sym_2_2150: la $2, sym_2_2150
+.globl sym_2_2151
+sym_2_2151: la $2, sym_2_2151
+.globl sym_2_2152
+sym_2_2152: la $2, sym_2_2152
+.globl sym_2_2153
+sym_2_2153: la $2, sym_2_2153
+.globl sym_2_2154
+sym_2_2154: la $2, sym_2_2154
+.globl sym_2_2155
+sym_2_2155: la $2, sym_2_2155
+.globl sym_2_2156
+sym_2_2156: la $2, sym_2_2156
+.globl sym_2_2157
+sym_2_2157: la $2, sym_2_2157
+.globl sym_2_2158
+sym_2_2158: la $2, sym_2_2158
+.globl sym_2_2159
+sym_2_2159: la $2, sym_2_2159
+.globl sym_2_2160
+sym_2_2160: la $2, sym_2_2160
+.globl sym_2_2161
+sym_2_2161: la $2, sym_2_2161
+.globl sym_2_2162
+sym_2_2162: la $2, sym_2_2162
+.globl sym_2_2163
+sym_2_2163: la $2, sym_2_2163
+.globl sym_2_2164
+sym_2_2164: la $2, sym_2_2164
+.globl sym_2_2165
+sym_2_2165: la $2, sym_2_2165
+.globl sym_2_2166
+sym_2_2166: la $2, sym_2_2166
+.globl sym_2_2167
+sym_2_2167: la $2, sym_2_2167
+.globl sym_2_2168
+sym_2_2168: la $2, sym_2_2168
+.globl sym_2_2169
+sym_2_2169: la $2, sym_2_2169
+.globl sym_2_2170
+sym_2_2170: la $2, sym_2_2170
+.globl sym_2_2171
+sym_2_2171: la $2, sym_2_2171
+.globl sym_2_2172
+sym_2_2172: la $2, sym_2_2172
+.globl sym_2_2173
+sym_2_2173: la $2, sym_2_2173
+.globl sym_2_2174
+sym_2_2174: la $2, sym_2_2174
+.globl sym_2_2175
+sym_2_2175: la $2, sym_2_2175
+.globl sym_2_2176
+sym_2_2176: la $2, sym_2_2176
+.globl sym_2_2177
+sym_2_2177: la $2, sym_2_2177
+.globl sym_2_2178
+sym_2_2178: la $2, sym_2_2178
+.globl sym_2_2179
+sym_2_2179: la $2, sym_2_2179
+.globl sym_2_2180
+sym_2_2180: la $2, sym_2_2180
+.globl sym_2_2181
+sym_2_2181: la $2, sym_2_2181
+.globl sym_2_2182
+sym_2_2182: la $2, sym_2_2182
+.globl sym_2_2183
+sym_2_2183: la $2, sym_2_2183
+.globl sym_2_2184
+sym_2_2184: la $2, sym_2_2184
+.globl sym_2_2185
+sym_2_2185: la $2, sym_2_2185
+.globl sym_2_2186
+sym_2_2186: la $2, sym_2_2186
+.globl sym_2_2187
+sym_2_2187: la $2, sym_2_2187
+.globl sym_2_2188
+sym_2_2188: la $2, sym_2_2188
+.globl sym_2_2189
+sym_2_2189: la $2, sym_2_2189
+.globl sym_2_2190
+sym_2_2190: la $2, sym_2_2190
+.globl sym_2_2191
+sym_2_2191: la $2, sym_2_2191
+.globl sym_2_2192
+sym_2_2192: la $2, sym_2_2192
+.globl sym_2_2193
+sym_2_2193: la $2, sym_2_2193
+.globl sym_2_2194
+sym_2_2194: la $2, sym_2_2194
+.globl sym_2_2195
+sym_2_2195: la $2, sym_2_2195
+.globl sym_2_2196
+sym_2_2196: la $2, sym_2_2196
+.globl sym_2_2197
+sym_2_2197: la $2, sym_2_2197
+.globl sym_2_2198
+sym_2_2198: la $2, sym_2_2198
+.globl sym_2_2199
+sym_2_2199: la $2, sym_2_2199
+.globl sym_2_2200
+sym_2_2200: la $2, sym_2_2200
+.globl sym_2_2201
+sym_2_2201: la $2, sym_2_2201
+.globl sym_2_2202
+sym_2_2202: la $2, sym_2_2202
+.globl sym_2_2203
+sym_2_2203: la $2, sym_2_2203
+.globl sym_2_2204
+sym_2_2204: la $2, sym_2_2204
+.globl sym_2_2205
+sym_2_2205: la $2, sym_2_2205
+.globl sym_2_2206
+sym_2_2206: la $2, sym_2_2206
+.globl sym_2_2207
+sym_2_2207: la $2, sym_2_2207
+.globl sym_2_2208
+sym_2_2208: la $2, sym_2_2208
+.globl sym_2_2209
+sym_2_2209: la $2, sym_2_2209
+.globl sym_2_2210
+sym_2_2210: la $2, sym_2_2210
+.globl sym_2_2211
+sym_2_2211: la $2, sym_2_2211
+.globl sym_2_2212
+sym_2_2212: la $2, sym_2_2212
+.globl sym_2_2213
+sym_2_2213: la $2, sym_2_2213
+.globl sym_2_2214
+sym_2_2214: la $2, sym_2_2214
+.globl sym_2_2215
+sym_2_2215: la $2, sym_2_2215
+.globl sym_2_2216
+sym_2_2216: la $2, sym_2_2216
+.globl sym_2_2217
+sym_2_2217: la $2, sym_2_2217
+.globl sym_2_2218
+sym_2_2218: la $2, sym_2_2218
+.globl sym_2_2219
+sym_2_2219: la $2, sym_2_2219
+.globl sym_2_2220
+sym_2_2220: la $2, sym_2_2220
+.globl sym_2_2221
+sym_2_2221: la $2, sym_2_2221
+.globl sym_2_2222
+sym_2_2222: la $2, sym_2_2222
+.globl sym_2_2223
+sym_2_2223: la $2, sym_2_2223
+.globl sym_2_2224
+sym_2_2224: la $2, sym_2_2224
+.globl sym_2_2225
+sym_2_2225: la $2, sym_2_2225
+.globl sym_2_2226
+sym_2_2226: la $2, sym_2_2226
+.globl sym_2_2227
+sym_2_2227: la $2, sym_2_2227
+.globl sym_2_2228
+sym_2_2228: la $2, sym_2_2228
+.globl sym_2_2229
+sym_2_2229: la $2, sym_2_2229
+.globl sym_2_2230
+sym_2_2230: la $2, sym_2_2230
+.globl sym_2_2231
+sym_2_2231: la $2, sym_2_2231
+.globl sym_2_2232
+sym_2_2232: la $2, sym_2_2232
+.globl sym_2_2233
+sym_2_2233: la $2, sym_2_2233
+.globl sym_2_2234
+sym_2_2234: la $2, sym_2_2234
+.globl sym_2_2235
+sym_2_2235: la $2, sym_2_2235
+.globl sym_2_2236
+sym_2_2236: la $2, sym_2_2236
+.globl sym_2_2237
+sym_2_2237: la $2, sym_2_2237
+.globl sym_2_2238
+sym_2_2238: la $2, sym_2_2238
+.globl sym_2_2239
+sym_2_2239: la $2, sym_2_2239
+.globl sym_2_2240
+sym_2_2240: la $2, sym_2_2240
+.globl sym_2_2241
+sym_2_2241: la $2, sym_2_2241
+.globl sym_2_2242
+sym_2_2242: la $2, sym_2_2242
+.globl sym_2_2243
+sym_2_2243: la $2, sym_2_2243
+.globl sym_2_2244
+sym_2_2244: la $2, sym_2_2244
+.globl sym_2_2245
+sym_2_2245: la $2, sym_2_2245
+.globl sym_2_2246
+sym_2_2246: la $2, sym_2_2246
+.globl sym_2_2247
+sym_2_2247: la $2, sym_2_2247
+.globl sym_2_2248
+sym_2_2248: la $2, sym_2_2248
+.globl sym_2_2249
+sym_2_2249: la $2, sym_2_2249
+.globl sym_2_2250
+sym_2_2250: la $2, sym_2_2250
+.globl sym_2_2251
+sym_2_2251: la $2, sym_2_2251
+.globl sym_2_2252
+sym_2_2252: la $2, sym_2_2252
+.globl sym_2_2253
+sym_2_2253: la $2, sym_2_2253
+.globl sym_2_2254
+sym_2_2254: la $2, sym_2_2254
+.globl sym_2_2255
+sym_2_2255: la $2, sym_2_2255
+.globl sym_2_2256
+sym_2_2256: la $2, sym_2_2256
+.globl sym_2_2257
+sym_2_2257: la $2, sym_2_2257
+.globl sym_2_2258
+sym_2_2258: la $2, sym_2_2258
+.globl sym_2_2259
+sym_2_2259: la $2, sym_2_2259
+.globl sym_2_2260
+sym_2_2260: la $2, sym_2_2260
+.globl sym_2_2261
+sym_2_2261: la $2, sym_2_2261
+.globl sym_2_2262
+sym_2_2262: la $2, sym_2_2262
+.globl sym_2_2263
+sym_2_2263: la $2, sym_2_2263
+.globl sym_2_2264
+sym_2_2264: la $2, sym_2_2264
+.globl sym_2_2265
+sym_2_2265: la $2, sym_2_2265
+.globl sym_2_2266
+sym_2_2266: la $2, sym_2_2266
+.globl sym_2_2267
+sym_2_2267: la $2, sym_2_2267
+.globl sym_2_2268
+sym_2_2268: la $2, sym_2_2268
+.globl sym_2_2269
+sym_2_2269: la $2, sym_2_2269
+.globl sym_2_2270
+sym_2_2270: la $2, sym_2_2270
+.globl sym_2_2271
+sym_2_2271: la $2, sym_2_2271
+.globl sym_2_2272
+sym_2_2272: la $2, sym_2_2272
+.globl sym_2_2273
+sym_2_2273: la $2, sym_2_2273
+.globl sym_2_2274
+sym_2_2274: la $2, sym_2_2274
+.globl sym_2_2275
+sym_2_2275: la $2, sym_2_2275
+.globl sym_2_2276
+sym_2_2276: la $2, sym_2_2276
+.globl sym_2_2277
+sym_2_2277: la $2, sym_2_2277
+.globl sym_2_2278
+sym_2_2278: la $2, sym_2_2278
+.globl sym_2_2279
+sym_2_2279: la $2, sym_2_2279
+.globl sym_2_2280
+sym_2_2280: la $2, sym_2_2280
+.globl sym_2_2281
+sym_2_2281: la $2, sym_2_2281
+.globl sym_2_2282
+sym_2_2282: la $2, sym_2_2282
+.globl sym_2_2283
+sym_2_2283: la $2, sym_2_2283
+.globl sym_2_2284
+sym_2_2284: la $2, sym_2_2284
+.globl sym_2_2285
+sym_2_2285: la $2, sym_2_2285
+.globl sym_2_2286
+sym_2_2286: la $2, sym_2_2286
+.globl sym_2_2287
+sym_2_2287: la $2, sym_2_2287
+.globl sym_2_2288
+sym_2_2288: la $2, sym_2_2288
+.globl sym_2_2289
+sym_2_2289: la $2, sym_2_2289
+.globl sym_2_2290
+sym_2_2290: la $2, sym_2_2290
+.globl sym_2_2291
+sym_2_2291: la $2, sym_2_2291
+.globl sym_2_2292
+sym_2_2292: la $2, sym_2_2292
+.globl sym_2_2293
+sym_2_2293: la $2, sym_2_2293
+.globl sym_2_2294
+sym_2_2294: la $2, sym_2_2294
+.globl sym_2_2295
+sym_2_2295: la $2, sym_2_2295
+.globl sym_2_2296
+sym_2_2296: la $2, sym_2_2296
+.globl sym_2_2297
+sym_2_2297: la $2, sym_2_2297
+.globl sym_2_2298
+sym_2_2298: la $2, sym_2_2298
+.globl sym_2_2299
+sym_2_2299: la $2, sym_2_2299
+.globl sym_2_2300
+sym_2_2300: la $2, sym_2_2300
+.globl sym_2_2301
+sym_2_2301: la $2, sym_2_2301
+.globl sym_2_2302
+sym_2_2302: la $2, sym_2_2302
+.globl sym_2_2303
+sym_2_2303: la $2, sym_2_2303
+.globl sym_2_2304
+sym_2_2304: la $2, sym_2_2304
+.globl sym_2_2305
+sym_2_2305: la $2, sym_2_2305
+.globl sym_2_2306
+sym_2_2306: la $2, sym_2_2306
+.globl sym_2_2307
+sym_2_2307: la $2, sym_2_2307
+.globl sym_2_2308
+sym_2_2308: la $2, sym_2_2308
+.globl sym_2_2309
+sym_2_2309: la $2, sym_2_2309
+.globl sym_2_2310
+sym_2_2310: la $2, sym_2_2310
+.globl sym_2_2311
+sym_2_2311: la $2, sym_2_2311
+.globl sym_2_2312
+sym_2_2312: la $2, sym_2_2312
+.globl sym_2_2313
+sym_2_2313: la $2, sym_2_2313
+.globl sym_2_2314
+sym_2_2314: la $2, sym_2_2314
+.globl sym_2_2315
+sym_2_2315: la $2, sym_2_2315
+.globl sym_2_2316
+sym_2_2316: la $2, sym_2_2316
+.globl sym_2_2317
+sym_2_2317: la $2, sym_2_2317
+.globl sym_2_2318
+sym_2_2318: la $2, sym_2_2318
+.globl sym_2_2319
+sym_2_2319: la $2, sym_2_2319
+.globl sym_2_2320
+sym_2_2320: la $2, sym_2_2320
+.globl sym_2_2321
+sym_2_2321: la $2, sym_2_2321
+.globl sym_2_2322
+sym_2_2322: la $2, sym_2_2322
+.globl sym_2_2323
+sym_2_2323: la $2, sym_2_2323
+.globl sym_2_2324
+sym_2_2324: la $2, sym_2_2324
+.globl sym_2_2325
+sym_2_2325: la $2, sym_2_2325
+.globl sym_2_2326
+sym_2_2326: la $2, sym_2_2326
+.globl sym_2_2327
+sym_2_2327: la $2, sym_2_2327
+.globl sym_2_2328
+sym_2_2328: la $2, sym_2_2328
+.globl sym_2_2329
+sym_2_2329: la $2, sym_2_2329
+.globl sym_2_2330
+sym_2_2330: la $2, sym_2_2330
+.globl sym_2_2331
+sym_2_2331: la $2, sym_2_2331
+.globl sym_2_2332
+sym_2_2332: la $2, sym_2_2332
+.globl sym_2_2333
+sym_2_2333: la $2, sym_2_2333
+.globl sym_2_2334
+sym_2_2334: la $2, sym_2_2334
+.globl sym_2_2335
+sym_2_2335: la $2, sym_2_2335
+.globl sym_2_2336
+sym_2_2336: la $2, sym_2_2336
+.globl sym_2_2337
+sym_2_2337: la $2, sym_2_2337
+.globl sym_2_2338
+sym_2_2338: la $2, sym_2_2338
+.globl sym_2_2339
+sym_2_2339: la $2, sym_2_2339
+.globl sym_2_2340
+sym_2_2340: la $2, sym_2_2340
+.globl sym_2_2341
+sym_2_2341: la $2, sym_2_2341
+.globl sym_2_2342
+sym_2_2342: la $2, sym_2_2342
+.globl sym_2_2343
+sym_2_2343: la $2, sym_2_2343
+.globl sym_2_2344
+sym_2_2344: la $2, sym_2_2344
+.globl sym_2_2345
+sym_2_2345: la $2, sym_2_2345
+.globl sym_2_2346
+sym_2_2346: la $2, sym_2_2346
+.globl sym_2_2347
+sym_2_2347: la $2, sym_2_2347
+.globl sym_2_2348
+sym_2_2348: la $2, sym_2_2348
+.globl sym_2_2349
+sym_2_2349: la $2, sym_2_2349
+.globl sym_2_2350
+sym_2_2350: la $2, sym_2_2350
+.globl sym_2_2351
+sym_2_2351: la $2, sym_2_2351
+.globl sym_2_2352
+sym_2_2352: la $2, sym_2_2352
+.globl sym_2_2353
+sym_2_2353: la $2, sym_2_2353
+.globl sym_2_2354
+sym_2_2354: la $2, sym_2_2354
+.globl sym_2_2355
+sym_2_2355: la $2, sym_2_2355
+.globl sym_2_2356
+sym_2_2356: la $2, sym_2_2356
+.globl sym_2_2357
+sym_2_2357: la $2, sym_2_2357
+.globl sym_2_2358
+sym_2_2358: la $2, sym_2_2358
+.globl sym_2_2359
+sym_2_2359: la $2, sym_2_2359
+.globl sym_2_2360
+sym_2_2360: la $2, sym_2_2360
+.globl sym_2_2361
+sym_2_2361: la $2, sym_2_2361
+.globl sym_2_2362
+sym_2_2362: la $2, sym_2_2362
+.globl sym_2_2363
+sym_2_2363: la $2, sym_2_2363
+.globl sym_2_2364
+sym_2_2364: la $2, sym_2_2364
+.globl sym_2_2365
+sym_2_2365: la $2, sym_2_2365
+.globl sym_2_2366
+sym_2_2366: la $2, sym_2_2366
+.globl sym_2_2367
+sym_2_2367: la $2, sym_2_2367
+.globl sym_2_2368
+sym_2_2368: la $2, sym_2_2368
+.globl sym_2_2369
+sym_2_2369: la $2, sym_2_2369
+.globl sym_2_2370
+sym_2_2370: la $2, sym_2_2370
+.globl sym_2_2371
+sym_2_2371: la $2, sym_2_2371
+.globl sym_2_2372
+sym_2_2372: la $2, sym_2_2372
+.globl sym_2_2373
+sym_2_2373: la $2, sym_2_2373
+.globl sym_2_2374
+sym_2_2374: la $2, sym_2_2374
+.globl sym_2_2375
+sym_2_2375: la $2, sym_2_2375
+.globl sym_2_2376
+sym_2_2376: la $2, sym_2_2376
+.globl sym_2_2377
+sym_2_2377: la $2, sym_2_2377
+.globl sym_2_2378
+sym_2_2378: la $2, sym_2_2378
+.globl sym_2_2379
+sym_2_2379: la $2, sym_2_2379
+.globl sym_2_2380
+sym_2_2380: la $2, sym_2_2380
+.globl sym_2_2381
+sym_2_2381: la $2, sym_2_2381
+.globl sym_2_2382
+sym_2_2382: la $2, sym_2_2382
+.globl sym_2_2383
+sym_2_2383: la $2, sym_2_2383
+.globl sym_2_2384
+sym_2_2384: la $2, sym_2_2384
+.globl sym_2_2385
+sym_2_2385: la $2, sym_2_2385
+.globl sym_2_2386
+sym_2_2386: la $2, sym_2_2386
+.globl sym_2_2387
+sym_2_2387: la $2, sym_2_2387
+.globl sym_2_2388
+sym_2_2388: la $2, sym_2_2388
+.globl sym_2_2389
+sym_2_2389: la $2, sym_2_2389
+.globl sym_2_2390
+sym_2_2390: la $2, sym_2_2390
+.globl sym_2_2391
+sym_2_2391: la $2, sym_2_2391
+.globl sym_2_2392
+sym_2_2392: la $2, sym_2_2392
+.globl sym_2_2393
+sym_2_2393: la $2, sym_2_2393
+.globl sym_2_2394
+sym_2_2394: la $2, sym_2_2394
+.globl sym_2_2395
+sym_2_2395: la $2, sym_2_2395
+.globl sym_2_2396
+sym_2_2396: la $2, sym_2_2396
+.globl sym_2_2397
+sym_2_2397: la $2, sym_2_2397
+.globl sym_2_2398
+sym_2_2398: la $2, sym_2_2398
+.globl sym_2_2399
+sym_2_2399: la $2, sym_2_2399
+.globl sym_2_2400
+sym_2_2400: la $2, sym_2_2400
+.globl sym_2_2401
+sym_2_2401: la $2, sym_2_2401
+.globl sym_2_2402
+sym_2_2402: la $2, sym_2_2402
+.globl sym_2_2403
+sym_2_2403: la $2, sym_2_2403
+.globl sym_2_2404
+sym_2_2404: la $2, sym_2_2404
+.globl sym_2_2405
+sym_2_2405: la $2, sym_2_2405
+.globl sym_2_2406
+sym_2_2406: la $2, sym_2_2406
+.globl sym_2_2407
+sym_2_2407: la $2, sym_2_2407
+.globl sym_2_2408
+sym_2_2408: la $2, sym_2_2408
+.globl sym_2_2409
+sym_2_2409: la $2, sym_2_2409
+.globl sym_2_2410
+sym_2_2410: la $2, sym_2_2410
+.globl sym_2_2411
+sym_2_2411: la $2, sym_2_2411
+.globl sym_2_2412
+sym_2_2412: la $2, sym_2_2412
+.globl sym_2_2413
+sym_2_2413: la $2, sym_2_2413
+.globl sym_2_2414
+sym_2_2414: la $2, sym_2_2414
+.globl sym_2_2415
+sym_2_2415: la $2, sym_2_2415
+.globl sym_2_2416
+sym_2_2416: la $2, sym_2_2416
+.globl sym_2_2417
+sym_2_2417: la $2, sym_2_2417
+.globl sym_2_2418
+sym_2_2418: la $2, sym_2_2418
+.globl sym_2_2419
+sym_2_2419: la $2, sym_2_2419
+.globl sym_2_2420
+sym_2_2420: la $2, sym_2_2420
+.globl sym_2_2421
+sym_2_2421: la $2, sym_2_2421
+.globl sym_2_2422
+sym_2_2422: la $2, sym_2_2422
+.globl sym_2_2423
+sym_2_2423: la $2, sym_2_2423
+.globl sym_2_2424
+sym_2_2424: la $2, sym_2_2424
+.globl sym_2_2425
+sym_2_2425: la $2, sym_2_2425
+.globl sym_2_2426
+sym_2_2426: la $2, sym_2_2426
+.globl sym_2_2427
+sym_2_2427: la $2, sym_2_2427
+.globl sym_2_2428
+sym_2_2428: la $2, sym_2_2428
+.globl sym_2_2429
+sym_2_2429: la $2, sym_2_2429
+.globl sym_2_2430
+sym_2_2430: la $2, sym_2_2430
+.globl sym_2_2431
+sym_2_2431: la $2, sym_2_2431
+.globl sym_2_2432
+sym_2_2432: la $2, sym_2_2432
+.globl sym_2_2433
+sym_2_2433: la $2, sym_2_2433
+.globl sym_2_2434
+sym_2_2434: la $2, sym_2_2434
+.globl sym_2_2435
+sym_2_2435: la $2, sym_2_2435
+.globl sym_2_2436
+sym_2_2436: la $2, sym_2_2436
+.globl sym_2_2437
+sym_2_2437: la $2, sym_2_2437
+.globl sym_2_2438
+sym_2_2438: la $2, sym_2_2438
+.globl sym_2_2439
+sym_2_2439: la $2, sym_2_2439
+.globl sym_2_2440
+sym_2_2440: la $2, sym_2_2440
+.globl sym_2_2441
+sym_2_2441: la $2, sym_2_2441
+.globl sym_2_2442
+sym_2_2442: la $2, sym_2_2442
+.globl sym_2_2443
+sym_2_2443: la $2, sym_2_2443
+.globl sym_2_2444
+sym_2_2444: la $2, sym_2_2444
+.globl sym_2_2445
+sym_2_2445: la $2, sym_2_2445
+.globl sym_2_2446
+sym_2_2446: la $2, sym_2_2446
+.globl sym_2_2447
+sym_2_2447: la $2, sym_2_2447
+.globl sym_2_2448
+sym_2_2448: la $2, sym_2_2448
+.globl sym_2_2449
+sym_2_2449: la $2, sym_2_2449
+.globl sym_2_2450
+sym_2_2450: la $2, sym_2_2450
+.globl sym_2_2451
+sym_2_2451: la $2, sym_2_2451
+.globl sym_2_2452
+sym_2_2452: la $2, sym_2_2452
+.globl sym_2_2453
+sym_2_2453: la $2, sym_2_2453
+.globl sym_2_2454
+sym_2_2454: la $2, sym_2_2454
+.globl sym_2_2455
+sym_2_2455: la $2, sym_2_2455
+.globl sym_2_2456
+sym_2_2456: la $2, sym_2_2456
+.globl sym_2_2457
+sym_2_2457: la $2, sym_2_2457
+.globl sym_2_2458
+sym_2_2458: la $2, sym_2_2458
+.globl sym_2_2459
+sym_2_2459: la $2, sym_2_2459
+.globl sym_2_2460
+sym_2_2460: la $2, sym_2_2460
+.globl sym_2_2461
+sym_2_2461: la $2, sym_2_2461
+.globl sym_2_2462
+sym_2_2462: la $2, sym_2_2462
+.globl sym_2_2463
+sym_2_2463: la $2, sym_2_2463
+.globl sym_2_2464
+sym_2_2464: la $2, sym_2_2464
+.globl sym_2_2465
+sym_2_2465: la $2, sym_2_2465
+.globl sym_2_2466
+sym_2_2466: la $2, sym_2_2466
+.globl sym_2_2467
+sym_2_2467: la $2, sym_2_2467
+.globl sym_2_2468
+sym_2_2468: la $2, sym_2_2468
+.globl sym_2_2469
+sym_2_2469: la $2, sym_2_2469
+.globl sym_2_2470
+sym_2_2470: la $2, sym_2_2470
+.globl sym_2_2471
+sym_2_2471: la $2, sym_2_2471
+.globl sym_2_2472
+sym_2_2472: la $2, sym_2_2472
+.globl sym_2_2473
+sym_2_2473: la $2, sym_2_2473
+.globl sym_2_2474
+sym_2_2474: la $2, sym_2_2474
+.globl sym_2_2475
+sym_2_2475: la $2, sym_2_2475
+.globl sym_2_2476
+sym_2_2476: la $2, sym_2_2476
+.globl sym_2_2477
+sym_2_2477: la $2, sym_2_2477
+.globl sym_2_2478
+sym_2_2478: la $2, sym_2_2478
+.globl sym_2_2479
+sym_2_2479: la $2, sym_2_2479
+.globl sym_2_2480
+sym_2_2480: la $2, sym_2_2480
+.globl sym_2_2481
+sym_2_2481: la $2, sym_2_2481
+.globl sym_2_2482
+sym_2_2482: la $2, sym_2_2482
+.globl sym_2_2483
+sym_2_2483: la $2, sym_2_2483
+.globl sym_2_2484
+sym_2_2484: la $2, sym_2_2484
+.globl sym_2_2485
+sym_2_2485: la $2, sym_2_2485
+.globl sym_2_2486
+sym_2_2486: la $2, sym_2_2486
+.globl sym_2_2487
+sym_2_2487: la $2, sym_2_2487
+.globl sym_2_2488
+sym_2_2488: la $2, sym_2_2488
+.globl sym_2_2489
+sym_2_2489: la $2, sym_2_2489
+.globl sym_2_2490
+sym_2_2490: la $2, sym_2_2490
+.globl sym_2_2491
+sym_2_2491: la $2, sym_2_2491
+.globl sym_2_2492
+sym_2_2492: la $2, sym_2_2492
+.globl sym_2_2493
+sym_2_2493: la $2, sym_2_2493
+.globl sym_2_2494
+sym_2_2494: la $2, sym_2_2494
+.globl sym_2_2495
+sym_2_2495: la $2, sym_2_2495
+.globl sym_2_2496
+sym_2_2496: la $2, sym_2_2496
+.globl sym_2_2497
+sym_2_2497: la $2, sym_2_2497
+.globl sym_2_2498
+sym_2_2498: la $2, sym_2_2498
+.globl sym_2_2499
+sym_2_2499: la $2, sym_2_2499
+.globl sym_2_2500
+sym_2_2500: la $2, sym_2_2500
+.globl sym_2_2501
+sym_2_2501: la $2, sym_2_2501
+.globl sym_2_2502
+sym_2_2502: la $2, sym_2_2502
+.globl sym_2_2503
+sym_2_2503: la $2, sym_2_2503
+.globl sym_2_2504
+sym_2_2504: la $2, sym_2_2504
+.globl sym_2_2505
+sym_2_2505: la $2, sym_2_2505
+.globl sym_2_2506
+sym_2_2506: la $2, sym_2_2506
+.globl sym_2_2507
+sym_2_2507: la $2, sym_2_2507
+.globl sym_2_2508
+sym_2_2508: la $2, sym_2_2508
+.globl sym_2_2509
+sym_2_2509: la $2, sym_2_2509
+.globl sym_2_2510
+sym_2_2510: la $2, sym_2_2510
+.globl sym_2_2511
+sym_2_2511: la $2, sym_2_2511
+.globl sym_2_2512
+sym_2_2512: la $2, sym_2_2512
+.globl sym_2_2513
+sym_2_2513: la $2, sym_2_2513
+.globl sym_2_2514
+sym_2_2514: la $2, sym_2_2514
+.globl sym_2_2515
+sym_2_2515: la $2, sym_2_2515
+.globl sym_2_2516
+sym_2_2516: la $2, sym_2_2516
+.globl sym_2_2517
+sym_2_2517: la $2, sym_2_2517
+.globl sym_2_2518
+sym_2_2518: la $2, sym_2_2518
+.globl sym_2_2519
+sym_2_2519: la $2, sym_2_2519
+.globl sym_2_2520
+sym_2_2520: la $2, sym_2_2520
+.globl sym_2_2521
+sym_2_2521: la $2, sym_2_2521
+.globl sym_2_2522
+sym_2_2522: la $2, sym_2_2522
+.globl sym_2_2523
+sym_2_2523: la $2, sym_2_2523
+.globl sym_2_2524
+sym_2_2524: la $2, sym_2_2524
+.globl sym_2_2525
+sym_2_2525: la $2, sym_2_2525
+.globl sym_2_2526
+sym_2_2526: la $2, sym_2_2526
+.globl sym_2_2527
+sym_2_2527: la $2, sym_2_2527
+.globl sym_2_2528
+sym_2_2528: la $2, sym_2_2528
+.globl sym_2_2529
+sym_2_2529: la $2, sym_2_2529
+.globl sym_2_2530
+sym_2_2530: la $2, sym_2_2530
+.globl sym_2_2531
+sym_2_2531: la $2, sym_2_2531
+.globl sym_2_2532
+sym_2_2532: la $2, sym_2_2532
+.globl sym_2_2533
+sym_2_2533: la $2, sym_2_2533
+.globl sym_2_2534
+sym_2_2534: la $2, sym_2_2534
+.globl sym_2_2535
+sym_2_2535: la $2, sym_2_2535
+.globl sym_2_2536
+sym_2_2536: la $2, sym_2_2536
+.globl sym_2_2537
+sym_2_2537: la $2, sym_2_2537
+.globl sym_2_2538
+sym_2_2538: la $2, sym_2_2538
+.globl sym_2_2539
+sym_2_2539: la $2, sym_2_2539
+.globl sym_2_2540
+sym_2_2540: la $2, sym_2_2540
+.globl sym_2_2541
+sym_2_2541: la $2, sym_2_2541
+.globl sym_2_2542
+sym_2_2542: la $2, sym_2_2542
+.globl sym_2_2543
+sym_2_2543: la $2, sym_2_2543
+.globl sym_2_2544
+sym_2_2544: la $2, sym_2_2544
+.globl sym_2_2545
+sym_2_2545: la $2, sym_2_2545
+.globl sym_2_2546
+sym_2_2546: la $2, sym_2_2546
+.globl sym_2_2547
+sym_2_2547: la $2, sym_2_2547
+.globl sym_2_2548
+sym_2_2548: la $2, sym_2_2548
+.globl sym_2_2549
+sym_2_2549: la $2, sym_2_2549
+.globl sym_2_2550
+sym_2_2550: la $2, sym_2_2550
+.globl sym_2_2551
+sym_2_2551: la $2, sym_2_2551
+.globl sym_2_2552
+sym_2_2552: la $2, sym_2_2552
+.globl sym_2_2553
+sym_2_2553: la $2, sym_2_2553
+.globl sym_2_2554
+sym_2_2554: la $2, sym_2_2554
+.globl sym_2_2555
+sym_2_2555: la $2, sym_2_2555
+.globl sym_2_2556
+sym_2_2556: la $2, sym_2_2556
+.globl sym_2_2557
+sym_2_2557: la $2, sym_2_2557
+.globl sym_2_2558
+sym_2_2558: la $2, sym_2_2558
+.globl sym_2_2559
+sym_2_2559: la $2, sym_2_2559
+.globl sym_2_2560
+sym_2_2560: la $2, sym_2_2560
+.globl sym_2_2561
+sym_2_2561: la $2, sym_2_2561
+.globl sym_2_2562
+sym_2_2562: la $2, sym_2_2562
+.globl sym_2_2563
+sym_2_2563: la $2, sym_2_2563
+.globl sym_2_2564
+sym_2_2564: la $2, sym_2_2564
+.globl sym_2_2565
+sym_2_2565: la $2, sym_2_2565
+.globl sym_2_2566
+sym_2_2566: la $2, sym_2_2566
+.globl sym_2_2567
+sym_2_2567: la $2, sym_2_2567
+.globl sym_2_2568
+sym_2_2568: la $2, sym_2_2568
+.globl sym_2_2569
+sym_2_2569: la $2, sym_2_2569
+.globl sym_2_2570
+sym_2_2570: la $2, sym_2_2570
+.globl sym_2_2571
+sym_2_2571: la $2, sym_2_2571
+.globl sym_2_2572
+sym_2_2572: la $2, sym_2_2572
+.globl sym_2_2573
+sym_2_2573: la $2, sym_2_2573
+.globl sym_2_2574
+sym_2_2574: la $2, sym_2_2574
+.globl sym_2_2575
+sym_2_2575: la $2, sym_2_2575
+.globl sym_2_2576
+sym_2_2576: la $2, sym_2_2576
+.globl sym_2_2577
+sym_2_2577: la $2, sym_2_2577
+.globl sym_2_2578
+sym_2_2578: la $2, sym_2_2578
+.globl sym_2_2579
+sym_2_2579: la $2, sym_2_2579
+.globl sym_2_2580
+sym_2_2580: la $2, sym_2_2580
+.globl sym_2_2581
+sym_2_2581: la $2, sym_2_2581
+.globl sym_2_2582
+sym_2_2582: la $2, sym_2_2582
+.globl sym_2_2583
+sym_2_2583: la $2, sym_2_2583
+.globl sym_2_2584
+sym_2_2584: la $2, sym_2_2584
+.globl sym_2_2585
+sym_2_2585: la $2, sym_2_2585
+.globl sym_2_2586
+sym_2_2586: la $2, sym_2_2586
+.globl sym_2_2587
+sym_2_2587: la $2, sym_2_2587
+.globl sym_2_2588
+sym_2_2588: la $2, sym_2_2588
+.globl sym_2_2589
+sym_2_2589: la $2, sym_2_2589
+.globl sym_2_2590
+sym_2_2590: la $2, sym_2_2590
+.globl sym_2_2591
+sym_2_2591: la $2, sym_2_2591
+.globl sym_2_2592
+sym_2_2592: la $2, sym_2_2592
+.globl sym_2_2593
+sym_2_2593: la $2, sym_2_2593
+.globl sym_2_2594
+sym_2_2594: la $2, sym_2_2594
+.globl sym_2_2595
+sym_2_2595: la $2, sym_2_2595
+.globl sym_2_2596
+sym_2_2596: la $2, sym_2_2596
+.globl sym_2_2597
+sym_2_2597: la $2, sym_2_2597
+.globl sym_2_2598
+sym_2_2598: la $2, sym_2_2598
+.globl sym_2_2599
+sym_2_2599: la $2, sym_2_2599
+.globl sym_2_2600
+sym_2_2600: la $2, sym_2_2600
+.globl sym_2_2601
+sym_2_2601: la $2, sym_2_2601
+.globl sym_2_2602
+sym_2_2602: la $2, sym_2_2602
+.globl sym_2_2603
+sym_2_2603: la $2, sym_2_2603
+.globl sym_2_2604
+sym_2_2604: la $2, sym_2_2604
+.globl sym_2_2605
+sym_2_2605: la $2, sym_2_2605
+.globl sym_2_2606
+sym_2_2606: la $2, sym_2_2606
+.globl sym_2_2607
+sym_2_2607: la $2, sym_2_2607
+.globl sym_2_2608
+sym_2_2608: la $2, sym_2_2608
+.globl sym_2_2609
+sym_2_2609: la $2, sym_2_2609
+.globl sym_2_2610
+sym_2_2610: la $2, sym_2_2610
+.globl sym_2_2611
+sym_2_2611: la $2, sym_2_2611
+.globl sym_2_2612
+sym_2_2612: la $2, sym_2_2612
+.globl sym_2_2613
+sym_2_2613: la $2, sym_2_2613
+.globl sym_2_2614
+sym_2_2614: la $2, sym_2_2614
+.globl sym_2_2615
+sym_2_2615: la $2, sym_2_2615
+.globl sym_2_2616
+sym_2_2616: la $2, sym_2_2616
+.globl sym_2_2617
+sym_2_2617: la $2, sym_2_2617
+.globl sym_2_2618
+sym_2_2618: la $2, sym_2_2618
+.globl sym_2_2619
+sym_2_2619: la $2, sym_2_2619
+.globl sym_2_2620
+sym_2_2620: la $2, sym_2_2620
+.globl sym_2_2621
+sym_2_2621: la $2, sym_2_2621
+.globl sym_2_2622
+sym_2_2622: la $2, sym_2_2622
+.globl sym_2_2623
+sym_2_2623: la $2, sym_2_2623
+.globl sym_2_2624
+sym_2_2624: la $2, sym_2_2624
+.globl sym_2_2625
+sym_2_2625: la $2, sym_2_2625
+.globl sym_2_2626
+sym_2_2626: la $2, sym_2_2626
+.globl sym_2_2627
+sym_2_2627: la $2, sym_2_2627
+.globl sym_2_2628
+sym_2_2628: la $2, sym_2_2628
+.globl sym_2_2629
+sym_2_2629: la $2, sym_2_2629
+.globl sym_2_2630
+sym_2_2630: la $2, sym_2_2630
+.globl sym_2_2631
+sym_2_2631: la $2, sym_2_2631
+.globl sym_2_2632
+sym_2_2632: la $2, sym_2_2632
+.globl sym_2_2633
+sym_2_2633: la $2, sym_2_2633
+.globl sym_2_2634
+sym_2_2634: la $2, sym_2_2634
+.globl sym_2_2635
+sym_2_2635: la $2, sym_2_2635
+.globl sym_2_2636
+sym_2_2636: la $2, sym_2_2636
+.globl sym_2_2637
+sym_2_2637: la $2, sym_2_2637
+.globl sym_2_2638
+sym_2_2638: la $2, sym_2_2638
+.globl sym_2_2639
+sym_2_2639: la $2, sym_2_2639
+.globl sym_2_2640
+sym_2_2640: la $2, sym_2_2640
+.globl sym_2_2641
+sym_2_2641: la $2, sym_2_2641
+.globl sym_2_2642
+sym_2_2642: la $2, sym_2_2642
+.globl sym_2_2643
+sym_2_2643: la $2, sym_2_2643
+.globl sym_2_2644
+sym_2_2644: la $2, sym_2_2644
+.globl sym_2_2645
+sym_2_2645: la $2, sym_2_2645
+.globl sym_2_2646
+sym_2_2646: la $2, sym_2_2646
+.globl sym_2_2647
+sym_2_2647: la $2, sym_2_2647
+.globl sym_2_2648
+sym_2_2648: la $2, sym_2_2648
+.globl sym_2_2649
+sym_2_2649: la $2, sym_2_2649
+.globl sym_2_2650
+sym_2_2650: la $2, sym_2_2650
+.globl sym_2_2651
+sym_2_2651: la $2, sym_2_2651
+.globl sym_2_2652
+sym_2_2652: la $2, sym_2_2652
+.globl sym_2_2653
+sym_2_2653: la $2, sym_2_2653
+.globl sym_2_2654
+sym_2_2654: la $2, sym_2_2654
+.globl sym_2_2655
+sym_2_2655: la $2, sym_2_2655
+.globl sym_2_2656
+sym_2_2656: la $2, sym_2_2656
+.globl sym_2_2657
+sym_2_2657: la $2, sym_2_2657
+.globl sym_2_2658
+sym_2_2658: la $2, sym_2_2658
+.globl sym_2_2659
+sym_2_2659: la $2, sym_2_2659
+.globl sym_2_2660
+sym_2_2660: la $2, sym_2_2660
+.globl sym_2_2661
+sym_2_2661: la $2, sym_2_2661
+.globl sym_2_2662
+sym_2_2662: la $2, sym_2_2662
+.globl sym_2_2663
+sym_2_2663: la $2, sym_2_2663
+.globl sym_2_2664
+sym_2_2664: la $2, sym_2_2664
+.globl sym_2_2665
+sym_2_2665: la $2, sym_2_2665
+.globl sym_2_2666
+sym_2_2666: la $2, sym_2_2666
+.globl sym_2_2667
+sym_2_2667: la $2, sym_2_2667
+.globl sym_2_2668
+sym_2_2668: la $2, sym_2_2668
+.globl sym_2_2669
+sym_2_2669: la $2, sym_2_2669
+.globl sym_2_2670
+sym_2_2670: la $2, sym_2_2670
+.globl sym_2_2671
+sym_2_2671: la $2, sym_2_2671
+.globl sym_2_2672
+sym_2_2672: la $2, sym_2_2672
+.globl sym_2_2673
+sym_2_2673: la $2, sym_2_2673
+.globl sym_2_2674
+sym_2_2674: la $2, sym_2_2674
+.globl sym_2_2675
+sym_2_2675: la $2, sym_2_2675
+.globl sym_2_2676
+sym_2_2676: la $2, sym_2_2676
+.globl sym_2_2677
+sym_2_2677: la $2, sym_2_2677
+.globl sym_2_2678
+sym_2_2678: la $2, sym_2_2678
+.globl sym_2_2679
+sym_2_2679: la $2, sym_2_2679
+.globl sym_2_2680
+sym_2_2680: la $2, sym_2_2680
+.globl sym_2_2681
+sym_2_2681: la $2, sym_2_2681
+.globl sym_2_2682
+sym_2_2682: la $2, sym_2_2682
+.globl sym_2_2683
+sym_2_2683: la $2, sym_2_2683
+.globl sym_2_2684
+sym_2_2684: la $2, sym_2_2684
+.globl sym_2_2685
+sym_2_2685: la $2, sym_2_2685
+.globl sym_2_2686
+sym_2_2686: la $2, sym_2_2686
+.globl sym_2_2687
+sym_2_2687: la $2, sym_2_2687
+.globl sym_2_2688
+sym_2_2688: la $2, sym_2_2688
+.globl sym_2_2689
+sym_2_2689: la $2, sym_2_2689
+.globl sym_2_2690
+sym_2_2690: la $2, sym_2_2690
+.globl sym_2_2691
+sym_2_2691: la $2, sym_2_2691
+.globl sym_2_2692
+sym_2_2692: la $2, sym_2_2692
+.globl sym_2_2693
+sym_2_2693: la $2, sym_2_2693
+.globl sym_2_2694
+sym_2_2694: la $2, sym_2_2694
+.globl sym_2_2695
+sym_2_2695: la $2, sym_2_2695
+.globl sym_2_2696
+sym_2_2696: la $2, sym_2_2696
+.globl sym_2_2697
+sym_2_2697: la $2, sym_2_2697
+.globl sym_2_2698
+sym_2_2698: la $2, sym_2_2698
+.globl sym_2_2699
+sym_2_2699: la $2, sym_2_2699
+.globl sym_2_2700
+sym_2_2700: la $2, sym_2_2700
+.globl sym_2_2701
+sym_2_2701: la $2, sym_2_2701
+.globl sym_2_2702
+sym_2_2702: la $2, sym_2_2702
+.globl sym_2_2703
+sym_2_2703: la $2, sym_2_2703
+.globl sym_2_2704
+sym_2_2704: la $2, sym_2_2704
+.globl sym_2_2705
+sym_2_2705: la $2, sym_2_2705
+.globl sym_2_2706
+sym_2_2706: la $2, sym_2_2706
+.globl sym_2_2707
+sym_2_2707: la $2, sym_2_2707
+.globl sym_2_2708
+sym_2_2708: la $2, sym_2_2708
+.globl sym_2_2709
+sym_2_2709: la $2, sym_2_2709
+.globl sym_2_2710
+sym_2_2710: la $2, sym_2_2710
+.globl sym_2_2711
+sym_2_2711: la $2, sym_2_2711
+.globl sym_2_2712
+sym_2_2712: la $2, sym_2_2712
+.globl sym_2_2713
+sym_2_2713: la $2, sym_2_2713
+.globl sym_2_2714
+sym_2_2714: la $2, sym_2_2714
+.globl sym_2_2715
+sym_2_2715: la $2, sym_2_2715
+.globl sym_2_2716
+sym_2_2716: la $2, sym_2_2716
+.globl sym_2_2717
+sym_2_2717: la $2, sym_2_2717
+.globl sym_2_2718
+sym_2_2718: la $2, sym_2_2718
+.globl sym_2_2719
+sym_2_2719: la $2, sym_2_2719
+.globl sym_2_2720
+sym_2_2720: la $2, sym_2_2720
+.globl sym_2_2721
+sym_2_2721: la $2, sym_2_2721
+.globl sym_2_2722
+sym_2_2722: la $2, sym_2_2722
+.globl sym_2_2723
+sym_2_2723: la $2, sym_2_2723
+.globl sym_2_2724
+sym_2_2724: la $2, sym_2_2724
+.globl sym_2_2725
+sym_2_2725: la $2, sym_2_2725
+.globl sym_2_2726
+sym_2_2726: la $2, sym_2_2726
+.globl sym_2_2727
+sym_2_2727: la $2, sym_2_2727
+.globl sym_2_2728
+sym_2_2728: la $2, sym_2_2728
+.globl sym_2_2729
+sym_2_2729: la $2, sym_2_2729
+.globl sym_2_2730
+sym_2_2730: la $2, sym_2_2730
+.globl sym_2_2731
+sym_2_2731: la $2, sym_2_2731
+.globl sym_2_2732
+sym_2_2732: la $2, sym_2_2732
+.globl sym_2_2733
+sym_2_2733: la $2, sym_2_2733
+.globl sym_2_2734
+sym_2_2734: la $2, sym_2_2734
+.globl sym_2_2735
+sym_2_2735: la $2, sym_2_2735
+.globl sym_2_2736
+sym_2_2736: la $2, sym_2_2736
+.globl sym_2_2737
+sym_2_2737: la $2, sym_2_2737
+.globl sym_2_2738
+sym_2_2738: la $2, sym_2_2738
+.globl sym_2_2739
+sym_2_2739: la $2, sym_2_2739
+.globl sym_2_2740
+sym_2_2740: la $2, sym_2_2740
+.globl sym_2_2741
+sym_2_2741: la $2, sym_2_2741
+.globl sym_2_2742
+sym_2_2742: la $2, sym_2_2742
+.globl sym_2_2743
+sym_2_2743: la $2, sym_2_2743
+.globl sym_2_2744
+sym_2_2744: la $2, sym_2_2744
+.globl sym_2_2745
+sym_2_2745: la $2, sym_2_2745
+.globl sym_2_2746
+sym_2_2746: la $2, sym_2_2746
+.globl sym_2_2747
+sym_2_2747: la $2, sym_2_2747
+.globl sym_2_2748
+sym_2_2748: la $2, sym_2_2748
+.globl sym_2_2749
+sym_2_2749: la $2, sym_2_2749
+.globl sym_2_2750
+sym_2_2750: la $2, sym_2_2750
+.globl sym_2_2751
+sym_2_2751: la $2, sym_2_2751
+.globl sym_2_2752
+sym_2_2752: la $2, sym_2_2752
+.globl sym_2_2753
+sym_2_2753: la $2, sym_2_2753
+.globl sym_2_2754
+sym_2_2754: la $2, sym_2_2754
+.globl sym_2_2755
+sym_2_2755: la $2, sym_2_2755
+.globl sym_2_2756
+sym_2_2756: la $2, sym_2_2756
+.globl sym_2_2757
+sym_2_2757: la $2, sym_2_2757
+.globl sym_2_2758
+sym_2_2758: la $2, sym_2_2758
+.globl sym_2_2759
+sym_2_2759: la $2, sym_2_2759
+.globl sym_2_2760
+sym_2_2760: la $2, sym_2_2760
+.globl sym_2_2761
+sym_2_2761: la $2, sym_2_2761
+.globl sym_2_2762
+sym_2_2762: la $2, sym_2_2762
+.globl sym_2_2763
+sym_2_2763: la $2, sym_2_2763
+.globl sym_2_2764
+sym_2_2764: la $2, sym_2_2764
+.globl sym_2_2765
+sym_2_2765: la $2, sym_2_2765
+.globl sym_2_2766
+sym_2_2766: la $2, sym_2_2766
+.globl sym_2_2767
+sym_2_2767: la $2, sym_2_2767
+.globl sym_2_2768
+sym_2_2768: la $2, sym_2_2768
+.globl sym_2_2769
+sym_2_2769: la $2, sym_2_2769
+.globl sym_2_2770
+sym_2_2770: la $2, sym_2_2770
+.globl sym_2_2771
+sym_2_2771: la $2, sym_2_2771
+.globl sym_2_2772
+sym_2_2772: la $2, sym_2_2772
+.globl sym_2_2773
+sym_2_2773: la $2, sym_2_2773
+.globl sym_2_2774
+sym_2_2774: la $2, sym_2_2774
+.globl sym_2_2775
+sym_2_2775: la $2, sym_2_2775
+.globl sym_2_2776
+sym_2_2776: la $2, sym_2_2776
+.globl sym_2_2777
+sym_2_2777: la $2, sym_2_2777
+.globl sym_2_2778
+sym_2_2778: la $2, sym_2_2778
+.globl sym_2_2779
+sym_2_2779: la $2, sym_2_2779
+.globl sym_2_2780
+sym_2_2780: la $2, sym_2_2780
+.globl sym_2_2781
+sym_2_2781: la $2, sym_2_2781
+.globl sym_2_2782
+sym_2_2782: la $2, sym_2_2782
+.globl sym_2_2783
+sym_2_2783: la $2, sym_2_2783
+.globl sym_2_2784
+sym_2_2784: la $2, sym_2_2784
+.globl sym_2_2785
+sym_2_2785: la $2, sym_2_2785
+.globl sym_2_2786
+sym_2_2786: la $2, sym_2_2786
+.globl sym_2_2787
+sym_2_2787: la $2, sym_2_2787
+.globl sym_2_2788
+sym_2_2788: la $2, sym_2_2788
+.globl sym_2_2789
+sym_2_2789: la $2, sym_2_2789
+.globl sym_2_2790
+sym_2_2790: la $2, sym_2_2790
+.globl sym_2_2791
+sym_2_2791: la $2, sym_2_2791
+.globl sym_2_2792
+sym_2_2792: la $2, sym_2_2792
+.globl sym_2_2793
+sym_2_2793: la $2, sym_2_2793
+.globl sym_2_2794
+sym_2_2794: la $2, sym_2_2794
+.globl sym_2_2795
+sym_2_2795: la $2, sym_2_2795
+.globl sym_2_2796
+sym_2_2796: la $2, sym_2_2796
+.globl sym_2_2797
+sym_2_2797: la $2, sym_2_2797
+.globl sym_2_2798
+sym_2_2798: la $2, sym_2_2798
+.globl sym_2_2799
+sym_2_2799: la $2, sym_2_2799
+.globl sym_2_2800
+sym_2_2800: la $2, sym_2_2800
+.globl sym_2_2801
+sym_2_2801: la $2, sym_2_2801
+.globl sym_2_2802
+sym_2_2802: la $2, sym_2_2802
+.globl sym_2_2803
+sym_2_2803: la $2, sym_2_2803
+.globl sym_2_2804
+sym_2_2804: la $2, sym_2_2804
+.globl sym_2_2805
+sym_2_2805: la $2, sym_2_2805
+.globl sym_2_2806
+sym_2_2806: la $2, sym_2_2806
+.globl sym_2_2807
+sym_2_2807: la $2, sym_2_2807
+.globl sym_2_2808
+sym_2_2808: la $2, sym_2_2808
+.globl sym_2_2809
+sym_2_2809: la $2, sym_2_2809
+.globl sym_2_2810
+sym_2_2810: la $2, sym_2_2810
+.globl sym_2_2811
+sym_2_2811: la $2, sym_2_2811
+.globl sym_2_2812
+sym_2_2812: la $2, sym_2_2812
+.globl sym_2_2813
+sym_2_2813: la $2, sym_2_2813
+.globl sym_2_2814
+sym_2_2814: la $2, sym_2_2814
+.globl sym_2_2815
+sym_2_2815: la $2, sym_2_2815
+.globl sym_2_2816
+sym_2_2816: la $2, sym_2_2816
+.globl sym_2_2817
+sym_2_2817: la $2, sym_2_2817
+.globl sym_2_2818
+sym_2_2818: la $2, sym_2_2818
+.globl sym_2_2819
+sym_2_2819: la $2, sym_2_2819
+.globl sym_2_2820
+sym_2_2820: la $2, sym_2_2820
+.globl sym_2_2821
+sym_2_2821: la $2, sym_2_2821
+.globl sym_2_2822
+sym_2_2822: la $2, sym_2_2822
+.globl sym_2_2823
+sym_2_2823: la $2, sym_2_2823
+.globl sym_2_2824
+sym_2_2824: la $2, sym_2_2824
+.globl sym_2_2825
+sym_2_2825: la $2, sym_2_2825
+.globl sym_2_2826
+sym_2_2826: la $2, sym_2_2826
+.globl sym_2_2827
+sym_2_2827: la $2, sym_2_2827
+.globl sym_2_2828
+sym_2_2828: la $2, sym_2_2828
+.globl sym_2_2829
+sym_2_2829: la $2, sym_2_2829
+.globl sym_2_2830
+sym_2_2830: la $2, sym_2_2830
+.globl sym_2_2831
+sym_2_2831: la $2, sym_2_2831
+.globl sym_2_2832
+sym_2_2832: la $2, sym_2_2832
+.globl sym_2_2833
+sym_2_2833: la $2, sym_2_2833
+.globl sym_2_2834
+sym_2_2834: la $2, sym_2_2834
+.globl sym_2_2835
+sym_2_2835: la $2, sym_2_2835
+.globl sym_2_2836
+sym_2_2836: la $2, sym_2_2836
+.globl sym_2_2837
+sym_2_2837: la $2, sym_2_2837
+.globl sym_2_2838
+sym_2_2838: la $2, sym_2_2838
+.globl sym_2_2839
+sym_2_2839: la $2, sym_2_2839
+.globl sym_2_2840
+sym_2_2840: la $2, sym_2_2840
+.globl sym_2_2841
+sym_2_2841: la $2, sym_2_2841
+.globl sym_2_2842
+sym_2_2842: la $2, sym_2_2842
+.globl sym_2_2843
+sym_2_2843: la $2, sym_2_2843
+.globl sym_2_2844
+sym_2_2844: la $2, sym_2_2844
+.globl sym_2_2845
+sym_2_2845: la $2, sym_2_2845
+.globl sym_2_2846
+sym_2_2846: la $2, sym_2_2846
+.globl sym_2_2847
+sym_2_2847: la $2, sym_2_2847
+.globl sym_2_2848
+sym_2_2848: la $2, sym_2_2848
+.globl sym_2_2849
+sym_2_2849: la $2, sym_2_2849
+.globl sym_2_2850
+sym_2_2850: la $2, sym_2_2850
+.globl sym_2_2851
+sym_2_2851: la $2, sym_2_2851
+.globl sym_2_2852
+sym_2_2852: la $2, sym_2_2852
+.globl sym_2_2853
+sym_2_2853: la $2, sym_2_2853
+.globl sym_2_2854
+sym_2_2854: la $2, sym_2_2854
+.globl sym_2_2855
+sym_2_2855: la $2, sym_2_2855
+.globl sym_2_2856
+sym_2_2856: la $2, sym_2_2856
+.globl sym_2_2857
+sym_2_2857: la $2, sym_2_2857
+.globl sym_2_2858
+sym_2_2858: la $2, sym_2_2858
+.globl sym_2_2859
+sym_2_2859: la $2, sym_2_2859
+.globl sym_2_2860
+sym_2_2860: la $2, sym_2_2860
+.globl sym_2_2861
+sym_2_2861: la $2, sym_2_2861
+.globl sym_2_2862
+sym_2_2862: la $2, sym_2_2862
+.globl sym_2_2863
+sym_2_2863: la $2, sym_2_2863
+.globl sym_2_2864
+sym_2_2864: la $2, sym_2_2864
+.globl sym_2_2865
+sym_2_2865: la $2, sym_2_2865
+.globl sym_2_2866
+sym_2_2866: la $2, sym_2_2866
+.globl sym_2_2867
+sym_2_2867: la $2, sym_2_2867
+.globl sym_2_2868
+sym_2_2868: la $2, sym_2_2868
+.globl sym_2_2869
+sym_2_2869: la $2, sym_2_2869
+.globl sym_2_2870
+sym_2_2870: la $2, sym_2_2870
+.globl sym_2_2871
+sym_2_2871: la $2, sym_2_2871
+.globl sym_2_2872
+sym_2_2872: la $2, sym_2_2872
+.globl sym_2_2873
+sym_2_2873: la $2, sym_2_2873
+.globl sym_2_2874
+sym_2_2874: la $2, sym_2_2874
+.globl sym_2_2875
+sym_2_2875: la $2, sym_2_2875
+.globl sym_2_2876
+sym_2_2876: la $2, sym_2_2876
+.globl sym_2_2877
+sym_2_2877: la $2, sym_2_2877
+.globl sym_2_2878
+sym_2_2878: la $2, sym_2_2878
+.globl sym_2_2879
+sym_2_2879: la $2, sym_2_2879
+.globl sym_2_2880
+sym_2_2880: la $2, sym_2_2880
+.globl sym_2_2881
+sym_2_2881: la $2, sym_2_2881
+.globl sym_2_2882
+sym_2_2882: la $2, sym_2_2882
+.globl sym_2_2883
+sym_2_2883: la $2, sym_2_2883
+.globl sym_2_2884
+sym_2_2884: la $2, sym_2_2884
+.globl sym_2_2885
+sym_2_2885: la $2, sym_2_2885
+.globl sym_2_2886
+sym_2_2886: la $2, sym_2_2886
+.globl sym_2_2887
+sym_2_2887: la $2, sym_2_2887
+.globl sym_2_2888
+sym_2_2888: la $2, sym_2_2888
+.globl sym_2_2889
+sym_2_2889: la $2, sym_2_2889
+.globl sym_2_2890
+sym_2_2890: la $2, sym_2_2890
+.globl sym_2_2891
+sym_2_2891: la $2, sym_2_2891
+.globl sym_2_2892
+sym_2_2892: la $2, sym_2_2892
+.globl sym_2_2893
+sym_2_2893: la $2, sym_2_2893
+.globl sym_2_2894
+sym_2_2894: la $2, sym_2_2894
+.globl sym_2_2895
+sym_2_2895: la $2, sym_2_2895
+.globl sym_2_2896
+sym_2_2896: la $2, sym_2_2896
+.globl sym_2_2897
+sym_2_2897: la $2, sym_2_2897
+.globl sym_2_2898
+sym_2_2898: la $2, sym_2_2898
+.globl sym_2_2899
+sym_2_2899: la $2, sym_2_2899
+.globl sym_2_2900
+sym_2_2900: la $2, sym_2_2900
+.globl sym_2_2901
+sym_2_2901: la $2, sym_2_2901
+.globl sym_2_2902
+sym_2_2902: la $2, sym_2_2902
+.globl sym_2_2903
+sym_2_2903: la $2, sym_2_2903
+.globl sym_2_2904
+sym_2_2904: la $2, sym_2_2904
+.globl sym_2_2905
+sym_2_2905: la $2, sym_2_2905
+.globl sym_2_2906
+sym_2_2906: la $2, sym_2_2906
+.globl sym_2_2907
+sym_2_2907: la $2, sym_2_2907
+.globl sym_2_2908
+sym_2_2908: la $2, sym_2_2908
+.globl sym_2_2909
+sym_2_2909: la $2, sym_2_2909
+.globl sym_2_2910
+sym_2_2910: la $2, sym_2_2910
+.globl sym_2_2911
+sym_2_2911: la $2, sym_2_2911
+.globl sym_2_2912
+sym_2_2912: la $2, sym_2_2912
+.globl sym_2_2913
+sym_2_2913: la $2, sym_2_2913
+.globl sym_2_2914
+sym_2_2914: la $2, sym_2_2914
+.globl sym_2_2915
+sym_2_2915: la $2, sym_2_2915
+.globl sym_2_2916
+sym_2_2916: la $2, sym_2_2916
+.globl sym_2_2917
+sym_2_2917: la $2, sym_2_2917
+.globl sym_2_2918
+sym_2_2918: la $2, sym_2_2918
+.globl sym_2_2919
+sym_2_2919: la $2, sym_2_2919
+.globl sym_2_2920
+sym_2_2920: la $2, sym_2_2920
+.globl sym_2_2921
+sym_2_2921: la $2, sym_2_2921
+.globl sym_2_2922
+sym_2_2922: la $2, sym_2_2922
+.globl sym_2_2923
+sym_2_2923: la $2, sym_2_2923
+.globl sym_2_2924
+sym_2_2924: la $2, sym_2_2924
+.globl sym_2_2925
+sym_2_2925: la $2, sym_2_2925
+.globl sym_2_2926
+sym_2_2926: la $2, sym_2_2926
+.globl sym_2_2927
+sym_2_2927: la $2, sym_2_2927
+.globl sym_2_2928
+sym_2_2928: la $2, sym_2_2928
+.globl sym_2_2929
+sym_2_2929: la $2, sym_2_2929
+.globl sym_2_2930
+sym_2_2930: la $2, sym_2_2930
+.globl sym_2_2931
+sym_2_2931: la $2, sym_2_2931
+.globl sym_2_2932
+sym_2_2932: la $2, sym_2_2932
+.globl sym_2_2933
+sym_2_2933: la $2, sym_2_2933
+.globl sym_2_2934
+sym_2_2934: la $2, sym_2_2934
+.globl sym_2_2935
+sym_2_2935: la $2, sym_2_2935
+.globl sym_2_2936
+sym_2_2936: la $2, sym_2_2936
+.globl sym_2_2937
+sym_2_2937: la $2, sym_2_2937
+.globl sym_2_2938
+sym_2_2938: la $2, sym_2_2938
+.globl sym_2_2939
+sym_2_2939: la $2, sym_2_2939
+.globl sym_2_2940
+sym_2_2940: la $2, sym_2_2940
+.globl sym_2_2941
+sym_2_2941: la $2, sym_2_2941
+.globl sym_2_2942
+sym_2_2942: la $2, sym_2_2942
+.globl sym_2_2943
+sym_2_2943: la $2, sym_2_2943
+.globl sym_2_2944
+sym_2_2944: la $2, sym_2_2944
+.globl sym_2_2945
+sym_2_2945: la $2, sym_2_2945
+.globl sym_2_2946
+sym_2_2946: la $2, sym_2_2946
+.globl sym_2_2947
+sym_2_2947: la $2, sym_2_2947
+.globl sym_2_2948
+sym_2_2948: la $2, sym_2_2948
+.globl sym_2_2949
+sym_2_2949: la $2, sym_2_2949
+.globl sym_2_2950
+sym_2_2950: la $2, sym_2_2950
+.globl sym_2_2951
+sym_2_2951: la $2, sym_2_2951
+.globl sym_2_2952
+sym_2_2952: la $2, sym_2_2952
+.globl sym_2_2953
+sym_2_2953: la $2, sym_2_2953
+.globl sym_2_2954
+sym_2_2954: la $2, sym_2_2954
+.globl sym_2_2955
+sym_2_2955: la $2, sym_2_2955
+.globl sym_2_2956
+sym_2_2956: la $2, sym_2_2956
+.globl sym_2_2957
+sym_2_2957: la $2, sym_2_2957
+.globl sym_2_2958
+sym_2_2958: la $2, sym_2_2958
+.globl sym_2_2959
+sym_2_2959: la $2, sym_2_2959
+.globl sym_2_2960
+sym_2_2960: la $2, sym_2_2960
+.globl sym_2_2961
+sym_2_2961: la $2, sym_2_2961
+.globl sym_2_2962
+sym_2_2962: la $2, sym_2_2962
+.globl sym_2_2963
+sym_2_2963: la $2, sym_2_2963
+.globl sym_2_2964
+sym_2_2964: la $2, sym_2_2964
+.globl sym_2_2965
+sym_2_2965: la $2, sym_2_2965
+.globl sym_2_2966
+sym_2_2966: la $2, sym_2_2966
+.globl sym_2_2967
+sym_2_2967: la $2, sym_2_2967
+.globl sym_2_2968
+sym_2_2968: la $2, sym_2_2968
+.globl sym_2_2969
+sym_2_2969: la $2, sym_2_2969
+.globl sym_2_2970
+sym_2_2970: la $2, sym_2_2970
+.globl sym_2_2971
+sym_2_2971: la $2, sym_2_2971
+.globl sym_2_2972
+sym_2_2972: la $2, sym_2_2972
+.globl sym_2_2973
+sym_2_2973: la $2, sym_2_2973
+.globl sym_2_2974
+sym_2_2974: la $2, sym_2_2974
+.globl sym_2_2975
+sym_2_2975: la $2, sym_2_2975
+.globl sym_2_2976
+sym_2_2976: la $2, sym_2_2976
+.globl sym_2_2977
+sym_2_2977: la $2, sym_2_2977
+.globl sym_2_2978
+sym_2_2978: la $2, sym_2_2978
+.globl sym_2_2979
+sym_2_2979: la $2, sym_2_2979
+.globl sym_2_2980
+sym_2_2980: la $2, sym_2_2980
+.globl sym_2_2981
+sym_2_2981: la $2, sym_2_2981
+.globl sym_2_2982
+sym_2_2982: la $2, sym_2_2982
+.globl sym_2_2983
+sym_2_2983: la $2, sym_2_2983
+.globl sym_2_2984
+sym_2_2984: la $2, sym_2_2984
+.globl sym_2_2985
+sym_2_2985: la $2, sym_2_2985
+.globl sym_2_2986
+sym_2_2986: la $2, sym_2_2986
+.globl sym_2_2987
+sym_2_2987: la $2, sym_2_2987
+.globl sym_2_2988
+sym_2_2988: la $2, sym_2_2988
+.globl sym_2_2989
+sym_2_2989: la $2, sym_2_2989
+.globl sym_2_2990
+sym_2_2990: la $2, sym_2_2990
+.globl sym_2_2991
+sym_2_2991: la $2, sym_2_2991
+.globl sym_2_2992
+sym_2_2992: la $2, sym_2_2992
+.globl sym_2_2993
+sym_2_2993: la $2, sym_2_2993
+.globl sym_2_2994
+sym_2_2994: la $2, sym_2_2994
+.globl sym_2_2995
+sym_2_2995: la $2, sym_2_2995
+.globl sym_2_2996
+sym_2_2996: la $2, sym_2_2996
+.globl sym_2_2997
+sym_2_2997: la $2, sym_2_2997
+.globl sym_2_2998
+sym_2_2998: la $2, sym_2_2998
+.globl sym_2_2999
+sym_2_2999: la $2, sym_2_2999
+.globl sym_2_3000
+sym_2_3000: la $2, sym_2_3000
+.globl sym_2_3001
+sym_2_3001: la $2, sym_2_3001
+.globl sym_2_3002
+sym_2_3002: la $2, sym_2_3002
+.globl sym_2_3003
+sym_2_3003: la $2, sym_2_3003
+.globl sym_2_3004
+sym_2_3004: la $2, sym_2_3004
+.globl sym_2_3005
+sym_2_3005: la $2, sym_2_3005
+.globl sym_2_3006
+sym_2_3006: la $2, sym_2_3006
+.globl sym_2_3007
+sym_2_3007: la $2, sym_2_3007
+.globl sym_2_3008
+sym_2_3008: la $2, sym_2_3008
+.globl sym_2_3009
+sym_2_3009: la $2, sym_2_3009
+.globl sym_2_3010
+sym_2_3010: la $2, sym_2_3010
+.globl sym_2_3011
+sym_2_3011: la $2, sym_2_3011
+.globl sym_2_3012
+sym_2_3012: la $2, sym_2_3012
+.globl sym_2_3013
+sym_2_3013: la $2, sym_2_3013
+.globl sym_2_3014
+sym_2_3014: la $2, sym_2_3014
+.globl sym_2_3015
+sym_2_3015: la $2, sym_2_3015
+.globl sym_2_3016
+sym_2_3016: la $2, sym_2_3016
+.globl sym_2_3017
+sym_2_3017: la $2, sym_2_3017
+.globl sym_2_3018
+sym_2_3018: la $2, sym_2_3018
+.globl sym_2_3019
+sym_2_3019: la $2, sym_2_3019
+.globl sym_2_3020
+sym_2_3020: la $2, sym_2_3020
+.globl sym_2_3021
+sym_2_3021: la $2, sym_2_3021
+.globl sym_2_3022
+sym_2_3022: la $2, sym_2_3022
+.globl sym_2_3023
+sym_2_3023: la $2, sym_2_3023
+.globl sym_2_3024
+sym_2_3024: la $2, sym_2_3024
+.globl sym_2_3025
+sym_2_3025: la $2, sym_2_3025
+.globl sym_2_3026
+sym_2_3026: la $2, sym_2_3026
+.globl sym_2_3027
+sym_2_3027: la $2, sym_2_3027
+.globl sym_2_3028
+sym_2_3028: la $2, sym_2_3028
+.globl sym_2_3029
+sym_2_3029: la $2, sym_2_3029
+.globl sym_2_3030
+sym_2_3030: la $2, sym_2_3030
+.globl sym_2_3031
+sym_2_3031: la $2, sym_2_3031
+.globl sym_2_3032
+sym_2_3032: la $2, sym_2_3032
+.globl sym_2_3033
+sym_2_3033: la $2, sym_2_3033
+.globl sym_2_3034
+sym_2_3034: la $2, sym_2_3034
+.globl sym_2_3035
+sym_2_3035: la $2, sym_2_3035
+.globl sym_2_3036
+sym_2_3036: la $2, sym_2_3036
+.globl sym_2_3037
+sym_2_3037: la $2, sym_2_3037
+.globl sym_2_3038
+sym_2_3038: la $2, sym_2_3038
+.globl sym_2_3039
+sym_2_3039: la $2, sym_2_3039
+.globl sym_2_3040
+sym_2_3040: la $2, sym_2_3040
+.globl sym_2_3041
+sym_2_3041: la $2, sym_2_3041
+.globl sym_2_3042
+sym_2_3042: la $2, sym_2_3042
+.globl sym_2_3043
+sym_2_3043: la $2, sym_2_3043
+.globl sym_2_3044
+sym_2_3044: la $2, sym_2_3044
+.globl sym_2_3045
+sym_2_3045: la $2, sym_2_3045
+.globl sym_2_3046
+sym_2_3046: la $2, sym_2_3046
+.globl sym_2_3047
+sym_2_3047: la $2, sym_2_3047
+.globl sym_2_3048
+sym_2_3048: la $2, sym_2_3048
+.globl sym_2_3049
+sym_2_3049: la $2, sym_2_3049
+.globl sym_2_3050
+sym_2_3050: la $2, sym_2_3050
+.globl sym_2_3051
+sym_2_3051: la $2, sym_2_3051
+.globl sym_2_3052
+sym_2_3052: la $2, sym_2_3052
+.globl sym_2_3053
+sym_2_3053: la $2, sym_2_3053
+.globl sym_2_3054
+sym_2_3054: la $2, sym_2_3054
+.globl sym_2_3055
+sym_2_3055: la $2, sym_2_3055
+.globl sym_2_3056
+sym_2_3056: la $2, sym_2_3056
+.globl sym_2_3057
+sym_2_3057: la $2, sym_2_3057
+.globl sym_2_3058
+sym_2_3058: la $2, sym_2_3058
+.globl sym_2_3059
+sym_2_3059: la $2, sym_2_3059
+.globl sym_2_3060
+sym_2_3060: la $2, sym_2_3060
+.globl sym_2_3061
+sym_2_3061: la $2, sym_2_3061
+.globl sym_2_3062
+sym_2_3062: la $2, sym_2_3062
+.globl sym_2_3063
+sym_2_3063: la $2, sym_2_3063
+.globl sym_2_3064
+sym_2_3064: la $2, sym_2_3064
+.globl sym_2_3065
+sym_2_3065: la $2, sym_2_3065
+.globl sym_2_3066
+sym_2_3066: la $2, sym_2_3066
+.globl sym_2_3067
+sym_2_3067: la $2, sym_2_3067
+.globl sym_2_3068
+sym_2_3068: la $2, sym_2_3068
+.globl sym_2_3069
+sym_2_3069: la $2, sym_2_3069
+.globl sym_2_3070
+sym_2_3070: la $2, sym_2_3070
+.globl sym_2_3071
+sym_2_3071: la $2, sym_2_3071
+.globl sym_2_3072
+sym_2_3072: la $2, sym_2_3072
+.globl sym_2_3073
+sym_2_3073: la $2, sym_2_3073
+.globl sym_2_3074
+sym_2_3074: la $2, sym_2_3074
+.globl sym_2_3075
+sym_2_3075: la $2, sym_2_3075
+.globl sym_2_3076
+sym_2_3076: la $2, sym_2_3076
+.globl sym_2_3077
+sym_2_3077: la $2, sym_2_3077
+.globl sym_2_3078
+sym_2_3078: la $2, sym_2_3078
+.globl sym_2_3079
+sym_2_3079: la $2, sym_2_3079
+.globl sym_2_3080
+sym_2_3080: la $2, sym_2_3080
+.globl sym_2_3081
+sym_2_3081: la $2, sym_2_3081
+.globl sym_2_3082
+sym_2_3082: la $2, sym_2_3082
+.globl sym_2_3083
+sym_2_3083: la $2, sym_2_3083
+.globl sym_2_3084
+sym_2_3084: la $2, sym_2_3084
+.globl sym_2_3085
+sym_2_3085: la $2, sym_2_3085
+.globl sym_2_3086
+sym_2_3086: la $2, sym_2_3086
+.globl sym_2_3087
+sym_2_3087: la $2, sym_2_3087
+.globl sym_2_3088
+sym_2_3088: la $2, sym_2_3088
+.globl sym_2_3089
+sym_2_3089: la $2, sym_2_3089
+.globl sym_2_3090
+sym_2_3090: la $2, sym_2_3090
+.globl sym_2_3091
+sym_2_3091: la $2, sym_2_3091
+.globl sym_2_3092
+sym_2_3092: la $2, sym_2_3092
+.globl sym_2_3093
+sym_2_3093: la $2, sym_2_3093
+.globl sym_2_3094
+sym_2_3094: la $2, sym_2_3094
+.globl sym_2_3095
+sym_2_3095: la $2, sym_2_3095
+.globl sym_2_3096
+sym_2_3096: la $2, sym_2_3096
+.globl sym_2_3097
+sym_2_3097: la $2, sym_2_3097
+.globl sym_2_3098
+sym_2_3098: la $2, sym_2_3098
+.globl sym_2_3099
+sym_2_3099: la $2, sym_2_3099
+.globl sym_2_3100
+sym_2_3100: la $2, sym_2_3100
+.globl sym_2_3101
+sym_2_3101: la $2, sym_2_3101
+.globl sym_2_3102
+sym_2_3102: la $2, sym_2_3102
+.globl sym_2_3103
+sym_2_3103: la $2, sym_2_3103
+.globl sym_2_3104
+sym_2_3104: la $2, sym_2_3104
+.globl sym_2_3105
+sym_2_3105: la $2, sym_2_3105
+.globl sym_2_3106
+sym_2_3106: la $2, sym_2_3106
+.globl sym_2_3107
+sym_2_3107: la $2, sym_2_3107
+.globl sym_2_3108
+sym_2_3108: la $2, sym_2_3108
+.globl sym_2_3109
+sym_2_3109: la $2, sym_2_3109
+.globl sym_2_3110
+sym_2_3110: la $2, sym_2_3110
+.globl sym_2_3111
+sym_2_3111: la $2, sym_2_3111
+.globl sym_2_3112
+sym_2_3112: la $2, sym_2_3112
+.globl sym_2_3113
+sym_2_3113: la $2, sym_2_3113
+.globl sym_2_3114
+sym_2_3114: la $2, sym_2_3114
+.globl sym_2_3115
+sym_2_3115: la $2, sym_2_3115
+.globl sym_2_3116
+sym_2_3116: la $2, sym_2_3116
+.globl sym_2_3117
+sym_2_3117: la $2, sym_2_3117
+.globl sym_2_3118
+sym_2_3118: la $2, sym_2_3118
+.globl sym_2_3119
+sym_2_3119: la $2, sym_2_3119
+.globl sym_2_3120
+sym_2_3120: la $2, sym_2_3120
+.globl sym_2_3121
+sym_2_3121: la $2, sym_2_3121
+.globl sym_2_3122
+sym_2_3122: la $2, sym_2_3122
+.globl sym_2_3123
+sym_2_3123: la $2, sym_2_3123
+.globl sym_2_3124
+sym_2_3124: la $2, sym_2_3124
+.globl sym_2_3125
+sym_2_3125: la $2, sym_2_3125
+.globl sym_2_3126
+sym_2_3126: la $2, sym_2_3126
+.globl sym_2_3127
+sym_2_3127: la $2, sym_2_3127
+.globl sym_2_3128
+sym_2_3128: la $2, sym_2_3128
+.globl sym_2_3129
+sym_2_3129: la $2, sym_2_3129
+.globl sym_2_3130
+sym_2_3130: la $2, sym_2_3130
+.globl sym_2_3131
+sym_2_3131: la $2, sym_2_3131
+.globl sym_2_3132
+sym_2_3132: la $2, sym_2_3132
+.globl sym_2_3133
+sym_2_3133: la $2, sym_2_3133
+.globl sym_2_3134
+sym_2_3134: la $2, sym_2_3134
+.globl sym_2_3135
+sym_2_3135: la $2, sym_2_3135
+.globl sym_2_3136
+sym_2_3136: la $2, sym_2_3136
+.globl sym_2_3137
+sym_2_3137: la $2, sym_2_3137
+.globl sym_2_3138
+sym_2_3138: la $2, sym_2_3138
+.globl sym_2_3139
+sym_2_3139: la $2, sym_2_3139
+.globl sym_2_3140
+sym_2_3140: la $2, sym_2_3140
+.globl sym_2_3141
+sym_2_3141: la $2, sym_2_3141
+.globl sym_2_3142
+sym_2_3142: la $2, sym_2_3142
+.globl sym_2_3143
+sym_2_3143: la $2, sym_2_3143
+.globl sym_2_3144
+sym_2_3144: la $2, sym_2_3144
+.globl sym_2_3145
+sym_2_3145: la $2, sym_2_3145
+.globl sym_2_3146
+sym_2_3146: la $2, sym_2_3146
+.globl sym_2_3147
+sym_2_3147: la $2, sym_2_3147
+.globl sym_2_3148
+sym_2_3148: la $2, sym_2_3148
+.globl sym_2_3149
+sym_2_3149: la $2, sym_2_3149
+.globl sym_2_3150
+sym_2_3150: la $2, sym_2_3150
+.globl sym_2_3151
+sym_2_3151: la $2, sym_2_3151
+.globl sym_2_3152
+sym_2_3152: la $2, sym_2_3152
+.globl sym_2_3153
+sym_2_3153: la $2, sym_2_3153
+.globl sym_2_3154
+sym_2_3154: la $2, sym_2_3154
+.globl sym_2_3155
+sym_2_3155: la $2, sym_2_3155
+.globl sym_2_3156
+sym_2_3156: la $2, sym_2_3156
+.globl sym_2_3157
+sym_2_3157: la $2, sym_2_3157
+.globl sym_2_3158
+sym_2_3158: la $2, sym_2_3158
+.globl sym_2_3159
+sym_2_3159: la $2, sym_2_3159
+.globl sym_2_3160
+sym_2_3160: la $2, sym_2_3160
+.globl sym_2_3161
+sym_2_3161: la $2, sym_2_3161
+.globl sym_2_3162
+sym_2_3162: la $2, sym_2_3162
+.globl sym_2_3163
+sym_2_3163: la $2, sym_2_3163
+.globl sym_2_3164
+sym_2_3164: la $2, sym_2_3164
+.globl sym_2_3165
+sym_2_3165: la $2, sym_2_3165
+.globl sym_2_3166
+sym_2_3166: la $2, sym_2_3166
+.globl sym_2_3167
+sym_2_3167: la $2, sym_2_3167
+.globl sym_2_3168
+sym_2_3168: la $2, sym_2_3168
+.globl sym_2_3169
+sym_2_3169: la $2, sym_2_3169
+.globl sym_2_3170
+sym_2_3170: la $2, sym_2_3170
+.globl sym_2_3171
+sym_2_3171: la $2, sym_2_3171
+.globl sym_2_3172
+sym_2_3172: la $2, sym_2_3172
+.globl sym_2_3173
+sym_2_3173: la $2, sym_2_3173
+.globl sym_2_3174
+sym_2_3174: la $2, sym_2_3174
+.globl sym_2_3175
+sym_2_3175: la $2, sym_2_3175
+.globl sym_2_3176
+sym_2_3176: la $2, sym_2_3176
+.globl sym_2_3177
+sym_2_3177: la $2, sym_2_3177
+.globl sym_2_3178
+sym_2_3178: la $2, sym_2_3178
+.globl sym_2_3179
+sym_2_3179: la $2, sym_2_3179
+.globl sym_2_3180
+sym_2_3180: la $2, sym_2_3180
+.globl sym_2_3181
+sym_2_3181: la $2, sym_2_3181
+.globl sym_2_3182
+sym_2_3182: la $2, sym_2_3182
+.globl sym_2_3183
+sym_2_3183: la $2, sym_2_3183
+.globl sym_2_3184
+sym_2_3184: la $2, sym_2_3184
+.globl sym_2_3185
+sym_2_3185: la $2, sym_2_3185
+.globl sym_2_3186
+sym_2_3186: la $2, sym_2_3186
+.globl sym_2_3187
+sym_2_3187: la $2, sym_2_3187
+.globl sym_2_3188
+sym_2_3188: la $2, sym_2_3188
+.globl sym_2_3189
+sym_2_3189: la $2, sym_2_3189
+.globl sym_2_3190
+sym_2_3190: la $2, sym_2_3190
+.globl sym_2_3191
+sym_2_3191: la $2, sym_2_3191
+.globl sym_2_3192
+sym_2_3192: la $2, sym_2_3192
+.globl sym_2_3193
+sym_2_3193: la $2, sym_2_3193
+.globl sym_2_3194
+sym_2_3194: la $2, sym_2_3194
+.globl sym_2_3195
+sym_2_3195: la $2, sym_2_3195
+.globl sym_2_3196
+sym_2_3196: la $2, sym_2_3196
+.globl sym_2_3197
+sym_2_3197: la $2, sym_2_3197
+.globl sym_2_3198
+sym_2_3198: la $2, sym_2_3198
+.globl sym_2_3199
+sym_2_3199: la $2, sym_2_3199
+.globl sym_2_3200
+sym_2_3200: la $2, sym_2_3200
+.globl sym_2_3201
+sym_2_3201: la $2, sym_2_3201
+.globl sym_2_3202
+sym_2_3202: la $2, sym_2_3202
+.globl sym_2_3203
+sym_2_3203: la $2, sym_2_3203
+.globl sym_2_3204
+sym_2_3204: la $2, sym_2_3204
+.globl sym_2_3205
+sym_2_3205: la $2, sym_2_3205
+.globl sym_2_3206
+sym_2_3206: la $2, sym_2_3206
+.globl sym_2_3207
+sym_2_3207: la $2, sym_2_3207
+.globl sym_2_3208
+sym_2_3208: la $2, sym_2_3208
+.globl sym_2_3209
+sym_2_3209: la $2, sym_2_3209
+.globl sym_2_3210
+sym_2_3210: la $2, sym_2_3210
+.globl sym_2_3211
+sym_2_3211: la $2, sym_2_3211
+.globl sym_2_3212
+sym_2_3212: la $2, sym_2_3212
+.globl sym_2_3213
+sym_2_3213: la $2, sym_2_3213
+.globl sym_2_3214
+sym_2_3214: la $2, sym_2_3214
+.globl sym_2_3215
+sym_2_3215: la $2, sym_2_3215
+.globl sym_2_3216
+sym_2_3216: la $2, sym_2_3216
+.globl sym_2_3217
+sym_2_3217: la $2, sym_2_3217
+.globl sym_2_3218
+sym_2_3218: la $2, sym_2_3218
+.globl sym_2_3219
+sym_2_3219: la $2, sym_2_3219
+.globl sym_2_3220
+sym_2_3220: la $2, sym_2_3220
+.globl sym_2_3221
+sym_2_3221: la $2, sym_2_3221
+.globl sym_2_3222
+sym_2_3222: la $2, sym_2_3222
+.globl sym_2_3223
+sym_2_3223: la $2, sym_2_3223
+.globl sym_2_3224
+sym_2_3224: la $2, sym_2_3224
+.globl sym_2_3225
+sym_2_3225: la $2, sym_2_3225
+.globl sym_2_3226
+sym_2_3226: la $2, sym_2_3226
+.globl sym_2_3227
+sym_2_3227: la $2, sym_2_3227
+.globl sym_2_3228
+sym_2_3228: la $2, sym_2_3228
+.globl sym_2_3229
+sym_2_3229: la $2, sym_2_3229
+.globl sym_2_3230
+sym_2_3230: la $2, sym_2_3230
+.globl sym_2_3231
+sym_2_3231: la $2, sym_2_3231
+.globl sym_2_3232
+sym_2_3232: la $2, sym_2_3232
+.globl sym_2_3233
+sym_2_3233: la $2, sym_2_3233
+.globl sym_2_3234
+sym_2_3234: la $2, sym_2_3234
+.globl sym_2_3235
+sym_2_3235: la $2, sym_2_3235
+.globl sym_2_3236
+sym_2_3236: la $2, sym_2_3236
+.globl sym_2_3237
+sym_2_3237: la $2, sym_2_3237
+.globl sym_2_3238
+sym_2_3238: la $2, sym_2_3238
+.globl sym_2_3239
+sym_2_3239: la $2, sym_2_3239
+.globl sym_2_3240
+sym_2_3240: la $2, sym_2_3240
+.globl sym_2_3241
+sym_2_3241: la $2, sym_2_3241
+.globl sym_2_3242
+sym_2_3242: la $2, sym_2_3242
+.globl sym_2_3243
+sym_2_3243: la $2, sym_2_3243
+.globl sym_2_3244
+sym_2_3244: la $2, sym_2_3244
+.globl sym_2_3245
+sym_2_3245: la $2, sym_2_3245
+.globl sym_2_3246
+sym_2_3246: la $2, sym_2_3246
+.globl sym_2_3247
+sym_2_3247: la $2, sym_2_3247
+.globl sym_2_3248
+sym_2_3248: la $2, sym_2_3248
+.globl sym_2_3249
+sym_2_3249: la $2, sym_2_3249
+.globl sym_2_3250
+sym_2_3250: la $2, sym_2_3250
+.globl sym_2_3251
+sym_2_3251: la $2, sym_2_3251
+.globl sym_2_3252
+sym_2_3252: la $2, sym_2_3252
+.globl sym_2_3253
+sym_2_3253: la $2, sym_2_3253
+.globl sym_2_3254
+sym_2_3254: la $2, sym_2_3254
+.globl sym_2_3255
+sym_2_3255: la $2, sym_2_3255
+.globl sym_2_3256
+sym_2_3256: la $2, sym_2_3256
+.globl sym_2_3257
+sym_2_3257: la $2, sym_2_3257
+.globl sym_2_3258
+sym_2_3258: la $2, sym_2_3258
+.globl sym_2_3259
+sym_2_3259: la $2, sym_2_3259
+.globl sym_2_3260
+sym_2_3260: la $2, sym_2_3260
+.globl sym_2_3261
+sym_2_3261: la $2, sym_2_3261
+.globl sym_2_3262
+sym_2_3262: la $2, sym_2_3262
+.globl sym_2_3263
+sym_2_3263: la $2, sym_2_3263
+.globl sym_2_3264
+sym_2_3264: la $2, sym_2_3264
+.globl sym_2_3265
+sym_2_3265: la $2, sym_2_3265
+.globl sym_2_3266
+sym_2_3266: la $2, sym_2_3266
+.globl sym_2_3267
+sym_2_3267: la $2, sym_2_3267
+.globl sym_2_3268
+sym_2_3268: la $2, sym_2_3268
+.globl sym_2_3269
+sym_2_3269: la $2, sym_2_3269
+.globl sym_2_3270
+sym_2_3270: la $2, sym_2_3270
+.globl sym_2_3271
+sym_2_3271: la $2, sym_2_3271
+.globl sym_2_3272
+sym_2_3272: la $2, sym_2_3272
+.globl sym_2_3273
+sym_2_3273: la $2, sym_2_3273
+.globl sym_2_3274
+sym_2_3274: la $2, sym_2_3274
+.globl sym_2_3275
+sym_2_3275: la $2, sym_2_3275
+.globl sym_2_3276
+sym_2_3276: la $2, sym_2_3276
+.globl sym_2_3277
+sym_2_3277: la $2, sym_2_3277
+.globl sym_2_3278
+sym_2_3278: la $2, sym_2_3278
+.globl sym_2_3279
+sym_2_3279: la $2, sym_2_3279
+.globl sym_2_3280
+sym_2_3280: la $2, sym_2_3280
+.globl sym_2_3281
+sym_2_3281: la $2, sym_2_3281
+.globl sym_2_3282
+sym_2_3282: la $2, sym_2_3282
+.globl sym_2_3283
+sym_2_3283: la $2, sym_2_3283
+.globl sym_2_3284
+sym_2_3284: la $2, sym_2_3284
+.globl sym_2_3285
+sym_2_3285: la $2, sym_2_3285
+.globl sym_2_3286
+sym_2_3286: la $2, sym_2_3286
+.globl sym_2_3287
+sym_2_3287: la $2, sym_2_3287
+.globl sym_2_3288
+sym_2_3288: la $2, sym_2_3288
+.globl sym_2_3289
+sym_2_3289: la $2, sym_2_3289
+.globl sym_2_3290
+sym_2_3290: la $2, sym_2_3290
+.globl sym_2_3291
+sym_2_3291: la $2, sym_2_3291
+.globl sym_2_3292
+sym_2_3292: la $2, sym_2_3292
+.globl sym_2_3293
+sym_2_3293: la $2, sym_2_3293
+.globl sym_2_3294
+sym_2_3294: la $2, sym_2_3294
+.globl sym_2_3295
+sym_2_3295: la $2, sym_2_3295
+.globl sym_2_3296
+sym_2_3296: la $2, sym_2_3296
+.globl sym_2_3297
+sym_2_3297: la $2, sym_2_3297
+.globl sym_2_3298
+sym_2_3298: la $2, sym_2_3298
+.globl sym_2_3299
+sym_2_3299: la $2, sym_2_3299
+.globl sym_2_3300
+sym_2_3300: la $2, sym_2_3300
+.globl sym_2_3301
+sym_2_3301: la $2, sym_2_3301
+.globl sym_2_3302
+sym_2_3302: la $2, sym_2_3302
+.globl sym_2_3303
+sym_2_3303: la $2, sym_2_3303
+.globl sym_2_3304
+sym_2_3304: la $2, sym_2_3304
+.globl sym_2_3305
+sym_2_3305: la $2, sym_2_3305
+.globl sym_2_3306
+sym_2_3306: la $2, sym_2_3306
+.globl sym_2_3307
+sym_2_3307: la $2, sym_2_3307
+.globl sym_2_3308
+sym_2_3308: la $2, sym_2_3308
+.globl sym_2_3309
+sym_2_3309: la $2, sym_2_3309
+.globl sym_2_3310
+sym_2_3310: la $2, sym_2_3310
+.globl sym_2_3311
+sym_2_3311: la $2, sym_2_3311
+.globl sym_2_3312
+sym_2_3312: la $2, sym_2_3312
+.globl sym_2_3313
+sym_2_3313: la $2, sym_2_3313
+.globl sym_2_3314
+sym_2_3314: la $2, sym_2_3314
+.globl sym_2_3315
+sym_2_3315: la $2, sym_2_3315
+.globl sym_2_3316
+sym_2_3316: la $2, sym_2_3316
+.globl sym_2_3317
+sym_2_3317: la $2, sym_2_3317
+.globl sym_2_3318
+sym_2_3318: la $2, sym_2_3318
+.globl sym_2_3319
+sym_2_3319: la $2, sym_2_3319
+.globl sym_2_3320
+sym_2_3320: la $2, sym_2_3320
+.globl sym_2_3321
+sym_2_3321: la $2, sym_2_3321
+.globl sym_2_3322
+sym_2_3322: la $2, sym_2_3322
+.globl sym_2_3323
+sym_2_3323: la $2, sym_2_3323
+.globl sym_2_3324
+sym_2_3324: la $2, sym_2_3324
+.globl sym_2_3325
+sym_2_3325: la $2, sym_2_3325
+.globl sym_2_3326
+sym_2_3326: la $2, sym_2_3326
+.globl sym_2_3327
+sym_2_3327: la $2, sym_2_3327
+.globl sym_2_3328
+sym_2_3328: la $2, sym_2_3328
+.globl sym_2_3329
+sym_2_3329: la $2, sym_2_3329
+.globl sym_2_3330
+sym_2_3330: la $2, sym_2_3330
+.globl sym_2_3331
+sym_2_3331: la $2, sym_2_3331
+.globl sym_2_3332
+sym_2_3332: la $2, sym_2_3332
+.globl sym_2_3333
+sym_2_3333: la $2, sym_2_3333
+.globl sym_2_3334
+sym_2_3334: la $2, sym_2_3334
+.globl sym_2_3335
+sym_2_3335: la $2, sym_2_3335
+.globl sym_2_3336
+sym_2_3336: la $2, sym_2_3336
+.globl sym_2_3337
+sym_2_3337: la $2, sym_2_3337
+.globl sym_2_3338
+sym_2_3338: la $2, sym_2_3338
+.globl sym_2_3339
+sym_2_3339: la $2, sym_2_3339
+.globl sym_2_3340
+sym_2_3340: la $2, sym_2_3340
+.globl sym_2_3341
+sym_2_3341: la $2, sym_2_3341
+.globl sym_2_3342
+sym_2_3342: la $2, sym_2_3342
+.globl sym_2_3343
+sym_2_3343: la $2, sym_2_3343
+.globl sym_2_3344
+sym_2_3344: la $2, sym_2_3344
+.globl sym_2_3345
+sym_2_3345: la $2, sym_2_3345
+.globl sym_2_3346
+sym_2_3346: la $2, sym_2_3346
+.globl sym_2_3347
+sym_2_3347: la $2, sym_2_3347
+.globl sym_2_3348
+sym_2_3348: la $2, sym_2_3348
+.globl sym_2_3349
+sym_2_3349: la $2, sym_2_3349
+.globl sym_2_3350
+sym_2_3350: la $2, sym_2_3350
+.globl sym_2_3351
+sym_2_3351: la $2, sym_2_3351
+.globl sym_2_3352
+sym_2_3352: la $2, sym_2_3352
+.globl sym_2_3353
+sym_2_3353: la $2, sym_2_3353
+.globl sym_2_3354
+sym_2_3354: la $2, sym_2_3354
+.globl sym_2_3355
+sym_2_3355: la $2, sym_2_3355
+.globl sym_2_3356
+sym_2_3356: la $2, sym_2_3356
+.globl sym_2_3357
+sym_2_3357: la $2, sym_2_3357
+.globl sym_2_3358
+sym_2_3358: la $2, sym_2_3358
+.globl sym_2_3359
+sym_2_3359: la $2, sym_2_3359
+.globl sym_2_3360
+sym_2_3360: la $2, sym_2_3360
+.globl sym_2_3361
+sym_2_3361: la $2, sym_2_3361
+.globl sym_2_3362
+sym_2_3362: la $2, sym_2_3362
+.globl sym_2_3363
+sym_2_3363: la $2, sym_2_3363
+.globl sym_2_3364
+sym_2_3364: la $2, sym_2_3364
+.globl sym_2_3365
+sym_2_3365: la $2, sym_2_3365
+.globl sym_2_3366
+sym_2_3366: la $2, sym_2_3366
+.globl sym_2_3367
+sym_2_3367: la $2, sym_2_3367
+.globl sym_2_3368
+sym_2_3368: la $2, sym_2_3368
+.globl sym_2_3369
+sym_2_3369: la $2, sym_2_3369
+.globl sym_2_3370
+sym_2_3370: la $2, sym_2_3370
+.globl sym_2_3371
+sym_2_3371: la $2, sym_2_3371
+.globl sym_2_3372
+sym_2_3372: la $2, sym_2_3372
+.globl sym_2_3373
+sym_2_3373: la $2, sym_2_3373
+.globl sym_2_3374
+sym_2_3374: la $2, sym_2_3374
+.globl sym_2_3375
+sym_2_3375: la $2, sym_2_3375
+.globl sym_2_3376
+sym_2_3376: la $2, sym_2_3376
+.globl sym_2_3377
+sym_2_3377: la $2, sym_2_3377
+.globl sym_2_3378
+sym_2_3378: la $2, sym_2_3378
+.globl sym_2_3379
+sym_2_3379: la $2, sym_2_3379
+.globl sym_2_3380
+sym_2_3380: la $2, sym_2_3380
+.globl sym_2_3381
+sym_2_3381: la $2, sym_2_3381
+.globl sym_2_3382
+sym_2_3382: la $2, sym_2_3382
+.globl sym_2_3383
+sym_2_3383: la $2, sym_2_3383
+.globl sym_2_3384
+sym_2_3384: la $2, sym_2_3384
+.globl sym_2_3385
+sym_2_3385: la $2, sym_2_3385
+.globl sym_2_3386
+sym_2_3386: la $2, sym_2_3386
+.globl sym_2_3387
+sym_2_3387: la $2, sym_2_3387
+.globl sym_2_3388
+sym_2_3388: la $2, sym_2_3388
+.globl sym_2_3389
+sym_2_3389: la $2, sym_2_3389
+.globl sym_2_3390
+sym_2_3390: la $2, sym_2_3390
+.globl sym_2_3391
+sym_2_3391: la $2, sym_2_3391
+.globl sym_2_3392
+sym_2_3392: la $2, sym_2_3392
+.globl sym_2_3393
+sym_2_3393: la $2, sym_2_3393
+.globl sym_2_3394
+sym_2_3394: la $2, sym_2_3394
+.globl sym_2_3395
+sym_2_3395: la $2, sym_2_3395
+.globl sym_2_3396
+sym_2_3396: la $2, sym_2_3396
+.globl sym_2_3397
+sym_2_3397: la $2, sym_2_3397
+.globl sym_2_3398
+sym_2_3398: la $2, sym_2_3398
+.globl sym_2_3399
+sym_2_3399: la $2, sym_2_3399
+.globl sym_2_3400
+sym_2_3400: la $2, sym_2_3400
+.globl sym_2_3401
+sym_2_3401: la $2, sym_2_3401
+.globl sym_2_3402
+sym_2_3402: la $2, sym_2_3402
+.globl sym_2_3403
+sym_2_3403: la $2, sym_2_3403
+.globl sym_2_3404
+sym_2_3404: la $2, sym_2_3404
+.globl sym_2_3405
+sym_2_3405: la $2, sym_2_3405
+.globl sym_2_3406
+sym_2_3406: la $2, sym_2_3406
+.globl sym_2_3407
+sym_2_3407: la $2, sym_2_3407
+.globl sym_2_3408
+sym_2_3408: la $2, sym_2_3408
+.globl sym_2_3409
+sym_2_3409: la $2, sym_2_3409
+.globl sym_2_3410
+sym_2_3410: la $2, sym_2_3410
+.globl sym_2_3411
+sym_2_3411: la $2, sym_2_3411
+.globl sym_2_3412
+sym_2_3412: la $2, sym_2_3412
+.globl sym_2_3413
+sym_2_3413: la $2, sym_2_3413
+.globl sym_2_3414
+sym_2_3414: la $2, sym_2_3414
+.globl sym_2_3415
+sym_2_3415: la $2, sym_2_3415
+.globl sym_2_3416
+sym_2_3416: la $2, sym_2_3416
+.globl sym_2_3417
+sym_2_3417: la $2, sym_2_3417
+.globl sym_2_3418
+sym_2_3418: la $2, sym_2_3418
+.globl sym_2_3419
+sym_2_3419: la $2, sym_2_3419
+.globl sym_2_3420
+sym_2_3420: la $2, sym_2_3420
+.globl sym_2_3421
+sym_2_3421: la $2, sym_2_3421
+.globl sym_2_3422
+sym_2_3422: la $2, sym_2_3422
+.globl sym_2_3423
+sym_2_3423: la $2, sym_2_3423
+.globl sym_2_3424
+sym_2_3424: la $2, sym_2_3424
+.globl sym_2_3425
+sym_2_3425: la $2, sym_2_3425
+.globl sym_2_3426
+sym_2_3426: la $2, sym_2_3426
+.globl sym_2_3427
+sym_2_3427: la $2, sym_2_3427
+.globl sym_2_3428
+sym_2_3428: la $2, sym_2_3428
+.globl sym_2_3429
+sym_2_3429: la $2, sym_2_3429
+.globl sym_2_3430
+sym_2_3430: la $2, sym_2_3430
+.globl sym_2_3431
+sym_2_3431: la $2, sym_2_3431
+.globl sym_2_3432
+sym_2_3432: la $2, sym_2_3432
+.globl sym_2_3433
+sym_2_3433: la $2, sym_2_3433
+.globl sym_2_3434
+sym_2_3434: la $2, sym_2_3434
+.globl sym_2_3435
+sym_2_3435: la $2, sym_2_3435
+.globl sym_2_3436
+sym_2_3436: la $2, sym_2_3436
+.globl sym_2_3437
+sym_2_3437: la $2, sym_2_3437
+.globl sym_2_3438
+sym_2_3438: la $2, sym_2_3438
+.globl sym_2_3439
+sym_2_3439: la $2, sym_2_3439
+.globl sym_2_3440
+sym_2_3440: la $2, sym_2_3440
+.globl sym_2_3441
+sym_2_3441: la $2, sym_2_3441
+.globl sym_2_3442
+sym_2_3442: la $2, sym_2_3442
+.globl sym_2_3443
+sym_2_3443: la $2, sym_2_3443
+.globl sym_2_3444
+sym_2_3444: la $2, sym_2_3444
+.globl sym_2_3445
+sym_2_3445: la $2, sym_2_3445
+.globl sym_2_3446
+sym_2_3446: la $2, sym_2_3446
+.globl sym_2_3447
+sym_2_3447: la $2, sym_2_3447
+.globl sym_2_3448
+sym_2_3448: la $2, sym_2_3448
+.globl sym_2_3449
+sym_2_3449: la $2, sym_2_3449
+.globl sym_2_3450
+sym_2_3450: la $2, sym_2_3450
+.globl sym_2_3451
+sym_2_3451: la $2, sym_2_3451
+.globl sym_2_3452
+sym_2_3452: la $2, sym_2_3452
+.globl sym_2_3453
+sym_2_3453: la $2, sym_2_3453
+.globl sym_2_3454
+sym_2_3454: la $2, sym_2_3454
+.globl sym_2_3455
+sym_2_3455: la $2, sym_2_3455
+.globl sym_2_3456
+sym_2_3456: la $2, sym_2_3456
+.globl sym_2_3457
+sym_2_3457: la $2, sym_2_3457
+.globl sym_2_3458
+sym_2_3458: la $2, sym_2_3458
+.globl sym_2_3459
+sym_2_3459: la $2, sym_2_3459
+.globl sym_2_3460
+sym_2_3460: la $2, sym_2_3460
+.globl sym_2_3461
+sym_2_3461: la $2, sym_2_3461
+.globl sym_2_3462
+sym_2_3462: la $2, sym_2_3462
+.globl sym_2_3463
+sym_2_3463: la $2, sym_2_3463
+.globl sym_2_3464
+sym_2_3464: la $2, sym_2_3464
+.globl sym_2_3465
+sym_2_3465: la $2, sym_2_3465
+.globl sym_2_3466
+sym_2_3466: la $2, sym_2_3466
+.globl sym_2_3467
+sym_2_3467: la $2, sym_2_3467
+.globl sym_2_3468
+sym_2_3468: la $2, sym_2_3468
+.globl sym_2_3469
+sym_2_3469: la $2, sym_2_3469
+.globl sym_2_3470
+sym_2_3470: la $2, sym_2_3470
+.globl sym_2_3471
+sym_2_3471: la $2, sym_2_3471
+.globl sym_2_3472
+sym_2_3472: la $2, sym_2_3472
+.globl sym_2_3473
+sym_2_3473: la $2, sym_2_3473
+.globl sym_2_3474
+sym_2_3474: la $2, sym_2_3474
+.globl sym_2_3475
+sym_2_3475: la $2, sym_2_3475
+.globl sym_2_3476
+sym_2_3476: la $2, sym_2_3476
+.globl sym_2_3477
+sym_2_3477: la $2, sym_2_3477
+.globl sym_2_3478
+sym_2_3478: la $2, sym_2_3478
+.globl sym_2_3479
+sym_2_3479: la $2, sym_2_3479
+.globl sym_2_3480
+sym_2_3480: la $2, sym_2_3480
+.globl sym_2_3481
+sym_2_3481: la $2, sym_2_3481
+.globl sym_2_3482
+sym_2_3482: la $2, sym_2_3482
+.globl sym_2_3483
+sym_2_3483: la $2, sym_2_3483
+.globl sym_2_3484
+sym_2_3484: la $2, sym_2_3484
+.globl sym_2_3485
+sym_2_3485: la $2, sym_2_3485
+.globl sym_2_3486
+sym_2_3486: la $2, sym_2_3486
+.globl sym_2_3487
+sym_2_3487: la $2, sym_2_3487
+.globl sym_2_3488
+sym_2_3488: la $2, sym_2_3488
+.globl sym_2_3489
+sym_2_3489: la $2, sym_2_3489
+.globl sym_2_3490
+sym_2_3490: la $2, sym_2_3490
+.globl sym_2_3491
+sym_2_3491: la $2, sym_2_3491
+.globl sym_2_3492
+sym_2_3492: la $2, sym_2_3492
+.globl sym_2_3493
+sym_2_3493: la $2, sym_2_3493
+.globl sym_2_3494
+sym_2_3494: la $2, sym_2_3494
+.globl sym_2_3495
+sym_2_3495: la $2, sym_2_3495
+.globl sym_2_3496
+sym_2_3496: la $2, sym_2_3496
+.globl sym_2_3497
+sym_2_3497: la $2, sym_2_3497
+.globl sym_2_3498
+sym_2_3498: la $2, sym_2_3498
+.globl sym_2_3499
+sym_2_3499: la $2, sym_2_3499
+.globl sym_2_3500
+sym_2_3500: la $2, sym_2_3500
+.globl sym_2_3501
+sym_2_3501: la $2, sym_2_3501
+.globl sym_2_3502
+sym_2_3502: la $2, sym_2_3502
+.globl sym_2_3503
+sym_2_3503: la $2, sym_2_3503
+.globl sym_2_3504
+sym_2_3504: la $2, sym_2_3504
+.globl sym_2_3505
+sym_2_3505: la $2, sym_2_3505
+.globl sym_2_3506
+sym_2_3506: la $2, sym_2_3506
+.globl sym_2_3507
+sym_2_3507: la $2, sym_2_3507
+.globl sym_2_3508
+sym_2_3508: la $2, sym_2_3508
+.globl sym_2_3509
+sym_2_3509: la $2, sym_2_3509
+.globl sym_2_3510
+sym_2_3510: la $2, sym_2_3510
+.globl sym_2_3511
+sym_2_3511: la $2, sym_2_3511
+.globl sym_2_3512
+sym_2_3512: la $2, sym_2_3512
+.globl sym_2_3513
+sym_2_3513: la $2, sym_2_3513
+.globl sym_2_3514
+sym_2_3514: la $2, sym_2_3514
+.globl sym_2_3515
+sym_2_3515: la $2, sym_2_3515
+.globl sym_2_3516
+sym_2_3516: la $2, sym_2_3516
+.globl sym_2_3517
+sym_2_3517: la $2, sym_2_3517
+.globl sym_2_3518
+sym_2_3518: la $2, sym_2_3518
+.globl sym_2_3519
+sym_2_3519: la $2, sym_2_3519
+.globl sym_2_3520
+sym_2_3520: la $2, sym_2_3520
+.globl sym_2_3521
+sym_2_3521: la $2, sym_2_3521
+.globl sym_2_3522
+sym_2_3522: la $2, sym_2_3522
+.globl sym_2_3523
+sym_2_3523: la $2, sym_2_3523
+.globl sym_2_3524
+sym_2_3524: la $2, sym_2_3524
+.globl sym_2_3525
+sym_2_3525: la $2, sym_2_3525
+.globl sym_2_3526
+sym_2_3526: la $2, sym_2_3526
+.globl sym_2_3527
+sym_2_3527: la $2, sym_2_3527
+.globl sym_2_3528
+sym_2_3528: la $2, sym_2_3528
+.globl sym_2_3529
+sym_2_3529: la $2, sym_2_3529
+.globl sym_2_3530
+sym_2_3530: la $2, sym_2_3530
+.globl sym_2_3531
+sym_2_3531: la $2, sym_2_3531
+.globl sym_2_3532
+sym_2_3532: la $2, sym_2_3532
+.globl sym_2_3533
+sym_2_3533: la $2, sym_2_3533
+.globl sym_2_3534
+sym_2_3534: la $2, sym_2_3534
+.globl sym_2_3535
+sym_2_3535: la $2, sym_2_3535
+.globl sym_2_3536
+sym_2_3536: la $2, sym_2_3536
+.globl sym_2_3537
+sym_2_3537: la $2, sym_2_3537
+.globl sym_2_3538
+sym_2_3538: la $2, sym_2_3538
+.globl sym_2_3539
+sym_2_3539: la $2, sym_2_3539
+.globl sym_2_3540
+sym_2_3540: la $2, sym_2_3540
+.globl sym_2_3541
+sym_2_3541: la $2, sym_2_3541
+.globl sym_2_3542
+sym_2_3542: la $2, sym_2_3542
+.globl sym_2_3543
+sym_2_3543: la $2, sym_2_3543
+.globl sym_2_3544
+sym_2_3544: la $2, sym_2_3544
+.globl sym_2_3545
+sym_2_3545: la $2, sym_2_3545
+.globl sym_2_3546
+sym_2_3546: la $2, sym_2_3546
+.globl sym_2_3547
+sym_2_3547: la $2, sym_2_3547
+.globl sym_2_3548
+sym_2_3548: la $2, sym_2_3548
+.globl sym_2_3549
+sym_2_3549: la $2, sym_2_3549
+.globl sym_2_3550
+sym_2_3550: la $2, sym_2_3550
+.globl sym_2_3551
+sym_2_3551: la $2, sym_2_3551
+.globl sym_2_3552
+sym_2_3552: la $2, sym_2_3552
+.globl sym_2_3553
+sym_2_3553: la $2, sym_2_3553
+.globl sym_2_3554
+sym_2_3554: la $2, sym_2_3554
+.globl sym_2_3555
+sym_2_3555: la $2, sym_2_3555
+.globl sym_2_3556
+sym_2_3556: la $2, sym_2_3556
+.globl sym_2_3557
+sym_2_3557: la $2, sym_2_3557
+.globl sym_2_3558
+sym_2_3558: la $2, sym_2_3558
+.globl sym_2_3559
+sym_2_3559: la $2, sym_2_3559
+.globl sym_2_3560
+sym_2_3560: la $2, sym_2_3560
+.globl sym_2_3561
+sym_2_3561: la $2, sym_2_3561
+.globl sym_2_3562
+sym_2_3562: la $2, sym_2_3562
+.globl sym_2_3563
+sym_2_3563: la $2, sym_2_3563
+.globl sym_2_3564
+sym_2_3564: la $2, sym_2_3564
+.globl sym_2_3565
+sym_2_3565: la $2, sym_2_3565
+.globl sym_2_3566
+sym_2_3566: la $2, sym_2_3566
+.globl sym_2_3567
+sym_2_3567: la $2, sym_2_3567
+.globl sym_2_3568
+sym_2_3568: la $2, sym_2_3568
+.globl sym_2_3569
+sym_2_3569: la $2, sym_2_3569
+.globl sym_2_3570
+sym_2_3570: la $2, sym_2_3570
+.globl sym_2_3571
+sym_2_3571: la $2, sym_2_3571
+.globl sym_2_3572
+sym_2_3572: la $2, sym_2_3572
+.globl sym_2_3573
+sym_2_3573: la $2, sym_2_3573
+.globl sym_2_3574
+sym_2_3574: la $2, sym_2_3574
+.globl sym_2_3575
+sym_2_3575: la $2, sym_2_3575
+.globl sym_2_3576
+sym_2_3576: la $2, sym_2_3576
+.globl sym_2_3577
+sym_2_3577: la $2, sym_2_3577
+.globl sym_2_3578
+sym_2_3578: la $2, sym_2_3578
+.globl sym_2_3579
+sym_2_3579: la $2, sym_2_3579
+.globl sym_2_3580
+sym_2_3580: la $2, sym_2_3580
+.globl sym_2_3581
+sym_2_3581: la $2, sym_2_3581
+.globl sym_2_3582
+sym_2_3582: la $2, sym_2_3582
+.globl sym_2_3583
+sym_2_3583: la $2, sym_2_3583
+.globl sym_2_3584
+sym_2_3584: la $2, sym_2_3584
+.globl sym_2_3585
+sym_2_3585: la $2, sym_2_3585
+.globl sym_2_3586
+sym_2_3586: la $2, sym_2_3586
+.globl sym_2_3587
+sym_2_3587: la $2, sym_2_3587
+.globl sym_2_3588
+sym_2_3588: la $2, sym_2_3588
+.globl sym_2_3589
+sym_2_3589: la $2, sym_2_3589
+.globl sym_2_3590
+sym_2_3590: la $2, sym_2_3590
+.globl sym_2_3591
+sym_2_3591: la $2, sym_2_3591
+.globl sym_2_3592
+sym_2_3592: la $2, sym_2_3592
+.globl sym_2_3593
+sym_2_3593: la $2, sym_2_3593
+.globl sym_2_3594
+sym_2_3594: la $2, sym_2_3594
+.globl sym_2_3595
+sym_2_3595: la $2, sym_2_3595
+.globl sym_2_3596
+sym_2_3596: la $2, sym_2_3596
+.globl sym_2_3597
+sym_2_3597: la $2, sym_2_3597
+.globl sym_2_3598
+sym_2_3598: la $2, sym_2_3598
+.globl sym_2_3599
+sym_2_3599: la $2, sym_2_3599
+.globl sym_2_3600
+sym_2_3600: la $2, sym_2_3600
+.globl sym_2_3601
+sym_2_3601: la $2, sym_2_3601
+.globl sym_2_3602
+sym_2_3602: la $2, sym_2_3602
+.globl sym_2_3603
+sym_2_3603: la $2, sym_2_3603
+.globl sym_2_3604
+sym_2_3604: la $2, sym_2_3604
+.globl sym_2_3605
+sym_2_3605: la $2, sym_2_3605
+.globl sym_2_3606
+sym_2_3606: la $2, sym_2_3606
+.globl sym_2_3607
+sym_2_3607: la $2, sym_2_3607
+.globl sym_2_3608
+sym_2_3608: la $2, sym_2_3608
+.globl sym_2_3609
+sym_2_3609: la $2, sym_2_3609
+.globl sym_2_3610
+sym_2_3610: la $2, sym_2_3610
+.globl sym_2_3611
+sym_2_3611: la $2, sym_2_3611
+.globl sym_2_3612
+sym_2_3612: la $2, sym_2_3612
+.globl sym_2_3613
+sym_2_3613: la $2, sym_2_3613
+.globl sym_2_3614
+sym_2_3614: la $2, sym_2_3614
+.globl sym_2_3615
+sym_2_3615: la $2, sym_2_3615
+.globl sym_2_3616
+sym_2_3616: la $2, sym_2_3616
+.globl sym_2_3617
+sym_2_3617: la $2, sym_2_3617
+.globl sym_2_3618
+sym_2_3618: la $2, sym_2_3618
+.globl sym_2_3619
+sym_2_3619: la $2, sym_2_3619
+.globl sym_2_3620
+sym_2_3620: la $2, sym_2_3620
+.globl sym_2_3621
+sym_2_3621: la $2, sym_2_3621
+.globl sym_2_3622
+sym_2_3622: la $2, sym_2_3622
+.globl sym_2_3623
+sym_2_3623: la $2, sym_2_3623
+.globl sym_2_3624
+sym_2_3624: la $2, sym_2_3624
+.globl sym_2_3625
+sym_2_3625: la $2, sym_2_3625
+.globl sym_2_3626
+sym_2_3626: la $2, sym_2_3626
+.globl sym_2_3627
+sym_2_3627: la $2, sym_2_3627
+.globl sym_2_3628
+sym_2_3628: la $2, sym_2_3628
+.globl sym_2_3629
+sym_2_3629: la $2, sym_2_3629
+.globl sym_2_3630
+sym_2_3630: la $2, sym_2_3630
+.globl sym_2_3631
+sym_2_3631: la $2, sym_2_3631
+.globl sym_2_3632
+sym_2_3632: la $2, sym_2_3632
+.globl sym_2_3633
+sym_2_3633: la $2, sym_2_3633
+.globl sym_2_3634
+sym_2_3634: la $2, sym_2_3634
+.globl sym_2_3635
+sym_2_3635: la $2, sym_2_3635
+.globl sym_2_3636
+sym_2_3636: la $2, sym_2_3636
+.globl sym_2_3637
+sym_2_3637: la $2, sym_2_3637
+.globl sym_2_3638
+sym_2_3638: la $2, sym_2_3638
+.globl sym_2_3639
+sym_2_3639: la $2, sym_2_3639
+.globl sym_2_3640
+sym_2_3640: la $2, sym_2_3640
+.globl sym_2_3641
+sym_2_3641: la $2, sym_2_3641
+.globl sym_2_3642
+sym_2_3642: la $2, sym_2_3642
+.globl sym_2_3643
+sym_2_3643: la $2, sym_2_3643
+.globl sym_2_3644
+sym_2_3644: la $2, sym_2_3644
+.globl sym_2_3645
+sym_2_3645: la $2, sym_2_3645
+.globl sym_2_3646
+sym_2_3646: la $2, sym_2_3646
+.globl sym_2_3647
+sym_2_3647: la $2, sym_2_3647
+.globl sym_2_3648
+sym_2_3648: la $2, sym_2_3648
+.globl sym_2_3649
+sym_2_3649: la $2, sym_2_3649
+.globl sym_2_3650
+sym_2_3650: la $2, sym_2_3650
+.globl sym_2_3651
+sym_2_3651: la $2, sym_2_3651
+.globl sym_2_3652
+sym_2_3652: la $2, sym_2_3652
+.globl sym_2_3653
+sym_2_3653: la $2, sym_2_3653
+.globl sym_2_3654
+sym_2_3654: la $2, sym_2_3654
+.globl sym_2_3655
+sym_2_3655: la $2, sym_2_3655
+.globl sym_2_3656
+sym_2_3656: la $2, sym_2_3656
+.globl sym_2_3657
+sym_2_3657: la $2, sym_2_3657
+.globl sym_2_3658
+sym_2_3658: la $2, sym_2_3658
+.globl sym_2_3659
+sym_2_3659: la $2, sym_2_3659
+.globl sym_2_3660
+sym_2_3660: la $2, sym_2_3660
+.globl sym_2_3661
+sym_2_3661: la $2, sym_2_3661
+.globl sym_2_3662
+sym_2_3662: la $2, sym_2_3662
+.globl sym_2_3663
+sym_2_3663: la $2, sym_2_3663
+.globl sym_2_3664
+sym_2_3664: la $2, sym_2_3664
+.globl sym_2_3665
+sym_2_3665: la $2, sym_2_3665
+.globl sym_2_3666
+sym_2_3666: la $2, sym_2_3666
+.globl sym_2_3667
+sym_2_3667: la $2, sym_2_3667
+.globl sym_2_3668
+sym_2_3668: la $2, sym_2_3668
+.globl sym_2_3669
+sym_2_3669: la $2, sym_2_3669
+.globl sym_2_3670
+sym_2_3670: la $2, sym_2_3670
+.globl sym_2_3671
+sym_2_3671: la $2, sym_2_3671
+.globl sym_2_3672
+sym_2_3672: la $2, sym_2_3672
+.globl sym_2_3673
+sym_2_3673: la $2, sym_2_3673
+.globl sym_2_3674
+sym_2_3674: la $2, sym_2_3674
+.globl sym_2_3675
+sym_2_3675: la $2, sym_2_3675
+.globl sym_2_3676
+sym_2_3676: la $2, sym_2_3676
+.globl sym_2_3677
+sym_2_3677: la $2, sym_2_3677
+.globl sym_2_3678
+sym_2_3678: la $2, sym_2_3678
+.globl sym_2_3679
+sym_2_3679: la $2, sym_2_3679
+.globl sym_2_3680
+sym_2_3680: la $2, sym_2_3680
+.globl sym_2_3681
+sym_2_3681: la $2, sym_2_3681
+.globl sym_2_3682
+sym_2_3682: la $2, sym_2_3682
+.globl sym_2_3683
+sym_2_3683: la $2, sym_2_3683
+.globl sym_2_3684
+sym_2_3684: la $2, sym_2_3684
+.globl sym_2_3685
+sym_2_3685: la $2, sym_2_3685
+.globl sym_2_3686
+sym_2_3686: la $2, sym_2_3686
+.globl sym_2_3687
+sym_2_3687: la $2, sym_2_3687
+.globl sym_2_3688
+sym_2_3688: la $2, sym_2_3688
+.globl sym_2_3689
+sym_2_3689: la $2, sym_2_3689
+.globl sym_2_3690
+sym_2_3690: la $2, sym_2_3690
+.globl sym_2_3691
+sym_2_3691: la $2, sym_2_3691
+.globl sym_2_3692
+sym_2_3692: la $2, sym_2_3692
+.globl sym_2_3693
+sym_2_3693: la $2, sym_2_3693
+.globl sym_2_3694
+sym_2_3694: la $2, sym_2_3694
+.globl sym_2_3695
+sym_2_3695: la $2, sym_2_3695
+.globl sym_2_3696
+sym_2_3696: la $2, sym_2_3696
+.globl sym_2_3697
+sym_2_3697: la $2, sym_2_3697
+.globl sym_2_3698
+sym_2_3698: la $2, sym_2_3698
+.globl sym_2_3699
+sym_2_3699: la $2, sym_2_3699
+.globl sym_2_3700
+sym_2_3700: la $2, sym_2_3700
+.globl sym_2_3701
+sym_2_3701: la $2, sym_2_3701
+.globl sym_2_3702
+sym_2_3702: la $2, sym_2_3702
+.globl sym_2_3703
+sym_2_3703: la $2, sym_2_3703
+.globl sym_2_3704
+sym_2_3704: la $2, sym_2_3704
+.globl sym_2_3705
+sym_2_3705: la $2, sym_2_3705
+.globl sym_2_3706
+sym_2_3706: la $2, sym_2_3706
+.globl sym_2_3707
+sym_2_3707: la $2, sym_2_3707
+.globl sym_2_3708
+sym_2_3708: la $2, sym_2_3708
+.globl sym_2_3709
+sym_2_3709: la $2, sym_2_3709
+.globl sym_2_3710
+sym_2_3710: la $2, sym_2_3710
+.globl sym_2_3711
+sym_2_3711: la $2, sym_2_3711
+.globl sym_2_3712
+sym_2_3712: la $2, sym_2_3712
+.globl sym_2_3713
+sym_2_3713: la $2, sym_2_3713
+.globl sym_2_3714
+sym_2_3714: la $2, sym_2_3714
+.globl sym_2_3715
+sym_2_3715: la $2, sym_2_3715
+.globl sym_2_3716
+sym_2_3716: la $2, sym_2_3716
+.globl sym_2_3717
+sym_2_3717: la $2, sym_2_3717
+.globl sym_2_3718
+sym_2_3718: la $2, sym_2_3718
+.globl sym_2_3719
+sym_2_3719: la $2, sym_2_3719
+.globl sym_2_3720
+sym_2_3720: la $2, sym_2_3720
+.globl sym_2_3721
+sym_2_3721: la $2, sym_2_3721
+.globl sym_2_3722
+sym_2_3722: la $2, sym_2_3722
+.globl sym_2_3723
+sym_2_3723: la $2, sym_2_3723
+.globl sym_2_3724
+sym_2_3724: la $2, sym_2_3724
+.globl sym_2_3725
+sym_2_3725: la $2, sym_2_3725
+.globl sym_2_3726
+sym_2_3726: la $2, sym_2_3726
+.globl sym_2_3727
+sym_2_3727: la $2, sym_2_3727
+.globl sym_2_3728
+sym_2_3728: la $2, sym_2_3728
+.globl sym_2_3729
+sym_2_3729: la $2, sym_2_3729
+.globl sym_2_3730
+sym_2_3730: la $2, sym_2_3730
+.globl sym_2_3731
+sym_2_3731: la $2, sym_2_3731
+.globl sym_2_3732
+sym_2_3732: la $2, sym_2_3732
+.globl sym_2_3733
+sym_2_3733: la $2, sym_2_3733
+.globl sym_2_3734
+sym_2_3734: la $2, sym_2_3734
+.globl sym_2_3735
+sym_2_3735: la $2, sym_2_3735
+.globl sym_2_3736
+sym_2_3736: la $2, sym_2_3736
+.globl sym_2_3737
+sym_2_3737: la $2, sym_2_3737
+.globl sym_2_3738
+sym_2_3738: la $2, sym_2_3738
+.globl sym_2_3739
+sym_2_3739: la $2, sym_2_3739
+.globl sym_2_3740
+sym_2_3740: la $2, sym_2_3740
+.globl sym_2_3741
+sym_2_3741: la $2, sym_2_3741
+.globl sym_2_3742
+sym_2_3742: la $2, sym_2_3742
+.globl sym_2_3743
+sym_2_3743: la $2, sym_2_3743
+.globl sym_2_3744
+sym_2_3744: la $2, sym_2_3744
+.globl sym_2_3745
+sym_2_3745: la $2, sym_2_3745
+.globl sym_2_3746
+sym_2_3746: la $2, sym_2_3746
+.globl sym_2_3747
+sym_2_3747: la $2, sym_2_3747
+.globl sym_2_3748
+sym_2_3748: la $2, sym_2_3748
+.globl sym_2_3749
+sym_2_3749: la $2, sym_2_3749
+.globl sym_2_3750
+sym_2_3750: la $2, sym_2_3750
+.globl sym_2_3751
+sym_2_3751: la $2, sym_2_3751
+.globl sym_2_3752
+sym_2_3752: la $2, sym_2_3752
+.globl sym_2_3753
+sym_2_3753: la $2, sym_2_3753
+.globl sym_2_3754
+sym_2_3754: la $2, sym_2_3754
+.globl sym_2_3755
+sym_2_3755: la $2, sym_2_3755
+.globl sym_2_3756
+sym_2_3756: la $2, sym_2_3756
+.globl sym_2_3757
+sym_2_3757: la $2, sym_2_3757
+.globl sym_2_3758
+sym_2_3758: la $2, sym_2_3758
+.globl sym_2_3759
+sym_2_3759: la $2, sym_2_3759
+.globl sym_2_3760
+sym_2_3760: la $2, sym_2_3760
+.globl sym_2_3761
+sym_2_3761: la $2, sym_2_3761
+.globl sym_2_3762
+sym_2_3762: la $2, sym_2_3762
+.globl sym_2_3763
+sym_2_3763: la $2, sym_2_3763
+.globl sym_2_3764
+sym_2_3764: la $2, sym_2_3764
+.globl sym_2_3765
+sym_2_3765: la $2, sym_2_3765
+.globl sym_2_3766
+sym_2_3766: la $2, sym_2_3766
+.globl sym_2_3767
+sym_2_3767: la $2, sym_2_3767
+.globl sym_2_3768
+sym_2_3768: la $2, sym_2_3768
+.globl sym_2_3769
+sym_2_3769: la $2, sym_2_3769
+.globl sym_2_3770
+sym_2_3770: la $2, sym_2_3770
+.globl sym_2_3771
+sym_2_3771: la $2, sym_2_3771
+.globl sym_2_3772
+sym_2_3772: la $2, sym_2_3772
+.globl sym_2_3773
+sym_2_3773: la $2, sym_2_3773
+.globl sym_2_3774
+sym_2_3774: la $2, sym_2_3774
+.globl sym_2_3775
+sym_2_3775: la $2, sym_2_3775
+.globl sym_2_3776
+sym_2_3776: la $2, sym_2_3776
+.globl sym_2_3777
+sym_2_3777: la $2, sym_2_3777
+.globl sym_2_3778
+sym_2_3778: la $2, sym_2_3778
+.globl sym_2_3779
+sym_2_3779: la $2, sym_2_3779
+.globl sym_2_3780
+sym_2_3780: la $2, sym_2_3780
+.globl sym_2_3781
+sym_2_3781: la $2, sym_2_3781
+.globl sym_2_3782
+sym_2_3782: la $2, sym_2_3782
+.globl sym_2_3783
+sym_2_3783: la $2, sym_2_3783
+.globl sym_2_3784
+sym_2_3784: la $2, sym_2_3784
+.globl sym_2_3785
+sym_2_3785: la $2, sym_2_3785
+.globl sym_2_3786
+sym_2_3786: la $2, sym_2_3786
+.globl sym_2_3787
+sym_2_3787: la $2, sym_2_3787
+.globl sym_2_3788
+sym_2_3788: la $2, sym_2_3788
+.globl sym_2_3789
+sym_2_3789: la $2, sym_2_3789
+.globl sym_2_3790
+sym_2_3790: la $2, sym_2_3790
+.globl sym_2_3791
+sym_2_3791: la $2, sym_2_3791
+.globl sym_2_3792
+sym_2_3792: la $2, sym_2_3792
+.globl sym_2_3793
+sym_2_3793: la $2, sym_2_3793
+.globl sym_2_3794
+sym_2_3794: la $2, sym_2_3794
+.globl sym_2_3795
+sym_2_3795: la $2, sym_2_3795
+.globl sym_2_3796
+sym_2_3796: la $2, sym_2_3796
+.globl sym_2_3797
+sym_2_3797: la $2, sym_2_3797
+.globl sym_2_3798
+sym_2_3798: la $2, sym_2_3798
+.globl sym_2_3799
+sym_2_3799: la $2, sym_2_3799
+.globl sym_2_3800
+sym_2_3800: la $2, sym_2_3800
+.globl sym_2_3801
+sym_2_3801: la $2, sym_2_3801
+.globl sym_2_3802
+sym_2_3802: la $2, sym_2_3802
+.globl sym_2_3803
+sym_2_3803: la $2, sym_2_3803
+.globl sym_2_3804
+sym_2_3804: la $2, sym_2_3804
+.globl sym_2_3805
+sym_2_3805: la $2, sym_2_3805
+.globl sym_2_3806
+sym_2_3806: la $2, sym_2_3806
+.globl sym_2_3807
+sym_2_3807: la $2, sym_2_3807
+.globl sym_2_3808
+sym_2_3808: la $2, sym_2_3808
+.globl sym_2_3809
+sym_2_3809: la $2, sym_2_3809
+.globl sym_2_3810
+sym_2_3810: la $2, sym_2_3810
+.globl sym_2_3811
+sym_2_3811: la $2, sym_2_3811
+.globl sym_2_3812
+sym_2_3812: la $2, sym_2_3812
+.globl sym_2_3813
+sym_2_3813: la $2, sym_2_3813
+.globl sym_2_3814
+sym_2_3814: la $2, sym_2_3814
+.globl sym_2_3815
+sym_2_3815: la $2, sym_2_3815
+.globl sym_2_3816
+sym_2_3816: la $2, sym_2_3816
+.globl sym_2_3817
+sym_2_3817: la $2, sym_2_3817
+.globl sym_2_3818
+sym_2_3818: la $2, sym_2_3818
+.globl sym_2_3819
+sym_2_3819: la $2, sym_2_3819
+.globl sym_2_3820
+sym_2_3820: la $2, sym_2_3820
+.globl sym_2_3821
+sym_2_3821: la $2, sym_2_3821
+.globl sym_2_3822
+sym_2_3822: la $2, sym_2_3822
+.globl sym_2_3823
+sym_2_3823: la $2, sym_2_3823
+.globl sym_2_3824
+sym_2_3824: la $2, sym_2_3824
+.globl sym_2_3825
+sym_2_3825: la $2, sym_2_3825
+.globl sym_2_3826
+sym_2_3826: la $2, sym_2_3826
+.globl sym_2_3827
+sym_2_3827: la $2, sym_2_3827
+.globl sym_2_3828
+sym_2_3828: la $2, sym_2_3828
+.globl sym_2_3829
+sym_2_3829: la $2, sym_2_3829
+.globl sym_2_3830
+sym_2_3830: la $2, sym_2_3830
+.globl sym_2_3831
+sym_2_3831: la $2, sym_2_3831
+.globl sym_2_3832
+sym_2_3832: la $2, sym_2_3832
+.globl sym_2_3833
+sym_2_3833: la $2, sym_2_3833
+.globl sym_2_3834
+sym_2_3834: la $2, sym_2_3834
+.globl sym_2_3835
+sym_2_3835: la $2, sym_2_3835
+.globl sym_2_3836
+sym_2_3836: la $2, sym_2_3836
+.globl sym_2_3837
+sym_2_3837: la $2, sym_2_3837
+.globl sym_2_3838
+sym_2_3838: la $2, sym_2_3838
+.globl sym_2_3839
+sym_2_3839: la $2, sym_2_3839
+.globl sym_2_3840
+sym_2_3840: la $2, sym_2_3840
+.globl sym_2_3841
+sym_2_3841: la $2, sym_2_3841
+.globl sym_2_3842
+sym_2_3842: la $2, sym_2_3842
+.globl sym_2_3843
+sym_2_3843: la $2, sym_2_3843
+.globl sym_2_3844
+sym_2_3844: la $2, sym_2_3844
+.globl sym_2_3845
+sym_2_3845: la $2, sym_2_3845
+.globl sym_2_3846
+sym_2_3846: la $2, sym_2_3846
+.globl sym_2_3847
+sym_2_3847: la $2, sym_2_3847
+.globl sym_2_3848
+sym_2_3848: la $2, sym_2_3848
+.globl sym_2_3849
+sym_2_3849: la $2, sym_2_3849
+.globl sym_2_3850
+sym_2_3850: la $2, sym_2_3850
+.globl sym_2_3851
+sym_2_3851: la $2, sym_2_3851
+.globl sym_2_3852
+sym_2_3852: la $2, sym_2_3852
+.globl sym_2_3853
+sym_2_3853: la $2, sym_2_3853
+.globl sym_2_3854
+sym_2_3854: la $2, sym_2_3854
+.globl sym_2_3855
+sym_2_3855: la $2, sym_2_3855
+.globl sym_2_3856
+sym_2_3856: la $2, sym_2_3856
+.globl sym_2_3857
+sym_2_3857: la $2, sym_2_3857
+.globl sym_2_3858
+sym_2_3858: la $2, sym_2_3858
+.globl sym_2_3859
+sym_2_3859: la $2, sym_2_3859
+.globl sym_2_3860
+sym_2_3860: la $2, sym_2_3860
+.globl sym_2_3861
+sym_2_3861: la $2, sym_2_3861
+.globl sym_2_3862
+sym_2_3862: la $2, sym_2_3862
+.globl sym_2_3863
+sym_2_3863: la $2, sym_2_3863
+.globl sym_2_3864
+sym_2_3864: la $2, sym_2_3864
+.globl sym_2_3865
+sym_2_3865: la $2, sym_2_3865
+.globl sym_2_3866
+sym_2_3866: la $2, sym_2_3866
+.globl sym_2_3867
+sym_2_3867: la $2, sym_2_3867
+.globl sym_2_3868
+sym_2_3868: la $2, sym_2_3868
+.globl sym_2_3869
+sym_2_3869: la $2, sym_2_3869
+.globl sym_2_3870
+sym_2_3870: la $2, sym_2_3870
+.globl sym_2_3871
+sym_2_3871: la $2, sym_2_3871
+.globl sym_2_3872
+sym_2_3872: la $2, sym_2_3872
+.globl sym_2_3873
+sym_2_3873: la $2, sym_2_3873
+.globl sym_2_3874
+sym_2_3874: la $2, sym_2_3874
+.globl sym_2_3875
+sym_2_3875: la $2, sym_2_3875
+.globl sym_2_3876
+sym_2_3876: la $2, sym_2_3876
+.globl sym_2_3877
+sym_2_3877: la $2, sym_2_3877
+.globl sym_2_3878
+sym_2_3878: la $2, sym_2_3878
+.globl sym_2_3879
+sym_2_3879: la $2, sym_2_3879
+.globl sym_2_3880
+sym_2_3880: la $2, sym_2_3880
+.globl sym_2_3881
+sym_2_3881: la $2, sym_2_3881
+.globl sym_2_3882
+sym_2_3882: la $2, sym_2_3882
+.globl sym_2_3883
+sym_2_3883: la $2, sym_2_3883
+.globl sym_2_3884
+sym_2_3884: la $2, sym_2_3884
+.globl sym_2_3885
+sym_2_3885: la $2, sym_2_3885
+.globl sym_2_3886
+sym_2_3886: la $2, sym_2_3886
+.globl sym_2_3887
+sym_2_3887: la $2, sym_2_3887
+.globl sym_2_3888
+sym_2_3888: la $2, sym_2_3888
+.globl sym_2_3889
+sym_2_3889: la $2, sym_2_3889
+.globl sym_2_3890
+sym_2_3890: la $2, sym_2_3890
+.globl sym_2_3891
+sym_2_3891: la $2, sym_2_3891
+.globl sym_2_3892
+sym_2_3892: la $2, sym_2_3892
+.globl sym_2_3893
+sym_2_3893: la $2, sym_2_3893
+.globl sym_2_3894
+sym_2_3894: la $2, sym_2_3894
+.globl sym_2_3895
+sym_2_3895: la $2, sym_2_3895
+.globl sym_2_3896
+sym_2_3896: la $2, sym_2_3896
+.globl sym_2_3897
+sym_2_3897: la $2, sym_2_3897
+.globl sym_2_3898
+sym_2_3898: la $2, sym_2_3898
+.globl sym_2_3899
+sym_2_3899: la $2, sym_2_3899
+.globl sym_2_3900
+sym_2_3900: la $2, sym_2_3900
+.globl sym_2_3901
+sym_2_3901: la $2, sym_2_3901
+.globl sym_2_3902
+sym_2_3902: la $2, sym_2_3902
+.globl sym_2_3903
+sym_2_3903: la $2, sym_2_3903
+.globl sym_2_3904
+sym_2_3904: la $2, sym_2_3904
+.globl sym_2_3905
+sym_2_3905: la $2, sym_2_3905
+.globl sym_2_3906
+sym_2_3906: la $2, sym_2_3906
+.globl sym_2_3907
+sym_2_3907: la $2, sym_2_3907
+.globl sym_2_3908
+sym_2_3908: la $2, sym_2_3908
+.globl sym_2_3909
+sym_2_3909: la $2, sym_2_3909
+.globl sym_2_3910
+sym_2_3910: la $2, sym_2_3910
+.globl sym_2_3911
+sym_2_3911: la $2, sym_2_3911
+.globl sym_2_3912
+sym_2_3912: la $2, sym_2_3912
+.globl sym_2_3913
+sym_2_3913: la $2, sym_2_3913
+.globl sym_2_3914
+sym_2_3914: la $2, sym_2_3914
+.globl sym_2_3915
+sym_2_3915: la $2, sym_2_3915
+.globl sym_2_3916
+sym_2_3916: la $2, sym_2_3916
+.globl sym_2_3917
+sym_2_3917: la $2, sym_2_3917
+.globl sym_2_3918
+sym_2_3918: la $2, sym_2_3918
+.globl sym_2_3919
+sym_2_3919: la $2, sym_2_3919
+.globl sym_2_3920
+sym_2_3920: la $2, sym_2_3920
+.globl sym_2_3921
+sym_2_3921: la $2, sym_2_3921
+.globl sym_2_3922
+sym_2_3922: la $2, sym_2_3922
+.globl sym_2_3923
+sym_2_3923: la $2, sym_2_3923
+.globl sym_2_3924
+sym_2_3924: la $2, sym_2_3924
+.globl sym_2_3925
+sym_2_3925: la $2, sym_2_3925
+.globl sym_2_3926
+sym_2_3926: la $2, sym_2_3926
+.globl sym_2_3927
+sym_2_3927: la $2, sym_2_3927
+.globl sym_2_3928
+sym_2_3928: la $2, sym_2_3928
+.globl sym_2_3929
+sym_2_3929: la $2, sym_2_3929
+.globl sym_2_3930
+sym_2_3930: la $2, sym_2_3930
+.globl sym_2_3931
+sym_2_3931: la $2, sym_2_3931
+.globl sym_2_3932
+sym_2_3932: la $2, sym_2_3932
+.globl sym_2_3933
+sym_2_3933: la $2, sym_2_3933
+.globl sym_2_3934
+sym_2_3934: la $2, sym_2_3934
+.globl sym_2_3935
+sym_2_3935: la $2, sym_2_3935
+.globl sym_2_3936
+sym_2_3936: la $2, sym_2_3936
+.globl sym_2_3937
+sym_2_3937: la $2, sym_2_3937
+.globl sym_2_3938
+sym_2_3938: la $2, sym_2_3938
+.globl sym_2_3939
+sym_2_3939: la $2, sym_2_3939
+.globl sym_2_3940
+sym_2_3940: la $2, sym_2_3940
+.globl sym_2_3941
+sym_2_3941: la $2, sym_2_3941
+.globl sym_2_3942
+sym_2_3942: la $2, sym_2_3942
+.globl sym_2_3943
+sym_2_3943: la $2, sym_2_3943
+.globl sym_2_3944
+sym_2_3944: la $2, sym_2_3944
+.globl sym_2_3945
+sym_2_3945: la $2, sym_2_3945
+.globl sym_2_3946
+sym_2_3946: la $2, sym_2_3946
+.globl sym_2_3947
+sym_2_3947: la $2, sym_2_3947
+.globl sym_2_3948
+sym_2_3948: la $2, sym_2_3948
+.globl sym_2_3949
+sym_2_3949: la $2, sym_2_3949
+.globl sym_2_3950
+sym_2_3950: la $2, sym_2_3950
+.globl sym_2_3951
+sym_2_3951: la $2, sym_2_3951
+.globl sym_2_3952
+sym_2_3952: la $2, sym_2_3952
+.globl sym_2_3953
+sym_2_3953: la $2, sym_2_3953
+.globl sym_2_3954
+sym_2_3954: la $2, sym_2_3954
+.globl sym_2_3955
+sym_2_3955: la $2, sym_2_3955
+.globl sym_2_3956
+sym_2_3956: la $2, sym_2_3956
+.globl sym_2_3957
+sym_2_3957: la $2, sym_2_3957
+.globl sym_2_3958
+sym_2_3958: la $2, sym_2_3958
+.globl sym_2_3959
+sym_2_3959: la $2, sym_2_3959
+.globl sym_2_3960
+sym_2_3960: la $2, sym_2_3960
+.globl sym_2_3961
+sym_2_3961: la $2, sym_2_3961
+.globl sym_2_3962
+sym_2_3962: la $2, sym_2_3962
+.globl sym_2_3963
+sym_2_3963: la $2, sym_2_3963
+.globl sym_2_3964
+sym_2_3964: la $2, sym_2_3964
+.globl sym_2_3965
+sym_2_3965: la $2, sym_2_3965
+.globl sym_2_3966
+sym_2_3966: la $2, sym_2_3966
+.globl sym_2_3967
+sym_2_3967: la $2, sym_2_3967
+.globl sym_2_3968
+sym_2_3968: la $2, sym_2_3968
+.globl sym_2_3969
+sym_2_3969: la $2, sym_2_3969
+.globl sym_2_3970
+sym_2_3970: la $2, sym_2_3970
+.globl sym_2_3971
+sym_2_3971: la $2, sym_2_3971
+.globl sym_2_3972
+sym_2_3972: la $2, sym_2_3972
+.globl sym_2_3973
+sym_2_3973: la $2, sym_2_3973
+.globl sym_2_3974
+sym_2_3974: la $2, sym_2_3974
+.globl sym_2_3975
+sym_2_3975: la $2, sym_2_3975
+.globl sym_2_3976
+sym_2_3976: la $2, sym_2_3976
+.globl sym_2_3977
+sym_2_3977: la $2, sym_2_3977
+.globl sym_2_3978
+sym_2_3978: la $2, sym_2_3978
+.globl sym_2_3979
+sym_2_3979: la $2, sym_2_3979
+.globl sym_2_3980
+sym_2_3980: la $2, sym_2_3980
+.globl sym_2_3981
+sym_2_3981: la $2, sym_2_3981
+.globl sym_2_3982
+sym_2_3982: la $2, sym_2_3982
+.globl sym_2_3983
+sym_2_3983: la $2, sym_2_3983
+.globl sym_2_3984
+sym_2_3984: la $2, sym_2_3984
+.globl sym_2_3985
+sym_2_3985: la $2, sym_2_3985
+.globl sym_2_3986
+sym_2_3986: la $2, sym_2_3986
+.globl sym_2_3987
+sym_2_3987: la $2, sym_2_3987
+.globl sym_2_3988
+sym_2_3988: la $2, sym_2_3988
+.globl sym_2_3989
+sym_2_3989: la $2, sym_2_3989
+.globl sym_2_3990
+sym_2_3990: la $2, sym_2_3990
+.globl sym_2_3991
+sym_2_3991: la $2, sym_2_3991
+.globl sym_2_3992
+sym_2_3992: la $2, sym_2_3992
+.globl sym_2_3993
+sym_2_3993: la $2, sym_2_3993
+.globl sym_2_3994
+sym_2_3994: la $2, sym_2_3994
+.globl sym_2_3995
+sym_2_3995: la $2, sym_2_3995
+.globl sym_2_3996
+sym_2_3996: la $2, sym_2_3996
+.globl sym_2_3997
+sym_2_3997: la $2, sym_2_3997
+.globl sym_2_3998
+sym_2_3998: la $2, sym_2_3998
+.globl sym_2_3999
+sym_2_3999: la $2, sym_2_3999
+.globl sym_2_4000
+sym_2_4000: la $2, sym_2_4000
+.globl sym_2_4001
+sym_2_4001: la $2, sym_2_4001
+.globl sym_2_4002
+sym_2_4002: la $2, sym_2_4002
+.globl sym_2_4003
+sym_2_4003: la $2, sym_2_4003
+.globl sym_2_4004
+sym_2_4004: la $2, sym_2_4004
+.globl sym_2_4005
+sym_2_4005: la $2, sym_2_4005
+.globl sym_2_4006
+sym_2_4006: la $2, sym_2_4006
+.globl sym_2_4007
+sym_2_4007: la $2, sym_2_4007
+.globl sym_2_4008
+sym_2_4008: la $2, sym_2_4008
+.globl sym_2_4009
+sym_2_4009: la $2, sym_2_4009
+.globl sym_2_4010
+sym_2_4010: la $2, sym_2_4010
+.globl sym_2_4011
+sym_2_4011: la $2, sym_2_4011
+.globl sym_2_4012
+sym_2_4012: la $2, sym_2_4012
+.globl sym_2_4013
+sym_2_4013: la $2, sym_2_4013
+.globl sym_2_4014
+sym_2_4014: la $2, sym_2_4014
+.globl sym_2_4015
+sym_2_4015: la $2, sym_2_4015
+.globl sym_2_4016
+sym_2_4016: la $2, sym_2_4016
+.globl sym_2_4017
+sym_2_4017: la $2, sym_2_4017
+.globl sym_2_4018
+sym_2_4018: la $2, sym_2_4018
+.globl sym_2_4019
+sym_2_4019: la $2, sym_2_4019
+.globl sym_2_4020
+sym_2_4020: la $2, sym_2_4020
+.globl sym_2_4021
+sym_2_4021: la $2, sym_2_4021
+.globl sym_2_4022
+sym_2_4022: la $2, sym_2_4022
+.globl sym_2_4023
+sym_2_4023: la $2, sym_2_4023
+.globl sym_2_4024
+sym_2_4024: la $2, sym_2_4024
+.globl sym_2_4025
+sym_2_4025: la $2, sym_2_4025
+.globl sym_2_4026
+sym_2_4026: la $2, sym_2_4026
+.globl sym_2_4027
+sym_2_4027: la $2, sym_2_4027
+.globl sym_2_4028
+sym_2_4028: la $2, sym_2_4028
+.globl sym_2_4029
+sym_2_4029: la $2, sym_2_4029
+.globl sym_2_4030
+sym_2_4030: la $2, sym_2_4030
+.globl sym_2_4031
+sym_2_4031: la $2, sym_2_4031
+.globl sym_2_4032
+sym_2_4032: la $2, sym_2_4032
+.globl sym_2_4033
+sym_2_4033: la $2, sym_2_4033
+.globl sym_2_4034
+sym_2_4034: la $2, sym_2_4034
+.globl sym_2_4035
+sym_2_4035: la $2, sym_2_4035
+.globl sym_2_4036
+sym_2_4036: la $2, sym_2_4036
+.globl sym_2_4037
+sym_2_4037: la $2, sym_2_4037
+.globl sym_2_4038
+sym_2_4038: la $2, sym_2_4038
+.globl sym_2_4039
+sym_2_4039: la $2, sym_2_4039
+.globl sym_2_4040
+sym_2_4040: la $2, sym_2_4040
+.globl sym_2_4041
+sym_2_4041: la $2, sym_2_4041
+.globl sym_2_4042
+sym_2_4042: la $2, sym_2_4042
+.globl sym_2_4043
+sym_2_4043: la $2, sym_2_4043
+.globl sym_2_4044
+sym_2_4044: la $2, sym_2_4044
+.globl sym_2_4045
+sym_2_4045: la $2, sym_2_4045
+.globl sym_2_4046
+sym_2_4046: la $2, sym_2_4046
+.globl sym_2_4047
+sym_2_4047: la $2, sym_2_4047
+.globl sym_2_4048
+sym_2_4048: la $2, sym_2_4048
+.globl sym_2_4049
+sym_2_4049: la $2, sym_2_4049
+.globl sym_2_4050
+sym_2_4050: la $2, sym_2_4050
+.globl sym_2_4051
+sym_2_4051: la $2, sym_2_4051
+.globl sym_2_4052
+sym_2_4052: la $2, sym_2_4052
+.globl sym_2_4053
+sym_2_4053: la $2, sym_2_4053
+.globl sym_2_4054
+sym_2_4054: la $2, sym_2_4054
+.globl sym_2_4055
+sym_2_4055: la $2, sym_2_4055
+.globl sym_2_4056
+sym_2_4056: la $2, sym_2_4056
+.globl sym_2_4057
+sym_2_4057: la $2, sym_2_4057
+.globl sym_2_4058
+sym_2_4058: la $2, sym_2_4058
+.globl sym_2_4059
+sym_2_4059: la $2, sym_2_4059
+.globl sym_2_4060
+sym_2_4060: la $2, sym_2_4060
+.globl sym_2_4061
+sym_2_4061: la $2, sym_2_4061
+.globl sym_2_4062
+sym_2_4062: la $2, sym_2_4062
+.globl sym_2_4063
+sym_2_4063: la $2, sym_2_4063
+.globl sym_2_4064
+sym_2_4064: la $2, sym_2_4064
+.globl sym_2_4065
+sym_2_4065: la $2, sym_2_4065
+.globl sym_2_4066
+sym_2_4066: la $2, sym_2_4066
+.globl sym_2_4067
+sym_2_4067: la $2, sym_2_4067
+.globl sym_2_4068
+sym_2_4068: la $2, sym_2_4068
+.globl sym_2_4069
+sym_2_4069: la $2, sym_2_4069
+.globl sym_2_4070
+sym_2_4070: la $2, sym_2_4070
+.globl sym_2_4071
+sym_2_4071: la $2, sym_2_4071
+.globl sym_2_4072
+sym_2_4072: la $2, sym_2_4072
+.globl sym_2_4073
+sym_2_4073: la $2, sym_2_4073
+.globl sym_2_4074
+sym_2_4074: la $2, sym_2_4074
+.globl sym_2_4075
+sym_2_4075: la $2, sym_2_4075
+.globl sym_2_4076
+sym_2_4076: la $2, sym_2_4076
+.globl sym_2_4077
+sym_2_4077: la $2, sym_2_4077
+.globl sym_2_4078
+sym_2_4078: la $2, sym_2_4078
+.globl sym_2_4079
+sym_2_4079: la $2, sym_2_4079
+.globl sym_2_4080
+sym_2_4080: la $2, sym_2_4080
+.globl sym_2_4081
+sym_2_4081: la $2, sym_2_4081
+.globl sym_2_4082
+sym_2_4082: la $2, sym_2_4082
+.globl sym_2_4083
+sym_2_4083: la $2, sym_2_4083
+.globl sym_2_4084
+sym_2_4084: la $2, sym_2_4084
+.globl sym_2_4085
+sym_2_4085: la $2, sym_2_4085
+.globl sym_2_4086
+sym_2_4086: la $2, sym_2_4086
+.globl sym_2_4087
+sym_2_4087: la $2, sym_2_4087
+.globl sym_2_4088
+sym_2_4088: la $2, sym_2_4088
+.globl sym_2_4089
+sym_2_4089: la $2, sym_2_4089
+.globl sym_2_4090
+sym_2_4090: la $2, sym_2_4090
+.globl sym_2_4091
+sym_2_4091: la $2, sym_2_4091
+.globl sym_2_4092
+sym_2_4092: la $2, sym_2_4092
+.globl sym_2_4093
+sym_2_4093: la $2, sym_2_4093
+.globl sym_2_4094
+sym_2_4094: la $2, sym_2_4094
+.globl sym_2_4095
+sym_2_4095: la $2, sym_2_4095
+.globl sym_2_4096
+sym_2_4096: la $2, sym_2_4096
+.globl sym_2_4097
+sym_2_4097: la $2, sym_2_4097
+.globl sym_2_4098
+sym_2_4098: la $2, sym_2_4098
+.globl sym_2_4099
+sym_2_4099: la $2, sym_2_4099
+.globl sym_2_4100
+sym_2_4100: la $2, sym_2_4100
+.globl sym_2_4101
+sym_2_4101: la $2, sym_2_4101
+.globl sym_2_4102
+sym_2_4102: la $2, sym_2_4102
+.globl sym_2_4103
+sym_2_4103: la $2, sym_2_4103
+.globl sym_2_4104
+sym_2_4104: la $2, sym_2_4104
+.globl sym_2_4105
+sym_2_4105: la $2, sym_2_4105
+.globl sym_2_4106
+sym_2_4106: la $2, sym_2_4106
+.globl sym_2_4107
+sym_2_4107: la $2, sym_2_4107
+.globl sym_2_4108
+sym_2_4108: la $2, sym_2_4108
+.globl sym_2_4109
+sym_2_4109: la $2, sym_2_4109
+.globl sym_2_4110
+sym_2_4110: la $2, sym_2_4110
+.globl sym_2_4111
+sym_2_4111: la $2, sym_2_4111
+.globl sym_2_4112
+sym_2_4112: la $2, sym_2_4112
+.globl sym_2_4113
+sym_2_4113: la $2, sym_2_4113
+.globl sym_2_4114
+sym_2_4114: la $2, sym_2_4114
+.globl sym_2_4115
+sym_2_4115: la $2, sym_2_4115
+.globl sym_2_4116
+sym_2_4116: la $2, sym_2_4116
+.globl sym_2_4117
+sym_2_4117: la $2, sym_2_4117
+.globl sym_2_4118
+sym_2_4118: la $2, sym_2_4118
+.globl sym_2_4119
+sym_2_4119: la $2, sym_2_4119
+.globl sym_2_4120
+sym_2_4120: la $2, sym_2_4120
+.globl sym_2_4121
+sym_2_4121: la $2, sym_2_4121
+.globl sym_2_4122
+sym_2_4122: la $2, sym_2_4122
+.globl sym_2_4123
+sym_2_4123: la $2, sym_2_4123
+.globl sym_2_4124
+sym_2_4124: la $2, sym_2_4124
+.globl sym_2_4125
+sym_2_4125: la $2, sym_2_4125
+.globl sym_2_4126
+sym_2_4126: la $2, sym_2_4126
+.globl sym_2_4127
+sym_2_4127: la $2, sym_2_4127
+.globl sym_2_4128
+sym_2_4128: la $2, sym_2_4128
+.globl sym_2_4129
+sym_2_4129: la $2, sym_2_4129
+.globl sym_2_4130
+sym_2_4130: la $2, sym_2_4130
+.globl sym_2_4131
+sym_2_4131: la $2, sym_2_4131
+.globl sym_2_4132
+sym_2_4132: la $2, sym_2_4132
+.globl sym_2_4133
+sym_2_4133: la $2, sym_2_4133
+.globl sym_2_4134
+sym_2_4134: la $2, sym_2_4134
+.globl sym_2_4135
+sym_2_4135: la $2, sym_2_4135
+.globl sym_2_4136
+sym_2_4136: la $2, sym_2_4136
+.globl sym_2_4137
+sym_2_4137: la $2, sym_2_4137
+.globl sym_2_4138
+sym_2_4138: la $2, sym_2_4138
+.globl sym_2_4139
+sym_2_4139: la $2, sym_2_4139
+.globl sym_2_4140
+sym_2_4140: la $2, sym_2_4140
+.globl sym_2_4141
+sym_2_4141: la $2, sym_2_4141
+.globl sym_2_4142
+sym_2_4142: la $2, sym_2_4142
+.globl sym_2_4143
+sym_2_4143: la $2, sym_2_4143
+.globl sym_2_4144
+sym_2_4144: la $2, sym_2_4144
+.globl sym_2_4145
+sym_2_4145: la $2, sym_2_4145
+.globl sym_2_4146
+sym_2_4146: la $2, sym_2_4146
+.globl sym_2_4147
+sym_2_4147: la $2, sym_2_4147
+.globl sym_2_4148
+sym_2_4148: la $2, sym_2_4148
+.globl sym_2_4149
+sym_2_4149: la $2, sym_2_4149
+.globl sym_2_4150
+sym_2_4150: la $2, sym_2_4150
+.globl sym_2_4151
+sym_2_4151: la $2, sym_2_4151
+.globl sym_2_4152
+sym_2_4152: la $2, sym_2_4152
+.globl sym_2_4153
+sym_2_4153: la $2, sym_2_4153
+.globl sym_2_4154
+sym_2_4154: la $2, sym_2_4154
+.globl sym_2_4155
+sym_2_4155: la $2, sym_2_4155
+.globl sym_2_4156
+sym_2_4156: la $2, sym_2_4156
+.globl sym_2_4157
+sym_2_4157: la $2, sym_2_4157
+.globl sym_2_4158
+sym_2_4158: la $2, sym_2_4158
+.globl sym_2_4159
+sym_2_4159: la $2, sym_2_4159
+.globl sym_2_4160
+sym_2_4160: la $2, sym_2_4160
+.globl sym_2_4161
+sym_2_4161: la $2, sym_2_4161
+.globl sym_2_4162
+sym_2_4162: la $2, sym_2_4162
+.globl sym_2_4163
+sym_2_4163: la $2, sym_2_4163
+.globl sym_2_4164
+sym_2_4164: la $2, sym_2_4164
+.globl sym_2_4165
+sym_2_4165: la $2, sym_2_4165
+.globl sym_2_4166
+sym_2_4166: la $2, sym_2_4166
+.globl sym_2_4167
+sym_2_4167: la $2, sym_2_4167
+.globl sym_2_4168
+sym_2_4168: la $2, sym_2_4168
+.globl sym_2_4169
+sym_2_4169: la $2, sym_2_4169
+.globl sym_2_4170
+sym_2_4170: la $2, sym_2_4170
+.globl sym_2_4171
+sym_2_4171: la $2, sym_2_4171
+.globl sym_2_4172
+sym_2_4172: la $2, sym_2_4172
+.globl sym_2_4173
+sym_2_4173: la $2, sym_2_4173
+.globl sym_2_4174
+sym_2_4174: la $2, sym_2_4174
+.globl sym_2_4175
+sym_2_4175: la $2, sym_2_4175
+.globl sym_2_4176
+sym_2_4176: la $2, sym_2_4176
+.globl sym_2_4177
+sym_2_4177: la $2, sym_2_4177
+.globl sym_2_4178
+sym_2_4178: la $2, sym_2_4178
+.globl sym_2_4179
+sym_2_4179: la $2, sym_2_4179
+.globl sym_2_4180
+sym_2_4180: la $2, sym_2_4180
+.globl sym_2_4181
+sym_2_4181: la $2, sym_2_4181
+.globl sym_2_4182
+sym_2_4182: la $2, sym_2_4182
+.globl sym_2_4183
+sym_2_4183: la $2, sym_2_4183
+.globl sym_2_4184
+sym_2_4184: la $2, sym_2_4184
+.globl sym_2_4185
+sym_2_4185: la $2, sym_2_4185
+.globl sym_2_4186
+sym_2_4186: la $2, sym_2_4186
+.globl sym_2_4187
+sym_2_4187: la $2, sym_2_4187
+.globl sym_2_4188
+sym_2_4188: la $2, sym_2_4188
+.globl sym_2_4189
+sym_2_4189: la $2, sym_2_4189
+.globl sym_2_4190
+sym_2_4190: la $2, sym_2_4190
+.globl sym_2_4191
+sym_2_4191: la $2, sym_2_4191
+.globl sym_2_4192
+sym_2_4192: la $2, sym_2_4192
+.globl sym_2_4193
+sym_2_4193: la $2, sym_2_4193
+.globl sym_2_4194
+sym_2_4194: la $2, sym_2_4194
+.globl sym_2_4195
+sym_2_4195: la $2, sym_2_4195
+.globl sym_2_4196
+sym_2_4196: la $2, sym_2_4196
+.globl sym_2_4197
+sym_2_4197: la $2, sym_2_4197
+.globl sym_2_4198
+sym_2_4198: la $2, sym_2_4198
+.globl sym_2_4199
+sym_2_4199: la $2, sym_2_4199
+.globl sym_2_4200
+sym_2_4200: la $2, sym_2_4200
+.globl sym_2_4201
+sym_2_4201: la $2, sym_2_4201
+.globl sym_2_4202
+sym_2_4202: la $2, sym_2_4202
+.globl sym_2_4203
+sym_2_4203: la $2, sym_2_4203
+.globl sym_2_4204
+sym_2_4204: la $2, sym_2_4204
+.globl sym_2_4205
+sym_2_4205: la $2, sym_2_4205
+.globl sym_2_4206
+sym_2_4206: la $2, sym_2_4206
+.globl sym_2_4207
+sym_2_4207: la $2, sym_2_4207
+.globl sym_2_4208
+sym_2_4208: la $2, sym_2_4208
+.globl sym_2_4209
+sym_2_4209: la $2, sym_2_4209
+.globl sym_2_4210
+sym_2_4210: la $2, sym_2_4210
+.globl sym_2_4211
+sym_2_4211: la $2, sym_2_4211
+.globl sym_2_4212
+sym_2_4212: la $2, sym_2_4212
+.globl sym_2_4213
+sym_2_4213: la $2, sym_2_4213
+.globl sym_2_4214
+sym_2_4214: la $2, sym_2_4214
+.globl sym_2_4215
+sym_2_4215: la $2, sym_2_4215
+.globl sym_2_4216
+sym_2_4216: la $2, sym_2_4216
+.globl sym_2_4217
+sym_2_4217: la $2, sym_2_4217
+.globl sym_2_4218
+sym_2_4218: la $2, sym_2_4218
+.globl sym_2_4219
+sym_2_4219: la $2, sym_2_4219
+.globl sym_2_4220
+sym_2_4220: la $2, sym_2_4220
+.globl sym_2_4221
+sym_2_4221: la $2, sym_2_4221
+.globl sym_2_4222
+sym_2_4222: la $2, sym_2_4222
+.globl sym_2_4223
+sym_2_4223: la $2, sym_2_4223
+.globl sym_2_4224
+sym_2_4224: la $2, sym_2_4224
+.globl sym_2_4225
+sym_2_4225: la $2, sym_2_4225
+.globl sym_2_4226
+sym_2_4226: la $2, sym_2_4226
+.globl sym_2_4227
+sym_2_4227: la $2, sym_2_4227
+.globl sym_2_4228
+sym_2_4228: la $2, sym_2_4228
+.globl sym_2_4229
+sym_2_4229: la $2, sym_2_4229
+.globl sym_2_4230
+sym_2_4230: la $2, sym_2_4230
+.globl sym_2_4231
+sym_2_4231: la $2, sym_2_4231
+.globl sym_2_4232
+sym_2_4232: la $2, sym_2_4232
+.globl sym_2_4233
+sym_2_4233: la $2, sym_2_4233
+.globl sym_2_4234
+sym_2_4234: la $2, sym_2_4234
+.globl sym_2_4235
+sym_2_4235: la $2, sym_2_4235
+.globl sym_2_4236
+sym_2_4236: la $2, sym_2_4236
+.globl sym_2_4237
+sym_2_4237: la $2, sym_2_4237
+.globl sym_2_4238
+sym_2_4238: la $2, sym_2_4238
+.globl sym_2_4239
+sym_2_4239: la $2, sym_2_4239
+.globl sym_2_4240
+sym_2_4240: la $2, sym_2_4240
+.globl sym_2_4241
+sym_2_4241: la $2, sym_2_4241
+.globl sym_2_4242
+sym_2_4242: la $2, sym_2_4242
+.globl sym_2_4243
+sym_2_4243: la $2, sym_2_4243
+.globl sym_2_4244
+sym_2_4244: la $2, sym_2_4244
+.globl sym_2_4245
+sym_2_4245: la $2, sym_2_4245
+.globl sym_2_4246
+sym_2_4246: la $2, sym_2_4246
+.globl sym_2_4247
+sym_2_4247: la $2, sym_2_4247
+.globl sym_2_4248
+sym_2_4248: la $2, sym_2_4248
+.globl sym_2_4249
+sym_2_4249: la $2, sym_2_4249
+.globl sym_2_4250
+sym_2_4250: la $2, sym_2_4250
+.globl sym_2_4251
+sym_2_4251: la $2, sym_2_4251
+.globl sym_2_4252
+sym_2_4252: la $2, sym_2_4252
+.globl sym_2_4253
+sym_2_4253: la $2, sym_2_4253
+.globl sym_2_4254
+sym_2_4254: la $2, sym_2_4254
+.globl sym_2_4255
+sym_2_4255: la $2, sym_2_4255
+.globl sym_2_4256
+sym_2_4256: la $2, sym_2_4256
+.globl sym_2_4257
+sym_2_4257: la $2, sym_2_4257
+.globl sym_2_4258
+sym_2_4258: la $2, sym_2_4258
+.globl sym_2_4259
+sym_2_4259: la $2, sym_2_4259
+.globl sym_2_4260
+sym_2_4260: la $2, sym_2_4260
+.globl sym_2_4261
+sym_2_4261: la $2, sym_2_4261
+.globl sym_2_4262
+sym_2_4262: la $2, sym_2_4262
+.globl sym_2_4263
+sym_2_4263: la $2, sym_2_4263
+.globl sym_2_4264
+sym_2_4264: la $2, sym_2_4264
+.globl sym_2_4265
+sym_2_4265: la $2, sym_2_4265
+.globl sym_2_4266
+sym_2_4266: la $2, sym_2_4266
+.globl sym_2_4267
+sym_2_4267: la $2, sym_2_4267
+.globl sym_2_4268
+sym_2_4268: la $2, sym_2_4268
+.globl sym_2_4269
+sym_2_4269: la $2, sym_2_4269
+.globl sym_2_4270
+sym_2_4270: la $2, sym_2_4270
+.globl sym_2_4271
+sym_2_4271: la $2, sym_2_4271
+.globl sym_2_4272
+sym_2_4272: la $2, sym_2_4272
+.globl sym_2_4273
+sym_2_4273: la $2, sym_2_4273
+.globl sym_2_4274
+sym_2_4274: la $2, sym_2_4274
+.globl sym_2_4275
+sym_2_4275: la $2, sym_2_4275
+.globl sym_2_4276
+sym_2_4276: la $2, sym_2_4276
+.globl sym_2_4277
+sym_2_4277: la $2, sym_2_4277
+.globl sym_2_4278
+sym_2_4278: la $2, sym_2_4278
+.globl sym_2_4279
+sym_2_4279: la $2, sym_2_4279
+.globl sym_2_4280
+sym_2_4280: la $2, sym_2_4280
+.globl sym_2_4281
+sym_2_4281: la $2, sym_2_4281
+.globl sym_2_4282
+sym_2_4282: la $2, sym_2_4282
+.globl sym_2_4283
+sym_2_4283: la $2, sym_2_4283
+.globl sym_2_4284
+sym_2_4284: la $2, sym_2_4284
+.globl sym_2_4285
+sym_2_4285: la $2, sym_2_4285
+.globl sym_2_4286
+sym_2_4286: la $2, sym_2_4286
+.globl sym_2_4287
+sym_2_4287: la $2, sym_2_4287
+.globl sym_2_4288
+sym_2_4288: la $2, sym_2_4288
+.globl sym_2_4289
+sym_2_4289: la $2, sym_2_4289
+.globl sym_2_4290
+sym_2_4290: la $2, sym_2_4290
+.globl sym_2_4291
+sym_2_4291: la $2, sym_2_4291
+.globl sym_2_4292
+sym_2_4292: la $2, sym_2_4292
+.globl sym_2_4293
+sym_2_4293: la $2, sym_2_4293
+.globl sym_2_4294
+sym_2_4294: la $2, sym_2_4294
+.globl sym_2_4295
+sym_2_4295: la $2, sym_2_4295
+.globl sym_2_4296
+sym_2_4296: la $2, sym_2_4296
+.globl sym_2_4297
+sym_2_4297: la $2, sym_2_4297
+.globl sym_2_4298
+sym_2_4298: la $2, sym_2_4298
+.globl sym_2_4299
+sym_2_4299: la $2, sym_2_4299
+.globl sym_2_4300
+sym_2_4300: la $2, sym_2_4300
+.globl sym_2_4301
+sym_2_4301: la $2, sym_2_4301
+.globl sym_2_4302
+sym_2_4302: la $2, sym_2_4302
+.globl sym_2_4303
+sym_2_4303: la $2, sym_2_4303
+.globl sym_2_4304
+sym_2_4304: la $2, sym_2_4304
+.globl sym_2_4305
+sym_2_4305: la $2, sym_2_4305
+.globl sym_2_4306
+sym_2_4306: la $2, sym_2_4306
+.globl sym_2_4307
+sym_2_4307: la $2, sym_2_4307
+.globl sym_2_4308
+sym_2_4308: la $2, sym_2_4308
+.globl sym_2_4309
+sym_2_4309: la $2, sym_2_4309
+.globl sym_2_4310
+sym_2_4310: la $2, sym_2_4310
+.globl sym_2_4311
+sym_2_4311: la $2, sym_2_4311
+.globl sym_2_4312
+sym_2_4312: la $2, sym_2_4312
+.globl sym_2_4313
+sym_2_4313: la $2, sym_2_4313
+.globl sym_2_4314
+sym_2_4314: la $2, sym_2_4314
+.globl sym_2_4315
+sym_2_4315: la $2, sym_2_4315
+.globl sym_2_4316
+sym_2_4316: la $2, sym_2_4316
+.globl sym_2_4317
+sym_2_4317: la $2, sym_2_4317
+.globl sym_2_4318
+sym_2_4318: la $2, sym_2_4318
+.globl sym_2_4319
+sym_2_4319: la $2, sym_2_4319
+.globl sym_2_4320
+sym_2_4320: la $2, sym_2_4320
+.globl sym_2_4321
+sym_2_4321: la $2, sym_2_4321
+.globl sym_2_4322
+sym_2_4322: la $2, sym_2_4322
+.globl sym_2_4323
+sym_2_4323: la $2, sym_2_4323
+.globl sym_2_4324
+sym_2_4324: la $2, sym_2_4324
+.globl sym_2_4325
+sym_2_4325: la $2, sym_2_4325
+.globl sym_2_4326
+sym_2_4326: la $2, sym_2_4326
+.globl sym_2_4327
+sym_2_4327: la $2, sym_2_4327
+.globl sym_2_4328
+sym_2_4328: la $2, sym_2_4328
+.globl sym_2_4329
+sym_2_4329: la $2, sym_2_4329
+.globl sym_2_4330
+sym_2_4330: la $2, sym_2_4330
+.globl sym_2_4331
+sym_2_4331: la $2, sym_2_4331
+.globl sym_2_4332
+sym_2_4332: la $2, sym_2_4332
+.globl sym_2_4333
+sym_2_4333: la $2, sym_2_4333
+.globl sym_2_4334
+sym_2_4334: la $2, sym_2_4334
+.globl sym_2_4335
+sym_2_4335: la $2, sym_2_4335
+.globl sym_2_4336
+sym_2_4336: la $2, sym_2_4336
+.globl sym_2_4337
+sym_2_4337: la $2, sym_2_4337
+.globl sym_2_4338
+sym_2_4338: la $2, sym_2_4338
+.globl sym_2_4339
+sym_2_4339: la $2, sym_2_4339
+.globl sym_2_4340
+sym_2_4340: la $2, sym_2_4340
+.globl sym_2_4341
+sym_2_4341: la $2, sym_2_4341
+.globl sym_2_4342
+sym_2_4342: la $2, sym_2_4342
+.globl sym_2_4343
+sym_2_4343: la $2, sym_2_4343
+.globl sym_2_4344
+sym_2_4344: la $2, sym_2_4344
+.globl sym_2_4345
+sym_2_4345: la $2, sym_2_4345
+.globl sym_2_4346
+sym_2_4346: la $2, sym_2_4346
+.globl sym_2_4347
+sym_2_4347: la $2, sym_2_4347
+.globl sym_2_4348
+sym_2_4348: la $2, sym_2_4348
+.globl sym_2_4349
+sym_2_4349: la $2, sym_2_4349
+.globl sym_2_4350
+sym_2_4350: la $2, sym_2_4350
+.globl sym_2_4351
+sym_2_4351: la $2, sym_2_4351
+.globl sym_2_4352
+sym_2_4352: la $2, sym_2_4352
+.globl sym_2_4353
+sym_2_4353: la $2, sym_2_4353
+.globl sym_2_4354
+sym_2_4354: la $2, sym_2_4354
+.globl sym_2_4355
+sym_2_4355: la $2, sym_2_4355
+.globl sym_2_4356
+sym_2_4356: la $2, sym_2_4356
+.globl sym_2_4357
+sym_2_4357: la $2, sym_2_4357
+.globl sym_2_4358
+sym_2_4358: la $2, sym_2_4358
+.globl sym_2_4359
+sym_2_4359: la $2, sym_2_4359
+.globl sym_2_4360
+sym_2_4360: la $2, sym_2_4360
+.globl sym_2_4361
+sym_2_4361: la $2, sym_2_4361
+.globl sym_2_4362
+sym_2_4362: la $2, sym_2_4362
+.globl sym_2_4363
+sym_2_4363: la $2, sym_2_4363
+.globl sym_2_4364
+sym_2_4364: la $2, sym_2_4364
+.globl sym_2_4365
+sym_2_4365: la $2, sym_2_4365
+.globl sym_2_4366
+sym_2_4366: la $2, sym_2_4366
+.globl sym_2_4367
+sym_2_4367: la $2, sym_2_4367
+.globl sym_2_4368
+sym_2_4368: la $2, sym_2_4368
+.globl sym_2_4369
+sym_2_4369: la $2, sym_2_4369
+.globl sym_2_4370
+sym_2_4370: la $2, sym_2_4370
+.globl sym_2_4371
+sym_2_4371: la $2, sym_2_4371
+.globl sym_2_4372
+sym_2_4372: la $2, sym_2_4372
+.globl sym_2_4373
+sym_2_4373: la $2, sym_2_4373
+.globl sym_2_4374
+sym_2_4374: la $2, sym_2_4374
+.globl sym_2_4375
+sym_2_4375: la $2, sym_2_4375
+.globl sym_2_4376
+sym_2_4376: la $2, sym_2_4376
+.globl sym_2_4377
+sym_2_4377: la $2, sym_2_4377
+.globl sym_2_4378
+sym_2_4378: la $2, sym_2_4378
+.globl sym_2_4379
+sym_2_4379: la $2, sym_2_4379
+.globl sym_2_4380
+sym_2_4380: la $2, sym_2_4380
+.globl sym_2_4381
+sym_2_4381: la $2, sym_2_4381
+.globl sym_2_4382
+sym_2_4382: la $2, sym_2_4382
+.globl sym_2_4383
+sym_2_4383: la $2, sym_2_4383
+.globl sym_2_4384
+sym_2_4384: la $2, sym_2_4384
+.globl sym_2_4385
+sym_2_4385: la $2, sym_2_4385
+.globl sym_2_4386
+sym_2_4386: la $2, sym_2_4386
+.globl sym_2_4387
+sym_2_4387: la $2, sym_2_4387
+.globl sym_2_4388
+sym_2_4388: la $2, sym_2_4388
+.globl sym_2_4389
+sym_2_4389: la $2, sym_2_4389
+.globl sym_2_4390
+sym_2_4390: la $2, sym_2_4390
+.globl sym_2_4391
+sym_2_4391: la $2, sym_2_4391
+.globl sym_2_4392
+sym_2_4392: la $2, sym_2_4392
+.globl sym_2_4393
+sym_2_4393: la $2, sym_2_4393
+.globl sym_2_4394
+sym_2_4394: la $2, sym_2_4394
+.globl sym_2_4395
+sym_2_4395: la $2, sym_2_4395
+.globl sym_2_4396
+sym_2_4396: la $2, sym_2_4396
+.globl sym_2_4397
+sym_2_4397: la $2, sym_2_4397
+.globl sym_2_4398
+sym_2_4398: la $2, sym_2_4398
+.globl sym_2_4399
+sym_2_4399: la $2, sym_2_4399
+.globl sym_2_4400
+sym_2_4400: la $2, sym_2_4400
+.globl sym_2_4401
+sym_2_4401: la $2, sym_2_4401
+.globl sym_2_4402
+sym_2_4402: la $2, sym_2_4402
+.globl sym_2_4403
+sym_2_4403: la $2, sym_2_4403
+.globl sym_2_4404
+sym_2_4404: la $2, sym_2_4404
+.globl sym_2_4405
+sym_2_4405: la $2, sym_2_4405
+.globl sym_2_4406
+sym_2_4406: la $2, sym_2_4406
+.globl sym_2_4407
+sym_2_4407: la $2, sym_2_4407
+.globl sym_2_4408
+sym_2_4408: la $2, sym_2_4408
+.globl sym_2_4409
+sym_2_4409: la $2, sym_2_4409
+.globl sym_2_4410
+sym_2_4410: la $2, sym_2_4410
+.globl sym_2_4411
+sym_2_4411: la $2, sym_2_4411
+.globl sym_2_4412
+sym_2_4412: la $2, sym_2_4412
+.globl sym_2_4413
+sym_2_4413: la $2, sym_2_4413
+.globl sym_2_4414
+sym_2_4414: la $2, sym_2_4414
+.globl sym_2_4415
+sym_2_4415: la $2, sym_2_4415
+.globl sym_2_4416
+sym_2_4416: la $2, sym_2_4416
+.globl sym_2_4417
+sym_2_4417: la $2, sym_2_4417
+.globl sym_2_4418
+sym_2_4418: la $2, sym_2_4418
+.globl sym_2_4419
+sym_2_4419: la $2, sym_2_4419
+.globl sym_2_4420
+sym_2_4420: la $2, sym_2_4420
+.globl sym_2_4421
+sym_2_4421: la $2, sym_2_4421
+.globl sym_2_4422
+sym_2_4422: la $2, sym_2_4422
+.globl sym_2_4423
+sym_2_4423: la $2, sym_2_4423
+.globl sym_2_4424
+sym_2_4424: la $2, sym_2_4424
+.globl sym_2_4425
+sym_2_4425: la $2, sym_2_4425
+.globl sym_2_4426
+sym_2_4426: la $2, sym_2_4426
+.globl sym_2_4427
+sym_2_4427: la $2, sym_2_4427
+.globl sym_2_4428
+sym_2_4428: la $2, sym_2_4428
+.globl sym_2_4429
+sym_2_4429: la $2, sym_2_4429
+.globl sym_2_4430
+sym_2_4430: la $2, sym_2_4430
+.globl sym_2_4431
+sym_2_4431: la $2, sym_2_4431
+.globl sym_2_4432
+sym_2_4432: la $2, sym_2_4432
+.globl sym_2_4433
+sym_2_4433: la $2, sym_2_4433
+.globl sym_2_4434
+sym_2_4434: la $2, sym_2_4434
+.globl sym_2_4435
+sym_2_4435: la $2, sym_2_4435
+.globl sym_2_4436
+sym_2_4436: la $2, sym_2_4436
+.globl sym_2_4437
+sym_2_4437: la $2, sym_2_4437
+.globl sym_2_4438
+sym_2_4438: la $2, sym_2_4438
+.globl sym_2_4439
+sym_2_4439: la $2, sym_2_4439
+.globl sym_2_4440
+sym_2_4440: la $2, sym_2_4440
+.globl sym_2_4441
+sym_2_4441: la $2, sym_2_4441
+.globl sym_2_4442
+sym_2_4442: la $2, sym_2_4442
+.globl sym_2_4443
+sym_2_4443: la $2, sym_2_4443
+.globl sym_2_4444
+sym_2_4444: la $2, sym_2_4444
+.globl sym_2_4445
+sym_2_4445: la $2, sym_2_4445
+.globl sym_2_4446
+sym_2_4446: la $2, sym_2_4446
+.globl sym_2_4447
+sym_2_4447: la $2, sym_2_4447
+.globl sym_2_4448
+sym_2_4448: la $2, sym_2_4448
+.globl sym_2_4449
+sym_2_4449: la $2, sym_2_4449
+.globl sym_2_4450
+sym_2_4450: la $2, sym_2_4450
+.globl sym_2_4451
+sym_2_4451: la $2, sym_2_4451
+.globl sym_2_4452
+sym_2_4452: la $2, sym_2_4452
+.globl sym_2_4453
+sym_2_4453: la $2, sym_2_4453
+.globl sym_2_4454
+sym_2_4454: la $2, sym_2_4454
+.globl sym_2_4455
+sym_2_4455: la $2, sym_2_4455
+.globl sym_2_4456
+sym_2_4456: la $2, sym_2_4456
+.globl sym_2_4457
+sym_2_4457: la $2, sym_2_4457
+.globl sym_2_4458
+sym_2_4458: la $2, sym_2_4458
+.globl sym_2_4459
+sym_2_4459: la $2, sym_2_4459
+.globl sym_2_4460
+sym_2_4460: la $2, sym_2_4460
+.globl sym_2_4461
+sym_2_4461: la $2, sym_2_4461
+.globl sym_2_4462
+sym_2_4462: la $2, sym_2_4462
+.globl sym_2_4463
+sym_2_4463: la $2, sym_2_4463
+.globl sym_2_4464
+sym_2_4464: la $2, sym_2_4464
+.globl sym_2_4465
+sym_2_4465: la $2, sym_2_4465
+.globl sym_2_4466
+sym_2_4466: la $2, sym_2_4466
+.globl sym_2_4467
+sym_2_4467: la $2, sym_2_4467
+.globl sym_2_4468
+sym_2_4468: la $2, sym_2_4468
+.globl sym_2_4469
+sym_2_4469: la $2, sym_2_4469
+.globl sym_2_4470
+sym_2_4470: la $2, sym_2_4470
+.globl sym_2_4471
+sym_2_4471: la $2, sym_2_4471
+.globl sym_2_4472
+sym_2_4472: la $2, sym_2_4472
+.globl sym_2_4473
+sym_2_4473: la $2, sym_2_4473
+.globl sym_2_4474
+sym_2_4474: la $2, sym_2_4474
+.globl sym_2_4475
+sym_2_4475: la $2, sym_2_4475
+.globl sym_2_4476
+sym_2_4476: la $2, sym_2_4476
+.globl sym_2_4477
+sym_2_4477: la $2, sym_2_4477
+.globl sym_2_4478
+sym_2_4478: la $2, sym_2_4478
+.globl sym_2_4479
+sym_2_4479: la $2, sym_2_4479
+.globl sym_2_4480
+sym_2_4480: la $2, sym_2_4480
+.globl sym_2_4481
+sym_2_4481: la $2, sym_2_4481
+.globl sym_2_4482
+sym_2_4482: la $2, sym_2_4482
+.globl sym_2_4483
+sym_2_4483: la $2, sym_2_4483
+.globl sym_2_4484
+sym_2_4484: la $2, sym_2_4484
+.globl sym_2_4485
+sym_2_4485: la $2, sym_2_4485
+.globl sym_2_4486
+sym_2_4486: la $2, sym_2_4486
+.globl sym_2_4487
+sym_2_4487: la $2, sym_2_4487
+.globl sym_2_4488
+sym_2_4488: la $2, sym_2_4488
+.globl sym_2_4489
+sym_2_4489: la $2, sym_2_4489
+.globl sym_2_4490
+sym_2_4490: la $2, sym_2_4490
+.globl sym_2_4491
+sym_2_4491: la $2, sym_2_4491
+.globl sym_2_4492
+sym_2_4492: la $2, sym_2_4492
+.globl sym_2_4493
+sym_2_4493: la $2, sym_2_4493
+.globl sym_2_4494
+sym_2_4494: la $2, sym_2_4494
+.globl sym_2_4495
+sym_2_4495: la $2, sym_2_4495
+.globl sym_2_4496
+sym_2_4496: la $2, sym_2_4496
+.globl sym_2_4497
+sym_2_4497: la $2, sym_2_4497
+.globl sym_2_4498
+sym_2_4498: la $2, sym_2_4498
+.globl sym_2_4499
+sym_2_4499: la $2, sym_2_4499
+.globl sym_2_4500
+sym_2_4500: la $2, sym_2_4500
+.globl sym_2_4501
+sym_2_4501: la $2, sym_2_4501
+.globl sym_2_4502
+sym_2_4502: la $2, sym_2_4502
+.globl sym_2_4503
+sym_2_4503: la $2, sym_2_4503
+.globl sym_2_4504
+sym_2_4504: la $2, sym_2_4504
+.globl sym_2_4505
+sym_2_4505: la $2, sym_2_4505
+.globl sym_2_4506
+sym_2_4506: la $2, sym_2_4506
+.globl sym_2_4507
+sym_2_4507: la $2, sym_2_4507
+.globl sym_2_4508
+sym_2_4508: la $2, sym_2_4508
+.globl sym_2_4509
+sym_2_4509: la $2, sym_2_4509
+.globl sym_2_4510
+sym_2_4510: la $2, sym_2_4510
+.globl sym_2_4511
+sym_2_4511: la $2, sym_2_4511
+.globl sym_2_4512
+sym_2_4512: la $2, sym_2_4512
+.globl sym_2_4513
+sym_2_4513: la $2, sym_2_4513
+.globl sym_2_4514
+sym_2_4514: la $2, sym_2_4514
+.globl sym_2_4515
+sym_2_4515: la $2, sym_2_4515
+.globl sym_2_4516
+sym_2_4516: la $2, sym_2_4516
+.globl sym_2_4517
+sym_2_4517: la $2, sym_2_4517
+.globl sym_2_4518
+sym_2_4518: la $2, sym_2_4518
+.globl sym_2_4519
+sym_2_4519: la $2, sym_2_4519
+.globl sym_2_4520
+sym_2_4520: la $2, sym_2_4520
+.globl sym_2_4521
+sym_2_4521: la $2, sym_2_4521
+.globl sym_2_4522
+sym_2_4522: la $2, sym_2_4522
+.globl sym_2_4523
+sym_2_4523: la $2, sym_2_4523
+.globl sym_2_4524
+sym_2_4524: la $2, sym_2_4524
+.globl sym_2_4525
+sym_2_4525: la $2, sym_2_4525
+.globl sym_2_4526
+sym_2_4526: la $2, sym_2_4526
+.globl sym_2_4527
+sym_2_4527: la $2, sym_2_4527
+.globl sym_2_4528
+sym_2_4528: la $2, sym_2_4528
+.globl sym_2_4529
+sym_2_4529: la $2, sym_2_4529
+.globl sym_2_4530
+sym_2_4530: la $2, sym_2_4530
+.globl sym_2_4531
+sym_2_4531: la $2, sym_2_4531
+.globl sym_2_4532
+sym_2_4532: la $2, sym_2_4532
+.globl sym_2_4533
+sym_2_4533: la $2, sym_2_4533
+.globl sym_2_4534
+sym_2_4534: la $2, sym_2_4534
+.globl sym_2_4535
+sym_2_4535: la $2, sym_2_4535
+.globl sym_2_4536
+sym_2_4536: la $2, sym_2_4536
+.globl sym_2_4537
+sym_2_4537: la $2, sym_2_4537
+.globl sym_2_4538
+sym_2_4538: la $2, sym_2_4538
+.globl sym_2_4539
+sym_2_4539: la $2, sym_2_4539
+.globl sym_2_4540
+sym_2_4540: la $2, sym_2_4540
+.globl sym_2_4541
+sym_2_4541: la $2, sym_2_4541
+.globl sym_2_4542
+sym_2_4542: la $2, sym_2_4542
+.globl sym_2_4543
+sym_2_4543: la $2, sym_2_4543
+.globl sym_2_4544
+sym_2_4544: la $2, sym_2_4544
+.globl sym_2_4545
+sym_2_4545: la $2, sym_2_4545
+.globl sym_2_4546
+sym_2_4546: la $2, sym_2_4546
+.globl sym_2_4547
+sym_2_4547: la $2, sym_2_4547
+.globl sym_2_4548
+sym_2_4548: la $2, sym_2_4548
+.globl sym_2_4549
+sym_2_4549: la $2, sym_2_4549
+.globl sym_2_4550
+sym_2_4550: la $2, sym_2_4550
+.globl sym_2_4551
+sym_2_4551: la $2, sym_2_4551
+.globl sym_2_4552
+sym_2_4552: la $2, sym_2_4552
+.globl sym_2_4553
+sym_2_4553: la $2, sym_2_4553
+.globl sym_2_4554
+sym_2_4554: la $2, sym_2_4554
+.globl sym_2_4555
+sym_2_4555: la $2, sym_2_4555
+.globl sym_2_4556
+sym_2_4556: la $2, sym_2_4556
+.globl sym_2_4557
+sym_2_4557: la $2, sym_2_4557
+.globl sym_2_4558
+sym_2_4558: la $2, sym_2_4558
+.globl sym_2_4559
+sym_2_4559: la $2, sym_2_4559
+.globl sym_2_4560
+sym_2_4560: la $2, sym_2_4560
+.globl sym_2_4561
+sym_2_4561: la $2, sym_2_4561
+.globl sym_2_4562
+sym_2_4562: la $2, sym_2_4562
+.globl sym_2_4563
+sym_2_4563: la $2, sym_2_4563
+.globl sym_2_4564
+sym_2_4564: la $2, sym_2_4564
+.globl sym_2_4565
+sym_2_4565: la $2, sym_2_4565
+.globl sym_2_4566
+sym_2_4566: la $2, sym_2_4566
+.globl sym_2_4567
+sym_2_4567: la $2, sym_2_4567
+.globl sym_2_4568
+sym_2_4568: la $2, sym_2_4568
+.globl sym_2_4569
+sym_2_4569: la $2, sym_2_4569
+.globl sym_2_4570
+sym_2_4570: la $2, sym_2_4570
+.globl sym_2_4571
+sym_2_4571: la $2, sym_2_4571
+.globl sym_2_4572
+sym_2_4572: la $2, sym_2_4572
+.globl sym_2_4573
+sym_2_4573: la $2, sym_2_4573
+.globl sym_2_4574
+sym_2_4574: la $2, sym_2_4574
+.globl sym_2_4575
+sym_2_4575: la $2, sym_2_4575
+.globl sym_2_4576
+sym_2_4576: la $2, sym_2_4576
+.globl sym_2_4577
+sym_2_4577: la $2, sym_2_4577
+.globl sym_2_4578
+sym_2_4578: la $2, sym_2_4578
+.globl sym_2_4579
+sym_2_4579: la $2, sym_2_4579
+.globl sym_2_4580
+sym_2_4580: la $2, sym_2_4580
+.globl sym_2_4581
+sym_2_4581: la $2, sym_2_4581
+.globl sym_2_4582
+sym_2_4582: la $2, sym_2_4582
+.globl sym_2_4583
+sym_2_4583: la $2, sym_2_4583
+.globl sym_2_4584
+sym_2_4584: la $2, sym_2_4584
+.globl sym_2_4585
+sym_2_4585: la $2, sym_2_4585
+.globl sym_2_4586
+sym_2_4586: la $2, sym_2_4586
+.globl sym_2_4587
+sym_2_4587: la $2, sym_2_4587
+.globl sym_2_4588
+sym_2_4588: la $2, sym_2_4588
+.globl sym_2_4589
+sym_2_4589: la $2, sym_2_4589
+.globl sym_2_4590
+sym_2_4590: la $2, sym_2_4590
+.globl sym_2_4591
+sym_2_4591: la $2, sym_2_4591
+.globl sym_2_4592
+sym_2_4592: la $2, sym_2_4592
+.globl sym_2_4593
+sym_2_4593: la $2, sym_2_4593
+.globl sym_2_4594
+sym_2_4594: la $2, sym_2_4594
+.globl sym_2_4595
+sym_2_4595: la $2, sym_2_4595
+.globl sym_2_4596
+sym_2_4596: la $2, sym_2_4596
+.globl sym_2_4597
+sym_2_4597: la $2, sym_2_4597
+.globl sym_2_4598
+sym_2_4598: la $2, sym_2_4598
+.globl sym_2_4599
+sym_2_4599: la $2, sym_2_4599
+.globl sym_2_4600
+sym_2_4600: la $2, sym_2_4600
+.globl sym_2_4601
+sym_2_4601: la $2, sym_2_4601
+.globl sym_2_4602
+sym_2_4602: la $2, sym_2_4602
+.globl sym_2_4603
+sym_2_4603: la $2, sym_2_4603
+.globl sym_2_4604
+sym_2_4604: la $2, sym_2_4604
+.globl sym_2_4605
+sym_2_4605: la $2, sym_2_4605
+.globl sym_2_4606
+sym_2_4606: la $2, sym_2_4606
+.globl sym_2_4607
+sym_2_4607: la $2, sym_2_4607
+.globl sym_2_4608
+sym_2_4608: la $2, sym_2_4608
+.globl sym_2_4609
+sym_2_4609: la $2, sym_2_4609
+.globl sym_2_4610
+sym_2_4610: la $2, sym_2_4610
+.globl sym_2_4611
+sym_2_4611: la $2, sym_2_4611
+.globl sym_2_4612
+sym_2_4612: la $2, sym_2_4612
+.globl sym_2_4613
+sym_2_4613: la $2, sym_2_4613
+.globl sym_2_4614
+sym_2_4614: la $2, sym_2_4614
+.globl sym_2_4615
+sym_2_4615: la $2, sym_2_4615
+.globl sym_2_4616
+sym_2_4616: la $2, sym_2_4616
+.globl sym_2_4617
+sym_2_4617: la $2, sym_2_4617
+.globl sym_2_4618
+sym_2_4618: la $2, sym_2_4618
+.globl sym_2_4619
+sym_2_4619: la $2, sym_2_4619
+.globl sym_2_4620
+sym_2_4620: la $2, sym_2_4620
+.globl sym_2_4621
+sym_2_4621: la $2, sym_2_4621
+.globl sym_2_4622
+sym_2_4622: la $2, sym_2_4622
+.globl sym_2_4623
+sym_2_4623: la $2, sym_2_4623
+.globl sym_2_4624
+sym_2_4624: la $2, sym_2_4624
+.globl sym_2_4625
+sym_2_4625: la $2, sym_2_4625
+.globl sym_2_4626
+sym_2_4626: la $2, sym_2_4626
+.globl sym_2_4627
+sym_2_4627: la $2, sym_2_4627
+.globl sym_2_4628
+sym_2_4628: la $2, sym_2_4628
+.globl sym_2_4629
+sym_2_4629: la $2, sym_2_4629
+.globl sym_2_4630
+sym_2_4630: la $2, sym_2_4630
+.globl sym_2_4631
+sym_2_4631: la $2, sym_2_4631
+.globl sym_2_4632
+sym_2_4632: la $2, sym_2_4632
+.globl sym_2_4633
+sym_2_4633: la $2, sym_2_4633
+.globl sym_2_4634
+sym_2_4634: la $2, sym_2_4634
+.globl sym_2_4635
+sym_2_4635: la $2, sym_2_4635
+.globl sym_2_4636
+sym_2_4636: la $2, sym_2_4636
+.globl sym_2_4637
+sym_2_4637: la $2, sym_2_4637
+.globl sym_2_4638
+sym_2_4638: la $2, sym_2_4638
+.globl sym_2_4639
+sym_2_4639: la $2, sym_2_4639
+.globl sym_2_4640
+sym_2_4640: la $2, sym_2_4640
+.globl sym_2_4641
+sym_2_4641: la $2, sym_2_4641
+.globl sym_2_4642
+sym_2_4642: la $2, sym_2_4642
+.globl sym_2_4643
+sym_2_4643: la $2, sym_2_4643
+.globl sym_2_4644
+sym_2_4644: la $2, sym_2_4644
+.globl sym_2_4645
+sym_2_4645: la $2, sym_2_4645
+.globl sym_2_4646
+sym_2_4646: la $2, sym_2_4646
+.globl sym_2_4647
+sym_2_4647: la $2, sym_2_4647
+.globl sym_2_4648
+sym_2_4648: la $2, sym_2_4648
+.globl sym_2_4649
+sym_2_4649: la $2, sym_2_4649
+.globl sym_2_4650
+sym_2_4650: la $2, sym_2_4650
+.globl sym_2_4651
+sym_2_4651: la $2, sym_2_4651
+.globl sym_2_4652
+sym_2_4652: la $2, sym_2_4652
+.globl sym_2_4653
+sym_2_4653: la $2, sym_2_4653
+.globl sym_2_4654
+sym_2_4654: la $2, sym_2_4654
+.globl sym_2_4655
+sym_2_4655: la $2, sym_2_4655
+.globl sym_2_4656
+sym_2_4656: la $2, sym_2_4656
+.globl sym_2_4657
+sym_2_4657: la $2, sym_2_4657
+.globl sym_2_4658
+sym_2_4658: la $2, sym_2_4658
+.globl sym_2_4659
+sym_2_4659: la $2, sym_2_4659
+.globl sym_2_4660
+sym_2_4660: la $2, sym_2_4660
+.globl sym_2_4661
+sym_2_4661: la $2, sym_2_4661
+.globl sym_2_4662
+sym_2_4662: la $2, sym_2_4662
+.globl sym_2_4663
+sym_2_4663: la $2, sym_2_4663
+.globl sym_2_4664
+sym_2_4664: la $2, sym_2_4664
+.globl sym_2_4665
+sym_2_4665: la $2, sym_2_4665
+.globl sym_2_4666
+sym_2_4666: la $2, sym_2_4666
+.globl sym_2_4667
+sym_2_4667: la $2, sym_2_4667
+.globl sym_2_4668
+sym_2_4668: la $2, sym_2_4668
+.globl sym_2_4669
+sym_2_4669: la $2, sym_2_4669
+.globl sym_2_4670
+sym_2_4670: la $2, sym_2_4670
+.globl sym_2_4671
+sym_2_4671: la $2, sym_2_4671
+.globl sym_2_4672
+sym_2_4672: la $2, sym_2_4672
+.globl sym_2_4673
+sym_2_4673: la $2, sym_2_4673
+.globl sym_2_4674
+sym_2_4674: la $2, sym_2_4674
+.globl sym_2_4675
+sym_2_4675: la $2, sym_2_4675
+.globl sym_2_4676
+sym_2_4676: la $2, sym_2_4676
+.globl sym_2_4677
+sym_2_4677: la $2, sym_2_4677
+.globl sym_2_4678
+sym_2_4678: la $2, sym_2_4678
+.globl sym_2_4679
+sym_2_4679: la $2, sym_2_4679
+.globl sym_2_4680
+sym_2_4680: la $2, sym_2_4680
+.globl sym_2_4681
+sym_2_4681: la $2, sym_2_4681
+.globl sym_2_4682
+sym_2_4682: la $2, sym_2_4682
+.globl sym_2_4683
+sym_2_4683: la $2, sym_2_4683
+.globl sym_2_4684
+sym_2_4684: la $2, sym_2_4684
+.globl sym_2_4685
+sym_2_4685: la $2, sym_2_4685
+.globl sym_2_4686
+sym_2_4686: la $2, sym_2_4686
+.globl sym_2_4687
+sym_2_4687: la $2, sym_2_4687
+.globl sym_2_4688
+sym_2_4688: la $2, sym_2_4688
+.globl sym_2_4689
+sym_2_4689: la $2, sym_2_4689
+.globl sym_2_4690
+sym_2_4690: la $2, sym_2_4690
+.globl sym_2_4691
+sym_2_4691: la $2, sym_2_4691
+.globl sym_2_4692
+sym_2_4692: la $2, sym_2_4692
+.globl sym_2_4693
+sym_2_4693: la $2, sym_2_4693
+.globl sym_2_4694
+sym_2_4694: la $2, sym_2_4694
+.globl sym_2_4695
+sym_2_4695: la $2, sym_2_4695
+.globl sym_2_4696
+sym_2_4696: la $2, sym_2_4696
+.globl sym_2_4697
+sym_2_4697: la $2, sym_2_4697
+.globl sym_2_4698
+sym_2_4698: la $2, sym_2_4698
+.globl sym_2_4699
+sym_2_4699: la $2, sym_2_4699
+.globl sym_2_4700
+sym_2_4700: la $2, sym_2_4700
+.globl sym_2_4701
+sym_2_4701: la $2, sym_2_4701
+.globl sym_2_4702
+sym_2_4702: la $2, sym_2_4702
+.globl sym_2_4703
+sym_2_4703: la $2, sym_2_4703
+.globl sym_2_4704
+sym_2_4704: la $2, sym_2_4704
+.globl sym_2_4705
+sym_2_4705: la $2, sym_2_4705
+.globl sym_2_4706
+sym_2_4706: la $2, sym_2_4706
+.globl sym_2_4707
+sym_2_4707: la $2, sym_2_4707
+.globl sym_2_4708
+sym_2_4708: la $2, sym_2_4708
+.globl sym_2_4709
+sym_2_4709: la $2, sym_2_4709
+.globl sym_2_4710
+sym_2_4710: la $2, sym_2_4710
+.globl sym_2_4711
+sym_2_4711: la $2, sym_2_4711
+.globl sym_2_4712
+sym_2_4712: la $2, sym_2_4712
+.globl sym_2_4713
+sym_2_4713: la $2, sym_2_4713
+.globl sym_2_4714
+sym_2_4714: la $2, sym_2_4714
+.globl sym_2_4715
+sym_2_4715: la $2, sym_2_4715
+.globl sym_2_4716
+sym_2_4716: la $2, sym_2_4716
+.globl sym_2_4717
+sym_2_4717: la $2, sym_2_4717
+.globl sym_2_4718
+sym_2_4718: la $2, sym_2_4718
+.globl sym_2_4719
+sym_2_4719: la $2, sym_2_4719
+.globl sym_2_4720
+sym_2_4720: la $2, sym_2_4720
+.globl sym_2_4721
+sym_2_4721: la $2, sym_2_4721
+.globl sym_2_4722
+sym_2_4722: la $2, sym_2_4722
+.globl sym_2_4723
+sym_2_4723: la $2, sym_2_4723
+.globl sym_2_4724
+sym_2_4724: la $2, sym_2_4724
+.globl sym_2_4725
+sym_2_4725: la $2, sym_2_4725
+.globl sym_2_4726
+sym_2_4726: la $2, sym_2_4726
+.globl sym_2_4727
+sym_2_4727: la $2, sym_2_4727
+.globl sym_2_4728
+sym_2_4728: la $2, sym_2_4728
+.globl sym_2_4729
+sym_2_4729: la $2, sym_2_4729
+.globl sym_2_4730
+sym_2_4730: la $2, sym_2_4730
+.globl sym_2_4731
+sym_2_4731: la $2, sym_2_4731
+.globl sym_2_4732
+sym_2_4732: la $2, sym_2_4732
+.globl sym_2_4733
+sym_2_4733: la $2, sym_2_4733
+.globl sym_2_4734
+sym_2_4734: la $2, sym_2_4734
+.globl sym_2_4735
+sym_2_4735: la $2, sym_2_4735
+.globl sym_2_4736
+sym_2_4736: la $2, sym_2_4736
+.globl sym_2_4737
+sym_2_4737: la $2, sym_2_4737
+.globl sym_2_4738
+sym_2_4738: la $2, sym_2_4738
+.globl sym_2_4739
+sym_2_4739: la $2, sym_2_4739
+.globl sym_2_4740
+sym_2_4740: la $2, sym_2_4740
+.globl sym_2_4741
+sym_2_4741: la $2, sym_2_4741
+.globl sym_2_4742
+sym_2_4742: la $2, sym_2_4742
+.globl sym_2_4743
+sym_2_4743: la $2, sym_2_4743
+.globl sym_2_4744
+sym_2_4744: la $2, sym_2_4744
+.globl sym_2_4745
+sym_2_4745: la $2, sym_2_4745
+.globl sym_2_4746
+sym_2_4746: la $2, sym_2_4746
+.globl sym_2_4747
+sym_2_4747: la $2, sym_2_4747
+.globl sym_2_4748
+sym_2_4748: la $2, sym_2_4748
+.globl sym_2_4749
+sym_2_4749: la $2, sym_2_4749
+.globl sym_2_4750
+sym_2_4750: la $2, sym_2_4750
+.globl sym_2_4751
+sym_2_4751: la $2, sym_2_4751
+.globl sym_2_4752
+sym_2_4752: la $2, sym_2_4752
+.globl sym_2_4753
+sym_2_4753: la $2, sym_2_4753
+.globl sym_2_4754
+sym_2_4754: la $2, sym_2_4754
+.globl sym_2_4755
+sym_2_4755: la $2, sym_2_4755
+.globl sym_2_4756
+sym_2_4756: la $2, sym_2_4756
+.globl sym_2_4757
+sym_2_4757: la $2, sym_2_4757
+.globl sym_2_4758
+sym_2_4758: la $2, sym_2_4758
+.globl sym_2_4759
+sym_2_4759: la $2, sym_2_4759
+.globl sym_2_4760
+sym_2_4760: la $2, sym_2_4760
+.globl sym_2_4761
+sym_2_4761: la $2, sym_2_4761
+.globl sym_2_4762
+sym_2_4762: la $2, sym_2_4762
+.globl sym_2_4763
+sym_2_4763: la $2, sym_2_4763
+.globl sym_2_4764
+sym_2_4764: la $2, sym_2_4764
+.globl sym_2_4765
+sym_2_4765: la $2, sym_2_4765
+.globl sym_2_4766
+sym_2_4766: la $2, sym_2_4766
+.globl sym_2_4767
+sym_2_4767: la $2, sym_2_4767
+.globl sym_2_4768
+sym_2_4768: la $2, sym_2_4768
+.globl sym_2_4769
+sym_2_4769: la $2, sym_2_4769
+.globl sym_2_4770
+sym_2_4770: la $2, sym_2_4770
+.globl sym_2_4771
+sym_2_4771: la $2, sym_2_4771
+.globl sym_2_4772
+sym_2_4772: la $2, sym_2_4772
+.globl sym_2_4773
+sym_2_4773: la $2, sym_2_4773
+.globl sym_2_4774
+sym_2_4774: la $2, sym_2_4774
+.globl sym_2_4775
+sym_2_4775: la $2, sym_2_4775
+.globl sym_2_4776
+sym_2_4776: la $2, sym_2_4776
+.globl sym_2_4777
+sym_2_4777: la $2, sym_2_4777
+.globl sym_2_4778
+sym_2_4778: la $2, sym_2_4778
+.globl sym_2_4779
+sym_2_4779: la $2, sym_2_4779
+.globl sym_2_4780
+sym_2_4780: la $2, sym_2_4780
+.globl sym_2_4781
+sym_2_4781: la $2, sym_2_4781
+.globl sym_2_4782
+sym_2_4782: la $2, sym_2_4782
+.globl sym_2_4783
+sym_2_4783: la $2, sym_2_4783
+.globl sym_2_4784
+sym_2_4784: la $2, sym_2_4784
+.globl sym_2_4785
+sym_2_4785: la $2, sym_2_4785
+.globl sym_2_4786
+sym_2_4786: la $2, sym_2_4786
+.globl sym_2_4787
+sym_2_4787: la $2, sym_2_4787
+.globl sym_2_4788
+sym_2_4788: la $2, sym_2_4788
+.globl sym_2_4789
+sym_2_4789: la $2, sym_2_4789
+.globl sym_2_4790
+sym_2_4790: la $2, sym_2_4790
+.globl sym_2_4791
+sym_2_4791: la $2, sym_2_4791
+.globl sym_2_4792
+sym_2_4792: la $2, sym_2_4792
+.globl sym_2_4793
+sym_2_4793: la $2, sym_2_4793
+.globl sym_2_4794
+sym_2_4794: la $2, sym_2_4794
+.globl sym_2_4795
+sym_2_4795: la $2, sym_2_4795
+.globl sym_2_4796
+sym_2_4796: la $2, sym_2_4796
+.globl sym_2_4797
+sym_2_4797: la $2, sym_2_4797
+.globl sym_2_4798
+sym_2_4798: la $2, sym_2_4798
+.globl sym_2_4799
+sym_2_4799: la $2, sym_2_4799
+.globl sym_2_4800
+sym_2_4800: la $2, sym_2_4800
+.globl sym_2_4801
+sym_2_4801: la $2, sym_2_4801
+.globl sym_2_4802
+sym_2_4802: la $2, sym_2_4802
+.globl sym_2_4803
+sym_2_4803: la $2, sym_2_4803
+.globl sym_2_4804
+sym_2_4804: la $2, sym_2_4804
+.globl sym_2_4805
+sym_2_4805: la $2, sym_2_4805
+.globl sym_2_4806
+sym_2_4806: la $2, sym_2_4806
+.globl sym_2_4807
+sym_2_4807: la $2, sym_2_4807
+.globl sym_2_4808
+sym_2_4808: la $2, sym_2_4808
+.globl sym_2_4809
+sym_2_4809: la $2, sym_2_4809
+.globl sym_2_4810
+sym_2_4810: la $2, sym_2_4810
+.globl sym_2_4811
+sym_2_4811: la $2, sym_2_4811
+.globl sym_2_4812
+sym_2_4812: la $2, sym_2_4812
+.globl sym_2_4813
+sym_2_4813: la $2, sym_2_4813
+.globl sym_2_4814
+sym_2_4814: la $2, sym_2_4814
+.globl sym_2_4815
+sym_2_4815: la $2, sym_2_4815
+.globl sym_2_4816
+sym_2_4816: la $2, sym_2_4816
+.globl sym_2_4817
+sym_2_4817: la $2, sym_2_4817
+.globl sym_2_4818
+sym_2_4818: la $2, sym_2_4818
+.globl sym_2_4819
+sym_2_4819: la $2, sym_2_4819
+.globl sym_2_4820
+sym_2_4820: la $2, sym_2_4820
+.globl sym_2_4821
+sym_2_4821: la $2, sym_2_4821
+.globl sym_2_4822
+sym_2_4822: la $2, sym_2_4822
+.globl sym_2_4823
+sym_2_4823: la $2, sym_2_4823
+.globl sym_2_4824
+sym_2_4824: la $2, sym_2_4824
+.globl sym_2_4825
+sym_2_4825: la $2, sym_2_4825
+.globl sym_2_4826
+sym_2_4826: la $2, sym_2_4826
+.globl sym_2_4827
+sym_2_4827: la $2, sym_2_4827
+.globl sym_2_4828
+sym_2_4828: la $2, sym_2_4828
+.globl sym_2_4829
+sym_2_4829: la $2, sym_2_4829
+.globl sym_2_4830
+sym_2_4830: la $2, sym_2_4830
+.globl sym_2_4831
+sym_2_4831: la $2, sym_2_4831
+.globl sym_2_4832
+sym_2_4832: la $2, sym_2_4832
+.globl sym_2_4833
+sym_2_4833: la $2, sym_2_4833
+.globl sym_2_4834
+sym_2_4834: la $2, sym_2_4834
+.globl sym_2_4835
+sym_2_4835: la $2, sym_2_4835
+.globl sym_2_4836
+sym_2_4836: la $2, sym_2_4836
+.globl sym_2_4837
+sym_2_4837: la $2, sym_2_4837
+.globl sym_2_4838
+sym_2_4838: la $2, sym_2_4838
+.globl sym_2_4839
+sym_2_4839: la $2, sym_2_4839
+.globl sym_2_4840
+sym_2_4840: la $2, sym_2_4840
+.globl sym_2_4841
+sym_2_4841: la $2, sym_2_4841
+.globl sym_2_4842
+sym_2_4842: la $2, sym_2_4842
+.globl sym_2_4843
+sym_2_4843: la $2, sym_2_4843
+.globl sym_2_4844
+sym_2_4844: la $2, sym_2_4844
+.globl sym_2_4845
+sym_2_4845: la $2, sym_2_4845
+.globl sym_2_4846
+sym_2_4846: la $2, sym_2_4846
+.globl sym_2_4847
+sym_2_4847: la $2, sym_2_4847
+.globl sym_2_4848
+sym_2_4848: la $2, sym_2_4848
+.globl sym_2_4849
+sym_2_4849: la $2, sym_2_4849
+.globl sym_2_4850
+sym_2_4850: la $2, sym_2_4850
+.globl sym_2_4851
+sym_2_4851: la $2, sym_2_4851
+.globl sym_2_4852
+sym_2_4852: la $2, sym_2_4852
+.globl sym_2_4853
+sym_2_4853: la $2, sym_2_4853
+.globl sym_2_4854
+sym_2_4854: la $2, sym_2_4854
+.globl sym_2_4855
+sym_2_4855: la $2, sym_2_4855
+.globl sym_2_4856
+sym_2_4856: la $2, sym_2_4856
+.globl sym_2_4857
+sym_2_4857: la $2, sym_2_4857
+.globl sym_2_4858
+sym_2_4858: la $2, sym_2_4858
+.globl sym_2_4859
+sym_2_4859: la $2, sym_2_4859
+.globl sym_2_4860
+sym_2_4860: la $2, sym_2_4860
+.globl sym_2_4861
+sym_2_4861: la $2, sym_2_4861
+.globl sym_2_4862
+sym_2_4862: la $2, sym_2_4862
+.globl sym_2_4863
+sym_2_4863: la $2, sym_2_4863
+.globl sym_2_4864
+sym_2_4864: la $2, sym_2_4864
+.globl sym_2_4865
+sym_2_4865: la $2, sym_2_4865
+.globl sym_2_4866
+sym_2_4866: la $2, sym_2_4866
+.globl sym_2_4867
+sym_2_4867: la $2, sym_2_4867
+.globl sym_2_4868
+sym_2_4868: la $2, sym_2_4868
+.globl sym_2_4869
+sym_2_4869: la $2, sym_2_4869
+.globl sym_2_4870
+sym_2_4870: la $2, sym_2_4870
+.globl sym_2_4871
+sym_2_4871: la $2, sym_2_4871
+.globl sym_2_4872
+sym_2_4872: la $2, sym_2_4872
+.globl sym_2_4873
+sym_2_4873: la $2, sym_2_4873
+.globl sym_2_4874
+sym_2_4874: la $2, sym_2_4874
+.globl sym_2_4875
+sym_2_4875: la $2, sym_2_4875
+.globl sym_2_4876
+sym_2_4876: la $2, sym_2_4876
+.globl sym_2_4877
+sym_2_4877: la $2, sym_2_4877
+.globl sym_2_4878
+sym_2_4878: la $2, sym_2_4878
+.globl sym_2_4879
+sym_2_4879: la $2, sym_2_4879
+.globl sym_2_4880
+sym_2_4880: la $2, sym_2_4880
+.globl sym_2_4881
+sym_2_4881: la $2, sym_2_4881
+.globl sym_2_4882
+sym_2_4882: la $2, sym_2_4882
+.globl sym_2_4883
+sym_2_4883: la $2, sym_2_4883
+.globl sym_2_4884
+sym_2_4884: la $2, sym_2_4884
+.globl sym_2_4885
+sym_2_4885: la $2, sym_2_4885
+.globl sym_2_4886
+sym_2_4886: la $2, sym_2_4886
+.globl sym_2_4887
+sym_2_4887: la $2, sym_2_4887
+.globl sym_2_4888
+sym_2_4888: la $2, sym_2_4888
+.globl sym_2_4889
+sym_2_4889: la $2, sym_2_4889
+.globl sym_2_4890
+sym_2_4890: la $2, sym_2_4890
+.globl sym_2_4891
+sym_2_4891: la $2, sym_2_4891
+.globl sym_2_4892
+sym_2_4892: la $2, sym_2_4892
+.globl sym_2_4893
+sym_2_4893: la $2, sym_2_4893
+.globl sym_2_4894
+sym_2_4894: la $2, sym_2_4894
+.globl sym_2_4895
+sym_2_4895: la $2, sym_2_4895
+.globl sym_2_4896
+sym_2_4896: la $2, sym_2_4896
+.globl sym_2_4897
+sym_2_4897: la $2, sym_2_4897
+.globl sym_2_4898
+sym_2_4898: la $2, sym_2_4898
+.globl sym_2_4899
+sym_2_4899: la $2, sym_2_4899
+.globl sym_2_4900
+sym_2_4900: la $2, sym_2_4900
+.globl sym_2_4901
+sym_2_4901: la $2, sym_2_4901
+.globl sym_2_4902
+sym_2_4902: la $2, sym_2_4902
+.globl sym_2_4903
+sym_2_4903: la $2, sym_2_4903
+.globl sym_2_4904
+sym_2_4904: la $2, sym_2_4904
+.globl sym_2_4905
+sym_2_4905: la $2, sym_2_4905
+.globl sym_2_4906
+sym_2_4906: la $2, sym_2_4906
+.globl sym_2_4907
+sym_2_4907: la $2, sym_2_4907
+.globl sym_2_4908
+sym_2_4908: la $2, sym_2_4908
+.globl sym_2_4909
+sym_2_4909: la $2, sym_2_4909
+.globl sym_2_4910
+sym_2_4910: la $2, sym_2_4910
+.globl sym_2_4911
+sym_2_4911: la $2, sym_2_4911
+.globl sym_2_4912
+sym_2_4912: la $2, sym_2_4912
+.globl sym_2_4913
+sym_2_4913: la $2, sym_2_4913
+.globl sym_2_4914
+sym_2_4914: la $2, sym_2_4914
+.globl sym_2_4915
+sym_2_4915: la $2, sym_2_4915
+.globl sym_2_4916
+sym_2_4916: la $2, sym_2_4916
+.globl sym_2_4917
+sym_2_4917: la $2, sym_2_4917
+.globl sym_2_4918
+sym_2_4918: la $2, sym_2_4918
+.globl sym_2_4919
+sym_2_4919: la $2, sym_2_4919
+.globl sym_2_4920
+sym_2_4920: la $2, sym_2_4920
+.globl sym_2_4921
+sym_2_4921: la $2, sym_2_4921
+.globl sym_2_4922
+sym_2_4922: la $2, sym_2_4922
+.globl sym_2_4923
+sym_2_4923: la $2, sym_2_4923
+.globl sym_2_4924
+sym_2_4924: la $2, sym_2_4924
+.globl sym_2_4925
+sym_2_4925: la $2, sym_2_4925
+.globl sym_2_4926
+sym_2_4926: la $2, sym_2_4926
+.globl sym_2_4927
+sym_2_4927: la $2, sym_2_4927
+.globl sym_2_4928
+sym_2_4928: la $2, sym_2_4928
+.globl sym_2_4929
+sym_2_4929: la $2, sym_2_4929
+.globl sym_2_4930
+sym_2_4930: la $2, sym_2_4930
+.globl sym_2_4931
+sym_2_4931: la $2, sym_2_4931
+.globl sym_2_4932
+sym_2_4932: la $2, sym_2_4932
+.globl sym_2_4933
+sym_2_4933: la $2, sym_2_4933
+.globl sym_2_4934
+sym_2_4934: la $2, sym_2_4934
+.globl sym_2_4935
+sym_2_4935: la $2, sym_2_4935
+.globl sym_2_4936
+sym_2_4936: la $2, sym_2_4936
+.globl sym_2_4937
+sym_2_4937: la $2, sym_2_4937
+.globl sym_2_4938
+sym_2_4938: la $2, sym_2_4938
+.globl sym_2_4939
+sym_2_4939: la $2, sym_2_4939
+.globl sym_2_4940
+sym_2_4940: la $2, sym_2_4940
+.globl sym_2_4941
+sym_2_4941: la $2, sym_2_4941
+.globl sym_2_4942
+sym_2_4942: la $2, sym_2_4942
+.globl sym_2_4943
+sym_2_4943: la $2, sym_2_4943
+.globl sym_2_4944
+sym_2_4944: la $2, sym_2_4944
+.globl sym_2_4945
+sym_2_4945: la $2, sym_2_4945
+.globl sym_2_4946
+sym_2_4946: la $2, sym_2_4946
+.globl sym_2_4947
+sym_2_4947: la $2, sym_2_4947
+.globl sym_2_4948
+sym_2_4948: la $2, sym_2_4948
+.globl sym_2_4949
+sym_2_4949: la $2, sym_2_4949
+.globl sym_2_4950
+sym_2_4950: la $2, sym_2_4950
+.globl sym_2_4951
+sym_2_4951: la $2, sym_2_4951
+.globl sym_2_4952
+sym_2_4952: la $2, sym_2_4952
+.globl sym_2_4953
+sym_2_4953: la $2, sym_2_4953
+.globl sym_2_4954
+sym_2_4954: la $2, sym_2_4954
+.globl sym_2_4955
+sym_2_4955: la $2, sym_2_4955
+.globl sym_2_4956
+sym_2_4956: la $2, sym_2_4956
+.globl sym_2_4957
+sym_2_4957: la $2, sym_2_4957
+.globl sym_2_4958
+sym_2_4958: la $2, sym_2_4958
+.globl sym_2_4959
+sym_2_4959: la $2, sym_2_4959
+.globl sym_2_4960
+sym_2_4960: la $2, sym_2_4960
+.globl sym_2_4961
+sym_2_4961: la $2, sym_2_4961
+.globl sym_2_4962
+sym_2_4962: la $2, sym_2_4962
+.globl sym_2_4963
+sym_2_4963: la $2, sym_2_4963
+.globl sym_2_4964
+sym_2_4964: la $2, sym_2_4964
+.globl sym_2_4965
+sym_2_4965: la $2, sym_2_4965
+.globl sym_2_4966
+sym_2_4966: la $2, sym_2_4966
+.globl sym_2_4967
+sym_2_4967: la $2, sym_2_4967
+.globl sym_2_4968
+sym_2_4968: la $2, sym_2_4968
+.globl sym_2_4969
+sym_2_4969: la $2, sym_2_4969
+.globl sym_2_4970
+sym_2_4970: la $2, sym_2_4970
+.globl sym_2_4971
+sym_2_4971: la $2, sym_2_4971
+.globl sym_2_4972
+sym_2_4972: la $2, sym_2_4972
+.globl sym_2_4973
+sym_2_4973: la $2, sym_2_4973
+.globl sym_2_4974
+sym_2_4974: la $2, sym_2_4974
+.globl sym_2_4975
+sym_2_4975: la $2, sym_2_4975
+.globl sym_2_4976
+sym_2_4976: la $2, sym_2_4976
+.globl sym_2_4977
+sym_2_4977: la $2, sym_2_4977
+.globl sym_2_4978
+sym_2_4978: la $2, sym_2_4978
+.globl sym_2_4979
+sym_2_4979: la $2, sym_2_4979
+.globl sym_2_4980
+sym_2_4980: la $2, sym_2_4980
+.globl sym_2_4981
+sym_2_4981: la $2, sym_2_4981
+.globl sym_2_4982
+sym_2_4982: la $2, sym_2_4982
+.globl sym_2_4983
+sym_2_4983: la $2, sym_2_4983
+.globl sym_2_4984
+sym_2_4984: la $2, sym_2_4984
+.globl sym_2_4985
+sym_2_4985: la $2, sym_2_4985
+.globl sym_2_4986
+sym_2_4986: la $2, sym_2_4986
+.globl sym_2_4987
+sym_2_4987: la $2, sym_2_4987
+.globl sym_2_4988
+sym_2_4988: la $2, sym_2_4988
+.globl sym_2_4989
+sym_2_4989: la $2, sym_2_4989
+.globl sym_2_4990
+sym_2_4990: la $2, sym_2_4990
+.globl sym_2_4991
+sym_2_4991: la $2, sym_2_4991
+.globl sym_2_4992
+sym_2_4992: la $2, sym_2_4992
+.globl sym_2_4993
+sym_2_4993: la $2, sym_2_4993
+.globl sym_2_4994
+sym_2_4994: la $2, sym_2_4994
+.globl sym_2_4995
+sym_2_4995: la $2, sym_2_4995
+.globl sym_2_4996
+sym_2_4996: la $2, sym_2_4996
+.globl sym_2_4997
+sym_2_4997: la $2, sym_2_4997
+.globl sym_2_4998
+sym_2_4998: la $2, sym_2_4998
+.globl sym_2_4999
+sym_2_4999: la $2, sym_2_4999
+.globl sym_2_5000
+sym_2_5000: la $2, sym_2_5000
+.globl sym_2_5001
+sym_2_5001: la $2, sym_2_5001
+.globl sym_2_5002
+sym_2_5002: la $2, sym_2_5002
+.globl sym_2_5003
+sym_2_5003: la $2, sym_2_5003
+.globl sym_2_5004
+sym_2_5004: la $2, sym_2_5004
+.globl sym_2_5005
+sym_2_5005: la $2, sym_2_5005
+.globl sym_2_5006
+sym_2_5006: la $2, sym_2_5006
+.globl sym_2_5007
+sym_2_5007: la $2, sym_2_5007
+.globl sym_2_5008
+sym_2_5008: la $2, sym_2_5008
+.globl sym_2_5009
+sym_2_5009: la $2, sym_2_5009
+.globl sym_2_5010
+sym_2_5010: la $2, sym_2_5010
+.globl sym_2_5011
+sym_2_5011: la $2, sym_2_5011
+.globl sym_2_5012
+sym_2_5012: la $2, sym_2_5012
+.globl sym_2_5013
+sym_2_5013: la $2, sym_2_5013
+.globl sym_2_5014
+sym_2_5014: la $2, sym_2_5014
+.globl sym_2_5015
+sym_2_5015: la $2, sym_2_5015
+.globl sym_2_5016
+sym_2_5016: la $2, sym_2_5016
+.globl sym_2_5017
+sym_2_5017: la $2, sym_2_5017
+.globl sym_2_5018
+sym_2_5018: la $2, sym_2_5018
+.globl sym_2_5019
+sym_2_5019: la $2, sym_2_5019
+.globl sym_2_5020
+sym_2_5020: la $2, sym_2_5020
+.globl sym_2_5021
+sym_2_5021: la $2, sym_2_5021
+.globl sym_2_5022
+sym_2_5022: la $2, sym_2_5022
+.globl sym_2_5023
+sym_2_5023: la $2, sym_2_5023
+.globl sym_2_5024
+sym_2_5024: la $2, sym_2_5024
+.globl sym_2_5025
+sym_2_5025: la $2, sym_2_5025
+.globl sym_2_5026
+sym_2_5026: la $2, sym_2_5026
+.globl sym_2_5027
+sym_2_5027: la $2, sym_2_5027
+.globl sym_2_5028
+sym_2_5028: la $2, sym_2_5028
+.globl sym_2_5029
+sym_2_5029: la $2, sym_2_5029
+.globl sym_2_5030
+sym_2_5030: la $2, sym_2_5030
+.globl sym_2_5031
+sym_2_5031: la $2, sym_2_5031
+.globl sym_2_5032
+sym_2_5032: la $2, sym_2_5032
+.globl sym_2_5033
+sym_2_5033: la $2, sym_2_5033
+.globl sym_2_5034
+sym_2_5034: la $2, sym_2_5034
+.globl sym_2_5035
+sym_2_5035: la $2, sym_2_5035
+.globl sym_2_5036
+sym_2_5036: la $2, sym_2_5036
+.globl sym_2_5037
+sym_2_5037: la $2, sym_2_5037
+.globl sym_2_5038
+sym_2_5038: la $2, sym_2_5038
+.globl sym_2_5039
+sym_2_5039: la $2, sym_2_5039
+.globl sym_2_5040
+sym_2_5040: la $2, sym_2_5040
+.globl sym_2_5041
+sym_2_5041: la $2, sym_2_5041
+.globl sym_2_5042
+sym_2_5042: la $2, sym_2_5042
+.globl sym_2_5043
+sym_2_5043: la $2, sym_2_5043
+.globl sym_2_5044
+sym_2_5044: la $2, sym_2_5044
+.globl sym_2_5045
+sym_2_5045: la $2, sym_2_5045
+.globl sym_2_5046
+sym_2_5046: la $2, sym_2_5046
+.globl sym_2_5047
+sym_2_5047: la $2, sym_2_5047
+.globl sym_2_5048
+sym_2_5048: la $2, sym_2_5048
+.globl sym_2_5049
+sym_2_5049: la $2, sym_2_5049
+.globl sym_2_5050
+sym_2_5050: la $2, sym_2_5050
+.globl sym_2_5051
+sym_2_5051: la $2, sym_2_5051
+.globl sym_2_5052
+sym_2_5052: la $2, sym_2_5052
+.globl sym_2_5053
+sym_2_5053: la $2, sym_2_5053
+.globl sym_2_5054
+sym_2_5054: la $2, sym_2_5054
+.globl sym_2_5055
+sym_2_5055: la $2, sym_2_5055
+.globl sym_2_5056
+sym_2_5056: la $2, sym_2_5056
+.globl sym_2_5057
+sym_2_5057: la $2, sym_2_5057
+.globl sym_2_5058
+sym_2_5058: la $2, sym_2_5058
+.globl sym_2_5059
+sym_2_5059: la $2, sym_2_5059
+.globl sym_2_5060
+sym_2_5060: la $2, sym_2_5060
+.globl sym_2_5061
+sym_2_5061: la $2, sym_2_5061
+.globl sym_2_5062
+sym_2_5062: la $2, sym_2_5062
+.globl sym_2_5063
+sym_2_5063: la $2, sym_2_5063
+.globl sym_2_5064
+sym_2_5064: la $2, sym_2_5064
+.globl sym_2_5065
+sym_2_5065: la $2, sym_2_5065
+.globl sym_2_5066
+sym_2_5066: la $2, sym_2_5066
+.globl sym_2_5067
+sym_2_5067: la $2, sym_2_5067
+.globl sym_2_5068
+sym_2_5068: la $2, sym_2_5068
+.globl sym_2_5069
+sym_2_5069: la $2, sym_2_5069
+.globl sym_2_5070
+sym_2_5070: la $2, sym_2_5070
+.globl sym_2_5071
+sym_2_5071: la $2, sym_2_5071
+.globl sym_2_5072
+sym_2_5072: la $2, sym_2_5072
+.globl sym_2_5073
+sym_2_5073: la $2, sym_2_5073
+.globl sym_2_5074
+sym_2_5074: la $2, sym_2_5074
+.globl sym_2_5075
+sym_2_5075: la $2, sym_2_5075
+.globl sym_2_5076
+sym_2_5076: la $2, sym_2_5076
+.globl sym_2_5077
+sym_2_5077: la $2, sym_2_5077
+.globl sym_2_5078
+sym_2_5078: la $2, sym_2_5078
+.globl sym_2_5079
+sym_2_5079: la $2, sym_2_5079
+.globl sym_2_5080
+sym_2_5080: la $2, sym_2_5080
+.globl sym_2_5081
+sym_2_5081: la $2, sym_2_5081
+.globl sym_2_5082
+sym_2_5082: la $2, sym_2_5082
+.globl sym_2_5083
+sym_2_5083: la $2, sym_2_5083
+.globl sym_2_5084
+sym_2_5084: la $2, sym_2_5084
+.globl sym_2_5085
+sym_2_5085: la $2, sym_2_5085
+.globl sym_2_5086
+sym_2_5086: la $2, sym_2_5086
+.globl sym_2_5087
+sym_2_5087: la $2, sym_2_5087
+.globl sym_2_5088
+sym_2_5088: la $2, sym_2_5088
+.globl sym_2_5089
+sym_2_5089: la $2, sym_2_5089
+.globl sym_2_5090
+sym_2_5090: la $2, sym_2_5090
+.globl sym_2_5091
+sym_2_5091: la $2, sym_2_5091
+.globl sym_2_5092
+sym_2_5092: la $2, sym_2_5092
+.globl sym_2_5093
+sym_2_5093: la $2, sym_2_5093
+.globl sym_2_5094
+sym_2_5094: la $2, sym_2_5094
+.globl sym_2_5095
+sym_2_5095: la $2, sym_2_5095
+.globl sym_2_5096
+sym_2_5096: la $2, sym_2_5096
+.globl sym_2_5097
+sym_2_5097: la $2, sym_2_5097
+.globl sym_2_5098
+sym_2_5098: la $2, sym_2_5098
+.globl sym_2_5099
+sym_2_5099: la $2, sym_2_5099
+.globl sym_2_5100
+sym_2_5100: la $2, sym_2_5100
+.globl sym_2_5101
+sym_2_5101: la $2, sym_2_5101
+.globl sym_2_5102
+sym_2_5102: la $2, sym_2_5102
+.globl sym_2_5103
+sym_2_5103: la $2, sym_2_5103
+.globl sym_2_5104
+sym_2_5104: la $2, sym_2_5104
+.globl sym_2_5105
+sym_2_5105: la $2, sym_2_5105
+.globl sym_2_5106
+sym_2_5106: la $2, sym_2_5106
+.globl sym_2_5107
+sym_2_5107: la $2, sym_2_5107
+.globl sym_2_5108
+sym_2_5108: la $2, sym_2_5108
+.globl sym_2_5109
+sym_2_5109: la $2, sym_2_5109
+.globl sym_2_5110
+sym_2_5110: la $2, sym_2_5110
+.globl sym_2_5111
+sym_2_5111: la $2, sym_2_5111
+.globl sym_2_5112
+sym_2_5112: la $2, sym_2_5112
+.globl sym_2_5113
+sym_2_5113: la $2, sym_2_5113
+.globl sym_2_5114
+sym_2_5114: la $2, sym_2_5114
+.globl sym_2_5115
+sym_2_5115: la $2, sym_2_5115
+.globl sym_2_5116
+sym_2_5116: la $2, sym_2_5116
+.globl sym_2_5117
+sym_2_5117: la $2, sym_2_5117
+.globl sym_2_5118
+sym_2_5118: la $2, sym_2_5118
+.globl sym_2_5119
+sym_2_5119: la $2, sym_2_5119
+.globl sym_2_5120
+sym_2_5120: la $2, sym_2_5120
+.globl sym_2_5121
+sym_2_5121: la $2, sym_2_5121
+.globl sym_2_5122
+sym_2_5122: la $2, sym_2_5122
+.globl sym_2_5123
+sym_2_5123: la $2, sym_2_5123
+.globl sym_2_5124
+sym_2_5124: la $2, sym_2_5124
+.globl sym_2_5125
+sym_2_5125: la $2, sym_2_5125
+.globl sym_2_5126
+sym_2_5126: la $2, sym_2_5126
+.globl sym_2_5127
+sym_2_5127: la $2, sym_2_5127
+.globl sym_2_5128
+sym_2_5128: la $2, sym_2_5128
+.globl sym_2_5129
+sym_2_5129: la $2, sym_2_5129
+.globl sym_2_5130
+sym_2_5130: la $2, sym_2_5130
+.globl sym_2_5131
+sym_2_5131: la $2, sym_2_5131
+.globl sym_2_5132
+sym_2_5132: la $2, sym_2_5132
+.globl sym_2_5133
+sym_2_5133: la $2, sym_2_5133
+.globl sym_2_5134
+sym_2_5134: la $2, sym_2_5134
+.globl sym_2_5135
+sym_2_5135: la $2, sym_2_5135
+.globl sym_2_5136
+sym_2_5136: la $2, sym_2_5136
+.globl sym_2_5137
+sym_2_5137: la $2, sym_2_5137
+.globl sym_2_5138
+sym_2_5138: la $2, sym_2_5138
+.globl sym_2_5139
+sym_2_5139: la $2, sym_2_5139
+.globl sym_2_5140
+sym_2_5140: la $2, sym_2_5140
+.globl sym_2_5141
+sym_2_5141: la $2, sym_2_5141
+.globl sym_2_5142
+sym_2_5142: la $2, sym_2_5142
+.globl sym_2_5143
+sym_2_5143: la $2, sym_2_5143
+.globl sym_2_5144
+sym_2_5144: la $2, sym_2_5144
+.globl sym_2_5145
+sym_2_5145: la $2, sym_2_5145
+.globl sym_2_5146
+sym_2_5146: la $2, sym_2_5146
+.globl sym_2_5147
+sym_2_5147: la $2, sym_2_5147
+.globl sym_2_5148
+sym_2_5148: la $2, sym_2_5148
+.globl sym_2_5149
+sym_2_5149: la $2, sym_2_5149
+.globl sym_2_5150
+sym_2_5150: la $2, sym_2_5150
+.globl sym_2_5151
+sym_2_5151: la $2, sym_2_5151
+.globl sym_2_5152
+sym_2_5152: la $2, sym_2_5152
+.globl sym_2_5153
+sym_2_5153: la $2, sym_2_5153
+.globl sym_2_5154
+sym_2_5154: la $2, sym_2_5154
+.globl sym_2_5155
+sym_2_5155: la $2, sym_2_5155
+.globl sym_2_5156
+sym_2_5156: la $2, sym_2_5156
+.globl sym_2_5157
+sym_2_5157: la $2, sym_2_5157
+.globl sym_2_5158
+sym_2_5158: la $2, sym_2_5158
+.globl sym_2_5159
+sym_2_5159: la $2, sym_2_5159
+.globl sym_2_5160
+sym_2_5160: la $2, sym_2_5160
+.globl sym_2_5161
+sym_2_5161: la $2, sym_2_5161
+.globl sym_2_5162
+sym_2_5162: la $2, sym_2_5162
+.globl sym_2_5163
+sym_2_5163: la $2, sym_2_5163
+.globl sym_2_5164
+sym_2_5164: la $2, sym_2_5164
+.globl sym_2_5165
+sym_2_5165: la $2, sym_2_5165
+.globl sym_2_5166
+sym_2_5166: la $2, sym_2_5166
+.globl sym_2_5167
+sym_2_5167: la $2, sym_2_5167
+.globl sym_2_5168
+sym_2_5168: la $2, sym_2_5168
+.globl sym_2_5169
+sym_2_5169: la $2, sym_2_5169
+.globl sym_2_5170
+sym_2_5170: la $2, sym_2_5170
+.globl sym_2_5171
+sym_2_5171: la $2, sym_2_5171
+.globl sym_2_5172
+sym_2_5172: la $2, sym_2_5172
+.globl sym_2_5173
+sym_2_5173: la $2, sym_2_5173
+.globl sym_2_5174
+sym_2_5174: la $2, sym_2_5174
+.globl sym_2_5175
+sym_2_5175: la $2, sym_2_5175
+.globl sym_2_5176
+sym_2_5176: la $2, sym_2_5176
+.globl sym_2_5177
+sym_2_5177: la $2, sym_2_5177
+.globl sym_2_5178
+sym_2_5178: la $2, sym_2_5178
+.globl sym_2_5179
+sym_2_5179: la $2, sym_2_5179
+.globl sym_2_5180
+sym_2_5180: la $2, sym_2_5180
+.globl sym_2_5181
+sym_2_5181: la $2, sym_2_5181
+.globl sym_2_5182
+sym_2_5182: la $2, sym_2_5182
+.globl sym_2_5183
+sym_2_5183: la $2, sym_2_5183
+.globl sym_2_5184
+sym_2_5184: la $2, sym_2_5184
+.globl sym_2_5185
+sym_2_5185: la $2, sym_2_5185
+.globl sym_2_5186
+sym_2_5186: la $2, sym_2_5186
+.globl sym_2_5187
+sym_2_5187: la $2, sym_2_5187
+.globl sym_2_5188
+sym_2_5188: la $2, sym_2_5188
+.globl sym_2_5189
+sym_2_5189: la $2, sym_2_5189
+.globl sym_2_5190
+sym_2_5190: la $2, sym_2_5190
+.globl sym_2_5191
+sym_2_5191: la $2, sym_2_5191
+.globl sym_2_5192
+sym_2_5192: la $2, sym_2_5192
+.globl sym_2_5193
+sym_2_5193: la $2, sym_2_5193
+.globl sym_2_5194
+sym_2_5194: la $2, sym_2_5194
+.globl sym_2_5195
+sym_2_5195: la $2, sym_2_5195
+.globl sym_2_5196
+sym_2_5196: la $2, sym_2_5196
+.globl sym_2_5197
+sym_2_5197: la $2, sym_2_5197
+.globl sym_2_5198
+sym_2_5198: la $2, sym_2_5198
+.globl sym_2_5199
+sym_2_5199: la $2, sym_2_5199
+.globl sym_2_5200
+sym_2_5200: la $2, sym_2_5200
+.globl sym_2_5201
+sym_2_5201: la $2, sym_2_5201
+.globl sym_2_5202
+sym_2_5202: la $2, sym_2_5202
+.globl sym_2_5203
+sym_2_5203: la $2, sym_2_5203
+.globl sym_2_5204
+sym_2_5204: la $2, sym_2_5204
+.globl sym_2_5205
+sym_2_5205: la $2, sym_2_5205
+.globl sym_2_5206
+sym_2_5206: la $2, sym_2_5206
+.globl sym_2_5207
+sym_2_5207: la $2, sym_2_5207
+.globl sym_2_5208
+sym_2_5208: la $2, sym_2_5208
+.globl sym_2_5209
+sym_2_5209: la $2, sym_2_5209
+.globl sym_2_5210
+sym_2_5210: la $2, sym_2_5210
+.globl sym_2_5211
+sym_2_5211: la $2, sym_2_5211
+.globl sym_2_5212
+sym_2_5212: la $2, sym_2_5212
+.globl sym_2_5213
+sym_2_5213: la $2, sym_2_5213
+.globl sym_2_5214
+sym_2_5214: la $2, sym_2_5214
+.globl sym_2_5215
+sym_2_5215: la $2, sym_2_5215
+.globl sym_2_5216
+sym_2_5216: la $2, sym_2_5216
+.globl sym_2_5217
+sym_2_5217: la $2, sym_2_5217
+.globl sym_2_5218
+sym_2_5218: la $2, sym_2_5218
+.globl sym_2_5219
+sym_2_5219: la $2, sym_2_5219
+.globl sym_2_5220
+sym_2_5220: la $2, sym_2_5220
+.globl sym_2_5221
+sym_2_5221: la $2, sym_2_5221
+.globl sym_2_5222
+sym_2_5222: la $2, sym_2_5222
+.globl sym_2_5223
+sym_2_5223: la $2, sym_2_5223
+.globl sym_2_5224
+sym_2_5224: la $2, sym_2_5224
+.globl sym_2_5225
+sym_2_5225: la $2, sym_2_5225
+.globl sym_2_5226
+sym_2_5226: la $2, sym_2_5226
+.globl sym_2_5227
+sym_2_5227: la $2, sym_2_5227
+.globl sym_2_5228
+sym_2_5228: la $2, sym_2_5228
+.globl sym_2_5229
+sym_2_5229: la $2, sym_2_5229
+.globl sym_2_5230
+sym_2_5230: la $2, sym_2_5230
+.globl sym_2_5231
+sym_2_5231: la $2, sym_2_5231
+.globl sym_2_5232
+sym_2_5232: la $2, sym_2_5232
+.globl sym_2_5233
+sym_2_5233: la $2, sym_2_5233
+.globl sym_2_5234
+sym_2_5234: la $2, sym_2_5234
+.globl sym_2_5235
+sym_2_5235: la $2, sym_2_5235
+.globl sym_2_5236
+sym_2_5236: la $2, sym_2_5236
+.globl sym_2_5237
+sym_2_5237: la $2, sym_2_5237
+.globl sym_2_5238
+sym_2_5238: la $2, sym_2_5238
+.globl sym_2_5239
+sym_2_5239: la $2, sym_2_5239
+.globl sym_2_5240
+sym_2_5240: la $2, sym_2_5240
+.globl sym_2_5241
+sym_2_5241: la $2, sym_2_5241
+.globl sym_2_5242
+sym_2_5242: la $2, sym_2_5242
+.globl sym_2_5243
+sym_2_5243: la $2, sym_2_5243
+.globl sym_2_5244
+sym_2_5244: la $2, sym_2_5244
+.globl sym_2_5245
+sym_2_5245: la $2, sym_2_5245
+.globl sym_2_5246
+sym_2_5246: la $2, sym_2_5246
+.globl sym_2_5247
+sym_2_5247: la $2, sym_2_5247
+.globl sym_2_5248
+sym_2_5248: la $2, sym_2_5248
+.globl sym_2_5249
+sym_2_5249: la $2, sym_2_5249
+.globl sym_2_5250
+sym_2_5250: la $2, sym_2_5250
+.globl sym_2_5251
+sym_2_5251: la $2, sym_2_5251
+.globl sym_2_5252
+sym_2_5252: la $2, sym_2_5252
+.globl sym_2_5253
+sym_2_5253: la $2, sym_2_5253
+.globl sym_2_5254
+sym_2_5254: la $2, sym_2_5254
+.globl sym_2_5255
+sym_2_5255: la $2, sym_2_5255
+.globl sym_2_5256
+sym_2_5256: la $2, sym_2_5256
+.globl sym_2_5257
+sym_2_5257: la $2, sym_2_5257
+.globl sym_2_5258
+sym_2_5258: la $2, sym_2_5258
+.globl sym_2_5259
+sym_2_5259: la $2, sym_2_5259
+.globl sym_2_5260
+sym_2_5260: la $2, sym_2_5260
+.globl sym_2_5261
+sym_2_5261: la $2, sym_2_5261
+.globl sym_2_5262
+sym_2_5262: la $2, sym_2_5262
+.globl sym_2_5263
+sym_2_5263: la $2, sym_2_5263
+.globl sym_2_5264
+sym_2_5264: la $2, sym_2_5264
+.globl sym_2_5265
+sym_2_5265: la $2, sym_2_5265
+.globl sym_2_5266
+sym_2_5266: la $2, sym_2_5266
+.globl sym_2_5267
+sym_2_5267: la $2, sym_2_5267
+.globl sym_2_5268
+sym_2_5268: la $2, sym_2_5268
+.globl sym_2_5269
+sym_2_5269: la $2, sym_2_5269
+.globl sym_2_5270
+sym_2_5270: la $2, sym_2_5270
+.globl sym_2_5271
+sym_2_5271: la $2, sym_2_5271
+.globl sym_2_5272
+sym_2_5272: la $2, sym_2_5272
+.globl sym_2_5273
+sym_2_5273: la $2, sym_2_5273
+.globl sym_2_5274
+sym_2_5274: la $2, sym_2_5274
+.globl sym_2_5275
+sym_2_5275: la $2, sym_2_5275
+.globl sym_2_5276
+sym_2_5276: la $2, sym_2_5276
+.globl sym_2_5277
+sym_2_5277: la $2, sym_2_5277
+.globl sym_2_5278
+sym_2_5278: la $2, sym_2_5278
+.globl sym_2_5279
+sym_2_5279: la $2, sym_2_5279
+.globl sym_2_5280
+sym_2_5280: la $2, sym_2_5280
+.globl sym_2_5281
+sym_2_5281: la $2, sym_2_5281
+.globl sym_2_5282
+sym_2_5282: la $2, sym_2_5282
+.globl sym_2_5283
+sym_2_5283: la $2, sym_2_5283
+.globl sym_2_5284
+sym_2_5284: la $2, sym_2_5284
+.globl sym_2_5285
+sym_2_5285: la $2, sym_2_5285
+.globl sym_2_5286
+sym_2_5286: la $2, sym_2_5286
+.globl sym_2_5287
+sym_2_5287: la $2, sym_2_5287
+.globl sym_2_5288
+sym_2_5288: la $2, sym_2_5288
+.globl sym_2_5289
+sym_2_5289: la $2, sym_2_5289
+.globl sym_2_5290
+sym_2_5290: la $2, sym_2_5290
+.globl sym_2_5291
+sym_2_5291: la $2, sym_2_5291
+.globl sym_2_5292
+sym_2_5292: la $2, sym_2_5292
+.globl sym_2_5293
+sym_2_5293: la $2, sym_2_5293
+.globl sym_2_5294
+sym_2_5294: la $2, sym_2_5294
+.globl sym_2_5295
+sym_2_5295: la $2, sym_2_5295
+.globl sym_2_5296
+sym_2_5296: la $2, sym_2_5296
+.globl sym_2_5297
+sym_2_5297: la $2, sym_2_5297
+.globl sym_2_5298
+sym_2_5298: la $2, sym_2_5298
+.globl sym_2_5299
+sym_2_5299: la $2, sym_2_5299
+.globl sym_2_5300
+sym_2_5300: la $2, sym_2_5300
+.globl sym_2_5301
+sym_2_5301: la $2, sym_2_5301
+.globl sym_2_5302
+sym_2_5302: la $2, sym_2_5302
+.globl sym_2_5303
+sym_2_5303: la $2, sym_2_5303
+.globl sym_2_5304
+sym_2_5304: la $2, sym_2_5304
+.globl sym_2_5305
+sym_2_5305: la $2, sym_2_5305
+.globl sym_2_5306
+sym_2_5306: la $2, sym_2_5306
+.globl sym_2_5307
+sym_2_5307: la $2, sym_2_5307
+.globl sym_2_5308
+sym_2_5308: la $2, sym_2_5308
+.globl sym_2_5309
+sym_2_5309: la $2, sym_2_5309
+.globl sym_2_5310
+sym_2_5310: la $2, sym_2_5310
+.globl sym_2_5311
+sym_2_5311: la $2, sym_2_5311
+.globl sym_2_5312
+sym_2_5312: la $2, sym_2_5312
+.globl sym_2_5313
+sym_2_5313: la $2, sym_2_5313
+.globl sym_2_5314
+sym_2_5314: la $2, sym_2_5314
+.globl sym_2_5315
+sym_2_5315: la $2, sym_2_5315
+.globl sym_2_5316
+sym_2_5316: la $2, sym_2_5316
+.globl sym_2_5317
+sym_2_5317: la $2, sym_2_5317
+.globl sym_2_5318
+sym_2_5318: la $2, sym_2_5318
+.globl sym_2_5319
+sym_2_5319: la $2, sym_2_5319
+.globl sym_2_5320
+sym_2_5320: la $2, sym_2_5320
+.globl sym_2_5321
+sym_2_5321: la $2, sym_2_5321
+.globl sym_2_5322
+sym_2_5322: la $2, sym_2_5322
+.globl sym_2_5323
+sym_2_5323: la $2, sym_2_5323
+.globl sym_2_5324
+sym_2_5324: la $2, sym_2_5324
+.globl sym_2_5325
+sym_2_5325: la $2, sym_2_5325
+.globl sym_2_5326
+sym_2_5326: la $2, sym_2_5326
+.globl sym_2_5327
+sym_2_5327: la $2, sym_2_5327
+.globl sym_2_5328
+sym_2_5328: la $2, sym_2_5328
+.globl sym_2_5329
+sym_2_5329: la $2, sym_2_5329
+.globl sym_2_5330
+sym_2_5330: la $2, sym_2_5330
+.globl sym_2_5331
+sym_2_5331: la $2, sym_2_5331
+.globl sym_2_5332
+sym_2_5332: la $2, sym_2_5332
+.globl sym_2_5333
+sym_2_5333: la $2, sym_2_5333
+.globl sym_2_5334
+sym_2_5334: la $2, sym_2_5334
+.globl sym_2_5335
+sym_2_5335: la $2, sym_2_5335
+.globl sym_2_5336
+sym_2_5336: la $2, sym_2_5336
+.globl sym_2_5337
+sym_2_5337: la $2, sym_2_5337
+.globl sym_2_5338
+sym_2_5338: la $2, sym_2_5338
+.globl sym_2_5339
+sym_2_5339: la $2, sym_2_5339
+.globl sym_2_5340
+sym_2_5340: la $2, sym_2_5340
+.globl sym_2_5341
+sym_2_5341: la $2, sym_2_5341
+.globl sym_2_5342
+sym_2_5342: la $2, sym_2_5342
+.globl sym_2_5343
+sym_2_5343: la $2, sym_2_5343
+.globl sym_2_5344
+sym_2_5344: la $2, sym_2_5344
+.globl sym_2_5345
+sym_2_5345: la $2, sym_2_5345
+.globl sym_2_5346
+sym_2_5346: la $2, sym_2_5346
+.globl sym_2_5347
+sym_2_5347: la $2, sym_2_5347
+.globl sym_2_5348
+sym_2_5348: la $2, sym_2_5348
+.globl sym_2_5349
+sym_2_5349: la $2, sym_2_5349
+.globl sym_2_5350
+sym_2_5350: la $2, sym_2_5350
+.globl sym_2_5351
+sym_2_5351: la $2, sym_2_5351
+.globl sym_2_5352
+sym_2_5352: la $2, sym_2_5352
+.globl sym_2_5353
+sym_2_5353: la $2, sym_2_5353
+.globl sym_2_5354
+sym_2_5354: la $2, sym_2_5354
+.globl sym_2_5355
+sym_2_5355: la $2, sym_2_5355
+.globl sym_2_5356
+sym_2_5356: la $2, sym_2_5356
+.globl sym_2_5357
+sym_2_5357: la $2, sym_2_5357
+.globl sym_2_5358
+sym_2_5358: la $2, sym_2_5358
+.globl sym_2_5359
+sym_2_5359: la $2, sym_2_5359
+.globl sym_2_5360
+sym_2_5360: la $2, sym_2_5360
+.globl sym_2_5361
+sym_2_5361: la $2, sym_2_5361
+.globl sym_2_5362
+sym_2_5362: la $2, sym_2_5362
+.globl sym_2_5363
+sym_2_5363: la $2, sym_2_5363
+.globl sym_2_5364
+sym_2_5364: la $2, sym_2_5364
+.globl sym_2_5365
+sym_2_5365: la $2, sym_2_5365
+.globl sym_2_5366
+sym_2_5366: la $2, sym_2_5366
+.globl sym_2_5367
+sym_2_5367: la $2, sym_2_5367
+.globl sym_2_5368
+sym_2_5368: la $2, sym_2_5368
+.globl sym_2_5369
+sym_2_5369: la $2, sym_2_5369
+.globl sym_2_5370
+sym_2_5370: la $2, sym_2_5370
+.globl sym_2_5371
+sym_2_5371: la $2, sym_2_5371
+.globl sym_2_5372
+sym_2_5372: la $2, sym_2_5372
+.globl sym_2_5373
+sym_2_5373: la $2, sym_2_5373
+.globl sym_2_5374
+sym_2_5374: la $2, sym_2_5374
+.globl sym_2_5375
+sym_2_5375: la $2, sym_2_5375
+.globl sym_2_5376
+sym_2_5376: la $2, sym_2_5376
+.globl sym_2_5377
+sym_2_5377: la $2, sym_2_5377
+.globl sym_2_5378
+sym_2_5378: la $2, sym_2_5378
+.globl sym_2_5379
+sym_2_5379: la $2, sym_2_5379
+.globl sym_2_5380
+sym_2_5380: la $2, sym_2_5380
+.globl sym_2_5381
+sym_2_5381: la $2, sym_2_5381
+.globl sym_2_5382
+sym_2_5382: la $2, sym_2_5382
+.globl sym_2_5383
+sym_2_5383: la $2, sym_2_5383
+.globl sym_2_5384
+sym_2_5384: la $2, sym_2_5384
+.globl sym_2_5385
+sym_2_5385: la $2, sym_2_5385
+.globl sym_2_5386
+sym_2_5386: la $2, sym_2_5386
+.globl sym_2_5387
+sym_2_5387: la $2, sym_2_5387
+.globl sym_2_5388
+sym_2_5388: la $2, sym_2_5388
+.globl sym_2_5389
+sym_2_5389: la $2, sym_2_5389
+.globl sym_2_5390
+sym_2_5390: la $2, sym_2_5390
+.globl sym_2_5391
+sym_2_5391: la $2, sym_2_5391
+.globl sym_2_5392
+sym_2_5392: la $2, sym_2_5392
+.globl sym_2_5393
+sym_2_5393: la $2, sym_2_5393
+.globl sym_2_5394
+sym_2_5394: la $2, sym_2_5394
+.globl sym_2_5395
+sym_2_5395: la $2, sym_2_5395
+.globl sym_2_5396
+sym_2_5396: la $2, sym_2_5396
+.globl sym_2_5397
+sym_2_5397: la $2, sym_2_5397
+.globl sym_2_5398
+sym_2_5398: la $2, sym_2_5398
+.globl sym_2_5399
+sym_2_5399: la $2, sym_2_5399
+.globl sym_2_5400
+sym_2_5400: la $2, sym_2_5400
+.globl sym_2_5401
+sym_2_5401: la $2, sym_2_5401
+.globl sym_2_5402
+sym_2_5402: la $2, sym_2_5402
+.globl sym_2_5403
+sym_2_5403: la $2, sym_2_5403
+.globl sym_2_5404
+sym_2_5404: la $2, sym_2_5404
+.globl sym_2_5405
+sym_2_5405: la $2, sym_2_5405
+.globl sym_2_5406
+sym_2_5406: la $2, sym_2_5406
+.globl sym_2_5407
+sym_2_5407: la $2, sym_2_5407
+.globl sym_2_5408
+sym_2_5408: la $2, sym_2_5408
+.globl sym_2_5409
+sym_2_5409: la $2, sym_2_5409
+.globl sym_2_5410
+sym_2_5410: la $2, sym_2_5410
+.globl sym_2_5411
+sym_2_5411: la $2, sym_2_5411
+.globl sym_2_5412
+sym_2_5412: la $2, sym_2_5412
+.globl sym_2_5413
+sym_2_5413: la $2, sym_2_5413
+.globl sym_2_5414
+sym_2_5414: la $2, sym_2_5414
+.globl sym_2_5415
+sym_2_5415: la $2, sym_2_5415
+.globl sym_2_5416
+sym_2_5416: la $2, sym_2_5416
+.globl sym_2_5417
+sym_2_5417: la $2, sym_2_5417
+.globl sym_2_5418
+sym_2_5418: la $2, sym_2_5418
+.globl sym_2_5419
+sym_2_5419: la $2, sym_2_5419
+.globl sym_2_5420
+sym_2_5420: la $2, sym_2_5420
+.globl sym_2_5421
+sym_2_5421: la $2, sym_2_5421
+.globl sym_2_5422
+sym_2_5422: la $2, sym_2_5422
+.globl sym_2_5423
+sym_2_5423: la $2, sym_2_5423
+.globl sym_2_5424
+sym_2_5424: la $2, sym_2_5424
+.globl sym_2_5425
+sym_2_5425: la $2, sym_2_5425
+.globl sym_2_5426
+sym_2_5426: la $2, sym_2_5426
+.globl sym_2_5427
+sym_2_5427: la $2, sym_2_5427
+.globl sym_2_5428
+sym_2_5428: la $2, sym_2_5428
+.globl sym_2_5429
+sym_2_5429: la $2, sym_2_5429
+.globl sym_2_5430
+sym_2_5430: la $2, sym_2_5430
+.globl sym_2_5431
+sym_2_5431: la $2, sym_2_5431
+.globl sym_2_5432
+sym_2_5432: la $2, sym_2_5432
+.globl sym_2_5433
+sym_2_5433: la $2, sym_2_5433
+.globl sym_2_5434
+sym_2_5434: la $2, sym_2_5434
+.globl sym_2_5435
+sym_2_5435: la $2, sym_2_5435
+.globl sym_2_5436
+sym_2_5436: la $2, sym_2_5436
+.globl sym_2_5437
+sym_2_5437: la $2, sym_2_5437
+.globl sym_2_5438
+sym_2_5438: la $2, sym_2_5438
+.globl sym_2_5439
+sym_2_5439: la $2, sym_2_5439
+.globl sym_2_5440
+sym_2_5440: la $2, sym_2_5440
+.globl sym_2_5441
+sym_2_5441: la $2, sym_2_5441
+.globl sym_2_5442
+sym_2_5442: la $2, sym_2_5442
+.globl sym_2_5443
+sym_2_5443: la $2, sym_2_5443
+.globl sym_2_5444
+sym_2_5444: la $2, sym_2_5444
+.globl sym_2_5445
+sym_2_5445: la $2, sym_2_5445
+.globl sym_2_5446
+sym_2_5446: la $2, sym_2_5446
+.globl sym_2_5447
+sym_2_5447: la $2, sym_2_5447
+.globl sym_2_5448
+sym_2_5448: la $2, sym_2_5448
+.globl sym_2_5449
+sym_2_5449: la $2, sym_2_5449
+.globl sym_2_5450
+sym_2_5450: la $2, sym_2_5450
+.globl sym_2_5451
+sym_2_5451: la $2, sym_2_5451
+.globl sym_2_5452
+sym_2_5452: la $2, sym_2_5452
+.globl sym_2_5453
+sym_2_5453: la $2, sym_2_5453
+.globl sym_2_5454
+sym_2_5454: la $2, sym_2_5454
+.globl sym_2_5455
+sym_2_5455: la $2, sym_2_5455
+.globl sym_2_5456
+sym_2_5456: la $2, sym_2_5456
+.globl sym_2_5457
+sym_2_5457: la $2, sym_2_5457
+.globl sym_2_5458
+sym_2_5458: la $2, sym_2_5458
+.globl sym_2_5459
+sym_2_5459: la $2, sym_2_5459
+.globl sym_2_5460
+sym_2_5460: la $2, sym_2_5460
+.globl sym_2_5461
+sym_2_5461: la $2, sym_2_5461
+.globl sym_2_5462
+sym_2_5462: la $2, sym_2_5462
+.globl sym_2_5463
+sym_2_5463: la $2, sym_2_5463
+.globl sym_2_5464
+sym_2_5464: la $2, sym_2_5464
+.globl sym_2_5465
+sym_2_5465: la $2, sym_2_5465
+.globl sym_2_5466
+sym_2_5466: la $2, sym_2_5466
+.globl sym_2_5467
+sym_2_5467: la $2, sym_2_5467
+.globl sym_2_5468
+sym_2_5468: la $2, sym_2_5468
+.globl sym_2_5469
+sym_2_5469: la $2, sym_2_5469
+.globl sym_2_5470
+sym_2_5470: la $2, sym_2_5470
+.globl sym_2_5471
+sym_2_5471: la $2, sym_2_5471
+.globl sym_2_5472
+sym_2_5472: la $2, sym_2_5472
+.globl sym_2_5473
+sym_2_5473: la $2, sym_2_5473
+.globl sym_2_5474
+sym_2_5474: la $2, sym_2_5474
+.globl sym_2_5475
+sym_2_5475: la $2, sym_2_5475
+.globl sym_2_5476
+sym_2_5476: la $2, sym_2_5476
+.globl sym_2_5477
+sym_2_5477: la $2, sym_2_5477
+.globl sym_2_5478
+sym_2_5478: la $2, sym_2_5478
+.globl sym_2_5479
+sym_2_5479: la $2, sym_2_5479
+.globl sym_2_5480
+sym_2_5480: la $2, sym_2_5480
+.globl sym_2_5481
+sym_2_5481: la $2, sym_2_5481
+.globl sym_2_5482
+sym_2_5482: la $2, sym_2_5482
+.globl sym_2_5483
+sym_2_5483: la $2, sym_2_5483
+.globl sym_2_5484
+sym_2_5484: la $2, sym_2_5484
+.globl sym_2_5485
+sym_2_5485: la $2, sym_2_5485
+.globl sym_2_5486
+sym_2_5486: la $2, sym_2_5486
+.globl sym_2_5487
+sym_2_5487: la $2, sym_2_5487
+.globl sym_2_5488
+sym_2_5488: la $2, sym_2_5488
+.globl sym_2_5489
+sym_2_5489: la $2, sym_2_5489
+.globl sym_2_5490
+sym_2_5490: la $2, sym_2_5490
+.globl sym_2_5491
+sym_2_5491: la $2, sym_2_5491
+.globl sym_2_5492
+sym_2_5492: la $2, sym_2_5492
+.globl sym_2_5493
+sym_2_5493: la $2, sym_2_5493
+.globl sym_2_5494
+sym_2_5494: la $2, sym_2_5494
+.globl sym_2_5495
+sym_2_5495: la $2, sym_2_5495
+.globl sym_2_5496
+sym_2_5496: la $2, sym_2_5496
+.globl sym_2_5497
+sym_2_5497: la $2, sym_2_5497
+.globl sym_2_5498
+sym_2_5498: la $2, sym_2_5498
+.globl sym_2_5499
+sym_2_5499: la $2, sym_2_5499
+.globl sym_2_5500
+sym_2_5500: la $2, sym_2_5500
+.globl sym_2_5501
+sym_2_5501: la $2, sym_2_5501
+.globl sym_2_5502
+sym_2_5502: la $2, sym_2_5502
+.globl sym_2_5503
+sym_2_5503: la $2, sym_2_5503
+.globl sym_2_5504
+sym_2_5504: la $2, sym_2_5504
+.globl sym_2_5505
+sym_2_5505: la $2, sym_2_5505
+.globl sym_2_5506
+sym_2_5506: la $2, sym_2_5506
+.globl sym_2_5507
+sym_2_5507: la $2, sym_2_5507
+.globl sym_2_5508
+sym_2_5508: la $2, sym_2_5508
+.globl sym_2_5509
+sym_2_5509: la $2, sym_2_5509
+.globl sym_2_5510
+sym_2_5510: la $2, sym_2_5510
+.globl sym_2_5511
+sym_2_5511: la $2, sym_2_5511
+.globl sym_2_5512
+sym_2_5512: la $2, sym_2_5512
+.globl sym_2_5513
+sym_2_5513: la $2, sym_2_5513
+.globl sym_2_5514
+sym_2_5514: la $2, sym_2_5514
+.globl sym_2_5515
+sym_2_5515: la $2, sym_2_5515
+.globl sym_2_5516
+sym_2_5516: la $2, sym_2_5516
+.globl sym_2_5517
+sym_2_5517: la $2, sym_2_5517
+.globl sym_2_5518
+sym_2_5518: la $2, sym_2_5518
+.globl sym_2_5519
+sym_2_5519: la $2, sym_2_5519
+.globl sym_2_5520
+sym_2_5520: la $2, sym_2_5520
+.globl sym_2_5521
+sym_2_5521: la $2, sym_2_5521
+.globl sym_2_5522
+sym_2_5522: la $2, sym_2_5522
+.globl sym_2_5523
+sym_2_5523: la $2, sym_2_5523
+.globl sym_2_5524
+sym_2_5524: la $2, sym_2_5524
+.globl sym_2_5525
+sym_2_5525: la $2, sym_2_5525
+.globl sym_2_5526
+sym_2_5526: la $2, sym_2_5526
+.globl sym_2_5527
+sym_2_5527: la $2, sym_2_5527
+.globl sym_2_5528
+sym_2_5528: la $2, sym_2_5528
+.globl sym_2_5529
+sym_2_5529: la $2, sym_2_5529
+.globl sym_2_5530
+sym_2_5530: la $2, sym_2_5530
+.globl sym_2_5531
+sym_2_5531: la $2, sym_2_5531
+.globl sym_2_5532
+sym_2_5532: la $2, sym_2_5532
+.globl sym_2_5533
+sym_2_5533: la $2, sym_2_5533
+.globl sym_2_5534
+sym_2_5534: la $2, sym_2_5534
+.globl sym_2_5535
+sym_2_5535: la $2, sym_2_5535
+.globl sym_2_5536
+sym_2_5536: la $2, sym_2_5536
+.globl sym_2_5537
+sym_2_5537: la $2, sym_2_5537
+.globl sym_2_5538
+sym_2_5538: la $2, sym_2_5538
+.globl sym_2_5539
+sym_2_5539: la $2, sym_2_5539
+.globl sym_2_5540
+sym_2_5540: la $2, sym_2_5540
+.globl sym_2_5541
+sym_2_5541: la $2, sym_2_5541
+.globl sym_2_5542
+sym_2_5542: la $2, sym_2_5542
+.globl sym_2_5543
+sym_2_5543: la $2, sym_2_5543
+.globl sym_2_5544
+sym_2_5544: la $2, sym_2_5544
+.globl sym_2_5545
+sym_2_5545: la $2, sym_2_5545
+.globl sym_2_5546
+sym_2_5546: la $2, sym_2_5546
+.globl sym_2_5547
+sym_2_5547: la $2, sym_2_5547
+.globl sym_2_5548
+sym_2_5548: la $2, sym_2_5548
+.globl sym_2_5549
+sym_2_5549: la $2, sym_2_5549
+.globl sym_2_5550
+sym_2_5550: la $2, sym_2_5550
+.globl sym_2_5551
+sym_2_5551: la $2, sym_2_5551
+.globl sym_2_5552
+sym_2_5552: la $2, sym_2_5552
+.globl sym_2_5553
+sym_2_5553: la $2, sym_2_5553
+.globl sym_2_5554
+sym_2_5554: la $2, sym_2_5554
+.globl sym_2_5555
+sym_2_5555: la $2, sym_2_5555
+.globl sym_2_5556
+sym_2_5556: la $2, sym_2_5556
+.globl sym_2_5557
+sym_2_5557: la $2, sym_2_5557
+.globl sym_2_5558
+sym_2_5558: la $2, sym_2_5558
+.globl sym_2_5559
+sym_2_5559: la $2, sym_2_5559
+.globl sym_2_5560
+sym_2_5560: la $2, sym_2_5560
+.globl sym_2_5561
+sym_2_5561: la $2, sym_2_5561
+.globl sym_2_5562
+sym_2_5562: la $2, sym_2_5562
+.globl sym_2_5563
+sym_2_5563: la $2, sym_2_5563
+.globl sym_2_5564
+sym_2_5564: la $2, sym_2_5564
+.globl sym_2_5565
+sym_2_5565: la $2, sym_2_5565
+.globl sym_2_5566
+sym_2_5566: la $2, sym_2_5566
+.globl sym_2_5567
+sym_2_5567: la $2, sym_2_5567
+.globl sym_2_5568
+sym_2_5568: la $2, sym_2_5568
+.globl sym_2_5569
+sym_2_5569: la $2, sym_2_5569
+.globl sym_2_5570
+sym_2_5570: la $2, sym_2_5570
+.globl sym_2_5571
+sym_2_5571: la $2, sym_2_5571
+.globl sym_2_5572
+sym_2_5572: la $2, sym_2_5572
+.globl sym_2_5573
+sym_2_5573: la $2, sym_2_5573
+.globl sym_2_5574
+sym_2_5574: la $2, sym_2_5574
+.globl sym_2_5575
+sym_2_5575: la $2, sym_2_5575
+.globl sym_2_5576
+sym_2_5576: la $2, sym_2_5576
+.globl sym_2_5577
+sym_2_5577: la $2, sym_2_5577
+.globl sym_2_5578
+sym_2_5578: la $2, sym_2_5578
+.globl sym_2_5579
+sym_2_5579: la $2, sym_2_5579
+.globl sym_2_5580
+sym_2_5580: la $2, sym_2_5580
+.globl sym_2_5581
+sym_2_5581: la $2, sym_2_5581
+.globl sym_2_5582
+sym_2_5582: la $2, sym_2_5582
+.globl sym_2_5583
+sym_2_5583: la $2, sym_2_5583
+.globl sym_2_5584
+sym_2_5584: la $2, sym_2_5584
+.globl sym_2_5585
+sym_2_5585: la $2, sym_2_5585
+.globl sym_2_5586
+sym_2_5586: la $2, sym_2_5586
+.globl sym_2_5587
+sym_2_5587: la $2, sym_2_5587
+.globl sym_2_5588
+sym_2_5588: la $2, sym_2_5588
+.globl sym_2_5589
+sym_2_5589: la $2, sym_2_5589
+.globl sym_2_5590
+sym_2_5590: la $2, sym_2_5590
+.globl sym_2_5591
+sym_2_5591: la $2, sym_2_5591
+.globl sym_2_5592
+sym_2_5592: la $2, sym_2_5592
+.globl sym_2_5593
+sym_2_5593: la $2, sym_2_5593
+.globl sym_2_5594
+sym_2_5594: la $2, sym_2_5594
+.globl sym_2_5595
+sym_2_5595: la $2, sym_2_5595
+.globl sym_2_5596
+sym_2_5596: la $2, sym_2_5596
+.globl sym_2_5597
+sym_2_5597: la $2, sym_2_5597
+.globl sym_2_5598
+sym_2_5598: la $2, sym_2_5598
+.globl sym_2_5599
+sym_2_5599: la $2, sym_2_5599
+.globl sym_2_5600
+sym_2_5600: la $2, sym_2_5600
+.globl sym_2_5601
+sym_2_5601: la $2, sym_2_5601
+.globl sym_2_5602
+sym_2_5602: la $2, sym_2_5602
+.globl sym_2_5603
+sym_2_5603: la $2, sym_2_5603
+.globl sym_2_5604
+sym_2_5604: la $2, sym_2_5604
+.globl sym_2_5605
+sym_2_5605: la $2, sym_2_5605
+.globl sym_2_5606
+sym_2_5606: la $2, sym_2_5606
+.globl sym_2_5607
+sym_2_5607: la $2, sym_2_5607
+.globl sym_2_5608
+sym_2_5608: la $2, sym_2_5608
+.globl sym_2_5609
+sym_2_5609: la $2, sym_2_5609
+.globl sym_2_5610
+sym_2_5610: la $2, sym_2_5610
+.globl sym_2_5611
+sym_2_5611: la $2, sym_2_5611
+.globl sym_2_5612
+sym_2_5612: la $2, sym_2_5612
+.globl sym_2_5613
+sym_2_5613: la $2, sym_2_5613
+.globl sym_2_5614
+sym_2_5614: la $2, sym_2_5614
+.globl sym_2_5615
+sym_2_5615: la $2, sym_2_5615
+.globl sym_2_5616
+sym_2_5616: la $2, sym_2_5616
+.globl sym_2_5617
+sym_2_5617: la $2, sym_2_5617
+.globl sym_2_5618
+sym_2_5618: la $2, sym_2_5618
+.globl sym_2_5619
+sym_2_5619: la $2, sym_2_5619
+.globl sym_2_5620
+sym_2_5620: la $2, sym_2_5620
+.globl sym_2_5621
+sym_2_5621: la $2, sym_2_5621
+.globl sym_2_5622
+sym_2_5622: la $2, sym_2_5622
+.globl sym_2_5623
+sym_2_5623: la $2, sym_2_5623
+.globl sym_2_5624
+sym_2_5624: la $2, sym_2_5624
+.globl sym_2_5625
+sym_2_5625: la $2, sym_2_5625
+.globl sym_2_5626
+sym_2_5626: la $2, sym_2_5626
+.globl sym_2_5627
+sym_2_5627: la $2, sym_2_5627
+.globl sym_2_5628
+sym_2_5628: la $2, sym_2_5628
+.globl sym_2_5629
+sym_2_5629: la $2, sym_2_5629
+.globl sym_2_5630
+sym_2_5630: la $2, sym_2_5630
+.globl sym_2_5631
+sym_2_5631: la $2, sym_2_5631
+.globl sym_2_5632
+sym_2_5632: la $2, sym_2_5632
+.globl sym_2_5633
+sym_2_5633: la $2, sym_2_5633
+.globl sym_2_5634
+sym_2_5634: la $2, sym_2_5634
+.globl sym_2_5635
+sym_2_5635: la $2, sym_2_5635
+.globl sym_2_5636
+sym_2_5636: la $2, sym_2_5636
+.globl sym_2_5637
+sym_2_5637: la $2, sym_2_5637
+.globl sym_2_5638
+sym_2_5638: la $2, sym_2_5638
+.globl sym_2_5639
+sym_2_5639: la $2, sym_2_5639
+.globl sym_2_5640
+sym_2_5640: la $2, sym_2_5640
+.globl sym_2_5641
+sym_2_5641: la $2, sym_2_5641
+.globl sym_2_5642
+sym_2_5642: la $2, sym_2_5642
+.globl sym_2_5643
+sym_2_5643: la $2, sym_2_5643
+.globl sym_2_5644
+sym_2_5644: la $2, sym_2_5644
+.globl sym_2_5645
+sym_2_5645: la $2, sym_2_5645
+.globl sym_2_5646
+sym_2_5646: la $2, sym_2_5646
+.globl sym_2_5647
+sym_2_5647: la $2, sym_2_5647
+.globl sym_2_5648
+sym_2_5648: la $2, sym_2_5648
+.globl sym_2_5649
+sym_2_5649: la $2, sym_2_5649
+.globl sym_2_5650
+sym_2_5650: la $2, sym_2_5650
+.globl sym_2_5651
+sym_2_5651: la $2, sym_2_5651
+.globl sym_2_5652
+sym_2_5652: la $2, sym_2_5652
+.globl sym_2_5653
+sym_2_5653: la $2, sym_2_5653
+.globl sym_2_5654
+sym_2_5654: la $2, sym_2_5654
+.globl sym_2_5655
+sym_2_5655: la $2, sym_2_5655
+.globl sym_2_5656
+sym_2_5656: la $2, sym_2_5656
+.globl sym_2_5657
+sym_2_5657: la $2, sym_2_5657
+.globl sym_2_5658
+sym_2_5658: la $2, sym_2_5658
+.globl sym_2_5659
+sym_2_5659: la $2, sym_2_5659
+.globl sym_2_5660
+sym_2_5660: la $2, sym_2_5660
+.globl sym_2_5661
+sym_2_5661: la $2, sym_2_5661
+.globl sym_2_5662
+sym_2_5662: la $2, sym_2_5662
+.globl sym_2_5663
+sym_2_5663: la $2, sym_2_5663
+.globl sym_2_5664
+sym_2_5664: la $2, sym_2_5664
+.globl sym_2_5665
+sym_2_5665: la $2, sym_2_5665
+.globl sym_2_5666
+sym_2_5666: la $2, sym_2_5666
+.globl sym_2_5667
+sym_2_5667: la $2, sym_2_5667
+.globl sym_2_5668
+sym_2_5668: la $2, sym_2_5668
+.globl sym_2_5669
+sym_2_5669: la $2, sym_2_5669
+.globl sym_2_5670
+sym_2_5670: la $2, sym_2_5670
+.globl sym_2_5671
+sym_2_5671: la $2, sym_2_5671
+.globl sym_2_5672
+sym_2_5672: la $2, sym_2_5672
+.globl sym_2_5673
+sym_2_5673: la $2, sym_2_5673
+.globl sym_2_5674
+sym_2_5674: la $2, sym_2_5674
+.globl sym_2_5675
+sym_2_5675: la $2, sym_2_5675
+.globl sym_2_5676
+sym_2_5676: la $2, sym_2_5676
+.globl sym_2_5677
+sym_2_5677: la $2, sym_2_5677
+.globl sym_2_5678
+sym_2_5678: la $2, sym_2_5678
+.globl sym_2_5679
+sym_2_5679: la $2, sym_2_5679
+.globl sym_2_5680
+sym_2_5680: la $2, sym_2_5680
+.globl sym_2_5681
+sym_2_5681: la $2, sym_2_5681
+.globl sym_2_5682
+sym_2_5682: la $2, sym_2_5682
+.globl sym_2_5683
+sym_2_5683: la $2, sym_2_5683
+.globl sym_2_5684
+sym_2_5684: la $2, sym_2_5684
+.globl sym_2_5685
+sym_2_5685: la $2, sym_2_5685
+.globl sym_2_5686
+sym_2_5686: la $2, sym_2_5686
+.globl sym_2_5687
+sym_2_5687: la $2, sym_2_5687
+.globl sym_2_5688
+sym_2_5688: la $2, sym_2_5688
+.globl sym_2_5689
+sym_2_5689: la $2, sym_2_5689
+.globl sym_2_5690
+sym_2_5690: la $2, sym_2_5690
+.globl sym_2_5691
+sym_2_5691: la $2, sym_2_5691
+.globl sym_2_5692
+sym_2_5692: la $2, sym_2_5692
+.globl sym_2_5693
+sym_2_5693: la $2, sym_2_5693
+.globl sym_2_5694
+sym_2_5694: la $2, sym_2_5694
+.globl sym_2_5695
+sym_2_5695: la $2, sym_2_5695
+.globl sym_2_5696
+sym_2_5696: la $2, sym_2_5696
+.globl sym_2_5697
+sym_2_5697: la $2, sym_2_5697
+.globl sym_2_5698
+sym_2_5698: la $2, sym_2_5698
+.globl sym_2_5699
+sym_2_5699: la $2, sym_2_5699
+.globl sym_2_5700
+sym_2_5700: la $2, sym_2_5700
+.globl sym_2_5701
+sym_2_5701: la $2, sym_2_5701
+.globl sym_2_5702
+sym_2_5702: la $2, sym_2_5702
+.globl sym_2_5703
+sym_2_5703: la $2, sym_2_5703
+.globl sym_2_5704
+sym_2_5704: la $2, sym_2_5704
+.globl sym_2_5705
+sym_2_5705: la $2, sym_2_5705
+.globl sym_2_5706
+sym_2_5706: la $2, sym_2_5706
+.globl sym_2_5707
+sym_2_5707: la $2, sym_2_5707
+.globl sym_2_5708
+sym_2_5708: la $2, sym_2_5708
+.globl sym_2_5709
+sym_2_5709: la $2, sym_2_5709
+.globl sym_2_5710
+sym_2_5710: la $2, sym_2_5710
+.globl sym_2_5711
+sym_2_5711: la $2, sym_2_5711
+.globl sym_2_5712
+sym_2_5712: la $2, sym_2_5712
+.globl sym_2_5713
+sym_2_5713: la $2, sym_2_5713
+.globl sym_2_5714
+sym_2_5714: la $2, sym_2_5714
+.globl sym_2_5715
+sym_2_5715: la $2, sym_2_5715
+.globl sym_2_5716
+sym_2_5716: la $2, sym_2_5716
+.globl sym_2_5717
+sym_2_5717: la $2, sym_2_5717
+.globl sym_2_5718
+sym_2_5718: la $2, sym_2_5718
+.globl sym_2_5719
+sym_2_5719: la $2, sym_2_5719
+.globl sym_2_5720
+sym_2_5720: la $2, sym_2_5720
+.globl sym_2_5721
+sym_2_5721: la $2, sym_2_5721
+.globl sym_2_5722
+sym_2_5722: la $2, sym_2_5722
+.globl sym_2_5723
+sym_2_5723: la $2, sym_2_5723
+.globl sym_2_5724
+sym_2_5724: la $2, sym_2_5724
+.globl sym_2_5725
+sym_2_5725: la $2, sym_2_5725
+.globl sym_2_5726
+sym_2_5726: la $2, sym_2_5726
+.globl sym_2_5727
+sym_2_5727: la $2, sym_2_5727
+.globl sym_2_5728
+sym_2_5728: la $2, sym_2_5728
+.globl sym_2_5729
+sym_2_5729: la $2, sym_2_5729
+.globl sym_2_5730
+sym_2_5730: la $2, sym_2_5730
+.globl sym_2_5731
+sym_2_5731: la $2, sym_2_5731
+.globl sym_2_5732
+sym_2_5732: la $2, sym_2_5732
+.globl sym_2_5733
+sym_2_5733: la $2, sym_2_5733
+.globl sym_2_5734
+sym_2_5734: la $2, sym_2_5734
+.globl sym_2_5735
+sym_2_5735: la $2, sym_2_5735
+.globl sym_2_5736
+sym_2_5736: la $2, sym_2_5736
+.globl sym_2_5737
+sym_2_5737: la $2, sym_2_5737
+.globl sym_2_5738
+sym_2_5738: la $2, sym_2_5738
+.globl sym_2_5739
+sym_2_5739: la $2, sym_2_5739
+.globl sym_2_5740
+sym_2_5740: la $2, sym_2_5740
+.globl sym_2_5741
+sym_2_5741: la $2, sym_2_5741
+.globl sym_2_5742
+sym_2_5742: la $2, sym_2_5742
+.globl sym_2_5743
+sym_2_5743: la $2, sym_2_5743
+.globl sym_2_5744
+sym_2_5744: la $2, sym_2_5744
+.globl sym_2_5745
+sym_2_5745: la $2, sym_2_5745
+.globl sym_2_5746
+sym_2_5746: la $2, sym_2_5746
+.globl sym_2_5747
+sym_2_5747: la $2, sym_2_5747
+.globl sym_2_5748
+sym_2_5748: la $2, sym_2_5748
+.globl sym_2_5749
+sym_2_5749: la $2, sym_2_5749
+.globl sym_2_5750
+sym_2_5750: la $2, sym_2_5750
+.globl sym_2_5751
+sym_2_5751: la $2, sym_2_5751
+.globl sym_2_5752
+sym_2_5752: la $2, sym_2_5752
+.globl sym_2_5753
+sym_2_5753: la $2, sym_2_5753
+.globl sym_2_5754
+sym_2_5754: la $2, sym_2_5754
+.globl sym_2_5755
+sym_2_5755: la $2, sym_2_5755
+.globl sym_2_5756
+sym_2_5756: la $2, sym_2_5756
+.globl sym_2_5757
+sym_2_5757: la $2, sym_2_5757
+.globl sym_2_5758
+sym_2_5758: la $2, sym_2_5758
+.globl sym_2_5759
+sym_2_5759: la $2, sym_2_5759
+.globl sym_2_5760
+sym_2_5760: la $2, sym_2_5760
+.globl sym_2_5761
+sym_2_5761: la $2, sym_2_5761
+.globl sym_2_5762
+sym_2_5762: la $2, sym_2_5762
+.globl sym_2_5763
+sym_2_5763: la $2, sym_2_5763
+.globl sym_2_5764
+sym_2_5764: la $2, sym_2_5764
+.globl sym_2_5765
+sym_2_5765: la $2, sym_2_5765
+.globl sym_2_5766
+sym_2_5766: la $2, sym_2_5766
+.globl sym_2_5767
+sym_2_5767: la $2, sym_2_5767
+.globl sym_2_5768
+sym_2_5768: la $2, sym_2_5768
+.globl sym_2_5769
+sym_2_5769: la $2, sym_2_5769
+.globl sym_2_5770
+sym_2_5770: la $2, sym_2_5770
+.globl sym_2_5771
+sym_2_5771: la $2, sym_2_5771
+.globl sym_2_5772
+sym_2_5772: la $2, sym_2_5772
+.globl sym_2_5773
+sym_2_5773: la $2, sym_2_5773
+.globl sym_2_5774
+sym_2_5774: la $2, sym_2_5774
+.globl sym_2_5775
+sym_2_5775: la $2, sym_2_5775
+.globl sym_2_5776
+sym_2_5776: la $2, sym_2_5776
+.globl sym_2_5777
+sym_2_5777: la $2, sym_2_5777
+.globl sym_2_5778
+sym_2_5778: la $2, sym_2_5778
+.globl sym_2_5779
+sym_2_5779: la $2, sym_2_5779
+.globl sym_2_5780
+sym_2_5780: la $2, sym_2_5780
+.globl sym_2_5781
+sym_2_5781: la $2, sym_2_5781
+.globl sym_2_5782
+sym_2_5782: la $2, sym_2_5782
+.globl sym_2_5783
+sym_2_5783: la $2, sym_2_5783
+.globl sym_2_5784
+sym_2_5784: la $2, sym_2_5784
+.globl sym_2_5785
+sym_2_5785: la $2, sym_2_5785
+.globl sym_2_5786
+sym_2_5786: la $2, sym_2_5786
+.globl sym_2_5787
+sym_2_5787: la $2, sym_2_5787
+.globl sym_2_5788
+sym_2_5788: la $2, sym_2_5788
+.globl sym_2_5789
+sym_2_5789: la $2, sym_2_5789
+.globl sym_2_5790
+sym_2_5790: la $2, sym_2_5790
+.globl sym_2_5791
+sym_2_5791: la $2, sym_2_5791
+.globl sym_2_5792
+sym_2_5792: la $2, sym_2_5792
+.globl sym_2_5793
+sym_2_5793: la $2, sym_2_5793
+.globl sym_2_5794
+sym_2_5794: la $2, sym_2_5794
+.globl sym_2_5795
+sym_2_5795: la $2, sym_2_5795
+.globl sym_2_5796
+sym_2_5796: la $2, sym_2_5796
+.globl sym_2_5797
+sym_2_5797: la $2, sym_2_5797
+.globl sym_2_5798
+sym_2_5798: la $2, sym_2_5798
+.globl sym_2_5799
+sym_2_5799: la $2, sym_2_5799
+.globl sym_2_5800
+sym_2_5800: la $2, sym_2_5800
+.globl sym_2_5801
+sym_2_5801: la $2, sym_2_5801
+.globl sym_2_5802
+sym_2_5802: la $2, sym_2_5802
+.globl sym_2_5803
+sym_2_5803: la $2, sym_2_5803
+.globl sym_2_5804
+sym_2_5804: la $2, sym_2_5804
+.globl sym_2_5805
+sym_2_5805: la $2, sym_2_5805
+.globl sym_2_5806
+sym_2_5806: la $2, sym_2_5806
+.globl sym_2_5807
+sym_2_5807: la $2, sym_2_5807
+.globl sym_2_5808
+sym_2_5808: la $2, sym_2_5808
+.globl sym_2_5809
+sym_2_5809: la $2, sym_2_5809
+.globl sym_2_5810
+sym_2_5810: la $2, sym_2_5810
+.globl sym_2_5811
+sym_2_5811: la $2, sym_2_5811
+.globl sym_2_5812
+sym_2_5812: la $2, sym_2_5812
+.globl sym_2_5813
+sym_2_5813: la $2, sym_2_5813
+.globl sym_2_5814
+sym_2_5814: la $2, sym_2_5814
+.globl sym_2_5815
+sym_2_5815: la $2, sym_2_5815
+.globl sym_2_5816
+sym_2_5816: la $2, sym_2_5816
+.globl sym_2_5817
+sym_2_5817: la $2, sym_2_5817
+.globl sym_2_5818
+sym_2_5818: la $2, sym_2_5818
+.globl sym_2_5819
+sym_2_5819: la $2, sym_2_5819
+.globl sym_2_5820
+sym_2_5820: la $2, sym_2_5820
+.globl sym_2_5821
+sym_2_5821: la $2, sym_2_5821
+.globl sym_2_5822
+sym_2_5822: la $2, sym_2_5822
+.globl sym_2_5823
+sym_2_5823: la $2, sym_2_5823
+.globl sym_2_5824
+sym_2_5824: la $2, sym_2_5824
+.globl sym_2_5825
+sym_2_5825: la $2, sym_2_5825
+.globl sym_2_5826
+sym_2_5826: la $2, sym_2_5826
+.globl sym_2_5827
+sym_2_5827: la $2, sym_2_5827
+.globl sym_2_5828
+sym_2_5828: la $2, sym_2_5828
+.globl sym_2_5829
+sym_2_5829: la $2, sym_2_5829
+.globl sym_2_5830
+sym_2_5830: la $2, sym_2_5830
+.globl sym_2_5831
+sym_2_5831: la $2, sym_2_5831
+.globl sym_2_5832
+sym_2_5832: la $2, sym_2_5832
+.globl sym_2_5833
+sym_2_5833: la $2, sym_2_5833
+.globl sym_2_5834
+sym_2_5834: la $2, sym_2_5834
+.globl sym_2_5835
+sym_2_5835: la $2, sym_2_5835
+.globl sym_2_5836
+sym_2_5836: la $2, sym_2_5836
+.globl sym_2_5837
+sym_2_5837: la $2, sym_2_5837
+.globl sym_2_5838
+sym_2_5838: la $2, sym_2_5838
+.globl sym_2_5839
+sym_2_5839: la $2, sym_2_5839
+.globl sym_2_5840
+sym_2_5840: la $2, sym_2_5840
+.globl sym_2_5841
+sym_2_5841: la $2, sym_2_5841
+.globl sym_2_5842
+sym_2_5842: la $2, sym_2_5842
+.globl sym_2_5843
+sym_2_5843: la $2, sym_2_5843
+.globl sym_2_5844
+sym_2_5844: la $2, sym_2_5844
+.globl sym_2_5845
+sym_2_5845: la $2, sym_2_5845
+.globl sym_2_5846
+sym_2_5846: la $2, sym_2_5846
+.globl sym_2_5847
+sym_2_5847: la $2, sym_2_5847
+.globl sym_2_5848
+sym_2_5848: la $2, sym_2_5848
+.globl sym_2_5849
+sym_2_5849: la $2, sym_2_5849
+.globl sym_2_5850
+sym_2_5850: la $2, sym_2_5850
+.globl sym_2_5851
+sym_2_5851: la $2, sym_2_5851
+.globl sym_2_5852
+sym_2_5852: la $2, sym_2_5852
+.globl sym_2_5853
+sym_2_5853: la $2, sym_2_5853
+.globl sym_2_5854
+sym_2_5854: la $2, sym_2_5854
+.globl sym_2_5855
+sym_2_5855: la $2, sym_2_5855
+.globl sym_2_5856
+sym_2_5856: la $2, sym_2_5856
+.globl sym_2_5857
+sym_2_5857: la $2, sym_2_5857
+.globl sym_2_5858
+sym_2_5858: la $2, sym_2_5858
+.globl sym_2_5859
+sym_2_5859: la $2, sym_2_5859
+.globl sym_2_5860
+sym_2_5860: la $2, sym_2_5860
+.globl sym_2_5861
+sym_2_5861: la $2, sym_2_5861
+.globl sym_2_5862
+sym_2_5862: la $2, sym_2_5862
+.globl sym_2_5863
+sym_2_5863: la $2, sym_2_5863
+.globl sym_2_5864
+sym_2_5864: la $2, sym_2_5864
+.globl sym_2_5865
+sym_2_5865: la $2, sym_2_5865
+.globl sym_2_5866
+sym_2_5866: la $2, sym_2_5866
+.globl sym_2_5867
+sym_2_5867: la $2, sym_2_5867
+.globl sym_2_5868
+sym_2_5868: la $2, sym_2_5868
+.globl sym_2_5869
+sym_2_5869: la $2, sym_2_5869
+.globl sym_2_5870
+sym_2_5870: la $2, sym_2_5870
+.globl sym_2_5871
+sym_2_5871: la $2, sym_2_5871
+.globl sym_2_5872
+sym_2_5872: la $2, sym_2_5872
+.globl sym_2_5873
+sym_2_5873: la $2, sym_2_5873
+.globl sym_2_5874
+sym_2_5874: la $2, sym_2_5874
+.globl sym_2_5875
+sym_2_5875: la $2, sym_2_5875
+.globl sym_2_5876
+sym_2_5876: la $2, sym_2_5876
+.globl sym_2_5877
+sym_2_5877: la $2, sym_2_5877
+.globl sym_2_5878
+sym_2_5878: la $2, sym_2_5878
+.globl sym_2_5879
+sym_2_5879: la $2, sym_2_5879
+.globl sym_2_5880
+sym_2_5880: la $2, sym_2_5880
+.globl sym_2_5881
+sym_2_5881: la $2, sym_2_5881
+.globl sym_2_5882
+sym_2_5882: la $2, sym_2_5882
+.globl sym_2_5883
+sym_2_5883: la $2, sym_2_5883
+.globl sym_2_5884
+sym_2_5884: la $2, sym_2_5884
+.globl sym_2_5885
+sym_2_5885: la $2, sym_2_5885
+.globl sym_2_5886
+sym_2_5886: la $2, sym_2_5886
+.globl sym_2_5887
+sym_2_5887: la $2, sym_2_5887
+.globl sym_2_5888
+sym_2_5888: la $2, sym_2_5888
+.globl sym_2_5889
+sym_2_5889: la $2, sym_2_5889
+.globl sym_2_5890
+sym_2_5890: la $2, sym_2_5890
+.globl sym_2_5891
+sym_2_5891: la $2, sym_2_5891
+.globl sym_2_5892
+sym_2_5892: la $2, sym_2_5892
+.globl sym_2_5893
+sym_2_5893: la $2, sym_2_5893
+.globl sym_2_5894
+sym_2_5894: la $2, sym_2_5894
+.globl sym_2_5895
+sym_2_5895: la $2, sym_2_5895
+.globl sym_2_5896
+sym_2_5896: la $2, sym_2_5896
+.globl sym_2_5897
+sym_2_5897: la $2, sym_2_5897
+.globl sym_2_5898
+sym_2_5898: la $2, sym_2_5898
+.globl sym_2_5899
+sym_2_5899: la $2, sym_2_5899
+.globl sym_2_5900
+sym_2_5900: la $2, sym_2_5900
+.globl sym_2_5901
+sym_2_5901: la $2, sym_2_5901
+.globl sym_2_5902
+sym_2_5902: la $2, sym_2_5902
+.globl sym_2_5903
+sym_2_5903: la $2, sym_2_5903
+.globl sym_2_5904
+sym_2_5904: la $2, sym_2_5904
+.globl sym_2_5905
+sym_2_5905: la $2, sym_2_5905
+.globl sym_2_5906
+sym_2_5906: la $2, sym_2_5906
+.globl sym_2_5907
+sym_2_5907: la $2, sym_2_5907
+.globl sym_2_5908
+sym_2_5908: la $2, sym_2_5908
+.globl sym_2_5909
+sym_2_5909: la $2, sym_2_5909
+.globl sym_2_5910
+sym_2_5910: la $2, sym_2_5910
+.globl sym_2_5911
+sym_2_5911: la $2, sym_2_5911
+.globl sym_2_5912
+sym_2_5912: la $2, sym_2_5912
+.globl sym_2_5913
+sym_2_5913: la $2, sym_2_5913
+.globl sym_2_5914
+sym_2_5914: la $2, sym_2_5914
+.globl sym_2_5915
+sym_2_5915: la $2, sym_2_5915
+.globl sym_2_5916
+sym_2_5916: la $2, sym_2_5916
+.globl sym_2_5917
+sym_2_5917: la $2, sym_2_5917
+.globl sym_2_5918
+sym_2_5918: la $2, sym_2_5918
+.globl sym_2_5919
+sym_2_5919: la $2, sym_2_5919
+.globl sym_2_5920
+sym_2_5920: la $2, sym_2_5920
+.globl sym_2_5921
+sym_2_5921: la $2, sym_2_5921
+.globl sym_2_5922
+sym_2_5922: la $2, sym_2_5922
+.globl sym_2_5923
+sym_2_5923: la $2, sym_2_5923
+.globl sym_2_5924
+sym_2_5924: la $2, sym_2_5924
+.globl sym_2_5925
+sym_2_5925: la $2, sym_2_5925
+.globl sym_2_5926
+sym_2_5926: la $2, sym_2_5926
+.globl sym_2_5927
+sym_2_5927: la $2, sym_2_5927
+.globl sym_2_5928
+sym_2_5928: la $2, sym_2_5928
+.globl sym_2_5929
+sym_2_5929: la $2, sym_2_5929
+.globl sym_2_5930
+sym_2_5930: la $2, sym_2_5930
+.globl sym_2_5931
+sym_2_5931: la $2, sym_2_5931
+.globl sym_2_5932
+sym_2_5932: la $2, sym_2_5932
+.globl sym_2_5933
+sym_2_5933: la $2, sym_2_5933
+.globl sym_2_5934
+sym_2_5934: la $2, sym_2_5934
+.globl sym_2_5935
+sym_2_5935: la $2, sym_2_5935
+.globl sym_2_5936
+sym_2_5936: la $2, sym_2_5936
+.globl sym_2_5937
+sym_2_5937: la $2, sym_2_5937
+.globl sym_2_5938
+sym_2_5938: la $2, sym_2_5938
+.globl sym_2_5939
+sym_2_5939: la $2, sym_2_5939
+.globl sym_2_5940
+sym_2_5940: la $2, sym_2_5940
+.globl sym_2_5941
+sym_2_5941: la $2, sym_2_5941
+.globl sym_2_5942
+sym_2_5942: la $2, sym_2_5942
+.globl sym_2_5943
+sym_2_5943: la $2, sym_2_5943
+.globl sym_2_5944
+sym_2_5944: la $2, sym_2_5944
+.globl sym_2_5945
+sym_2_5945: la $2, sym_2_5945
+.globl sym_2_5946
+sym_2_5946: la $2, sym_2_5946
+.globl sym_2_5947
+sym_2_5947: la $2, sym_2_5947
+.globl sym_2_5948
+sym_2_5948: la $2, sym_2_5948
+.globl sym_2_5949
+sym_2_5949: la $2, sym_2_5949
+.globl sym_2_5950
+sym_2_5950: la $2, sym_2_5950
+.globl sym_2_5951
+sym_2_5951: la $2, sym_2_5951
+.globl sym_2_5952
+sym_2_5952: la $2, sym_2_5952
+.globl sym_2_5953
+sym_2_5953: la $2, sym_2_5953
+.globl sym_2_5954
+sym_2_5954: la $2, sym_2_5954
+.globl sym_2_5955
+sym_2_5955: la $2, sym_2_5955
+.globl sym_2_5956
+sym_2_5956: la $2, sym_2_5956
+.globl sym_2_5957
+sym_2_5957: la $2, sym_2_5957
+.globl sym_2_5958
+sym_2_5958: la $2, sym_2_5958
+.globl sym_2_5959
+sym_2_5959: la $2, sym_2_5959
+.globl sym_2_5960
+sym_2_5960: la $2, sym_2_5960
+.globl sym_2_5961
+sym_2_5961: la $2, sym_2_5961
+.globl sym_2_5962
+sym_2_5962: la $2, sym_2_5962
+.globl sym_2_5963
+sym_2_5963: la $2, sym_2_5963
+.globl sym_2_5964
+sym_2_5964: la $2, sym_2_5964
+.globl sym_2_5965
+sym_2_5965: la $2, sym_2_5965
+.globl sym_2_5966
+sym_2_5966: la $2, sym_2_5966
+.globl sym_2_5967
+sym_2_5967: la $2, sym_2_5967
+.globl sym_2_5968
+sym_2_5968: la $2, sym_2_5968
+.globl sym_2_5969
+sym_2_5969: la $2, sym_2_5969
+.globl sym_2_5970
+sym_2_5970: la $2, sym_2_5970
+.globl sym_2_5971
+sym_2_5971: la $2, sym_2_5971
+.globl sym_2_5972
+sym_2_5972: la $2, sym_2_5972
+.globl sym_2_5973
+sym_2_5973: la $2, sym_2_5973
+.globl sym_2_5974
+sym_2_5974: la $2, sym_2_5974
+.globl sym_2_5975
+sym_2_5975: la $2, sym_2_5975
+.globl sym_2_5976
+sym_2_5976: la $2, sym_2_5976
+.globl sym_2_5977
+sym_2_5977: la $2, sym_2_5977
+.globl sym_2_5978
+sym_2_5978: la $2, sym_2_5978
+.globl sym_2_5979
+sym_2_5979: la $2, sym_2_5979
+.globl sym_2_5980
+sym_2_5980: la $2, sym_2_5980
+.globl sym_2_5981
+sym_2_5981: la $2, sym_2_5981
+.globl sym_2_5982
+sym_2_5982: la $2, sym_2_5982
+.globl sym_2_5983
+sym_2_5983: la $2, sym_2_5983
+.globl sym_2_5984
+sym_2_5984: la $2, sym_2_5984
+.globl sym_2_5985
+sym_2_5985: la $2, sym_2_5985
+.globl sym_2_5986
+sym_2_5986: la $2, sym_2_5986
+.globl sym_2_5987
+sym_2_5987: la $2, sym_2_5987
+.globl sym_2_5988
+sym_2_5988: la $2, sym_2_5988
+.globl sym_2_5989
+sym_2_5989: la $2, sym_2_5989
+.globl sym_2_5990
+sym_2_5990: la $2, sym_2_5990
+.globl sym_2_5991
+sym_2_5991: la $2, sym_2_5991
+.globl sym_2_5992
+sym_2_5992: la $2, sym_2_5992
+.globl sym_2_5993
+sym_2_5993: la $2, sym_2_5993
+.globl sym_2_5994
+sym_2_5994: la $2, sym_2_5994
+.globl sym_2_5995
+sym_2_5995: la $2, sym_2_5995
+.globl sym_2_5996
+sym_2_5996: la $2, sym_2_5996
+.globl sym_2_5997
+sym_2_5997: la $2, sym_2_5997
+.globl sym_2_5998
+sym_2_5998: la $2, sym_2_5998
+.globl sym_2_5999
+sym_2_5999: la $2, sym_2_5999
+.globl sym_2_6000
+sym_2_6000: la $2, sym_2_6000
+.globl sym_2_6001
+sym_2_6001: la $2, sym_2_6001
+.globl sym_2_6002
+sym_2_6002: la $2, sym_2_6002
+.globl sym_2_6003
+sym_2_6003: la $2, sym_2_6003
+.globl sym_2_6004
+sym_2_6004: la $2, sym_2_6004
+.globl sym_2_6005
+sym_2_6005: la $2, sym_2_6005
+.globl sym_2_6006
+sym_2_6006: la $2, sym_2_6006
+.globl sym_2_6007
+sym_2_6007: la $2, sym_2_6007
+.globl sym_2_6008
+sym_2_6008: la $2, sym_2_6008
+.globl sym_2_6009
+sym_2_6009: la $2, sym_2_6009
+.globl sym_2_6010
+sym_2_6010: la $2, sym_2_6010
+.globl sym_2_6011
+sym_2_6011: la $2, sym_2_6011
+.globl sym_2_6012
+sym_2_6012: la $2, sym_2_6012
+.globl sym_2_6013
+sym_2_6013: la $2, sym_2_6013
+.globl sym_2_6014
+sym_2_6014: la $2, sym_2_6014
+.globl sym_2_6015
+sym_2_6015: la $2, sym_2_6015
+.globl sym_2_6016
+sym_2_6016: la $2, sym_2_6016
+.globl sym_2_6017
+sym_2_6017: la $2, sym_2_6017
+.globl sym_2_6018
+sym_2_6018: la $2, sym_2_6018
+.globl sym_2_6019
+sym_2_6019: la $2, sym_2_6019
+.globl sym_2_6020
+sym_2_6020: la $2, sym_2_6020
+.globl sym_2_6021
+sym_2_6021: la $2, sym_2_6021
+.globl sym_2_6022
+sym_2_6022: la $2, sym_2_6022
+.globl sym_2_6023
+sym_2_6023: la $2, sym_2_6023
+.globl sym_2_6024
+sym_2_6024: la $2, sym_2_6024
+.globl sym_2_6025
+sym_2_6025: la $2, sym_2_6025
+.globl sym_2_6026
+sym_2_6026: la $2, sym_2_6026
+.globl sym_2_6027
+sym_2_6027: la $2, sym_2_6027
+.globl sym_2_6028
+sym_2_6028: la $2, sym_2_6028
+.globl sym_2_6029
+sym_2_6029: la $2, sym_2_6029
+.globl sym_2_6030
+sym_2_6030: la $2, sym_2_6030
+.globl sym_2_6031
+sym_2_6031: la $2, sym_2_6031
+.globl sym_2_6032
+sym_2_6032: la $2, sym_2_6032
+.globl sym_2_6033
+sym_2_6033: la $2, sym_2_6033
+.globl sym_2_6034
+sym_2_6034: la $2, sym_2_6034
+.globl sym_2_6035
+sym_2_6035: la $2, sym_2_6035
+.globl sym_2_6036
+sym_2_6036: la $2, sym_2_6036
+.globl sym_2_6037
+sym_2_6037: la $2, sym_2_6037
+.globl sym_2_6038
+sym_2_6038: la $2, sym_2_6038
+.globl sym_2_6039
+sym_2_6039: la $2, sym_2_6039
+.globl sym_2_6040
+sym_2_6040: la $2, sym_2_6040
+.globl sym_2_6041
+sym_2_6041: la $2, sym_2_6041
+.globl sym_2_6042
+sym_2_6042: la $2, sym_2_6042
+.globl sym_2_6043
+sym_2_6043: la $2, sym_2_6043
+.globl sym_2_6044
+sym_2_6044: la $2, sym_2_6044
+.globl sym_2_6045
+sym_2_6045: la $2, sym_2_6045
+.globl sym_2_6046
+sym_2_6046: la $2, sym_2_6046
+.globl sym_2_6047
+sym_2_6047: la $2, sym_2_6047
+.globl sym_2_6048
+sym_2_6048: la $2, sym_2_6048
+.globl sym_2_6049
+sym_2_6049: la $2, sym_2_6049
+.globl sym_2_6050
+sym_2_6050: la $2, sym_2_6050
+.globl sym_2_6051
+sym_2_6051: la $2, sym_2_6051
+.globl sym_2_6052
+sym_2_6052: la $2, sym_2_6052
+.globl sym_2_6053
+sym_2_6053: la $2, sym_2_6053
+.globl sym_2_6054
+sym_2_6054: la $2, sym_2_6054
+.globl sym_2_6055
+sym_2_6055: la $2, sym_2_6055
+.globl sym_2_6056
+sym_2_6056: la $2, sym_2_6056
+.globl sym_2_6057
+sym_2_6057: la $2, sym_2_6057
+.globl sym_2_6058
+sym_2_6058: la $2, sym_2_6058
+.globl sym_2_6059
+sym_2_6059: la $2, sym_2_6059
+.globl sym_2_6060
+sym_2_6060: la $2, sym_2_6060
+.globl sym_2_6061
+sym_2_6061: la $2, sym_2_6061
+.globl sym_2_6062
+sym_2_6062: la $2, sym_2_6062
+.globl sym_2_6063
+sym_2_6063: la $2, sym_2_6063
+.globl sym_2_6064
+sym_2_6064: la $2, sym_2_6064
+.globl sym_2_6065
+sym_2_6065: la $2, sym_2_6065
+.globl sym_2_6066
+sym_2_6066: la $2, sym_2_6066
+.globl sym_2_6067
+sym_2_6067: la $2, sym_2_6067
+.globl sym_2_6068
+sym_2_6068: la $2, sym_2_6068
+.globl sym_2_6069
+sym_2_6069: la $2, sym_2_6069
+.globl sym_2_6070
+sym_2_6070: la $2, sym_2_6070
+.globl sym_2_6071
+sym_2_6071: la $2, sym_2_6071
+.globl sym_2_6072
+sym_2_6072: la $2, sym_2_6072
+.globl sym_2_6073
+sym_2_6073: la $2, sym_2_6073
+.globl sym_2_6074
+sym_2_6074: la $2, sym_2_6074
+.globl sym_2_6075
+sym_2_6075: la $2, sym_2_6075
+.globl sym_2_6076
+sym_2_6076: la $2, sym_2_6076
+.globl sym_2_6077
+sym_2_6077: la $2, sym_2_6077
+.globl sym_2_6078
+sym_2_6078: la $2, sym_2_6078
+.globl sym_2_6079
+sym_2_6079: la $2, sym_2_6079
+.globl sym_2_6080
+sym_2_6080: la $2, sym_2_6080
+.globl sym_2_6081
+sym_2_6081: la $2, sym_2_6081
+.globl sym_2_6082
+sym_2_6082: la $2, sym_2_6082
+.globl sym_2_6083
+sym_2_6083: la $2, sym_2_6083
+.globl sym_2_6084
+sym_2_6084: la $2, sym_2_6084
+.globl sym_2_6085
+sym_2_6085: la $2, sym_2_6085
+.globl sym_2_6086
+sym_2_6086: la $2, sym_2_6086
+.globl sym_2_6087
+sym_2_6087: la $2, sym_2_6087
+.globl sym_2_6088
+sym_2_6088: la $2, sym_2_6088
+.globl sym_2_6089
+sym_2_6089: la $2, sym_2_6089
+.globl sym_2_6090
+sym_2_6090: la $2, sym_2_6090
+.globl sym_2_6091
+sym_2_6091: la $2, sym_2_6091
+.globl sym_2_6092
+sym_2_6092: la $2, sym_2_6092
+.globl sym_2_6093
+sym_2_6093: la $2, sym_2_6093
+.globl sym_2_6094
+sym_2_6094: la $2, sym_2_6094
+.globl sym_2_6095
+sym_2_6095: la $2, sym_2_6095
+.globl sym_2_6096
+sym_2_6096: la $2, sym_2_6096
+.globl sym_2_6097
+sym_2_6097: la $2, sym_2_6097
+.globl sym_2_6098
+sym_2_6098: la $2, sym_2_6098
+.globl sym_2_6099
+sym_2_6099: la $2, sym_2_6099
+.globl sym_2_6100
+sym_2_6100: la $2, sym_2_6100
+.globl sym_2_6101
+sym_2_6101: la $2, sym_2_6101
+.globl sym_2_6102
+sym_2_6102: la $2, sym_2_6102
+.globl sym_2_6103
+sym_2_6103: la $2, sym_2_6103
+.globl sym_2_6104
+sym_2_6104: la $2, sym_2_6104
+.globl sym_2_6105
+sym_2_6105: la $2, sym_2_6105
+.globl sym_2_6106
+sym_2_6106: la $2, sym_2_6106
+.globl sym_2_6107
+sym_2_6107: la $2, sym_2_6107
+.globl sym_2_6108
+sym_2_6108: la $2, sym_2_6108
+.globl sym_2_6109
+sym_2_6109: la $2, sym_2_6109
+.globl sym_2_6110
+sym_2_6110: la $2, sym_2_6110
+.globl sym_2_6111
+sym_2_6111: la $2, sym_2_6111
+.globl sym_2_6112
+sym_2_6112: la $2, sym_2_6112
+.globl sym_2_6113
+sym_2_6113: la $2, sym_2_6113
+.globl sym_2_6114
+sym_2_6114: la $2, sym_2_6114
+.globl sym_2_6115
+sym_2_6115: la $2, sym_2_6115
+.globl sym_2_6116
+sym_2_6116: la $2, sym_2_6116
+.globl sym_2_6117
+sym_2_6117: la $2, sym_2_6117
+.globl sym_2_6118
+sym_2_6118: la $2, sym_2_6118
+.globl sym_2_6119
+sym_2_6119: la $2, sym_2_6119
+.globl sym_2_6120
+sym_2_6120: la $2, sym_2_6120
+.globl sym_2_6121
+sym_2_6121: la $2, sym_2_6121
+.globl sym_2_6122
+sym_2_6122: la $2, sym_2_6122
+.globl sym_2_6123
+sym_2_6123: la $2, sym_2_6123
+.globl sym_2_6124
+sym_2_6124: la $2, sym_2_6124
+.globl sym_2_6125
+sym_2_6125: la $2, sym_2_6125
+.globl sym_2_6126
+sym_2_6126: la $2, sym_2_6126
+.globl sym_2_6127
+sym_2_6127: la $2, sym_2_6127
+.globl sym_2_6128
+sym_2_6128: la $2, sym_2_6128
+.globl sym_2_6129
+sym_2_6129: la $2, sym_2_6129
+.globl sym_2_6130
+sym_2_6130: la $2, sym_2_6130
+.globl sym_2_6131
+sym_2_6131: la $2, sym_2_6131
+.globl sym_2_6132
+sym_2_6132: la $2, sym_2_6132
+.globl sym_2_6133
+sym_2_6133: la $2, sym_2_6133
+.globl sym_2_6134
+sym_2_6134: la $2, sym_2_6134
+.globl sym_2_6135
+sym_2_6135: la $2, sym_2_6135
+.globl sym_2_6136
+sym_2_6136: la $2, sym_2_6136
+.globl sym_2_6137
+sym_2_6137: la $2, sym_2_6137
+.globl sym_2_6138
+sym_2_6138: la $2, sym_2_6138
+.globl sym_2_6139
+sym_2_6139: la $2, sym_2_6139
+.globl sym_2_6140
+sym_2_6140: la $2, sym_2_6140
+.globl sym_2_6141
+sym_2_6141: la $2, sym_2_6141
+.globl sym_2_6142
+sym_2_6142: la $2, sym_2_6142
+.globl sym_2_6143
+sym_2_6143: la $2, sym_2_6143
+.globl sym_2_6144
+sym_2_6144: la $2, sym_2_6144
+.globl sym_2_6145
+sym_2_6145: la $2, sym_2_6145
+.globl sym_2_6146
+sym_2_6146: la $2, sym_2_6146
+.globl sym_2_6147
+sym_2_6147: la $2, sym_2_6147
+.globl sym_2_6148
+sym_2_6148: la $2, sym_2_6148
+.globl sym_2_6149
+sym_2_6149: la $2, sym_2_6149
+.globl sym_2_6150
+sym_2_6150: la $2, sym_2_6150
+.globl sym_2_6151
+sym_2_6151: la $2, sym_2_6151
+.globl sym_2_6152
+sym_2_6152: la $2, sym_2_6152
+.globl sym_2_6153
+sym_2_6153: la $2, sym_2_6153
+.globl sym_2_6154
+sym_2_6154: la $2, sym_2_6154
+.globl sym_2_6155
+sym_2_6155: la $2, sym_2_6155
+.globl sym_2_6156
+sym_2_6156: la $2, sym_2_6156
+.globl sym_2_6157
+sym_2_6157: la $2, sym_2_6157
+.globl sym_2_6158
+sym_2_6158: la $2, sym_2_6158
+.globl sym_2_6159
+sym_2_6159: la $2, sym_2_6159
+.globl sym_2_6160
+sym_2_6160: la $2, sym_2_6160
+.globl sym_2_6161
+sym_2_6161: la $2, sym_2_6161
+.globl sym_2_6162
+sym_2_6162: la $2, sym_2_6162
+.globl sym_2_6163
+sym_2_6163: la $2, sym_2_6163
+.globl sym_2_6164
+sym_2_6164: la $2, sym_2_6164
+.globl sym_2_6165
+sym_2_6165: la $2, sym_2_6165
+.globl sym_2_6166
+sym_2_6166: la $2, sym_2_6166
+.globl sym_2_6167
+sym_2_6167: la $2, sym_2_6167
+.globl sym_2_6168
+sym_2_6168: la $2, sym_2_6168
+.globl sym_2_6169
+sym_2_6169: la $2, sym_2_6169
+.globl sym_2_6170
+sym_2_6170: la $2, sym_2_6170
+.globl sym_2_6171
+sym_2_6171: la $2, sym_2_6171
+.globl sym_2_6172
+sym_2_6172: la $2, sym_2_6172
+.globl sym_2_6173
+sym_2_6173: la $2, sym_2_6173
+.globl sym_2_6174
+sym_2_6174: la $2, sym_2_6174
+.globl sym_2_6175
+sym_2_6175: la $2, sym_2_6175
+.globl sym_2_6176
+sym_2_6176: la $2, sym_2_6176
+.globl sym_2_6177
+sym_2_6177: la $2, sym_2_6177
+.globl sym_2_6178
+sym_2_6178: la $2, sym_2_6178
+.globl sym_2_6179
+sym_2_6179: la $2, sym_2_6179
+.globl sym_2_6180
+sym_2_6180: la $2, sym_2_6180
+.globl sym_2_6181
+sym_2_6181: la $2, sym_2_6181
+.globl sym_2_6182
+sym_2_6182: la $2, sym_2_6182
+.globl sym_2_6183
+sym_2_6183: la $2, sym_2_6183
+.globl sym_2_6184
+sym_2_6184: la $2, sym_2_6184
+.globl sym_2_6185
+sym_2_6185: la $2, sym_2_6185
+.globl sym_2_6186
+sym_2_6186: la $2, sym_2_6186
+.globl sym_2_6187
+sym_2_6187: la $2, sym_2_6187
+.globl sym_2_6188
+sym_2_6188: la $2, sym_2_6188
+.globl sym_2_6189
+sym_2_6189: la $2, sym_2_6189
+.globl sym_2_6190
+sym_2_6190: la $2, sym_2_6190
+.globl sym_2_6191
+sym_2_6191: la $2, sym_2_6191
+.globl sym_2_6192
+sym_2_6192: la $2, sym_2_6192
+.globl sym_2_6193
+sym_2_6193: la $2, sym_2_6193
+.globl sym_2_6194
+sym_2_6194: la $2, sym_2_6194
+.globl sym_2_6195
+sym_2_6195: la $2, sym_2_6195
+.globl sym_2_6196
+sym_2_6196: la $2, sym_2_6196
+.globl sym_2_6197
+sym_2_6197: la $2, sym_2_6197
+.globl sym_2_6198
+sym_2_6198: la $2, sym_2_6198
+.globl sym_2_6199
+sym_2_6199: la $2, sym_2_6199
+.globl sym_2_6200
+sym_2_6200: la $2, sym_2_6200
+.globl sym_2_6201
+sym_2_6201: la $2, sym_2_6201
+.globl sym_2_6202
+sym_2_6202: la $2, sym_2_6202
+.globl sym_2_6203
+sym_2_6203: la $2, sym_2_6203
+.globl sym_2_6204
+sym_2_6204: la $2, sym_2_6204
+.globl sym_2_6205
+sym_2_6205: la $2, sym_2_6205
+.globl sym_2_6206
+sym_2_6206: la $2, sym_2_6206
+.globl sym_2_6207
+sym_2_6207: la $2, sym_2_6207
+.globl sym_2_6208
+sym_2_6208: la $2, sym_2_6208
+.globl sym_2_6209
+sym_2_6209: la $2, sym_2_6209
+.globl sym_2_6210
+sym_2_6210: la $2, sym_2_6210
+.globl sym_2_6211
+sym_2_6211: la $2, sym_2_6211
+.globl sym_2_6212
+sym_2_6212: la $2, sym_2_6212
+.globl sym_2_6213
+sym_2_6213: la $2, sym_2_6213
+.globl sym_2_6214
+sym_2_6214: la $2, sym_2_6214
+.globl sym_2_6215
+sym_2_6215: la $2, sym_2_6215
+.globl sym_2_6216
+sym_2_6216: la $2, sym_2_6216
+.globl sym_2_6217
+sym_2_6217: la $2, sym_2_6217
+.globl sym_2_6218
+sym_2_6218: la $2, sym_2_6218
+.globl sym_2_6219
+sym_2_6219: la $2, sym_2_6219
+.globl sym_2_6220
+sym_2_6220: la $2, sym_2_6220
+.globl sym_2_6221
+sym_2_6221: la $2, sym_2_6221
+.globl sym_2_6222
+sym_2_6222: la $2, sym_2_6222
+.globl sym_2_6223
+sym_2_6223: la $2, sym_2_6223
+.globl sym_2_6224
+sym_2_6224: la $2, sym_2_6224
+.globl sym_2_6225
+sym_2_6225: la $2, sym_2_6225
+.globl sym_2_6226
+sym_2_6226: la $2, sym_2_6226
+.globl sym_2_6227
+sym_2_6227: la $2, sym_2_6227
+.globl sym_2_6228
+sym_2_6228: la $2, sym_2_6228
+.globl sym_2_6229
+sym_2_6229: la $2, sym_2_6229
+.globl sym_2_6230
+sym_2_6230: la $2, sym_2_6230
+.globl sym_2_6231
+sym_2_6231: la $2, sym_2_6231
+.globl sym_2_6232
+sym_2_6232: la $2, sym_2_6232
+.globl sym_2_6233
+sym_2_6233: la $2, sym_2_6233
+.globl sym_2_6234
+sym_2_6234: la $2, sym_2_6234
+.globl sym_2_6235
+sym_2_6235: la $2, sym_2_6235
+.globl sym_2_6236
+sym_2_6236: la $2, sym_2_6236
+.globl sym_2_6237
+sym_2_6237: la $2, sym_2_6237
+.globl sym_2_6238
+sym_2_6238: la $2, sym_2_6238
+.globl sym_2_6239
+sym_2_6239: la $2, sym_2_6239
+.globl sym_2_6240
+sym_2_6240: la $2, sym_2_6240
+.globl sym_2_6241
+sym_2_6241: la $2, sym_2_6241
+.globl sym_2_6242
+sym_2_6242: la $2, sym_2_6242
+.globl sym_2_6243
+sym_2_6243: la $2, sym_2_6243
+.globl sym_2_6244
+sym_2_6244: la $2, sym_2_6244
+.globl sym_2_6245
+sym_2_6245: la $2, sym_2_6245
+.globl sym_2_6246
+sym_2_6246: la $2, sym_2_6246
+.globl sym_2_6247
+sym_2_6247: la $2, sym_2_6247
+.globl sym_2_6248
+sym_2_6248: la $2, sym_2_6248
+.globl sym_2_6249
+sym_2_6249: la $2, sym_2_6249
+.globl sym_2_6250
+sym_2_6250: la $2, sym_2_6250
+.globl sym_2_6251
+sym_2_6251: la $2, sym_2_6251
+.globl sym_2_6252
+sym_2_6252: la $2, sym_2_6252
+.globl sym_2_6253
+sym_2_6253: la $2, sym_2_6253
+.globl sym_2_6254
+sym_2_6254: la $2, sym_2_6254
+.globl sym_2_6255
+sym_2_6255: la $2, sym_2_6255
+.globl sym_2_6256
+sym_2_6256: la $2, sym_2_6256
+.globl sym_2_6257
+sym_2_6257: la $2, sym_2_6257
+.globl sym_2_6258
+sym_2_6258: la $2, sym_2_6258
+.globl sym_2_6259
+sym_2_6259: la $2, sym_2_6259
+.globl sym_2_6260
+sym_2_6260: la $2, sym_2_6260
+.globl sym_2_6261
+sym_2_6261: la $2, sym_2_6261
+.globl sym_2_6262
+sym_2_6262: la $2, sym_2_6262
+.globl sym_2_6263
+sym_2_6263: la $2, sym_2_6263
+.globl sym_2_6264
+sym_2_6264: la $2, sym_2_6264
+.globl sym_2_6265
+sym_2_6265: la $2, sym_2_6265
+.globl sym_2_6266
+sym_2_6266: la $2, sym_2_6266
+.globl sym_2_6267
+sym_2_6267: la $2, sym_2_6267
+.globl sym_2_6268
+sym_2_6268: la $2, sym_2_6268
+.globl sym_2_6269
+sym_2_6269: la $2, sym_2_6269
+.globl sym_2_6270
+sym_2_6270: la $2, sym_2_6270
+.globl sym_2_6271
+sym_2_6271: la $2, sym_2_6271
+.globl sym_2_6272
+sym_2_6272: la $2, sym_2_6272
+.globl sym_2_6273
+sym_2_6273: la $2, sym_2_6273
+.globl sym_2_6274
+sym_2_6274: la $2, sym_2_6274
+.globl sym_2_6275
+sym_2_6275: la $2, sym_2_6275
+.globl sym_2_6276
+sym_2_6276: la $2, sym_2_6276
+.globl sym_2_6277
+sym_2_6277: la $2, sym_2_6277
+.globl sym_2_6278
+sym_2_6278: la $2, sym_2_6278
+.globl sym_2_6279
+sym_2_6279: la $2, sym_2_6279
+.globl sym_2_6280
+sym_2_6280: la $2, sym_2_6280
+.globl sym_2_6281
+sym_2_6281: la $2, sym_2_6281
+.globl sym_2_6282
+sym_2_6282: la $2, sym_2_6282
+.globl sym_2_6283
+sym_2_6283: la $2, sym_2_6283
+.globl sym_2_6284
+sym_2_6284: la $2, sym_2_6284
+.globl sym_2_6285
+sym_2_6285: la $2, sym_2_6285
+.globl sym_2_6286
+sym_2_6286: la $2, sym_2_6286
+.globl sym_2_6287
+sym_2_6287: la $2, sym_2_6287
+.globl sym_2_6288
+sym_2_6288: la $2, sym_2_6288
+.globl sym_2_6289
+sym_2_6289: la $2, sym_2_6289
+.globl sym_2_6290
+sym_2_6290: la $2, sym_2_6290
+.globl sym_2_6291
+sym_2_6291: la $2, sym_2_6291
+.globl sym_2_6292
+sym_2_6292: la $2, sym_2_6292
+.globl sym_2_6293
+sym_2_6293: la $2, sym_2_6293
+.globl sym_2_6294
+sym_2_6294: la $2, sym_2_6294
+.globl sym_2_6295
+sym_2_6295: la $2, sym_2_6295
+.globl sym_2_6296
+sym_2_6296: la $2, sym_2_6296
+.globl sym_2_6297
+sym_2_6297: la $2, sym_2_6297
+.globl sym_2_6298
+sym_2_6298: la $2, sym_2_6298
+.globl sym_2_6299
+sym_2_6299: la $2, sym_2_6299
+.globl sym_2_6300
+sym_2_6300: la $2, sym_2_6300
+.globl sym_2_6301
+sym_2_6301: la $2, sym_2_6301
+.globl sym_2_6302
+sym_2_6302: la $2, sym_2_6302
+.globl sym_2_6303
+sym_2_6303: la $2, sym_2_6303
+.globl sym_2_6304
+sym_2_6304: la $2, sym_2_6304
+.globl sym_2_6305
+sym_2_6305: la $2, sym_2_6305
+.globl sym_2_6306
+sym_2_6306: la $2, sym_2_6306
+.globl sym_2_6307
+sym_2_6307: la $2, sym_2_6307
+.globl sym_2_6308
+sym_2_6308: la $2, sym_2_6308
+.globl sym_2_6309
+sym_2_6309: la $2, sym_2_6309
+.globl sym_2_6310
+sym_2_6310: la $2, sym_2_6310
+.globl sym_2_6311
+sym_2_6311: la $2, sym_2_6311
+.globl sym_2_6312
+sym_2_6312: la $2, sym_2_6312
+.globl sym_2_6313
+sym_2_6313: la $2, sym_2_6313
+.globl sym_2_6314
+sym_2_6314: la $2, sym_2_6314
+.globl sym_2_6315
+sym_2_6315: la $2, sym_2_6315
+.globl sym_2_6316
+sym_2_6316: la $2, sym_2_6316
+.globl sym_2_6317
+sym_2_6317: la $2, sym_2_6317
+.globl sym_2_6318
+sym_2_6318: la $2, sym_2_6318
+.globl sym_2_6319
+sym_2_6319: la $2, sym_2_6319
+.globl sym_2_6320
+sym_2_6320: la $2, sym_2_6320
+.globl sym_2_6321
+sym_2_6321: la $2, sym_2_6321
+.globl sym_2_6322
+sym_2_6322: la $2, sym_2_6322
+.globl sym_2_6323
+sym_2_6323: la $2, sym_2_6323
+.globl sym_2_6324
+sym_2_6324: la $2, sym_2_6324
+.globl sym_2_6325
+sym_2_6325: la $2, sym_2_6325
+.globl sym_2_6326
+sym_2_6326: la $2, sym_2_6326
+.globl sym_2_6327
+sym_2_6327: la $2, sym_2_6327
+.globl sym_2_6328
+sym_2_6328: la $2, sym_2_6328
+.globl sym_2_6329
+sym_2_6329: la $2, sym_2_6329
+.globl sym_2_6330
+sym_2_6330: la $2, sym_2_6330
+.globl sym_2_6331
+sym_2_6331: la $2, sym_2_6331
+.globl sym_2_6332
+sym_2_6332: la $2, sym_2_6332
+.globl sym_2_6333
+sym_2_6333: la $2, sym_2_6333
+.globl sym_2_6334
+sym_2_6334: la $2, sym_2_6334
+.globl sym_2_6335
+sym_2_6335: la $2, sym_2_6335
+.globl sym_2_6336
+sym_2_6336: la $2, sym_2_6336
+.globl sym_2_6337
+sym_2_6337: la $2, sym_2_6337
+.globl sym_2_6338
+sym_2_6338: la $2, sym_2_6338
+.globl sym_2_6339
+sym_2_6339: la $2, sym_2_6339
+.globl sym_2_6340
+sym_2_6340: la $2, sym_2_6340
+.globl sym_2_6341
+sym_2_6341: la $2, sym_2_6341
+.globl sym_2_6342
+sym_2_6342: la $2, sym_2_6342
+.globl sym_2_6343
+sym_2_6343: la $2, sym_2_6343
+.globl sym_2_6344
+sym_2_6344: la $2, sym_2_6344
+.globl sym_2_6345
+sym_2_6345: la $2, sym_2_6345
+.globl sym_2_6346
+sym_2_6346: la $2, sym_2_6346
+.globl sym_2_6347
+sym_2_6347: la $2, sym_2_6347
+.globl sym_2_6348
+sym_2_6348: la $2, sym_2_6348
+.globl sym_2_6349
+sym_2_6349: la $2, sym_2_6349
+.globl sym_2_6350
+sym_2_6350: la $2, sym_2_6350
+.globl sym_2_6351
+sym_2_6351: la $2, sym_2_6351
+.globl sym_2_6352
+sym_2_6352: la $2, sym_2_6352
+.globl sym_2_6353
+sym_2_6353: la $2, sym_2_6353
+.globl sym_2_6354
+sym_2_6354: la $2, sym_2_6354
+.globl sym_2_6355
+sym_2_6355: la $2, sym_2_6355
+.globl sym_2_6356
+sym_2_6356: la $2, sym_2_6356
+.globl sym_2_6357
+sym_2_6357: la $2, sym_2_6357
+.globl sym_2_6358
+sym_2_6358: la $2, sym_2_6358
+.globl sym_2_6359
+sym_2_6359: la $2, sym_2_6359
+.globl sym_2_6360
+sym_2_6360: la $2, sym_2_6360
+.globl sym_2_6361
+sym_2_6361: la $2, sym_2_6361
+.globl sym_2_6362
+sym_2_6362: la $2, sym_2_6362
+.globl sym_2_6363
+sym_2_6363: la $2, sym_2_6363
+.globl sym_2_6364
+sym_2_6364: la $2, sym_2_6364
+.globl sym_2_6365
+sym_2_6365: la $2, sym_2_6365
+.globl sym_2_6366
+sym_2_6366: la $2, sym_2_6366
+.globl sym_2_6367
+sym_2_6367: la $2, sym_2_6367
+.globl sym_2_6368
+sym_2_6368: la $2, sym_2_6368
+.globl sym_2_6369
+sym_2_6369: la $2, sym_2_6369
+.globl sym_2_6370
+sym_2_6370: la $2, sym_2_6370
+.globl sym_2_6371
+sym_2_6371: la $2, sym_2_6371
+.globl sym_2_6372
+sym_2_6372: la $2, sym_2_6372
+.globl sym_2_6373
+sym_2_6373: la $2, sym_2_6373
+.globl sym_2_6374
+sym_2_6374: la $2, sym_2_6374
+.globl sym_2_6375
+sym_2_6375: la $2, sym_2_6375
+.globl sym_2_6376
+sym_2_6376: la $2, sym_2_6376
+.globl sym_2_6377
+sym_2_6377: la $2, sym_2_6377
+.globl sym_2_6378
+sym_2_6378: la $2, sym_2_6378
+.globl sym_2_6379
+sym_2_6379: la $2, sym_2_6379
+.globl sym_2_6380
+sym_2_6380: la $2, sym_2_6380
+.globl sym_2_6381
+sym_2_6381: la $2, sym_2_6381
+.globl sym_2_6382
+sym_2_6382: la $2, sym_2_6382
+.globl sym_2_6383
+sym_2_6383: la $2, sym_2_6383
+.globl sym_2_6384
+sym_2_6384: la $2, sym_2_6384
+.globl sym_2_6385
+sym_2_6385: la $2, sym_2_6385
+.globl sym_2_6386
+sym_2_6386: la $2, sym_2_6386
+.globl sym_2_6387
+sym_2_6387: la $2, sym_2_6387
+.globl sym_2_6388
+sym_2_6388: la $2, sym_2_6388
+.globl sym_2_6389
+sym_2_6389: la $2, sym_2_6389
+.globl sym_2_6390
+sym_2_6390: la $2, sym_2_6390
+.globl sym_2_6391
+sym_2_6391: la $2, sym_2_6391
+.globl sym_2_6392
+sym_2_6392: la $2, sym_2_6392
+.globl sym_2_6393
+sym_2_6393: la $2, sym_2_6393
+.globl sym_2_6394
+sym_2_6394: la $2, sym_2_6394
+.globl sym_2_6395
+sym_2_6395: la $2, sym_2_6395
+.globl sym_2_6396
+sym_2_6396: la $2, sym_2_6396
+.globl sym_2_6397
+sym_2_6397: la $2, sym_2_6397
+.globl sym_2_6398
+sym_2_6398: la $2, sym_2_6398
+.globl sym_2_6399
+sym_2_6399: la $2, sym_2_6399
+.globl sym_2_6400
+sym_2_6400: la $2, sym_2_6400
+.globl sym_2_6401
+sym_2_6401: la $2, sym_2_6401
+.globl sym_2_6402
+sym_2_6402: la $2, sym_2_6402
+.globl sym_2_6403
+sym_2_6403: la $2, sym_2_6403
+.globl sym_2_6404
+sym_2_6404: la $2, sym_2_6404
+.globl sym_2_6405
+sym_2_6405: la $2, sym_2_6405
+.globl sym_2_6406
+sym_2_6406: la $2, sym_2_6406
+.globl sym_2_6407
+sym_2_6407: la $2, sym_2_6407
+.globl sym_2_6408
+sym_2_6408: la $2, sym_2_6408
+.globl sym_2_6409
+sym_2_6409: la $2, sym_2_6409
+.globl sym_2_6410
+sym_2_6410: la $2, sym_2_6410
+.globl sym_2_6411
+sym_2_6411: la $2, sym_2_6411
+.globl sym_2_6412
+sym_2_6412: la $2, sym_2_6412
+.globl sym_2_6413
+sym_2_6413: la $2, sym_2_6413
+.globl sym_2_6414
+sym_2_6414: la $2, sym_2_6414
+.globl sym_2_6415
+sym_2_6415: la $2, sym_2_6415
+.globl sym_2_6416
+sym_2_6416: la $2, sym_2_6416
+.globl sym_2_6417
+sym_2_6417: la $2, sym_2_6417
+.globl sym_2_6418
+sym_2_6418: la $2, sym_2_6418
+.globl sym_2_6419
+sym_2_6419: la $2, sym_2_6419
+.globl sym_2_6420
+sym_2_6420: la $2, sym_2_6420
+.globl sym_2_6421
+sym_2_6421: la $2, sym_2_6421
+.globl sym_2_6422
+sym_2_6422: la $2, sym_2_6422
+.globl sym_2_6423
+sym_2_6423: la $2, sym_2_6423
+.globl sym_2_6424
+sym_2_6424: la $2, sym_2_6424
+.globl sym_2_6425
+sym_2_6425: la $2, sym_2_6425
+.globl sym_2_6426
+sym_2_6426: la $2, sym_2_6426
+.globl sym_2_6427
+sym_2_6427: la $2, sym_2_6427
+.globl sym_2_6428
+sym_2_6428: la $2, sym_2_6428
+.globl sym_2_6429
+sym_2_6429: la $2, sym_2_6429
+.globl sym_2_6430
+sym_2_6430: la $2, sym_2_6430
+.globl sym_2_6431
+sym_2_6431: la $2, sym_2_6431
+.globl sym_2_6432
+sym_2_6432: la $2, sym_2_6432
+.globl sym_2_6433
+sym_2_6433: la $2, sym_2_6433
+.globl sym_2_6434
+sym_2_6434: la $2, sym_2_6434
+.globl sym_2_6435
+sym_2_6435: la $2, sym_2_6435
+.globl sym_2_6436
+sym_2_6436: la $2, sym_2_6436
+.globl sym_2_6437
+sym_2_6437: la $2, sym_2_6437
+.globl sym_2_6438
+sym_2_6438: la $2, sym_2_6438
+.globl sym_2_6439
+sym_2_6439: la $2, sym_2_6439
+.globl sym_2_6440
+sym_2_6440: la $2, sym_2_6440
+.globl sym_2_6441
+sym_2_6441: la $2, sym_2_6441
+.globl sym_2_6442
+sym_2_6442: la $2, sym_2_6442
+.globl sym_2_6443
+sym_2_6443: la $2, sym_2_6443
+.globl sym_2_6444
+sym_2_6444: la $2, sym_2_6444
+.globl sym_2_6445
+sym_2_6445: la $2, sym_2_6445
+.globl sym_2_6446
+sym_2_6446: la $2, sym_2_6446
+.globl sym_2_6447
+sym_2_6447: la $2, sym_2_6447
+.globl sym_2_6448
+sym_2_6448: la $2, sym_2_6448
+.globl sym_2_6449
+sym_2_6449: la $2, sym_2_6449
+.globl sym_2_6450
+sym_2_6450: la $2, sym_2_6450
+.globl sym_2_6451
+sym_2_6451: la $2, sym_2_6451
+.globl sym_2_6452
+sym_2_6452: la $2, sym_2_6452
+.globl sym_2_6453
+sym_2_6453: la $2, sym_2_6453
+.globl sym_2_6454
+sym_2_6454: la $2, sym_2_6454
+.globl sym_2_6455
+sym_2_6455: la $2, sym_2_6455
+.globl sym_2_6456
+sym_2_6456: la $2, sym_2_6456
+.globl sym_2_6457
+sym_2_6457: la $2, sym_2_6457
+.globl sym_2_6458
+sym_2_6458: la $2, sym_2_6458
+.globl sym_2_6459
+sym_2_6459: la $2, sym_2_6459
+.globl sym_2_6460
+sym_2_6460: la $2, sym_2_6460
+.globl sym_2_6461
+sym_2_6461: la $2, sym_2_6461
+.globl sym_2_6462
+sym_2_6462: la $2, sym_2_6462
+.globl sym_2_6463
+sym_2_6463: la $2, sym_2_6463
+.globl sym_2_6464
+sym_2_6464: la $2, sym_2_6464
+.globl sym_2_6465
+sym_2_6465: la $2, sym_2_6465
+.globl sym_2_6466
+sym_2_6466: la $2, sym_2_6466
+.globl sym_2_6467
+sym_2_6467: la $2, sym_2_6467
+.globl sym_2_6468
+sym_2_6468: la $2, sym_2_6468
+.globl sym_2_6469
+sym_2_6469: la $2, sym_2_6469
+.globl sym_2_6470
+sym_2_6470: la $2, sym_2_6470
+.globl sym_2_6471
+sym_2_6471: la $2, sym_2_6471
+.globl sym_2_6472
+sym_2_6472: la $2, sym_2_6472
+.globl sym_2_6473
+sym_2_6473: la $2, sym_2_6473
+.globl sym_2_6474
+sym_2_6474: la $2, sym_2_6474
+.globl sym_2_6475
+sym_2_6475: la $2, sym_2_6475
+.globl sym_2_6476
+sym_2_6476: la $2, sym_2_6476
+.globl sym_2_6477
+sym_2_6477: la $2, sym_2_6477
+.globl sym_2_6478
+sym_2_6478: la $2, sym_2_6478
+.globl sym_2_6479
+sym_2_6479: la $2, sym_2_6479
+.globl sym_2_6480
+sym_2_6480: la $2, sym_2_6480
+.globl sym_2_6481
+sym_2_6481: la $2, sym_2_6481
+.globl sym_2_6482
+sym_2_6482: la $2, sym_2_6482
+.globl sym_2_6483
+sym_2_6483: la $2, sym_2_6483
+.globl sym_2_6484
+sym_2_6484: la $2, sym_2_6484
+.globl sym_2_6485
+sym_2_6485: la $2, sym_2_6485
+.globl sym_2_6486
+sym_2_6486: la $2, sym_2_6486
+.globl sym_2_6487
+sym_2_6487: la $2, sym_2_6487
+.globl sym_2_6488
+sym_2_6488: la $2, sym_2_6488
+.globl sym_2_6489
+sym_2_6489: la $2, sym_2_6489
+.globl sym_2_6490
+sym_2_6490: la $2, sym_2_6490
+.globl sym_2_6491
+sym_2_6491: la $2, sym_2_6491
+.globl sym_2_6492
+sym_2_6492: la $2, sym_2_6492
+.globl sym_2_6493
+sym_2_6493: la $2, sym_2_6493
+.globl sym_2_6494
+sym_2_6494: la $2, sym_2_6494
+.globl sym_2_6495
+sym_2_6495: la $2, sym_2_6495
+.globl sym_2_6496
+sym_2_6496: la $2, sym_2_6496
+.globl sym_2_6497
+sym_2_6497: la $2, sym_2_6497
+.globl sym_2_6498
+sym_2_6498: la $2, sym_2_6498
+.globl sym_2_6499
+sym_2_6499: la $2, sym_2_6499
+.globl sym_2_6500
+sym_2_6500: la $2, sym_2_6500
+.globl sym_2_6501
+sym_2_6501: la $2, sym_2_6501
+.globl sym_2_6502
+sym_2_6502: la $2, sym_2_6502
+.globl sym_2_6503
+sym_2_6503: la $2, sym_2_6503
+.globl sym_2_6504
+sym_2_6504: la $2, sym_2_6504
+.globl sym_2_6505
+sym_2_6505: la $2, sym_2_6505
+.globl sym_2_6506
+sym_2_6506: la $2, sym_2_6506
+.globl sym_2_6507
+sym_2_6507: la $2, sym_2_6507
+.globl sym_2_6508
+sym_2_6508: la $2, sym_2_6508
+.globl sym_2_6509
+sym_2_6509: la $2, sym_2_6509
+.globl sym_2_6510
+sym_2_6510: la $2, sym_2_6510
+.globl sym_2_6511
+sym_2_6511: la $2, sym_2_6511
+.globl sym_2_6512
+sym_2_6512: la $2, sym_2_6512
+.globl sym_2_6513
+sym_2_6513: la $2, sym_2_6513
+.globl sym_2_6514
+sym_2_6514: la $2, sym_2_6514
+.globl sym_2_6515
+sym_2_6515: la $2, sym_2_6515
+.globl sym_2_6516
+sym_2_6516: la $2, sym_2_6516
+.globl sym_2_6517
+sym_2_6517: la $2, sym_2_6517
+.globl sym_2_6518
+sym_2_6518: la $2, sym_2_6518
+.globl sym_2_6519
+sym_2_6519: la $2, sym_2_6519
+.globl sym_2_6520
+sym_2_6520: la $2, sym_2_6520
+.globl sym_2_6521
+sym_2_6521: la $2, sym_2_6521
+.globl sym_2_6522
+sym_2_6522: la $2, sym_2_6522
+.globl sym_2_6523
+sym_2_6523: la $2, sym_2_6523
+.globl sym_2_6524
+sym_2_6524: la $2, sym_2_6524
+.globl sym_2_6525
+sym_2_6525: la $2, sym_2_6525
+.globl sym_2_6526
+sym_2_6526: la $2, sym_2_6526
+.globl sym_2_6527
+sym_2_6527: la $2, sym_2_6527
+.globl sym_2_6528
+sym_2_6528: la $2, sym_2_6528
+.globl sym_2_6529
+sym_2_6529: la $2, sym_2_6529
+.globl sym_2_6530
+sym_2_6530: la $2, sym_2_6530
+.globl sym_2_6531
+sym_2_6531: la $2, sym_2_6531
+.globl sym_2_6532
+sym_2_6532: la $2, sym_2_6532
+.globl sym_2_6533
+sym_2_6533: la $2, sym_2_6533
+.globl sym_2_6534
+sym_2_6534: la $2, sym_2_6534
+.globl sym_2_6535
+sym_2_6535: la $2, sym_2_6535
+.globl sym_2_6536
+sym_2_6536: la $2, sym_2_6536
+.globl sym_2_6537
+sym_2_6537: la $2, sym_2_6537
+.globl sym_2_6538
+sym_2_6538: la $2, sym_2_6538
+.globl sym_2_6539
+sym_2_6539: la $2, sym_2_6539
+.globl sym_2_6540
+sym_2_6540: la $2, sym_2_6540
+.globl sym_2_6541
+sym_2_6541: la $2, sym_2_6541
+.globl sym_2_6542
+sym_2_6542: la $2, sym_2_6542
+.globl sym_2_6543
+sym_2_6543: la $2, sym_2_6543
+.globl sym_2_6544
+sym_2_6544: la $2, sym_2_6544
+.globl sym_2_6545
+sym_2_6545: la $2, sym_2_6545
+.globl sym_2_6546
+sym_2_6546: la $2, sym_2_6546
+.globl sym_2_6547
+sym_2_6547: la $2, sym_2_6547
+.globl sym_2_6548
+sym_2_6548: la $2, sym_2_6548
+.globl sym_2_6549
+sym_2_6549: la $2, sym_2_6549
+.globl sym_2_6550
+sym_2_6550: la $2, sym_2_6550
+.globl sym_2_6551
+sym_2_6551: la $2, sym_2_6551
+.globl sym_2_6552
+sym_2_6552: la $2, sym_2_6552
+.globl sym_2_6553
+sym_2_6553: la $2, sym_2_6553
+.globl sym_2_6554
+sym_2_6554: la $2, sym_2_6554
+.globl sym_2_6555
+sym_2_6555: la $2, sym_2_6555
+.globl sym_2_6556
+sym_2_6556: la $2, sym_2_6556
+.globl sym_2_6557
+sym_2_6557: la $2, sym_2_6557
+.globl sym_2_6558
+sym_2_6558: la $2, sym_2_6558
+.globl sym_2_6559
+sym_2_6559: la $2, sym_2_6559
+.globl sym_2_6560
+sym_2_6560: la $2, sym_2_6560
+.globl sym_2_6561
+sym_2_6561: la $2, sym_2_6561
+.globl sym_2_6562
+sym_2_6562: la $2, sym_2_6562
+.globl sym_2_6563
+sym_2_6563: la $2, sym_2_6563
+.globl sym_2_6564
+sym_2_6564: la $2, sym_2_6564
+.globl sym_2_6565
+sym_2_6565: la $2, sym_2_6565
+.globl sym_2_6566
+sym_2_6566: la $2, sym_2_6566
+.globl sym_2_6567
+sym_2_6567: la $2, sym_2_6567
+.globl sym_2_6568
+sym_2_6568: la $2, sym_2_6568
+.globl sym_2_6569
+sym_2_6569: la $2, sym_2_6569
+.globl sym_2_6570
+sym_2_6570: la $2, sym_2_6570
+.globl sym_2_6571
+sym_2_6571: la $2, sym_2_6571
+.globl sym_2_6572
+sym_2_6572: la $2, sym_2_6572
+.globl sym_2_6573
+sym_2_6573: la $2, sym_2_6573
+.globl sym_2_6574
+sym_2_6574: la $2, sym_2_6574
+.globl sym_2_6575
+sym_2_6575: la $2, sym_2_6575
+.globl sym_2_6576
+sym_2_6576: la $2, sym_2_6576
+.globl sym_2_6577
+sym_2_6577: la $2, sym_2_6577
+.globl sym_2_6578
+sym_2_6578: la $2, sym_2_6578
+.globl sym_2_6579
+sym_2_6579: la $2, sym_2_6579
+.globl sym_2_6580
+sym_2_6580: la $2, sym_2_6580
+.globl sym_2_6581
+sym_2_6581: la $2, sym_2_6581
+.globl sym_2_6582
+sym_2_6582: la $2, sym_2_6582
+.globl sym_2_6583
+sym_2_6583: la $2, sym_2_6583
+.globl sym_2_6584
+sym_2_6584: la $2, sym_2_6584
+.globl sym_2_6585
+sym_2_6585: la $2, sym_2_6585
+.globl sym_2_6586
+sym_2_6586: la $2, sym_2_6586
+.globl sym_2_6587
+sym_2_6587: la $2, sym_2_6587
+.globl sym_2_6588
+sym_2_6588: la $2, sym_2_6588
+.globl sym_2_6589
+sym_2_6589: la $2, sym_2_6589
+.globl sym_2_6590
+sym_2_6590: la $2, sym_2_6590
+.globl sym_2_6591
+sym_2_6591: la $2, sym_2_6591
+.globl sym_2_6592
+sym_2_6592: la $2, sym_2_6592
+.globl sym_2_6593
+sym_2_6593: la $2, sym_2_6593
+.globl sym_2_6594
+sym_2_6594: la $2, sym_2_6594
+.globl sym_2_6595
+sym_2_6595: la $2, sym_2_6595
+.globl sym_2_6596
+sym_2_6596: la $2, sym_2_6596
+.globl sym_2_6597
+sym_2_6597: la $2, sym_2_6597
+.globl sym_2_6598
+sym_2_6598: la $2, sym_2_6598
+.globl sym_2_6599
+sym_2_6599: la $2, sym_2_6599
+.globl sym_2_6600
+sym_2_6600: la $2, sym_2_6600
+.globl sym_2_6601
+sym_2_6601: la $2, sym_2_6601
+.globl sym_2_6602
+sym_2_6602: la $2, sym_2_6602
+.globl sym_2_6603
+sym_2_6603: la $2, sym_2_6603
+.globl sym_2_6604
+sym_2_6604: la $2, sym_2_6604
+.globl sym_2_6605
+sym_2_6605: la $2, sym_2_6605
+.globl sym_2_6606
+sym_2_6606: la $2, sym_2_6606
+.globl sym_2_6607
+sym_2_6607: la $2, sym_2_6607
+.globl sym_2_6608
+sym_2_6608: la $2, sym_2_6608
+.globl sym_2_6609
+sym_2_6609: la $2, sym_2_6609
+.globl sym_2_6610
+sym_2_6610: la $2, sym_2_6610
+.globl sym_2_6611
+sym_2_6611: la $2, sym_2_6611
+.globl sym_2_6612
+sym_2_6612: la $2, sym_2_6612
+.globl sym_2_6613
+sym_2_6613: la $2, sym_2_6613
+.globl sym_2_6614
+sym_2_6614: la $2, sym_2_6614
+.globl sym_2_6615
+sym_2_6615: la $2, sym_2_6615
+.globl sym_2_6616
+sym_2_6616: la $2, sym_2_6616
+.globl sym_2_6617
+sym_2_6617: la $2, sym_2_6617
+.globl sym_2_6618
+sym_2_6618: la $2, sym_2_6618
+.globl sym_2_6619
+sym_2_6619: la $2, sym_2_6619
+.globl sym_2_6620
+sym_2_6620: la $2, sym_2_6620
+.globl sym_2_6621
+sym_2_6621: la $2, sym_2_6621
+.globl sym_2_6622
+sym_2_6622: la $2, sym_2_6622
+.globl sym_2_6623
+sym_2_6623: la $2, sym_2_6623
+.globl sym_2_6624
+sym_2_6624: la $2, sym_2_6624
+.globl sym_2_6625
+sym_2_6625: la $2, sym_2_6625
+.globl sym_2_6626
+sym_2_6626: la $2, sym_2_6626
+.globl sym_2_6627
+sym_2_6627: la $2, sym_2_6627
+.globl sym_2_6628
+sym_2_6628: la $2, sym_2_6628
+.globl sym_2_6629
+sym_2_6629: la $2, sym_2_6629
+.globl sym_2_6630
+sym_2_6630: la $2, sym_2_6630
+.globl sym_2_6631
+sym_2_6631: la $2, sym_2_6631
+.globl sym_2_6632
+sym_2_6632: la $2, sym_2_6632
+.globl sym_2_6633
+sym_2_6633: la $2, sym_2_6633
+.globl sym_2_6634
+sym_2_6634: la $2, sym_2_6634
+.globl sym_2_6635
+sym_2_6635: la $2, sym_2_6635
+.globl sym_2_6636
+sym_2_6636: la $2, sym_2_6636
+.globl sym_2_6637
+sym_2_6637: la $2, sym_2_6637
+.globl sym_2_6638
+sym_2_6638: la $2, sym_2_6638
+.globl sym_2_6639
+sym_2_6639: la $2, sym_2_6639
+.globl sym_2_6640
+sym_2_6640: la $2, sym_2_6640
+.globl sym_2_6641
+sym_2_6641: la $2, sym_2_6641
+.globl sym_2_6642
+sym_2_6642: la $2, sym_2_6642
+.globl sym_2_6643
+sym_2_6643: la $2, sym_2_6643
+.globl sym_2_6644
+sym_2_6644: la $2, sym_2_6644
+.globl sym_2_6645
+sym_2_6645: la $2, sym_2_6645
+.globl sym_2_6646
+sym_2_6646: la $2, sym_2_6646
+.globl sym_2_6647
+sym_2_6647: la $2, sym_2_6647
+.globl sym_2_6648
+sym_2_6648: la $2, sym_2_6648
+.globl sym_2_6649
+sym_2_6649: la $2, sym_2_6649
+.globl sym_2_6650
+sym_2_6650: la $2, sym_2_6650
+.globl sym_2_6651
+sym_2_6651: la $2, sym_2_6651
+.globl sym_2_6652
+sym_2_6652: la $2, sym_2_6652
+.globl sym_2_6653
+sym_2_6653: la $2, sym_2_6653
+.globl sym_2_6654
+sym_2_6654: la $2, sym_2_6654
+.globl sym_2_6655
+sym_2_6655: la $2, sym_2_6655
+.globl sym_2_6656
+sym_2_6656: la $2, sym_2_6656
+.globl sym_2_6657
+sym_2_6657: la $2, sym_2_6657
+.globl sym_2_6658
+sym_2_6658: la $2, sym_2_6658
+.globl sym_2_6659
+sym_2_6659: la $2, sym_2_6659
+.globl sym_2_6660
+sym_2_6660: la $2, sym_2_6660
+.globl sym_2_6661
+sym_2_6661: la $2, sym_2_6661
+.globl sym_2_6662
+sym_2_6662: la $2, sym_2_6662
+.globl sym_2_6663
+sym_2_6663: la $2, sym_2_6663
+.globl sym_2_6664
+sym_2_6664: la $2, sym_2_6664
+.globl sym_2_6665
+sym_2_6665: la $2, sym_2_6665
+.globl sym_2_6666
+sym_2_6666: la $2, sym_2_6666
+.globl sym_2_6667
+sym_2_6667: la $2, sym_2_6667
+.globl sym_2_6668
+sym_2_6668: la $2, sym_2_6668
+.globl sym_2_6669
+sym_2_6669: la $2, sym_2_6669
+.globl sym_2_6670
+sym_2_6670: la $2, sym_2_6670
+.globl sym_2_6671
+sym_2_6671: la $2, sym_2_6671
+.globl sym_2_6672
+sym_2_6672: la $2, sym_2_6672
+.globl sym_2_6673
+sym_2_6673: la $2, sym_2_6673
+.globl sym_2_6674
+sym_2_6674: la $2, sym_2_6674
+.globl sym_2_6675
+sym_2_6675: la $2, sym_2_6675
+.globl sym_2_6676
+sym_2_6676: la $2, sym_2_6676
+.globl sym_2_6677
+sym_2_6677: la $2, sym_2_6677
+.globl sym_2_6678
+sym_2_6678: la $2, sym_2_6678
+.globl sym_2_6679
+sym_2_6679: la $2, sym_2_6679
+.globl sym_2_6680
+sym_2_6680: la $2, sym_2_6680
+.globl sym_2_6681
+sym_2_6681: la $2, sym_2_6681
+.globl sym_2_6682
+sym_2_6682: la $2, sym_2_6682
+.globl sym_2_6683
+sym_2_6683: la $2, sym_2_6683
+.globl sym_2_6684
+sym_2_6684: la $2, sym_2_6684
+.globl sym_2_6685
+sym_2_6685: la $2, sym_2_6685
+.globl sym_2_6686
+sym_2_6686: la $2, sym_2_6686
+.globl sym_2_6687
+sym_2_6687: la $2, sym_2_6687
+.globl sym_2_6688
+sym_2_6688: la $2, sym_2_6688
+.globl sym_2_6689
+sym_2_6689: la $2, sym_2_6689
+.globl sym_2_6690
+sym_2_6690: la $2, sym_2_6690
+.globl sym_2_6691
+sym_2_6691: la $2, sym_2_6691
+.globl sym_2_6692
+sym_2_6692: la $2, sym_2_6692
+.globl sym_2_6693
+sym_2_6693: la $2, sym_2_6693
+.globl sym_2_6694
+sym_2_6694: la $2, sym_2_6694
+.globl sym_2_6695
+sym_2_6695: la $2, sym_2_6695
+.globl sym_2_6696
+sym_2_6696: la $2, sym_2_6696
+.globl sym_2_6697
+sym_2_6697: la $2, sym_2_6697
+.globl sym_2_6698
+sym_2_6698: la $2, sym_2_6698
+.globl sym_2_6699
+sym_2_6699: la $2, sym_2_6699
+.globl sym_2_6700
+sym_2_6700: la $2, sym_2_6700
+.globl sym_2_6701
+sym_2_6701: la $2, sym_2_6701
+.globl sym_2_6702
+sym_2_6702: la $2, sym_2_6702
+.globl sym_2_6703
+sym_2_6703: la $2, sym_2_6703
+.globl sym_2_6704
+sym_2_6704: la $2, sym_2_6704
+.globl sym_2_6705
+sym_2_6705: la $2, sym_2_6705
+.globl sym_2_6706
+sym_2_6706: la $2, sym_2_6706
+.globl sym_2_6707
+sym_2_6707: la $2, sym_2_6707
+.globl sym_2_6708
+sym_2_6708: la $2, sym_2_6708
+.globl sym_2_6709
+sym_2_6709: la $2, sym_2_6709
+.globl sym_2_6710
+sym_2_6710: la $2, sym_2_6710
+.globl sym_2_6711
+sym_2_6711: la $2, sym_2_6711
+.globl sym_2_6712
+sym_2_6712: la $2, sym_2_6712
+.globl sym_2_6713
+sym_2_6713: la $2, sym_2_6713
+.globl sym_2_6714
+sym_2_6714: la $2, sym_2_6714
+.globl sym_2_6715
+sym_2_6715: la $2, sym_2_6715
+.globl sym_2_6716
+sym_2_6716: la $2, sym_2_6716
+.globl sym_2_6717
+sym_2_6717: la $2, sym_2_6717
+.globl sym_2_6718
+sym_2_6718: la $2, sym_2_6718
+.globl sym_2_6719
+sym_2_6719: la $2, sym_2_6719
+.globl sym_2_6720
+sym_2_6720: la $2, sym_2_6720
+.globl sym_2_6721
+sym_2_6721: la $2, sym_2_6721
+.globl sym_2_6722
+sym_2_6722: la $2, sym_2_6722
+.globl sym_2_6723
+sym_2_6723: la $2, sym_2_6723
+.globl sym_2_6724
+sym_2_6724: la $2, sym_2_6724
+.globl sym_2_6725
+sym_2_6725: la $2, sym_2_6725
+.globl sym_2_6726
+sym_2_6726: la $2, sym_2_6726
+.globl sym_2_6727
+sym_2_6727: la $2, sym_2_6727
+.globl sym_2_6728
+sym_2_6728: la $2, sym_2_6728
+.globl sym_2_6729
+sym_2_6729: la $2, sym_2_6729
+.globl sym_2_6730
+sym_2_6730: la $2, sym_2_6730
+.globl sym_2_6731
+sym_2_6731: la $2, sym_2_6731
+.globl sym_2_6732
+sym_2_6732: la $2, sym_2_6732
+.globl sym_2_6733
+sym_2_6733: la $2, sym_2_6733
+.globl sym_2_6734
+sym_2_6734: la $2, sym_2_6734
+.globl sym_2_6735
+sym_2_6735: la $2, sym_2_6735
+.globl sym_2_6736
+sym_2_6736: la $2, sym_2_6736
+.globl sym_2_6737
+sym_2_6737: la $2, sym_2_6737
+.globl sym_2_6738
+sym_2_6738: la $2, sym_2_6738
+.globl sym_2_6739
+sym_2_6739: la $2, sym_2_6739
+.globl sym_2_6740
+sym_2_6740: la $2, sym_2_6740
+.globl sym_2_6741
+sym_2_6741: la $2, sym_2_6741
+.globl sym_2_6742
+sym_2_6742: la $2, sym_2_6742
+.globl sym_2_6743
+sym_2_6743: la $2, sym_2_6743
+.globl sym_2_6744
+sym_2_6744: la $2, sym_2_6744
+.globl sym_2_6745
+sym_2_6745: la $2, sym_2_6745
+.globl sym_2_6746
+sym_2_6746: la $2, sym_2_6746
+.globl sym_2_6747
+sym_2_6747: la $2, sym_2_6747
+.globl sym_2_6748
+sym_2_6748: la $2, sym_2_6748
+.globl sym_2_6749
+sym_2_6749: la $2, sym_2_6749
+.globl sym_2_6750
+sym_2_6750: la $2, sym_2_6750
+.globl sym_2_6751
+sym_2_6751: la $2, sym_2_6751
+.globl sym_2_6752
+sym_2_6752: la $2, sym_2_6752
+.globl sym_2_6753
+sym_2_6753: la $2, sym_2_6753
+.globl sym_2_6754
+sym_2_6754: la $2, sym_2_6754
+.globl sym_2_6755
+sym_2_6755: la $2, sym_2_6755
+.globl sym_2_6756
+sym_2_6756: la $2, sym_2_6756
+.globl sym_2_6757
+sym_2_6757: la $2, sym_2_6757
+.globl sym_2_6758
+sym_2_6758: la $2, sym_2_6758
+.globl sym_2_6759
+sym_2_6759: la $2, sym_2_6759
+.globl sym_2_6760
+sym_2_6760: la $2, sym_2_6760
+.globl sym_2_6761
+sym_2_6761: la $2, sym_2_6761
+.globl sym_2_6762
+sym_2_6762: la $2, sym_2_6762
+.globl sym_2_6763
+sym_2_6763: la $2, sym_2_6763
+.globl sym_2_6764
+sym_2_6764: la $2, sym_2_6764
+.globl sym_2_6765
+sym_2_6765: la $2, sym_2_6765
+.globl sym_2_6766
+sym_2_6766: la $2, sym_2_6766
+.globl sym_2_6767
+sym_2_6767: la $2, sym_2_6767
+.globl sym_2_6768
+sym_2_6768: la $2, sym_2_6768
+.globl sym_2_6769
+sym_2_6769: la $2, sym_2_6769
+.globl sym_2_6770
+sym_2_6770: la $2, sym_2_6770
+.globl sym_2_6771
+sym_2_6771: la $2, sym_2_6771
+.globl sym_2_6772
+sym_2_6772: la $2, sym_2_6772
+.globl sym_2_6773
+sym_2_6773: la $2, sym_2_6773
+.globl sym_2_6774
+sym_2_6774: la $2, sym_2_6774
+.globl sym_2_6775
+sym_2_6775: la $2, sym_2_6775
+.globl sym_2_6776
+sym_2_6776: la $2, sym_2_6776
+.globl sym_2_6777
+sym_2_6777: la $2, sym_2_6777
+.globl sym_2_6778
+sym_2_6778: la $2, sym_2_6778
+.globl sym_2_6779
+sym_2_6779: la $2, sym_2_6779
+.globl sym_2_6780
+sym_2_6780: la $2, sym_2_6780
+.globl sym_2_6781
+sym_2_6781: la $2, sym_2_6781
+.globl sym_2_6782
+sym_2_6782: la $2, sym_2_6782
+.globl sym_2_6783
+sym_2_6783: la $2, sym_2_6783
+.globl sym_2_6784
+sym_2_6784: la $2, sym_2_6784
+.globl sym_2_6785
+sym_2_6785: la $2, sym_2_6785
+.globl sym_2_6786
+sym_2_6786: la $2, sym_2_6786
+.globl sym_2_6787
+sym_2_6787: la $2, sym_2_6787
+.globl sym_2_6788
+sym_2_6788: la $2, sym_2_6788
+.globl sym_2_6789
+sym_2_6789: la $2, sym_2_6789
+.globl sym_2_6790
+sym_2_6790: la $2, sym_2_6790
+.globl sym_2_6791
+sym_2_6791: la $2, sym_2_6791
+.globl sym_2_6792
+sym_2_6792: la $2, sym_2_6792
+.globl sym_2_6793
+sym_2_6793: la $2, sym_2_6793
+.globl sym_2_6794
+sym_2_6794: la $2, sym_2_6794
+.globl sym_2_6795
+sym_2_6795: la $2, sym_2_6795
+.globl sym_2_6796
+sym_2_6796: la $2, sym_2_6796
+.globl sym_2_6797
+sym_2_6797: la $2, sym_2_6797
+.globl sym_2_6798
+sym_2_6798: la $2, sym_2_6798
+.globl sym_2_6799
+sym_2_6799: la $2, sym_2_6799
+.globl sym_2_6800
+sym_2_6800: la $2, sym_2_6800
+.globl sym_2_6801
+sym_2_6801: la $2, sym_2_6801
+.globl sym_2_6802
+sym_2_6802: la $2, sym_2_6802
+.globl sym_2_6803
+sym_2_6803: la $2, sym_2_6803
+.globl sym_2_6804
+sym_2_6804: la $2, sym_2_6804
+.globl sym_2_6805
+sym_2_6805: la $2, sym_2_6805
+.globl sym_2_6806
+sym_2_6806: la $2, sym_2_6806
+.globl sym_2_6807
+sym_2_6807: la $2, sym_2_6807
+.globl sym_2_6808
+sym_2_6808: la $2, sym_2_6808
+.globl sym_2_6809
+sym_2_6809: la $2, sym_2_6809
+.globl sym_2_6810
+sym_2_6810: la $2, sym_2_6810
+.globl sym_2_6811
+sym_2_6811: la $2, sym_2_6811
+.globl sym_2_6812
+sym_2_6812: la $2, sym_2_6812
+.globl sym_2_6813
+sym_2_6813: la $2, sym_2_6813
+.globl sym_2_6814
+sym_2_6814: la $2, sym_2_6814
+.globl sym_2_6815
+sym_2_6815: la $2, sym_2_6815
+.globl sym_2_6816
+sym_2_6816: la $2, sym_2_6816
+.globl sym_2_6817
+sym_2_6817: la $2, sym_2_6817
+.globl sym_2_6818
+sym_2_6818: la $2, sym_2_6818
+.globl sym_2_6819
+sym_2_6819: la $2, sym_2_6819
+.globl sym_2_6820
+sym_2_6820: la $2, sym_2_6820
+.globl sym_2_6821
+sym_2_6821: la $2, sym_2_6821
+.globl sym_2_6822
+sym_2_6822: la $2, sym_2_6822
+.globl sym_2_6823
+sym_2_6823: la $2, sym_2_6823
+.globl sym_2_6824
+sym_2_6824: la $2, sym_2_6824
+.globl sym_2_6825
+sym_2_6825: la $2, sym_2_6825
+.globl sym_2_6826
+sym_2_6826: la $2, sym_2_6826
+.globl sym_2_6827
+sym_2_6827: la $2, sym_2_6827
+.globl sym_2_6828
+sym_2_6828: la $2, sym_2_6828
+.globl sym_2_6829
+sym_2_6829: la $2, sym_2_6829
+.globl sym_2_6830
+sym_2_6830: la $2, sym_2_6830
+.globl sym_2_6831
+sym_2_6831: la $2, sym_2_6831
+.globl sym_2_6832
+sym_2_6832: la $2, sym_2_6832
+.globl sym_2_6833
+sym_2_6833: la $2, sym_2_6833
+.globl sym_2_6834
+sym_2_6834: la $2, sym_2_6834
+.globl sym_2_6835
+sym_2_6835: la $2, sym_2_6835
+.globl sym_2_6836
+sym_2_6836: la $2, sym_2_6836
+.globl sym_2_6837
+sym_2_6837: la $2, sym_2_6837
+.globl sym_2_6838
+sym_2_6838: la $2, sym_2_6838
+.globl sym_2_6839
+sym_2_6839: la $2, sym_2_6839
+.globl sym_2_6840
+sym_2_6840: la $2, sym_2_6840
+.globl sym_2_6841
+sym_2_6841: la $2, sym_2_6841
+.globl sym_2_6842
+sym_2_6842: la $2, sym_2_6842
+.globl sym_2_6843
+sym_2_6843: la $2, sym_2_6843
+.globl sym_2_6844
+sym_2_6844: la $2, sym_2_6844
+.globl sym_2_6845
+sym_2_6845: la $2, sym_2_6845
+.globl sym_2_6846
+sym_2_6846: la $2, sym_2_6846
+.globl sym_2_6847
+sym_2_6847: la $2, sym_2_6847
+.globl sym_2_6848
+sym_2_6848: la $2, sym_2_6848
+.globl sym_2_6849
+sym_2_6849: la $2, sym_2_6849
+.globl sym_2_6850
+sym_2_6850: la $2, sym_2_6850
+.globl sym_2_6851
+sym_2_6851: la $2, sym_2_6851
+.globl sym_2_6852
+sym_2_6852: la $2, sym_2_6852
+.globl sym_2_6853
+sym_2_6853: la $2, sym_2_6853
+.globl sym_2_6854
+sym_2_6854: la $2, sym_2_6854
+.globl sym_2_6855
+sym_2_6855: la $2, sym_2_6855
+.globl sym_2_6856
+sym_2_6856: la $2, sym_2_6856
+.globl sym_2_6857
+sym_2_6857: la $2, sym_2_6857
+.globl sym_2_6858
+sym_2_6858: la $2, sym_2_6858
+.globl sym_2_6859
+sym_2_6859: la $2, sym_2_6859
+.globl sym_2_6860
+sym_2_6860: la $2, sym_2_6860
+.globl sym_2_6861
+sym_2_6861: la $2, sym_2_6861
+.globl sym_2_6862
+sym_2_6862: la $2, sym_2_6862
+.globl sym_2_6863
+sym_2_6863: la $2, sym_2_6863
+.globl sym_2_6864
+sym_2_6864: la $2, sym_2_6864
+.globl sym_2_6865
+sym_2_6865: la $2, sym_2_6865
+.globl sym_2_6866
+sym_2_6866: la $2, sym_2_6866
+.globl sym_2_6867
+sym_2_6867: la $2, sym_2_6867
+.globl sym_2_6868
+sym_2_6868: la $2, sym_2_6868
+.globl sym_2_6869
+sym_2_6869: la $2, sym_2_6869
+.globl sym_2_6870
+sym_2_6870: la $2, sym_2_6870
+.globl sym_2_6871
+sym_2_6871: la $2, sym_2_6871
+.globl sym_2_6872
+sym_2_6872: la $2, sym_2_6872
+.globl sym_2_6873
+sym_2_6873: la $2, sym_2_6873
+.globl sym_2_6874
+sym_2_6874: la $2, sym_2_6874
+.globl sym_2_6875
+sym_2_6875: la $2, sym_2_6875
+.globl sym_2_6876
+sym_2_6876: la $2, sym_2_6876
+.globl sym_2_6877
+sym_2_6877: la $2, sym_2_6877
+.globl sym_2_6878
+sym_2_6878: la $2, sym_2_6878
+.globl sym_2_6879
+sym_2_6879: la $2, sym_2_6879
+.globl sym_2_6880
+sym_2_6880: la $2, sym_2_6880
+.globl sym_2_6881
+sym_2_6881: la $2, sym_2_6881
+.globl sym_2_6882
+sym_2_6882: la $2, sym_2_6882
+.globl sym_2_6883
+sym_2_6883: la $2, sym_2_6883
+.globl sym_2_6884
+sym_2_6884: la $2, sym_2_6884
+.globl sym_2_6885
+sym_2_6885: la $2, sym_2_6885
+.globl sym_2_6886
+sym_2_6886: la $2, sym_2_6886
+.globl sym_2_6887
+sym_2_6887: la $2, sym_2_6887
+.globl sym_2_6888
+sym_2_6888: la $2, sym_2_6888
+.globl sym_2_6889
+sym_2_6889: la $2, sym_2_6889
+.globl sym_2_6890
+sym_2_6890: la $2, sym_2_6890
+.globl sym_2_6891
+sym_2_6891: la $2, sym_2_6891
+.globl sym_2_6892
+sym_2_6892: la $2, sym_2_6892
+.globl sym_2_6893
+sym_2_6893: la $2, sym_2_6893
+.globl sym_2_6894
+sym_2_6894: la $2, sym_2_6894
+.globl sym_2_6895
+sym_2_6895: la $2, sym_2_6895
+.globl sym_2_6896
+sym_2_6896: la $2, sym_2_6896
+.globl sym_2_6897
+sym_2_6897: la $2, sym_2_6897
+.globl sym_2_6898
+sym_2_6898: la $2, sym_2_6898
+.globl sym_2_6899
+sym_2_6899: la $2, sym_2_6899
+.globl sym_2_6900
+sym_2_6900: la $2, sym_2_6900
+.globl sym_2_6901
+sym_2_6901: la $2, sym_2_6901
+.globl sym_2_6902
+sym_2_6902: la $2, sym_2_6902
+.globl sym_2_6903
+sym_2_6903: la $2, sym_2_6903
+.globl sym_2_6904
+sym_2_6904: la $2, sym_2_6904
+.globl sym_2_6905
+sym_2_6905: la $2, sym_2_6905
+.globl sym_2_6906
+sym_2_6906: la $2, sym_2_6906
+.globl sym_2_6907
+sym_2_6907: la $2, sym_2_6907
+.globl sym_2_6908
+sym_2_6908: la $2, sym_2_6908
+.globl sym_2_6909
+sym_2_6909: la $2, sym_2_6909
+.globl sym_2_6910
+sym_2_6910: la $2, sym_2_6910
+.globl sym_2_6911
+sym_2_6911: la $2, sym_2_6911
+.globl sym_2_6912
+sym_2_6912: la $2, sym_2_6912
+.globl sym_2_6913
+sym_2_6913: la $2, sym_2_6913
+.globl sym_2_6914
+sym_2_6914: la $2, sym_2_6914
+.globl sym_2_6915
+sym_2_6915: la $2, sym_2_6915
+.globl sym_2_6916
+sym_2_6916: la $2, sym_2_6916
+.globl sym_2_6917
+sym_2_6917: la $2, sym_2_6917
+.globl sym_2_6918
+sym_2_6918: la $2, sym_2_6918
+.globl sym_2_6919
+sym_2_6919: la $2, sym_2_6919
+.globl sym_2_6920
+sym_2_6920: la $2, sym_2_6920
+.globl sym_2_6921
+sym_2_6921: la $2, sym_2_6921
+.globl sym_2_6922
+sym_2_6922: la $2, sym_2_6922
+.globl sym_2_6923
+sym_2_6923: la $2, sym_2_6923
+.globl sym_2_6924
+sym_2_6924: la $2, sym_2_6924
+.globl sym_2_6925
+sym_2_6925: la $2, sym_2_6925
+.globl sym_2_6926
+sym_2_6926: la $2, sym_2_6926
+.globl sym_2_6927
+sym_2_6927: la $2, sym_2_6927
+.globl sym_2_6928
+sym_2_6928: la $2, sym_2_6928
+.globl sym_2_6929
+sym_2_6929: la $2, sym_2_6929
+.globl sym_2_6930
+sym_2_6930: la $2, sym_2_6930
+.globl sym_2_6931
+sym_2_6931: la $2, sym_2_6931
+.globl sym_2_6932
+sym_2_6932: la $2, sym_2_6932
+.globl sym_2_6933
+sym_2_6933: la $2, sym_2_6933
+.globl sym_2_6934
+sym_2_6934: la $2, sym_2_6934
+.globl sym_2_6935
+sym_2_6935: la $2, sym_2_6935
+.globl sym_2_6936
+sym_2_6936: la $2, sym_2_6936
+.globl sym_2_6937
+sym_2_6937: la $2, sym_2_6937
+.globl sym_2_6938
+sym_2_6938: la $2, sym_2_6938
+.globl sym_2_6939
+sym_2_6939: la $2, sym_2_6939
+.globl sym_2_6940
+sym_2_6940: la $2, sym_2_6940
+.globl sym_2_6941
+sym_2_6941: la $2, sym_2_6941
+.globl sym_2_6942
+sym_2_6942: la $2, sym_2_6942
+.globl sym_2_6943
+sym_2_6943: la $2, sym_2_6943
+.globl sym_2_6944
+sym_2_6944: la $2, sym_2_6944
+.globl sym_2_6945
+sym_2_6945: la $2, sym_2_6945
+.globl sym_2_6946
+sym_2_6946: la $2, sym_2_6946
+.globl sym_2_6947
+sym_2_6947: la $2, sym_2_6947
+.globl sym_2_6948
+sym_2_6948: la $2, sym_2_6948
+.globl sym_2_6949
+sym_2_6949: la $2, sym_2_6949
+.globl sym_2_6950
+sym_2_6950: la $2, sym_2_6950
+.globl sym_2_6951
+sym_2_6951: la $2, sym_2_6951
+.globl sym_2_6952
+sym_2_6952: la $2, sym_2_6952
+.globl sym_2_6953
+sym_2_6953: la $2, sym_2_6953
+.globl sym_2_6954
+sym_2_6954: la $2, sym_2_6954
+.globl sym_2_6955
+sym_2_6955: la $2, sym_2_6955
+.globl sym_2_6956
+sym_2_6956: la $2, sym_2_6956
+.globl sym_2_6957
+sym_2_6957: la $2, sym_2_6957
+.globl sym_2_6958
+sym_2_6958: la $2, sym_2_6958
+.globl sym_2_6959
+sym_2_6959: la $2, sym_2_6959
+.globl sym_2_6960
+sym_2_6960: la $2, sym_2_6960
+.globl sym_2_6961
+sym_2_6961: la $2, sym_2_6961
+.globl sym_2_6962
+sym_2_6962: la $2, sym_2_6962
+.globl sym_2_6963
+sym_2_6963: la $2, sym_2_6963
+.globl sym_2_6964
+sym_2_6964: la $2, sym_2_6964
+.globl sym_2_6965
+sym_2_6965: la $2, sym_2_6965
+.globl sym_2_6966
+sym_2_6966: la $2, sym_2_6966
+.globl sym_2_6967
+sym_2_6967: la $2, sym_2_6967
+.globl sym_2_6968
+sym_2_6968: la $2, sym_2_6968
+.globl sym_2_6969
+sym_2_6969: la $2, sym_2_6969
+.globl sym_2_6970
+sym_2_6970: la $2, sym_2_6970
+.globl sym_2_6971
+sym_2_6971: la $2, sym_2_6971
+.globl sym_2_6972
+sym_2_6972: la $2, sym_2_6972
+.globl sym_2_6973
+sym_2_6973: la $2, sym_2_6973
+.globl sym_2_6974
+sym_2_6974: la $2, sym_2_6974
+.globl sym_2_6975
+sym_2_6975: la $2, sym_2_6975
+.globl sym_2_6976
+sym_2_6976: la $2, sym_2_6976
+.globl sym_2_6977
+sym_2_6977: la $2, sym_2_6977
+.globl sym_2_6978
+sym_2_6978: la $2, sym_2_6978
+.globl sym_2_6979
+sym_2_6979: la $2, sym_2_6979
+.globl sym_2_6980
+sym_2_6980: la $2, sym_2_6980
+.globl sym_2_6981
+sym_2_6981: la $2, sym_2_6981
+.globl sym_2_6982
+sym_2_6982: la $2, sym_2_6982
+.globl sym_2_6983
+sym_2_6983: la $2, sym_2_6983
+.globl sym_2_6984
+sym_2_6984: la $2, sym_2_6984
+.globl sym_2_6985
+sym_2_6985: la $2, sym_2_6985
+.globl sym_2_6986
+sym_2_6986: la $2, sym_2_6986
+.globl sym_2_6987
+sym_2_6987: la $2, sym_2_6987
+.globl sym_2_6988
+sym_2_6988: la $2, sym_2_6988
+.globl sym_2_6989
+sym_2_6989: la $2, sym_2_6989
+.globl sym_2_6990
+sym_2_6990: la $2, sym_2_6990
+.globl sym_2_6991
+sym_2_6991: la $2, sym_2_6991
+.globl sym_2_6992
+sym_2_6992: la $2, sym_2_6992
+.globl sym_2_6993
+sym_2_6993: la $2, sym_2_6993
+.globl sym_2_6994
+sym_2_6994: la $2, sym_2_6994
+.globl sym_2_6995
+sym_2_6995: la $2, sym_2_6995
+.globl sym_2_6996
+sym_2_6996: la $2, sym_2_6996
+.globl sym_2_6997
+sym_2_6997: la $2, sym_2_6997
+.globl sym_2_6998
+sym_2_6998: la $2, sym_2_6998
+.globl sym_2_6999
+sym_2_6999: la $2, sym_2_6999
+.globl sym_2_7000
+sym_2_7000: la $2, sym_2_7000
+.globl sym_2_7001
+sym_2_7001: la $2, sym_2_7001
+.globl sym_2_7002
+sym_2_7002: la $2, sym_2_7002
+.globl sym_2_7003
+sym_2_7003: la $2, sym_2_7003
+.globl sym_2_7004
+sym_2_7004: la $2, sym_2_7004
+.globl sym_2_7005
+sym_2_7005: la $2, sym_2_7005
+.globl sym_2_7006
+sym_2_7006: la $2, sym_2_7006
+.globl sym_2_7007
+sym_2_7007: la $2, sym_2_7007
+.globl sym_2_7008
+sym_2_7008: la $2, sym_2_7008
+.globl sym_2_7009
+sym_2_7009: la $2, sym_2_7009
+.globl sym_2_7010
+sym_2_7010: la $2, sym_2_7010
+.globl sym_2_7011
+sym_2_7011: la $2, sym_2_7011
+.globl sym_2_7012
+sym_2_7012: la $2, sym_2_7012
+.globl sym_2_7013
+sym_2_7013: la $2, sym_2_7013
+.globl sym_2_7014
+sym_2_7014: la $2, sym_2_7014
+.globl sym_2_7015
+sym_2_7015: la $2, sym_2_7015
+.globl sym_2_7016
+sym_2_7016: la $2, sym_2_7016
+.globl sym_2_7017
+sym_2_7017: la $2, sym_2_7017
+.globl sym_2_7018
+sym_2_7018: la $2, sym_2_7018
+.globl sym_2_7019
+sym_2_7019: la $2, sym_2_7019
+.globl sym_2_7020
+sym_2_7020: la $2, sym_2_7020
+.globl sym_2_7021
+sym_2_7021: la $2, sym_2_7021
+.globl sym_2_7022
+sym_2_7022: la $2, sym_2_7022
+.globl sym_2_7023
+sym_2_7023: la $2, sym_2_7023
+.globl sym_2_7024
+sym_2_7024: la $2, sym_2_7024
+.globl sym_2_7025
+sym_2_7025: la $2, sym_2_7025
+.globl sym_2_7026
+sym_2_7026: la $2, sym_2_7026
+.globl sym_2_7027
+sym_2_7027: la $2, sym_2_7027
+.globl sym_2_7028
+sym_2_7028: la $2, sym_2_7028
+.globl sym_2_7029
+sym_2_7029: la $2, sym_2_7029
+.globl sym_2_7030
+sym_2_7030: la $2, sym_2_7030
+.globl sym_2_7031
+sym_2_7031: la $2, sym_2_7031
+.globl sym_2_7032
+sym_2_7032: la $2, sym_2_7032
+.globl sym_2_7033
+sym_2_7033: la $2, sym_2_7033
+.globl sym_2_7034
+sym_2_7034: la $2, sym_2_7034
+.globl sym_2_7035
+sym_2_7035: la $2, sym_2_7035
+.globl sym_2_7036
+sym_2_7036: la $2, sym_2_7036
+.globl sym_2_7037
+sym_2_7037: la $2, sym_2_7037
+.globl sym_2_7038
+sym_2_7038: la $2, sym_2_7038
+.globl sym_2_7039
+sym_2_7039: la $2, sym_2_7039
+.globl sym_2_7040
+sym_2_7040: la $2, sym_2_7040
+.globl sym_2_7041
+sym_2_7041: la $2, sym_2_7041
+.globl sym_2_7042
+sym_2_7042: la $2, sym_2_7042
+.globl sym_2_7043
+sym_2_7043: la $2, sym_2_7043
+.globl sym_2_7044
+sym_2_7044: la $2, sym_2_7044
+.globl sym_2_7045
+sym_2_7045: la $2, sym_2_7045
+.globl sym_2_7046
+sym_2_7046: la $2, sym_2_7046
+.globl sym_2_7047
+sym_2_7047: la $2, sym_2_7047
+.globl sym_2_7048
+sym_2_7048: la $2, sym_2_7048
+.globl sym_2_7049
+sym_2_7049: la $2, sym_2_7049
+.globl sym_2_7050
+sym_2_7050: la $2, sym_2_7050
+.globl sym_2_7051
+sym_2_7051: la $2, sym_2_7051
+.globl sym_2_7052
+sym_2_7052: la $2, sym_2_7052
+.globl sym_2_7053
+sym_2_7053: la $2, sym_2_7053
+.globl sym_2_7054
+sym_2_7054: la $2, sym_2_7054
+.globl sym_2_7055
+sym_2_7055: la $2, sym_2_7055
+.globl sym_2_7056
+sym_2_7056: la $2, sym_2_7056
+.globl sym_2_7057
+sym_2_7057: la $2, sym_2_7057
+.globl sym_2_7058
+sym_2_7058: la $2, sym_2_7058
+.globl sym_2_7059
+sym_2_7059: la $2, sym_2_7059
+.globl sym_2_7060
+sym_2_7060: la $2, sym_2_7060
+.globl sym_2_7061
+sym_2_7061: la $2, sym_2_7061
+.globl sym_2_7062
+sym_2_7062: la $2, sym_2_7062
+.globl sym_2_7063
+sym_2_7063: la $2, sym_2_7063
+.globl sym_2_7064
+sym_2_7064: la $2, sym_2_7064
+.globl sym_2_7065
+sym_2_7065: la $2, sym_2_7065
+.globl sym_2_7066
+sym_2_7066: la $2, sym_2_7066
+.globl sym_2_7067
+sym_2_7067: la $2, sym_2_7067
+.globl sym_2_7068
+sym_2_7068: la $2, sym_2_7068
+.globl sym_2_7069
+sym_2_7069: la $2, sym_2_7069
+.globl sym_2_7070
+sym_2_7070: la $2, sym_2_7070
+.globl sym_2_7071
+sym_2_7071: la $2, sym_2_7071
+.globl sym_2_7072
+sym_2_7072: la $2, sym_2_7072
+.globl sym_2_7073
+sym_2_7073: la $2, sym_2_7073
+.globl sym_2_7074
+sym_2_7074: la $2, sym_2_7074
+.globl sym_2_7075
+sym_2_7075: la $2, sym_2_7075
+.globl sym_2_7076
+sym_2_7076: la $2, sym_2_7076
+.globl sym_2_7077
+sym_2_7077: la $2, sym_2_7077
+.globl sym_2_7078
+sym_2_7078: la $2, sym_2_7078
+.globl sym_2_7079
+sym_2_7079: la $2, sym_2_7079
+.globl sym_2_7080
+sym_2_7080: la $2, sym_2_7080
+.globl sym_2_7081
+sym_2_7081: la $2, sym_2_7081
+.globl sym_2_7082
+sym_2_7082: la $2, sym_2_7082
+.globl sym_2_7083
+sym_2_7083: la $2, sym_2_7083
+.globl sym_2_7084
+sym_2_7084: la $2, sym_2_7084
+.globl sym_2_7085
+sym_2_7085: la $2, sym_2_7085
+.globl sym_2_7086
+sym_2_7086: la $2, sym_2_7086
+.globl sym_2_7087
+sym_2_7087: la $2, sym_2_7087
+.globl sym_2_7088
+sym_2_7088: la $2, sym_2_7088
+.globl sym_2_7089
+sym_2_7089: la $2, sym_2_7089
+.globl sym_2_7090
+sym_2_7090: la $2, sym_2_7090
+.globl sym_2_7091
+sym_2_7091: la $2, sym_2_7091
+.globl sym_2_7092
+sym_2_7092: la $2, sym_2_7092
+.globl sym_2_7093
+sym_2_7093: la $2, sym_2_7093
+.globl sym_2_7094
+sym_2_7094: la $2, sym_2_7094
+.globl sym_2_7095
+sym_2_7095: la $2, sym_2_7095
+.globl sym_2_7096
+sym_2_7096: la $2, sym_2_7096
+.globl sym_2_7097
+sym_2_7097: la $2, sym_2_7097
+.globl sym_2_7098
+sym_2_7098: la $2, sym_2_7098
+.globl sym_2_7099
+sym_2_7099: la $2, sym_2_7099
+.globl sym_2_7100
+sym_2_7100: la $2, sym_2_7100
+.globl sym_2_7101
+sym_2_7101: la $2, sym_2_7101
+.globl sym_2_7102
+sym_2_7102: la $2, sym_2_7102
+.globl sym_2_7103
+sym_2_7103: la $2, sym_2_7103
+.globl sym_2_7104
+sym_2_7104: la $2, sym_2_7104
+.globl sym_2_7105
+sym_2_7105: la $2, sym_2_7105
+.globl sym_2_7106
+sym_2_7106: la $2, sym_2_7106
+.globl sym_2_7107
+sym_2_7107: la $2, sym_2_7107
+.globl sym_2_7108
+sym_2_7108: la $2, sym_2_7108
+.globl sym_2_7109
+sym_2_7109: la $2, sym_2_7109
+.globl sym_2_7110
+sym_2_7110: la $2, sym_2_7110
+.globl sym_2_7111
+sym_2_7111: la $2, sym_2_7111
+.globl sym_2_7112
+sym_2_7112: la $2, sym_2_7112
+.globl sym_2_7113
+sym_2_7113: la $2, sym_2_7113
+.globl sym_2_7114
+sym_2_7114: la $2, sym_2_7114
+.globl sym_2_7115
+sym_2_7115: la $2, sym_2_7115
+.globl sym_2_7116
+sym_2_7116: la $2, sym_2_7116
+.globl sym_2_7117
+sym_2_7117: la $2, sym_2_7117
+.globl sym_2_7118
+sym_2_7118: la $2, sym_2_7118
+.globl sym_2_7119
+sym_2_7119: la $2, sym_2_7119
+.globl sym_2_7120
+sym_2_7120: la $2, sym_2_7120
+.globl sym_2_7121
+sym_2_7121: la $2, sym_2_7121
+.globl sym_2_7122
+sym_2_7122: la $2, sym_2_7122
+.globl sym_2_7123
+sym_2_7123: la $2, sym_2_7123
+.globl sym_2_7124
+sym_2_7124: la $2, sym_2_7124
+.globl sym_2_7125
+sym_2_7125: la $2, sym_2_7125
+.globl sym_2_7126
+sym_2_7126: la $2, sym_2_7126
+.globl sym_2_7127
+sym_2_7127: la $2, sym_2_7127
+.globl sym_2_7128
+sym_2_7128: la $2, sym_2_7128
+.globl sym_2_7129
+sym_2_7129: la $2, sym_2_7129
+.globl sym_2_7130
+sym_2_7130: la $2, sym_2_7130
+.globl sym_2_7131
+sym_2_7131: la $2, sym_2_7131
+.globl sym_2_7132
+sym_2_7132: la $2, sym_2_7132
+.globl sym_2_7133
+sym_2_7133: la $2, sym_2_7133
+.globl sym_2_7134
+sym_2_7134: la $2, sym_2_7134
+.globl sym_2_7135
+sym_2_7135: la $2, sym_2_7135
+.globl sym_2_7136
+sym_2_7136: la $2, sym_2_7136
+.globl sym_2_7137
+sym_2_7137: la $2, sym_2_7137
+.globl sym_2_7138
+sym_2_7138: la $2, sym_2_7138
+.globl sym_2_7139
+sym_2_7139: la $2, sym_2_7139
+.globl sym_2_7140
+sym_2_7140: la $2, sym_2_7140
+.globl sym_2_7141
+sym_2_7141: la $2, sym_2_7141
+.globl sym_2_7142
+sym_2_7142: la $2, sym_2_7142
+.globl sym_2_7143
+sym_2_7143: la $2, sym_2_7143
+.globl sym_2_7144
+sym_2_7144: la $2, sym_2_7144
+.globl sym_2_7145
+sym_2_7145: la $2, sym_2_7145
+.globl sym_2_7146
+sym_2_7146: la $2, sym_2_7146
+.globl sym_2_7147
+sym_2_7147: la $2, sym_2_7147
+.globl sym_2_7148
+sym_2_7148: la $2, sym_2_7148
+.globl sym_2_7149
+sym_2_7149: la $2, sym_2_7149
+.globl sym_2_7150
+sym_2_7150: la $2, sym_2_7150
+.globl sym_2_7151
+sym_2_7151: la $2, sym_2_7151
+.globl sym_2_7152
+sym_2_7152: la $2, sym_2_7152
+.globl sym_2_7153
+sym_2_7153: la $2, sym_2_7153
+.globl sym_2_7154
+sym_2_7154: la $2, sym_2_7154
+.globl sym_2_7155
+sym_2_7155: la $2, sym_2_7155
+.globl sym_2_7156
+sym_2_7156: la $2, sym_2_7156
+.globl sym_2_7157
+sym_2_7157: la $2, sym_2_7157
+.globl sym_2_7158
+sym_2_7158: la $2, sym_2_7158
+.globl sym_2_7159
+sym_2_7159: la $2, sym_2_7159
+.globl sym_2_7160
+sym_2_7160: la $2, sym_2_7160
+.globl sym_2_7161
+sym_2_7161: la $2, sym_2_7161
+.globl sym_2_7162
+sym_2_7162: la $2, sym_2_7162
+.globl sym_2_7163
+sym_2_7163: la $2, sym_2_7163
+.globl sym_2_7164
+sym_2_7164: la $2, sym_2_7164
+.globl sym_2_7165
+sym_2_7165: la $2, sym_2_7165
+.globl sym_2_7166
+sym_2_7166: la $2, sym_2_7166
+.globl sym_2_7167
+sym_2_7167: la $2, sym_2_7167
+.globl sym_2_7168
+sym_2_7168: la $2, sym_2_7168
+.globl sym_2_7169
+sym_2_7169: la $2, sym_2_7169
+.globl sym_2_7170
+sym_2_7170: la $2, sym_2_7170
+.globl sym_2_7171
+sym_2_7171: la $2, sym_2_7171
+.globl sym_2_7172
+sym_2_7172: la $2, sym_2_7172
+.globl sym_2_7173
+sym_2_7173: la $2, sym_2_7173
+.globl sym_2_7174
+sym_2_7174: la $2, sym_2_7174
+.globl sym_2_7175
+sym_2_7175: la $2, sym_2_7175
+.globl sym_2_7176
+sym_2_7176: la $2, sym_2_7176
+.globl sym_2_7177
+sym_2_7177: la $2, sym_2_7177
+.globl sym_2_7178
+sym_2_7178: la $2, sym_2_7178
+.globl sym_2_7179
+sym_2_7179: la $2, sym_2_7179
+.globl sym_2_7180
+sym_2_7180: la $2, sym_2_7180
+.globl sym_2_7181
+sym_2_7181: la $2, sym_2_7181
+.globl sym_2_7182
+sym_2_7182: la $2, sym_2_7182
+.globl sym_2_7183
+sym_2_7183: la $2, sym_2_7183
+.globl sym_2_7184
+sym_2_7184: la $2, sym_2_7184
+.globl sym_2_7185
+sym_2_7185: la $2, sym_2_7185
+.globl sym_2_7186
+sym_2_7186: la $2, sym_2_7186
+.globl sym_2_7187
+sym_2_7187: la $2, sym_2_7187
+.globl sym_2_7188
+sym_2_7188: la $2, sym_2_7188
+.globl sym_2_7189
+sym_2_7189: la $2, sym_2_7189
+.globl sym_2_7190
+sym_2_7190: la $2, sym_2_7190
+.globl sym_2_7191
+sym_2_7191: la $2, sym_2_7191
+.globl sym_2_7192
+sym_2_7192: la $2, sym_2_7192
+.globl sym_2_7193
+sym_2_7193: la $2, sym_2_7193
+.globl sym_2_7194
+sym_2_7194: la $2, sym_2_7194
+.globl sym_2_7195
+sym_2_7195: la $2, sym_2_7195
+.globl sym_2_7196
+sym_2_7196: la $2, sym_2_7196
+.globl sym_2_7197
+sym_2_7197: la $2, sym_2_7197
+.globl sym_2_7198
+sym_2_7198: la $2, sym_2_7198
+.globl sym_2_7199
+sym_2_7199: la $2, sym_2_7199
+.globl sym_2_7200
+sym_2_7200: la $2, sym_2_7200
+.globl sym_2_7201
+sym_2_7201: la $2, sym_2_7201
+.globl sym_2_7202
+sym_2_7202: la $2, sym_2_7202
+.globl sym_2_7203
+sym_2_7203: la $2, sym_2_7203
+.globl sym_2_7204
+sym_2_7204: la $2, sym_2_7204
+.globl sym_2_7205
+sym_2_7205: la $2, sym_2_7205
+.globl sym_2_7206
+sym_2_7206: la $2, sym_2_7206
+.globl sym_2_7207
+sym_2_7207: la $2, sym_2_7207
+.globl sym_2_7208
+sym_2_7208: la $2, sym_2_7208
+.globl sym_2_7209
+sym_2_7209: la $2, sym_2_7209
+.globl sym_2_7210
+sym_2_7210: la $2, sym_2_7210
+.globl sym_2_7211
+sym_2_7211: la $2, sym_2_7211
+.globl sym_2_7212
+sym_2_7212: la $2, sym_2_7212
+.globl sym_2_7213
+sym_2_7213: la $2, sym_2_7213
+.globl sym_2_7214
+sym_2_7214: la $2, sym_2_7214
+.globl sym_2_7215
+sym_2_7215: la $2, sym_2_7215
+.globl sym_2_7216
+sym_2_7216: la $2, sym_2_7216
+.globl sym_2_7217
+sym_2_7217: la $2, sym_2_7217
+.globl sym_2_7218
+sym_2_7218: la $2, sym_2_7218
+.globl sym_2_7219
+sym_2_7219: la $2, sym_2_7219
+.globl sym_2_7220
+sym_2_7220: la $2, sym_2_7220
+.globl sym_2_7221
+sym_2_7221: la $2, sym_2_7221
+.globl sym_2_7222
+sym_2_7222: la $2, sym_2_7222
+.globl sym_2_7223
+sym_2_7223: la $2, sym_2_7223
+.globl sym_2_7224
+sym_2_7224: la $2, sym_2_7224
+.globl sym_2_7225
+sym_2_7225: la $2, sym_2_7225
+.globl sym_2_7226
+sym_2_7226: la $2, sym_2_7226
+.globl sym_2_7227
+sym_2_7227: la $2, sym_2_7227
+.globl sym_2_7228
+sym_2_7228: la $2, sym_2_7228
+.globl sym_2_7229
+sym_2_7229: la $2, sym_2_7229
+.globl sym_2_7230
+sym_2_7230: la $2, sym_2_7230
+.globl sym_2_7231
+sym_2_7231: la $2, sym_2_7231
+.globl sym_2_7232
+sym_2_7232: la $2, sym_2_7232
+.globl sym_2_7233
+sym_2_7233: la $2, sym_2_7233
+.globl sym_2_7234
+sym_2_7234: la $2, sym_2_7234
+.globl sym_2_7235
+sym_2_7235: la $2, sym_2_7235
+.globl sym_2_7236
+sym_2_7236: la $2, sym_2_7236
+.globl sym_2_7237
+sym_2_7237: la $2, sym_2_7237
+.globl sym_2_7238
+sym_2_7238: la $2, sym_2_7238
+.globl sym_2_7239
+sym_2_7239: la $2, sym_2_7239
+.globl sym_2_7240
+sym_2_7240: la $2, sym_2_7240
+.globl sym_2_7241
+sym_2_7241: la $2, sym_2_7241
+.globl sym_2_7242
+sym_2_7242: la $2, sym_2_7242
+.globl sym_2_7243
+sym_2_7243: la $2, sym_2_7243
+.globl sym_2_7244
+sym_2_7244: la $2, sym_2_7244
+.globl sym_2_7245
+sym_2_7245: la $2, sym_2_7245
+.globl sym_2_7246
+sym_2_7246: la $2, sym_2_7246
+.globl sym_2_7247
+sym_2_7247: la $2, sym_2_7247
+.globl sym_2_7248
+sym_2_7248: la $2, sym_2_7248
+.globl sym_2_7249
+sym_2_7249: la $2, sym_2_7249
+.globl sym_2_7250
+sym_2_7250: la $2, sym_2_7250
+.globl sym_2_7251
+sym_2_7251: la $2, sym_2_7251
+.globl sym_2_7252
+sym_2_7252: la $2, sym_2_7252
+.globl sym_2_7253
+sym_2_7253: la $2, sym_2_7253
+.globl sym_2_7254
+sym_2_7254: la $2, sym_2_7254
+.globl sym_2_7255
+sym_2_7255: la $2, sym_2_7255
+.globl sym_2_7256
+sym_2_7256: la $2, sym_2_7256
+.globl sym_2_7257
+sym_2_7257: la $2, sym_2_7257
+.globl sym_2_7258
+sym_2_7258: la $2, sym_2_7258
+.globl sym_2_7259
+sym_2_7259: la $2, sym_2_7259
+.globl sym_2_7260
+sym_2_7260: la $2, sym_2_7260
+.globl sym_2_7261
+sym_2_7261: la $2, sym_2_7261
+.globl sym_2_7262
+sym_2_7262: la $2, sym_2_7262
+.globl sym_2_7263
+sym_2_7263: la $2, sym_2_7263
+.globl sym_2_7264
+sym_2_7264: la $2, sym_2_7264
+.globl sym_2_7265
+sym_2_7265: la $2, sym_2_7265
+.globl sym_2_7266
+sym_2_7266: la $2, sym_2_7266
+.globl sym_2_7267
+sym_2_7267: la $2, sym_2_7267
+.globl sym_2_7268
+sym_2_7268: la $2, sym_2_7268
+.globl sym_2_7269
+sym_2_7269: la $2, sym_2_7269
+.globl sym_2_7270
+sym_2_7270: la $2, sym_2_7270
+.globl sym_2_7271
+sym_2_7271: la $2, sym_2_7271
+.globl sym_2_7272
+sym_2_7272: la $2, sym_2_7272
+.globl sym_2_7273
+sym_2_7273: la $2, sym_2_7273
+.globl sym_2_7274
+sym_2_7274: la $2, sym_2_7274
+.globl sym_2_7275
+sym_2_7275: la $2, sym_2_7275
+.globl sym_2_7276
+sym_2_7276: la $2, sym_2_7276
+.globl sym_2_7277
+sym_2_7277: la $2, sym_2_7277
+.globl sym_2_7278
+sym_2_7278: la $2, sym_2_7278
+.globl sym_2_7279
+sym_2_7279: la $2, sym_2_7279
+.globl sym_2_7280
+sym_2_7280: la $2, sym_2_7280
+.globl sym_2_7281
+sym_2_7281: la $2, sym_2_7281
+.globl sym_2_7282
+sym_2_7282: la $2, sym_2_7282
+.globl sym_2_7283
+sym_2_7283: la $2, sym_2_7283
+.globl sym_2_7284
+sym_2_7284: la $2, sym_2_7284
+.globl sym_2_7285
+sym_2_7285: la $2, sym_2_7285
+.globl sym_2_7286
+sym_2_7286: la $2, sym_2_7286
+.globl sym_2_7287
+sym_2_7287: la $2, sym_2_7287
+.globl sym_2_7288
+sym_2_7288: la $2, sym_2_7288
+.globl sym_2_7289
+sym_2_7289: la $2, sym_2_7289
+.globl sym_2_7290
+sym_2_7290: la $2, sym_2_7290
+.globl sym_2_7291
+sym_2_7291: la $2, sym_2_7291
+.globl sym_2_7292
+sym_2_7292: la $2, sym_2_7292
+.globl sym_2_7293
+sym_2_7293: la $2, sym_2_7293
+.globl sym_2_7294
+sym_2_7294: la $2, sym_2_7294
+.globl sym_2_7295
+sym_2_7295: la $2, sym_2_7295
+.globl sym_2_7296
+sym_2_7296: la $2, sym_2_7296
+.globl sym_2_7297
+sym_2_7297: la $2, sym_2_7297
+.globl sym_2_7298
+sym_2_7298: la $2, sym_2_7298
+.globl sym_2_7299
+sym_2_7299: la $2, sym_2_7299
+.globl sym_2_7300
+sym_2_7300: la $2, sym_2_7300
+.globl sym_2_7301
+sym_2_7301: la $2, sym_2_7301
+.globl sym_2_7302
+sym_2_7302: la $2, sym_2_7302
+.globl sym_2_7303
+sym_2_7303: la $2, sym_2_7303
+.globl sym_2_7304
+sym_2_7304: la $2, sym_2_7304
+.globl sym_2_7305
+sym_2_7305: la $2, sym_2_7305
+.globl sym_2_7306
+sym_2_7306: la $2, sym_2_7306
+.globl sym_2_7307
+sym_2_7307: la $2, sym_2_7307
+.globl sym_2_7308
+sym_2_7308: la $2, sym_2_7308
+.globl sym_2_7309
+sym_2_7309: la $2, sym_2_7309
+.globl sym_2_7310
+sym_2_7310: la $2, sym_2_7310
+.globl sym_2_7311
+sym_2_7311: la $2, sym_2_7311
+.globl sym_2_7312
+sym_2_7312: la $2, sym_2_7312
+.globl sym_2_7313
+sym_2_7313: la $2, sym_2_7313
+.globl sym_2_7314
+sym_2_7314: la $2, sym_2_7314
+.globl sym_2_7315
+sym_2_7315: la $2, sym_2_7315
+.globl sym_2_7316
+sym_2_7316: la $2, sym_2_7316
+.globl sym_2_7317
+sym_2_7317: la $2, sym_2_7317
+.globl sym_2_7318
+sym_2_7318: la $2, sym_2_7318
+.globl sym_2_7319
+sym_2_7319: la $2, sym_2_7319
+.globl sym_2_7320
+sym_2_7320: la $2, sym_2_7320
+.globl sym_2_7321
+sym_2_7321: la $2, sym_2_7321
+.globl sym_2_7322
+sym_2_7322: la $2, sym_2_7322
+.globl sym_2_7323
+sym_2_7323: la $2, sym_2_7323
+.globl sym_2_7324
+sym_2_7324: la $2, sym_2_7324
+.globl sym_2_7325
+sym_2_7325: la $2, sym_2_7325
+.globl sym_2_7326
+sym_2_7326: la $2, sym_2_7326
+.globl sym_2_7327
+sym_2_7327: la $2, sym_2_7327
+.globl sym_2_7328
+sym_2_7328: la $2, sym_2_7328
+.globl sym_2_7329
+sym_2_7329: la $2, sym_2_7329
+.globl sym_2_7330
+sym_2_7330: la $2, sym_2_7330
+.globl sym_2_7331
+sym_2_7331: la $2, sym_2_7331
+.globl sym_2_7332
+sym_2_7332: la $2, sym_2_7332
+.globl sym_2_7333
+sym_2_7333: la $2, sym_2_7333
+.globl sym_2_7334
+sym_2_7334: la $2, sym_2_7334
+.globl sym_2_7335
+sym_2_7335: la $2, sym_2_7335
+.globl sym_2_7336
+sym_2_7336: la $2, sym_2_7336
+.globl sym_2_7337
+sym_2_7337: la $2, sym_2_7337
+.globl sym_2_7338
+sym_2_7338: la $2, sym_2_7338
+.globl sym_2_7339
+sym_2_7339: la $2, sym_2_7339
+.globl sym_2_7340
+sym_2_7340: la $2, sym_2_7340
+.globl sym_2_7341
+sym_2_7341: la $2, sym_2_7341
+.globl sym_2_7342
+sym_2_7342: la $2, sym_2_7342
+.globl sym_2_7343
+sym_2_7343: la $2, sym_2_7343
+.globl sym_2_7344
+sym_2_7344: la $2, sym_2_7344
+.globl sym_2_7345
+sym_2_7345: la $2, sym_2_7345
+.globl sym_2_7346
+sym_2_7346: la $2, sym_2_7346
+.globl sym_2_7347
+sym_2_7347: la $2, sym_2_7347
+.globl sym_2_7348
+sym_2_7348: la $2, sym_2_7348
+.globl sym_2_7349
+sym_2_7349: la $2, sym_2_7349
+.globl sym_2_7350
+sym_2_7350: la $2, sym_2_7350
+.globl sym_2_7351
+sym_2_7351: la $2, sym_2_7351
+.globl sym_2_7352
+sym_2_7352: la $2, sym_2_7352
+.globl sym_2_7353
+sym_2_7353: la $2, sym_2_7353
+.globl sym_2_7354
+sym_2_7354: la $2, sym_2_7354
+.globl sym_2_7355
+sym_2_7355: la $2, sym_2_7355
+.globl sym_2_7356
+sym_2_7356: la $2, sym_2_7356
+.globl sym_2_7357
+sym_2_7357: la $2, sym_2_7357
+.globl sym_2_7358
+sym_2_7358: la $2, sym_2_7358
+.globl sym_2_7359
+sym_2_7359: la $2, sym_2_7359
+.globl sym_2_7360
+sym_2_7360: la $2, sym_2_7360
+.globl sym_2_7361
+sym_2_7361: la $2, sym_2_7361
+.globl sym_2_7362
+sym_2_7362: la $2, sym_2_7362
+.globl sym_2_7363
+sym_2_7363: la $2, sym_2_7363
+.globl sym_2_7364
+sym_2_7364: la $2, sym_2_7364
+.globl sym_2_7365
+sym_2_7365: la $2, sym_2_7365
+.globl sym_2_7366
+sym_2_7366: la $2, sym_2_7366
+.globl sym_2_7367
+sym_2_7367: la $2, sym_2_7367
+.globl sym_2_7368
+sym_2_7368: la $2, sym_2_7368
+.globl sym_2_7369
+sym_2_7369: la $2, sym_2_7369
+.globl sym_2_7370
+sym_2_7370: la $2, sym_2_7370
+.globl sym_2_7371
+sym_2_7371: la $2, sym_2_7371
+.globl sym_2_7372
+sym_2_7372: la $2, sym_2_7372
+.globl sym_2_7373
+sym_2_7373: la $2, sym_2_7373
+.globl sym_2_7374
+sym_2_7374: la $2, sym_2_7374
+.globl sym_2_7375
+sym_2_7375: la $2, sym_2_7375
+.globl sym_2_7376
+sym_2_7376: la $2, sym_2_7376
+.globl sym_2_7377
+sym_2_7377: la $2, sym_2_7377
+.globl sym_2_7378
+sym_2_7378: la $2, sym_2_7378
+.globl sym_2_7379
+sym_2_7379: la $2, sym_2_7379
+.globl sym_2_7380
+sym_2_7380: la $2, sym_2_7380
+.globl sym_2_7381
+sym_2_7381: la $2, sym_2_7381
+.globl sym_2_7382
+sym_2_7382: la $2, sym_2_7382
+.globl sym_2_7383
+sym_2_7383: la $2, sym_2_7383
+.globl sym_2_7384
+sym_2_7384: la $2, sym_2_7384
+.globl sym_2_7385
+sym_2_7385: la $2, sym_2_7385
+.globl sym_2_7386
+sym_2_7386: la $2, sym_2_7386
+.globl sym_2_7387
+sym_2_7387: la $2, sym_2_7387
+.globl sym_2_7388
+sym_2_7388: la $2, sym_2_7388
+.globl sym_2_7389
+sym_2_7389: la $2, sym_2_7389
+.globl sym_2_7390
+sym_2_7390: la $2, sym_2_7390
+.globl sym_2_7391
+sym_2_7391: la $2, sym_2_7391
+.globl sym_2_7392
+sym_2_7392: la $2, sym_2_7392
+.globl sym_2_7393
+sym_2_7393: la $2, sym_2_7393
+.globl sym_2_7394
+sym_2_7394: la $2, sym_2_7394
+.globl sym_2_7395
+sym_2_7395: la $2, sym_2_7395
+.globl sym_2_7396
+sym_2_7396: la $2, sym_2_7396
+.globl sym_2_7397
+sym_2_7397: la $2, sym_2_7397
+.globl sym_2_7398
+sym_2_7398: la $2, sym_2_7398
+.globl sym_2_7399
+sym_2_7399: la $2, sym_2_7399
+.globl sym_2_7400
+sym_2_7400: la $2, sym_2_7400
+.globl sym_2_7401
+sym_2_7401: la $2, sym_2_7401
+.globl sym_2_7402
+sym_2_7402: la $2, sym_2_7402
+.globl sym_2_7403
+sym_2_7403: la $2, sym_2_7403
+.globl sym_2_7404
+sym_2_7404: la $2, sym_2_7404
+.globl sym_2_7405
+sym_2_7405: la $2, sym_2_7405
+.globl sym_2_7406
+sym_2_7406: la $2, sym_2_7406
+.globl sym_2_7407
+sym_2_7407: la $2, sym_2_7407
+.globl sym_2_7408
+sym_2_7408: la $2, sym_2_7408
+.globl sym_2_7409
+sym_2_7409: la $2, sym_2_7409
+.globl sym_2_7410
+sym_2_7410: la $2, sym_2_7410
+.globl sym_2_7411
+sym_2_7411: la $2, sym_2_7411
+.globl sym_2_7412
+sym_2_7412: la $2, sym_2_7412
+.globl sym_2_7413
+sym_2_7413: la $2, sym_2_7413
+.globl sym_2_7414
+sym_2_7414: la $2, sym_2_7414
+.globl sym_2_7415
+sym_2_7415: la $2, sym_2_7415
+.globl sym_2_7416
+sym_2_7416: la $2, sym_2_7416
+.globl sym_2_7417
+sym_2_7417: la $2, sym_2_7417
+.globl sym_2_7418
+sym_2_7418: la $2, sym_2_7418
+.globl sym_2_7419
+sym_2_7419: la $2, sym_2_7419
+.globl sym_2_7420
+sym_2_7420: la $2, sym_2_7420
+.globl sym_2_7421
+sym_2_7421: la $2, sym_2_7421
+.globl sym_2_7422
+sym_2_7422: la $2, sym_2_7422
+.globl sym_2_7423
+sym_2_7423: la $2, sym_2_7423
+.globl sym_2_7424
+sym_2_7424: la $2, sym_2_7424
+.globl sym_2_7425
+sym_2_7425: la $2, sym_2_7425
+.globl sym_2_7426
+sym_2_7426: la $2, sym_2_7426
+.globl sym_2_7427
+sym_2_7427: la $2, sym_2_7427
+.globl sym_2_7428
+sym_2_7428: la $2, sym_2_7428
+.globl sym_2_7429
+sym_2_7429: la $2, sym_2_7429
+.globl sym_2_7430
+sym_2_7430: la $2, sym_2_7430
+.globl sym_2_7431
+sym_2_7431: la $2, sym_2_7431
+.globl sym_2_7432
+sym_2_7432: la $2, sym_2_7432
+.globl sym_2_7433
+sym_2_7433: la $2, sym_2_7433
+.globl sym_2_7434
+sym_2_7434: la $2, sym_2_7434
+.globl sym_2_7435
+sym_2_7435: la $2, sym_2_7435
+.globl sym_2_7436
+sym_2_7436: la $2, sym_2_7436
+.globl sym_2_7437
+sym_2_7437: la $2, sym_2_7437
+.globl sym_2_7438
+sym_2_7438: la $2, sym_2_7438
+.globl sym_2_7439
+sym_2_7439: la $2, sym_2_7439
+.globl sym_2_7440
+sym_2_7440: la $2, sym_2_7440
+.globl sym_2_7441
+sym_2_7441: la $2, sym_2_7441
+.globl sym_2_7442
+sym_2_7442: la $2, sym_2_7442
+.globl sym_2_7443
+sym_2_7443: la $2, sym_2_7443
+.globl sym_2_7444
+sym_2_7444: la $2, sym_2_7444
+.globl sym_2_7445
+sym_2_7445: la $2, sym_2_7445
+.globl sym_2_7446
+sym_2_7446: la $2, sym_2_7446
+.globl sym_2_7447
+sym_2_7447: la $2, sym_2_7447
+.globl sym_2_7448
+sym_2_7448: la $2, sym_2_7448
+.globl sym_2_7449
+sym_2_7449: la $2, sym_2_7449
+.globl sym_2_7450
+sym_2_7450: la $2, sym_2_7450
+.globl sym_2_7451
+sym_2_7451: la $2, sym_2_7451
+.globl sym_2_7452
+sym_2_7452: la $2, sym_2_7452
+.globl sym_2_7453
+sym_2_7453: la $2, sym_2_7453
+.globl sym_2_7454
+sym_2_7454: la $2, sym_2_7454
+.globl sym_2_7455
+sym_2_7455: la $2, sym_2_7455
+.globl sym_2_7456
+sym_2_7456: la $2, sym_2_7456
+.globl sym_2_7457
+sym_2_7457: la $2, sym_2_7457
+.globl sym_2_7458
+sym_2_7458: la $2, sym_2_7458
+.globl sym_2_7459
+sym_2_7459: la $2, sym_2_7459
+.globl sym_2_7460
+sym_2_7460: la $2, sym_2_7460
+.globl sym_2_7461
+sym_2_7461: la $2, sym_2_7461
+.globl sym_2_7462
+sym_2_7462: la $2, sym_2_7462
+.globl sym_2_7463
+sym_2_7463: la $2, sym_2_7463
+.globl sym_2_7464
+sym_2_7464: la $2, sym_2_7464
+.globl sym_2_7465
+sym_2_7465: la $2, sym_2_7465
+.globl sym_2_7466
+sym_2_7466: la $2, sym_2_7466
+.globl sym_2_7467
+sym_2_7467: la $2, sym_2_7467
+.globl sym_2_7468
+sym_2_7468: la $2, sym_2_7468
+.globl sym_2_7469
+sym_2_7469: la $2, sym_2_7469
+.globl sym_2_7470
+sym_2_7470: la $2, sym_2_7470
+.globl sym_2_7471
+sym_2_7471: la $2, sym_2_7471
+.globl sym_2_7472
+sym_2_7472: la $2, sym_2_7472
+.globl sym_2_7473
+sym_2_7473: la $2, sym_2_7473
+.globl sym_2_7474
+sym_2_7474: la $2, sym_2_7474
+.globl sym_2_7475
+sym_2_7475: la $2, sym_2_7475
+.globl sym_2_7476
+sym_2_7476: la $2, sym_2_7476
+.globl sym_2_7477
+sym_2_7477: la $2, sym_2_7477
+.globl sym_2_7478
+sym_2_7478: la $2, sym_2_7478
+.globl sym_2_7479
+sym_2_7479: la $2, sym_2_7479
+.globl sym_2_7480
+sym_2_7480: la $2, sym_2_7480
+.globl sym_2_7481
+sym_2_7481: la $2, sym_2_7481
+.globl sym_2_7482
+sym_2_7482: la $2, sym_2_7482
+.globl sym_2_7483
+sym_2_7483: la $2, sym_2_7483
+.globl sym_2_7484
+sym_2_7484: la $2, sym_2_7484
+.globl sym_2_7485
+sym_2_7485: la $2, sym_2_7485
+.globl sym_2_7486
+sym_2_7486: la $2, sym_2_7486
+.globl sym_2_7487
+sym_2_7487: la $2, sym_2_7487
+.globl sym_2_7488
+sym_2_7488: la $2, sym_2_7488
+.globl sym_2_7489
+sym_2_7489: la $2, sym_2_7489
+.globl sym_2_7490
+sym_2_7490: la $2, sym_2_7490
+.globl sym_2_7491
+sym_2_7491: la $2, sym_2_7491
+.globl sym_2_7492
+sym_2_7492: la $2, sym_2_7492
+.globl sym_2_7493
+sym_2_7493: la $2, sym_2_7493
+.globl sym_2_7494
+sym_2_7494: la $2, sym_2_7494
+.globl sym_2_7495
+sym_2_7495: la $2, sym_2_7495
+.globl sym_2_7496
+sym_2_7496: la $2, sym_2_7496
+.globl sym_2_7497
+sym_2_7497: la $2, sym_2_7497
+.globl sym_2_7498
+sym_2_7498: la $2, sym_2_7498
+.globl sym_2_7499
+sym_2_7499: la $2, sym_2_7499
+.globl sym_2_7500
+sym_2_7500: la $2, sym_2_7500
+.globl sym_2_7501
+sym_2_7501: la $2, sym_2_7501
+.globl sym_2_7502
+sym_2_7502: la $2, sym_2_7502
+.globl sym_2_7503
+sym_2_7503: la $2, sym_2_7503
+.globl sym_2_7504
+sym_2_7504: la $2, sym_2_7504
+.globl sym_2_7505
+sym_2_7505: la $2, sym_2_7505
+.globl sym_2_7506
+sym_2_7506: la $2, sym_2_7506
+.globl sym_2_7507
+sym_2_7507: la $2, sym_2_7507
+.globl sym_2_7508
+sym_2_7508: la $2, sym_2_7508
+.globl sym_2_7509
+sym_2_7509: la $2, sym_2_7509
+.globl sym_2_7510
+sym_2_7510: la $2, sym_2_7510
+.globl sym_2_7511
+sym_2_7511: la $2, sym_2_7511
+.globl sym_2_7512
+sym_2_7512: la $2, sym_2_7512
+.globl sym_2_7513
+sym_2_7513: la $2, sym_2_7513
+.globl sym_2_7514
+sym_2_7514: la $2, sym_2_7514
+.globl sym_2_7515
+sym_2_7515: la $2, sym_2_7515
+.globl sym_2_7516
+sym_2_7516: la $2, sym_2_7516
+.globl sym_2_7517
+sym_2_7517: la $2, sym_2_7517
+.globl sym_2_7518
+sym_2_7518: la $2, sym_2_7518
+.globl sym_2_7519
+sym_2_7519: la $2, sym_2_7519
+.globl sym_2_7520
+sym_2_7520: la $2, sym_2_7520
+.globl sym_2_7521
+sym_2_7521: la $2, sym_2_7521
+.globl sym_2_7522
+sym_2_7522: la $2, sym_2_7522
+.globl sym_2_7523
+sym_2_7523: la $2, sym_2_7523
+.globl sym_2_7524
+sym_2_7524: la $2, sym_2_7524
+.globl sym_2_7525
+sym_2_7525: la $2, sym_2_7525
+.globl sym_2_7526
+sym_2_7526: la $2, sym_2_7526
+.globl sym_2_7527
+sym_2_7527: la $2, sym_2_7527
+.globl sym_2_7528
+sym_2_7528: la $2, sym_2_7528
+.globl sym_2_7529
+sym_2_7529: la $2, sym_2_7529
+.globl sym_2_7530
+sym_2_7530: la $2, sym_2_7530
+.globl sym_2_7531
+sym_2_7531: la $2, sym_2_7531
+.globl sym_2_7532
+sym_2_7532: la $2, sym_2_7532
+.globl sym_2_7533
+sym_2_7533: la $2, sym_2_7533
+.globl sym_2_7534
+sym_2_7534: la $2, sym_2_7534
+.globl sym_2_7535
+sym_2_7535: la $2, sym_2_7535
+.globl sym_2_7536
+sym_2_7536: la $2, sym_2_7536
+.globl sym_2_7537
+sym_2_7537: la $2, sym_2_7537
+.globl sym_2_7538
+sym_2_7538: la $2, sym_2_7538
+.globl sym_2_7539
+sym_2_7539: la $2, sym_2_7539
+.globl sym_2_7540
+sym_2_7540: la $2, sym_2_7540
+.globl sym_2_7541
+sym_2_7541: la $2, sym_2_7541
+.globl sym_2_7542
+sym_2_7542: la $2, sym_2_7542
+.globl sym_2_7543
+sym_2_7543: la $2, sym_2_7543
+.globl sym_2_7544
+sym_2_7544: la $2, sym_2_7544
+.globl sym_2_7545
+sym_2_7545: la $2, sym_2_7545
+.globl sym_2_7546
+sym_2_7546: la $2, sym_2_7546
+.globl sym_2_7547
+sym_2_7547: la $2, sym_2_7547
+.globl sym_2_7548
+sym_2_7548: la $2, sym_2_7548
+.globl sym_2_7549
+sym_2_7549: la $2, sym_2_7549
+.globl sym_2_7550
+sym_2_7550: la $2, sym_2_7550
+.globl sym_2_7551
+sym_2_7551: la $2, sym_2_7551
+.globl sym_2_7552
+sym_2_7552: la $2, sym_2_7552
+.globl sym_2_7553
+sym_2_7553: la $2, sym_2_7553
+.globl sym_2_7554
+sym_2_7554: la $2, sym_2_7554
+.globl sym_2_7555
+sym_2_7555: la $2, sym_2_7555
+.globl sym_2_7556
+sym_2_7556: la $2, sym_2_7556
+.globl sym_2_7557
+sym_2_7557: la $2, sym_2_7557
+.globl sym_2_7558
+sym_2_7558: la $2, sym_2_7558
+.globl sym_2_7559
+sym_2_7559: la $2, sym_2_7559
+.globl sym_2_7560
+sym_2_7560: la $2, sym_2_7560
+.globl sym_2_7561
+sym_2_7561: la $2, sym_2_7561
+.globl sym_2_7562
+sym_2_7562: la $2, sym_2_7562
+.globl sym_2_7563
+sym_2_7563: la $2, sym_2_7563
+.globl sym_2_7564
+sym_2_7564: la $2, sym_2_7564
+.globl sym_2_7565
+sym_2_7565: la $2, sym_2_7565
+.globl sym_2_7566
+sym_2_7566: la $2, sym_2_7566
+.globl sym_2_7567
+sym_2_7567: la $2, sym_2_7567
+.globl sym_2_7568
+sym_2_7568: la $2, sym_2_7568
+.globl sym_2_7569
+sym_2_7569: la $2, sym_2_7569
+.globl sym_2_7570
+sym_2_7570: la $2, sym_2_7570
+.globl sym_2_7571
+sym_2_7571: la $2, sym_2_7571
+.globl sym_2_7572
+sym_2_7572: la $2, sym_2_7572
+.globl sym_2_7573
+sym_2_7573: la $2, sym_2_7573
+.globl sym_2_7574
+sym_2_7574: la $2, sym_2_7574
+.globl sym_2_7575
+sym_2_7575: la $2, sym_2_7575
+.globl sym_2_7576
+sym_2_7576: la $2, sym_2_7576
+.globl sym_2_7577
+sym_2_7577: la $2, sym_2_7577
+.globl sym_2_7578
+sym_2_7578: la $2, sym_2_7578
+.globl sym_2_7579
+sym_2_7579: la $2, sym_2_7579
+.globl sym_2_7580
+sym_2_7580: la $2, sym_2_7580
+.globl sym_2_7581
+sym_2_7581: la $2, sym_2_7581
+.globl sym_2_7582
+sym_2_7582: la $2, sym_2_7582
+.globl sym_2_7583
+sym_2_7583: la $2, sym_2_7583
+.globl sym_2_7584
+sym_2_7584: la $2, sym_2_7584
+.globl sym_2_7585
+sym_2_7585: la $2, sym_2_7585
+.globl sym_2_7586
+sym_2_7586: la $2, sym_2_7586
+.globl sym_2_7587
+sym_2_7587: la $2, sym_2_7587
+.globl sym_2_7588
+sym_2_7588: la $2, sym_2_7588
+.globl sym_2_7589
+sym_2_7589: la $2, sym_2_7589
+.globl sym_2_7590
+sym_2_7590: la $2, sym_2_7590
+.globl sym_2_7591
+sym_2_7591: la $2, sym_2_7591
+.globl sym_2_7592
+sym_2_7592: la $2, sym_2_7592
+.globl sym_2_7593
+sym_2_7593: la $2, sym_2_7593
+.globl sym_2_7594
+sym_2_7594: la $2, sym_2_7594
+.globl sym_2_7595
+sym_2_7595: la $2, sym_2_7595
+.globl sym_2_7596
+sym_2_7596: la $2, sym_2_7596
+.globl sym_2_7597
+sym_2_7597: la $2, sym_2_7597
+.globl sym_2_7598
+sym_2_7598: la $2, sym_2_7598
+.globl sym_2_7599
+sym_2_7599: la $2, sym_2_7599
+.globl sym_2_7600
+sym_2_7600: la $2, sym_2_7600
+.globl sym_2_7601
+sym_2_7601: la $2, sym_2_7601
+.globl sym_2_7602
+sym_2_7602: la $2, sym_2_7602
+.globl sym_2_7603
+sym_2_7603: la $2, sym_2_7603
+.globl sym_2_7604
+sym_2_7604: la $2, sym_2_7604
+.globl sym_2_7605
+sym_2_7605: la $2, sym_2_7605
+.globl sym_2_7606
+sym_2_7606: la $2, sym_2_7606
+.globl sym_2_7607
+sym_2_7607: la $2, sym_2_7607
+.globl sym_2_7608
+sym_2_7608: la $2, sym_2_7608
+.globl sym_2_7609
+sym_2_7609: la $2, sym_2_7609
+.globl sym_2_7610
+sym_2_7610: la $2, sym_2_7610
+.globl sym_2_7611
+sym_2_7611: la $2, sym_2_7611
+.globl sym_2_7612
+sym_2_7612: la $2, sym_2_7612
+.globl sym_2_7613
+sym_2_7613: la $2, sym_2_7613
+.globl sym_2_7614
+sym_2_7614: la $2, sym_2_7614
+.globl sym_2_7615
+sym_2_7615: la $2, sym_2_7615
+.globl sym_2_7616
+sym_2_7616: la $2, sym_2_7616
+.globl sym_2_7617
+sym_2_7617: la $2, sym_2_7617
+.globl sym_2_7618
+sym_2_7618: la $2, sym_2_7618
+.globl sym_2_7619
+sym_2_7619: la $2, sym_2_7619
+.globl sym_2_7620
+sym_2_7620: la $2, sym_2_7620
+.globl sym_2_7621
+sym_2_7621: la $2, sym_2_7621
+.globl sym_2_7622
+sym_2_7622: la $2, sym_2_7622
+.globl sym_2_7623
+sym_2_7623: la $2, sym_2_7623
+.globl sym_2_7624
+sym_2_7624: la $2, sym_2_7624
+.globl sym_2_7625
+sym_2_7625: la $2, sym_2_7625
+.globl sym_2_7626
+sym_2_7626: la $2, sym_2_7626
+.globl sym_2_7627
+sym_2_7627: la $2, sym_2_7627
+.globl sym_2_7628
+sym_2_7628: la $2, sym_2_7628
+.globl sym_2_7629
+sym_2_7629: la $2, sym_2_7629
+.globl sym_2_7630
+sym_2_7630: la $2, sym_2_7630
+.globl sym_2_7631
+sym_2_7631: la $2, sym_2_7631
+.globl sym_2_7632
+sym_2_7632: la $2, sym_2_7632
+.globl sym_2_7633
+sym_2_7633: la $2, sym_2_7633
+.globl sym_2_7634
+sym_2_7634: la $2, sym_2_7634
+.globl sym_2_7635
+sym_2_7635: la $2, sym_2_7635
+.globl sym_2_7636
+sym_2_7636: la $2, sym_2_7636
+.globl sym_2_7637
+sym_2_7637: la $2, sym_2_7637
+.globl sym_2_7638
+sym_2_7638: la $2, sym_2_7638
+.globl sym_2_7639
+sym_2_7639: la $2, sym_2_7639
+.globl sym_2_7640
+sym_2_7640: la $2, sym_2_7640
+.globl sym_2_7641
+sym_2_7641: la $2, sym_2_7641
+.globl sym_2_7642
+sym_2_7642: la $2, sym_2_7642
+.globl sym_2_7643
+sym_2_7643: la $2, sym_2_7643
+.globl sym_2_7644
+sym_2_7644: la $2, sym_2_7644
+.globl sym_2_7645
+sym_2_7645: la $2, sym_2_7645
+.globl sym_2_7646
+sym_2_7646: la $2, sym_2_7646
+.globl sym_2_7647
+sym_2_7647: la $2, sym_2_7647
+.globl sym_2_7648
+sym_2_7648: la $2, sym_2_7648
+.globl sym_2_7649
+sym_2_7649: la $2, sym_2_7649
+.globl sym_2_7650
+sym_2_7650: la $2, sym_2_7650
+.globl sym_2_7651
+sym_2_7651: la $2, sym_2_7651
+.globl sym_2_7652
+sym_2_7652: la $2, sym_2_7652
+.globl sym_2_7653
+sym_2_7653: la $2, sym_2_7653
+.globl sym_2_7654
+sym_2_7654: la $2, sym_2_7654
+.globl sym_2_7655
+sym_2_7655: la $2, sym_2_7655
+.globl sym_2_7656
+sym_2_7656: la $2, sym_2_7656
+.globl sym_2_7657
+sym_2_7657: la $2, sym_2_7657
+.globl sym_2_7658
+sym_2_7658: la $2, sym_2_7658
+.globl sym_2_7659
+sym_2_7659: la $2, sym_2_7659
+.globl sym_2_7660
+sym_2_7660: la $2, sym_2_7660
+.globl sym_2_7661
+sym_2_7661: la $2, sym_2_7661
+.globl sym_2_7662
+sym_2_7662: la $2, sym_2_7662
+.globl sym_2_7663
+sym_2_7663: la $2, sym_2_7663
+.globl sym_2_7664
+sym_2_7664: la $2, sym_2_7664
+.globl sym_2_7665
+sym_2_7665: la $2, sym_2_7665
+.globl sym_2_7666
+sym_2_7666: la $2, sym_2_7666
+.globl sym_2_7667
+sym_2_7667: la $2, sym_2_7667
+.globl sym_2_7668
+sym_2_7668: la $2, sym_2_7668
+.globl sym_2_7669
+sym_2_7669: la $2, sym_2_7669
+.globl sym_2_7670
+sym_2_7670: la $2, sym_2_7670
+.globl sym_2_7671
+sym_2_7671: la $2, sym_2_7671
+.globl sym_2_7672
+sym_2_7672: la $2, sym_2_7672
+.globl sym_2_7673
+sym_2_7673: la $2, sym_2_7673
+.globl sym_2_7674
+sym_2_7674: la $2, sym_2_7674
+.globl sym_2_7675
+sym_2_7675: la $2, sym_2_7675
+.globl sym_2_7676
+sym_2_7676: la $2, sym_2_7676
+.globl sym_2_7677
+sym_2_7677: la $2, sym_2_7677
+.globl sym_2_7678
+sym_2_7678: la $2, sym_2_7678
+.globl sym_2_7679
+sym_2_7679: la $2, sym_2_7679
+.globl sym_2_7680
+sym_2_7680: la $2, sym_2_7680
+.globl sym_2_7681
+sym_2_7681: la $2, sym_2_7681
+.globl sym_2_7682
+sym_2_7682: la $2, sym_2_7682
+.globl sym_2_7683
+sym_2_7683: la $2, sym_2_7683
+.globl sym_2_7684
+sym_2_7684: la $2, sym_2_7684
+.globl sym_2_7685
+sym_2_7685: la $2, sym_2_7685
+.globl sym_2_7686
+sym_2_7686: la $2, sym_2_7686
+.globl sym_2_7687
+sym_2_7687: la $2, sym_2_7687
+.globl sym_2_7688
+sym_2_7688: la $2, sym_2_7688
+.globl sym_2_7689
+sym_2_7689: la $2, sym_2_7689
+.globl sym_2_7690
+sym_2_7690: la $2, sym_2_7690
+.globl sym_2_7691
+sym_2_7691: la $2, sym_2_7691
+.globl sym_2_7692
+sym_2_7692: la $2, sym_2_7692
+.globl sym_2_7693
+sym_2_7693: la $2, sym_2_7693
+.globl sym_2_7694
+sym_2_7694: la $2, sym_2_7694
+.globl sym_2_7695
+sym_2_7695: la $2, sym_2_7695
+.globl sym_2_7696
+sym_2_7696: la $2, sym_2_7696
+.globl sym_2_7697
+sym_2_7697: la $2, sym_2_7697
+.globl sym_2_7698
+sym_2_7698: la $2, sym_2_7698
+.globl sym_2_7699
+sym_2_7699: la $2, sym_2_7699
+.globl sym_2_7700
+sym_2_7700: la $2, sym_2_7700
+.globl sym_2_7701
+sym_2_7701: la $2, sym_2_7701
+.globl sym_2_7702
+sym_2_7702: la $2, sym_2_7702
+.globl sym_2_7703
+sym_2_7703: la $2, sym_2_7703
+.globl sym_2_7704
+sym_2_7704: la $2, sym_2_7704
+.globl sym_2_7705
+sym_2_7705: la $2, sym_2_7705
+.globl sym_2_7706
+sym_2_7706: la $2, sym_2_7706
+.globl sym_2_7707
+sym_2_7707: la $2, sym_2_7707
+.globl sym_2_7708
+sym_2_7708: la $2, sym_2_7708
+.globl sym_2_7709
+sym_2_7709: la $2, sym_2_7709
+.globl sym_2_7710
+sym_2_7710: la $2, sym_2_7710
+.globl sym_2_7711
+sym_2_7711: la $2, sym_2_7711
+.globl sym_2_7712
+sym_2_7712: la $2, sym_2_7712
+.globl sym_2_7713
+sym_2_7713: la $2, sym_2_7713
+.globl sym_2_7714
+sym_2_7714: la $2, sym_2_7714
+.globl sym_2_7715
+sym_2_7715: la $2, sym_2_7715
+.globl sym_2_7716
+sym_2_7716: la $2, sym_2_7716
+.globl sym_2_7717
+sym_2_7717: la $2, sym_2_7717
+.globl sym_2_7718
+sym_2_7718: la $2, sym_2_7718
+.globl sym_2_7719
+sym_2_7719: la $2, sym_2_7719
+.globl sym_2_7720
+sym_2_7720: la $2, sym_2_7720
+.globl sym_2_7721
+sym_2_7721: la $2, sym_2_7721
+.globl sym_2_7722
+sym_2_7722: la $2, sym_2_7722
+.globl sym_2_7723
+sym_2_7723: la $2, sym_2_7723
+.globl sym_2_7724
+sym_2_7724: la $2, sym_2_7724
+.globl sym_2_7725
+sym_2_7725: la $2, sym_2_7725
+.globl sym_2_7726
+sym_2_7726: la $2, sym_2_7726
+.globl sym_2_7727
+sym_2_7727: la $2, sym_2_7727
+.globl sym_2_7728
+sym_2_7728: la $2, sym_2_7728
+.globl sym_2_7729
+sym_2_7729: la $2, sym_2_7729
+.globl sym_2_7730
+sym_2_7730: la $2, sym_2_7730
+.globl sym_2_7731
+sym_2_7731: la $2, sym_2_7731
+.globl sym_2_7732
+sym_2_7732: la $2, sym_2_7732
+.globl sym_2_7733
+sym_2_7733: la $2, sym_2_7733
+.globl sym_2_7734
+sym_2_7734: la $2, sym_2_7734
+.globl sym_2_7735
+sym_2_7735: la $2, sym_2_7735
+.globl sym_2_7736
+sym_2_7736: la $2, sym_2_7736
+.globl sym_2_7737
+sym_2_7737: la $2, sym_2_7737
+.globl sym_2_7738
+sym_2_7738: la $2, sym_2_7738
+.globl sym_2_7739
+sym_2_7739: la $2, sym_2_7739
+.globl sym_2_7740
+sym_2_7740: la $2, sym_2_7740
+.globl sym_2_7741
+sym_2_7741: la $2, sym_2_7741
+.globl sym_2_7742
+sym_2_7742: la $2, sym_2_7742
+.globl sym_2_7743
+sym_2_7743: la $2, sym_2_7743
+.globl sym_2_7744
+sym_2_7744: la $2, sym_2_7744
+.globl sym_2_7745
+sym_2_7745: la $2, sym_2_7745
+.globl sym_2_7746
+sym_2_7746: la $2, sym_2_7746
+.globl sym_2_7747
+sym_2_7747: la $2, sym_2_7747
+.globl sym_2_7748
+sym_2_7748: la $2, sym_2_7748
+.globl sym_2_7749
+sym_2_7749: la $2, sym_2_7749
+.globl sym_2_7750
+sym_2_7750: la $2, sym_2_7750
+.globl sym_2_7751
+sym_2_7751: la $2, sym_2_7751
+.globl sym_2_7752
+sym_2_7752: la $2, sym_2_7752
+.globl sym_2_7753
+sym_2_7753: la $2, sym_2_7753
+.globl sym_2_7754
+sym_2_7754: la $2, sym_2_7754
+.globl sym_2_7755
+sym_2_7755: la $2, sym_2_7755
+.globl sym_2_7756
+sym_2_7756: la $2, sym_2_7756
+.globl sym_2_7757
+sym_2_7757: la $2, sym_2_7757
+.globl sym_2_7758
+sym_2_7758: la $2, sym_2_7758
+.globl sym_2_7759
+sym_2_7759: la $2, sym_2_7759
+.globl sym_2_7760
+sym_2_7760: la $2, sym_2_7760
+.globl sym_2_7761
+sym_2_7761: la $2, sym_2_7761
+.globl sym_2_7762
+sym_2_7762: la $2, sym_2_7762
+.globl sym_2_7763
+sym_2_7763: la $2, sym_2_7763
+.globl sym_2_7764
+sym_2_7764: la $2, sym_2_7764
+.globl sym_2_7765
+sym_2_7765: la $2, sym_2_7765
+.globl sym_2_7766
+sym_2_7766: la $2, sym_2_7766
+.globl sym_2_7767
+sym_2_7767: la $2, sym_2_7767
+.globl sym_2_7768
+sym_2_7768: la $2, sym_2_7768
+.globl sym_2_7769
+sym_2_7769: la $2, sym_2_7769
+.globl sym_2_7770
+sym_2_7770: la $2, sym_2_7770
+.globl sym_2_7771
+sym_2_7771: la $2, sym_2_7771
+.globl sym_2_7772
+sym_2_7772: la $2, sym_2_7772
+.globl sym_2_7773
+sym_2_7773: la $2, sym_2_7773
+.globl sym_2_7774
+sym_2_7774: la $2, sym_2_7774
+.globl sym_2_7775
+sym_2_7775: la $2, sym_2_7775
+.globl sym_2_7776
+sym_2_7776: la $2, sym_2_7776
+.globl sym_2_7777
+sym_2_7777: la $2, sym_2_7777
+.globl sym_2_7778
+sym_2_7778: la $2, sym_2_7778
+.globl sym_2_7779
+sym_2_7779: la $2, sym_2_7779
+.globl sym_2_7780
+sym_2_7780: la $2, sym_2_7780
+.globl sym_2_7781
+sym_2_7781: la $2, sym_2_7781
+.globl sym_2_7782
+sym_2_7782: la $2, sym_2_7782
+.globl sym_2_7783
+sym_2_7783: la $2, sym_2_7783
+.globl sym_2_7784
+sym_2_7784: la $2, sym_2_7784
+.globl sym_2_7785
+sym_2_7785: la $2, sym_2_7785
+.globl sym_2_7786
+sym_2_7786: la $2, sym_2_7786
+.globl sym_2_7787
+sym_2_7787: la $2, sym_2_7787
+.globl sym_2_7788
+sym_2_7788: la $2, sym_2_7788
+.globl sym_2_7789
+sym_2_7789: la $2, sym_2_7789
+.globl sym_2_7790
+sym_2_7790: la $2, sym_2_7790
+.globl sym_2_7791
+sym_2_7791: la $2, sym_2_7791
+.globl sym_2_7792
+sym_2_7792: la $2, sym_2_7792
+.globl sym_2_7793
+sym_2_7793: la $2, sym_2_7793
+.globl sym_2_7794
+sym_2_7794: la $2, sym_2_7794
+.globl sym_2_7795
+sym_2_7795: la $2, sym_2_7795
+.globl sym_2_7796
+sym_2_7796: la $2, sym_2_7796
+.globl sym_2_7797
+sym_2_7797: la $2, sym_2_7797
+.globl sym_2_7798
+sym_2_7798: la $2, sym_2_7798
+.globl sym_2_7799
+sym_2_7799: la $2, sym_2_7799
+.globl sym_2_7800
+sym_2_7800: la $2, sym_2_7800
+.globl sym_2_7801
+sym_2_7801: la $2, sym_2_7801
+.globl sym_2_7802
+sym_2_7802: la $2, sym_2_7802
+.globl sym_2_7803
+sym_2_7803: la $2, sym_2_7803
+.globl sym_2_7804
+sym_2_7804: la $2, sym_2_7804
+.globl sym_2_7805
+sym_2_7805: la $2, sym_2_7805
+.globl sym_2_7806
+sym_2_7806: la $2, sym_2_7806
+.globl sym_2_7807
+sym_2_7807: la $2, sym_2_7807
+.globl sym_2_7808
+sym_2_7808: la $2, sym_2_7808
+.globl sym_2_7809
+sym_2_7809: la $2, sym_2_7809
+.globl sym_2_7810
+sym_2_7810: la $2, sym_2_7810
+.globl sym_2_7811
+sym_2_7811: la $2, sym_2_7811
+.globl sym_2_7812
+sym_2_7812: la $2, sym_2_7812
+.globl sym_2_7813
+sym_2_7813: la $2, sym_2_7813
+.globl sym_2_7814
+sym_2_7814: la $2, sym_2_7814
+.globl sym_2_7815
+sym_2_7815: la $2, sym_2_7815
+.globl sym_2_7816
+sym_2_7816: la $2, sym_2_7816
+.globl sym_2_7817
+sym_2_7817: la $2, sym_2_7817
+.globl sym_2_7818
+sym_2_7818: la $2, sym_2_7818
+.globl sym_2_7819
+sym_2_7819: la $2, sym_2_7819
+.globl sym_2_7820
+sym_2_7820: la $2, sym_2_7820
+.globl sym_2_7821
+sym_2_7821: la $2, sym_2_7821
+.globl sym_2_7822
+sym_2_7822: la $2, sym_2_7822
+.globl sym_2_7823
+sym_2_7823: la $2, sym_2_7823
+.globl sym_2_7824
+sym_2_7824: la $2, sym_2_7824
+.globl sym_2_7825
+sym_2_7825: la $2, sym_2_7825
+.globl sym_2_7826
+sym_2_7826: la $2, sym_2_7826
+.globl sym_2_7827
+sym_2_7827: la $2, sym_2_7827
+.globl sym_2_7828
+sym_2_7828: la $2, sym_2_7828
+.globl sym_2_7829
+sym_2_7829: la $2, sym_2_7829
+.globl sym_2_7830
+sym_2_7830: la $2, sym_2_7830
+.globl sym_2_7831
+sym_2_7831: la $2, sym_2_7831
+.globl sym_2_7832
+sym_2_7832: la $2, sym_2_7832
+.globl sym_2_7833
+sym_2_7833: la $2, sym_2_7833
+.globl sym_2_7834
+sym_2_7834: la $2, sym_2_7834
+.globl sym_2_7835
+sym_2_7835: la $2, sym_2_7835
+.globl sym_2_7836
+sym_2_7836: la $2, sym_2_7836
+.globl sym_2_7837
+sym_2_7837: la $2, sym_2_7837
+.globl sym_2_7838
+sym_2_7838: la $2, sym_2_7838
+.globl sym_2_7839
+sym_2_7839: la $2, sym_2_7839
+.globl sym_2_7840
+sym_2_7840: la $2, sym_2_7840
+.globl sym_2_7841
+sym_2_7841: la $2, sym_2_7841
+.globl sym_2_7842
+sym_2_7842: la $2, sym_2_7842
+.globl sym_2_7843
+sym_2_7843: la $2, sym_2_7843
+.globl sym_2_7844
+sym_2_7844: la $2, sym_2_7844
+.globl sym_2_7845
+sym_2_7845: la $2, sym_2_7845
+.globl sym_2_7846
+sym_2_7846: la $2, sym_2_7846
+.globl sym_2_7847
+sym_2_7847: la $2, sym_2_7847
+.globl sym_2_7848
+sym_2_7848: la $2, sym_2_7848
+.globl sym_2_7849
+sym_2_7849: la $2, sym_2_7849
+.globl sym_2_7850
+sym_2_7850: la $2, sym_2_7850
+.globl sym_2_7851
+sym_2_7851: la $2, sym_2_7851
+.globl sym_2_7852
+sym_2_7852: la $2, sym_2_7852
+.globl sym_2_7853
+sym_2_7853: la $2, sym_2_7853
+.globl sym_2_7854
+sym_2_7854: la $2, sym_2_7854
+.globl sym_2_7855
+sym_2_7855: la $2, sym_2_7855
+.globl sym_2_7856
+sym_2_7856: la $2, sym_2_7856
+.globl sym_2_7857
+sym_2_7857: la $2, sym_2_7857
+.globl sym_2_7858
+sym_2_7858: la $2, sym_2_7858
+.globl sym_2_7859
+sym_2_7859: la $2, sym_2_7859
+.globl sym_2_7860
+sym_2_7860: la $2, sym_2_7860
+.globl sym_2_7861
+sym_2_7861: la $2, sym_2_7861
+.globl sym_2_7862
+sym_2_7862: la $2, sym_2_7862
+.globl sym_2_7863
+sym_2_7863: la $2, sym_2_7863
+.globl sym_2_7864
+sym_2_7864: la $2, sym_2_7864
+.globl sym_2_7865
+sym_2_7865: la $2, sym_2_7865
+.globl sym_2_7866
+sym_2_7866: la $2, sym_2_7866
+.globl sym_2_7867
+sym_2_7867: la $2, sym_2_7867
+.globl sym_2_7868
+sym_2_7868: la $2, sym_2_7868
+.globl sym_2_7869
+sym_2_7869: la $2, sym_2_7869
+.globl sym_2_7870
+sym_2_7870: la $2, sym_2_7870
+.globl sym_2_7871
+sym_2_7871: la $2, sym_2_7871
+.globl sym_2_7872
+sym_2_7872: la $2, sym_2_7872
+.globl sym_2_7873
+sym_2_7873: la $2, sym_2_7873
+.globl sym_2_7874
+sym_2_7874: la $2, sym_2_7874
+.globl sym_2_7875
+sym_2_7875: la $2, sym_2_7875
+.globl sym_2_7876
+sym_2_7876: la $2, sym_2_7876
+.globl sym_2_7877
+sym_2_7877: la $2, sym_2_7877
+.globl sym_2_7878
+sym_2_7878: la $2, sym_2_7878
+.globl sym_2_7879
+sym_2_7879: la $2, sym_2_7879
+.globl sym_2_7880
+sym_2_7880: la $2, sym_2_7880
+.globl sym_2_7881
+sym_2_7881: la $2, sym_2_7881
+.globl sym_2_7882
+sym_2_7882: la $2, sym_2_7882
+.globl sym_2_7883
+sym_2_7883: la $2, sym_2_7883
+.globl sym_2_7884
+sym_2_7884: la $2, sym_2_7884
+.globl sym_2_7885
+sym_2_7885: la $2, sym_2_7885
+.globl sym_2_7886
+sym_2_7886: la $2, sym_2_7886
+.globl sym_2_7887
+sym_2_7887: la $2, sym_2_7887
+.globl sym_2_7888
+sym_2_7888: la $2, sym_2_7888
+.globl sym_2_7889
+sym_2_7889: la $2, sym_2_7889
+.globl sym_2_7890
+sym_2_7890: la $2, sym_2_7890
+.globl sym_2_7891
+sym_2_7891: la $2, sym_2_7891
+.globl sym_2_7892
+sym_2_7892: la $2, sym_2_7892
+.globl sym_2_7893
+sym_2_7893: la $2, sym_2_7893
+.globl sym_2_7894
+sym_2_7894: la $2, sym_2_7894
+.globl sym_2_7895
+sym_2_7895: la $2, sym_2_7895
+.globl sym_2_7896
+sym_2_7896: la $2, sym_2_7896
+.globl sym_2_7897
+sym_2_7897: la $2, sym_2_7897
+.globl sym_2_7898
+sym_2_7898: la $2, sym_2_7898
+.globl sym_2_7899
+sym_2_7899: la $2, sym_2_7899
+.globl sym_2_7900
+sym_2_7900: la $2, sym_2_7900
+.globl sym_2_7901
+sym_2_7901: la $2, sym_2_7901
+.globl sym_2_7902
+sym_2_7902: la $2, sym_2_7902
+.globl sym_2_7903
+sym_2_7903: la $2, sym_2_7903
+.globl sym_2_7904
+sym_2_7904: la $2, sym_2_7904
+.globl sym_2_7905
+sym_2_7905: la $2, sym_2_7905
+.globl sym_2_7906
+sym_2_7906: la $2, sym_2_7906
+.globl sym_2_7907
+sym_2_7907: la $2, sym_2_7907
+.globl sym_2_7908
+sym_2_7908: la $2, sym_2_7908
+.globl sym_2_7909
+sym_2_7909: la $2, sym_2_7909
+.globl sym_2_7910
+sym_2_7910: la $2, sym_2_7910
+.globl sym_2_7911
+sym_2_7911: la $2, sym_2_7911
+.globl sym_2_7912
+sym_2_7912: la $2, sym_2_7912
+.globl sym_2_7913
+sym_2_7913: la $2, sym_2_7913
+.globl sym_2_7914
+sym_2_7914: la $2, sym_2_7914
+.globl sym_2_7915
+sym_2_7915: la $2, sym_2_7915
+.globl sym_2_7916
+sym_2_7916: la $2, sym_2_7916
+.globl sym_2_7917
+sym_2_7917: la $2, sym_2_7917
+.globl sym_2_7918
+sym_2_7918: la $2, sym_2_7918
+.globl sym_2_7919
+sym_2_7919: la $2, sym_2_7919
+.globl sym_2_7920
+sym_2_7920: la $2, sym_2_7920
+.globl sym_2_7921
+sym_2_7921: la $2, sym_2_7921
+.globl sym_2_7922
+sym_2_7922: la $2, sym_2_7922
+.globl sym_2_7923
+sym_2_7923: la $2, sym_2_7923
+.globl sym_2_7924
+sym_2_7924: la $2, sym_2_7924
+.globl sym_2_7925
+sym_2_7925: la $2, sym_2_7925
+.globl sym_2_7926
+sym_2_7926: la $2, sym_2_7926
+.globl sym_2_7927
+sym_2_7927: la $2, sym_2_7927
+.globl sym_2_7928
+sym_2_7928: la $2, sym_2_7928
+.globl sym_2_7929
+sym_2_7929: la $2, sym_2_7929
+.globl sym_2_7930
+sym_2_7930: la $2, sym_2_7930
+.globl sym_2_7931
+sym_2_7931: la $2, sym_2_7931
+.globl sym_2_7932
+sym_2_7932: la $2, sym_2_7932
+.globl sym_2_7933
+sym_2_7933: la $2, sym_2_7933
+.globl sym_2_7934
+sym_2_7934: la $2, sym_2_7934
+.globl sym_2_7935
+sym_2_7935: la $2, sym_2_7935
+.globl sym_2_7936
+sym_2_7936: la $2, sym_2_7936
+.globl sym_2_7937
+sym_2_7937: la $2, sym_2_7937
+.globl sym_2_7938
+sym_2_7938: la $2, sym_2_7938
+.globl sym_2_7939
+sym_2_7939: la $2, sym_2_7939
+.globl sym_2_7940
+sym_2_7940: la $2, sym_2_7940
+.globl sym_2_7941
+sym_2_7941: la $2, sym_2_7941
+.globl sym_2_7942
+sym_2_7942: la $2, sym_2_7942
+.globl sym_2_7943
+sym_2_7943: la $2, sym_2_7943
+.globl sym_2_7944
+sym_2_7944: la $2, sym_2_7944
+.globl sym_2_7945
+sym_2_7945: la $2, sym_2_7945
+.globl sym_2_7946
+sym_2_7946: la $2, sym_2_7946
+.globl sym_2_7947
+sym_2_7947: la $2, sym_2_7947
+.globl sym_2_7948
+sym_2_7948: la $2, sym_2_7948
+.globl sym_2_7949
+sym_2_7949: la $2, sym_2_7949
+.globl sym_2_7950
+sym_2_7950: la $2, sym_2_7950
+.globl sym_2_7951
+sym_2_7951: la $2, sym_2_7951
+.globl sym_2_7952
+sym_2_7952: la $2, sym_2_7952
+.globl sym_2_7953
+sym_2_7953: la $2, sym_2_7953
+.globl sym_2_7954
+sym_2_7954: la $2, sym_2_7954
+.globl sym_2_7955
+sym_2_7955: la $2, sym_2_7955
+.globl sym_2_7956
+sym_2_7956: la $2, sym_2_7956
+.globl sym_2_7957
+sym_2_7957: la $2, sym_2_7957
+.globl sym_2_7958
+sym_2_7958: la $2, sym_2_7958
+.globl sym_2_7959
+sym_2_7959: la $2, sym_2_7959
+.globl sym_2_7960
+sym_2_7960: la $2, sym_2_7960
+.globl sym_2_7961
+sym_2_7961: la $2, sym_2_7961
+.globl sym_2_7962
+sym_2_7962: la $2, sym_2_7962
+.globl sym_2_7963
+sym_2_7963: la $2, sym_2_7963
+.globl sym_2_7964
+sym_2_7964: la $2, sym_2_7964
+.globl sym_2_7965
+sym_2_7965: la $2, sym_2_7965
+.globl sym_2_7966
+sym_2_7966: la $2, sym_2_7966
+.globl sym_2_7967
+sym_2_7967: la $2, sym_2_7967
+.globl sym_2_7968
+sym_2_7968: la $2, sym_2_7968
+.globl sym_2_7969
+sym_2_7969: la $2, sym_2_7969
+.globl sym_2_7970
+sym_2_7970: la $2, sym_2_7970
+.globl sym_2_7971
+sym_2_7971: la $2, sym_2_7971
+.globl sym_2_7972
+sym_2_7972: la $2, sym_2_7972
+.globl sym_2_7973
+sym_2_7973: la $2, sym_2_7973
+.globl sym_2_7974
+sym_2_7974: la $2, sym_2_7974
+.globl sym_2_7975
+sym_2_7975: la $2, sym_2_7975
+.globl sym_2_7976
+sym_2_7976: la $2, sym_2_7976
+.globl sym_2_7977
+sym_2_7977: la $2, sym_2_7977
+.globl sym_2_7978
+sym_2_7978: la $2, sym_2_7978
+.globl sym_2_7979
+sym_2_7979: la $2, sym_2_7979
+.globl sym_2_7980
+sym_2_7980: la $2, sym_2_7980
+.globl sym_2_7981
+sym_2_7981: la $2, sym_2_7981
+.globl sym_2_7982
+sym_2_7982: la $2, sym_2_7982
+.globl sym_2_7983
+sym_2_7983: la $2, sym_2_7983
+.globl sym_2_7984
+sym_2_7984: la $2, sym_2_7984
+.globl sym_2_7985
+sym_2_7985: la $2, sym_2_7985
+.globl sym_2_7986
+sym_2_7986: la $2, sym_2_7986
+.globl sym_2_7987
+sym_2_7987: la $2, sym_2_7987
+.globl sym_2_7988
+sym_2_7988: la $2, sym_2_7988
+.globl sym_2_7989
+sym_2_7989: la $2, sym_2_7989
+.globl sym_2_7990
+sym_2_7990: la $2, sym_2_7990
+.globl sym_2_7991
+sym_2_7991: la $2, sym_2_7991
+.globl sym_2_7992
+sym_2_7992: la $2, sym_2_7992
+.globl sym_2_7993
+sym_2_7993: la $2, sym_2_7993
+.globl sym_2_7994
+sym_2_7994: la $2, sym_2_7994
+.globl sym_2_7995
+sym_2_7995: la $2, sym_2_7995
+.globl sym_2_7996
+sym_2_7996: la $2, sym_2_7996
+.globl sym_2_7997
+sym_2_7997: la $2, sym_2_7997
+.globl sym_2_7998
+sym_2_7998: la $2, sym_2_7998
+.globl sym_2_7999
+sym_2_7999: la $2, sym_2_7999
+.globl sym_2_8000
+sym_2_8000: la $2, sym_2_8000
+.globl sym_2_8001
+sym_2_8001: la $2, sym_2_8001
+.globl sym_2_8002
+sym_2_8002: la $2, sym_2_8002
+.globl sym_2_8003
+sym_2_8003: la $2, sym_2_8003
+.globl sym_2_8004
+sym_2_8004: la $2, sym_2_8004
+.globl sym_2_8005
+sym_2_8005: la $2, sym_2_8005
+.globl sym_2_8006
+sym_2_8006: la $2, sym_2_8006
+.globl sym_2_8007
+sym_2_8007: la $2, sym_2_8007
+.globl sym_2_8008
+sym_2_8008: la $2, sym_2_8008
+.globl sym_2_8009
+sym_2_8009: la $2, sym_2_8009
+.globl sym_2_8010
+sym_2_8010: la $2, sym_2_8010
+.globl sym_2_8011
+sym_2_8011: la $2, sym_2_8011
+.globl sym_2_8012
+sym_2_8012: la $2, sym_2_8012
+.globl sym_2_8013
+sym_2_8013: la $2, sym_2_8013
+.globl sym_2_8014
+sym_2_8014: la $2, sym_2_8014
+.globl sym_2_8015
+sym_2_8015: la $2, sym_2_8015
+.globl sym_2_8016
+sym_2_8016: la $2, sym_2_8016
+.globl sym_2_8017
+sym_2_8017: la $2, sym_2_8017
+.globl sym_2_8018
+sym_2_8018: la $2, sym_2_8018
+.globl sym_2_8019
+sym_2_8019: la $2, sym_2_8019
+.globl sym_2_8020
+sym_2_8020: la $2, sym_2_8020
+.globl sym_2_8021
+sym_2_8021: la $2, sym_2_8021
+.globl sym_2_8022
+sym_2_8022: la $2, sym_2_8022
+.globl sym_2_8023
+sym_2_8023: la $2, sym_2_8023
+.globl sym_2_8024
+sym_2_8024: la $2, sym_2_8024
+.globl sym_2_8025
+sym_2_8025: la $2, sym_2_8025
+.globl sym_2_8026
+sym_2_8026: la $2, sym_2_8026
+.globl sym_2_8027
+sym_2_8027: la $2, sym_2_8027
+.globl sym_2_8028
+sym_2_8028: la $2, sym_2_8028
+.globl sym_2_8029
+sym_2_8029: la $2, sym_2_8029
+.globl sym_2_8030
+sym_2_8030: la $2, sym_2_8030
+.globl sym_2_8031
+sym_2_8031: la $2, sym_2_8031
+.globl sym_2_8032
+sym_2_8032: la $2, sym_2_8032
+.globl sym_2_8033
+sym_2_8033: la $2, sym_2_8033
+.globl sym_2_8034
+sym_2_8034: la $2, sym_2_8034
+.globl sym_2_8035
+sym_2_8035: la $2, sym_2_8035
+.globl sym_2_8036
+sym_2_8036: la $2, sym_2_8036
+.globl sym_2_8037
+sym_2_8037: la $2, sym_2_8037
+.globl sym_2_8038
+sym_2_8038: la $2, sym_2_8038
+.globl sym_2_8039
+sym_2_8039: la $2, sym_2_8039
+.globl sym_2_8040
+sym_2_8040: la $2, sym_2_8040
+.globl sym_2_8041
+sym_2_8041: la $2, sym_2_8041
+.globl sym_2_8042
+sym_2_8042: la $2, sym_2_8042
+.globl sym_2_8043
+sym_2_8043: la $2, sym_2_8043
+.globl sym_2_8044
+sym_2_8044: la $2, sym_2_8044
+.globl sym_2_8045
+sym_2_8045: la $2, sym_2_8045
+.globl sym_2_8046
+sym_2_8046: la $2, sym_2_8046
+.globl sym_2_8047
+sym_2_8047: la $2, sym_2_8047
+.globl sym_2_8048
+sym_2_8048: la $2, sym_2_8048
+.globl sym_2_8049
+sym_2_8049: la $2, sym_2_8049
+.globl sym_2_8050
+sym_2_8050: la $2, sym_2_8050
+.globl sym_2_8051
+sym_2_8051: la $2, sym_2_8051
+.globl sym_2_8052
+sym_2_8052: la $2, sym_2_8052
+.globl sym_2_8053
+sym_2_8053: la $2, sym_2_8053
+.globl sym_2_8054
+sym_2_8054: la $2, sym_2_8054
+.globl sym_2_8055
+sym_2_8055: la $2, sym_2_8055
+.globl sym_2_8056
+sym_2_8056: la $2, sym_2_8056
+.globl sym_2_8057
+sym_2_8057: la $2, sym_2_8057
+.globl sym_2_8058
+sym_2_8058: la $2, sym_2_8058
+.globl sym_2_8059
+sym_2_8059: la $2, sym_2_8059
+.globl sym_2_8060
+sym_2_8060: la $2, sym_2_8060
+.globl sym_2_8061
+sym_2_8061: la $2, sym_2_8061
+.globl sym_2_8062
+sym_2_8062: la $2, sym_2_8062
+.globl sym_2_8063
+sym_2_8063: la $2, sym_2_8063
+.globl sym_2_8064
+sym_2_8064: la $2, sym_2_8064
+.globl sym_2_8065
+sym_2_8065: la $2, sym_2_8065
+.globl sym_2_8066
+sym_2_8066: la $2, sym_2_8066
+.globl sym_2_8067
+sym_2_8067: la $2, sym_2_8067
+.globl sym_2_8068
+sym_2_8068: la $2, sym_2_8068
+.globl sym_2_8069
+sym_2_8069: la $2, sym_2_8069
+.globl sym_2_8070
+sym_2_8070: la $2, sym_2_8070
+.globl sym_2_8071
+sym_2_8071: la $2, sym_2_8071
+.globl sym_2_8072
+sym_2_8072: la $2, sym_2_8072
+.globl sym_2_8073
+sym_2_8073: la $2, sym_2_8073
+.globl sym_2_8074
+sym_2_8074: la $2, sym_2_8074
+.globl sym_2_8075
+sym_2_8075: la $2, sym_2_8075
+.globl sym_2_8076
+sym_2_8076: la $2, sym_2_8076
+.globl sym_2_8077
+sym_2_8077: la $2, sym_2_8077
+.globl sym_2_8078
+sym_2_8078: la $2, sym_2_8078
+.globl sym_2_8079
+sym_2_8079: la $2, sym_2_8079
+.globl sym_2_8080
+sym_2_8080: la $2, sym_2_8080
+.globl sym_2_8081
+sym_2_8081: la $2, sym_2_8081
+.globl sym_2_8082
+sym_2_8082: la $2, sym_2_8082
+.globl sym_2_8083
+sym_2_8083: la $2, sym_2_8083
+.globl sym_2_8084
+sym_2_8084: la $2, sym_2_8084
+.globl sym_2_8085
+sym_2_8085: la $2, sym_2_8085
+.globl sym_2_8086
+sym_2_8086: la $2, sym_2_8086
+.globl sym_2_8087
+sym_2_8087: la $2, sym_2_8087
+.globl sym_2_8088
+sym_2_8088: la $2, sym_2_8088
+.globl sym_2_8089
+sym_2_8089: la $2, sym_2_8089
+.globl sym_2_8090
+sym_2_8090: la $2, sym_2_8090
+.globl sym_2_8091
+sym_2_8091: la $2, sym_2_8091
+.globl sym_2_8092
+sym_2_8092: la $2, sym_2_8092
+.globl sym_2_8093
+sym_2_8093: la $2, sym_2_8093
+.globl sym_2_8094
+sym_2_8094: la $2, sym_2_8094
+.globl sym_2_8095
+sym_2_8095: la $2, sym_2_8095
+.globl sym_2_8096
+sym_2_8096: la $2, sym_2_8096
+.globl sym_2_8097
+sym_2_8097: la $2, sym_2_8097
+.globl sym_2_8098
+sym_2_8098: la $2, sym_2_8098
+.globl sym_2_8099
+sym_2_8099: la $2, sym_2_8099
+.globl sym_2_8100
+sym_2_8100: la $2, sym_2_8100
+.globl sym_2_8101
+sym_2_8101: la $2, sym_2_8101
+.globl sym_2_8102
+sym_2_8102: la $2, sym_2_8102
+.globl sym_2_8103
+sym_2_8103: la $2, sym_2_8103
+.globl sym_2_8104
+sym_2_8104: la $2, sym_2_8104
+.globl sym_2_8105
+sym_2_8105: la $2, sym_2_8105
+.globl sym_2_8106
+sym_2_8106: la $2, sym_2_8106
+.globl sym_2_8107
+sym_2_8107: la $2, sym_2_8107
+.globl sym_2_8108
+sym_2_8108: la $2, sym_2_8108
+.globl sym_2_8109
+sym_2_8109: la $2, sym_2_8109
+.globl sym_2_8110
+sym_2_8110: la $2, sym_2_8110
+.globl sym_2_8111
+sym_2_8111: la $2, sym_2_8111
+.globl sym_2_8112
+sym_2_8112: la $2, sym_2_8112
+.globl sym_2_8113
+sym_2_8113: la $2, sym_2_8113
+.globl sym_2_8114
+sym_2_8114: la $2, sym_2_8114
+.globl sym_2_8115
+sym_2_8115: la $2, sym_2_8115
+.globl sym_2_8116
+sym_2_8116: la $2, sym_2_8116
+.globl sym_2_8117
+sym_2_8117: la $2, sym_2_8117
+.globl sym_2_8118
+sym_2_8118: la $2, sym_2_8118
+.globl sym_2_8119
+sym_2_8119: la $2, sym_2_8119
+.globl sym_2_8120
+sym_2_8120: la $2, sym_2_8120
+.globl sym_2_8121
+sym_2_8121: la $2, sym_2_8121
+.globl sym_2_8122
+sym_2_8122: la $2, sym_2_8122
+.globl sym_2_8123
+sym_2_8123: la $2, sym_2_8123
+.globl sym_2_8124
+sym_2_8124: la $2, sym_2_8124
+.globl sym_2_8125
+sym_2_8125: la $2, sym_2_8125
+.globl sym_2_8126
+sym_2_8126: la $2, sym_2_8126
+.globl sym_2_8127
+sym_2_8127: la $2, sym_2_8127
+.globl sym_2_8128
+sym_2_8128: la $2, sym_2_8128
+.globl sym_2_8129
+sym_2_8129: la $2, sym_2_8129
+.globl sym_2_8130
+sym_2_8130: la $2, sym_2_8130
+.globl sym_2_8131
+sym_2_8131: la $2, sym_2_8131
+.globl sym_2_8132
+sym_2_8132: la $2, sym_2_8132
+.globl sym_2_8133
+sym_2_8133: la $2, sym_2_8133
+.globl sym_2_8134
+sym_2_8134: la $2, sym_2_8134
+.globl sym_2_8135
+sym_2_8135: la $2, sym_2_8135
+.globl sym_2_8136
+sym_2_8136: la $2, sym_2_8136
+.globl sym_2_8137
+sym_2_8137: la $2, sym_2_8137
+.globl sym_2_8138
+sym_2_8138: la $2, sym_2_8138
+.globl sym_2_8139
+sym_2_8139: la $2, sym_2_8139
+.globl sym_2_8140
+sym_2_8140: la $2, sym_2_8140
+.globl sym_2_8141
+sym_2_8141: la $2, sym_2_8141
+.globl sym_2_8142
+sym_2_8142: la $2, sym_2_8142
+.globl sym_2_8143
+sym_2_8143: la $2, sym_2_8143
+.globl sym_2_8144
+sym_2_8144: la $2, sym_2_8144
+.globl sym_2_8145
+sym_2_8145: la $2, sym_2_8145
+.globl sym_2_8146
+sym_2_8146: la $2, sym_2_8146
+.globl sym_2_8147
+sym_2_8147: la $2, sym_2_8147
+.globl sym_2_8148
+sym_2_8148: la $2, sym_2_8148
+.globl sym_2_8149
+sym_2_8149: la $2, sym_2_8149
+.globl sym_2_8150
+sym_2_8150: la $2, sym_2_8150
+.globl sym_2_8151
+sym_2_8151: la $2, sym_2_8151
+.globl sym_2_8152
+sym_2_8152: la $2, sym_2_8152
+.globl sym_2_8153
+sym_2_8153: la $2, sym_2_8153
+.globl sym_2_8154
+sym_2_8154: la $2, sym_2_8154
+.globl sym_2_8155
+sym_2_8155: la $2, sym_2_8155
+.globl sym_2_8156
+sym_2_8156: la $2, sym_2_8156
+.globl sym_2_8157
+sym_2_8157: la $2, sym_2_8157
+.globl sym_2_8158
+sym_2_8158: la $2, sym_2_8158
+.globl sym_2_8159
+sym_2_8159: la $2, sym_2_8159
+.globl sym_2_8160
+sym_2_8160: la $2, sym_2_8160
+.globl sym_2_8161
+sym_2_8161: la $2, sym_2_8161
+.globl sym_2_8162
+sym_2_8162: la $2, sym_2_8162
+.globl sym_2_8163
+sym_2_8163: la $2, sym_2_8163
+.globl sym_2_8164
+sym_2_8164: la $2, sym_2_8164
+.globl sym_2_8165
+sym_2_8165: la $2, sym_2_8165
+.globl sym_2_8166
+sym_2_8166: la $2, sym_2_8166
+.globl sym_2_8167
+sym_2_8167: la $2, sym_2_8167
+.globl sym_2_8168
+sym_2_8168: la $2, sym_2_8168
+.globl sym_2_8169
+sym_2_8169: la $2, sym_2_8169
+.globl sym_2_8170
+sym_2_8170: la $2, sym_2_8170
+.globl sym_2_8171
+sym_2_8171: la $2, sym_2_8171
+.globl sym_2_8172
+sym_2_8172: la $2, sym_2_8172
+.globl sym_2_8173
+sym_2_8173: la $2, sym_2_8173
+.globl sym_2_8174
+sym_2_8174: la $2, sym_2_8174
+.globl sym_2_8175
+sym_2_8175: la $2, sym_2_8175
+.globl sym_2_8176
+sym_2_8176: la $2, sym_2_8176
+.globl sym_2_8177
+sym_2_8177: la $2, sym_2_8177
+.globl sym_2_8178
+sym_2_8178: la $2, sym_2_8178
+.globl sym_2_8179
+sym_2_8179: la $2, sym_2_8179
+.globl sym_2_8180
+sym_2_8180: la $2, sym_2_8180
+.globl sym_2_8181
+sym_2_8181: la $2, sym_2_8181
+.globl sym_2_8182
+sym_2_8182: la $2, sym_2_8182
+.globl sym_2_8183
+sym_2_8183: la $2, sym_2_8183
+.globl sym_2_8184
+sym_2_8184: la $2, sym_2_8184
+.globl sym_2_8185
+sym_2_8185: la $2, sym_2_8185
+.globl sym_2_8186
+sym_2_8186: la $2, sym_2_8186
+.globl sym_2_8187
+sym_2_8187: la $2, sym_2_8187
+.globl sym_2_8188
+sym_2_8188: la $2, sym_2_8188
+.globl sym_2_8189
+sym_2_8189: la $2, sym_2_8189
+.globl sym_2_8190
+sym_2_8190: la $2, sym_2_8190
+.globl sym_2_8191
+sym_2_8191: la $2, sym_2_8191
+.globl sym_2_8192
+sym_2_8192: la $2, sym_2_8192
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-1.d b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-1.d
new file mode 100644
index 0000000..15f04b2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-1.d
@@ -0,0 +1,8222 @@
+#name: MIPS multi-got-1
+#as: -EB -32 -KPIC
+#source: multi-got-1-1.s
+#source: multi-got-1-2.s
+#ld: -melf32btsmip -shared
+#readelf: -d -r
+
+Dynamic section at offset .* contains 17 entries:
+  Tag        Type                         Name/Value
+ 0x00000004 \(HASH\)                       0x[0-9a-f]+
+ 0x00000005 \(STRTAB\)                     0x[0-9a-f]+
+ 0x00000006 \(SYMTAB\)                     0x[0-9a-f]+
+ 0x0000000a \(STRSZ\)                      [0-9]+ \(bytes\)
+ 0x0000000b \(SYMENT\)                     16 \(bytes\)
+ 0x00000003 \(PLTGOT\)                     0x[0-9a-f]+
+ 0x00000011 \(REL\)                        0x[0-9a-f]+
+ 0x00000012 \(RELSZ\)                      65544 \(bytes\)
+ 0x00000013 \(RELENT\)                     8 \(bytes\)
+ 0x70000001 \(MIPS_RLD_VERSION\)           1
+ 0x70000005 \(MIPS_FLAGS\)                 NOTPOT
+ 0x70000006 \(MIPS_BASE_ADDRESS\)          0
+ 0x7000000a \(MIPS_LOCAL_GOTNO\)           2
+ 0x70000011 \(MIPS_SYMTABNO\)              [0-9]+
+ 0x70000012 \(MIPS_UNREFEXTNO\)            [0-9]+
+ 0x70000013 \(MIPS_GOTSYM\)                0x[0-9a-f]+
+ 0x00000000 \(NULL\)                       0x0
+
+Relocation section '\.rel\.dyn' at offset 0x[0-9a-f]+ contains 8193 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name
+00000000  00000000 R_MIPS_NONE      
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
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+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
+^[0-9a-f]+  [0-9a-f]+ R_MIPS_REL32      [0-9a-f]+   sym_2_[0-9]+
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-hidden-1.d b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-hidden-1.d
new file mode 100644
index 0000000..46bf519
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-hidden-1.d
@@ -0,0 +1,8 @@
+#name: MIPS multi-got-hidden-1
+#as: -EB -32 -KPIC
+#source: multi-got-1-1.s
+#source: multi-got-1-2.s
+#source: multi-got-hidden-1.s
+#ld: -melf32btsmip -e 0
+#objdump: -dr
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-hidden-1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-hidden-1.s
new file mode 100644
index 0000000..195d74b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-hidden-1.s
@@ -0,0 +1,5 @@
+.hidden __init_array_end
+.hidden __init_array_start
+sym_3_1:
+la $2, __init_array_start
+la $2, __init_array_end
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-hidden-2.d b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-hidden-2.d
new file mode 100644
index 0000000..e6173a0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-hidden-2.d
@@ -0,0 +1,7 @@
+#name: MIPS multi-got-hidden-2
+#as: -EB -32 -KPIC
+#source: multi-got-1-1.s
+#source: multi-got-hidden-2.s
+#ld: -melf32btsmip -e 0
+#objdump: -dr
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-hidden-2.s b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-hidden-2.s
new file mode 100644
index 0000000..067bcb2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-hidden-2.s
@@ -0,0 +1,16389 @@
+.globl sym_2_1
+sym_2_1: la $2, sym_2_1
+.globl sym_2_2
+sym_2_2: la $2, sym_2_2
+.globl sym_2_3
+sym_2_3: la $2, sym_2_3
+.globl sym_2_4
+sym_2_4: la $2, sym_2_4
+.globl sym_2_5
+sym_2_5: la $2, sym_2_5
+.globl sym_2_6
+sym_2_6: la $2, sym_2_6
+.globl sym_2_7
+sym_2_7: la $2, sym_2_7
+.globl sym_2_8
+sym_2_8: la $2, sym_2_8
+.globl sym_2_9
+sym_2_9: la $2, sym_2_9
+.globl sym_2_10
+sym_2_10: la $2, sym_2_10
+.globl sym_2_11
+sym_2_11: la $2, sym_2_11
+.globl sym_2_12
+sym_2_12: la $2, sym_2_12
+.globl sym_2_13
+sym_2_13: la $2, sym_2_13
+.globl sym_2_14
+sym_2_14: la $2, sym_2_14
+.globl sym_2_15
+sym_2_15: la $2, sym_2_15
+.globl sym_2_16
+sym_2_16: la $2, sym_2_16
+.globl sym_2_17
+sym_2_17: la $2, sym_2_17
+.globl sym_2_18
+sym_2_18: la $2, sym_2_18
+.globl sym_2_19
+sym_2_19: la $2, sym_2_19
+.globl sym_2_20
+sym_2_20: la $2, sym_2_20
+.globl sym_2_21
+sym_2_21: la $2, sym_2_21
+.globl sym_2_22
+sym_2_22: la $2, sym_2_22
+.globl sym_2_23
+sym_2_23: la $2, sym_2_23
+.globl sym_2_24
+sym_2_24: la $2, sym_2_24
+.globl sym_2_25
+sym_2_25: la $2, sym_2_25
+.globl sym_2_26
+sym_2_26: la $2, sym_2_26
+.globl sym_2_27
+sym_2_27: la $2, sym_2_27
+.globl sym_2_28
+sym_2_28: la $2, sym_2_28
+.globl sym_2_29
+sym_2_29: la $2, sym_2_29
+.globl sym_2_30
+sym_2_30: la $2, sym_2_30
+.globl sym_2_31
+sym_2_31: la $2, sym_2_31
+.globl sym_2_32
+sym_2_32: la $2, sym_2_32
+.globl sym_2_33
+sym_2_33: la $2, sym_2_33
+.globl sym_2_34
+sym_2_34: la $2, sym_2_34
+.globl sym_2_35
+sym_2_35: la $2, sym_2_35
+.globl sym_2_36
+sym_2_36: la $2, sym_2_36
+.globl sym_2_37
+sym_2_37: la $2, sym_2_37
+.globl sym_2_38
+sym_2_38: la $2, sym_2_38
+.globl sym_2_39
+sym_2_39: la $2, sym_2_39
+.globl sym_2_40
+sym_2_40: la $2, sym_2_40
+.globl sym_2_41
+sym_2_41: la $2, sym_2_41
+.globl sym_2_42
+sym_2_42: la $2, sym_2_42
+.globl sym_2_43
+sym_2_43: la $2, sym_2_43
+.globl sym_2_44
+sym_2_44: la $2, sym_2_44
+.globl sym_2_45
+sym_2_45: la $2, sym_2_45
+.globl sym_2_46
+sym_2_46: la $2, sym_2_46
+.globl sym_2_47
+sym_2_47: la $2, sym_2_47
+.globl sym_2_48
+sym_2_48: la $2, sym_2_48
+.globl sym_2_49
+sym_2_49: la $2, sym_2_49
+.globl sym_2_50
+sym_2_50: la $2, sym_2_50
+.globl sym_2_51
+sym_2_51: la $2, sym_2_51
+.globl sym_2_52
+sym_2_52: la $2, sym_2_52
+.globl sym_2_53
+sym_2_53: la $2, sym_2_53
+.globl sym_2_54
+sym_2_54: la $2, sym_2_54
+.globl sym_2_55
+sym_2_55: la $2, sym_2_55
+.globl sym_2_56
+sym_2_56: la $2, sym_2_56
+.globl sym_2_57
+sym_2_57: la $2, sym_2_57
+.globl sym_2_58
+sym_2_58: la $2, sym_2_58
+.globl sym_2_59
+sym_2_59: la $2, sym_2_59
+.globl sym_2_60
+sym_2_60: la $2, sym_2_60
+.globl sym_2_61
+sym_2_61: la $2, sym_2_61
+.globl sym_2_62
+sym_2_62: la $2, sym_2_62
+.globl sym_2_63
+sym_2_63: la $2, sym_2_63
+.globl sym_2_64
+sym_2_64: la $2, sym_2_64
+.globl sym_2_65
+sym_2_65: la $2, sym_2_65
+.globl sym_2_66
+sym_2_66: la $2, sym_2_66
+.globl sym_2_67
+sym_2_67: la $2, sym_2_67
+.globl sym_2_68
+sym_2_68: la $2, sym_2_68
+.globl sym_2_69
+sym_2_69: la $2, sym_2_69
+.globl sym_2_70
+sym_2_70: la $2, sym_2_70
+.globl sym_2_71
+sym_2_71: la $2, sym_2_71
+.globl sym_2_72
+sym_2_72: la $2, sym_2_72
+.globl sym_2_73
+sym_2_73: la $2, sym_2_73
+.globl sym_2_74
+sym_2_74: la $2, sym_2_74
+.globl sym_2_75
+sym_2_75: la $2, sym_2_75
+.globl sym_2_76
+sym_2_76: la $2, sym_2_76
+.globl sym_2_77
+sym_2_77: la $2, sym_2_77
+.globl sym_2_78
+sym_2_78: la $2, sym_2_78
+.globl sym_2_79
+sym_2_79: la $2, sym_2_79
+.globl sym_2_80
+sym_2_80: la $2, sym_2_80
+.globl sym_2_81
+sym_2_81: la $2, sym_2_81
+.globl sym_2_82
+sym_2_82: la $2, sym_2_82
+.globl sym_2_83
+sym_2_83: la $2, sym_2_83
+.globl sym_2_84
+sym_2_84: la $2, sym_2_84
+.globl sym_2_85
+sym_2_85: la $2, sym_2_85
+.globl sym_2_86
+sym_2_86: la $2, sym_2_86
+.globl sym_2_87
+sym_2_87: la $2, sym_2_87
+.globl sym_2_88
+sym_2_88: la $2, sym_2_88
+.globl sym_2_89
+sym_2_89: la $2, sym_2_89
+.globl sym_2_90
+sym_2_90: la $2, sym_2_90
+.globl sym_2_91
+sym_2_91: la $2, sym_2_91
+.globl sym_2_92
+sym_2_92: la $2, sym_2_92
+.globl sym_2_93
+sym_2_93: la $2, sym_2_93
+.globl sym_2_94
+sym_2_94: la $2, sym_2_94
+.globl sym_2_95
+sym_2_95: la $2, sym_2_95
+.globl sym_2_96
+sym_2_96: la $2, sym_2_96
+.globl sym_2_97
+sym_2_97: la $2, sym_2_97
+.globl sym_2_98
+sym_2_98: la $2, sym_2_98
+.globl sym_2_99
+sym_2_99: la $2, sym_2_99
+.globl sym_2_100
+sym_2_100: la $2, sym_2_100
+.globl sym_2_101
+sym_2_101: la $2, sym_2_101
+.globl sym_2_102
+sym_2_102: la $2, sym_2_102
+.globl sym_2_103
+sym_2_103: la $2, sym_2_103
+.globl sym_2_104
+sym_2_104: la $2, sym_2_104
+.globl sym_2_105
+sym_2_105: la $2, sym_2_105
+.globl sym_2_106
+sym_2_106: la $2, sym_2_106
+.globl sym_2_107
+sym_2_107: la $2, sym_2_107
+.globl sym_2_108
+sym_2_108: la $2, sym_2_108
+.globl sym_2_109
+sym_2_109: la $2, sym_2_109
+.globl sym_2_110
+sym_2_110: la $2, sym_2_110
+.globl sym_2_111
+sym_2_111: la $2, sym_2_111
+.globl sym_2_112
+sym_2_112: la $2, sym_2_112
+.globl sym_2_113
+sym_2_113: la $2, sym_2_113
+.globl sym_2_114
+sym_2_114: la $2, sym_2_114
+.globl sym_2_115
+sym_2_115: la $2, sym_2_115
+.globl sym_2_116
+sym_2_116: la $2, sym_2_116
+.globl sym_2_117
+sym_2_117: la $2, sym_2_117
+.globl sym_2_118
+sym_2_118: la $2, sym_2_118
+.globl sym_2_119
+sym_2_119: la $2, sym_2_119
+.globl sym_2_120
+sym_2_120: la $2, sym_2_120
+.globl sym_2_121
+sym_2_121: la $2, sym_2_121
+.globl sym_2_122
+sym_2_122: la $2, sym_2_122
+.globl sym_2_123
+sym_2_123: la $2, sym_2_123
+.globl sym_2_124
+sym_2_124: la $2, sym_2_124
+.globl sym_2_125
+sym_2_125: la $2, sym_2_125
+.globl sym_2_126
+sym_2_126: la $2, sym_2_126
+.globl sym_2_127
+sym_2_127: la $2, sym_2_127
+.globl sym_2_128
+sym_2_128: la $2, sym_2_128
+.globl sym_2_129
+sym_2_129: la $2, sym_2_129
+.globl sym_2_130
+sym_2_130: la $2, sym_2_130
+.globl sym_2_131
+sym_2_131: la $2, sym_2_131
+.globl sym_2_132
+sym_2_132: la $2, sym_2_132
+.globl sym_2_133
+sym_2_133: la $2, sym_2_133
+.globl sym_2_134
+sym_2_134: la $2, sym_2_134
+.globl sym_2_135
+sym_2_135: la $2, sym_2_135
+.globl sym_2_136
+sym_2_136: la $2, sym_2_136
+.globl sym_2_137
+sym_2_137: la $2, sym_2_137
+.globl sym_2_138
+sym_2_138: la $2, sym_2_138
+.globl sym_2_139
+sym_2_139: la $2, sym_2_139
+.globl sym_2_140
+sym_2_140: la $2, sym_2_140
+.globl sym_2_141
+sym_2_141: la $2, sym_2_141
+.globl sym_2_142
+sym_2_142: la $2, sym_2_142
+.globl sym_2_143
+sym_2_143: la $2, sym_2_143
+.globl sym_2_144
+sym_2_144: la $2, sym_2_144
+.globl sym_2_145
+sym_2_145: la $2, sym_2_145
+.globl sym_2_146
+sym_2_146: la $2, sym_2_146
+.globl sym_2_147
+sym_2_147: la $2, sym_2_147
+.globl sym_2_148
+sym_2_148: la $2, sym_2_148
+.globl sym_2_149
+sym_2_149: la $2, sym_2_149
+.globl sym_2_150
+sym_2_150: la $2, sym_2_150
+.globl sym_2_151
+sym_2_151: la $2, sym_2_151
+.globl sym_2_152
+sym_2_152: la $2, sym_2_152
+.globl sym_2_153
+sym_2_153: la $2, sym_2_153
+.globl sym_2_154
+sym_2_154: la $2, sym_2_154
+.globl sym_2_155
+sym_2_155: la $2, sym_2_155
+.globl sym_2_156
+sym_2_156: la $2, sym_2_156
+.globl sym_2_157
+sym_2_157: la $2, sym_2_157
+.globl sym_2_158
+sym_2_158: la $2, sym_2_158
+.globl sym_2_159
+sym_2_159: la $2, sym_2_159
+.globl sym_2_160
+sym_2_160: la $2, sym_2_160
+.globl sym_2_161
+sym_2_161: la $2, sym_2_161
+.globl sym_2_162
+sym_2_162: la $2, sym_2_162
+.globl sym_2_163
+sym_2_163: la $2, sym_2_163
+.globl sym_2_164
+sym_2_164: la $2, sym_2_164
+.globl sym_2_165
+sym_2_165: la $2, sym_2_165
+.globl sym_2_166
+sym_2_166: la $2, sym_2_166
+.globl sym_2_167
+sym_2_167: la $2, sym_2_167
+.globl sym_2_168
+sym_2_168: la $2, sym_2_168
+.globl sym_2_169
+sym_2_169: la $2, sym_2_169
+.globl sym_2_170
+sym_2_170: la $2, sym_2_170
+.globl sym_2_171
+sym_2_171: la $2, sym_2_171
+.globl sym_2_172
+sym_2_172: la $2, sym_2_172
+.globl sym_2_173
+sym_2_173: la $2, sym_2_173
+.globl sym_2_174
+sym_2_174: la $2, sym_2_174
+.globl sym_2_175
+sym_2_175: la $2, sym_2_175
+.globl sym_2_176
+sym_2_176: la $2, sym_2_176
+.globl sym_2_177
+sym_2_177: la $2, sym_2_177
+.globl sym_2_178
+sym_2_178: la $2, sym_2_178
+.globl sym_2_179
+sym_2_179: la $2, sym_2_179
+.globl sym_2_180
+sym_2_180: la $2, sym_2_180
+.globl sym_2_181
+sym_2_181: la $2, sym_2_181
+.globl sym_2_182
+sym_2_182: la $2, sym_2_182
+.globl sym_2_183
+sym_2_183: la $2, sym_2_183
+.globl sym_2_184
+sym_2_184: la $2, sym_2_184
+.globl sym_2_185
+sym_2_185: la $2, sym_2_185
+.globl sym_2_186
+sym_2_186: la $2, sym_2_186
+.globl sym_2_187
+sym_2_187: la $2, sym_2_187
+.globl sym_2_188
+sym_2_188: la $2, sym_2_188
+.globl sym_2_189
+sym_2_189: la $2, sym_2_189
+.globl sym_2_190
+sym_2_190: la $2, sym_2_190
+.globl sym_2_191
+sym_2_191: la $2, sym_2_191
+.globl sym_2_192
+sym_2_192: la $2, sym_2_192
+.globl sym_2_193
+sym_2_193: la $2, sym_2_193
+.globl sym_2_194
+sym_2_194: la $2, sym_2_194
+.globl sym_2_195
+sym_2_195: la $2, sym_2_195
+.globl sym_2_196
+sym_2_196: la $2, sym_2_196
+.globl sym_2_197
+sym_2_197: la $2, sym_2_197
+.globl sym_2_198
+sym_2_198: la $2, sym_2_198
+.globl sym_2_199
+sym_2_199: la $2, sym_2_199
+.globl sym_2_200
+sym_2_200: la $2, sym_2_200
+.globl sym_2_201
+sym_2_201: la $2, sym_2_201
+.globl sym_2_202
+sym_2_202: la $2, sym_2_202
+.globl sym_2_203
+sym_2_203: la $2, sym_2_203
+.globl sym_2_204
+sym_2_204: la $2, sym_2_204
+.globl sym_2_205
+sym_2_205: la $2, sym_2_205
+.globl sym_2_206
+sym_2_206: la $2, sym_2_206
+.globl sym_2_207
+sym_2_207: la $2, sym_2_207
+.globl sym_2_208
+sym_2_208: la $2, sym_2_208
+.globl sym_2_209
+sym_2_209: la $2, sym_2_209
+.globl sym_2_210
+sym_2_210: la $2, sym_2_210
+.globl sym_2_211
+sym_2_211: la $2, sym_2_211
+.globl sym_2_212
+sym_2_212: la $2, sym_2_212
+.globl sym_2_213
+sym_2_213: la $2, sym_2_213
+.globl sym_2_214
+sym_2_214: la $2, sym_2_214
+.globl sym_2_215
+sym_2_215: la $2, sym_2_215
+.globl sym_2_216
+sym_2_216: la $2, sym_2_216
+.globl sym_2_217
+sym_2_217: la $2, sym_2_217
+.globl sym_2_218
+sym_2_218: la $2, sym_2_218
+.globl sym_2_219
+sym_2_219: la $2, sym_2_219
+.globl sym_2_220
+sym_2_220: la $2, sym_2_220
+.globl sym_2_221
+sym_2_221: la $2, sym_2_221
+.globl sym_2_222
+sym_2_222: la $2, sym_2_222
+.globl sym_2_223
+sym_2_223: la $2, sym_2_223
+.globl sym_2_224
+sym_2_224: la $2, sym_2_224
+.globl sym_2_225
+sym_2_225: la $2, sym_2_225
+.globl sym_2_226
+sym_2_226: la $2, sym_2_226
+.globl sym_2_227
+sym_2_227: la $2, sym_2_227
+.globl sym_2_228
+sym_2_228: la $2, sym_2_228
+.globl sym_2_229
+sym_2_229: la $2, sym_2_229
+.globl sym_2_230
+sym_2_230: la $2, sym_2_230
+.globl sym_2_231
+sym_2_231: la $2, sym_2_231
+.globl sym_2_232
+sym_2_232: la $2, sym_2_232
+.globl sym_2_233
+sym_2_233: la $2, sym_2_233
+.globl sym_2_234
+sym_2_234: la $2, sym_2_234
+.globl sym_2_235
+sym_2_235: la $2, sym_2_235
+.globl sym_2_236
+sym_2_236: la $2, sym_2_236
+.globl sym_2_237
+sym_2_237: la $2, sym_2_237
+.globl sym_2_238
+sym_2_238: la $2, sym_2_238
+.globl sym_2_239
+sym_2_239: la $2, sym_2_239
+.globl sym_2_240
+sym_2_240: la $2, sym_2_240
+.globl sym_2_241
+sym_2_241: la $2, sym_2_241
+.globl sym_2_242
+sym_2_242: la $2, sym_2_242
+.globl sym_2_243
+sym_2_243: la $2, sym_2_243
+.globl sym_2_244
+sym_2_244: la $2, sym_2_244
+.globl sym_2_245
+sym_2_245: la $2, sym_2_245
+.globl sym_2_246
+sym_2_246: la $2, sym_2_246
+.globl sym_2_247
+sym_2_247: la $2, sym_2_247
+.globl sym_2_248
+sym_2_248: la $2, sym_2_248
+.globl sym_2_249
+sym_2_249: la $2, sym_2_249
+.globl sym_2_250
+sym_2_250: la $2, sym_2_250
+.globl sym_2_251
+sym_2_251: la $2, sym_2_251
+.globl sym_2_252
+sym_2_252: la $2, sym_2_252
+.globl sym_2_253
+sym_2_253: la $2, sym_2_253
+.globl sym_2_254
+sym_2_254: la $2, sym_2_254
+.globl sym_2_255
+sym_2_255: la $2, sym_2_255
+.globl sym_2_256
+sym_2_256: la $2, sym_2_256
+.globl sym_2_257
+sym_2_257: la $2, sym_2_257
+.globl sym_2_258
+sym_2_258: la $2, sym_2_258
+.globl sym_2_259
+sym_2_259: la $2, sym_2_259
+.globl sym_2_260
+sym_2_260: la $2, sym_2_260
+.globl sym_2_261
+sym_2_261: la $2, sym_2_261
+.globl sym_2_262
+sym_2_262: la $2, sym_2_262
+.globl sym_2_263
+sym_2_263: la $2, sym_2_263
+.globl sym_2_264
+sym_2_264: la $2, sym_2_264
+.globl sym_2_265
+sym_2_265: la $2, sym_2_265
+.globl sym_2_266
+sym_2_266: la $2, sym_2_266
+.globl sym_2_267
+sym_2_267: la $2, sym_2_267
+.globl sym_2_268
+sym_2_268: la $2, sym_2_268
+.globl sym_2_269
+sym_2_269: la $2, sym_2_269
+.globl sym_2_270
+sym_2_270: la $2, sym_2_270
+.globl sym_2_271
+sym_2_271: la $2, sym_2_271
+.globl sym_2_272
+sym_2_272: la $2, sym_2_272
+.globl sym_2_273
+sym_2_273: la $2, sym_2_273
+.globl sym_2_274
+sym_2_274: la $2, sym_2_274
+.globl sym_2_275
+sym_2_275: la $2, sym_2_275
+.globl sym_2_276
+sym_2_276: la $2, sym_2_276
+.globl sym_2_277
+sym_2_277: la $2, sym_2_277
+.globl sym_2_278
+sym_2_278: la $2, sym_2_278
+.globl sym_2_279
+sym_2_279: la $2, sym_2_279
+.globl sym_2_280
+sym_2_280: la $2, sym_2_280
+.globl sym_2_281
+sym_2_281: la $2, sym_2_281
+.globl sym_2_282
+sym_2_282: la $2, sym_2_282
+.globl sym_2_283
+sym_2_283: la $2, sym_2_283
+.globl sym_2_284
+sym_2_284: la $2, sym_2_284
+.globl sym_2_285
+sym_2_285: la $2, sym_2_285
+.globl sym_2_286
+sym_2_286: la $2, sym_2_286
+.globl sym_2_287
+sym_2_287: la $2, sym_2_287
+.globl sym_2_288
+sym_2_288: la $2, sym_2_288
+.globl sym_2_289
+sym_2_289: la $2, sym_2_289
+.globl sym_2_290
+sym_2_290: la $2, sym_2_290
+.globl sym_2_291
+sym_2_291: la $2, sym_2_291
+.globl sym_2_292
+sym_2_292: la $2, sym_2_292
+.globl sym_2_293
+sym_2_293: la $2, sym_2_293
+.globl sym_2_294
+sym_2_294: la $2, sym_2_294
+.globl sym_2_295
+sym_2_295: la $2, sym_2_295
+.globl sym_2_296
+sym_2_296: la $2, sym_2_296
+.globl sym_2_297
+sym_2_297: la $2, sym_2_297
+.globl sym_2_298
+sym_2_298: la $2, sym_2_298
+.globl sym_2_299
+sym_2_299: la $2, sym_2_299
+.globl sym_2_300
+sym_2_300: la $2, sym_2_300
+.globl sym_2_301
+sym_2_301: la $2, sym_2_301
+.globl sym_2_302
+sym_2_302: la $2, sym_2_302
+.globl sym_2_303
+sym_2_303: la $2, sym_2_303
+.globl sym_2_304
+sym_2_304: la $2, sym_2_304
+.globl sym_2_305
+sym_2_305: la $2, sym_2_305
+.globl sym_2_306
+sym_2_306: la $2, sym_2_306
+.globl sym_2_307
+sym_2_307: la $2, sym_2_307
+.globl sym_2_308
+sym_2_308: la $2, sym_2_308
+.globl sym_2_309
+sym_2_309: la $2, sym_2_309
+.globl sym_2_310
+sym_2_310: la $2, sym_2_310
+.globl sym_2_311
+sym_2_311: la $2, sym_2_311
+.globl sym_2_312
+sym_2_312: la $2, sym_2_312
+.globl sym_2_313
+sym_2_313: la $2, sym_2_313
+.globl sym_2_314
+sym_2_314: la $2, sym_2_314
+.globl sym_2_315
+sym_2_315: la $2, sym_2_315
+.globl sym_2_316
+sym_2_316: la $2, sym_2_316
+.globl sym_2_317
+sym_2_317: la $2, sym_2_317
+.globl sym_2_318
+sym_2_318: la $2, sym_2_318
+.globl sym_2_319
+sym_2_319: la $2, sym_2_319
+.globl sym_2_320
+sym_2_320: la $2, sym_2_320
+.globl sym_2_321
+sym_2_321: la $2, sym_2_321
+.globl sym_2_322
+sym_2_322: la $2, sym_2_322
+.globl sym_2_323
+sym_2_323: la $2, sym_2_323
+.globl sym_2_324
+sym_2_324: la $2, sym_2_324
+.globl sym_2_325
+sym_2_325: la $2, sym_2_325
+.globl sym_2_326
+sym_2_326: la $2, sym_2_326
+.globl sym_2_327
+sym_2_327: la $2, sym_2_327
+.globl sym_2_328
+sym_2_328: la $2, sym_2_328
+.globl sym_2_329
+sym_2_329: la $2, sym_2_329
+.globl sym_2_330
+sym_2_330: la $2, sym_2_330
+.globl sym_2_331
+sym_2_331: la $2, sym_2_331
+.globl sym_2_332
+sym_2_332: la $2, sym_2_332
+.globl sym_2_333
+sym_2_333: la $2, sym_2_333
+.globl sym_2_334
+sym_2_334: la $2, sym_2_334
+.globl sym_2_335
+sym_2_335: la $2, sym_2_335
+.globl sym_2_336
+sym_2_336: la $2, sym_2_336
+.globl sym_2_337
+sym_2_337: la $2, sym_2_337
+.globl sym_2_338
+sym_2_338: la $2, sym_2_338
+.globl sym_2_339
+sym_2_339: la $2, sym_2_339
+.globl sym_2_340
+sym_2_340: la $2, sym_2_340
+.globl sym_2_341
+sym_2_341: la $2, sym_2_341
+.globl sym_2_342
+sym_2_342: la $2, sym_2_342
+.globl sym_2_343
+sym_2_343: la $2, sym_2_343
+.globl sym_2_344
+sym_2_344: la $2, sym_2_344
+.globl sym_2_345
+sym_2_345: la $2, sym_2_345
+.globl sym_2_346
+sym_2_346: la $2, sym_2_346
+.globl sym_2_347
+sym_2_347: la $2, sym_2_347
+.globl sym_2_348
+sym_2_348: la $2, sym_2_348
+.globl sym_2_349
+sym_2_349: la $2, sym_2_349
+.globl sym_2_350
+sym_2_350: la $2, sym_2_350
+.globl sym_2_351
+sym_2_351: la $2, sym_2_351
+.globl sym_2_352
+sym_2_352: la $2, sym_2_352
+.globl sym_2_353
+sym_2_353: la $2, sym_2_353
+.globl sym_2_354
+sym_2_354: la $2, sym_2_354
+.globl sym_2_355
+sym_2_355: la $2, sym_2_355
+.globl sym_2_356
+sym_2_356: la $2, sym_2_356
+.globl sym_2_357
+sym_2_357: la $2, sym_2_357
+.globl sym_2_358
+sym_2_358: la $2, sym_2_358
+.globl sym_2_359
+sym_2_359: la $2, sym_2_359
+.globl sym_2_360
+sym_2_360: la $2, sym_2_360
+.globl sym_2_361
+sym_2_361: la $2, sym_2_361
+.globl sym_2_362
+sym_2_362: la $2, sym_2_362
+.globl sym_2_363
+sym_2_363: la $2, sym_2_363
+.globl sym_2_364
+sym_2_364: la $2, sym_2_364
+.globl sym_2_365
+sym_2_365: la $2, sym_2_365
+.globl sym_2_366
+sym_2_366: la $2, sym_2_366
+.globl sym_2_367
+sym_2_367: la $2, sym_2_367
+.globl sym_2_368
+sym_2_368: la $2, sym_2_368
+.globl sym_2_369
+sym_2_369: la $2, sym_2_369
+.globl sym_2_370
+sym_2_370: la $2, sym_2_370
+.globl sym_2_371
+sym_2_371: la $2, sym_2_371
+.globl sym_2_372
+sym_2_372: la $2, sym_2_372
+.globl sym_2_373
+sym_2_373: la $2, sym_2_373
+.globl sym_2_374
+sym_2_374: la $2, sym_2_374
+.globl sym_2_375
+sym_2_375: la $2, sym_2_375
+.globl sym_2_376
+sym_2_376: la $2, sym_2_376
+.globl sym_2_377
+sym_2_377: la $2, sym_2_377
+.globl sym_2_378
+sym_2_378: la $2, sym_2_378
+.globl sym_2_379
+sym_2_379: la $2, sym_2_379
+.globl sym_2_380
+sym_2_380: la $2, sym_2_380
+.globl sym_2_381
+sym_2_381: la $2, sym_2_381
+.globl sym_2_382
+sym_2_382: la $2, sym_2_382
+.globl sym_2_383
+sym_2_383: la $2, sym_2_383
+.globl sym_2_384
+sym_2_384: la $2, sym_2_384
+.globl sym_2_385
+sym_2_385: la $2, sym_2_385
+.globl sym_2_386
+sym_2_386: la $2, sym_2_386
+.globl sym_2_387
+sym_2_387: la $2, sym_2_387
+.globl sym_2_388
+sym_2_388: la $2, sym_2_388
+.globl sym_2_389
+sym_2_389: la $2, sym_2_389
+.globl sym_2_390
+sym_2_390: la $2, sym_2_390
+.globl sym_2_391
+sym_2_391: la $2, sym_2_391
+.globl sym_2_392
+sym_2_392: la $2, sym_2_392
+.globl sym_2_393
+sym_2_393: la $2, sym_2_393
+.globl sym_2_394
+sym_2_394: la $2, sym_2_394
+.globl sym_2_395
+sym_2_395: la $2, sym_2_395
+.globl sym_2_396
+sym_2_396: la $2, sym_2_396
+.globl sym_2_397
+sym_2_397: la $2, sym_2_397
+.globl sym_2_398
+sym_2_398: la $2, sym_2_398
+.globl sym_2_399
+sym_2_399: la $2, sym_2_399
+.globl sym_2_400
+sym_2_400: la $2, sym_2_400
+.globl sym_2_401
+sym_2_401: la $2, sym_2_401
+.globl sym_2_402
+sym_2_402: la $2, sym_2_402
+.globl sym_2_403
+sym_2_403: la $2, sym_2_403
+.globl sym_2_404
+sym_2_404: la $2, sym_2_404
+.globl sym_2_405
+sym_2_405: la $2, sym_2_405
+.globl sym_2_406
+sym_2_406: la $2, sym_2_406
+.globl sym_2_407
+sym_2_407: la $2, sym_2_407
+.globl sym_2_408
+sym_2_408: la $2, sym_2_408
+.globl sym_2_409
+sym_2_409: la $2, sym_2_409
+.globl sym_2_410
+sym_2_410: la $2, sym_2_410
+.globl sym_2_411
+sym_2_411: la $2, sym_2_411
+.globl sym_2_412
+sym_2_412: la $2, sym_2_412
+.globl sym_2_413
+sym_2_413: la $2, sym_2_413
+.globl sym_2_414
+sym_2_414: la $2, sym_2_414
+.globl sym_2_415
+sym_2_415: la $2, sym_2_415
+.globl sym_2_416
+sym_2_416: la $2, sym_2_416
+.globl sym_2_417
+sym_2_417: la $2, sym_2_417
+.globl sym_2_418
+sym_2_418: la $2, sym_2_418
+.globl sym_2_419
+sym_2_419: la $2, sym_2_419
+.globl sym_2_420
+sym_2_420: la $2, sym_2_420
+.globl sym_2_421
+sym_2_421: la $2, sym_2_421
+.globl sym_2_422
+sym_2_422: la $2, sym_2_422
+.globl sym_2_423
+sym_2_423: la $2, sym_2_423
+.globl sym_2_424
+sym_2_424: la $2, sym_2_424
+.globl sym_2_425
+sym_2_425: la $2, sym_2_425
+.globl sym_2_426
+sym_2_426: la $2, sym_2_426
+.globl sym_2_427
+sym_2_427: la $2, sym_2_427
+.globl sym_2_428
+sym_2_428: la $2, sym_2_428
+.globl sym_2_429
+sym_2_429: la $2, sym_2_429
+.globl sym_2_430
+sym_2_430: la $2, sym_2_430
+.globl sym_2_431
+sym_2_431: la $2, sym_2_431
+.globl sym_2_432
+sym_2_432: la $2, sym_2_432
+.globl sym_2_433
+sym_2_433: la $2, sym_2_433
+.globl sym_2_434
+sym_2_434: la $2, sym_2_434
+.globl sym_2_435
+sym_2_435: la $2, sym_2_435
+.globl sym_2_436
+sym_2_436: la $2, sym_2_436
+.globl sym_2_437
+sym_2_437: la $2, sym_2_437
+.globl sym_2_438
+sym_2_438: la $2, sym_2_438
+.globl sym_2_439
+sym_2_439: la $2, sym_2_439
+.globl sym_2_440
+sym_2_440: la $2, sym_2_440
+.globl sym_2_441
+sym_2_441: la $2, sym_2_441
+.globl sym_2_442
+sym_2_442: la $2, sym_2_442
+.globl sym_2_443
+sym_2_443: la $2, sym_2_443
+.globl sym_2_444
+sym_2_444: la $2, sym_2_444
+.globl sym_2_445
+sym_2_445: la $2, sym_2_445
+.globl sym_2_446
+sym_2_446: la $2, sym_2_446
+.globl sym_2_447
+sym_2_447: la $2, sym_2_447
+.globl sym_2_448
+sym_2_448: la $2, sym_2_448
+.globl sym_2_449
+sym_2_449: la $2, sym_2_449
+.globl sym_2_450
+sym_2_450: la $2, sym_2_450
+.globl sym_2_451
+sym_2_451: la $2, sym_2_451
+.globl sym_2_452
+sym_2_452: la $2, sym_2_452
+.globl sym_2_453
+sym_2_453: la $2, sym_2_453
+.globl sym_2_454
+sym_2_454: la $2, sym_2_454
+.globl sym_2_455
+sym_2_455: la $2, sym_2_455
+.globl sym_2_456
+sym_2_456: la $2, sym_2_456
+.globl sym_2_457
+sym_2_457: la $2, sym_2_457
+.globl sym_2_458
+sym_2_458: la $2, sym_2_458
+.globl sym_2_459
+sym_2_459: la $2, sym_2_459
+.globl sym_2_460
+sym_2_460: la $2, sym_2_460
+.globl sym_2_461
+sym_2_461: la $2, sym_2_461
+.globl sym_2_462
+sym_2_462: la $2, sym_2_462
+.globl sym_2_463
+sym_2_463: la $2, sym_2_463
+.globl sym_2_464
+sym_2_464: la $2, sym_2_464
+.globl sym_2_465
+sym_2_465: la $2, sym_2_465
+.globl sym_2_466
+sym_2_466: la $2, sym_2_466
+.globl sym_2_467
+sym_2_467: la $2, sym_2_467
+.globl sym_2_468
+sym_2_468: la $2, sym_2_468
+.globl sym_2_469
+sym_2_469: la $2, sym_2_469
+.globl sym_2_470
+sym_2_470: la $2, sym_2_470
+.globl sym_2_471
+sym_2_471: la $2, sym_2_471
+.globl sym_2_472
+sym_2_472: la $2, sym_2_472
+.globl sym_2_473
+sym_2_473: la $2, sym_2_473
+.globl sym_2_474
+sym_2_474: la $2, sym_2_474
+.globl sym_2_475
+sym_2_475: la $2, sym_2_475
+.globl sym_2_476
+sym_2_476: la $2, sym_2_476
+.globl sym_2_477
+sym_2_477: la $2, sym_2_477
+.globl sym_2_478
+sym_2_478: la $2, sym_2_478
+.globl sym_2_479
+sym_2_479: la $2, sym_2_479
+.globl sym_2_480
+sym_2_480: la $2, sym_2_480
+.globl sym_2_481
+sym_2_481: la $2, sym_2_481
+.globl sym_2_482
+sym_2_482: la $2, sym_2_482
+.globl sym_2_483
+sym_2_483: la $2, sym_2_483
+.globl sym_2_484
+sym_2_484: la $2, sym_2_484
+.globl sym_2_485
+sym_2_485: la $2, sym_2_485
+.globl sym_2_486
+sym_2_486: la $2, sym_2_486
+.globl sym_2_487
+sym_2_487: la $2, sym_2_487
+.globl sym_2_488
+sym_2_488: la $2, sym_2_488
+.globl sym_2_489
+sym_2_489: la $2, sym_2_489
+.globl sym_2_490
+sym_2_490: la $2, sym_2_490
+.globl sym_2_491
+sym_2_491: la $2, sym_2_491
+.globl sym_2_492
+sym_2_492: la $2, sym_2_492
+.globl sym_2_493
+sym_2_493: la $2, sym_2_493
+.globl sym_2_494
+sym_2_494: la $2, sym_2_494
+.globl sym_2_495
+sym_2_495: la $2, sym_2_495
+.globl sym_2_496
+sym_2_496: la $2, sym_2_496
+.globl sym_2_497
+sym_2_497: la $2, sym_2_497
+.globl sym_2_498
+sym_2_498: la $2, sym_2_498
+.globl sym_2_499
+sym_2_499: la $2, sym_2_499
+.globl sym_2_500
+sym_2_500: la $2, sym_2_500
+.globl sym_2_501
+sym_2_501: la $2, sym_2_501
+.globl sym_2_502
+sym_2_502: la $2, sym_2_502
+.globl sym_2_503
+sym_2_503: la $2, sym_2_503
+.globl sym_2_504
+sym_2_504: la $2, sym_2_504
+.globl sym_2_505
+sym_2_505: la $2, sym_2_505
+.globl sym_2_506
+sym_2_506: la $2, sym_2_506
+.globl sym_2_507
+sym_2_507: la $2, sym_2_507
+.globl sym_2_508
+sym_2_508: la $2, sym_2_508
+.globl sym_2_509
+sym_2_509: la $2, sym_2_509
+.globl sym_2_510
+sym_2_510: la $2, sym_2_510
+.globl sym_2_511
+sym_2_511: la $2, sym_2_511
+.globl sym_2_512
+sym_2_512: la $2, sym_2_512
+.globl sym_2_513
+sym_2_513: la $2, sym_2_513
+.globl sym_2_514
+sym_2_514: la $2, sym_2_514
+.globl sym_2_515
+sym_2_515: la $2, sym_2_515
+.globl sym_2_516
+sym_2_516: la $2, sym_2_516
+.globl sym_2_517
+sym_2_517: la $2, sym_2_517
+.globl sym_2_518
+sym_2_518: la $2, sym_2_518
+.globl sym_2_519
+sym_2_519: la $2, sym_2_519
+.globl sym_2_520
+sym_2_520: la $2, sym_2_520
+.globl sym_2_521
+sym_2_521: la $2, sym_2_521
+.globl sym_2_522
+sym_2_522: la $2, sym_2_522
+.globl sym_2_523
+sym_2_523: la $2, sym_2_523
+.globl sym_2_524
+sym_2_524: la $2, sym_2_524
+.globl sym_2_525
+sym_2_525: la $2, sym_2_525
+.globl sym_2_526
+sym_2_526: la $2, sym_2_526
+.globl sym_2_527
+sym_2_527: la $2, sym_2_527
+.globl sym_2_528
+sym_2_528: la $2, sym_2_528
+.globl sym_2_529
+sym_2_529: la $2, sym_2_529
+.globl sym_2_530
+sym_2_530: la $2, sym_2_530
+.globl sym_2_531
+sym_2_531: la $2, sym_2_531
+.globl sym_2_532
+sym_2_532: la $2, sym_2_532
+.globl sym_2_533
+sym_2_533: la $2, sym_2_533
+.globl sym_2_534
+sym_2_534: la $2, sym_2_534
+.globl sym_2_535
+sym_2_535: la $2, sym_2_535
+.globl sym_2_536
+sym_2_536: la $2, sym_2_536
+.globl sym_2_537
+sym_2_537: la $2, sym_2_537
+.globl sym_2_538
+sym_2_538: la $2, sym_2_538
+.globl sym_2_539
+sym_2_539: la $2, sym_2_539
+.globl sym_2_540
+sym_2_540: la $2, sym_2_540
+.globl sym_2_541
+sym_2_541: la $2, sym_2_541
+.globl sym_2_542
+sym_2_542: la $2, sym_2_542
+.globl sym_2_543
+sym_2_543: la $2, sym_2_543
+.globl sym_2_544
+sym_2_544: la $2, sym_2_544
+.globl sym_2_545
+sym_2_545: la $2, sym_2_545
+.globl sym_2_546
+sym_2_546: la $2, sym_2_546
+.globl sym_2_547
+sym_2_547: la $2, sym_2_547
+.globl sym_2_548
+sym_2_548: la $2, sym_2_548
+.globl sym_2_549
+sym_2_549: la $2, sym_2_549
+.globl sym_2_550
+sym_2_550: la $2, sym_2_550
+.globl sym_2_551
+sym_2_551: la $2, sym_2_551
+.globl sym_2_552
+sym_2_552: la $2, sym_2_552
+.globl sym_2_553
+sym_2_553: la $2, sym_2_553
+.globl sym_2_554
+sym_2_554: la $2, sym_2_554
+.globl sym_2_555
+sym_2_555: la $2, sym_2_555
+.globl sym_2_556
+sym_2_556: la $2, sym_2_556
+.globl sym_2_557
+sym_2_557: la $2, sym_2_557
+.globl sym_2_558
+sym_2_558: la $2, sym_2_558
+.globl sym_2_559
+sym_2_559: la $2, sym_2_559
+.globl sym_2_560
+sym_2_560: la $2, sym_2_560
+.globl sym_2_561
+sym_2_561: la $2, sym_2_561
+.globl sym_2_562
+sym_2_562: la $2, sym_2_562
+.globl sym_2_563
+sym_2_563: la $2, sym_2_563
+.globl sym_2_564
+sym_2_564: la $2, sym_2_564
+.globl sym_2_565
+sym_2_565: la $2, sym_2_565
+.globl sym_2_566
+sym_2_566: la $2, sym_2_566
+.globl sym_2_567
+sym_2_567: la $2, sym_2_567
+.globl sym_2_568
+sym_2_568: la $2, sym_2_568
+.globl sym_2_569
+sym_2_569: la $2, sym_2_569
+.globl sym_2_570
+sym_2_570: la $2, sym_2_570
+.globl sym_2_571
+sym_2_571: la $2, sym_2_571
+.globl sym_2_572
+sym_2_572: la $2, sym_2_572
+.globl sym_2_573
+sym_2_573: la $2, sym_2_573
+.globl sym_2_574
+sym_2_574: la $2, sym_2_574
+.globl sym_2_575
+sym_2_575: la $2, sym_2_575
+.globl sym_2_576
+sym_2_576: la $2, sym_2_576
+.globl sym_2_577
+sym_2_577: la $2, sym_2_577
+.globl sym_2_578
+sym_2_578: la $2, sym_2_578
+.globl sym_2_579
+sym_2_579: la $2, sym_2_579
+.globl sym_2_580
+sym_2_580: la $2, sym_2_580
+.globl sym_2_581
+sym_2_581: la $2, sym_2_581
+.globl sym_2_582
+sym_2_582: la $2, sym_2_582
+.globl sym_2_583
+sym_2_583: la $2, sym_2_583
+.globl sym_2_584
+sym_2_584: la $2, sym_2_584
+.globl sym_2_585
+sym_2_585: la $2, sym_2_585
+.globl sym_2_586
+sym_2_586: la $2, sym_2_586
+.globl sym_2_587
+sym_2_587: la $2, sym_2_587
+.globl sym_2_588
+sym_2_588: la $2, sym_2_588
+.globl sym_2_589
+sym_2_589: la $2, sym_2_589
+.globl sym_2_590
+sym_2_590: la $2, sym_2_590
+.globl sym_2_591
+sym_2_591: la $2, sym_2_591
+.globl sym_2_592
+sym_2_592: la $2, sym_2_592
+.globl sym_2_593
+sym_2_593: la $2, sym_2_593
+.globl sym_2_594
+sym_2_594: la $2, sym_2_594
+.globl sym_2_595
+sym_2_595: la $2, sym_2_595
+.globl sym_2_596
+sym_2_596: la $2, sym_2_596
+.globl sym_2_597
+sym_2_597: la $2, sym_2_597
+.globl sym_2_598
+sym_2_598: la $2, sym_2_598
+.globl sym_2_599
+sym_2_599: la $2, sym_2_599
+.globl sym_2_600
+sym_2_600: la $2, sym_2_600
+.globl sym_2_601
+sym_2_601: la $2, sym_2_601
+.globl sym_2_602
+sym_2_602: la $2, sym_2_602
+.globl sym_2_603
+sym_2_603: la $2, sym_2_603
+.globl sym_2_604
+sym_2_604: la $2, sym_2_604
+.globl sym_2_605
+sym_2_605: la $2, sym_2_605
+.globl sym_2_606
+sym_2_606: la $2, sym_2_606
+.globl sym_2_607
+sym_2_607: la $2, sym_2_607
+.globl sym_2_608
+sym_2_608: la $2, sym_2_608
+.globl sym_2_609
+sym_2_609: la $2, sym_2_609
+.globl sym_2_610
+sym_2_610: la $2, sym_2_610
+.globl sym_2_611
+sym_2_611: la $2, sym_2_611
+.globl sym_2_612
+sym_2_612: la $2, sym_2_612
+.globl sym_2_613
+sym_2_613: la $2, sym_2_613
+.globl sym_2_614
+sym_2_614: la $2, sym_2_614
+.globl sym_2_615
+sym_2_615: la $2, sym_2_615
+.globl sym_2_616
+sym_2_616: la $2, sym_2_616
+.globl sym_2_617
+sym_2_617: la $2, sym_2_617
+.globl sym_2_618
+sym_2_618: la $2, sym_2_618
+.globl sym_2_619
+sym_2_619: la $2, sym_2_619
+.globl sym_2_620
+sym_2_620: la $2, sym_2_620
+.globl sym_2_621
+sym_2_621: la $2, sym_2_621
+.globl sym_2_622
+sym_2_622: la $2, sym_2_622
+.globl sym_2_623
+sym_2_623: la $2, sym_2_623
+.globl sym_2_624
+sym_2_624: la $2, sym_2_624
+.globl sym_2_625
+sym_2_625: la $2, sym_2_625
+.globl sym_2_626
+sym_2_626: la $2, sym_2_626
+.globl sym_2_627
+sym_2_627: la $2, sym_2_627
+.globl sym_2_628
+sym_2_628: la $2, sym_2_628
+.globl sym_2_629
+sym_2_629: la $2, sym_2_629
+.globl sym_2_630
+sym_2_630: la $2, sym_2_630
+.globl sym_2_631
+sym_2_631: la $2, sym_2_631
+.globl sym_2_632
+sym_2_632: la $2, sym_2_632
+.globl sym_2_633
+sym_2_633: la $2, sym_2_633
+.globl sym_2_634
+sym_2_634: la $2, sym_2_634
+.globl sym_2_635
+sym_2_635: la $2, sym_2_635
+.globl sym_2_636
+sym_2_636: la $2, sym_2_636
+.globl sym_2_637
+sym_2_637: la $2, sym_2_637
+.globl sym_2_638
+sym_2_638: la $2, sym_2_638
+.globl sym_2_639
+sym_2_639: la $2, sym_2_639
+.globl sym_2_640
+sym_2_640: la $2, sym_2_640
+.globl sym_2_641
+sym_2_641: la $2, sym_2_641
+.globl sym_2_642
+sym_2_642: la $2, sym_2_642
+.globl sym_2_643
+sym_2_643: la $2, sym_2_643
+.globl sym_2_644
+sym_2_644: la $2, sym_2_644
+.globl sym_2_645
+sym_2_645: la $2, sym_2_645
+.globl sym_2_646
+sym_2_646: la $2, sym_2_646
+.globl sym_2_647
+sym_2_647: la $2, sym_2_647
+.globl sym_2_648
+sym_2_648: la $2, sym_2_648
+.globl sym_2_649
+sym_2_649: la $2, sym_2_649
+.globl sym_2_650
+sym_2_650: la $2, sym_2_650
+.globl sym_2_651
+sym_2_651: la $2, sym_2_651
+.globl sym_2_652
+sym_2_652: la $2, sym_2_652
+.globl sym_2_653
+sym_2_653: la $2, sym_2_653
+.globl sym_2_654
+sym_2_654: la $2, sym_2_654
+.globl sym_2_655
+sym_2_655: la $2, sym_2_655
+.globl sym_2_656
+sym_2_656: la $2, sym_2_656
+.globl sym_2_657
+sym_2_657: la $2, sym_2_657
+.globl sym_2_658
+sym_2_658: la $2, sym_2_658
+.globl sym_2_659
+sym_2_659: la $2, sym_2_659
+.globl sym_2_660
+sym_2_660: la $2, sym_2_660
+.globl sym_2_661
+sym_2_661: la $2, sym_2_661
+.globl sym_2_662
+sym_2_662: la $2, sym_2_662
+.globl sym_2_663
+sym_2_663: la $2, sym_2_663
+.globl sym_2_664
+sym_2_664: la $2, sym_2_664
+.globl sym_2_665
+sym_2_665: la $2, sym_2_665
+.globl sym_2_666
+sym_2_666: la $2, sym_2_666
+.globl sym_2_667
+sym_2_667: la $2, sym_2_667
+.globl sym_2_668
+sym_2_668: la $2, sym_2_668
+.globl sym_2_669
+sym_2_669: la $2, sym_2_669
+.globl sym_2_670
+sym_2_670: la $2, sym_2_670
+.globl sym_2_671
+sym_2_671: la $2, sym_2_671
+.globl sym_2_672
+sym_2_672: la $2, sym_2_672
+.globl sym_2_673
+sym_2_673: la $2, sym_2_673
+.globl sym_2_674
+sym_2_674: la $2, sym_2_674
+.globl sym_2_675
+sym_2_675: la $2, sym_2_675
+.globl sym_2_676
+sym_2_676: la $2, sym_2_676
+.globl sym_2_677
+sym_2_677: la $2, sym_2_677
+.globl sym_2_678
+sym_2_678: la $2, sym_2_678
+.globl sym_2_679
+sym_2_679: la $2, sym_2_679
+.globl sym_2_680
+sym_2_680: la $2, sym_2_680
+.globl sym_2_681
+sym_2_681: la $2, sym_2_681
+.globl sym_2_682
+sym_2_682: la $2, sym_2_682
+.globl sym_2_683
+sym_2_683: la $2, sym_2_683
+.globl sym_2_684
+sym_2_684: la $2, sym_2_684
+.globl sym_2_685
+sym_2_685: la $2, sym_2_685
+.globl sym_2_686
+sym_2_686: la $2, sym_2_686
+.globl sym_2_687
+sym_2_687: la $2, sym_2_687
+.globl sym_2_688
+sym_2_688: la $2, sym_2_688
+.globl sym_2_689
+sym_2_689: la $2, sym_2_689
+.globl sym_2_690
+sym_2_690: la $2, sym_2_690
+.globl sym_2_691
+sym_2_691: la $2, sym_2_691
+.globl sym_2_692
+sym_2_692: la $2, sym_2_692
+.globl sym_2_693
+sym_2_693: la $2, sym_2_693
+.globl sym_2_694
+sym_2_694: la $2, sym_2_694
+.globl sym_2_695
+sym_2_695: la $2, sym_2_695
+.globl sym_2_696
+sym_2_696: la $2, sym_2_696
+.globl sym_2_697
+sym_2_697: la $2, sym_2_697
+.globl sym_2_698
+sym_2_698: la $2, sym_2_698
+.globl sym_2_699
+sym_2_699: la $2, sym_2_699
+.globl sym_2_700
+sym_2_700: la $2, sym_2_700
+.globl sym_2_701
+sym_2_701: la $2, sym_2_701
+.globl sym_2_702
+sym_2_702: la $2, sym_2_702
+.globl sym_2_703
+sym_2_703: la $2, sym_2_703
+.globl sym_2_704
+sym_2_704: la $2, sym_2_704
+.globl sym_2_705
+sym_2_705: la $2, sym_2_705
+.globl sym_2_706
+sym_2_706: la $2, sym_2_706
+.globl sym_2_707
+sym_2_707: la $2, sym_2_707
+.globl sym_2_708
+sym_2_708: la $2, sym_2_708
+.globl sym_2_709
+sym_2_709: la $2, sym_2_709
+.globl sym_2_710
+sym_2_710: la $2, sym_2_710
+.globl sym_2_711
+sym_2_711: la $2, sym_2_711
+.globl sym_2_712
+sym_2_712: la $2, sym_2_712
+.globl sym_2_713
+sym_2_713: la $2, sym_2_713
+.globl sym_2_714
+sym_2_714: la $2, sym_2_714
+.globl sym_2_715
+sym_2_715: la $2, sym_2_715
+.globl sym_2_716
+sym_2_716: la $2, sym_2_716
+.globl sym_2_717
+sym_2_717: la $2, sym_2_717
+.globl sym_2_718
+sym_2_718: la $2, sym_2_718
+.globl sym_2_719
+sym_2_719: la $2, sym_2_719
+.globl sym_2_720
+sym_2_720: la $2, sym_2_720
+.globl sym_2_721
+sym_2_721: la $2, sym_2_721
+.globl sym_2_722
+sym_2_722: la $2, sym_2_722
+.globl sym_2_723
+sym_2_723: la $2, sym_2_723
+.globl sym_2_724
+sym_2_724: la $2, sym_2_724
+.globl sym_2_725
+sym_2_725: la $2, sym_2_725
+.globl sym_2_726
+sym_2_726: la $2, sym_2_726
+.globl sym_2_727
+sym_2_727: la $2, sym_2_727
+.globl sym_2_728
+sym_2_728: la $2, sym_2_728
+.globl sym_2_729
+sym_2_729: la $2, sym_2_729
+.globl sym_2_730
+sym_2_730: la $2, sym_2_730
+.globl sym_2_731
+sym_2_731: la $2, sym_2_731
+.globl sym_2_732
+sym_2_732: la $2, sym_2_732
+.globl sym_2_733
+sym_2_733: la $2, sym_2_733
+.globl sym_2_734
+sym_2_734: la $2, sym_2_734
+.globl sym_2_735
+sym_2_735: la $2, sym_2_735
+.globl sym_2_736
+sym_2_736: la $2, sym_2_736
+.globl sym_2_737
+sym_2_737: la $2, sym_2_737
+.globl sym_2_738
+sym_2_738: la $2, sym_2_738
+.globl sym_2_739
+sym_2_739: la $2, sym_2_739
+.globl sym_2_740
+sym_2_740: la $2, sym_2_740
+.globl sym_2_741
+sym_2_741: la $2, sym_2_741
+.globl sym_2_742
+sym_2_742: la $2, sym_2_742
+.globl sym_2_743
+sym_2_743: la $2, sym_2_743
+.globl sym_2_744
+sym_2_744: la $2, sym_2_744
+.globl sym_2_745
+sym_2_745: la $2, sym_2_745
+.globl sym_2_746
+sym_2_746: la $2, sym_2_746
+.globl sym_2_747
+sym_2_747: la $2, sym_2_747
+.globl sym_2_748
+sym_2_748: la $2, sym_2_748
+.globl sym_2_749
+sym_2_749: la $2, sym_2_749
+.globl sym_2_750
+sym_2_750: la $2, sym_2_750
+.globl sym_2_751
+sym_2_751: la $2, sym_2_751
+.globl sym_2_752
+sym_2_752: la $2, sym_2_752
+.globl sym_2_753
+sym_2_753: la $2, sym_2_753
+.globl sym_2_754
+sym_2_754: la $2, sym_2_754
+.globl sym_2_755
+sym_2_755: la $2, sym_2_755
+.globl sym_2_756
+sym_2_756: la $2, sym_2_756
+.globl sym_2_757
+sym_2_757: la $2, sym_2_757
+.globl sym_2_758
+sym_2_758: la $2, sym_2_758
+.globl sym_2_759
+sym_2_759: la $2, sym_2_759
+.globl sym_2_760
+sym_2_760: la $2, sym_2_760
+.globl sym_2_761
+sym_2_761: la $2, sym_2_761
+.globl sym_2_762
+sym_2_762: la $2, sym_2_762
+.globl sym_2_763
+sym_2_763: la $2, sym_2_763
+.globl sym_2_764
+sym_2_764: la $2, sym_2_764
+.globl sym_2_765
+sym_2_765: la $2, sym_2_765
+.globl sym_2_766
+sym_2_766: la $2, sym_2_766
+.globl sym_2_767
+sym_2_767: la $2, sym_2_767
+.globl sym_2_768
+sym_2_768: la $2, sym_2_768
+.globl sym_2_769
+sym_2_769: la $2, sym_2_769
+.globl sym_2_770
+sym_2_770: la $2, sym_2_770
+.globl sym_2_771
+sym_2_771: la $2, sym_2_771
+.globl sym_2_772
+sym_2_772: la $2, sym_2_772
+.globl sym_2_773
+sym_2_773: la $2, sym_2_773
+.globl sym_2_774
+sym_2_774: la $2, sym_2_774
+.globl sym_2_775
+sym_2_775: la $2, sym_2_775
+.globl sym_2_776
+sym_2_776: la $2, sym_2_776
+.globl sym_2_777
+sym_2_777: la $2, sym_2_777
+.globl sym_2_778
+sym_2_778: la $2, sym_2_778
+.globl sym_2_779
+sym_2_779: la $2, sym_2_779
+.globl sym_2_780
+sym_2_780: la $2, sym_2_780
+.globl sym_2_781
+sym_2_781: la $2, sym_2_781
+.globl sym_2_782
+sym_2_782: la $2, sym_2_782
+.globl sym_2_783
+sym_2_783: la $2, sym_2_783
+.globl sym_2_784
+sym_2_784: la $2, sym_2_784
+.globl sym_2_785
+sym_2_785: la $2, sym_2_785
+.globl sym_2_786
+sym_2_786: la $2, sym_2_786
+.globl sym_2_787
+sym_2_787: la $2, sym_2_787
+.globl sym_2_788
+sym_2_788: la $2, sym_2_788
+.globl sym_2_789
+sym_2_789: la $2, sym_2_789
+.globl sym_2_790
+sym_2_790: la $2, sym_2_790
+.globl sym_2_791
+sym_2_791: la $2, sym_2_791
+.globl sym_2_792
+sym_2_792: la $2, sym_2_792
+.globl sym_2_793
+sym_2_793: la $2, sym_2_793
+.globl sym_2_794
+sym_2_794: la $2, sym_2_794
+.globl sym_2_795
+sym_2_795: la $2, sym_2_795
+.globl sym_2_796
+sym_2_796: la $2, sym_2_796
+.globl sym_2_797
+sym_2_797: la $2, sym_2_797
+.globl sym_2_798
+sym_2_798: la $2, sym_2_798
+.globl sym_2_799
+sym_2_799: la $2, sym_2_799
+.globl sym_2_800
+sym_2_800: la $2, sym_2_800
+.globl sym_2_801
+sym_2_801: la $2, sym_2_801
+.globl sym_2_802
+sym_2_802: la $2, sym_2_802
+.globl sym_2_803
+sym_2_803: la $2, sym_2_803
+.globl sym_2_804
+sym_2_804: la $2, sym_2_804
+.globl sym_2_805
+sym_2_805: la $2, sym_2_805
+.globl sym_2_806
+sym_2_806: la $2, sym_2_806
+.globl sym_2_807
+sym_2_807: la $2, sym_2_807
+.globl sym_2_808
+sym_2_808: la $2, sym_2_808
+.globl sym_2_809
+sym_2_809: la $2, sym_2_809
+.globl sym_2_810
+sym_2_810: la $2, sym_2_810
+.globl sym_2_811
+sym_2_811: la $2, sym_2_811
+.globl sym_2_812
+sym_2_812: la $2, sym_2_812
+.globl sym_2_813
+sym_2_813: la $2, sym_2_813
+.globl sym_2_814
+sym_2_814: la $2, sym_2_814
+.globl sym_2_815
+sym_2_815: la $2, sym_2_815
+.globl sym_2_816
+sym_2_816: la $2, sym_2_816
+.globl sym_2_817
+sym_2_817: la $2, sym_2_817
+.globl sym_2_818
+sym_2_818: la $2, sym_2_818
+.globl sym_2_819
+sym_2_819: la $2, sym_2_819
+.globl sym_2_820
+sym_2_820: la $2, sym_2_820
+.globl sym_2_821
+sym_2_821: la $2, sym_2_821
+.globl sym_2_822
+sym_2_822: la $2, sym_2_822
+.globl sym_2_823
+sym_2_823: la $2, sym_2_823
+.globl sym_2_824
+sym_2_824: la $2, sym_2_824
+.globl sym_2_825
+sym_2_825: la $2, sym_2_825
+.globl sym_2_826
+sym_2_826: la $2, sym_2_826
+.globl sym_2_827
+sym_2_827: la $2, sym_2_827
+.globl sym_2_828
+sym_2_828: la $2, sym_2_828
+.globl sym_2_829
+sym_2_829: la $2, sym_2_829
+.globl sym_2_830
+sym_2_830: la $2, sym_2_830
+.globl sym_2_831
+sym_2_831: la $2, sym_2_831
+.globl sym_2_832
+sym_2_832: la $2, sym_2_832
+.globl sym_2_833
+sym_2_833: la $2, sym_2_833
+.globl sym_2_834
+sym_2_834: la $2, sym_2_834
+.globl sym_2_835
+sym_2_835: la $2, sym_2_835
+.globl sym_2_836
+sym_2_836: la $2, sym_2_836
+.globl sym_2_837
+sym_2_837: la $2, sym_2_837
+.globl sym_2_838
+sym_2_838: la $2, sym_2_838
+.globl sym_2_839
+sym_2_839: la $2, sym_2_839
+.globl sym_2_840
+sym_2_840: la $2, sym_2_840
+.globl sym_2_841
+sym_2_841: la $2, sym_2_841
+.globl sym_2_842
+sym_2_842: la $2, sym_2_842
+.globl sym_2_843
+sym_2_843: la $2, sym_2_843
+.globl sym_2_844
+sym_2_844: la $2, sym_2_844
+.globl sym_2_845
+sym_2_845: la $2, sym_2_845
+.globl sym_2_846
+sym_2_846: la $2, sym_2_846
+.globl sym_2_847
+sym_2_847: la $2, sym_2_847
+.globl sym_2_848
+sym_2_848: la $2, sym_2_848
+.globl sym_2_849
+sym_2_849: la $2, sym_2_849
+.globl sym_2_850
+sym_2_850: la $2, sym_2_850
+.globl sym_2_851
+sym_2_851: la $2, sym_2_851
+.globl sym_2_852
+sym_2_852: la $2, sym_2_852
+.globl sym_2_853
+sym_2_853: la $2, sym_2_853
+.globl sym_2_854
+sym_2_854: la $2, sym_2_854
+.globl sym_2_855
+sym_2_855: la $2, sym_2_855
+.globl sym_2_856
+sym_2_856: la $2, sym_2_856
+.globl sym_2_857
+sym_2_857: la $2, sym_2_857
+.globl sym_2_858
+sym_2_858: la $2, sym_2_858
+.globl sym_2_859
+sym_2_859: la $2, sym_2_859
+.globl sym_2_860
+sym_2_860: la $2, sym_2_860
+.globl sym_2_861
+sym_2_861: la $2, sym_2_861
+.globl sym_2_862
+sym_2_862: la $2, sym_2_862
+.globl sym_2_863
+sym_2_863: la $2, sym_2_863
+.globl sym_2_864
+sym_2_864: la $2, sym_2_864
+.globl sym_2_865
+sym_2_865: la $2, sym_2_865
+.globl sym_2_866
+sym_2_866: la $2, sym_2_866
+.globl sym_2_867
+sym_2_867: la $2, sym_2_867
+.globl sym_2_868
+sym_2_868: la $2, sym_2_868
+.globl sym_2_869
+sym_2_869: la $2, sym_2_869
+.globl sym_2_870
+sym_2_870: la $2, sym_2_870
+.globl sym_2_871
+sym_2_871: la $2, sym_2_871
+.globl sym_2_872
+sym_2_872: la $2, sym_2_872
+.globl sym_2_873
+sym_2_873: la $2, sym_2_873
+.globl sym_2_874
+sym_2_874: la $2, sym_2_874
+.globl sym_2_875
+sym_2_875: la $2, sym_2_875
+.globl sym_2_876
+sym_2_876: la $2, sym_2_876
+.globl sym_2_877
+sym_2_877: la $2, sym_2_877
+.globl sym_2_878
+sym_2_878: la $2, sym_2_878
+.globl sym_2_879
+sym_2_879: la $2, sym_2_879
+.globl sym_2_880
+sym_2_880: la $2, sym_2_880
+.globl sym_2_881
+sym_2_881: la $2, sym_2_881
+.globl sym_2_882
+sym_2_882: la $2, sym_2_882
+.globl sym_2_883
+sym_2_883: la $2, sym_2_883
+.globl sym_2_884
+sym_2_884: la $2, sym_2_884
+.globl sym_2_885
+sym_2_885: la $2, sym_2_885
+.globl sym_2_886
+sym_2_886: la $2, sym_2_886
+.globl sym_2_887
+sym_2_887: la $2, sym_2_887
+.globl sym_2_888
+sym_2_888: la $2, sym_2_888
+.globl sym_2_889
+sym_2_889: la $2, sym_2_889
+.globl sym_2_890
+sym_2_890: la $2, sym_2_890
+.globl sym_2_891
+sym_2_891: la $2, sym_2_891
+.globl sym_2_892
+sym_2_892: la $2, sym_2_892
+.globl sym_2_893
+sym_2_893: la $2, sym_2_893
+.globl sym_2_894
+sym_2_894: la $2, sym_2_894
+.globl sym_2_895
+sym_2_895: la $2, sym_2_895
+.globl sym_2_896
+sym_2_896: la $2, sym_2_896
+.globl sym_2_897
+sym_2_897: la $2, sym_2_897
+.globl sym_2_898
+sym_2_898: la $2, sym_2_898
+.globl sym_2_899
+sym_2_899: la $2, sym_2_899
+.globl sym_2_900
+sym_2_900: la $2, sym_2_900
+.globl sym_2_901
+sym_2_901: la $2, sym_2_901
+.globl sym_2_902
+sym_2_902: la $2, sym_2_902
+.globl sym_2_903
+sym_2_903: la $2, sym_2_903
+.globl sym_2_904
+sym_2_904: la $2, sym_2_904
+.globl sym_2_905
+sym_2_905: la $2, sym_2_905
+.globl sym_2_906
+sym_2_906: la $2, sym_2_906
+.globl sym_2_907
+sym_2_907: la $2, sym_2_907
+.globl sym_2_908
+sym_2_908: la $2, sym_2_908
+.globl sym_2_909
+sym_2_909: la $2, sym_2_909
+.globl sym_2_910
+sym_2_910: la $2, sym_2_910
+.globl sym_2_911
+sym_2_911: la $2, sym_2_911
+.globl sym_2_912
+sym_2_912: la $2, sym_2_912
+.globl sym_2_913
+sym_2_913: la $2, sym_2_913
+.globl sym_2_914
+sym_2_914: la $2, sym_2_914
+.globl sym_2_915
+sym_2_915: la $2, sym_2_915
+.globl sym_2_916
+sym_2_916: la $2, sym_2_916
+.globl sym_2_917
+sym_2_917: la $2, sym_2_917
+.globl sym_2_918
+sym_2_918: la $2, sym_2_918
+.globl sym_2_919
+sym_2_919: la $2, sym_2_919
+.globl sym_2_920
+sym_2_920: la $2, sym_2_920
+.globl sym_2_921
+sym_2_921: la $2, sym_2_921
+.globl sym_2_922
+sym_2_922: la $2, sym_2_922
+.globl sym_2_923
+sym_2_923: la $2, sym_2_923
+.globl sym_2_924
+sym_2_924: la $2, sym_2_924
+.globl sym_2_925
+sym_2_925: la $2, sym_2_925
+.globl sym_2_926
+sym_2_926: la $2, sym_2_926
+.globl sym_2_927
+sym_2_927: la $2, sym_2_927
+.globl sym_2_928
+sym_2_928: la $2, sym_2_928
+.globl sym_2_929
+sym_2_929: la $2, sym_2_929
+.globl sym_2_930
+sym_2_930: la $2, sym_2_930
+.globl sym_2_931
+sym_2_931: la $2, sym_2_931
+.globl sym_2_932
+sym_2_932: la $2, sym_2_932
+.globl sym_2_933
+sym_2_933: la $2, sym_2_933
+.globl sym_2_934
+sym_2_934: la $2, sym_2_934
+.globl sym_2_935
+sym_2_935: la $2, sym_2_935
+.globl sym_2_936
+sym_2_936: la $2, sym_2_936
+.globl sym_2_937
+sym_2_937: la $2, sym_2_937
+.globl sym_2_938
+sym_2_938: la $2, sym_2_938
+.globl sym_2_939
+sym_2_939: la $2, sym_2_939
+.globl sym_2_940
+sym_2_940: la $2, sym_2_940
+.globl sym_2_941
+sym_2_941: la $2, sym_2_941
+.globl sym_2_942
+sym_2_942: la $2, sym_2_942
+.globl sym_2_943
+sym_2_943: la $2, sym_2_943
+.globl sym_2_944
+sym_2_944: la $2, sym_2_944
+.globl sym_2_945
+sym_2_945: la $2, sym_2_945
+.globl sym_2_946
+sym_2_946: la $2, sym_2_946
+.globl sym_2_947
+sym_2_947: la $2, sym_2_947
+.globl sym_2_948
+sym_2_948: la $2, sym_2_948
+.globl sym_2_949
+sym_2_949: la $2, sym_2_949
+.globl sym_2_950
+sym_2_950: la $2, sym_2_950
+.globl sym_2_951
+sym_2_951: la $2, sym_2_951
+.globl sym_2_952
+sym_2_952: la $2, sym_2_952
+.globl sym_2_953
+sym_2_953: la $2, sym_2_953
+.globl sym_2_954
+sym_2_954: la $2, sym_2_954
+.globl sym_2_955
+sym_2_955: la $2, sym_2_955
+.globl sym_2_956
+sym_2_956: la $2, sym_2_956
+.globl sym_2_957
+sym_2_957: la $2, sym_2_957
+.globl sym_2_958
+sym_2_958: la $2, sym_2_958
+.globl sym_2_959
+sym_2_959: la $2, sym_2_959
+.globl sym_2_960
+sym_2_960: la $2, sym_2_960
+.globl sym_2_961
+sym_2_961: la $2, sym_2_961
+.globl sym_2_962
+sym_2_962: la $2, sym_2_962
+.globl sym_2_963
+sym_2_963: la $2, sym_2_963
+.globl sym_2_964
+sym_2_964: la $2, sym_2_964
+.globl sym_2_965
+sym_2_965: la $2, sym_2_965
+.globl sym_2_966
+sym_2_966: la $2, sym_2_966
+.globl sym_2_967
+sym_2_967: la $2, sym_2_967
+.globl sym_2_968
+sym_2_968: la $2, sym_2_968
+.globl sym_2_969
+sym_2_969: la $2, sym_2_969
+.globl sym_2_970
+sym_2_970: la $2, sym_2_970
+.globl sym_2_971
+sym_2_971: la $2, sym_2_971
+.globl sym_2_972
+sym_2_972: la $2, sym_2_972
+.globl sym_2_973
+sym_2_973: la $2, sym_2_973
+.globl sym_2_974
+sym_2_974: la $2, sym_2_974
+.globl sym_2_975
+sym_2_975: la $2, sym_2_975
+.globl sym_2_976
+sym_2_976: la $2, sym_2_976
+.globl sym_2_977
+sym_2_977: la $2, sym_2_977
+.globl sym_2_978
+sym_2_978: la $2, sym_2_978
+.globl sym_2_979
+sym_2_979: la $2, sym_2_979
+.globl sym_2_980
+sym_2_980: la $2, sym_2_980
+.globl sym_2_981
+sym_2_981: la $2, sym_2_981
+.globl sym_2_982
+sym_2_982: la $2, sym_2_982
+.globl sym_2_983
+sym_2_983: la $2, sym_2_983
+.globl sym_2_984
+sym_2_984: la $2, sym_2_984
+.globl sym_2_985
+sym_2_985: la $2, sym_2_985
+.globl sym_2_986
+sym_2_986: la $2, sym_2_986
+.globl sym_2_987
+sym_2_987: la $2, sym_2_987
+.globl sym_2_988
+sym_2_988: la $2, sym_2_988
+.globl sym_2_989
+sym_2_989: la $2, sym_2_989
+.globl sym_2_990
+sym_2_990: la $2, sym_2_990
+.globl sym_2_991
+sym_2_991: la $2, sym_2_991
+.globl sym_2_992
+sym_2_992: la $2, sym_2_992
+.globl sym_2_993
+sym_2_993: la $2, sym_2_993
+.globl sym_2_994
+sym_2_994: la $2, sym_2_994
+.globl sym_2_995
+sym_2_995: la $2, sym_2_995
+.globl sym_2_996
+sym_2_996: la $2, sym_2_996
+.globl sym_2_997
+sym_2_997: la $2, sym_2_997
+.globl sym_2_998
+sym_2_998: la $2, sym_2_998
+.globl sym_2_999
+sym_2_999: la $2, sym_2_999
+.globl sym_2_1000
+sym_2_1000: la $2, sym_2_1000
+.globl sym_2_1001
+sym_2_1001: la $2, sym_2_1001
+.globl sym_2_1002
+sym_2_1002: la $2, sym_2_1002
+.globl sym_2_1003
+sym_2_1003: la $2, sym_2_1003
+.globl sym_2_1004
+sym_2_1004: la $2, sym_2_1004
+.globl sym_2_1005
+sym_2_1005: la $2, sym_2_1005
+.globl sym_2_1006
+sym_2_1006: la $2, sym_2_1006
+.globl sym_2_1007
+sym_2_1007: la $2, sym_2_1007
+.globl sym_2_1008
+sym_2_1008: la $2, sym_2_1008
+.globl sym_2_1009
+sym_2_1009: la $2, sym_2_1009
+.globl sym_2_1010
+sym_2_1010: la $2, sym_2_1010
+.globl sym_2_1011
+sym_2_1011: la $2, sym_2_1011
+.globl sym_2_1012
+sym_2_1012: la $2, sym_2_1012
+.globl sym_2_1013
+sym_2_1013: la $2, sym_2_1013
+.globl sym_2_1014
+sym_2_1014: la $2, sym_2_1014
+.globl sym_2_1015
+sym_2_1015: la $2, sym_2_1015
+.globl sym_2_1016
+sym_2_1016: la $2, sym_2_1016
+.globl sym_2_1017
+sym_2_1017: la $2, sym_2_1017
+.globl sym_2_1018
+sym_2_1018: la $2, sym_2_1018
+.globl sym_2_1019
+sym_2_1019: la $2, sym_2_1019
+.globl sym_2_1020
+sym_2_1020: la $2, sym_2_1020
+.globl sym_2_1021
+sym_2_1021: la $2, sym_2_1021
+.globl sym_2_1022
+sym_2_1022: la $2, sym_2_1022
+.globl sym_2_1023
+sym_2_1023: la $2, sym_2_1023
+.globl sym_2_1024
+sym_2_1024: la $2, sym_2_1024
+.globl sym_2_1025
+sym_2_1025: la $2, sym_2_1025
+.globl sym_2_1026
+sym_2_1026: la $2, sym_2_1026
+.globl sym_2_1027
+sym_2_1027: la $2, sym_2_1027
+.globl sym_2_1028
+sym_2_1028: la $2, sym_2_1028
+.globl sym_2_1029
+sym_2_1029: la $2, sym_2_1029
+.globl sym_2_1030
+sym_2_1030: la $2, sym_2_1030
+.globl sym_2_1031
+sym_2_1031: la $2, sym_2_1031
+.globl sym_2_1032
+sym_2_1032: la $2, sym_2_1032
+.globl sym_2_1033
+sym_2_1033: la $2, sym_2_1033
+.globl sym_2_1034
+sym_2_1034: la $2, sym_2_1034
+.globl sym_2_1035
+sym_2_1035: la $2, sym_2_1035
+.globl sym_2_1036
+sym_2_1036: la $2, sym_2_1036
+.globl sym_2_1037
+sym_2_1037: la $2, sym_2_1037
+.globl sym_2_1038
+sym_2_1038: la $2, sym_2_1038
+.globl sym_2_1039
+sym_2_1039: la $2, sym_2_1039
+.globl sym_2_1040
+sym_2_1040: la $2, sym_2_1040
+.globl sym_2_1041
+sym_2_1041: la $2, sym_2_1041
+.globl sym_2_1042
+sym_2_1042: la $2, sym_2_1042
+.globl sym_2_1043
+sym_2_1043: la $2, sym_2_1043
+.globl sym_2_1044
+sym_2_1044: la $2, sym_2_1044
+.globl sym_2_1045
+sym_2_1045: la $2, sym_2_1045
+.globl sym_2_1046
+sym_2_1046: la $2, sym_2_1046
+.globl sym_2_1047
+sym_2_1047: la $2, sym_2_1047
+.globl sym_2_1048
+sym_2_1048: la $2, sym_2_1048
+.globl sym_2_1049
+sym_2_1049: la $2, sym_2_1049
+.globl sym_2_1050
+sym_2_1050: la $2, sym_2_1050
+.globl sym_2_1051
+sym_2_1051: la $2, sym_2_1051
+.globl sym_2_1052
+sym_2_1052: la $2, sym_2_1052
+.globl sym_2_1053
+sym_2_1053: la $2, sym_2_1053
+.globl sym_2_1054
+sym_2_1054: la $2, sym_2_1054
+.globl sym_2_1055
+sym_2_1055: la $2, sym_2_1055
+.globl sym_2_1056
+sym_2_1056: la $2, sym_2_1056
+.globl sym_2_1057
+sym_2_1057: la $2, sym_2_1057
+.globl sym_2_1058
+sym_2_1058: la $2, sym_2_1058
+.globl sym_2_1059
+sym_2_1059: la $2, sym_2_1059
+.globl sym_2_1060
+sym_2_1060: la $2, sym_2_1060
+.globl sym_2_1061
+sym_2_1061: la $2, sym_2_1061
+.globl sym_2_1062
+sym_2_1062: la $2, sym_2_1062
+.globl sym_2_1063
+sym_2_1063: la $2, sym_2_1063
+.globl sym_2_1064
+sym_2_1064: la $2, sym_2_1064
+.globl sym_2_1065
+sym_2_1065: la $2, sym_2_1065
+.globl sym_2_1066
+sym_2_1066: la $2, sym_2_1066
+.globl sym_2_1067
+sym_2_1067: la $2, sym_2_1067
+.globl sym_2_1068
+sym_2_1068: la $2, sym_2_1068
+.globl sym_2_1069
+sym_2_1069: la $2, sym_2_1069
+.globl sym_2_1070
+sym_2_1070: la $2, sym_2_1070
+.globl sym_2_1071
+sym_2_1071: la $2, sym_2_1071
+.globl sym_2_1072
+sym_2_1072: la $2, sym_2_1072
+.globl sym_2_1073
+sym_2_1073: la $2, sym_2_1073
+.globl sym_2_1074
+sym_2_1074: la $2, sym_2_1074
+.globl sym_2_1075
+sym_2_1075: la $2, sym_2_1075
+.globl sym_2_1076
+sym_2_1076: la $2, sym_2_1076
+.globl sym_2_1077
+sym_2_1077: la $2, sym_2_1077
+.globl sym_2_1078
+sym_2_1078: la $2, sym_2_1078
+.globl sym_2_1079
+sym_2_1079: la $2, sym_2_1079
+.globl sym_2_1080
+sym_2_1080: la $2, sym_2_1080
+.globl sym_2_1081
+sym_2_1081: la $2, sym_2_1081
+.globl sym_2_1082
+sym_2_1082: la $2, sym_2_1082
+.globl sym_2_1083
+sym_2_1083: la $2, sym_2_1083
+.globl sym_2_1084
+sym_2_1084: la $2, sym_2_1084
+.globl sym_2_1085
+sym_2_1085: la $2, sym_2_1085
+.globl sym_2_1086
+sym_2_1086: la $2, sym_2_1086
+.globl sym_2_1087
+sym_2_1087: la $2, sym_2_1087
+.globl sym_2_1088
+sym_2_1088: la $2, sym_2_1088
+.globl sym_2_1089
+sym_2_1089: la $2, sym_2_1089
+.globl sym_2_1090
+sym_2_1090: la $2, sym_2_1090
+.globl sym_2_1091
+sym_2_1091: la $2, sym_2_1091
+.globl sym_2_1092
+sym_2_1092: la $2, sym_2_1092
+.globl sym_2_1093
+sym_2_1093: la $2, sym_2_1093
+.globl sym_2_1094
+sym_2_1094: la $2, sym_2_1094
+.globl sym_2_1095
+sym_2_1095: la $2, sym_2_1095
+.globl sym_2_1096
+sym_2_1096: la $2, sym_2_1096
+.globl sym_2_1097
+sym_2_1097: la $2, sym_2_1097
+.globl sym_2_1098
+sym_2_1098: la $2, sym_2_1098
+.globl sym_2_1099
+sym_2_1099: la $2, sym_2_1099
+.globl sym_2_1100
+sym_2_1100: la $2, sym_2_1100
+.globl sym_2_1101
+sym_2_1101: la $2, sym_2_1101
+.globl sym_2_1102
+sym_2_1102: la $2, sym_2_1102
+.globl sym_2_1103
+sym_2_1103: la $2, sym_2_1103
+.globl sym_2_1104
+sym_2_1104: la $2, sym_2_1104
+.globl sym_2_1105
+sym_2_1105: la $2, sym_2_1105
+.globl sym_2_1106
+sym_2_1106: la $2, sym_2_1106
+.globl sym_2_1107
+sym_2_1107: la $2, sym_2_1107
+.globl sym_2_1108
+sym_2_1108: la $2, sym_2_1108
+.globl sym_2_1109
+sym_2_1109: la $2, sym_2_1109
+.globl sym_2_1110
+sym_2_1110: la $2, sym_2_1110
+.globl sym_2_1111
+sym_2_1111: la $2, sym_2_1111
+.globl sym_2_1112
+sym_2_1112: la $2, sym_2_1112
+.globl sym_2_1113
+sym_2_1113: la $2, sym_2_1113
+.globl sym_2_1114
+sym_2_1114: la $2, sym_2_1114
+.globl sym_2_1115
+sym_2_1115: la $2, sym_2_1115
+.globl sym_2_1116
+sym_2_1116: la $2, sym_2_1116
+.globl sym_2_1117
+sym_2_1117: la $2, sym_2_1117
+.globl sym_2_1118
+sym_2_1118: la $2, sym_2_1118
+.globl sym_2_1119
+sym_2_1119: la $2, sym_2_1119
+.globl sym_2_1120
+sym_2_1120: la $2, sym_2_1120
+.globl sym_2_1121
+sym_2_1121: la $2, sym_2_1121
+.globl sym_2_1122
+sym_2_1122: la $2, sym_2_1122
+.globl sym_2_1123
+sym_2_1123: la $2, sym_2_1123
+.globl sym_2_1124
+sym_2_1124: la $2, sym_2_1124
+.globl sym_2_1125
+sym_2_1125: la $2, sym_2_1125
+.globl sym_2_1126
+sym_2_1126: la $2, sym_2_1126
+.globl sym_2_1127
+sym_2_1127: la $2, sym_2_1127
+.globl sym_2_1128
+sym_2_1128: la $2, sym_2_1128
+.globl sym_2_1129
+sym_2_1129: la $2, sym_2_1129
+.globl sym_2_1130
+sym_2_1130: la $2, sym_2_1130
+.globl sym_2_1131
+sym_2_1131: la $2, sym_2_1131
+.globl sym_2_1132
+sym_2_1132: la $2, sym_2_1132
+.globl sym_2_1133
+sym_2_1133: la $2, sym_2_1133
+.globl sym_2_1134
+sym_2_1134: la $2, sym_2_1134
+.globl sym_2_1135
+sym_2_1135: la $2, sym_2_1135
+.globl sym_2_1136
+sym_2_1136: la $2, sym_2_1136
+.globl sym_2_1137
+sym_2_1137: la $2, sym_2_1137
+.globl sym_2_1138
+sym_2_1138: la $2, sym_2_1138
+.globl sym_2_1139
+sym_2_1139: la $2, sym_2_1139
+.globl sym_2_1140
+sym_2_1140: la $2, sym_2_1140
+.globl sym_2_1141
+sym_2_1141: la $2, sym_2_1141
+.globl sym_2_1142
+sym_2_1142: la $2, sym_2_1142
+.globl sym_2_1143
+sym_2_1143: la $2, sym_2_1143
+.globl sym_2_1144
+sym_2_1144: la $2, sym_2_1144
+.globl sym_2_1145
+sym_2_1145: la $2, sym_2_1145
+.globl sym_2_1146
+sym_2_1146: la $2, sym_2_1146
+.globl sym_2_1147
+sym_2_1147: la $2, sym_2_1147
+.globl sym_2_1148
+sym_2_1148: la $2, sym_2_1148
+.globl sym_2_1149
+sym_2_1149: la $2, sym_2_1149
+.globl sym_2_1150
+sym_2_1150: la $2, sym_2_1150
+.globl sym_2_1151
+sym_2_1151: la $2, sym_2_1151
+.globl sym_2_1152
+sym_2_1152: la $2, sym_2_1152
+.globl sym_2_1153
+sym_2_1153: la $2, sym_2_1153
+.globl sym_2_1154
+sym_2_1154: la $2, sym_2_1154
+.globl sym_2_1155
+sym_2_1155: la $2, sym_2_1155
+.globl sym_2_1156
+sym_2_1156: la $2, sym_2_1156
+.globl sym_2_1157
+sym_2_1157: la $2, sym_2_1157
+.globl sym_2_1158
+sym_2_1158: la $2, sym_2_1158
+.globl sym_2_1159
+sym_2_1159: la $2, sym_2_1159
+.globl sym_2_1160
+sym_2_1160: la $2, sym_2_1160
+.globl sym_2_1161
+sym_2_1161: la $2, sym_2_1161
+.globl sym_2_1162
+sym_2_1162: la $2, sym_2_1162
+.globl sym_2_1163
+sym_2_1163: la $2, sym_2_1163
+.globl sym_2_1164
+sym_2_1164: la $2, sym_2_1164
+.globl sym_2_1165
+sym_2_1165: la $2, sym_2_1165
+.globl sym_2_1166
+sym_2_1166: la $2, sym_2_1166
+.globl sym_2_1167
+sym_2_1167: la $2, sym_2_1167
+.globl sym_2_1168
+sym_2_1168: la $2, sym_2_1168
+.globl sym_2_1169
+sym_2_1169: la $2, sym_2_1169
+.globl sym_2_1170
+sym_2_1170: la $2, sym_2_1170
+.globl sym_2_1171
+sym_2_1171: la $2, sym_2_1171
+.globl sym_2_1172
+sym_2_1172: la $2, sym_2_1172
+.globl sym_2_1173
+sym_2_1173: la $2, sym_2_1173
+.globl sym_2_1174
+sym_2_1174: la $2, sym_2_1174
+.globl sym_2_1175
+sym_2_1175: la $2, sym_2_1175
+.globl sym_2_1176
+sym_2_1176: la $2, sym_2_1176
+.globl sym_2_1177
+sym_2_1177: la $2, sym_2_1177
+.globl sym_2_1178
+sym_2_1178: la $2, sym_2_1178
+.globl sym_2_1179
+sym_2_1179: la $2, sym_2_1179
+.globl sym_2_1180
+sym_2_1180: la $2, sym_2_1180
+.globl sym_2_1181
+sym_2_1181: la $2, sym_2_1181
+.globl sym_2_1182
+sym_2_1182: la $2, sym_2_1182
+.globl sym_2_1183
+sym_2_1183: la $2, sym_2_1183
+.globl sym_2_1184
+sym_2_1184: la $2, sym_2_1184
+.globl sym_2_1185
+sym_2_1185: la $2, sym_2_1185
+.globl sym_2_1186
+sym_2_1186: la $2, sym_2_1186
+.globl sym_2_1187
+sym_2_1187: la $2, sym_2_1187
+.globl sym_2_1188
+sym_2_1188: la $2, sym_2_1188
+.globl sym_2_1189
+sym_2_1189: la $2, sym_2_1189
+.globl sym_2_1190
+sym_2_1190: la $2, sym_2_1190
+.globl sym_2_1191
+sym_2_1191: la $2, sym_2_1191
+.globl sym_2_1192
+sym_2_1192: la $2, sym_2_1192
+.globl sym_2_1193
+sym_2_1193: la $2, sym_2_1193
+.globl sym_2_1194
+sym_2_1194: la $2, sym_2_1194
+.globl sym_2_1195
+sym_2_1195: la $2, sym_2_1195
+.globl sym_2_1196
+sym_2_1196: la $2, sym_2_1196
+.globl sym_2_1197
+sym_2_1197: la $2, sym_2_1197
+.globl sym_2_1198
+sym_2_1198: la $2, sym_2_1198
+.globl sym_2_1199
+sym_2_1199: la $2, sym_2_1199
+.globl sym_2_1200
+sym_2_1200: la $2, sym_2_1200
+.globl sym_2_1201
+sym_2_1201: la $2, sym_2_1201
+.globl sym_2_1202
+sym_2_1202: la $2, sym_2_1202
+.globl sym_2_1203
+sym_2_1203: la $2, sym_2_1203
+.globl sym_2_1204
+sym_2_1204: la $2, sym_2_1204
+.globl sym_2_1205
+sym_2_1205: la $2, sym_2_1205
+.globl sym_2_1206
+sym_2_1206: la $2, sym_2_1206
+.globl sym_2_1207
+sym_2_1207: la $2, sym_2_1207
+.globl sym_2_1208
+sym_2_1208: la $2, sym_2_1208
+.globl sym_2_1209
+sym_2_1209: la $2, sym_2_1209
+.globl sym_2_1210
+sym_2_1210: la $2, sym_2_1210
+.globl sym_2_1211
+sym_2_1211: la $2, sym_2_1211
+.globl sym_2_1212
+sym_2_1212: la $2, sym_2_1212
+.globl sym_2_1213
+sym_2_1213: la $2, sym_2_1213
+.globl sym_2_1214
+sym_2_1214: la $2, sym_2_1214
+.globl sym_2_1215
+sym_2_1215: la $2, sym_2_1215
+.globl sym_2_1216
+sym_2_1216: la $2, sym_2_1216
+.globl sym_2_1217
+sym_2_1217: la $2, sym_2_1217
+.globl sym_2_1218
+sym_2_1218: la $2, sym_2_1218
+.globl sym_2_1219
+sym_2_1219: la $2, sym_2_1219
+.globl sym_2_1220
+sym_2_1220: la $2, sym_2_1220
+.globl sym_2_1221
+sym_2_1221: la $2, sym_2_1221
+.globl sym_2_1222
+sym_2_1222: la $2, sym_2_1222
+.globl sym_2_1223
+sym_2_1223: la $2, sym_2_1223
+.globl sym_2_1224
+sym_2_1224: la $2, sym_2_1224
+.globl sym_2_1225
+sym_2_1225: la $2, sym_2_1225
+.globl sym_2_1226
+sym_2_1226: la $2, sym_2_1226
+.globl sym_2_1227
+sym_2_1227: la $2, sym_2_1227
+.globl sym_2_1228
+sym_2_1228: la $2, sym_2_1228
+.globl sym_2_1229
+sym_2_1229: la $2, sym_2_1229
+.globl sym_2_1230
+sym_2_1230: la $2, sym_2_1230
+.globl sym_2_1231
+sym_2_1231: la $2, sym_2_1231
+.globl sym_2_1232
+sym_2_1232: la $2, sym_2_1232
+.globl sym_2_1233
+sym_2_1233: la $2, sym_2_1233
+.globl sym_2_1234
+sym_2_1234: la $2, sym_2_1234
+.globl sym_2_1235
+sym_2_1235: la $2, sym_2_1235
+.globl sym_2_1236
+sym_2_1236: la $2, sym_2_1236
+.globl sym_2_1237
+sym_2_1237: la $2, sym_2_1237
+.globl sym_2_1238
+sym_2_1238: la $2, sym_2_1238
+.globl sym_2_1239
+sym_2_1239: la $2, sym_2_1239
+.globl sym_2_1240
+sym_2_1240: la $2, sym_2_1240
+.globl sym_2_1241
+sym_2_1241: la $2, sym_2_1241
+.globl sym_2_1242
+sym_2_1242: la $2, sym_2_1242
+.globl sym_2_1243
+sym_2_1243: la $2, sym_2_1243
+.globl sym_2_1244
+sym_2_1244: la $2, sym_2_1244
+.globl sym_2_1245
+sym_2_1245: la $2, sym_2_1245
+.globl sym_2_1246
+sym_2_1246: la $2, sym_2_1246
+.globl sym_2_1247
+sym_2_1247: la $2, sym_2_1247
+.globl sym_2_1248
+sym_2_1248: la $2, sym_2_1248
+.globl sym_2_1249
+sym_2_1249: la $2, sym_2_1249
+.globl sym_2_1250
+sym_2_1250: la $2, sym_2_1250
+.globl sym_2_1251
+sym_2_1251: la $2, sym_2_1251
+.globl sym_2_1252
+sym_2_1252: la $2, sym_2_1252
+.globl sym_2_1253
+sym_2_1253: la $2, sym_2_1253
+.globl sym_2_1254
+sym_2_1254: la $2, sym_2_1254
+.globl sym_2_1255
+sym_2_1255: la $2, sym_2_1255
+.globl sym_2_1256
+sym_2_1256: la $2, sym_2_1256
+.globl sym_2_1257
+sym_2_1257: la $2, sym_2_1257
+.globl sym_2_1258
+sym_2_1258: la $2, sym_2_1258
+.globl sym_2_1259
+sym_2_1259: la $2, sym_2_1259
+.globl sym_2_1260
+sym_2_1260: la $2, sym_2_1260
+.globl sym_2_1261
+sym_2_1261: la $2, sym_2_1261
+.globl sym_2_1262
+sym_2_1262: la $2, sym_2_1262
+.globl sym_2_1263
+sym_2_1263: la $2, sym_2_1263
+.globl sym_2_1264
+sym_2_1264: la $2, sym_2_1264
+.globl sym_2_1265
+sym_2_1265: la $2, sym_2_1265
+.globl sym_2_1266
+sym_2_1266: la $2, sym_2_1266
+.globl sym_2_1267
+sym_2_1267: la $2, sym_2_1267
+.globl sym_2_1268
+sym_2_1268: la $2, sym_2_1268
+.globl sym_2_1269
+sym_2_1269: la $2, sym_2_1269
+.globl sym_2_1270
+sym_2_1270: la $2, sym_2_1270
+.globl sym_2_1271
+sym_2_1271: la $2, sym_2_1271
+.globl sym_2_1272
+sym_2_1272: la $2, sym_2_1272
+.globl sym_2_1273
+sym_2_1273: la $2, sym_2_1273
+.globl sym_2_1274
+sym_2_1274: la $2, sym_2_1274
+.globl sym_2_1275
+sym_2_1275: la $2, sym_2_1275
+.globl sym_2_1276
+sym_2_1276: la $2, sym_2_1276
+.globl sym_2_1277
+sym_2_1277: la $2, sym_2_1277
+.globl sym_2_1278
+sym_2_1278: la $2, sym_2_1278
+.globl sym_2_1279
+sym_2_1279: la $2, sym_2_1279
+.globl sym_2_1280
+sym_2_1280: la $2, sym_2_1280
+.globl sym_2_1281
+sym_2_1281: la $2, sym_2_1281
+.globl sym_2_1282
+sym_2_1282: la $2, sym_2_1282
+.globl sym_2_1283
+sym_2_1283: la $2, sym_2_1283
+.globl sym_2_1284
+sym_2_1284: la $2, sym_2_1284
+.globl sym_2_1285
+sym_2_1285: la $2, sym_2_1285
+.globl sym_2_1286
+sym_2_1286: la $2, sym_2_1286
+.globl sym_2_1287
+sym_2_1287: la $2, sym_2_1287
+.globl sym_2_1288
+sym_2_1288: la $2, sym_2_1288
+.globl sym_2_1289
+sym_2_1289: la $2, sym_2_1289
+.globl sym_2_1290
+sym_2_1290: la $2, sym_2_1290
+.globl sym_2_1291
+sym_2_1291: la $2, sym_2_1291
+.globl sym_2_1292
+sym_2_1292: la $2, sym_2_1292
+.globl sym_2_1293
+sym_2_1293: la $2, sym_2_1293
+.globl sym_2_1294
+sym_2_1294: la $2, sym_2_1294
+.globl sym_2_1295
+sym_2_1295: la $2, sym_2_1295
+.globl sym_2_1296
+sym_2_1296: la $2, sym_2_1296
+.globl sym_2_1297
+sym_2_1297: la $2, sym_2_1297
+.globl sym_2_1298
+sym_2_1298: la $2, sym_2_1298
+.globl sym_2_1299
+sym_2_1299: la $2, sym_2_1299
+.globl sym_2_1300
+sym_2_1300: la $2, sym_2_1300
+.globl sym_2_1301
+sym_2_1301: la $2, sym_2_1301
+.globl sym_2_1302
+sym_2_1302: la $2, sym_2_1302
+.globl sym_2_1303
+sym_2_1303: la $2, sym_2_1303
+.globl sym_2_1304
+sym_2_1304: la $2, sym_2_1304
+.globl sym_2_1305
+sym_2_1305: la $2, sym_2_1305
+.globl sym_2_1306
+sym_2_1306: la $2, sym_2_1306
+.globl sym_2_1307
+sym_2_1307: la $2, sym_2_1307
+.globl sym_2_1308
+sym_2_1308: la $2, sym_2_1308
+.globl sym_2_1309
+sym_2_1309: la $2, sym_2_1309
+.globl sym_2_1310
+sym_2_1310: la $2, sym_2_1310
+.globl sym_2_1311
+sym_2_1311: la $2, sym_2_1311
+.globl sym_2_1312
+sym_2_1312: la $2, sym_2_1312
+.globl sym_2_1313
+sym_2_1313: la $2, sym_2_1313
+.globl sym_2_1314
+sym_2_1314: la $2, sym_2_1314
+.globl sym_2_1315
+sym_2_1315: la $2, sym_2_1315
+.globl sym_2_1316
+sym_2_1316: la $2, sym_2_1316
+.globl sym_2_1317
+sym_2_1317: la $2, sym_2_1317
+.globl sym_2_1318
+sym_2_1318: la $2, sym_2_1318
+.globl sym_2_1319
+sym_2_1319: la $2, sym_2_1319
+.globl sym_2_1320
+sym_2_1320: la $2, sym_2_1320
+.globl sym_2_1321
+sym_2_1321: la $2, sym_2_1321
+.globl sym_2_1322
+sym_2_1322: la $2, sym_2_1322
+.globl sym_2_1323
+sym_2_1323: la $2, sym_2_1323
+.globl sym_2_1324
+sym_2_1324: la $2, sym_2_1324
+.globl sym_2_1325
+sym_2_1325: la $2, sym_2_1325
+.globl sym_2_1326
+sym_2_1326: la $2, sym_2_1326
+.globl sym_2_1327
+sym_2_1327: la $2, sym_2_1327
+.globl sym_2_1328
+sym_2_1328: la $2, sym_2_1328
+.globl sym_2_1329
+sym_2_1329: la $2, sym_2_1329
+.globl sym_2_1330
+sym_2_1330: la $2, sym_2_1330
+.globl sym_2_1331
+sym_2_1331: la $2, sym_2_1331
+.globl sym_2_1332
+sym_2_1332: la $2, sym_2_1332
+.globl sym_2_1333
+sym_2_1333: la $2, sym_2_1333
+.globl sym_2_1334
+sym_2_1334: la $2, sym_2_1334
+.globl sym_2_1335
+sym_2_1335: la $2, sym_2_1335
+.globl sym_2_1336
+sym_2_1336: la $2, sym_2_1336
+.globl sym_2_1337
+sym_2_1337: la $2, sym_2_1337
+.globl sym_2_1338
+sym_2_1338: la $2, sym_2_1338
+.globl sym_2_1339
+sym_2_1339: la $2, sym_2_1339
+.globl sym_2_1340
+sym_2_1340: la $2, sym_2_1340
+.globl sym_2_1341
+sym_2_1341: la $2, sym_2_1341
+.globl sym_2_1342
+sym_2_1342: la $2, sym_2_1342
+.globl sym_2_1343
+sym_2_1343: la $2, sym_2_1343
+.globl sym_2_1344
+sym_2_1344: la $2, sym_2_1344
+.globl sym_2_1345
+sym_2_1345: la $2, sym_2_1345
+.globl sym_2_1346
+sym_2_1346: la $2, sym_2_1346
+.globl sym_2_1347
+sym_2_1347: la $2, sym_2_1347
+.globl sym_2_1348
+sym_2_1348: la $2, sym_2_1348
+.globl sym_2_1349
+sym_2_1349: la $2, sym_2_1349
+.globl sym_2_1350
+sym_2_1350: la $2, sym_2_1350
+.globl sym_2_1351
+sym_2_1351: la $2, sym_2_1351
+.globl sym_2_1352
+sym_2_1352: la $2, sym_2_1352
+.globl sym_2_1353
+sym_2_1353: la $2, sym_2_1353
+.globl sym_2_1354
+sym_2_1354: la $2, sym_2_1354
+.globl sym_2_1355
+sym_2_1355: la $2, sym_2_1355
+.globl sym_2_1356
+sym_2_1356: la $2, sym_2_1356
+.globl sym_2_1357
+sym_2_1357: la $2, sym_2_1357
+.globl sym_2_1358
+sym_2_1358: la $2, sym_2_1358
+.globl sym_2_1359
+sym_2_1359: la $2, sym_2_1359
+.globl sym_2_1360
+sym_2_1360: la $2, sym_2_1360
+.globl sym_2_1361
+sym_2_1361: la $2, sym_2_1361
+.globl sym_2_1362
+sym_2_1362: la $2, sym_2_1362
+.globl sym_2_1363
+sym_2_1363: la $2, sym_2_1363
+.globl sym_2_1364
+sym_2_1364: la $2, sym_2_1364
+.globl sym_2_1365
+sym_2_1365: la $2, sym_2_1365
+.globl sym_2_1366
+sym_2_1366: la $2, sym_2_1366
+.globl sym_2_1367
+sym_2_1367: la $2, sym_2_1367
+.globl sym_2_1368
+sym_2_1368: la $2, sym_2_1368
+.globl sym_2_1369
+sym_2_1369: la $2, sym_2_1369
+.globl sym_2_1370
+sym_2_1370: la $2, sym_2_1370
+.globl sym_2_1371
+sym_2_1371: la $2, sym_2_1371
+.globl sym_2_1372
+sym_2_1372: la $2, sym_2_1372
+.globl sym_2_1373
+sym_2_1373: la $2, sym_2_1373
+.globl sym_2_1374
+sym_2_1374: la $2, sym_2_1374
+.globl sym_2_1375
+sym_2_1375: la $2, sym_2_1375
+.globl sym_2_1376
+sym_2_1376: la $2, sym_2_1376
+.globl sym_2_1377
+sym_2_1377: la $2, sym_2_1377
+.globl sym_2_1378
+sym_2_1378: la $2, sym_2_1378
+.globl sym_2_1379
+sym_2_1379: la $2, sym_2_1379
+.globl sym_2_1380
+sym_2_1380: la $2, sym_2_1380
+.globl sym_2_1381
+sym_2_1381: la $2, sym_2_1381
+.globl sym_2_1382
+sym_2_1382: la $2, sym_2_1382
+.globl sym_2_1383
+sym_2_1383: la $2, sym_2_1383
+.globl sym_2_1384
+sym_2_1384: la $2, sym_2_1384
+.globl sym_2_1385
+sym_2_1385: la $2, sym_2_1385
+.globl sym_2_1386
+sym_2_1386: la $2, sym_2_1386
+.globl sym_2_1387
+sym_2_1387: la $2, sym_2_1387
+.globl sym_2_1388
+sym_2_1388: la $2, sym_2_1388
+.globl sym_2_1389
+sym_2_1389: la $2, sym_2_1389
+.globl sym_2_1390
+sym_2_1390: la $2, sym_2_1390
+.globl sym_2_1391
+sym_2_1391: la $2, sym_2_1391
+.globl sym_2_1392
+sym_2_1392: la $2, sym_2_1392
+.globl sym_2_1393
+sym_2_1393: la $2, sym_2_1393
+.globl sym_2_1394
+sym_2_1394: la $2, sym_2_1394
+.globl sym_2_1395
+sym_2_1395: la $2, sym_2_1395
+.globl sym_2_1396
+sym_2_1396: la $2, sym_2_1396
+.globl sym_2_1397
+sym_2_1397: la $2, sym_2_1397
+.globl sym_2_1398
+sym_2_1398: la $2, sym_2_1398
+.globl sym_2_1399
+sym_2_1399: la $2, sym_2_1399
+.globl sym_2_1400
+sym_2_1400: la $2, sym_2_1400
+.globl sym_2_1401
+sym_2_1401: la $2, sym_2_1401
+.globl sym_2_1402
+sym_2_1402: la $2, sym_2_1402
+.globl sym_2_1403
+sym_2_1403: la $2, sym_2_1403
+.globl sym_2_1404
+sym_2_1404: la $2, sym_2_1404
+.globl sym_2_1405
+sym_2_1405: la $2, sym_2_1405
+.globl sym_2_1406
+sym_2_1406: la $2, sym_2_1406
+.globl sym_2_1407
+sym_2_1407: la $2, sym_2_1407
+.globl sym_2_1408
+sym_2_1408: la $2, sym_2_1408
+.globl sym_2_1409
+sym_2_1409: la $2, sym_2_1409
+.globl sym_2_1410
+sym_2_1410: la $2, sym_2_1410
+.globl sym_2_1411
+sym_2_1411: la $2, sym_2_1411
+.globl sym_2_1412
+sym_2_1412: la $2, sym_2_1412
+.globl sym_2_1413
+sym_2_1413: la $2, sym_2_1413
+.globl sym_2_1414
+sym_2_1414: la $2, sym_2_1414
+.globl sym_2_1415
+sym_2_1415: la $2, sym_2_1415
+.globl sym_2_1416
+sym_2_1416: la $2, sym_2_1416
+.globl sym_2_1417
+sym_2_1417: la $2, sym_2_1417
+.globl sym_2_1418
+sym_2_1418: la $2, sym_2_1418
+.globl sym_2_1419
+sym_2_1419: la $2, sym_2_1419
+.globl sym_2_1420
+sym_2_1420: la $2, sym_2_1420
+.globl sym_2_1421
+sym_2_1421: la $2, sym_2_1421
+.globl sym_2_1422
+sym_2_1422: la $2, sym_2_1422
+.globl sym_2_1423
+sym_2_1423: la $2, sym_2_1423
+.globl sym_2_1424
+sym_2_1424: la $2, sym_2_1424
+.globl sym_2_1425
+sym_2_1425: la $2, sym_2_1425
+.globl sym_2_1426
+sym_2_1426: la $2, sym_2_1426
+.globl sym_2_1427
+sym_2_1427: la $2, sym_2_1427
+.globl sym_2_1428
+sym_2_1428: la $2, sym_2_1428
+.globl sym_2_1429
+sym_2_1429: la $2, sym_2_1429
+.globl sym_2_1430
+sym_2_1430: la $2, sym_2_1430
+.globl sym_2_1431
+sym_2_1431: la $2, sym_2_1431
+.globl sym_2_1432
+sym_2_1432: la $2, sym_2_1432
+.globl sym_2_1433
+sym_2_1433: la $2, sym_2_1433
+.globl sym_2_1434
+sym_2_1434: la $2, sym_2_1434
+.globl sym_2_1435
+sym_2_1435: la $2, sym_2_1435
+.globl sym_2_1436
+sym_2_1436: la $2, sym_2_1436
+.globl sym_2_1437
+sym_2_1437: la $2, sym_2_1437
+.globl sym_2_1438
+sym_2_1438: la $2, sym_2_1438
+.globl sym_2_1439
+sym_2_1439: la $2, sym_2_1439
+.globl sym_2_1440
+sym_2_1440: la $2, sym_2_1440
+.globl sym_2_1441
+sym_2_1441: la $2, sym_2_1441
+.globl sym_2_1442
+sym_2_1442: la $2, sym_2_1442
+.globl sym_2_1443
+sym_2_1443: la $2, sym_2_1443
+.globl sym_2_1444
+sym_2_1444: la $2, sym_2_1444
+.globl sym_2_1445
+sym_2_1445: la $2, sym_2_1445
+.globl sym_2_1446
+sym_2_1446: la $2, sym_2_1446
+.globl sym_2_1447
+sym_2_1447: la $2, sym_2_1447
+.globl sym_2_1448
+sym_2_1448: la $2, sym_2_1448
+.globl sym_2_1449
+sym_2_1449: la $2, sym_2_1449
+.globl sym_2_1450
+sym_2_1450: la $2, sym_2_1450
+.globl sym_2_1451
+sym_2_1451: la $2, sym_2_1451
+.globl sym_2_1452
+sym_2_1452: la $2, sym_2_1452
+.globl sym_2_1453
+sym_2_1453: la $2, sym_2_1453
+.globl sym_2_1454
+sym_2_1454: la $2, sym_2_1454
+.globl sym_2_1455
+sym_2_1455: la $2, sym_2_1455
+.globl sym_2_1456
+sym_2_1456: la $2, sym_2_1456
+.globl sym_2_1457
+sym_2_1457: la $2, sym_2_1457
+.globl sym_2_1458
+sym_2_1458: la $2, sym_2_1458
+.globl sym_2_1459
+sym_2_1459: la $2, sym_2_1459
+.globl sym_2_1460
+sym_2_1460: la $2, sym_2_1460
+.globl sym_2_1461
+sym_2_1461: la $2, sym_2_1461
+.globl sym_2_1462
+sym_2_1462: la $2, sym_2_1462
+.globl sym_2_1463
+sym_2_1463: la $2, sym_2_1463
+.globl sym_2_1464
+sym_2_1464: la $2, sym_2_1464
+.globl sym_2_1465
+sym_2_1465: la $2, sym_2_1465
+.globl sym_2_1466
+sym_2_1466: la $2, sym_2_1466
+.globl sym_2_1467
+sym_2_1467: la $2, sym_2_1467
+.globl sym_2_1468
+sym_2_1468: la $2, sym_2_1468
+.globl sym_2_1469
+sym_2_1469: la $2, sym_2_1469
+.globl sym_2_1470
+sym_2_1470: la $2, sym_2_1470
+.globl sym_2_1471
+sym_2_1471: la $2, sym_2_1471
+.globl sym_2_1472
+sym_2_1472: la $2, sym_2_1472
+.globl sym_2_1473
+sym_2_1473: la $2, sym_2_1473
+.globl sym_2_1474
+sym_2_1474: la $2, sym_2_1474
+.globl sym_2_1475
+sym_2_1475: la $2, sym_2_1475
+.globl sym_2_1476
+sym_2_1476: la $2, sym_2_1476
+.globl sym_2_1477
+sym_2_1477: la $2, sym_2_1477
+.globl sym_2_1478
+sym_2_1478: la $2, sym_2_1478
+.globl sym_2_1479
+sym_2_1479: la $2, sym_2_1479
+.globl sym_2_1480
+sym_2_1480: la $2, sym_2_1480
+.globl sym_2_1481
+sym_2_1481: la $2, sym_2_1481
+.globl sym_2_1482
+sym_2_1482: la $2, sym_2_1482
+.globl sym_2_1483
+sym_2_1483: la $2, sym_2_1483
+.globl sym_2_1484
+sym_2_1484: la $2, sym_2_1484
+.globl sym_2_1485
+sym_2_1485: la $2, sym_2_1485
+.globl sym_2_1486
+sym_2_1486: la $2, sym_2_1486
+.globl sym_2_1487
+sym_2_1487: la $2, sym_2_1487
+.globl sym_2_1488
+sym_2_1488: la $2, sym_2_1488
+.globl sym_2_1489
+sym_2_1489: la $2, sym_2_1489
+.globl sym_2_1490
+sym_2_1490: la $2, sym_2_1490
+.globl sym_2_1491
+sym_2_1491: la $2, sym_2_1491
+.globl sym_2_1492
+sym_2_1492: la $2, sym_2_1492
+.globl sym_2_1493
+sym_2_1493: la $2, sym_2_1493
+.globl sym_2_1494
+sym_2_1494: la $2, sym_2_1494
+.globl sym_2_1495
+sym_2_1495: la $2, sym_2_1495
+.globl sym_2_1496
+sym_2_1496: la $2, sym_2_1496
+.globl sym_2_1497
+sym_2_1497: la $2, sym_2_1497
+.globl sym_2_1498
+sym_2_1498: la $2, sym_2_1498
+.globl sym_2_1499
+sym_2_1499: la $2, sym_2_1499
+.globl sym_2_1500
+sym_2_1500: la $2, sym_2_1500
+.globl sym_2_1501
+sym_2_1501: la $2, sym_2_1501
+.globl sym_2_1502
+sym_2_1502: la $2, sym_2_1502
+.globl sym_2_1503
+sym_2_1503: la $2, sym_2_1503
+.globl sym_2_1504
+sym_2_1504: la $2, sym_2_1504
+.globl sym_2_1505
+sym_2_1505: la $2, sym_2_1505
+.globl sym_2_1506
+sym_2_1506: la $2, sym_2_1506
+.globl sym_2_1507
+sym_2_1507: la $2, sym_2_1507
+.globl sym_2_1508
+sym_2_1508: la $2, sym_2_1508
+.globl sym_2_1509
+sym_2_1509: la $2, sym_2_1509
+.globl sym_2_1510
+sym_2_1510: la $2, sym_2_1510
+.globl sym_2_1511
+sym_2_1511: la $2, sym_2_1511
+.globl sym_2_1512
+sym_2_1512: la $2, sym_2_1512
+.globl sym_2_1513
+sym_2_1513: la $2, sym_2_1513
+.globl sym_2_1514
+sym_2_1514: la $2, sym_2_1514
+.globl sym_2_1515
+sym_2_1515: la $2, sym_2_1515
+.globl sym_2_1516
+sym_2_1516: la $2, sym_2_1516
+.globl sym_2_1517
+sym_2_1517: la $2, sym_2_1517
+.globl sym_2_1518
+sym_2_1518: la $2, sym_2_1518
+.globl sym_2_1519
+sym_2_1519: la $2, sym_2_1519
+.globl sym_2_1520
+sym_2_1520: la $2, sym_2_1520
+.globl sym_2_1521
+sym_2_1521: la $2, sym_2_1521
+.globl sym_2_1522
+sym_2_1522: la $2, sym_2_1522
+.globl sym_2_1523
+sym_2_1523: la $2, sym_2_1523
+.globl sym_2_1524
+sym_2_1524: la $2, sym_2_1524
+.globl sym_2_1525
+sym_2_1525: la $2, sym_2_1525
+.globl sym_2_1526
+sym_2_1526: la $2, sym_2_1526
+.globl sym_2_1527
+sym_2_1527: la $2, sym_2_1527
+.globl sym_2_1528
+sym_2_1528: la $2, sym_2_1528
+.globl sym_2_1529
+sym_2_1529: la $2, sym_2_1529
+.globl sym_2_1530
+sym_2_1530: la $2, sym_2_1530
+.globl sym_2_1531
+sym_2_1531: la $2, sym_2_1531
+.globl sym_2_1532
+sym_2_1532: la $2, sym_2_1532
+.globl sym_2_1533
+sym_2_1533: la $2, sym_2_1533
+.globl sym_2_1534
+sym_2_1534: la $2, sym_2_1534
+.globl sym_2_1535
+sym_2_1535: la $2, sym_2_1535
+.globl sym_2_1536
+sym_2_1536: la $2, sym_2_1536
+.globl sym_2_1537
+sym_2_1537: la $2, sym_2_1537
+.globl sym_2_1538
+sym_2_1538: la $2, sym_2_1538
+.globl sym_2_1539
+sym_2_1539: la $2, sym_2_1539
+.globl sym_2_1540
+sym_2_1540: la $2, sym_2_1540
+.globl sym_2_1541
+sym_2_1541: la $2, sym_2_1541
+.globl sym_2_1542
+sym_2_1542: la $2, sym_2_1542
+.globl sym_2_1543
+sym_2_1543: la $2, sym_2_1543
+.globl sym_2_1544
+sym_2_1544: la $2, sym_2_1544
+.globl sym_2_1545
+sym_2_1545: la $2, sym_2_1545
+.globl sym_2_1546
+sym_2_1546: la $2, sym_2_1546
+.globl sym_2_1547
+sym_2_1547: la $2, sym_2_1547
+.globl sym_2_1548
+sym_2_1548: la $2, sym_2_1548
+.globl sym_2_1549
+sym_2_1549: la $2, sym_2_1549
+.globl sym_2_1550
+sym_2_1550: la $2, sym_2_1550
+.globl sym_2_1551
+sym_2_1551: la $2, sym_2_1551
+.globl sym_2_1552
+sym_2_1552: la $2, sym_2_1552
+.globl sym_2_1553
+sym_2_1553: la $2, sym_2_1553
+.globl sym_2_1554
+sym_2_1554: la $2, sym_2_1554
+.globl sym_2_1555
+sym_2_1555: la $2, sym_2_1555
+.globl sym_2_1556
+sym_2_1556: la $2, sym_2_1556
+.globl sym_2_1557
+sym_2_1557: la $2, sym_2_1557
+.globl sym_2_1558
+sym_2_1558: la $2, sym_2_1558
+.globl sym_2_1559
+sym_2_1559: la $2, sym_2_1559
+.globl sym_2_1560
+sym_2_1560: la $2, sym_2_1560
+.globl sym_2_1561
+sym_2_1561: la $2, sym_2_1561
+.globl sym_2_1562
+sym_2_1562: la $2, sym_2_1562
+.globl sym_2_1563
+sym_2_1563: la $2, sym_2_1563
+.globl sym_2_1564
+sym_2_1564: la $2, sym_2_1564
+.globl sym_2_1565
+sym_2_1565: la $2, sym_2_1565
+.globl sym_2_1566
+sym_2_1566: la $2, sym_2_1566
+.globl sym_2_1567
+sym_2_1567: la $2, sym_2_1567
+.globl sym_2_1568
+sym_2_1568: la $2, sym_2_1568
+.globl sym_2_1569
+sym_2_1569: la $2, sym_2_1569
+.globl sym_2_1570
+sym_2_1570: la $2, sym_2_1570
+.globl sym_2_1571
+sym_2_1571: la $2, sym_2_1571
+.globl sym_2_1572
+sym_2_1572: la $2, sym_2_1572
+.globl sym_2_1573
+sym_2_1573: la $2, sym_2_1573
+.globl sym_2_1574
+sym_2_1574: la $2, sym_2_1574
+.globl sym_2_1575
+sym_2_1575: la $2, sym_2_1575
+.globl sym_2_1576
+sym_2_1576: la $2, sym_2_1576
+.globl sym_2_1577
+sym_2_1577: la $2, sym_2_1577
+.globl sym_2_1578
+sym_2_1578: la $2, sym_2_1578
+.globl sym_2_1579
+sym_2_1579: la $2, sym_2_1579
+.globl sym_2_1580
+sym_2_1580: la $2, sym_2_1580
+.globl sym_2_1581
+sym_2_1581: la $2, sym_2_1581
+.globl sym_2_1582
+sym_2_1582: la $2, sym_2_1582
+.globl sym_2_1583
+sym_2_1583: la $2, sym_2_1583
+.globl sym_2_1584
+sym_2_1584: la $2, sym_2_1584
+.globl sym_2_1585
+sym_2_1585: la $2, sym_2_1585
+.globl sym_2_1586
+sym_2_1586: la $2, sym_2_1586
+.globl sym_2_1587
+sym_2_1587: la $2, sym_2_1587
+.globl sym_2_1588
+sym_2_1588: la $2, sym_2_1588
+.globl sym_2_1589
+sym_2_1589: la $2, sym_2_1589
+.globl sym_2_1590
+sym_2_1590: la $2, sym_2_1590
+.globl sym_2_1591
+sym_2_1591: la $2, sym_2_1591
+.globl sym_2_1592
+sym_2_1592: la $2, sym_2_1592
+.globl sym_2_1593
+sym_2_1593: la $2, sym_2_1593
+.globl sym_2_1594
+sym_2_1594: la $2, sym_2_1594
+.globl sym_2_1595
+sym_2_1595: la $2, sym_2_1595
+.globl sym_2_1596
+sym_2_1596: la $2, sym_2_1596
+.globl sym_2_1597
+sym_2_1597: la $2, sym_2_1597
+.globl sym_2_1598
+sym_2_1598: la $2, sym_2_1598
+.globl sym_2_1599
+sym_2_1599: la $2, sym_2_1599
+.globl sym_2_1600
+sym_2_1600: la $2, sym_2_1600
+.globl sym_2_1601
+sym_2_1601: la $2, sym_2_1601
+.globl sym_2_1602
+sym_2_1602: la $2, sym_2_1602
+.globl sym_2_1603
+sym_2_1603: la $2, sym_2_1603
+.globl sym_2_1604
+sym_2_1604: la $2, sym_2_1604
+.globl sym_2_1605
+sym_2_1605: la $2, sym_2_1605
+.globl sym_2_1606
+sym_2_1606: la $2, sym_2_1606
+.globl sym_2_1607
+sym_2_1607: la $2, sym_2_1607
+.globl sym_2_1608
+sym_2_1608: la $2, sym_2_1608
+.globl sym_2_1609
+sym_2_1609: la $2, sym_2_1609
+.globl sym_2_1610
+sym_2_1610: la $2, sym_2_1610
+.globl sym_2_1611
+sym_2_1611: la $2, sym_2_1611
+.globl sym_2_1612
+sym_2_1612: la $2, sym_2_1612
+.globl sym_2_1613
+sym_2_1613: la $2, sym_2_1613
+.globl sym_2_1614
+sym_2_1614: la $2, sym_2_1614
+.globl sym_2_1615
+sym_2_1615: la $2, sym_2_1615
+.globl sym_2_1616
+sym_2_1616: la $2, sym_2_1616
+.globl sym_2_1617
+sym_2_1617: la $2, sym_2_1617
+.globl sym_2_1618
+sym_2_1618: la $2, sym_2_1618
+.globl sym_2_1619
+sym_2_1619: la $2, sym_2_1619
+.globl sym_2_1620
+sym_2_1620: la $2, sym_2_1620
+.globl sym_2_1621
+sym_2_1621: la $2, sym_2_1621
+.globl sym_2_1622
+sym_2_1622: la $2, sym_2_1622
+.globl sym_2_1623
+sym_2_1623: la $2, sym_2_1623
+.globl sym_2_1624
+sym_2_1624: la $2, sym_2_1624
+.globl sym_2_1625
+sym_2_1625: la $2, sym_2_1625
+.globl sym_2_1626
+sym_2_1626: la $2, sym_2_1626
+.globl sym_2_1627
+sym_2_1627: la $2, sym_2_1627
+.globl sym_2_1628
+sym_2_1628: la $2, sym_2_1628
+.globl sym_2_1629
+sym_2_1629: la $2, sym_2_1629
+.globl sym_2_1630
+sym_2_1630: la $2, sym_2_1630
+.globl sym_2_1631
+sym_2_1631: la $2, sym_2_1631
+.globl sym_2_1632
+sym_2_1632: la $2, sym_2_1632
+.globl sym_2_1633
+sym_2_1633: la $2, sym_2_1633
+.globl sym_2_1634
+sym_2_1634: la $2, sym_2_1634
+.globl sym_2_1635
+sym_2_1635: la $2, sym_2_1635
+.globl sym_2_1636
+sym_2_1636: la $2, sym_2_1636
+.globl sym_2_1637
+sym_2_1637: la $2, sym_2_1637
+.globl sym_2_1638
+sym_2_1638: la $2, sym_2_1638
+.globl sym_2_1639
+sym_2_1639: la $2, sym_2_1639
+.globl sym_2_1640
+sym_2_1640: la $2, sym_2_1640
+.globl sym_2_1641
+sym_2_1641: la $2, sym_2_1641
+.globl sym_2_1642
+sym_2_1642: la $2, sym_2_1642
+.globl sym_2_1643
+sym_2_1643: la $2, sym_2_1643
+.globl sym_2_1644
+sym_2_1644: la $2, sym_2_1644
+.globl sym_2_1645
+sym_2_1645: la $2, sym_2_1645
+.globl sym_2_1646
+sym_2_1646: la $2, sym_2_1646
+.globl sym_2_1647
+sym_2_1647: la $2, sym_2_1647
+.globl sym_2_1648
+sym_2_1648: la $2, sym_2_1648
+.globl sym_2_1649
+sym_2_1649: la $2, sym_2_1649
+.globl sym_2_1650
+sym_2_1650: la $2, sym_2_1650
+.globl sym_2_1651
+sym_2_1651: la $2, sym_2_1651
+.globl sym_2_1652
+sym_2_1652: la $2, sym_2_1652
+.globl sym_2_1653
+sym_2_1653: la $2, sym_2_1653
+.globl sym_2_1654
+sym_2_1654: la $2, sym_2_1654
+.globl sym_2_1655
+sym_2_1655: la $2, sym_2_1655
+.globl sym_2_1656
+sym_2_1656: la $2, sym_2_1656
+.globl sym_2_1657
+sym_2_1657: la $2, sym_2_1657
+.globl sym_2_1658
+sym_2_1658: la $2, sym_2_1658
+.globl sym_2_1659
+sym_2_1659: la $2, sym_2_1659
+.globl sym_2_1660
+sym_2_1660: la $2, sym_2_1660
+.globl sym_2_1661
+sym_2_1661: la $2, sym_2_1661
+.globl sym_2_1662
+sym_2_1662: la $2, sym_2_1662
+.globl sym_2_1663
+sym_2_1663: la $2, sym_2_1663
+.globl sym_2_1664
+sym_2_1664: la $2, sym_2_1664
+.globl sym_2_1665
+sym_2_1665: la $2, sym_2_1665
+.globl sym_2_1666
+sym_2_1666: la $2, sym_2_1666
+.globl sym_2_1667
+sym_2_1667: la $2, sym_2_1667
+.globl sym_2_1668
+sym_2_1668: la $2, sym_2_1668
+.globl sym_2_1669
+sym_2_1669: la $2, sym_2_1669
+.globl sym_2_1670
+sym_2_1670: la $2, sym_2_1670
+.globl sym_2_1671
+sym_2_1671: la $2, sym_2_1671
+.globl sym_2_1672
+sym_2_1672: la $2, sym_2_1672
+.globl sym_2_1673
+sym_2_1673: la $2, sym_2_1673
+.globl sym_2_1674
+sym_2_1674: la $2, sym_2_1674
+.globl sym_2_1675
+sym_2_1675: la $2, sym_2_1675
+.globl sym_2_1676
+sym_2_1676: la $2, sym_2_1676
+.globl sym_2_1677
+sym_2_1677: la $2, sym_2_1677
+.globl sym_2_1678
+sym_2_1678: la $2, sym_2_1678
+.globl sym_2_1679
+sym_2_1679: la $2, sym_2_1679
+.globl sym_2_1680
+sym_2_1680: la $2, sym_2_1680
+.globl sym_2_1681
+sym_2_1681: la $2, sym_2_1681
+.globl sym_2_1682
+sym_2_1682: la $2, sym_2_1682
+.globl sym_2_1683
+sym_2_1683: la $2, sym_2_1683
+.globl sym_2_1684
+sym_2_1684: la $2, sym_2_1684
+.globl sym_2_1685
+sym_2_1685: la $2, sym_2_1685
+.globl sym_2_1686
+sym_2_1686: la $2, sym_2_1686
+.globl sym_2_1687
+sym_2_1687: la $2, sym_2_1687
+.globl sym_2_1688
+sym_2_1688: la $2, sym_2_1688
+.globl sym_2_1689
+sym_2_1689: la $2, sym_2_1689
+.globl sym_2_1690
+sym_2_1690: la $2, sym_2_1690
+.globl sym_2_1691
+sym_2_1691: la $2, sym_2_1691
+.globl sym_2_1692
+sym_2_1692: la $2, sym_2_1692
+.globl sym_2_1693
+sym_2_1693: la $2, sym_2_1693
+.globl sym_2_1694
+sym_2_1694: la $2, sym_2_1694
+.globl sym_2_1695
+sym_2_1695: la $2, sym_2_1695
+.globl sym_2_1696
+sym_2_1696: la $2, sym_2_1696
+.globl sym_2_1697
+sym_2_1697: la $2, sym_2_1697
+.globl sym_2_1698
+sym_2_1698: la $2, sym_2_1698
+.globl sym_2_1699
+sym_2_1699: la $2, sym_2_1699
+.globl sym_2_1700
+sym_2_1700: la $2, sym_2_1700
+.globl sym_2_1701
+sym_2_1701: la $2, sym_2_1701
+.globl sym_2_1702
+sym_2_1702: la $2, sym_2_1702
+.globl sym_2_1703
+sym_2_1703: la $2, sym_2_1703
+.globl sym_2_1704
+sym_2_1704: la $2, sym_2_1704
+.globl sym_2_1705
+sym_2_1705: la $2, sym_2_1705
+.globl sym_2_1706
+sym_2_1706: la $2, sym_2_1706
+.globl sym_2_1707
+sym_2_1707: la $2, sym_2_1707
+.globl sym_2_1708
+sym_2_1708: la $2, sym_2_1708
+.globl sym_2_1709
+sym_2_1709: la $2, sym_2_1709
+.globl sym_2_1710
+sym_2_1710: la $2, sym_2_1710
+.globl sym_2_1711
+sym_2_1711: la $2, sym_2_1711
+.globl sym_2_1712
+sym_2_1712: la $2, sym_2_1712
+.globl sym_2_1713
+sym_2_1713: la $2, sym_2_1713
+.globl sym_2_1714
+sym_2_1714: la $2, sym_2_1714
+.globl sym_2_1715
+sym_2_1715: la $2, sym_2_1715
+.globl sym_2_1716
+sym_2_1716: la $2, sym_2_1716
+.globl sym_2_1717
+sym_2_1717: la $2, sym_2_1717
+.globl sym_2_1718
+sym_2_1718: la $2, sym_2_1718
+.globl sym_2_1719
+sym_2_1719: la $2, sym_2_1719
+.globl sym_2_1720
+sym_2_1720: la $2, sym_2_1720
+.globl sym_2_1721
+sym_2_1721: la $2, sym_2_1721
+.globl sym_2_1722
+sym_2_1722: la $2, sym_2_1722
+.globl sym_2_1723
+sym_2_1723: la $2, sym_2_1723
+.globl sym_2_1724
+sym_2_1724: la $2, sym_2_1724
+.globl sym_2_1725
+sym_2_1725: la $2, sym_2_1725
+.globl sym_2_1726
+sym_2_1726: la $2, sym_2_1726
+.globl sym_2_1727
+sym_2_1727: la $2, sym_2_1727
+.globl sym_2_1728
+sym_2_1728: la $2, sym_2_1728
+.globl sym_2_1729
+sym_2_1729: la $2, sym_2_1729
+.globl sym_2_1730
+sym_2_1730: la $2, sym_2_1730
+.globl sym_2_1731
+sym_2_1731: la $2, sym_2_1731
+.globl sym_2_1732
+sym_2_1732: la $2, sym_2_1732
+.globl sym_2_1733
+sym_2_1733: la $2, sym_2_1733
+.globl sym_2_1734
+sym_2_1734: la $2, sym_2_1734
+.globl sym_2_1735
+sym_2_1735: la $2, sym_2_1735
+.globl sym_2_1736
+sym_2_1736: la $2, sym_2_1736
+.globl sym_2_1737
+sym_2_1737: la $2, sym_2_1737
+.globl sym_2_1738
+sym_2_1738: la $2, sym_2_1738
+.globl sym_2_1739
+sym_2_1739: la $2, sym_2_1739
+.globl sym_2_1740
+sym_2_1740: la $2, sym_2_1740
+.globl sym_2_1741
+sym_2_1741: la $2, sym_2_1741
+.globl sym_2_1742
+sym_2_1742: la $2, sym_2_1742
+.globl sym_2_1743
+sym_2_1743: la $2, sym_2_1743
+.globl sym_2_1744
+sym_2_1744: la $2, sym_2_1744
+.globl sym_2_1745
+sym_2_1745: la $2, sym_2_1745
+.globl sym_2_1746
+sym_2_1746: la $2, sym_2_1746
+.globl sym_2_1747
+sym_2_1747: la $2, sym_2_1747
+.globl sym_2_1748
+sym_2_1748: la $2, sym_2_1748
+.globl sym_2_1749
+sym_2_1749: la $2, sym_2_1749
+.globl sym_2_1750
+sym_2_1750: la $2, sym_2_1750
+.globl sym_2_1751
+sym_2_1751: la $2, sym_2_1751
+.globl sym_2_1752
+sym_2_1752: la $2, sym_2_1752
+.globl sym_2_1753
+sym_2_1753: la $2, sym_2_1753
+.globl sym_2_1754
+sym_2_1754: la $2, sym_2_1754
+.globl sym_2_1755
+sym_2_1755: la $2, sym_2_1755
+.globl sym_2_1756
+sym_2_1756: la $2, sym_2_1756
+.globl sym_2_1757
+sym_2_1757: la $2, sym_2_1757
+.globl sym_2_1758
+sym_2_1758: la $2, sym_2_1758
+.globl sym_2_1759
+sym_2_1759: la $2, sym_2_1759
+.globl sym_2_1760
+sym_2_1760: la $2, sym_2_1760
+.globl sym_2_1761
+sym_2_1761: la $2, sym_2_1761
+.globl sym_2_1762
+sym_2_1762: la $2, sym_2_1762
+.globl sym_2_1763
+sym_2_1763: la $2, sym_2_1763
+.globl sym_2_1764
+sym_2_1764: la $2, sym_2_1764
+.globl sym_2_1765
+sym_2_1765: la $2, sym_2_1765
+.globl sym_2_1766
+sym_2_1766: la $2, sym_2_1766
+.globl sym_2_1767
+sym_2_1767: la $2, sym_2_1767
+.globl sym_2_1768
+sym_2_1768: la $2, sym_2_1768
+.globl sym_2_1769
+sym_2_1769: la $2, sym_2_1769
+.globl sym_2_1770
+sym_2_1770: la $2, sym_2_1770
+.globl sym_2_1771
+sym_2_1771: la $2, sym_2_1771
+.globl sym_2_1772
+sym_2_1772: la $2, sym_2_1772
+.globl sym_2_1773
+sym_2_1773: la $2, sym_2_1773
+.globl sym_2_1774
+sym_2_1774: la $2, sym_2_1774
+.globl sym_2_1775
+sym_2_1775: la $2, sym_2_1775
+.globl sym_2_1776
+sym_2_1776: la $2, sym_2_1776
+.globl sym_2_1777
+sym_2_1777: la $2, sym_2_1777
+.globl sym_2_1778
+sym_2_1778: la $2, sym_2_1778
+.globl sym_2_1779
+sym_2_1779: la $2, sym_2_1779
+.globl sym_2_1780
+sym_2_1780: la $2, sym_2_1780
+.globl sym_2_1781
+sym_2_1781: la $2, sym_2_1781
+.globl sym_2_1782
+sym_2_1782: la $2, sym_2_1782
+.globl sym_2_1783
+sym_2_1783: la $2, sym_2_1783
+.globl sym_2_1784
+sym_2_1784: la $2, sym_2_1784
+.globl sym_2_1785
+sym_2_1785: la $2, sym_2_1785
+.globl sym_2_1786
+sym_2_1786: la $2, sym_2_1786
+.globl sym_2_1787
+sym_2_1787: la $2, sym_2_1787
+.globl sym_2_1788
+sym_2_1788: la $2, sym_2_1788
+.globl sym_2_1789
+sym_2_1789: la $2, sym_2_1789
+.globl sym_2_1790
+sym_2_1790: la $2, sym_2_1790
+.globl sym_2_1791
+sym_2_1791: la $2, sym_2_1791
+.globl sym_2_1792
+sym_2_1792: la $2, sym_2_1792
+.globl sym_2_1793
+sym_2_1793: la $2, sym_2_1793
+.globl sym_2_1794
+sym_2_1794: la $2, sym_2_1794
+.globl sym_2_1795
+sym_2_1795: la $2, sym_2_1795
+.globl sym_2_1796
+sym_2_1796: la $2, sym_2_1796
+.globl sym_2_1797
+sym_2_1797: la $2, sym_2_1797
+.globl sym_2_1798
+sym_2_1798: la $2, sym_2_1798
+.globl sym_2_1799
+sym_2_1799: la $2, sym_2_1799
+.globl sym_2_1800
+sym_2_1800: la $2, sym_2_1800
+.globl sym_2_1801
+sym_2_1801: la $2, sym_2_1801
+.globl sym_2_1802
+sym_2_1802: la $2, sym_2_1802
+.globl sym_2_1803
+sym_2_1803: la $2, sym_2_1803
+.globl sym_2_1804
+sym_2_1804: la $2, sym_2_1804
+.globl sym_2_1805
+sym_2_1805: la $2, sym_2_1805
+.globl sym_2_1806
+sym_2_1806: la $2, sym_2_1806
+.globl sym_2_1807
+sym_2_1807: la $2, sym_2_1807
+.globl sym_2_1808
+sym_2_1808: la $2, sym_2_1808
+.globl sym_2_1809
+sym_2_1809: la $2, sym_2_1809
+.globl sym_2_1810
+sym_2_1810: la $2, sym_2_1810
+.globl sym_2_1811
+sym_2_1811: la $2, sym_2_1811
+.globl sym_2_1812
+sym_2_1812: la $2, sym_2_1812
+.globl sym_2_1813
+sym_2_1813: la $2, sym_2_1813
+.globl sym_2_1814
+sym_2_1814: la $2, sym_2_1814
+.globl sym_2_1815
+sym_2_1815: la $2, sym_2_1815
+.globl sym_2_1816
+sym_2_1816: la $2, sym_2_1816
+.globl sym_2_1817
+sym_2_1817: la $2, sym_2_1817
+.globl sym_2_1818
+sym_2_1818: la $2, sym_2_1818
+.globl sym_2_1819
+sym_2_1819: la $2, sym_2_1819
+.globl sym_2_1820
+sym_2_1820: la $2, sym_2_1820
+.globl sym_2_1821
+sym_2_1821: la $2, sym_2_1821
+.globl sym_2_1822
+sym_2_1822: la $2, sym_2_1822
+.globl sym_2_1823
+sym_2_1823: la $2, sym_2_1823
+.globl sym_2_1824
+sym_2_1824: la $2, sym_2_1824
+.globl sym_2_1825
+sym_2_1825: la $2, sym_2_1825
+.globl sym_2_1826
+sym_2_1826: la $2, sym_2_1826
+.globl sym_2_1827
+sym_2_1827: la $2, sym_2_1827
+.globl sym_2_1828
+sym_2_1828: la $2, sym_2_1828
+.globl sym_2_1829
+sym_2_1829: la $2, sym_2_1829
+.globl sym_2_1830
+sym_2_1830: la $2, sym_2_1830
+.globl sym_2_1831
+sym_2_1831: la $2, sym_2_1831
+.globl sym_2_1832
+sym_2_1832: la $2, sym_2_1832
+.globl sym_2_1833
+sym_2_1833: la $2, sym_2_1833
+.globl sym_2_1834
+sym_2_1834: la $2, sym_2_1834
+.globl sym_2_1835
+sym_2_1835: la $2, sym_2_1835
+.globl sym_2_1836
+sym_2_1836: la $2, sym_2_1836
+.globl sym_2_1837
+sym_2_1837: la $2, sym_2_1837
+.globl sym_2_1838
+sym_2_1838: la $2, sym_2_1838
+.globl sym_2_1839
+sym_2_1839: la $2, sym_2_1839
+.globl sym_2_1840
+sym_2_1840: la $2, sym_2_1840
+.globl sym_2_1841
+sym_2_1841: la $2, sym_2_1841
+.globl sym_2_1842
+sym_2_1842: la $2, sym_2_1842
+.globl sym_2_1843
+sym_2_1843: la $2, sym_2_1843
+.globl sym_2_1844
+sym_2_1844: la $2, sym_2_1844
+.globl sym_2_1845
+sym_2_1845: la $2, sym_2_1845
+.globl sym_2_1846
+sym_2_1846: la $2, sym_2_1846
+.globl sym_2_1847
+sym_2_1847: la $2, sym_2_1847
+.globl sym_2_1848
+sym_2_1848: la $2, sym_2_1848
+.globl sym_2_1849
+sym_2_1849: la $2, sym_2_1849
+.globl sym_2_1850
+sym_2_1850: la $2, sym_2_1850
+.globl sym_2_1851
+sym_2_1851: la $2, sym_2_1851
+.globl sym_2_1852
+sym_2_1852: la $2, sym_2_1852
+.globl sym_2_1853
+sym_2_1853: la $2, sym_2_1853
+.globl sym_2_1854
+sym_2_1854: la $2, sym_2_1854
+.globl sym_2_1855
+sym_2_1855: la $2, sym_2_1855
+.globl sym_2_1856
+sym_2_1856: la $2, sym_2_1856
+.globl sym_2_1857
+sym_2_1857: la $2, sym_2_1857
+.globl sym_2_1858
+sym_2_1858: la $2, sym_2_1858
+.globl sym_2_1859
+sym_2_1859: la $2, sym_2_1859
+.globl sym_2_1860
+sym_2_1860: la $2, sym_2_1860
+.globl sym_2_1861
+sym_2_1861: la $2, sym_2_1861
+.globl sym_2_1862
+sym_2_1862: la $2, sym_2_1862
+.globl sym_2_1863
+sym_2_1863: la $2, sym_2_1863
+.globl sym_2_1864
+sym_2_1864: la $2, sym_2_1864
+.globl sym_2_1865
+sym_2_1865: la $2, sym_2_1865
+.globl sym_2_1866
+sym_2_1866: la $2, sym_2_1866
+.globl sym_2_1867
+sym_2_1867: la $2, sym_2_1867
+.globl sym_2_1868
+sym_2_1868: la $2, sym_2_1868
+.globl sym_2_1869
+sym_2_1869: la $2, sym_2_1869
+.globl sym_2_1870
+sym_2_1870: la $2, sym_2_1870
+.globl sym_2_1871
+sym_2_1871: la $2, sym_2_1871
+.globl sym_2_1872
+sym_2_1872: la $2, sym_2_1872
+.globl sym_2_1873
+sym_2_1873: la $2, sym_2_1873
+.globl sym_2_1874
+sym_2_1874: la $2, sym_2_1874
+.globl sym_2_1875
+sym_2_1875: la $2, sym_2_1875
+.globl sym_2_1876
+sym_2_1876: la $2, sym_2_1876
+.globl sym_2_1877
+sym_2_1877: la $2, sym_2_1877
+.globl sym_2_1878
+sym_2_1878: la $2, sym_2_1878
+.globl sym_2_1879
+sym_2_1879: la $2, sym_2_1879
+.globl sym_2_1880
+sym_2_1880: la $2, sym_2_1880
+.globl sym_2_1881
+sym_2_1881: la $2, sym_2_1881
+.globl sym_2_1882
+sym_2_1882: la $2, sym_2_1882
+.globl sym_2_1883
+sym_2_1883: la $2, sym_2_1883
+.globl sym_2_1884
+sym_2_1884: la $2, sym_2_1884
+.globl sym_2_1885
+sym_2_1885: la $2, sym_2_1885
+.globl sym_2_1886
+sym_2_1886: la $2, sym_2_1886
+.globl sym_2_1887
+sym_2_1887: la $2, sym_2_1887
+.globl sym_2_1888
+sym_2_1888: la $2, sym_2_1888
+.globl sym_2_1889
+sym_2_1889: la $2, sym_2_1889
+.globl sym_2_1890
+sym_2_1890: la $2, sym_2_1890
+.globl sym_2_1891
+sym_2_1891: la $2, sym_2_1891
+.globl sym_2_1892
+sym_2_1892: la $2, sym_2_1892
+.globl sym_2_1893
+sym_2_1893: la $2, sym_2_1893
+.globl sym_2_1894
+sym_2_1894: la $2, sym_2_1894
+.globl sym_2_1895
+sym_2_1895: la $2, sym_2_1895
+.globl sym_2_1896
+sym_2_1896: la $2, sym_2_1896
+.globl sym_2_1897
+sym_2_1897: la $2, sym_2_1897
+.globl sym_2_1898
+sym_2_1898: la $2, sym_2_1898
+.globl sym_2_1899
+sym_2_1899: la $2, sym_2_1899
+.globl sym_2_1900
+sym_2_1900: la $2, sym_2_1900
+.globl sym_2_1901
+sym_2_1901: la $2, sym_2_1901
+.globl sym_2_1902
+sym_2_1902: la $2, sym_2_1902
+.globl sym_2_1903
+sym_2_1903: la $2, sym_2_1903
+.globl sym_2_1904
+sym_2_1904: la $2, sym_2_1904
+.globl sym_2_1905
+sym_2_1905: la $2, sym_2_1905
+.globl sym_2_1906
+sym_2_1906: la $2, sym_2_1906
+.globl sym_2_1907
+sym_2_1907: la $2, sym_2_1907
+.globl sym_2_1908
+sym_2_1908: la $2, sym_2_1908
+.globl sym_2_1909
+sym_2_1909: la $2, sym_2_1909
+.globl sym_2_1910
+sym_2_1910: la $2, sym_2_1910
+.globl sym_2_1911
+sym_2_1911: la $2, sym_2_1911
+.globl sym_2_1912
+sym_2_1912: la $2, sym_2_1912
+.globl sym_2_1913
+sym_2_1913: la $2, sym_2_1913
+.globl sym_2_1914
+sym_2_1914: la $2, sym_2_1914
+.globl sym_2_1915
+sym_2_1915: la $2, sym_2_1915
+.globl sym_2_1916
+sym_2_1916: la $2, sym_2_1916
+.globl sym_2_1917
+sym_2_1917: la $2, sym_2_1917
+.globl sym_2_1918
+sym_2_1918: la $2, sym_2_1918
+.globl sym_2_1919
+sym_2_1919: la $2, sym_2_1919
+.globl sym_2_1920
+sym_2_1920: la $2, sym_2_1920
+.globl sym_2_1921
+sym_2_1921: la $2, sym_2_1921
+.globl sym_2_1922
+sym_2_1922: la $2, sym_2_1922
+.globl sym_2_1923
+sym_2_1923: la $2, sym_2_1923
+.globl sym_2_1924
+sym_2_1924: la $2, sym_2_1924
+.globl sym_2_1925
+sym_2_1925: la $2, sym_2_1925
+.globl sym_2_1926
+sym_2_1926: la $2, sym_2_1926
+.globl sym_2_1927
+sym_2_1927: la $2, sym_2_1927
+.globl sym_2_1928
+sym_2_1928: la $2, sym_2_1928
+.globl sym_2_1929
+sym_2_1929: la $2, sym_2_1929
+.globl sym_2_1930
+sym_2_1930: la $2, sym_2_1930
+.globl sym_2_1931
+sym_2_1931: la $2, sym_2_1931
+.globl sym_2_1932
+sym_2_1932: la $2, sym_2_1932
+.globl sym_2_1933
+sym_2_1933: la $2, sym_2_1933
+.globl sym_2_1934
+sym_2_1934: la $2, sym_2_1934
+.globl sym_2_1935
+sym_2_1935: la $2, sym_2_1935
+.globl sym_2_1936
+sym_2_1936: la $2, sym_2_1936
+.globl sym_2_1937
+sym_2_1937: la $2, sym_2_1937
+.globl sym_2_1938
+sym_2_1938: la $2, sym_2_1938
+.globl sym_2_1939
+sym_2_1939: la $2, sym_2_1939
+.globl sym_2_1940
+sym_2_1940: la $2, sym_2_1940
+.globl sym_2_1941
+sym_2_1941: la $2, sym_2_1941
+.globl sym_2_1942
+sym_2_1942: la $2, sym_2_1942
+.globl sym_2_1943
+sym_2_1943: la $2, sym_2_1943
+.globl sym_2_1944
+sym_2_1944: la $2, sym_2_1944
+.globl sym_2_1945
+sym_2_1945: la $2, sym_2_1945
+.globl sym_2_1946
+sym_2_1946: la $2, sym_2_1946
+.globl sym_2_1947
+sym_2_1947: la $2, sym_2_1947
+.globl sym_2_1948
+sym_2_1948: la $2, sym_2_1948
+.globl sym_2_1949
+sym_2_1949: la $2, sym_2_1949
+.globl sym_2_1950
+sym_2_1950: la $2, sym_2_1950
+.globl sym_2_1951
+sym_2_1951: la $2, sym_2_1951
+.globl sym_2_1952
+sym_2_1952: la $2, sym_2_1952
+.globl sym_2_1953
+sym_2_1953: la $2, sym_2_1953
+.globl sym_2_1954
+sym_2_1954: la $2, sym_2_1954
+.globl sym_2_1955
+sym_2_1955: la $2, sym_2_1955
+.globl sym_2_1956
+sym_2_1956: la $2, sym_2_1956
+.globl sym_2_1957
+sym_2_1957: la $2, sym_2_1957
+.globl sym_2_1958
+sym_2_1958: la $2, sym_2_1958
+.globl sym_2_1959
+sym_2_1959: la $2, sym_2_1959
+.globl sym_2_1960
+sym_2_1960: la $2, sym_2_1960
+.globl sym_2_1961
+sym_2_1961: la $2, sym_2_1961
+.globl sym_2_1962
+sym_2_1962: la $2, sym_2_1962
+.globl sym_2_1963
+sym_2_1963: la $2, sym_2_1963
+.globl sym_2_1964
+sym_2_1964: la $2, sym_2_1964
+.globl sym_2_1965
+sym_2_1965: la $2, sym_2_1965
+.globl sym_2_1966
+sym_2_1966: la $2, sym_2_1966
+.globl sym_2_1967
+sym_2_1967: la $2, sym_2_1967
+.globl sym_2_1968
+sym_2_1968: la $2, sym_2_1968
+.globl sym_2_1969
+sym_2_1969: la $2, sym_2_1969
+.globl sym_2_1970
+sym_2_1970: la $2, sym_2_1970
+.globl sym_2_1971
+sym_2_1971: la $2, sym_2_1971
+.globl sym_2_1972
+sym_2_1972: la $2, sym_2_1972
+.globl sym_2_1973
+sym_2_1973: la $2, sym_2_1973
+.globl sym_2_1974
+sym_2_1974: la $2, sym_2_1974
+.globl sym_2_1975
+sym_2_1975: la $2, sym_2_1975
+.globl sym_2_1976
+sym_2_1976: la $2, sym_2_1976
+.globl sym_2_1977
+sym_2_1977: la $2, sym_2_1977
+.globl sym_2_1978
+sym_2_1978: la $2, sym_2_1978
+.globl sym_2_1979
+sym_2_1979: la $2, sym_2_1979
+.globl sym_2_1980
+sym_2_1980: la $2, sym_2_1980
+.globl sym_2_1981
+sym_2_1981: la $2, sym_2_1981
+.globl sym_2_1982
+sym_2_1982: la $2, sym_2_1982
+.globl sym_2_1983
+sym_2_1983: la $2, sym_2_1983
+.globl sym_2_1984
+sym_2_1984: la $2, sym_2_1984
+.globl sym_2_1985
+sym_2_1985: la $2, sym_2_1985
+.globl sym_2_1986
+sym_2_1986: la $2, sym_2_1986
+.globl sym_2_1987
+sym_2_1987: la $2, sym_2_1987
+.globl sym_2_1988
+sym_2_1988: la $2, sym_2_1988
+.globl sym_2_1989
+sym_2_1989: la $2, sym_2_1989
+.globl sym_2_1990
+sym_2_1990: la $2, sym_2_1990
+.globl sym_2_1991
+sym_2_1991: la $2, sym_2_1991
+.globl sym_2_1992
+sym_2_1992: la $2, sym_2_1992
+.globl sym_2_1993
+sym_2_1993: la $2, sym_2_1993
+.globl sym_2_1994
+sym_2_1994: la $2, sym_2_1994
+.globl sym_2_1995
+sym_2_1995: la $2, sym_2_1995
+.globl sym_2_1996
+sym_2_1996: la $2, sym_2_1996
+.globl sym_2_1997
+sym_2_1997: la $2, sym_2_1997
+.globl sym_2_1998
+sym_2_1998: la $2, sym_2_1998
+.globl sym_2_1999
+sym_2_1999: la $2, sym_2_1999
+.globl sym_2_2000
+sym_2_2000: la $2, sym_2_2000
+.globl sym_2_2001
+sym_2_2001: la $2, sym_2_2001
+.globl sym_2_2002
+sym_2_2002: la $2, sym_2_2002
+.globl sym_2_2003
+sym_2_2003: la $2, sym_2_2003
+.globl sym_2_2004
+sym_2_2004: la $2, sym_2_2004
+.globl sym_2_2005
+sym_2_2005: la $2, sym_2_2005
+.globl sym_2_2006
+sym_2_2006: la $2, sym_2_2006
+.globl sym_2_2007
+sym_2_2007: la $2, sym_2_2007
+.globl sym_2_2008
+sym_2_2008: la $2, sym_2_2008
+.globl sym_2_2009
+sym_2_2009: la $2, sym_2_2009
+.globl sym_2_2010
+sym_2_2010: la $2, sym_2_2010
+.globl sym_2_2011
+sym_2_2011: la $2, sym_2_2011
+.globl sym_2_2012
+sym_2_2012: la $2, sym_2_2012
+.globl sym_2_2013
+sym_2_2013: la $2, sym_2_2013
+.globl sym_2_2014
+sym_2_2014: la $2, sym_2_2014
+.globl sym_2_2015
+sym_2_2015: la $2, sym_2_2015
+.globl sym_2_2016
+sym_2_2016: la $2, sym_2_2016
+.globl sym_2_2017
+sym_2_2017: la $2, sym_2_2017
+.globl sym_2_2018
+sym_2_2018: la $2, sym_2_2018
+.globl sym_2_2019
+sym_2_2019: la $2, sym_2_2019
+.globl sym_2_2020
+sym_2_2020: la $2, sym_2_2020
+.globl sym_2_2021
+sym_2_2021: la $2, sym_2_2021
+.globl sym_2_2022
+sym_2_2022: la $2, sym_2_2022
+.globl sym_2_2023
+sym_2_2023: la $2, sym_2_2023
+.globl sym_2_2024
+sym_2_2024: la $2, sym_2_2024
+.globl sym_2_2025
+sym_2_2025: la $2, sym_2_2025
+.globl sym_2_2026
+sym_2_2026: la $2, sym_2_2026
+.globl sym_2_2027
+sym_2_2027: la $2, sym_2_2027
+.globl sym_2_2028
+sym_2_2028: la $2, sym_2_2028
+.globl sym_2_2029
+sym_2_2029: la $2, sym_2_2029
+.globl sym_2_2030
+sym_2_2030: la $2, sym_2_2030
+.globl sym_2_2031
+sym_2_2031: la $2, sym_2_2031
+.globl sym_2_2032
+sym_2_2032: la $2, sym_2_2032
+.globl sym_2_2033
+sym_2_2033: la $2, sym_2_2033
+.globl sym_2_2034
+sym_2_2034: la $2, sym_2_2034
+.globl sym_2_2035
+sym_2_2035: la $2, sym_2_2035
+.globl sym_2_2036
+sym_2_2036: la $2, sym_2_2036
+.globl sym_2_2037
+sym_2_2037: la $2, sym_2_2037
+.globl sym_2_2038
+sym_2_2038: la $2, sym_2_2038
+.globl sym_2_2039
+sym_2_2039: la $2, sym_2_2039
+.globl sym_2_2040
+sym_2_2040: la $2, sym_2_2040
+.globl sym_2_2041
+sym_2_2041: la $2, sym_2_2041
+.globl sym_2_2042
+sym_2_2042: la $2, sym_2_2042
+.globl sym_2_2043
+sym_2_2043: la $2, sym_2_2043
+.globl sym_2_2044
+sym_2_2044: la $2, sym_2_2044
+.globl sym_2_2045
+sym_2_2045: la $2, sym_2_2045
+.globl sym_2_2046
+sym_2_2046: la $2, sym_2_2046
+.globl sym_2_2047
+sym_2_2047: la $2, sym_2_2047
+.globl sym_2_2048
+sym_2_2048: la $2, sym_2_2048
+.globl sym_2_2049
+sym_2_2049: la $2, sym_2_2049
+.globl sym_2_2050
+sym_2_2050: la $2, sym_2_2050
+.globl sym_2_2051
+sym_2_2051: la $2, sym_2_2051
+.globl sym_2_2052
+sym_2_2052: la $2, sym_2_2052
+.globl sym_2_2053
+sym_2_2053: la $2, sym_2_2053
+.globl sym_2_2054
+sym_2_2054: la $2, sym_2_2054
+.globl sym_2_2055
+sym_2_2055: la $2, sym_2_2055
+.globl sym_2_2056
+sym_2_2056: la $2, sym_2_2056
+.globl sym_2_2057
+sym_2_2057: la $2, sym_2_2057
+.globl sym_2_2058
+sym_2_2058: la $2, sym_2_2058
+.globl sym_2_2059
+sym_2_2059: la $2, sym_2_2059
+.globl sym_2_2060
+sym_2_2060: la $2, sym_2_2060
+.globl sym_2_2061
+sym_2_2061: la $2, sym_2_2061
+.globl sym_2_2062
+sym_2_2062: la $2, sym_2_2062
+.globl sym_2_2063
+sym_2_2063: la $2, sym_2_2063
+.globl sym_2_2064
+sym_2_2064: la $2, sym_2_2064
+.globl sym_2_2065
+sym_2_2065: la $2, sym_2_2065
+.globl sym_2_2066
+sym_2_2066: la $2, sym_2_2066
+.globl sym_2_2067
+sym_2_2067: la $2, sym_2_2067
+.globl sym_2_2068
+sym_2_2068: la $2, sym_2_2068
+.globl sym_2_2069
+sym_2_2069: la $2, sym_2_2069
+.globl sym_2_2070
+sym_2_2070: la $2, sym_2_2070
+.globl sym_2_2071
+sym_2_2071: la $2, sym_2_2071
+.globl sym_2_2072
+sym_2_2072: la $2, sym_2_2072
+.globl sym_2_2073
+sym_2_2073: la $2, sym_2_2073
+.globl sym_2_2074
+sym_2_2074: la $2, sym_2_2074
+.globl sym_2_2075
+sym_2_2075: la $2, sym_2_2075
+.globl sym_2_2076
+sym_2_2076: la $2, sym_2_2076
+.globl sym_2_2077
+sym_2_2077: la $2, sym_2_2077
+.globl sym_2_2078
+sym_2_2078: la $2, sym_2_2078
+.globl sym_2_2079
+sym_2_2079: la $2, sym_2_2079
+.globl sym_2_2080
+sym_2_2080: la $2, sym_2_2080
+.globl sym_2_2081
+sym_2_2081: la $2, sym_2_2081
+.globl sym_2_2082
+sym_2_2082: la $2, sym_2_2082
+.globl sym_2_2083
+sym_2_2083: la $2, sym_2_2083
+.globl sym_2_2084
+sym_2_2084: la $2, sym_2_2084
+.globl sym_2_2085
+sym_2_2085: la $2, sym_2_2085
+.globl sym_2_2086
+sym_2_2086: la $2, sym_2_2086
+.globl sym_2_2087
+sym_2_2087: la $2, sym_2_2087
+.globl sym_2_2088
+sym_2_2088: la $2, sym_2_2088
+.globl sym_2_2089
+sym_2_2089: la $2, sym_2_2089
+.globl sym_2_2090
+sym_2_2090: la $2, sym_2_2090
+.globl sym_2_2091
+sym_2_2091: la $2, sym_2_2091
+.globl sym_2_2092
+sym_2_2092: la $2, sym_2_2092
+.globl sym_2_2093
+sym_2_2093: la $2, sym_2_2093
+.globl sym_2_2094
+sym_2_2094: la $2, sym_2_2094
+.globl sym_2_2095
+sym_2_2095: la $2, sym_2_2095
+.globl sym_2_2096
+sym_2_2096: la $2, sym_2_2096
+.globl sym_2_2097
+sym_2_2097: la $2, sym_2_2097
+.globl sym_2_2098
+sym_2_2098: la $2, sym_2_2098
+.globl sym_2_2099
+sym_2_2099: la $2, sym_2_2099
+.globl sym_2_2100
+sym_2_2100: la $2, sym_2_2100
+.globl sym_2_2101
+sym_2_2101: la $2, sym_2_2101
+.globl sym_2_2102
+sym_2_2102: la $2, sym_2_2102
+.globl sym_2_2103
+sym_2_2103: la $2, sym_2_2103
+.globl sym_2_2104
+sym_2_2104: la $2, sym_2_2104
+.globl sym_2_2105
+sym_2_2105: la $2, sym_2_2105
+.globl sym_2_2106
+sym_2_2106: la $2, sym_2_2106
+.globl sym_2_2107
+sym_2_2107: la $2, sym_2_2107
+.globl sym_2_2108
+sym_2_2108: la $2, sym_2_2108
+.globl sym_2_2109
+sym_2_2109: la $2, sym_2_2109
+.globl sym_2_2110
+sym_2_2110: la $2, sym_2_2110
+.globl sym_2_2111
+sym_2_2111: la $2, sym_2_2111
+.globl sym_2_2112
+sym_2_2112: la $2, sym_2_2112
+.globl sym_2_2113
+sym_2_2113: la $2, sym_2_2113
+.globl sym_2_2114
+sym_2_2114: la $2, sym_2_2114
+.globl sym_2_2115
+sym_2_2115: la $2, sym_2_2115
+.globl sym_2_2116
+sym_2_2116: la $2, sym_2_2116
+.globl sym_2_2117
+sym_2_2117: la $2, sym_2_2117
+.globl sym_2_2118
+sym_2_2118: la $2, sym_2_2118
+.globl sym_2_2119
+sym_2_2119: la $2, sym_2_2119
+.globl sym_2_2120
+sym_2_2120: la $2, sym_2_2120
+.globl sym_2_2121
+sym_2_2121: la $2, sym_2_2121
+.globl sym_2_2122
+sym_2_2122: la $2, sym_2_2122
+.globl sym_2_2123
+sym_2_2123: la $2, sym_2_2123
+.globl sym_2_2124
+sym_2_2124: la $2, sym_2_2124
+.globl sym_2_2125
+sym_2_2125: la $2, sym_2_2125
+.globl sym_2_2126
+sym_2_2126: la $2, sym_2_2126
+.globl sym_2_2127
+sym_2_2127: la $2, sym_2_2127
+.globl sym_2_2128
+sym_2_2128: la $2, sym_2_2128
+.globl sym_2_2129
+sym_2_2129: la $2, sym_2_2129
+.globl sym_2_2130
+sym_2_2130: la $2, sym_2_2130
+.globl sym_2_2131
+sym_2_2131: la $2, sym_2_2131
+.globl sym_2_2132
+sym_2_2132: la $2, sym_2_2132
+.globl sym_2_2133
+sym_2_2133: la $2, sym_2_2133
+.globl sym_2_2134
+sym_2_2134: la $2, sym_2_2134
+.globl sym_2_2135
+sym_2_2135: la $2, sym_2_2135
+.globl sym_2_2136
+sym_2_2136: la $2, sym_2_2136
+.globl sym_2_2137
+sym_2_2137: la $2, sym_2_2137
+.globl sym_2_2138
+sym_2_2138: la $2, sym_2_2138
+.globl sym_2_2139
+sym_2_2139: la $2, sym_2_2139
+.globl sym_2_2140
+sym_2_2140: la $2, sym_2_2140
+.globl sym_2_2141
+sym_2_2141: la $2, sym_2_2141
+.globl sym_2_2142
+sym_2_2142: la $2, sym_2_2142
+.globl sym_2_2143
+sym_2_2143: la $2, sym_2_2143
+.globl sym_2_2144
+sym_2_2144: la $2, sym_2_2144
+.globl sym_2_2145
+sym_2_2145: la $2, sym_2_2145
+.globl sym_2_2146
+sym_2_2146: la $2, sym_2_2146
+.globl sym_2_2147
+sym_2_2147: la $2, sym_2_2147
+.globl sym_2_2148
+sym_2_2148: la $2, sym_2_2148
+.globl sym_2_2149
+sym_2_2149: la $2, sym_2_2149
+.globl sym_2_2150
+sym_2_2150: la $2, sym_2_2150
+.globl sym_2_2151
+sym_2_2151: la $2, sym_2_2151
+.globl sym_2_2152
+sym_2_2152: la $2, sym_2_2152
+.globl sym_2_2153
+sym_2_2153: la $2, sym_2_2153
+.globl sym_2_2154
+sym_2_2154: la $2, sym_2_2154
+.globl sym_2_2155
+sym_2_2155: la $2, sym_2_2155
+.globl sym_2_2156
+sym_2_2156: la $2, sym_2_2156
+.globl sym_2_2157
+sym_2_2157: la $2, sym_2_2157
+.globl sym_2_2158
+sym_2_2158: la $2, sym_2_2158
+.globl sym_2_2159
+sym_2_2159: la $2, sym_2_2159
+.globl sym_2_2160
+sym_2_2160: la $2, sym_2_2160
+.globl sym_2_2161
+sym_2_2161: la $2, sym_2_2161
+.globl sym_2_2162
+sym_2_2162: la $2, sym_2_2162
+.globl sym_2_2163
+sym_2_2163: la $2, sym_2_2163
+.globl sym_2_2164
+sym_2_2164: la $2, sym_2_2164
+.globl sym_2_2165
+sym_2_2165: la $2, sym_2_2165
+.globl sym_2_2166
+sym_2_2166: la $2, sym_2_2166
+.globl sym_2_2167
+sym_2_2167: la $2, sym_2_2167
+.globl sym_2_2168
+sym_2_2168: la $2, sym_2_2168
+.globl sym_2_2169
+sym_2_2169: la $2, sym_2_2169
+.globl sym_2_2170
+sym_2_2170: la $2, sym_2_2170
+.globl sym_2_2171
+sym_2_2171: la $2, sym_2_2171
+.globl sym_2_2172
+sym_2_2172: la $2, sym_2_2172
+.globl sym_2_2173
+sym_2_2173: la $2, sym_2_2173
+.globl sym_2_2174
+sym_2_2174: la $2, sym_2_2174
+.globl sym_2_2175
+sym_2_2175: la $2, sym_2_2175
+.globl sym_2_2176
+sym_2_2176: la $2, sym_2_2176
+.globl sym_2_2177
+sym_2_2177: la $2, sym_2_2177
+.globl sym_2_2178
+sym_2_2178: la $2, sym_2_2178
+.globl sym_2_2179
+sym_2_2179: la $2, sym_2_2179
+.globl sym_2_2180
+sym_2_2180: la $2, sym_2_2180
+.globl sym_2_2181
+sym_2_2181: la $2, sym_2_2181
+.globl sym_2_2182
+sym_2_2182: la $2, sym_2_2182
+.globl sym_2_2183
+sym_2_2183: la $2, sym_2_2183
+.globl sym_2_2184
+sym_2_2184: la $2, sym_2_2184
+.globl sym_2_2185
+sym_2_2185: la $2, sym_2_2185
+.globl sym_2_2186
+sym_2_2186: la $2, sym_2_2186
+.globl sym_2_2187
+sym_2_2187: la $2, sym_2_2187
+.globl sym_2_2188
+sym_2_2188: la $2, sym_2_2188
+.globl sym_2_2189
+sym_2_2189: la $2, sym_2_2189
+.globl sym_2_2190
+sym_2_2190: la $2, sym_2_2190
+.globl sym_2_2191
+sym_2_2191: la $2, sym_2_2191
+.globl sym_2_2192
+sym_2_2192: la $2, sym_2_2192
+.globl sym_2_2193
+sym_2_2193: la $2, sym_2_2193
+.globl sym_2_2194
+sym_2_2194: la $2, sym_2_2194
+.globl sym_2_2195
+sym_2_2195: la $2, sym_2_2195
+.globl sym_2_2196
+sym_2_2196: la $2, sym_2_2196
+.globl sym_2_2197
+sym_2_2197: la $2, sym_2_2197
+.globl sym_2_2198
+sym_2_2198: la $2, sym_2_2198
+.globl sym_2_2199
+sym_2_2199: la $2, sym_2_2199
+.globl sym_2_2200
+sym_2_2200: la $2, sym_2_2200
+.globl sym_2_2201
+sym_2_2201: la $2, sym_2_2201
+.globl sym_2_2202
+sym_2_2202: la $2, sym_2_2202
+.globl sym_2_2203
+sym_2_2203: la $2, sym_2_2203
+.globl sym_2_2204
+sym_2_2204: la $2, sym_2_2204
+.globl sym_2_2205
+sym_2_2205: la $2, sym_2_2205
+.globl sym_2_2206
+sym_2_2206: la $2, sym_2_2206
+.globl sym_2_2207
+sym_2_2207: la $2, sym_2_2207
+.globl sym_2_2208
+sym_2_2208: la $2, sym_2_2208
+.globl sym_2_2209
+sym_2_2209: la $2, sym_2_2209
+.globl sym_2_2210
+sym_2_2210: la $2, sym_2_2210
+.globl sym_2_2211
+sym_2_2211: la $2, sym_2_2211
+.globl sym_2_2212
+sym_2_2212: la $2, sym_2_2212
+.globl sym_2_2213
+sym_2_2213: la $2, sym_2_2213
+.globl sym_2_2214
+sym_2_2214: la $2, sym_2_2214
+.globl sym_2_2215
+sym_2_2215: la $2, sym_2_2215
+.globl sym_2_2216
+sym_2_2216: la $2, sym_2_2216
+.globl sym_2_2217
+sym_2_2217: la $2, sym_2_2217
+.globl sym_2_2218
+sym_2_2218: la $2, sym_2_2218
+.globl sym_2_2219
+sym_2_2219: la $2, sym_2_2219
+.globl sym_2_2220
+sym_2_2220: la $2, sym_2_2220
+.globl sym_2_2221
+sym_2_2221: la $2, sym_2_2221
+.globl sym_2_2222
+sym_2_2222: la $2, sym_2_2222
+.globl sym_2_2223
+sym_2_2223: la $2, sym_2_2223
+.globl sym_2_2224
+sym_2_2224: la $2, sym_2_2224
+.globl sym_2_2225
+sym_2_2225: la $2, sym_2_2225
+.globl sym_2_2226
+sym_2_2226: la $2, sym_2_2226
+.globl sym_2_2227
+sym_2_2227: la $2, sym_2_2227
+.globl sym_2_2228
+sym_2_2228: la $2, sym_2_2228
+.globl sym_2_2229
+sym_2_2229: la $2, sym_2_2229
+.globl sym_2_2230
+sym_2_2230: la $2, sym_2_2230
+.globl sym_2_2231
+sym_2_2231: la $2, sym_2_2231
+.globl sym_2_2232
+sym_2_2232: la $2, sym_2_2232
+.globl sym_2_2233
+sym_2_2233: la $2, sym_2_2233
+.globl sym_2_2234
+sym_2_2234: la $2, sym_2_2234
+.globl sym_2_2235
+sym_2_2235: la $2, sym_2_2235
+.globl sym_2_2236
+sym_2_2236: la $2, sym_2_2236
+.globl sym_2_2237
+sym_2_2237: la $2, sym_2_2237
+.globl sym_2_2238
+sym_2_2238: la $2, sym_2_2238
+.globl sym_2_2239
+sym_2_2239: la $2, sym_2_2239
+.globl sym_2_2240
+sym_2_2240: la $2, sym_2_2240
+.globl sym_2_2241
+sym_2_2241: la $2, sym_2_2241
+.globl sym_2_2242
+sym_2_2242: la $2, sym_2_2242
+.globl sym_2_2243
+sym_2_2243: la $2, sym_2_2243
+.globl sym_2_2244
+sym_2_2244: la $2, sym_2_2244
+.globl sym_2_2245
+sym_2_2245: la $2, sym_2_2245
+.globl sym_2_2246
+sym_2_2246: la $2, sym_2_2246
+.globl sym_2_2247
+sym_2_2247: la $2, sym_2_2247
+.globl sym_2_2248
+sym_2_2248: la $2, sym_2_2248
+.globl sym_2_2249
+sym_2_2249: la $2, sym_2_2249
+.globl sym_2_2250
+sym_2_2250: la $2, sym_2_2250
+.globl sym_2_2251
+sym_2_2251: la $2, sym_2_2251
+.globl sym_2_2252
+sym_2_2252: la $2, sym_2_2252
+.globl sym_2_2253
+sym_2_2253: la $2, sym_2_2253
+.globl sym_2_2254
+sym_2_2254: la $2, sym_2_2254
+.globl sym_2_2255
+sym_2_2255: la $2, sym_2_2255
+.globl sym_2_2256
+sym_2_2256: la $2, sym_2_2256
+.globl sym_2_2257
+sym_2_2257: la $2, sym_2_2257
+.globl sym_2_2258
+sym_2_2258: la $2, sym_2_2258
+.globl sym_2_2259
+sym_2_2259: la $2, sym_2_2259
+.globl sym_2_2260
+sym_2_2260: la $2, sym_2_2260
+.globl sym_2_2261
+sym_2_2261: la $2, sym_2_2261
+.globl sym_2_2262
+sym_2_2262: la $2, sym_2_2262
+.globl sym_2_2263
+sym_2_2263: la $2, sym_2_2263
+.globl sym_2_2264
+sym_2_2264: la $2, sym_2_2264
+.globl sym_2_2265
+sym_2_2265: la $2, sym_2_2265
+.globl sym_2_2266
+sym_2_2266: la $2, sym_2_2266
+.globl sym_2_2267
+sym_2_2267: la $2, sym_2_2267
+.globl sym_2_2268
+sym_2_2268: la $2, sym_2_2268
+.globl sym_2_2269
+sym_2_2269: la $2, sym_2_2269
+.globl sym_2_2270
+sym_2_2270: la $2, sym_2_2270
+.globl sym_2_2271
+sym_2_2271: la $2, sym_2_2271
+.globl sym_2_2272
+sym_2_2272: la $2, sym_2_2272
+.globl sym_2_2273
+sym_2_2273: la $2, sym_2_2273
+.globl sym_2_2274
+sym_2_2274: la $2, sym_2_2274
+.globl sym_2_2275
+sym_2_2275: la $2, sym_2_2275
+.globl sym_2_2276
+sym_2_2276: la $2, sym_2_2276
+.globl sym_2_2277
+sym_2_2277: la $2, sym_2_2277
+.globl sym_2_2278
+sym_2_2278: la $2, sym_2_2278
+.globl sym_2_2279
+sym_2_2279: la $2, sym_2_2279
+.globl sym_2_2280
+sym_2_2280: la $2, sym_2_2280
+.globl sym_2_2281
+sym_2_2281: la $2, sym_2_2281
+.globl sym_2_2282
+sym_2_2282: la $2, sym_2_2282
+.globl sym_2_2283
+sym_2_2283: la $2, sym_2_2283
+.globl sym_2_2284
+sym_2_2284: la $2, sym_2_2284
+.globl sym_2_2285
+sym_2_2285: la $2, sym_2_2285
+.globl sym_2_2286
+sym_2_2286: la $2, sym_2_2286
+.globl sym_2_2287
+sym_2_2287: la $2, sym_2_2287
+.globl sym_2_2288
+sym_2_2288: la $2, sym_2_2288
+.globl sym_2_2289
+sym_2_2289: la $2, sym_2_2289
+.globl sym_2_2290
+sym_2_2290: la $2, sym_2_2290
+.globl sym_2_2291
+sym_2_2291: la $2, sym_2_2291
+.globl sym_2_2292
+sym_2_2292: la $2, sym_2_2292
+.globl sym_2_2293
+sym_2_2293: la $2, sym_2_2293
+.globl sym_2_2294
+sym_2_2294: la $2, sym_2_2294
+.globl sym_2_2295
+sym_2_2295: la $2, sym_2_2295
+.globl sym_2_2296
+sym_2_2296: la $2, sym_2_2296
+.globl sym_2_2297
+sym_2_2297: la $2, sym_2_2297
+.globl sym_2_2298
+sym_2_2298: la $2, sym_2_2298
+.globl sym_2_2299
+sym_2_2299: la $2, sym_2_2299
+.globl sym_2_2300
+sym_2_2300: la $2, sym_2_2300
+.globl sym_2_2301
+sym_2_2301: la $2, sym_2_2301
+.globl sym_2_2302
+sym_2_2302: la $2, sym_2_2302
+.globl sym_2_2303
+sym_2_2303: la $2, sym_2_2303
+.globl sym_2_2304
+sym_2_2304: la $2, sym_2_2304
+.globl sym_2_2305
+sym_2_2305: la $2, sym_2_2305
+.globl sym_2_2306
+sym_2_2306: la $2, sym_2_2306
+.globl sym_2_2307
+sym_2_2307: la $2, sym_2_2307
+.globl sym_2_2308
+sym_2_2308: la $2, sym_2_2308
+.globl sym_2_2309
+sym_2_2309: la $2, sym_2_2309
+.globl sym_2_2310
+sym_2_2310: la $2, sym_2_2310
+.globl sym_2_2311
+sym_2_2311: la $2, sym_2_2311
+.globl sym_2_2312
+sym_2_2312: la $2, sym_2_2312
+.globl sym_2_2313
+sym_2_2313: la $2, sym_2_2313
+.globl sym_2_2314
+sym_2_2314: la $2, sym_2_2314
+.globl sym_2_2315
+sym_2_2315: la $2, sym_2_2315
+.globl sym_2_2316
+sym_2_2316: la $2, sym_2_2316
+.globl sym_2_2317
+sym_2_2317: la $2, sym_2_2317
+.globl sym_2_2318
+sym_2_2318: la $2, sym_2_2318
+.globl sym_2_2319
+sym_2_2319: la $2, sym_2_2319
+.globl sym_2_2320
+sym_2_2320: la $2, sym_2_2320
+.globl sym_2_2321
+sym_2_2321: la $2, sym_2_2321
+.globl sym_2_2322
+sym_2_2322: la $2, sym_2_2322
+.globl sym_2_2323
+sym_2_2323: la $2, sym_2_2323
+.globl sym_2_2324
+sym_2_2324: la $2, sym_2_2324
+.globl sym_2_2325
+sym_2_2325: la $2, sym_2_2325
+.globl sym_2_2326
+sym_2_2326: la $2, sym_2_2326
+.globl sym_2_2327
+sym_2_2327: la $2, sym_2_2327
+.globl sym_2_2328
+sym_2_2328: la $2, sym_2_2328
+.globl sym_2_2329
+sym_2_2329: la $2, sym_2_2329
+.globl sym_2_2330
+sym_2_2330: la $2, sym_2_2330
+.globl sym_2_2331
+sym_2_2331: la $2, sym_2_2331
+.globl sym_2_2332
+sym_2_2332: la $2, sym_2_2332
+.globl sym_2_2333
+sym_2_2333: la $2, sym_2_2333
+.globl sym_2_2334
+sym_2_2334: la $2, sym_2_2334
+.globl sym_2_2335
+sym_2_2335: la $2, sym_2_2335
+.globl sym_2_2336
+sym_2_2336: la $2, sym_2_2336
+.globl sym_2_2337
+sym_2_2337: la $2, sym_2_2337
+.globl sym_2_2338
+sym_2_2338: la $2, sym_2_2338
+.globl sym_2_2339
+sym_2_2339: la $2, sym_2_2339
+.globl sym_2_2340
+sym_2_2340: la $2, sym_2_2340
+.globl sym_2_2341
+sym_2_2341: la $2, sym_2_2341
+.globl sym_2_2342
+sym_2_2342: la $2, sym_2_2342
+.globl sym_2_2343
+sym_2_2343: la $2, sym_2_2343
+.globl sym_2_2344
+sym_2_2344: la $2, sym_2_2344
+.globl sym_2_2345
+sym_2_2345: la $2, sym_2_2345
+.globl sym_2_2346
+sym_2_2346: la $2, sym_2_2346
+.globl sym_2_2347
+sym_2_2347: la $2, sym_2_2347
+.globl sym_2_2348
+sym_2_2348: la $2, sym_2_2348
+.globl sym_2_2349
+sym_2_2349: la $2, sym_2_2349
+.globl sym_2_2350
+sym_2_2350: la $2, sym_2_2350
+.globl sym_2_2351
+sym_2_2351: la $2, sym_2_2351
+.globl sym_2_2352
+sym_2_2352: la $2, sym_2_2352
+.globl sym_2_2353
+sym_2_2353: la $2, sym_2_2353
+.globl sym_2_2354
+sym_2_2354: la $2, sym_2_2354
+.globl sym_2_2355
+sym_2_2355: la $2, sym_2_2355
+.globl sym_2_2356
+sym_2_2356: la $2, sym_2_2356
+.globl sym_2_2357
+sym_2_2357: la $2, sym_2_2357
+.globl sym_2_2358
+sym_2_2358: la $2, sym_2_2358
+.globl sym_2_2359
+sym_2_2359: la $2, sym_2_2359
+.globl sym_2_2360
+sym_2_2360: la $2, sym_2_2360
+.globl sym_2_2361
+sym_2_2361: la $2, sym_2_2361
+.globl sym_2_2362
+sym_2_2362: la $2, sym_2_2362
+.globl sym_2_2363
+sym_2_2363: la $2, sym_2_2363
+.globl sym_2_2364
+sym_2_2364: la $2, sym_2_2364
+.globl sym_2_2365
+sym_2_2365: la $2, sym_2_2365
+.globl sym_2_2366
+sym_2_2366: la $2, sym_2_2366
+.globl sym_2_2367
+sym_2_2367: la $2, sym_2_2367
+.globl sym_2_2368
+sym_2_2368: la $2, sym_2_2368
+.globl sym_2_2369
+sym_2_2369: la $2, sym_2_2369
+.globl sym_2_2370
+sym_2_2370: la $2, sym_2_2370
+.globl sym_2_2371
+sym_2_2371: la $2, sym_2_2371
+.globl sym_2_2372
+sym_2_2372: la $2, sym_2_2372
+.globl sym_2_2373
+sym_2_2373: la $2, sym_2_2373
+.globl sym_2_2374
+sym_2_2374: la $2, sym_2_2374
+.globl sym_2_2375
+sym_2_2375: la $2, sym_2_2375
+.globl sym_2_2376
+sym_2_2376: la $2, sym_2_2376
+.globl sym_2_2377
+sym_2_2377: la $2, sym_2_2377
+.globl sym_2_2378
+sym_2_2378: la $2, sym_2_2378
+.globl sym_2_2379
+sym_2_2379: la $2, sym_2_2379
+.globl sym_2_2380
+sym_2_2380: la $2, sym_2_2380
+.globl sym_2_2381
+sym_2_2381: la $2, sym_2_2381
+.globl sym_2_2382
+sym_2_2382: la $2, sym_2_2382
+.globl sym_2_2383
+sym_2_2383: la $2, sym_2_2383
+.globl sym_2_2384
+sym_2_2384: la $2, sym_2_2384
+.globl sym_2_2385
+sym_2_2385: la $2, sym_2_2385
+.globl sym_2_2386
+sym_2_2386: la $2, sym_2_2386
+.globl sym_2_2387
+sym_2_2387: la $2, sym_2_2387
+.globl sym_2_2388
+sym_2_2388: la $2, sym_2_2388
+.globl sym_2_2389
+sym_2_2389: la $2, sym_2_2389
+.globl sym_2_2390
+sym_2_2390: la $2, sym_2_2390
+.globl sym_2_2391
+sym_2_2391: la $2, sym_2_2391
+.globl sym_2_2392
+sym_2_2392: la $2, sym_2_2392
+.globl sym_2_2393
+sym_2_2393: la $2, sym_2_2393
+.globl sym_2_2394
+sym_2_2394: la $2, sym_2_2394
+.globl sym_2_2395
+sym_2_2395: la $2, sym_2_2395
+.globl sym_2_2396
+sym_2_2396: la $2, sym_2_2396
+.globl sym_2_2397
+sym_2_2397: la $2, sym_2_2397
+.globl sym_2_2398
+sym_2_2398: la $2, sym_2_2398
+.globl sym_2_2399
+sym_2_2399: la $2, sym_2_2399
+.globl sym_2_2400
+sym_2_2400: la $2, sym_2_2400
+.globl sym_2_2401
+sym_2_2401: la $2, sym_2_2401
+.globl sym_2_2402
+sym_2_2402: la $2, sym_2_2402
+.globl sym_2_2403
+sym_2_2403: la $2, sym_2_2403
+.globl sym_2_2404
+sym_2_2404: la $2, sym_2_2404
+.globl sym_2_2405
+sym_2_2405: la $2, sym_2_2405
+.globl sym_2_2406
+sym_2_2406: la $2, sym_2_2406
+.globl sym_2_2407
+sym_2_2407: la $2, sym_2_2407
+.globl sym_2_2408
+sym_2_2408: la $2, sym_2_2408
+.globl sym_2_2409
+sym_2_2409: la $2, sym_2_2409
+.globl sym_2_2410
+sym_2_2410: la $2, sym_2_2410
+.globl sym_2_2411
+sym_2_2411: la $2, sym_2_2411
+.globl sym_2_2412
+sym_2_2412: la $2, sym_2_2412
+.globl sym_2_2413
+sym_2_2413: la $2, sym_2_2413
+.globl sym_2_2414
+sym_2_2414: la $2, sym_2_2414
+.globl sym_2_2415
+sym_2_2415: la $2, sym_2_2415
+.globl sym_2_2416
+sym_2_2416: la $2, sym_2_2416
+.globl sym_2_2417
+sym_2_2417: la $2, sym_2_2417
+.globl sym_2_2418
+sym_2_2418: la $2, sym_2_2418
+.globl sym_2_2419
+sym_2_2419: la $2, sym_2_2419
+.globl sym_2_2420
+sym_2_2420: la $2, sym_2_2420
+.globl sym_2_2421
+sym_2_2421: la $2, sym_2_2421
+.globl sym_2_2422
+sym_2_2422: la $2, sym_2_2422
+.globl sym_2_2423
+sym_2_2423: la $2, sym_2_2423
+.globl sym_2_2424
+sym_2_2424: la $2, sym_2_2424
+.globl sym_2_2425
+sym_2_2425: la $2, sym_2_2425
+.globl sym_2_2426
+sym_2_2426: la $2, sym_2_2426
+.globl sym_2_2427
+sym_2_2427: la $2, sym_2_2427
+.globl sym_2_2428
+sym_2_2428: la $2, sym_2_2428
+.globl sym_2_2429
+sym_2_2429: la $2, sym_2_2429
+.globl sym_2_2430
+sym_2_2430: la $2, sym_2_2430
+.globl sym_2_2431
+sym_2_2431: la $2, sym_2_2431
+.globl sym_2_2432
+sym_2_2432: la $2, sym_2_2432
+.globl sym_2_2433
+sym_2_2433: la $2, sym_2_2433
+.globl sym_2_2434
+sym_2_2434: la $2, sym_2_2434
+.globl sym_2_2435
+sym_2_2435: la $2, sym_2_2435
+.globl sym_2_2436
+sym_2_2436: la $2, sym_2_2436
+.globl sym_2_2437
+sym_2_2437: la $2, sym_2_2437
+.globl sym_2_2438
+sym_2_2438: la $2, sym_2_2438
+.globl sym_2_2439
+sym_2_2439: la $2, sym_2_2439
+.globl sym_2_2440
+sym_2_2440: la $2, sym_2_2440
+.globl sym_2_2441
+sym_2_2441: la $2, sym_2_2441
+.globl sym_2_2442
+sym_2_2442: la $2, sym_2_2442
+.globl sym_2_2443
+sym_2_2443: la $2, sym_2_2443
+.globl sym_2_2444
+sym_2_2444: la $2, sym_2_2444
+.globl sym_2_2445
+sym_2_2445: la $2, sym_2_2445
+.globl sym_2_2446
+sym_2_2446: la $2, sym_2_2446
+.globl sym_2_2447
+sym_2_2447: la $2, sym_2_2447
+.globl sym_2_2448
+sym_2_2448: la $2, sym_2_2448
+.globl sym_2_2449
+sym_2_2449: la $2, sym_2_2449
+.globl sym_2_2450
+sym_2_2450: la $2, sym_2_2450
+.globl sym_2_2451
+sym_2_2451: la $2, sym_2_2451
+.globl sym_2_2452
+sym_2_2452: la $2, sym_2_2452
+.globl sym_2_2453
+sym_2_2453: la $2, sym_2_2453
+.globl sym_2_2454
+sym_2_2454: la $2, sym_2_2454
+.globl sym_2_2455
+sym_2_2455: la $2, sym_2_2455
+.globl sym_2_2456
+sym_2_2456: la $2, sym_2_2456
+.globl sym_2_2457
+sym_2_2457: la $2, sym_2_2457
+.globl sym_2_2458
+sym_2_2458: la $2, sym_2_2458
+.globl sym_2_2459
+sym_2_2459: la $2, sym_2_2459
+.globl sym_2_2460
+sym_2_2460: la $2, sym_2_2460
+.globl sym_2_2461
+sym_2_2461: la $2, sym_2_2461
+.globl sym_2_2462
+sym_2_2462: la $2, sym_2_2462
+.globl sym_2_2463
+sym_2_2463: la $2, sym_2_2463
+.globl sym_2_2464
+sym_2_2464: la $2, sym_2_2464
+.globl sym_2_2465
+sym_2_2465: la $2, sym_2_2465
+.globl sym_2_2466
+sym_2_2466: la $2, sym_2_2466
+.globl sym_2_2467
+sym_2_2467: la $2, sym_2_2467
+.globl sym_2_2468
+sym_2_2468: la $2, sym_2_2468
+.globl sym_2_2469
+sym_2_2469: la $2, sym_2_2469
+.globl sym_2_2470
+sym_2_2470: la $2, sym_2_2470
+.globl sym_2_2471
+sym_2_2471: la $2, sym_2_2471
+.globl sym_2_2472
+sym_2_2472: la $2, sym_2_2472
+.globl sym_2_2473
+sym_2_2473: la $2, sym_2_2473
+.globl sym_2_2474
+sym_2_2474: la $2, sym_2_2474
+.globl sym_2_2475
+sym_2_2475: la $2, sym_2_2475
+.globl sym_2_2476
+sym_2_2476: la $2, sym_2_2476
+.globl sym_2_2477
+sym_2_2477: la $2, sym_2_2477
+.globl sym_2_2478
+sym_2_2478: la $2, sym_2_2478
+.globl sym_2_2479
+sym_2_2479: la $2, sym_2_2479
+.globl sym_2_2480
+sym_2_2480: la $2, sym_2_2480
+.globl sym_2_2481
+sym_2_2481: la $2, sym_2_2481
+.globl sym_2_2482
+sym_2_2482: la $2, sym_2_2482
+.globl sym_2_2483
+sym_2_2483: la $2, sym_2_2483
+.globl sym_2_2484
+sym_2_2484: la $2, sym_2_2484
+.globl sym_2_2485
+sym_2_2485: la $2, sym_2_2485
+.globl sym_2_2486
+sym_2_2486: la $2, sym_2_2486
+.globl sym_2_2487
+sym_2_2487: la $2, sym_2_2487
+.globl sym_2_2488
+sym_2_2488: la $2, sym_2_2488
+.globl sym_2_2489
+sym_2_2489: la $2, sym_2_2489
+.globl sym_2_2490
+sym_2_2490: la $2, sym_2_2490
+.globl sym_2_2491
+sym_2_2491: la $2, sym_2_2491
+.globl sym_2_2492
+sym_2_2492: la $2, sym_2_2492
+.globl sym_2_2493
+sym_2_2493: la $2, sym_2_2493
+.globl sym_2_2494
+sym_2_2494: la $2, sym_2_2494
+.globl sym_2_2495
+sym_2_2495: la $2, sym_2_2495
+.globl sym_2_2496
+sym_2_2496: la $2, sym_2_2496
+.globl sym_2_2497
+sym_2_2497: la $2, sym_2_2497
+.globl sym_2_2498
+sym_2_2498: la $2, sym_2_2498
+.globl sym_2_2499
+sym_2_2499: la $2, sym_2_2499
+.globl sym_2_2500
+sym_2_2500: la $2, sym_2_2500
+.globl sym_2_2501
+sym_2_2501: la $2, sym_2_2501
+.globl sym_2_2502
+sym_2_2502: la $2, sym_2_2502
+.globl sym_2_2503
+sym_2_2503: la $2, sym_2_2503
+.globl sym_2_2504
+sym_2_2504: la $2, sym_2_2504
+.globl sym_2_2505
+sym_2_2505: la $2, sym_2_2505
+.globl sym_2_2506
+sym_2_2506: la $2, sym_2_2506
+.globl sym_2_2507
+sym_2_2507: la $2, sym_2_2507
+.globl sym_2_2508
+sym_2_2508: la $2, sym_2_2508
+.globl sym_2_2509
+sym_2_2509: la $2, sym_2_2509
+.globl sym_2_2510
+sym_2_2510: la $2, sym_2_2510
+.globl sym_2_2511
+sym_2_2511: la $2, sym_2_2511
+.globl sym_2_2512
+sym_2_2512: la $2, sym_2_2512
+.globl sym_2_2513
+sym_2_2513: la $2, sym_2_2513
+.globl sym_2_2514
+sym_2_2514: la $2, sym_2_2514
+.globl sym_2_2515
+sym_2_2515: la $2, sym_2_2515
+.globl sym_2_2516
+sym_2_2516: la $2, sym_2_2516
+.globl sym_2_2517
+sym_2_2517: la $2, sym_2_2517
+.globl sym_2_2518
+sym_2_2518: la $2, sym_2_2518
+.globl sym_2_2519
+sym_2_2519: la $2, sym_2_2519
+.globl sym_2_2520
+sym_2_2520: la $2, sym_2_2520
+.globl sym_2_2521
+sym_2_2521: la $2, sym_2_2521
+.globl sym_2_2522
+sym_2_2522: la $2, sym_2_2522
+.globl sym_2_2523
+sym_2_2523: la $2, sym_2_2523
+.globl sym_2_2524
+sym_2_2524: la $2, sym_2_2524
+.globl sym_2_2525
+sym_2_2525: la $2, sym_2_2525
+.globl sym_2_2526
+sym_2_2526: la $2, sym_2_2526
+.globl sym_2_2527
+sym_2_2527: la $2, sym_2_2527
+.globl sym_2_2528
+sym_2_2528: la $2, sym_2_2528
+.globl sym_2_2529
+sym_2_2529: la $2, sym_2_2529
+.globl sym_2_2530
+sym_2_2530: la $2, sym_2_2530
+.globl sym_2_2531
+sym_2_2531: la $2, sym_2_2531
+.globl sym_2_2532
+sym_2_2532: la $2, sym_2_2532
+.globl sym_2_2533
+sym_2_2533: la $2, sym_2_2533
+.globl sym_2_2534
+sym_2_2534: la $2, sym_2_2534
+.globl sym_2_2535
+sym_2_2535: la $2, sym_2_2535
+.globl sym_2_2536
+sym_2_2536: la $2, sym_2_2536
+.globl sym_2_2537
+sym_2_2537: la $2, sym_2_2537
+.globl sym_2_2538
+sym_2_2538: la $2, sym_2_2538
+.globl sym_2_2539
+sym_2_2539: la $2, sym_2_2539
+.globl sym_2_2540
+sym_2_2540: la $2, sym_2_2540
+.globl sym_2_2541
+sym_2_2541: la $2, sym_2_2541
+.globl sym_2_2542
+sym_2_2542: la $2, sym_2_2542
+.globl sym_2_2543
+sym_2_2543: la $2, sym_2_2543
+.globl sym_2_2544
+sym_2_2544: la $2, sym_2_2544
+.globl sym_2_2545
+sym_2_2545: la $2, sym_2_2545
+.globl sym_2_2546
+sym_2_2546: la $2, sym_2_2546
+.globl sym_2_2547
+sym_2_2547: la $2, sym_2_2547
+.globl sym_2_2548
+sym_2_2548: la $2, sym_2_2548
+.globl sym_2_2549
+sym_2_2549: la $2, sym_2_2549
+.globl sym_2_2550
+sym_2_2550: la $2, sym_2_2550
+.globl sym_2_2551
+sym_2_2551: la $2, sym_2_2551
+.globl sym_2_2552
+sym_2_2552: la $2, sym_2_2552
+.globl sym_2_2553
+sym_2_2553: la $2, sym_2_2553
+.globl sym_2_2554
+sym_2_2554: la $2, sym_2_2554
+.globl sym_2_2555
+sym_2_2555: la $2, sym_2_2555
+.globl sym_2_2556
+sym_2_2556: la $2, sym_2_2556
+.globl sym_2_2557
+sym_2_2557: la $2, sym_2_2557
+.globl sym_2_2558
+sym_2_2558: la $2, sym_2_2558
+.globl sym_2_2559
+sym_2_2559: la $2, sym_2_2559
+.globl sym_2_2560
+sym_2_2560: la $2, sym_2_2560
+.globl sym_2_2561
+sym_2_2561: la $2, sym_2_2561
+.globl sym_2_2562
+sym_2_2562: la $2, sym_2_2562
+.globl sym_2_2563
+sym_2_2563: la $2, sym_2_2563
+.globl sym_2_2564
+sym_2_2564: la $2, sym_2_2564
+.globl sym_2_2565
+sym_2_2565: la $2, sym_2_2565
+.globl sym_2_2566
+sym_2_2566: la $2, sym_2_2566
+.globl sym_2_2567
+sym_2_2567: la $2, sym_2_2567
+.globl sym_2_2568
+sym_2_2568: la $2, sym_2_2568
+.globl sym_2_2569
+sym_2_2569: la $2, sym_2_2569
+.globl sym_2_2570
+sym_2_2570: la $2, sym_2_2570
+.globl sym_2_2571
+sym_2_2571: la $2, sym_2_2571
+.globl sym_2_2572
+sym_2_2572: la $2, sym_2_2572
+.globl sym_2_2573
+sym_2_2573: la $2, sym_2_2573
+.globl sym_2_2574
+sym_2_2574: la $2, sym_2_2574
+.globl sym_2_2575
+sym_2_2575: la $2, sym_2_2575
+.globl sym_2_2576
+sym_2_2576: la $2, sym_2_2576
+.globl sym_2_2577
+sym_2_2577: la $2, sym_2_2577
+.globl sym_2_2578
+sym_2_2578: la $2, sym_2_2578
+.globl sym_2_2579
+sym_2_2579: la $2, sym_2_2579
+.globl sym_2_2580
+sym_2_2580: la $2, sym_2_2580
+.globl sym_2_2581
+sym_2_2581: la $2, sym_2_2581
+.globl sym_2_2582
+sym_2_2582: la $2, sym_2_2582
+.globl sym_2_2583
+sym_2_2583: la $2, sym_2_2583
+.globl sym_2_2584
+sym_2_2584: la $2, sym_2_2584
+.globl sym_2_2585
+sym_2_2585: la $2, sym_2_2585
+.globl sym_2_2586
+sym_2_2586: la $2, sym_2_2586
+.globl sym_2_2587
+sym_2_2587: la $2, sym_2_2587
+.globl sym_2_2588
+sym_2_2588: la $2, sym_2_2588
+.globl sym_2_2589
+sym_2_2589: la $2, sym_2_2589
+.globl sym_2_2590
+sym_2_2590: la $2, sym_2_2590
+.globl sym_2_2591
+sym_2_2591: la $2, sym_2_2591
+.globl sym_2_2592
+sym_2_2592: la $2, sym_2_2592
+.globl sym_2_2593
+sym_2_2593: la $2, sym_2_2593
+.globl sym_2_2594
+sym_2_2594: la $2, sym_2_2594
+.globl sym_2_2595
+sym_2_2595: la $2, sym_2_2595
+.globl sym_2_2596
+sym_2_2596: la $2, sym_2_2596
+.globl sym_2_2597
+sym_2_2597: la $2, sym_2_2597
+.globl sym_2_2598
+sym_2_2598: la $2, sym_2_2598
+.globl sym_2_2599
+sym_2_2599: la $2, sym_2_2599
+.globl sym_2_2600
+sym_2_2600: la $2, sym_2_2600
+.globl sym_2_2601
+sym_2_2601: la $2, sym_2_2601
+.globl sym_2_2602
+sym_2_2602: la $2, sym_2_2602
+.globl sym_2_2603
+sym_2_2603: la $2, sym_2_2603
+.globl sym_2_2604
+sym_2_2604: la $2, sym_2_2604
+.globl sym_2_2605
+sym_2_2605: la $2, sym_2_2605
+.globl sym_2_2606
+sym_2_2606: la $2, sym_2_2606
+.globl sym_2_2607
+sym_2_2607: la $2, sym_2_2607
+.globl sym_2_2608
+sym_2_2608: la $2, sym_2_2608
+.globl sym_2_2609
+sym_2_2609: la $2, sym_2_2609
+.globl sym_2_2610
+sym_2_2610: la $2, sym_2_2610
+.globl sym_2_2611
+sym_2_2611: la $2, sym_2_2611
+.globl sym_2_2612
+sym_2_2612: la $2, sym_2_2612
+.globl sym_2_2613
+sym_2_2613: la $2, sym_2_2613
+.globl sym_2_2614
+sym_2_2614: la $2, sym_2_2614
+.globl sym_2_2615
+sym_2_2615: la $2, sym_2_2615
+.globl sym_2_2616
+sym_2_2616: la $2, sym_2_2616
+.globl sym_2_2617
+sym_2_2617: la $2, sym_2_2617
+.globl sym_2_2618
+sym_2_2618: la $2, sym_2_2618
+.globl sym_2_2619
+sym_2_2619: la $2, sym_2_2619
+.globl sym_2_2620
+sym_2_2620: la $2, sym_2_2620
+.globl sym_2_2621
+sym_2_2621: la $2, sym_2_2621
+.globl sym_2_2622
+sym_2_2622: la $2, sym_2_2622
+.globl sym_2_2623
+sym_2_2623: la $2, sym_2_2623
+.globl sym_2_2624
+sym_2_2624: la $2, sym_2_2624
+.globl sym_2_2625
+sym_2_2625: la $2, sym_2_2625
+.globl sym_2_2626
+sym_2_2626: la $2, sym_2_2626
+.globl sym_2_2627
+sym_2_2627: la $2, sym_2_2627
+.globl sym_2_2628
+sym_2_2628: la $2, sym_2_2628
+.globl sym_2_2629
+sym_2_2629: la $2, sym_2_2629
+.globl sym_2_2630
+sym_2_2630: la $2, sym_2_2630
+.globl sym_2_2631
+sym_2_2631: la $2, sym_2_2631
+.globl sym_2_2632
+sym_2_2632: la $2, sym_2_2632
+.globl sym_2_2633
+sym_2_2633: la $2, sym_2_2633
+.globl sym_2_2634
+sym_2_2634: la $2, sym_2_2634
+.globl sym_2_2635
+sym_2_2635: la $2, sym_2_2635
+.globl sym_2_2636
+sym_2_2636: la $2, sym_2_2636
+.globl sym_2_2637
+sym_2_2637: la $2, sym_2_2637
+.globl sym_2_2638
+sym_2_2638: la $2, sym_2_2638
+.globl sym_2_2639
+sym_2_2639: la $2, sym_2_2639
+.globl sym_2_2640
+sym_2_2640: la $2, sym_2_2640
+.globl sym_2_2641
+sym_2_2641: la $2, sym_2_2641
+.globl sym_2_2642
+sym_2_2642: la $2, sym_2_2642
+.globl sym_2_2643
+sym_2_2643: la $2, sym_2_2643
+.globl sym_2_2644
+sym_2_2644: la $2, sym_2_2644
+.globl sym_2_2645
+sym_2_2645: la $2, sym_2_2645
+.globl sym_2_2646
+sym_2_2646: la $2, sym_2_2646
+.globl sym_2_2647
+sym_2_2647: la $2, sym_2_2647
+.globl sym_2_2648
+sym_2_2648: la $2, sym_2_2648
+.globl sym_2_2649
+sym_2_2649: la $2, sym_2_2649
+.globl sym_2_2650
+sym_2_2650: la $2, sym_2_2650
+.globl sym_2_2651
+sym_2_2651: la $2, sym_2_2651
+.globl sym_2_2652
+sym_2_2652: la $2, sym_2_2652
+.globl sym_2_2653
+sym_2_2653: la $2, sym_2_2653
+.globl sym_2_2654
+sym_2_2654: la $2, sym_2_2654
+.globl sym_2_2655
+sym_2_2655: la $2, sym_2_2655
+.globl sym_2_2656
+sym_2_2656: la $2, sym_2_2656
+.globl sym_2_2657
+sym_2_2657: la $2, sym_2_2657
+.globl sym_2_2658
+sym_2_2658: la $2, sym_2_2658
+.globl sym_2_2659
+sym_2_2659: la $2, sym_2_2659
+.globl sym_2_2660
+sym_2_2660: la $2, sym_2_2660
+.globl sym_2_2661
+sym_2_2661: la $2, sym_2_2661
+.globl sym_2_2662
+sym_2_2662: la $2, sym_2_2662
+.globl sym_2_2663
+sym_2_2663: la $2, sym_2_2663
+.globl sym_2_2664
+sym_2_2664: la $2, sym_2_2664
+.globl sym_2_2665
+sym_2_2665: la $2, sym_2_2665
+.globl sym_2_2666
+sym_2_2666: la $2, sym_2_2666
+.globl sym_2_2667
+sym_2_2667: la $2, sym_2_2667
+.globl sym_2_2668
+sym_2_2668: la $2, sym_2_2668
+.globl sym_2_2669
+sym_2_2669: la $2, sym_2_2669
+.globl sym_2_2670
+sym_2_2670: la $2, sym_2_2670
+.globl sym_2_2671
+sym_2_2671: la $2, sym_2_2671
+.globl sym_2_2672
+sym_2_2672: la $2, sym_2_2672
+.globl sym_2_2673
+sym_2_2673: la $2, sym_2_2673
+.globl sym_2_2674
+sym_2_2674: la $2, sym_2_2674
+.globl sym_2_2675
+sym_2_2675: la $2, sym_2_2675
+.globl sym_2_2676
+sym_2_2676: la $2, sym_2_2676
+.globl sym_2_2677
+sym_2_2677: la $2, sym_2_2677
+.globl sym_2_2678
+sym_2_2678: la $2, sym_2_2678
+.globl sym_2_2679
+sym_2_2679: la $2, sym_2_2679
+.globl sym_2_2680
+sym_2_2680: la $2, sym_2_2680
+.globl sym_2_2681
+sym_2_2681: la $2, sym_2_2681
+.globl sym_2_2682
+sym_2_2682: la $2, sym_2_2682
+.globl sym_2_2683
+sym_2_2683: la $2, sym_2_2683
+.globl sym_2_2684
+sym_2_2684: la $2, sym_2_2684
+.globl sym_2_2685
+sym_2_2685: la $2, sym_2_2685
+.globl sym_2_2686
+sym_2_2686: la $2, sym_2_2686
+.globl sym_2_2687
+sym_2_2687: la $2, sym_2_2687
+.globl sym_2_2688
+sym_2_2688: la $2, sym_2_2688
+.globl sym_2_2689
+sym_2_2689: la $2, sym_2_2689
+.globl sym_2_2690
+sym_2_2690: la $2, sym_2_2690
+.globl sym_2_2691
+sym_2_2691: la $2, sym_2_2691
+.globl sym_2_2692
+sym_2_2692: la $2, sym_2_2692
+.globl sym_2_2693
+sym_2_2693: la $2, sym_2_2693
+.globl sym_2_2694
+sym_2_2694: la $2, sym_2_2694
+.globl sym_2_2695
+sym_2_2695: la $2, sym_2_2695
+.globl sym_2_2696
+sym_2_2696: la $2, sym_2_2696
+.globl sym_2_2697
+sym_2_2697: la $2, sym_2_2697
+.globl sym_2_2698
+sym_2_2698: la $2, sym_2_2698
+.globl sym_2_2699
+sym_2_2699: la $2, sym_2_2699
+.globl sym_2_2700
+sym_2_2700: la $2, sym_2_2700
+.globl sym_2_2701
+sym_2_2701: la $2, sym_2_2701
+.globl sym_2_2702
+sym_2_2702: la $2, sym_2_2702
+.globl sym_2_2703
+sym_2_2703: la $2, sym_2_2703
+.globl sym_2_2704
+sym_2_2704: la $2, sym_2_2704
+.globl sym_2_2705
+sym_2_2705: la $2, sym_2_2705
+.globl sym_2_2706
+sym_2_2706: la $2, sym_2_2706
+.globl sym_2_2707
+sym_2_2707: la $2, sym_2_2707
+.globl sym_2_2708
+sym_2_2708: la $2, sym_2_2708
+.globl sym_2_2709
+sym_2_2709: la $2, sym_2_2709
+.globl sym_2_2710
+sym_2_2710: la $2, sym_2_2710
+.globl sym_2_2711
+sym_2_2711: la $2, sym_2_2711
+.globl sym_2_2712
+sym_2_2712: la $2, sym_2_2712
+.globl sym_2_2713
+sym_2_2713: la $2, sym_2_2713
+.globl sym_2_2714
+sym_2_2714: la $2, sym_2_2714
+.globl sym_2_2715
+sym_2_2715: la $2, sym_2_2715
+.globl sym_2_2716
+sym_2_2716: la $2, sym_2_2716
+.globl sym_2_2717
+sym_2_2717: la $2, sym_2_2717
+.globl sym_2_2718
+sym_2_2718: la $2, sym_2_2718
+.globl sym_2_2719
+sym_2_2719: la $2, sym_2_2719
+.globl sym_2_2720
+sym_2_2720: la $2, sym_2_2720
+.globl sym_2_2721
+sym_2_2721: la $2, sym_2_2721
+.globl sym_2_2722
+sym_2_2722: la $2, sym_2_2722
+.globl sym_2_2723
+sym_2_2723: la $2, sym_2_2723
+.globl sym_2_2724
+sym_2_2724: la $2, sym_2_2724
+.globl sym_2_2725
+sym_2_2725: la $2, sym_2_2725
+.globl sym_2_2726
+sym_2_2726: la $2, sym_2_2726
+.globl sym_2_2727
+sym_2_2727: la $2, sym_2_2727
+.globl sym_2_2728
+sym_2_2728: la $2, sym_2_2728
+.globl sym_2_2729
+sym_2_2729: la $2, sym_2_2729
+.globl sym_2_2730
+sym_2_2730: la $2, sym_2_2730
+.globl sym_2_2731
+sym_2_2731: la $2, sym_2_2731
+.globl sym_2_2732
+sym_2_2732: la $2, sym_2_2732
+.globl sym_2_2733
+sym_2_2733: la $2, sym_2_2733
+.globl sym_2_2734
+sym_2_2734: la $2, sym_2_2734
+.globl sym_2_2735
+sym_2_2735: la $2, sym_2_2735
+.globl sym_2_2736
+sym_2_2736: la $2, sym_2_2736
+.globl sym_2_2737
+sym_2_2737: la $2, sym_2_2737
+.globl sym_2_2738
+sym_2_2738: la $2, sym_2_2738
+.globl sym_2_2739
+sym_2_2739: la $2, sym_2_2739
+.globl sym_2_2740
+sym_2_2740: la $2, sym_2_2740
+.globl sym_2_2741
+sym_2_2741: la $2, sym_2_2741
+.globl sym_2_2742
+sym_2_2742: la $2, sym_2_2742
+.globl sym_2_2743
+sym_2_2743: la $2, sym_2_2743
+.globl sym_2_2744
+sym_2_2744: la $2, sym_2_2744
+.globl sym_2_2745
+sym_2_2745: la $2, sym_2_2745
+.globl sym_2_2746
+sym_2_2746: la $2, sym_2_2746
+.globl sym_2_2747
+sym_2_2747: la $2, sym_2_2747
+.globl sym_2_2748
+sym_2_2748: la $2, sym_2_2748
+.globl sym_2_2749
+sym_2_2749: la $2, sym_2_2749
+.globl sym_2_2750
+sym_2_2750: la $2, sym_2_2750
+.globl sym_2_2751
+sym_2_2751: la $2, sym_2_2751
+.globl sym_2_2752
+sym_2_2752: la $2, sym_2_2752
+.globl sym_2_2753
+sym_2_2753: la $2, sym_2_2753
+.globl sym_2_2754
+sym_2_2754: la $2, sym_2_2754
+.globl sym_2_2755
+sym_2_2755: la $2, sym_2_2755
+.globl sym_2_2756
+sym_2_2756: la $2, sym_2_2756
+.globl sym_2_2757
+sym_2_2757: la $2, sym_2_2757
+.globl sym_2_2758
+sym_2_2758: la $2, sym_2_2758
+.globl sym_2_2759
+sym_2_2759: la $2, sym_2_2759
+.globl sym_2_2760
+sym_2_2760: la $2, sym_2_2760
+.globl sym_2_2761
+sym_2_2761: la $2, sym_2_2761
+.globl sym_2_2762
+sym_2_2762: la $2, sym_2_2762
+.globl sym_2_2763
+sym_2_2763: la $2, sym_2_2763
+.globl sym_2_2764
+sym_2_2764: la $2, sym_2_2764
+.globl sym_2_2765
+sym_2_2765: la $2, sym_2_2765
+.globl sym_2_2766
+sym_2_2766: la $2, sym_2_2766
+.globl sym_2_2767
+sym_2_2767: la $2, sym_2_2767
+.globl sym_2_2768
+sym_2_2768: la $2, sym_2_2768
+.globl sym_2_2769
+sym_2_2769: la $2, sym_2_2769
+.globl sym_2_2770
+sym_2_2770: la $2, sym_2_2770
+.globl sym_2_2771
+sym_2_2771: la $2, sym_2_2771
+.globl sym_2_2772
+sym_2_2772: la $2, sym_2_2772
+.globl sym_2_2773
+sym_2_2773: la $2, sym_2_2773
+.globl sym_2_2774
+sym_2_2774: la $2, sym_2_2774
+.globl sym_2_2775
+sym_2_2775: la $2, sym_2_2775
+.globl sym_2_2776
+sym_2_2776: la $2, sym_2_2776
+.globl sym_2_2777
+sym_2_2777: la $2, sym_2_2777
+.globl sym_2_2778
+sym_2_2778: la $2, sym_2_2778
+.globl sym_2_2779
+sym_2_2779: la $2, sym_2_2779
+.globl sym_2_2780
+sym_2_2780: la $2, sym_2_2780
+.globl sym_2_2781
+sym_2_2781: la $2, sym_2_2781
+.globl sym_2_2782
+sym_2_2782: la $2, sym_2_2782
+.globl sym_2_2783
+sym_2_2783: la $2, sym_2_2783
+.globl sym_2_2784
+sym_2_2784: la $2, sym_2_2784
+.globl sym_2_2785
+sym_2_2785: la $2, sym_2_2785
+.globl sym_2_2786
+sym_2_2786: la $2, sym_2_2786
+.globl sym_2_2787
+sym_2_2787: la $2, sym_2_2787
+.globl sym_2_2788
+sym_2_2788: la $2, sym_2_2788
+.globl sym_2_2789
+sym_2_2789: la $2, sym_2_2789
+.globl sym_2_2790
+sym_2_2790: la $2, sym_2_2790
+.globl sym_2_2791
+sym_2_2791: la $2, sym_2_2791
+.globl sym_2_2792
+sym_2_2792: la $2, sym_2_2792
+.globl sym_2_2793
+sym_2_2793: la $2, sym_2_2793
+.globl sym_2_2794
+sym_2_2794: la $2, sym_2_2794
+.globl sym_2_2795
+sym_2_2795: la $2, sym_2_2795
+.globl sym_2_2796
+sym_2_2796: la $2, sym_2_2796
+.globl sym_2_2797
+sym_2_2797: la $2, sym_2_2797
+.globl sym_2_2798
+sym_2_2798: la $2, sym_2_2798
+.globl sym_2_2799
+sym_2_2799: la $2, sym_2_2799
+.globl sym_2_2800
+sym_2_2800: la $2, sym_2_2800
+.globl sym_2_2801
+sym_2_2801: la $2, sym_2_2801
+.globl sym_2_2802
+sym_2_2802: la $2, sym_2_2802
+.globl sym_2_2803
+sym_2_2803: la $2, sym_2_2803
+.globl sym_2_2804
+sym_2_2804: la $2, sym_2_2804
+.globl sym_2_2805
+sym_2_2805: la $2, sym_2_2805
+.globl sym_2_2806
+sym_2_2806: la $2, sym_2_2806
+.globl sym_2_2807
+sym_2_2807: la $2, sym_2_2807
+.globl sym_2_2808
+sym_2_2808: la $2, sym_2_2808
+.globl sym_2_2809
+sym_2_2809: la $2, sym_2_2809
+.globl sym_2_2810
+sym_2_2810: la $2, sym_2_2810
+.globl sym_2_2811
+sym_2_2811: la $2, sym_2_2811
+.globl sym_2_2812
+sym_2_2812: la $2, sym_2_2812
+.globl sym_2_2813
+sym_2_2813: la $2, sym_2_2813
+.globl sym_2_2814
+sym_2_2814: la $2, sym_2_2814
+.globl sym_2_2815
+sym_2_2815: la $2, sym_2_2815
+.globl sym_2_2816
+sym_2_2816: la $2, sym_2_2816
+.globl sym_2_2817
+sym_2_2817: la $2, sym_2_2817
+.globl sym_2_2818
+sym_2_2818: la $2, sym_2_2818
+.globl sym_2_2819
+sym_2_2819: la $2, sym_2_2819
+.globl sym_2_2820
+sym_2_2820: la $2, sym_2_2820
+.globl sym_2_2821
+sym_2_2821: la $2, sym_2_2821
+.globl sym_2_2822
+sym_2_2822: la $2, sym_2_2822
+.globl sym_2_2823
+sym_2_2823: la $2, sym_2_2823
+.globl sym_2_2824
+sym_2_2824: la $2, sym_2_2824
+.globl sym_2_2825
+sym_2_2825: la $2, sym_2_2825
+.globl sym_2_2826
+sym_2_2826: la $2, sym_2_2826
+.globl sym_2_2827
+sym_2_2827: la $2, sym_2_2827
+.globl sym_2_2828
+sym_2_2828: la $2, sym_2_2828
+.globl sym_2_2829
+sym_2_2829: la $2, sym_2_2829
+.globl sym_2_2830
+sym_2_2830: la $2, sym_2_2830
+.globl sym_2_2831
+sym_2_2831: la $2, sym_2_2831
+.globl sym_2_2832
+sym_2_2832: la $2, sym_2_2832
+.globl sym_2_2833
+sym_2_2833: la $2, sym_2_2833
+.globl sym_2_2834
+sym_2_2834: la $2, sym_2_2834
+.globl sym_2_2835
+sym_2_2835: la $2, sym_2_2835
+.globl sym_2_2836
+sym_2_2836: la $2, sym_2_2836
+.globl sym_2_2837
+sym_2_2837: la $2, sym_2_2837
+.globl sym_2_2838
+sym_2_2838: la $2, sym_2_2838
+.globl sym_2_2839
+sym_2_2839: la $2, sym_2_2839
+.globl sym_2_2840
+sym_2_2840: la $2, sym_2_2840
+.globl sym_2_2841
+sym_2_2841: la $2, sym_2_2841
+.globl sym_2_2842
+sym_2_2842: la $2, sym_2_2842
+.globl sym_2_2843
+sym_2_2843: la $2, sym_2_2843
+.globl sym_2_2844
+sym_2_2844: la $2, sym_2_2844
+.globl sym_2_2845
+sym_2_2845: la $2, sym_2_2845
+.globl sym_2_2846
+sym_2_2846: la $2, sym_2_2846
+.globl sym_2_2847
+sym_2_2847: la $2, sym_2_2847
+.globl sym_2_2848
+sym_2_2848: la $2, sym_2_2848
+.globl sym_2_2849
+sym_2_2849: la $2, sym_2_2849
+.globl sym_2_2850
+sym_2_2850: la $2, sym_2_2850
+.globl sym_2_2851
+sym_2_2851: la $2, sym_2_2851
+.globl sym_2_2852
+sym_2_2852: la $2, sym_2_2852
+.globl sym_2_2853
+sym_2_2853: la $2, sym_2_2853
+.globl sym_2_2854
+sym_2_2854: la $2, sym_2_2854
+.globl sym_2_2855
+sym_2_2855: la $2, sym_2_2855
+.globl sym_2_2856
+sym_2_2856: la $2, sym_2_2856
+.globl sym_2_2857
+sym_2_2857: la $2, sym_2_2857
+.globl sym_2_2858
+sym_2_2858: la $2, sym_2_2858
+.globl sym_2_2859
+sym_2_2859: la $2, sym_2_2859
+.globl sym_2_2860
+sym_2_2860: la $2, sym_2_2860
+.globl sym_2_2861
+sym_2_2861: la $2, sym_2_2861
+.globl sym_2_2862
+sym_2_2862: la $2, sym_2_2862
+.globl sym_2_2863
+sym_2_2863: la $2, sym_2_2863
+.globl sym_2_2864
+sym_2_2864: la $2, sym_2_2864
+.globl sym_2_2865
+sym_2_2865: la $2, sym_2_2865
+.globl sym_2_2866
+sym_2_2866: la $2, sym_2_2866
+.globl sym_2_2867
+sym_2_2867: la $2, sym_2_2867
+.globl sym_2_2868
+sym_2_2868: la $2, sym_2_2868
+.globl sym_2_2869
+sym_2_2869: la $2, sym_2_2869
+.globl sym_2_2870
+sym_2_2870: la $2, sym_2_2870
+.globl sym_2_2871
+sym_2_2871: la $2, sym_2_2871
+.globl sym_2_2872
+sym_2_2872: la $2, sym_2_2872
+.globl sym_2_2873
+sym_2_2873: la $2, sym_2_2873
+.globl sym_2_2874
+sym_2_2874: la $2, sym_2_2874
+.globl sym_2_2875
+sym_2_2875: la $2, sym_2_2875
+.globl sym_2_2876
+sym_2_2876: la $2, sym_2_2876
+.globl sym_2_2877
+sym_2_2877: la $2, sym_2_2877
+.globl sym_2_2878
+sym_2_2878: la $2, sym_2_2878
+.globl sym_2_2879
+sym_2_2879: la $2, sym_2_2879
+.globl sym_2_2880
+sym_2_2880: la $2, sym_2_2880
+.globl sym_2_2881
+sym_2_2881: la $2, sym_2_2881
+.globl sym_2_2882
+sym_2_2882: la $2, sym_2_2882
+.globl sym_2_2883
+sym_2_2883: la $2, sym_2_2883
+.globl sym_2_2884
+sym_2_2884: la $2, sym_2_2884
+.globl sym_2_2885
+sym_2_2885: la $2, sym_2_2885
+.globl sym_2_2886
+sym_2_2886: la $2, sym_2_2886
+.globl sym_2_2887
+sym_2_2887: la $2, sym_2_2887
+.globl sym_2_2888
+sym_2_2888: la $2, sym_2_2888
+.globl sym_2_2889
+sym_2_2889: la $2, sym_2_2889
+.globl sym_2_2890
+sym_2_2890: la $2, sym_2_2890
+.globl sym_2_2891
+sym_2_2891: la $2, sym_2_2891
+.globl sym_2_2892
+sym_2_2892: la $2, sym_2_2892
+.globl sym_2_2893
+sym_2_2893: la $2, sym_2_2893
+.globl sym_2_2894
+sym_2_2894: la $2, sym_2_2894
+.globl sym_2_2895
+sym_2_2895: la $2, sym_2_2895
+.globl sym_2_2896
+sym_2_2896: la $2, sym_2_2896
+.globl sym_2_2897
+sym_2_2897: la $2, sym_2_2897
+.globl sym_2_2898
+sym_2_2898: la $2, sym_2_2898
+.globl sym_2_2899
+sym_2_2899: la $2, sym_2_2899
+.globl sym_2_2900
+sym_2_2900: la $2, sym_2_2900
+.globl sym_2_2901
+sym_2_2901: la $2, sym_2_2901
+.globl sym_2_2902
+sym_2_2902: la $2, sym_2_2902
+.globl sym_2_2903
+sym_2_2903: la $2, sym_2_2903
+.globl sym_2_2904
+sym_2_2904: la $2, sym_2_2904
+.globl sym_2_2905
+sym_2_2905: la $2, sym_2_2905
+.globl sym_2_2906
+sym_2_2906: la $2, sym_2_2906
+.globl sym_2_2907
+sym_2_2907: la $2, sym_2_2907
+.globl sym_2_2908
+sym_2_2908: la $2, sym_2_2908
+.globl sym_2_2909
+sym_2_2909: la $2, sym_2_2909
+.globl sym_2_2910
+sym_2_2910: la $2, sym_2_2910
+.globl sym_2_2911
+sym_2_2911: la $2, sym_2_2911
+.globl sym_2_2912
+sym_2_2912: la $2, sym_2_2912
+.globl sym_2_2913
+sym_2_2913: la $2, sym_2_2913
+.globl sym_2_2914
+sym_2_2914: la $2, sym_2_2914
+.globl sym_2_2915
+sym_2_2915: la $2, sym_2_2915
+.globl sym_2_2916
+sym_2_2916: la $2, sym_2_2916
+.globl sym_2_2917
+sym_2_2917: la $2, sym_2_2917
+.globl sym_2_2918
+sym_2_2918: la $2, sym_2_2918
+.globl sym_2_2919
+sym_2_2919: la $2, sym_2_2919
+.globl sym_2_2920
+sym_2_2920: la $2, sym_2_2920
+.globl sym_2_2921
+sym_2_2921: la $2, sym_2_2921
+.globl sym_2_2922
+sym_2_2922: la $2, sym_2_2922
+.globl sym_2_2923
+sym_2_2923: la $2, sym_2_2923
+.globl sym_2_2924
+sym_2_2924: la $2, sym_2_2924
+.globl sym_2_2925
+sym_2_2925: la $2, sym_2_2925
+.globl sym_2_2926
+sym_2_2926: la $2, sym_2_2926
+.globl sym_2_2927
+sym_2_2927: la $2, sym_2_2927
+.globl sym_2_2928
+sym_2_2928: la $2, sym_2_2928
+.globl sym_2_2929
+sym_2_2929: la $2, sym_2_2929
+.globl sym_2_2930
+sym_2_2930: la $2, sym_2_2930
+.globl sym_2_2931
+sym_2_2931: la $2, sym_2_2931
+.globl sym_2_2932
+sym_2_2932: la $2, sym_2_2932
+.globl sym_2_2933
+sym_2_2933: la $2, sym_2_2933
+.globl sym_2_2934
+sym_2_2934: la $2, sym_2_2934
+.globl sym_2_2935
+sym_2_2935: la $2, sym_2_2935
+.globl sym_2_2936
+sym_2_2936: la $2, sym_2_2936
+.globl sym_2_2937
+sym_2_2937: la $2, sym_2_2937
+.globl sym_2_2938
+sym_2_2938: la $2, sym_2_2938
+.globl sym_2_2939
+sym_2_2939: la $2, sym_2_2939
+.globl sym_2_2940
+sym_2_2940: la $2, sym_2_2940
+.globl sym_2_2941
+sym_2_2941: la $2, sym_2_2941
+.globl sym_2_2942
+sym_2_2942: la $2, sym_2_2942
+.globl sym_2_2943
+sym_2_2943: la $2, sym_2_2943
+.globl sym_2_2944
+sym_2_2944: la $2, sym_2_2944
+.globl sym_2_2945
+sym_2_2945: la $2, sym_2_2945
+.globl sym_2_2946
+sym_2_2946: la $2, sym_2_2946
+.globl sym_2_2947
+sym_2_2947: la $2, sym_2_2947
+.globl sym_2_2948
+sym_2_2948: la $2, sym_2_2948
+.globl sym_2_2949
+sym_2_2949: la $2, sym_2_2949
+.globl sym_2_2950
+sym_2_2950: la $2, sym_2_2950
+.globl sym_2_2951
+sym_2_2951: la $2, sym_2_2951
+.globl sym_2_2952
+sym_2_2952: la $2, sym_2_2952
+.globl sym_2_2953
+sym_2_2953: la $2, sym_2_2953
+.globl sym_2_2954
+sym_2_2954: la $2, sym_2_2954
+.globl sym_2_2955
+sym_2_2955: la $2, sym_2_2955
+.globl sym_2_2956
+sym_2_2956: la $2, sym_2_2956
+.globl sym_2_2957
+sym_2_2957: la $2, sym_2_2957
+.globl sym_2_2958
+sym_2_2958: la $2, sym_2_2958
+.globl sym_2_2959
+sym_2_2959: la $2, sym_2_2959
+.globl sym_2_2960
+sym_2_2960: la $2, sym_2_2960
+.globl sym_2_2961
+sym_2_2961: la $2, sym_2_2961
+.globl sym_2_2962
+sym_2_2962: la $2, sym_2_2962
+.globl sym_2_2963
+sym_2_2963: la $2, sym_2_2963
+.globl sym_2_2964
+sym_2_2964: la $2, sym_2_2964
+.globl sym_2_2965
+sym_2_2965: la $2, sym_2_2965
+.globl sym_2_2966
+sym_2_2966: la $2, sym_2_2966
+.globl sym_2_2967
+sym_2_2967: la $2, sym_2_2967
+.globl sym_2_2968
+sym_2_2968: la $2, sym_2_2968
+.globl sym_2_2969
+sym_2_2969: la $2, sym_2_2969
+.globl sym_2_2970
+sym_2_2970: la $2, sym_2_2970
+.globl sym_2_2971
+sym_2_2971: la $2, sym_2_2971
+.globl sym_2_2972
+sym_2_2972: la $2, sym_2_2972
+.globl sym_2_2973
+sym_2_2973: la $2, sym_2_2973
+.globl sym_2_2974
+sym_2_2974: la $2, sym_2_2974
+.globl sym_2_2975
+sym_2_2975: la $2, sym_2_2975
+.globl sym_2_2976
+sym_2_2976: la $2, sym_2_2976
+.globl sym_2_2977
+sym_2_2977: la $2, sym_2_2977
+.globl sym_2_2978
+sym_2_2978: la $2, sym_2_2978
+.globl sym_2_2979
+sym_2_2979: la $2, sym_2_2979
+.globl sym_2_2980
+sym_2_2980: la $2, sym_2_2980
+.globl sym_2_2981
+sym_2_2981: la $2, sym_2_2981
+.globl sym_2_2982
+sym_2_2982: la $2, sym_2_2982
+.globl sym_2_2983
+sym_2_2983: la $2, sym_2_2983
+.globl sym_2_2984
+sym_2_2984: la $2, sym_2_2984
+.globl sym_2_2985
+sym_2_2985: la $2, sym_2_2985
+.globl sym_2_2986
+sym_2_2986: la $2, sym_2_2986
+.globl sym_2_2987
+sym_2_2987: la $2, sym_2_2987
+.globl sym_2_2988
+sym_2_2988: la $2, sym_2_2988
+.globl sym_2_2989
+sym_2_2989: la $2, sym_2_2989
+.globl sym_2_2990
+sym_2_2990: la $2, sym_2_2990
+.globl sym_2_2991
+sym_2_2991: la $2, sym_2_2991
+.globl sym_2_2992
+sym_2_2992: la $2, sym_2_2992
+.globl sym_2_2993
+sym_2_2993: la $2, sym_2_2993
+.globl sym_2_2994
+sym_2_2994: la $2, sym_2_2994
+.globl sym_2_2995
+sym_2_2995: la $2, sym_2_2995
+.globl sym_2_2996
+sym_2_2996: la $2, sym_2_2996
+.globl sym_2_2997
+sym_2_2997: la $2, sym_2_2997
+.globl sym_2_2998
+sym_2_2998: la $2, sym_2_2998
+.globl sym_2_2999
+sym_2_2999: la $2, sym_2_2999
+.globl sym_2_3000
+sym_2_3000: la $2, sym_2_3000
+.globl sym_2_3001
+sym_2_3001: la $2, sym_2_3001
+.globl sym_2_3002
+sym_2_3002: la $2, sym_2_3002
+.globl sym_2_3003
+sym_2_3003: la $2, sym_2_3003
+.globl sym_2_3004
+sym_2_3004: la $2, sym_2_3004
+.globl sym_2_3005
+sym_2_3005: la $2, sym_2_3005
+.globl sym_2_3006
+sym_2_3006: la $2, sym_2_3006
+.globl sym_2_3007
+sym_2_3007: la $2, sym_2_3007
+.globl sym_2_3008
+sym_2_3008: la $2, sym_2_3008
+.globl sym_2_3009
+sym_2_3009: la $2, sym_2_3009
+.globl sym_2_3010
+sym_2_3010: la $2, sym_2_3010
+.globl sym_2_3011
+sym_2_3011: la $2, sym_2_3011
+.globl sym_2_3012
+sym_2_3012: la $2, sym_2_3012
+.globl sym_2_3013
+sym_2_3013: la $2, sym_2_3013
+.globl sym_2_3014
+sym_2_3014: la $2, sym_2_3014
+.globl sym_2_3015
+sym_2_3015: la $2, sym_2_3015
+.globl sym_2_3016
+sym_2_3016: la $2, sym_2_3016
+.globl sym_2_3017
+sym_2_3017: la $2, sym_2_3017
+.globl sym_2_3018
+sym_2_3018: la $2, sym_2_3018
+.globl sym_2_3019
+sym_2_3019: la $2, sym_2_3019
+.globl sym_2_3020
+sym_2_3020: la $2, sym_2_3020
+.globl sym_2_3021
+sym_2_3021: la $2, sym_2_3021
+.globl sym_2_3022
+sym_2_3022: la $2, sym_2_3022
+.globl sym_2_3023
+sym_2_3023: la $2, sym_2_3023
+.globl sym_2_3024
+sym_2_3024: la $2, sym_2_3024
+.globl sym_2_3025
+sym_2_3025: la $2, sym_2_3025
+.globl sym_2_3026
+sym_2_3026: la $2, sym_2_3026
+.globl sym_2_3027
+sym_2_3027: la $2, sym_2_3027
+.globl sym_2_3028
+sym_2_3028: la $2, sym_2_3028
+.globl sym_2_3029
+sym_2_3029: la $2, sym_2_3029
+.globl sym_2_3030
+sym_2_3030: la $2, sym_2_3030
+.globl sym_2_3031
+sym_2_3031: la $2, sym_2_3031
+.globl sym_2_3032
+sym_2_3032: la $2, sym_2_3032
+.globl sym_2_3033
+sym_2_3033: la $2, sym_2_3033
+.globl sym_2_3034
+sym_2_3034: la $2, sym_2_3034
+.globl sym_2_3035
+sym_2_3035: la $2, sym_2_3035
+.globl sym_2_3036
+sym_2_3036: la $2, sym_2_3036
+.globl sym_2_3037
+sym_2_3037: la $2, sym_2_3037
+.globl sym_2_3038
+sym_2_3038: la $2, sym_2_3038
+.globl sym_2_3039
+sym_2_3039: la $2, sym_2_3039
+.globl sym_2_3040
+sym_2_3040: la $2, sym_2_3040
+.globl sym_2_3041
+sym_2_3041: la $2, sym_2_3041
+.globl sym_2_3042
+sym_2_3042: la $2, sym_2_3042
+.globl sym_2_3043
+sym_2_3043: la $2, sym_2_3043
+.globl sym_2_3044
+sym_2_3044: la $2, sym_2_3044
+.globl sym_2_3045
+sym_2_3045: la $2, sym_2_3045
+.globl sym_2_3046
+sym_2_3046: la $2, sym_2_3046
+.globl sym_2_3047
+sym_2_3047: la $2, sym_2_3047
+.globl sym_2_3048
+sym_2_3048: la $2, sym_2_3048
+.globl sym_2_3049
+sym_2_3049: la $2, sym_2_3049
+.globl sym_2_3050
+sym_2_3050: la $2, sym_2_3050
+.globl sym_2_3051
+sym_2_3051: la $2, sym_2_3051
+.globl sym_2_3052
+sym_2_3052: la $2, sym_2_3052
+.globl sym_2_3053
+sym_2_3053: la $2, sym_2_3053
+.globl sym_2_3054
+sym_2_3054: la $2, sym_2_3054
+.globl sym_2_3055
+sym_2_3055: la $2, sym_2_3055
+.globl sym_2_3056
+sym_2_3056: la $2, sym_2_3056
+.globl sym_2_3057
+sym_2_3057: la $2, sym_2_3057
+.globl sym_2_3058
+sym_2_3058: la $2, sym_2_3058
+.globl sym_2_3059
+sym_2_3059: la $2, sym_2_3059
+.globl sym_2_3060
+sym_2_3060: la $2, sym_2_3060
+.globl sym_2_3061
+sym_2_3061: la $2, sym_2_3061
+.globl sym_2_3062
+sym_2_3062: la $2, sym_2_3062
+.globl sym_2_3063
+sym_2_3063: la $2, sym_2_3063
+.globl sym_2_3064
+sym_2_3064: la $2, sym_2_3064
+.globl sym_2_3065
+sym_2_3065: la $2, sym_2_3065
+.globl sym_2_3066
+sym_2_3066: la $2, sym_2_3066
+.globl sym_2_3067
+sym_2_3067: la $2, sym_2_3067
+.globl sym_2_3068
+sym_2_3068: la $2, sym_2_3068
+.globl sym_2_3069
+sym_2_3069: la $2, sym_2_3069
+.globl sym_2_3070
+sym_2_3070: la $2, sym_2_3070
+.globl sym_2_3071
+sym_2_3071: la $2, sym_2_3071
+.globl sym_2_3072
+sym_2_3072: la $2, sym_2_3072
+.globl sym_2_3073
+sym_2_3073: la $2, sym_2_3073
+.globl sym_2_3074
+sym_2_3074: la $2, sym_2_3074
+.globl sym_2_3075
+sym_2_3075: la $2, sym_2_3075
+.globl sym_2_3076
+sym_2_3076: la $2, sym_2_3076
+.globl sym_2_3077
+sym_2_3077: la $2, sym_2_3077
+.globl sym_2_3078
+sym_2_3078: la $2, sym_2_3078
+.globl sym_2_3079
+sym_2_3079: la $2, sym_2_3079
+.globl sym_2_3080
+sym_2_3080: la $2, sym_2_3080
+.globl sym_2_3081
+sym_2_3081: la $2, sym_2_3081
+.globl sym_2_3082
+sym_2_3082: la $2, sym_2_3082
+.globl sym_2_3083
+sym_2_3083: la $2, sym_2_3083
+.globl sym_2_3084
+sym_2_3084: la $2, sym_2_3084
+.globl sym_2_3085
+sym_2_3085: la $2, sym_2_3085
+.globl sym_2_3086
+sym_2_3086: la $2, sym_2_3086
+.globl sym_2_3087
+sym_2_3087: la $2, sym_2_3087
+.globl sym_2_3088
+sym_2_3088: la $2, sym_2_3088
+.globl sym_2_3089
+sym_2_3089: la $2, sym_2_3089
+.globl sym_2_3090
+sym_2_3090: la $2, sym_2_3090
+.globl sym_2_3091
+sym_2_3091: la $2, sym_2_3091
+.globl sym_2_3092
+sym_2_3092: la $2, sym_2_3092
+.globl sym_2_3093
+sym_2_3093: la $2, sym_2_3093
+.globl sym_2_3094
+sym_2_3094: la $2, sym_2_3094
+.globl sym_2_3095
+sym_2_3095: la $2, sym_2_3095
+.globl sym_2_3096
+sym_2_3096: la $2, sym_2_3096
+.globl sym_2_3097
+sym_2_3097: la $2, sym_2_3097
+.globl sym_2_3098
+sym_2_3098: la $2, sym_2_3098
+.globl sym_2_3099
+sym_2_3099: la $2, sym_2_3099
+.globl sym_2_3100
+sym_2_3100: la $2, sym_2_3100
+.globl sym_2_3101
+sym_2_3101: la $2, sym_2_3101
+.globl sym_2_3102
+sym_2_3102: la $2, sym_2_3102
+.globl sym_2_3103
+sym_2_3103: la $2, sym_2_3103
+.globl sym_2_3104
+sym_2_3104: la $2, sym_2_3104
+.globl sym_2_3105
+sym_2_3105: la $2, sym_2_3105
+.globl sym_2_3106
+sym_2_3106: la $2, sym_2_3106
+.globl sym_2_3107
+sym_2_3107: la $2, sym_2_3107
+.globl sym_2_3108
+sym_2_3108: la $2, sym_2_3108
+.globl sym_2_3109
+sym_2_3109: la $2, sym_2_3109
+.globl sym_2_3110
+sym_2_3110: la $2, sym_2_3110
+.globl sym_2_3111
+sym_2_3111: la $2, sym_2_3111
+.globl sym_2_3112
+sym_2_3112: la $2, sym_2_3112
+.globl sym_2_3113
+sym_2_3113: la $2, sym_2_3113
+.globl sym_2_3114
+sym_2_3114: la $2, sym_2_3114
+.globl sym_2_3115
+sym_2_3115: la $2, sym_2_3115
+.globl sym_2_3116
+sym_2_3116: la $2, sym_2_3116
+.globl sym_2_3117
+sym_2_3117: la $2, sym_2_3117
+.globl sym_2_3118
+sym_2_3118: la $2, sym_2_3118
+.globl sym_2_3119
+sym_2_3119: la $2, sym_2_3119
+.globl sym_2_3120
+sym_2_3120: la $2, sym_2_3120
+.globl sym_2_3121
+sym_2_3121: la $2, sym_2_3121
+.globl sym_2_3122
+sym_2_3122: la $2, sym_2_3122
+.globl sym_2_3123
+sym_2_3123: la $2, sym_2_3123
+.globl sym_2_3124
+sym_2_3124: la $2, sym_2_3124
+.globl sym_2_3125
+sym_2_3125: la $2, sym_2_3125
+.globl sym_2_3126
+sym_2_3126: la $2, sym_2_3126
+.globl sym_2_3127
+sym_2_3127: la $2, sym_2_3127
+.globl sym_2_3128
+sym_2_3128: la $2, sym_2_3128
+.globl sym_2_3129
+sym_2_3129: la $2, sym_2_3129
+.globl sym_2_3130
+sym_2_3130: la $2, sym_2_3130
+.globl sym_2_3131
+sym_2_3131: la $2, sym_2_3131
+.globl sym_2_3132
+sym_2_3132: la $2, sym_2_3132
+.globl sym_2_3133
+sym_2_3133: la $2, sym_2_3133
+.globl sym_2_3134
+sym_2_3134: la $2, sym_2_3134
+.globl sym_2_3135
+sym_2_3135: la $2, sym_2_3135
+.globl sym_2_3136
+sym_2_3136: la $2, sym_2_3136
+.globl sym_2_3137
+sym_2_3137: la $2, sym_2_3137
+.globl sym_2_3138
+sym_2_3138: la $2, sym_2_3138
+.globl sym_2_3139
+sym_2_3139: la $2, sym_2_3139
+.globl sym_2_3140
+sym_2_3140: la $2, sym_2_3140
+.globl sym_2_3141
+sym_2_3141: la $2, sym_2_3141
+.globl sym_2_3142
+sym_2_3142: la $2, sym_2_3142
+.globl sym_2_3143
+sym_2_3143: la $2, sym_2_3143
+.globl sym_2_3144
+sym_2_3144: la $2, sym_2_3144
+.globl sym_2_3145
+sym_2_3145: la $2, sym_2_3145
+.globl sym_2_3146
+sym_2_3146: la $2, sym_2_3146
+.globl sym_2_3147
+sym_2_3147: la $2, sym_2_3147
+.globl sym_2_3148
+sym_2_3148: la $2, sym_2_3148
+.globl sym_2_3149
+sym_2_3149: la $2, sym_2_3149
+.globl sym_2_3150
+sym_2_3150: la $2, sym_2_3150
+.globl sym_2_3151
+sym_2_3151: la $2, sym_2_3151
+.globl sym_2_3152
+sym_2_3152: la $2, sym_2_3152
+.globl sym_2_3153
+sym_2_3153: la $2, sym_2_3153
+.globl sym_2_3154
+sym_2_3154: la $2, sym_2_3154
+.globl sym_2_3155
+sym_2_3155: la $2, sym_2_3155
+.globl sym_2_3156
+sym_2_3156: la $2, sym_2_3156
+.globl sym_2_3157
+sym_2_3157: la $2, sym_2_3157
+.globl sym_2_3158
+sym_2_3158: la $2, sym_2_3158
+.globl sym_2_3159
+sym_2_3159: la $2, sym_2_3159
+.globl sym_2_3160
+sym_2_3160: la $2, sym_2_3160
+.globl sym_2_3161
+sym_2_3161: la $2, sym_2_3161
+.globl sym_2_3162
+sym_2_3162: la $2, sym_2_3162
+.globl sym_2_3163
+sym_2_3163: la $2, sym_2_3163
+.globl sym_2_3164
+sym_2_3164: la $2, sym_2_3164
+.globl sym_2_3165
+sym_2_3165: la $2, sym_2_3165
+.globl sym_2_3166
+sym_2_3166: la $2, sym_2_3166
+.globl sym_2_3167
+sym_2_3167: la $2, sym_2_3167
+.globl sym_2_3168
+sym_2_3168: la $2, sym_2_3168
+.globl sym_2_3169
+sym_2_3169: la $2, sym_2_3169
+.globl sym_2_3170
+sym_2_3170: la $2, sym_2_3170
+.globl sym_2_3171
+sym_2_3171: la $2, sym_2_3171
+.globl sym_2_3172
+sym_2_3172: la $2, sym_2_3172
+.globl sym_2_3173
+sym_2_3173: la $2, sym_2_3173
+.globl sym_2_3174
+sym_2_3174: la $2, sym_2_3174
+.globl sym_2_3175
+sym_2_3175: la $2, sym_2_3175
+.globl sym_2_3176
+sym_2_3176: la $2, sym_2_3176
+.globl sym_2_3177
+sym_2_3177: la $2, sym_2_3177
+.globl sym_2_3178
+sym_2_3178: la $2, sym_2_3178
+.globl sym_2_3179
+sym_2_3179: la $2, sym_2_3179
+.globl sym_2_3180
+sym_2_3180: la $2, sym_2_3180
+.globl sym_2_3181
+sym_2_3181: la $2, sym_2_3181
+.globl sym_2_3182
+sym_2_3182: la $2, sym_2_3182
+.globl sym_2_3183
+sym_2_3183: la $2, sym_2_3183
+.globl sym_2_3184
+sym_2_3184: la $2, sym_2_3184
+.globl sym_2_3185
+sym_2_3185: la $2, sym_2_3185
+.globl sym_2_3186
+sym_2_3186: la $2, sym_2_3186
+.globl sym_2_3187
+sym_2_3187: la $2, sym_2_3187
+.globl sym_2_3188
+sym_2_3188: la $2, sym_2_3188
+.globl sym_2_3189
+sym_2_3189: la $2, sym_2_3189
+.globl sym_2_3190
+sym_2_3190: la $2, sym_2_3190
+.globl sym_2_3191
+sym_2_3191: la $2, sym_2_3191
+.globl sym_2_3192
+sym_2_3192: la $2, sym_2_3192
+.globl sym_2_3193
+sym_2_3193: la $2, sym_2_3193
+.globl sym_2_3194
+sym_2_3194: la $2, sym_2_3194
+.globl sym_2_3195
+sym_2_3195: la $2, sym_2_3195
+.globl sym_2_3196
+sym_2_3196: la $2, sym_2_3196
+.globl sym_2_3197
+sym_2_3197: la $2, sym_2_3197
+.globl sym_2_3198
+sym_2_3198: la $2, sym_2_3198
+.globl sym_2_3199
+sym_2_3199: la $2, sym_2_3199
+.globl sym_2_3200
+sym_2_3200: la $2, sym_2_3200
+.globl sym_2_3201
+sym_2_3201: la $2, sym_2_3201
+.globl sym_2_3202
+sym_2_3202: la $2, sym_2_3202
+.globl sym_2_3203
+sym_2_3203: la $2, sym_2_3203
+.globl sym_2_3204
+sym_2_3204: la $2, sym_2_3204
+.globl sym_2_3205
+sym_2_3205: la $2, sym_2_3205
+.globl sym_2_3206
+sym_2_3206: la $2, sym_2_3206
+.globl sym_2_3207
+sym_2_3207: la $2, sym_2_3207
+.globl sym_2_3208
+sym_2_3208: la $2, sym_2_3208
+.globl sym_2_3209
+sym_2_3209: la $2, sym_2_3209
+.globl sym_2_3210
+sym_2_3210: la $2, sym_2_3210
+.globl sym_2_3211
+sym_2_3211: la $2, sym_2_3211
+.globl sym_2_3212
+sym_2_3212: la $2, sym_2_3212
+.globl sym_2_3213
+sym_2_3213: la $2, sym_2_3213
+.globl sym_2_3214
+sym_2_3214: la $2, sym_2_3214
+.globl sym_2_3215
+sym_2_3215: la $2, sym_2_3215
+.globl sym_2_3216
+sym_2_3216: la $2, sym_2_3216
+.globl sym_2_3217
+sym_2_3217: la $2, sym_2_3217
+.globl sym_2_3218
+sym_2_3218: la $2, sym_2_3218
+.globl sym_2_3219
+sym_2_3219: la $2, sym_2_3219
+.globl sym_2_3220
+sym_2_3220: la $2, sym_2_3220
+.globl sym_2_3221
+sym_2_3221: la $2, sym_2_3221
+.globl sym_2_3222
+sym_2_3222: la $2, sym_2_3222
+.globl sym_2_3223
+sym_2_3223: la $2, sym_2_3223
+.globl sym_2_3224
+sym_2_3224: la $2, sym_2_3224
+.globl sym_2_3225
+sym_2_3225: la $2, sym_2_3225
+.globl sym_2_3226
+sym_2_3226: la $2, sym_2_3226
+.globl sym_2_3227
+sym_2_3227: la $2, sym_2_3227
+.globl sym_2_3228
+sym_2_3228: la $2, sym_2_3228
+.globl sym_2_3229
+sym_2_3229: la $2, sym_2_3229
+.globl sym_2_3230
+sym_2_3230: la $2, sym_2_3230
+.globl sym_2_3231
+sym_2_3231: la $2, sym_2_3231
+.globl sym_2_3232
+sym_2_3232: la $2, sym_2_3232
+.globl sym_2_3233
+sym_2_3233: la $2, sym_2_3233
+.globl sym_2_3234
+sym_2_3234: la $2, sym_2_3234
+.globl sym_2_3235
+sym_2_3235: la $2, sym_2_3235
+.globl sym_2_3236
+sym_2_3236: la $2, sym_2_3236
+.globl sym_2_3237
+sym_2_3237: la $2, sym_2_3237
+.globl sym_2_3238
+sym_2_3238: la $2, sym_2_3238
+.globl sym_2_3239
+sym_2_3239: la $2, sym_2_3239
+.globl sym_2_3240
+sym_2_3240: la $2, sym_2_3240
+.globl sym_2_3241
+sym_2_3241: la $2, sym_2_3241
+.globl sym_2_3242
+sym_2_3242: la $2, sym_2_3242
+.globl sym_2_3243
+sym_2_3243: la $2, sym_2_3243
+.globl sym_2_3244
+sym_2_3244: la $2, sym_2_3244
+.globl sym_2_3245
+sym_2_3245: la $2, sym_2_3245
+.globl sym_2_3246
+sym_2_3246: la $2, sym_2_3246
+.globl sym_2_3247
+sym_2_3247: la $2, sym_2_3247
+.globl sym_2_3248
+sym_2_3248: la $2, sym_2_3248
+.globl sym_2_3249
+sym_2_3249: la $2, sym_2_3249
+.globl sym_2_3250
+sym_2_3250: la $2, sym_2_3250
+.globl sym_2_3251
+sym_2_3251: la $2, sym_2_3251
+.globl sym_2_3252
+sym_2_3252: la $2, sym_2_3252
+.globl sym_2_3253
+sym_2_3253: la $2, sym_2_3253
+.globl sym_2_3254
+sym_2_3254: la $2, sym_2_3254
+.globl sym_2_3255
+sym_2_3255: la $2, sym_2_3255
+.globl sym_2_3256
+sym_2_3256: la $2, sym_2_3256
+.globl sym_2_3257
+sym_2_3257: la $2, sym_2_3257
+.globl sym_2_3258
+sym_2_3258: la $2, sym_2_3258
+.globl sym_2_3259
+sym_2_3259: la $2, sym_2_3259
+.globl sym_2_3260
+sym_2_3260: la $2, sym_2_3260
+.globl sym_2_3261
+sym_2_3261: la $2, sym_2_3261
+.globl sym_2_3262
+sym_2_3262: la $2, sym_2_3262
+.globl sym_2_3263
+sym_2_3263: la $2, sym_2_3263
+.globl sym_2_3264
+sym_2_3264: la $2, sym_2_3264
+.globl sym_2_3265
+sym_2_3265: la $2, sym_2_3265
+.globl sym_2_3266
+sym_2_3266: la $2, sym_2_3266
+.globl sym_2_3267
+sym_2_3267: la $2, sym_2_3267
+.globl sym_2_3268
+sym_2_3268: la $2, sym_2_3268
+.globl sym_2_3269
+sym_2_3269: la $2, sym_2_3269
+.globl sym_2_3270
+sym_2_3270: la $2, sym_2_3270
+.globl sym_2_3271
+sym_2_3271: la $2, sym_2_3271
+.globl sym_2_3272
+sym_2_3272: la $2, sym_2_3272
+.globl sym_2_3273
+sym_2_3273: la $2, sym_2_3273
+.globl sym_2_3274
+sym_2_3274: la $2, sym_2_3274
+.globl sym_2_3275
+sym_2_3275: la $2, sym_2_3275
+.globl sym_2_3276
+sym_2_3276: la $2, sym_2_3276
+.globl sym_2_3277
+sym_2_3277: la $2, sym_2_3277
+.globl sym_2_3278
+sym_2_3278: la $2, sym_2_3278
+.globl sym_2_3279
+sym_2_3279: la $2, sym_2_3279
+.globl sym_2_3280
+sym_2_3280: la $2, sym_2_3280
+.globl sym_2_3281
+sym_2_3281: la $2, sym_2_3281
+.globl sym_2_3282
+sym_2_3282: la $2, sym_2_3282
+.globl sym_2_3283
+sym_2_3283: la $2, sym_2_3283
+.globl sym_2_3284
+sym_2_3284: la $2, sym_2_3284
+.globl sym_2_3285
+sym_2_3285: la $2, sym_2_3285
+.globl sym_2_3286
+sym_2_3286: la $2, sym_2_3286
+.globl sym_2_3287
+sym_2_3287: la $2, sym_2_3287
+.globl sym_2_3288
+sym_2_3288: la $2, sym_2_3288
+.globl sym_2_3289
+sym_2_3289: la $2, sym_2_3289
+.globl sym_2_3290
+sym_2_3290: la $2, sym_2_3290
+.globl sym_2_3291
+sym_2_3291: la $2, sym_2_3291
+.globl sym_2_3292
+sym_2_3292: la $2, sym_2_3292
+.globl sym_2_3293
+sym_2_3293: la $2, sym_2_3293
+.globl sym_2_3294
+sym_2_3294: la $2, sym_2_3294
+.globl sym_2_3295
+sym_2_3295: la $2, sym_2_3295
+.globl sym_2_3296
+sym_2_3296: la $2, sym_2_3296
+.globl sym_2_3297
+sym_2_3297: la $2, sym_2_3297
+.globl sym_2_3298
+sym_2_3298: la $2, sym_2_3298
+.globl sym_2_3299
+sym_2_3299: la $2, sym_2_3299
+.globl sym_2_3300
+sym_2_3300: la $2, sym_2_3300
+.globl sym_2_3301
+sym_2_3301: la $2, sym_2_3301
+.globl sym_2_3302
+sym_2_3302: la $2, sym_2_3302
+.globl sym_2_3303
+sym_2_3303: la $2, sym_2_3303
+.globl sym_2_3304
+sym_2_3304: la $2, sym_2_3304
+.globl sym_2_3305
+sym_2_3305: la $2, sym_2_3305
+.globl sym_2_3306
+sym_2_3306: la $2, sym_2_3306
+.globl sym_2_3307
+sym_2_3307: la $2, sym_2_3307
+.globl sym_2_3308
+sym_2_3308: la $2, sym_2_3308
+.globl sym_2_3309
+sym_2_3309: la $2, sym_2_3309
+.globl sym_2_3310
+sym_2_3310: la $2, sym_2_3310
+.globl sym_2_3311
+sym_2_3311: la $2, sym_2_3311
+.globl sym_2_3312
+sym_2_3312: la $2, sym_2_3312
+.globl sym_2_3313
+sym_2_3313: la $2, sym_2_3313
+.globl sym_2_3314
+sym_2_3314: la $2, sym_2_3314
+.globl sym_2_3315
+sym_2_3315: la $2, sym_2_3315
+.globl sym_2_3316
+sym_2_3316: la $2, sym_2_3316
+.globl sym_2_3317
+sym_2_3317: la $2, sym_2_3317
+.globl sym_2_3318
+sym_2_3318: la $2, sym_2_3318
+.globl sym_2_3319
+sym_2_3319: la $2, sym_2_3319
+.globl sym_2_3320
+sym_2_3320: la $2, sym_2_3320
+.globl sym_2_3321
+sym_2_3321: la $2, sym_2_3321
+.globl sym_2_3322
+sym_2_3322: la $2, sym_2_3322
+.globl sym_2_3323
+sym_2_3323: la $2, sym_2_3323
+.globl sym_2_3324
+sym_2_3324: la $2, sym_2_3324
+.globl sym_2_3325
+sym_2_3325: la $2, sym_2_3325
+.globl sym_2_3326
+sym_2_3326: la $2, sym_2_3326
+.globl sym_2_3327
+sym_2_3327: la $2, sym_2_3327
+.globl sym_2_3328
+sym_2_3328: la $2, sym_2_3328
+.globl sym_2_3329
+sym_2_3329: la $2, sym_2_3329
+.globl sym_2_3330
+sym_2_3330: la $2, sym_2_3330
+.globl sym_2_3331
+sym_2_3331: la $2, sym_2_3331
+.globl sym_2_3332
+sym_2_3332: la $2, sym_2_3332
+.globl sym_2_3333
+sym_2_3333: la $2, sym_2_3333
+.globl sym_2_3334
+sym_2_3334: la $2, sym_2_3334
+.globl sym_2_3335
+sym_2_3335: la $2, sym_2_3335
+.globl sym_2_3336
+sym_2_3336: la $2, sym_2_3336
+.globl sym_2_3337
+sym_2_3337: la $2, sym_2_3337
+.globl sym_2_3338
+sym_2_3338: la $2, sym_2_3338
+.globl sym_2_3339
+sym_2_3339: la $2, sym_2_3339
+.globl sym_2_3340
+sym_2_3340: la $2, sym_2_3340
+.globl sym_2_3341
+sym_2_3341: la $2, sym_2_3341
+.globl sym_2_3342
+sym_2_3342: la $2, sym_2_3342
+.globl sym_2_3343
+sym_2_3343: la $2, sym_2_3343
+.globl sym_2_3344
+sym_2_3344: la $2, sym_2_3344
+.globl sym_2_3345
+sym_2_3345: la $2, sym_2_3345
+.globl sym_2_3346
+sym_2_3346: la $2, sym_2_3346
+.globl sym_2_3347
+sym_2_3347: la $2, sym_2_3347
+.globl sym_2_3348
+sym_2_3348: la $2, sym_2_3348
+.globl sym_2_3349
+sym_2_3349: la $2, sym_2_3349
+.globl sym_2_3350
+sym_2_3350: la $2, sym_2_3350
+.globl sym_2_3351
+sym_2_3351: la $2, sym_2_3351
+.globl sym_2_3352
+sym_2_3352: la $2, sym_2_3352
+.globl sym_2_3353
+sym_2_3353: la $2, sym_2_3353
+.globl sym_2_3354
+sym_2_3354: la $2, sym_2_3354
+.globl sym_2_3355
+sym_2_3355: la $2, sym_2_3355
+.globl sym_2_3356
+sym_2_3356: la $2, sym_2_3356
+.globl sym_2_3357
+sym_2_3357: la $2, sym_2_3357
+.globl sym_2_3358
+sym_2_3358: la $2, sym_2_3358
+.globl sym_2_3359
+sym_2_3359: la $2, sym_2_3359
+.globl sym_2_3360
+sym_2_3360: la $2, sym_2_3360
+.globl sym_2_3361
+sym_2_3361: la $2, sym_2_3361
+.globl sym_2_3362
+sym_2_3362: la $2, sym_2_3362
+.globl sym_2_3363
+sym_2_3363: la $2, sym_2_3363
+.globl sym_2_3364
+sym_2_3364: la $2, sym_2_3364
+.globl sym_2_3365
+sym_2_3365: la $2, sym_2_3365
+.globl sym_2_3366
+sym_2_3366: la $2, sym_2_3366
+.globl sym_2_3367
+sym_2_3367: la $2, sym_2_3367
+.globl sym_2_3368
+sym_2_3368: la $2, sym_2_3368
+.globl sym_2_3369
+sym_2_3369: la $2, sym_2_3369
+.globl sym_2_3370
+sym_2_3370: la $2, sym_2_3370
+.globl sym_2_3371
+sym_2_3371: la $2, sym_2_3371
+.globl sym_2_3372
+sym_2_3372: la $2, sym_2_3372
+.globl sym_2_3373
+sym_2_3373: la $2, sym_2_3373
+.globl sym_2_3374
+sym_2_3374: la $2, sym_2_3374
+.globl sym_2_3375
+sym_2_3375: la $2, sym_2_3375
+.globl sym_2_3376
+sym_2_3376: la $2, sym_2_3376
+.globl sym_2_3377
+sym_2_3377: la $2, sym_2_3377
+.globl sym_2_3378
+sym_2_3378: la $2, sym_2_3378
+.globl sym_2_3379
+sym_2_3379: la $2, sym_2_3379
+.globl sym_2_3380
+sym_2_3380: la $2, sym_2_3380
+.globl sym_2_3381
+sym_2_3381: la $2, sym_2_3381
+.globl sym_2_3382
+sym_2_3382: la $2, sym_2_3382
+.globl sym_2_3383
+sym_2_3383: la $2, sym_2_3383
+.globl sym_2_3384
+sym_2_3384: la $2, sym_2_3384
+.globl sym_2_3385
+sym_2_3385: la $2, sym_2_3385
+.globl sym_2_3386
+sym_2_3386: la $2, sym_2_3386
+.globl sym_2_3387
+sym_2_3387: la $2, sym_2_3387
+.globl sym_2_3388
+sym_2_3388: la $2, sym_2_3388
+.globl sym_2_3389
+sym_2_3389: la $2, sym_2_3389
+.globl sym_2_3390
+sym_2_3390: la $2, sym_2_3390
+.globl sym_2_3391
+sym_2_3391: la $2, sym_2_3391
+.globl sym_2_3392
+sym_2_3392: la $2, sym_2_3392
+.globl sym_2_3393
+sym_2_3393: la $2, sym_2_3393
+.globl sym_2_3394
+sym_2_3394: la $2, sym_2_3394
+.globl sym_2_3395
+sym_2_3395: la $2, sym_2_3395
+.globl sym_2_3396
+sym_2_3396: la $2, sym_2_3396
+.globl sym_2_3397
+sym_2_3397: la $2, sym_2_3397
+.globl sym_2_3398
+sym_2_3398: la $2, sym_2_3398
+.globl sym_2_3399
+sym_2_3399: la $2, sym_2_3399
+.globl sym_2_3400
+sym_2_3400: la $2, sym_2_3400
+.globl sym_2_3401
+sym_2_3401: la $2, sym_2_3401
+.globl sym_2_3402
+sym_2_3402: la $2, sym_2_3402
+.globl sym_2_3403
+sym_2_3403: la $2, sym_2_3403
+.globl sym_2_3404
+sym_2_3404: la $2, sym_2_3404
+.globl sym_2_3405
+sym_2_3405: la $2, sym_2_3405
+.globl sym_2_3406
+sym_2_3406: la $2, sym_2_3406
+.globl sym_2_3407
+sym_2_3407: la $2, sym_2_3407
+.globl sym_2_3408
+sym_2_3408: la $2, sym_2_3408
+.globl sym_2_3409
+sym_2_3409: la $2, sym_2_3409
+.globl sym_2_3410
+sym_2_3410: la $2, sym_2_3410
+.globl sym_2_3411
+sym_2_3411: la $2, sym_2_3411
+.globl sym_2_3412
+sym_2_3412: la $2, sym_2_3412
+.globl sym_2_3413
+sym_2_3413: la $2, sym_2_3413
+.globl sym_2_3414
+sym_2_3414: la $2, sym_2_3414
+.globl sym_2_3415
+sym_2_3415: la $2, sym_2_3415
+.globl sym_2_3416
+sym_2_3416: la $2, sym_2_3416
+.globl sym_2_3417
+sym_2_3417: la $2, sym_2_3417
+.globl sym_2_3418
+sym_2_3418: la $2, sym_2_3418
+.globl sym_2_3419
+sym_2_3419: la $2, sym_2_3419
+.globl sym_2_3420
+sym_2_3420: la $2, sym_2_3420
+.globl sym_2_3421
+sym_2_3421: la $2, sym_2_3421
+.globl sym_2_3422
+sym_2_3422: la $2, sym_2_3422
+.globl sym_2_3423
+sym_2_3423: la $2, sym_2_3423
+.globl sym_2_3424
+sym_2_3424: la $2, sym_2_3424
+.globl sym_2_3425
+sym_2_3425: la $2, sym_2_3425
+.globl sym_2_3426
+sym_2_3426: la $2, sym_2_3426
+.globl sym_2_3427
+sym_2_3427: la $2, sym_2_3427
+.globl sym_2_3428
+sym_2_3428: la $2, sym_2_3428
+.globl sym_2_3429
+sym_2_3429: la $2, sym_2_3429
+.globl sym_2_3430
+sym_2_3430: la $2, sym_2_3430
+.globl sym_2_3431
+sym_2_3431: la $2, sym_2_3431
+.globl sym_2_3432
+sym_2_3432: la $2, sym_2_3432
+.globl sym_2_3433
+sym_2_3433: la $2, sym_2_3433
+.globl sym_2_3434
+sym_2_3434: la $2, sym_2_3434
+.globl sym_2_3435
+sym_2_3435: la $2, sym_2_3435
+.globl sym_2_3436
+sym_2_3436: la $2, sym_2_3436
+.globl sym_2_3437
+sym_2_3437: la $2, sym_2_3437
+.globl sym_2_3438
+sym_2_3438: la $2, sym_2_3438
+.globl sym_2_3439
+sym_2_3439: la $2, sym_2_3439
+.globl sym_2_3440
+sym_2_3440: la $2, sym_2_3440
+.globl sym_2_3441
+sym_2_3441: la $2, sym_2_3441
+.globl sym_2_3442
+sym_2_3442: la $2, sym_2_3442
+.globl sym_2_3443
+sym_2_3443: la $2, sym_2_3443
+.globl sym_2_3444
+sym_2_3444: la $2, sym_2_3444
+.globl sym_2_3445
+sym_2_3445: la $2, sym_2_3445
+.globl sym_2_3446
+sym_2_3446: la $2, sym_2_3446
+.globl sym_2_3447
+sym_2_3447: la $2, sym_2_3447
+.globl sym_2_3448
+sym_2_3448: la $2, sym_2_3448
+.globl sym_2_3449
+sym_2_3449: la $2, sym_2_3449
+.globl sym_2_3450
+sym_2_3450: la $2, sym_2_3450
+.globl sym_2_3451
+sym_2_3451: la $2, sym_2_3451
+.globl sym_2_3452
+sym_2_3452: la $2, sym_2_3452
+.globl sym_2_3453
+sym_2_3453: la $2, sym_2_3453
+.globl sym_2_3454
+sym_2_3454: la $2, sym_2_3454
+.globl sym_2_3455
+sym_2_3455: la $2, sym_2_3455
+.globl sym_2_3456
+sym_2_3456: la $2, sym_2_3456
+.globl sym_2_3457
+sym_2_3457: la $2, sym_2_3457
+.globl sym_2_3458
+sym_2_3458: la $2, sym_2_3458
+.globl sym_2_3459
+sym_2_3459: la $2, sym_2_3459
+.globl sym_2_3460
+sym_2_3460: la $2, sym_2_3460
+.globl sym_2_3461
+sym_2_3461: la $2, sym_2_3461
+.globl sym_2_3462
+sym_2_3462: la $2, sym_2_3462
+.globl sym_2_3463
+sym_2_3463: la $2, sym_2_3463
+.globl sym_2_3464
+sym_2_3464: la $2, sym_2_3464
+.globl sym_2_3465
+sym_2_3465: la $2, sym_2_3465
+.globl sym_2_3466
+sym_2_3466: la $2, sym_2_3466
+.globl sym_2_3467
+sym_2_3467: la $2, sym_2_3467
+.globl sym_2_3468
+sym_2_3468: la $2, sym_2_3468
+.globl sym_2_3469
+sym_2_3469: la $2, sym_2_3469
+.globl sym_2_3470
+sym_2_3470: la $2, sym_2_3470
+.globl sym_2_3471
+sym_2_3471: la $2, sym_2_3471
+.globl sym_2_3472
+sym_2_3472: la $2, sym_2_3472
+.globl sym_2_3473
+sym_2_3473: la $2, sym_2_3473
+.globl sym_2_3474
+sym_2_3474: la $2, sym_2_3474
+.globl sym_2_3475
+sym_2_3475: la $2, sym_2_3475
+.globl sym_2_3476
+sym_2_3476: la $2, sym_2_3476
+.globl sym_2_3477
+sym_2_3477: la $2, sym_2_3477
+.globl sym_2_3478
+sym_2_3478: la $2, sym_2_3478
+.globl sym_2_3479
+sym_2_3479: la $2, sym_2_3479
+.globl sym_2_3480
+sym_2_3480: la $2, sym_2_3480
+.globl sym_2_3481
+sym_2_3481: la $2, sym_2_3481
+.globl sym_2_3482
+sym_2_3482: la $2, sym_2_3482
+.globl sym_2_3483
+sym_2_3483: la $2, sym_2_3483
+.globl sym_2_3484
+sym_2_3484: la $2, sym_2_3484
+.globl sym_2_3485
+sym_2_3485: la $2, sym_2_3485
+.globl sym_2_3486
+sym_2_3486: la $2, sym_2_3486
+.globl sym_2_3487
+sym_2_3487: la $2, sym_2_3487
+.globl sym_2_3488
+sym_2_3488: la $2, sym_2_3488
+.globl sym_2_3489
+sym_2_3489: la $2, sym_2_3489
+.globl sym_2_3490
+sym_2_3490: la $2, sym_2_3490
+.globl sym_2_3491
+sym_2_3491: la $2, sym_2_3491
+.globl sym_2_3492
+sym_2_3492: la $2, sym_2_3492
+.globl sym_2_3493
+sym_2_3493: la $2, sym_2_3493
+.globl sym_2_3494
+sym_2_3494: la $2, sym_2_3494
+.globl sym_2_3495
+sym_2_3495: la $2, sym_2_3495
+.globl sym_2_3496
+sym_2_3496: la $2, sym_2_3496
+.globl sym_2_3497
+sym_2_3497: la $2, sym_2_3497
+.globl sym_2_3498
+sym_2_3498: la $2, sym_2_3498
+.globl sym_2_3499
+sym_2_3499: la $2, sym_2_3499
+.globl sym_2_3500
+sym_2_3500: la $2, sym_2_3500
+.globl sym_2_3501
+sym_2_3501: la $2, sym_2_3501
+.globl sym_2_3502
+sym_2_3502: la $2, sym_2_3502
+.globl sym_2_3503
+sym_2_3503: la $2, sym_2_3503
+.globl sym_2_3504
+sym_2_3504: la $2, sym_2_3504
+.globl sym_2_3505
+sym_2_3505: la $2, sym_2_3505
+.globl sym_2_3506
+sym_2_3506: la $2, sym_2_3506
+.globl sym_2_3507
+sym_2_3507: la $2, sym_2_3507
+.globl sym_2_3508
+sym_2_3508: la $2, sym_2_3508
+.globl sym_2_3509
+sym_2_3509: la $2, sym_2_3509
+.globl sym_2_3510
+sym_2_3510: la $2, sym_2_3510
+.globl sym_2_3511
+sym_2_3511: la $2, sym_2_3511
+.globl sym_2_3512
+sym_2_3512: la $2, sym_2_3512
+.globl sym_2_3513
+sym_2_3513: la $2, sym_2_3513
+.globl sym_2_3514
+sym_2_3514: la $2, sym_2_3514
+.globl sym_2_3515
+sym_2_3515: la $2, sym_2_3515
+.globl sym_2_3516
+sym_2_3516: la $2, sym_2_3516
+.globl sym_2_3517
+sym_2_3517: la $2, sym_2_3517
+.globl sym_2_3518
+sym_2_3518: la $2, sym_2_3518
+.globl sym_2_3519
+sym_2_3519: la $2, sym_2_3519
+.globl sym_2_3520
+sym_2_3520: la $2, sym_2_3520
+.globl sym_2_3521
+sym_2_3521: la $2, sym_2_3521
+.globl sym_2_3522
+sym_2_3522: la $2, sym_2_3522
+.globl sym_2_3523
+sym_2_3523: la $2, sym_2_3523
+.globl sym_2_3524
+sym_2_3524: la $2, sym_2_3524
+.globl sym_2_3525
+sym_2_3525: la $2, sym_2_3525
+.globl sym_2_3526
+sym_2_3526: la $2, sym_2_3526
+.globl sym_2_3527
+sym_2_3527: la $2, sym_2_3527
+.globl sym_2_3528
+sym_2_3528: la $2, sym_2_3528
+.globl sym_2_3529
+sym_2_3529: la $2, sym_2_3529
+.globl sym_2_3530
+sym_2_3530: la $2, sym_2_3530
+.globl sym_2_3531
+sym_2_3531: la $2, sym_2_3531
+.globl sym_2_3532
+sym_2_3532: la $2, sym_2_3532
+.globl sym_2_3533
+sym_2_3533: la $2, sym_2_3533
+.globl sym_2_3534
+sym_2_3534: la $2, sym_2_3534
+.globl sym_2_3535
+sym_2_3535: la $2, sym_2_3535
+.globl sym_2_3536
+sym_2_3536: la $2, sym_2_3536
+.globl sym_2_3537
+sym_2_3537: la $2, sym_2_3537
+.globl sym_2_3538
+sym_2_3538: la $2, sym_2_3538
+.globl sym_2_3539
+sym_2_3539: la $2, sym_2_3539
+.globl sym_2_3540
+sym_2_3540: la $2, sym_2_3540
+.globl sym_2_3541
+sym_2_3541: la $2, sym_2_3541
+.globl sym_2_3542
+sym_2_3542: la $2, sym_2_3542
+.globl sym_2_3543
+sym_2_3543: la $2, sym_2_3543
+.globl sym_2_3544
+sym_2_3544: la $2, sym_2_3544
+.globl sym_2_3545
+sym_2_3545: la $2, sym_2_3545
+.globl sym_2_3546
+sym_2_3546: la $2, sym_2_3546
+.globl sym_2_3547
+sym_2_3547: la $2, sym_2_3547
+.globl sym_2_3548
+sym_2_3548: la $2, sym_2_3548
+.globl sym_2_3549
+sym_2_3549: la $2, sym_2_3549
+.globl sym_2_3550
+sym_2_3550: la $2, sym_2_3550
+.globl sym_2_3551
+sym_2_3551: la $2, sym_2_3551
+.globl sym_2_3552
+sym_2_3552: la $2, sym_2_3552
+.globl sym_2_3553
+sym_2_3553: la $2, sym_2_3553
+.globl sym_2_3554
+sym_2_3554: la $2, sym_2_3554
+.globl sym_2_3555
+sym_2_3555: la $2, sym_2_3555
+.globl sym_2_3556
+sym_2_3556: la $2, sym_2_3556
+.globl sym_2_3557
+sym_2_3557: la $2, sym_2_3557
+.globl sym_2_3558
+sym_2_3558: la $2, sym_2_3558
+.globl sym_2_3559
+sym_2_3559: la $2, sym_2_3559
+.globl sym_2_3560
+sym_2_3560: la $2, sym_2_3560
+.globl sym_2_3561
+sym_2_3561: la $2, sym_2_3561
+.globl sym_2_3562
+sym_2_3562: la $2, sym_2_3562
+.globl sym_2_3563
+sym_2_3563: la $2, sym_2_3563
+.globl sym_2_3564
+sym_2_3564: la $2, sym_2_3564
+.globl sym_2_3565
+sym_2_3565: la $2, sym_2_3565
+.globl sym_2_3566
+sym_2_3566: la $2, sym_2_3566
+.globl sym_2_3567
+sym_2_3567: la $2, sym_2_3567
+.globl sym_2_3568
+sym_2_3568: la $2, sym_2_3568
+.globl sym_2_3569
+sym_2_3569: la $2, sym_2_3569
+.globl sym_2_3570
+sym_2_3570: la $2, sym_2_3570
+.globl sym_2_3571
+sym_2_3571: la $2, sym_2_3571
+.globl sym_2_3572
+sym_2_3572: la $2, sym_2_3572
+.globl sym_2_3573
+sym_2_3573: la $2, sym_2_3573
+.globl sym_2_3574
+sym_2_3574: la $2, sym_2_3574
+.globl sym_2_3575
+sym_2_3575: la $2, sym_2_3575
+.globl sym_2_3576
+sym_2_3576: la $2, sym_2_3576
+.globl sym_2_3577
+sym_2_3577: la $2, sym_2_3577
+.globl sym_2_3578
+sym_2_3578: la $2, sym_2_3578
+.globl sym_2_3579
+sym_2_3579: la $2, sym_2_3579
+.globl sym_2_3580
+sym_2_3580: la $2, sym_2_3580
+.globl sym_2_3581
+sym_2_3581: la $2, sym_2_3581
+.globl sym_2_3582
+sym_2_3582: la $2, sym_2_3582
+.globl sym_2_3583
+sym_2_3583: la $2, sym_2_3583
+.globl sym_2_3584
+sym_2_3584: la $2, sym_2_3584
+.globl sym_2_3585
+sym_2_3585: la $2, sym_2_3585
+.globl sym_2_3586
+sym_2_3586: la $2, sym_2_3586
+.globl sym_2_3587
+sym_2_3587: la $2, sym_2_3587
+.globl sym_2_3588
+sym_2_3588: la $2, sym_2_3588
+.globl sym_2_3589
+sym_2_3589: la $2, sym_2_3589
+.globl sym_2_3590
+sym_2_3590: la $2, sym_2_3590
+.globl sym_2_3591
+sym_2_3591: la $2, sym_2_3591
+.globl sym_2_3592
+sym_2_3592: la $2, sym_2_3592
+.globl sym_2_3593
+sym_2_3593: la $2, sym_2_3593
+.globl sym_2_3594
+sym_2_3594: la $2, sym_2_3594
+.globl sym_2_3595
+sym_2_3595: la $2, sym_2_3595
+.globl sym_2_3596
+sym_2_3596: la $2, sym_2_3596
+.globl sym_2_3597
+sym_2_3597: la $2, sym_2_3597
+.globl sym_2_3598
+sym_2_3598: la $2, sym_2_3598
+.globl sym_2_3599
+sym_2_3599: la $2, sym_2_3599
+.globl sym_2_3600
+sym_2_3600: la $2, sym_2_3600
+.globl sym_2_3601
+sym_2_3601: la $2, sym_2_3601
+.globl sym_2_3602
+sym_2_3602: la $2, sym_2_3602
+.globl sym_2_3603
+sym_2_3603: la $2, sym_2_3603
+.globl sym_2_3604
+sym_2_3604: la $2, sym_2_3604
+.globl sym_2_3605
+sym_2_3605: la $2, sym_2_3605
+.globl sym_2_3606
+sym_2_3606: la $2, sym_2_3606
+.globl sym_2_3607
+sym_2_3607: la $2, sym_2_3607
+.globl sym_2_3608
+sym_2_3608: la $2, sym_2_3608
+.globl sym_2_3609
+sym_2_3609: la $2, sym_2_3609
+.globl sym_2_3610
+sym_2_3610: la $2, sym_2_3610
+.globl sym_2_3611
+sym_2_3611: la $2, sym_2_3611
+.globl sym_2_3612
+sym_2_3612: la $2, sym_2_3612
+.globl sym_2_3613
+sym_2_3613: la $2, sym_2_3613
+.globl sym_2_3614
+sym_2_3614: la $2, sym_2_3614
+.globl sym_2_3615
+sym_2_3615: la $2, sym_2_3615
+.globl sym_2_3616
+sym_2_3616: la $2, sym_2_3616
+.globl sym_2_3617
+sym_2_3617: la $2, sym_2_3617
+.globl sym_2_3618
+sym_2_3618: la $2, sym_2_3618
+.globl sym_2_3619
+sym_2_3619: la $2, sym_2_3619
+.globl sym_2_3620
+sym_2_3620: la $2, sym_2_3620
+.globl sym_2_3621
+sym_2_3621: la $2, sym_2_3621
+.globl sym_2_3622
+sym_2_3622: la $2, sym_2_3622
+.globl sym_2_3623
+sym_2_3623: la $2, sym_2_3623
+.globl sym_2_3624
+sym_2_3624: la $2, sym_2_3624
+.globl sym_2_3625
+sym_2_3625: la $2, sym_2_3625
+.globl sym_2_3626
+sym_2_3626: la $2, sym_2_3626
+.globl sym_2_3627
+sym_2_3627: la $2, sym_2_3627
+.globl sym_2_3628
+sym_2_3628: la $2, sym_2_3628
+.globl sym_2_3629
+sym_2_3629: la $2, sym_2_3629
+.globl sym_2_3630
+sym_2_3630: la $2, sym_2_3630
+.globl sym_2_3631
+sym_2_3631: la $2, sym_2_3631
+.globl sym_2_3632
+sym_2_3632: la $2, sym_2_3632
+.globl sym_2_3633
+sym_2_3633: la $2, sym_2_3633
+.globl sym_2_3634
+sym_2_3634: la $2, sym_2_3634
+.globl sym_2_3635
+sym_2_3635: la $2, sym_2_3635
+.globl sym_2_3636
+sym_2_3636: la $2, sym_2_3636
+.globl sym_2_3637
+sym_2_3637: la $2, sym_2_3637
+.globl sym_2_3638
+sym_2_3638: la $2, sym_2_3638
+.globl sym_2_3639
+sym_2_3639: la $2, sym_2_3639
+.globl sym_2_3640
+sym_2_3640: la $2, sym_2_3640
+.globl sym_2_3641
+sym_2_3641: la $2, sym_2_3641
+.globl sym_2_3642
+sym_2_3642: la $2, sym_2_3642
+.globl sym_2_3643
+sym_2_3643: la $2, sym_2_3643
+.globl sym_2_3644
+sym_2_3644: la $2, sym_2_3644
+.globl sym_2_3645
+sym_2_3645: la $2, sym_2_3645
+.globl sym_2_3646
+sym_2_3646: la $2, sym_2_3646
+.globl sym_2_3647
+sym_2_3647: la $2, sym_2_3647
+.globl sym_2_3648
+sym_2_3648: la $2, sym_2_3648
+.globl sym_2_3649
+sym_2_3649: la $2, sym_2_3649
+.globl sym_2_3650
+sym_2_3650: la $2, sym_2_3650
+.globl sym_2_3651
+sym_2_3651: la $2, sym_2_3651
+.globl sym_2_3652
+sym_2_3652: la $2, sym_2_3652
+.globl sym_2_3653
+sym_2_3653: la $2, sym_2_3653
+.globl sym_2_3654
+sym_2_3654: la $2, sym_2_3654
+.globl sym_2_3655
+sym_2_3655: la $2, sym_2_3655
+.globl sym_2_3656
+sym_2_3656: la $2, sym_2_3656
+.globl sym_2_3657
+sym_2_3657: la $2, sym_2_3657
+.globl sym_2_3658
+sym_2_3658: la $2, sym_2_3658
+.globl sym_2_3659
+sym_2_3659: la $2, sym_2_3659
+.globl sym_2_3660
+sym_2_3660: la $2, sym_2_3660
+.globl sym_2_3661
+sym_2_3661: la $2, sym_2_3661
+.globl sym_2_3662
+sym_2_3662: la $2, sym_2_3662
+.globl sym_2_3663
+sym_2_3663: la $2, sym_2_3663
+.globl sym_2_3664
+sym_2_3664: la $2, sym_2_3664
+.globl sym_2_3665
+sym_2_3665: la $2, sym_2_3665
+.globl sym_2_3666
+sym_2_3666: la $2, sym_2_3666
+.globl sym_2_3667
+sym_2_3667: la $2, sym_2_3667
+.globl sym_2_3668
+sym_2_3668: la $2, sym_2_3668
+.globl sym_2_3669
+sym_2_3669: la $2, sym_2_3669
+.globl sym_2_3670
+sym_2_3670: la $2, sym_2_3670
+.globl sym_2_3671
+sym_2_3671: la $2, sym_2_3671
+.globl sym_2_3672
+sym_2_3672: la $2, sym_2_3672
+.globl sym_2_3673
+sym_2_3673: la $2, sym_2_3673
+.globl sym_2_3674
+sym_2_3674: la $2, sym_2_3674
+.globl sym_2_3675
+sym_2_3675: la $2, sym_2_3675
+.globl sym_2_3676
+sym_2_3676: la $2, sym_2_3676
+.globl sym_2_3677
+sym_2_3677: la $2, sym_2_3677
+.globl sym_2_3678
+sym_2_3678: la $2, sym_2_3678
+.globl sym_2_3679
+sym_2_3679: la $2, sym_2_3679
+.globl sym_2_3680
+sym_2_3680: la $2, sym_2_3680
+.globl sym_2_3681
+sym_2_3681: la $2, sym_2_3681
+.globl sym_2_3682
+sym_2_3682: la $2, sym_2_3682
+.globl sym_2_3683
+sym_2_3683: la $2, sym_2_3683
+.globl sym_2_3684
+sym_2_3684: la $2, sym_2_3684
+.globl sym_2_3685
+sym_2_3685: la $2, sym_2_3685
+.globl sym_2_3686
+sym_2_3686: la $2, sym_2_3686
+.globl sym_2_3687
+sym_2_3687: la $2, sym_2_3687
+.globl sym_2_3688
+sym_2_3688: la $2, sym_2_3688
+.globl sym_2_3689
+sym_2_3689: la $2, sym_2_3689
+.globl sym_2_3690
+sym_2_3690: la $2, sym_2_3690
+.globl sym_2_3691
+sym_2_3691: la $2, sym_2_3691
+.globl sym_2_3692
+sym_2_3692: la $2, sym_2_3692
+.globl sym_2_3693
+sym_2_3693: la $2, sym_2_3693
+.globl sym_2_3694
+sym_2_3694: la $2, sym_2_3694
+.globl sym_2_3695
+sym_2_3695: la $2, sym_2_3695
+.globl sym_2_3696
+sym_2_3696: la $2, sym_2_3696
+.globl sym_2_3697
+sym_2_3697: la $2, sym_2_3697
+.globl sym_2_3698
+sym_2_3698: la $2, sym_2_3698
+.globl sym_2_3699
+sym_2_3699: la $2, sym_2_3699
+.globl sym_2_3700
+sym_2_3700: la $2, sym_2_3700
+.globl sym_2_3701
+sym_2_3701: la $2, sym_2_3701
+.globl sym_2_3702
+sym_2_3702: la $2, sym_2_3702
+.globl sym_2_3703
+sym_2_3703: la $2, sym_2_3703
+.globl sym_2_3704
+sym_2_3704: la $2, sym_2_3704
+.globl sym_2_3705
+sym_2_3705: la $2, sym_2_3705
+.globl sym_2_3706
+sym_2_3706: la $2, sym_2_3706
+.globl sym_2_3707
+sym_2_3707: la $2, sym_2_3707
+.globl sym_2_3708
+sym_2_3708: la $2, sym_2_3708
+.globl sym_2_3709
+sym_2_3709: la $2, sym_2_3709
+.globl sym_2_3710
+sym_2_3710: la $2, sym_2_3710
+.globl sym_2_3711
+sym_2_3711: la $2, sym_2_3711
+.globl sym_2_3712
+sym_2_3712: la $2, sym_2_3712
+.globl sym_2_3713
+sym_2_3713: la $2, sym_2_3713
+.globl sym_2_3714
+sym_2_3714: la $2, sym_2_3714
+.globl sym_2_3715
+sym_2_3715: la $2, sym_2_3715
+.globl sym_2_3716
+sym_2_3716: la $2, sym_2_3716
+.globl sym_2_3717
+sym_2_3717: la $2, sym_2_3717
+.globl sym_2_3718
+sym_2_3718: la $2, sym_2_3718
+.globl sym_2_3719
+sym_2_3719: la $2, sym_2_3719
+.globl sym_2_3720
+sym_2_3720: la $2, sym_2_3720
+.globl sym_2_3721
+sym_2_3721: la $2, sym_2_3721
+.globl sym_2_3722
+sym_2_3722: la $2, sym_2_3722
+.globl sym_2_3723
+sym_2_3723: la $2, sym_2_3723
+.globl sym_2_3724
+sym_2_3724: la $2, sym_2_3724
+.globl sym_2_3725
+sym_2_3725: la $2, sym_2_3725
+.globl sym_2_3726
+sym_2_3726: la $2, sym_2_3726
+.globl sym_2_3727
+sym_2_3727: la $2, sym_2_3727
+.globl sym_2_3728
+sym_2_3728: la $2, sym_2_3728
+.globl sym_2_3729
+sym_2_3729: la $2, sym_2_3729
+.globl sym_2_3730
+sym_2_3730: la $2, sym_2_3730
+.globl sym_2_3731
+sym_2_3731: la $2, sym_2_3731
+.globl sym_2_3732
+sym_2_3732: la $2, sym_2_3732
+.globl sym_2_3733
+sym_2_3733: la $2, sym_2_3733
+.globl sym_2_3734
+sym_2_3734: la $2, sym_2_3734
+.globl sym_2_3735
+sym_2_3735: la $2, sym_2_3735
+.globl sym_2_3736
+sym_2_3736: la $2, sym_2_3736
+.globl sym_2_3737
+sym_2_3737: la $2, sym_2_3737
+.globl sym_2_3738
+sym_2_3738: la $2, sym_2_3738
+.globl sym_2_3739
+sym_2_3739: la $2, sym_2_3739
+.globl sym_2_3740
+sym_2_3740: la $2, sym_2_3740
+.globl sym_2_3741
+sym_2_3741: la $2, sym_2_3741
+.globl sym_2_3742
+sym_2_3742: la $2, sym_2_3742
+.globl sym_2_3743
+sym_2_3743: la $2, sym_2_3743
+.globl sym_2_3744
+sym_2_3744: la $2, sym_2_3744
+.globl sym_2_3745
+sym_2_3745: la $2, sym_2_3745
+.globl sym_2_3746
+sym_2_3746: la $2, sym_2_3746
+.globl sym_2_3747
+sym_2_3747: la $2, sym_2_3747
+.globl sym_2_3748
+sym_2_3748: la $2, sym_2_3748
+.globl sym_2_3749
+sym_2_3749: la $2, sym_2_3749
+.globl sym_2_3750
+sym_2_3750: la $2, sym_2_3750
+.globl sym_2_3751
+sym_2_3751: la $2, sym_2_3751
+.globl sym_2_3752
+sym_2_3752: la $2, sym_2_3752
+.globl sym_2_3753
+sym_2_3753: la $2, sym_2_3753
+.globl sym_2_3754
+sym_2_3754: la $2, sym_2_3754
+.globl sym_2_3755
+sym_2_3755: la $2, sym_2_3755
+.globl sym_2_3756
+sym_2_3756: la $2, sym_2_3756
+.globl sym_2_3757
+sym_2_3757: la $2, sym_2_3757
+.globl sym_2_3758
+sym_2_3758: la $2, sym_2_3758
+.globl sym_2_3759
+sym_2_3759: la $2, sym_2_3759
+.globl sym_2_3760
+sym_2_3760: la $2, sym_2_3760
+.globl sym_2_3761
+sym_2_3761: la $2, sym_2_3761
+.globl sym_2_3762
+sym_2_3762: la $2, sym_2_3762
+.globl sym_2_3763
+sym_2_3763: la $2, sym_2_3763
+.globl sym_2_3764
+sym_2_3764: la $2, sym_2_3764
+.globl sym_2_3765
+sym_2_3765: la $2, sym_2_3765
+.globl sym_2_3766
+sym_2_3766: la $2, sym_2_3766
+.globl sym_2_3767
+sym_2_3767: la $2, sym_2_3767
+.globl sym_2_3768
+sym_2_3768: la $2, sym_2_3768
+.globl sym_2_3769
+sym_2_3769: la $2, sym_2_3769
+.globl sym_2_3770
+sym_2_3770: la $2, sym_2_3770
+.globl sym_2_3771
+sym_2_3771: la $2, sym_2_3771
+.globl sym_2_3772
+sym_2_3772: la $2, sym_2_3772
+.globl sym_2_3773
+sym_2_3773: la $2, sym_2_3773
+.globl sym_2_3774
+sym_2_3774: la $2, sym_2_3774
+.globl sym_2_3775
+sym_2_3775: la $2, sym_2_3775
+.globl sym_2_3776
+sym_2_3776: la $2, sym_2_3776
+.globl sym_2_3777
+sym_2_3777: la $2, sym_2_3777
+.globl sym_2_3778
+sym_2_3778: la $2, sym_2_3778
+.globl sym_2_3779
+sym_2_3779: la $2, sym_2_3779
+.globl sym_2_3780
+sym_2_3780: la $2, sym_2_3780
+.globl sym_2_3781
+sym_2_3781: la $2, sym_2_3781
+.globl sym_2_3782
+sym_2_3782: la $2, sym_2_3782
+.globl sym_2_3783
+sym_2_3783: la $2, sym_2_3783
+.globl sym_2_3784
+sym_2_3784: la $2, sym_2_3784
+.globl sym_2_3785
+sym_2_3785: la $2, sym_2_3785
+.globl sym_2_3786
+sym_2_3786: la $2, sym_2_3786
+.globl sym_2_3787
+sym_2_3787: la $2, sym_2_3787
+.globl sym_2_3788
+sym_2_3788: la $2, sym_2_3788
+.globl sym_2_3789
+sym_2_3789: la $2, sym_2_3789
+.globl sym_2_3790
+sym_2_3790: la $2, sym_2_3790
+.globl sym_2_3791
+sym_2_3791: la $2, sym_2_3791
+.globl sym_2_3792
+sym_2_3792: la $2, sym_2_3792
+.globl sym_2_3793
+sym_2_3793: la $2, sym_2_3793
+.globl sym_2_3794
+sym_2_3794: la $2, sym_2_3794
+.globl sym_2_3795
+sym_2_3795: la $2, sym_2_3795
+.globl sym_2_3796
+sym_2_3796: la $2, sym_2_3796
+.globl sym_2_3797
+sym_2_3797: la $2, sym_2_3797
+.globl sym_2_3798
+sym_2_3798: la $2, sym_2_3798
+.globl sym_2_3799
+sym_2_3799: la $2, sym_2_3799
+.globl sym_2_3800
+sym_2_3800: la $2, sym_2_3800
+.globl sym_2_3801
+sym_2_3801: la $2, sym_2_3801
+.globl sym_2_3802
+sym_2_3802: la $2, sym_2_3802
+.globl sym_2_3803
+sym_2_3803: la $2, sym_2_3803
+.globl sym_2_3804
+sym_2_3804: la $2, sym_2_3804
+.globl sym_2_3805
+sym_2_3805: la $2, sym_2_3805
+.globl sym_2_3806
+sym_2_3806: la $2, sym_2_3806
+.globl sym_2_3807
+sym_2_3807: la $2, sym_2_3807
+.globl sym_2_3808
+sym_2_3808: la $2, sym_2_3808
+.globl sym_2_3809
+sym_2_3809: la $2, sym_2_3809
+.globl sym_2_3810
+sym_2_3810: la $2, sym_2_3810
+.globl sym_2_3811
+sym_2_3811: la $2, sym_2_3811
+.globl sym_2_3812
+sym_2_3812: la $2, sym_2_3812
+.globl sym_2_3813
+sym_2_3813: la $2, sym_2_3813
+.globl sym_2_3814
+sym_2_3814: la $2, sym_2_3814
+.globl sym_2_3815
+sym_2_3815: la $2, sym_2_3815
+.globl sym_2_3816
+sym_2_3816: la $2, sym_2_3816
+.globl sym_2_3817
+sym_2_3817: la $2, sym_2_3817
+.globl sym_2_3818
+sym_2_3818: la $2, sym_2_3818
+.globl sym_2_3819
+sym_2_3819: la $2, sym_2_3819
+.globl sym_2_3820
+sym_2_3820: la $2, sym_2_3820
+.globl sym_2_3821
+sym_2_3821: la $2, sym_2_3821
+.globl sym_2_3822
+sym_2_3822: la $2, sym_2_3822
+.globl sym_2_3823
+sym_2_3823: la $2, sym_2_3823
+.globl sym_2_3824
+sym_2_3824: la $2, sym_2_3824
+.globl sym_2_3825
+sym_2_3825: la $2, sym_2_3825
+.globl sym_2_3826
+sym_2_3826: la $2, sym_2_3826
+.globl sym_2_3827
+sym_2_3827: la $2, sym_2_3827
+.globl sym_2_3828
+sym_2_3828: la $2, sym_2_3828
+.globl sym_2_3829
+sym_2_3829: la $2, sym_2_3829
+.globl sym_2_3830
+sym_2_3830: la $2, sym_2_3830
+.globl sym_2_3831
+sym_2_3831: la $2, sym_2_3831
+.globl sym_2_3832
+sym_2_3832: la $2, sym_2_3832
+.globl sym_2_3833
+sym_2_3833: la $2, sym_2_3833
+.globl sym_2_3834
+sym_2_3834: la $2, sym_2_3834
+.globl sym_2_3835
+sym_2_3835: la $2, sym_2_3835
+.globl sym_2_3836
+sym_2_3836: la $2, sym_2_3836
+.globl sym_2_3837
+sym_2_3837: la $2, sym_2_3837
+.globl sym_2_3838
+sym_2_3838: la $2, sym_2_3838
+.globl sym_2_3839
+sym_2_3839: la $2, sym_2_3839
+.globl sym_2_3840
+sym_2_3840: la $2, sym_2_3840
+.globl sym_2_3841
+sym_2_3841: la $2, sym_2_3841
+.globl sym_2_3842
+sym_2_3842: la $2, sym_2_3842
+.globl sym_2_3843
+sym_2_3843: la $2, sym_2_3843
+.globl sym_2_3844
+sym_2_3844: la $2, sym_2_3844
+.globl sym_2_3845
+sym_2_3845: la $2, sym_2_3845
+.globl sym_2_3846
+sym_2_3846: la $2, sym_2_3846
+.globl sym_2_3847
+sym_2_3847: la $2, sym_2_3847
+.globl sym_2_3848
+sym_2_3848: la $2, sym_2_3848
+.globl sym_2_3849
+sym_2_3849: la $2, sym_2_3849
+.globl sym_2_3850
+sym_2_3850: la $2, sym_2_3850
+.globl sym_2_3851
+sym_2_3851: la $2, sym_2_3851
+.globl sym_2_3852
+sym_2_3852: la $2, sym_2_3852
+.globl sym_2_3853
+sym_2_3853: la $2, sym_2_3853
+.globl sym_2_3854
+sym_2_3854: la $2, sym_2_3854
+.globl sym_2_3855
+sym_2_3855: la $2, sym_2_3855
+.globl sym_2_3856
+sym_2_3856: la $2, sym_2_3856
+.globl sym_2_3857
+sym_2_3857: la $2, sym_2_3857
+.globl sym_2_3858
+sym_2_3858: la $2, sym_2_3858
+.globl sym_2_3859
+sym_2_3859: la $2, sym_2_3859
+.globl sym_2_3860
+sym_2_3860: la $2, sym_2_3860
+.globl sym_2_3861
+sym_2_3861: la $2, sym_2_3861
+.globl sym_2_3862
+sym_2_3862: la $2, sym_2_3862
+.globl sym_2_3863
+sym_2_3863: la $2, sym_2_3863
+.globl sym_2_3864
+sym_2_3864: la $2, sym_2_3864
+.globl sym_2_3865
+sym_2_3865: la $2, sym_2_3865
+.globl sym_2_3866
+sym_2_3866: la $2, sym_2_3866
+.globl sym_2_3867
+sym_2_3867: la $2, sym_2_3867
+.globl sym_2_3868
+sym_2_3868: la $2, sym_2_3868
+.globl sym_2_3869
+sym_2_3869: la $2, sym_2_3869
+.globl sym_2_3870
+sym_2_3870: la $2, sym_2_3870
+.globl sym_2_3871
+sym_2_3871: la $2, sym_2_3871
+.globl sym_2_3872
+sym_2_3872: la $2, sym_2_3872
+.globl sym_2_3873
+sym_2_3873: la $2, sym_2_3873
+.globl sym_2_3874
+sym_2_3874: la $2, sym_2_3874
+.globl sym_2_3875
+sym_2_3875: la $2, sym_2_3875
+.globl sym_2_3876
+sym_2_3876: la $2, sym_2_3876
+.globl sym_2_3877
+sym_2_3877: la $2, sym_2_3877
+.globl sym_2_3878
+sym_2_3878: la $2, sym_2_3878
+.globl sym_2_3879
+sym_2_3879: la $2, sym_2_3879
+.globl sym_2_3880
+sym_2_3880: la $2, sym_2_3880
+.globl sym_2_3881
+sym_2_3881: la $2, sym_2_3881
+.globl sym_2_3882
+sym_2_3882: la $2, sym_2_3882
+.globl sym_2_3883
+sym_2_3883: la $2, sym_2_3883
+.globl sym_2_3884
+sym_2_3884: la $2, sym_2_3884
+.globl sym_2_3885
+sym_2_3885: la $2, sym_2_3885
+.globl sym_2_3886
+sym_2_3886: la $2, sym_2_3886
+.globl sym_2_3887
+sym_2_3887: la $2, sym_2_3887
+.globl sym_2_3888
+sym_2_3888: la $2, sym_2_3888
+.globl sym_2_3889
+sym_2_3889: la $2, sym_2_3889
+.globl sym_2_3890
+sym_2_3890: la $2, sym_2_3890
+.globl sym_2_3891
+sym_2_3891: la $2, sym_2_3891
+.globl sym_2_3892
+sym_2_3892: la $2, sym_2_3892
+.globl sym_2_3893
+sym_2_3893: la $2, sym_2_3893
+.globl sym_2_3894
+sym_2_3894: la $2, sym_2_3894
+.globl sym_2_3895
+sym_2_3895: la $2, sym_2_3895
+.globl sym_2_3896
+sym_2_3896: la $2, sym_2_3896
+.globl sym_2_3897
+sym_2_3897: la $2, sym_2_3897
+.globl sym_2_3898
+sym_2_3898: la $2, sym_2_3898
+.globl sym_2_3899
+sym_2_3899: la $2, sym_2_3899
+.globl sym_2_3900
+sym_2_3900: la $2, sym_2_3900
+.globl sym_2_3901
+sym_2_3901: la $2, sym_2_3901
+.globl sym_2_3902
+sym_2_3902: la $2, sym_2_3902
+.globl sym_2_3903
+sym_2_3903: la $2, sym_2_3903
+.globl sym_2_3904
+sym_2_3904: la $2, sym_2_3904
+.globl sym_2_3905
+sym_2_3905: la $2, sym_2_3905
+.globl sym_2_3906
+sym_2_3906: la $2, sym_2_3906
+.globl sym_2_3907
+sym_2_3907: la $2, sym_2_3907
+.globl sym_2_3908
+sym_2_3908: la $2, sym_2_3908
+.globl sym_2_3909
+sym_2_3909: la $2, sym_2_3909
+.globl sym_2_3910
+sym_2_3910: la $2, sym_2_3910
+.globl sym_2_3911
+sym_2_3911: la $2, sym_2_3911
+.globl sym_2_3912
+sym_2_3912: la $2, sym_2_3912
+.globl sym_2_3913
+sym_2_3913: la $2, sym_2_3913
+.globl sym_2_3914
+sym_2_3914: la $2, sym_2_3914
+.globl sym_2_3915
+sym_2_3915: la $2, sym_2_3915
+.globl sym_2_3916
+sym_2_3916: la $2, sym_2_3916
+.globl sym_2_3917
+sym_2_3917: la $2, sym_2_3917
+.globl sym_2_3918
+sym_2_3918: la $2, sym_2_3918
+.globl sym_2_3919
+sym_2_3919: la $2, sym_2_3919
+.globl sym_2_3920
+sym_2_3920: la $2, sym_2_3920
+.globl sym_2_3921
+sym_2_3921: la $2, sym_2_3921
+.globl sym_2_3922
+sym_2_3922: la $2, sym_2_3922
+.globl sym_2_3923
+sym_2_3923: la $2, sym_2_3923
+.globl sym_2_3924
+sym_2_3924: la $2, sym_2_3924
+.globl sym_2_3925
+sym_2_3925: la $2, sym_2_3925
+.globl sym_2_3926
+sym_2_3926: la $2, sym_2_3926
+.globl sym_2_3927
+sym_2_3927: la $2, sym_2_3927
+.globl sym_2_3928
+sym_2_3928: la $2, sym_2_3928
+.globl sym_2_3929
+sym_2_3929: la $2, sym_2_3929
+.globl sym_2_3930
+sym_2_3930: la $2, sym_2_3930
+.globl sym_2_3931
+sym_2_3931: la $2, sym_2_3931
+.globl sym_2_3932
+sym_2_3932: la $2, sym_2_3932
+.globl sym_2_3933
+sym_2_3933: la $2, sym_2_3933
+.globl sym_2_3934
+sym_2_3934: la $2, sym_2_3934
+.globl sym_2_3935
+sym_2_3935: la $2, sym_2_3935
+.globl sym_2_3936
+sym_2_3936: la $2, sym_2_3936
+.globl sym_2_3937
+sym_2_3937: la $2, sym_2_3937
+.globl sym_2_3938
+sym_2_3938: la $2, sym_2_3938
+.globl sym_2_3939
+sym_2_3939: la $2, sym_2_3939
+.globl sym_2_3940
+sym_2_3940: la $2, sym_2_3940
+.globl sym_2_3941
+sym_2_3941: la $2, sym_2_3941
+.globl sym_2_3942
+sym_2_3942: la $2, sym_2_3942
+.globl sym_2_3943
+sym_2_3943: la $2, sym_2_3943
+.globl sym_2_3944
+sym_2_3944: la $2, sym_2_3944
+.globl sym_2_3945
+sym_2_3945: la $2, sym_2_3945
+.globl sym_2_3946
+sym_2_3946: la $2, sym_2_3946
+.globl sym_2_3947
+sym_2_3947: la $2, sym_2_3947
+.globl sym_2_3948
+sym_2_3948: la $2, sym_2_3948
+.globl sym_2_3949
+sym_2_3949: la $2, sym_2_3949
+.globl sym_2_3950
+sym_2_3950: la $2, sym_2_3950
+.globl sym_2_3951
+sym_2_3951: la $2, sym_2_3951
+.globl sym_2_3952
+sym_2_3952: la $2, sym_2_3952
+.globl sym_2_3953
+sym_2_3953: la $2, sym_2_3953
+.globl sym_2_3954
+sym_2_3954: la $2, sym_2_3954
+.globl sym_2_3955
+sym_2_3955: la $2, sym_2_3955
+.globl sym_2_3956
+sym_2_3956: la $2, sym_2_3956
+.globl sym_2_3957
+sym_2_3957: la $2, sym_2_3957
+.globl sym_2_3958
+sym_2_3958: la $2, sym_2_3958
+.globl sym_2_3959
+sym_2_3959: la $2, sym_2_3959
+.globl sym_2_3960
+sym_2_3960: la $2, sym_2_3960
+.globl sym_2_3961
+sym_2_3961: la $2, sym_2_3961
+.globl sym_2_3962
+sym_2_3962: la $2, sym_2_3962
+.globl sym_2_3963
+sym_2_3963: la $2, sym_2_3963
+.globl sym_2_3964
+sym_2_3964: la $2, sym_2_3964
+.globl sym_2_3965
+sym_2_3965: la $2, sym_2_3965
+.globl sym_2_3966
+sym_2_3966: la $2, sym_2_3966
+.globl sym_2_3967
+sym_2_3967: la $2, sym_2_3967
+.globl sym_2_3968
+sym_2_3968: la $2, sym_2_3968
+.globl sym_2_3969
+sym_2_3969: la $2, sym_2_3969
+.globl sym_2_3970
+sym_2_3970: la $2, sym_2_3970
+.globl sym_2_3971
+sym_2_3971: la $2, sym_2_3971
+.globl sym_2_3972
+sym_2_3972: la $2, sym_2_3972
+.globl sym_2_3973
+sym_2_3973: la $2, sym_2_3973
+.globl sym_2_3974
+sym_2_3974: la $2, sym_2_3974
+.globl sym_2_3975
+sym_2_3975: la $2, sym_2_3975
+.globl sym_2_3976
+sym_2_3976: la $2, sym_2_3976
+.globl sym_2_3977
+sym_2_3977: la $2, sym_2_3977
+.globl sym_2_3978
+sym_2_3978: la $2, sym_2_3978
+.globl sym_2_3979
+sym_2_3979: la $2, sym_2_3979
+.globl sym_2_3980
+sym_2_3980: la $2, sym_2_3980
+.globl sym_2_3981
+sym_2_3981: la $2, sym_2_3981
+.globl sym_2_3982
+sym_2_3982: la $2, sym_2_3982
+.globl sym_2_3983
+sym_2_3983: la $2, sym_2_3983
+.globl sym_2_3984
+sym_2_3984: la $2, sym_2_3984
+.globl sym_2_3985
+sym_2_3985: la $2, sym_2_3985
+.globl sym_2_3986
+sym_2_3986: la $2, sym_2_3986
+.globl sym_2_3987
+sym_2_3987: la $2, sym_2_3987
+.globl sym_2_3988
+sym_2_3988: la $2, sym_2_3988
+.globl sym_2_3989
+sym_2_3989: la $2, sym_2_3989
+.globl sym_2_3990
+sym_2_3990: la $2, sym_2_3990
+.globl sym_2_3991
+sym_2_3991: la $2, sym_2_3991
+.globl sym_2_3992
+sym_2_3992: la $2, sym_2_3992
+.globl sym_2_3993
+sym_2_3993: la $2, sym_2_3993
+.globl sym_2_3994
+sym_2_3994: la $2, sym_2_3994
+.globl sym_2_3995
+sym_2_3995: la $2, sym_2_3995
+.globl sym_2_3996
+sym_2_3996: la $2, sym_2_3996
+.globl sym_2_3997
+sym_2_3997: la $2, sym_2_3997
+.globl sym_2_3998
+sym_2_3998: la $2, sym_2_3998
+.globl sym_2_3999
+sym_2_3999: la $2, sym_2_3999
+.globl sym_2_4000
+sym_2_4000: la $2, sym_2_4000
+.globl sym_2_4001
+sym_2_4001: la $2, sym_2_4001
+.globl sym_2_4002
+sym_2_4002: la $2, sym_2_4002
+.globl sym_2_4003
+sym_2_4003: la $2, sym_2_4003
+.globl sym_2_4004
+sym_2_4004: la $2, sym_2_4004
+.globl sym_2_4005
+sym_2_4005: la $2, sym_2_4005
+.globl sym_2_4006
+sym_2_4006: la $2, sym_2_4006
+.globl sym_2_4007
+sym_2_4007: la $2, sym_2_4007
+.globl sym_2_4008
+sym_2_4008: la $2, sym_2_4008
+.globl sym_2_4009
+sym_2_4009: la $2, sym_2_4009
+.globl sym_2_4010
+sym_2_4010: la $2, sym_2_4010
+.globl sym_2_4011
+sym_2_4011: la $2, sym_2_4011
+.globl sym_2_4012
+sym_2_4012: la $2, sym_2_4012
+.globl sym_2_4013
+sym_2_4013: la $2, sym_2_4013
+.globl sym_2_4014
+sym_2_4014: la $2, sym_2_4014
+.globl sym_2_4015
+sym_2_4015: la $2, sym_2_4015
+.globl sym_2_4016
+sym_2_4016: la $2, sym_2_4016
+.globl sym_2_4017
+sym_2_4017: la $2, sym_2_4017
+.globl sym_2_4018
+sym_2_4018: la $2, sym_2_4018
+.globl sym_2_4019
+sym_2_4019: la $2, sym_2_4019
+.globl sym_2_4020
+sym_2_4020: la $2, sym_2_4020
+.globl sym_2_4021
+sym_2_4021: la $2, sym_2_4021
+.globl sym_2_4022
+sym_2_4022: la $2, sym_2_4022
+.globl sym_2_4023
+sym_2_4023: la $2, sym_2_4023
+.globl sym_2_4024
+sym_2_4024: la $2, sym_2_4024
+.globl sym_2_4025
+sym_2_4025: la $2, sym_2_4025
+.globl sym_2_4026
+sym_2_4026: la $2, sym_2_4026
+.globl sym_2_4027
+sym_2_4027: la $2, sym_2_4027
+.globl sym_2_4028
+sym_2_4028: la $2, sym_2_4028
+.globl sym_2_4029
+sym_2_4029: la $2, sym_2_4029
+.globl sym_2_4030
+sym_2_4030: la $2, sym_2_4030
+.globl sym_2_4031
+sym_2_4031: la $2, sym_2_4031
+.globl sym_2_4032
+sym_2_4032: la $2, sym_2_4032
+.globl sym_2_4033
+sym_2_4033: la $2, sym_2_4033
+.globl sym_2_4034
+sym_2_4034: la $2, sym_2_4034
+.globl sym_2_4035
+sym_2_4035: la $2, sym_2_4035
+.globl sym_2_4036
+sym_2_4036: la $2, sym_2_4036
+.globl sym_2_4037
+sym_2_4037: la $2, sym_2_4037
+.globl sym_2_4038
+sym_2_4038: la $2, sym_2_4038
+.globl sym_2_4039
+sym_2_4039: la $2, sym_2_4039
+.globl sym_2_4040
+sym_2_4040: la $2, sym_2_4040
+.globl sym_2_4041
+sym_2_4041: la $2, sym_2_4041
+.globl sym_2_4042
+sym_2_4042: la $2, sym_2_4042
+.globl sym_2_4043
+sym_2_4043: la $2, sym_2_4043
+.globl sym_2_4044
+sym_2_4044: la $2, sym_2_4044
+.globl sym_2_4045
+sym_2_4045: la $2, sym_2_4045
+.globl sym_2_4046
+sym_2_4046: la $2, sym_2_4046
+.globl sym_2_4047
+sym_2_4047: la $2, sym_2_4047
+.globl sym_2_4048
+sym_2_4048: la $2, sym_2_4048
+.globl sym_2_4049
+sym_2_4049: la $2, sym_2_4049
+.globl sym_2_4050
+sym_2_4050: la $2, sym_2_4050
+.globl sym_2_4051
+sym_2_4051: la $2, sym_2_4051
+.globl sym_2_4052
+sym_2_4052: la $2, sym_2_4052
+.globl sym_2_4053
+sym_2_4053: la $2, sym_2_4053
+.globl sym_2_4054
+sym_2_4054: la $2, sym_2_4054
+.globl sym_2_4055
+sym_2_4055: la $2, sym_2_4055
+.globl sym_2_4056
+sym_2_4056: la $2, sym_2_4056
+.globl sym_2_4057
+sym_2_4057: la $2, sym_2_4057
+.globl sym_2_4058
+sym_2_4058: la $2, sym_2_4058
+.globl sym_2_4059
+sym_2_4059: la $2, sym_2_4059
+.globl sym_2_4060
+sym_2_4060: la $2, sym_2_4060
+.globl sym_2_4061
+sym_2_4061: la $2, sym_2_4061
+.globl sym_2_4062
+sym_2_4062: la $2, sym_2_4062
+.globl sym_2_4063
+sym_2_4063: la $2, sym_2_4063
+.globl sym_2_4064
+sym_2_4064: la $2, sym_2_4064
+.globl sym_2_4065
+sym_2_4065: la $2, sym_2_4065
+.globl sym_2_4066
+sym_2_4066: la $2, sym_2_4066
+.globl sym_2_4067
+sym_2_4067: la $2, sym_2_4067
+.globl sym_2_4068
+sym_2_4068: la $2, sym_2_4068
+.globl sym_2_4069
+sym_2_4069: la $2, sym_2_4069
+.globl sym_2_4070
+sym_2_4070: la $2, sym_2_4070
+.globl sym_2_4071
+sym_2_4071: la $2, sym_2_4071
+.globl sym_2_4072
+sym_2_4072: la $2, sym_2_4072
+.globl sym_2_4073
+sym_2_4073: la $2, sym_2_4073
+.globl sym_2_4074
+sym_2_4074: la $2, sym_2_4074
+.globl sym_2_4075
+sym_2_4075: la $2, sym_2_4075
+.globl sym_2_4076
+sym_2_4076: la $2, sym_2_4076
+.globl sym_2_4077
+sym_2_4077: la $2, sym_2_4077
+.globl sym_2_4078
+sym_2_4078: la $2, sym_2_4078
+.globl sym_2_4079
+sym_2_4079: la $2, sym_2_4079
+.globl sym_2_4080
+sym_2_4080: la $2, sym_2_4080
+.globl sym_2_4081
+sym_2_4081: la $2, sym_2_4081
+.globl sym_2_4082
+sym_2_4082: la $2, sym_2_4082
+.globl sym_2_4083
+sym_2_4083: la $2, sym_2_4083
+.globl sym_2_4084
+sym_2_4084: la $2, sym_2_4084
+.globl sym_2_4085
+sym_2_4085: la $2, sym_2_4085
+.globl sym_2_4086
+sym_2_4086: la $2, sym_2_4086
+.globl sym_2_4087
+sym_2_4087: la $2, sym_2_4087
+.globl sym_2_4088
+sym_2_4088: la $2, sym_2_4088
+.globl sym_2_4089
+sym_2_4089: la $2, sym_2_4089
+.globl sym_2_4090
+sym_2_4090: la $2, sym_2_4090
+.globl sym_2_4091
+sym_2_4091: la $2, sym_2_4091
+.globl sym_2_4092
+sym_2_4092: la $2, sym_2_4092
+.globl sym_2_4093
+sym_2_4093: la $2, sym_2_4093
+.globl sym_2_4094
+sym_2_4094: la $2, sym_2_4094
+.globl sym_2_4095
+sym_2_4095: la $2, sym_2_4095
+.globl sym_2_4096
+sym_2_4096: la $2, sym_2_4096
+.globl sym_2_4097
+sym_2_4097: la $2, sym_2_4097
+.globl sym_2_4098
+sym_2_4098: la $2, sym_2_4098
+.globl sym_2_4099
+sym_2_4099: la $2, sym_2_4099
+.globl sym_2_4100
+sym_2_4100: la $2, sym_2_4100
+.globl sym_2_4101
+sym_2_4101: la $2, sym_2_4101
+.globl sym_2_4102
+sym_2_4102: la $2, sym_2_4102
+.globl sym_2_4103
+sym_2_4103: la $2, sym_2_4103
+.globl sym_2_4104
+sym_2_4104: la $2, sym_2_4104
+.globl sym_2_4105
+sym_2_4105: la $2, sym_2_4105
+.globl sym_2_4106
+sym_2_4106: la $2, sym_2_4106
+.globl sym_2_4107
+sym_2_4107: la $2, sym_2_4107
+.globl sym_2_4108
+sym_2_4108: la $2, sym_2_4108
+.globl sym_2_4109
+sym_2_4109: la $2, sym_2_4109
+.globl sym_2_4110
+sym_2_4110: la $2, sym_2_4110
+.globl sym_2_4111
+sym_2_4111: la $2, sym_2_4111
+.globl sym_2_4112
+sym_2_4112: la $2, sym_2_4112
+.globl sym_2_4113
+sym_2_4113: la $2, sym_2_4113
+.globl sym_2_4114
+sym_2_4114: la $2, sym_2_4114
+.globl sym_2_4115
+sym_2_4115: la $2, sym_2_4115
+.globl sym_2_4116
+sym_2_4116: la $2, sym_2_4116
+.globl sym_2_4117
+sym_2_4117: la $2, sym_2_4117
+.globl sym_2_4118
+sym_2_4118: la $2, sym_2_4118
+.globl sym_2_4119
+sym_2_4119: la $2, sym_2_4119
+.globl sym_2_4120
+sym_2_4120: la $2, sym_2_4120
+.globl sym_2_4121
+sym_2_4121: la $2, sym_2_4121
+.globl sym_2_4122
+sym_2_4122: la $2, sym_2_4122
+.globl sym_2_4123
+sym_2_4123: la $2, sym_2_4123
+.globl sym_2_4124
+sym_2_4124: la $2, sym_2_4124
+.globl sym_2_4125
+sym_2_4125: la $2, sym_2_4125
+.globl sym_2_4126
+sym_2_4126: la $2, sym_2_4126
+.globl sym_2_4127
+sym_2_4127: la $2, sym_2_4127
+.globl sym_2_4128
+sym_2_4128: la $2, sym_2_4128
+.globl sym_2_4129
+sym_2_4129: la $2, sym_2_4129
+.globl sym_2_4130
+sym_2_4130: la $2, sym_2_4130
+.globl sym_2_4131
+sym_2_4131: la $2, sym_2_4131
+.globl sym_2_4132
+sym_2_4132: la $2, sym_2_4132
+.globl sym_2_4133
+sym_2_4133: la $2, sym_2_4133
+.globl sym_2_4134
+sym_2_4134: la $2, sym_2_4134
+.globl sym_2_4135
+sym_2_4135: la $2, sym_2_4135
+.globl sym_2_4136
+sym_2_4136: la $2, sym_2_4136
+.globl sym_2_4137
+sym_2_4137: la $2, sym_2_4137
+.globl sym_2_4138
+sym_2_4138: la $2, sym_2_4138
+.globl sym_2_4139
+sym_2_4139: la $2, sym_2_4139
+.globl sym_2_4140
+sym_2_4140: la $2, sym_2_4140
+.globl sym_2_4141
+sym_2_4141: la $2, sym_2_4141
+.globl sym_2_4142
+sym_2_4142: la $2, sym_2_4142
+.globl sym_2_4143
+sym_2_4143: la $2, sym_2_4143
+.globl sym_2_4144
+sym_2_4144: la $2, sym_2_4144
+.globl sym_2_4145
+sym_2_4145: la $2, sym_2_4145
+.globl sym_2_4146
+sym_2_4146: la $2, sym_2_4146
+.globl sym_2_4147
+sym_2_4147: la $2, sym_2_4147
+.globl sym_2_4148
+sym_2_4148: la $2, sym_2_4148
+.globl sym_2_4149
+sym_2_4149: la $2, sym_2_4149
+.globl sym_2_4150
+sym_2_4150: la $2, sym_2_4150
+.globl sym_2_4151
+sym_2_4151: la $2, sym_2_4151
+.globl sym_2_4152
+sym_2_4152: la $2, sym_2_4152
+.globl sym_2_4153
+sym_2_4153: la $2, sym_2_4153
+.globl sym_2_4154
+sym_2_4154: la $2, sym_2_4154
+.globl sym_2_4155
+sym_2_4155: la $2, sym_2_4155
+.globl sym_2_4156
+sym_2_4156: la $2, sym_2_4156
+.globl sym_2_4157
+sym_2_4157: la $2, sym_2_4157
+.globl sym_2_4158
+sym_2_4158: la $2, sym_2_4158
+.globl sym_2_4159
+sym_2_4159: la $2, sym_2_4159
+.globl sym_2_4160
+sym_2_4160: la $2, sym_2_4160
+.globl sym_2_4161
+sym_2_4161: la $2, sym_2_4161
+.globl sym_2_4162
+sym_2_4162: la $2, sym_2_4162
+.globl sym_2_4163
+sym_2_4163: la $2, sym_2_4163
+.globl sym_2_4164
+sym_2_4164: la $2, sym_2_4164
+.globl sym_2_4165
+sym_2_4165: la $2, sym_2_4165
+.globl sym_2_4166
+sym_2_4166: la $2, sym_2_4166
+.globl sym_2_4167
+sym_2_4167: la $2, sym_2_4167
+.globl sym_2_4168
+sym_2_4168: la $2, sym_2_4168
+.globl sym_2_4169
+sym_2_4169: la $2, sym_2_4169
+.globl sym_2_4170
+sym_2_4170: la $2, sym_2_4170
+.globl sym_2_4171
+sym_2_4171: la $2, sym_2_4171
+.globl sym_2_4172
+sym_2_4172: la $2, sym_2_4172
+.globl sym_2_4173
+sym_2_4173: la $2, sym_2_4173
+.globl sym_2_4174
+sym_2_4174: la $2, sym_2_4174
+.globl sym_2_4175
+sym_2_4175: la $2, sym_2_4175
+.globl sym_2_4176
+sym_2_4176: la $2, sym_2_4176
+.globl sym_2_4177
+sym_2_4177: la $2, sym_2_4177
+.globl sym_2_4178
+sym_2_4178: la $2, sym_2_4178
+.globl sym_2_4179
+sym_2_4179: la $2, sym_2_4179
+.globl sym_2_4180
+sym_2_4180: la $2, sym_2_4180
+.globl sym_2_4181
+sym_2_4181: la $2, sym_2_4181
+.globl sym_2_4182
+sym_2_4182: la $2, sym_2_4182
+.globl sym_2_4183
+sym_2_4183: la $2, sym_2_4183
+.globl sym_2_4184
+sym_2_4184: la $2, sym_2_4184
+.globl sym_2_4185
+sym_2_4185: la $2, sym_2_4185
+.globl sym_2_4186
+sym_2_4186: la $2, sym_2_4186
+.globl sym_2_4187
+sym_2_4187: la $2, sym_2_4187
+.globl sym_2_4188
+sym_2_4188: la $2, sym_2_4188
+.globl sym_2_4189
+sym_2_4189: la $2, sym_2_4189
+.globl sym_2_4190
+sym_2_4190: la $2, sym_2_4190
+.globl sym_2_4191
+sym_2_4191: la $2, sym_2_4191
+.globl sym_2_4192
+sym_2_4192: la $2, sym_2_4192
+.globl sym_2_4193
+sym_2_4193: la $2, sym_2_4193
+.globl sym_2_4194
+sym_2_4194: la $2, sym_2_4194
+.globl sym_2_4195
+sym_2_4195: la $2, sym_2_4195
+.globl sym_2_4196
+sym_2_4196: la $2, sym_2_4196
+.globl sym_2_4197
+sym_2_4197: la $2, sym_2_4197
+.globl sym_2_4198
+sym_2_4198: la $2, sym_2_4198
+.globl sym_2_4199
+sym_2_4199: la $2, sym_2_4199
+.globl sym_2_4200
+sym_2_4200: la $2, sym_2_4200
+.globl sym_2_4201
+sym_2_4201: la $2, sym_2_4201
+.globl sym_2_4202
+sym_2_4202: la $2, sym_2_4202
+.globl sym_2_4203
+sym_2_4203: la $2, sym_2_4203
+.globl sym_2_4204
+sym_2_4204: la $2, sym_2_4204
+.globl sym_2_4205
+sym_2_4205: la $2, sym_2_4205
+.globl sym_2_4206
+sym_2_4206: la $2, sym_2_4206
+.globl sym_2_4207
+sym_2_4207: la $2, sym_2_4207
+.globl sym_2_4208
+sym_2_4208: la $2, sym_2_4208
+.globl sym_2_4209
+sym_2_4209: la $2, sym_2_4209
+.globl sym_2_4210
+sym_2_4210: la $2, sym_2_4210
+.globl sym_2_4211
+sym_2_4211: la $2, sym_2_4211
+.globl sym_2_4212
+sym_2_4212: la $2, sym_2_4212
+.globl sym_2_4213
+sym_2_4213: la $2, sym_2_4213
+.globl sym_2_4214
+sym_2_4214: la $2, sym_2_4214
+.globl sym_2_4215
+sym_2_4215: la $2, sym_2_4215
+.globl sym_2_4216
+sym_2_4216: la $2, sym_2_4216
+.globl sym_2_4217
+sym_2_4217: la $2, sym_2_4217
+.globl sym_2_4218
+sym_2_4218: la $2, sym_2_4218
+.globl sym_2_4219
+sym_2_4219: la $2, sym_2_4219
+.globl sym_2_4220
+sym_2_4220: la $2, sym_2_4220
+.globl sym_2_4221
+sym_2_4221: la $2, sym_2_4221
+.globl sym_2_4222
+sym_2_4222: la $2, sym_2_4222
+.globl sym_2_4223
+sym_2_4223: la $2, sym_2_4223
+.globl sym_2_4224
+sym_2_4224: la $2, sym_2_4224
+.globl sym_2_4225
+sym_2_4225: la $2, sym_2_4225
+.globl sym_2_4226
+sym_2_4226: la $2, sym_2_4226
+.globl sym_2_4227
+sym_2_4227: la $2, sym_2_4227
+.globl sym_2_4228
+sym_2_4228: la $2, sym_2_4228
+.globl sym_2_4229
+sym_2_4229: la $2, sym_2_4229
+.globl sym_2_4230
+sym_2_4230: la $2, sym_2_4230
+.globl sym_2_4231
+sym_2_4231: la $2, sym_2_4231
+.globl sym_2_4232
+sym_2_4232: la $2, sym_2_4232
+.globl sym_2_4233
+sym_2_4233: la $2, sym_2_4233
+.globl sym_2_4234
+sym_2_4234: la $2, sym_2_4234
+.globl sym_2_4235
+sym_2_4235: la $2, sym_2_4235
+.globl sym_2_4236
+sym_2_4236: la $2, sym_2_4236
+.globl sym_2_4237
+sym_2_4237: la $2, sym_2_4237
+.globl sym_2_4238
+sym_2_4238: la $2, sym_2_4238
+.globl sym_2_4239
+sym_2_4239: la $2, sym_2_4239
+.globl sym_2_4240
+sym_2_4240: la $2, sym_2_4240
+.globl sym_2_4241
+sym_2_4241: la $2, sym_2_4241
+.globl sym_2_4242
+sym_2_4242: la $2, sym_2_4242
+.globl sym_2_4243
+sym_2_4243: la $2, sym_2_4243
+.globl sym_2_4244
+sym_2_4244: la $2, sym_2_4244
+.globl sym_2_4245
+sym_2_4245: la $2, sym_2_4245
+.globl sym_2_4246
+sym_2_4246: la $2, sym_2_4246
+.globl sym_2_4247
+sym_2_4247: la $2, sym_2_4247
+.globl sym_2_4248
+sym_2_4248: la $2, sym_2_4248
+.globl sym_2_4249
+sym_2_4249: la $2, sym_2_4249
+.globl sym_2_4250
+sym_2_4250: la $2, sym_2_4250
+.globl sym_2_4251
+sym_2_4251: la $2, sym_2_4251
+.globl sym_2_4252
+sym_2_4252: la $2, sym_2_4252
+.globl sym_2_4253
+sym_2_4253: la $2, sym_2_4253
+.globl sym_2_4254
+sym_2_4254: la $2, sym_2_4254
+.globl sym_2_4255
+sym_2_4255: la $2, sym_2_4255
+.globl sym_2_4256
+sym_2_4256: la $2, sym_2_4256
+.globl sym_2_4257
+sym_2_4257: la $2, sym_2_4257
+.globl sym_2_4258
+sym_2_4258: la $2, sym_2_4258
+.globl sym_2_4259
+sym_2_4259: la $2, sym_2_4259
+.globl sym_2_4260
+sym_2_4260: la $2, sym_2_4260
+.globl sym_2_4261
+sym_2_4261: la $2, sym_2_4261
+.globl sym_2_4262
+sym_2_4262: la $2, sym_2_4262
+.globl sym_2_4263
+sym_2_4263: la $2, sym_2_4263
+.globl sym_2_4264
+sym_2_4264: la $2, sym_2_4264
+.globl sym_2_4265
+sym_2_4265: la $2, sym_2_4265
+.globl sym_2_4266
+sym_2_4266: la $2, sym_2_4266
+.globl sym_2_4267
+sym_2_4267: la $2, sym_2_4267
+.globl sym_2_4268
+sym_2_4268: la $2, sym_2_4268
+.globl sym_2_4269
+sym_2_4269: la $2, sym_2_4269
+.globl sym_2_4270
+sym_2_4270: la $2, sym_2_4270
+.globl sym_2_4271
+sym_2_4271: la $2, sym_2_4271
+.globl sym_2_4272
+sym_2_4272: la $2, sym_2_4272
+.globl sym_2_4273
+sym_2_4273: la $2, sym_2_4273
+.globl sym_2_4274
+sym_2_4274: la $2, sym_2_4274
+.globl sym_2_4275
+sym_2_4275: la $2, sym_2_4275
+.globl sym_2_4276
+sym_2_4276: la $2, sym_2_4276
+.globl sym_2_4277
+sym_2_4277: la $2, sym_2_4277
+.globl sym_2_4278
+sym_2_4278: la $2, sym_2_4278
+.globl sym_2_4279
+sym_2_4279: la $2, sym_2_4279
+.globl sym_2_4280
+sym_2_4280: la $2, sym_2_4280
+.globl sym_2_4281
+sym_2_4281: la $2, sym_2_4281
+.globl sym_2_4282
+sym_2_4282: la $2, sym_2_4282
+.globl sym_2_4283
+sym_2_4283: la $2, sym_2_4283
+.globl sym_2_4284
+sym_2_4284: la $2, sym_2_4284
+.globl sym_2_4285
+sym_2_4285: la $2, sym_2_4285
+.globl sym_2_4286
+sym_2_4286: la $2, sym_2_4286
+.globl sym_2_4287
+sym_2_4287: la $2, sym_2_4287
+.globl sym_2_4288
+sym_2_4288: la $2, sym_2_4288
+.globl sym_2_4289
+sym_2_4289: la $2, sym_2_4289
+.globl sym_2_4290
+sym_2_4290: la $2, sym_2_4290
+.globl sym_2_4291
+sym_2_4291: la $2, sym_2_4291
+.globl sym_2_4292
+sym_2_4292: la $2, sym_2_4292
+.globl sym_2_4293
+sym_2_4293: la $2, sym_2_4293
+.globl sym_2_4294
+sym_2_4294: la $2, sym_2_4294
+.globl sym_2_4295
+sym_2_4295: la $2, sym_2_4295
+.globl sym_2_4296
+sym_2_4296: la $2, sym_2_4296
+.globl sym_2_4297
+sym_2_4297: la $2, sym_2_4297
+.globl sym_2_4298
+sym_2_4298: la $2, sym_2_4298
+.globl sym_2_4299
+sym_2_4299: la $2, sym_2_4299
+.globl sym_2_4300
+sym_2_4300: la $2, sym_2_4300
+.globl sym_2_4301
+sym_2_4301: la $2, sym_2_4301
+.globl sym_2_4302
+sym_2_4302: la $2, sym_2_4302
+.globl sym_2_4303
+sym_2_4303: la $2, sym_2_4303
+.globl sym_2_4304
+sym_2_4304: la $2, sym_2_4304
+.globl sym_2_4305
+sym_2_4305: la $2, sym_2_4305
+.globl sym_2_4306
+sym_2_4306: la $2, sym_2_4306
+.globl sym_2_4307
+sym_2_4307: la $2, sym_2_4307
+.globl sym_2_4308
+sym_2_4308: la $2, sym_2_4308
+.globl sym_2_4309
+sym_2_4309: la $2, sym_2_4309
+.globl sym_2_4310
+sym_2_4310: la $2, sym_2_4310
+.globl sym_2_4311
+sym_2_4311: la $2, sym_2_4311
+.globl sym_2_4312
+sym_2_4312: la $2, sym_2_4312
+.globl sym_2_4313
+sym_2_4313: la $2, sym_2_4313
+.globl sym_2_4314
+sym_2_4314: la $2, sym_2_4314
+.globl sym_2_4315
+sym_2_4315: la $2, sym_2_4315
+.globl sym_2_4316
+sym_2_4316: la $2, sym_2_4316
+.globl sym_2_4317
+sym_2_4317: la $2, sym_2_4317
+.globl sym_2_4318
+sym_2_4318: la $2, sym_2_4318
+.globl sym_2_4319
+sym_2_4319: la $2, sym_2_4319
+.globl sym_2_4320
+sym_2_4320: la $2, sym_2_4320
+.globl sym_2_4321
+sym_2_4321: la $2, sym_2_4321
+.globl sym_2_4322
+sym_2_4322: la $2, sym_2_4322
+.globl sym_2_4323
+sym_2_4323: la $2, sym_2_4323
+.globl sym_2_4324
+sym_2_4324: la $2, sym_2_4324
+.globl sym_2_4325
+sym_2_4325: la $2, sym_2_4325
+.globl sym_2_4326
+sym_2_4326: la $2, sym_2_4326
+.globl sym_2_4327
+sym_2_4327: la $2, sym_2_4327
+.globl sym_2_4328
+sym_2_4328: la $2, sym_2_4328
+.globl sym_2_4329
+sym_2_4329: la $2, sym_2_4329
+.globl sym_2_4330
+sym_2_4330: la $2, sym_2_4330
+.globl sym_2_4331
+sym_2_4331: la $2, sym_2_4331
+.globl sym_2_4332
+sym_2_4332: la $2, sym_2_4332
+.globl sym_2_4333
+sym_2_4333: la $2, sym_2_4333
+.globl sym_2_4334
+sym_2_4334: la $2, sym_2_4334
+.globl sym_2_4335
+sym_2_4335: la $2, sym_2_4335
+.globl sym_2_4336
+sym_2_4336: la $2, sym_2_4336
+.globl sym_2_4337
+sym_2_4337: la $2, sym_2_4337
+.globl sym_2_4338
+sym_2_4338: la $2, sym_2_4338
+.globl sym_2_4339
+sym_2_4339: la $2, sym_2_4339
+.globl sym_2_4340
+sym_2_4340: la $2, sym_2_4340
+.globl sym_2_4341
+sym_2_4341: la $2, sym_2_4341
+.globl sym_2_4342
+sym_2_4342: la $2, sym_2_4342
+.globl sym_2_4343
+sym_2_4343: la $2, sym_2_4343
+.globl sym_2_4344
+sym_2_4344: la $2, sym_2_4344
+.globl sym_2_4345
+sym_2_4345: la $2, sym_2_4345
+.globl sym_2_4346
+sym_2_4346: la $2, sym_2_4346
+.globl sym_2_4347
+sym_2_4347: la $2, sym_2_4347
+.globl sym_2_4348
+sym_2_4348: la $2, sym_2_4348
+.globl sym_2_4349
+sym_2_4349: la $2, sym_2_4349
+.globl sym_2_4350
+sym_2_4350: la $2, sym_2_4350
+.globl sym_2_4351
+sym_2_4351: la $2, sym_2_4351
+.globl sym_2_4352
+sym_2_4352: la $2, sym_2_4352
+.globl sym_2_4353
+sym_2_4353: la $2, sym_2_4353
+.globl sym_2_4354
+sym_2_4354: la $2, sym_2_4354
+.globl sym_2_4355
+sym_2_4355: la $2, sym_2_4355
+.globl sym_2_4356
+sym_2_4356: la $2, sym_2_4356
+.globl sym_2_4357
+sym_2_4357: la $2, sym_2_4357
+.globl sym_2_4358
+sym_2_4358: la $2, sym_2_4358
+.globl sym_2_4359
+sym_2_4359: la $2, sym_2_4359
+.globl sym_2_4360
+sym_2_4360: la $2, sym_2_4360
+.globl sym_2_4361
+sym_2_4361: la $2, sym_2_4361
+.globl sym_2_4362
+sym_2_4362: la $2, sym_2_4362
+.globl sym_2_4363
+sym_2_4363: la $2, sym_2_4363
+.globl sym_2_4364
+sym_2_4364: la $2, sym_2_4364
+.globl sym_2_4365
+sym_2_4365: la $2, sym_2_4365
+.globl sym_2_4366
+sym_2_4366: la $2, sym_2_4366
+.globl sym_2_4367
+sym_2_4367: la $2, sym_2_4367
+.globl sym_2_4368
+sym_2_4368: la $2, sym_2_4368
+.globl sym_2_4369
+sym_2_4369: la $2, sym_2_4369
+.globl sym_2_4370
+sym_2_4370: la $2, sym_2_4370
+.globl sym_2_4371
+sym_2_4371: la $2, sym_2_4371
+.globl sym_2_4372
+sym_2_4372: la $2, sym_2_4372
+.globl sym_2_4373
+sym_2_4373: la $2, sym_2_4373
+.globl sym_2_4374
+sym_2_4374: la $2, sym_2_4374
+.globl sym_2_4375
+sym_2_4375: la $2, sym_2_4375
+.globl sym_2_4376
+sym_2_4376: la $2, sym_2_4376
+.globl sym_2_4377
+sym_2_4377: la $2, sym_2_4377
+.globl sym_2_4378
+sym_2_4378: la $2, sym_2_4378
+.globl sym_2_4379
+sym_2_4379: la $2, sym_2_4379
+.globl sym_2_4380
+sym_2_4380: la $2, sym_2_4380
+.globl sym_2_4381
+sym_2_4381: la $2, sym_2_4381
+.globl sym_2_4382
+sym_2_4382: la $2, sym_2_4382
+.globl sym_2_4383
+sym_2_4383: la $2, sym_2_4383
+.globl sym_2_4384
+sym_2_4384: la $2, sym_2_4384
+.globl sym_2_4385
+sym_2_4385: la $2, sym_2_4385
+.globl sym_2_4386
+sym_2_4386: la $2, sym_2_4386
+.globl sym_2_4387
+sym_2_4387: la $2, sym_2_4387
+.globl sym_2_4388
+sym_2_4388: la $2, sym_2_4388
+.globl sym_2_4389
+sym_2_4389: la $2, sym_2_4389
+.globl sym_2_4390
+sym_2_4390: la $2, sym_2_4390
+.globl sym_2_4391
+sym_2_4391: la $2, sym_2_4391
+.globl sym_2_4392
+sym_2_4392: la $2, sym_2_4392
+.globl sym_2_4393
+sym_2_4393: la $2, sym_2_4393
+.globl sym_2_4394
+sym_2_4394: la $2, sym_2_4394
+.globl sym_2_4395
+sym_2_4395: la $2, sym_2_4395
+.globl sym_2_4396
+sym_2_4396: la $2, sym_2_4396
+.globl sym_2_4397
+sym_2_4397: la $2, sym_2_4397
+.globl sym_2_4398
+sym_2_4398: la $2, sym_2_4398
+.globl sym_2_4399
+sym_2_4399: la $2, sym_2_4399
+.globl sym_2_4400
+sym_2_4400: la $2, sym_2_4400
+.globl sym_2_4401
+sym_2_4401: la $2, sym_2_4401
+.globl sym_2_4402
+sym_2_4402: la $2, sym_2_4402
+.globl sym_2_4403
+sym_2_4403: la $2, sym_2_4403
+.globl sym_2_4404
+sym_2_4404: la $2, sym_2_4404
+.globl sym_2_4405
+sym_2_4405: la $2, sym_2_4405
+.globl sym_2_4406
+sym_2_4406: la $2, sym_2_4406
+.globl sym_2_4407
+sym_2_4407: la $2, sym_2_4407
+.globl sym_2_4408
+sym_2_4408: la $2, sym_2_4408
+.globl sym_2_4409
+sym_2_4409: la $2, sym_2_4409
+.globl sym_2_4410
+sym_2_4410: la $2, sym_2_4410
+.globl sym_2_4411
+sym_2_4411: la $2, sym_2_4411
+.globl sym_2_4412
+sym_2_4412: la $2, sym_2_4412
+.globl sym_2_4413
+sym_2_4413: la $2, sym_2_4413
+.globl sym_2_4414
+sym_2_4414: la $2, sym_2_4414
+.globl sym_2_4415
+sym_2_4415: la $2, sym_2_4415
+.globl sym_2_4416
+sym_2_4416: la $2, sym_2_4416
+.globl sym_2_4417
+sym_2_4417: la $2, sym_2_4417
+.globl sym_2_4418
+sym_2_4418: la $2, sym_2_4418
+.globl sym_2_4419
+sym_2_4419: la $2, sym_2_4419
+.globl sym_2_4420
+sym_2_4420: la $2, sym_2_4420
+.globl sym_2_4421
+sym_2_4421: la $2, sym_2_4421
+.globl sym_2_4422
+sym_2_4422: la $2, sym_2_4422
+.globl sym_2_4423
+sym_2_4423: la $2, sym_2_4423
+.globl sym_2_4424
+sym_2_4424: la $2, sym_2_4424
+.globl sym_2_4425
+sym_2_4425: la $2, sym_2_4425
+.globl sym_2_4426
+sym_2_4426: la $2, sym_2_4426
+.globl sym_2_4427
+sym_2_4427: la $2, sym_2_4427
+.globl sym_2_4428
+sym_2_4428: la $2, sym_2_4428
+.globl sym_2_4429
+sym_2_4429: la $2, sym_2_4429
+.globl sym_2_4430
+sym_2_4430: la $2, sym_2_4430
+.globl sym_2_4431
+sym_2_4431: la $2, sym_2_4431
+.globl sym_2_4432
+sym_2_4432: la $2, sym_2_4432
+.globl sym_2_4433
+sym_2_4433: la $2, sym_2_4433
+.globl sym_2_4434
+sym_2_4434: la $2, sym_2_4434
+.globl sym_2_4435
+sym_2_4435: la $2, sym_2_4435
+.globl sym_2_4436
+sym_2_4436: la $2, sym_2_4436
+.globl sym_2_4437
+sym_2_4437: la $2, sym_2_4437
+.globl sym_2_4438
+sym_2_4438: la $2, sym_2_4438
+.globl sym_2_4439
+sym_2_4439: la $2, sym_2_4439
+.globl sym_2_4440
+sym_2_4440: la $2, sym_2_4440
+.globl sym_2_4441
+sym_2_4441: la $2, sym_2_4441
+.globl sym_2_4442
+sym_2_4442: la $2, sym_2_4442
+.globl sym_2_4443
+sym_2_4443: la $2, sym_2_4443
+.globl sym_2_4444
+sym_2_4444: la $2, sym_2_4444
+.globl sym_2_4445
+sym_2_4445: la $2, sym_2_4445
+.globl sym_2_4446
+sym_2_4446: la $2, sym_2_4446
+.globl sym_2_4447
+sym_2_4447: la $2, sym_2_4447
+.globl sym_2_4448
+sym_2_4448: la $2, sym_2_4448
+.globl sym_2_4449
+sym_2_4449: la $2, sym_2_4449
+.globl sym_2_4450
+sym_2_4450: la $2, sym_2_4450
+.globl sym_2_4451
+sym_2_4451: la $2, sym_2_4451
+.globl sym_2_4452
+sym_2_4452: la $2, sym_2_4452
+.globl sym_2_4453
+sym_2_4453: la $2, sym_2_4453
+.globl sym_2_4454
+sym_2_4454: la $2, sym_2_4454
+.globl sym_2_4455
+sym_2_4455: la $2, sym_2_4455
+.globl sym_2_4456
+sym_2_4456: la $2, sym_2_4456
+.globl sym_2_4457
+sym_2_4457: la $2, sym_2_4457
+.globl sym_2_4458
+sym_2_4458: la $2, sym_2_4458
+.globl sym_2_4459
+sym_2_4459: la $2, sym_2_4459
+.globl sym_2_4460
+sym_2_4460: la $2, sym_2_4460
+.globl sym_2_4461
+sym_2_4461: la $2, sym_2_4461
+.globl sym_2_4462
+sym_2_4462: la $2, sym_2_4462
+.globl sym_2_4463
+sym_2_4463: la $2, sym_2_4463
+.globl sym_2_4464
+sym_2_4464: la $2, sym_2_4464
+.globl sym_2_4465
+sym_2_4465: la $2, sym_2_4465
+.globl sym_2_4466
+sym_2_4466: la $2, sym_2_4466
+.globl sym_2_4467
+sym_2_4467: la $2, sym_2_4467
+.globl sym_2_4468
+sym_2_4468: la $2, sym_2_4468
+.globl sym_2_4469
+sym_2_4469: la $2, sym_2_4469
+.globl sym_2_4470
+sym_2_4470: la $2, sym_2_4470
+.globl sym_2_4471
+sym_2_4471: la $2, sym_2_4471
+.globl sym_2_4472
+sym_2_4472: la $2, sym_2_4472
+.globl sym_2_4473
+sym_2_4473: la $2, sym_2_4473
+.globl sym_2_4474
+sym_2_4474: la $2, sym_2_4474
+.globl sym_2_4475
+sym_2_4475: la $2, sym_2_4475
+.globl sym_2_4476
+sym_2_4476: la $2, sym_2_4476
+.globl sym_2_4477
+sym_2_4477: la $2, sym_2_4477
+.globl sym_2_4478
+sym_2_4478: la $2, sym_2_4478
+.globl sym_2_4479
+sym_2_4479: la $2, sym_2_4479
+.globl sym_2_4480
+sym_2_4480: la $2, sym_2_4480
+.globl sym_2_4481
+sym_2_4481: la $2, sym_2_4481
+.globl sym_2_4482
+sym_2_4482: la $2, sym_2_4482
+.globl sym_2_4483
+sym_2_4483: la $2, sym_2_4483
+.globl sym_2_4484
+sym_2_4484: la $2, sym_2_4484
+.globl sym_2_4485
+sym_2_4485: la $2, sym_2_4485
+.globl sym_2_4486
+sym_2_4486: la $2, sym_2_4486
+.globl sym_2_4487
+sym_2_4487: la $2, sym_2_4487
+.globl sym_2_4488
+sym_2_4488: la $2, sym_2_4488
+.globl sym_2_4489
+sym_2_4489: la $2, sym_2_4489
+.globl sym_2_4490
+sym_2_4490: la $2, sym_2_4490
+.globl sym_2_4491
+sym_2_4491: la $2, sym_2_4491
+.globl sym_2_4492
+sym_2_4492: la $2, sym_2_4492
+.globl sym_2_4493
+sym_2_4493: la $2, sym_2_4493
+.globl sym_2_4494
+sym_2_4494: la $2, sym_2_4494
+.globl sym_2_4495
+sym_2_4495: la $2, sym_2_4495
+.globl sym_2_4496
+sym_2_4496: la $2, sym_2_4496
+.globl sym_2_4497
+sym_2_4497: la $2, sym_2_4497
+.globl sym_2_4498
+sym_2_4498: la $2, sym_2_4498
+.globl sym_2_4499
+sym_2_4499: la $2, sym_2_4499
+.globl sym_2_4500
+sym_2_4500: la $2, sym_2_4500
+.globl sym_2_4501
+sym_2_4501: la $2, sym_2_4501
+.globl sym_2_4502
+sym_2_4502: la $2, sym_2_4502
+.globl sym_2_4503
+sym_2_4503: la $2, sym_2_4503
+.globl sym_2_4504
+sym_2_4504: la $2, sym_2_4504
+.globl sym_2_4505
+sym_2_4505: la $2, sym_2_4505
+.globl sym_2_4506
+sym_2_4506: la $2, sym_2_4506
+.globl sym_2_4507
+sym_2_4507: la $2, sym_2_4507
+.globl sym_2_4508
+sym_2_4508: la $2, sym_2_4508
+.globl sym_2_4509
+sym_2_4509: la $2, sym_2_4509
+.globl sym_2_4510
+sym_2_4510: la $2, sym_2_4510
+.globl sym_2_4511
+sym_2_4511: la $2, sym_2_4511
+.globl sym_2_4512
+sym_2_4512: la $2, sym_2_4512
+.globl sym_2_4513
+sym_2_4513: la $2, sym_2_4513
+.globl sym_2_4514
+sym_2_4514: la $2, sym_2_4514
+.globl sym_2_4515
+sym_2_4515: la $2, sym_2_4515
+.globl sym_2_4516
+sym_2_4516: la $2, sym_2_4516
+.globl sym_2_4517
+sym_2_4517: la $2, sym_2_4517
+.globl sym_2_4518
+sym_2_4518: la $2, sym_2_4518
+.globl sym_2_4519
+sym_2_4519: la $2, sym_2_4519
+.globl sym_2_4520
+sym_2_4520: la $2, sym_2_4520
+.globl sym_2_4521
+sym_2_4521: la $2, sym_2_4521
+.globl sym_2_4522
+sym_2_4522: la $2, sym_2_4522
+.globl sym_2_4523
+sym_2_4523: la $2, sym_2_4523
+.globl sym_2_4524
+sym_2_4524: la $2, sym_2_4524
+.globl sym_2_4525
+sym_2_4525: la $2, sym_2_4525
+.globl sym_2_4526
+sym_2_4526: la $2, sym_2_4526
+.globl sym_2_4527
+sym_2_4527: la $2, sym_2_4527
+.globl sym_2_4528
+sym_2_4528: la $2, sym_2_4528
+.globl sym_2_4529
+sym_2_4529: la $2, sym_2_4529
+.globl sym_2_4530
+sym_2_4530: la $2, sym_2_4530
+.globl sym_2_4531
+sym_2_4531: la $2, sym_2_4531
+.globl sym_2_4532
+sym_2_4532: la $2, sym_2_4532
+.globl sym_2_4533
+sym_2_4533: la $2, sym_2_4533
+.globl sym_2_4534
+sym_2_4534: la $2, sym_2_4534
+.globl sym_2_4535
+sym_2_4535: la $2, sym_2_4535
+.globl sym_2_4536
+sym_2_4536: la $2, sym_2_4536
+.globl sym_2_4537
+sym_2_4537: la $2, sym_2_4537
+.globl sym_2_4538
+sym_2_4538: la $2, sym_2_4538
+.globl sym_2_4539
+sym_2_4539: la $2, sym_2_4539
+.globl sym_2_4540
+sym_2_4540: la $2, sym_2_4540
+.globl sym_2_4541
+sym_2_4541: la $2, sym_2_4541
+.globl sym_2_4542
+sym_2_4542: la $2, sym_2_4542
+.globl sym_2_4543
+sym_2_4543: la $2, sym_2_4543
+.globl sym_2_4544
+sym_2_4544: la $2, sym_2_4544
+.globl sym_2_4545
+sym_2_4545: la $2, sym_2_4545
+.globl sym_2_4546
+sym_2_4546: la $2, sym_2_4546
+.globl sym_2_4547
+sym_2_4547: la $2, sym_2_4547
+.globl sym_2_4548
+sym_2_4548: la $2, sym_2_4548
+.globl sym_2_4549
+sym_2_4549: la $2, sym_2_4549
+.globl sym_2_4550
+sym_2_4550: la $2, sym_2_4550
+.globl sym_2_4551
+sym_2_4551: la $2, sym_2_4551
+.globl sym_2_4552
+sym_2_4552: la $2, sym_2_4552
+.globl sym_2_4553
+sym_2_4553: la $2, sym_2_4553
+.globl sym_2_4554
+sym_2_4554: la $2, sym_2_4554
+.globl sym_2_4555
+sym_2_4555: la $2, sym_2_4555
+.globl sym_2_4556
+sym_2_4556: la $2, sym_2_4556
+.globl sym_2_4557
+sym_2_4557: la $2, sym_2_4557
+.globl sym_2_4558
+sym_2_4558: la $2, sym_2_4558
+.globl sym_2_4559
+sym_2_4559: la $2, sym_2_4559
+.globl sym_2_4560
+sym_2_4560: la $2, sym_2_4560
+.globl sym_2_4561
+sym_2_4561: la $2, sym_2_4561
+.globl sym_2_4562
+sym_2_4562: la $2, sym_2_4562
+.globl sym_2_4563
+sym_2_4563: la $2, sym_2_4563
+.globl sym_2_4564
+sym_2_4564: la $2, sym_2_4564
+.globl sym_2_4565
+sym_2_4565: la $2, sym_2_4565
+.globl sym_2_4566
+sym_2_4566: la $2, sym_2_4566
+.globl sym_2_4567
+sym_2_4567: la $2, sym_2_4567
+.globl sym_2_4568
+sym_2_4568: la $2, sym_2_4568
+.globl sym_2_4569
+sym_2_4569: la $2, sym_2_4569
+.globl sym_2_4570
+sym_2_4570: la $2, sym_2_4570
+.globl sym_2_4571
+sym_2_4571: la $2, sym_2_4571
+.globl sym_2_4572
+sym_2_4572: la $2, sym_2_4572
+.globl sym_2_4573
+sym_2_4573: la $2, sym_2_4573
+.globl sym_2_4574
+sym_2_4574: la $2, sym_2_4574
+.globl sym_2_4575
+sym_2_4575: la $2, sym_2_4575
+.globl sym_2_4576
+sym_2_4576: la $2, sym_2_4576
+.globl sym_2_4577
+sym_2_4577: la $2, sym_2_4577
+.globl sym_2_4578
+sym_2_4578: la $2, sym_2_4578
+.globl sym_2_4579
+sym_2_4579: la $2, sym_2_4579
+.globl sym_2_4580
+sym_2_4580: la $2, sym_2_4580
+.globl sym_2_4581
+sym_2_4581: la $2, sym_2_4581
+.globl sym_2_4582
+sym_2_4582: la $2, sym_2_4582
+.globl sym_2_4583
+sym_2_4583: la $2, sym_2_4583
+.globl sym_2_4584
+sym_2_4584: la $2, sym_2_4584
+.globl sym_2_4585
+sym_2_4585: la $2, sym_2_4585
+.globl sym_2_4586
+sym_2_4586: la $2, sym_2_4586
+.globl sym_2_4587
+sym_2_4587: la $2, sym_2_4587
+.globl sym_2_4588
+sym_2_4588: la $2, sym_2_4588
+.globl sym_2_4589
+sym_2_4589: la $2, sym_2_4589
+.globl sym_2_4590
+sym_2_4590: la $2, sym_2_4590
+.globl sym_2_4591
+sym_2_4591: la $2, sym_2_4591
+.globl sym_2_4592
+sym_2_4592: la $2, sym_2_4592
+.globl sym_2_4593
+sym_2_4593: la $2, sym_2_4593
+.globl sym_2_4594
+sym_2_4594: la $2, sym_2_4594
+.globl sym_2_4595
+sym_2_4595: la $2, sym_2_4595
+.globl sym_2_4596
+sym_2_4596: la $2, sym_2_4596
+.globl sym_2_4597
+sym_2_4597: la $2, sym_2_4597
+.globl sym_2_4598
+sym_2_4598: la $2, sym_2_4598
+.globl sym_2_4599
+sym_2_4599: la $2, sym_2_4599
+.globl sym_2_4600
+sym_2_4600: la $2, sym_2_4600
+.globl sym_2_4601
+sym_2_4601: la $2, sym_2_4601
+.globl sym_2_4602
+sym_2_4602: la $2, sym_2_4602
+.globl sym_2_4603
+sym_2_4603: la $2, sym_2_4603
+.globl sym_2_4604
+sym_2_4604: la $2, sym_2_4604
+.globl sym_2_4605
+sym_2_4605: la $2, sym_2_4605
+.globl sym_2_4606
+sym_2_4606: la $2, sym_2_4606
+.globl sym_2_4607
+sym_2_4607: la $2, sym_2_4607
+.globl sym_2_4608
+sym_2_4608: la $2, sym_2_4608
+.globl sym_2_4609
+sym_2_4609: la $2, sym_2_4609
+.globl sym_2_4610
+sym_2_4610: la $2, sym_2_4610
+.globl sym_2_4611
+sym_2_4611: la $2, sym_2_4611
+.globl sym_2_4612
+sym_2_4612: la $2, sym_2_4612
+.globl sym_2_4613
+sym_2_4613: la $2, sym_2_4613
+.globl sym_2_4614
+sym_2_4614: la $2, sym_2_4614
+.globl sym_2_4615
+sym_2_4615: la $2, sym_2_4615
+.globl sym_2_4616
+sym_2_4616: la $2, sym_2_4616
+.globl sym_2_4617
+sym_2_4617: la $2, sym_2_4617
+.globl sym_2_4618
+sym_2_4618: la $2, sym_2_4618
+.globl sym_2_4619
+sym_2_4619: la $2, sym_2_4619
+.globl sym_2_4620
+sym_2_4620: la $2, sym_2_4620
+.globl sym_2_4621
+sym_2_4621: la $2, sym_2_4621
+.globl sym_2_4622
+sym_2_4622: la $2, sym_2_4622
+.globl sym_2_4623
+sym_2_4623: la $2, sym_2_4623
+.globl sym_2_4624
+sym_2_4624: la $2, sym_2_4624
+.globl sym_2_4625
+sym_2_4625: la $2, sym_2_4625
+.globl sym_2_4626
+sym_2_4626: la $2, sym_2_4626
+.globl sym_2_4627
+sym_2_4627: la $2, sym_2_4627
+.globl sym_2_4628
+sym_2_4628: la $2, sym_2_4628
+.globl sym_2_4629
+sym_2_4629: la $2, sym_2_4629
+.globl sym_2_4630
+sym_2_4630: la $2, sym_2_4630
+.globl sym_2_4631
+sym_2_4631: la $2, sym_2_4631
+.globl sym_2_4632
+sym_2_4632: la $2, sym_2_4632
+.globl sym_2_4633
+sym_2_4633: la $2, sym_2_4633
+.globl sym_2_4634
+sym_2_4634: la $2, sym_2_4634
+.globl sym_2_4635
+sym_2_4635: la $2, sym_2_4635
+.globl sym_2_4636
+sym_2_4636: la $2, sym_2_4636
+.globl sym_2_4637
+sym_2_4637: la $2, sym_2_4637
+.globl sym_2_4638
+sym_2_4638: la $2, sym_2_4638
+.globl sym_2_4639
+sym_2_4639: la $2, sym_2_4639
+.globl sym_2_4640
+sym_2_4640: la $2, sym_2_4640
+.globl sym_2_4641
+sym_2_4641: la $2, sym_2_4641
+.globl sym_2_4642
+sym_2_4642: la $2, sym_2_4642
+.globl sym_2_4643
+sym_2_4643: la $2, sym_2_4643
+.globl sym_2_4644
+sym_2_4644: la $2, sym_2_4644
+.globl sym_2_4645
+sym_2_4645: la $2, sym_2_4645
+.globl sym_2_4646
+sym_2_4646: la $2, sym_2_4646
+.globl sym_2_4647
+sym_2_4647: la $2, sym_2_4647
+.globl sym_2_4648
+sym_2_4648: la $2, sym_2_4648
+.globl sym_2_4649
+sym_2_4649: la $2, sym_2_4649
+.globl sym_2_4650
+sym_2_4650: la $2, sym_2_4650
+.globl sym_2_4651
+sym_2_4651: la $2, sym_2_4651
+.globl sym_2_4652
+sym_2_4652: la $2, sym_2_4652
+.globl sym_2_4653
+sym_2_4653: la $2, sym_2_4653
+.globl sym_2_4654
+sym_2_4654: la $2, sym_2_4654
+.globl sym_2_4655
+sym_2_4655: la $2, sym_2_4655
+.globl sym_2_4656
+sym_2_4656: la $2, sym_2_4656
+.globl sym_2_4657
+sym_2_4657: la $2, sym_2_4657
+.globl sym_2_4658
+sym_2_4658: la $2, sym_2_4658
+.globl sym_2_4659
+sym_2_4659: la $2, sym_2_4659
+.globl sym_2_4660
+sym_2_4660: la $2, sym_2_4660
+.globl sym_2_4661
+sym_2_4661: la $2, sym_2_4661
+.globl sym_2_4662
+sym_2_4662: la $2, sym_2_4662
+.globl sym_2_4663
+sym_2_4663: la $2, sym_2_4663
+.globl sym_2_4664
+sym_2_4664: la $2, sym_2_4664
+.globl sym_2_4665
+sym_2_4665: la $2, sym_2_4665
+.globl sym_2_4666
+sym_2_4666: la $2, sym_2_4666
+.globl sym_2_4667
+sym_2_4667: la $2, sym_2_4667
+.globl sym_2_4668
+sym_2_4668: la $2, sym_2_4668
+.globl sym_2_4669
+sym_2_4669: la $2, sym_2_4669
+.globl sym_2_4670
+sym_2_4670: la $2, sym_2_4670
+.globl sym_2_4671
+sym_2_4671: la $2, sym_2_4671
+.globl sym_2_4672
+sym_2_4672: la $2, sym_2_4672
+.globl sym_2_4673
+sym_2_4673: la $2, sym_2_4673
+.globl sym_2_4674
+sym_2_4674: la $2, sym_2_4674
+.globl sym_2_4675
+sym_2_4675: la $2, sym_2_4675
+.globl sym_2_4676
+sym_2_4676: la $2, sym_2_4676
+.globl sym_2_4677
+sym_2_4677: la $2, sym_2_4677
+.globl sym_2_4678
+sym_2_4678: la $2, sym_2_4678
+.globl sym_2_4679
+sym_2_4679: la $2, sym_2_4679
+.globl sym_2_4680
+sym_2_4680: la $2, sym_2_4680
+.globl sym_2_4681
+sym_2_4681: la $2, sym_2_4681
+.globl sym_2_4682
+sym_2_4682: la $2, sym_2_4682
+.globl sym_2_4683
+sym_2_4683: la $2, sym_2_4683
+.globl sym_2_4684
+sym_2_4684: la $2, sym_2_4684
+.globl sym_2_4685
+sym_2_4685: la $2, sym_2_4685
+.globl sym_2_4686
+sym_2_4686: la $2, sym_2_4686
+.globl sym_2_4687
+sym_2_4687: la $2, sym_2_4687
+.globl sym_2_4688
+sym_2_4688: la $2, sym_2_4688
+.globl sym_2_4689
+sym_2_4689: la $2, sym_2_4689
+.globl sym_2_4690
+sym_2_4690: la $2, sym_2_4690
+.globl sym_2_4691
+sym_2_4691: la $2, sym_2_4691
+.globl sym_2_4692
+sym_2_4692: la $2, sym_2_4692
+.globl sym_2_4693
+sym_2_4693: la $2, sym_2_4693
+.globl sym_2_4694
+sym_2_4694: la $2, sym_2_4694
+.globl sym_2_4695
+sym_2_4695: la $2, sym_2_4695
+.globl sym_2_4696
+sym_2_4696: la $2, sym_2_4696
+.globl sym_2_4697
+sym_2_4697: la $2, sym_2_4697
+.globl sym_2_4698
+sym_2_4698: la $2, sym_2_4698
+.globl sym_2_4699
+sym_2_4699: la $2, sym_2_4699
+.globl sym_2_4700
+sym_2_4700: la $2, sym_2_4700
+.globl sym_2_4701
+sym_2_4701: la $2, sym_2_4701
+.globl sym_2_4702
+sym_2_4702: la $2, sym_2_4702
+.globl sym_2_4703
+sym_2_4703: la $2, sym_2_4703
+.globl sym_2_4704
+sym_2_4704: la $2, sym_2_4704
+.globl sym_2_4705
+sym_2_4705: la $2, sym_2_4705
+.globl sym_2_4706
+sym_2_4706: la $2, sym_2_4706
+.globl sym_2_4707
+sym_2_4707: la $2, sym_2_4707
+.globl sym_2_4708
+sym_2_4708: la $2, sym_2_4708
+.globl sym_2_4709
+sym_2_4709: la $2, sym_2_4709
+.globl sym_2_4710
+sym_2_4710: la $2, sym_2_4710
+.globl sym_2_4711
+sym_2_4711: la $2, sym_2_4711
+.globl sym_2_4712
+sym_2_4712: la $2, sym_2_4712
+.globl sym_2_4713
+sym_2_4713: la $2, sym_2_4713
+.globl sym_2_4714
+sym_2_4714: la $2, sym_2_4714
+.globl sym_2_4715
+sym_2_4715: la $2, sym_2_4715
+.globl sym_2_4716
+sym_2_4716: la $2, sym_2_4716
+.globl sym_2_4717
+sym_2_4717: la $2, sym_2_4717
+.globl sym_2_4718
+sym_2_4718: la $2, sym_2_4718
+.globl sym_2_4719
+sym_2_4719: la $2, sym_2_4719
+.globl sym_2_4720
+sym_2_4720: la $2, sym_2_4720
+.globl sym_2_4721
+sym_2_4721: la $2, sym_2_4721
+.globl sym_2_4722
+sym_2_4722: la $2, sym_2_4722
+.globl sym_2_4723
+sym_2_4723: la $2, sym_2_4723
+.globl sym_2_4724
+sym_2_4724: la $2, sym_2_4724
+.globl sym_2_4725
+sym_2_4725: la $2, sym_2_4725
+.globl sym_2_4726
+sym_2_4726: la $2, sym_2_4726
+.globl sym_2_4727
+sym_2_4727: la $2, sym_2_4727
+.globl sym_2_4728
+sym_2_4728: la $2, sym_2_4728
+.globl sym_2_4729
+sym_2_4729: la $2, sym_2_4729
+.globl sym_2_4730
+sym_2_4730: la $2, sym_2_4730
+.globl sym_2_4731
+sym_2_4731: la $2, sym_2_4731
+.globl sym_2_4732
+sym_2_4732: la $2, sym_2_4732
+.globl sym_2_4733
+sym_2_4733: la $2, sym_2_4733
+.globl sym_2_4734
+sym_2_4734: la $2, sym_2_4734
+.globl sym_2_4735
+sym_2_4735: la $2, sym_2_4735
+.globl sym_2_4736
+sym_2_4736: la $2, sym_2_4736
+.globl sym_2_4737
+sym_2_4737: la $2, sym_2_4737
+.globl sym_2_4738
+sym_2_4738: la $2, sym_2_4738
+.globl sym_2_4739
+sym_2_4739: la $2, sym_2_4739
+.globl sym_2_4740
+sym_2_4740: la $2, sym_2_4740
+.globl sym_2_4741
+sym_2_4741: la $2, sym_2_4741
+.globl sym_2_4742
+sym_2_4742: la $2, sym_2_4742
+.globl sym_2_4743
+sym_2_4743: la $2, sym_2_4743
+.globl sym_2_4744
+sym_2_4744: la $2, sym_2_4744
+.globl sym_2_4745
+sym_2_4745: la $2, sym_2_4745
+.globl sym_2_4746
+sym_2_4746: la $2, sym_2_4746
+.globl sym_2_4747
+sym_2_4747: la $2, sym_2_4747
+.globl sym_2_4748
+sym_2_4748: la $2, sym_2_4748
+.globl sym_2_4749
+sym_2_4749: la $2, sym_2_4749
+.globl sym_2_4750
+sym_2_4750: la $2, sym_2_4750
+.globl sym_2_4751
+sym_2_4751: la $2, sym_2_4751
+.globl sym_2_4752
+sym_2_4752: la $2, sym_2_4752
+.globl sym_2_4753
+sym_2_4753: la $2, sym_2_4753
+.globl sym_2_4754
+sym_2_4754: la $2, sym_2_4754
+.globl sym_2_4755
+sym_2_4755: la $2, sym_2_4755
+.globl sym_2_4756
+sym_2_4756: la $2, sym_2_4756
+.globl sym_2_4757
+sym_2_4757: la $2, sym_2_4757
+.globl sym_2_4758
+sym_2_4758: la $2, sym_2_4758
+.globl sym_2_4759
+sym_2_4759: la $2, sym_2_4759
+.globl sym_2_4760
+sym_2_4760: la $2, sym_2_4760
+.globl sym_2_4761
+sym_2_4761: la $2, sym_2_4761
+.globl sym_2_4762
+sym_2_4762: la $2, sym_2_4762
+.globl sym_2_4763
+sym_2_4763: la $2, sym_2_4763
+.globl sym_2_4764
+sym_2_4764: la $2, sym_2_4764
+.globl sym_2_4765
+sym_2_4765: la $2, sym_2_4765
+.globl sym_2_4766
+sym_2_4766: la $2, sym_2_4766
+.globl sym_2_4767
+sym_2_4767: la $2, sym_2_4767
+.globl sym_2_4768
+sym_2_4768: la $2, sym_2_4768
+.globl sym_2_4769
+sym_2_4769: la $2, sym_2_4769
+.globl sym_2_4770
+sym_2_4770: la $2, sym_2_4770
+.globl sym_2_4771
+sym_2_4771: la $2, sym_2_4771
+.globl sym_2_4772
+sym_2_4772: la $2, sym_2_4772
+.globl sym_2_4773
+sym_2_4773: la $2, sym_2_4773
+.globl sym_2_4774
+sym_2_4774: la $2, sym_2_4774
+.globl sym_2_4775
+sym_2_4775: la $2, sym_2_4775
+.globl sym_2_4776
+sym_2_4776: la $2, sym_2_4776
+.globl sym_2_4777
+sym_2_4777: la $2, sym_2_4777
+.globl sym_2_4778
+sym_2_4778: la $2, sym_2_4778
+.globl sym_2_4779
+sym_2_4779: la $2, sym_2_4779
+.globl sym_2_4780
+sym_2_4780: la $2, sym_2_4780
+.globl sym_2_4781
+sym_2_4781: la $2, sym_2_4781
+.globl sym_2_4782
+sym_2_4782: la $2, sym_2_4782
+.globl sym_2_4783
+sym_2_4783: la $2, sym_2_4783
+.globl sym_2_4784
+sym_2_4784: la $2, sym_2_4784
+.globl sym_2_4785
+sym_2_4785: la $2, sym_2_4785
+.globl sym_2_4786
+sym_2_4786: la $2, sym_2_4786
+.globl sym_2_4787
+sym_2_4787: la $2, sym_2_4787
+.globl sym_2_4788
+sym_2_4788: la $2, sym_2_4788
+.globl sym_2_4789
+sym_2_4789: la $2, sym_2_4789
+.globl sym_2_4790
+sym_2_4790: la $2, sym_2_4790
+.globl sym_2_4791
+sym_2_4791: la $2, sym_2_4791
+.globl sym_2_4792
+sym_2_4792: la $2, sym_2_4792
+.globl sym_2_4793
+sym_2_4793: la $2, sym_2_4793
+.globl sym_2_4794
+sym_2_4794: la $2, sym_2_4794
+.globl sym_2_4795
+sym_2_4795: la $2, sym_2_4795
+.globl sym_2_4796
+sym_2_4796: la $2, sym_2_4796
+.globl sym_2_4797
+sym_2_4797: la $2, sym_2_4797
+.globl sym_2_4798
+sym_2_4798: la $2, sym_2_4798
+.globl sym_2_4799
+sym_2_4799: la $2, sym_2_4799
+.globl sym_2_4800
+sym_2_4800: la $2, sym_2_4800
+.globl sym_2_4801
+sym_2_4801: la $2, sym_2_4801
+.globl sym_2_4802
+sym_2_4802: la $2, sym_2_4802
+.globl sym_2_4803
+sym_2_4803: la $2, sym_2_4803
+.globl sym_2_4804
+sym_2_4804: la $2, sym_2_4804
+.globl sym_2_4805
+sym_2_4805: la $2, sym_2_4805
+.globl sym_2_4806
+sym_2_4806: la $2, sym_2_4806
+.globl sym_2_4807
+sym_2_4807: la $2, sym_2_4807
+.globl sym_2_4808
+sym_2_4808: la $2, sym_2_4808
+.globl sym_2_4809
+sym_2_4809: la $2, sym_2_4809
+.globl sym_2_4810
+sym_2_4810: la $2, sym_2_4810
+.globl sym_2_4811
+sym_2_4811: la $2, sym_2_4811
+.globl sym_2_4812
+sym_2_4812: la $2, sym_2_4812
+.globl sym_2_4813
+sym_2_4813: la $2, sym_2_4813
+.globl sym_2_4814
+sym_2_4814: la $2, sym_2_4814
+.globl sym_2_4815
+sym_2_4815: la $2, sym_2_4815
+.globl sym_2_4816
+sym_2_4816: la $2, sym_2_4816
+.globl sym_2_4817
+sym_2_4817: la $2, sym_2_4817
+.globl sym_2_4818
+sym_2_4818: la $2, sym_2_4818
+.globl sym_2_4819
+sym_2_4819: la $2, sym_2_4819
+.globl sym_2_4820
+sym_2_4820: la $2, sym_2_4820
+.globl sym_2_4821
+sym_2_4821: la $2, sym_2_4821
+.globl sym_2_4822
+sym_2_4822: la $2, sym_2_4822
+.globl sym_2_4823
+sym_2_4823: la $2, sym_2_4823
+.globl sym_2_4824
+sym_2_4824: la $2, sym_2_4824
+.globl sym_2_4825
+sym_2_4825: la $2, sym_2_4825
+.globl sym_2_4826
+sym_2_4826: la $2, sym_2_4826
+.globl sym_2_4827
+sym_2_4827: la $2, sym_2_4827
+.globl sym_2_4828
+sym_2_4828: la $2, sym_2_4828
+.globl sym_2_4829
+sym_2_4829: la $2, sym_2_4829
+.globl sym_2_4830
+sym_2_4830: la $2, sym_2_4830
+.globl sym_2_4831
+sym_2_4831: la $2, sym_2_4831
+.globl sym_2_4832
+sym_2_4832: la $2, sym_2_4832
+.globl sym_2_4833
+sym_2_4833: la $2, sym_2_4833
+.globl sym_2_4834
+sym_2_4834: la $2, sym_2_4834
+.globl sym_2_4835
+sym_2_4835: la $2, sym_2_4835
+.globl sym_2_4836
+sym_2_4836: la $2, sym_2_4836
+.globl sym_2_4837
+sym_2_4837: la $2, sym_2_4837
+.globl sym_2_4838
+sym_2_4838: la $2, sym_2_4838
+.globl sym_2_4839
+sym_2_4839: la $2, sym_2_4839
+.globl sym_2_4840
+sym_2_4840: la $2, sym_2_4840
+.globl sym_2_4841
+sym_2_4841: la $2, sym_2_4841
+.globl sym_2_4842
+sym_2_4842: la $2, sym_2_4842
+.globl sym_2_4843
+sym_2_4843: la $2, sym_2_4843
+.globl sym_2_4844
+sym_2_4844: la $2, sym_2_4844
+.globl sym_2_4845
+sym_2_4845: la $2, sym_2_4845
+.globl sym_2_4846
+sym_2_4846: la $2, sym_2_4846
+.globl sym_2_4847
+sym_2_4847: la $2, sym_2_4847
+.globl sym_2_4848
+sym_2_4848: la $2, sym_2_4848
+.globl sym_2_4849
+sym_2_4849: la $2, sym_2_4849
+.globl sym_2_4850
+sym_2_4850: la $2, sym_2_4850
+.globl sym_2_4851
+sym_2_4851: la $2, sym_2_4851
+.globl sym_2_4852
+sym_2_4852: la $2, sym_2_4852
+.globl sym_2_4853
+sym_2_4853: la $2, sym_2_4853
+.globl sym_2_4854
+sym_2_4854: la $2, sym_2_4854
+.globl sym_2_4855
+sym_2_4855: la $2, sym_2_4855
+.globl sym_2_4856
+sym_2_4856: la $2, sym_2_4856
+.globl sym_2_4857
+sym_2_4857: la $2, sym_2_4857
+.globl sym_2_4858
+sym_2_4858: la $2, sym_2_4858
+.globl sym_2_4859
+sym_2_4859: la $2, sym_2_4859
+.globl sym_2_4860
+sym_2_4860: la $2, sym_2_4860
+.globl sym_2_4861
+sym_2_4861: la $2, sym_2_4861
+.globl sym_2_4862
+sym_2_4862: la $2, sym_2_4862
+.globl sym_2_4863
+sym_2_4863: la $2, sym_2_4863
+.globl sym_2_4864
+sym_2_4864: la $2, sym_2_4864
+.globl sym_2_4865
+sym_2_4865: la $2, sym_2_4865
+.globl sym_2_4866
+sym_2_4866: la $2, sym_2_4866
+.globl sym_2_4867
+sym_2_4867: la $2, sym_2_4867
+.globl sym_2_4868
+sym_2_4868: la $2, sym_2_4868
+.globl sym_2_4869
+sym_2_4869: la $2, sym_2_4869
+.globl sym_2_4870
+sym_2_4870: la $2, sym_2_4870
+.globl sym_2_4871
+sym_2_4871: la $2, sym_2_4871
+.globl sym_2_4872
+sym_2_4872: la $2, sym_2_4872
+.globl sym_2_4873
+sym_2_4873: la $2, sym_2_4873
+.globl sym_2_4874
+sym_2_4874: la $2, sym_2_4874
+.globl sym_2_4875
+sym_2_4875: la $2, sym_2_4875
+.globl sym_2_4876
+sym_2_4876: la $2, sym_2_4876
+.globl sym_2_4877
+sym_2_4877: la $2, sym_2_4877
+.globl sym_2_4878
+sym_2_4878: la $2, sym_2_4878
+.globl sym_2_4879
+sym_2_4879: la $2, sym_2_4879
+.globl sym_2_4880
+sym_2_4880: la $2, sym_2_4880
+.globl sym_2_4881
+sym_2_4881: la $2, sym_2_4881
+.globl sym_2_4882
+sym_2_4882: la $2, sym_2_4882
+.globl sym_2_4883
+sym_2_4883: la $2, sym_2_4883
+.globl sym_2_4884
+sym_2_4884: la $2, sym_2_4884
+.globl sym_2_4885
+sym_2_4885: la $2, sym_2_4885
+.globl sym_2_4886
+sym_2_4886: la $2, sym_2_4886
+.globl sym_2_4887
+sym_2_4887: la $2, sym_2_4887
+.globl sym_2_4888
+sym_2_4888: la $2, sym_2_4888
+.globl sym_2_4889
+sym_2_4889: la $2, sym_2_4889
+.globl sym_2_4890
+sym_2_4890: la $2, sym_2_4890
+.globl sym_2_4891
+sym_2_4891: la $2, sym_2_4891
+.globl sym_2_4892
+sym_2_4892: la $2, sym_2_4892
+.globl sym_2_4893
+sym_2_4893: la $2, sym_2_4893
+.globl sym_2_4894
+sym_2_4894: la $2, sym_2_4894
+.globl sym_2_4895
+sym_2_4895: la $2, sym_2_4895
+.globl sym_2_4896
+sym_2_4896: la $2, sym_2_4896
+.globl sym_2_4897
+sym_2_4897: la $2, sym_2_4897
+.globl sym_2_4898
+sym_2_4898: la $2, sym_2_4898
+.globl sym_2_4899
+sym_2_4899: la $2, sym_2_4899
+.globl sym_2_4900
+sym_2_4900: la $2, sym_2_4900
+.globl sym_2_4901
+sym_2_4901: la $2, sym_2_4901
+.globl sym_2_4902
+sym_2_4902: la $2, sym_2_4902
+.globl sym_2_4903
+sym_2_4903: la $2, sym_2_4903
+.globl sym_2_4904
+sym_2_4904: la $2, sym_2_4904
+.globl sym_2_4905
+sym_2_4905: la $2, sym_2_4905
+.globl sym_2_4906
+sym_2_4906: la $2, sym_2_4906
+.globl sym_2_4907
+sym_2_4907: la $2, sym_2_4907
+.globl sym_2_4908
+sym_2_4908: la $2, sym_2_4908
+.globl sym_2_4909
+sym_2_4909: la $2, sym_2_4909
+.globl sym_2_4910
+sym_2_4910: la $2, sym_2_4910
+.globl sym_2_4911
+sym_2_4911: la $2, sym_2_4911
+.globl sym_2_4912
+sym_2_4912: la $2, sym_2_4912
+.globl sym_2_4913
+sym_2_4913: la $2, sym_2_4913
+.globl sym_2_4914
+sym_2_4914: la $2, sym_2_4914
+.globl sym_2_4915
+sym_2_4915: la $2, sym_2_4915
+.globl sym_2_4916
+sym_2_4916: la $2, sym_2_4916
+.globl sym_2_4917
+sym_2_4917: la $2, sym_2_4917
+.globl sym_2_4918
+sym_2_4918: la $2, sym_2_4918
+.globl sym_2_4919
+sym_2_4919: la $2, sym_2_4919
+.globl sym_2_4920
+sym_2_4920: la $2, sym_2_4920
+.globl sym_2_4921
+sym_2_4921: la $2, sym_2_4921
+.globl sym_2_4922
+sym_2_4922: la $2, sym_2_4922
+.globl sym_2_4923
+sym_2_4923: la $2, sym_2_4923
+.globl sym_2_4924
+sym_2_4924: la $2, sym_2_4924
+.globl sym_2_4925
+sym_2_4925: la $2, sym_2_4925
+.globl sym_2_4926
+sym_2_4926: la $2, sym_2_4926
+.globl sym_2_4927
+sym_2_4927: la $2, sym_2_4927
+.globl sym_2_4928
+sym_2_4928: la $2, sym_2_4928
+.globl sym_2_4929
+sym_2_4929: la $2, sym_2_4929
+.globl sym_2_4930
+sym_2_4930: la $2, sym_2_4930
+.globl sym_2_4931
+sym_2_4931: la $2, sym_2_4931
+.globl sym_2_4932
+sym_2_4932: la $2, sym_2_4932
+.globl sym_2_4933
+sym_2_4933: la $2, sym_2_4933
+.globl sym_2_4934
+sym_2_4934: la $2, sym_2_4934
+.globl sym_2_4935
+sym_2_4935: la $2, sym_2_4935
+.globl sym_2_4936
+sym_2_4936: la $2, sym_2_4936
+.globl sym_2_4937
+sym_2_4937: la $2, sym_2_4937
+.globl sym_2_4938
+sym_2_4938: la $2, sym_2_4938
+.globl sym_2_4939
+sym_2_4939: la $2, sym_2_4939
+.globl sym_2_4940
+sym_2_4940: la $2, sym_2_4940
+.globl sym_2_4941
+sym_2_4941: la $2, sym_2_4941
+.globl sym_2_4942
+sym_2_4942: la $2, sym_2_4942
+.globl sym_2_4943
+sym_2_4943: la $2, sym_2_4943
+.globl sym_2_4944
+sym_2_4944: la $2, sym_2_4944
+.globl sym_2_4945
+sym_2_4945: la $2, sym_2_4945
+.globl sym_2_4946
+sym_2_4946: la $2, sym_2_4946
+.globl sym_2_4947
+sym_2_4947: la $2, sym_2_4947
+.globl sym_2_4948
+sym_2_4948: la $2, sym_2_4948
+.globl sym_2_4949
+sym_2_4949: la $2, sym_2_4949
+.globl sym_2_4950
+sym_2_4950: la $2, sym_2_4950
+.globl sym_2_4951
+sym_2_4951: la $2, sym_2_4951
+.globl sym_2_4952
+sym_2_4952: la $2, sym_2_4952
+.globl sym_2_4953
+sym_2_4953: la $2, sym_2_4953
+.globl sym_2_4954
+sym_2_4954: la $2, sym_2_4954
+.globl sym_2_4955
+sym_2_4955: la $2, sym_2_4955
+.globl sym_2_4956
+sym_2_4956: la $2, sym_2_4956
+.globl sym_2_4957
+sym_2_4957: la $2, sym_2_4957
+.globl sym_2_4958
+sym_2_4958: la $2, sym_2_4958
+.globl sym_2_4959
+sym_2_4959: la $2, sym_2_4959
+.globl sym_2_4960
+sym_2_4960: la $2, sym_2_4960
+.globl sym_2_4961
+sym_2_4961: la $2, sym_2_4961
+.globl sym_2_4962
+sym_2_4962: la $2, sym_2_4962
+.globl sym_2_4963
+sym_2_4963: la $2, sym_2_4963
+.globl sym_2_4964
+sym_2_4964: la $2, sym_2_4964
+.globl sym_2_4965
+sym_2_4965: la $2, sym_2_4965
+.globl sym_2_4966
+sym_2_4966: la $2, sym_2_4966
+.globl sym_2_4967
+sym_2_4967: la $2, sym_2_4967
+.globl sym_2_4968
+sym_2_4968: la $2, sym_2_4968
+.globl sym_2_4969
+sym_2_4969: la $2, sym_2_4969
+.globl sym_2_4970
+sym_2_4970: la $2, sym_2_4970
+.globl sym_2_4971
+sym_2_4971: la $2, sym_2_4971
+.globl sym_2_4972
+sym_2_4972: la $2, sym_2_4972
+.globl sym_2_4973
+sym_2_4973: la $2, sym_2_4973
+.globl sym_2_4974
+sym_2_4974: la $2, sym_2_4974
+.globl sym_2_4975
+sym_2_4975: la $2, sym_2_4975
+.globl sym_2_4976
+sym_2_4976: la $2, sym_2_4976
+.globl sym_2_4977
+sym_2_4977: la $2, sym_2_4977
+.globl sym_2_4978
+sym_2_4978: la $2, sym_2_4978
+.globl sym_2_4979
+sym_2_4979: la $2, sym_2_4979
+.globl sym_2_4980
+sym_2_4980: la $2, sym_2_4980
+.globl sym_2_4981
+sym_2_4981: la $2, sym_2_4981
+.globl sym_2_4982
+sym_2_4982: la $2, sym_2_4982
+.globl sym_2_4983
+sym_2_4983: la $2, sym_2_4983
+.globl sym_2_4984
+sym_2_4984: la $2, sym_2_4984
+.globl sym_2_4985
+sym_2_4985: la $2, sym_2_4985
+.globl sym_2_4986
+sym_2_4986: la $2, sym_2_4986
+.globl sym_2_4987
+sym_2_4987: la $2, sym_2_4987
+.globl sym_2_4988
+sym_2_4988: la $2, sym_2_4988
+.globl sym_2_4989
+sym_2_4989: la $2, sym_2_4989
+.globl sym_2_4990
+sym_2_4990: la $2, sym_2_4990
+.globl sym_2_4991
+sym_2_4991: la $2, sym_2_4991
+.globl sym_2_4992
+sym_2_4992: la $2, sym_2_4992
+.globl sym_2_4993
+sym_2_4993: la $2, sym_2_4993
+.globl sym_2_4994
+sym_2_4994: la $2, sym_2_4994
+.globl sym_2_4995
+sym_2_4995: la $2, sym_2_4995
+.globl sym_2_4996
+sym_2_4996: la $2, sym_2_4996
+.globl sym_2_4997
+sym_2_4997: la $2, sym_2_4997
+.globl sym_2_4998
+sym_2_4998: la $2, sym_2_4998
+.globl sym_2_4999
+sym_2_4999: la $2, sym_2_4999
+.globl sym_2_5000
+sym_2_5000: la $2, sym_2_5000
+.globl sym_2_5001
+sym_2_5001: la $2, sym_2_5001
+.globl sym_2_5002
+sym_2_5002: la $2, sym_2_5002
+.globl sym_2_5003
+sym_2_5003: la $2, sym_2_5003
+.globl sym_2_5004
+sym_2_5004: la $2, sym_2_5004
+.globl sym_2_5005
+sym_2_5005: la $2, sym_2_5005
+.globl sym_2_5006
+sym_2_5006: la $2, sym_2_5006
+.globl sym_2_5007
+sym_2_5007: la $2, sym_2_5007
+.globl sym_2_5008
+sym_2_5008: la $2, sym_2_5008
+.globl sym_2_5009
+sym_2_5009: la $2, sym_2_5009
+.globl sym_2_5010
+sym_2_5010: la $2, sym_2_5010
+.globl sym_2_5011
+sym_2_5011: la $2, sym_2_5011
+.globl sym_2_5012
+sym_2_5012: la $2, sym_2_5012
+.globl sym_2_5013
+sym_2_5013: la $2, sym_2_5013
+.globl sym_2_5014
+sym_2_5014: la $2, sym_2_5014
+.globl sym_2_5015
+sym_2_5015: la $2, sym_2_5015
+.globl sym_2_5016
+sym_2_5016: la $2, sym_2_5016
+.globl sym_2_5017
+sym_2_5017: la $2, sym_2_5017
+.globl sym_2_5018
+sym_2_5018: la $2, sym_2_5018
+.globl sym_2_5019
+sym_2_5019: la $2, sym_2_5019
+.globl sym_2_5020
+sym_2_5020: la $2, sym_2_5020
+.globl sym_2_5021
+sym_2_5021: la $2, sym_2_5021
+.globl sym_2_5022
+sym_2_5022: la $2, sym_2_5022
+.globl sym_2_5023
+sym_2_5023: la $2, sym_2_5023
+.globl sym_2_5024
+sym_2_5024: la $2, sym_2_5024
+.globl sym_2_5025
+sym_2_5025: la $2, sym_2_5025
+.globl sym_2_5026
+sym_2_5026: la $2, sym_2_5026
+.globl sym_2_5027
+sym_2_5027: la $2, sym_2_5027
+.globl sym_2_5028
+sym_2_5028: la $2, sym_2_5028
+.globl sym_2_5029
+sym_2_5029: la $2, sym_2_5029
+.globl sym_2_5030
+sym_2_5030: la $2, sym_2_5030
+.globl sym_2_5031
+sym_2_5031: la $2, sym_2_5031
+.globl sym_2_5032
+sym_2_5032: la $2, sym_2_5032
+.globl sym_2_5033
+sym_2_5033: la $2, sym_2_5033
+.globl sym_2_5034
+sym_2_5034: la $2, sym_2_5034
+.globl sym_2_5035
+sym_2_5035: la $2, sym_2_5035
+.globl sym_2_5036
+sym_2_5036: la $2, sym_2_5036
+.globl sym_2_5037
+sym_2_5037: la $2, sym_2_5037
+.globl sym_2_5038
+sym_2_5038: la $2, sym_2_5038
+.globl sym_2_5039
+sym_2_5039: la $2, sym_2_5039
+.globl sym_2_5040
+sym_2_5040: la $2, sym_2_5040
+.globl sym_2_5041
+sym_2_5041: la $2, sym_2_5041
+.globl sym_2_5042
+sym_2_5042: la $2, sym_2_5042
+.globl sym_2_5043
+sym_2_5043: la $2, sym_2_5043
+.globl sym_2_5044
+sym_2_5044: la $2, sym_2_5044
+.globl sym_2_5045
+sym_2_5045: la $2, sym_2_5045
+.globl sym_2_5046
+sym_2_5046: la $2, sym_2_5046
+.globl sym_2_5047
+sym_2_5047: la $2, sym_2_5047
+.globl sym_2_5048
+sym_2_5048: la $2, sym_2_5048
+.globl sym_2_5049
+sym_2_5049: la $2, sym_2_5049
+.globl sym_2_5050
+sym_2_5050: la $2, sym_2_5050
+.globl sym_2_5051
+sym_2_5051: la $2, sym_2_5051
+.globl sym_2_5052
+sym_2_5052: la $2, sym_2_5052
+.globl sym_2_5053
+sym_2_5053: la $2, sym_2_5053
+.globl sym_2_5054
+sym_2_5054: la $2, sym_2_5054
+.globl sym_2_5055
+sym_2_5055: la $2, sym_2_5055
+.globl sym_2_5056
+sym_2_5056: la $2, sym_2_5056
+.globl sym_2_5057
+sym_2_5057: la $2, sym_2_5057
+.globl sym_2_5058
+sym_2_5058: la $2, sym_2_5058
+.globl sym_2_5059
+sym_2_5059: la $2, sym_2_5059
+.globl sym_2_5060
+sym_2_5060: la $2, sym_2_5060
+.globl sym_2_5061
+sym_2_5061: la $2, sym_2_5061
+.globl sym_2_5062
+sym_2_5062: la $2, sym_2_5062
+.globl sym_2_5063
+sym_2_5063: la $2, sym_2_5063
+.globl sym_2_5064
+sym_2_5064: la $2, sym_2_5064
+.globl sym_2_5065
+sym_2_5065: la $2, sym_2_5065
+.globl sym_2_5066
+sym_2_5066: la $2, sym_2_5066
+.globl sym_2_5067
+sym_2_5067: la $2, sym_2_5067
+.globl sym_2_5068
+sym_2_5068: la $2, sym_2_5068
+.globl sym_2_5069
+sym_2_5069: la $2, sym_2_5069
+.globl sym_2_5070
+sym_2_5070: la $2, sym_2_5070
+.globl sym_2_5071
+sym_2_5071: la $2, sym_2_5071
+.globl sym_2_5072
+sym_2_5072: la $2, sym_2_5072
+.globl sym_2_5073
+sym_2_5073: la $2, sym_2_5073
+.globl sym_2_5074
+sym_2_5074: la $2, sym_2_5074
+.globl sym_2_5075
+sym_2_5075: la $2, sym_2_5075
+.globl sym_2_5076
+sym_2_5076: la $2, sym_2_5076
+.globl sym_2_5077
+sym_2_5077: la $2, sym_2_5077
+.globl sym_2_5078
+sym_2_5078: la $2, sym_2_5078
+.globl sym_2_5079
+sym_2_5079: la $2, sym_2_5079
+.globl sym_2_5080
+sym_2_5080: la $2, sym_2_5080
+.globl sym_2_5081
+sym_2_5081: la $2, sym_2_5081
+.globl sym_2_5082
+sym_2_5082: la $2, sym_2_5082
+.globl sym_2_5083
+sym_2_5083: la $2, sym_2_5083
+.globl sym_2_5084
+sym_2_5084: la $2, sym_2_5084
+.globl sym_2_5085
+sym_2_5085: la $2, sym_2_5085
+.globl sym_2_5086
+sym_2_5086: la $2, sym_2_5086
+.globl sym_2_5087
+sym_2_5087: la $2, sym_2_5087
+.globl sym_2_5088
+sym_2_5088: la $2, sym_2_5088
+.globl sym_2_5089
+sym_2_5089: la $2, sym_2_5089
+.globl sym_2_5090
+sym_2_5090: la $2, sym_2_5090
+.globl sym_2_5091
+sym_2_5091: la $2, sym_2_5091
+.globl sym_2_5092
+sym_2_5092: la $2, sym_2_5092
+.globl sym_2_5093
+sym_2_5093: la $2, sym_2_5093
+.globl sym_2_5094
+sym_2_5094: la $2, sym_2_5094
+.globl sym_2_5095
+sym_2_5095: la $2, sym_2_5095
+.globl sym_2_5096
+sym_2_5096: la $2, sym_2_5096
+.globl sym_2_5097
+sym_2_5097: la $2, sym_2_5097
+.globl sym_2_5098
+sym_2_5098: la $2, sym_2_5098
+.globl sym_2_5099
+sym_2_5099: la $2, sym_2_5099
+.globl sym_2_5100
+sym_2_5100: la $2, sym_2_5100
+.globl sym_2_5101
+sym_2_5101: la $2, sym_2_5101
+.globl sym_2_5102
+sym_2_5102: la $2, sym_2_5102
+.globl sym_2_5103
+sym_2_5103: la $2, sym_2_5103
+.globl sym_2_5104
+sym_2_5104: la $2, sym_2_5104
+.globl sym_2_5105
+sym_2_5105: la $2, sym_2_5105
+.globl sym_2_5106
+sym_2_5106: la $2, sym_2_5106
+.globl sym_2_5107
+sym_2_5107: la $2, sym_2_5107
+.globl sym_2_5108
+sym_2_5108: la $2, sym_2_5108
+.globl sym_2_5109
+sym_2_5109: la $2, sym_2_5109
+.globl sym_2_5110
+sym_2_5110: la $2, sym_2_5110
+.globl sym_2_5111
+sym_2_5111: la $2, sym_2_5111
+.globl sym_2_5112
+sym_2_5112: la $2, sym_2_5112
+.globl sym_2_5113
+sym_2_5113: la $2, sym_2_5113
+.globl sym_2_5114
+sym_2_5114: la $2, sym_2_5114
+.globl sym_2_5115
+sym_2_5115: la $2, sym_2_5115
+.globl sym_2_5116
+sym_2_5116: la $2, sym_2_5116
+.globl sym_2_5117
+sym_2_5117: la $2, sym_2_5117
+.globl sym_2_5118
+sym_2_5118: la $2, sym_2_5118
+.globl sym_2_5119
+sym_2_5119: la $2, sym_2_5119
+.globl sym_2_5120
+sym_2_5120: la $2, sym_2_5120
+.globl sym_2_5121
+sym_2_5121: la $2, sym_2_5121
+.globl sym_2_5122
+sym_2_5122: la $2, sym_2_5122
+.globl sym_2_5123
+sym_2_5123: la $2, sym_2_5123
+.globl sym_2_5124
+sym_2_5124: la $2, sym_2_5124
+.globl sym_2_5125
+sym_2_5125: la $2, sym_2_5125
+.globl sym_2_5126
+sym_2_5126: la $2, sym_2_5126
+.globl sym_2_5127
+sym_2_5127: la $2, sym_2_5127
+.globl sym_2_5128
+sym_2_5128: la $2, sym_2_5128
+.globl sym_2_5129
+sym_2_5129: la $2, sym_2_5129
+.globl sym_2_5130
+sym_2_5130: la $2, sym_2_5130
+.globl sym_2_5131
+sym_2_5131: la $2, sym_2_5131
+.globl sym_2_5132
+sym_2_5132: la $2, sym_2_5132
+.globl sym_2_5133
+sym_2_5133: la $2, sym_2_5133
+.globl sym_2_5134
+sym_2_5134: la $2, sym_2_5134
+.globl sym_2_5135
+sym_2_5135: la $2, sym_2_5135
+.globl sym_2_5136
+sym_2_5136: la $2, sym_2_5136
+.globl sym_2_5137
+sym_2_5137: la $2, sym_2_5137
+.globl sym_2_5138
+sym_2_5138: la $2, sym_2_5138
+.globl sym_2_5139
+sym_2_5139: la $2, sym_2_5139
+.globl sym_2_5140
+sym_2_5140: la $2, sym_2_5140
+.globl sym_2_5141
+sym_2_5141: la $2, sym_2_5141
+.globl sym_2_5142
+sym_2_5142: la $2, sym_2_5142
+.globl sym_2_5143
+sym_2_5143: la $2, sym_2_5143
+.globl sym_2_5144
+sym_2_5144: la $2, sym_2_5144
+.globl sym_2_5145
+sym_2_5145: la $2, sym_2_5145
+.globl sym_2_5146
+sym_2_5146: la $2, sym_2_5146
+.globl sym_2_5147
+sym_2_5147: la $2, sym_2_5147
+.globl sym_2_5148
+sym_2_5148: la $2, sym_2_5148
+.globl sym_2_5149
+sym_2_5149: la $2, sym_2_5149
+.globl sym_2_5150
+sym_2_5150: la $2, sym_2_5150
+.globl sym_2_5151
+sym_2_5151: la $2, sym_2_5151
+.globl sym_2_5152
+sym_2_5152: la $2, sym_2_5152
+.globl sym_2_5153
+sym_2_5153: la $2, sym_2_5153
+.globl sym_2_5154
+sym_2_5154: la $2, sym_2_5154
+.globl sym_2_5155
+sym_2_5155: la $2, sym_2_5155
+.globl sym_2_5156
+sym_2_5156: la $2, sym_2_5156
+.globl sym_2_5157
+sym_2_5157: la $2, sym_2_5157
+.globl sym_2_5158
+sym_2_5158: la $2, sym_2_5158
+.globl sym_2_5159
+sym_2_5159: la $2, sym_2_5159
+.globl sym_2_5160
+sym_2_5160: la $2, sym_2_5160
+.globl sym_2_5161
+sym_2_5161: la $2, sym_2_5161
+.globl sym_2_5162
+sym_2_5162: la $2, sym_2_5162
+.globl sym_2_5163
+sym_2_5163: la $2, sym_2_5163
+.globl sym_2_5164
+sym_2_5164: la $2, sym_2_5164
+.globl sym_2_5165
+sym_2_5165: la $2, sym_2_5165
+.globl sym_2_5166
+sym_2_5166: la $2, sym_2_5166
+.globl sym_2_5167
+sym_2_5167: la $2, sym_2_5167
+.globl sym_2_5168
+sym_2_5168: la $2, sym_2_5168
+.globl sym_2_5169
+sym_2_5169: la $2, sym_2_5169
+.globl sym_2_5170
+sym_2_5170: la $2, sym_2_5170
+.globl sym_2_5171
+sym_2_5171: la $2, sym_2_5171
+.globl sym_2_5172
+sym_2_5172: la $2, sym_2_5172
+.globl sym_2_5173
+sym_2_5173: la $2, sym_2_5173
+.globl sym_2_5174
+sym_2_5174: la $2, sym_2_5174
+.globl sym_2_5175
+sym_2_5175: la $2, sym_2_5175
+.globl sym_2_5176
+sym_2_5176: la $2, sym_2_5176
+.globl sym_2_5177
+sym_2_5177: la $2, sym_2_5177
+.globl sym_2_5178
+sym_2_5178: la $2, sym_2_5178
+.globl sym_2_5179
+sym_2_5179: la $2, sym_2_5179
+.globl sym_2_5180
+sym_2_5180: la $2, sym_2_5180
+.globl sym_2_5181
+sym_2_5181: la $2, sym_2_5181
+.globl sym_2_5182
+sym_2_5182: la $2, sym_2_5182
+.globl sym_2_5183
+sym_2_5183: la $2, sym_2_5183
+.globl sym_2_5184
+sym_2_5184: la $2, sym_2_5184
+.globl sym_2_5185
+sym_2_5185: la $2, sym_2_5185
+.globl sym_2_5186
+sym_2_5186: la $2, sym_2_5186
+.globl sym_2_5187
+sym_2_5187: la $2, sym_2_5187
+.globl sym_2_5188
+sym_2_5188: la $2, sym_2_5188
+.globl sym_2_5189
+sym_2_5189: la $2, sym_2_5189
+.globl sym_2_5190
+sym_2_5190: la $2, sym_2_5190
+.globl sym_2_5191
+sym_2_5191: la $2, sym_2_5191
+.globl sym_2_5192
+sym_2_5192: la $2, sym_2_5192
+.globl sym_2_5193
+sym_2_5193: la $2, sym_2_5193
+.globl sym_2_5194
+sym_2_5194: la $2, sym_2_5194
+.globl sym_2_5195
+sym_2_5195: la $2, sym_2_5195
+.globl sym_2_5196
+sym_2_5196: la $2, sym_2_5196
+.globl sym_2_5197
+sym_2_5197: la $2, sym_2_5197
+.globl sym_2_5198
+sym_2_5198: la $2, sym_2_5198
+.globl sym_2_5199
+sym_2_5199: la $2, sym_2_5199
+.globl sym_2_5200
+sym_2_5200: la $2, sym_2_5200
+.globl sym_2_5201
+sym_2_5201: la $2, sym_2_5201
+.globl sym_2_5202
+sym_2_5202: la $2, sym_2_5202
+.globl sym_2_5203
+sym_2_5203: la $2, sym_2_5203
+.globl sym_2_5204
+sym_2_5204: la $2, sym_2_5204
+.globl sym_2_5205
+sym_2_5205: la $2, sym_2_5205
+.globl sym_2_5206
+sym_2_5206: la $2, sym_2_5206
+.globl sym_2_5207
+sym_2_5207: la $2, sym_2_5207
+.globl sym_2_5208
+sym_2_5208: la $2, sym_2_5208
+.globl sym_2_5209
+sym_2_5209: la $2, sym_2_5209
+.globl sym_2_5210
+sym_2_5210: la $2, sym_2_5210
+.globl sym_2_5211
+sym_2_5211: la $2, sym_2_5211
+.globl sym_2_5212
+sym_2_5212: la $2, sym_2_5212
+.globl sym_2_5213
+sym_2_5213: la $2, sym_2_5213
+.globl sym_2_5214
+sym_2_5214: la $2, sym_2_5214
+.globl sym_2_5215
+sym_2_5215: la $2, sym_2_5215
+.globl sym_2_5216
+sym_2_5216: la $2, sym_2_5216
+.globl sym_2_5217
+sym_2_5217: la $2, sym_2_5217
+.globl sym_2_5218
+sym_2_5218: la $2, sym_2_5218
+.globl sym_2_5219
+sym_2_5219: la $2, sym_2_5219
+.globl sym_2_5220
+sym_2_5220: la $2, sym_2_5220
+.globl sym_2_5221
+sym_2_5221: la $2, sym_2_5221
+.globl sym_2_5222
+sym_2_5222: la $2, sym_2_5222
+.globl sym_2_5223
+sym_2_5223: la $2, sym_2_5223
+.globl sym_2_5224
+sym_2_5224: la $2, sym_2_5224
+.globl sym_2_5225
+sym_2_5225: la $2, sym_2_5225
+.globl sym_2_5226
+sym_2_5226: la $2, sym_2_5226
+.globl sym_2_5227
+sym_2_5227: la $2, sym_2_5227
+.globl sym_2_5228
+sym_2_5228: la $2, sym_2_5228
+.globl sym_2_5229
+sym_2_5229: la $2, sym_2_5229
+.globl sym_2_5230
+sym_2_5230: la $2, sym_2_5230
+.globl sym_2_5231
+sym_2_5231: la $2, sym_2_5231
+.globl sym_2_5232
+sym_2_5232: la $2, sym_2_5232
+.globl sym_2_5233
+sym_2_5233: la $2, sym_2_5233
+.globl sym_2_5234
+sym_2_5234: la $2, sym_2_5234
+.globl sym_2_5235
+sym_2_5235: la $2, sym_2_5235
+.globl sym_2_5236
+sym_2_5236: la $2, sym_2_5236
+.globl sym_2_5237
+sym_2_5237: la $2, sym_2_5237
+.globl sym_2_5238
+sym_2_5238: la $2, sym_2_5238
+.globl sym_2_5239
+sym_2_5239: la $2, sym_2_5239
+.globl sym_2_5240
+sym_2_5240: la $2, sym_2_5240
+.globl sym_2_5241
+sym_2_5241: la $2, sym_2_5241
+.globl sym_2_5242
+sym_2_5242: la $2, sym_2_5242
+.globl sym_2_5243
+sym_2_5243: la $2, sym_2_5243
+.globl sym_2_5244
+sym_2_5244: la $2, sym_2_5244
+.globl sym_2_5245
+sym_2_5245: la $2, sym_2_5245
+.globl sym_2_5246
+sym_2_5246: la $2, sym_2_5246
+.globl sym_2_5247
+sym_2_5247: la $2, sym_2_5247
+.globl sym_2_5248
+sym_2_5248: la $2, sym_2_5248
+.globl sym_2_5249
+sym_2_5249: la $2, sym_2_5249
+.globl sym_2_5250
+sym_2_5250: la $2, sym_2_5250
+.globl sym_2_5251
+sym_2_5251: la $2, sym_2_5251
+.globl sym_2_5252
+sym_2_5252: la $2, sym_2_5252
+.globl sym_2_5253
+sym_2_5253: la $2, sym_2_5253
+.globl sym_2_5254
+sym_2_5254: la $2, sym_2_5254
+.globl sym_2_5255
+sym_2_5255: la $2, sym_2_5255
+.globl sym_2_5256
+sym_2_5256: la $2, sym_2_5256
+.globl sym_2_5257
+sym_2_5257: la $2, sym_2_5257
+.globl sym_2_5258
+sym_2_5258: la $2, sym_2_5258
+.globl sym_2_5259
+sym_2_5259: la $2, sym_2_5259
+.globl sym_2_5260
+sym_2_5260: la $2, sym_2_5260
+.globl sym_2_5261
+sym_2_5261: la $2, sym_2_5261
+.globl sym_2_5262
+sym_2_5262: la $2, sym_2_5262
+.globl sym_2_5263
+sym_2_5263: la $2, sym_2_5263
+.globl sym_2_5264
+sym_2_5264: la $2, sym_2_5264
+.globl sym_2_5265
+sym_2_5265: la $2, sym_2_5265
+.globl sym_2_5266
+sym_2_5266: la $2, sym_2_5266
+.globl sym_2_5267
+sym_2_5267: la $2, sym_2_5267
+.globl sym_2_5268
+sym_2_5268: la $2, sym_2_5268
+.globl sym_2_5269
+sym_2_5269: la $2, sym_2_5269
+.globl sym_2_5270
+sym_2_5270: la $2, sym_2_5270
+.globl sym_2_5271
+sym_2_5271: la $2, sym_2_5271
+.globl sym_2_5272
+sym_2_5272: la $2, sym_2_5272
+.globl sym_2_5273
+sym_2_5273: la $2, sym_2_5273
+.globl sym_2_5274
+sym_2_5274: la $2, sym_2_5274
+.globl sym_2_5275
+sym_2_5275: la $2, sym_2_5275
+.globl sym_2_5276
+sym_2_5276: la $2, sym_2_5276
+.globl sym_2_5277
+sym_2_5277: la $2, sym_2_5277
+.globl sym_2_5278
+sym_2_5278: la $2, sym_2_5278
+.globl sym_2_5279
+sym_2_5279: la $2, sym_2_5279
+.globl sym_2_5280
+sym_2_5280: la $2, sym_2_5280
+.globl sym_2_5281
+sym_2_5281: la $2, sym_2_5281
+.globl sym_2_5282
+sym_2_5282: la $2, sym_2_5282
+.globl sym_2_5283
+sym_2_5283: la $2, sym_2_5283
+.globl sym_2_5284
+sym_2_5284: la $2, sym_2_5284
+.globl sym_2_5285
+sym_2_5285: la $2, sym_2_5285
+.globl sym_2_5286
+sym_2_5286: la $2, sym_2_5286
+.globl sym_2_5287
+sym_2_5287: la $2, sym_2_5287
+.globl sym_2_5288
+sym_2_5288: la $2, sym_2_5288
+.globl sym_2_5289
+sym_2_5289: la $2, sym_2_5289
+.globl sym_2_5290
+sym_2_5290: la $2, sym_2_5290
+.globl sym_2_5291
+sym_2_5291: la $2, sym_2_5291
+.globl sym_2_5292
+sym_2_5292: la $2, sym_2_5292
+.globl sym_2_5293
+sym_2_5293: la $2, sym_2_5293
+.globl sym_2_5294
+sym_2_5294: la $2, sym_2_5294
+.globl sym_2_5295
+sym_2_5295: la $2, sym_2_5295
+.globl sym_2_5296
+sym_2_5296: la $2, sym_2_5296
+.globl sym_2_5297
+sym_2_5297: la $2, sym_2_5297
+.globl sym_2_5298
+sym_2_5298: la $2, sym_2_5298
+.globl sym_2_5299
+sym_2_5299: la $2, sym_2_5299
+.globl sym_2_5300
+sym_2_5300: la $2, sym_2_5300
+.globl sym_2_5301
+sym_2_5301: la $2, sym_2_5301
+.globl sym_2_5302
+sym_2_5302: la $2, sym_2_5302
+.globl sym_2_5303
+sym_2_5303: la $2, sym_2_5303
+.globl sym_2_5304
+sym_2_5304: la $2, sym_2_5304
+.globl sym_2_5305
+sym_2_5305: la $2, sym_2_5305
+.globl sym_2_5306
+sym_2_5306: la $2, sym_2_5306
+.globl sym_2_5307
+sym_2_5307: la $2, sym_2_5307
+.globl sym_2_5308
+sym_2_5308: la $2, sym_2_5308
+.globl sym_2_5309
+sym_2_5309: la $2, sym_2_5309
+.globl sym_2_5310
+sym_2_5310: la $2, sym_2_5310
+.globl sym_2_5311
+sym_2_5311: la $2, sym_2_5311
+.globl sym_2_5312
+sym_2_5312: la $2, sym_2_5312
+.globl sym_2_5313
+sym_2_5313: la $2, sym_2_5313
+.globl sym_2_5314
+sym_2_5314: la $2, sym_2_5314
+.globl sym_2_5315
+sym_2_5315: la $2, sym_2_5315
+.globl sym_2_5316
+sym_2_5316: la $2, sym_2_5316
+.globl sym_2_5317
+sym_2_5317: la $2, sym_2_5317
+.globl sym_2_5318
+sym_2_5318: la $2, sym_2_5318
+.globl sym_2_5319
+sym_2_5319: la $2, sym_2_5319
+.globl sym_2_5320
+sym_2_5320: la $2, sym_2_5320
+.globl sym_2_5321
+sym_2_5321: la $2, sym_2_5321
+.globl sym_2_5322
+sym_2_5322: la $2, sym_2_5322
+.globl sym_2_5323
+sym_2_5323: la $2, sym_2_5323
+.globl sym_2_5324
+sym_2_5324: la $2, sym_2_5324
+.globl sym_2_5325
+sym_2_5325: la $2, sym_2_5325
+.globl sym_2_5326
+sym_2_5326: la $2, sym_2_5326
+.globl sym_2_5327
+sym_2_5327: la $2, sym_2_5327
+.globl sym_2_5328
+sym_2_5328: la $2, sym_2_5328
+.globl sym_2_5329
+sym_2_5329: la $2, sym_2_5329
+.globl sym_2_5330
+sym_2_5330: la $2, sym_2_5330
+.globl sym_2_5331
+sym_2_5331: la $2, sym_2_5331
+.globl sym_2_5332
+sym_2_5332: la $2, sym_2_5332
+.globl sym_2_5333
+sym_2_5333: la $2, sym_2_5333
+.globl sym_2_5334
+sym_2_5334: la $2, sym_2_5334
+.globl sym_2_5335
+sym_2_5335: la $2, sym_2_5335
+.globl sym_2_5336
+sym_2_5336: la $2, sym_2_5336
+.globl sym_2_5337
+sym_2_5337: la $2, sym_2_5337
+.globl sym_2_5338
+sym_2_5338: la $2, sym_2_5338
+.globl sym_2_5339
+sym_2_5339: la $2, sym_2_5339
+.globl sym_2_5340
+sym_2_5340: la $2, sym_2_5340
+.globl sym_2_5341
+sym_2_5341: la $2, sym_2_5341
+.globl sym_2_5342
+sym_2_5342: la $2, sym_2_5342
+.globl sym_2_5343
+sym_2_5343: la $2, sym_2_5343
+.globl sym_2_5344
+sym_2_5344: la $2, sym_2_5344
+.globl sym_2_5345
+sym_2_5345: la $2, sym_2_5345
+.globl sym_2_5346
+sym_2_5346: la $2, sym_2_5346
+.globl sym_2_5347
+sym_2_5347: la $2, sym_2_5347
+.globl sym_2_5348
+sym_2_5348: la $2, sym_2_5348
+.globl sym_2_5349
+sym_2_5349: la $2, sym_2_5349
+.globl sym_2_5350
+sym_2_5350: la $2, sym_2_5350
+.globl sym_2_5351
+sym_2_5351: la $2, sym_2_5351
+.globl sym_2_5352
+sym_2_5352: la $2, sym_2_5352
+.globl sym_2_5353
+sym_2_5353: la $2, sym_2_5353
+.globl sym_2_5354
+sym_2_5354: la $2, sym_2_5354
+.globl sym_2_5355
+sym_2_5355: la $2, sym_2_5355
+.globl sym_2_5356
+sym_2_5356: la $2, sym_2_5356
+.globl sym_2_5357
+sym_2_5357: la $2, sym_2_5357
+.globl sym_2_5358
+sym_2_5358: la $2, sym_2_5358
+.globl sym_2_5359
+sym_2_5359: la $2, sym_2_5359
+.globl sym_2_5360
+sym_2_5360: la $2, sym_2_5360
+.globl sym_2_5361
+sym_2_5361: la $2, sym_2_5361
+.globl sym_2_5362
+sym_2_5362: la $2, sym_2_5362
+.globl sym_2_5363
+sym_2_5363: la $2, sym_2_5363
+.globl sym_2_5364
+sym_2_5364: la $2, sym_2_5364
+.globl sym_2_5365
+sym_2_5365: la $2, sym_2_5365
+.globl sym_2_5366
+sym_2_5366: la $2, sym_2_5366
+.globl sym_2_5367
+sym_2_5367: la $2, sym_2_5367
+.globl sym_2_5368
+sym_2_5368: la $2, sym_2_5368
+.globl sym_2_5369
+sym_2_5369: la $2, sym_2_5369
+.globl sym_2_5370
+sym_2_5370: la $2, sym_2_5370
+.globl sym_2_5371
+sym_2_5371: la $2, sym_2_5371
+.globl sym_2_5372
+sym_2_5372: la $2, sym_2_5372
+.globl sym_2_5373
+sym_2_5373: la $2, sym_2_5373
+.globl sym_2_5374
+sym_2_5374: la $2, sym_2_5374
+.globl sym_2_5375
+sym_2_5375: la $2, sym_2_5375
+.globl sym_2_5376
+sym_2_5376: la $2, sym_2_5376
+.globl sym_2_5377
+sym_2_5377: la $2, sym_2_5377
+.globl sym_2_5378
+sym_2_5378: la $2, sym_2_5378
+.globl sym_2_5379
+sym_2_5379: la $2, sym_2_5379
+.globl sym_2_5380
+sym_2_5380: la $2, sym_2_5380
+.globl sym_2_5381
+sym_2_5381: la $2, sym_2_5381
+.globl sym_2_5382
+sym_2_5382: la $2, sym_2_5382
+.globl sym_2_5383
+sym_2_5383: la $2, sym_2_5383
+.globl sym_2_5384
+sym_2_5384: la $2, sym_2_5384
+.globl sym_2_5385
+sym_2_5385: la $2, sym_2_5385
+.globl sym_2_5386
+sym_2_5386: la $2, sym_2_5386
+.globl sym_2_5387
+sym_2_5387: la $2, sym_2_5387
+.globl sym_2_5388
+sym_2_5388: la $2, sym_2_5388
+.globl sym_2_5389
+sym_2_5389: la $2, sym_2_5389
+.globl sym_2_5390
+sym_2_5390: la $2, sym_2_5390
+.globl sym_2_5391
+sym_2_5391: la $2, sym_2_5391
+.globl sym_2_5392
+sym_2_5392: la $2, sym_2_5392
+.globl sym_2_5393
+sym_2_5393: la $2, sym_2_5393
+.globl sym_2_5394
+sym_2_5394: la $2, sym_2_5394
+.globl sym_2_5395
+sym_2_5395: la $2, sym_2_5395
+.globl sym_2_5396
+sym_2_5396: la $2, sym_2_5396
+.globl sym_2_5397
+sym_2_5397: la $2, sym_2_5397
+.globl sym_2_5398
+sym_2_5398: la $2, sym_2_5398
+.globl sym_2_5399
+sym_2_5399: la $2, sym_2_5399
+.globl sym_2_5400
+sym_2_5400: la $2, sym_2_5400
+.globl sym_2_5401
+sym_2_5401: la $2, sym_2_5401
+.globl sym_2_5402
+sym_2_5402: la $2, sym_2_5402
+.globl sym_2_5403
+sym_2_5403: la $2, sym_2_5403
+.globl sym_2_5404
+sym_2_5404: la $2, sym_2_5404
+.globl sym_2_5405
+sym_2_5405: la $2, sym_2_5405
+.globl sym_2_5406
+sym_2_5406: la $2, sym_2_5406
+.globl sym_2_5407
+sym_2_5407: la $2, sym_2_5407
+.globl sym_2_5408
+sym_2_5408: la $2, sym_2_5408
+.globl sym_2_5409
+sym_2_5409: la $2, sym_2_5409
+.globl sym_2_5410
+sym_2_5410: la $2, sym_2_5410
+.globl sym_2_5411
+sym_2_5411: la $2, sym_2_5411
+.globl sym_2_5412
+sym_2_5412: la $2, sym_2_5412
+.globl sym_2_5413
+sym_2_5413: la $2, sym_2_5413
+.globl sym_2_5414
+sym_2_5414: la $2, sym_2_5414
+.globl sym_2_5415
+sym_2_5415: la $2, sym_2_5415
+.globl sym_2_5416
+sym_2_5416: la $2, sym_2_5416
+.globl sym_2_5417
+sym_2_5417: la $2, sym_2_5417
+.globl sym_2_5418
+sym_2_5418: la $2, sym_2_5418
+.globl sym_2_5419
+sym_2_5419: la $2, sym_2_5419
+.globl sym_2_5420
+sym_2_5420: la $2, sym_2_5420
+.globl sym_2_5421
+sym_2_5421: la $2, sym_2_5421
+.globl sym_2_5422
+sym_2_5422: la $2, sym_2_5422
+.globl sym_2_5423
+sym_2_5423: la $2, sym_2_5423
+.globl sym_2_5424
+sym_2_5424: la $2, sym_2_5424
+.globl sym_2_5425
+sym_2_5425: la $2, sym_2_5425
+.globl sym_2_5426
+sym_2_5426: la $2, sym_2_5426
+.globl sym_2_5427
+sym_2_5427: la $2, sym_2_5427
+.globl sym_2_5428
+sym_2_5428: la $2, sym_2_5428
+.globl sym_2_5429
+sym_2_5429: la $2, sym_2_5429
+.globl sym_2_5430
+sym_2_5430: la $2, sym_2_5430
+.globl sym_2_5431
+sym_2_5431: la $2, sym_2_5431
+.globl sym_2_5432
+sym_2_5432: la $2, sym_2_5432
+.globl sym_2_5433
+sym_2_5433: la $2, sym_2_5433
+.globl sym_2_5434
+sym_2_5434: la $2, sym_2_5434
+.globl sym_2_5435
+sym_2_5435: la $2, sym_2_5435
+.globl sym_2_5436
+sym_2_5436: la $2, sym_2_5436
+.globl sym_2_5437
+sym_2_5437: la $2, sym_2_5437
+.globl sym_2_5438
+sym_2_5438: la $2, sym_2_5438
+.globl sym_2_5439
+sym_2_5439: la $2, sym_2_5439
+.globl sym_2_5440
+sym_2_5440: la $2, sym_2_5440
+.globl sym_2_5441
+sym_2_5441: la $2, sym_2_5441
+.globl sym_2_5442
+sym_2_5442: la $2, sym_2_5442
+.globl sym_2_5443
+sym_2_5443: la $2, sym_2_5443
+.globl sym_2_5444
+sym_2_5444: la $2, sym_2_5444
+.globl sym_2_5445
+sym_2_5445: la $2, sym_2_5445
+.globl sym_2_5446
+sym_2_5446: la $2, sym_2_5446
+.globl sym_2_5447
+sym_2_5447: la $2, sym_2_5447
+.globl sym_2_5448
+sym_2_5448: la $2, sym_2_5448
+.globl sym_2_5449
+sym_2_5449: la $2, sym_2_5449
+.globl sym_2_5450
+sym_2_5450: la $2, sym_2_5450
+.globl sym_2_5451
+sym_2_5451: la $2, sym_2_5451
+.globl sym_2_5452
+sym_2_5452: la $2, sym_2_5452
+.globl sym_2_5453
+sym_2_5453: la $2, sym_2_5453
+.globl sym_2_5454
+sym_2_5454: la $2, sym_2_5454
+.globl sym_2_5455
+sym_2_5455: la $2, sym_2_5455
+.globl sym_2_5456
+sym_2_5456: la $2, sym_2_5456
+.globl sym_2_5457
+sym_2_5457: la $2, sym_2_5457
+.globl sym_2_5458
+sym_2_5458: la $2, sym_2_5458
+.globl sym_2_5459
+sym_2_5459: la $2, sym_2_5459
+.globl sym_2_5460
+sym_2_5460: la $2, sym_2_5460
+.globl sym_2_5461
+sym_2_5461: la $2, sym_2_5461
+.globl sym_2_5462
+sym_2_5462: la $2, sym_2_5462
+.globl sym_2_5463
+sym_2_5463: la $2, sym_2_5463
+.globl sym_2_5464
+sym_2_5464: la $2, sym_2_5464
+.globl sym_2_5465
+sym_2_5465: la $2, sym_2_5465
+.globl sym_2_5466
+sym_2_5466: la $2, sym_2_5466
+.globl sym_2_5467
+sym_2_5467: la $2, sym_2_5467
+.globl sym_2_5468
+sym_2_5468: la $2, sym_2_5468
+.globl sym_2_5469
+sym_2_5469: la $2, sym_2_5469
+.globl sym_2_5470
+sym_2_5470: la $2, sym_2_5470
+.globl sym_2_5471
+sym_2_5471: la $2, sym_2_5471
+.globl sym_2_5472
+sym_2_5472: la $2, sym_2_5472
+.globl sym_2_5473
+sym_2_5473: la $2, sym_2_5473
+.globl sym_2_5474
+sym_2_5474: la $2, sym_2_5474
+.globl sym_2_5475
+sym_2_5475: la $2, sym_2_5475
+.globl sym_2_5476
+sym_2_5476: la $2, sym_2_5476
+.globl sym_2_5477
+sym_2_5477: la $2, sym_2_5477
+.globl sym_2_5478
+sym_2_5478: la $2, sym_2_5478
+.globl sym_2_5479
+sym_2_5479: la $2, sym_2_5479
+.globl sym_2_5480
+sym_2_5480: la $2, sym_2_5480
+.globl sym_2_5481
+sym_2_5481: la $2, sym_2_5481
+.globl sym_2_5482
+sym_2_5482: la $2, sym_2_5482
+.globl sym_2_5483
+sym_2_5483: la $2, sym_2_5483
+.globl sym_2_5484
+sym_2_5484: la $2, sym_2_5484
+.globl sym_2_5485
+sym_2_5485: la $2, sym_2_5485
+.globl sym_2_5486
+sym_2_5486: la $2, sym_2_5486
+.globl sym_2_5487
+sym_2_5487: la $2, sym_2_5487
+.globl sym_2_5488
+sym_2_5488: la $2, sym_2_5488
+.globl sym_2_5489
+sym_2_5489: la $2, sym_2_5489
+.globl sym_2_5490
+sym_2_5490: la $2, sym_2_5490
+.globl sym_2_5491
+sym_2_5491: la $2, sym_2_5491
+.globl sym_2_5492
+sym_2_5492: la $2, sym_2_5492
+.globl sym_2_5493
+sym_2_5493: la $2, sym_2_5493
+.globl sym_2_5494
+sym_2_5494: la $2, sym_2_5494
+.globl sym_2_5495
+sym_2_5495: la $2, sym_2_5495
+.globl sym_2_5496
+sym_2_5496: la $2, sym_2_5496
+.globl sym_2_5497
+sym_2_5497: la $2, sym_2_5497
+.globl sym_2_5498
+sym_2_5498: la $2, sym_2_5498
+.globl sym_2_5499
+sym_2_5499: la $2, sym_2_5499
+.globl sym_2_5500
+sym_2_5500: la $2, sym_2_5500
+.globl sym_2_5501
+sym_2_5501: la $2, sym_2_5501
+.globl sym_2_5502
+sym_2_5502: la $2, sym_2_5502
+.globl sym_2_5503
+sym_2_5503: la $2, sym_2_5503
+.globl sym_2_5504
+sym_2_5504: la $2, sym_2_5504
+.globl sym_2_5505
+sym_2_5505: la $2, sym_2_5505
+.globl sym_2_5506
+sym_2_5506: la $2, sym_2_5506
+.globl sym_2_5507
+sym_2_5507: la $2, sym_2_5507
+.globl sym_2_5508
+sym_2_5508: la $2, sym_2_5508
+.globl sym_2_5509
+sym_2_5509: la $2, sym_2_5509
+.globl sym_2_5510
+sym_2_5510: la $2, sym_2_5510
+.globl sym_2_5511
+sym_2_5511: la $2, sym_2_5511
+.globl sym_2_5512
+sym_2_5512: la $2, sym_2_5512
+.globl sym_2_5513
+sym_2_5513: la $2, sym_2_5513
+.globl sym_2_5514
+sym_2_5514: la $2, sym_2_5514
+.globl sym_2_5515
+sym_2_5515: la $2, sym_2_5515
+.globl sym_2_5516
+sym_2_5516: la $2, sym_2_5516
+.globl sym_2_5517
+sym_2_5517: la $2, sym_2_5517
+.globl sym_2_5518
+sym_2_5518: la $2, sym_2_5518
+.globl sym_2_5519
+sym_2_5519: la $2, sym_2_5519
+.globl sym_2_5520
+sym_2_5520: la $2, sym_2_5520
+.globl sym_2_5521
+sym_2_5521: la $2, sym_2_5521
+.globl sym_2_5522
+sym_2_5522: la $2, sym_2_5522
+.globl sym_2_5523
+sym_2_5523: la $2, sym_2_5523
+.globl sym_2_5524
+sym_2_5524: la $2, sym_2_5524
+.globl sym_2_5525
+sym_2_5525: la $2, sym_2_5525
+.globl sym_2_5526
+sym_2_5526: la $2, sym_2_5526
+.globl sym_2_5527
+sym_2_5527: la $2, sym_2_5527
+.globl sym_2_5528
+sym_2_5528: la $2, sym_2_5528
+.globl sym_2_5529
+sym_2_5529: la $2, sym_2_5529
+.globl sym_2_5530
+sym_2_5530: la $2, sym_2_5530
+.globl sym_2_5531
+sym_2_5531: la $2, sym_2_5531
+.globl sym_2_5532
+sym_2_5532: la $2, sym_2_5532
+.globl sym_2_5533
+sym_2_5533: la $2, sym_2_5533
+.globl sym_2_5534
+sym_2_5534: la $2, sym_2_5534
+.globl sym_2_5535
+sym_2_5535: la $2, sym_2_5535
+.globl sym_2_5536
+sym_2_5536: la $2, sym_2_5536
+.globl sym_2_5537
+sym_2_5537: la $2, sym_2_5537
+.globl sym_2_5538
+sym_2_5538: la $2, sym_2_5538
+.globl sym_2_5539
+sym_2_5539: la $2, sym_2_5539
+.globl sym_2_5540
+sym_2_5540: la $2, sym_2_5540
+.globl sym_2_5541
+sym_2_5541: la $2, sym_2_5541
+.globl sym_2_5542
+sym_2_5542: la $2, sym_2_5542
+.globl sym_2_5543
+sym_2_5543: la $2, sym_2_5543
+.globl sym_2_5544
+sym_2_5544: la $2, sym_2_5544
+.globl sym_2_5545
+sym_2_5545: la $2, sym_2_5545
+.globl sym_2_5546
+sym_2_5546: la $2, sym_2_5546
+.globl sym_2_5547
+sym_2_5547: la $2, sym_2_5547
+.globl sym_2_5548
+sym_2_5548: la $2, sym_2_5548
+.globl sym_2_5549
+sym_2_5549: la $2, sym_2_5549
+.globl sym_2_5550
+sym_2_5550: la $2, sym_2_5550
+.globl sym_2_5551
+sym_2_5551: la $2, sym_2_5551
+.globl sym_2_5552
+sym_2_5552: la $2, sym_2_5552
+.globl sym_2_5553
+sym_2_5553: la $2, sym_2_5553
+.globl sym_2_5554
+sym_2_5554: la $2, sym_2_5554
+.globl sym_2_5555
+sym_2_5555: la $2, sym_2_5555
+.globl sym_2_5556
+sym_2_5556: la $2, sym_2_5556
+.globl sym_2_5557
+sym_2_5557: la $2, sym_2_5557
+.globl sym_2_5558
+sym_2_5558: la $2, sym_2_5558
+.globl sym_2_5559
+sym_2_5559: la $2, sym_2_5559
+.globl sym_2_5560
+sym_2_5560: la $2, sym_2_5560
+.globl sym_2_5561
+sym_2_5561: la $2, sym_2_5561
+.globl sym_2_5562
+sym_2_5562: la $2, sym_2_5562
+.globl sym_2_5563
+sym_2_5563: la $2, sym_2_5563
+.globl sym_2_5564
+sym_2_5564: la $2, sym_2_5564
+.globl sym_2_5565
+sym_2_5565: la $2, sym_2_5565
+.globl sym_2_5566
+sym_2_5566: la $2, sym_2_5566
+.globl sym_2_5567
+sym_2_5567: la $2, sym_2_5567
+.globl sym_2_5568
+sym_2_5568: la $2, sym_2_5568
+.globl sym_2_5569
+sym_2_5569: la $2, sym_2_5569
+.globl sym_2_5570
+sym_2_5570: la $2, sym_2_5570
+.globl sym_2_5571
+sym_2_5571: la $2, sym_2_5571
+.globl sym_2_5572
+sym_2_5572: la $2, sym_2_5572
+.globl sym_2_5573
+sym_2_5573: la $2, sym_2_5573
+.globl sym_2_5574
+sym_2_5574: la $2, sym_2_5574
+.globl sym_2_5575
+sym_2_5575: la $2, sym_2_5575
+.globl sym_2_5576
+sym_2_5576: la $2, sym_2_5576
+.globl sym_2_5577
+sym_2_5577: la $2, sym_2_5577
+.globl sym_2_5578
+sym_2_5578: la $2, sym_2_5578
+.globl sym_2_5579
+sym_2_5579: la $2, sym_2_5579
+.globl sym_2_5580
+sym_2_5580: la $2, sym_2_5580
+.globl sym_2_5581
+sym_2_5581: la $2, sym_2_5581
+.globl sym_2_5582
+sym_2_5582: la $2, sym_2_5582
+.globl sym_2_5583
+sym_2_5583: la $2, sym_2_5583
+.globl sym_2_5584
+sym_2_5584: la $2, sym_2_5584
+.globl sym_2_5585
+sym_2_5585: la $2, sym_2_5585
+.globl sym_2_5586
+sym_2_5586: la $2, sym_2_5586
+.globl sym_2_5587
+sym_2_5587: la $2, sym_2_5587
+.globl sym_2_5588
+sym_2_5588: la $2, sym_2_5588
+.globl sym_2_5589
+sym_2_5589: la $2, sym_2_5589
+.globl sym_2_5590
+sym_2_5590: la $2, sym_2_5590
+.globl sym_2_5591
+sym_2_5591: la $2, sym_2_5591
+.globl sym_2_5592
+sym_2_5592: la $2, sym_2_5592
+.globl sym_2_5593
+sym_2_5593: la $2, sym_2_5593
+.globl sym_2_5594
+sym_2_5594: la $2, sym_2_5594
+.globl sym_2_5595
+sym_2_5595: la $2, sym_2_5595
+.globl sym_2_5596
+sym_2_5596: la $2, sym_2_5596
+.globl sym_2_5597
+sym_2_5597: la $2, sym_2_5597
+.globl sym_2_5598
+sym_2_5598: la $2, sym_2_5598
+.globl sym_2_5599
+sym_2_5599: la $2, sym_2_5599
+.globl sym_2_5600
+sym_2_5600: la $2, sym_2_5600
+.globl sym_2_5601
+sym_2_5601: la $2, sym_2_5601
+.globl sym_2_5602
+sym_2_5602: la $2, sym_2_5602
+.globl sym_2_5603
+sym_2_5603: la $2, sym_2_5603
+.globl sym_2_5604
+sym_2_5604: la $2, sym_2_5604
+.globl sym_2_5605
+sym_2_5605: la $2, sym_2_5605
+.globl sym_2_5606
+sym_2_5606: la $2, sym_2_5606
+.globl sym_2_5607
+sym_2_5607: la $2, sym_2_5607
+.globl sym_2_5608
+sym_2_5608: la $2, sym_2_5608
+.globl sym_2_5609
+sym_2_5609: la $2, sym_2_5609
+.globl sym_2_5610
+sym_2_5610: la $2, sym_2_5610
+.globl sym_2_5611
+sym_2_5611: la $2, sym_2_5611
+.globl sym_2_5612
+sym_2_5612: la $2, sym_2_5612
+.globl sym_2_5613
+sym_2_5613: la $2, sym_2_5613
+.globl sym_2_5614
+sym_2_5614: la $2, sym_2_5614
+.globl sym_2_5615
+sym_2_5615: la $2, sym_2_5615
+.globl sym_2_5616
+sym_2_5616: la $2, sym_2_5616
+.globl sym_2_5617
+sym_2_5617: la $2, sym_2_5617
+.globl sym_2_5618
+sym_2_5618: la $2, sym_2_5618
+.globl sym_2_5619
+sym_2_5619: la $2, sym_2_5619
+.globl sym_2_5620
+sym_2_5620: la $2, sym_2_5620
+.globl sym_2_5621
+sym_2_5621: la $2, sym_2_5621
+.globl sym_2_5622
+sym_2_5622: la $2, sym_2_5622
+.globl sym_2_5623
+sym_2_5623: la $2, sym_2_5623
+.globl sym_2_5624
+sym_2_5624: la $2, sym_2_5624
+.globl sym_2_5625
+sym_2_5625: la $2, sym_2_5625
+.globl sym_2_5626
+sym_2_5626: la $2, sym_2_5626
+.globl sym_2_5627
+sym_2_5627: la $2, sym_2_5627
+.globl sym_2_5628
+sym_2_5628: la $2, sym_2_5628
+.globl sym_2_5629
+sym_2_5629: la $2, sym_2_5629
+.globl sym_2_5630
+sym_2_5630: la $2, sym_2_5630
+.globl sym_2_5631
+sym_2_5631: la $2, sym_2_5631
+.globl sym_2_5632
+sym_2_5632: la $2, sym_2_5632
+.globl sym_2_5633
+sym_2_5633: la $2, sym_2_5633
+.globl sym_2_5634
+sym_2_5634: la $2, sym_2_5634
+.globl sym_2_5635
+sym_2_5635: la $2, sym_2_5635
+.globl sym_2_5636
+sym_2_5636: la $2, sym_2_5636
+.globl sym_2_5637
+sym_2_5637: la $2, sym_2_5637
+.globl sym_2_5638
+sym_2_5638: la $2, sym_2_5638
+.globl sym_2_5639
+sym_2_5639: la $2, sym_2_5639
+.globl sym_2_5640
+sym_2_5640: la $2, sym_2_5640
+.globl sym_2_5641
+sym_2_5641: la $2, sym_2_5641
+.globl sym_2_5642
+sym_2_5642: la $2, sym_2_5642
+.globl sym_2_5643
+sym_2_5643: la $2, sym_2_5643
+.globl sym_2_5644
+sym_2_5644: la $2, sym_2_5644
+.globl sym_2_5645
+sym_2_5645: la $2, sym_2_5645
+.globl sym_2_5646
+sym_2_5646: la $2, sym_2_5646
+.globl sym_2_5647
+sym_2_5647: la $2, sym_2_5647
+.globl sym_2_5648
+sym_2_5648: la $2, sym_2_5648
+.globl sym_2_5649
+sym_2_5649: la $2, sym_2_5649
+.globl sym_2_5650
+sym_2_5650: la $2, sym_2_5650
+.globl sym_2_5651
+sym_2_5651: la $2, sym_2_5651
+.globl sym_2_5652
+sym_2_5652: la $2, sym_2_5652
+.globl sym_2_5653
+sym_2_5653: la $2, sym_2_5653
+.globl sym_2_5654
+sym_2_5654: la $2, sym_2_5654
+.globl sym_2_5655
+sym_2_5655: la $2, sym_2_5655
+.globl sym_2_5656
+sym_2_5656: la $2, sym_2_5656
+.globl sym_2_5657
+sym_2_5657: la $2, sym_2_5657
+.globl sym_2_5658
+sym_2_5658: la $2, sym_2_5658
+.globl sym_2_5659
+sym_2_5659: la $2, sym_2_5659
+.globl sym_2_5660
+sym_2_5660: la $2, sym_2_5660
+.globl sym_2_5661
+sym_2_5661: la $2, sym_2_5661
+.globl sym_2_5662
+sym_2_5662: la $2, sym_2_5662
+.globl sym_2_5663
+sym_2_5663: la $2, sym_2_5663
+.globl sym_2_5664
+sym_2_5664: la $2, sym_2_5664
+.globl sym_2_5665
+sym_2_5665: la $2, sym_2_5665
+.globl sym_2_5666
+sym_2_5666: la $2, sym_2_5666
+.globl sym_2_5667
+sym_2_5667: la $2, sym_2_5667
+.globl sym_2_5668
+sym_2_5668: la $2, sym_2_5668
+.globl sym_2_5669
+sym_2_5669: la $2, sym_2_5669
+.globl sym_2_5670
+sym_2_5670: la $2, sym_2_5670
+.globl sym_2_5671
+sym_2_5671: la $2, sym_2_5671
+.globl sym_2_5672
+sym_2_5672: la $2, sym_2_5672
+.globl sym_2_5673
+sym_2_5673: la $2, sym_2_5673
+.globl sym_2_5674
+sym_2_5674: la $2, sym_2_5674
+.globl sym_2_5675
+sym_2_5675: la $2, sym_2_5675
+.globl sym_2_5676
+sym_2_5676: la $2, sym_2_5676
+.globl sym_2_5677
+sym_2_5677: la $2, sym_2_5677
+.globl sym_2_5678
+sym_2_5678: la $2, sym_2_5678
+.globl sym_2_5679
+sym_2_5679: la $2, sym_2_5679
+.globl sym_2_5680
+sym_2_5680: la $2, sym_2_5680
+.globl sym_2_5681
+sym_2_5681: la $2, sym_2_5681
+.globl sym_2_5682
+sym_2_5682: la $2, sym_2_5682
+.globl sym_2_5683
+sym_2_5683: la $2, sym_2_5683
+.globl sym_2_5684
+sym_2_5684: la $2, sym_2_5684
+.globl sym_2_5685
+sym_2_5685: la $2, sym_2_5685
+.globl sym_2_5686
+sym_2_5686: la $2, sym_2_5686
+.globl sym_2_5687
+sym_2_5687: la $2, sym_2_5687
+.globl sym_2_5688
+sym_2_5688: la $2, sym_2_5688
+.globl sym_2_5689
+sym_2_5689: la $2, sym_2_5689
+.globl sym_2_5690
+sym_2_5690: la $2, sym_2_5690
+.globl sym_2_5691
+sym_2_5691: la $2, sym_2_5691
+.globl sym_2_5692
+sym_2_5692: la $2, sym_2_5692
+.globl sym_2_5693
+sym_2_5693: la $2, sym_2_5693
+.globl sym_2_5694
+sym_2_5694: la $2, sym_2_5694
+.globl sym_2_5695
+sym_2_5695: la $2, sym_2_5695
+.globl sym_2_5696
+sym_2_5696: la $2, sym_2_5696
+.globl sym_2_5697
+sym_2_5697: la $2, sym_2_5697
+.globl sym_2_5698
+sym_2_5698: la $2, sym_2_5698
+.globl sym_2_5699
+sym_2_5699: la $2, sym_2_5699
+.globl sym_2_5700
+sym_2_5700: la $2, sym_2_5700
+.globl sym_2_5701
+sym_2_5701: la $2, sym_2_5701
+.globl sym_2_5702
+sym_2_5702: la $2, sym_2_5702
+.globl sym_2_5703
+sym_2_5703: la $2, sym_2_5703
+.globl sym_2_5704
+sym_2_5704: la $2, sym_2_5704
+.globl sym_2_5705
+sym_2_5705: la $2, sym_2_5705
+.globl sym_2_5706
+sym_2_5706: la $2, sym_2_5706
+.globl sym_2_5707
+sym_2_5707: la $2, sym_2_5707
+.globl sym_2_5708
+sym_2_5708: la $2, sym_2_5708
+.globl sym_2_5709
+sym_2_5709: la $2, sym_2_5709
+.globl sym_2_5710
+sym_2_5710: la $2, sym_2_5710
+.globl sym_2_5711
+sym_2_5711: la $2, sym_2_5711
+.globl sym_2_5712
+sym_2_5712: la $2, sym_2_5712
+.globl sym_2_5713
+sym_2_5713: la $2, sym_2_5713
+.globl sym_2_5714
+sym_2_5714: la $2, sym_2_5714
+.globl sym_2_5715
+sym_2_5715: la $2, sym_2_5715
+.globl sym_2_5716
+sym_2_5716: la $2, sym_2_5716
+.globl sym_2_5717
+sym_2_5717: la $2, sym_2_5717
+.globl sym_2_5718
+sym_2_5718: la $2, sym_2_5718
+.globl sym_2_5719
+sym_2_5719: la $2, sym_2_5719
+.globl sym_2_5720
+sym_2_5720: la $2, sym_2_5720
+.globl sym_2_5721
+sym_2_5721: la $2, sym_2_5721
+.globl sym_2_5722
+sym_2_5722: la $2, sym_2_5722
+.globl sym_2_5723
+sym_2_5723: la $2, sym_2_5723
+.globl sym_2_5724
+sym_2_5724: la $2, sym_2_5724
+.globl sym_2_5725
+sym_2_5725: la $2, sym_2_5725
+.globl sym_2_5726
+sym_2_5726: la $2, sym_2_5726
+.globl sym_2_5727
+sym_2_5727: la $2, sym_2_5727
+.globl sym_2_5728
+sym_2_5728: la $2, sym_2_5728
+.globl sym_2_5729
+sym_2_5729: la $2, sym_2_5729
+.globl sym_2_5730
+sym_2_5730: la $2, sym_2_5730
+.globl sym_2_5731
+sym_2_5731: la $2, sym_2_5731
+.globl sym_2_5732
+sym_2_5732: la $2, sym_2_5732
+.globl sym_2_5733
+sym_2_5733: la $2, sym_2_5733
+.globl sym_2_5734
+sym_2_5734: la $2, sym_2_5734
+.globl sym_2_5735
+sym_2_5735: la $2, sym_2_5735
+.globl sym_2_5736
+sym_2_5736: la $2, sym_2_5736
+.globl sym_2_5737
+sym_2_5737: la $2, sym_2_5737
+.globl sym_2_5738
+sym_2_5738: la $2, sym_2_5738
+.globl sym_2_5739
+sym_2_5739: la $2, sym_2_5739
+.globl sym_2_5740
+sym_2_5740: la $2, sym_2_5740
+.globl sym_2_5741
+sym_2_5741: la $2, sym_2_5741
+.globl sym_2_5742
+sym_2_5742: la $2, sym_2_5742
+.globl sym_2_5743
+sym_2_5743: la $2, sym_2_5743
+.globl sym_2_5744
+sym_2_5744: la $2, sym_2_5744
+.globl sym_2_5745
+sym_2_5745: la $2, sym_2_5745
+.globl sym_2_5746
+sym_2_5746: la $2, sym_2_5746
+.globl sym_2_5747
+sym_2_5747: la $2, sym_2_5747
+.globl sym_2_5748
+sym_2_5748: la $2, sym_2_5748
+.globl sym_2_5749
+sym_2_5749: la $2, sym_2_5749
+.globl sym_2_5750
+sym_2_5750: la $2, sym_2_5750
+.globl sym_2_5751
+sym_2_5751: la $2, sym_2_5751
+.globl sym_2_5752
+sym_2_5752: la $2, sym_2_5752
+.globl sym_2_5753
+sym_2_5753: la $2, sym_2_5753
+.globl sym_2_5754
+sym_2_5754: la $2, sym_2_5754
+.globl sym_2_5755
+sym_2_5755: la $2, sym_2_5755
+.globl sym_2_5756
+sym_2_5756: la $2, sym_2_5756
+.globl sym_2_5757
+sym_2_5757: la $2, sym_2_5757
+.globl sym_2_5758
+sym_2_5758: la $2, sym_2_5758
+.globl sym_2_5759
+sym_2_5759: la $2, sym_2_5759
+.globl sym_2_5760
+sym_2_5760: la $2, sym_2_5760
+.globl sym_2_5761
+sym_2_5761: la $2, sym_2_5761
+.globl sym_2_5762
+sym_2_5762: la $2, sym_2_5762
+.globl sym_2_5763
+sym_2_5763: la $2, sym_2_5763
+.globl sym_2_5764
+sym_2_5764: la $2, sym_2_5764
+.globl sym_2_5765
+sym_2_5765: la $2, sym_2_5765
+.globl sym_2_5766
+sym_2_5766: la $2, sym_2_5766
+.globl sym_2_5767
+sym_2_5767: la $2, sym_2_5767
+.globl sym_2_5768
+sym_2_5768: la $2, sym_2_5768
+.globl sym_2_5769
+sym_2_5769: la $2, sym_2_5769
+.globl sym_2_5770
+sym_2_5770: la $2, sym_2_5770
+.globl sym_2_5771
+sym_2_5771: la $2, sym_2_5771
+.globl sym_2_5772
+sym_2_5772: la $2, sym_2_5772
+.globl sym_2_5773
+sym_2_5773: la $2, sym_2_5773
+.globl sym_2_5774
+sym_2_5774: la $2, sym_2_5774
+.globl sym_2_5775
+sym_2_5775: la $2, sym_2_5775
+.globl sym_2_5776
+sym_2_5776: la $2, sym_2_5776
+.globl sym_2_5777
+sym_2_5777: la $2, sym_2_5777
+.globl sym_2_5778
+sym_2_5778: la $2, sym_2_5778
+.globl sym_2_5779
+sym_2_5779: la $2, sym_2_5779
+.globl sym_2_5780
+sym_2_5780: la $2, sym_2_5780
+.globl sym_2_5781
+sym_2_5781: la $2, sym_2_5781
+.globl sym_2_5782
+sym_2_5782: la $2, sym_2_5782
+.globl sym_2_5783
+sym_2_5783: la $2, sym_2_5783
+.globl sym_2_5784
+sym_2_5784: la $2, sym_2_5784
+.globl sym_2_5785
+sym_2_5785: la $2, sym_2_5785
+.globl sym_2_5786
+sym_2_5786: la $2, sym_2_5786
+.globl sym_2_5787
+sym_2_5787: la $2, sym_2_5787
+.globl sym_2_5788
+sym_2_5788: la $2, sym_2_5788
+.globl sym_2_5789
+sym_2_5789: la $2, sym_2_5789
+.globl sym_2_5790
+sym_2_5790: la $2, sym_2_5790
+.globl sym_2_5791
+sym_2_5791: la $2, sym_2_5791
+.globl sym_2_5792
+sym_2_5792: la $2, sym_2_5792
+.globl sym_2_5793
+sym_2_5793: la $2, sym_2_5793
+.globl sym_2_5794
+sym_2_5794: la $2, sym_2_5794
+.globl sym_2_5795
+sym_2_5795: la $2, sym_2_5795
+.globl sym_2_5796
+sym_2_5796: la $2, sym_2_5796
+.globl sym_2_5797
+sym_2_5797: la $2, sym_2_5797
+.globl sym_2_5798
+sym_2_5798: la $2, sym_2_5798
+.globl sym_2_5799
+sym_2_5799: la $2, sym_2_5799
+.globl sym_2_5800
+sym_2_5800: la $2, sym_2_5800
+.globl sym_2_5801
+sym_2_5801: la $2, sym_2_5801
+.globl sym_2_5802
+sym_2_5802: la $2, sym_2_5802
+.globl sym_2_5803
+sym_2_5803: la $2, sym_2_5803
+.globl sym_2_5804
+sym_2_5804: la $2, sym_2_5804
+.globl sym_2_5805
+sym_2_5805: la $2, sym_2_5805
+.globl sym_2_5806
+sym_2_5806: la $2, sym_2_5806
+.globl sym_2_5807
+sym_2_5807: la $2, sym_2_5807
+.globl sym_2_5808
+sym_2_5808: la $2, sym_2_5808
+.globl sym_2_5809
+sym_2_5809: la $2, sym_2_5809
+.globl sym_2_5810
+sym_2_5810: la $2, sym_2_5810
+.globl sym_2_5811
+sym_2_5811: la $2, sym_2_5811
+.globl sym_2_5812
+sym_2_5812: la $2, sym_2_5812
+.globl sym_2_5813
+sym_2_5813: la $2, sym_2_5813
+.globl sym_2_5814
+sym_2_5814: la $2, sym_2_5814
+.globl sym_2_5815
+sym_2_5815: la $2, sym_2_5815
+.globl sym_2_5816
+sym_2_5816: la $2, sym_2_5816
+.globl sym_2_5817
+sym_2_5817: la $2, sym_2_5817
+.globl sym_2_5818
+sym_2_5818: la $2, sym_2_5818
+.globl sym_2_5819
+sym_2_5819: la $2, sym_2_5819
+.globl sym_2_5820
+sym_2_5820: la $2, sym_2_5820
+.globl sym_2_5821
+sym_2_5821: la $2, sym_2_5821
+.globl sym_2_5822
+sym_2_5822: la $2, sym_2_5822
+.globl sym_2_5823
+sym_2_5823: la $2, sym_2_5823
+.globl sym_2_5824
+sym_2_5824: la $2, sym_2_5824
+.globl sym_2_5825
+sym_2_5825: la $2, sym_2_5825
+.globl sym_2_5826
+sym_2_5826: la $2, sym_2_5826
+.globl sym_2_5827
+sym_2_5827: la $2, sym_2_5827
+.globl sym_2_5828
+sym_2_5828: la $2, sym_2_5828
+.globl sym_2_5829
+sym_2_5829: la $2, sym_2_5829
+.globl sym_2_5830
+sym_2_5830: la $2, sym_2_5830
+.globl sym_2_5831
+sym_2_5831: la $2, sym_2_5831
+.globl sym_2_5832
+sym_2_5832: la $2, sym_2_5832
+.globl sym_2_5833
+sym_2_5833: la $2, sym_2_5833
+.globl sym_2_5834
+sym_2_5834: la $2, sym_2_5834
+.globl sym_2_5835
+sym_2_5835: la $2, sym_2_5835
+.globl sym_2_5836
+sym_2_5836: la $2, sym_2_5836
+.globl sym_2_5837
+sym_2_5837: la $2, sym_2_5837
+.globl sym_2_5838
+sym_2_5838: la $2, sym_2_5838
+.globl sym_2_5839
+sym_2_5839: la $2, sym_2_5839
+.globl sym_2_5840
+sym_2_5840: la $2, sym_2_5840
+.globl sym_2_5841
+sym_2_5841: la $2, sym_2_5841
+.globl sym_2_5842
+sym_2_5842: la $2, sym_2_5842
+.globl sym_2_5843
+sym_2_5843: la $2, sym_2_5843
+.globl sym_2_5844
+sym_2_5844: la $2, sym_2_5844
+.globl sym_2_5845
+sym_2_5845: la $2, sym_2_5845
+.globl sym_2_5846
+sym_2_5846: la $2, sym_2_5846
+.globl sym_2_5847
+sym_2_5847: la $2, sym_2_5847
+.globl sym_2_5848
+sym_2_5848: la $2, sym_2_5848
+.globl sym_2_5849
+sym_2_5849: la $2, sym_2_5849
+.globl sym_2_5850
+sym_2_5850: la $2, sym_2_5850
+.globl sym_2_5851
+sym_2_5851: la $2, sym_2_5851
+.globl sym_2_5852
+sym_2_5852: la $2, sym_2_5852
+.globl sym_2_5853
+sym_2_5853: la $2, sym_2_5853
+.globl sym_2_5854
+sym_2_5854: la $2, sym_2_5854
+.globl sym_2_5855
+sym_2_5855: la $2, sym_2_5855
+.globl sym_2_5856
+sym_2_5856: la $2, sym_2_5856
+.globl sym_2_5857
+sym_2_5857: la $2, sym_2_5857
+.globl sym_2_5858
+sym_2_5858: la $2, sym_2_5858
+.globl sym_2_5859
+sym_2_5859: la $2, sym_2_5859
+.globl sym_2_5860
+sym_2_5860: la $2, sym_2_5860
+.globl sym_2_5861
+sym_2_5861: la $2, sym_2_5861
+.globl sym_2_5862
+sym_2_5862: la $2, sym_2_5862
+.globl sym_2_5863
+sym_2_5863: la $2, sym_2_5863
+.globl sym_2_5864
+sym_2_5864: la $2, sym_2_5864
+.globl sym_2_5865
+sym_2_5865: la $2, sym_2_5865
+.globl sym_2_5866
+sym_2_5866: la $2, sym_2_5866
+.globl sym_2_5867
+sym_2_5867: la $2, sym_2_5867
+.globl sym_2_5868
+sym_2_5868: la $2, sym_2_5868
+.globl sym_2_5869
+sym_2_5869: la $2, sym_2_5869
+.globl sym_2_5870
+sym_2_5870: la $2, sym_2_5870
+.globl sym_2_5871
+sym_2_5871: la $2, sym_2_5871
+.globl sym_2_5872
+sym_2_5872: la $2, sym_2_5872
+.globl sym_2_5873
+sym_2_5873: la $2, sym_2_5873
+.globl sym_2_5874
+sym_2_5874: la $2, sym_2_5874
+.globl sym_2_5875
+sym_2_5875: la $2, sym_2_5875
+.globl sym_2_5876
+sym_2_5876: la $2, sym_2_5876
+.globl sym_2_5877
+sym_2_5877: la $2, sym_2_5877
+.globl sym_2_5878
+sym_2_5878: la $2, sym_2_5878
+.globl sym_2_5879
+sym_2_5879: la $2, sym_2_5879
+.globl sym_2_5880
+sym_2_5880: la $2, sym_2_5880
+.globl sym_2_5881
+sym_2_5881: la $2, sym_2_5881
+.globl sym_2_5882
+sym_2_5882: la $2, sym_2_5882
+.globl sym_2_5883
+sym_2_5883: la $2, sym_2_5883
+.globl sym_2_5884
+sym_2_5884: la $2, sym_2_5884
+.globl sym_2_5885
+sym_2_5885: la $2, sym_2_5885
+.globl sym_2_5886
+sym_2_5886: la $2, sym_2_5886
+.globl sym_2_5887
+sym_2_5887: la $2, sym_2_5887
+.globl sym_2_5888
+sym_2_5888: la $2, sym_2_5888
+.globl sym_2_5889
+sym_2_5889: la $2, sym_2_5889
+.globl sym_2_5890
+sym_2_5890: la $2, sym_2_5890
+.globl sym_2_5891
+sym_2_5891: la $2, sym_2_5891
+.globl sym_2_5892
+sym_2_5892: la $2, sym_2_5892
+.globl sym_2_5893
+sym_2_5893: la $2, sym_2_5893
+.globl sym_2_5894
+sym_2_5894: la $2, sym_2_5894
+.globl sym_2_5895
+sym_2_5895: la $2, sym_2_5895
+.globl sym_2_5896
+sym_2_5896: la $2, sym_2_5896
+.globl sym_2_5897
+sym_2_5897: la $2, sym_2_5897
+.globl sym_2_5898
+sym_2_5898: la $2, sym_2_5898
+.globl sym_2_5899
+sym_2_5899: la $2, sym_2_5899
+.globl sym_2_5900
+sym_2_5900: la $2, sym_2_5900
+.globl sym_2_5901
+sym_2_5901: la $2, sym_2_5901
+.globl sym_2_5902
+sym_2_5902: la $2, sym_2_5902
+.globl sym_2_5903
+sym_2_5903: la $2, sym_2_5903
+.globl sym_2_5904
+sym_2_5904: la $2, sym_2_5904
+.globl sym_2_5905
+sym_2_5905: la $2, sym_2_5905
+.globl sym_2_5906
+sym_2_5906: la $2, sym_2_5906
+.globl sym_2_5907
+sym_2_5907: la $2, sym_2_5907
+.globl sym_2_5908
+sym_2_5908: la $2, sym_2_5908
+.globl sym_2_5909
+sym_2_5909: la $2, sym_2_5909
+.globl sym_2_5910
+sym_2_5910: la $2, sym_2_5910
+.globl sym_2_5911
+sym_2_5911: la $2, sym_2_5911
+.globl sym_2_5912
+sym_2_5912: la $2, sym_2_5912
+.globl sym_2_5913
+sym_2_5913: la $2, sym_2_5913
+.globl sym_2_5914
+sym_2_5914: la $2, sym_2_5914
+.globl sym_2_5915
+sym_2_5915: la $2, sym_2_5915
+.globl sym_2_5916
+sym_2_5916: la $2, sym_2_5916
+.globl sym_2_5917
+sym_2_5917: la $2, sym_2_5917
+.globl sym_2_5918
+sym_2_5918: la $2, sym_2_5918
+.globl sym_2_5919
+sym_2_5919: la $2, sym_2_5919
+.globl sym_2_5920
+sym_2_5920: la $2, sym_2_5920
+.globl sym_2_5921
+sym_2_5921: la $2, sym_2_5921
+.globl sym_2_5922
+sym_2_5922: la $2, sym_2_5922
+.globl sym_2_5923
+sym_2_5923: la $2, sym_2_5923
+.globl sym_2_5924
+sym_2_5924: la $2, sym_2_5924
+.globl sym_2_5925
+sym_2_5925: la $2, sym_2_5925
+.globl sym_2_5926
+sym_2_5926: la $2, sym_2_5926
+.globl sym_2_5927
+sym_2_5927: la $2, sym_2_5927
+.globl sym_2_5928
+sym_2_5928: la $2, sym_2_5928
+.globl sym_2_5929
+sym_2_5929: la $2, sym_2_5929
+.globl sym_2_5930
+sym_2_5930: la $2, sym_2_5930
+.globl sym_2_5931
+sym_2_5931: la $2, sym_2_5931
+.globl sym_2_5932
+sym_2_5932: la $2, sym_2_5932
+.globl sym_2_5933
+sym_2_5933: la $2, sym_2_5933
+.globl sym_2_5934
+sym_2_5934: la $2, sym_2_5934
+.globl sym_2_5935
+sym_2_5935: la $2, sym_2_5935
+.globl sym_2_5936
+sym_2_5936: la $2, sym_2_5936
+.globl sym_2_5937
+sym_2_5937: la $2, sym_2_5937
+.globl sym_2_5938
+sym_2_5938: la $2, sym_2_5938
+.globl sym_2_5939
+sym_2_5939: la $2, sym_2_5939
+.globl sym_2_5940
+sym_2_5940: la $2, sym_2_5940
+.globl sym_2_5941
+sym_2_5941: la $2, sym_2_5941
+.globl sym_2_5942
+sym_2_5942: la $2, sym_2_5942
+.globl sym_2_5943
+sym_2_5943: la $2, sym_2_5943
+.globl sym_2_5944
+sym_2_5944: la $2, sym_2_5944
+.globl sym_2_5945
+sym_2_5945: la $2, sym_2_5945
+.globl sym_2_5946
+sym_2_5946: la $2, sym_2_5946
+.globl sym_2_5947
+sym_2_5947: la $2, sym_2_5947
+.globl sym_2_5948
+sym_2_5948: la $2, sym_2_5948
+.globl sym_2_5949
+sym_2_5949: la $2, sym_2_5949
+.globl sym_2_5950
+sym_2_5950: la $2, sym_2_5950
+.globl sym_2_5951
+sym_2_5951: la $2, sym_2_5951
+.globl sym_2_5952
+sym_2_5952: la $2, sym_2_5952
+.globl sym_2_5953
+sym_2_5953: la $2, sym_2_5953
+.globl sym_2_5954
+sym_2_5954: la $2, sym_2_5954
+.globl sym_2_5955
+sym_2_5955: la $2, sym_2_5955
+.globl sym_2_5956
+sym_2_5956: la $2, sym_2_5956
+.globl sym_2_5957
+sym_2_5957: la $2, sym_2_5957
+.globl sym_2_5958
+sym_2_5958: la $2, sym_2_5958
+.globl sym_2_5959
+sym_2_5959: la $2, sym_2_5959
+.globl sym_2_5960
+sym_2_5960: la $2, sym_2_5960
+.globl sym_2_5961
+sym_2_5961: la $2, sym_2_5961
+.globl sym_2_5962
+sym_2_5962: la $2, sym_2_5962
+.globl sym_2_5963
+sym_2_5963: la $2, sym_2_5963
+.globl sym_2_5964
+sym_2_5964: la $2, sym_2_5964
+.globl sym_2_5965
+sym_2_5965: la $2, sym_2_5965
+.globl sym_2_5966
+sym_2_5966: la $2, sym_2_5966
+.globl sym_2_5967
+sym_2_5967: la $2, sym_2_5967
+.globl sym_2_5968
+sym_2_5968: la $2, sym_2_5968
+.globl sym_2_5969
+sym_2_5969: la $2, sym_2_5969
+.globl sym_2_5970
+sym_2_5970: la $2, sym_2_5970
+.globl sym_2_5971
+sym_2_5971: la $2, sym_2_5971
+.globl sym_2_5972
+sym_2_5972: la $2, sym_2_5972
+.globl sym_2_5973
+sym_2_5973: la $2, sym_2_5973
+.globl sym_2_5974
+sym_2_5974: la $2, sym_2_5974
+.globl sym_2_5975
+sym_2_5975: la $2, sym_2_5975
+.globl sym_2_5976
+sym_2_5976: la $2, sym_2_5976
+.globl sym_2_5977
+sym_2_5977: la $2, sym_2_5977
+.globl sym_2_5978
+sym_2_5978: la $2, sym_2_5978
+.globl sym_2_5979
+sym_2_5979: la $2, sym_2_5979
+.globl sym_2_5980
+sym_2_5980: la $2, sym_2_5980
+.globl sym_2_5981
+sym_2_5981: la $2, sym_2_5981
+.globl sym_2_5982
+sym_2_5982: la $2, sym_2_5982
+.globl sym_2_5983
+sym_2_5983: la $2, sym_2_5983
+.globl sym_2_5984
+sym_2_5984: la $2, sym_2_5984
+.globl sym_2_5985
+sym_2_5985: la $2, sym_2_5985
+.globl sym_2_5986
+sym_2_5986: la $2, sym_2_5986
+.globl sym_2_5987
+sym_2_5987: la $2, sym_2_5987
+.globl sym_2_5988
+sym_2_5988: la $2, sym_2_5988
+.globl sym_2_5989
+sym_2_5989: la $2, sym_2_5989
+.globl sym_2_5990
+sym_2_5990: la $2, sym_2_5990
+.globl sym_2_5991
+sym_2_5991: la $2, sym_2_5991
+.globl sym_2_5992
+sym_2_5992: la $2, sym_2_5992
+.globl sym_2_5993
+sym_2_5993: la $2, sym_2_5993
+.globl sym_2_5994
+sym_2_5994: la $2, sym_2_5994
+.globl sym_2_5995
+sym_2_5995: la $2, sym_2_5995
+.globl sym_2_5996
+sym_2_5996: la $2, sym_2_5996
+.globl sym_2_5997
+sym_2_5997: la $2, sym_2_5997
+.globl sym_2_5998
+sym_2_5998: la $2, sym_2_5998
+.globl sym_2_5999
+sym_2_5999: la $2, sym_2_5999
+.globl sym_2_6000
+sym_2_6000: la $2, sym_2_6000
+.globl sym_2_6001
+sym_2_6001: la $2, sym_2_6001
+.globl sym_2_6002
+sym_2_6002: la $2, sym_2_6002
+.globl sym_2_6003
+sym_2_6003: la $2, sym_2_6003
+.globl sym_2_6004
+sym_2_6004: la $2, sym_2_6004
+.globl sym_2_6005
+sym_2_6005: la $2, sym_2_6005
+.globl sym_2_6006
+sym_2_6006: la $2, sym_2_6006
+.globl sym_2_6007
+sym_2_6007: la $2, sym_2_6007
+.globl sym_2_6008
+sym_2_6008: la $2, sym_2_6008
+.globl sym_2_6009
+sym_2_6009: la $2, sym_2_6009
+.globl sym_2_6010
+sym_2_6010: la $2, sym_2_6010
+.globl sym_2_6011
+sym_2_6011: la $2, sym_2_6011
+.globl sym_2_6012
+sym_2_6012: la $2, sym_2_6012
+.globl sym_2_6013
+sym_2_6013: la $2, sym_2_6013
+.globl sym_2_6014
+sym_2_6014: la $2, sym_2_6014
+.globl sym_2_6015
+sym_2_6015: la $2, sym_2_6015
+.globl sym_2_6016
+sym_2_6016: la $2, sym_2_6016
+.globl sym_2_6017
+sym_2_6017: la $2, sym_2_6017
+.globl sym_2_6018
+sym_2_6018: la $2, sym_2_6018
+.globl sym_2_6019
+sym_2_6019: la $2, sym_2_6019
+.globl sym_2_6020
+sym_2_6020: la $2, sym_2_6020
+.globl sym_2_6021
+sym_2_6021: la $2, sym_2_6021
+.globl sym_2_6022
+sym_2_6022: la $2, sym_2_6022
+.globl sym_2_6023
+sym_2_6023: la $2, sym_2_6023
+.globl sym_2_6024
+sym_2_6024: la $2, sym_2_6024
+.globl sym_2_6025
+sym_2_6025: la $2, sym_2_6025
+.globl sym_2_6026
+sym_2_6026: la $2, sym_2_6026
+.globl sym_2_6027
+sym_2_6027: la $2, sym_2_6027
+.globl sym_2_6028
+sym_2_6028: la $2, sym_2_6028
+.globl sym_2_6029
+sym_2_6029: la $2, sym_2_6029
+.globl sym_2_6030
+sym_2_6030: la $2, sym_2_6030
+.globl sym_2_6031
+sym_2_6031: la $2, sym_2_6031
+.globl sym_2_6032
+sym_2_6032: la $2, sym_2_6032
+.globl sym_2_6033
+sym_2_6033: la $2, sym_2_6033
+.globl sym_2_6034
+sym_2_6034: la $2, sym_2_6034
+.globl sym_2_6035
+sym_2_6035: la $2, sym_2_6035
+.globl sym_2_6036
+sym_2_6036: la $2, sym_2_6036
+.globl sym_2_6037
+sym_2_6037: la $2, sym_2_6037
+.globl sym_2_6038
+sym_2_6038: la $2, sym_2_6038
+.globl sym_2_6039
+sym_2_6039: la $2, sym_2_6039
+.globl sym_2_6040
+sym_2_6040: la $2, sym_2_6040
+.globl sym_2_6041
+sym_2_6041: la $2, sym_2_6041
+.globl sym_2_6042
+sym_2_6042: la $2, sym_2_6042
+.globl sym_2_6043
+sym_2_6043: la $2, sym_2_6043
+.globl sym_2_6044
+sym_2_6044: la $2, sym_2_6044
+.globl sym_2_6045
+sym_2_6045: la $2, sym_2_6045
+.globl sym_2_6046
+sym_2_6046: la $2, sym_2_6046
+.globl sym_2_6047
+sym_2_6047: la $2, sym_2_6047
+.globl sym_2_6048
+sym_2_6048: la $2, sym_2_6048
+.globl sym_2_6049
+sym_2_6049: la $2, sym_2_6049
+.globl sym_2_6050
+sym_2_6050: la $2, sym_2_6050
+.globl sym_2_6051
+sym_2_6051: la $2, sym_2_6051
+.globl sym_2_6052
+sym_2_6052: la $2, sym_2_6052
+.globl sym_2_6053
+sym_2_6053: la $2, sym_2_6053
+.globl sym_2_6054
+sym_2_6054: la $2, sym_2_6054
+.globl sym_2_6055
+sym_2_6055: la $2, sym_2_6055
+.globl sym_2_6056
+sym_2_6056: la $2, sym_2_6056
+.globl sym_2_6057
+sym_2_6057: la $2, sym_2_6057
+.globl sym_2_6058
+sym_2_6058: la $2, sym_2_6058
+.globl sym_2_6059
+sym_2_6059: la $2, sym_2_6059
+.globl sym_2_6060
+sym_2_6060: la $2, sym_2_6060
+.globl sym_2_6061
+sym_2_6061: la $2, sym_2_6061
+.globl sym_2_6062
+sym_2_6062: la $2, sym_2_6062
+.globl sym_2_6063
+sym_2_6063: la $2, sym_2_6063
+.globl sym_2_6064
+sym_2_6064: la $2, sym_2_6064
+.globl sym_2_6065
+sym_2_6065: la $2, sym_2_6065
+.globl sym_2_6066
+sym_2_6066: la $2, sym_2_6066
+.globl sym_2_6067
+sym_2_6067: la $2, sym_2_6067
+.globl sym_2_6068
+sym_2_6068: la $2, sym_2_6068
+.globl sym_2_6069
+sym_2_6069: la $2, sym_2_6069
+.globl sym_2_6070
+sym_2_6070: la $2, sym_2_6070
+.globl sym_2_6071
+sym_2_6071: la $2, sym_2_6071
+.globl sym_2_6072
+sym_2_6072: la $2, sym_2_6072
+.globl sym_2_6073
+sym_2_6073: la $2, sym_2_6073
+.globl sym_2_6074
+sym_2_6074: la $2, sym_2_6074
+.globl sym_2_6075
+sym_2_6075: la $2, sym_2_6075
+.globl sym_2_6076
+sym_2_6076: la $2, sym_2_6076
+.globl sym_2_6077
+sym_2_6077: la $2, sym_2_6077
+.globl sym_2_6078
+sym_2_6078: la $2, sym_2_6078
+.globl sym_2_6079
+sym_2_6079: la $2, sym_2_6079
+.globl sym_2_6080
+sym_2_6080: la $2, sym_2_6080
+.globl sym_2_6081
+sym_2_6081: la $2, sym_2_6081
+.globl sym_2_6082
+sym_2_6082: la $2, sym_2_6082
+.globl sym_2_6083
+sym_2_6083: la $2, sym_2_6083
+.globl sym_2_6084
+sym_2_6084: la $2, sym_2_6084
+.globl sym_2_6085
+sym_2_6085: la $2, sym_2_6085
+.globl sym_2_6086
+sym_2_6086: la $2, sym_2_6086
+.globl sym_2_6087
+sym_2_6087: la $2, sym_2_6087
+.globl sym_2_6088
+sym_2_6088: la $2, sym_2_6088
+.globl sym_2_6089
+sym_2_6089: la $2, sym_2_6089
+.globl sym_2_6090
+sym_2_6090: la $2, sym_2_6090
+.globl sym_2_6091
+sym_2_6091: la $2, sym_2_6091
+.globl sym_2_6092
+sym_2_6092: la $2, sym_2_6092
+.globl sym_2_6093
+sym_2_6093: la $2, sym_2_6093
+.globl sym_2_6094
+sym_2_6094: la $2, sym_2_6094
+.globl sym_2_6095
+sym_2_6095: la $2, sym_2_6095
+.globl sym_2_6096
+sym_2_6096: la $2, sym_2_6096
+.globl sym_2_6097
+sym_2_6097: la $2, sym_2_6097
+.globl sym_2_6098
+sym_2_6098: la $2, sym_2_6098
+.globl sym_2_6099
+sym_2_6099: la $2, sym_2_6099
+.globl sym_2_6100
+sym_2_6100: la $2, sym_2_6100
+.globl sym_2_6101
+sym_2_6101: la $2, sym_2_6101
+.globl sym_2_6102
+sym_2_6102: la $2, sym_2_6102
+.globl sym_2_6103
+sym_2_6103: la $2, sym_2_6103
+.globl sym_2_6104
+sym_2_6104: la $2, sym_2_6104
+.globl sym_2_6105
+sym_2_6105: la $2, sym_2_6105
+.globl sym_2_6106
+sym_2_6106: la $2, sym_2_6106
+.globl sym_2_6107
+sym_2_6107: la $2, sym_2_6107
+.globl sym_2_6108
+sym_2_6108: la $2, sym_2_6108
+.globl sym_2_6109
+sym_2_6109: la $2, sym_2_6109
+.globl sym_2_6110
+sym_2_6110: la $2, sym_2_6110
+.globl sym_2_6111
+sym_2_6111: la $2, sym_2_6111
+.globl sym_2_6112
+sym_2_6112: la $2, sym_2_6112
+.globl sym_2_6113
+sym_2_6113: la $2, sym_2_6113
+.globl sym_2_6114
+sym_2_6114: la $2, sym_2_6114
+.globl sym_2_6115
+sym_2_6115: la $2, sym_2_6115
+.globl sym_2_6116
+sym_2_6116: la $2, sym_2_6116
+.globl sym_2_6117
+sym_2_6117: la $2, sym_2_6117
+.globl sym_2_6118
+sym_2_6118: la $2, sym_2_6118
+.globl sym_2_6119
+sym_2_6119: la $2, sym_2_6119
+.globl sym_2_6120
+sym_2_6120: la $2, sym_2_6120
+.globl sym_2_6121
+sym_2_6121: la $2, sym_2_6121
+.globl sym_2_6122
+sym_2_6122: la $2, sym_2_6122
+.globl sym_2_6123
+sym_2_6123: la $2, sym_2_6123
+.globl sym_2_6124
+sym_2_6124: la $2, sym_2_6124
+.globl sym_2_6125
+sym_2_6125: la $2, sym_2_6125
+.globl sym_2_6126
+sym_2_6126: la $2, sym_2_6126
+.globl sym_2_6127
+sym_2_6127: la $2, sym_2_6127
+.globl sym_2_6128
+sym_2_6128: la $2, sym_2_6128
+.globl sym_2_6129
+sym_2_6129: la $2, sym_2_6129
+.globl sym_2_6130
+sym_2_6130: la $2, sym_2_6130
+.globl sym_2_6131
+sym_2_6131: la $2, sym_2_6131
+.globl sym_2_6132
+sym_2_6132: la $2, sym_2_6132
+.globl sym_2_6133
+sym_2_6133: la $2, sym_2_6133
+.globl sym_2_6134
+sym_2_6134: la $2, sym_2_6134
+.globl sym_2_6135
+sym_2_6135: la $2, sym_2_6135
+.globl sym_2_6136
+sym_2_6136: la $2, sym_2_6136
+.globl sym_2_6137
+sym_2_6137: la $2, sym_2_6137
+.globl sym_2_6138
+sym_2_6138: la $2, sym_2_6138
+.globl sym_2_6139
+sym_2_6139: la $2, sym_2_6139
+.globl sym_2_6140
+sym_2_6140: la $2, sym_2_6140
+.globl sym_2_6141
+sym_2_6141: la $2, sym_2_6141
+.globl sym_2_6142
+sym_2_6142: la $2, sym_2_6142
+.globl sym_2_6143
+sym_2_6143: la $2, sym_2_6143
+.globl sym_2_6144
+sym_2_6144: la $2, sym_2_6144
+.globl sym_2_6145
+sym_2_6145: la $2, sym_2_6145
+.globl sym_2_6146
+sym_2_6146: la $2, sym_2_6146
+.globl sym_2_6147
+sym_2_6147: la $2, sym_2_6147
+.globl sym_2_6148
+sym_2_6148: la $2, sym_2_6148
+.globl sym_2_6149
+sym_2_6149: la $2, sym_2_6149
+.globl sym_2_6150
+sym_2_6150: la $2, sym_2_6150
+.globl sym_2_6151
+sym_2_6151: la $2, sym_2_6151
+.globl sym_2_6152
+sym_2_6152: la $2, sym_2_6152
+.globl sym_2_6153
+sym_2_6153: la $2, sym_2_6153
+.globl sym_2_6154
+sym_2_6154: la $2, sym_2_6154
+.globl sym_2_6155
+sym_2_6155: la $2, sym_2_6155
+.globl sym_2_6156
+sym_2_6156: la $2, sym_2_6156
+.globl sym_2_6157
+sym_2_6157: la $2, sym_2_6157
+.globl sym_2_6158
+sym_2_6158: la $2, sym_2_6158
+.globl sym_2_6159
+sym_2_6159: la $2, sym_2_6159
+.globl sym_2_6160
+sym_2_6160: la $2, sym_2_6160
+.globl sym_2_6161
+sym_2_6161: la $2, sym_2_6161
+.globl sym_2_6162
+sym_2_6162: la $2, sym_2_6162
+.globl sym_2_6163
+sym_2_6163: la $2, sym_2_6163
+.globl sym_2_6164
+sym_2_6164: la $2, sym_2_6164
+.globl sym_2_6165
+sym_2_6165: la $2, sym_2_6165
+.globl sym_2_6166
+sym_2_6166: la $2, sym_2_6166
+.globl sym_2_6167
+sym_2_6167: la $2, sym_2_6167
+.globl sym_2_6168
+sym_2_6168: la $2, sym_2_6168
+.globl sym_2_6169
+sym_2_6169: la $2, sym_2_6169
+.globl sym_2_6170
+sym_2_6170: la $2, sym_2_6170
+.globl sym_2_6171
+sym_2_6171: la $2, sym_2_6171
+.globl sym_2_6172
+sym_2_6172: la $2, sym_2_6172
+.globl sym_2_6173
+sym_2_6173: la $2, sym_2_6173
+.globl sym_2_6174
+sym_2_6174: la $2, sym_2_6174
+.globl sym_2_6175
+sym_2_6175: la $2, sym_2_6175
+.globl sym_2_6176
+sym_2_6176: la $2, sym_2_6176
+.globl sym_2_6177
+sym_2_6177: la $2, sym_2_6177
+.globl sym_2_6178
+sym_2_6178: la $2, sym_2_6178
+.globl sym_2_6179
+sym_2_6179: la $2, sym_2_6179
+.globl sym_2_6180
+sym_2_6180: la $2, sym_2_6180
+.globl sym_2_6181
+sym_2_6181: la $2, sym_2_6181
+.globl sym_2_6182
+sym_2_6182: la $2, sym_2_6182
+.globl sym_2_6183
+sym_2_6183: la $2, sym_2_6183
+.globl sym_2_6184
+sym_2_6184: la $2, sym_2_6184
+.globl sym_2_6185
+sym_2_6185: la $2, sym_2_6185
+.globl sym_2_6186
+sym_2_6186: la $2, sym_2_6186
+.globl sym_2_6187
+sym_2_6187: la $2, sym_2_6187
+.globl sym_2_6188
+sym_2_6188: la $2, sym_2_6188
+.globl sym_2_6189
+sym_2_6189: la $2, sym_2_6189
+.globl sym_2_6190
+sym_2_6190: la $2, sym_2_6190
+.globl sym_2_6191
+sym_2_6191: la $2, sym_2_6191
+.globl sym_2_6192
+sym_2_6192: la $2, sym_2_6192
+.globl sym_2_6193
+sym_2_6193: la $2, sym_2_6193
+.globl sym_2_6194
+sym_2_6194: la $2, sym_2_6194
+.globl sym_2_6195
+sym_2_6195: la $2, sym_2_6195
+.globl sym_2_6196
+sym_2_6196: la $2, sym_2_6196
+.globl sym_2_6197
+sym_2_6197: la $2, sym_2_6197
+.globl sym_2_6198
+sym_2_6198: la $2, sym_2_6198
+.globl sym_2_6199
+sym_2_6199: la $2, sym_2_6199
+.globl sym_2_6200
+sym_2_6200: la $2, sym_2_6200
+.globl sym_2_6201
+sym_2_6201: la $2, sym_2_6201
+.globl sym_2_6202
+sym_2_6202: la $2, sym_2_6202
+.globl sym_2_6203
+sym_2_6203: la $2, sym_2_6203
+.globl sym_2_6204
+sym_2_6204: la $2, sym_2_6204
+.globl sym_2_6205
+sym_2_6205: la $2, sym_2_6205
+.globl sym_2_6206
+sym_2_6206: la $2, sym_2_6206
+.globl sym_2_6207
+sym_2_6207: la $2, sym_2_6207
+.globl sym_2_6208
+sym_2_6208: la $2, sym_2_6208
+.globl sym_2_6209
+sym_2_6209: la $2, sym_2_6209
+.globl sym_2_6210
+sym_2_6210: la $2, sym_2_6210
+.globl sym_2_6211
+sym_2_6211: la $2, sym_2_6211
+.globl sym_2_6212
+sym_2_6212: la $2, sym_2_6212
+.globl sym_2_6213
+sym_2_6213: la $2, sym_2_6213
+.globl sym_2_6214
+sym_2_6214: la $2, sym_2_6214
+.globl sym_2_6215
+sym_2_6215: la $2, sym_2_6215
+.globl sym_2_6216
+sym_2_6216: la $2, sym_2_6216
+.globl sym_2_6217
+sym_2_6217: la $2, sym_2_6217
+.globl sym_2_6218
+sym_2_6218: la $2, sym_2_6218
+.globl sym_2_6219
+sym_2_6219: la $2, sym_2_6219
+.globl sym_2_6220
+sym_2_6220: la $2, sym_2_6220
+.globl sym_2_6221
+sym_2_6221: la $2, sym_2_6221
+.globl sym_2_6222
+sym_2_6222: la $2, sym_2_6222
+.globl sym_2_6223
+sym_2_6223: la $2, sym_2_6223
+.globl sym_2_6224
+sym_2_6224: la $2, sym_2_6224
+.globl sym_2_6225
+sym_2_6225: la $2, sym_2_6225
+.globl sym_2_6226
+sym_2_6226: la $2, sym_2_6226
+.globl sym_2_6227
+sym_2_6227: la $2, sym_2_6227
+.globl sym_2_6228
+sym_2_6228: la $2, sym_2_6228
+.globl sym_2_6229
+sym_2_6229: la $2, sym_2_6229
+.globl sym_2_6230
+sym_2_6230: la $2, sym_2_6230
+.globl sym_2_6231
+sym_2_6231: la $2, sym_2_6231
+.globl sym_2_6232
+sym_2_6232: la $2, sym_2_6232
+.globl sym_2_6233
+sym_2_6233: la $2, sym_2_6233
+.globl sym_2_6234
+sym_2_6234: la $2, sym_2_6234
+.globl sym_2_6235
+sym_2_6235: la $2, sym_2_6235
+.globl sym_2_6236
+sym_2_6236: la $2, sym_2_6236
+.globl sym_2_6237
+sym_2_6237: la $2, sym_2_6237
+.globl sym_2_6238
+sym_2_6238: la $2, sym_2_6238
+.globl sym_2_6239
+sym_2_6239: la $2, sym_2_6239
+.globl sym_2_6240
+sym_2_6240: la $2, sym_2_6240
+.globl sym_2_6241
+sym_2_6241: la $2, sym_2_6241
+.globl sym_2_6242
+sym_2_6242: la $2, sym_2_6242
+.globl sym_2_6243
+sym_2_6243: la $2, sym_2_6243
+.globl sym_2_6244
+sym_2_6244: la $2, sym_2_6244
+.globl sym_2_6245
+sym_2_6245: la $2, sym_2_6245
+.globl sym_2_6246
+sym_2_6246: la $2, sym_2_6246
+.globl sym_2_6247
+sym_2_6247: la $2, sym_2_6247
+.globl sym_2_6248
+sym_2_6248: la $2, sym_2_6248
+.globl sym_2_6249
+sym_2_6249: la $2, sym_2_6249
+.globl sym_2_6250
+sym_2_6250: la $2, sym_2_6250
+.globl sym_2_6251
+sym_2_6251: la $2, sym_2_6251
+.globl sym_2_6252
+sym_2_6252: la $2, sym_2_6252
+.globl sym_2_6253
+sym_2_6253: la $2, sym_2_6253
+.globl sym_2_6254
+sym_2_6254: la $2, sym_2_6254
+.globl sym_2_6255
+sym_2_6255: la $2, sym_2_6255
+.globl sym_2_6256
+sym_2_6256: la $2, sym_2_6256
+.globl sym_2_6257
+sym_2_6257: la $2, sym_2_6257
+.globl sym_2_6258
+sym_2_6258: la $2, sym_2_6258
+.globl sym_2_6259
+sym_2_6259: la $2, sym_2_6259
+.globl sym_2_6260
+sym_2_6260: la $2, sym_2_6260
+.globl sym_2_6261
+sym_2_6261: la $2, sym_2_6261
+.globl sym_2_6262
+sym_2_6262: la $2, sym_2_6262
+.globl sym_2_6263
+sym_2_6263: la $2, sym_2_6263
+.globl sym_2_6264
+sym_2_6264: la $2, sym_2_6264
+.globl sym_2_6265
+sym_2_6265: la $2, sym_2_6265
+.globl sym_2_6266
+sym_2_6266: la $2, sym_2_6266
+.globl sym_2_6267
+sym_2_6267: la $2, sym_2_6267
+.globl sym_2_6268
+sym_2_6268: la $2, sym_2_6268
+.globl sym_2_6269
+sym_2_6269: la $2, sym_2_6269
+.globl sym_2_6270
+sym_2_6270: la $2, sym_2_6270
+.globl sym_2_6271
+sym_2_6271: la $2, sym_2_6271
+.globl sym_2_6272
+sym_2_6272: la $2, sym_2_6272
+.globl sym_2_6273
+sym_2_6273: la $2, sym_2_6273
+.globl sym_2_6274
+sym_2_6274: la $2, sym_2_6274
+.globl sym_2_6275
+sym_2_6275: la $2, sym_2_6275
+.globl sym_2_6276
+sym_2_6276: la $2, sym_2_6276
+.globl sym_2_6277
+sym_2_6277: la $2, sym_2_6277
+.globl sym_2_6278
+sym_2_6278: la $2, sym_2_6278
+.globl sym_2_6279
+sym_2_6279: la $2, sym_2_6279
+.globl sym_2_6280
+sym_2_6280: la $2, sym_2_6280
+.globl sym_2_6281
+sym_2_6281: la $2, sym_2_6281
+.globl sym_2_6282
+sym_2_6282: la $2, sym_2_6282
+.globl sym_2_6283
+sym_2_6283: la $2, sym_2_6283
+.globl sym_2_6284
+sym_2_6284: la $2, sym_2_6284
+.globl sym_2_6285
+sym_2_6285: la $2, sym_2_6285
+.globl sym_2_6286
+sym_2_6286: la $2, sym_2_6286
+.globl sym_2_6287
+sym_2_6287: la $2, sym_2_6287
+.globl sym_2_6288
+sym_2_6288: la $2, sym_2_6288
+.globl sym_2_6289
+sym_2_6289: la $2, sym_2_6289
+.globl sym_2_6290
+sym_2_6290: la $2, sym_2_6290
+.globl sym_2_6291
+sym_2_6291: la $2, sym_2_6291
+.globl sym_2_6292
+sym_2_6292: la $2, sym_2_6292
+.globl sym_2_6293
+sym_2_6293: la $2, sym_2_6293
+.globl sym_2_6294
+sym_2_6294: la $2, sym_2_6294
+.globl sym_2_6295
+sym_2_6295: la $2, sym_2_6295
+.globl sym_2_6296
+sym_2_6296: la $2, sym_2_6296
+.globl sym_2_6297
+sym_2_6297: la $2, sym_2_6297
+.globl sym_2_6298
+sym_2_6298: la $2, sym_2_6298
+.globl sym_2_6299
+sym_2_6299: la $2, sym_2_6299
+.globl sym_2_6300
+sym_2_6300: la $2, sym_2_6300
+.globl sym_2_6301
+sym_2_6301: la $2, sym_2_6301
+.globl sym_2_6302
+sym_2_6302: la $2, sym_2_6302
+.globl sym_2_6303
+sym_2_6303: la $2, sym_2_6303
+.globl sym_2_6304
+sym_2_6304: la $2, sym_2_6304
+.globl sym_2_6305
+sym_2_6305: la $2, sym_2_6305
+.globl sym_2_6306
+sym_2_6306: la $2, sym_2_6306
+.globl sym_2_6307
+sym_2_6307: la $2, sym_2_6307
+.globl sym_2_6308
+sym_2_6308: la $2, sym_2_6308
+.globl sym_2_6309
+sym_2_6309: la $2, sym_2_6309
+.globl sym_2_6310
+sym_2_6310: la $2, sym_2_6310
+.globl sym_2_6311
+sym_2_6311: la $2, sym_2_6311
+.globl sym_2_6312
+sym_2_6312: la $2, sym_2_6312
+.globl sym_2_6313
+sym_2_6313: la $2, sym_2_6313
+.globl sym_2_6314
+sym_2_6314: la $2, sym_2_6314
+.globl sym_2_6315
+sym_2_6315: la $2, sym_2_6315
+.globl sym_2_6316
+sym_2_6316: la $2, sym_2_6316
+.globl sym_2_6317
+sym_2_6317: la $2, sym_2_6317
+.globl sym_2_6318
+sym_2_6318: la $2, sym_2_6318
+.globl sym_2_6319
+sym_2_6319: la $2, sym_2_6319
+.globl sym_2_6320
+sym_2_6320: la $2, sym_2_6320
+.globl sym_2_6321
+sym_2_6321: la $2, sym_2_6321
+.globl sym_2_6322
+sym_2_6322: la $2, sym_2_6322
+.globl sym_2_6323
+sym_2_6323: la $2, sym_2_6323
+.globl sym_2_6324
+sym_2_6324: la $2, sym_2_6324
+.globl sym_2_6325
+sym_2_6325: la $2, sym_2_6325
+.globl sym_2_6326
+sym_2_6326: la $2, sym_2_6326
+.globl sym_2_6327
+sym_2_6327: la $2, sym_2_6327
+.globl sym_2_6328
+sym_2_6328: la $2, sym_2_6328
+.globl sym_2_6329
+sym_2_6329: la $2, sym_2_6329
+.globl sym_2_6330
+sym_2_6330: la $2, sym_2_6330
+.globl sym_2_6331
+sym_2_6331: la $2, sym_2_6331
+.globl sym_2_6332
+sym_2_6332: la $2, sym_2_6332
+.globl sym_2_6333
+sym_2_6333: la $2, sym_2_6333
+.globl sym_2_6334
+sym_2_6334: la $2, sym_2_6334
+.globl sym_2_6335
+sym_2_6335: la $2, sym_2_6335
+.globl sym_2_6336
+sym_2_6336: la $2, sym_2_6336
+.globl sym_2_6337
+sym_2_6337: la $2, sym_2_6337
+.globl sym_2_6338
+sym_2_6338: la $2, sym_2_6338
+.globl sym_2_6339
+sym_2_6339: la $2, sym_2_6339
+.globl sym_2_6340
+sym_2_6340: la $2, sym_2_6340
+.globl sym_2_6341
+sym_2_6341: la $2, sym_2_6341
+.globl sym_2_6342
+sym_2_6342: la $2, sym_2_6342
+.globl sym_2_6343
+sym_2_6343: la $2, sym_2_6343
+.globl sym_2_6344
+sym_2_6344: la $2, sym_2_6344
+.globl sym_2_6345
+sym_2_6345: la $2, sym_2_6345
+.globl sym_2_6346
+sym_2_6346: la $2, sym_2_6346
+.globl sym_2_6347
+sym_2_6347: la $2, sym_2_6347
+.globl sym_2_6348
+sym_2_6348: la $2, sym_2_6348
+.globl sym_2_6349
+sym_2_6349: la $2, sym_2_6349
+.globl sym_2_6350
+sym_2_6350: la $2, sym_2_6350
+.globl sym_2_6351
+sym_2_6351: la $2, sym_2_6351
+.globl sym_2_6352
+sym_2_6352: la $2, sym_2_6352
+.globl sym_2_6353
+sym_2_6353: la $2, sym_2_6353
+.globl sym_2_6354
+sym_2_6354: la $2, sym_2_6354
+.globl sym_2_6355
+sym_2_6355: la $2, sym_2_6355
+.globl sym_2_6356
+sym_2_6356: la $2, sym_2_6356
+.globl sym_2_6357
+sym_2_6357: la $2, sym_2_6357
+.globl sym_2_6358
+sym_2_6358: la $2, sym_2_6358
+.globl sym_2_6359
+sym_2_6359: la $2, sym_2_6359
+.globl sym_2_6360
+sym_2_6360: la $2, sym_2_6360
+.globl sym_2_6361
+sym_2_6361: la $2, sym_2_6361
+.globl sym_2_6362
+sym_2_6362: la $2, sym_2_6362
+.globl sym_2_6363
+sym_2_6363: la $2, sym_2_6363
+.globl sym_2_6364
+sym_2_6364: la $2, sym_2_6364
+.globl sym_2_6365
+sym_2_6365: la $2, sym_2_6365
+.globl sym_2_6366
+sym_2_6366: la $2, sym_2_6366
+.globl sym_2_6367
+sym_2_6367: la $2, sym_2_6367
+.globl sym_2_6368
+sym_2_6368: la $2, sym_2_6368
+.globl sym_2_6369
+sym_2_6369: la $2, sym_2_6369
+.globl sym_2_6370
+sym_2_6370: la $2, sym_2_6370
+.globl sym_2_6371
+sym_2_6371: la $2, sym_2_6371
+.globl sym_2_6372
+sym_2_6372: la $2, sym_2_6372
+.globl sym_2_6373
+sym_2_6373: la $2, sym_2_6373
+.globl sym_2_6374
+sym_2_6374: la $2, sym_2_6374
+.globl sym_2_6375
+sym_2_6375: la $2, sym_2_6375
+.globl sym_2_6376
+sym_2_6376: la $2, sym_2_6376
+.globl sym_2_6377
+sym_2_6377: la $2, sym_2_6377
+.globl sym_2_6378
+sym_2_6378: la $2, sym_2_6378
+.globl sym_2_6379
+sym_2_6379: la $2, sym_2_6379
+.globl sym_2_6380
+sym_2_6380: la $2, sym_2_6380
+.globl sym_2_6381
+sym_2_6381: la $2, sym_2_6381
+.globl sym_2_6382
+sym_2_6382: la $2, sym_2_6382
+.globl sym_2_6383
+sym_2_6383: la $2, sym_2_6383
+.globl sym_2_6384
+sym_2_6384: la $2, sym_2_6384
+.globl sym_2_6385
+sym_2_6385: la $2, sym_2_6385
+.globl sym_2_6386
+sym_2_6386: la $2, sym_2_6386
+.globl sym_2_6387
+sym_2_6387: la $2, sym_2_6387
+.globl sym_2_6388
+sym_2_6388: la $2, sym_2_6388
+.globl sym_2_6389
+sym_2_6389: la $2, sym_2_6389
+.globl sym_2_6390
+sym_2_6390: la $2, sym_2_6390
+.globl sym_2_6391
+sym_2_6391: la $2, sym_2_6391
+.globl sym_2_6392
+sym_2_6392: la $2, sym_2_6392
+.globl sym_2_6393
+sym_2_6393: la $2, sym_2_6393
+.globl sym_2_6394
+sym_2_6394: la $2, sym_2_6394
+.globl sym_2_6395
+sym_2_6395: la $2, sym_2_6395
+.globl sym_2_6396
+sym_2_6396: la $2, sym_2_6396
+.globl sym_2_6397
+sym_2_6397: la $2, sym_2_6397
+.globl sym_2_6398
+sym_2_6398: la $2, sym_2_6398
+.globl sym_2_6399
+sym_2_6399: la $2, sym_2_6399
+.globl sym_2_6400
+sym_2_6400: la $2, sym_2_6400
+.globl sym_2_6401
+sym_2_6401: la $2, sym_2_6401
+.globl sym_2_6402
+sym_2_6402: la $2, sym_2_6402
+.globl sym_2_6403
+sym_2_6403: la $2, sym_2_6403
+.globl sym_2_6404
+sym_2_6404: la $2, sym_2_6404
+.globl sym_2_6405
+sym_2_6405: la $2, sym_2_6405
+.globl sym_2_6406
+sym_2_6406: la $2, sym_2_6406
+.globl sym_2_6407
+sym_2_6407: la $2, sym_2_6407
+.globl sym_2_6408
+sym_2_6408: la $2, sym_2_6408
+.globl sym_2_6409
+sym_2_6409: la $2, sym_2_6409
+.globl sym_2_6410
+sym_2_6410: la $2, sym_2_6410
+.globl sym_2_6411
+sym_2_6411: la $2, sym_2_6411
+.globl sym_2_6412
+sym_2_6412: la $2, sym_2_6412
+.globl sym_2_6413
+sym_2_6413: la $2, sym_2_6413
+.globl sym_2_6414
+sym_2_6414: la $2, sym_2_6414
+.globl sym_2_6415
+sym_2_6415: la $2, sym_2_6415
+.globl sym_2_6416
+sym_2_6416: la $2, sym_2_6416
+.globl sym_2_6417
+sym_2_6417: la $2, sym_2_6417
+.globl sym_2_6418
+sym_2_6418: la $2, sym_2_6418
+.globl sym_2_6419
+sym_2_6419: la $2, sym_2_6419
+.globl sym_2_6420
+sym_2_6420: la $2, sym_2_6420
+.globl sym_2_6421
+sym_2_6421: la $2, sym_2_6421
+.globl sym_2_6422
+sym_2_6422: la $2, sym_2_6422
+.globl sym_2_6423
+sym_2_6423: la $2, sym_2_6423
+.globl sym_2_6424
+sym_2_6424: la $2, sym_2_6424
+.globl sym_2_6425
+sym_2_6425: la $2, sym_2_6425
+.globl sym_2_6426
+sym_2_6426: la $2, sym_2_6426
+.globl sym_2_6427
+sym_2_6427: la $2, sym_2_6427
+.globl sym_2_6428
+sym_2_6428: la $2, sym_2_6428
+.globl sym_2_6429
+sym_2_6429: la $2, sym_2_6429
+.globl sym_2_6430
+sym_2_6430: la $2, sym_2_6430
+.globl sym_2_6431
+sym_2_6431: la $2, sym_2_6431
+.globl sym_2_6432
+sym_2_6432: la $2, sym_2_6432
+.globl sym_2_6433
+sym_2_6433: la $2, sym_2_6433
+.globl sym_2_6434
+sym_2_6434: la $2, sym_2_6434
+.globl sym_2_6435
+sym_2_6435: la $2, sym_2_6435
+.globl sym_2_6436
+sym_2_6436: la $2, sym_2_6436
+.globl sym_2_6437
+sym_2_6437: la $2, sym_2_6437
+.globl sym_2_6438
+sym_2_6438: la $2, sym_2_6438
+.globl sym_2_6439
+sym_2_6439: la $2, sym_2_6439
+.globl sym_2_6440
+sym_2_6440: la $2, sym_2_6440
+.globl sym_2_6441
+sym_2_6441: la $2, sym_2_6441
+.globl sym_2_6442
+sym_2_6442: la $2, sym_2_6442
+.globl sym_2_6443
+sym_2_6443: la $2, sym_2_6443
+.globl sym_2_6444
+sym_2_6444: la $2, sym_2_6444
+.globl sym_2_6445
+sym_2_6445: la $2, sym_2_6445
+.globl sym_2_6446
+sym_2_6446: la $2, sym_2_6446
+.globl sym_2_6447
+sym_2_6447: la $2, sym_2_6447
+.globl sym_2_6448
+sym_2_6448: la $2, sym_2_6448
+.globl sym_2_6449
+sym_2_6449: la $2, sym_2_6449
+.globl sym_2_6450
+sym_2_6450: la $2, sym_2_6450
+.globl sym_2_6451
+sym_2_6451: la $2, sym_2_6451
+.globl sym_2_6452
+sym_2_6452: la $2, sym_2_6452
+.globl sym_2_6453
+sym_2_6453: la $2, sym_2_6453
+.globl sym_2_6454
+sym_2_6454: la $2, sym_2_6454
+.globl sym_2_6455
+sym_2_6455: la $2, sym_2_6455
+.globl sym_2_6456
+sym_2_6456: la $2, sym_2_6456
+.globl sym_2_6457
+sym_2_6457: la $2, sym_2_6457
+.globl sym_2_6458
+sym_2_6458: la $2, sym_2_6458
+.globl sym_2_6459
+sym_2_6459: la $2, sym_2_6459
+.globl sym_2_6460
+sym_2_6460: la $2, sym_2_6460
+.globl sym_2_6461
+sym_2_6461: la $2, sym_2_6461
+.globl sym_2_6462
+sym_2_6462: la $2, sym_2_6462
+.globl sym_2_6463
+sym_2_6463: la $2, sym_2_6463
+.globl sym_2_6464
+sym_2_6464: la $2, sym_2_6464
+.globl sym_2_6465
+sym_2_6465: la $2, sym_2_6465
+.globl sym_2_6466
+sym_2_6466: la $2, sym_2_6466
+.globl sym_2_6467
+sym_2_6467: la $2, sym_2_6467
+.globl sym_2_6468
+sym_2_6468: la $2, sym_2_6468
+.globl sym_2_6469
+sym_2_6469: la $2, sym_2_6469
+.globl sym_2_6470
+sym_2_6470: la $2, sym_2_6470
+.globl sym_2_6471
+sym_2_6471: la $2, sym_2_6471
+.globl sym_2_6472
+sym_2_6472: la $2, sym_2_6472
+.globl sym_2_6473
+sym_2_6473: la $2, sym_2_6473
+.globl sym_2_6474
+sym_2_6474: la $2, sym_2_6474
+.globl sym_2_6475
+sym_2_6475: la $2, sym_2_6475
+.globl sym_2_6476
+sym_2_6476: la $2, sym_2_6476
+.globl sym_2_6477
+sym_2_6477: la $2, sym_2_6477
+.globl sym_2_6478
+sym_2_6478: la $2, sym_2_6478
+.globl sym_2_6479
+sym_2_6479: la $2, sym_2_6479
+.globl sym_2_6480
+sym_2_6480: la $2, sym_2_6480
+.globl sym_2_6481
+sym_2_6481: la $2, sym_2_6481
+.globl sym_2_6482
+sym_2_6482: la $2, sym_2_6482
+.globl sym_2_6483
+sym_2_6483: la $2, sym_2_6483
+.globl sym_2_6484
+sym_2_6484: la $2, sym_2_6484
+.globl sym_2_6485
+sym_2_6485: la $2, sym_2_6485
+.globl sym_2_6486
+sym_2_6486: la $2, sym_2_6486
+.globl sym_2_6487
+sym_2_6487: la $2, sym_2_6487
+.globl sym_2_6488
+sym_2_6488: la $2, sym_2_6488
+.globl sym_2_6489
+sym_2_6489: la $2, sym_2_6489
+.globl sym_2_6490
+sym_2_6490: la $2, sym_2_6490
+.globl sym_2_6491
+sym_2_6491: la $2, sym_2_6491
+.globl sym_2_6492
+sym_2_6492: la $2, sym_2_6492
+.globl sym_2_6493
+sym_2_6493: la $2, sym_2_6493
+.globl sym_2_6494
+sym_2_6494: la $2, sym_2_6494
+.globl sym_2_6495
+sym_2_6495: la $2, sym_2_6495
+.globl sym_2_6496
+sym_2_6496: la $2, sym_2_6496
+.globl sym_2_6497
+sym_2_6497: la $2, sym_2_6497
+.globl sym_2_6498
+sym_2_6498: la $2, sym_2_6498
+.globl sym_2_6499
+sym_2_6499: la $2, sym_2_6499
+.globl sym_2_6500
+sym_2_6500: la $2, sym_2_6500
+.globl sym_2_6501
+sym_2_6501: la $2, sym_2_6501
+.globl sym_2_6502
+sym_2_6502: la $2, sym_2_6502
+.globl sym_2_6503
+sym_2_6503: la $2, sym_2_6503
+.globl sym_2_6504
+sym_2_6504: la $2, sym_2_6504
+.globl sym_2_6505
+sym_2_6505: la $2, sym_2_6505
+.globl sym_2_6506
+sym_2_6506: la $2, sym_2_6506
+.globl sym_2_6507
+sym_2_6507: la $2, sym_2_6507
+.globl sym_2_6508
+sym_2_6508: la $2, sym_2_6508
+.globl sym_2_6509
+sym_2_6509: la $2, sym_2_6509
+.globl sym_2_6510
+sym_2_6510: la $2, sym_2_6510
+.globl sym_2_6511
+sym_2_6511: la $2, sym_2_6511
+.globl sym_2_6512
+sym_2_6512: la $2, sym_2_6512
+.globl sym_2_6513
+sym_2_6513: la $2, sym_2_6513
+.globl sym_2_6514
+sym_2_6514: la $2, sym_2_6514
+.globl sym_2_6515
+sym_2_6515: la $2, sym_2_6515
+.globl sym_2_6516
+sym_2_6516: la $2, sym_2_6516
+.globl sym_2_6517
+sym_2_6517: la $2, sym_2_6517
+.globl sym_2_6518
+sym_2_6518: la $2, sym_2_6518
+.globl sym_2_6519
+sym_2_6519: la $2, sym_2_6519
+.globl sym_2_6520
+sym_2_6520: la $2, sym_2_6520
+.globl sym_2_6521
+sym_2_6521: la $2, sym_2_6521
+.globl sym_2_6522
+sym_2_6522: la $2, sym_2_6522
+.globl sym_2_6523
+sym_2_6523: la $2, sym_2_6523
+.globl sym_2_6524
+sym_2_6524: la $2, sym_2_6524
+.globl sym_2_6525
+sym_2_6525: la $2, sym_2_6525
+.globl sym_2_6526
+sym_2_6526: la $2, sym_2_6526
+.globl sym_2_6527
+sym_2_6527: la $2, sym_2_6527
+.globl sym_2_6528
+sym_2_6528: la $2, sym_2_6528
+.globl sym_2_6529
+sym_2_6529: la $2, sym_2_6529
+.globl sym_2_6530
+sym_2_6530: la $2, sym_2_6530
+.globl sym_2_6531
+sym_2_6531: la $2, sym_2_6531
+.globl sym_2_6532
+sym_2_6532: la $2, sym_2_6532
+.globl sym_2_6533
+sym_2_6533: la $2, sym_2_6533
+.globl sym_2_6534
+sym_2_6534: la $2, sym_2_6534
+.globl sym_2_6535
+sym_2_6535: la $2, sym_2_6535
+.globl sym_2_6536
+sym_2_6536: la $2, sym_2_6536
+.globl sym_2_6537
+sym_2_6537: la $2, sym_2_6537
+.globl sym_2_6538
+sym_2_6538: la $2, sym_2_6538
+.globl sym_2_6539
+sym_2_6539: la $2, sym_2_6539
+.globl sym_2_6540
+sym_2_6540: la $2, sym_2_6540
+.globl sym_2_6541
+sym_2_6541: la $2, sym_2_6541
+.globl sym_2_6542
+sym_2_6542: la $2, sym_2_6542
+.globl sym_2_6543
+sym_2_6543: la $2, sym_2_6543
+.globl sym_2_6544
+sym_2_6544: la $2, sym_2_6544
+.globl sym_2_6545
+sym_2_6545: la $2, sym_2_6545
+.globl sym_2_6546
+sym_2_6546: la $2, sym_2_6546
+.globl sym_2_6547
+sym_2_6547: la $2, sym_2_6547
+.globl sym_2_6548
+sym_2_6548: la $2, sym_2_6548
+.globl sym_2_6549
+sym_2_6549: la $2, sym_2_6549
+.globl sym_2_6550
+sym_2_6550: la $2, sym_2_6550
+.globl sym_2_6551
+sym_2_6551: la $2, sym_2_6551
+.globl sym_2_6552
+sym_2_6552: la $2, sym_2_6552
+.globl sym_2_6553
+sym_2_6553: la $2, sym_2_6553
+.globl sym_2_6554
+sym_2_6554: la $2, sym_2_6554
+.globl sym_2_6555
+sym_2_6555: la $2, sym_2_6555
+.globl sym_2_6556
+sym_2_6556: la $2, sym_2_6556
+.globl sym_2_6557
+sym_2_6557: la $2, sym_2_6557
+.globl sym_2_6558
+sym_2_6558: la $2, sym_2_6558
+.globl sym_2_6559
+sym_2_6559: la $2, sym_2_6559
+.globl sym_2_6560
+sym_2_6560: la $2, sym_2_6560
+.globl sym_2_6561
+sym_2_6561: la $2, sym_2_6561
+.globl sym_2_6562
+sym_2_6562: la $2, sym_2_6562
+.globl sym_2_6563
+sym_2_6563: la $2, sym_2_6563
+.globl sym_2_6564
+sym_2_6564: la $2, sym_2_6564
+.globl sym_2_6565
+sym_2_6565: la $2, sym_2_6565
+.globl sym_2_6566
+sym_2_6566: la $2, sym_2_6566
+.globl sym_2_6567
+sym_2_6567: la $2, sym_2_6567
+.globl sym_2_6568
+sym_2_6568: la $2, sym_2_6568
+.globl sym_2_6569
+sym_2_6569: la $2, sym_2_6569
+.globl sym_2_6570
+sym_2_6570: la $2, sym_2_6570
+.globl sym_2_6571
+sym_2_6571: la $2, sym_2_6571
+.globl sym_2_6572
+sym_2_6572: la $2, sym_2_6572
+.globl sym_2_6573
+sym_2_6573: la $2, sym_2_6573
+.globl sym_2_6574
+sym_2_6574: la $2, sym_2_6574
+.globl sym_2_6575
+sym_2_6575: la $2, sym_2_6575
+.globl sym_2_6576
+sym_2_6576: la $2, sym_2_6576
+.globl sym_2_6577
+sym_2_6577: la $2, sym_2_6577
+.globl sym_2_6578
+sym_2_6578: la $2, sym_2_6578
+.globl sym_2_6579
+sym_2_6579: la $2, sym_2_6579
+.globl sym_2_6580
+sym_2_6580: la $2, sym_2_6580
+.globl sym_2_6581
+sym_2_6581: la $2, sym_2_6581
+.globl sym_2_6582
+sym_2_6582: la $2, sym_2_6582
+.globl sym_2_6583
+sym_2_6583: la $2, sym_2_6583
+.globl sym_2_6584
+sym_2_6584: la $2, sym_2_6584
+.globl sym_2_6585
+sym_2_6585: la $2, sym_2_6585
+.globl sym_2_6586
+sym_2_6586: la $2, sym_2_6586
+.globl sym_2_6587
+sym_2_6587: la $2, sym_2_6587
+.globl sym_2_6588
+sym_2_6588: la $2, sym_2_6588
+.globl sym_2_6589
+sym_2_6589: la $2, sym_2_6589
+.globl sym_2_6590
+sym_2_6590: la $2, sym_2_6590
+.globl sym_2_6591
+sym_2_6591: la $2, sym_2_6591
+.globl sym_2_6592
+sym_2_6592: la $2, sym_2_6592
+.globl sym_2_6593
+sym_2_6593: la $2, sym_2_6593
+.globl sym_2_6594
+sym_2_6594: la $2, sym_2_6594
+.globl sym_2_6595
+sym_2_6595: la $2, sym_2_6595
+.globl sym_2_6596
+sym_2_6596: la $2, sym_2_6596
+.globl sym_2_6597
+sym_2_6597: la $2, sym_2_6597
+.globl sym_2_6598
+sym_2_6598: la $2, sym_2_6598
+.globl sym_2_6599
+sym_2_6599: la $2, sym_2_6599
+.globl sym_2_6600
+sym_2_6600: la $2, sym_2_6600
+.globl sym_2_6601
+sym_2_6601: la $2, sym_2_6601
+.globl sym_2_6602
+sym_2_6602: la $2, sym_2_6602
+.globl sym_2_6603
+sym_2_6603: la $2, sym_2_6603
+.globl sym_2_6604
+sym_2_6604: la $2, sym_2_6604
+.globl sym_2_6605
+sym_2_6605: la $2, sym_2_6605
+.globl sym_2_6606
+sym_2_6606: la $2, sym_2_6606
+.globl sym_2_6607
+sym_2_6607: la $2, sym_2_6607
+.globl sym_2_6608
+sym_2_6608: la $2, sym_2_6608
+.globl sym_2_6609
+sym_2_6609: la $2, sym_2_6609
+.globl sym_2_6610
+sym_2_6610: la $2, sym_2_6610
+.globl sym_2_6611
+sym_2_6611: la $2, sym_2_6611
+.globl sym_2_6612
+sym_2_6612: la $2, sym_2_6612
+.globl sym_2_6613
+sym_2_6613: la $2, sym_2_6613
+.globl sym_2_6614
+sym_2_6614: la $2, sym_2_6614
+.globl sym_2_6615
+sym_2_6615: la $2, sym_2_6615
+.globl sym_2_6616
+sym_2_6616: la $2, sym_2_6616
+.globl sym_2_6617
+sym_2_6617: la $2, sym_2_6617
+.globl sym_2_6618
+sym_2_6618: la $2, sym_2_6618
+.globl sym_2_6619
+sym_2_6619: la $2, sym_2_6619
+.globl sym_2_6620
+sym_2_6620: la $2, sym_2_6620
+.globl sym_2_6621
+sym_2_6621: la $2, sym_2_6621
+.globl sym_2_6622
+sym_2_6622: la $2, sym_2_6622
+.globl sym_2_6623
+sym_2_6623: la $2, sym_2_6623
+.globl sym_2_6624
+sym_2_6624: la $2, sym_2_6624
+.globl sym_2_6625
+sym_2_6625: la $2, sym_2_6625
+.globl sym_2_6626
+sym_2_6626: la $2, sym_2_6626
+.globl sym_2_6627
+sym_2_6627: la $2, sym_2_6627
+.globl sym_2_6628
+sym_2_6628: la $2, sym_2_6628
+.globl sym_2_6629
+sym_2_6629: la $2, sym_2_6629
+.globl sym_2_6630
+sym_2_6630: la $2, sym_2_6630
+.globl sym_2_6631
+sym_2_6631: la $2, sym_2_6631
+.globl sym_2_6632
+sym_2_6632: la $2, sym_2_6632
+.globl sym_2_6633
+sym_2_6633: la $2, sym_2_6633
+.globl sym_2_6634
+sym_2_6634: la $2, sym_2_6634
+.globl sym_2_6635
+sym_2_6635: la $2, sym_2_6635
+.globl sym_2_6636
+sym_2_6636: la $2, sym_2_6636
+.globl sym_2_6637
+sym_2_6637: la $2, sym_2_6637
+.globl sym_2_6638
+sym_2_6638: la $2, sym_2_6638
+.globl sym_2_6639
+sym_2_6639: la $2, sym_2_6639
+.globl sym_2_6640
+sym_2_6640: la $2, sym_2_6640
+.globl sym_2_6641
+sym_2_6641: la $2, sym_2_6641
+.globl sym_2_6642
+sym_2_6642: la $2, sym_2_6642
+.globl sym_2_6643
+sym_2_6643: la $2, sym_2_6643
+.globl sym_2_6644
+sym_2_6644: la $2, sym_2_6644
+.globl sym_2_6645
+sym_2_6645: la $2, sym_2_6645
+.globl sym_2_6646
+sym_2_6646: la $2, sym_2_6646
+.globl sym_2_6647
+sym_2_6647: la $2, sym_2_6647
+.globl sym_2_6648
+sym_2_6648: la $2, sym_2_6648
+.globl sym_2_6649
+sym_2_6649: la $2, sym_2_6649
+.globl sym_2_6650
+sym_2_6650: la $2, sym_2_6650
+.globl sym_2_6651
+sym_2_6651: la $2, sym_2_6651
+.globl sym_2_6652
+sym_2_6652: la $2, sym_2_6652
+.globl sym_2_6653
+sym_2_6653: la $2, sym_2_6653
+.globl sym_2_6654
+sym_2_6654: la $2, sym_2_6654
+.globl sym_2_6655
+sym_2_6655: la $2, sym_2_6655
+.globl sym_2_6656
+sym_2_6656: la $2, sym_2_6656
+.globl sym_2_6657
+sym_2_6657: la $2, sym_2_6657
+.globl sym_2_6658
+sym_2_6658: la $2, sym_2_6658
+.globl sym_2_6659
+sym_2_6659: la $2, sym_2_6659
+.globl sym_2_6660
+sym_2_6660: la $2, sym_2_6660
+.globl sym_2_6661
+sym_2_6661: la $2, sym_2_6661
+.globl sym_2_6662
+sym_2_6662: la $2, sym_2_6662
+.globl sym_2_6663
+sym_2_6663: la $2, sym_2_6663
+.globl sym_2_6664
+sym_2_6664: la $2, sym_2_6664
+.globl sym_2_6665
+sym_2_6665: la $2, sym_2_6665
+.globl sym_2_6666
+sym_2_6666: la $2, sym_2_6666
+.globl sym_2_6667
+sym_2_6667: la $2, sym_2_6667
+.globl sym_2_6668
+sym_2_6668: la $2, sym_2_6668
+.globl sym_2_6669
+sym_2_6669: la $2, sym_2_6669
+.globl sym_2_6670
+sym_2_6670: la $2, sym_2_6670
+.globl sym_2_6671
+sym_2_6671: la $2, sym_2_6671
+.globl sym_2_6672
+sym_2_6672: la $2, sym_2_6672
+.globl sym_2_6673
+sym_2_6673: la $2, sym_2_6673
+.globl sym_2_6674
+sym_2_6674: la $2, sym_2_6674
+.globl sym_2_6675
+sym_2_6675: la $2, sym_2_6675
+.globl sym_2_6676
+sym_2_6676: la $2, sym_2_6676
+.globl sym_2_6677
+sym_2_6677: la $2, sym_2_6677
+.globl sym_2_6678
+sym_2_6678: la $2, sym_2_6678
+.globl sym_2_6679
+sym_2_6679: la $2, sym_2_6679
+.globl sym_2_6680
+sym_2_6680: la $2, sym_2_6680
+.globl sym_2_6681
+sym_2_6681: la $2, sym_2_6681
+.globl sym_2_6682
+sym_2_6682: la $2, sym_2_6682
+.globl sym_2_6683
+sym_2_6683: la $2, sym_2_6683
+.globl sym_2_6684
+sym_2_6684: la $2, sym_2_6684
+.globl sym_2_6685
+sym_2_6685: la $2, sym_2_6685
+.globl sym_2_6686
+sym_2_6686: la $2, sym_2_6686
+.globl sym_2_6687
+sym_2_6687: la $2, sym_2_6687
+.globl sym_2_6688
+sym_2_6688: la $2, sym_2_6688
+.globl sym_2_6689
+sym_2_6689: la $2, sym_2_6689
+.globl sym_2_6690
+sym_2_6690: la $2, sym_2_6690
+.globl sym_2_6691
+sym_2_6691: la $2, sym_2_6691
+.globl sym_2_6692
+sym_2_6692: la $2, sym_2_6692
+.globl sym_2_6693
+sym_2_6693: la $2, sym_2_6693
+.globl sym_2_6694
+sym_2_6694: la $2, sym_2_6694
+.globl sym_2_6695
+sym_2_6695: la $2, sym_2_6695
+.globl sym_2_6696
+sym_2_6696: la $2, sym_2_6696
+.globl sym_2_6697
+sym_2_6697: la $2, sym_2_6697
+.globl sym_2_6698
+sym_2_6698: la $2, sym_2_6698
+.globl sym_2_6699
+sym_2_6699: la $2, sym_2_6699
+.globl sym_2_6700
+sym_2_6700: la $2, sym_2_6700
+.globl sym_2_6701
+sym_2_6701: la $2, sym_2_6701
+.globl sym_2_6702
+sym_2_6702: la $2, sym_2_6702
+.globl sym_2_6703
+sym_2_6703: la $2, sym_2_6703
+.globl sym_2_6704
+sym_2_6704: la $2, sym_2_6704
+.globl sym_2_6705
+sym_2_6705: la $2, sym_2_6705
+.globl sym_2_6706
+sym_2_6706: la $2, sym_2_6706
+.globl sym_2_6707
+sym_2_6707: la $2, sym_2_6707
+.globl sym_2_6708
+sym_2_6708: la $2, sym_2_6708
+.globl sym_2_6709
+sym_2_6709: la $2, sym_2_6709
+.globl sym_2_6710
+sym_2_6710: la $2, sym_2_6710
+.globl sym_2_6711
+sym_2_6711: la $2, sym_2_6711
+.globl sym_2_6712
+sym_2_6712: la $2, sym_2_6712
+.globl sym_2_6713
+sym_2_6713: la $2, sym_2_6713
+.globl sym_2_6714
+sym_2_6714: la $2, sym_2_6714
+.globl sym_2_6715
+sym_2_6715: la $2, sym_2_6715
+.globl sym_2_6716
+sym_2_6716: la $2, sym_2_6716
+.globl sym_2_6717
+sym_2_6717: la $2, sym_2_6717
+.globl sym_2_6718
+sym_2_6718: la $2, sym_2_6718
+.globl sym_2_6719
+sym_2_6719: la $2, sym_2_6719
+.globl sym_2_6720
+sym_2_6720: la $2, sym_2_6720
+.globl sym_2_6721
+sym_2_6721: la $2, sym_2_6721
+.globl sym_2_6722
+sym_2_6722: la $2, sym_2_6722
+.globl sym_2_6723
+sym_2_6723: la $2, sym_2_6723
+.globl sym_2_6724
+sym_2_6724: la $2, sym_2_6724
+.globl sym_2_6725
+sym_2_6725: la $2, sym_2_6725
+.globl sym_2_6726
+sym_2_6726: la $2, sym_2_6726
+.globl sym_2_6727
+sym_2_6727: la $2, sym_2_6727
+.globl sym_2_6728
+sym_2_6728: la $2, sym_2_6728
+.globl sym_2_6729
+sym_2_6729: la $2, sym_2_6729
+.globl sym_2_6730
+sym_2_6730: la $2, sym_2_6730
+.globl sym_2_6731
+sym_2_6731: la $2, sym_2_6731
+.globl sym_2_6732
+sym_2_6732: la $2, sym_2_6732
+.globl sym_2_6733
+sym_2_6733: la $2, sym_2_6733
+.globl sym_2_6734
+sym_2_6734: la $2, sym_2_6734
+.globl sym_2_6735
+sym_2_6735: la $2, sym_2_6735
+.globl sym_2_6736
+sym_2_6736: la $2, sym_2_6736
+.globl sym_2_6737
+sym_2_6737: la $2, sym_2_6737
+.globl sym_2_6738
+sym_2_6738: la $2, sym_2_6738
+.globl sym_2_6739
+sym_2_6739: la $2, sym_2_6739
+.globl sym_2_6740
+sym_2_6740: la $2, sym_2_6740
+.globl sym_2_6741
+sym_2_6741: la $2, sym_2_6741
+.globl sym_2_6742
+sym_2_6742: la $2, sym_2_6742
+.globl sym_2_6743
+sym_2_6743: la $2, sym_2_6743
+.globl sym_2_6744
+sym_2_6744: la $2, sym_2_6744
+.globl sym_2_6745
+sym_2_6745: la $2, sym_2_6745
+.globl sym_2_6746
+sym_2_6746: la $2, sym_2_6746
+.globl sym_2_6747
+sym_2_6747: la $2, sym_2_6747
+.globl sym_2_6748
+sym_2_6748: la $2, sym_2_6748
+.globl sym_2_6749
+sym_2_6749: la $2, sym_2_6749
+.globl sym_2_6750
+sym_2_6750: la $2, sym_2_6750
+.globl sym_2_6751
+sym_2_6751: la $2, sym_2_6751
+.globl sym_2_6752
+sym_2_6752: la $2, sym_2_6752
+.globl sym_2_6753
+sym_2_6753: la $2, sym_2_6753
+.globl sym_2_6754
+sym_2_6754: la $2, sym_2_6754
+.globl sym_2_6755
+sym_2_6755: la $2, sym_2_6755
+.globl sym_2_6756
+sym_2_6756: la $2, sym_2_6756
+.globl sym_2_6757
+sym_2_6757: la $2, sym_2_6757
+.globl sym_2_6758
+sym_2_6758: la $2, sym_2_6758
+.globl sym_2_6759
+sym_2_6759: la $2, sym_2_6759
+.globl sym_2_6760
+sym_2_6760: la $2, sym_2_6760
+.globl sym_2_6761
+sym_2_6761: la $2, sym_2_6761
+.globl sym_2_6762
+sym_2_6762: la $2, sym_2_6762
+.globl sym_2_6763
+sym_2_6763: la $2, sym_2_6763
+.globl sym_2_6764
+sym_2_6764: la $2, sym_2_6764
+.globl sym_2_6765
+sym_2_6765: la $2, sym_2_6765
+.globl sym_2_6766
+sym_2_6766: la $2, sym_2_6766
+.globl sym_2_6767
+sym_2_6767: la $2, sym_2_6767
+.globl sym_2_6768
+sym_2_6768: la $2, sym_2_6768
+.globl sym_2_6769
+sym_2_6769: la $2, sym_2_6769
+.globl sym_2_6770
+sym_2_6770: la $2, sym_2_6770
+.globl sym_2_6771
+sym_2_6771: la $2, sym_2_6771
+.globl sym_2_6772
+sym_2_6772: la $2, sym_2_6772
+.globl sym_2_6773
+sym_2_6773: la $2, sym_2_6773
+.globl sym_2_6774
+sym_2_6774: la $2, sym_2_6774
+.globl sym_2_6775
+sym_2_6775: la $2, sym_2_6775
+.globl sym_2_6776
+sym_2_6776: la $2, sym_2_6776
+.globl sym_2_6777
+sym_2_6777: la $2, sym_2_6777
+.globl sym_2_6778
+sym_2_6778: la $2, sym_2_6778
+.globl sym_2_6779
+sym_2_6779: la $2, sym_2_6779
+.globl sym_2_6780
+sym_2_6780: la $2, sym_2_6780
+.globl sym_2_6781
+sym_2_6781: la $2, sym_2_6781
+.globl sym_2_6782
+sym_2_6782: la $2, sym_2_6782
+.globl sym_2_6783
+sym_2_6783: la $2, sym_2_6783
+.globl sym_2_6784
+sym_2_6784: la $2, sym_2_6784
+.globl sym_2_6785
+sym_2_6785: la $2, sym_2_6785
+.globl sym_2_6786
+sym_2_6786: la $2, sym_2_6786
+.globl sym_2_6787
+sym_2_6787: la $2, sym_2_6787
+.globl sym_2_6788
+sym_2_6788: la $2, sym_2_6788
+.globl sym_2_6789
+sym_2_6789: la $2, sym_2_6789
+.globl sym_2_6790
+sym_2_6790: la $2, sym_2_6790
+.globl sym_2_6791
+sym_2_6791: la $2, sym_2_6791
+.globl sym_2_6792
+sym_2_6792: la $2, sym_2_6792
+.globl sym_2_6793
+sym_2_6793: la $2, sym_2_6793
+.globl sym_2_6794
+sym_2_6794: la $2, sym_2_6794
+.globl sym_2_6795
+sym_2_6795: la $2, sym_2_6795
+.globl sym_2_6796
+sym_2_6796: la $2, sym_2_6796
+.globl sym_2_6797
+sym_2_6797: la $2, sym_2_6797
+.globl sym_2_6798
+sym_2_6798: la $2, sym_2_6798
+.globl sym_2_6799
+sym_2_6799: la $2, sym_2_6799
+.globl sym_2_6800
+sym_2_6800: la $2, sym_2_6800
+.globl sym_2_6801
+sym_2_6801: la $2, sym_2_6801
+.globl sym_2_6802
+sym_2_6802: la $2, sym_2_6802
+.globl sym_2_6803
+sym_2_6803: la $2, sym_2_6803
+.globl sym_2_6804
+sym_2_6804: la $2, sym_2_6804
+.globl sym_2_6805
+sym_2_6805: la $2, sym_2_6805
+.globl sym_2_6806
+sym_2_6806: la $2, sym_2_6806
+.globl sym_2_6807
+sym_2_6807: la $2, sym_2_6807
+.globl sym_2_6808
+sym_2_6808: la $2, sym_2_6808
+.globl sym_2_6809
+sym_2_6809: la $2, sym_2_6809
+.globl sym_2_6810
+sym_2_6810: la $2, sym_2_6810
+.globl sym_2_6811
+sym_2_6811: la $2, sym_2_6811
+.globl sym_2_6812
+sym_2_6812: la $2, sym_2_6812
+.globl sym_2_6813
+sym_2_6813: la $2, sym_2_6813
+.globl sym_2_6814
+sym_2_6814: la $2, sym_2_6814
+.globl sym_2_6815
+sym_2_6815: la $2, sym_2_6815
+.globl sym_2_6816
+sym_2_6816: la $2, sym_2_6816
+.globl sym_2_6817
+sym_2_6817: la $2, sym_2_6817
+.globl sym_2_6818
+sym_2_6818: la $2, sym_2_6818
+.globl sym_2_6819
+sym_2_6819: la $2, sym_2_6819
+.globl sym_2_6820
+sym_2_6820: la $2, sym_2_6820
+.globl sym_2_6821
+sym_2_6821: la $2, sym_2_6821
+.globl sym_2_6822
+sym_2_6822: la $2, sym_2_6822
+.globl sym_2_6823
+sym_2_6823: la $2, sym_2_6823
+.globl sym_2_6824
+sym_2_6824: la $2, sym_2_6824
+.globl sym_2_6825
+sym_2_6825: la $2, sym_2_6825
+.globl sym_2_6826
+sym_2_6826: la $2, sym_2_6826
+.globl sym_2_6827
+sym_2_6827: la $2, sym_2_6827
+.globl sym_2_6828
+sym_2_6828: la $2, sym_2_6828
+.globl sym_2_6829
+sym_2_6829: la $2, sym_2_6829
+.globl sym_2_6830
+sym_2_6830: la $2, sym_2_6830
+.globl sym_2_6831
+sym_2_6831: la $2, sym_2_6831
+.globl sym_2_6832
+sym_2_6832: la $2, sym_2_6832
+.globl sym_2_6833
+sym_2_6833: la $2, sym_2_6833
+.globl sym_2_6834
+sym_2_6834: la $2, sym_2_6834
+.globl sym_2_6835
+sym_2_6835: la $2, sym_2_6835
+.globl sym_2_6836
+sym_2_6836: la $2, sym_2_6836
+.globl sym_2_6837
+sym_2_6837: la $2, sym_2_6837
+.globl sym_2_6838
+sym_2_6838: la $2, sym_2_6838
+.globl sym_2_6839
+sym_2_6839: la $2, sym_2_6839
+.globl sym_2_6840
+sym_2_6840: la $2, sym_2_6840
+.globl sym_2_6841
+sym_2_6841: la $2, sym_2_6841
+.globl sym_2_6842
+sym_2_6842: la $2, sym_2_6842
+.globl sym_2_6843
+sym_2_6843: la $2, sym_2_6843
+.globl sym_2_6844
+sym_2_6844: la $2, sym_2_6844
+.globl sym_2_6845
+sym_2_6845: la $2, sym_2_6845
+.globl sym_2_6846
+sym_2_6846: la $2, sym_2_6846
+.globl sym_2_6847
+sym_2_6847: la $2, sym_2_6847
+.globl sym_2_6848
+sym_2_6848: la $2, sym_2_6848
+.globl sym_2_6849
+sym_2_6849: la $2, sym_2_6849
+.globl sym_2_6850
+sym_2_6850: la $2, sym_2_6850
+.globl sym_2_6851
+sym_2_6851: la $2, sym_2_6851
+.globl sym_2_6852
+sym_2_6852: la $2, sym_2_6852
+.globl sym_2_6853
+sym_2_6853: la $2, sym_2_6853
+.globl sym_2_6854
+sym_2_6854: la $2, sym_2_6854
+.globl sym_2_6855
+sym_2_6855: la $2, sym_2_6855
+.globl sym_2_6856
+sym_2_6856: la $2, sym_2_6856
+.globl sym_2_6857
+sym_2_6857: la $2, sym_2_6857
+.globl sym_2_6858
+sym_2_6858: la $2, sym_2_6858
+.globl sym_2_6859
+sym_2_6859: la $2, sym_2_6859
+.globl sym_2_6860
+sym_2_6860: la $2, sym_2_6860
+.globl sym_2_6861
+sym_2_6861: la $2, sym_2_6861
+.globl sym_2_6862
+sym_2_6862: la $2, sym_2_6862
+.globl sym_2_6863
+sym_2_6863: la $2, sym_2_6863
+.globl sym_2_6864
+sym_2_6864: la $2, sym_2_6864
+.globl sym_2_6865
+sym_2_6865: la $2, sym_2_6865
+.globl sym_2_6866
+sym_2_6866: la $2, sym_2_6866
+.globl sym_2_6867
+sym_2_6867: la $2, sym_2_6867
+.globl sym_2_6868
+sym_2_6868: la $2, sym_2_6868
+.globl sym_2_6869
+sym_2_6869: la $2, sym_2_6869
+.globl sym_2_6870
+sym_2_6870: la $2, sym_2_6870
+.globl sym_2_6871
+sym_2_6871: la $2, sym_2_6871
+.globl sym_2_6872
+sym_2_6872: la $2, sym_2_6872
+.globl sym_2_6873
+sym_2_6873: la $2, sym_2_6873
+.globl sym_2_6874
+sym_2_6874: la $2, sym_2_6874
+.globl sym_2_6875
+sym_2_6875: la $2, sym_2_6875
+.globl sym_2_6876
+sym_2_6876: la $2, sym_2_6876
+.globl sym_2_6877
+sym_2_6877: la $2, sym_2_6877
+.globl sym_2_6878
+sym_2_6878: la $2, sym_2_6878
+.globl sym_2_6879
+sym_2_6879: la $2, sym_2_6879
+.globl sym_2_6880
+sym_2_6880: la $2, sym_2_6880
+.globl sym_2_6881
+sym_2_6881: la $2, sym_2_6881
+.globl sym_2_6882
+sym_2_6882: la $2, sym_2_6882
+.globl sym_2_6883
+sym_2_6883: la $2, sym_2_6883
+.globl sym_2_6884
+sym_2_6884: la $2, sym_2_6884
+.globl sym_2_6885
+sym_2_6885: la $2, sym_2_6885
+.globl sym_2_6886
+sym_2_6886: la $2, sym_2_6886
+.globl sym_2_6887
+sym_2_6887: la $2, sym_2_6887
+.globl sym_2_6888
+sym_2_6888: la $2, sym_2_6888
+.globl sym_2_6889
+sym_2_6889: la $2, sym_2_6889
+.globl sym_2_6890
+sym_2_6890: la $2, sym_2_6890
+.globl sym_2_6891
+sym_2_6891: la $2, sym_2_6891
+.globl sym_2_6892
+sym_2_6892: la $2, sym_2_6892
+.globl sym_2_6893
+sym_2_6893: la $2, sym_2_6893
+.globl sym_2_6894
+sym_2_6894: la $2, sym_2_6894
+.globl sym_2_6895
+sym_2_6895: la $2, sym_2_6895
+.globl sym_2_6896
+sym_2_6896: la $2, sym_2_6896
+.globl sym_2_6897
+sym_2_6897: la $2, sym_2_6897
+.globl sym_2_6898
+sym_2_6898: la $2, sym_2_6898
+.globl sym_2_6899
+sym_2_6899: la $2, sym_2_6899
+.globl sym_2_6900
+sym_2_6900: la $2, sym_2_6900
+.globl sym_2_6901
+sym_2_6901: la $2, sym_2_6901
+.globl sym_2_6902
+sym_2_6902: la $2, sym_2_6902
+.globl sym_2_6903
+sym_2_6903: la $2, sym_2_6903
+.globl sym_2_6904
+sym_2_6904: la $2, sym_2_6904
+.globl sym_2_6905
+sym_2_6905: la $2, sym_2_6905
+.globl sym_2_6906
+sym_2_6906: la $2, sym_2_6906
+.globl sym_2_6907
+sym_2_6907: la $2, sym_2_6907
+.globl sym_2_6908
+sym_2_6908: la $2, sym_2_6908
+.globl sym_2_6909
+sym_2_6909: la $2, sym_2_6909
+.globl sym_2_6910
+sym_2_6910: la $2, sym_2_6910
+.globl sym_2_6911
+sym_2_6911: la $2, sym_2_6911
+.globl sym_2_6912
+sym_2_6912: la $2, sym_2_6912
+.globl sym_2_6913
+sym_2_6913: la $2, sym_2_6913
+.globl sym_2_6914
+sym_2_6914: la $2, sym_2_6914
+.globl sym_2_6915
+sym_2_6915: la $2, sym_2_6915
+.globl sym_2_6916
+sym_2_6916: la $2, sym_2_6916
+.globl sym_2_6917
+sym_2_6917: la $2, sym_2_6917
+.globl sym_2_6918
+sym_2_6918: la $2, sym_2_6918
+.globl sym_2_6919
+sym_2_6919: la $2, sym_2_6919
+.globl sym_2_6920
+sym_2_6920: la $2, sym_2_6920
+.globl sym_2_6921
+sym_2_6921: la $2, sym_2_6921
+.globl sym_2_6922
+sym_2_6922: la $2, sym_2_6922
+.globl sym_2_6923
+sym_2_6923: la $2, sym_2_6923
+.globl sym_2_6924
+sym_2_6924: la $2, sym_2_6924
+.globl sym_2_6925
+sym_2_6925: la $2, sym_2_6925
+.globl sym_2_6926
+sym_2_6926: la $2, sym_2_6926
+.globl sym_2_6927
+sym_2_6927: la $2, sym_2_6927
+.globl sym_2_6928
+sym_2_6928: la $2, sym_2_6928
+.globl sym_2_6929
+sym_2_6929: la $2, sym_2_6929
+.globl sym_2_6930
+sym_2_6930: la $2, sym_2_6930
+.globl sym_2_6931
+sym_2_6931: la $2, sym_2_6931
+.globl sym_2_6932
+sym_2_6932: la $2, sym_2_6932
+.globl sym_2_6933
+sym_2_6933: la $2, sym_2_6933
+.globl sym_2_6934
+sym_2_6934: la $2, sym_2_6934
+.globl sym_2_6935
+sym_2_6935: la $2, sym_2_6935
+.globl sym_2_6936
+sym_2_6936: la $2, sym_2_6936
+.globl sym_2_6937
+sym_2_6937: la $2, sym_2_6937
+.globl sym_2_6938
+sym_2_6938: la $2, sym_2_6938
+.globl sym_2_6939
+sym_2_6939: la $2, sym_2_6939
+.globl sym_2_6940
+sym_2_6940: la $2, sym_2_6940
+.globl sym_2_6941
+sym_2_6941: la $2, sym_2_6941
+.globl sym_2_6942
+sym_2_6942: la $2, sym_2_6942
+.globl sym_2_6943
+sym_2_6943: la $2, sym_2_6943
+.globl sym_2_6944
+sym_2_6944: la $2, sym_2_6944
+.globl sym_2_6945
+sym_2_6945: la $2, sym_2_6945
+.globl sym_2_6946
+sym_2_6946: la $2, sym_2_6946
+.globl sym_2_6947
+sym_2_6947: la $2, sym_2_6947
+.globl sym_2_6948
+sym_2_6948: la $2, sym_2_6948
+.globl sym_2_6949
+sym_2_6949: la $2, sym_2_6949
+.globl sym_2_6950
+sym_2_6950: la $2, sym_2_6950
+.globl sym_2_6951
+sym_2_6951: la $2, sym_2_6951
+.globl sym_2_6952
+sym_2_6952: la $2, sym_2_6952
+.globl sym_2_6953
+sym_2_6953: la $2, sym_2_6953
+.globl sym_2_6954
+sym_2_6954: la $2, sym_2_6954
+.globl sym_2_6955
+sym_2_6955: la $2, sym_2_6955
+.globl sym_2_6956
+sym_2_6956: la $2, sym_2_6956
+.globl sym_2_6957
+sym_2_6957: la $2, sym_2_6957
+.globl sym_2_6958
+sym_2_6958: la $2, sym_2_6958
+.globl sym_2_6959
+sym_2_6959: la $2, sym_2_6959
+.globl sym_2_6960
+sym_2_6960: la $2, sym_2_6960
+.globl sym_2_6961
+sym_2_6961: la $2, sym_2_6961
+.globl sym_2_6962
+sym_2_6962: la $2, sym_2_6962
+.globl sym_2_6963
+sym_2_6963: la $2, sym_2_6963
+.globl sym_2_6964
+sym_2_6964: la $2, sym_2_6964
+.globl sym_2_6965
+sym_2_6965: la $2, sym_2_6965
+.globl sym_2_6966
+sym_2_6966: la $2, sym_2_6966
+.globl sym_2_6967
+sym_2_6967: la $2, sym_2_6967
+.globl sym_2_6968
+sym_2_6968: la $2, sym_2_6968
+.globl sym_2_6969
+sym_2_6969: la $2, sym_2_6969
+.globl sym_2_6970
+sym_2_6970: la $2, sym_2_6970
+.globl sym_2_6971
+sym_2_6971: la $2, sym_2_6971
+.globl sym_2_6972
+sym_2_6972: la $2, sym_2_6972
+.globl sym_2_6973
+sym_2_6973: la $2, sym_2_6973
+.globl sym_2_6974
+sym_2_6974: la $2, sym_2_6974
+.globl sym_2_6975
+sym_2_6975: la $2, sym_2_6975
+.globl sym_2_6976
+sym_2_6976: la $2, sym_2_6976
+.globl sym_2_6977
+sym_2_6977: la $2, sym_2_6977
+.globl sym_2_6978
+sym_2_6978: la $2, sym_2_6978
+.globl sym_2_6979
+sym_2_6979: la $2, sym_2_6979
+.globl sym_2_6980
+sym_2_6980: la $2, sym_2_6980
+.globl sym_2_6981
+sym_2_6981: la $2, sym_2_6981
+.globl sym_2_6982
+sym_2_6982: la $2, sym_2_6982
+.globl sym_2_6983
+sym_2_6983: la $2, sym_2_6983
+.globl sym_2_6984
+sym_2_6984: la $2, sym_2_6984
+.globl sym_2_6985
+sym_2_6985: la $2, sym_2_6985
+.globl sym_2_6986
+sym_2_6986: la $2, sym_2_6986
+.globl sym_2_6987
+sym_2_6987: la $2, sym_2_6987
+.globl sym_2_6988
+sym_2_6988: la $2, sym_2_6988
+.globl sym_2_6989
+sym_2_6989: la $2, sym_2_6989
+.globl sym_2_6990
+sym_2_6990: la $2, sym_2_6990
+.globl sym_2_6991
+sym_2_6991: la $2, sym_2_6991
+.globl sym_2_6992
+sym_2_6992: la $2, sym_2_6992
+.globl sym_2_6993
+sym_2_6993: la $2, sym_2_6993
+.globl sym_2_6994
+sym_2_6994: la $2, sym_2_6994
+.globl sym_2_6995
+sym_2_6995: la $2, sym_2_6995
+.globl sym_2_6996
+sym_2_6996: la $2, sym_2_6996
+.globl sym_2_6997
+sym_2_6997: la $2, sym_2_6997
+.globl sym_2_6998
+sym_2_6998: la $2, sym_2_6998
+.globl sym_2_6999
+sym_2_6999: la $2, sym_2_6999
+.globl sym_2_7000
+sym_2_7000: la $2, sym_2_7000
+.globl sym_2_7001
+sym_2_7001: la $2, sym_2_7001
+.globl sym_2_7002
+sym_2_7002: la $2, sym_2_7002
+.globl sym_2_7003
+sym_2_7003: la $2, sym_2_7003
+.globl sym_2_7004
+sym_2_7004: la $2, sym_2_7004
+.globl sym_2_7005
+sym_2_7005: la $2, sym_2_7005
+.globl sym_2_7006
+sym_2_7006: la $2, sym_2_7006
+.globl sym_2_7007
+sym_2_7007: la $2, sym_2_7007
+.globl sym_2_7008
+sym_2_7008: la $2, sym_2_7008
+.globl sym_2_7009
+sym_2_7009: la $2, sym_2_7009
+.globl sym_2_7010
+sym_2_7010: la $2, sym_2_7010
+.globl sym_2_7011
+sym_2_7011: la $2, sym_2_7011
+.globl sym_2_7012
+sym_2_7012: la $2, sym_2_7012
+.globl sym_2_7013
+sym_2_7013: la $2, sym_2_7013
+.globl sym_2_7014
+sym_2_7014: la $2, sym_2_7014
+.globl sym_2_7015
+sym_2_7015: la $2, sym_2_7015
+.globl sym_2_7016
+sym_2_7016: la $2, sym_2_7016
+.globl sym_2_7017
+sym_2_7017: la $2, sym_2_7017
+.globl sym_2_7018
+sym_2_7018: la $2, sym_2_7018
+.globl sym_2_7019
+sym_2_7019: la $2, sym_2_7019
+.globl sym_2_7020
+sym_2_7020: la $2, sym_2_7020
+.globl sym_2_7021
+sym_2_7021: la $2, sym_2_7021
+.globl sym_2_7022
+sym_2_7022: la $2, sym_2_7022
+.globl sym_2_7023
+sym_2_7023: la $2, sym_2_7023
+.globl sym_2_7024
+sym_2_7024: la $2, sym_2_7024
+.globl sym_2_7025
+sym_2_7025: la $2, sym_2_7025
+.globl sym_2_7026
+sym_2_7026: la $2, sym_2_7026
+.globl sym_2_7027
+sym_2_7027: la $2, sym_2_7027
+.globl sym_2_7028
+sym_2_7028: la $2, sym_2_7028
+.globl sym_2_7029
+sym_2_7029: la $2, sym_2_7029
+.globl sym_2_7030
+sym_2_7030: la $2, sym_2_7030
+.globl sym_2_7031
+sym_2_7031: la $2, sym_2_7031
+.globl sym_2_7032
+sym_2_7032: la $2, sym_2_7032
+.globl sym_2_7033
+sym_2_7033: la $2, sym_2_7033
+.globl sym_2_7034
+sym_2_7034: la $2, sym_2_7034
+.globl sym_2_7035
+sym_2_7035: la $2, sym_2_7035
+.globl sym_2_7036
+sym_2_7036: la $2, sym_2_7036
+.globl sym_2_7037
+sym_2_7037: la $2, sym_2_7037
+.globl sym_2_7038
+sym_2_7038: la $2, sym_2_7038
+.globl sym_2_7039
+sym_2_7039: la $2, sym_2_7039
+.globl sym_2_7040
+sym_2_7040: la $2, sym_2_7040
+.globl sym_2_7041
+sym_2_7041: la $2, sym_2_7041
+.globl sym_2_7042
+sym_2_7042: la $2, sym_2_7042
+.globl sym_2_7043
+sym_2_7043: la $2, sym_2_7043
+.globl sym_2_7044
+sym_2_7044: la $2, sym_2_7044
+.globl sym_2_7045
+sym_2_7045: la $2, sym_2_7045
+.globl sym_2_7046
+sym_2_7046: la $2, sym_2_7046
+.globl sym_2_7047
+sym_2_7047: la $2, sym_2_7047
+.globl sym_2_7048
+sym_2_7048: la $2, sym_2_7048
+.globl sym_2_7049
+sym_2_7049: la $2, sym_2_7049
+.globl sym_2_7050
+sym_2_7050: la $2, sym_2_7050
+.globl sym_2_7051
+sym_2_7051: la $2, sym_2_7051
+.globl sym_2_7052
+sym_2_7052: la $2, sym_2_7052
+.globl sym_2_7053
+sym_2_7053: la $2, sym_2_7053
+.globl sym_2_7054
+sym_2_7054: la $2, sym_2_7054
+.globl sym_2_7055
+sym_2_7055: la $2, sym_2_7055
+.globl sym_2_7056
+sym_2_7056: la $2, sym_2_7056
+.globl sym_2_7057
+sym_2_7057: la $2, sym_2_7057
+.globl sym_2_7058
+sym_2_7058: la $2, sym_2_7058
+.globl sym_2_7059
+sym_2_7059: la $2, sym_2_7059
+.globl sym_2_7060
+sym_2_7060: la $2, sym_2_7060
+.globl sym_2_7061
+sym_2_7061: la $2, sym_2_7061
+.globl sym_2_7062
+sym_2_7062: la $2, sym_2_7062
+.globl sym_2_7063
+sym_2_7063: la $2, sym_2_7063
+.globl sym_2_7064
+sym_2_7064: la $2, sym_2_7064
+.globl sym_2_7065
+sym_2_7065: la $2, sym_2_7065
+.globl sym_2_7066
+sym_2_7066: la $2, sym_2_7066
+.globl sym_2_7067
+sym_2_7067: la $2, sym_2_7067
+.globl sym_2_7068
+sym_2_7068: la $2, sym_2_7068
+.globl sym_2_7069
+sym_2_7069: la $2, sym_2_7069
+.globl sym_2_7070
+sym_2_7070: la $2, sym_2_7070
+.globl sym_2_7071
+sym_2_7071: la $2, sym_2_7071
+.globl sym_2_7072
+sym_2_7072: la $2, sym_2_7072
+.globl sym_2_7073
+sym_2_7073: la $2, sym_2_7073
+.globl sym_2_7074
+sym_2_7074: la $2, sym_2_7074
+.globl sym_2_7075
+sym_2_7075: la $2, sym_2_7075
+.globl sym_2_7076
+sym_2_7076: la $2, sym_2_7076
+.globl sym_2_7077
+sym_2_7077: la $2, sym_2_7077
+.globl sym_2_7078
+sym_2_7078: la $2, sym_2_7078
+.globl sym_2_7079
+sym_2_7079: la $2, sym_2_7079
+.globl sym_2_7080
+sym_2_7080: la $2, sym_2_7080
+.globl sym_2_7081
+sym_2_7081: la $2, sym_2_7081
+.globl sym_2_7082
+sym_2_7082: la $2, sym_2_7082
+.globl sym_2_7083
+sym_2_7083: la $2, sym_2_7083
+.globl sym_2_7084
+sym_2_7084: la $2, sym_2_7084
+.globl sym_2_7085
+sym_2_7085: la $2, sym_2_7085
+.globl sym_2_7086
+sym_2_7086: la $2, sym_2_7086
+.globl sym_2_7087
+sym_2_7087: la $2, sym_2_7087
+.globl sym_2_7088
+sym_2_7088: la $2, sym_2_7088
+.globl sym_2_7089
+sym_2_7089: la $2, sym_2_7089
+.globl sym_2_7090
+sym_2_7090: la $2, sym_2_7090
+.globl sym_2_7091
+sym_2_7091: la $2, sym_2_7091
+.globl sym_2_7092
+sym_2_7092: la $2, sym_2_7092
+.globl sym_2_7093
+sym_2_7093: la $2, sym_2_7093
+.globl sym_2_7094
+sym_2_7094: la $2, sym_2_7094
+.globl sym_2_7095
+sym_2_7095: la $2, sym_2_7095
+.globl sym_2_7096
+sym_2_7096: la $2, sym_2_7096
+.globl sym_2_7097
+sym_2_7097: la $2, sym_2_7097
+.globl sym_2_7098
+sym_2_7098: la $2, sym_2_7098
+.globl sym_2_7099
+sym_2_7099: la $2, sym_2_7099
+.globl sym_2_7100
+sym_2_7100: la $2, sym_2_7100
+.globl sym_2_7101
+sym_2_7101: la $2, sym_2_7101
+.globl sym_2_7102
+sym_2_7102: la $2, sym_2_7102
+.globl sym_2_7103
+sym_2_7103: la $2, sym_2_7103
+.globl sym_2_7104
+sym_2_7104: la $2, sym_2_7104
+.globl sym_2_7105
+sym_2_7105: la $2, sym_2_7105
+.globl sym_2_7106
+sym_2_7106: la $2, sym_2_7106
+.globl sym_2_7107
+sym_2_7107: la $2, sym_2_7107
+.globl sym_2_7108
+sym_2_7108: la $2, sym_2_7108
+.globl sym_2_7109
+sym_2_7109: la $2, sym_2_7109
+.globl sym_2_7110
+sym_2_7110: la $2, sym_2_7110
+.globl sym_2_7111
+sym_2_7111: la $2, sym_2_7111
+.globl sym_2_7112
+sym_2_7112: la $2, sym_2_7112
+.globl sym_2_7113
+sym_2_7113: la $2, sym_2_7113
+.globl sym_2_7114
+sym_2_7114: la $2, sym_2_7114
+.globl sym_2_7115
+sym_2_7115: la $2, sym_2_7115
+.globl sym_2_7116
+sym_2_7116: la $2, sym_2_7116
+.globl sym_2_7117
+sym_2_7117: la $2, sym_2_7117
+.globl sym_2_7118
+sym_2_7118: la $2, sym_2_7118
+.globl sym_2_7119
+sym_2_7119: la $2, sym_2_7119
+.globl sym_2_7120
+sym_2_7120: la $2, sym_2_7120
+.globl sym_2_7121
+sym_2_7121: la $2, sym_2_7121
+.globl sym_2_7122
+sym_2_7122: la $2, sym_2_7122
+.globl sym_2_7123
+sym_2_7123: la $2, sym_2_7123
+.globl sym_2_7124
+sym_2_7124: la $2, sym_2_7124
+.globl sym_2_7125
+sym_2_7125: la $2, sym_2_7125
+.globl sym_2_7126
+sym_2_7126: la $2, sym_2_7126
+.globl sym_2_7127
+sym_2_7127: la $2, sym_2_7127
+.globl sym_2_7128
+sym_2_7128: la $2, sym_2_7128
+.globl sym_2_7129
+sym_2_7129: la $2, sym_2_7129
+.globl sym_2_7130
+sym_2_7130: la $2, sym_2_7130
+.globl sym_2_7131
+sym_2_7131: la $2, sym_2_7131
+.globl sym_2_7132
+sym_2_7132: la $2, sym_2_7132
+.globl sym_2_7133
+sym_2_7133: la $2, sym_2_7133
+.globl sym_2_7134
+sym_2_7134: la $2, sym_2_7134
+.globl sym_2_7135
+sym_2_7135: la $2, sym_2_7135
+.globl sym_2_7136
+sym_2_7136: la $2, sym_2_7136
+.globl sym_2_7137
+sym_2_7137: la $2, sym_2_7137
+.globl sym_2_7138
+sym_2_7138: la $2, sym_2_7138
+.globl sym_2_7139
+sym_2_7139: la $2, sym_2_7139
+.globl sym_2_7140
+sym_2_7140: la $2, sym_2_7140
+.globl sym_2_7141
+sym_2_7141: la $2, sym_2_7141
+.globl sym_2_7142
+sym_2_7142: la $2, sym_2_7142
+.globl sym_2_7143
+sym_2_7143: la $2, sym_2_7143
+.globl sym_2_7144
+sym_2_7144: la $2, sym_2_7144
+.globl sym_2_7145
+sym_2_7145: la $2, sym_2_7145
+.globl sym_2_7146
+sym_2_7146: la $2, sym_2_7146
+.globl sym_2_7147
+sym_2_7147: la $2, sym_2_7147
+.globl sym_2_7148
+sym_2_7148: la $2, sym_2_7148
+.globl sym_2_7149
+sym_2_7149: la $2, sym_2_7149
+.globl sym_2_7150
+sym_2_7150: la $2, sym_2_7150
+.globl sym_2_7151
+sym_2_7151: la $2, sym_2_7151
+.globl sym_2_7152
+sym_2_7152: la $2, sym_2_7152
+.globl sym_2_7153
+sym_2_7153: la $2, sym_2_7153
+.globl sym_2_7154
+sym_2_7154: la $2, sym_2_7154
+.globl sym_2_7155
+sym_2_7155: la $2, sym_2_7155
+.globl sym_2_7156
+sym_2_7156: la $2, sym_2_7156
+.globl sym_2_7157
+sym_2_7157: la $2, sym_2_7157
+.globl sym_2_7158
+sym_2_7158: la $2, sym_2_7158
+.globl sym_2_7159
+sym_2_7159: la $2, sym_2_7159
+.globl sym_2_7160
+sym_2_7160: la $2, sym_2_7160
+.globl sym_2_7161
+sym_2_7161: la $2, sym_2_7161
+.globl sym_2_7162
+sym_2_7162: la $2, sym_2_7162
+.globl sym_2_7163
+sym_2_7163: la $2, sym_2_7163
+.globl sym_2_7164
+sym_2_7164: la $2, sym_2_7164
+.globl sym_2_7165
+sym_2_7165: la $2, sym_2_7165
+.globl sym_2_7166
+sym_2_7166: la $2, sym_2_7166
+.globl sym_2_7167
+sym_2_7167: la $2, sym_2_7167
+.globl sym_2_7168
+sym_2_7168: la $2, sym_2_7168
+.globl sym_2_7169
+sym_2_7169: la $2, sym_2_7169
+.globl sym_2_7170
+sym_2_7170: la $2, sym_2_7170
+.globl sym_2_7171
+sym_2_7171: la $2, sym_2_7171
+.globl sym_2_7172
+sym_2_7172: la $2, sym_2_7172
+.globl sym_2_7173
+sym_2_7173: la $2, sym_2_7173
+.globl sym_2_7174
+sym_2_7174: la $2, sym_2_7174
+.globl sym_2_7175
+sym_2_7175: la $2, sym_2_7175
+.globl sym_2_7176
+sym_2_7176: la $2, sym_2_7176
+.globl sym_2_7177
+sym_2_7177: la $2, sym_2_7177
+.globl sym_2_7178
+sym_2_7178: la $2, sym_2_7178
+.globl sym_2_7179
+sym_2_7179: la $2, sym_2_7179
+.globl sym_2_7180
+sym_2_7180: la $2, sym_2_7180
+.globl sym_2_7181
+sym_2_7181: la $2, sym_2_7181
+.globl sym_2_7182
+sym_2_7182: la $2, sym_2_7182
+.globl sym_2_7183
+sym_2_7183: la $2, sym_2_7183
+.globl sym_2_7184
+sym_2_7184: la $2, sym_2_7184
+.globl sym_2_7185
+sym_2_7185: la $2, sym_2_7185
+.globl sym_2_7186
+sym_2_7186: la $2, sym_2_7186
+.globl sym_2_7187
+sym_2_7187: la $2, sym_2_7187
+.globl sym_2_7188
+sym_2_7188: la $2, sym_2_7188
+.globl sym_2_7189
+sym_2_7189: la $2, sym_2_7189
+.globl sym_2_7190
+sym_2_7190: la $2, sym_2_7190
+.globl sym_2_7191
+sym_2_7191: la $2, sym_2_7191
+.globl sym_2_7192
+sym_2_7192: la $2, sym_2_7192
+.globl sym_2_7193
+sym_2_7193: la $2, sym_2_7193
+.globl sym_2_7194
+sym_2_7194: la $2, sym_2_7194
+.globl sym_2_7195
+sym_2_7195: la $2, sym_2_7195
+.globl sym_2_7196
+sym_2_7196: la $2, sym_2_7196
+.globl sym_2_7197
+sym_2_7197: la $2, sym_2_7197
+.globl sym_2_7198
+sym_2_7198: la $2, sym_2_7198
+.globl sym_2_7199
+sym_2_7199: la $2, sym_2_7199
+.globl sym_2_7200
+sym_2_7200: la $2, sym_2_7200
+.globl sym_2_7201
+sym_2_7201: la $2, sym_2_7201
+.globl sym_2_7202
+sym_2_7202: la $2, sym_2_7202
+.globl sym_2_7203
+sym_2_7203: la $2, sym_2_7203
+.globl sym_2_7204
+sym_2_7204: la $2, sym_2_7204
+.globl sym_2_7205
+sym_2_7205: la $2, sym_2_7205
+.globl sym_2_7206
+sym_2_7206: la $2, sym_2_7206
+.globl sym_2_7207
+sym_2_7207: la $2, sym_2_7207
+.globl sym_2_7208
+sym_2_7208: la $2, sym_2_7208
+.globl sym_2_7209
+sym_2_7209: la $2, sym_2_7209
+.globl sym_2_7210
+sym_2_7210: la $2, sym_2_7210
+.globl sym_2_7211
+sym_2_7211: la $2, sym_2_7211
+.globl sym_2_7212
+sym_2_7212: la $2, sym_2_7212
+.globl sym_2_7213
+sym_2_7213: la $2, sym_2_7213
+.globl sym_2_7214
+sym_2_7214: la $2, sym_2_7214
+.globl sym_2_7215
+sym_2_7215: la $2, sym_2_7215
+.globl sym_2_7216
+sym_2_7216: la $2, sym_2_7216
+.globl sym_2_7217
+sym_2_7217: la $2, sym_2_7217
+.globl sym_2_7218
+sym_2_7218: la $2, sym_2_7218
+.globl sym_2_7219
+sym_2_7219: la $2, sym_2_7219
+.globl sym_2_7220
+sym_2_7220: la $2, sym_2_7220
+.globl sym_2_7221
+sym_2_7221: la $2, sym_2_7221
+.globl sym_2_7222
+sym_2_7222: la $2, sym_2_7222
+.globl sym_2_7223
+sym_2_7223: la $2, sym_2_7223
+.globl sym_2_7224
+sym_2_7224: la $2, sym_2_7224
+.globl sym_2_7225
+sym_2_7225: la $2, sym_2_7225
+.globl sym_2_7226
+sym_2_7226: la $2, sym_2_7226
+.globl sym_2_7227
+sym_2_7227: la $2, sym_2_7227
+.globl sym_2_7228
+sym_2_7228: la $2, sym_2_7228
+.globl sym_2_7229
+sym_2_7229: la $2, sym_2_7229
+.globl sym_2_7230
+sym_2_7230: la $2, sym_2_7230
+.globl sym_2_7231
+sym_2_7231: la $2, sym_2_7231
+.globl sym_2_7232
+sym_2_7232: la $2, sym_2_7232
+.globl sym_2_7233
+sym_2_7233: la $2, sym_2_7233
+.globl sym_2_7234
+sym_2_7234: la $2, sym_2_7234
+.globl sym_2_7235
+sym_2_7235: la $2, sym_2_7235
+.globl sym_2_7236
+sym_2_7236: la $2, sym_2_7236
+.globl sym_2_7237
+sym_2_7237: la $2, sym_2_7237
+.globl sym_2_7238
+sym_2_7238: la $2, sym_2_7238
+.globl sym_2_7239
+sym_2_7239: la $2, sym_2_7239
+.globl sym_2_7240
+sym_2_7240: la $2, sym_2_7240
+.globl sym_2_7241
+sym_2_7241: la $2, sym_2_7241
+.globl sym_2_7242
+sym_2_7242: la $2, sym_2_7242
+.globl sym_2_7243
+sym_2_7243: la $2, sym_2_7243
+.globl sym_2_7244
+sym_2_7244: la $2, sym_2_7244
+.globl sym_2_7245
+sym_2_7245: la $2, sym_2_7245
+.globl sym_2_7246
+sym_2_7246: la $2, sym_2_7246
+.globl sym_2_7247
+sym_2_7247: la $2, sym_2_7247
+.globl sym_2_7248
+sym_2_7248: la $2, sym_2_7248
+.globl sym_2_7249
+sym_2_7249: la $2, sym_2_7249
+.globl sym_2_7250
+sym_2_7250: la $2, sym_2_7250
+.globl sym_2_7251
+sym_2_7251: la $2, sym_2_7251
+.globl sym_2_7252
+sym_2_7252: la $2, sym_2_7252
+.globl sym_2_7253
+sym_2_7253: la $2, sym_2_7253
+.globl sym_2_7254
+sym_2_7254: la $2, sym_2_7254
+.globl sym_2_7255
+sym_2_7255: la $2, sym_2_7255
+.globl sym_2_7256
+sym_2_7256: la $2, sym_2_7256
+.globl sym_2_7257
+sym_2_7257: la $2, sym_2_7257
+.globl sym_2_7258
+sym_2_7258: la $2, sym_2_7258
+.globl sym_2_7259
+sym_2_7259: la $2, sym_2_7259
+.globl sym_2_7260
+sym_2_7260: la $2, sym_2_7260
+.globl sym_2_7261
+sym_2_7261: la $2, sym_2_7261
+.globl sym_2_7262
+sym_2_7262: la $2, sym_2_7262
+.globl sym_2_7263
+sym_2_7263: la $2, sym_2_7263
+.globl sym_2_7264
+sym_2_7264: la $2, sym_2_7264
+.globl sym_2_7265
+sym_2_7265: la $2, sym_2_7265
+.globl sym_2_7266
+sym_2_7266: la $2, sym_2_7266
+.globl sym_2_7267
+sym_2_7267: la $2, sym_2_7267
+.globl sym_2_7268
+sym_2_7268: la $2, sym_2_7268
+.globl sym_2_7269
+sym_2_7269: la $2, sym_2_7269
+.globl sym_2_7270
+sym_2_7270: la $2, sym_2_7270
+.globl sym_2_7271
+sym_2_7271: la $2, sym_2_7271
+.globl sym_2_7272
+sym_2_7272: la $2, sym_2_7272
+.globl sym_2_7273
+sym_2_7273: la $2, sym_2_7273
+.globl sym_2_7274
+sym_2_7274: la $2, sym_2_7274
+.globl sym_2_7275
+sym_2_7275: la $2, sym_2_7275
+.globl sym_2_7276
+sym_2_7276: la $2, sym_2_7276
+.globl sym_2_7277
+sym_2_7277: la $2, sym_2_7277
+.globl sym_2_7278
+sym_2_7278: la $2, sym_2_7278
+.globl sym_2_7279
+sym_2_7279: la $2, sym_2_7279
+.globl sym_2_7280
+sym_2_7280: la $2, sym_2_7280
+.globl sym_2_7281
+sym_2_7281: la $2, sym_2_7281
+.globl sym_2_7282
+sym_2_7282: la $2, sym_2_7282
+.globl sym_2_7283
+sym_2_7283: la $2, sym_2_7283
+.globl sym_2_7284
+sym_2_7284: la $2, sym_2_7284
+.globl sym_2_7285
+sym_2_7285: la $2, sym_2_7285
+.globl sym_2_7286
+sym_2_7286: la $2, sym_2_7286
+.globl sym_2_7287
+sym_2_7287: la $2, sym_2_7287
+.globl sym_2_7288
+sym_2_7288: la $2, sym_2_7288
+.globl sym_2_7289
+sym_2_7289: la $2, sym_2_7289
+.globl sym_2_7290
+sym_2_7290: la $2, sym_2_7290
+.globl sym_2_7291
+sym_2_7291: la $2, sym_2_7291
+.globl sym_2_7292
+sym_2_7292: la $2, sym_2_7292
+.globl sym_2_7293
+sym_2_7293: la $2, sym_2_7293
+.globl sym_2_7294
+sym_2_7294: la $2, sym_2_7294
+.globl sym_2_7295
+sym_2_7295: la $2, sym_2_7295
+.globl sym_2_7296
+sym_2_7296: la $2, sym_2_7296
+.globl sym_2_7297
+sym_2_7297: la $2, sym_2_7297
+.globl sym_2_7298
+sym_2_7298: la $2, sym_2_7298
+.globl sym_2_7299
+sym_2_7299: la $2, sym_2_7299
+.globl sym_2_7300
+sym_2_7300: la $2, sym_2_7300
+.globl sym_2_7301
+sym_2_7301: la $2, sym_2_7301
+.globl sym_2_7302
+sym_2_7302: la $2, sym_2_7302
+.globl sym_2_7303
+sym_2_7303: la $2, sym_2_7303
+.globl sym_2_7304
+sym_2_7304: la $2, sym_2_7304
+.globl sym_2_7305
+sym_2_7305: la $2, sym_2_7305
+.globl sym_2_7306
+sym_2_7306: la $2, sym_2_7306
+.globl sym_2_7307
+sym_2_7307: la $2, sym_2_7307
+.globl sym_2_7308
+sym_2_7308: la $2, sym_2_7308
+.globl sym_2_7309
+sym_2_7309: la $2, sym_2_7309
+.globl sym_2_7310
+sym_2_7310: la $2, sym_2_7310
+.globl sym_2_7311
+sym_2_7311: la $2, sym_2_7311
+.globl sym_2_7312
+sym_2_7312: la $2, sym_2_7312
+.globl sym_2_7313
+sym_2_7313: la $2, sym_2_7313
+.globl sym_2_7314
+sym_2_7314: la $2, sym_2_7314
+.globl sym_2_7315
+sym_2_7315: la $2, sym_2_7315
+.globl sym_2_7316
+sym_2_7316: la $2, sym_2_7316
+.globl sym_2_7317
+sym_2_7317: la $2, sym_2_7317
+.globl sym_2_7318
+sym_2_7318: la $2, sym_2_7318
+.globl sym_2_7319
+sym_2_7319: la $2, sym_2_7319
+.globl sym_2_7320
+sym_2_7320: la $2, sym_2_7320
+.globl sym_2_7321
+sym_2_7321: la $2, sym_2_7321
+.globl sym_2_7322
+sym_2_7322: la $2, sym_2_7322
+.globl sym_2_7323
+sym_2_7323: la $2, sym_2_7323
+.globl sym_2_7324
+sym_2_7324: la $2, sym_2_7324
+.globl sym_2_7325
+sym_2_7325: la $2, sym_2_7325
+.globl sym_2_7326
+sym_2_7326: la $2, sym_2_7326
+.globl sym_2_7327
+sym_2_7327: la $2, sym_2_7327
+.globl sym_2_7328
+sym_2_7328: la $2, sym_2_7328
+.globl sym_2_7329
+sym_2_7329: la $2, sym_2_7329
+.globl sym_2_7330
+sym_2_7330: la $2, sym_2_7330
+.globl sym_2_7331
+sym_2_7331: la $2, sym_2_7331
+.globl sym_2_7332
+sym_2_7332: la $2, sym_2_7332
+.globl sym_2_7333
+sym_2_7333: la $2, sym_2_7333
+.globl sym_2_7334
+sym_2_7334: la $2, sym_2_7334
+.globl sym_2_7335
+sym_2_7335: la $2, sym_2_7335
+.globl sym_2_7336
+sym_2_7336: la $2, sym_2_7336
+.globl sym_2_7337
+sym_2_7337: la $2, sym_2_7337
+.globl sym_2_7338
+sym_2_7338: la $2, sym_2_7338
+.globl sym_2_7339
+sym_2_7339: la $2, sym_2_7339
+.globl sym_2_7340
+sym_2_7340: la $2, sym_2_7340
+.globl sym_2_7341
+sym_2_7341: la $2, sym_2_7341
+.globl sym_2_7342
+sym_2_7342: la $2, sym_2_7342
+.globl sym_2_7343
+sym_2_7343: la $2, sym_2_7343
+.globl sym_2_7344
+sym_2_7344: la $2, sym_2_7344
+.globl sym_2_7345
+sym_2_7345: la $2, sym_2_7345
+.globl sym_2_7346
+sym_2_7346: la $2, sym_2_7346
+.globl sym_2_7347
+sym_2_7347: la $2, sym_2_7347
+.globl sym_2_7348
+sym_2_7348: la $2, sym_2_7348
+.globl sym_2_7349
+sym_2_7349: la $2, sym_2_7349
+.globl sym_2_7350
+sym_2_7350: la $2, sym_2_7350
+.globl sym_2_7351
+sym_2_7351: la $2, sym_2_7351
+.globl sym_2_7352
+sym_2_7352: la $2, sym_2_7352
+.globl sym_2_7353
+sym_2_7353: la $2, sym_2_7353
+.globl sym_2_7354
+sym_2_7354: la $2, sym_2_7354
+.globl sym_2_7355
+sym_2_7355: la $2, sym_2_7355
+.globl sym_2_7356
+sym_2_7356: la $2, sym_2_7356
+.globl sym_2_7357
+sym_2_7357: la $2, sym_2_7357
+.globl sym_2_7358
+sym_2_7358: la $2, sym_2_7358
+.globl sym_2_7359
+sym_2_7359: la $2, sym_2_7359
+.globl sym_2_7360
+sym_2_7360: la $2, sym_2_7360
+.globl sym_2_7361
+sym_2_7361: la $2, sym_2_7361
+.globl sym_2_7362
+sym_2_7362: la $2, sym_2_7362
+.globl sym_2_7363
+sym_2_7363: la $2, sym_2_7363
+.globl sym_2_7364
+sym_2_7364: la $2, sym_2_7364
+.globl sym_2_7365
+sym_2_7365: la $2, sym_2_7365
+.globl sym_2_7366
+sym_2_7366: la $2, sym_2_7366
+.globl sym_2_7367
+sym_2_7367: la $2, sym_2_7367
+.globl sym_2_7368
+sym_2_7368: la $2, sym_2_7368
+.globl sym_2_7369
+sym_2_7369: la $2, sym_2_7369
+.globl sym_2_7370
+sym_2_7370: la $2, sym_2_7370
+.globl sym_2_7371
+sym_2_7371: la $2, sym_2_7371
+.globl sym_2_7372
+sym_2_7372: la $2, sym_2_7372
+.globl sym_2_7373
+sym_2_7373: la $2, sym_2_7373
+.globl sym_2_7374
+sym_2_7374: la $2, sym_2_7374
+.globl sym_2_7375
+sym_2_7375: la $2, sym_2_7375
+.globl sym_2_7376
+sym_2_7376: la $2, sym_2_7376
+.globl sym_2_7377
+sym_2_7377: la $2, sym_2_7377
+.globl sym_2_7378
+sym_2_7378: la $2, sym_2_7378
+.globl sym_2_7379
+sym_2_7379: la $2, sym_2_7379
+.globl sym_2_7380
+sym_2_7380: la $2, sym_2_7380
+.globl sym_2_7381
+sym_2_7381: la $2, sym_2_7381
+.globl sym_2_7382
+sym_2_7382: la $2, sym_2_7382
+.globl sym_2_7383
+sym_2_7383: la $2, sym_2_7383
+.globl sym_2_7384
+sym_2_7384: la $2, sym_2_7384
+.globl sym_2_7385
+sym_2_7385: la $2, sym_2_7385
+.globl sym_2_7386
+sym_2_7386: la $2, sym_2_7386
+.globl sym_2_7387
+sym_2_7387: la $2, sym_2_7387
+.globl sym_2_7388
+sym_2_7388: la $2, sym_2_7388
+.globl sym_2_7389
+sym_2_7389: la $2, sym_2_7389
+.globl sym_2_7390
+sym_2_7390: la $2, sym_2_7390
+.globl sym_2_7391
+sym_2_7391: la $2, sym_2_7391
+.globl sym_2_7392
+sym_2_7392: la $2, sym_2_7392
+.globl sym_2_7393
+sym_2_7393: la $2, sym_2_7393
+.globl sym_2_7394
+sym_2_7394: la $2, sym_2_7394
+.globl sym_2_7395
+sym_2_7395: la $2, sym_2_7395
+.globl sym_2_7396
+sym_2_7396: la $2, sym_2_7396
+.globl sym_2_7397
+sym_2_7397: la $2, sym_2_7397
+.globl sym_2_7398
+sym_2_7398: la $2, sym_2_7398
+.globl sym_2_7399
+sym_2_7399: la $2, sym_2_7399
+.globl sym_2_7400
+sym_2_7400: la $2, sym_2_7400
+.globl sym_2_7401
+sym_2_7401: la $2, sym_2_7401
+.globl sym_2_7402
+sym_2_7402: la $2, sym_2_7402
+.globl sym_2_7403
+sym_2_7403: la $2, sym_2_7403
+.globl sym_2_7404
+sym_2_7404: la $2, sym_2_7404
+.globl sym_2_7405
+sym_2_7405: la $2, sym_2_7405
+.globl sym_2_7406
+sym_2_7406: la $2, sym_2_7406
+.globl sym_2_7407
+sym_2_7407: la $2, sym_2_7407
+.globl sym_2_7408
+sym_2_7408: la $2, sym_2_7408
+.globl sym_2_7409
+sym_2_7409: la $2, sym_2_7409
+.globl sym_2_7410
+sym_2_7410: la $2, sym_2_7410
+.globl sym_2_7411
+sym_2_7411: la $2, sym_2_7411
+.globl sym_2_7412
+sym_2_7412: la $2, sym_2_7412
+.globl sym_2_7413
+sym_2_7413: la $2, sym_2_7413
+.globl sym_2_7414
+sym_2_7414: la $2, sym_2_7414
+.globl sym_2_7415
+sym_2_7415: la $2, sym_2_7415
+.globl sym_2_7416
+sym_2_7416: la $2, sym_2_7416
+.globl sym_2_7417
+sym_2_7417: la $2, sym_2_7417
+.globl sym_2_7418
+sym_2_7418: la $2, sym_2_7418
+.globl sym_2_7419
+sym_2_7419: la $2, sym_2_7419
+.globl sym_2_7420
+sym_2_7420: la $2, sym_2_7420
+.globl sym_2_7421
+sym_2_7421: la $2, sym_2_7421
+.globl sym_2_7422
+sym_2_7422: la $2, sym_2_7422
+.globl sym_2_7423
+sym_2_7423: la $2, sym_2_7423
+.globl sym_2_7424
+sym_2_7424: la $2, sym_2_7424
+.globl sym_2_7425
+sym_2_7425: la $2, sym_2_7425
+.globl sym_2_7426
+sym_2_7426: la $2, sym_2_7426
+.globl sym_2_7427
+sym_2_7427: la $2, sym_2_7427
+.globl sym_2_7428
+sym_2_7428: la $2, sym_2_7428
+.globl sym_2_7429
+sym_2_7429: la $2, sym_2_7429
+.globl sym_2_7430
+sym_2_7430: la $2, sym_2_7430
+.globl sym_2_7431
+sym_2_7431: la $2, sym_2_7431
+.globl sym_2_7432
+sym_2_7432: la $2, sym_2_7432
+.globl sym_2_7433
+sym_2_7433: la $2, sym_2_7433
+.globl sym_2_7434
+sym_2_7434: la $2, sym_2_7434
+.globl sym_2_7435
+sym_2_7435: la $2, sym_2_7435
+.globl sym_2_7436
+sym_2_7436: la $2, sym_2_7436
+.globl sym_2_7437
+sym_2_7437: la $2, sym_2_7437
+.globl sym_2_7438
+sym_2_7438: la $2, sym_2_7438
+.globl sym_2_7439
+sym_2_7439: la $2, sym_2_7439
+.globl sym_2_7440
+sym_2_7440: la $2, sym_2_7440
+.globl sym_2_7441
+sym_2_7441: la $2, sym_2_7441
+.globl sym_2_7442
+sym_2_7442: la $2, sym_2_7442
+.globl sym_2_7443
+sym_2_7443: la $2, sym_2_7443
+.globl sym_2_7444
+sym_2_7444: la $2, sym_2_7444
+.globl sym_2_7445
+sym_2_7445: la $2, sym_2_7445
+.globl sym_2_7446
+sym_2_7446: la $2, sym_2_7446
+.globl sym_2_7447
+sym_2_7447: la $2, sym_2_7447
+.globl sym_2_7448
+sym_2_7448: la $2, sym_2_7448
+.globl sym_2_7449
+sym_2_7449: la $2, sym_2_7449
+.globl sym_2_7450
+sym_2_7450: la $2, sym_2_7450
+.globl sym_2_7451
+sym_2_7451: la $2, sym_2_7451
+.globl sym_2_7452
+sym_2_7452: la $2, sym_2_7452
+.globl sym_2_7453
+sym_2_7453: la $2, sym_2_7453
+.globl sym_2_7454
+sym_2_7454: la $2, sym_2_7454
+.globl sym_2_7455
+sym_2_7455: la $2, sym_2_7455
+.globl sym_2_7456
+sym_2_7456: la $2, sym_2_7456
+.globl sym_2_7457
+sym_2_7457: la $2, sym_2_7457
+.globl sym_2_7458
+sym_2_7458: la $2, sym_2_7458
+.globl sym_2_7459
+sym_2_7459: la $2, sym_2_7459
+.globl sym_2_7460
+sym_2_7460: la $2, sym_2_7460
+.globl sym_2_7461
+sym_2_7461: la $2, sym_2_7461
+.globl sym_2_7462
+sym_2_7462: la $2, sym_2_7462
+.globl sym_2_7463
+sym_2_7463: la $2, sym_2_7463
+.globl sym_2_7464
+sym_2_7464: la $2, sym_2_7464
+.globl sym_2_7465
+sym_2_7465: la $2, sym_2_7465
+.globl sym_2_7466
+sym_2_7466: la $2, sym_2_7466
+.globl sym_2_7467
+sym_2_7467: la $2, sym_2_7467
+.globl sym_2_7468
+sym_2_7468: la $2, sym_2_7468
+.globl sym_2_7469
+sym_2_7469: la $2, sym_2_7469
+.globl sym_2_7470
+sym_2_7470: la $2, sym_2_7470
+.globl sym_2_7471
+sym_2_7471: la $2, sym_2_7471
+.globl sym_2_7472
+sym_2_7472: la $2, sym_2_7472
+.globl sym_2_7473
+sym_2_7473: la $2, sym_2_7473
+.globl sym_2_7474
+sym_2_7474: la $2, sym_2_7474
+.globl sym_2_7475
+sym_2_7475: la $2, sym_2_7475
+.globl sym_2_7476
+sym_2_7476: la $2, sym_2_7476
+.globl sym_2_7477
+sym_2_7477: la $2, sym_2_7477
+.globl sym_2_7478
+sym_2_7478: la $2, sym_2_7478
+.globl sym_2_7479
+sym_2_7479: la $2, sym_2_7479
+.globl sym_2_7480
+sym_2_7480: la $2, sym_2_7480
+.globl sym_2_7481
+sym_2_7481: la $2, sym_2_7481
+.globl sym_2_7482
+sym_2_7482: la $2, sym_2_7482
+.globl sym_2_7483
+sym_2_7483: la $2, sym_2_7483
+.globl sym_2_7484
+sym_2_7484: la $2, sym_2_7484
+.globl sym_2_7485
+sym_2_7485: la $2, sym_2_7485
+.globl sym_2_7486
+sym_2_7486: la $2, sym_2_7486
+.globl sym_2_7487
+sym_2_7487: la $2, sym_2_7487
+.globl sym_2_7488
+sym_2_7488: la $2, sym_2_7488
+.globl sym_2_7489
+sym_2_7489: la $2, sym_2_7489
+.globl sym_2_7490
+sym_2_7490: la $2, sym_2_7490
+.globl sym_2_7491
+sym_2_7491: la $2, sym_2_7491
+.globl sym_2_7492
+sym_2_7492: la $2, sym_2_7492
+.globl sym_2_7493
+sym_2_7493: la $2, sym_2_7493
+.globl sym_2_7494
+sym_2_7494: la $2, sym_2_7494
+.globl sym_2_7495
+sym_2_7495: la $2, sym_2_7495
+.globl sym_2_7496
+sym_2_7496: la $2, sym_2_7496
+.globl sym_2_7497
+sym_2_7497: la $2, sym_2_7497
+.globl sym_2_7498
+sym_2_7498: la $2, sym_2_7498
+.globl sym_2_7499
+sym_2_7499: la $2, sym_2_7499
+.globl sym_2_7500
+sym_2_7500: la $2, sym_2_7500
+.globl sym_2_7501
+sym_2_7501: la $2, sym_2_7501
+.globl sym_2_7502
+sym_2_7502: la $2, sym_2_7502
+.globl sym_2_7503
+sym_2_7503: la $2, sym_2_7503
+.globl sym_2_7504
+sym_2_7504: la $2, sym_2_7504
+.globl sym_2_7505
+sym_2_7505: la $2, sym_2_7505
+.globl sym_2_7506
+sym_2_7506: la $2, sym_2_7506
+.globl sym_2_7507
+sym_2_7507: la $2, sym_2_7507
+.globl sym_2_7508
+sym_2_7508: la $2, sym_2_7508
+.globl sym_2_7509
+sym_2_7509: la $2, sym_2_7509
+.globl sym_2_7510
+sym_2_7510: la $2, sym_2_7510
+.globl sym_2_7511
+sym_2_7511: la $2, sym_2_7511
+.globl sym_2_7512
+sym_2_7512: la $2, sym_2_7512
+.globl sym_2_7513
+sym_2_7513: la $2, sym_2_7513
+.globl sym_2_7514
+sym_2_7514: la $2, sym_2_7514
+.globl sym_2_7515
+sym_2_7515: la $2, sym_2_7515
+.globl sym_2_7516
+sym_2_7516: la $2, sym_2_7516
+.globl sym_2_7517
+sym_2_7517: la $2, sym_2_7517
+.globl sym_2_7518
+sym_2_7518: la $2, sym_2_7518
+.globl sym_2_7519
+sym_2_7519: la $2, sym_2_7519
+.globl sym_2_7520
+sym_2_7520: la $2, sym_2_7520
+.globl sym_2_7521
+sym_2_7521: la $2, sym_2_7521
+.globl sym_2_7522
+sym_2_7522: la $2, sym_2_7522
+.globl sym_2_7523
+sym_2_7523: la $2, sym_2_7523
+.globl sym_2_7524
+sym_2_7524: la $2, sym_2_7524
+.globl sym_2_7525
+sym_2_7525: la $2, sym_2_7525
+.globl sym_2_7526
+sym_2_7526: la $2, sym_2_7526
+.globl sym_2_7527
+sym_2_7527: la $2, sym_2_7527
+.globl sym_2_7528
+sym_2_7528: la $2, sym_2_7528
+.globl sym_2_7529
+sym_2_7529: la $2, sym_2_7529
+.globl sym_2_7530
+sym_2_7530: la $2, sym_2_7530
+.globl sym_2_7531
+sym_2_7531: la $2, sym_2_7531
+.globl sym_2_7532
+sym_2_7532: la $2, sym_2_7532
+.globl sym_2_7533
+sym_2_7533: la $2, sym_2_7533
+.globl sym_2_7534
+sym_2_7534: la $2, sym_2_7534
+.globl sym_2_7535
+sym_2_7535: la $2, sym_2_7535
+.globl sym_2_7536
+sym_2_7536: la $2, sym_2_7536
+.globl sym_2_7537
+sym_2_7537: la $2, sym_2_7537
+.globl sym_2_7538
+sym_2_7538: la $2, sym_2_7538
+.globl sym_2_7539
+sym_2_7539: la $2, sym_2_7539
+.globl sym_2_7540
+sym_2_7540: la $2, sym_2_7540
+.globl sym_2_7541
+sym_2_7541: la $2, sym_2_7541
+.globl sym_2_7542
+sym_2_7542: la $2, sym_2_7542
+.globl sym_2_7543
+sym_2_7543: la $2, sym_2_7543
+.globl sym_2_7544
+sym_2_7544: la $2, sym_2_7544
+.globl sym_2_7545
+sym_2_7545: la $2, sym_2_7545
+.globl sym_2_7546
+sym_2_7546: la $2, sym_2_7546
+.globl sym_2_7547
+sym_2_7547: la $2, sym_2_7547
+.globl sym_2_7548
+sym_2_7548: la $2, sym_2_7548
+.globl sym_2_7549
+sym_2_7549: la $2, sym_2_7549
+.globl sym_2_7550
+sym_2_7550: la $2, sym_2_7550
+.globl sym_2_7551
+sym_2_7551: la $2, sym_2_7551
+.globl sym_2_7552
+sym_2_7552: la $2, sym_2_7552
+.globl sym_2_7553
+sym_2_7553: la $2, sym_2_7553
+.globl sym_2_7554
+sym_2_7554: la $2, sym_2_7554
+.globl sym_2_7555
+sym_2_7555: la $2, sym_2_7555
+.globl sym_2_7556
+sym_2_7556: la $2, sym_2_7556
+.globl sym_2_7557
+sym_2_7557: la $2, sym_2_7557
+.globl sym_2_7558
+sym_2_7558: la $2, sym_2_7558
+.globl sym_2_7559
+sym_2_7559: la $2, sym_2_7559
+.globl sym_2_7560
+sym_2_7560: la $2, sym_2_7560
+.globl sym_2_7561
+sym_2_7561: la $2, sym_2_7561
+.globl sym_2_7562
+sym_2_7562: la $2, sym_2_7562
+.globl sym_2_7563
+sym_2_7563: la $2, sym_2_7563
+.globl sym_2_7564
+sym_2_7564: la $2, sym_2_7564
+.globl sym_2_7565
+sym_2_7565: la $2, sym_2_7565
+.globl sym_2_7566
+sym_2_7566: la $2, sym_2_7566
+.globl sym_2_7567
+sym_2_7567: la $2, sym_2_7567
+.globl sym_2_7568
+sym_2_7568: la $2, sym_2_7568
+.globl sym_2_7569
+sym_2_7569: la $2, sym_2_7569
+.globl sym_2_7570
+sym_2_7570: la $2, sym_2_7570
+.globl sym_2_7571
+sym_2_7571: la $2, sym_2_7571
+.globl sym_2_7572
+sym_2_7572: la $2, sym_2_7572
+.globl sym_2_7573
+sym_2_7573: la $2, sym_2_7573
+.globl sym_2_7574
+sym_2_7574: la $2, sym_2_7574
+.globl sym_2_7575
+sym_2_7575: la $2, sym_2_7575
+.globl sym_2_7576
+sym_2_7576: la $2, sym_2_7576
+.globl sym_2_7577
+sym_2_7577: la $2, sym_2_7577
+.globl sym_2_7578
+sym_2_7578: la $2, sym_2_7578
+.globl sym_2_7579
+sym_2_7579: la $2, sym_2_7579
+.globl sym_2_7580
+sym_2_7580: la $2, sym_2_7580
+.globl sym_2_7581
+sym_2_7581: la $2, sym_2_7581
+.globl sym_2_7582
+sym_2_7582: la $2, sym_2_7582
+.globl sym_2_7583
+sym_2_7583: la $2, sym_2_7583
+.globl sym_2_7584
+sym_2_7584: la $2, sym_2_7584
+.globl sym_2_7585
+sym_2_7585: la $2, sym_2_7585
+.globl sym_2_7586
+sym_2_7586: la $2, sym_2_7586
+.globl sym_2_7587
+sym_2_7587: la $2, sym_2_7587
+.globl sym_2_7588
+sym_2_7588: la $2, sym_2_7588
+.globl sym_2_7589
+sym_2_7589: la $2, sym_2_7589
+.globl sym_2_7590
+sym_2_7590: la $2, sym_2_7590
+.globl sym_2_7591
+sym_2_7591: la $2, sym_2_7591
+.globl sym_2_7592
+sym_2_7592: la $2, sym_2_7592
+.globl sym_2_7593
+sym_2_7593: la $2, sym_2_7593
+.globl sym_2_7594
+sym_2_7594: la $2, sym_2_7594
+.globl sym_2_7595
+sym_2_7595: la $2, sym_2_7595
+.globl sym_2_7596
+sym_2_7596: la $2, sym_2_7596
+.globl sym_2_7597
+sym_2_7597: la $2, sym_2_7597
+.globl sym_2_7598
+sym_2_7598: la $2, sym_2_7598
+.globl sym_2_7599
+sym_2_7599: la $2, sym_2_7599
+.globl sym_2_7600
+sym_2_7600: la $2, sym_2_7600
+.globl sym_2_7601
+sym_2_7601: la $2, sym_2_7601
+.globl sym_2_7602
+sym_2_7602: la $2, sym_2_7602
+.globl sym_2_7603
+sym_2_7603: la $2, sym_2_7603
+.globl sym_2_7604
+sym_2_7604: la $2, sym_2_7604
+.globl sym_2_7605
+sym_2_7605: la $2, sym_2_7605
+.globl sym_2_7606
+sym_2_7606: la $2, sym_2_7606
+.globl sym_2_7607
+sym_2_7607: la $2, sym_2_7607
+.globl sym_2_7608
+sym_2_7608: la $2, sym_2_7608
+.globl sym_2_7609
+sym_2_7609: la $2, sym_2_7609
+.globl sym_2_7610
+sym_2_7610: la $2, sym_2_7610
+.globl sym_2_7611
+sym_2_7611: la $2, sym_2_7611
+.globl sym_2_7612
+sym_2_7612: la $2, sym_2_7612
+.globl sym_2_7613
+sym_2_7613: la $2, sym_2_7613
+.globl sym_2_7614
+sym_2_7614: la $2, sym_2_7614
+.globl sym_2_7615
+sym_2_7615: la $2, sym_2_7615
+.globl sym_2_7616
+sym_2_7616: la $2, sym_2_7616
+.globl sym_2_7617
+sym_2_7617: la $2, sym_2_7617
+.globl sym_2_7618
+sym_2_7618: la $2, sym_2_7618
+.globl sym_2_7619
+sym_2_7619: la $2, sym_2_7619
+.globl sym_2_7620
+sym_2_7620: la $2, sym_2_7620
+.globl sym_2_7621
+sym_2_7621: la $2, sym_2_7621
+.globl sym_2_7622
+sym_2_7622: la $2, sym_2_7622
+.globl sym_2_7623
+sym_2_7623: la $2, sym_2_7623
+.globl sym_2_7624
+sym_2_7624: la $2, sym_2_7624
+.globl sym_2_7625
+sym_2_7625: la $2, sym_2_7625
+.globl sym_2_7626
+sym_2_7626: la $2, sym_2_7626
+.globl sym_2_7627
+sym_2_7627: la $2, sym_2_7627
+.globl sym_2_7628
+sym_2_7628: la $2, sym_2_7628
+.globl sym_2_7629
+sym_2_7629: la $2, sym_2_7629
+.globl sym_2_7630
+sym_2_7630: la $2, sym_2_7630
+.globl sym_2_7631
+sym_2_7631: la $2, sym_2_7631
+.globl sym_2_7632
+sym_2_7632: la $2, sym_2_7632
+.globl sym_2_7633
+sym_2_7633: la $2, sym_2_7633
+.globl sym_2_7634
+sym_2_7634: la $2, sym_2_7634
+.globl sym_2_7635
+sym_2_7635: la $2, sym_2_7635
+.globl sym_2_7636
+sym_2_7636: la $2, sym_2_7636
+.globl sym_2_7637
+sym_2_7637: la $2, sym_2_7637
+.globl sym_2_7638
+sym_2_7638: la $2, sym_2_7638
+.globl sym_2_7639
+sym_2_7639: la $2, sym_2_7639
+.globl sym_2_7640
+sym_2_7640: la $2, sym_2_7640
+.globl sym_2_7641
+sym_2_7641: la $2, sym_2_7641
+.globl sym_2_7642
+sym_2_7642: la $2, sym_2_7642
+.globl sym_2_7643
+sym_2_7643: la $2, sym_2_7643
+.globl sym_2_7644
+sym_2_7644: la $2, sym_2_7644
+.globl sym_2_7645
+sym_2_7645: la $2, sym_2_7645
+.globl sym_2_7646
+sym_2_7646: la $2, sym_2_7646
+.globl sym_2_7647
+sym_2_7647: la $2, sym_2_7647
+.globl sym_2_7648
+sym_2_7648: la $2, sym_2_7648
+.globl sym_2_7649
+sym_2_7649: la $2, sym_2_7649
+.globl sym_2_7650
+sym_2_7650: la $2, sym_2_7650
+.globl sym_2_7651
+sym_2_7651: la $2, sym_2_7651
+.globl sym_2_7652
+sym_2_7652: la $2, sym_2_7652
+.globl sym_2_7653
+sym_2_7653: la $2, sym_2_7653
+.globl sym_2_7654
+sym_2_7654: la $2, sym_2_7654
+.globl sym_2_7655
+sym_2_7655: la $2, sym_2_7655
+.globl sym_2_7656
+sym_2_7656: la $2, sym_2_7656
+.globl sym_2_7657
+sym_2_7657: la $2, sym_2_7657
+.globl sym_2_7658
+sym_2_7658: la $2, sym_2_7658
+.globl sym_2_7659
+sym_2_7659: la $2, sym_2_7659
+.globl sym_2_7660
+sym_2_7660: la $2, sym_2_7660
+.globl sym_2_7661
+sym_2_7661: la $2, sym_2_7661
+.globl sym_2_7662
+sym_2_7662: la $2, sym_2_7662
+.globl sym_2_7663
+sym_2_7663: la $2, sym_2_7663
+.globl sym_2_7664
+sym_2_7664: la $2, sym_2_7664
+.globl sym_2_7665
+sym_2_7665: la $2, sym_2_7665
+.globl sym_2_7666
+sym_2_7666: la $2, sym_2_7666
+.globl sym_2_7667
+sym_2_7667: la $2, sym_2_7667
+.globl sym_2_7668
+sym_2_7668: la $2, sym_2_7668
+.globl sym_2_7669
+sym_2_7669: la $2, sym_2_7669
+.globl sym_2_7670
+sym_2_7670: la $2, sym_2_7670
+.globl sym_2_7671
+sym_2_7671: la $2, sym_2_7671
+.globl sym_2_7672
+sym_2_7672: la $2, sym_2_7672
+.globl sym_2_7673
+sym_2_7673: la $2, sym_2_7673
+.globl sym_2_7674
+sym_2_7674: la $2, sym_2_7674
+.globl sym_2_7675
+sym_2_7675: la $2, sym_2_7675
+.globl sym_2_7676
+sym_2_7676: la $2, sym_2_7676
+.globl sym_2_7677
+sym_2_7677: la $2, sym_2_7677
+.globl sym_2_7678
+sym_2_7678: la $2, sym_2_7678
+.globl sym_2_7679
+sym_2_7679: la $2, sym_2_7679
+.globl sym_2_7680
+sym_2_7680: la $2, sym_2_7680
+.globl sym_2_7681
+sym_2_7681: la $2, sym_2_7681
+.globl sym_2_7682
+sym_2_7682: la $2, sym_2_7682
+.globl sym_2_7683
+sym_2_7683: la $2, sym_2_7683
+.globl sym_2_7684
+sym_2_7684: la $2, sym_2_7684
+.globl sym_2_7685
+sym_2_7685: la $2, sym_2_7685
+.globl sym_2_7686
+sym_2_7686: la $2, sym_2_7686
+.globl sym_2_7687
+sym_2_7687: la $2, sym_2_7687
+.globl sym_2_7688
+sym_2_7688: la $2, sym_2_7688
+.globl sym_2_7689
+sym_2_7689: la $2, sym_2_7689
+.globl sym_2_7690
+sym_2_7690: la $2, sym_2_7690
+.globl sym_2_7691
+sym_2_7691: la $2, sym_2_7691
+.globl sym_2_7692
+sym_2_7692: la $2, sym_2_7692
+.globl sym_2_7693
+sym_2_7693: la $2, sym_2_7693
+.globl sym_2_7694
+sym_2_7694: la $2, sym_2_7694
+.globl sym_2_7695
+sym_2_7695: la $2, sym_2_7695
+.globl sym_2_7696
+sym_2_7696: la $2, sym_2_7696
+.globl sym_2_7697
+sym_2_7697: la $2, sym_2_7697
+.globl sym_2_7698
+sym_2_7698: la $2, sym_2_7698
+.globl sym_2_7699
+sym_2_7699: la $2, sym_2_7699
+.globl sym_2_7700
+sym_2_7700: la $2, sym_2_7700
+.globl sym_2_7701
+sym_2_7701: la $2, sym_2_7701
+.globl sym_2_7702
+sym_2_7702: la $2, sym_2_7702
+.globl sym_2_7703
+sym_2_7703: la $2, sym_2_7703
+.globl sym_2_7704
+sym_2_7704: la $2, sym_2_7704
+.globl sym_2_7705
+sym_2_7705: la $2, sym_2_7705
+.globl sym_2_7706
+sym_2_7706: la $2, sym_2_7706
+.globl sym_2_7707
+sym_2_7707: la $2, sym_2_7707
+.globl sym_2_7708
+sym_2_7708: la $2, sym_2_7708
+.globl sym_2_7709
+sym_2_7709: la $2, sym_2_7709
+.globl sym_2_7710
+sym_2_7710: la $2, sym_2_7710
+.globl sym_2_7711
+sym_2_7711: la $2, sym_2_7711
+.globl sym_2_7712
+sym_2_7712: la $2, sym_2_7712
+.globl sym_2_7713
+sym_2_7713: la $2, sym_2_7713
+.globl sym_2_7714
+sym_2_7714: la $2, sym_2_7714
+.globl sym_2_7715
+sym_2_7715: la $2, sym_2_7715
+.globl sym_2_7716
+sym_2_7716: la $2, sym_2_7716
+.globl sym_2_7717
+sym_2_7717: la $2, sym_2_7717
+.globl sym_2_7718
+sym_2_7718: la $2, sym_2_7718
+.globl sym_2_7719
+sym_2_7719: la $2, sym_2_7719
+.globl sym_2_7720
+sym_2_7720: la $2, sym_2_7720
+.globl sym_2_7721
+sym_2_7721: la $2, sym_2_7721
+.globl sym_2_7722
+sym_2_7722: la $2, sym_2_7722
+.globl sym_2_7723
+sym_2_7723: la $2, sym_2_7723
+.globl sym_2_7724
+sym_2_7724: la $2, sym_2_7724
+.globl sym_2_7725
+sym_2_7725: la $2, sym_2_7725
+.globl sym_2_7726
+sym_2_7726: la $2, sym_2_7726
+.globl sym_2_7727
+sym_2_7727: la $2, sym_2_7727
+.globl sym_2_7728
+sym_2_7728: la $2, sym_2_7728
+.globl sym_2_7729
+sym_2_7729: la $2, sym_2_7729
+.globl sym_2_7730
+sym_2_7730: la $2, sym_2_7730
+.globl sym_2_7731
+sym_2_7731: la $2, sym_2_7731
+.globl sym_2_7732
+sym_2_7732: la $2, sym_2_7732
+.globl sym_2_7733
+sym_2_7733: la $2, sym_2_7733
+.globl sym_2_7734
+sym_2_7734: la $2, sym_2_7734
+.globl sym_2_7735
+sym_2_7735: la $2, sym_2_7735
+.globl sym_2_7736
+sym_2_7736: la $2, sym_2_7736
+.globl sym_2_7737
+sym_2_7737: la $2, sym_2_7737
+.globl sym_2_7738
+sym_2_7738: la $2, sym_2_7738
+.globl sym_2_7739
+sym_2_7739: la $2, sym_2_7739
+.globl sym_2_7740
+sym_2_7740: la $2, sym_2_7740
+.globl sym_2_7741
+sym_2_7741: la $2, sym_2_7741
+.globl sym_2_7742
+sym_2_7742: la $2, sym_2_7742
+.globl sym_2_7743
+sym_2_7743: la $2, sym_2_7743
+.globl sym_2_7744
+sym_2_7744: la $2, sym_2_7744
+.globl sym_2_7745
+sym_2_7745: la $2, sym_2_7745
+.globl sym_2_7746
+sym_2_7746: la $2, sym_2_7746
+.globl sym_2_7747
+sym_2_7747: la $2, sym_2_7747
+.globl sym_2_7748
+sym_2_7748: la $2, sym_2_7748
+.globl sym_2_7749
+sym_2_7749: la $2, sym_2_7749
+.globl sym_2_7750
+sym_2_7750: la $2, sym_2_7750
+.globl sym_2_7751
+sym_2_7751: la $2, sym_2_7751
+.globl sym_2_7752
+sym_2_7752: la $2, sym_2_7752
+.globl sym_2_7753
+sym_2_7753: la $2, sym_2_7753
+.globl sym_2_7754
+sym_2_7754: la $2, sym_2_7754
+.globl sym_2_7755
+sym_2_7755: la $2, sym_2_7755
+.globl sym_2_7756
+sym_2_7756: la $2, sym_2_7756
+.globl sym_2_7757
+sym_2_7757: la $2, sym_2_7757
+.globl sym_2_7758
+sym_2_7758: la $2, sym_2_7758
+.globl sym_2_7759
+sym_2_7759: la $2, sym_2_7759
+.globl sym_2_7760
+sym_2_7760: la $2, sym_2_7760
+.globl sym_2_7761
+sym_2_7761: la $2, sym_2_7761
+.globl sym_2_7762
+sym_2_7762: la $2, sym_2_7762
+.globl sym_2_7763
+sym_2_7763: la $2, sym_2_7763
+.globl sym_2_7764
+sym_2_7764: la $2, sym_2_7764
+.globl sym_2_7765
+sym_2_7765: la $2, sym_2_7765
+.globl sym_2_7766
+sym_2_7766: la $2, sym_2_7766
+.globl sym_2_7767
+sym_2_7767: la $2, sym_2_7767
+.globl sym_2_7768
+sym_2_7768: la $2, sym_2_7768
+.globl sym_2_7769
+sym_2_7769: la $2, sym_2_7769
+.globl sym_2_7770
+sym_2_7770: la $2, sym_2_7770
+.globl sym_2_7771
+sym_2_7771: la $2, sym_2_7771
+.globl sym_2_7772
+sym_2_7772: la $2, sym_2_7772
+.globl sym_2_7773
+sym_2_7773: la $2, sym_2_7773
+.globl sym_2_7774
+sym_2_7774: la $2, sym_2_7774
+.globl sym_2_7775
+sym_2_7775: la $2, sym_2_7775
+.globl sym_2_7776
+sym_2_7776: la $2, sym_2_7776
+.globl sym_2_7777
+sym_2_7777: la $2, sym_2_7777
+.globl sym_2_7778
+sym_2_7778: la $2, sym_2_7778
+.globl sym_2_7779
+sym_2_7779: la $2, sym_2_7779
+.globl sym_2_7780
+sym_2_7780: la $2, sym_2_7780
+.globl sym_2_7781
+sym_2_7781: la $2, sym_2_7781
+.globl sym_2_7782
+sym_2_7782: la $2, sym_2_7782
+.globl sym_2_7783
+sym_2_7783: la $2, sym_2_7783
+.globl sym_2_7784
+sym_2_7784: la $2, sym_2_7784
+.globl sym_2_7785
+sym_2_7785: la $2, sym_2_7785
+.globl sym_2_7786
+sym_2_7786: la $2, sym_2_7786
+.globl sym_2_7787
+sym_2_7787: la $2, sym_2_7787
+.globl sym_2_7788
+sym_2_7788: la $2, sym_2_7788
+.globl sym_2_7789
+sym_2_7789: la $2, sym_2_7789
+.globl sym_2_7790
+sym_2_7790: la $2, sym_2_7790
+.globl sym_2_7791
+sym_2_7791: la $2, sym_2_7791
+.globl sym_2_7792
+sym_2_7792: la $2, sym_2_7792
+.globl sym_2_7793
+sym_2_7793: la $2, sym_2_7793
+.globl sym_2_7794
+sym_2_7794: la $2, sym_2_7794
+.globl sym_2_7795
+sym_2_7795: la $2, sym_2_7795
+.globl sym_2_7796
+sym_2_7796: la $2, sym_2_7796
+.globl sym_2_7797
+sym_2_7797: la $2, sym_2_7797
+.globl sym_2_7798
+sym_2_7798: la $2, sym_2_7798
+.globl sym_2_7799
+sym_2_7799: la $2, sym_2_7799
+.globl sym_2_7800
+sym_2_7800: la $2, sym_2_7800
+.globl sym_2_7801
+sym_2_7801: la $2, sym_2_7801
+.globl sym_2_7802
+sym_2_7802: la $2, sym_2_7802
+.globl sym_2_7803
+sym_2_7803: la $2, sym_2_7803
+.globl sym_2_7804
+sym_2_7804: la $2, sym_2_7804
+.globl sym_2_7805
+sym_2_7805: la $2, sym_2_7805
+.globl sym_2_7806
+sym_2_7806: la $2, sym_2_7806
+.globl sym_2_7807
+sym_2_7807: la $2, sym_2_7807
+.globl sym_2_7808
+sym_2_7808: la $2, sym_2_7808
+.globl sym_2_7809
+sym_2_7809: la $2, sym_2_7809
+.globl sym_2_7810
+sym_2_7810: la $2, sym_2_7810
+.globl sym_2_7811
+sym_2_7811: la $2, sym_2_7811
+.globl sym_2_7812
+sym_2_7812: la $2, sym_2_7812
+.globl sym_2_7813
+sym_2_7813: la $2, sym_2_7813
+.globl sym_2_7814
+sym_2_7814: la $2, sym_2_7814
+.globl sym_2_7815
+sym_2_7815: la $2, sym_2_7815
+.globl sym_2_7816
+sym_2_7816: la $2, sym_2_7816
+.globl sym_2_7817
+sym_2_7817: la $2, sym_2_7817
+.globl sym_2_7818
+sym_2_7818: la $2, sym_2_7818
+.globl sym_2_7819
+sym_2_7819: la $2, sym_2_7819
+.globl sym_2_7820
+sym_2_7820: la $2, sym_2_7820
+.globl sym_2_7821
+sym_2_7821: la $2, sym_2_7821
+.globl sym_2_7822
+sym_2_7822: la $2, sym_2_7822
+.globl sym_2_7823
+sym_2_7823: la $2, sym_2_7823
+.globl sym_2_7824
+sym_2_7824: la $2, sym_2_7824
+.globl sym_2_7825
+sym_2_7825: la $2, sym_2_7825
+.globl sym_2_7826
+sym_2_7826: la $2, sym_2_7826
+.globl sym_2_7827
+sym_2_7827: la $2, sym_2_7827
+.globl sym_2_7828
+sym_2_7828: la $2, sym_2_7828
+.globl sym_2_7829
+sym_2_7829: la $2, sym_2_7829
+.globl sym_2_7830
+sym_2_7830: la $2, sym_2_7830
+.globl sym_2_7831
+sym_2_7831: la $2, sym_2_7831
+.globl sym_2_7832
+sym_2_7832: la $2, sym_2_7832
+.globl sym_2_7833
+sym_2_7833: la $2, sym_2_7833
+.globl sym_2_7834
+sym_2_7834: la $2, sym_2_7834
+.globl sym_2_7835
+sym_2_7835: la $2, sym_2_7835
+.globl sym_2_7836
+sym_2_7836: la $2, sym_2_7836
+.globl sym_2_7837
+sym_2_7837: la $2, sym_2_7837
+.globl sym_2_7838
+sym_2_7838: la $2, sym_2_7838
+.globl sym_2_7839
+sym_2_7839: la $2, sym_2_7839
+.globl sym_2_7840
+sym_2_7840: la $2, sym_2_7840
+.globl sym_2_7841
+sym_2_7841: la $2, sym_2_7841
+.globl sym_2_7842
+sym_2_7842: la $2, sym_2_7842
+.globl sym_2_7843
+sym_2_7843: la $2, sym_2_7843
+.globl sym_2_7844
+sym_2_7844: la $2, sym_2_7844
+.globl sym_2_7845
+sym_2_7845: la $2, sym_2_7845
+.globl sym_2_7846
+sym_2_7846: la $2, sym_2_7846
+.globl sym_2_7847
+sym_2_7847: la $2, sym_2_7847
+.globl sym_2_7848
+sym_2_7848: la $2, sym_2_7848
+.globl sym_2_7849
+sym_2_7849: la $2, sym_2_7849
+.globl sym_2_7850
+sym_2_7850: la $2, sym_2_7850
+.globl sym_2_7851
+sym_2_7851: la $2, sym_2_7851
+.globl sym_2_7852
+sym_2_7852: la $2, sym_2_7852
+.globl sym_2_7853
+sym_2_7853: la $2, sym_2_7853
+.globl sym_2_7854
+sym_2_7854: la $2, sym_2_7854
+.globl sym_2_7855
+sym_2_7855: la $2, sym_2_7855
+.globl sym_2_7856
+sym_2_7856: la $2, sym_2_7856
+.globl sym_2_7857
+sym_2_7857: la $2, sym_2_7857
+.globl sym_2_7858
+sym_2_7858: la $2, sym_2_7858
+.globl sym_2_7859
+sym_2_7859: la $2, sym_2_7859
+.globl sym_2_7860
+sym_2_7860: la $2, sym_2_7860
+.globl sym_2_7861
+sym_2_7861: la $2, sym_2_7861
+.globl sym_2_7862
+sym_2_7862: la $2, sym_2_7862
+.globl sym_2_7863
+sym_2_7863: la $2, sym_2_7863
+.globl sym_2_7864
+sym_2_7864: la $2, sym_2_7864
+.globl sym_2_7865
+sym_2_7865: la $2, sym_2_7865
+.globl sym_2_7866
+sym_2_7866: la $2, sym_2_7866
+.globl sym_2_7867
+sym_2_7867: la $2, sym_2_7867
+.globl sym_2_7868
+sym_2_7868: la $2, sym_2_7868
+.globl sym_2_7869
+sym_2_7869: la $2, sym_2_7869
+.globl sym_2_7870
+sym_2_7870: la $2, sym_2_7870
+.globl sym_2_7871
+sym_2_7871: la $2, sym_2_7871
+.globl sym_2_7872
+sym_2_7872: la $2, sym_2_7872
+.globl sym_2_7873
+sym_2_7873: la $2, sym_2_7873
+.globl sym_2_7874
+sym_2_7874: la $2, sym_2_7874
+.globl sym_2_7875
+sym_2_7875: la $2, sym_2_7875
+.globl sym_2_7876
+sym_2_7876: la $2, sym_2_7876
+.globl sym_2_7877
+sym_2_7877: la $2, sym_2_7877
+.globl sym_2_7878
+sym_2_7878: la $2, sym_2_7878
+.globl sym_2_7879
+sym_2_7879: la $2, sym_2_7879
+.globl sym_2_7880
+sym_2_7880: la $2, sym_2_7880
+.globl sym_2_7881
+sym_2_7881: la $2, sym_2_7881
+.globl sym_2_7882
+sym_2_7882: la $2, sym_2_7882
+.globl sym_2_7883
+sym_2_7883: la $2, sym_2_7883
+.globl sym_2_7884
+sym_2_7884: la $2, sym_2_7884
+.globl sym_2_7885
+sym_2_7885: la $2, sym_2_7885
+.globl sym_2_7886
+sym_2_7886: la $2, sym_2_7886
+.globl sym_2_7887
+sym_2_7887: la $2, sym_2_7887
+.globl sym_2_7888
+sym_2_7888: la $2, sym_2_7888
+.globl sym_2_7889
+sym_2_7889: la $2, sym_2_7889
+.globl sym_2_7890
+sym_2_7890: la $2, sym_2_7890
+.globl sym_2_7891
+sym_2_7891: la $2, sym_2_7891
+.globl sym_2_7892
+sym_2_7892: la $2, sym_2_7892
+.globl sym_2_7893
+sym_2_7893: la $2, sym_2_7893
+.globl sym_2_7894
+sym_2_7894: la $2, sym_2_7894
+.globl sym_2_7895
+sym_2_7895: la $2, sym_2_7895
+.globl sym_2_7896
+sym_2_7896: la $2, sym_2_7896
+.globl sym_2_7897
+sym_2_7897: la $2, sym_2_7897
+.globl sym_2_7898
+sym_2_7898: la $2, sym_2_7898
+.globl sym_2_7899
+sym_2_7899: la $2, sym_2_7899
+.globl sym_2_7900
+sym_2_7900: la $2, sym_2_7900
+.globl sym_2_7901
+sym_2_7901: la $2, sym_2_7901
+.globl sym_2_7902
+sym_2_7902: la $2, sym_2_7902
+.globl sym_2_7903
+sym_2_7903: la $2, sym_2_7903
+.globl sym_2_7904
+sym_2_7904: la $2, sym_2_7904
+.globl sym_2_7905
+sym_2_7905: la $2, sym_2_7905
+.globl sym_2_7906
+sym_2_7906: la $2, sym_2_7906
+.globl sym_2_7907
+sym_2_7907: la $2, sym_2_7907
+.globl sym_2_7908
+sym_2_7908: la $2, sym_2_7908
+.globl sym_2_7909
+sym_2_7909: la $2, sym_2_7909
+.globl sym_2_7910
+sym_2_7910: la $2, sym_2_7910
+.globl sym_2_7911
+sym_2_7911: la $2, sym_2_7911
+.globl sym_2_7912
+sym_2_7912: la $2, sym_2_7912
+.globl sym_2_7913
+sym_2_7913: la $2, sym_2_7913
+.globl sym_2_7914
+sym_2_7914: la $2, sym_2_7914
+.globl sym_2_7915
+sym_2_7915: la $2, sym_2_7915
+.globl sym_2_7916
+sym_2_7916: la $2, sym_2_7916
+.globl sym_2_7917
+sym_2_7917: la $2, sym_2_7917
+.globl sym_2_7918
+sym_2_7918: la $2, sym_2_7918
+.globl sym_2_7919
+sym_2_7919: la $2, sym_2_7919
+.globl sym_2_7920
+sym_2_7920: la $2, sym_2_7920
+.globl sym_2_7921
+sym_2_7921: la $2, sym_2_7921
+.globl sym_2_7922
+sym_2_7922: la $2, sym_2_7922
+.globl sym_2_7923
+sym_2_7923: la $2, sym_2_7923
+.globl sym_2_7924
+sym_2_7924: la $2, sym_2_7924
+.globl sym_2_7925
+sym_2_7925: la $2, sym_2_7925
+.globl sym_2_7926
+sym_2_7926: la $2, sym_2_7926
+.globl sym_2_7927
+sym_2_7927: la $2, sym_2_7927
+.globl sym_2_7928
+sym_2_7928: la $2, sym_2_7928
+.globl sym_2_7929
+sym_2_7929: la $2, sym_2_7929
+.globl sym_2_7930
+sym_2_7930: la $2, sym_2_7930
+.globl sym_2_7931
+sym_2_7931: la $2, sym_2_7931
+.globl sym_2_7932
+sym_2_7932: la $2, sym_2_7932
+.globl sym_2_7933
+sym_2_7933: la $2, sym_2_7933
+.globl sym_2_7934
+sym_2_7934: la $2, sym_2_7934
+.globl sym_2_7935
+sym_2_7935: la $2, sym_2_7935
+.globl sym_2_7936
+sym_2_7936: la $2, sym_2_7936
+.globl sym_2_7937
+sym_2_7937: la $2, sym_2_7937
+.globl sym_2_7938
+sym_2_7938: la $2, sym_2_7938
+.globl sym_2_7939
+sym_2_7939: la $2, sym_2_7939
+.globl sym_2_7940
+sym_2_7940: la $2, sym_2_7940
+.globl sym_2_7941
+sym_2_7941: la $2, sym_2_7941
+.globl sym_2_7942
+sym_2_7942: la $2, sym_2_7942
+.globl sym_2_7943
+sym_2_7943: la $2, sym_2_7943
+.globl sym_2_7944
+sym_2_7944: la $2, sym_2_7944
+.globl sym_2_7945
+sym_2_7945: la $2, sym_2_7945
+.globl sym_2_7946
+sym_2_7946: la $2, sym_2_7946
+.globl sym_2_7947
+sym_2_7947: la $2, sym_2_7947
+.globl sym_2_7948
+sym_2_7948: la $2, sym_2_7948
+.globl sym_2_7949
+sym_2_7949: la $2, sym_2_7949
+.globl sym_2_7950
+sym_2_7950: la $2, sym_2_7950
+.globl sym_2_7951
+sym_2_7951: la $2, sym_2_7951
+.globl sym_2_7952
+sym_2_7952: la $2, sym_2_7952
+.globl sym_2_7953
+sym_2_7953: la $2, sym_2_7953
+.globl sym_2_7954
+sym_2_7954: la $2, sym_2_7954
+.globl sym_2_7955
+sym_2_7955: la $2, sym_2_7955
+.globl sym_2_7956
+sym_2_7956: la $2, sym_2_7956
+.globl sym_2_7957
+sym_2_7957: la $2, sym_2_7957
+.globl sym_2_7958
+sym_2_7958: la $2, sym_2_7958
+.globl sym_2_7959
+sym_2_7959: la $2, sym_2_7959
+.globl sym_2_7960
+sym_2_7960: la $2, sym_2_7960
+.globl sym_2_7961
+sym_2_7961: la $2, sym_2_7961
+.globl sym_2_7962
+sym_2_7962: la $2, sym_2_7962
+.globl sym_2_7963
+sym_2_7963: la $2, sym_2_7963
+.globl sym_2_7964
+sym_2_7964: la $2, sym_2_7964
+.globl sym_2_7965
+sym_2_7965: la $2, sym_2_7965
+.globl sym_2_7966
+sym_2_7966: la $2, sym_2_7966
+.globl sym_2_7967
+sym_2_7967: la $2, sym_2_7967
+.globl sym_2_7968
+sym_2_7968: la $2, sym_2_7968
+.globl sym_2_7969
+sym_2_7969: la $2, sym_2_7969
+.globl sym_2_7970
+sym_2_7970: la $2, sym_2_7970
+.globl sym_2_7971
+sym_2_7971: la $2, sym_2_7971
+.globl sym_2_7972
+sym_2_7972: la $2, sym_2_7972
+.globl sym_2_7973
+sym_2_7973: la $2, sym_2_7973
+.globl sym_2_7974
+sym_2_7974: la $2, sym_2_7974
+.globl sym_2_7975
+sym_2_7975: la $2, sym_2_7975
+.globl sym_2_7976
+sym_2_7976: la $2, sym_2_7976
+.globl sym_2_7977
+sym_2_7977: la $2, sym_2_7977
+.globl sym_2_7978
+sym_2_7978: la $2, sym_2_7978
+.globl sym_2_7979
+sym_2_7979: la $2, sym_2_7979
+.globl sym_2_7980
+sym_2_7980: la $2, sym_2_7980
+.globl sym_2_7981
+sym_2_7981: la $2, sym_2_7981
+.globl sym_2_7982
+sym_2_7982: la $2, sym_2_7982
+.globl sym_2_7983
+sym_2_7983: la $2, sym_2_7983
+.globl sym_2_7984
+sym_2_7984: la $2, sym_2_7984
+.globl sym_2_7985
+sym_2_7985: la $2, sym_2_7985
+.globl sym_2_7986
+sym_2_7986: la $2, sym_2_7986
+.globl sym_2_7987
+sym_2_7987: la $2, sym_2_7987
+.globl sym_2_7988
+sym_2_7988: la $2, sym_2_7988
+.globl sym_2_7989
+sym_2_7989: la $2, sym_2_7989
+.globl sym_2_7990
+sym_2_7990: la $2, sym_2_7990
+.globl sym_2_7991
+sym_2_7991: la $2, sym_2_7991
+.globl sym_2_7992
+sym_2_7992: la $2, sym_2_7992
+.globl sym_2_7993
+sym_2_7993: la $2, sym_2_7993
+.globl sym_2_7994
+sym_2_7994: la $2, sym_2_7994
+.globl sym_2_7995
+sym_2_7995: la $2, sym_2_7995
+.globl sym_2_7996
+sym_2_7996: la $2, sym_2_7996
+.globl sym_2_7997
+sym_2_7997: la $2, sym_2_7997
+.globl sym_2_7998
+sym_2_7998: la $2, sym_2_7998
+.globl sym_2_7999
+sym_2_7999: la $2, sym_2_7999
+.globl sym_2_8000
+sym_2_8000: la $2, sym_2_8000
+.globl sym_2_8001
+sym_2_8001: la $2, sym_2_8001
+.globl sym_2_8002
+sym_2_8002: la $2, sym_2_8002
+.globl sym_2_8003
+sym_2_8003: la $2, sym_2_8003
+.globl sym_2_8004
+sym_2_8004: la $2, sym_2_8004
+.globl sym_2_8005
+sym_2_8005: la $2, sym_2_8005
+.globl sym_2_8006
+sym_2_8006: la $2, sym_2_8006
+.globl sym_2_8007
+sym_2_8007: la $2, sym_2_8007
+.globl sym_2_8008
+sym_2_8008: la $2, sym_2_8008
+.globl sym_2_8009
+sym_2_8009: la $2, sym_2_8009
+.globl sym_2_8010
+sym_2_8010: la $2, sym_2_8010
+.globl sym_2_8011
+sym_2_8011: la $2, sym_2_8011
+.globl sym_2_8012
+sym_2_8012: la $2, sym_2_8012
+.globl sym_2_8013
+sym_2_8013: la $2, sym_2_8013
+.globl sym_2_8014
+sym_2_8014: la $2, sym_2_8014
+.globl sym_2_8015
+sym_2_8015: la $2, sym_2_8015
+.globl sym_2_8016
+sym_2_8016: la $2, sym_2_8016
+.globl sym_2_8017
+sym_2_8017: la $2, sym_2_8017
+.globl sym_2_8018
+sym_2_8018: la $2, sym_2_8018
+.globl sym_2_8019
+sym_2_8019: la $2, sym_2_8019
+.globl sym_2_8020
+sym_2_8020: la $2, sym_2_8020
+.globl sym_2_8021
+sym_2_8021: la $2, sym_2_8021
+.globl sym_2_8022
+sym_2_8022: la $2, sym_2_8022
+.globl sym_2_8023
+sym_2_8023: la $2, sym_2_8023
+.globl sym_2_8024
+sym_2_8024: la $2, sym_2_8024
+.globl sym_2_8025
+sym_2_8025: la $2, sym_2_8025
+.globl sym_2_8026
+sym_2_8026: la $2, sym_2_8026
+.globl sym_2_8027
+sym_2_8027: la $2, sym_2_8027
+.globl sym_2_8028
+sym_2_8028: la $2, sym_2_8028
+.globl sym_2_8029
+sym_2_8029: la $2, sym_2_8029
+.globl sym_2_8030
+sym_2_8030: la $2, sym_2_8030
+.globl sym_2_8031
+sym_2_8031: la $2, sym_2_8031
+.globl sym_2_8032
+sym_2_8032: la $2, sym_2_8032
+.globl sym_2_8033
+sym_2_8033: la $2, sym_2_8033
+.globl sym_2_8034
+sym_2_8034: la $2, sym_2_8034
+.globl sym_2_8035
+sym_2_8035: la $2, sym_2_8035
+.globl sym_2_8036
+sym_2_8036: la $2, sym_2_8036
+.globl sym_2_8037
+sym_2_8037: la $2, sym_2_8037
+.globl sym_2_8038
+sym_2_8038: la $2, sym_2_8038
+.globl sym_2_8039
+sym_2_8039: la $2, sym_2_8039
+.globl sym_2_8040
+sym_2_8040: la $2, sym_2_8040
+.globl sym_2_8041
+sym_2_8041: la $2, sym_2_8041
+.globl sym_2_8042
+sym_2_8042: la $2, sym_2_8042
+.globl sym_2_8043
+sym_2_8043: la $2, sym_2_8043
+.globl sym_2_8044
+sym_2_8044: la $2, sym_2_8044
+.globl sym_2_8045
+sym_2_8045: la $2, sym_2_8045
+.globl sym_2_8046
+sym_2_8046: la $2, sym_2_8046
+.globl sym_2_8047
+sym_2_8047: la $2, sym_2_8047
+.globl sym_2_8048
+sym_2_8048: la $2, sym_2_8048
+.globl sym_2_8049
+sym_2_8049: la $2, sym_2_8049
+.globl sym_2_8050
+sym_2_8050: la $2, sym_2_8050
+.globl sym_2_8051
+sym_2_8051: la $2, sym_2_8051
+.globl sym_2_8052
+sym_2_8052: la $2, sym_2_8052
+.globl sym_2_8053
+sym_2_8053: la $2, sym_2_8053
+.globl sym_2_8054
+sym_2_8054: la $2, sym_2_8054
+.globl sym_2_8055
+sym_2_8055: la $2, sym_2_8055
+.globl sym_2_8056
+sym_2_8056: la $2, sym_2_8056
+.globl sym_2_8057
+sym_2_8057: la $2, sym_2_8057
+.globl sym_2_8058
+sym_2_8058: la $2, sym_2_8058
+.globl sym_2_8059
+sym_2_8059: la $2, sym_2_8059
+.globl sym_2_8060
+sym_2_8060: la $2, sym_2_8060
+.globl sym_2_8061
+sym_2_8061: la $2, sym_2_8061
+.globl sym_2_8062
+sym_2_8062: la $2, sym_2_8062
+.globl sym_2_8063
+sym_2_8063: la $2, sym_2_8063
+.globl sym_2_8064
+sym_2_8064: la $2, sym_2_8064
+.globl sym_2_8065
+sym_2_8065: la $2, sym_2_8065
+.globl sym_2_8066
+sym_2_8066: la $2, sym_2_8066
+.globl sym_2_8067
+sym_2_8067: la $2, sym_2_8067
+.globl sym_2_8068
+sym_2_8068: la $2, sym_2_8068
+.globl sym_2_8069
+sym_2_8069: la $2, sym_2_8069
+.globl sym_2_8070
+sym_2_8070: la $2, sym_2_8070
+.globl sym_2_8071
+sym_2_8071: la $2, sym_2_8071
+.globl sym_2_8072
+sym_2_8072: la $2, sym_2_8072
+.globl sym_2_8073
+sym_2_8073: la $2, sym_2_8073
+.globl sym_2_8074
+sym_2_8074: la $2, sym_2_8074
+.globl sym_2_8075
+sym_2_8075: la $2, sym_2_8075
+.globl sym_2_8076
+sym_2_8076: la $2, sym_2_8076
+.globl sym_2_8077
+sym_2_8077: la $2, sym_2_8077
+.globl sym_2_8078
+sym_2_8078: la $2, sym_2_8078
+.globl sym_2_8079
+sym_2_8079: la $2, sym_2_8079
+.globl sym_2_8080
+sym_2_8080: la $2, sym_2_8080
+.globl sym_2_8081
+sym_2_8081: la $2, sym_2_8081
+.globl sym_2_8082
+sym_2_8082: la $2, sym_2_8082
+.globl sym_2_8083
+sym_2_8083: la $2, sym_2_8083
+.globl sym_2_8084
+sym_2_8084: la $2, sym_2_8084
+.globl sym_2_8085
+sym_2_8085: la $2, sym_2_8085
+.globl sym_2_8086
+sym_2_8086: la $2, sym_2_8086
+.globl sym_2_8087
+sym_2_8087: la $2, sym_2_8087
+.globl sym_2_8088
+sym_2_8088: la $2, sym_2_8088
+.globl sym_2_8089
+sym_2_8089: la $2, sym_2_8089
+.globl sym_2_8090
+sym_2_8090: la $2, sym_2_8090
+.globl sym_2_8091
+sym_2_8091: la $2, sym_2_8091
+.globl sym_2_8092
+sym_2_8092: la $2, sym_2_8092
+.globl sym_2_8093
+sym_2_8093: la $2, sym_2_8093
+.globl sym_2_8094
+sym_2_8094: la $2, sym_2_8094
+.globl sym_2_8095
+sym_2_8095: la $2, sym_2_8095
+.globl sym_2_8096
+sym_2_8096: la $2, sym_2_8096
+.globl sym_2_8097
+sym_2_8097: la $2, sym_2_8097
+.globl sym_2_8098
+sym_2_8098: la $2, sym_2_8098
+.globl sym_2_8099
+sym_2_8099: la $2, sym_2_8099
+.globl sym_2_8100
+sym_2_8100: la $2, sym_2_8100
+.globl sym_2_8101
+sym_2_8101: la $2, sym_2_8101
+.globl sym_2_8102
+sym_2_8102: la $2, sym_2_8102
+.globl sym_2_8103
+sym_2_8103: la $2, sym_2_8103
+.globl sym_2_8104
+sym_2_8104: la $2, sym_2_8104
+.globl sym_2_8105
+sym_2_8105: la $2, sym_2_8105
+.globl sym_2_8106
+sym_2_8106: la $2, sym_2_8106
+.globl sym_2_8107
+sym_2_8107: la $2, sym_2_8107
+.globl sym_2_8108
+sym_2_8108: la $2, sym_2_8108
+.globl sym_2_8109
+sym_2_8109: la $2, sym_2_8109
+.globl sym_2_8110
+sym_2_8110: la $2, sym_2_8110
+.globl sym_2_8111
+sym_2_8111: la $2, sym_2_8111
+.globl sym_2_8112
+sym_2_8112: la $2, sym_2_8112
+.globl sym_2_8113
+sym_2_8113: la $2, sym_2_8113
+.globl sym_2_8114
+sym_2_8114: la $2, sym_2_8114
+.globl sym_2_8115
+sym_2_8115: la $2, sym_2_8115
+.globl sym_2_8116
+sym_2_8116: la $2, sym_2_8116
+.globl sym_2_8117
+sym_2_8117: la $2, sym_2_8117
+.globl sym_2_8118
+sym_2_8118: la $2, sym_2_8118
+.globl sym_2_8119
+sym_2_8119: la $2, sym_2_8119
+.globl sym_2_8120
+sym_2_8120: la $2, sym_2_8120
+.globl sym_2_8121
+sym_2_8121: la $2, sym_2_8121
+.globl sym_2_8122
+sym_2_8122: la $2, sym_2_8122
+.globl sym_2_8123
+sym_2_8123: la $2, sym_2_8123
+.globl sym_2_8124
+sym_2_8124: la $2, sym_2_8124
+.globl sym_2_8125
+sym_2_8125: la $2, sym_2_8125
+.globl sym_2_8126
+sym_2_8126: la $2, sym_2_8126
+.globl sym_2_8127
+sym_2_8127: la $2, sym_2_8127
+.globl sym_2_8128
+sym_2_8128: la $2, sym_2_8128
+.globl sym_2_8129
+sym_2_8129: la $2, sym_2_8129
+.globl sym_2_8130
+sym_2_8130: la $2, sym_2_8130
+.globl sym_2_8131
+sym_2_8131: la $2, sym_2_8131
+.globl sym_2_8132
+sym_2_8132: la $2, sym_2_8132
+.globl sym_2_8133
+sym_2_8133: la $2, sym_2_8133
+.globl sym_2_8134
+sym_2_8134: la $2, sym_2_8134
+.globl sym_2_8135
+sym_2_8135: la $2, sym_2_8135
+.globl sym_2_8136
+sym_2_8136: la $2, sym_2_8136
+.globl sym_2_8137
+sym_2_8137: la $2, sym_2_8137
+.globl sym_2_8138
+sym_2_8138: la $2, sym_2_8138
+.globl sym_2_8139
+sym_2_8139: la $2, sym_2_8139
+.globl sym_2_8140
+sym_2_8140: la $2, sym_2_8140
+.globl sym_2_8141
+sym_2_8141: la $2, sym_2_8141
+.globl sym_2_8142
+sym_2_8142: la $2, sym_2_8142
+.globl sym_2_8143
+sym_2_8143: la $2, sym_2_8143
+.globl sym_2_8144
+sym_2_8144: la $2, sym_2_8144
+.globl sym_2_8145
+sym_2_8145: la $2, sym_2_8145
+.globl sym_2_8146
+sym_2_8146: la $2, sym_2_8146
+.globl sym_2_8147
+sym_2_8147: la $2, sym_2_8147
+.globl sym_2_8148
+sym_2_8148: la $2, sym_2_8148
+.globl sym_2_8149
+sym_2_8149: la $2, sym_2_8149
+.globl sym_2_8150
+sym_2_8150: la $2, sym_2_8150
+.globl sym_2_8151
+sym_2_8151: la $2, sym_2_8151
+.globl sym_2_8152
+sym_2_8152: la $2, sym_2_8152
+.globl sym_2_8153
+sym_2_8153: la $2, sym_2_8153
+.globl sym_2_8154
+sym_2_8154: la $2, sym_2_8154
+.globl sym_2_8155
+sym_2_8155: la $2, sym_2_8155
+.globl sym_2_8156
+sym_2_8156: la $2, sym_2_8156
+.globl sym_2_8157
+sym_2_8157: la $2, sym_2_8157
+.globl sym_2_8158
+sym_2_8158: la $2, sym_2_8158
+.globl sym_2_8159
+sym_2_8159: la $2, sym_2_8159
+.globl sym_2_8160
+sym_2_8160: la $2, sym_2_8160
+.globl sym_2_8161
+sym_2_8161: la $2, sym_2_8161
+.globl sym_2_8162
+sym_2_8162: la $2, sym_2_8162
+.globl sym_2_8163
+sym_2_8163: la $2, sym_2_8163
+.globl sym_2_8164
+sym_2_8164: la $2, sym_2_8164
+.globl sym_2_8165
+sym_2_8165: la $2, sym_2_8165
+.globl sym_2_8166
+sym_2_8166: la $2, sym_2_8166
+.globl sym_2_8167
+sym_2_8167: la $2, sym_2_8167
+.globl sym_2_8168
+sym_2_8168: la $2, sym_2_8168
+.globl sym_2_8169
+sym_2_8169: la $2, sym_2_8169
+.globl sym_2_8170
+sym_2_8170: la $2, sym_2_8170
+.globl sym_2_8171
+sym_2_8171: la $2, sym_2_8171
+.globl sym_2_8172
+sym_2_8172: la $2, sym_2_8172
+.globl sym_2_8173
+sym_2_8173: la $2, sym_2_8173
+.globl sym_2_8174
+sym_2_8174: la $2, sym_2_8174
+.globl sym_2_8175
+sym_2_8175: la $2, sym_2_8175
+.globl sym_2_8176
+sym_2_8176: la $2, sym_2_8176
+.globl sym_2_8177
+sym_2_8177: la $2, sym_2_8177
+.globl sym_2_8178
+sym_2_8178: la $2, sym_2_8178
+.globl sym_2_8179
+sym_2_8179: la $2, sym_2_8179
+.globl sym_2_8180
+sym_2_8180: la $2, sym_2_8180
+.globl sym_2_8181
+sym_2_8181: la $2, sym_2_8181
+.globl sym_2_8182
+sym_2_8182: la $2, sym_2_8182
+.globl sym_2_8183
+sym_2_8183: la $2, sym_2_8183
+.globl sym_2_8184
+sym_2_8184: la $2, sym_2_8184
+.globl sym_2_8185
+sym_2_8185: la $2, sym_2_8185
+.globl sym_2_8186
+sym_2_8186: la $2, sym_2_8186
+.globl sym_2_8187
+sym_2_8187: la $2, sym_2_8187
+.globl sym_2_8188
+sym_2_8188: la $2, sym_2_8188
+.globl sym_2_8189
+sym_2_8189: la $2, sym_2_8189
+.globl sym_2_8190
+sym_2_8190: la $2, sym_2_8190
+.globl sym_2_8191
+sym_2_8191: la $2, sym_2_8191
+.globl sym_2_8192
+sym_2_8192: la $2, sym_2_8192
+.hidden __init_array_end
+.hidden __init_array_start
+sym_3_1:
+la $2, __init_array_start
+la $2, __init_array_end
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-no-shared-1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-no-shared-1.s
new file mode 100644
index 0000000..a2eee84
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-no-shared-1.s
@@ -0,0 +1,29 @@
+	.macro  one_sym count
+	.globl  sym_1_\count
+sym_1_\count:
+        la      $2, sym_1_\count
+	.endm
+
+	
+	.text
+	.globl	func1
+	.ent	func1
+func1:
+	.frame	$sp,0,$31
+	.set noreorder
+	.cpload	$25
+	.set reorder
+	.cprestore 8
+	.set noreorder
+
+	.irp    thou,0,1,2,3,4,5,6,7,8
+	.irp    hund,0,1,2,3,4,5,6,7,8,9
+	.irp    tens,0,1,2,3,4,5,6,7,8,9
+	.irp    ones,0,1,2,3,4,5,6,7,8,9
+	one_sym \thou\hund\tens\ones
+	.endr
+	.endr
+	.endr
+	.endr
+
+	.end	func1
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-no-shared-2.s b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-no-shared-2.s
new file mode 100644
index 0000000..1de7a14
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-no-shared-2.s
@@ -0,0 +1,27 @@
+	.macro  one_sym count
+	.globl  sym_2_\count
+sym_2_\count:
+        la      $2, sym_2_\count
+	.endm
+
+	.text
+	.ent	func2
+func2:
+	.frame	$sp,0,$31
+	.set noreorder
+	.cpload	$25
+	.set reorder
+	.cprestore 8
+	.set noreorder
+
+	.irp    thou,0,1,2,3,4,5,6,7,8
+	.irp    hund,0,1,2,3,4,5,6,7,8,9
+	.irp    tens,0,1,2,3,4,5,6,7,8,9
+	.irp    ones,0,1,2,3,4,5,6,7,8,9
+	one_sym \thou\hund\tens\ones
+	.endr
+	.endr
+	.endr
+	.endr
+
+	.end	func2
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-no-shared.d b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-no-shared.d
new file mode 100644
index 0000000..6a539dc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/multi-got-no-shared.d
@@ -0,0 +1,18 @@
+#name: MIPS multi-got-no-shared
+#as: -EB -32 -KPIC -mno-shared
+#source: multi-got-no-shared-1.s
+#source: multi-got-no-shared-2.s
+#ld: -melf32btsmip --entry func1
+#objdump: -D -j .text --prefix-addresses --show-raw-insn
+
+.*: +file format.*
+
+Disassembly of section \.text:
+004000b0 <[^>]*> 3c1c0043 	lui	gp,0x43
+004000b4 <[^>]*> 279c9a00 	addiu	gp,gp,-26112
+004000b8 <[^>]*> afbc0008 	sw	gp,8\(sp\)
+#...
+00408d60 <[^>]*> 3c1c0044 	lui	gp,0x44
+00408d64 <[^>]*> 279cb348 	addiu	gp,gp,-19640
+00408d68 <[^>]*> afbc0008 	sw	gp,8\(sp\)
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1-n32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1-n32.d
new file mode 100644
index 0000000..a28b22e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1-n32.d
@@ -0,0 +1,25 @@
+#as: -mabi=n32 -EB
+#source: no-shared-1-o32.s
+#ld: -melf32btsmipn32 -T no-shared-1.ld
+#objdump: -dr -j.text -j.data -j.got
+
+.*
+
+
+Disassembly of section \.text:
+
+00050000 <__start>:
+   50000:	3c020007 	lui	v0,0x7
+   50004:	24428000 	addiu	v0,v0,-32768
+   50008:	8f828018 	lw	v0,-32744\(gp\)
+   5000c:	8f828018 	lw	v0,-32744\(gp\)
+#...
+Disassembly of section \.data:
+
+00060000 <\.data>:
+   60000:	00068000 	.*
+#...
+Disassembly of section \.got:
+
+00060010 <_GLOBAL_OFFSET_TABLE_>:
+   60010:	00000000 80000000 00068000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1-n64.d b/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1-n64.d
new file mode 100644
index 0000000..ea74ebb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1-n64.d
@@ -0,0 +1,26 @@
+#as: -mabi=64 -EB
+#ld: -melf64btsmip -T no-shared-1.ld
+#objdump: -dr -j.text -j.data -j.got
+
+.*
+
+
+Disassembly of section \.text:
+
+0000000000050000 <__start>:
+   50000:	3c020007 	lui	v0,0x7
+   50004:	64428000 	daddiu	v0,v0,-32768
+   50008:	df828020 	ld	v0,-32736\(gp\)
+   5000c:	df828020 	ld	v0,-32736\(gp\)
+#...
+Disassembly of section \.data:
+
+0000000000060000 <\.data>:
+   60000:	00000000 	.*
+   60004:	00068000 	.*
+#...
+Disassembly of section \.got:
+
+0000000000060010 <_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
+   60018:	80000000 00000000 00000000 00068000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1-n64.s b/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1-n64.s
new file mode 100644
index 0000000..8eedf12
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1-n64.s
@@ -0,0 +1,13 @@
+	.abicalls
+	.text
+	.globl	__start
+	.ent	__start
+__start:
+	lui	$2,%hi(__gnu_local_gp)
+	daddiu	$2,$2,%lo(__gnu_local_gp)
+	ld	$2,%got(__gnu_local_gp)($gp)
+	ld	$2,%call16(__gnu_local_gp)($gp)
+	.end	__start
+
+	.data
+	.8byte	__gnu_local_gp
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1-o32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1-o32.d
new file mode 100644
index 0000000..b67737f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1-o32.d
@@ -0,0 +1,24 @@
+#as: -mabi=32 -EB
+#ld: -melf32btsmip -T no-shared-1.ld
+#objdump: -dr -j.text -j.data -j.got
+
+.*
+
+
+Disassembly of section \.text:
+
+00050000 <__start>:
+   50000:	3c020007 	lui	v0,0x7
+   50004:	24428000 	addiu	v0,v0,-32768
+   50008:	8f828018 	lw	v0,-32744\(gp\)
+   5000c:	8f828018 	lw	v0,-32744\(gp\)
+#...
+Disassembly of section \.data:
+
+00060000 <\.data>:
+   60000:	00068000 	.*
+#...
+Disassembly of section \.got:
+
+00060010 <_GLOBAL_OFFSET_TABLE_>:
+   60010:	00000000 80000000 00068000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1-o32.s b/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1-o32.s
new file mode 100644
index 0000000..f00fc4b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1-o32.s
@@ -0,0 +1,13 @@
+	.abicalls
+	.text
+	.globl	__start
+	.ent	__start
+__start:
+	lui	$2,%hi(__gnu_local_gp)
+	addiu	$2,$2,%lo(__gnu_local_gp)
+	lw	$2,%got(__gnu_local_gp)($gp)
+	lw	$2,%call16(__gnu_local_gp)($gp)
+	.end	__start
+
+	.data
+	.4byte	__gnu_local_gp
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1.ld
new file mode 100644
index 0000000..06d28a6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/no-shared-1.ld
@@ -0,0 +1,11 @@
+SECTIONS
+{
+  . = 0x50000;
+  .text : { *(.text) }
+  .MIPS.stubs : { *(.MIPS.stubs) }
+
+  . = 0x60000;
+  .data : { *(.data) }
+  _gp = ALIGN (16) + 0x7ff0;
+  .got : { *(.got) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-rel.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-rel.dd
new file mode 100644
index 0000000..4d15a58
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-rel.dd
@@ -0,0 +1,46 @@
+
+.*
+
+Disassembly of section \.text:
+
+00000000 <f1>:
+   0:	3c1c0000 	lui	gp,0x0
+			0: R_MIPS_HI16	_gp_disp
+   4:	279c0000 	addiu	gp,gp,0
+			4: R_MIPS_LO16	_gp_disp
+   8:	0399e021 	addu	gp,gp,t9
+   c:	0c000000 	jal	0 .*
+			c: R_MIPS_26	f3
+  10:	00000000 	nop
+  14:	03e00008 	jr	ra
+  18:	00000000 	nop
+
+0000001c <f2>:
+  1c:	3c1c0000 	lui	gp,0x0
+			1c: R_MIPS_HI16	_gp_disp
+  20:	279c0000 	addiu	gp,gp,0
+			20: R_MIPS_LO16	_gp_disp
+  24:	0399e021 	addu	gp,gp,t9
+  28:	03e00008 	jr	ra
+  2c:	00000000 	nop
+
+00000030 <f3>:
+  30:	f000 6a00 	li	v0,0
+			30: R_MIPS16_HI16	_gp_disp
+  34:	f000 0b00 	la	v1,34 .*
+			34: R_MIPS16_LO16	_gp_disp
+  38:	f400 3240 	sll	v0,16
+  3c:	e269      	addu	v0,v1
+  3e:	6500      	nop
+
+00000040 <__start>:
+  40:	0c000000 	jal	0 .*
+			40: R_MIPS_26	f1
+  44:	00000000 	nop
+  48:	0c000000 	jal	0 .*
+			48: R_MIPS_26	f2
+  4c:	00000000 	nop
+  50:	0c000000 	jal	0 .*
+			50: R_MIPS_26	f3
+  54:	00000000 	nop
+	...
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-rel.nd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-rel.nd
new file mode 100644
index 0000000..c5f0b51
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-rel.nd
@@ -0,0 +1,5 @@
+#...
+.*: 00000030    14 FUNC    GLOBAL DEFAULT \[MIPS16\] .* f3
+.*: 00000040    24 FUNC    GLOBAL DEFAULT .* __start
+.*: 0000001c    20 FUNC    GLOBAL DEFAULT \[MIPS PIC\] .* f2
+.*: 00000000    28 FUNC    GLOBAL DEFAULT \[MIPS PIC\] .* f1
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1.dd
new file mode 100644
index 0000000..9d5b1db
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1.dd
@@ -0,0 +1,46 @@
+
+.*
+
+Disassembly of section \.text:
+
+00041000 <\.pic\.f2>:
+   41000:	3c190004 	lui	t9,0x4
+   41004:	0801040f 	j	4103c <f2>
+   41008:	2739103c 	addiu	t9,t9,4156
+	\.\.\.
+
+00041018 <\.pic\.f1>:
+   41018:	3c190004 	lui	t9,0x4
+   4101c:	27391020 	addiu	t9,t9,4128
+
+00041020 <f1>:
+   41020:	3c1c0002 	lui	gp,0x2
+   41024:	279c6fe0 	addiu	gp,gp,28640
+   41028:	0399e021 	addu	gp,gp,t9
+   4102c:	74010414 	jalx	41050 <f3>
+   41030:	00000000 	nop
+   41034:	03e00008 	jr	ra
+   41038:	00000000 	nop
+
+0004103c <f2>:
+   4103c:	3c1c0002 	lui	gp,0x2
+   41040:	279c6fc4 	addiu	gp,gp,28612
+   41044:	0399e021 	addu	gp,gp,t9
+   41048:	03e00008 	jr	ra
+   4104c:	00000000 	nop
+
+00041050 <f3>:
+   41050:	f000 6a02 	li	v0,2
+   41054:	f7ad 0b0c 	la	v1,48000 .*
+   41058:	f400 3240 	sll	v0,16
+   4105c:	e269      	addu	v0,v1
+   4105e:	6500      	nop
+
+00041060 <__start>:
+   41060:	0c010406 	jal	41018 <\.pic\.f1>
+   41064:	00000000 	nop
+   41068:	0c010400 	jal	41000 <\.pic\.f2>
+   4106c:	00000000 	nop
+   41070:	74010414 	jalx	41050 <f3>
+   41074:	00000000 	nop
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1.ld
new file mode 100644
index 0000000..3aa140e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1.ld
@@ -0,0 +1,9 @@
+SECTIONS
+{
+  . = 0x40000;
+  .reginfo : { *(.reginfo) }
+  .pdr : { *(.pdr) }
+  . = 0x41000;
+  .text : { *(.text) }
+  _gp = 0x68000;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1.nd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1.nd
new file mode 100644
index 0000000..506685a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1.nd
@@ -0,0 +1,9 @@
+#...
+.*: 00041018     8 FUNC    LOCAL  DEFAULT .* .pic.f1
+.*: 00041000    16 FUNC    LOCAL  DEFAULT .* .pic.f2
+.*: 00000000     0 OBJECT  GLOBAL DEFAULT  UND _gp_disp
+.*: 00068000     0 NOTYPE  GLOBAL DEFAULT  ABS _gp
+.*: 00041050    14 FUNC    GLOBAL DEFAULT \[MIPS16\] .* f3
+.*: 00041060    24 FUNC    GLOBAL DEFAULT .* __start
+.*: 0004103c    20 FUNC    GLOBAL DEFAULT .* f2
+.*: 00041020    28 FUNC    GLOBAL DEFAULT .* f1
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1a.s
new file mode 100644
index 0000000..c54030e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1a.s
@@ -0,0 +1,31 @@
+	.abicalls
+	.global	f1
+	.global	f2
+	.global	f3
+	.ent	f1
+f1:
+	.set	noreorder
+	.cpload	$25
+	.set	reorder
+	.option	pic0
+	jal	f3
+	.option	pic2
+	jr	$31
+	.end	f1
+
+	.ent	f2
+f2:
+	.set	noreorder
+	.cpload	$25
+	.set	reorder
+	jr	$31
+	.end	f2
+
+	.set	mips16
+	.ent	f3
+f3:
+	li	$2,%hi(_gp_disp)
+	addiu	$3,$pc,%lo(_gp_disp)
+	sll	$2,16
+	addu	$2,$2,$3
+	.end	f3
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1b.s
new file mode 100644
index 0000000..5739fef
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-1b.s
@@ -0,0 +1,9 @@
+	.abicalls
+	.option	pic0
+	.global	__start
+	.ent	__start
+__start:
+	jal	f1
+	jal	f2
+	jal	f3
+	.end	__start
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-2.d b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-2.d
new file mode 100644
index 0000000..da28cc3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-2.d
@@ -0,0 +1,23 @@
+#source: pic-and-nonpic-2a.s
+#source: pic-and-nonpic-2b.s
+#as: -32 -EB
+#ld: -melf32btsmip -Tpic-and-nonpic-1.ld
+#objdump: -dr
+
+.*
+
+Disassembly of section \.text:
+
+00041000 <__start>:
+   41000:	0c010406 	jal	41018 <\.pic\.foo@@V2>
+   41004:	00000000 	nop
+	\.\.\.
+
+00041018 <\.pic\.foo@@V2>:
+   41018:	3c190004 	lui	t9,0x4
+   4101c:	27391020 	addiu	t9,t9,4128
+
+00041020 <foo2>:
+   41020:	03e00008 	jr	ra
+   41024:	00000000 	nop
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-2a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-2a.s
new file mode 100644
index 0000000..45a490f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-2a.s
@@ -0,0 +1,7 @@
+	.abicalls
+	.option	pic0
+	.global	__start
+	.ent	__start
+__start:
+	jal	foo
+	.end	__start
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-2b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-2b.s
new file mode 100644
index 0000000..4770b22
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-2b.s
@@ -0,0 +1,6 @@
+	.abicalls
+	.symver	foo2,foo@@V2
+	.global	foo2
+	.ent	foo2
+foo2:	jr	$31
+	.end	foo2
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3-error.d b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3-error.d
new file mode 100644
index 0000000..975ffa7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3-error.d
@@ -0,0 +1,5 @@
+#name: PIC and non-PIC test 3 (error)
+#source: pic-and-nonpic-3b.s
+#as: -EB -32 -mips2
+#ld: tmpdir/pic-and-nonpic-3a.so -melf32btsmip -znocopyreloc
+#error: .*: non-dynamic relocations refer to dynamic symbol foo
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.dd
new file mode 100644
index 0000000..320e4ca
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.dd
@@ -0,0 +1,39 @@
+# GOT layout:
+#
+# -32752: lazy resolution function
+# -32748: reserved for module pointer
+# -32744: the GOT page entry
+# -32740: foo's GOT entry
+# -32736: ext's GOT entry
+
+.*
+
+Disassembly of section \.text:
+
+00000800 <foo>:
+ 800:	3c1c0001 	lui	gp,0x1
+ 804:	279c7bf0 	addiu	gp,gp,31728
+ 808:	0399e021 	addu	gp,gp,t9
+ 80c:	8f99801c 	lw	t9,-32740\(gp\)
+ 810:	8f828018 	lw	v0,-32744\(gp\)
+ 814:	03200008 	jr	t9
+ 818:	24420000 	addiu	v0,v0,0
+
+0000081c <bar>:
+ 81c:	f000 6a01 	li	v0,1
+ 820:	f3cf 0a10 	la	v0,83f0 .*
+ 824:	f400 3240 	sll	v0,16
+ 828:	e269      	addu	v0,v1
+ 82a:	f030 9a60 	lw	v1,-32736\(v0\)
+ 82e:	659a      	move	gp,v0
+ 830:	eb00      	jr	v1
+ 832:	653b      	move	t9,v1
+#...
+Disassembly of section \.MIPS\.stubs:
+
+00000c00 <.MIPS.stubs>:
+ c00:	8f998010 	lw	t9,-32752\(gp\)
+ c04:	03e07821 	move	t7,ra
+ c08:	0320f809 	jalr	t9
+ c0c:	24180007 	li	t8,7
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.gd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.gd
new file mode 100644
index 0000000..aa9579b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.gd
@@ -0,0 +1,18 @@
+
+Primary GOT:
+ Canonical gp value: 000183f0
+
+ Reserved entries:
+   Address     Access  Initial Purpose
+  00010400 -32752\(gp\) 00000000 Lazy resolver
+  00010404 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+ Local entries:
+   Address     Access  Initial
+  00010408 -32744\(gp\) 00010000
+
+ Global entries:
+   Address     Access  Initial Sym\.Val\. Type    Ndx Name
+  0001040c -32740\(gp\) 00000800 00000800 FUNC      6 foo
+  00010410 -32736\(gp\) 00000c00 00000c00 FUNC    UND ext
+
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.ld
new file mode 100644
index 0000000..cc4bd55
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.ld
@@ -0,0 +1,23 @@
+SECTIONS
+{
+  . = 0;
+  .reginfo : { *(.reginfo) }
+
+  . = ALIGN (0x400);
+  .dynamic : { *(.dynamic) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+
+  . = ALIGN (0x400);
+  .text : { *(.text) }
+
+  . = ALIGN (0x400);
+  .MIPS.stubs : { *(.MIPS.stubs) }
+
+  . = ALIGN (0x10000);
+  .data : { *(.data) }
+
+  . = ALIGN (0x400);
+  _gp = . + 0x7ff0;
+  .got : { *(.got) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.s
new file mode 100644
index 0000000..385e7fd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.s
@@ -0,0 +1,29 @@
+	.abicalls
+	.set	noreorder
+	.set	nomips16
+	.global	foo
+	.ent	foo
+foo:
+	.cpload	$25
+	lw	$25,%call16(foo)($28)
+	lw	$2,%got(data)($28)
+	jr	$25
+	addiu	$2,$2,%lo(data)
+	.end	foo
+
+	.set	mips16
+	.global	bar
+	.ent	bar
+bar:
+	li	$2,%hi(_gp_disp)
+	addiu	$2,$pc,%lo(_gp_disp)
+	sll	$2,16
+	addu	$2,$2,$3
+	lw	$3,%call16(ext)($2)
+	move	$28,$2
+	jr	$3
+	move	$25,$3
+	.end	bar
+
+	.data
+data:	.word	0x12345678
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd
new file mode 100644
index 0000000..58b50c3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd
@@ -0,0 +1,20 @@
+
+Elf file type is DYN \(Shared object file\)
+Entry point .*
+There are 5 program headers, starting at offset .*
+
+Program Headers:
+ * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align
+ * REGINFO * [^ ]+ * 0x0+00000 * 0x0+00000 [^ ]+ * [^ ]+ * R * 0x.*
+ * LOAD * [^ ]+ * 0x0+00000 * 0x0+00000 [^ ]+ * [^ ]+ * R E * 0x.*
+ * LOAD * [^ ]+ * 0x0+10000 * 0x0+10000 [^ ]+ * [^ ]+ * RW  * 0x.*
+ * DYNAMIC * [^ ]+ * 0x0+00400 * 0x0+00400 .*
+ * NULL * .*
+
+ *Section to Segment mapping:
+ *Segment Sections\.\.\.
+ *0*0 * \.reginfo *
+ *0*1 * \.reginfo \.dynamic \.dynsym \.dynstr \.hash \.text \.MIPS.stubs *
+ *0*2 * \.data \.got *
+ *0*3 * \.dynamic *
+ *0*4 *
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ad b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ad
new file mode 100644
index 0000000..fdcc0b1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ad
@@ -0,0 +1,27 @@
+
+Dynamic section at offset .* contains .*:
+ * Tag * Type * Name/Value
+ 0x00000001 \(NEEDED\) .*
+ 0x00000004 \(HASH\) .*
+ 0x00000005 \(STRTAB\) .*
+ 0x00000006 \(SYMTAB\) .*
+ 0x0000000a \(STRSZ\) .*
+ 0x0000000b \(SYMENT\) .*
+ 0x70000016 \(MIPS_RLD_MAP\) * 0x80000
+ 0x00000015 \(DEBUG\) * 0x0
+ 0x00000003 \(PLTGOT\) * 0xa0000
+ 0x70000001 \(MIPS_RLD_VERSION\) * 1
+ 0x70000005 \(MIPS_FLAGS\) * NOTPOT
+ 0x70000006 \(MIPS_BASE_ADDRESS\) * 0x40000
+# This must be the number of GOT entries - 1, the last entry being for "bar".
+ 0x7000000a \(MIPS_LOCAL_GOTNO\) * 3
+# This must be MIPS_GOTSYM + 1.
+ 0x70000011 \(MIPS_SYMTABNO\) * 8
+ 0x70000012 \(MIPS_UNREFEXTNO\) .*
+# This must be the index of "bar".
+ 0x70000013 \(MIPS_GOTSYM\) * 0x7
+ 0x00000014 \(PLTREL\) * REL
+ 0x00000017 \(JMPREL\) * 0x43000
+ 0x00000002 \(PLTRELSZ\) * 8 \(bytes\)
+ 0x70000032 \(MIPS_PLTGOT\) * 0x81000
+ 0x00000000 \(NULL\) * 0x0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.dd
new file mode 100644
index 0000000..b0dfafc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.dd
@@ -0,0 +1,53 @@
+# GOT layout:
+#
+# -32752: lazy resolution function
+# -32748: reserved for module pointer
+# -32744: GOT page entry.
+# -32740: bar's GOT entry
+
+.*
+
+Disassembly of section \.plt:
+
+00043020 <.*>:
+.*:	3c1c0008 	lui	gp,0x8
+.*:	8f991000 	lw	t9,4096\(gp\)
+.*:	279c1000 	addiu	gp,gp,4096
+.*:	031cc023 	subu	t8,t8,gp
+.*:	03e07821 	move	t7,ra
+.*:	0018c082 	srl	t8,t8,0x2
+.*:	0320f809 	jalr	t9
+.*:	2718fffe 	addiu	t8,t8,-2
+
+00043040 <foo@plt>:
+.*:	3c0f0008 	lui	t7,0x8
+.*:	8df91008 	lw	t9,4104\(t7\)
+.*:	25f81008 	addiu	t8,t7,4104
+.*:	03200008 	jr	t9
+.*:	00000000 	nop
+
+Disassembly of section \.text:
+
+00044000 <__start>:
+.*:	0c010c10 	jal	43040 <foo@plt>
+.*:	00000000 	nop
+.*:	08011004 	j	44010 <ext>
+.*:	00000000 	nop
+
+00044010 <ext>:
+.*:	3c1c000a 	lui	gp,0xa
+.*:	279c7ff0 	addiu	gp,gp,32752
+.*:	8f828018 	lw	v0,-32744\(gp\)
+.*:	24421000 	addiu	v0,v0,4096
+.*:	8f99801c 	lw	t9,-32740\(gp\)
+.*:	03200008 	jr	t9
+.*:	00000000 	nop
+.*:	00000000 	nop
+Disassembly of section .MIPS.stubs:
+
+00044030 <\.MIPS\.stubs>:
+.*:	8f998010 	lw	t9,-32752\(gp\)
+.*:	03e07821 	move	t7,ra
+.*:	0320f809 	jalr	t9
+.*:	24180007 	li	t8,7
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.gd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.gd
new file mode 100644
index 0000000..6d3d677
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.gd
@@ -0,0 +1,28 @@
+
+Primary GOT:
+ Canonical gp value: 000a7ff0
+
+ Reserved entries:
+   Address     Access  Initial Purpose
+  000a0000 -32752\(gp\) 00000000 Lazy resolver
+  000a0004 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+ Local entries:
+   Address     Access  Initial
+  000a0008 -32744\(gp\) 000a0000
+
+ Global entries:
+   Address     Access  Initial Sym\.Val\. Type    Ndx Name
+  000a000c -32740\(gp\) 00044030 00044030 FUNC    UND bar
+
+
+PLT GOT:
+
+ Reserved entries:
+   Address  Initial Purpose
+  00081000 00000000 PLT lazy resolver
+  00081004 00000000 Module pointer
+
+ Entries:
+   Address  Initial Sym.Val. Type    Ndx Name
+  00081008 00043020 00000000 FUNC    UND foo
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ld
new file mode 100644
index 0000000..d41c8f9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ld
@@ -0,0 +1,35 @@
+SECTIONS
+{
+  . = 0x40000 + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+
+  . = 0x41000;
+  .reginfo : { *(.reginfo) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+
+  . = 0x42000;
+  .dynamic : { *(.dynamic) }
+
+  . = 0x43000;
+  .rel.plt : { *(.rel.plt) }
+  .plt : { *(.plt) }
+
+  . = 0x44000;
+  .text : { *(.text) }
+  .MIPS.stubs : { *(.MIPS.stubs) }
+
+  . = 0x80000;
+  .rld_map : { *(.rld_map) }
+
+  . = 0x81000;
+  .got.plt : { *(.got.plt) }
+
+  . = 0xa0000;
+  _gp = . + 0x7ff0;
+  .got : { *(.got) }
+
+  . = 0xa1000;
+  .data : { *(.data) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.nd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.nd
new file mode 100644
index 0000000..f115be5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.nd
@@ -0,0 +1,9 @@
+
+Symbol table '\.dynsym' contains .*:
+#...
+.*: 00000000 * 0 * FUNC * GLOBAL * DEFAULT * UND * foo
+# The index on the next line should correspond to MIPS_GOTSYM.
+#...
+ *7: 00044030 * 0 * FUNC * GLOBAL * DEFAULT * UND * bar
+
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.pd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.pd
new file mode 100644
index 0000000..00f8713
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.pd
@@ -0,0 +1,5 @@
+
+.*
+
+Contents of section \.got\.plt:
+ 81000 00000000 00000000 00043020          .*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.rd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.rd
new file mode 100644
index 0000000..d3418db
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.rd
@@ -0,0 +1,4 @@
+
+Relocation section '\.rel\.plt' at offset .* contains .*:
+ * Offset * Info * Type * Sym\.Value * Sym\. Name
+00081008 * 0000057f * R_MIPS_JUMP_SLOT * 00000000 * foo
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.s
new file mode 100644
index 0000000..571c774
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.s
@@ -0,0 +1,22 @@
+	.abicalls
+	.option	pic0
+	.global	__start
+	.ent	__start
+__start:
+	jal	foo
+	j	ext
+	.end	__start
+
+	.global	ext
+	.ent	ext
+ext:
+	lui	$gp,%hi(__gnu_local_gp)
+	addiu	$gp,$gp,%lo(__gnu_local_gp)
+	lw	$2,%got(local)($gp)
+	addiu	$2,$2,%lo(local)
+	lw	$25,%call16(bar)($gp)
+	jr	$25
+	.end	ext
+
+	.data
+local:	.word	1
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.sd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.sd
new file mode 100644
index 0000000..c73ac59
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.sd
@@ -0,0 +1,27 @@
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x44000
+There are 8 program headers, starting at offset .*
+
+Program Headers:
+ * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align
+ * PHDR * .*
+ * INTERP * .*
+.*
+ * REGINFO * [^ ]+ * 0x0+41000 * 0x0+41000 * [^ ]+ * [^ ]+ * R * 0x.*
+ * LOAD * [^ ]+ * 0x0+40000 * 0x0+40000 [^ ]+ * [^ ]+ * R E * 0x.*
+ * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW  * 0x.*
+ * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW  * 0x.*
+ * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .*
+ * NULL * .*
+
+ *Section to Segment mapping:
+ *Segment Sections\.\.\.
+ *0*0 *
+ *0*1 *\.interp *
+ *0*2 *\.reginfo *
+ *0*3 *\.interp \.reginfo \.hash \.dynsym \.dynstr \.dynamic \.rel\.plt \.plt \.text \.MIPS.stubs *
+ *0*4 *\.rld_map \.got\.plt *
+ *0*5 *\.got \.data *
+ *0*6 *\.dynamic *
+ *0*7 *
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4-error.d b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4-error.d
new file mode 100644
index 0000000..7bc0c25
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4-error.d
@@ -0,0 +1,5 @@
+#name: PIC and non-PIC test 4 (error)
+#source: pic-and-nonpic-4b.s
+#as: -EB -32 -mips2
+#ld: tmpdir/pic-and-nonpic-4a.so -melf32btsmip -znocopyreloc
+#error: .*: non-dynamic relocations refer to dynamic symbol obj1
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4a.s
new file mode 100644
index 0000000..54b285a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4a.s
@@ -0,0 +1,22 @@
+	.abicalls
+	.option	pic0
+	.global	obj1
+	.global	obj2
+	.global	obj3
+
+	.type	obj1,%object
+	.type	obj2,%object
+	.type	obj3,%object
+
+	.size	obj1,8
+	.size	obj2,4
+	.size	obj3,16
+
+	.data
+obj1:
+	.word	1, 2
+obj2:
+	.word	3
+obj3:
+	.word	5, 6, 7, 8
+
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ad b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ad
new file mode 100644
index 0000000..ad300b4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ad
@@ -0,0 +1,26 @@
+
+Dynamic section at offset .* contains .*:
+ * Tag * Type * Name/Value
+ 0x00000001 \(NEEDED\) .*
+ 0x00000004 \(HASH\) .*
+ 0x00000005 \(STRTAB\) .*
+ 0x00000006 \(SYMTAB\) .*
+ 0x0000000a \(STRSZ\) .*
+ 0x0000000b \(SYMENT\) .*
+ 0x70000016 \(MIPS_RLD_MAP\) * 0x80000
+ 0x00000015 \(DEBUG\) * 0x0
+ 0x00000003 \(PLTGOT\) * 0xa0000
+ 0x00000011 \(REL\) * 0x43000
+ 0x00000012 \(RELSZ\) * 32 \(bytes\)
+ 0x00000013 \(RELENT\) * 8 \(bytes\)
+ 0x70000001 \(MIPS_RLD_VERSION\) * 1
+ 0x70000005 \(MIPS_FLAGS\) * NOTPOT
+ 0x70000006 \(MIPS_BASE_ADDRESS\) * 0x40000
+# This must be the number of GOT entries - 1, the last entry being for "obj3".
+ 0x7000000a \(MIPS_LOCAL_GOTNO\) * 2
+# This must be MIPS_GOTSYM + 1.
+ 0x70000011 \(MIPS_SYMTABNO\) * 8
+ 0x70000012 \(MIPS_UNREFEXTNO\) .*
+# This must be the index of "obj3".
+ 0x70000013 \(MIPS_GOTSYM\) * 0x7
+ 0x00000000 \(NULL\) * 0x0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.dd
new file mode 100644
index 0000000..d276098
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.dd
@@ -0,0 +1,10 @@
+
+.*
+
+Disassembly of section \.text:
+
+00044000 <__start>:
+   44000:	3c02000a 	lui	v0,0xa
+   44004:	24422000 	addiu	v0,v0,8192
+   44008:	000a2008 	.*
+   4400c:	00000000 	nop
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.gd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.gd
new file mode 100644
index 0000000..0a8a77d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.gd
@@ -0,0 +1,7 @@
+
+.*
+
+Contents of section \.got:
+ a0000 00000000 80000000 00000000           .*
+Contents of section \.data:
+ a1000 000a2008 00000000 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ld
new file mode 100644
index 0000000..bcf9e3a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ld
@@ -0,0 +1,33 @@
+SECTIONS
+{
+  . = 0x40000 + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+
+  . = 0x41000;
+  .reginfo : { *(.reginfo) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+
+  . = 0x42000;
+  .dynamic : { *(.dynamic) }
+
+  . = 0x43000;
+  .rel.dyn : { *(.rel.dyn) }
+
+  . = 0x44000;
+  .text : { *(.text) }
+
+  . = 0x80000;
+  .rld_map : { *(.rld_map) }
+
+  . = 0xa0000;
+  _gp = . + 0x7ff0;
+  .got : { *(.got) }
+
+  . = 0xa1000;
+  .data : { *(.data) }
+
+  . = 0xa2000;
+  .bss : { *(.dynbss) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.nd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.nd
new file mode 100644
index 0000000..d63426c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.nd
@@ -0,0 +1,12 @@
+
+Symbol table '\.dynsym' contains .*:
+# The order of the next two symbols is not important.
+#...
+.*: 000a2000 * 8 * OBJECT * GLOBAL * DEFAULT * [0-9]+ * obj1
+#...
+.*: 000a2008 * 4 * OBJECT * GLOBAL * DEFAULT * [0-9]+ * obj2
+# The index on the next line should correspond to MIPS_GOTSYM.
+#...
+ *7: 0+ * 0 * OBJECT * GLOBAL * DEFAULT * UND * obj3
+
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.rd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.rd
new file mode 100644
index 0000000..452d9c7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.rd
@@ -0,0 +1,7 @@
+
+Relocation section '\.rel\.dyn' at offset .* contains .*:
+ * Offset * Info * Type * Sym\.Value * Sym\. Name
+00000000 * 00000000 * R_MIPS_NONE *
+000a2000 * 0000017e * R_MIPS_COPY * 000a2000 * obj1
+000a2008 * 0000047e * R_MIPS_COPY * 000a2008 * obj2
+000a1004 * 00000703 * R_MIPS_REL32 * 00000000 * obj3
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.s
new file mode 100644
index 0000000..7e25bf4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.s
@@ -0,0 +1,13 @@
+	.abicalls
+	.option	pic0
+	.global	__start
+	.ent	__start
+__start:
+	lui	$2,%hi(obj1)
+	addiu	$2,$2,%lo(obj1)
+	.end	__start
+	.word	obj2
+
+	.data
+	.word	obj2
+	.word	obj3
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.sd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.sd
new file mode 100644
index 0000000..14b13ed
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.sd
@@ -0,0 +1,27 @@
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x44000
+There are 8 program headers, starting at offset .*
+
+Program Headers:
+ * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align
+ * PHDR * .*
+ * INTERP * .*
+.*
+ * REGINFO * [^ ]+ * 0x0+41000 * 0x0+41000 * [^ ]+ * [^ ]+ * R * 0x.*
+ * LOAD * [^ ]+ * 0x0+40000 * 0x0+40000 [^ ]+ * [^ ]+ * R E * 0x.*
+ * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW  * 0x.*
+ * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW  * 0x.*
+ * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .*
+ * NULL * .*
+
+ *Section to Segment mapping:
+ *Segment Sections\.\.\.
+ *0*0 *
+ *0*1 * \.interp *
+ *0*2 * \.reginfo *
+ *0*3 * \.interp \.reginfo \.hash \.dynsym \.dynstr \.dynamic \.rel\.dyn \.text *
+ *0*4 * \.rld_map *
+ *0*5 * \.got \.data \.bss *
+ *0*6 * \.dynamic *
+ *0*7 *
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5a.s
new file mode 100644
index 0000000..7452f5e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5a.s
@@ -0,0 +1,16 @@
+	.abicalls
+	.option	pic0
+	.global	__start
+	.ent	__start
+__start:
+	lui	$2,%hi(foo)
+	addiu	$2,$2,%lo(foo)
+	lui	$2,%hi(obj1)
+	addiu	$2,$2,%lo(obj1)
+	.end	__start
+
+	.data
+	.word	foo
+	.word	bar
+	.word	obj1
+	.word	obj2
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ad b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ad
new file mode 100644
index 0000000..e448ec2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ad
@@ -0,0 +1,32 @@
+
+Dynamic section at offset .* contains .*:
+ * Tag * Type * Name/Value
+ 0x00000001 \(NEEDED\) .*
+ 0x00000001 \(NEEDED\) .*
+ 0x00000004 \(HASH\) .*
+ 0x00000005 \(STRTAB\) .*
+ 0x00000006 \(SYMTAB\) .*
+ 0x0000000a \(STRSZ\) .*
+ 0x0000000b \(SYMENT\) .*
+ 0x70000016 \(MIPS_RLD_MAP\) * 0x80000
+ 0x00000015 \(DEBUG\) * 0x0
+ 0x00000016 \(TEXTREL\) * 0x0
+ 0x00000003 \(PLTGOT\) * 0xa0000
+ 0x00000011 \(REL\) * 0x43000
+ 0x00000012 \(RELSZ\) * 48 \(bytes\)
+ 0x00000013 \(RELENT\) * 8 \(bytes\)
+ 0x70000001 \(MIPS_RLD_VERSION\) * 1
+ 0x70000005 \(MIPS_FLAGS\) * NOTPOT
+ 0x70000006 \(MIPS_BASE_ADDRESS\) * 0x40000
+# This must be the number of GOT entries - 2.  The last two entries are
+# for "bar" and "obj2".
+ 0x7000000a \(MIPS_LOCAL_GOTNO\) * 2
+# This must be MIPS_GOTSYM + 2.
+ 0x70000011 \(MIPS_SYMTABNO\) * 10
+ 0x70000012 \(MIPS_UNREFEXTNO\) * .*
+ 0x70000013 \(MIPS_GOTSYM\) * 0x8
+ 0x00000014 \(PLTREL\) * REL
+ 0x00000017 \(JMPREL\) * 0x43030
+ 0x00000002 \(PLTRELSZ\) * 8 \(bytes\)
+ 0x70000032 \(MIPS_PLTGOT\) * 0x81000
+ 0x00000000 \(NULL\) * 0x0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.dd
new file mode 100644
index 0000000..ff18883
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.dd
@@ -0,0 +1,35 @@
+
+.*
+
+Disassembly of section \.plt:
+
+00043040 <.*>:
+.*:	3c1c0008 	lui	gp,0x8
+.*:	8f991000 	lw	t9,4096\(gp\)
+.*:	279c1000 	addiu	gp,gp,4096
+.*:	031cc023 	subu	t8,t8,gp
+.*:	03e07821 	move	t7,ra
+.*:	0018c082 	srl	t8,t8,0x2
+.*:	0320f809 	jalr	t9
+.*:	2718fffe 	addiu	t8,t8,-2
+
+00043060 <foo@plt>:
+.*:	3c0f0008 	lui	t7,0x8
+.*:	8df91008 	lw	t9,4104\(t7\)
+.*:	25f81008 	addiu	t8,t7,4104
+.*:	03200008 	jr	t9
+.*:	00000000 	nop
+
+Disassembly of section .text:
+
+00044000 <__start>:
+   44000:	3c020004 	lui	v0,0x4
+   44004:	24423060 	addiu	v0,v0,12384
+   44008:	3c02000a 	lui	v0,0xa
+   4400c:	24422000 	addiu	v0,v0,8192
+
+00044010 <ext>:
+   44010:	00043060 	.*
+   44014:	00000000 	.*
+   44018:	000a2000 	.*
+   4401c:	00000000 	.*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.gd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.gd
new file mode 100644
index 0000000..6919a69
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.gd
@@ -0,0 +1,26 @@
+
+Primary GOT:
+ Canonical gp value: 000a7ff0
+
+ Reserved entries:
+   Address     Access  Initial Purpose
+  000a0000 -32752\(gp\) 00000000 Lazy resolver
+  000a0004 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+# There must be GOT entries for the R_MIPS_REL32 relocation symbols.
+ Global entries:
+   Address     Access  Initial Sym\.Val\. Type    Ndx Name
+  000a0008 -32744\(gp\) 00000000 00000000 OBJECT  UND obj2
+  000a000c -32740\(gp\) 00000000 00000000 FUNC    UND bar
+
+
+PLT GOT:
+
+ Reserved entries:
+   Address  Initial Purpose
+  00081000 00000000 PLT lazy resolver
+  00081004 00000000 Module pointer
+
+ Entries:
+   Address  Initial Sym.Val. Type    Ndx Name
+  00081008 00043040 00043060 FUNC    UND foo
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ld
new file mode 100644
index 0000000..6cb7530
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ld
@@ -0,0 +1,38 @@
+SECTIONS
+{
+  . = 0x40000 + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+
+  . = 0x41000;
+  .reginfo : { *(.reginfo) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+
+  . = 0x42000;
+  .dynamic : { *(.dynamic) }
+
+  . = 0x43000;
+  .rel.dyn : { *(.rel.dyn) }
+  .rel.plt : { *(.rel.plt) }
+  .plt : { *(.plt) }
+
+  . = 0x44000;
+  .text : { *(.text) }
+
+  . = 0x80000;
+  .rld_map : { *(.rld_map) }
+
+  . = 0x81000;
+  .got.plt : { *(.got.plt) }
+
+  . = 0xa0000;
+  _gp = . + 0x7ff0;
+  .got : { *(.got) }
+
+  . = 0xa1000;
+  .data : { *(.data) }
+
+  . = 0xa2000;
+  .bss : { *(.dynbss) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.nd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.nd
new file mode 100644
index 0000000..5622f91
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.nd
@@ -0,0 +1,10 @@
+
+Symbol table '\.dynsym' contains .*:
+#...
+.*: 00043060 * 0 * FUNC * GLOBAL * DEFAULT * \[MIPS PLT\] * UND * foo
+# The index on the next line should correspond to MIPS_GOTSYM.
+#...
+ *8: 0+ * 0 * OBJECT * GLOBAL * DEFAULT * UND * obj2
+ *9: 0+ * 0 * FUNC * GLOBAL * DEFAULT * UND * bar
+
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.pd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.pd
new file mode 100644
index 0000000..73b2059
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.pd
@@ -0,0 +1,7 @@
+
+.*
+
+Contents of section \.got\.plt:
+ 81000 00000000 00000000 00043040           .*
+Contents of section \.data:
+ a1000 00043060 00000000 000a2000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.rd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.rd
new file mode 100644
index 0000000..21b2961
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.rd
@@ -0,0 +1,13 @@
+
+Relocation section '\.rel\.dyn' at offset .* contains .*:
+ * Offset * Info * Type * Sym\.Value * Sym\. Name
+00000000 * 00000000 * R_MIPS_NONE *
+000a2000 * [^ ]*7e * R_MIPS_COPY * 000a2000 * obj1
+0004401c * [^ ]*03 * R_MIPS_REL32 * 00000000 * obj2
+000a100c * [^ ]*03 * R_MIPS_REL32 * 00000000 * obj2
+00044014 * [^ ]*03 * R_MIPS_REL32 * 00000000 * bar
+000a1004 * [^ ]*03 * R_MIPS_REL32 * 00000000 * bar
+
+Relocation section '\.rel\.plt' at offset .* contains .*:
+ * Offset * Info * Type * Sym\.Value * Sym\. Name
+00081008 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00043060 * foo
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.s
new file mode 100644
index 0000000..73b518f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.s
@@ -0,0 +1,9 @@
+	.abicalls
+	.global	ext
+	.ent	ext
+ext:
+	.word	foo
+	.word	bar
+	.word	obj1
+	.word	obj2
+	.end	ext
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.sd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.sd
new file mode 100644
index 0000000..b7d7e3a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.sd
@@ -0,0 +1,27 @@
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x44000
+There are 8 program headers, starting at offset .*
+
+Program Headers:
+ * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align
+ * PHDR * .*
+ * INTERP * .*
+.*
+ * REGINFO * [^ ]+ * 0x0+41000 * 0x0+41000 * [^ ]+ * [^ ]+ * R * 0x.*
+ * LOAD * [^ ]+ * 0x0+40000 * 0x0+40000 [^ ]+ * [^ ]+ * R E * 0x.*
+ * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW  * 0x.*
+ * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW  * 0x.*
+ * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .*
+ * NULL * .*
+
+ *Section to Segment mapping:
+ *Segment Sections\.\.\.
+ *0*0 *
+ *0*1 * \.interp *
+ *0*2 * \.reginfo *
+ *0*3 * \.interp \.reginfo \.hash \.dynsym \.dynstr \.dynamic \.rel\.dyn \.rel\.plt \.plt \.text *
+ *0*4 * \.rld_map \.got\.plt *
+ *0*5 * \.got \.data \.bss *
+ *0*6 * \.dynamic *
+ *0*7 *
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.ad b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.ad
new file mode 100644
index 0000000..4be2ac0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.ad
@@ -0,0 +1,27 @@
+
+Dynamic section at offset .* contains .*:
+ * Tag * Type * Name/Value
+ 0x00000001 \(NEEDED\) .*
+ 0x00000004 \(HASH\) .*
+ 0x00000005 \(STRTAB\) .*
+ 0x00000006 \(SYMTAB\) .*
+ 0x0000000a \(STRSZ\) .*
+ 0x0000000b \(SYMENT\) .*
+ 0x70000016 \(MIPS_RLD_MAP\) * 0x80000
+ 0x00000015 \(DEBUG\) * 0x0
+ 0x00000003 \(PLTGOT\) * 0xa0000
+ 0x00000011 \(REL\) * 0x43000
+ 0x00000012 \(RELSZ\) * 40 \(bytes\)
+ 0x00000013 \(RELENT\) * 8 \(bytes\)
+ 0x70000001 \(MIPS_RLD_VERSION\) * 1
+ 0x70000005 \(MIPS_FLAGS\) * NOTPOT
+ 0x70000006 \(MIPS_BASE_ADDRESS\) * 0x40000
+ 0x7000000a \(MIPS_LOCAL_GOTNO\) * 2
+ 0x70000011 \(MIPS_SYMTABNO\) * 14
+ 0x70000012 \(MIPS_UNREFEXTNO\) * .*
+ 0x70000013 \(MIPS_GOTSYM\) * 0x7
+ 0x00000014 \(PLTREL\) * REL
+ 0x00000017 \(JMPREL\) * 0x43028
+ 0x00000002 \(PLTRELSZ\) * 24 \(bytes\)
+ 0x70000032 \(MIPS_PLTGOT\) * 0x81000
+ 0x00000000 \(NULL\) * 0x0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd
new file mode 100644
index 0000000..068e5b3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd
@@ -0,0 +1,102 @@
+# GOT layout:
+#
+# -32752: lazy resolution function
+# -32748: reserved for module pointer
+# -32744: extf2's GOT entry (undefined 0)
+# -32740: extf3's GOT entry (PLT entry)
+# -32736: extd2's GOT entry (copy reloc)
+# -32732: extf1's GOT entry (.MIPS.stubs entry)
+# -32728: extd1's GOT entry (undefined 0)
+# -32724: extf4's GOT entry (PLT entry)
+# -32620: extd4's GOT entry (undefined 0, reloc only)
+
+.*
+
+Disassembly of section \.plt:
+
+00043040 <.*>:
+.*:	3c0e0008 	lui	t2,0x8
+.*:	8dd91000 	lw	t9,4096\(t2\)
+.*:	25ce1000 	addiu	t2,t2,4096
+.*:	030ec023 	subu	t8,t8,t2
+.*:	03e07821 	move	t3,ra
+.*:	0018c082 	srl	t8,t8,0x2
+.*:	0320f809 	jalr	t9
+.*:	2718fffe 	addiu	t8,t8,-2
+
+00043060 <extf4@plt>:
+.*:	3c0f0008 	lui	t3,0x8
+.*:	8df91008 	lw	t9,4104\(t3\)
+.*:	25f81008 	addiu	t8,t3,4104
+.*:	03200008 	jr	t9
+
+00043070 <extf5@plt>:
+.*:	3c0f0008 	lui	t3,0x8
+.*:	8df9100c 	lw	t9,4108\(t3\)
+.*:	25f8100c 	addiu	t8,t3,4108
+.*:	03200008 	jr	t9
+
+00043080 <extf3@plt>:
+.*:	3c0f0008 	lui	t3,0x8
+.*:	8df91010 	lw	t9,4112\(t3\)
+.*:	25f81010 	addiu	t8,t3,4112
+.*:	03200008 	jr	t9
+.*:	00000000 	nop
+
+Disassembly of section \.text:
+
+00044000 <.*>:
+	\.\.\.
+
+00044008 <\.pic\.f1>:
+   44008:	3c190004 	lui	t9,0x4
+   4400c:	27394010 	addiu	t9,t9,16400
+
+00044010 <f1>:
+   44010:	0c011013 	jal	4404c <f3>
+   44014:	3c020004 	lui	v0,0x4
+   44018:	03e00008 	jr	ra
+   4401c:	24424020 	addiu	v0,v0,16416
+
+00044020 <f2>:
+   44020:	3c1c0006 	lui	gp,0x6
+   44024:	0399e021 	addu	gp,gp,t9
+   44028:	279c3fd0 	addiu	gp,gp,16336
+   4402c:	8f998024 	lw	t9,-32732\(gp\)
+   44030:	8f848018 	lw	a0,-32744\(gp\)
+   44034:	8f858028 	lw	a1,-32728\(gp\)
+   44038:	0320f809 	jalr	t9
+   4403c:	8f868020 	lw	a2,-32736\(gp\)
+   44040:	8f99801c 	lw	t9,-32740\(gp\)
+   44044:	03200008 	jr	t9
+   44048:	8f84802c 	lw	a0,-32724\(gp\)
+
+0004404c <f3>:
+   4404c:	03e00008 	jr	ra
+   44050:	00000000 	nop
+	\.\.\.
+
+00044060 <__start>:
+   44060:	0c011002 	jal	44008 <\.pic\.f1>
+   44064:	00000000 	nop
+   44068:	3c020004 	lui	v0,0x4
+   4406c:	24424020 	addiu	v0,v0,16416
+   44070:	0c010c20 	jal	43080 <extf3@plt>
+   44074:	00000000 	nop
+   44078:	0c010c18 	jal	43060 <extf4@plt>
+   4407c:	00000000 	nop
+   44080:	0c010c1c 	jal	43070 <extf5@plt>
+   44084:	00000000 	nop
+   44088:	3c02000a 	lui	v0,0xa
+   4408c:	24422000 	addiu	v0,v0,8192
+   44090:	3c02000a 	lui	v0,0xa
+   44094:	24422018 	addiu	v0,v0,8216
+	\.\.\.
+Disassembly of section \.MIPS\.stubs:
+
+000440a0 <\.MIPS\.stubs>:
+   440a0:	8f998010 	lw	t9,-32752\(gp\)
+   440a4:	03e07821 	move	t3,ra
+   440a8:	0320f809 	jalr	t9
+   440ac:	2418000a 	li	t8,10
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.gd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.gd
new file mode 100644
index 0000000..8b6b5a0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.gd
@@ -0,0 +1,32 @@
+
+Primary GOT:
+ Canonical gp value: 000a7ff0
+
+ Reserved entries:
+   Address     Access  Initial Purpose
+  000a0000 -32752\(gp\) 00000000 Lazy resolver
+  000a0004 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+ Global entries:
+   Address     Access  Initial Sym\.Val\. Type    Ndx Name
+  000a0008 -32744\(gp\) 00000000 00000000 FUNC    UND extf2
+  000a000c -32740\(gp\) 00000000 00000000 FUNC    UND extf3
+  000a0010 -32736\(gp\) 000a2000 000a2000 OBJECT   16 extd2
+  000a0014 -32732\(gp\) 000440a0 000440a0 FUNC    UND extf1
+  000a0018 -32728\(gp\) 00000000 00000000 OBJECT  UND extd1
+  000a001c -32724\(gp\) 00000000 00000000 FUNC    UND extf4
+  000a0020 -32720\(gp\) 00000000 00000000 OBJECT  UND extd4
+
+
+PLT GOT:
+
+ Reserved entries:
+   Address  Initial Purpose
+  00081000 00000000 PLT lazy resolver
+  00081004 00000000 Module pointer
+
+ Entries:
+   Address  Initial Sym.Val. Type    Ndx Name
+  00081008 00043040 00000000 FUNC    UND extf4
+  0008100c 00043040 00000000 FUNC    UND extf5
+  00081010 00043040 00000000 FUNC    UND extf3
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.nd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.nd
new file mode 100644
index 0000000..8b0d0a6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.nd
@@ -0,0 +1,17 @@
+
+Symbol table '\.dynsym' contains .*:
+#...
+.*: 00000000 * 0 * FUNC * GLOBAL * DEFAULT * UND * extf5
+# The index on the next line should correspond to MIPS_GOTSYM,
+# and the remaining symbols should have the same order as the
+# GOT layout given in the *.dd dump.
+#...
+ *7: 0+ * 0 * FUNC * GLOBAL * DEFAULT * UND * extf2
+ *8: 0+ * 0 * * FUNC * GLOBAL * DEFAULT * UND * extf3
+ *9: 0+a2000 * 24 * OBJECT * GLOBAL * DEFAULT * [0-9]+ * extd2
+ *10: 0+440a0 * 0 * FUNC * GLOBAL * DEFAULT * UND * extf1
+ *11: 0+ * 0 * OBJECT * GLOBAL * DEFAULT * UND * extd1
+ *12: 0+ * 0 * FUNC * GLOBAL * DEFAULT * UND * extf4
+ *13: 0+ * 0 * OBJECT * GLOBAL * DEFAULT * UND * extd4
+
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.pd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.pd
new file mode 100644
index 0000000..5f5de62
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.pd
@@ -0,0 +1,6 @@
+
+.*
+
+Contents of section \.got\.plt:
+ 81000 00000000 00000000 00043040 00043040  .*
+ 81010 00043040                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.rd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.rd
new file mode 100644
index 0000000..0fd5b7e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.rd
@@ -0,0 +1,14 @@
+
+Relocation section '\.rel\.dyn' at offset .* contains .*:
+ * Offset * Info * Type * Sym\.Value * Sym\. Name
+00000000 * 00000000 * R_MIPS_NONE *
+000a2018 * [^ ]*7e * R_MIPS_COPY * 000a2018 * extd3
+000a2000 * [^ ]*7e * R_MIPS_COPY * 000a2000 * extd2
+000a1000 * [^ ]*03 * R_MIPS_REL32 * 00000000 * extd1
+000a1014 * [^ ]*03 * R_MIPS_REL32 * 00000000 * extd4
+
+Relocation section '\.rel\.plt' at offset .* contains .*:
+ * Offset * Info * Type * Sym\.Value * Sym\. Name
+00081008 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf4
+0008100c * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf5
+00081010 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf3
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.sd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.sd
new file mode 100644
index 0000000..b5d51b3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.sd
@@ -0,0 +1,27 @@
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x44000
+There are 8 program headers, starting at offset .*
+
+Program Headers:
+ * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align
+ * PHDR * .*
+ * INTERP * .*
+.*
+ * REGINFO * [^ ]+ * 0x0+41000 * 0x0+41000 * [^ ]+ * [^ ]+ * R * 0x.*
+ * LOAD * [^ ]+ * 0x0+40000 * 0x0+40000 [^ ]+ * [^ ]+ * R E * 0x.*
+ * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW  * 0x.*
+ * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW  * 0x.*
+ * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .*
+ * NULL * .*
+
+ *Section to Segment mapping:
+ *Segment Sections\.\.\.
+ *0*0 *
+ *0*1 * \.interp *
+ *0*2 * \.reginfo *
+ *0*3 * \.interp \.reginfo \.hash \.dynsym \.dynstr \.dynamic \.rel\.dyn \.rel\.plt \.plt \.text \.MIPS\.stubs *
+ *0*4 * \.rld_map \.got\.plt *
+ *0*5 * \.got \.data \.bss *
+ *0*6 * \.dynamic *
+ *0*7 *
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32a.s
new file mode 100644
index 0000000..a4c0075
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32a.s
@@ -0,0 +1,48 @@
+	.abicalls
+	.global	extf1
+	.ent	extf1
+extf1:
+	jr	$31
+	.end	extf1
+
+	.global	extf2
+	.ent	extf2
+extf2:
+	jr	$31
+	.end	extf2
+
+	.global	extf3
+	.ent	extf3
+extf3:
+	jr	$31
+	.end	extf3
+
+	.global	extf4
+	.ent	extf4
+extf4:
+	jr	$31
+	.end	extf4
+
+	.global	extf5
+	.ent	extf5
+extf5:
+	jr	$31
+	.end	extf5
+
+	.data
+	.global	extd1
+	.global	extd2
+	.global	extd3
+	.global	extd4
+	.type	extd1,%object
+	.type	extd2,%object
+	.type	extd3,%object
+	.type	extd4,%object
+	.size	extd1,20
+	.size	extd2,24
+	.size	extd3,28
+	.size	extd4,8
+extd1:	.space	20
+extd2:	.space	24
+extd3:	.space	28
+extd4:	.space	8
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32b.s
new file mode 100644
index 0000000..48cf97f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32b.s
@@ -0,0 +1,39 @@
+	.set	noreorder
+	.abicalls
+	.global	f1
+	.ent	f1
+f1:
+	.option	pic0
+	jal	f3
+	.option	pic2
+	lui	$2,%hi(f2)
+	jr	$31
+	addiu	$2,$2,%lo(f2)
+	.end	f1
+
+	.global	f2
+	.ent	f2
+f2:
+	lui	$28,%hi(%neg(%gp_rel(f2)))
+	addu	$28,$28,$25
+	addiu	$28,$28,%lo(%neg(%gp_rel(f2)))
+	lw	$25,%call16(extf1)($28)
+	lw	$4,%got_disp(extf2)($28)
+	lw	$5,%got_disp(extd1)($28)
+	jalr	$25
+	lw	$6,%got_disp(extd2)($28)
+	lw	$25,%call16(extf3)($28)
+	jr	$25
+	lw	$4,%got_disp(extf4)($28)
+	.end	f2
+
+	.global	f3
+	.ent	f3
+f3:
+	jr	$31
+	nop
+	.end	f3
+
+	.data
+	.word	extd1
+	.word	extd3
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32c.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32c.s
new file mode 100644
index 0000000..578626a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32c.s
@@ -0,0 +1,25 @@
+	.abicalls
+	.option	pic0
+	.set	noreorder
+	.global	__start
+	.ent	__start
+__start:
+	jal	f1
+	nop
+	lui	$2,%hi(f2)
+	addiu	$2,$2,%lo(f2)
+	jal	extf3
+	nop
+	jal	extf4
+	nop
+	jal	extf5
+	nop
+	lui	$2,%hi(extd2)
+	addiu	$2,$2,%lo(extd2)
+	lui	$2,%hi(extd3)
+	addiu	$2,$2,%lo(extd3)
+	.end	__start
+
+	.data
+	.word	extd2
+	.word	extd4
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.ad b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.ad
new file mode 100644
index 0000000..2ccb8b8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.ad
@@ -0,0 +1,27 @@
+
+Dynamic section at offset .* contains .*:
+ * Tag * Type * Name/Value
+ 0x0+00000001 \(NEEDED\) .*
+ 0x0+00000004 \(HASH\) .*
+ 0x0+00000005 \(STRTAB\) .*
+ 0x0+00000006 \(SYMTAB\) .*
+ 0x0+0000000a \(STRSZ\) .*
+ 0x0+0000000b \(SYMENT\) .*
+ 0x0+70000016 \(MIPS_RLD_MAP\) * 0x80000
+ 0x0+00000015 \(DEBUG\) * 0x0
+ 0x0+00000003 \(PLTGOT\) * 0xa0000
+ 0x0+00000011 \(REL\) * 0x43000
+ 0x0+00000012 \(RELSZ\) * 80 \(bytes\)
+ 0x0+00000013 \(RELENT\) * 16 \(bytes\)
+ 0x0+70000001 \(MIPS_RLD_VERSION\) * 1
+ 0x0+70000005 \(MIPS_FLAGS\) * NOTPOT
+ 0x0+70000006 \(MIPS_BASE_ADDRESS\) * 0x40000
+ 0x0+7000000a \(MIPS_LOCAL_GOTNO\) * 2
+ 0x0+70000011 \(MIPS_SYMTABNO\) * 14
+ 0x0+70000012 \(MIPS_UNREFEXTNO\) * .*
+ 0x0+70000013 \(MIPS_GOTSYM\) * 0x7
+ 0x0+00000014 \(PLTREL\) * REL
+ 0x0+00000017 \(JMPREL\) * 0x43050
+ 0x0+00000002 \(PLTRELSZ\) * 48 \(bytes\)
+ 0x0+70000032 \(MIPS_PLTGOT\) * 0x81000
+ 0x0+00000000 \(NULL\) * 0x0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd
new file mode 100644
index 0000000..c1a5681
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd
@@ -0,0 +1,102 @@
+# GOT layout:
+#
+# -32752: lazy resolution function
+# -32744: reserved for module pointer
+# -32736: extf2's GOT entry (undefined 0)
+# -32728: extf3's GOT entry (PLT entry)
+# -32720: extd2's GOT entry (copy reloc)
+# -32712: extf1's GOT entry (.MIPS.stubs entry)
+# -32704: extd1's GOT entry (undefined 0)
+# -32696: extf4's GOT entry (PLT entry)
+# -32688: extd4's GOT entry (undefined 0, reloc only)
+
+.*
+
+Disassembly of section \.plt:
+
+0+43080 <.*>:
+.*:	3c0e0008 	lui	t2,0x8
+.*:	ddd91000 	ld	t9,4096\(t2\)
+.*:	25ce1000 	addiu	t2,t2,4096
+.*:	030ec023 	subu	t8,t8,t2
+.*:	03e07821 	move	t3,ra
+.*:	0018c0c2 	srl	t8,t8,0x3
+.*:	0320f809 	jalr	t9
+.*:	2718fffe 	addiu	t8,t8,-2
+
+0+430a0 <extf4@plt>:
+.*:	3c0f0008 	lui	t3,0x8
+.*:	ddf91010 	ld	t9,4112\(t3\)
+.*:	25f81010 	addiu	t8,t3,4112
+.*:	03200008 	jr	t9
+
+0+430b0 <extf5@plt>:
+.*:	3c0f0008 	lui	t3,0x8
+.*:	ddf91018 	ld	t9,4120\(t3\)
+.*:	25f81018 	addiu	t8,t3,4120
+.*:	03200008 	jr	t9
+
+0+430c0 <extf3@plt>:
+.*:	3c0f0008 	lui	t3,0x8
+.*:	ddf91020 	ld	t9,4128\(t3\)
+.*:	25f81020 	addiu	t8,t3,4128
+.*:	03200008 	jr	t9
+.*:	00000000 	nop
+
+Disassembly of section \.text:
+
+0+44000 <.*>:
+	\.\.\.
+
+0+44008 <\.pic\.f1>:
+   44008:	3c190004 	lui	t9,0x4
+   4400c:	27394010 	addiu	t9,t9,16400
+
+0+44010 <f1>:
+   44010:	0c011013 	jal	4404c <f3>
+   44014:	3c020004 	lui	v0,0x4
+   44018:	03e00008 	jr	ra
+   4401c:	24424020 	addiu	v0,v0,16416
+
+0+44020 <f2>:
+   44020:	3c1c0006 	lui	gp,0x6
+   44024:	0399e021 	addu	gp,gp,t9
+   44028:	279c3fd0 	addiu	gp,gp,16336
+   4402c:	df998038 	ld	t9,-32712\(gp\)
+   44030:	df848020 	ld	a0,-32736\(gp\)
+   44034:	df858040 	ld	a1,-32704\(gp\)
+   44038:	0320f809 	jalr	t9
+   4403c:	df868030 	ld	a2,-32720\(gp\)
+   44040:	df998028 	ld	t9,-32728\(gp\)
+   44044:	03200008 	jr	t9
+   44048:	df848048 	ld	a0,-32696\(gp\)
+
+0+4404c <f3>:
+   4404c:	03e00008 	jr	ra
+   44050:	00000000 	nop
+	\.\.\.
+
+0+44060 <__start>:
+   44060:	0c011002 	jal	44008 <\.pic\.f1>
+   44064:	00000000 	nop
+   44068:	3c020004 	lui	v0,0x4
+   4406c:	24424020 	addiu	v0,v0,16416
+   44070:	0c010c30 	jal	430c0 <extf3@plt>
+   44074:	00000000 	nop
+   44078:	0c010c28 	jal	430a0 <extf4@plt>
+   4407c:	00000000 	nop
+   44080:	0c010c2c 	jal	430b0 <extf5@plt>
+   44084:	00000000 	nop
+   44088:	3c02000a 	lui	v0,0xa
+   4408c:	24422000 	addiu	v0,v0,8192
+   44090:	3c02000a 	lui	v0,0xa
+   44094:	24422018 	addiu	v0,v0,8216
+	\.\.\.
+Disassembly of section \.MIPS\.stubs:
+
+0+440a0 <\.MIPS\.stubs>:
+   440a0:	df998010 	ld	t9,-32752\(gp\)
+   440a4:	03e0782d 	move	t3,ra
+   440a8:	0320f809 	jalr	t9
+   440ac:	6418000a 	daddiu	t8,zero,10
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.gd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.gd
new file mode 100644
index 0000000..767d150
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.gd
@@ -0,0 +1,32 @@
+
+Primary GOT:
+ Canonical gp value: 00000000000a7ff0
+
+ Reserved entries:
+           Address     Access          Initial Purpose
+  00000000000a0000 -32752\(gp\) 0000000000000000 Lazy resolver
+  00000000000a0008 -32744\(gp\) 8000000000000000 Module pointer \(GNU extension\)
+
+ Global entries:
+           Address     Access          Initial         Sym\.Val\. Type    Ndx Name
+  00000000000a0010 -32736\(gp\) 0000000000000000 0000000000000000 FUNC    UND extf2
+  00000000000a0018 -32728\(gp\) 0000000000000000 0000000000000000 FUNC    UND extf3
+  00000000000a0020 -32720\(gp\) 00000000000a2000 00000000000a2000 OBJECT   16 extd2
+  00000000000a0028 -32712\(gp\) 00000000000440a0 00000000000440a0 FUNC    UND extf1
+  00000000000a0030 -32704\(gp\) 0000000000000000 0000000000000000 OBJECT  UND extd1
+  00000000000a0038 -32696\(gp\) 0000000000000000 0000000000000000 FUNC    UND extf4
+  00000000000a0040 -32688\(gp\) 0000000000000000 0000000000000000 OBJECT  UND extd4
+
+
+PLT GOT:
+
+ Reserved entries:
+           Address          Initial Purpose
+  0000000000081000 0000000000000000 PLT lazy resolver
+  0000000000081008 0000000000000000 Module pointer
+
+ Entries:
+           Address          Initial         Sym.Val. Type    Ndx Name
+  0000000000081010 0000000000043080 0000000000000000 FUNC    UND extf4
+  0000000000081018 0000000000043080 0000000000000000 FUNC    UND extf5
+  0000000000081020 0000000000043080 0000000000000000 FUNC    UND extf3
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.nd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.nd
new file mode 100644
index 0000000..8ee90e4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.nd
@@ -0,0 +1,17 @@
+
+Symbol table '\.dynsym' contains .*:
+#...
+.*: 0+ * 0 * FUNC * GLOBAL * DEFAULT * UND * extf5
+# The index on the next line should correspond to MIPS_GOTSYM,
+# and the remaining symbols should have the same order as the
+# GOT layout given in the *.dd dump.
+#...
+ *7: 0+ * 0 * FUNC * GLOBAL * DEFAULT * UND * extf2
+ *8: 0+ * 0 * FUNC * GLOBAL * DEFAULT * UND * extf3
+ *9: 0+a2000 * 24 * OBJECT * GLOBAL * DEFAULT * [0-9]+ * extd2
+ *10: 0+440a0 * 0 * FUNC * GLOBAL * DEFAULT * UND * extf1
+ *11: 0+ * 0 * OBJECT * GLOBAL * DEFAULT * UND * extd1
+ *12: 0+ * 0 * FUNC * GLOBAL * DEFAULT * UND * extf4
+ *13: 0+ * 0 * OBJECT * GLOBAL * DEFAULT * UND * extd4
+
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.pd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.pd
new file mode 100644
index 0000000..fed9d94
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.pd
@@ -0,0 +1,7 @@
+
+.*
+
+Contents of section \.got\.plt:
+ 81000 00000000 00000000 00000000 00000000  .*
+ 81010 00000000 00043080 00000000 00043080  .*
+ 81020 00000000 00043080                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.rd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.rd
new file mode 100644
index 0000000..666785e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.rd
@@ -0,0 +1,30 @@
+
+Relocation section '\.rel\.dyn' at offset .* contains .*:
+ * Offset * Info * Type * Sym\. Value * Sym\. Name
+0+00000 * 0+ * R_MIPS_NONE *
+ *Type2: R_MIPS_NONE *
+ *Type3: R_MIPS_NONE *
+0+a2018 * [^ ]*7e * R_MIPS_COPY * 0+a2018 * extd3
+ *Type2: R_MIPS_NONE *
+ *Type3: R_MIPS_NONE *
+0+a2000 * [^ ]*7e * R_MIPS_COPY * 0+a2000 * extd2
+ *Type2: R_MIPS_NONE *
+ *Type3: R_MIPS_NONE *
+0+a1000 * [^ ]*03 * R_MIPS_REL32 * 0+00000 * extd1
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+0+a1014 * [^ ]*03 * R_MIPS_REL32 * 0+00000 * extd4
+ *Type2: R_MIPS_64 *
+ *Type3: R_MIPS_NONE *
+
+Relocation section '\.rel\.plt' at offset .* contains .*:
+ * Offset * Info * Type * Sym\. Value * Sym\. Name
+0+81010 * [^ ]*7f * R_MIPS_JUMP_SLOT * 0+00000 * extf4
+ *Type2: R_MIPS_NONE *
+ *Type3: R_MIPS_NONE *
+0+81018 * [^ ]*7f * R_MIPS_JUMP_SLOT * 0+00000 * extf5
+ *Type2: R_MIPS_NONE *
+ *Type3: R_MIPS_NONE *
+0+81020 * [^ ]*7f * R_MIPS_JUMP_SLOT * 0+00000 * extf3
+ *Type2: R_MIPS_NONE *
+ *Type3: R_MIPS_NONE *
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.sd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.sd
new file mode 100644
index 0000000..3842baa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.sd
@@ -0,0 +1,25 @@
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x44000
+There are 7 program headers, starting at offset .*
+
+Program Headers:
+ * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align
+ * PHDR * .*
+ * INTERP * .*
+.*
+ * LOAD * [^ ]+ * 0x0+40000 * 0x0+40000 [^ ]+ * [^ ]+ * R E * 0x.*
+ * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW  * 0x.*
+ * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW  * 0x.*
+ * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .*
+ * NULL * .*
+
+ *Section to Segment mapping:
+ *Segment Sections\.\.\.
+ *0*0 *
+ *0*1 * \.interp *
+ *0*2 * \.interp \.hash \.dynsym \.dynstr \.dynamic \.rel\.dyn \.rel\.plt \.plt \.text \.MIPS\.stubs \.MIPS\.options *
+ *0*3 * \.rld_map \.got\.plt *
+ *0*4 * \.got \.data \.bss *
+ *0*5 * \.dynamic *
+ *0*6 *
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64a.s
new file mode 100644
index 0000000..a4c0075
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64a.s
@@ -0,0 +1,48 @@
+	.abicalls
+	.global	extf1
+	.ent	extf1
+extf1:
+	jr	$31
+	.end	extf1
+
+	.global	extf2
+	.ent	extf2
+extf2:
+	jr	$31
+	.end	extf2
+
+	.global	extf3
+	.ent	extf3
+extf3:
+	jr	$31
+	.end	extf3
+
+	.global	extf4
+	.ent	extf4
+extf4:
+	jr	$31
+	.end	extf4
+
+	.global	extf5
+	.ent	extf5
+extf5:
+	jr	$31
+	.end	extf5
+
+	.data
+	.global	extd1
+	.global	extd2
+	.global	extd3
+	.global	extd4
+	.type	extd1,%object
+	.type	extd2,%object
+	.type	extd3,%object
+	.type	extd4,%object
+	.size	extd1,20
+	.size	extd2,24
+	.size	extd3,28
+	.size	extd4,8
+extd1:	.space	20
+extd2:	.space	24
+extd3:	.space	28
+extd4:	.space	8
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64b.s
new file mode 100644
index 0000000..7a7979c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64b.s
@@ -0,0 +1,39 @@
+	.set	noreorder
+	.abicalls
+	.global	f1
+	.ent	f1
+f1:
+	.option	pic0
+	jal	f3
+	.option	pic2
+	lui	$2,%hi(f2)
+	jr	$31
+	addiu	$2,$2,%lo(f2)
+	.end	f1
+
+	.global	f2
+	.ent	f2
+f2:
+	lui	$28,%hi(%neg(%gp_rel(f2)))
+	addu	$28,$28,$25
+	addiu	$28,$28,%lo(%neg(%gp_rel(f2)))
+	ld	$25,%call16(extf1)($28)
+	ld	$4,%got_disp(extf2)($28)
+	ld	$5,%got_disp(extd1)($28)
+	jalr	$25
+	ld	$6,%got_disp(extd2)($28)
+	ld	$25,%call16(extf3)($28)
+	jr	$25
+	ld	$4,%got_disp(extf4)($28)
+	.end	f2
+
+	.global	f3
+	.ent	f3
+f3:
+	jr	$31
+	nop
+	.end	f3
+
+	.data
+	.word	extd1
+	.word	extd3
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64c.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64c.s
new file mode 100644
index 0000000..578626a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64c.s
@@ -0,0 +1,25 @@
+	.abicalls
+	.option	pic0
+	.set	noreorder
+	.global	__start
+	.ent	__start
+__start:
+	jal	f1
+	nop
+	lui	$2,%hi(f2)
+	addiu	$2,$2,%lo(f2)
+	jal	extf3
+	nop
+	jal	extf4
+	nop
+	jal	extf5
+	nop
+	lui	$2,%hi(extd2)
+	addiu	$2,$2,%lo(extd2)
+	lui	$2,%hi(extd3)
+	addiu	$2,$2,%lo(extd3)
+	.end	__start
+
+	.data
+	.word	extd2
+	.word	extd4
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.ad b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.ad
new file mode 100644
index 0000000..4be2ac0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.ad
@@ -0,0 +1,27 @@
+
+Dynamic section at offset .* contains .*:
+ * Tag * Type * Name/Value
+ 0x00000001 \(NEEDED\) .*
+ 0x00000004 \(HASH\) .*
+ 0x00000005 \(STRTAB\) .*
+ 0x00000006 \(SYMTAB\) .*
+ 0x0000000a \(STRSZ\) .*
+ 0x0000000b \(SYMENT\) .*
+ 0x70000016 \(MIPS_RLD_MAP\) * 0x80000
+ 0x00000015 \(DEBUG\) * 0x0
+ 0x00000003 \(PLTGOT\) * 0xa0000
+ 0x00000011 \(REL\) * 0x43000
+ 0x00000012 \(RELSZ\) * 40 \(bytes\)
+ 0x00000013 \(RELENT\) * 8 \(bytes\)
+ 0x70000001 \(MIPS_RLD_VERSION\) * 1
+ 0x70000005 \(MIPS_FLAGS\) * NOTPOT
+ 0x70000006 \(MIPS_BASE_ADDRESS\) * 0x40000
+ 0x7000000a \(MIPS_LOCAL_GOTNO\) * 2
+ 0x70000011 \(MIPS_SYMTABNO\) * 14
+ 0x70000012 \(MIPS_UNREFEXTNO\) * .*
+ 0x70000013 \(MIPS_GOTSYM\) * 0x7
+ 0x00000014 \(PLTREL\) * REL
+ 0x00000017 \(JMPREL\) * 0x43028
+ 0x00000002 \(PLTRELSZ\) * 24 \(bytes\)
+ 0x70000032 \(MIPS_PLTGOT\) * 0x81000
+ 0x00000000 \(NULL\) * 0x0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd
new file mode 100644
index 0000000..731b8ed
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd
@@ -0,0 +1,102 @@
+# GOT layout:
+#
+# -32752: lazy resolution function
+# -32748: reserved for module pointer
+# -32744: extf2's GOT entry (undefined 0)
+# -32740: extf3's GOT entry (PLT entry)
+# -32736: extd2's GOT entry (copy reloc)
+# -32732: extf1's GOT entry (.MIPS.stubs entry)
+# -32728: extd1's GOT entry (undefined 0)
+# -32724: extf4's GOT entry (PLT entry)
+# -32620: extd4's GOT entry (undefined 0, reloc only)
+
+.*
+
+Disassembly of section \.plt:
+
+00043040 <.*>:
+.*:	3c1c0008 	lui	gp,0x8
+.*:	8f991000 	lw	t9,4096\(gp\)
+.*:	279c1000 	addiu	gp,gp,4096
+.*:	031cc023 	subu	t8,t8,gp
+.*:	03e07821 	move	t7,ra
+.*:	0018c082 	srl	t8,t8,0x2
+.*:	0320f809 	jalr	t9
+.*:	2718fffe 	addiu	t8,t8,-2
+
+00043060 <extf4@plt>:
+.*:	3c0f0008 	lui	t7,0x8
+.*:	8df91008 	lw	t9,4104\(t7\)
+.*:	25f81008 	addiu	t8,t7,4104
+.*:	03200008 	jr	t9
+
+00043070 <extf5@plt>:
+.*:	3c0f0008 	lui	t7,0x8
+.*:	8df9100c 	lw	t9,4108\(t7\)
+.*:	25f8100c 	addiu	t8,t7,4108
+.*:	03200008 	jr	t9
+
+00043080 <extf3@plt>:
+.*:	3c0f0008 	lui	t7,0x8
+.*:	8df91010 	lw	t9,4112\(t7\)
+.*:	25f81010 	addiu	t8,t7,4112
+.*:	03200008 	jr	t9
+.*:	00000000 	nop
+
+Disassembly of section \.text:
+
+00044000 <.*>:
+	\.\.\.
+
+00044008 <\.pic\.f1>:
+   44008:	3c190004 	lui	t9,0x4
+   4400c:	27394010 	addiu	t9,t9,16400
+
+00044010 <f1>:
+   44010:	0c011013 	jal	4404c <f3>
+   44014:	3c020004 	lui	v0,0x4
+   44018:	03e00008 	jr	ra
+   4401c:	24424020 	addiu	v0,v0,16416
+
+00044020 <f2>:
+   44020:	3c1c0006 	lui	gp,0x6
+   44024:	279c3fd0 	addiu	gp,gp,16336
+   44028:	0399e021 	addu	gp,gp,t9
+   4402c:	8f998024 	lw	t9,-32732\(gp\)
+   44030:	8f848018 	lw	a0,-32744\(gp\)
+   44034:	8f858028 	lw	a1,-32728\(gp\)
+   44038:	0320f809 	jalr	t9
+   4403c:	8f868020 	lw	a2,-32736\(gp\)
+   44040:	8f99801c 	lw	t9,-32740\(gp\)
+   44044:	03200008 	jr	t9
+   44048:	8f84802c 	lw	a0,-32724\(gp\)
+
+0004404c <f3>:
+   4404c:	03e00008 	jr	ra
+   44050:	00000000 	nop
+	\.\.\.
+
+00044060 <__start>:
+   44060:	0c011002 	jal	44008 <\.pic\.f1>
+   44064:	00000000 	nop
+   44068:	3c020004 	lui	v0,0x4
+   4406c:	24424020 	addiu	v0,v0,16416
+   44070:	0c010c20 	jal	43080 <extf3@plt>
+   44074:	00000000 	nop
+   44078:	0c010c18 	jal	43060 <extf4@plt>
+   4407c:	00000000 	nop
+   44080:	0c010c1c 	jal	43070 <extf5@plt>
+   44084:	00000000 	nop
+   44088:	3c02000a 	lui	v0,0xa
+   4408c:	24422000 	addiu	v0,v0,8192
+   44090:	3c02000a 	lui	v0,0xa
+   44094:	24422018 	addiu	v0,v0,8216
+	\.\.\.
+Disassembly of section \.MIPS\.stubs:
+
+000440a0 <\.MIPS\.stubs>:
+   440a0:	8f998010 	lw	t9,-32752\(gp\)
+   440a4:	03e07821 	move	t7,ra
+   440a8:	0320f809 	jalr	t9
+   440ac:	2418000a 	li	t8,10
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.gd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.gd
new file mode 100644
index 0000000..8b6b5a0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.gd
@@ -0,0 +1,32 @@
+
+Primary GOT:
+ Canonical gp value: 000a7ff0
+
+ Reserved entries:
+   Address     Access  Initial Purpose
+  000a0000 -32752\(gp\) 00000000 Lazy resolver
+  000a0004 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+ Global entries:
+   Address     Access  Initial Sym\.Val\. Type    Ndx Name
+  000a0008 -32744\(gp\) 00000000 00000000 FUNC    UND extf2
+  000a000c -32740\(gp\) 00000000 00000000 FUNC    UND extf3
+  000a0010 -32736\(gp\) 000a2000 000a2000 OBJECT   16 extd2
+  000a0014 -32732\(gp\) 000440a0 000440a0 FUNC    UND extf1
+  000a0018 -32728\(gp\) 00000000 00000000 OBJECT  UND extd1
+  000a001c -32724\(gp\) 00000000 00000000 FUNC    UND extf4
+  000a0020 -32720\(gp\) 00000000 00000000 OBJECT  UND extd4
+
+
+PLT GOT:
+
+ Reserved entries:
+   Address  Initial Purpose
+  00081000 00000000 PLT lazy resolver
+  00081004 00000000 Module pointer
+
+ Entries:
+   Address  Initial Sym.Val. Type    Ndx Name
+  00081008 00043040 00000000 FUNC    UND extf4
+  0008100c 00043040 00000000 FUNC    UND extf5
+  00081010 00043040 00000000 FUNC    UND extf3
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.nd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.nd
new file mode 100644
index 0000000..15ace17
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.nd
@@ -0,0 +1,17 @@
+
+Symbol table '\.dynsym' contains .*:
+#...
+.*: 00000000 * 0 * FUNC * GLOBAL * DEFAULT * UND * extf5
+# The index on the next line should correspond to MIPS_GOTSYM,
+# and the remaining symbols should have the same order as the
+# GOT layout given in the *.dd dump.
+#...
+ *7: 0+ * 0 * FUNC * GLOBAL * DEFAULT * UND * extf2
+ *8: 0+ * 0 * FUNC * GLOBAL * DEFAULT * UND * extf3
+ *9: 0+a2000 * 24 * OBJECT * GLOBAL * DEFAULT * [0-9]+ * extd2
+ *10: 0+440a0 * 0 * FUNC * GLOBAL * DEFAULT * UND * extf1
+ *11: 0+ * 0 * OBJECT * GLOBAL * DEFAULT * UND * extd1
+ *12: 0+ * 0 * FUNC * GLOBAL * DEFAULT * UND * extf4
+ *13: 0+ * 0 * OBJECT * GLOBAL * DEFAULT * UND * extd4
+
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.pd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.pd
new file mode 100644
index 0000000..5f5de62
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.pd
@@ -0,0 +1,6 @@
+
+.*
+
+Contents of section \.got\.plt:
+ 81000 00000000 00000000 00043040 00043040  .*
+ 81010 00043040                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.rd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.rd
new file mode 100644
index 0000000..0fd5b7e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.rd
@@ -0,0 +1,14 @@
+
+Relocation section '\.rel\.dyn' at offset .* contains .*:
+ * Offset * Info * Type * Sym\.Value * Sym\. Name
+00000000 * 00000000 * R_MIPS_NONE *
+000a2018 * [^ ]*7e * R_MIPS_COPY * 000a2018 * extd3
+000a2000 * [^ ]*7e * R_MIPS_COPY * 000a2000 * extd2
+000a1000 * [^ ]*03 * R_MIPS_REL32 * 00000000 * extd1
+000a1014 * [^ ]*03 * R_MIPS_REL32 * 00000000 * extd4
+
+Relocation section '\.rel\.plt' at offset .* contains .*:
+ * Offset * Info * Type * Sym\.Value * Sym\. Name
+00081008 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf4
+0008100c * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf5
+00081010 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf3
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.sd b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.sd
new file mode 100644
index 0000000..b5d51b3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.sd
@@ -0,0 +1,27 @@
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x44000
+There are 8 program headers, starting at offset .*
+
+Program Headers:
+ * Type * Offset * VirtAddr * PhysAddr * FileSiz * MemSiz * Flg * Align
+ * PHDR * .*
+ * INTERP * .*
+.*
+ * REGINFO * [^ ]+ * 0x0+41000 * 0x0+41000 * [^ ]+ * [^ ]+ * R * 0x.*
+ * LOAD * [^ ]+ * 0x0+40000 * 0x0+40000 [^ ]+ * [^ ]+ * R E * 0x.*
+ * LOAD * [^ ]+ * 0x0+80000 * 0x0+80000 [^ ]+ * [^ ]+ * RW  * 0x.*
+ * LOAD * [^ ]+ * 0x0+a0000 * 0x0+a0000 [^ ]+ * [^ ]+ * RW  * 0x.*
+ * DYNAMIC * [^ ]+ * 0x0+42000 * 0x0+42000 .*
+ * NULL * .*
+
+ *Section to Segment mapping:
+ *Segment Sections\.\.\.
+ *0*0 *
+ *0*1 * \.interp *
+ *0*2 * \.reginfo *
+ *0*3 * \.interp \.reginfo \.hash \.dynsym \.dynstr \.dynamic \.rel\.dyn \.rel\.plt \.plt \.text \.MIPS\.stubs *
+ *0*4 * \.rld_map \.got\.plt *
+ *0*5 * \.got \.data \.bss *
+ *0*6 * \.dynamic *
+ *0*7 *
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32a.s
new file mode 100644
index 0000000..a4c0075
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32a.s
@@ -0,0 +1,48 @@
+	.abicalls
+	.global	extf1
+	.ent	extf1
+extf1:
+	jr	$31
+	.end	extf1
+
+	.global	extf2
+	.ent	extf2
+extf2:
+	jr	$31
+	.end	extf2
+
+	.global	extf3
+	.ent	extf3
+extf3:
+	jr	$31
+	.end	extf3
+
+	.global	extf4
+	.ent	extf4
+extf4:
+	jr	$31
+	.end	extf4
+
+	.global	extf5
+	.ent	extf5
+extf5:
+	jr	$31
+	.end	extf5
+
+	.data
+	.global	extd1
+	.global	extd2
+	.global	extd3
+	.global	extd4
+	.type	extd1,%object
+	.type	extd2,%object
+	.type	extd3,%object
+	.type	extd4,%object
+	.size	extd1,20
+	.size	extd2,24
+	.size	extd3,28
+	.size	extd4,8
+extd1:	.space	20
+extd2:	.space	24
+extd3:	.space	28
+extd4:	.space	8
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32b.s
new file mode 100644
index 0000000..4f8816b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32b.s
@@ -0,0 +1,37 @@
+	.set	noreorder
+	.abicalls
+	.global	f1
+	.ent	f1
+f1:
+	.option	pic0
+	jal	f3
+	.option	pic2
+	lui	$2,%hi(f2)
+	jr	$31
+	addiu	$2,$2,%lo(f2)
+	.end	f1
+
+	.global	f2
+	.ent	f2
+f2:
+	.cpload	$25
+	lw	$25,%call16(extf1)($28)
+	lw	$4,%got(extf2)($28)
+	lw	$5,%got(extd1)($28)
+	jalr	$25
+	lw	$6,%got(extd2)($28)
+	lw	$25,%call16(extf3)($28)
+	jr	$25
+	lw	$4,%got(extf4)($28)
+	.end	f2
+
+	.global	f3
+	.ent	f3
+f3:
+	jr	$31
+	nop
+	.end	f3
+
+	.data
+	.word	extd1
+	.word	extd3
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32c.s b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32c.s
new file mode 100644
index 0000000..578626a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32c.s
@@ -0,0 +1,25 @@
+	.abicalls
+	.option	pic0
+	.set	noreorder
+	.global	__start
+	.ent	__start
+__start:
+	jal	f1
+	nop
+	lui	$2,%hi(f2)
+	addiu	$2,$2,%lo(f2)
+	jal	extf3
+	nop
+	jal	extf4
+	nop
+	jal	extf5
+	nop
+	lui	$2,%hi(extd2)
+	addiu	$2,$2,%lo(extd2)
+	lui	$2,%hi(extd3)
+	addiu	$2,$2,%lo(extd3)
+	.end	__start
+
+	.data
+	.word	extd2
+	.word	extd4
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6.ld
new file mode 100644
index 0000000..aff900e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/pic-and-nonpic-6.ld
@@ -0,0 +1,40 @@
+SECTIONS
+{
+  . = 0x40000 + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+
+  . = 0x41000;
+  .reginfo : { *(.reginfo) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+
+  . = 0x42000;
+  .dynamic : { *(.dynamic) }
+
+  . = 0x43000;
+  .rel.dyn : { *(.rel.dyn) }
+  .rel.plt : { *(.rel.plt) }
+  .plt : { *(.plt) }
+
+  . = 0x44000;
+  .text : { *(.text) }
+  .MIPS.stubs : { *(.MIPS.stubs) }
+  .MIPS.options : { *(.MIPS.options) }
+
+  . = 0x80000;
+  .rld_map : { *(.rld_map) }
+
+  . = 0x81000;
+  .got.plt : { *(.got.plt) }
+
+  . = 0xa0000;
+  _gp = . + 0x7ff0;
+  .got : { *(.got) }
+
+  . = 0xa1000;
+  .data : { *(.data) }
+
+  . = 0xa2000;
+  .bss : { *(.dynbss) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/region1.d b/binutils-2.19/ld/testsuite/ld-mips-elf/region1.d
new file mode 100644
index 0000000..4e65f53
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/region1.d
@@ -0,0 +1,11 @@
+# as: -mabi=eabi -mips1 -G0
+# source: region1a.s
+# source: region1b.s
+# ld: -T region1.t
+# name: MIPS region1
+# objdump: --headers
+#...
+  0 \.text +0+004 +0+10000 .*
+#...
+  1 \.data +0+004 +0+20000 .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/region1.t b/binutils-2.19/ld/testsuite/ld-mips-elf/region1.t
new file mode 100644
index 0000000..13077ab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/region1.t
@@ -0,0 +1,12 @@
+MEMORY
+{
+  TEXTMEM : ORIGIN = 0x10000, LENGTH = 32K
+  DATAMEM : ORIGIN = 0x20000, LENGTH = 32K
+}
+
+SECTIONS
+{
+  .text : { *(.text) } > TEXTMEM
+  .data : { *(.data) } > DATAMEM
+  .bss  : { *(.bss)  } > DATAMEM
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/region1a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/region1a.s
new file mode 100644
index 0000000..715a986
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/region1a.s
@@ -0,0 +1,3 @@
+	.text
+	.global foo
+foo:	.4byte	1
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/region1b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/region1b.s
new file mode 100644
index 0000000..9a72c96
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/region1b.s
@@ -0,0 +1,2 @@
+	.data
+	.4byte	foo
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/rel32-n32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/rel32-n32.d
new file mode 100644
index 0000000..aae33b3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/rel32-n32.d
@@ -0,0 +1,15 @@
+#name: MIPS rel32 n32
+#source: rel32.s
+#as: -KPIC -EB -n32
+#readelf: -x .text -r
+#ld: -shared -melf32btsmipn32
+
+Relocation section '.rel.dyn' at offset .* contains 2 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name
+[0-9a-f ]+R_MIPS_NONE      
+[0-9a-f ]+R_MIPS_REL32     
+
+Hex dump of section '.text':
+  0x000002e0 00000000 00000000 00000000 00000000 ................
+  0x000002f0 000002f0 00000000 00000000 00000000 ................
+  0x00000300 00000000 00000000 00000000 00000000 ................
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/rel32-o32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/rel32-o32.d
new file mode 100644
index 0000000..742cdaa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/rel32-o32.d
@@ -0,0 +1,15 @@
+#name: MIPS rel32 o32
+#source: rel32.s
+#as: -KPIC -EB -32
+#readelf: -x .text -r
+#ld: -shared -melf32btsmip
+
+Relocation section '.rel.dyn' at offset .* contains 2 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name
+[0-9a-f ]+R_MIPS_NONE      
+[0-9a-f ]+R_MIPS_REL32     
+
+Hex dump of section '.text':
+  0x000002e0 00000000 00000000 00000000 00000000 ................
+  0x000002f0 000002f0 00000000 00000000 00000000 ................
+  0x00000300 00000000 00000000 00000000 00000000 ................
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/rel32.s b/binutils-2.19/ld/testsuite/ld-mips-elf/rel32.s
new file mode 100644
index 0000000..dad4670
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/rel32.s
@@ -0,0 +1,4 @@
+	.space 16
+.Lfoo:
+	.word .Lfoo
+	.space 16
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/rel64.d b/binutils-2.19/ld/testsuite/ld-mips-elf/rel64.d
new file mode 100644
index 0000000..4279e28
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/rel64.d
@@ -0,0 +1,19 @@
+#name: MIPS rel64 n64
+#source: rel64.s
+#as: -KPIC -EB -64
+#readelf: -x .text -r
+#ld: -shared -melf64btsmip
+
+Relocation section '.rel.dyn' at offset .* contains 2 entries:
+  Offset          Info           Type           Sym. Value    Sym. Name
+[0-9a-f ]+R_MIPS_NONE      
+ +Type2: R_MIPS_NONE      
+ +Type3: R_MIPS_NONE      
+[0-9a-f ]+R_MIPS_REL32     
+ +Type2: R_MIPS_64        
+ +Type3: R_MIPS_NONE      
+
+Hex dump of section '.text':
+  0x00000450 00000000 00000000 00000000 00000000 ................
+  0x00000460 00000000 00000460 00000000 00000000 ................
+  0x00000470 00000000 00000000 00000000 00000000 ................
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/rel64.s b/binutils-2.19/ld/testsuite/ld-mips-elf/rel64.s
new file mode 100644
index 0000000..3971eb8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/rel64.s
@@ -0,0 +1,4 @@
+	.space 16
+.Lfoo:
+	.dword .Lfoo
+	.space 16
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/relax-jalr-n32-shared.d b/binutils-2.19/ld/testsuite/ld-mips-elf/relax-jalr-n32-shared.d
new file mode 100644
index 0000000..c9288c1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/relax-jalr-n32-shared.d
@@ -0,0 +1,23 @@
+#name: MIPS relax-jalr-shared n32
+#source: relax-jalr.s
+#as: -KPIC -n32 -EB
+#objdump: --prefix-addresses -d --show-raw-insn
+#ld: --relax -shared -melf32btsmipn32
+
+.*:     file format elf.*mips.*
+
+Disassembly of section \.text:
+	\.\.\.
+	\.\.\.
+.*	lw	t9,.*
+.*	jalr	t9
+.*	nop
+	\.\.\.
+.*	lw	t9,.*
+.*	jalr	t9
+.*	nop
+	\.\.\.
+.*	lw	t9,.*
+.*	bal	.* <__start>
+.*	nop
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/relax-jalr-n32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/relax-jalr-n32.d
new file mode 100644
index 0000000..2478b52
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/relax-jalr-n32.d
@@ -0,0 +1,23 @@
+#name: MIPS relax-jalr n32
+#source: relax-jalr.s
+#as: -KPIC -n32 -EB
+#objdump: --prefix-addresses -d --show-raw-insn
+#ld: --relax -melf32btsmipn32
+
+.*:     file format elf.*mips.*
+
+Disassembly of section \.text:
+	\.\.\.
+	\.\.\.
+.*	lw	t9,.*
+.*	bal	.* <__start>
+.*	nop
+	\.\.\.
+.*	lw	t9,.*
+.*	bal	.* <__start>
+.*	nop
+	\.\.\.
+.*	lw	t9,.*
+.*	bal	.* <__start>
+.*	nop
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/relax-jalr-n64-shared.d b/binutils-2.19/ld/testsuite/ld-mips-elf/relax-jalr-n64-shared.d
new file mode 100644
index 0000000..e26d5f1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/relax-jalr-n64-shared.d
@@ -0,0 +1,23 @@
+#name: MIPS relax-jalr-shared n64
+#source: relax-jalr.s
+#as: -KPIC -64 -EB
+#objdump: --prefix-addresses -d --show-raw-insn
+#ld: --relax -shared -melf64btsmip
+
+.*:     file format elf.*mips.*
+
+Disassembly of section \.text:
+	\.\.\.
+	\.\.\.
+.*	ld	t9,.*
+.*	jalr	t9
+.*	nop
+	\.\.\.
+.*	ld	t9,.*
+.*	jalr	t9
+.*	nop
+	\.\.\.
+.*	ld	t9,.*
+.*	bal	.* <__start>
+.*	nop
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/relax-jalr-n64.d b/binutils-2.19/ld/testsuite/ld-mips-elf/relax-jalr-n64.d
new file mode 100644
index 0000000..9e16974
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/relax-jalr-n64.d
@@ -0,0 +1,23 @@
+#name: MIPS relax-jalr n64
+#source: relax-jalr.s
+#as: -KPIC -64 -EB
+#objdump: --prefix-addresses -d --show-raw-insn
+#ld: --relax -melf64btsmip
+
+.*:     file format elf.*mips.*
+
+Disassembly of section \.text:
+	\.\.\.
+	\.\.\.
+.*	ld	t9,.*
+.*	bal	.* <__start>
+.*	nop
+	\.\.\.
+.*	ld	t9,.*
+.*	bal	.* <__start>
+.*	nop
+	\.\.\.
+.*	ld	t9,.*
+.*	bal	.* <__start>
+.*	nop
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/relax-jalr.s b/binutils-2.19/ld/testsuite/ld-mips-elf/relax-jalr.s
new file mode 100644
index 0000000..ba7ea1a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/relax-jalr.s
@@ -0,0 +1,15 @@
+.globl __start
+	.space 8
+.ent __start
+__start:
+.Lstart:
+	.space 16
+        jal __start
+	.space 32
+        jal __start
+	.space 64
+	jal .Lstart
+.end __start
+
+# make objdump print ...
+	.space 8
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-1-n32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-1-n32.d
new file mode 100644
index 0000000..dd41822
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-1-n32.d
@@ -0,0 +1,199 @@
+#source: reloc-1a.s -mabi=n32
+#source: reloc-1b.s -mabi=n32
+#ld: -r
+#readelf: --relocs
+
+Relocation section '\.rela\.text' .*
+.*
+#
+# Relocations against tstarta
+#
+.* R_MIPS_HI16 .* \.text \+ ffff7ff0
+.* R_MIPS_LO16 .* \.text \+ ffff7ff0
+.* R_MIPS_HI16 .* \.text \+ ffff8000
+.* R_MIPS_LO16 .* \.text \+ ffff8000
+.* R_MIPS_HI16 .* \.text \+ 0
+.* R_MIPS_LO16 .* \.text \+ 0
+.* R_MIPS_HI16 .* \.text \+ 7ff0
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_HI16 .* \.text \+ 8010
+.* R_MIPS_LO16 .* \.text \+ 8010
+#
+# Relocations against t32a
+#
+.* R_MIPS_HI16 .* \.text \+ ffff8010
+.* R_MIPS_LO16 .* \.text \+ ffff8010
+.* R_MIPS_HI16 .* \.text \+ ffff8020
+.* R_MIPS_LO16 .* \.text \+ ffff8020
+.* R_MIPS_HI16 .* \.text \+ 20
+.* R_MIPS_LO16 .* \.text \+ 20
+.* R_MIPS_HI16 .* \.text \+ 8010
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_HI16 .* \.text \+ 8030
+.* R_MIPS_LO16 .* \.text \+ 8030
+#
+# Relocations against _start
+#
+.* R_MIPS_HI16 .* _start \+ ffff7ff0
+.* R_MIPS_LO16 .* _start \+ ffff7ff0
+.* R_MIPS_HI16 .* _start \+ ffff8000
+.* R_MIPS_LO16 .* _start \+ ffff8000
+.* R_MIPS_HI16 .* _start \+ 0
+.* R_MIPS_LO16 .* _start \+ 0
+.* R_MIPS_HI16 .* _start \+ 7ff0
+.* R_MIPS_LO16 .* _start \+ 7ff0
+.* R_MIPS_HI16 .* _start \+ 8010
+.* R_MIPS_LO16 .* _start \+ 8010
+#
+# Relocations against tstarta
+#
+.* R_MIPS_GOT16 .* \.text \+ ffff7ff0
+.* R_MIPS_LO16 .* \.text \+ ffff7ff0
+.* R_MIPS_GOT16 .* \.text \+ ffff8000
+.* R_MIPS_LO16 .* \.text \+ ffff8000
+.* R_MIPS_GOT16 .* \.text \+ 0
+.* R_MIPS_LO16 .* \.text \+ 0
+.* R_MIPS_GOT16 .* \.text \+ 7ff0
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_GOT16 .* \.text \+ 8010
+.* R_MIPS_LO16 .* \.text \+ 8010
+#
+# Relocations against t32a
+#
+.* R_MIPS_GOT16 .* \.text \+ ffff8010
+.* R_MIPS_LO16 .* \.text \+ ffff8010
+.* R_MIPS_GOT16 .* \.text \+ ffff8020
+.* R_MIPS_LO16 .* \.text \+ ffff8020
+.* R_MIPS_GOT16 .* \.text \+ 20
+.* R_MIPS_LO16 .* \.text \+ 20
+.* R_MIPS_GOT16 .* \.text \+ 8010
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_GOT16 .* \.text \+ 8030
+.* R_MIPS_LO16 .* \.text \+ 8030
+#
+# Relocations against sdg
+#
+.* R_MIPS_GPREL16 .* sdg \+ fffffffc
+.* R_MIPS_GPREL16 .* sdg \+ 0
+.* R_MIPS_GPREL16 .* sdg \+ 4
+#
+# Relocations against sdla.  .sdata should be the first piece of gp-relative
+# data, which the linker script should put _gp - 0x7ff0.
+#
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff801c
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff8020
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff8024
+#
+# Relocations against tstarta
+#
+.* R_MIPS_26 .* \.text \+ fffffffc
+.* R_MIPS_26 .* \.text \+ 0
+.* R_MIPS_26 .* \.text \+ 4
+#
+# Relocations against t32a
+#
+.* R_MIPS_26 .* \.text \+ 1c
+.* R_MIPS_26 .* \.text \+ 20
+.* R_MIPS_26 .* \.text \+ 24
+#
+# Relocations against _start
+#
+.* R_MIPS_26 .* _start \+ fffffffc
+.* R_MIPS_26 .* _start \+ 0
+.* R_MIPS_26 .* _start \+ 4
+#
+# Relocations against tstartb
+#
+.* R_MIPS_HI16 .* \.text \+ 7fe0
+.* R_MIPS_LO16 .* \.text \+ 7fe0
+.* R_MIPS_HI16 .* \.text \+ 7ff0
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_HI16 .* \.text \+ fff0
+.* R_MIPS_LO16 .* \.text \+ fff0
+.* R_MIPS_HI16 .* \.text \+ 17fe0
+.* R_MIPS_LO16 .* \.text \+ 17fe0
+.* R_MIPS_HI16 .* \.text \+ 18000
+.* R_MIPS_LO16 .* \.text \+ 18000
+#
+# Relocations against t32b
+#
+.* R_MIPS_HI16 .* \.text \+ 8000
+.* R_MIPS_LO16 .* \.text \+ 8000
+.* R_MIPS_HI16 .* \.text \+ 8010
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_HI16 .* \.text \+ 10010
+.* R_MIPS_LO16 .* \.text \+ 10010
+.* R_MIPS_HI16 .* \.text \+ 18000
+.* R_MIPS_LO16 .* \.text \+ 18000
+.* R_MIPS_HI16 .* \.text \+ 18020
+.* R_MIPS_LO16 .* \.text \+ 18020
+#
+# Relocations against _start
+#
+.* R_MIPS_HI16 .* _start \+ ffff7ff0
+.* R_MIPS_LO16 .* _start \+ ffff7ff0
+.* R_MIPS_HI16 .* _start \+ ffff8000
+.* R_MIPS_LO16 .* _start \+ ffff8000
+.* R_MIPS_HI16 .* _start \+ 0
+.* R_MIPS_LO16 .* _start \+ 0
+.* R_MIPS_HI16 .* _start \+ 7ff0
+.* R_MIPS_LO16 .* _start \+ 7ff0
+.* R_MIPS_HI16 .* _start \+ 8010
+.* R_MIPS_LO16 .* _start \+ 8010
+#
+# Relocations against tstartb
+#
+.* R_MIPS_GOT16 .* \.text \+ 7fe0
+.* R_MIPS_LO16 .* \.text \+ 7fe0
+.* R_MIPS_GOT16 .* \.text \+ 7ff0
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_GOT16 .* \.text \+ fff0
+.* R_MIPS_LO16 .* \.text \+ fff0
+.* R_MIPS_GOT16 .* \.text \+ 17fe0
+.* R_MIPS_LO16 .* \.text \+ 17fe0
+.* R_MIPS_GOT16 .* \.text \+ 18000
+.* R_MIPS_LO16 .* \.text \+ 18000
+#
+# Relocations against t32b
+#
+.* R_MIPS_GOT16 .* \.text \+ 8000
+.* R_MIPS_LO16 .* \.text \+ 8000
+.* R_MIPS_GOT16 .* \.text \+ 8010
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_GOT16 .* \.text \+ 10010
+.* R_MIPS_LO16 .* \.text \+ 10010
+.* R_MIPS_GOT16 .* \.text \+ 18000
+.* R_MIPS_LO16 .* \.text \+ 18000
+.* R_MIPS_GOT16 .* \.text \+ 18020
+.* R_MIPS_LO16 .* \.text \+ 18020
+#
+# Relocations against sdg
+#
+.* R_MIPS_GPREL16 .* sdg \+ fffffffc
+.* R_MIPS_GPREL16 .* sdg \+ 0
+.* R_MIPS_GPREL16 .* sdg \+ 4
+#
+# Relocations against sdlb
+#
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff803c
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff8040
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff8044
+#
+# Relocations against tstartb
+#
+.* R_MIPS_26 .* \.text \+ ffec
+.* R_MIPS_26 .* \.text \+ fff0
+.* R_MIPS_26 .* \.text \+ fff4
+#
+# Relocations against t32b
+#
+.* R_MIPS_26 .* \.text \+ 1000c
+.* R_MIPS_26 .* \.text \+ 10010
+.* R_MIPS_26 .* \.text \+ 10014
+#
+# Relocations against _start
+#
+.* R_MIPS_26 .* _start \+ fffffffc
+.* R_MIPS_26 .* _start \+ 0
+.* R_MIPS_26 .* _start \+ 4
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-1-n64.d b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-1-n64.d
new file mode 100644
index 0000000..42d74ea
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-1-n64.d
@@ -0,0 +1,459 @@
+#source: reloc-1a.s -mabi=64 -EB
+#source: reloc-1b.s -mabi=64 -EB
+#ld: -melf64btsmip -r
+#readelf: --relocs
+
+Relocation section '\.rela\.text' .*
+.*
+#
+# Relocations against tstarta
+#
+.* R_MIPS_HI16 .* \.text \+ f+7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ f+7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ f+8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ f+8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against t32a
+#
+.* R_MIPS_HI16 .* \.text \+ f+8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ f+8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ f+8020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ f+8020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 20
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 20
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 8030
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8030
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against _start
+#
+.* R_MIPS_HI16 .* _start \+ f+7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ f+7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ f+8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ f+8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against tstarta
+#
+.* R_MIPS_GOT16 .* \.text \+ f+7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ f+7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ f+8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ f+8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against t32a
+#
+.* R_MIPS_GOT16 .* \.text \+ f+8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ f+8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ f+8020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ f+8020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 20
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 20
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 8030
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8030
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against sdg
+#
+.* R_MIPS_GPREL16 .* sdg \+ f+fffc
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* sdg \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* sdg \+ 4
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against sdla.  .sdata should be the first piece of gp-relative
+# data, which the linker script should put _gp - 0x7ff0.
+#
+.* R_MIPS_GPREL16 .* \.sdata \+ f+801c
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* \.sdata \+ f+8020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* \.sdata \+ f+8024
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against tstarta
+#
+.* R_MIPS_26 .* \.text \+ f+fffc
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ 4
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against t32a
+#
+.* R_MIPS_26 .* \.text \+ 1c
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ 20
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ 24
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against _start
+#
+.* R_MIPS_26 .* _start \+ f+fffc
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* _start \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* _start \+ 4
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against tstartb
+#
+.* R_MIPS_HI16 .* \.text \+ 7fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 7fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ fff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ fff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 17fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 17fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against t32b
+#
+.* R_MIPS_HI16 .* \.text \+ 8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 10010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 10010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 18020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 18020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against _start
+#
+.* R_MIPS_HI16 .* _start \+ f+7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ f+7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ f+8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ f+8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against tstartb
+#
+.* R_MIPS_GOT16 .* \.text \+ 7fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 7fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ fff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ fff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 17fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 17fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against t32b
+#
+.* R_MIPS_GOT16 .* \.text \+ 8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 10010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 10010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 18020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 18020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against sdg
+#
+.* R_MIPS_GPREL16 .* sdg \+ f+fffc
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* sdg \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* sdg \+ 4
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against sdlb
+#
+.* R_MIPS_GPREL16 .* \.sdata \+ f+803c
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* \.sdata \+ f+8040
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* \.sdata \+ f+8044
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against tstartb
+#
+.* R_MIPS_26 .* \.text \+ ffec
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ fff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ fff4
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against t32b
+#
+.* R_MIPS_26 .* \.text \+ 1000c
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ 10010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ 10014
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against _start
+#
+.* R_MIPS_26 .* _start \+ f+fffc
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* _start \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* _start \+ 4
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-1-rel.d b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-1-rel.d
new file mode 100644
index 0000000..e37da1e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-1-rel.d
@@ -0,0 +1,356 @@
+#source: reloc-1a.s
+#source: reloc-1b.s
+#ld: -r
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+.* <.*>:
+#
+# Relocations against tstarta
+#
+.*:	3c04ffff 	lui	a0,0xffff
+			.*: R_MIPS_HI16	\.text
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24840000 	addiu	a0,a0,0
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	\.text
+
+.* <t32a>:
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against t32a
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24848020 	addiu	a0,a0,-32736
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24840020 	addiu	a0,a0,32
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	24848030 	addiu	a0,a0,-32720
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against _start
+#
+.*:	3c04ffff 	lui	a0,0xffff
+			.*: R_MIPS_HI16	_start
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	_start
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	_start
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	_start
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	_start
+.*:	24840000 	addiu	a0,a0,0
+			.*: R_MIPS_LO16	_start
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	_start
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	_start
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	_start
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	_start
+#
+# Relocations against tstarta
+#
+.*:	3c04ffff 	lui	a0,0xffff
+			.*: R_MIPS_GOT16	\.text
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24840000 	addiu	a0,a0,0
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against t32a
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24848020 	addiu	a0,a0,-32736
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24840020 	addiu	a0,a0,32
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	24848030 	addiu	a0,a0,-32720
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against sdg
+#
+.*:	2484fffc 	addiu	a0,a0,-4
+			.*: R_MIPS_GPREL16	sdg
+.*:	24840000 	addiu	a0,a0,0
+			.*: R_MIPS_GPREL16	sdg
+.*:	24840004 	addiu	a0,a0,4
+			.*: R_MIPS_GPREL16	sdg
+#
+# Relocations against sdla
+#
+.*:	2484801c 	addiu	a0,a0,-32740
+			.*: R_MIPS_GPREL16	\.sdata\+0x7ff0
+.*:	24848020 	addiu	a0,a0,-32736
+			.*: R_MIPS_GPREL16	\.sdata\+0x7ff0
+.*:	24848024 	addiu	a0,a0,-32732
+			.*: R_MIPS_GPREL16	\.sdata\+0x7ff0
+#
+# Relocations against tstarta
+#
+.*:	0fffffff 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c000000 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c000001 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+#
+# Relocations against t32a
+#
+.*:	0c000007 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c000008 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c000009 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+#
+# Relocations against _start
+#
+.*:	0fffffff 	jal	.*
+			.*: R_MIPS_26	_start
+.*:	00000000 	nop
+.*:	0c000000 	jal	.*
+			.*: R_MIPS_26	_start
+.*:	00000000 	nop
+.*:	0c000001 	jal	.*
+			.*: R_MIPS_26	_start
+.*:	00000000 	nop
+	\.\.\.
+
+.* <tstartb>:
+#
+# Relocations against tstartb
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24847fe0 	addiu	a0,a0,32736
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	2484fff0 	addiu	a0,a0,-16
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	24847fe0 	addiu	a0,a0,32736
+			.*: R_MIPS_LO16	\.text
+
+.* <t32b>:
+.*:	3c040002 	lui	a0,0x2
+			.*: R_MIPS_HI16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against t32b
+#
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	24840010 	addiu	a0,a0,16
+			.*: R_MIPS_LO16	\.text
+.*:	3c040002 	lui	a0,0x2
+			.*: R_MIPS_HI16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+.*:	3c040002 	lui	a0,0x2
+			.*: R_MIPS_HI16	\.text
+.*:	24848020 	addiu	a0,a0,-32736
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against _start
+#
+.*:	3c04ffff 	lui	a0,0xffff
+			.*: R_MIPS_HI16	_start
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	_start
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	_start
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	_start
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	_start
+.*:	24840000 	addiu	a0,a0,0
+			.*: R_MIPS_LO16	_start
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	_start
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	_start
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	_start
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	_start
+#
+# Relocations against tstartb
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24847fe0 	addiu	a0,a0,32736
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	2484fff0 	addiu	a0,a0,-16
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	24847fe0 	addiu	a0,a0,32736
+			.*: R_MIPS_LO16	\.text
+.*:	3c040002 	lui	a0,0x2
+			.*: R_MIPS_GOT16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against t32b
+#
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	24840010 	addiu	a0,a0,16
+			.*: R_MIPS_LO16	\.text
+.*:	3c040002 	lui	a0,0x2
+			.*: R_MIPS_GOT16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+.*:	3c040002 	lui	a0,0x2
+			.*: R_MIPS_GOT16	\.text
+.*:	24848020 	addiu	a0,a0,-32736
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against sdg
+#
+.*:	2484fffc 	addiu	a0,a0,-4
+			.*: R_MIPS_GPREL16	sdg
+.*:	24840000 	addiu	a0,a0,0
+			.*: R_MIPS_GPREL16	sdg
+.*:	24840004 	addiu	a0,a0,4
+			.*: R_MIPS_GPREL16	sdg
+#
+# Relocations against sdlb
+#
+.*:	2484803c 	addiu	a0,a0,-32708
+			.*: R_MIPS_GPREL16	\.sdata\+0x7ff0
+.*:	24848040 	addiu	a0,a0,-32704
+			.*: R_MIPS_GPREL16	\.sdata\+0x7ff0
+.*:	24848044 	addiu	a0,a0,-32700
+			.*: R_MIPS_GPREL16	\.sdata\+0x7ff0
+#
+# Relocations against tstartb
+#
+.*:	0c003ffb 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c003ffc 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c003ffd 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+#
+# Relocations against t32b
+#
+.*:	0c004003 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c004004 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c004005 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+#
+# Relocations against _start
+#
+.*:	0fffffff 	jal	.*
+			.*: R_MIPS_26	_start
+.*:	00000000 	nop
+.*:	0c000000 	jal	.*
+			.*: R_MIPS_26	_start
+.*:	00000000 	nop
+.*:	0c000001 	jal	.*
+			.*: R_MIPS_26	_start
+.*:	00000000 	nop
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-1a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-1a.s
new file mode 100644
index 0000000..5fcd4bb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-1a.s
@@ -0,0 +1,100 @@
+	.globl	_start
+	.globl	sdg
+	.set	noreorder
+	.ent	tstarta
+tstarta:
+_start:
+	lui	$4,%hi(tstarta - 0x8010)
+	addiu	$4,$4,%lo(tstarta - 0x8010)
+	lui	$4,%hi(tstarta - 0x8000)
+	addiu	$4,$4,%lo(tstarta - 0x8000)
+	lui	$4,%hi(tstarta)
+	addiu	$4,$4,%lo(tstarta)
+	lui	$4,%hi(tstarta + 0x7ff0)
+	addiu	$4,$4,%lo(tstarta + 0x7ff0)
+t32a:
+	lui	$4,%hi(tstarta + 0x8010)
+	addiu	$4,$4,%lo(tstarta + 0x8010)
+
+	lui	$4,%hi(t32a - 0x8010)
+	addiu	$4,$4,%lo(t32a - 0x8010)
+	lui	$4,%hi(t32a - 0x8000)
+	addiu	$4,$4,%lo(t32a - 0x8000)
+	lui	$4,%hi(t32a)
+	addiu	$4,$4,%lo(t32a)
+	lui	$4,%hi(t32a + 0x7ff0)
+	addiu	$4,$4,%lo(t32a + 0x7ff0)
+	lui	$4,%hi(t32a + 0x8010)
+	addiu	$4,$4,%lo(t32a + 0x8010)
+
+	lui	$4,%hi(_start - 0x8010)
+	addiu	$4,$4,%lo(_start - 0x8010)
+	lui	$4,%hi(_start - 0x8000)
+	addiu	$4,$4,%lo(_start - 0x8000)
+	lui	$4,%hi(_start)
+	addiu	$4,$4,%lo(_start)
+	lui	$4,%hi(_start + 0x7ff0)
+	addiu	$4,$4,%lo(_start + 0x7ff0)
+	lui	$4,%hi(_start + 0x8010)
+	addiu	$4,$4,%lo(_start + 0x8010)
+
+	lui	$4,%got(tstarta - 0x8010)
+	addiu	$4,$4,%lo(tstarta - 0x8010)
+	lui	$4,%got(tstarta - 0x8000)
+	addiu	$4,$4,%lo(tstarta - 0x8000)
+	lui	$4,%got(tstarta)
+	addiu	$4,$4,%lo(tstarta)
+	lui	$4,%got(tstarta + 0x7ff0)
+	addiu	$4,$4,%lo(tstarta + 0x7ff0)
+	lui	$4,%got(tstarta + 0x8010)
+	addiu	$4,$4,%lo(tstarta + 0x8010)
+
+	lui	$4,%got(t32a - 0x8010)
+	addiu	$4,$4,%lo(t32a - 0x8010)
+	lui	$4,%got(t32a - 0x8000)
+	addiu	$4,$4,%lo(t32a - 0x8000)
+	lui	$4,%got(t32a)
+	addiu	$4,$4,%lo(t32a)
+	lui	$4,%got(t32a + 0x7ff0)
+	addiu	$4,$4,%lo(t32a + 0x7ff0)
+	lui	$4,%got(t32a + 0x8010)
+	addiu	$4,$4,%lo(t32a + 0x8010)
+
+	addiu	$4,$4,%gp_rel(sdg - 4)
+	addiu	$4,$4,%gp_rel(sdg)
+	addiu	$4,$4,%gp_rel(sdg + 4)
+
+	addiu	$4,$4,%gp_rel(sdla - 4)
+	addiu	$4,$4,%gp_rel(sdla)
+	addiu	$4,$4,%gp_rel(sdla + 4)
+
+	jal	tstarta - 4
+	nop
+	jal	tstarta
+	nop
+	jal	tstarta + 4
+	nop
+
+	jal	t32a - 4
+	nop
+	jal	t32a
+	nop
+	jal	t32a + 4
+	nop
+
+	jal	_start - 4
+	nop
+	jal	_start
+	nop
+	jal	_start + 4
+	nop
+
+	.org	0xfff0
+
+	.end	tstarta
+
+	.section .sdata
+	.space	16
+sdg:
+sdla:
+	.space	16
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-1b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-1b.s
new file mode 100644
index 0000000..8b9544c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-1b.s
@@ -0,0 +1,95 @@
+	.set	noreorder
+	.ent	tstartb
+tstartb:
+	lui	$4,%hi(tstartb - 0x8010)	# .text + 0x7fe0
+	addiu	$4,$4,%lo(tstartb - 0x8010)
+	lui	$4,%hi(tstartb - 0x8000)	# .text + 0x7ff0
+	addiu	$4,$4,%lo(tstartb - 0x8000)
+	lui	$4,%hi(tstartb)			# .text + 0xfff0
+	addiu	$4,$4,%lo(tstartb)
+	lui	$4,%hi(tstartb + 0x7ff0)	# .text + 0x17fe0
+	addiu	$4,$4,%lo(tstartb + 0x7ff0)
+t32b:
+	lui	$4,%hi(tstartb + 0x8010)	# .text + 0x18000
+	addiu	$4,$4,%lo(tstartb + 0x8010)
+
+	lui	$4,%hi(t32b - 0x8010)		# .text + 0x8000
+	addiu	$4,$4,%lo(t32b - 0x8010)
+	lui	$4,%hi(t32b - 0x8000)		# .text + 0x8010
+	addiu	$4,$4,%lo(t32b - 0x8000)
+	lui	$4,%hi(t32b)			# .text + 0x10010
+	addiu	$4,$4,%lo(t32b)
+	lui	$4,%hi(t32b + 0x7ff0)		# .text + 0x18000
+	addiu	$4,$4,%lo(t32b + 0x7ff0)
+	lui	$4,%hi(t32b + 0x8010)		# .text + 0x18020
+	addiu	$4,$4,%lo(t32b + 0x8010)
+
+	lui	$4,%hi(_start - 0x8010)
+	addiu	$4,$4,%lo(_start - 0x8010)
+	lui	$4,%hi(_start - 0x8000)
+	addiu	$4,$4,%lo(_start - 0x8000)
+	lui	$4,%hi(_start)
+	addiu	$4,$4,%lo(_start)
+	lui	$4,%hi(_start + 0x7ff0)
+	addiu	$4,$4,%lo(_start + 0x7ff0)
+	lui	$4,%hi(_start + 0x8010)
+	addiu	$4,$4,%lo(_start + 0x8010)
+
+	lui	$4,%got(tstartb - 0x8010)	# .text + 0x7fe0
+	addiu	$4,$4,%lo(tstartb - 0x8010)
+	lui	$4,%got(tstartb - 0x8000)	# .text + 0x7ff0
+	addiu	$4,$4,%lo(tstartb - 0x8000)
+	lui	$4,%got(tstartb)			# .text + 0xfff0
+	addiu	$4,$4,%lo(tstartb)
+	lui	$4,%got(tstartb + 0x7ff0)	# .text + 0x17fe0
+	addiu	$4,$4,%lo(tstartb + 0x7ff0)
+	lui	$4,%got(tstartb + 0x8010)	# .text + 0x18000
+	addiu	$4,$4,%lo(tstartb + 0x8010)
+
+	lui	$4,%got(t32b - 0x8010)		# .text + 0x8000
+	addiu	$4,$4,%lo(t32b - 0x8010)
+	lui	$4,%got(t32b - 0x8000)		# .text + 0x8010
+	addiu	$4,$4,%lo(t32b - 0x8000)
+	lui	$4,%got(t32b)			# .text + 0x10010
+	addiu	$4,$4,%lo(t32b)
+	lui	$4,%got(t32b + 0x7ff0)		# .text + 0x18000
+	addiu	$4,$4,%lo(t32b + 0x7ff0)
+	lui	$4,%got(t32b + 0x8010)		# .text + 0x18020
+	addiu	$4,$4,%lo(t32b + 0x8010)
+
+	addiu	$4,$4,%gp_rel(sdg - 4)
+	addiu	$4,$4,%gp_rel(sdg)
+	addiu	$4,$4,%gp_rel(sdg + 4)
+
+	addiu	$4,$4,%gp_rel(sdlb - 4)
+	addiu	$4,$4,%gp_rel(sdlb)
+	addiu	$4,$4,%gp_rel(sdlb + 4)
+
+	jal	tstartb - 4			# .text + 0xffec
+	nop
+	jal	tstartb				# .text + 0xfff0
+	nop
+	jal	tstartb + 4			# .text + 0xfff4
+	nop
+
+	jal	t32b - 4			# .text + 0x1000c
+	nop
+	jal	t32b				# .text + 0x10010
+	nop
+	jal	t32b + 4			# .text + 0x10014
+	nop
+
+	jal	_start - 4
+	nop
+	jal	_start
+	nop
+	jal	_start + 4
+	nop
+
+	.space	16
+	.end	tstartb
+
+	.section .sdata
+	.space	16
+sdlb:
+	.space	16
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-2.d b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-2.d
new file mode 100644
index 0000000..740211e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-2.d
@@ -0,0 +1,169 @@
+#source: reloc-2a.s -EB -mabi=32
+#source: reloc-2b.s -EB -mabi=32
+#ld: --oformat=srec -Treloc-2.ld
+#objdump: -D -mmips:4000 --endian=big
+
+.*:     file format .*
+
+Disassembly of section .*:
+
+.* <.*>:
+#
+# Relocations against tstarta
+#
+.*:	3c040020 	lui	a0,0x20
+.*:	2484fff0 	addiu	a0,a0,-16
+.*:	3c040020 	lui	a0,0x20
+.*:	24840000 	addiu	a0,a0,0
+.*:	3c040021 	lui	a0,0x21
+.*:	24848000 	addiu	a0,a0,-32768
+.*:	3c040021 	lui	a0,0x21
+.*:	2484fff0 	addiu	a0,a0,-16
+.*:	3c040021 	lui	a0,0x21
+.*:	24840010 	addiu	a0,a0,16
+#
+# Relocations against t32a
+#
+.*:	3c040020 	lui	a0,0x20
+.*:	24840010 	addiu	a0,a0,16
+.*:	3c040020 	lui	a0,0x20
+.*:	24840020 	addiu	a0,a0,32
+.*:	3c040021 	lui	a0,0x21
+.*:	24848020 	addiu	a0,a0,-32736
+.*:	3c040021 	lui	a0,0x21
+.*:	24840010 	addiu	a0,a0,16
+.*:	3c040021 	lui	a0,0x21
+.*:	24840030 	addiu	a0,a0,48
+#
+# Relocations against _start
+#
+.*:	3c040020 	lui	a0,0x20
+.*:	2484fff0 	addiu	a0,a0,-16
+.*:	3c040020 	lui	a0,0x20
+.*:	24840000 	addiu	a0,a0,0
+.*:	3c040021 	lui	a0,0x21
+.*:	24848000 	addiu	a0,a0,-32768
+.*:	3c040021 	lui	a0,0x21
+.*:	2484fff0 	addiu	a0,a0,-16
+.*:	3c040021 	lui	a0,0x21
+.*:	24840010 	addiu	a0,a0,16
+#
+# Relocations against sdg
+#
+.*:	2484edd8 	addiu	a0,a0,-4648
+.*:	2484eddc 	addiu	a0,a0,-4644
+.*:	2484ede0 	addiu	a0,a0,-4640
+#
+# Relocations against sdla
+#
+.*:	2484edd8 	addiu	a0,a0,-4648
+.*:	2484eddc 	addiu	a0,a0,-4644
+.*:	2484ede0 	addiu	a0,a0,-4640
+#
+# Relocations against tstarta
+#
+.*:	0c081fff 	jal	0x207ffc
+.*:	00000000 	nop
+.*:	0c082000 	jal	0x208000
+.*:	00000000 	nop
+.*:	0c082001 	jal	0x208004
+.*:	00000000 	nop
+#
+# Relocations against t32a
+#
+.*:	0c082007 	jal	0x20801c
+.*:	00000000 	nop
+.*:	0c082008 	jal	0x208020
+.*:	00000000 	nop
+.*:	0c082009 	jal	0x208024
+.*:	00000000 	nop
+#
+# Relocations against _start
+#
+.*:	0c081fff 	jal	0x207ffc
+.*:	00000000 	nop
+.*:	0c082000 	jal	0x208000
+.*:	00000000 	nop
+.*:	0c082001 	jal	0x208004
+.*:	00000000 	nop
+	\.\.\.
+#
+# Relocations against tstartb
+#
+.*:	3c040021 	lui	a0,0x21
+.*:	2484ffe0 	addiu	a0,a0,-32
+.*:	3c040021 	lui	a0,0x21
+.*:	2484fff0 	addiu	a0,a0,-16
+.*:	3c040021 	lui	a0,0x21
+.*:	24847ff0 	addiu	a0,a0,32752
+.*:	3c040022 	lui	a0,0x22
+.*:	2484ffe0 	addiu	a0,a0,-32
+.*:	3c040022 	lui	a0,0x22
+.*:	24840000 	addiu	a0,a0,0
+#
+# Relocations against t32b
+#
+.*:	3c040021 	lui	a0,0x21
+.*:	24840000 	addiu	a0,a0,0
+.*:	3c040021 	lui	a0,0x21
+.*:	24840010 	addiu	a0,a0,16
+.*:	3c040022 	lui	a0,0x22
+.*:	24848010 	addiu	a0,a0,-32752
+.*:	3c040022 	lui	a0,0x22
+.*:	24840000 	addiu	a0,a0,0
+.*:	3c040022 	lui	a0,0x22
+.*:	24840020 	addiu	a0,a0,32
+#
+# Relocations against _start
+#
+.*:	3c040020 	lui	a0,0x20
+.*:	2484fff0 	addiu	a0,a0,-16
+.*:	3c040020 	lui	a0,0x20
+.*:	24840000 	addiu	a0,a0,0
+.*:	3c040021 	lui	a0,0x21
+.*:	24848000 	addiu	a0,a0,-32768
+.*:	3c040021 	lui	a0,0x21
+.*:	2484fff0 	addiu	a0,a0,-16
+.*:	3c040021 	lui	a0,0x21
+.*:	24840010 	addiu	a0,a0,16
+#
+# Relocations against sdg
+#
+.*:	2484edd8 	addiu	a0,a0,-4648
+.*:	2484eddc 	addiu	a0,a0,-4644
+.*:	2484ede0 	addiu	a0,a0,-4640
+#
+# Relocations against sdl2
+#
+.*:	2484edf8 	addiu	a0,a0,-4616
+.*:	2484edfc 	addiu	a0,a0,-4612
+.*:	2484ee00 	addiu	a0,a0,-4608
+#
+# Relocations against tstartb
+#
+.*:	0c085ffb 	jal	0x217fec
+.*:	00000000 	nop
+.*:	0c085ffc 	jal	0x217ff0
+.*:	00000000 	nop
+.*:	0c085ffd 	jal	0x217ff4
+.*:	00000000 	nop
+#
+# Relocations against t32b
+#
+.*:	0c086003 	jal	0x21800c
+.*:	00000000 	nop
+.*:	0c086004 	jal	0x218010
+.*:	00000000 	nop
+.*:	0c086005 	jal	0x218014
+.*:	00000000 	nop
+#
+# Relocations against _start
+#
+.*:	0c081fff 	jal	0x207ffc
+.*:	00000000 	nop
+.*:	0c082000 	jal	0x208000
+.*:	00000000 	nop
+.*:	0c082001 	jal	0x208004
+.*:	00000000 	nop
+	\.\.\.
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-2.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-2.ld
new file mode 100644
index 0000000..ff0b291
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-2.ld
@@ -0,0 +1,9 @@
+SECTIONS
+{
+  . = 0x208000;
+  .text : { *(.text) }
+  . = 0x400000;
+  _gp = 0x401234;
+  .sdata : { *(.sdata) }
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-2a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-2a.s
new file mode 100644
index 0000000..0ea830a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-2a.s
@@ -0,0 +1,78 @@
+	.globl	_start
+	.globl	sdg
+	.set	noreorder
+	.ent	tstarta
+tstarta:
+_start:
+	lui	$4,%hi(tstarta - 0x8010)
+	addiu	$4,$4,%lo(tstarta - 0x8010)
+	lui	$4,%hi(tstarta - 0x8000)
+	addiu	$4,$4,%lo(tstarta - 0x8000)
+	lui	$4,%hi(tstarta)
+	addiu	$4,$4,%lo(tstarta)
+	lui	$4,%hi(tstarta + 0x7ff0)
+	addiu	$4,$4,%lo(tstarta + 0x7ff0)
+t32a:
+	lui	$4,%hi(tstarta + 0x8010)
+	addiu	$4,$4,%lo(tstarta + 0x8010)
+
+	lui	$4,%hi(t32a - 0x8010)
+	addiu	$4,$4,%lo(t32a - 0x8010)
+	lui	$4,%hi(t32a - 0x8000)
+	addiu	$4,$4,%lo(t32a - 0x8000)
+	lui	$4,%hi(t32a)
+	addiu	$4,$4,%lo(t32a)
+	lui	$4,%hi(t32a + 0x7ff0)
+	addiu	$4,$4,%lo(t32a + 0x7ff0)
+	lui	$4,%hi(t32a + 0x8010)
+	addiu	$4,$4,%lo(t32a + 0x8010)
+
+	lui	$4,%hi(_start - 0x8010)
+	addiu	$4,$4,%lo(_start - 0x8010)
+	lui	$4,%hi(_start - 0x8000)
+	addiu	$4,$4,%lo(_start - 0x8000)
+	lui	$4,%hi(_start)
+	addiu	$4,$4,%lo(_start)
+	lui	$4,%hi(_start + 0x7ff0)
+	addiu	$4,$4,%lo(_start + 0x7ff0)
+	lui	$4,%hi(_start + 0x8010)
+	addiu	$4,$4,%lo(_start + 0x8010)
+
+	addiu	$4,$4,%gp_rel(sdg - 4)
+	addiu	$4,$4,%gp_rel(sdg)
+	addiu	$4,$4,%gp_rel(sdg + 4)
+
+	addiu	$4,$4,%gp_rel(sdla - 4)
+	addiu	$4,$4,%gp_rel(sdla)
+	addiu	$4,$4,%gp_rel(sdla + 4)
+
+	jal	tstarta - 4
+	nop
+	jal	tstarta
+	nop
+	jal	tstarta + 4
+	nop
+
+	jal	t32a - 4
+	nop
+	jal	t32a
+	nop
+	jal	t32a + 4
+	nop
+
+	jal	_start - 4
+	nop
+	jal	_start
+	nop
+	jal	_start + 4
+	nop
+
+	.org	0xfff0
+
+	.end	tstarta
+
+	.section .sdata
+	.space	16
+sdg:
+sdla:
+	.space	16
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-2b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-2b.s
new file mode 100644
index 0000000..3a9d694
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-2b.s
@@ -0,0 +1,73 @@
+	.set	noreorder
+	.ent	tstartb
+tstartb:
+	lui	$4,%hi(tstartb - 0x8010)	# .text + 0x7fe0
+	addiu	$4,$4,%lo(tstartb - 0x8010)
+	lui	$4,%hi(tstartb - 0x8000)	# .text + 0x7ff0
+	addiu	$4,$4,%lo(tstartb - 0x8000)
+	lui	$4,%hi(tstartb)			# .text + 0xfff0
+	addiu	$4,$4,%lo(tstartb)
+	lui	$4,%hi(tstartb + 0x7ff0)	# .text + 0x17fe0
+	addiu	$4,$4,%lo(tstartb + 0x7ff0)
+t32b:
+	lui	$4,%hi(tstartb + 0x8010)	# .text + 0x18000
+	addiu	$4,$4,%lo(tstartb + 0x8010)
+
+	lui	$4,%hi(t32b - 0x8010)		# .text + 0x8000
+	addiu	$4,$4,%lo(t32b - 0x8010)
+	lui	$4,%hi(t32b - 0x8000)		# .text + 0x8010
+	addiu	$4,$4,%lo(t32b - 0x8000)
+	lui	$4,%hi(t32b)			# .text + 0x10010
+	addiu	$4,$4,%lo(t32b)
+	lui	$4,%hi(t32b + 0x7ff0)		# .text + 0x18000
+	addiu	$4,$4,%lo(t32b + 0x7ff0)
+	lui	$4,%hi(t32b + 0x8010)		# .text + 0x18020
+	addiu	$4,$4,%lo(t32b + 0x8010)
+
+	lui	$4,%hi(_start - 0x8010)
+	addiu	$4,$4,%lo(_start - 0x8010)
+	lui	$4,%hi(_start - 0x8000)
+	addiu	$4,$4,%lo(_start - 0x8000)
+	lui	$4,%hi(_start)
+	addiu	$4,$4,%lo(_start)
+	lui	$4,%hi(_start + 0x7ff0)
+	addiu	$4,$4,%lo(_start + 0x7ff0)
+	lui	$4,%hi(_start + 0x8010)
+	addiu	$4,$4,%lo(_start + 0x8010)
+
+	addiu	$4,$4,%gp_rel(sdg - 4)
+	addiu	$4,$4,%gp_rel(sdg)
+	addiu	$4,$4,%gp_rel(sdg + 4)
+
+	addiu	$4,$4,%gp_rel(sdlb - 4)
+	addiu	$4,$4,%gp_rel(sdlb)
+	addiu	$4,$4,%gp_rel(sdlb + 4)
+
+	jal	tstartb - 4			# .text + 0xffec
+	nop
+	jal	tstartb				# .text + 0xfff0
+	nop
+	jal	tstartb + 4			# .text + 0xfff4
+	nop
+
+	jal	t32b - 4			# .text + 0x1000c
+	nop
+	jal	t32b				# .text + 0x10010
+	nop
+	jal	t32b + 4			# .text + 0x10014
+	nop
+
+	jal	_start - 4
+	nop
+	jal	_start
+	nop
+	jal	_start + 4
+	nop
+
+	.space	16
+	.end	tstartb
+
+	.section .sdata
+	.space	16
+sdlb:
+	.space	16
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-3-n32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-3-n32.d
new file mode 100644
index 0000000..e90180b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-3-n32.d
@@ -0,0 +1,18 @@
+#name: R_MIPS16_GPREL reloc n32
+#source: ../../../gas/testsuite/gas/mips/elf-rel6.s
+#as: -march=mips64 -mabi=n32 -EB
+#objdump: --prefix-addresses -tdr --show-raw-insn
+#ld: -Ttext 0x20000000 -e 0x20000000 -N -melf32btsmipn32
+
+
+.*:     file format elf.*mips.*
+
+#...
+
+Disassembly of section \.text:
+0*20000000 <[^>]*> f010 8352 	lb	v0,-32750\(v1\)
+0*20000004 <[^>]*> f010 8353 	lb	v0,-32749\(v1\)
+0*20000008 <[^>]*> f252 8346 	lb	v0,-28090\(v1\)
+0*2000000c <[^>]*> 6500      	nop
+0*2000000e <[^>]*> 6500      	nop
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-3.d b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-3.d
new file mode 100644
index 0000000..1ec51c5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-3.d
@@ -0,0 +1,16 @@
+#name: R_MIPS16_GPREL reloc
+#source: ../../../gas/testsuite/gas/mips/elf-rel6.s
+#objdump: --prefix-addresses -tdr --show-raw-insn
+#ld: -Ttext 0x20000000 -e 0x20000000 -N
+
+.*:     file format elf.*mips.*
+
+#...
+
+Disassembly of section \.text:
+0*20000000 <[^>]*> f010 8352 	lb	v0,-32750\(v1\)
+0*20000004 <[^>]*> f010 8353 	lb	v0,-32749\(v1\)
+0*20000008 <[^>]*> f252 8346 	lb	v0,-28090\(v1\)
+0*2000000c <[^>]*> 6500      	nop
+0*2000000e <[^>]*> 6500      	nop
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-4.d b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-4.d
new file mode 100644
index 0000000..936a861
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-4.d
@@ -0,0 +1,3 @@
+#source: reloc-4.s
+#ld:
+#error: small-data section exceeds 64KB.*truncated to fit: R_MIPS_LITERAL
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-4.s b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-4.s
new file mode 100644
index 0000000..061fa80
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-4.s
@@ -0,0 +1,7 @@
+	.text
+	.globl	_start
+_start:
+        li.d    $f2,1.10000000000000000000e0
+
+	.section .sdata
+	.space 0x10000
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-5.d b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-5.d
new file mode 100644
index 0000000..2fc74ea
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-5.d
@@ -0,0 +1,3 @@
+#source: reloc-5.s
+#ld:
+#error: small-data section exceeds 64KB.*truncated to fit: R_MIPS_GPREL16
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-5.s b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-5.s
new file mode 100644
index 0000000..a4b31b7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-5.s
@@ -0,0 +1,11 @@
+	.text
+	.globl	_start
+_start:
+        lw	$2, %gp_rel(i)($28)
+
+	.section .sdata
+	.space 0x10000
+
+	.section .sbss
+i:
+	.space	4
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-estimate-1.d b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-estimate-1.d
new file mode 100644
index 0000000..0d49b05
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-estimate-1.d
@@ -0,0 +1,18 @@
+#name: MIPS reloc estimation 1
+#source: reloc-estimate-1a.s
+#source: reloc-estimate-1b.s
+#ld: -shared -T reloc-estimate-1.ld
+#objdump: -R -sj.foo
+
+.*
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+00000000 R_MIPS_NONE       \*ABS\*
+00010000 R_MIPS_REL32      foo
+
+
+# The address must be 0x810.  We should only ever allocate one dynamic
+# reloc over and above the first R_MIPS_NONE entry.
+Contents of section \.foo:
+ 0810 (deadbeef|efbeadde)                             ....            
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-estimate-1.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-estimate-1.ld
new file mode 100644
index 0000000..776e503
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-estimate-1.ld
@@ -0,0 +1,29 @@
+SECTIONS
+{
+  . = 0;
+  .reginfo : { *(.reginfo) }
+
+  . = ALIGN (0x400);
+  .dynamic : { *(.dynamic) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+
+  . = ALIGN (0x400);
+  .rel.dyn : { *(.rel.dyn) }
+  .foo : { *(.foo) }
+  .text : { *(.text) }
+
+  . = ALIGN (0x400);
+  .MIPS.stubs : { *(.MIPS.stubs) }
+
+  . = ALIGN (0x10000);
+  .data : { *(.data) }
+
+  . = ALIGN (0x400);
+  _gp = . + 0x7ff0;
+  .got : { *(.got) }
+}
+
+VERSION {
+  V2 { global: foo; local: *; };
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-estimate-1a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-estimate-1a.s
new file mode 100644
index 0000000..564c62a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-estimate-1a.s
@@ -0,0 +1,6 @@
+	.section .foo,"a",@progbits
+	.word	0xdeadbeef
+
+	.abicalls
+	.data
+	.word	foo
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-estimate-1b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-estimate-1b.s
new file mode 100644
index 0000000..dd308b4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-estimate-1b.s
@@ -0,0 +1,7 @@
+	.abicalls
+	.symver	foo2,foo@@V2
+	.global	foo2
+	.data
+	.type	foo2,%object
+	.size	foo2,4
+foo2:	.word	0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-merge-lo16.d b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-merge-lo16.d
new file mode 100644
index 0000000..7cb3cfe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-merge-lo16.d
@@ -0,0 +1,16 @@
+#name: MIPS ELF lo16 merge
+#source: reloc-merge-lo16.s
+#ld: -Treloc-merge-lo16.ld
+#objdump: -td --prefix-addresses --show-raw-insn
+
+# Test lo16 reloc calculation with string merging.
+
+.*: +file format .*mips.*
+#...
+0+80fe70 l       .rodata	0+000000 g
+0+400000 g     F .text	0+00000c __start
+#...
+0+400000 <[^>]*> 3c020081 	lui	v0,0x81
+0+400004 <[^>]*> 2443fe70 	addiu	v1,v0,-400
+0+400008 <[^>]*> 2442fe70 	addiu	v0,v0,-400
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-merge-lo16.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-merge-lo16.ld
new file mode 100644
index 0000000..4d487dd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-merge-lo16.ld
@@ -0,0 +1,9 @@
+ENTRY(__start)
+SECTIONS
+{
+  . = 0x0400000;
+  .text : { *(.text) }
+  . = 0x0800000;
+  .rodata : { *(.rodata.*) }
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-merge-lo16.s b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-merge-lo16.s
new file mode 100644
index 0000000..33158b1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/reloc-merge-lo16.s
@@ -0,0 +1,28 @@
+	.section .rodata.str1.4,"aMS", @progbits, 1
+	.macro	fillstr char
+	.rept	0x3fff - \char
+	.byte	\char
+	.endr
+	.byte	0
+	.endm
+	fillstr	'a'
+	fillstr	'h'
+	fillstr	'c'
+	fillstr	'd'
+	fillstr	'g'
+	fillstr	'f'
+g:
+	fillstr	'g'
+	fillstr	'h'
+
+	.text
+	.globl	__start
+	.ent	__start
+	.type	__start, @function
+__start:
+	lui	$2, %hi(g)
+	addiu	$3, $2, %lo(g)
+	addiu	$2, $2, %lo(g)
+	.end	__start
+
+	.space	16
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1-10000.d b/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1-10000.d
new file mode 100644
index 0000000..b59bb5f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1-10000.d
@@ -0,0 +1,18 @@
+
+.*:     file format elf32-tradbigmips
+
+Disassembly of section \.MIPS\.stubs:
+
+.* <\.MIPS.stubs>:
+.*:	8f998010 	lw	t9,-32752\(gp\)
+.*:	03e07821 	move	t7,ra
+.*:	3c180001 	lui	t8,0x1
+.*:	0320f809 	jalr	t9
+.*:	37180000 	ori	t8,t8,0x0
+.*:	00000000 	nop
+.*:	00000000 	nop
+.*:	00000000 	nop
+.*:	00000000 	nop
+.*:	00000000 	nop
+Disassembly of section .text:
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1-2fe80.d b/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1-2fe80.d
new file mode 100644
index 0000000..07ca1a2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1-2fe80.d
@@ -0,0 +1,18 @@
+
+.*:     file format elf32-tradbigmips
+
+Disassembly of section \.MIPS\.stubs:
+
+.* <\.MIPS.stubs>:
+.*:	8f998010 	lw	t9,-32752\(gp\)
+.*:	03e07821 	move	t7,ra
+.*:	3c180002 	lui	t8,0x2
+.*:	0320f809 	jalr	t9
+.*:	3718fe80 	ori	t8,t8,0xfe80
+.*:	00000000 	nop
+.*:	00000000 	nop
+.*:	00000000 	nop
+.*:	00000000 	nop
+.*:	00000000 	nop
+Disassembly of section .text:
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1-7fff.d b/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1-7fff.d
new file mode 100644
index 0000000..bfc94c5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1-7fff.d
@@ -0,0 +1,16 @@
+
+.*:     file format elf32-tradbigmips
+
+Disassembly of section \.MIPS\.stubs:
+
+.* <\.MIPS.stubs>:
+.*:	8f998010 	lw	t9,-32752\(gp\)
+.*:	03e07821 	move	t7,ra
+.*:	0320f809 	jalr	t9
+.*:	24187fff 	li	t8,32767
+.*:	00000000 	nop
+.*:	00000000 	nop
+.*:	00000000 	nop
+.*:	00000000 	nop
+Disassembly of section .text:
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1-8000.d b/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1-8000.d
new file mode 100644
index 0000000..2861ac2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1-8000.d
@@ -0,0 +1,16 @@
+
+.*:     file format elf32-tradbigmips
+
+Disassembly of section \.MIPS\.stubs:
+
+.* <\.MIPS.stubs>:
+.*:	8f998010 	lw	t9,-32752\(gp\)
+.*:	03e07821 	move	t7,ra
+.*:	0320f809 	jalr	t9
+.*:	34188000 	li	t8,0x8000
+.*:	00000000 	nop
+.*:	00000000 	nop
+.*:	00000000 	nop
+.*:	00000000 	nop
+Disassembly of section .text:
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1-fff0.d b/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1-fff0.d
new file mode 100644
index 0000000..440d32a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1-fff0.d
@@ -0,0 +1,16 @@
+
+.*:     file format elf32-tradbigmips
+
+Disassembly of section \.MIPS\.stubs:
+
+.* <\.MIPS.stubs>:
+.*:	8f998010 	lw	t9,-32752\(gp\)
+.*:	03e07821 	move	t7,ra
+.*:	0320f809 	jalr	t9
+.*:	3418fff0 	li	t8,0xfff0
+.*:	00000000 	nop
+.*:	00000000 	nop
+.*:	00000000 	nop
+.*:	00000000 	nop
+Disassembly of section .text:
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld
new file mode 100644
index 0000000..17c998d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld
@@ -0,0 +1,17 @@
+SECTIONS
+{
+  . = 0x80000;
+  .interp : { *(.interp) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+  .rel.dyn : { *(.rel.dyn) }
+  .MIPS.stubs : { *(.MIPS.stubs) }
+  .text : { *(.text) }
+
+  . = ALIGN (0x10000);
+  _gp = . + 0x7ff0;
+  .got : { *(.got) }
+
+  /DISCARD/ : { *(.reginfo) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1.s
new file mode 100644
index 0000000..15d2e1b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/stub-dynsym-1.s
@@ -0,0 +1,10 @@
+	.macro	decl
+	.global	exported\@
+	.equ	exported\@,\@
+	.endm
+
+	.rept	dynsym - base_syms
+	decl
+	.endr
+
+	lw	$25,%call16(foo)($gp)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/textrel-1.d b/binutils-2.19/ld/testsuite/ld-mips-elf/textrel-1.d
new file mode 100644
index 0000000..16bd727
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/textrel-1.d
@@ -0,0 +1,25 @@
+#name: MIPS textrel-1
+#source: textrel-1.s
+#as: -EB -n32
+#ld: -shared -melf32btsmipn32
+#readelf: -d
+
+Dynamic section at offset .* contains 17 entries:
+  Tag        Type                         Name/Value
+ 0x00000004 \(HASH\)                       0x[0-9a-f]*
+ 0x00000005 \(STRTAB\)                     0x[0-9a-f]*
+ 0x00000006 \(SYMTAB\)                     0x[0-9a-f]*
+ 0x0000000a \(STRSZ\)                      [0-9]* \(bytes\)
+ 0x0000000b \(SYMENT\)                     16 \(bytes\)
+ 0x00000003 \(PLTGOT\)                     0x[0-9a-f]*
+ 0x00000011 \(REL\)                        0x[0-9a-f]*
+ 0x00000012 \(RELSZ\)                      8 \(bytes\)
+ 0x00000013 \(RELENT\)                     8 \(bytes\)
+ 0x70000001 \(MIPS_RLD_VERSION\)           1
+ 0x70000005 \(MIPS_FLAGS\)                 NOTPOT
+ 0x70000006 \(MIPS_BASE_ADDRESS\)          0
+ 0x7000000a \(MIPS_LOCAL_GOTNO\)           [0-9]*
+ 0x70000011 \(MIPS_SYMTABNO\)              [0-9]*
+ 0x70000012 \(MIPS_UNREFEXTNO\)            [0-9]*
+ 0x70000013 \(MIPS_GOTSYM\)                0x[0-9a-f]*
+ 0x00000000 \(NULL\)                       0x0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/textrel-1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/textrel-1.s
new file mode 100644
index 0000000..f6b4a6a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/textrel-1.s
@@ -0,0 +1,9 @@
+        .globl foo
+foo:
+        .cfi_startproc
+        nop
+        .cfi_def_cfa_offset 4
+        nop
+        .cfi_register $29, $0
+        nop
+        .cfi_endproc
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden2-got.d b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden2-got.d
new file mode 100644
index 0000000..9c252ee
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden2-got.d
@@ -0,0 +1,5 @@
+
+.*file format.*
+
+Contents of section \.got:
+ *[0-9a-f]* 00000000 80000000 00000ba8          *\..*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden2.d b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden2.d
new file mode 100644
index 0000000..58e6eac
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden2.d
@@ -0,0 +1,10 @@
+
+.*file format.*
+
+Disassembly of section \.text:
+
+.* <.*>:
+.*:	8f828018 *	lw	v0,-32744\(gp\)
+	\.\.\.
+.*:	8f828018 *	lw	v0,-32744\(gp\)
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden2a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden2a.s
new file mode 100644
index 0000000..91a0b9e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden2a.s
@@ -0,0 +1,11 @@
+	.text
+	lw	$2,%gottprel(tls_hidden)($28)
+
+	.section .tdata,"awT"
+	.globl	tls_hidden
+	.hidden	tls_hidden
+	.type	tls_hidden,@object
+	.size	tls_hidden,4
+	.space	0xba8
+tls_hidden:
+	.word	1
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden2b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden2b.s
new file mode 100644
index 0000000..6a8e190
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden2b.s
@@ -0,0 +1,2 @@
+	.text
+	lw	$2,%gottprel(tls_hidden)($28)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3.d b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3.d
new file mode 100644
index 0000000..06a0c66
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3.d
@@ -0,0 +1,24 @@
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+#
+# The TLS entries are ordered as follows:
+#
+#	foo0	(-0x7ff0 + 0x20)
+#	foo2	(-0x7ff0 + 0x24)
+#	foo3	(-0x7ff0 + 0x28)
+#	foo1	(-0x7ff0 + 0x2c)
+#
+# Any order would be acceptable, but it must match the .got dump.
+#
+00080c00 <\.text>:
+   80c00:	8f84801c 	lw	a0,-32740\(gp\)
+   80c04:	8f848028 	lw	a0,-32728\(gp\)
+   80c08:	8f848020 	lw	a0,-32736\(gp\)
+   80c0c:	8f848024 	lw	a0,-32732\(gp\)
+   80c10:	8f84801c 	lw	a0,-32740\(gp\)
+   80c14:	8f848028 	lw	a0,-32728\(gp\)
+   80c18:	8f848020 	lw	a0,-32736\(gp\)
+   80c1c:	8f848024 	lw	a0,-32732\(gp\)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3.got b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3.got
new file mode 100644
index 0000000..282a027
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3.got
@@ -0,0 +1,23 @@
+
+.*:     file format .*
+
+#
+# The GOT layout is:
+#
+#	- 2 reserved entries
+#	- 5 local page entries
+#	- 1 global entry for "undef"
+#	- 4 TLS entries
+#
+# The order of the TLS entries is:
+#
+#	foo0	(offset 0x20)
+#	foo2	(offset 0x24)
+#	foo3	(offset 0x28)
+#	foo1	(offset 0x2c)
+#
+# Any order would be acceptable, but it must match the .d dump.
+#
+Contents of section \.got:
+ 90000 00000000 80000000 00000000 0000abc0  .*
+ 90010 0000abc8 0000abcc 0000abc4           .*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3.ld
new file mode 100644
index 0000000..261edce
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3.ld
@@ -0,0 +1,28 @@
+SECTIONS
+{
+  . = 0x80000;
+  .interp : { *(.interp) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+
+  . = ALIGN (0x400);
+  .rel.dyn : { *(.rel.dyn) }
+
+  . = ALIGN (0x400) + 0x400;
+  .text : { *(.text) }
+
+  . = ALIGN (0x10000);
+  _gp = . + 0x7ff0;
+  .got : { *(.got) }
+
+  . = ALIGN (0x400);
+  .tdata : { *(.tdata) }
+
+  /DISCARD/ : { *(.reginfo) }
+}
+
+VERSION
+{
+  { local: *; };
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3.r b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3.r
new file mode 100644
index 0000000..e7b7665
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3.r
@@ -0,0 +1,13 @@
+
+Relocation section '\.rel\.dyn' at offset .* contains 6 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name
+00000000  00000000 R_MIPS_NONE      
+#
+# The order of the next four entries doesn't matter.  The important thing
+# is that there is exactly one entry per GOT TLS slot.
+#
+0009000c  0000002f R_MIPS_TLS_TPREL3
+00090010  0000002f R_MIPS_TLS_TPREL3
+00090014  0000002f R_MIPS_TLS_TPREL3
+00090018  0000002f R_MIPS_TLS_TPREL3
+00090020  .*03 R_MIPS_REL32      00000000   undef
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3a.s
new file mode 100644
index 0000000..d1e6d64
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3a.s
@@ -0,0 +1,10 @@
+	.macro	load
+	lw	$4,%gottprel(foo\@)($gp)
+	.endm
+
+	.rept	4
+	load
+	.endr
+
+	.section .tdata,"awT",@progbits
+	.fill	0xabc0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3b.s
new file mode 100644
index 0000000..0744b07
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden3b.s
@@ -0,0 +1,18 @@
+	.macro	load
+	.text
+	lw	$4,%gottprel(foo\@)($gp)
+
+	.global foo\@
+	.type   foo\@,@object
+	.size   foo\@,4
+	.section .tdata,"awT",@progbits
+foo\@:
+	.word   \@
+	.endm
+
+	.rept	4
+	load
+	.endr
+
+	.data
+	.word	undef
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden4.got b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden4.got
new file mode 100644
index 0000000..e6b2115
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden4.got
@@ -0,0 +1,29 @@
+
+.*:     file format .*
+
+Contents of section \.got:
+#
+# The order of the TLS entries in this GOT is:
+#
+#     foo2
+#     foo3
+#     foo0
+#     foo1
+#
+# The order and address don't matter; the important thing is that the
+# addresses match the relocs in the .r dump and that there is a separate
+# entry for each symbol.
+#
+#...
+ 1c4010 00000000 0000abc8 0000abcc 0000abc0  .*
+ 1c4020 0000abc4 00000000 80000000 00000000  .*
+#
+# Likewise, but the order of the entries in this GOT is:
+#
+#     foo3
+#     foo2
+#     foo0
+#     foo1
+#...
+ 1d0020 00000000 00000000 00000000 0000abcc  .*
+ 1d0030 0000abc8 0000abc0 0000abc4           .*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden4.r b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden4.r
new file mode 100644
index 0000000..ccf2e80
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden4.r
@@ -0,0 +1,19 @@
+
+Relocation section '\.rel\.dyn' at offset .* contains .* entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name
+00000000  00000000 R_MIPS_NONE      
+#
+# The order and addresses of the next eight entries don't matter.  The
+# important thing is that there is exactly one entry per GOT TLS slot
+# and that the addresses match those in the .got dump.
+#
+001c4014  0000002f R_MIPS_TLS_TPREL3
+001c4018  0000002f R_MIPS_TLS_TPREL3
+001c401c  0000002f R_MIPS_TLS_TPREL3
+001c4020  0000002f R_MIPS_TLS_TPREL3
+001d002c  0000002f R_MIPS_TLS_TPREL3
+001d0030  0000002f R_MIPS_TLS_TPREL3
+001d0034  0000002f R_MIPS_TLS_TPREL3
+001d0038  0000002f R_MIPS_TLS_TPREL3
+.* R_MIPS_REL32 .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden4a.s b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden4a.s
new file mode 100644
index 0000000..02a0d35
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden4a.s
@@ -0,0 +1,18 @@
+	.macro	load
+	lw	$4,%gottprel(foo\@)($gp)
+	.endm
+
+	.rept	4
+	load
+	.endr
+
+	.macro	load2
+	lw	$4,%got(undefa\@)($gp)
+	.endm
+
+	.rept	0x3000
+	load2
+	.endr
+
+	.section .tdata,"awT",@progbits
+	.fill	0xabc0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden4b.s b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden4b.s
new file mode 100644
index 0000000..d6deb00
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-hidden4b.s
@@ -0,0 +1,27 @@
+	.macro	load
+	.text
+	lw	$4,%gottprel(foo\@)($gp)
+
+	.global foo\@
+	.type   foo\@,@object
+	.size   foo\@,4
+	.section .tdata,"awT",@progbits
+foo\@:
+	.word   \@
+	.endm
+
+	.rept	4
+	load
+	.endr
+
+	.text
+	.macro	load2
+	lw	$4,%got(undefb\@)($gp)
+	.endm
+
+	.rept	0x3000
+	load2
+	.endr
+
+	.data
+	.word	undef
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-multi-got-1-1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-multi-got-1-1.s
new file mode 100644
index 0000000..60f6717
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-multi-got-1-1.s
@@ -0,0 +1,39 @@
+.macro	one_sym	count
+.globl	sym_1_\count
+sym_1_\count:
+	la	$2, sym_1_\count
+.endm
+
+.irp	thou,0,1,2,3,4,5,6,7,8,9
+.irp	hund,0,1,2,3,4,5,6,7,8,9
+.irp	tens,0,1,2,3,4,5,6,7,8,9
+.irp	ones,0,1,2,3,4,5,6,7,8,9
+one_sym	\thou\hund\tens\ones
+.endr
+.endr
+.endr
+.endr
+
+tls_bits_1:
+	addiu	$4,$28,%tlsgd(tlsvar_gd)
+	addiu	$4,$28,%tlsldm(tlsvar_ld)
+	addiu	$4,$2,%gottprel(tlsvar_ie)
+
+        .section                .tbss,"awT",@nobits
+        .align  2
+        .global tlsvar_gd
+        .type   tlsvar_gd,@object
+        .size   tlsvar_gd,4
+tlsvar_gd:
+        .space  4
+        .global tlsvar_ie
+        .type   tlsvar_ie,@object
+        .size   tlsvar_ie,4
+tlsvar_ie:
+        .space  4
+        .global tlsvar_ld
+        .hidden tlsvar_ld
+        .type   tlsvar_ld,@object
+        .size   tlsvar_ld,4
+tlsvar_ld:
+        .word   1
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-multi-got-1-2.s b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-multi-got-1-2.s
new file mode 100644
index 0000000..6b04b98
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-multi-got-1-2.s
@@ -0,0 +1,20 @@
+.macro	one_sym	count
+.globl	sym_2_\count
+sym_2_\count:
+	la	$2, sym_2_\count
+.endm
+
+.irp	thou,0,1,2,3,4,5,6,7,8,9
+.irp	hund,0,1,2,3,4,5,6,7,8,9
+.irp	tens,0,1,2,3,4,5,6,7,8,9
+.irp	ones,0,1,2,3,4,5,6,7,8,9
+one_sym	\thou\hund\tens\ones
+.endr
+.endr
+.endr
+.endr
+
+tls_bits_2:
+	addiu	$4,$28,%tlsgd(tlsvar_gd)
+	addiu	$4,$28,%tlsldm(tlsvar_ld)
+	addiu	$4,$2,%gottprel(tlsvar_ie)
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-multi-got-1.d b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-multi-got-1.d
new file mode 100644
index 0000000..147dc83
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-multi-got-1.d
@@ -0,0 +1,20 @@
+
+.*:     file format elf32-tradbigmips
+
+Disassembly of section .text:
+
+#...
+[0-9a-f]+ <tls_bits_1>:
+   [0-9a-f]+:	27841c64 	addiu	a0,gp,7268
+   [0-9a-f]+:	27841c58 	addiu	a0,gp,7256
+   [0-9a-f]+:	24441c60 	addiu	a0,v0,7264
+   [0-9a-f]+:	00000000 	nop
+
+[0-9a-f]+ <sym_2_0000>:
+#...
+[0-9a-f]+ <tls_bits_2>:
+   [0-9a-f]+:	27841c64 	addiu	a0,gp,7268
+   [0-9a-f]+:	27841c58 	addiu	a0,gp,7256
+   [0-9a-f]+:	24441c60 	addiu	a0,v0,7264
+   [0-9a-f]+:	00000000 	nop
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-multi-got-1.got b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-multi-got-1.got
new file mode 100644
index 0000000..b62d413
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-multi-got-1.got
@@ -0,0 +1,36 @@
+
+.*:     file format elf32-tradbigmips
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+00000000 R_MIPS_NONE       \*ABS\*
+0013f830 R_MIPS_TLS_DTPMOD32  \*ABS\*
+0014948c R_MIPS_TLS_DTPMOD32  \*ABS\*
+0013f83c R_MIPS_TLS_DTPMOD32  tlsvar_gd
+0013f840 R_MIPS_TLS_DTPREL32  tlsvar_gd
+00149498 R_MIPS_TLS_DTPMOD32  tlsvar_gd
+0014949c R_MIPS_TLS_DTPREL32  tlsvar_gd
+0013f838 R_MIPS_TLS_TPREL32  tlsvar_ie
+00149494 R_MIPS_TLS_TPREL32  tlsvar_ie
+00143e38 R_MIPS_REL32      sym_1_9526
+#...
+00139ab8 R_MIPS_REL32      sym_2_8654
+
+
+Contents of section .got:
+ 122360 00000000 80000000 000d7f98 000d65f4  .*
+ 122370 000d1fa4 000d6010 000d5a48 000d19c0  .*
+#...
+ 135be0 000cf204 000e0e48 00000000 80000000  .*
+ 135bf0 00000000 00000000 00000000 00000000  .*
+#...
+ 13f820 00000000 00000000 00000000 00000000  .*
+ 13f830 00000000 00000000 00000000 00000000  .*
+ 13f840 00000000 00000000 80000000 00000000  .*
+#...
+ 149450 00000000 00000000 00000000 00000000  .*
+ 149460 00000000 00000000 00000000 00000000  .*
+ 149470 00000000 00000000 00000000 00000000  .*
+ 149480 00000000 00000000 00000000 00000000  .*
+ 149490 00000000 00000000 00000000 00000000  .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tls-multi-got-1.r b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-multi-got-1.r
new file mode 100644
index 0000000..a51abf1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tls-multi-got-1.r
@@ -0,0 +1,38 @@
+
+Dynamic section at offset .* contains 18 entries:
+  Tag        Type                         Name/Value
+ 0x00000004 \(HASH\)                       0x1c4
+ 0x00000005 \(STRTAB\).*
+ 0x00000006 \(SYMTAB\).*
+ 0x0000000a \(STRSZ\)                      220091 \(bytes\)
+ 0x0000000b \(SYMENT\)                     16 \(bytes\)
+ 0x00000003 \(PLTGOT\)                     0x122360
+ 0x00000011 \(REL\)                        0xa7978
+ 0x00000012 \(RELSZ\)                      160072 \(bytes\)
+ 0x00000013 \(RELENT\)                     8 \(bytes\)
+ 0x70000001 \(MIPS_RLD_VERSION\)           1
+ 0x70000005 \(MIPS_FLAGS\)                 NOTPOT
+ 0x70000006 \(MIPS_BASE_ADDRESS\)          0
+ 0x7000000a \(MIPS_LOCAL_GOTNO\)           2
+ 0x70000011 \(MIPS_SYMTABNO\)              20013
+ 0x70000012 \(MIPS_UNREFEXTNO\)            10
+ 0x70000013 \(MIPS_GOTSYM\)                0xd
+ 0x0000001e \(FLAGS\)                      STATIC_TLS
+ 0x00000000 \(NULL\)                       0x0
+
+Relocation section '\.rel\.dyn' at offset 0x[0-9a-f]+ contains 20009 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name
+[0-9a-f ]+R_MIPS_NONE      
+[0-9a-f ]+R_MIPS_TLS_DTPMOD
+[0-9a-f ]+R_MIPS_TLS_DTPMOD
+[0-9a-f ]+R_MIPS_TLS_DTPMOD 00000000   tlsvar_gd
+[0-9a-f ]+R_MIPS_TLS_DTPREL 00000000   tlsvar_gd
+[0-9a-f ]+R_MIPS_TLS_DTPMOD 00000000   tlsvar_gd
+[0-9a-f ]+R_MIPS_TLS_DTPREL 00000000   tlsvar_gd
+[0-9a-f ]+R_MIPS_TLS_TPREL3 00000004   tlsvar_ie
+[0-9a-f ]+R_MIPS_TLS_TPREL3 00000004   tlsvar_ie
+[0-9a-f ]+R_MIPS_REL32      000d7f98   sym_1_9526
+[0-9a-f ]+R_MIPS_REL32      000d65f4   sym_1_7885
+#...
+[0-9a-f ]+R_MIPS_REL32      000cf204   sym_1_0465
+[0-9a-f ]+R_MIPS_REL32      000e0e48   sym_2_8654
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlsbin-o32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsbin-o32.d
new file mode 100644
index 0000000..0319649
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsbin-o32.d
@@ -0,0 +1,43 @@
+.*:     file format elf32-tradbigmips
+
+Disassembly of section .text:
+
+004000d0 <__start>:
+  4000d0:	3c1c0fc0 	lui	gp,0xfc0
+  4000d4:	279c7f30 	addiu	gp,gp,32560
+  4000d8:	0399e021 	addu	gp,gp,t9
+  4000dc:	27bdfff0 	addiu	sp,sp,-16
+  4000e0:	afbe0008 	sw	s8,8\(sp\)
+  4000e4:	03a0f021 	move	s8,sp
+  4000e8:	afbc0000 	sw	gp,0\(sp\)
+  4000ec:	8f998018 	lw	t9,-32744\(gp\)
+  4000f0:	27848028 	addiu	a0,gp,-32728
+  4000f4:	0320f809 	jalr	t9
+  4000f8:	00000000 	nop
+  4000fc:	8fdc0000 	lw	gp,0\(s8\)
+  400100:	00000000 	nop
+  400104:	8f998018 	lw	t9,-32744\(gp\)
+  400108:	27848020 	addiu	a0,gp,-32736
+  40010c:	0320f809 	jalr	t9
+  400110:	00000000 	nop
+  400114:	8fdc0000 	lw	gp,0\(s8\)
+  400118:	00401021 	move	v0,v0
+  40011c:	3c030000 	lui	v1,0x0
+  400120:	24638000 	addiu	v1,v1,-32768
+  400124:	00621821 	addu	v1,v1,v0
+  400128:	7c02283b 	rdhwr	v0,\$5
+  40012c:	8f83801c 	lw	v1,-32740\(gp\)
+  400130:	00000000 	nop
+  400134:	00621821 	addu	v1,v1,v0
+  400138:	7c02283b 	rdhwr	v0,\$5
+  40013c:	3c030000 	lui	v1,0x0
+  400140:	24639004 	addiu	v1,v1,-28668
+  400144:	00621821 	addu	v1,v1,v0
+  400148:	03c0e821 	move	sp,s8
+  40014c:	8fbe0008 	lw	s8,8\(sp\)
+  400150:	03e00008 	jr	ra
+  400154:	27bd0010 	addiu	sp,sp,16
+
+00400158 <__tls_get_addr>:
+  400158:	03e00008 	jr	ra
+  40015c:	00000000 	nop
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlsbin-o32.got b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsbin-o32.got
new file mode 100644
index 0000000..7deecf5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsbin-o32.got
@@ -0,0 +1,6 @@
+
+.*:     file format elf32-tradbigmips
+
+Contents of section .got:
+ 10000010 00000000 80000000 00400158 ffff900c  .........@.X....
+ 10000020 00000001 00000000 00000001 ffff8008  ................
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlsbin-o32.s b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsbin-o32.s
new file mode 100644
index 0000000..8ff9831
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsbin-o32.s
@@ -0,0 +1,89 @@
+	.file	1 "tlsbin-o32.s"
+	.abicalls
+	.text
+	.align	2
+	.globl	__start
+	.ent	__start
+	.type	__start,@function
+__start:
+	.frame	$fp,16,$31
+	.mask	0x40000000,-8
+	.fmask	0x00000000,0
+	.set	noreorder
+	.cpload $25
+	.set	reorder
+	addiu	$sp,$sp,-16
+	sw	$fp,8($sp)
+	move	$fp,$sp
+	.cprestore	0
+
+	# General Dynamic
+	lw	$25,%call16(__tls_get_addr)($28)
+	addiu	$4,$28,%tlsgd(tlsvar_gd)
+	jal	$25
+
+	# Local Dynamic
+	lw	$25,%call16(__tls_get_addr)($28)
+	addiu	$4,$28,%tlsldm(tlsvar_ld)
+	jal	$25
+
+	move	$2,$2		# Arbitrary instructions
+
+	lui	$3,%dtprel_hi(tlsvar_ld)
+	addiu	$3,$3,%dtprel_lo(tlsvar_ld)
+	addu	$3,$3,$2
+
+	# Initial Exec
+	.set	push
+	.set	mips32r2
+	rdhwr	$2, $5
+	.set	pop
+	lw	$3,%gottprel(tlsvar_ie)($28)
+	addu	$3,$3,$2
+
+	# Local Exec
+	.set	push
+	.set	mips32r2
+	rdhwr	$2, $5
+	.set	pop
+	lui	$3,%tprel_hi(tlsvar_le)
+	addiu	$3,$3,%tprel_lo(tlsvar_le)
+	addu	$3,$3,$2
+
+	move	$sp,$fp
+	lw	$fp,8($sp)
+	addiu	$sp,$sp,16
+	j	$31
+	.end	__start
+
+	.globl __tls_get_addr
+__tls_get_addr:
+	j $31
+
+	.section		.tbss,"awT",@nobits
+	.align	2
+	.global	tlsvar_gd
+	.type	tlsvar_gd,@object
+	.size	tlsvar_gd,4
+tlsvar_gd:
+	.space	4
+	.global	tlsvar_ie
+	.type	tlsvar_ie,@object
+	.size	tlsvar_ie,4
+tlsvar_ie:
+	.space	4
+
+	.section		.tdata,"awT"
+	.align	2
+	.global	tlsvar_ld
+	.hidden	tlsvar_ld
+	.type	tlsvar_ld,@object
+	.size	tlsvar_ld,4
+tlsvar_ld:
+	.word	1
+	.global	tlsvar_le
+	.hidden	tlsvar_le
+	.type	tlsvar_le,@object
+	.size	tlsvar_le,4
+tlsvar_le:
+	.word	1
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-1.d b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-1.d
new file mode 100644
index 0000000..bf803c8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-1.d
@@ -0,0 +1,100 @@
+
+.*:     file format elf32-tradbigmips
+
+Disassembly of section .text:
+
+.* <__start>:
+  .*:	3c1c0fc0 	lui	gp,0xfc0
+  .*:	279c7b80 	addiu	gp,gp,31616
+  .*:	0399e021 	addu	gp,gp,t9
+  .*:	27bdfff0 	addiu	sp,sp,-16
+  .*:	afbe0008 	sw	s8,8\(sp\)
+  .*:	03a0f021 	move	s8,sp
+  .*:	afbc0000 	sw	gp,0\(sp\)
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848030 	addiu	a0,gp,-32720
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00000000 	nop
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848024 	addiu	a0,gp,-32732
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00000000 	nop
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	2784801c 	addiu	a0,gp,-32740
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00401021 	move	v0,v0
+  .*:	3c030000 	lui	v1,0x0
+  .*:	24638000 	addiu	v1,v1,-32768
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	7c02283b 	rdhwr	v0,\$5
+  .*:	8f838038 	lw	v1,-32712\(gp\)
+  .*:	00000000 	nop
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	8f83802c 	lw	v1,-32724\(gp\)
+  .*:	00000000 	nop
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	7c02283b 	rdhwr	v0,\$5
+  .*:	3c030000 	lui	v1,0x0
+  .*:	24639004 	addiu	v1,v1,-28668
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	03c0e821 	move	sp,s8
+  .*:	8fbe0008 	lw	s8,8\(sp\)
+  .*:	03e00008 	jr	ra
+  .*:	27bd0010 	addiu	sp,sp,16
+
+.* <__tls_get_addr>:
+  .*:	03e00008 	jr	ra
+  .*:	00000000 	nop
+	...
+
+.* <other>:
+  .*:	3c1c0fc0 	lui	gp,0xfc0
+  .*:	279c7ac0 	addiu	gp,gp,31424
+  .*:	0399e021 	addu	gp,gp,t9
+  .*:	27bdfff0 	addiu	sp,sp,-16
+  .*:	afbe0008 	sw	s8,8\(sp\)
+  .*:	03a0f021 	move	s8,sp
+  .*:	afbc0000 	sw	gp,0\(sp\)
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848030 	addiu	a0,gp,-32720
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00000000 	nop
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848024 	addiu	a0,gp,-32732
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00000000 	nop
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	2784801c 	addiu	a0,gp,-32740
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00401021 	move	v0,v0
+  .*:	3c030000 	lui	v1,0x0
+  .*:	24638000 	addiu	v1,v1,-32768
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	7c02283b 	rdhwr	v0,\$5
+  .*:	8f838038 	lw	v1,-32712\(gp\)
+  .*:	00000000 	nop
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	8f83802c 	lw	v1,-32724\(gp\)
+  .*:	00000000 	nop
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	7c02283b 	rdhwr	v0,\$5
+  .*:	3c030000 	lui	v1,0x0
+  .*:	24639004 	addiu	v1,v1,-28668
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	03c0e821 	move	sp,s8
+  .*:	8fbe0008 	lw	s8,8\(sp\)
+  .*:	03e00008 	jr	ra
+  .*:	27bd0010 	addiu	sp,sp,16
+  .*:	00000000 	nop
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-1.got b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-1.got
new file mode 100644
index 0000000..7053939
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-1.got
@@ -0,0 +1,18 @@
+
+.*:     file format elf32-tradbigmips
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+00000000 R_MIPS_NONE       \*ABS\*
+10000040 R_MIPS_TLS_DTPMOD32  tlsbin_gd
+10000044 R_MIPS_TLS_DTPREL32  tlsbin_gd
+10000034 R_MIPS_TLS_DTPMOD32  tlsvar_gd
+10000038 R_MIPS_TLS_DTPREL32  tlsvar_gd
+1000003c R_MIPS_TLS_TPREL32  tlsvar_ie
+10000048 R_MIPS_TLS_TPREL32  tlsbin_ie
+
+
+Contents of section .got:
+ 10000020 00000000 80000000 0040053c 00000001  .........@......
+ 10000030 00000000 00000000 00000000 00000000  ................
+ 10000040 00000000 00000000 00000000           ............    
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-2.d b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-2.d
new file mode 100644
index 0000000..e1f76b5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-2.d
@@ -0,0 +1,100 @@
+
+.*:     file format elf32-tradbigmips
+
+Disassembly of section .text:
+
+.* <__start>:
+  .*:	3c1c0fc0 	lui	gp,0xfc0
+  .*:	279c7b80 	addiu	gp,gp,31616
+  .*:	0399e021 	addu	gp,gp,t9
+  .*:	27bdfff0 	addiu	sp,sp,-16
+  .*:	afbe0008 	sw	s8,8\(sp\)
+  .*:	03a0f021 	move	s8,sp
+  .*:	afbc0000 	sw	gp,0\(sp\)
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848028 	addiu	a0,gp,-32728
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00000000 	nop
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848020 	addiu	a0,gp,-32736
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00000000 	nop
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848030 	addiu	a0,gp,-32720
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00401021 	move	v0,v0
+  .*:	3c030000 	lui	v1,0x0
+  .*:	24638000 	addiu	v1,v1,-32768
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	7c02283b 	rdhwr	v0,\$5
+  .*:	8f838038 	lw	v1,-32712\(gp\)
+  .*:	00000000 	nop
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	8f83801c 	lw	v1,-32740\(gp\)
+  .*:	00000000 	nop
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	7c02283b 	rdhwr	v0,\$5
+  .*:	3c030000 	lui	v1,0x0
+  .*:	24639004 	addiu	v1,v1,-28668
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	03c0e821 	move	sp,s8
+  .*:	8fbe0008 	lw	s8,8\(sp\)
+  .*:	03e00008 	jr	ra
+  .*:	27bd0010 	addiu	sp,sp,16
+
+.* <__tls_get_addr>:
+  .*:	03e00008 	jr	ra
+  .*:	00000000 	nop
+	...
+
+.* <other>:
+  .*:	3c1c0fc0 	lui	gp,0xfc0
+  .*:	279c7ac0 	addiu	gp,gp,31424
+  .*:	0399e021 	addu	gp,gp,t9
+  .*:	27bdfff0 	addiu	sp,sp,-16
+  .*:	afbe0008 	sw	s8,8\(sp\)
+  .*:	03a0f021 	move	s8,sp
+  .*:	afbc0000 	sw	gp,0\(sp\)
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848028 	addiu	a0,gp,-32728
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00000000 	nop
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848020 	addiu	a0,gp,-32736
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00000000 	nop
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848030 	addiu	a0,gp,-32720
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00401021 	move	v0,v0
+  .*:	3c030000 	lui	v1,0x0
+  .*:	24638000 	addiu	v1,v1,-32768
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	7c02283b 	rdhwr	v0,\$5
+  .*:	8f838038 	lw	v1,-32712\(gp\)
+  .*:	00000000 	nop
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	8f83801c 	lw	v1,-32740\(gp\)
+  .*:	00000000 	nop
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	7c02283b 	rdhwr	v0,\$5
+  .*:	3c030000 	lui	v1,0x0
+  .*:	24639004 	addiu	v1,v1,-28668
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	03c0e821 	move	sp,s8
+  .*:	8fbe0008 	lw	s8,8\(sp\)
+  .*:	03e00008 	jr	ra
+  .*:	27bd0010 	addiu	sp,sp,16
+  .*:	00000000 	nop
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-2.got b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-2.got
new file mode 100644
index 0000000..c5516c5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-2.got
@@ -0,0 +1,19 @@
+
+.*:     file format elf32-tradbigmips
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+00000000 R_MIPS_NONE       \*ABS\*
+10000038 R_MIPS_TLS_DTPMOD32  tlsbin_gd
+1000003c R_MIPS_TLS_DTPREL32  tlsbin_gd
+10000030 R_MIPS_TLS_DTPMOD32  tlsvar_gd
+10000034 R_MIPS_TLS_DTPREL32  tlsvar_gd
+1000002c R_MIPS_TLS_TPREL32  tlsvar_ie
+10000048 R_MIPS_TLS_TPREL32  tlsbin_ie
+
+
+Contents of section .got:
+ 10000020 00000000 80000000 0040053c 00000000  .*
+ 10000030 00000000 00000000 00000000 00000000  .*
+ 10000040 00000001 00000000 00000000 00000000  .*
+ 10000050 00000000 00000000                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-2.s b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-2.s
new file mode 100644
index 0000000..7943775
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-2.s
@@ -0,0 +1,64 @@
+	.file	1 "tlsbin-o32.s"
+	.abicalls
+	.text
+	.align	2
+	.globl	other
+	.ent	other
+	.type	other,@function
+other:
+	.frame	$fp,16,$31
+	.mask	0x40000000,-8
+	.fmask	0x00000000,0
+	.set	noreorder
+	.cpload $25
+	.set	reorder
+	addiu	$sp,$sp,-16
+	sw	$fp,8($sp)
+	move	$fp,$sp
+	.cprestore	0
+
+	# General Dynamic
+	lw	$25,%call16(__tls_get_addr)($28)
+	addiu	$4,$28,%tlsgd(tlsbin_gd)
+	jal	$25
+
+	lw	$25,%call16(__tls_get_addr)($28)
+	addiu	$4,$28,%tlsgd(tlsvar_gd)
+	jal	$25
+
+	# Local Dynamic
+	lw	$25,%call16(__tls_get_addr)($28)
+	addiu	$4,$28,%tlsldm(tlsbin_ld)
+	jal	$25
+
+	move	$2,$2		# Arbitrary instructions
+
+	lui	$3,%dtprel_hi(tlsbin_ld)
+	addiu	$3,$3,%dtprel_lo(tlsbin_ld)
+	addu	$3,$3,$2
+
+	# Initial Exec
+	.set	push
+	.set	mips32r2
+	rdhwr	$2, $5
+	.set	pop
+	lw	$3,%gottprel(tlsbin_ie)($28)
+	addu	$3,$3,$2
+
+	lw	$3,%gottprel(tlsvar_ie)($28)
+	addu	$3,$3,$2
+
+	# Local Exec
+	.set	push
+	.set	mips32r2
+	rdhwr	$2, $5
+	.set	pop
+	lui	$3,%tprel_hi(tlsbin_le)
+	addiu	$3,$3,%tprel_lo(tlsbin_le)
+	addu	$3,$3,$2
+
+	move	$sp,$fp
+	lw	$fp,8($sp)
+	addiu	$sp,$sp,16
+	j	$31
+	.end	other
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-3.d b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-3.d
new file mode 100644
index 0000000..27db816
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-3.d
@@ -0,0 +1,100 @@
+
+.*:     file format elf32-tradbigmips
+
+Disassembly of section .text:
+
+.* <other>:
+  .*:	3c1c0fc0 	lui	gp,0xfc0
+  .*:	279c7b80 	addiu	gp,gp,31616
+  .*:	0399e021 	addu	gp,gp,t9
+  .*:	27bdfff0 	addiu	sp,sp,-16
+  .*:	afbe0008 	sw	s8,8\(sp\)
+  .*:	03a0f021 	move	s8,sp
+  .*:	afbc0000 	sw	gp,0\(sp\)
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848028 	addiu	a0,gp,-32728
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00000000 	nop
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848020 	addiu	a0,gp,-32736
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00000000 	nop
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848030 	addiu	a0,gp,-32720
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00401021 	move	v0,v0
+  .*:	3c030000 	lui	v1,0x0
+  .*:	24638000 	addiu	v1,v1,-32768
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	7c02283b 	rdhwr	v0,\$5
+  .*:	8f838038 	lw	v1,-32712\(gp\)
+  .*:	00000000 	nop
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	8f83801c 	lw	v1,-32740\(gp\)
+  .*:	00000000 	nop
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	7c02283b 	rdhwr	v0,\$5
+  .*:	3c030000 	lui	v1,0x0
+  .*:	24639004 	addiu	v1,v1,-28668
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	03c0e821 	move	sp,s8
+  .*:	8fbe0008 	lw	s8,8\(sp\)
+  .*:	03e00008 	jr	ra
+  .*:	27bd0010 	addiu	sp,sp,16
+  .*:	00000000 	nop
+
+.* <__start>:
+  .*:	3c1c0fc0 	lui	gp,0xfc0
+  .*:	279c7ad0 	addiu	gp,gp,31440
+  .*:	0399e021 	addu	gp,gp,t9
+  .*:	27bdfff0 	addiu	sp,sp,-16
+  .*:	afbe0008 	sw	s8,8\(sp\)
+  .*:	03a0f021 	move	s8,sp
+  .*:	afbc0000 	sw	gp,0\(sp\)
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848028 	addiu	a0,gp,-32728
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00000000 	nop
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848020 	addiu	a0,gp,-32736
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00000000 	nop
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848030 	addiu	a0,gp,-32720
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00401021 	move	v0,v0
+  .*:	3c030000 	lui	v1,0x0
+  .*:	24638000 	addiu	v1,v1,-32768
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	7c02283b 	rdhwr	v0,\$5
+  .*:	8f838038 	lw	v1,-32712\(gp\)
+  .*:	00000000 	nop
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	8f83801c 	lw	v1,-32740\(gp\)
+  .*:	00000000 	nop
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	7c02283b 	rdhwr	v0,\$5
+  .*:	3c030000 	lui	v1,0x0
+  .*:	24639004 	addiu	v1,v1,-28668
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	03c0e821 	move	sp,s8
+  .*:	8fbe0008 	lw	s8,8\(sp\)
+  .*:	03e00008 	jr	ra
+  .*:	27bd0010 	addiu	sp,sp,16
+
+.* <__tls_get_addr>:
+  .*:	03e00008 	jr	ra
+  .*:	00000000 	nop
+	...
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-3.got b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-3.got
new file mode 100644
index 0000000..54f491e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32-3.got
@@ -0,0 +1,19 @@
+
+.*:     file format elf32-tradbigmips
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+00000000 R_MIPS_NONE       \*ABS\*
+10000038 R_MIPS_TLS_DTPMOD32  tlsbin_gd
+1000003c R_MIPS_TLS_DTPREL32  tlsbin_gd
+10000030 R_MIPS_TLS_DTPMOD32  tlsvar_gd
+10000034 R_MIPS_TLS_DTPREL32  tlsvar_gd
+1000002c R_MIPS_TLS_TPREL32  tlsvar_ie
+10000048 R_MIPS_TLS_TPREL32  tlsbin_ie
+
+
+Contents of section .got:
+ 10000020 00000000 80000000 004005ec 00000000  .*
+ 10000030 00000000 00000000 00000000 00000000  .*
+ 10000040 00000001 00000000 00000000 00000000  .*
+ 10000050 00000000 00000000                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32.d
new file mode 100644
index 0000000..32c3e7d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32.d
@@ -0,0 +1,54 @@
+
+.*:     file format elf32-tradbigmips
+
+Disassembly of section .text:
+
+.* <__start>:
+  .*:	3c1c0fc0 	lui	gp,0xfc0
+  .*:	279c7ba0 	addiu	gp,gp,31648
+  .*:	0399e021 	addu	gp,gp,t9
+  .*:	27bdfff0 	addiu	sp,sp,-16
+  .*:	afbe0008 	sw	s8,8\(sp\)
+  .*:	03a0f021 	move	s8,sp
+  .*:	afbc0000 	sw	gp,0\(sp\)
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848024 	addiu	a0,gp,-32732
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00000000 	nop
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	27848034 	addiu	a0,gp,-32716
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00000000 	nop
+  .*:	8f998018 	lw	t9,-32744\(gp\)
+  .*:	2784801c 	addiu	a0,gp,-32740
+  .*:	0320f809 	jalr	t9
+  .*:	00000000 	nop
+  .*:	8fdc0000 	lw	gp,0\(s8\)
+  .*:	00401021 	move	v0,v0
+  .*:	3c030000 	lui	v1,0x0
+  .*:	24638000 	addiu	v1,v1,-32768
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	7c02283b 	rdhwr	v0,\$5
+  .*:	8f838030 	lw	v1,-32720\(gp\)
+  .*:	00000000 	nop
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	8f83802c 	lw	v1,-32724\(gp\)
+  .*:	00000000 	nop
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	7c02283b 	rdhwr	v0,\$5
+  .*:	3c030000 	lui	v1,0x0
+  .*:	24639004 	addiu	v1,v1,-28668
+  .*:	00621821 	addu	v1,v1,v0
+  .*:	03c0e821 	move	sp,s8
+  .*:	8fbe0008 	lw	s8,8\(sp\)
+  .*:	03e00008 	jr	ra
+  .*:	27bd0010 	addiu	sp,sp,16
+
+.* <__tls_get_addr>:
+  .*:	03e00008 	jr	ra
+  .*:	00000000 	nop
+	...
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32.got b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32.got
new file mode 100644
index 0000000..5f93c17
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32.got
@@ -0,0 +1,18 @@
+
+tmpdir/tls-dynamic-o32:     file format elf32-tradbigmips
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+00000000 R_MIPS_NONE       \*ABS\*
+10000034 R_MIPS_TLS_DTPMOD32  tlsbin_gd
+10000038 R_MIPS_TLS_DTPREL32  tlsbin_gd
+10000044 R_MIPS_TLS_DTPMOD32  tlsvar_gd
+10000048 R_MIPS_TLS_DTPREL32  tlsvar_gd
+10000040 R_MIPS_TLS_TPREL32  tlsbin_ie
+1000003c R_MIPS_TLS_TPREL32  tlsvar_ie
+
+
+Contents of section .got:
+ 10000020 00000000 80000000 0040051c 00000001  ................
+ 10000030 00000000 00000000 00000000 00000000  ................
+ 10000040 00000000 00000000 00000000           ............    
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32.s b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32.s
new file mode 100644
index 0000000..2924221
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlsdyn-o32.s
@@ -0,0 +1,96 @@
+	.file	1 "tlsbin-o32.s"
+	.abicalls
+	.text
+	.align	2
+	.globl	__start
+	.ent	__start
+	.type	__start,@function
+__start:
+	.frame	$fp,16,$31
+	.mask	0x40000000,-8
+	.fmask	0x00000000,0
+	.set	noreorder
+	.cpload $25
+	.set	reorder
+	addiu	$sp,$sp,-16
+	sw	$fp,8($sp)
+	move	$fp,$sp
+	.cprestore	0
+
+	# General Dynamic
+	lw	$25,%call16(__tls_get_addr)($28)
+	addiu	$4,$28,%tlsgd(tlsbin_gd)
+	jal	$25
+
+	lw	$25,%call16(__tls_get_addr)($28)
+	addiu	$4,$28,%tlsgd(tlsvar_gd)
+	jal	$25
+
+	# Local Dynamic
+	lw	$25,%call16(__tls_get_addr)($28)
+	addiu	$4,$28,%tlsldm(tlsbin_ld)
+	jal	$25
+
+	move	$2,$2		# Arbitrary instructions
+
+	lui	$3,%dtprel_hi(tlsbin_ld)
+	addiu	$3,$3,%dtprel_lo(tlsbin_ld)
+	addu	$3,$3,$2
+
+	# Initial Exec
+	.set	push
+	.set	mips32r2
+	rdhwr	$2, $5
+	.set	pop
+	lw	$3,%gottprel(tlsbin_ie)($28)
+	addu	$3,$3,$2
+
+	lw	$3,%gottprel(tlsvar_ie)($28)
+	addu	$3,$3,$2
+
+	# Local Exec
+	.set	push
+	.set	mips32r2
+	rdhwr	$2, $5
+	.set	pop
+	lui	$3,%tprel_hi(tlsbin_le)
+	addiu	$3,$3,%tprel_lo(tlsbin_le)
+	addu	$3,$3,$2
+
+	move	$sp,$fp
+	lw	$fp,8($sp)
+	addiu	$sp,$sp,16
+	j	$31
+	.end	__start
+
+	.globl __tls_get_addr
+__tls_get_addr:
+	j $31
+
+	.section		.tbss,"awT",@nobits
+	.align	2
+	.global	tlsbin_gd
+	.type	tlsbin_gd,@object
+	.size	tlsbin_gd,4
+tlsbin_gd:
+	.space	4
+	.global	tlsbin_ie
+	.type	tlsbin_ie,@object
+	.size	tlsbin_ie,4
+tlsbin_ie:
+	.space	4
+
+	.section		.tdata,"awT"
+	.align	2
+	.global	tlsbin_ld
+	.hidden	tlsbin_ld
+	.type	tlsbin_ld,@object
+	.size	tlsbin_ld,4
+tlsbin_ld:
+	.word	1
+	.global	tlsbin_le
+	.hidden	tlsbin_le
+	.type	tlsbin_le,@object
+	.size	tlsbin_le,4
+tlsbin_le:
+	.word	1
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-hidden.ver b/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-hidden.ver
new file mode 100644
index 0000000..e59012f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-hidden.ver
@@ -0,0 +1,3 @@
+VER_1 {
+  local: *;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-o32-hidden.got b/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-o32-hidden.got
new file mode 100644
index 0000000..b1a8317
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-o32-hidden.got
@@ -0,0 +1,14 @@
+
+.*:     file format elf32-tradbigmips
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+00000000 R_MIPS_NONE       \*ABS\*
+000403bc R_MIPS_TLS_TPREL32  \*ABS\*
+000403c0 R_MIPS_TLS_DTPMOD32  \*ABS\*
+000403c8 R_MIPS_TLS_DTPMOD32  \*ABS\*
+
+
+Contents of section .got:
+ 403b0 00000000 80000000 00000380 00000008  ................
+ 403c0 00000000 00000000 00000000 ffff8004  ................
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-o32-ver.got b/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-o32-ver.got
new file mode 100644
index 0000000..a2bc239
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-o32-ver.got
@@ -0,0 +1,15 @@
+
+.*:     file format elf32-tradbigmips
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+00000000 R_MIPS_NONE       \*ABS\*
+00040520 R_MIPS_TLS_DTPMOD32  \*ABS\*
+00040528 R_MIPS_TLS_DTPMOD32  tlsvar_gd
+0004052c R_MIPS_TLS_DTPREL32  tlsvar_gd
+0004051c R_MIPS_TLS_TPREL32  tlsvar_ie
+
+
+Contents of section .got:
+ 40510 00000000 80000000 000004e0 00000000  ................
+ 40520 00000000 00000000 00000000 00000000  ................
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-o32.d b/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-o32.d
new file mode 100644
index 0000000..cdeeded
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-o32.d
@@ -0,0 +1,45 @@
+
+.*:     file format elf32-tradbigmips
+
+Disassembly of section .text:
+
+.* <fn>:
+ .*:	3c1c0005 	lui	gp,0x5
+ .*:	279c80a0 	addiu	gp,gp,-32608
+ .*:	0399e021 	addu	gp,gp,t9
+ .*:	27bdfff0 	addiu	sp,sp,-16
+ .*:	afbe0008 	sw	s8,8\(sp\)
+ .*:	03a0f021 	move	s8,sp
+ .*:	afbc0000 	sw	gp,0\(sp\)
+ .*:	8f998018 	lw	t9,-32744\(gp\)
+ .*:	27848028 	addiu	a0,gp,-32728
+ .*:	0320f809 	jalr	t9
+ .*:	00000000 	nop
+ .*:	8fdc0000 	lw	gp,0\(s8\)
+ .*:	00000000 	nop
+ .*:	8f998018 	lw	t9,-32744\(gp\)
+ .*:	27848020 	addiu	a0,gp,-32736
+ .*:	0320f809 	jalr	t9
+ .*:	00000000 	nop
+ .*:	8fdc0000 	lw	gp,0\(s8\)
+ .*:	00401021 	move	v0,v0
+ .*:	3c030000 	lui	v1,0x0
+ .*:	24638000 	addiu	v1,v1,-32768
+ .*:	00621821 	addu	v1,v1,v0
+ .*:	7c02283b 	rdhwr	v0,\$5
+ .*:	8f83801c 	lw	v1,-32740\(gp\)
+ .*:	00000000 	nop
+ .*:	00621821 	addu	v1,v1,v0
+ .*:	03c0e821 	move	sp,s8
+ .*:	8fbe0008 	lw	s8,8\(sp\)
+ .*:	03e00008 	jr	ra
+ .*:	27bd0010 	addiu	sp,sp,16
+	...
+Disassembly of section .MIPS.stubs:
+
+.* <.MIPS.stubs>:
+ .*:	8f998010 	lw	t9,-32752\(gp\)
+ .*:	03e07821 	move	t7,ra
+ .*:	0320f809 	jalr	t9
+ .*:	241800.* 	li	t8,.*
+	...
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-o32.got b/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-o32.got
new file mode 100644
index 0000000..7dca58e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-o32.got
@@ -0,0 +1,15 @@
+
+tmpdir/tlslib-o32.so:     file format elf32-tradbigmips
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+00000000 R_MIPS_NONE       \*ABS\*
+00040480 R_MIPS_TLS_DTPMOD32  \*ABS\*
+00040488 R_MIPS_TLS_DTPMOD32  tlsvar_gd
+0004048c R_MIPS_TLS_DTPREL32  tlsvar_gd
+0004047c R_MIPS_TLS_TPREL32  tlsvar_ie
+
+
+Contents of section .got:
+ 40470 00000000 80000000 00000440 00000000  ................
+ 40480 00000000 00000000 00000000 00000000  ................
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-o32.s b/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-o32.s
new file mode 100644
index 0000000..c15829f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib-o32.s
@@ -0,0 +1,70 @@
+	.file	1 "tlslib-o32.s"
+	.abicalls
+	.text
+	.align	2
+	.globl	fn
+	.ent	fn
+	.type	fn,@function
+fn:
+	.frame	$fp,16,$31
+	.mask	0x40000000,-8
+	.fmask	0x00000000,0
+	.set	noreorder
+	.cpload $25
+	.set	reorder
+	addiu	$sp,$sp,-16
+	sw	$fp,8($sp)
+	move	$fp,$sp
+	.cprestore	0
+
+	# General Dynamic
+	lw	$25,%call16(__tls_get_addr)($28)
+	addiu	$4,$28,%tlsgd(tlsvar_gd)
+	jal	$25
+
+	# Local Dynamic
+	lw	$25,%call16(__tls_get_addr)($28)
+	addiu	$4,$28,%tlsldm(tlsvar_ld)
+	jal	$25
+
+	move	$2,$2		# Arbitrary instructions
+
+	lui	$3,%dtprel_hi(tlsvar_ld)
+	addiu	$3,$3,%dtprel_lo(tlsvar_ld)
+	addu	$3,$3,$2
+
+	# Initial Exec
+	.set	push
+	.set	mips32r2
+	rdhwr	$2, $5
+	.set	pop
+	lw	$3,%gottprel(tlsvar_ie)($28)
+	addu	$3,$3,$2
+
+	move	$sp,$fp
+	lw	$fp,8($sp)
+	addiu	$sp,$sp,16
+	j	$31
+	.end	fn
+
+	.section		.tbss,"awT",@nobits
+	.align	2
+	.global	tlsvar_gd
+	.type	tlsvar_gd,@object
+	.size	tlsvar_gd,4
+tlsvar_gd:
+	.space	4
+	.global	tlsvar_ie
+	.type	tlsvar_ie,@object
+	.size	tlsvar_ie,4
+tlsvar_ie:
+	.space	4
+
+	.section		.tdata,"awT"
+	.align	2
+	.global	tlsvar_ld
+	.hidden	tlsvar_ld
+	.type	tlsvar_ld,@object
+	.size	tlsvar_ld,4
+tlsvar_ld:
+	.word	1
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib.ver b/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib.ver
new file mode 100644
index 0000000..441c525
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/tlslib.ver
@@ -0,0 +1,3 @@
+VER_1 {
+  global: *;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks-forced-local-1.d b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks-forced-local-1.d
new file mode 100644
index 0000000..dc02a3b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks-forced-local-1.d
@@ -0,0 +1,12 @@
+#as: -mips2 -mvxworks-pic
+#source: vxworks-forced-local-1.s
+#ld: -shared -Tvxworks1.ld --version-script vxworks-forced-local-1.ver
+#readelf: --relocs
+
+Relocation section '\.rela\.dyn' .*
+.*
+0008140c  00000002 R_MIPS_32 *00080810
+00081410  00000002 R_MIPS_32 *00080814
+00081414  00000002 R_MIPS_32 *00080818
+00081418  00000302 R_MIPS_32 *00000000 *bar \+ 0
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks-forced-local-1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks-forced-local-1.s
new file mode 100644
index 0000000..a0c0212
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks-forced-local-1.s
@@ -0,0 +1,13 @@
+	.globl	foo1
+	.globl	foo2
+	.globl	foo3
+	lw	$4,%call16(foo1)($gp)
+	lw	$4,%call16(foo2)($gp)
+	lw	$4,%call16(foo3)($gp)
+	lw	$4,%got(bar)($gp)
+foo1:
+	nop
+foo2:
+	nop
+foo3:
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks-forced-local-1.ver b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks-forced-local-1.ver
new file mode 100644
index 0000000..a53c620
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks-forced-local-1.ver
@@ -0,0 +1 @@
+{ local: foo*; };
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-lib.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-lib.dd
new file mode 100644
index 0000000..17ea125
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-lib.dd
@@ -0,0 +1,50 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+00080800 <_PROCEDURE_LINKAGE_TABLE_>:
+   80800:	8f990008 	lw	t9,8\(gp\)
+   80804:	00000000 	nop
+   80808:	03200008 	jr	t9
+   8080c:	00000000 	nop
+	\.\.\.
+   80818:	1000fff9 	b	80800 <_PROCEDURE_LINKAGE_TABLE_>
+   8081c:	24180000 	li	t8,0
+   80820:	1000fff7 	b	80800 <_PROCEDURE_LINKAGE_TABLE_>
+   80824:	24180001 	li	t8,1
+Disassembly of section \.text:
+
+00080c00 <foo>:
+   80c00:	27bdffe0 	addiu	sp,sp,-32
+   80c04:	afbf0000 	sw	ra,0\(sp\)
+   80c08:	afbc0004 	sw	gp,4\(sp\)
+   80c0c:	3c1c0000 	lui	gp,0x0
+   80c10:	8f9c0000 	lw	gp,0\(gp\)
+   80c14:	8f9c0000 	lw	gp,0\(gp\)
+   80c18:	8f820010 	lw	v0,16\(gp\)
+   80c1c:	8c430000 	lw	v1,0\(v0\)
+   80c20:	24630001 	addiu	v1,v1,1
+   80c24:	ac430000 	sw	v1,0\(v0\)
+   80c28:	8f99000c 	lw	t9,12\(gp\)
+   80c2c:	0320f809 	jalr	t9
+   80c30:	00000000 	nop
+   80c34:	8f99fff4 	lw	t9,-12\(gp\)
+   80c38:	0320f809 	jalr	t9
+   80c3c:	00000000 	nop
+   80c40:	8f99fff0 	lw	t9,-16\(gp\)
+   80c44:	0320f809 	jalr	t9
+   80c48:	00000000 	nop
+   80c4c:	8fbf0000 	lw	ra,0\(sp\)
+   80c50:	8fbc0004 	lw	gp,4\(sp\)
+   80c54:	03e00008 	jr	ra
+   80c58:	27bd0020 	addiu	sp,sp,32
+
+00080c5c <slocal>:
+   80c5c:	03e00008 	jr	ra
+   80c60:	00000000 	nop
+
+00080c64 <sglobal>:
+   80c64:	03e00008 	jr	ra
+   80c68:	00000000 	nop
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-lib.nd b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-lib.nd
new file mode 100644
index 0000000..adbf7d7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-lib.nd
@@ -0,0 +1,9 @@
+#...
+Symbol table '\.dynsym' .*:
+#...
+.*: 00081410 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
+#...
+Symbol table '\.symtab' .*:
+#...
+.*: 00081410 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-lib.rd b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-lib.rd
new file mode 100644
index 0000000..12ceb00
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-lib.rd
@@ -0,0 +1,17 @@
+
+Relocation section '\.rela\.dyn' at offset .* contains .* entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+00080c0c  .*05 R_MIPS_HI16       00000000   __GOTT_BASE__ \+ 0
+00080c10  .*06 R_MIPS_LO16       00000000   __GOTT_BASE__ \+ 0
+00080c14  .*01 R_MIPS_16         00000000   __GOTT_INDEX__ \+ 0
+0008141c  00000002 R_MIPS_32                                    00080c5c
+00081800  00000002 R_MIPS_32                                    00080c5c
+00081804  00000002 R_MIPS_32                                    00081800
+00081808  .*02 R_MIPS_32         00081808   dglobal \+ 0
+0008180c  .*02 R_MIPS_32         00000000   dexternal \+ 0
+00081420  .*02 R_MIPS_32         00081c00   x \+ 0
+
+Relocation section '\.rela\.plt' at offset .* contains 2 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+00081400  .*7f R_MIPS_JUMP_SLOT  00000000   sexternal \+ 0
+00081404  .*7f R_MIPS_JUMP_SLOT  00080c64   sglobal \+ 0
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-lib.s b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-lib.s
new file mode 100644
index 0000000..827332c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-lib.s
@@ -0,0 +1,52 @@
+	.text
+	.globl	foo
+	.type	foo, @function
+foo:
+	addiu	$sp,$sp,-32
+	sw	$31,($sp)
+	sw	$28,4($sp)
+	lui	$28,%hi(__GOTT_BASE__)
+	lw	$28,%lo(__GOTT_BASE__)($28)
+	lw	$28,%half(__GOTT_INDEX__)($28)
+	lw	$2,%got(x)($28)
+	lw	$3,($2)
+	addiu	$3,$3,1
+	sw	$3,($2)
+	lw	$25,%got(slocal)($gp)
+	jalr	$25
+	lw	$25,%call16(sglobal)($gp)
+	jalr	$25
+	lw	$25,%call16(sexternal)($gp)
+	jalr	$25
+	lw	$31,($sp)
+	lw	$28,4($sp)
+	addiu	$sp,$sp,32
+	jr	$31
+	.size	foo, .-foo
+
+	.type	slocal, @function
+slocal:
+	jr	$31
+	.size	slocal, .-slocal
+
+	.globl	sglobal
+	.type	sglobal, @function
+sglobal:
+	jr	$31
+	.size	sglobal, .-sglobal
+
+	.comm	x,4,4
+
+	.data
+	.type	dlocal, @object
+dlocal:
+	.word	slocal
+	.word	dlocal
+	.size	dlocal, .-dlocal
+
+	.globl	dglobal
+	.type	dglobal, @object
+dglobal:
+	.word	dglobal
+	.word	dexternal
+	.size	dglobal, .-dglobal
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-lib.td b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-lib.td
new file mode 100644
index 0000000..9f223e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-lib.td
@@ -0,0 +1,3 @@
+#...
+ 0x0+16 \(TEXTREL\) +0x0
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-static.d b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-static.d
new file mode 100644
index 0000000..69765ae
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1-static.d
@@ -0,0 +1,4 @@
+#name: VxWorks executable test 1 (static)
+#source: vxworks1.s
+#ld: tmpdir/libvxworks1.so -Tvxworks1.ld [big_or_little_endian]
+#error: Dynamic sections created in non-dynamic link
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1.dd b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1.dd
new file mode 100644
index 0000000..af9e354
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1.dd
@@ -0,0 +1,51 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+00080800 <_PROCEDURE_LINKAGE_TABLE_>:
+   80800:	3c190008 	lui	t9,0x8
+			80800: R_MIPS_HI16	_GLOBAL_OFFSET_TABLE_
+   80804:	27391410 	addiu	t9,t9,5136
+			80804: R_MIPS_LO16	_GLOBAL_OFFSET_TABLE_
+   80808:	8f390008 	lw	t9,8\(t9\)
+   8080c:	00000000 	nop
+   80810:	03200008 	jr	t9
+   80814:	00000000 	nop
+   80818:	1000fff9 	b	80800 <_PROCEDURE_LINKAGE_TABLE_>
+   8081c:	24180000 	li	t8,0
+   80820:	3c190008 	lui	t9,0x8
+			80820: R_MIPS_HI16	_GLOBAL_OFFSET_TABLE_\+0xfffffff0
+   80824:	27391400 	addiu	t9,t9,5120
+			80824: R_MIPS_LO16	_GLOBAL_OFFSET_TABLE_\+0xfffffff0
+   80828:	8f390000 	lw	t9,0\(t9\)
+   8082c:	00000000 	nop
+   80830:	03200008 	jr	t9
+   80834:	00000000 	nop
+   80838:	1000fff1 	b	80800 <_PROCEDURE_LINKAGE_TABLE_>
+   8083c:	24180001 	li	t8,1
+   80840:	3c190008 	lui	t9,0x8
+			80840: R_MIPS_HI16	_GLOBAL_OFFSET_TABLE_\+0xfffffff4
+   80844:	27391404 	addiu	t9,t9,5124
+			80844: R_MIPS_LO16	_GLOBAL_OFFSET_TABLE_\+0xfffffff4
+   80848:	8f390000 	lw	t9,0\(t9\)
+   8084c:	00000000 	nop
+   80850:	03200008 	jr	t9
+   80854:	00000000 	nop
+Disassembly of section \.text:
+
+00080c00 <_start>:
+   80c00:	0c020210 	jal	80840 <_PROCEDURE_LINKAGE_TABLE_\+0x40>
+			80c00: R_MIPS_26	\.plt\+0x40
+   80c04:	00000000 	nop
+   80c08:	0c020306 	jal	80c18 <sexternal>
+			80c08: R_MIPS_26	sexternal
+   80c0c:	00000000 	nop
+   80c10:	08020208 	j	80820 <_PROCEDURE_LINKAGE_TABLE_\+0x20>
+			80c10: R_MIPS_26	\.plt\+0x20
+   80c14:	00000000 	nop
+
+00080c18 <sexternal>:
+   80c18:	03e00008 	jr	ra
+   80c1c:	00000000 	nop
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1.ld b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1.ld
new file mode 100644
index 0000000..8fe3c48
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1.ld
@@ -0,0 +1,32 @@
+SECTIONS
+{
+  . = 0x80000;
+  .interp : { *(.interp) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+
+  . = ALIGN (0x400);
+  .rela.dyn : { *(.rela.dyn) }
+  .rela.plt : { *(.rela.plt) }
+
+  . = ALIGN (0x400);
+  .plt : { *(.plt) }
+
+  . = ALIGN (0x400);
+  .text : { *(.text) }
+
+  . = ALIGN (0x1000);
+  .dynamic : { *(.dynamic) }
+
+  . = ALIGN (0x400);
+  .got : { *(.got.plt) *(.got) }
+
+  . = ALIGN (0x400);
+  .data : { *(.data) }
+
+  . = ALIGN (0x400);
+  .bss : { *(.bss) *(.dynbss) }
+
+  /DISCARD/ : { *(.reginfo) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1.rd b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1.rd
new file mode 100644
index 0000000..f4455f5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1.rd
@@ -0,0 +1,32 @@
+
+Relocation section '\.rela\.dyn' at offset .* contains 1 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name \+ Addend
+00081c00  .*7e R_MIPS_COPY       00081c00   dglobal \+ 0
+
+Relocation section '\.rela\.plt' at offset .* contains 2 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+00081400  .*7f R_MIPS_JUMP_SLOT  00080820   sglobal \+ 0
+00081404  .*7f R_MIPS_JUMP_SLOT  00080840   foo \+ 0
+
+Relocation section '\.rela\.text' at offset .* contains 3 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+00080c00  .*04 R_MIPS_26         00080800   \.plt \+ 40
+00080c08  .*04 R_MIPS_26         00080c18   sexternal \+ 0
+00080c10  .*04 R_MIPS_26         00080800   \.plt \+ 20
+
+Relocation section '\.rela\.data' at offset .* contains 3 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name \+ Addend
+00081800  .*02 R_MIPS_32         00081800   .data \+ 0
+00081804  .*02 R_MIPS_32         00081c00   .bss \+ 0
+00081808  .*02 R_MIPS_32         00081804   dexternal \+ 0
+
+Relocation section '\.rela\.plt\.unloaded' at offset .* contains 8 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+00080800  .*05 R_MIPS_HI16       00081410   _GLOBAL_OFFSET_TABLE_ \+ 0
+00080804  .*06 R_MIPS_LO16       00081410   _GLOBAL_OFFSET_TABLE_ \+ 0
+00081400  .*02 R_MIPS_32         00080800   _PROCEDURE_LINKAGE_TAB.* \+ 18
+00080820  .*05 R_MIPS_HI16       00081410   _GLOBAL_OFFSET_TABLE_ \+ fffffff0
+00080824  .*06 R_MIPS_LO16       00081410   _GLOBAL_OFFSET_TABLE_ \+ fffffff0
+00081404  .*02 R_MIPS_32         00080800   _PROCEDURE_LINKAGE_TAB.* \+ 38
+00080840  .*05 R_MIPS_HI16       00081410   _GLOBAL_OFFSET_TABLE_ \+ fffffff4
+00080844  .*06 R_MIPS_LO16       00081410   _GLOBAL_OFFSET_TABLE_ \+ fffffff4
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1.s b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1.s
new file mode 100644
index 0000000..33a247f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks1.s
@@ -0,0 +1,27 @@
+	.text
+	.globl	_start
+	.type	_start, @function
+_start:
+	jal	foo
+	jal	sexternal
+	j	sglobal
+	.size	_start, .-_start
+
+	.globl	sexternal
+	.type	sexternal, @function
+sexternal:
+	jr	$31
+	.size	sexternal, .-sexternal
+
+	.data
+	.type	dlocal, @object
+dlocal:
+	.word	dlocal
+	.size	dlocal, .-dlocal
+
+	.globl	dexternal
+	.type	dexternal, @object
+dexternal:
+	.word	dglobal
+	.word	dexternal
+	.size	dexternal, .-dexternal
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks2-static.sd b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks2-static.sd
new file mode 100644
index 0000000..912755b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks2-static.sd
@@ -0,0 +1,9 @@
+#...
+Elf file type is EXEC \(Executable file\)
+Entry point 0x80000
+#...
+Program Headers:
+  Type .*
+  LOAD .* 0x00080000 0x00080000 .* R E 0x1000
+
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks2.s b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks2.s
new file mode 100644
index 0000000..25f078e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks2.s
@@ -0,0 +1,5 @@
+	.globl	_start
+	.type	_start, @function
+_start:
+	jr	$31
+	.size	_start, .-_start
diff --git a/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks2.sd b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks2.sd
new file mode 100644
index 0000000..5ff87d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mips-elf/vxworks2.sd
@@ -0,0 +1,13 @@
+#...
+Elf file type is EXEC \(Executable file\)
+Entry point 0x80400
+#...
+Program Headers:
+  Type .*
+  PHDR .*
+#...
+  LOAD .* 0x00080000 0x00080000 .* R E 0x1000
+  LOAD .* 0x00081000 0x00081000 .* RW  0x1000
+  DYNAMIC .*
+
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/a.s b/binutils-2.19/ld/testsuite/ld-mmix/a.s
new file mode 100644
index 0000000..20e571b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/a.s
@@ -0,0 +1,5 @@
+* The symbol "a" is found here.
+ .text
+ .global a
+a:
+ SET $253,4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/areg-256.s b/binutils-2.19/ld/testsuite/ld-mmix/areg-256.s
new file mode 100644
index 0000000..21012d8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/areg-256.s
@@ -0,0 +1,2 @@
+ .global areg
+areg	IS $255+1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/areg-t.s b/binutils-2.19/ld/testsuite/ld-mmix/areg-t.s
new file mode 100644
index 0000000..364b01c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/areg-t.s
@@ -0,0 +1,3 @@
+ .text
+ .global areg
+areg SWYM 4,8,16
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/aregm.s b/binutils-2.19/ld/testsuite/ld-mmix/aregm.s
new file mode 100644
index 0000000..2dacbad
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/aregm.s
@@ -0,0 +1,5 @@
+  .global areg
+areg GREG Main+4
+  LDOU $3,areg,16
+  LDOU $3,$7,areg
+  LDOU $5,Main+8
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badfil1.d b/binutils-2.19/ld/testsuite/ld-mmix/b-badfil1.d
new file mode 100644
index 0000000..8a945fb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badfil1.d
@@ -0,0 +1,7 @@
+#source: b-twoinsn.s
+#source: b-badfil1.s
+#source: b-post1.s
+#source: b-goodmain.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: invalid mmo file: file number 42 `bar.s', was already entered as `foo.s'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badfil1.s b/binutils-2.19/ld/testsuite/ld-mmix/b-badfil1.s
new file mode 100644
index 0000000..256fa78
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badfil1.s
@@ -0,0 +1,10 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s and b-goodmain.s, and will provide two LOP_FILEs, but
+% specifying the same file number.
+ .text
+ .byte 0x98,06,42,2
+ .ascii "foo.s"
+ .byte 0,0,0
+ .byte 0x98,06,42,2
+ .ascii "bar.s"
+ .byte 0,0,0
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badfil2.d b/binutils-2.19/ld/testsuite/ld-mmix/b-badfil2.d
new file mode 100644
index 0000000..3f98a77
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badfil2.d
@@ -0,0 +1,7 @@
+#source: b-twoinsn.s
+#source: b-badfil2.s
+#source: b-post1.s
+#source: b-goodmain.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: invalid mmo file: file name for number 42 was not specified before use
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badfil2.s b/binutils-2.19/ld/testsuite/ld-mmix/b-badfil2.s
new file mode 100644
index 0000000..23d68ba
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badfil2.s
@@ -0,0 +1,6 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s and b-goodmain.s, and will provide a LOP_FILE for file
+% number 42, without specifying the file name, which an earlier LOP_FILE
+% for the same file number was supposed to have filled in
+ .text
+ .byte 0x98,06,42,0
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badfixo.d b/binutils-2.19/ld/testsuite/ld-mmix/b-badfixo.d
new file mode 100644
index 0000000..3cb6088
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badfixo.d
@@ -0,0 +1,7 @@
+#source: b-twoinsn.s
+#source: b-badfixo.s
+#source: b-post1.s
+#source: b-goodmain.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: invalid mmo file: .* lop_fixo
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badfixo.s b/binutils-2.19/ld/testsuite/ld-mmix/b-badfixo.s
new file mode 100644
index 0000000..93cd6d0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badfixo.s
@@ -0,0 +1,5 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s and b-goodmain.s, and will provide a LOP_FIXO with invalid;
+% (!= 1, != 2), YZ field.
+ .text
+ .byte 0x98,3,0,3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badloc.d b/binutils-2.19/ld/testsuite/ld-mmix/b-badloc.d
new file mode 100644
index 0000000..dce1ebf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badloc.d
@@ -0,0 +1,7 @@
+#source: b-twoinsn.s
+#source: b-badloc.s
+#source: b-post1.s
+#source: b-goodmain.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: invalid mmo file: .* lop_loc
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badloc.s b/binutils-2.19/ld/testsuite/ld-mmix/b-badloc.s
new file mode 100644
index 0000000..098098a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badloc.s
@@ -0,0 +1,5 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s and b-goodmain.s, and will provide a LOP_LOC with invalid;
+% (!= 1, != 2), YZ field.
+ .text
+ .byte 0x98,1,0,0
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badlop.d b/binutils-2.19/ld/testsuite/ld-mmix/b-badlop.d
new file mode 100644
index 0000000..b8c55e5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badlop.d
@@ -0,0 +1,7 @@
+#source: b-twoinsn.s
+#source: b-badlop.s
+#source: b-post1.s
+#source: b-goodmain.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: invalid mmo file: unsupported lopcode
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badlop.s b/binutils-2.19/ld/testsuite/ld-mmix/b-badlop.s
new file mode 100644
index 0000000..9e13332
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badlop.s
@@ -0,0 +1,4 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s and b-goodmain.s, and will provide an invalid lopcode.
+ .text
+ .byte 0x98,0xff,0,0
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badm.d b/binutils-2.19/ld/testsuite/ld-mmix/b-badm.d
new file mode 100644
index 0000000..39d8ecb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badm.d
@@ -0,0 +1,6 @@
+#source: b-twoinsn.s
+#source: b-post1.s
+#source: b-badmain.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: invalid mmo file: initialization value for .255 is not `Main'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badm2.s b/binutils-2.19/ld/testsuite/ld-mmix/b-badm2.s
new file mode 100644
index 0000000..eb94278
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badm2.s
@@ -0,0 +1,6 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s.  It will provide an incorrect LOP_END; its YZ field is not
+% the number of tetras to the preceding LOP_STAB.
+ .text
+ .byte 0x98,0x0b,0x00,0x00,0x20,0x3a,0x30,0x4d,0x20,0x61,0x20,0x69
+ .byte 0x01,0x6e,0x04,0x81,0x01,0x61,0x04,0x82,0x98,0x0c,0x00,0x03
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badmain.s b/binutils-2.19/ld/testsuite/ld-mmix/b-badmain.s
new file mode 100644
index 0000000..4736955
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badmain.s
@@ -0,0 +1,7 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s, and will provide the end of a mmo file with a value of
+% :Main that does not correspond to the address in the initialization of
+% $255 - the start address.
+ .text
+ .byte 0x98,0x0b,0,0,0x20,0x3a,0x30,0x4d,0x20,0x61,0x20,0x69
+ .byte 1,0x6e,0,0x81,1,0x61,4,0x82,0x98,0x0c,0,4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badquot.d b/binutils-2.19/ld/testsuite/ld-mmix/b-badquot.d
new file mode 100644
index 0000000..ae3d095
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badquot.d
@@ -0,0 +1,7 @@
+#source: b-twoinsn.s
+#source: b-badquot.s
+#source: b-post1.s
+#source: b-goodmain.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: invalid mmo file: .* lop_quote
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badquot.s b/binutils-2.19/ld/testsuite/ld-mmix/b-badquot.s
new file mode 100644
index 0000000..77742db
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badquot.s
@@ -0,0 +1,5 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s and b-goodmain.s, and will provide a LOP_QUOTE with invalid;
+% non-zero, YZ field.
+ .text
+ .byte 0x98,0,0xff,0
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badrx1.d b/binutils-2.19/ld/testsuite/ld-mmix/b-badrx1.d
new file mode 100644
index 0000000..1033476
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badrx1.d
@@ -0,0 +1,7 @@
+#source: b-twoinsn.s
+#source: b-badrx1.s
+#source: b-post1.s
+#source: b-goodmain.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: invalid mmo file: expected y = 0, .* lop_fixrx
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badrx1.s b/binutils-2.19/ld/testsuite/ld-mmix/b-badrx1.s
new file mode 100644
index 0000000..dd35763
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badrx1.s
@@ -0,0 +1,6 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s and b-goodmain.s, and will provide a LOP_FIXRX with invalid
+% (non-zero), Y field.
+ .text
+ .byte 0x98,5,1,0
+ .4byte 0
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badrx2.d b/binutils-2.19/ld/testsuite/ld-mmix/b-badrx2.d
new file mode 100644
index 0000000..6e13019
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badrx2.d
@@ -0,0 +1,7 @@
+#source: b-twoinsn.s
+#source: b-badrx2.s
+#source: b-post1.s
+#source: b-goodmain.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: invalid mmo file: expected z .* lop_fixrx
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badrx2.s b/binutils-2.19/ld/testsuite/ld-mmix/b-badrx2.s
new file mode 100644
index 0000000..20def6c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badrx2.s
@@ -0,0 +1,6 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s and b-goodmain.s, and will provide a LOP_FIXRX with invalid
+% (!= 16, != 24), Z field.
+ .text
+ .byte 0x98,5,0,8
+ .4byte 0
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badrx3.d b/binutils-2.19/ld/testsuite/ld-mmix/b-badrx3.d
new file mode 100644
index 0000000..c1cffed
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badrx3.d
@@ -0,0 +1,7 @@
+#source: b-twoinsn.s
+#source: b-badrx3.s
+#source: b-post1.s
+#source: b-goodmain.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: invalid mmo file: leading byte of operand word .* lop_fixrx
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-badrx3.s b/binutils-2.19/ld/testsuite/ld-mmix/b-badrx3.s
new file mode 100644
index 0000000..59cd5cb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-badrx3.s
@@ -0,0 +1,6 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s and b-goodmain.s, and will provide a LOP_FIXRX with invalid
+% (!= 0, != 1), first byte of the operand word.
+ .text
+ .byte 0x98,5,0,24
+ .byte 2,0,0,0
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-bend.s b/binutils-2.19/ld/testsuite/ld-mmix/b-bend.s
new file mode 100644
index 0000000..1168ee9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-bend.s
@@ -0,0 +1,6 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s and b-goodmain.s, and will provide an invalid LOP_END; one
+% not at the end of a file.  It also does not in YZ specify a correct
+% number of bytes between it and a preceding lop_stab.
+ .text
+ .byte 0x98,12,0,0
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-bend1.d b/binutils-2.19/ld/testsuite/ld-mmix/b-bend1.d
new file mode 100644
index 0000000..e747753
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-bend1.d
@@ -0,0 +1,11 @@
+#source: b-twoinsn.s
+#source: b-bend.s
+#source: b-post1.s
+#source: b-goodmain.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: invalid mmo file: lop_end not last item in file
+
+# This test depend on that the non-at-end condition is tested before
+# not-correct-YZ-field and might need tweaking if the implementation
+# changes.
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-bend2.d b/binutils-2.19/ld/testsuite/ld-mmix/b-bend2.d
new file mode 100644
index 0000000..234b4e5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-bend2.d
@@ -0,0 +1,10 @@
+#source: b-twoinsn.s
+#source: b-post1.s
+#source: b-goodmain.s
+#source: b-bend.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: invalid mmo file: lop_end not last item in file
+
+# We use the b-bend.s file just to make the correct lop_end in
+# b-goodmain.s not the last one.
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-bend3.d b/binutils-2.19/ld/testsuite/ld-mmix/b-bend3.d
new file mode 100644
index 0000000..3448c22
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-bend3.d
@@ -0,0 +1,6 @@
+#source: b-twoinsn.s
+#source: b-post1.s
+#source: b-badm2.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: invalid mmo file: YZ of lop_end .* not equal to the number of tetras to the preceding lop_stab
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-bstab1.d b/binutils-2.19/ld/testsuite/ld-mmix/b-bstab1.d
new file mode 100644
index 0000000..6281f06
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-bstab1.d
@@ -0,0 +1,7 @@
+#source: b-twoinsn.s
+#source: b-bstab1.s
+#source: b-post1.s
+#source: b-goodmain.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: invalid mmo file: fields y and z of lop_stab non-zero, y: 1, z: 2
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-bstab1.s b/binutils-2.19/ld/testsuite/ld-mmix/b-bstab1.s
new file mode 100644
index 0000000..0210106
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-bstab1.s
@@ -0,0 +1,5 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s and b-goodmain.s, and will provide an invalid LOP_STAB, one
+% with non-zero y and/or z.
+ .text
+ .byte 0x98,11,1,2
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-fixo2.d b/binutils-2.19/ld/testsuite/ld-mmix/b-fixo2.d
new file mode 100644
index 0000000..e8e2ff8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-fixo2.d
@@ -0,0 +1,27 @@
+#source: b-twoinsn.s
+#source: b-fixo2.s
+#source: b-post1.s
+#source: b-goodmain.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#objdump: -sht
+
+# Note that we "optimize" out the high tetrabyte of 0 written to
+# 2068098510aa5560, hence only the low part is left.
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+8  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 \.data         0+4  2068098510aa5564  2068098510aa5564  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD
+SYMBOL TABLE:
+0+4 g       \.text Main
+0+4 g       \.text a
+
+Contents of section \.text:
+ 0000 e3fd0001 e3fd0004                    .*
+Contents of section \.data:
+ 2068098510aa5564 00000008                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-fixo2.s b/binutils-2.19/ld/testsuite/ld-mmix/b-fixo2.s
new file mode 100644
index 0000000..f892999
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-fixo2.s
@@ -0,0 +1,6 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s and b-goodmain.s, and will provide a LOP_FIXO storing the
+% current address at address 0x2068098510aa5560.
+ .text
+ .byte 0x98,3,0x20,2
+ .8byte 0x68098510aa5560
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-goodmain.s b/binutils-2.19/ld/testsuite/ld-mmix/b-goodmain.s
new file mode 100644
index 0000000..c90063e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-goodmain.s
@@ -0,0 +1,5 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s, and will provide a valid end of a mmo file.
+ .text
+ .byte 0x98,0x0b,0x00,0x00,0x20,0x3a,0x30,0x4d,0x20,0x61,0x20,0x69
+ .byte 0x01,0x6e,0x04,0x81,0x01,0x61,0x04,0x82,0x98,0x0c,0x00,0x04
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-loc64k.d b/binutils-2.19/ld/testsuite/ld-mmix/b-loc64k.d
new file mode 100644
index 0000000..0124643
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-loc64k.d
@@ -0,0 +1,24 @@
+#source: b-loc64k.s
+#source: b-goodmain.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#objdump: -dht
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+10004  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+SYMBOL TABLE:
+0+4 g       \.text Main
+0+4 g       \.text a
+
+Disassembly of section \.text:
+
+0+ <Main-0x4>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <Main>:
+	\.\.\.
+   10000:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-loc64k.s b/binutils-2.19/ld/testsuite/ld-mmix/b-loc64k.s
new file mode 100644
index 0000000..ea563d2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-loc64k.s
@@ -0,0 +1,8 @@
+% The .text contents is supposed to be linked --oformat binary, and will
+% correspond to the start of a mmo file with two instructions, 64k apart.
+% This file ends before the LOP_STAB.
+ .text
+ .byte 0x98,9,1,1,0x3b,0x7f,0x9c,0xe3,0x98,1,0,2,0,0,0,0
+ .byte 0,0,0,0,0xe3,0xfd,0,1,0x98,1,0,2,0,0,0,0
+ .byte 0,1,0,0,0xe3,0xfd,0,4,0x98,0x0a,0,0xff,0,0,0,0
+ .byte 0,0,0,4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-nosym.d b/binutils-2.19/ld/testsuite/ld-mmix/b-nosym.d
new file mode 100644
index 0000000..c7953ec
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-nosym.d
@@ -0,0 +1,18 @@
+#source: b-twoinsn.s
+#source: b-post1.s
+#source: b-nosym.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#objdump: -st 2>/dev/null
+
+# Note that we have to redirect stderr when objdumping to get rid of the
+# "no symbols" message that would otherwise cause a spurious failure and
+# which we seemingly can't identify or prune in another way.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+no symbols
+
+Contents of section \.text:
+ 0000 e3fd0001 e3fd0004                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-nosym.s b/binutils-2.19/ld/testsuite/ld-mmix/b-nosym.s
new file mode 100644
index 0000000..08bfdbf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-nosym.s
@@ -0,0 +1,5 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s, and will provide a valid end of a mmo file but with no
+% symbols (if that is actually valid).
+ .text
+ .byte 0x98,0x0b,0x00,0x00,0x98,0x0c,0x00,0x00
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-offloc.s b/binutils-2.19/ld/testsuite/ld-mmix/b-offloc.s
new file mode 100644
index 0000000..c2fb2cc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-offloc.s
@@ -0,0 +1,9 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-post1.s and b-goodmain.s.  The code below will provide a LOP_LOC
+% with a 64-bit address (0x789abcdef0123456) then 16 bytes of % random data.
+
+ .text
+ .byte 0x98,1,0,2
+ .8byte 0x789abcdef0123458
+ .byte 0xb0,0x45,0x19,0x7d,0x2c,0x1b,0x3,0xb2
+ .byte 0xe4,0xdb,0xf8,0x77,0xf,0xc7,0x66,0xfb
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-post1.s b/binutils-2.19/ld/testsuite/ld-mmix/b-post1.s
new file mode 100644
index 0000000..a60aece
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-post1.s
@@ -0,0 +1,5 @@
+% The .text contents is supposed to be linked --oformat binary, and will
+% correspond to a LOP_POST for an initialization of $255 with 4.  A
+% LOP_STAB, such as in b-goodmain.s should follow.
+ .text
+ .byte 0x98,0x0a,0,0xff,0,0,0,0,0,0,0,4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-twoinsn.s b/binutils-2.19/ld/testsuite/ld-mmix/b-twoinsn.s
new file mode 100644
index 0000000..d9e0147
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-twoinsn.s
@@ -0,0 +1,7 @@
+% The .text contents is supposed to be linked --oformat binary, and will
+% correspond to the start of a mmo file with two instructions.  This file
+% ends before the LOP_STAB.
+ .text
+ .byte 0x98,9,1,1,0x3b,0x7f,0x9c,0xe3,0x98,1,0,2,0,0,0,0
+ .byte 0,0,0,0,0xe3,0xfd,0,1,0x98,1,0,2,0,0,0,0
+ .byte 0,0,0,4,0xe3,0xfd,0,4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-widec.s b/binutils-2.19/ld/testsuite/ld-mmix/b-widec.s
new file mode 100644
index 0000000..c6f8c30
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-widec.s
@@ -0,0 +1,7 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s, and will provide a valid end of a mmo file, but with the
+% "n" in :Main in wide character format; the widening is with a nil, so it
+% is treated like a normal "n".
+ .text
+ .byte 0x98,0x0b,0x00,0x00,0x20,0x3a,0x30,0x4d,0x20,0x61,0x20,0x69
+ .byte 0x81,0,0x6e,0x04,0x81,0x01,0x61,0x04,0x82,0,0,0,0x98,0x0c,0x00,0x05
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-widec1.d b/binutils-2.19/ld/testsuite/ld-mmix/b-widec1.d
new file mode 100644
index 0000000..e290ba1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-widec1.d
@@ -0,0 +1,12 @@
+#source: b-twoinsn.s
+#source: b-post1.s
+#source: b-widec.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#objdump: -t
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+4 g       \.text Main
+0+4 g       \.text a
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-widec2.d b/binutils-2.19/ld/testsuite/ld-mmix/b-widec2.d
new file mode 100644
index 0000000..4094b59
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-widec2.d
@@ -0,0 +1,6 @@
+#source: b-twoinsn.s
+#source: b-post1.s
+#source: b-widec2.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: unsupported wide character sequence 0xFF 0x6E
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-widec2.s b/binutils-2.19/ld/testsuite/ld-mmix/b-widec2.s
new file mode 100644
index 0000000..7745365
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-widec2.s
@@ -0,0 +1,7 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s, and will provide a valid end of a mmo file, but with the
+% "n" in :Main in wide character format; the widening is with a 0xff, so it
+% isn't supported, and the file is rejected.
+ .text
+ .byte 0x98,0x0b,0x00,0x00,0x20,0x3a,0x30,0x4d,0x20,0x61,0x20,0x69
+ .byte 0x81,0xff,0x6e,0x04,0x81,0x01,0x61,0x04,0x82,0,0,0,0x98,0x0c,0x00,0x05
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-widec3.d b/binutils-2.19/ld/testsuite/ld-mmix/b-widec3.d
new file mode 100644
index 0000000..f4cb3b9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-widec3.d
@@ -0,0 +1,6 @@
+#source: b-twoinsn.s
+#source: b-post1.s
+#source: b-widec3.s
+#ld: --oformat binary
+#objcopy_linked_file:
+#error: invalid symbol table: duplicate symbol `Main'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/b-widec3.s b/binutils-2.19/ld/testsuite/ld-mmix/b-widec3.s
new file mode 100644
index 0000000..0c02892
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/b-widec3.s
@@ -0,0 +1,8 @@
+% The .text contents is supposed to be linked --oformat binary with
+% b-twoinsn.s, and will provide a valid end of a mmo file, but with the
+% "n" in :Main in wide character format; the widening is with a nil, so it
+% is treated like a normal "n".  Also, it provides a normal "n", so the
+% two symbols collide.
+ .text
+ .byte 0x98,0x0b,0x00,0x00,0x20,0x3a,0x30,0x4d,0x20,0x61,0x20,0x69
+ .byte 0x91,0,0x6e,0x04,0x81,0x01,0x6e,0x04,0x83,1,0x01,0x61,0x04,0x82,0,0,0x98,0x0c,0,0x06
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-1.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-1.d
new file mode 100644
index 0000000..97bc33d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-1.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: bpo-1.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#objdump: -st
+
+# Just a simple linker-allocated GREG with no explicit GREGs.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0000000000000000 l    d  \.text	0+ (|\.text)
+0+7f0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+4 l       \.text	0+ x
+0+ g       \.text	0+ _start
+#...
+
+Contents of section \.text:
+ 0000 e3fd0001 232afe00                    .*
+Contents of section \.MMIX\.reg_contents:
+ 07f0 00000000 0000002e                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-1.s b/binutils-2.19/ld/testsuite/ld-mmix/bpo-1.s
new file mode 100644
index 0000000..0a76e40
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-1.s
@@ -0,0 +1,2 @@
+# A most simple instruction needing a linker-supplied GREG.
+x LDA $42,x+42
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-10.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-10.d
new file mode 100644
index 0000000..713d7ad
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-10.d
@@ -0,0 +1,22 @@
+#source: start4.s
+#source: bpo-6.s
+#source: bpo-5.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix --gc-sections
+#objdump: -st
+
+# Check that GC removes all (two) BPO:s when all are collected.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.init	0+ (|\.init)
+0+7f8 l +d  \.MMIX.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+ l       \.init	0+ _start
+2000000000000000 g       \*ABS\*	0+ __bss_start
+2000000000000000 g       \*ABS\*	0+ _edata
+2000000000000000 g       \*ABS\*	0+ _end
+0+4 g       \.init	0+ _start\.
+
+Contents of section \.init:
+ 0000 e37704a6                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-10.s b/binutils-2.19/ld/testsuite/ld-mmix/bpo-10.s
new file mode 100644
index 0000000..a4d1c12
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-10.s
@@ -0,0 +1,6 @@
+# Overflow; specify 223*8 registers.
+ .set i,0
+ .rept 223*4*8
+ LDA $11,_start+i*64
+ .set i,i+1
+ .endr
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-11.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-11.d
new file mode 100644
index 0000000..5925cff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-11.d
@@ -0,0 +1,31 @@
+#source: start3.s
+#source: bpo-6.s
+#source: bpo-2.s
+#source: bpo-5.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix --gc-sections
+#objdump: -st
+
+# Check that GC removes one of the three BPO:s, for the collected section.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.init	0+ (|\.init)
+0+10 l    d  \.text	0+ (|\.text)
+0+7e8 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+ l       \.init	0+ _start
+0+14 g       \.text	0+ x
+0+10 g       \.text	0+ x2
+2000000000000000 g       \*ABS\*	0+ __bss_start
+2000000000000000 g       \*ABS\*	0+ _edata
+2000000000000000 g       \*ABS\*	0+ _end
+0+10 g       \.text	0+ _start\.
+
+
+Contents of section \.init:
+ 0000 00000000 0000003d 00000000 0000003a  .*
+Contents of section \.text:
+ 0010 232dfe00 232dfd00                    .*
+Contents of section \.MMIX\.reg_contents:
+ 07e8 00000000 0000107c 00000000 0000a420  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-11.s b/binutils-2.19/ld/testsuite/ld-mmix/bpo-11.s
new file mode 100644
index 0000000..51ed92f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-11.s
@@ -0,0 +1,5 @@
+ .set i,0
+ .rept 222
+ LDA $11,_start+i*256
+ .set i,i+1
+ .endr
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-12.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-12.d
new file mode 100644
index 0000000..2961e8b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-12.d
@@ -0,0 +1,9 @@
+#source: start.s
+#source: bpo-7.s
+#source: greg-1.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#error: base-plus-offset relocation against register symbol
+
+# Check that we get an error message if we see a BPO against a register
+# symbol.  Variant 1: a GREG allocated register.
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-12m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-12m.d
new file mode 100644
index 0000000..7d847fe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-12m.d
@@ -0,0 +1,9 @@
+#source: start.s
+#source: bpo-7.s
+#source: greg-1.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#error: base-plus-offset relocation against register symbol
+
+# Check that we get an error message if we see a BPO against a register
+# symbol.  Variant 1: a GREG allocated register.
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-13.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-13.d
new file mode 100644
index 0000000..78f7c7a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-13.d
@@ -0,0 +1,9 @@
+#source: start.s
+#source: bpo-7.s
+#source: areg-256.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#error: base-plus-offset relocation against register symbol
+
+# Check that we get an error message if we see a BPO against a register
+# symbol.  Variant 2: a register symbol.
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-13m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-13m.d
new file mode 100644
index 0000000..8bd0bf6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-13m.d
@@ -0,0 +1,9 @@
+#source: start.s
+#source: bpo-7.s
+#source: areg-256.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#error: base-plus-offset relocation against register symbol
+
+# Check that we get an error message if we see a BPO against a register
+# symbol.  Variant 2: a register symbol.
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-14.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-14.d
new file mode 100644
index 0000000..e19e4a8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-14.d
@@ -0,0 +1,22 @@
+#source: start.s
+#source: bpo-7.s
+#source: areg-t.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#objdump: -st
+
+# A BPO against an external symbol.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+7f0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+ g       \.text	0+ _start
+0+8 g       \.text	0+ areg
+#...
+
+Contents of section \.text:
+ 0000 e3fd0001 234dfe00 fd040810           .*
+Contents of section \.MMIX\.reg_contents:
+ 07f0 00000000 00000003                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-14m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-14m.d
new file mode 100644
index 0000000..541b108
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-14m.d
@@ -0,0 +1,20 @@
+#source: start.s
+#source: bpo-7.s
+#source: areg-t.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#objdump: -st
+
+# A BPO against an external symbol.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g       \.text Main
+0+ g       \.text _start
+0+8 g       \.text areg
+
+Contents of section \.text:
+ 0000 e3fd0001 234dfe00 fd040810           .*
+Contents of section \.MMIX\.reg_contents:
+ 07f0 00000000 00000003                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-15.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-15.d
new file mode 100644
index 0000000..6845a87
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-15.d
@@ -0,0 +1,7 @@
+#source: start.s
+#source: bpo-7.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#error: ^[^c][^h][^i][^l][^d].* undefined reference to `areg'$
+
+# A BPO against an undefined symbol.
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-15m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-15m.d
new file mode 100644
index 0000000..eacedf5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-15m.d
@@ -0,0 +1,7 @@
+#source: start.s
+#source: bpo-7.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#error: ^[^c][^h][^i][^l][^d].* undefined reference to `areg'$
+
+# A BPO against an undefined symbol.
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-16.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-16.d
new file mode 100644
index 0000000..d7e372c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-16.d
@@ -0,0 +1,23 @@
+#source: start.s
+#source: bpo-7.s
+#source: bpo-7.s
+#source: areg-t.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#objdump: -st
+
+# Two BPO:s against the same value get merged.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+7f0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+ g       \.text	0+ _start
+0+c g       \.text	0+ areg
+#...
+
+Contents of section \.text:
+ 0000 e3fd0001 234dfe00 234dfe00 fd040810  .*
+Contents of section \.MMIX\.reg_contents:
+ 07f0 00000000 00000007                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-16m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-16m.d
new file mode 100644
index 0000000..f1fe336
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-16m.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: bpo-7.s
+#source: bpo-7.s
+#source: areg-t.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#objdump: -st
+
+# Two BPO:s against the same value get merged.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g       \.text Main
+0+ g       \.text _start
+0+c g       \.text areg
+
+Contents of section \.text:
+ 0000 e3fd0001 234dfe00 234dfe00 fd040810  .*
+Contents of section \.MMIX\.reg_contents:
+ 07f0 00000000 00000007                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-17.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-17.d
new file mode 100644
index 0000000..f70b852
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-17.d
@@ -0,0 +1,23 @@
+#source: start.s
+#source: bpo-8.s
+#source: areg-t.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#objdump: -st
+
+# A BPO and another reloc in the same section.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+7f0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+ g       \.text	0+ _start
+0+10 g       \.text	0+ areg
+#...
+
+Contents of section \.text:
+ 0000 e3fd0001 2336fe00 00000000 0000000c  .*
+ 0010 fd040810                             .*
+Contents of section \.MMIX\.reg_contents:
+ 07f0 00000000 00000008                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-17m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-17m.d
new file mode 100644
index 0000000..6458ebe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-17m.d
@@ -0,0 +1,22 @@
+#source: start.s
+#source: bpo-8.s
+#source: areg-t.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#objdump: -st
+
+# A BPO and another reloc in the same section.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g       \.text Main
+0+ g       \.text _start
+0+10 g       \.text areg
+
+
+Contents of section \.text:
+ 0000 e3fd0001 2336fe00 00000000 0000000c  .*
+ 0010 fd040810                             .*
+Contents of section \.MMIX\.reg_contents:
+ 07f0 00000000 00000008                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-18.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-18.d
new file mode 100644
index 0000000..3d1d2f1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-18.d
@@ -0,0 +1,29 @@
+#source: start.s
+#source: bpo-1.s
+#source: bpo-2.s
+#source: bpo-5.s
+#source: bpo-6.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix -T$srcdir/$subdir/bpo64addr.ld
+#objdump: -st
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+100 l    d  \.text	0+ (|\.text)
+4000000000001060 l    d  \.text\.away	0+ (|\.text\.away)
+0+7e0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+4000000000001064 l       \.text\.away	0+ x
+0+100 g       \.text	0+ x
+4000000000001060 g       \.text\.away	0+ Main
+0+104 g       \.text	0+ x2
+4000000000001060 g       \.text\.away	0+ _start
+4000000000001068 g       \.text\.away	0+ y
+
+Contents of section \.text:
+ 0100 232dfc00 232dfd00                    .*
+Contents of section \.text\.away:
+ 4000000000001060 e3fd0001 232afe1e 2321fe00           .*
+Contents of section \.MMIX\.reg_contents:
+ 07e0 00000000 00001168 00000000 0000a514  .*
+ 07f0 40000000 00001070                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-18m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-18m.d
new file mode 100644
index 0000000..b21b6cf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-18m.d
@@ -0,0 +1,25 @@
+#source: start.s
+#source: bpo-1.s
+#source: bpo-2.s
+#source: bpo-5.s
+#source: bpo-6.s
+#as: -linker-allocated-gregs
+#ld: -m mmo -T$srcdir/$subdir/bpo64addr.ld
+#objdump: -st
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+4000000000001060 g       \*ABS\* Main
+0+100 g       \.text x
+0+104 g       \.text x2
+4000000000001060 g       \*ABS\* _start
+4000000000001068 g       \*ABS\* y
+
+Contents of section \.text:
+ 0100 232dfc00 232dfd00                    .*
+Contents of section \.text\.away:
+ 4000000000001060 e3fd0001 232afe1e 2321fe00           .*
+Contents of section \.MMIX\.reg_contents:
+ 07e0 00000000 00001168 00000000 0000a514  .*
+ 07f0 40000000 00001070                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-19.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-19.d
new file mode 100644
index 0000000..d8ee554
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-19.d
@@ -0,0 +1,33 @@
+#source: start.s
+#source: bpo-9.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#objdump: -st
+
+# 223 (max) linker-allocated GREGs, four relocs merged for each register
+# allocated.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+100 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+#...
+0+ g       \.text	0+ _start
+#...
+
+Contents of section \.text:
+ 0000 e3fd0001 230b2000 230b2040 230b2080  .*
+ 0010 230b20c0 230b2100 230b2140 230b2180  .*
+ 0020 230b21c0 230b2200 230b2240 230b2280  .*
+#...
+ 0dd0 230bfcc0 230bfd00 230bfd40 230bfd80  .*
+ 0de0 230bfdc0 230bfe00 230bfe40 230bfe80  .*
+ 0df0 230bfec0                             .*
+Contents of section \.MMIX\.reg_contents:
+ 0100 00000000 00000000 00000000 00000100  .*
+ 0110 00000000 00000200 00000000 00000300  .*
+#...
+ 07d0 00000000 0000da00 00000000 0000db00  .*
+ 07e0 00000000 0000dc00 00000000 0000dd00  .*
+ 07f0 00000000 0000de00                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-19m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-19m.d
new file mode 100644
index 0000000..7f740e1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-19m.d
@@ -0,0 +1,30 @@
+#source: start.s
+#source: bpo-9.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#objdump: -st
+
+# 223 (max) linker-allocated GREGs, four relocs merged for each register
+# allocated.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g       \.text Main
+0+ g       \.text _start
+
+Contents of section \.text:
+ 0000 e3fd0001 230b2000 230b2040 230b2080  .*
+ 0010 230b20c0 230b2100 230b2140 230b2180  .*
+ 0020 230b21c0 230b2200 230b2240 230b2280  .*
+#...
+ 0dd0 230bfcc0 230bfd00 230bfd40 230bfd80  .*
+ 0de0 230bfdc0 230bfe00 230bfe40 230bfe80  .*
+ 0df0 230bfec0                             .*
+Contents of section \.MMIX\.reg_contents:
+ 0100 00000000 00000000 00000000 00000100  .*
+ 0110 00000000 00000200 00000000 00000300  .*
+#...
+ 07d0 00000000 0000da00 00000000 0000db00  .*
+ 07e0 00000000 0000dc00 00000000 0000dd00  .*
+ 07f0 00000000 0000de00                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-1m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-1m.d
new file mode 100644
index 0000000..b2d0384
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-1m.d
@@ -0,0 +1,18 @@
+#source: start.s
+#source: bpo-1.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#objdump: -st
+
+# Just a simple linker-allocated GREG with no explicit GREGs.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g       \.text Main
+0+ g       \.text _start
+
+Contents of section \.text:
+ 0000 e3fd0001 232afe00                    .*
+Contents of section \.MMIX\.reg_contents:
+ 07f0 00000000 0000002e                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-2.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-2.d
new file mode 100644
index 0000000..7206cab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-2.d
@@ -0,0 +1,23 @@
+#source: start.s
+#source: greg-1.s
+#source: bpo-1.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#objdump: -st
+
+# Just a simple linker-allocated GREG plus one explicit GREG.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+7e8 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+4 l       \.text	0+ x
+0+ g       \.text	0+ _start
+0+fe g       \*REG\*	0+ areg
+#...
+
+Contents of section \.text:
+ 0000 e3fd0001 232afd00                    .*
+Contents of section \.MMIX\.reg_contents:
+ 07e8 00000000 0000002e 00007048 860f3a38  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-2.s b/binutils-2.19/ld/testsuite/ld-mmix/bpo-2.s
new file mode 100644
index 0000000..02c7901
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-2.s
@@ -0,0 +1,2 @@
+	.global y
+y	LDA	$33,y+8
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-20.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-20.d
new file mode 100644
index 0000000..f05edfb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-20.d
@@ -0,0 +1,8 @@
+#source: start.s
+#source: bpo-10.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#error: Too many global registers
+
+# Check that many too many gregs are recognized (and not signed/unsigned
+# bugs with checks for < 32 appear).
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-20m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-20m.d
new file mode 100644
index 0000000..91126b4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-20m.d
@@ -0,0 +1,8 @@
+#source: start.s
+#source: bpo-10.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#error: Too many global registers
+
+# Check that many too many gregs are recognized (and not signed/unsigned
+# bugs with checks for < 32 appear).
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-21.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-21.d
new file mode 100644
index 0000000..f208cb6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-21.d
@@ -0,0 +1,10 @@
+#source: start.s
+#source: bpo-11.s
+#source: bpo-7.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#error: ^[^c][^h][^i][^l][^d].* undefined reference to `areg'$
+
+# A BPO reloc against an undefined symbol, with a full set of normal
+# BPO:s.
+
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-21m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-21m.d
new file mode 100644
index 0000000..b437dd3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-21m.d
@@ -0,0 +1,9 @@
+#source: start.s
+#source: bpo-11.s
+#source: bpo-7.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#error: ^[^c][^h][^i][^l][^d].* undefined reference to `areg'$
+
+# A BPO reloc against an undefined symbol, with a full set of normal
+# BPO:s.
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-22.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-22.d
new file mode 100644
index 0000000..c6a1314
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-22.d
@@ -0,0 +1,22 @@
+#source: start.s
+#source: bpo-1.s
+#as: -linker-allocated-gregs
+#ld: -m mmo --oformat elf64-mmix
+#objdump: -st
+
+# This weird combination of format and emulation options caused hiccups in
+# the reloc accounting machinery.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0000000000000000 l    d  \.text	0+ (|\.text)
+0+7f0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+4 l       \.text	0+ x
+0+ g       \.text	0+ Main
+0+ g       \.text	0+ _start
+
+Contents of section \.text:
+ 0000 e3fd0001 232afe00                    .*
+Contents of section \.MMIX\.reg_contents:
+ 07f0 00000000 0000002e                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-2m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-2m.d
new file mode 100644
index 0000000..7ddcfd2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-2m.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: greg-1.s
+#source: bpo-1.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#objdump: -st
+
+# Just a simple linker-allocated GREG plus one explicit GREG.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g       \.text Main
+0+ g       \.text _start
+0+fe g       \*REG\* areg
+
+Contents of section \.text:
+ 0000 e3fd0001 232afd00                    .*
+Contents of section \.MMIX\.reg_contents:
+ 07e8 00000000 0000002e 00007048 860f3a38  .*
+
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-3.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-3.d
new file mode 100644
index 0000000..e1435ef
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-3.d
@@ -0,0 +1,24 @@
+#source: start.s
+#source: bpo-1.s
+#source: bpo-2.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#objdump: -st
+
+# Just two BPO relocs merged as one linker-allocated GREG.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+7f0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+4 l       \.text	0+ x
+0+ g       \.text	0+ _start
+#...
+0+8 g       \.text	0+ y
+#...
+
+Contents of section \.text:
+ 0000 e3fd0001 232afe1e 2321fe00           .*
+Contents of section \.MMIX\.reg_contents:
+ 07f0 00000000 00000010                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-3.s b/binutils-2.19/ld/testsuite/ld-mmix/bpo-3.s
new file mode 100644
index 0000000..b975a82
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-3.s
@@ -0,0 +1 @@
+ LDOU $121,_start+42+4+4+257
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-3m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-3m.d
new file mode 100644
index 0000000..c0f4707
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-3m.d
@@ -0,0 +1,20 @@
+#source: start.s
+#source: bpo-1.s
+#source: bpo-2.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#objdump: -st
+
+# Just two BPO relocs merged as one linker-allocated GREG.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g       \.text Main
+0+ g       \.text _start
+0+8 g       \.text y
+
+Contents of section \.text:
+ 0000 e3fd0001 232afe1e 2321fe00           .*
+Contents of section \.MMIX\.reg_contents:
+ 07f0 00000000 00000010                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-4.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-4.d
new file mode 100644
index 0000000..372e7e6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-4.d
@@ -0,0 +1,25 @@
+#source: start.s
+#source: greg-1.s
+#source: bpo-3.s
+#source: bpo-1.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#objdump: -st
+
+# Three GREGs: one explicit, two linker-allocated.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+7e0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+8 l       \.text	0+ x
+0+ g       \.text	0+ _start
+0+fe g       \*REG\*	0+ areg
+#...
+
+Contents of section \.text:
+ 0000 e3fd0001 8f79fd00 232afc00           .*
+Contents of section \.MMIX\.reg_contents:
+ 07e0 00000000 00000032 00000000 00000133  .*
+ 07f0 00007048 860f3a38                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-4.s b/binutils-2.19/ld/testsuite/ld-mmix/bpo-4.s
new file mode 100644
index 0000000..c5c21cf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-4.s
@@ -0,0 +1,5 @@
+ .set i,0
+ .rept 223
+ LDA $11,_start+i*256
+ .set i,i+1
+ .endr
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-4m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-4m.d
new file mode 100644
index 0000000..2f3b59c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-4m.d
@@ -0,0 +1,22 @@
+#source: start.s
+#source: greg-1.s
+#source: bpo-3.s
+#source: bpo-1.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#objdump: -st
+
+# Three GREGs: one explicit, two linker-allocated.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g       \.text Main
+0+ g       \.text _start
+0+fe g       \*REG\* areg
+
+Contents of section \.text:
+ 0000 e3fd0001 8f79fd00 232afc00           .*
+Contents of section \.MMIX\.reg_contents:
+ 07e0 00000000 00000032 00000000 00000133  .*
+ 07f0 00007048 860f3a38                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-5.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-5.d
new file mode 100644
index 0000000..a1a192d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-5.d
@@ -0,0 +1,25 @@
+#source: start.s
+#source: bpo-1.s
+#source: bpo-3.s
+#source: bpo-2.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#objdump: -st
+
+# Three linker-allocated GREGs: one eliminated.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+7e8 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+4 l       \.text	0+ x
+0+ g       \.text	0+ _start
+#...
+0+c g       \.text	0+ y
+#...
+
+Contents of section \.text:
+ 0000 e3fd0001 232afd1a 8f79fe00 2321fd00  .*
+Contents of section \.MMIX\.reg_contents:
+ 07e8 00000000 00000014 00000000 00000133  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-5.s b/binutils-2.19/ld/testsuite/ld-mmix/bpo-5.s
new file mode 100644
index 0000000..c0fcfac
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-5.s
@@ -0,0 +1,4 @@
+# A section with a symbol and a BPO allocation.
+ .section .text.x,"ax",@progbits
+ .global x
+x LDA $45,x+4200
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-5m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-5m.d
new file mode 100644
index 0000000..078d34e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-5m.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: bpo-1.s
+#source: bpo-3.s
+#source: bpo-2.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#objdump: -st
+
+# Three linker-allocated GREGs: one eliminated.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g       \.text Main
+0+ g       \.text _start
+0+c g       \.text y
+
+Contents of section \.text:
+ 0000 e3fd0001 232afd1a 8f79fe00 2321fd00  .*
+Contents of section \.MMIX\.reg_contents:
+ 07e8 00000000 00000014 00000000 00000133  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-6.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-6.d
new file mode 100644
index 0000000..a5978c9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-6.d
@@ -0,0 +1,30 @@
+#source: start.s
+#source: bpo-4.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#objdump: -st
+
+# 223 (max) linker-allocated GREGs.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+100 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+#...
+0+ g       \.text	0+ _start
+#...
+
+Contents of section \.text:
+ 0000 e3fd0001 230b2000 230b2100 230b2200  .*
+ 0010 230b2300 230b2400 230b2500 230b2600  .*
+#...
+ 0360 230bf700 230bf800 230bf900 230bfa00  .*
+ 0370 230bfb00 230bfc00 230bfd00 230bfe00  .*
+Contents of section \.MMIX\.reg_contents:
+ 0100 00000000 00000000 00000000 00000100  .*
+ 0110 00000000 00000200 00000000 00000300  .*
+#...
+ 07d0 00000000 0000da00 00000000 0000db00  .*
+ 07e0 00000000 0000dc00 00000000 0000dd00  .*
+ 07f0 00000000 0000de00                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-6.s b/binutils-2.19/ld/testsuite/ld-mmix/bpo-6.s
new file mode 100644
index 0000000..a10e9a8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-6.s
@@ -0,0 +1,4 @@
+# A section with a symbol and a BPO allocation.
+ .section .text.x2,"ax",@progbits
+ .global x2
+x2 LDA $45,x2+42000
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-6m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-6m.d
new file mode 100644
index 0000000..9d8e304
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-6m.d
@@ -0,0 +1,27 @@
+#source: start.s
+#source: bpo-4.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#objdump: -st
+
+# 223 (max) linker-allocated GREGs.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g       \.text Main
+0+ g       \.text _start
+
+Contents of section \.text:
+ 0000 e3fd0001 230b2000 230b2100 230b2200  .*
+ 0010 230b2300 230b2400 230b2500 230b2600  .*
+#...
+ 0360 230bf700 230bf800 230bf900 230bfa00  .*
+ 0370 230bfb00 230bfc00 230bfd00 230bfe00  .*
+Contents of section \.MMIX\.reg_contents:
+ 0100 00000000 00000000 00000000 00000100  .*
+ 0110 00000000 00000200 00000000 00000300  .*
+#...
+ 07d0 00000000 0000da00 00000000 0000db00  .*
+ 07e0 00000000 0000dc00 00000000 0000dd00  .*
+ 07f0 00000000 0000de00                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-7.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-7.d
new file mode 100644
index 0000000..693a502
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-7.d
@@ -0,0 +1,6 @@
+#source: start.s
+#source: bpo-4.s
+#source: greg-1.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#error: Too many global registers: 224
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-7.s b/binutils-2.19/ld/testsuite/ld-mmix/bpo-7.s
new file mode 100644
index 0000000..b920764
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-7.s
@@ -0,0 +1,2 @@
+# If the symbol is a register then this is an error.
+ LDA $77,areg-5
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-7m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-7m.d
new file mode 100644
index 0000000..21c4659
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-7m.d
@@ -0,0 +1,6 @@
+#source: start.s
+#source: bpo-4.s
+#source: greg-1.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#error: Too many global registers: 224
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-8.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-8.d
new file mode 100644
index 0000000..438b072
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-8.d
@@ -0,0 +1,7 @@
+#source: start.s
+#source: bpo-4.s
+#source: pad2p18m32.s
+#source: bpo-1.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix
+#error: Too many global registers: 224
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-8.s b/binutils-2.19/ld/testsuite/ld-mmix/bpo-8.s
new file mode 100644
index 0000000..ebe410d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-8.s
@@ -0,0 +1,3 @@
+# A BPO and an ordinary reloc in the same section.
+ LDA $54,areg-8
+ .quad areg-4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-8m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-8m.d
new file mode 100644
index 0000000..9187672
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-8m.d
@@ -0,0 +1,7 @@
+#source: start.s
+#source: bpo-4.s
+#source: pad2p18m32.s
+#source: bpo-1.s
+#as: -linker-allocated-gregs
+#ld: -m mmo
+#error: Too many global registers: 224
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-9.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-9.d
new file mode 100644
index 0000000..16d0017
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-9.d
@@ -0,0 +1,26 @@
+#source: start3.s
+#source: bpo-6.s
+#source: bpo-5.s
+#as: -linker-allocated-gregs
+#ld: -m elf64mmix --gc-sections
+#objdump: -st
+
+# Check that GC does not mess up things when no BPO:s are collected.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.init	0+ (|\.init)
+0+10 l    d  \.text	0+ (|\.text)
+0+7e8 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+ l       \.init	0+ _start
+0+14 g       \.text	0+ x
+0+10 g       \.text	0+ x2
+#...
+
+Contents of section \.init:
+ 0000 00000000 0000003d 00000000 0000003a  .*
+Contents of section \.text:
+ 0010 232dfe00 232dfd00                    .*
+Contents of section \.MMIX\.reg_contents:
+ 07e8 00000000 0000107c 00000000 0000a420  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-9.s b/binutils-2.19/ld/testsuite/ld-mmix/bpo-9.s
new file mode 100644
index 0000000..a608c68
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-9.s
@@ -0,0 +1,5 @@
+ .set i,0
+ .rept 223*4
+ LDA $11,_start+i*64
+ .set i,i+1
+ .endr
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo-9m.d b/binutils-2.19/ld/testsuite/ld-mmix/bpo-9m.d
new file mode 100644
index 0000000..fa3f97c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo-9m.d
@@ -0,0 +1,22 @@
+#source: start3.s
+#source: bpo-6.s
+#source: bpo-5.s
+#as: -linker-allocated-gregs
+#ld: -m mmo --gc-sections
+#objdump: -st
+
+# Check that GC does not mess up things when no BPO:s are collected.
+# Note that mmo doesn't support GC at the moment; it's a nop.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g       \.text Main
+0+4 g       \.text x
+0+ g       \.text x2
+
+Contents of section \.text:
+ 0000 232dfe00 232dfd00 00000000 0000002d  .*
+ 0010 00000000 0000002a                    .*
+Contents of section \.MMIX\.reg_contents:
+ 07e8 00000000 0000106c 00000000 0000a410  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bpo64addr.ld b/binutils-2.19/ld/testsuite/ld-mmix/bpo64addr.ld
new file mode 100644
index 0000000..0324aa5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bpo64addr.ld
@@ -0,0 +1,13 @@
+OUTPUT_ARCH(mmix)
+ENTRY(Main)
+SECTIONS
+{
+  .text 0x100 :
+  { *(.text.x); *(.text.x2); }
+
+  .text.away 0x4000000000001060 :
+  { *(.text); Main = _start; }
+
+  .MMIX.reg_contents :
+  { *(.MMIX.reg_contents.linker_allocated); *(.MMIX.reg_contents); }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bspec1.d b/binutils-2.19/ld/testsuite/ld-mmix/bspec1.d
new file mode 100644
index 0000000..79d53d4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bspec1.d
@@ -0,0 +1,43 @@
+#source: bspec1.s
+#source: start.s
+#ld: -m elf64mmix
+#readelf: -Ssr -x1 -x2
+
+There are 6 section headers, starting at offset 0xb8:
+
+Section Headers:
+  \[Nr\] Name              Type             Address           Offset
+       Size              EntSize          Flags  Link  Info  Align
+  \[ 0\]                   NULL             0+  0+
+       0+  0+           0     0     0
+  \[ 1\] \.text             PROGBITS         0+  0+78
+       0+4  0+  AX       0     0     4
+  \[ 2\] \.MMIX\.spec_data\.2 PROGBITS         0+  0+7c
+       0+4  0+           0     0     4
+  \[ 3\] \.shstrtab         STRTAB           0+  0+80
+       0+33  0+           0     0     1
+  \[ 4\] \.symtab           SYMTAB           0+  0+238
+       0+d8  0+18           5     3     8
+  \[ 5\] \.strtab           STRTAB           0+  0+310
+       0+2d  0+           0     0     1
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+There are no relocations in this file\.
+
+Symbol table '\.symtab' contains 9 entries:
+   Num:    Value          Size Type    Bind   Vis      Ndx Name
+     0: 0+     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 0+     0 SECTION LOCAL  DEFAULT    1 
+     2: 0+     0 SECTION LOCAL  DEFAULT    2 
+     3: 0+     0 FUNC    GLOBAL DEFAULT    1 Main
+     4: 0+     0 NOTYPE  GLOBAL DEFAULT    1 _start
+#...
+
+Hex dump of section '\.text':
+  0x0+ e3fd0001                            .*
+
+Hex dump of section '\.MMIX\.spec_data\.2':
+  0x0+ 0000002a                            .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bspec1.s b/binutils-2.19/ld/testsuite/ld-mmix/bspec1.s
new file mode 100644
index 0000000..0c1707f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bspec1.s
@@ -0,0 +1,3 @@
+ BSPEC 2
+ TETRA :Main+42
+ ESPEC
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bspec1m.d b/binutils-2.19/ld/testsuite/ld-mmix/bspec1m.d
new file mode 100644
index 0000000..c3fedf8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bspec1m.d
@@ -0,0 +1,15 @@
+#source: bspec1.s
+#source: start.s
+#ld: -m mmo
+#objdump: -str
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g       \.text Main
+0+ g       \.text _start
+
+Contents of section \.text:
+ 0+ e3fd0001                             .*
+Contents of section \.MMIX\.spec_data\.2:
+ 0000 0000002a                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bspec2.d b/binutils-2.19/ld/testsuite/ld-mmix/bspec2.d
new file mode 100644
index 0000000..98296e7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bspec2.d
@@ -0,0 +1,53 @@
+#source: bspec1.s
+#source: bspec2.s
+#source: bspec1.s
+#source: start.s
+#source: ext1.s
+#ld: -m elf64mmix
+#readelf: -Ssr -x1 -x2 -x3
+
+There are 7 section headers, starting at offset 0xd0:
+
+Section Headers:
+  \[Nr\] Name              Type             Address           Offset
+       Size              EntSize          Flags  Link  Info  Align
+  \[ 0\]                   NULL             0+  0+
+       0+  0+           0     0     0
+  \[ 1\] \.text             PROGBITS         0+  0+78
+       0+4  0+  AX       0     0     4
+  \[ 2\] \.MMIX\.spec_data\.2 PROGBITS         0+  0+7c
+       0+8  0+           0     0     4
+  \[ 3\] \.MMIX\.spec_data\.3 PROGBITS         0+  0+84
+       0+4  0+           0     0     4
+  \[ 4\] \.shstrtab         STRTAB           0+  0+88
+       0+45  0+           0     0     1
+  \[ 5\] \.symtab           SYMTAB           0+  0+290
+       0+108  0+18           6     4     8
+  \[ 6\] \.strtab           STRTAB           0+  0+398
+       0+32  0+           0     0     1
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+There are no relocations in this file\.
+
+Symbol table '\.symtab' contains 11 entries:
+   Num:    Value          Size Type    Bind   Vis      Ndx Name
+     0: 0+     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 0+     0 SECTION LOCAL  DEFAULT    1 
+     2: 0+     0 SECTION LOCAL  DEFAULT    2 
+     3: 0+     0 SECTION LOCAL  DEFAULT    3 
+     4: 0+     0 FUNC    GLOBAL DEFAULT    1 Main
+     5: 0+fc     0 NOTYPE  GLOBAL DEFAULT  ABS ext1
+     6: 0+     0 NOTYPE  GLOBAL DEFAULT    1 _start
+#...
+
+Hex dump of section '\.text':
+  0x0+ e3fd0001                            .*
+
+Hex dump of section '\.MMIX\.spec_data\.2':
+  0x0+ 0000002a 0000002a                   .*
+
+Hex dump of section '\.MMIX\.spec_data\.3':
+  0x0+ 000000fc                            .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bspec2.s b/binutils-2.19/ld/testsuite/ld-mmix/bspec2.s
new file mode 100644
index 0000000..f939d77
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bspec2.s
@@ -0,0 +1,3 @@
+ BSPEC 3
+ TETRA ext1
+ ESPEC
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bspec2m.d b/binutils-2.19/ld/testsuite/ld-mmix/bspec2m.d
new file mode 100644
index 0000000..11bd48e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bspec2m.d
@@ -0,0 +1,21 @@
+#source: bspec1.s
+#source: bspec2.s
+#source: bspec1.s
+#source: start.s
+#source: ext1.s
+#ld: -m mmo
+#objdump: -str
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g       \.text Main
+0+fc g       \*ABS\* ext1
+0+ g       \.text _start
+
+Contents of section \.text:
+ 0+ e3fd0001                             .*
+Contents of section \.MMIX\.spec_data\.2:
+ 0000 0000002a 0000002a                    .*
+Contents of section \.MMIX\.spec_data\.3:
+ 0000 000000fc                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bspec801.s b/binutils-2.19/ld/testsuite/ld-mmix/bspec801.s
new file mode 100644
index 0000000..9c62909
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bspec801.s
@@ -0,0 +1,3 @@
+ BSPEC 80
+ TETRA 0x98000001
+ ESPEC
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bspec802.s b/binutils-2.19/ld/testsuite/ld-mmix/bspec802.s
new file mode 100644
index 0000000..13cbec4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bspec802.s
@@ -0,0 +1,7 @@
+ BSPEC 80
+ TETRA 4 % Decent section length name (in 32-bit words).  However...
+ ESPEC % Everything ends here.  The next thing is a LOP_LOC for .data, or
+       % an ending LOP-something, hence a non-LOP_QUOTE in the name.
+
+ .data
+ TETRA 0x112233
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bspec803.s b/binutils-2.19/ld/testsuite/ld-mmix/bspec803.s
new file mode 100644
index 0000000..64b5e3b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bspec803.s
@@ -0,0 +1,9 @@
+ BSPEC 80
+ TETRA 2 % Decent section length name (in 32-bit words).  However...
+ BYTE  "aaaa"
+ BYTE  0x98,"aaa" # A LOP_QUOTEd part here.  And also...
+ ESPEC % Everything ends here.  The next thing is a LOP_LOC for .data, or
+       % an ending LOP-something, hence a non-LOP_QUOTE in the section flags.
+
+ .data
+ TETRA 0x112233
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bspec804.s b/binutils-2.19/ld/testsuite/ld-mmix/bspec804.s
new file mode 100644
index 0000000..2c64c0a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bspec804.s
@@ -0,0 +1,9 @@
+ BSPEC 80
+ TETRA 2 % Decent section length name (in 32-bit words).
+ BYTE  "aaaaaaaa"
+ TETRA 0x11 % Flags.  However...
+ ESPEC % Everything ends here.  The next thing is a LOP_LOC for .data, or
+       % an ending LOP-something, hence a non-LOP_QUOTE in the section
+       % length, high part.
+ .data
+ TETRA 0x112233
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bspec805.s b/binutils-2.19/ld/testsuite/ld-mmix/bspec805.s
new file mode 100644
index 0000000..a5c09e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bspec805.s
@@ -0,0 +1,10 @@
+ BSPEC 80
+ TETRA 2 % Decent section length name (in 32-bit words).
+ BYTE  "aaaaaaaa"
+ TETRA 0x11 % Flags.
+ TETRA 0 % Decent high-part of section length.  However...
+ ESPEC % Everything ends here.  The next thing is a LOP_LOC for .data, or
+       % an ending LOP-something, hence a non-LOP_QUOTE in the section
+       % length, high part.
+ .data
+ TETRA 0x112233
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bspec806.s b/binutils-2.19/ld/testsuite/ld-mmix/bspec806.s
new file mode 100644
index 0000000..8f6c75f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bspec806.s
@@ -0,0 +1,10 @@
+ BSPEC 80
+ TETRA 2 % Decent section length name (in 32-bit words).
+ BYTE  "aaaaaaaa"
+ TETRA 0x11 % Flags.
+ OCTA 12 % Decent section length.  However...
+ ESPEC % Everything ends here.  The next thing is a LOP_LOC for .data, or
+       % an ending LOP-something, hence a non-LOP_QUOTE in the section
+       % length, high part.
+ .data
+ TETRA 0x112233
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bspec807.s b/binutils-2.19/ld/testsuite/ld-mmix/bspec807.s
new file mode 100644
index 0000000..3c16c12
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bspec807.s
@@ -0,0 +1,9 @@
+ BSPEC 80
+ TETRA 2 % Decent section length name (in 32-bit words).
+ BYTE  "aaaaaaaa"
+ TETRA 0x11 % Flags.
+ TETRA 0,12 % Decent section length.  However...
+ TETRA 0 % Things end stops after the high part of the VMA.
+ ESPEC
+ .data
+ TETRA 0x112233
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bspec808.s b/binutils-2.19/ld/testsuite/ld-mmix/bspec808.s
new file mode 100644
index 0000000..b8fc495
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bspec808.s
@@ -0,0 +1,9 @@
+ BSPEC 80
+ TETRA 2 % Decent section length name (in 32-bit words).
+ BYTE  "aaaaaaaa"
+ TETRA 0x11 % Flags.
+ TETRA 0xff00,0 % Indecent section length
+ TETRA 0xff,0 % Decent vma.
+ ESPEC
+ .data
+ TETRA 0x112233
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bza-1b.d b/binutils-2.19/ld/testsuite/ld-mmix/bza-1b.d
new file mode 100644
index 0000000..dcd0313
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bza-1b.d
@@ -0,0 +1,26 @@
+#source: start.s
+#source: a.s
+#source: bza.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0+:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <bza>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	5aea0006 	pbnz \$234,24 <bza\+0x1c>
+  10:	e3ff0004 	setl \$255,0x4
+  14:	e6ff0000 	incml \$255,0x0
+  18:	e5ff0000 	incmh \$255,0x0
+  1c:	e4ff0000 	inch \$255,0x0
+  20:	9fffff00 	go \$255,\$255,0
+  24:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bza-1f.d b/binutils-2.19/ld/testsuite/ld-mmix/bza-1f.d
new file mode 100644
index 0000000..bc4006f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bza-1f.d
@@ -0,0 +1,26 @@
+#source: start.s
+#source: bza.s
+#source: a.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0+:	e3fd0001 	setl \$253,0x1
+
+0+4 <bza>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	5aea0006 	pbnz \$234,20 <bza\+0x1c>
+   c:	e3ff0024 	setl \$255,0x24
+  10:	e6ff0000 	incml \$255,0x0
+  14:	e5ff0000 	incmh \$255,0x0
+  18:	e4ff0000 	inch \$255,0x0
+  1c:	9fffff00 	go \$255,\$255,0
+  20:	e3fd0003 	setl \$253,0x3
+
+0+24 <a>:
+  24:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bza-2b.d b/binutils-2.19/ld/testsuite/ld-mmix/bza-2b.d
new file mode 100644
index 0000000..a5d9b28
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bza-2b.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: a.s
+#source: bza.s
+#as: -no-expand
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0+:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <bza>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	43eafffe 	bz \$234,4 <a>
+  10:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bza-2f.d b/binutils-2.19/ld/testsuite/ld-mmix/bza-2f.d
new file mode 100644
index 0000000..21a6ca9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bza-2f.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: bza.s
+#source: a.s
+#as: -no-expand
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <bza>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	42ea0002 	bz \$234,10 <a>
+   c:	e3fd0003 	setl \$253,0x3
+
+0+10 <a>:
+  10:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bza-7b.d b/binutils-2.19/ld/testsuite/ld-mmix/bza-7b.d
new file mode 100644
index 0000000..ab98ad3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bza-7b.d
@@ -0,0 +1,26 @@
+#source: start.s
+#source: a.s
+#source: bza.s
+#as: -x
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+   0+:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <bza>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	5aea0006 	pbnz \$234,24 <bza\+0x1c>
+  10:	e3ff0004 	setl \$255,0x4
+  14:	e6ff0000 	incml \$255,0x0
+  18:	e5ff0000 	incmh \$255,0x0
+  1c:	e4ff0000 	inch \$255,0x0
+  20:	9fffff00 	go \$255,\$255,0
+  24:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bza-7f.d b/binutils-2.19/ld/testsuite/ld-mmix/bza-7f.d
new file mode 100644
index 0000000..be2ea56
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bza-7f.d
@@ -0,0 +1,26 @@
+#source: start.s
+#source: bza.s
+#source: a.s
+#as: -x
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+   0+:	e3fd0001 	setl \$253,0x1
+
+0+4 <bza>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	5aea0006 	pbnz \$234,20 <bza\+0x1c>
+   c:	e3ff0024 	setl \$255,0x24
+  10:	e6ff0000 	incml \$255,0x0
+  14:	e5ff0000 	incmh \$255,0x0
+  18:	e4ff0000 	inch \$255,0x0
+  1c:	9fffff00 	go \$255,\$255,0
+  20:	e3fd0003 	setl \$253,0x3
+
+0+24 <a>:
+  24:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bza-8b.d b/binutils-2.19/ld/testsuite/ld-mmix/bza-8b.d
new file mode 100644
index 0000000..b0eef74
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bza-8b.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: a.s
+#source: bza.s
+#as: -no-expand
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+   0+:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <bza>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	43eafffe 	bz \$234,4 <a>
+  10:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bza-8f.d b/binutils-2.19/ld/testsuite/ld-mmix/bza-8f.d
new file mode 100644
index 0000000..2d2a521
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bza-8f.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: bza.s
+#source: a.s
+#as: -no-expand
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+   0+:	e3fd0001 	setl \$253,0x1
+
+0+4 <bza>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	42ea0002 	bz \$234,10 <a>
+   c:	e3fd0003 	setl \$253,0x3
+
+0+10 <a>:
+  10:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/bza.s b/binutils-2.19/ld/testsuite/ld-mmix/bza.s
new file mode 100644
index 0000000..4cf848d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/bza.s
@@ -0,0 +1,7 @@
+* Just BEQs to an external symbol, with some padding.
+ .text
+ .global bza
+bza:
+ SET $253,2
+ BZ $234,a
+ SET $253,3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/data1.s b/binutils-2.19/ld/testsuite/ld-mmix/data1.s
new file mode 100644
index 0000000..0f4baf9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/data1.s
@@ -0,0 +1,2 @@
+ LOC #20 << 56
+xx OCTA Main+44
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/dloc1.s b/binutils-2.19/ld/testsuite/ld-mmix/dloc1.s
new file mode 100644
index 0000000..ba095c4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/dloc1.s
@@ -0,0 +1,3 @@
+ LOC #20 << 56 + #200
+dloc1 TETRA 4,5,6
+ .global dloc1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/dloc2.s b/binutils-2.19/ld/testsuite/ld-mmix/dloc2.s
new file mode 100644
index 0000000..704da08
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/dloc2.s
@@ -0,0 +1,3 @@
+ LOC #20 << 56 + #200
+dloc2 TETRA 7,8,9
+ .global dloc2
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/ext1-254.s b/binutils-2.19/ld/testsuite/ld-mmix/ext1-254.s
new file mode 100644
index 0000000..baaf22f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/ext1-254.s
@@ -0,0 +1,2 @@
+ .global ext1
+ext1 IS 254
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/ext1.s b/binutils-2.19/ld/testsuite/ld-mmix/ext1.s
new file mode 100644
index 0000000..d69420e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/ext1.s
@@ -0,0 +1,2 @@
+ .global ext1
+ext1 IS 252
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/ext1g.s b/binutils-2.19/ld/testsuite/ld-mmix/ext1g.s
new file mode 100644
index 0000000..1a167ab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/ext1g.s
@@ -0,0 +1,2 @@
+ .global ext1
+ext1 GREG
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/ext1l.s b/binutils-2.19/ld/testsuite/ld-mmix/ext1l.s
new file mode 100644
index 0000000..b7e6096
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/ext1l.s
@@ -0,0 +1,2 @@
+ .global ext1
+ext1 SWYM 4,8,16
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa-1b.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa-1b.d
new file mode 100644
index 0000000..84b477d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa-1b.d
@@ -0,0 +1,24 @@
+#source: start.s
+#source: a.s
+#source: getaa.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0+:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <getaa>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	e37b0004 	setl \$123,0x4
+  10:	e67b0000 	incml \$123,0x0
+  14:	e57b0000 	incmh \$123,0x0
+  18:	e47b0000 	inch \$123,0x0
+  1c:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa-1f.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa-1f.d
new file mode 100644
index 0000000..cc628a2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa-1f.d
@@ -0,0 +1,24 @@
+#source: start.s
+#source: getaa.s
+#source: a.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0+:	e3fd0001 	setl \$253,0x1
+
+0+4 <getaa>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	e37b001c 	setl \$123,0x1c
+   c:	e67b0000 	incml \$123,0x0
+  10:	e57b0000 	incmh \$123,0x0
+  14:	e47b0000 	inch \$123,0x0
+  18:	e3fd0003 	setl \$253,0x3
+
+0+1c <a>:
+  1c:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa-2b.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa-2b.d
new file mode 100644
index 0000000..4300128
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa-2b.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: a.s
+#source: getaa.s
+#as: -no-expand
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0+:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <getaa>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	f57bfffe 	geta \$123,4 <a>
+  10:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa-2f.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa-2f.d
new file mode 100644
index 0000000..fd32834
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa-2f.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: getaa.s
+#source: a.s
+#as: -no-expand
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0+:	e3fd0001 	setl \$253,0x1
+
+0+4 <getaa>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	f47b0002 	geta \$123,10 <a>
+   c:	e3fd0003 	setl \$253,0x3
+
+0+10 <a>:
+  10:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa-4b.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa-4b.d
new file mode 100644
index 0000000..1a3614b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa-4b.d
@@ -0,0 +1,26 @@
+#source: start.s
+#source: a.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: getaa.s
+#as: -no-expand
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+       4:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+
+0+40000 <getaa>:
+   40000:	e3fd0002 	setl \$253,0x2
+   40004:	f57b0000 	geta \$123,4 <a>
+   40008:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa-4f.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa-4f.d
new file mode 100644
index 0000000..30062a6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa-4f.d
@@ -0,0 +1,25 @@
+#source: start.s
+#source: getaa.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: a.s
+#as: -no-expand
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <getaa>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f47bffff 	geta \$123,40004 <a>
+       c:	e3fd0003 	setl \$253,0x3
+	\.\.\.
+
+0+40004 <a>:
+   40004:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa-6b.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa-6b.d
new file mode 100644
index 0000000..0d3c711
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa-6b.d
@@ -0,0 +1,11 @@
+#source: start.s
+#source: a.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: pad4.s
+#source: getaa.s
+#as: -no-expand
+#ld: -m elf64mmix
+#error: relocation truncated to fit: R_MMIX_ADDR19 against symbol `a'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa-6f.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa-6f.d
new file mode 100644
index 0000000..370f614
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa-6f.d
@@ -0,0 +1,10 @@
+#source: start.s
+#source: getaa.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: a.s
+#as: -no-expand
+#ld: -m elf64mmix
+#error: relocation truncated to fit: R_MMIX_ADDR19 against symbol `a'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa-7b.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa-7b.d
new file mode 100644
index 0000000..7a71c31
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa-7b.d
@@ -0,0 +1,24 @@
+#source: start.s
+#source: a.s
+#source: getaa.s
+#as: -x
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section .text:
+
+0+ <(Main|_start)>:
+   0+:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <getaa>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	e37b0004 	setl \$123,0x4
+  10:	e67b0000 	incml \$123,0x0
+  14:	e57b0000 	incmh \$123,0x0
+  18:	e47b0000 	inch \$123,0x0
+  1c:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa-7f.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa-7f.d
new file mode 100644
index 0000000..ea831a9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa-7f.d
@@ -0,0 +1,24 @@
+#source: start.s
+#source: getaa.s
+#source: a.s
+#as: -x
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+   0+:	e3fd0001 	setl \$253,0x1
+
+0+4 <getaa>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	e37b001c 	setl \$123,0x1c
+   c:	e67b0000 	incml \$123,0x0
+  10:	e57b0000 	incmh \$123,0x0
+  14:	e47b0000 	inch \$123,0x0
+  18:	e3fd0003 	setl \$253,0x3
+
+0+1c <a>:
+  1c:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa-8b.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa-8b.d
new file mode 100644
index 0000000..a54cc10
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa-8b.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: a.s
+#source: getaa.s
+#as: -no-expand
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+   0+:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <getaa>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	f57bfffe 	geta \$123,4 <a>
+  10:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa-8f.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa-8f.d
new file mode 100644
index 0000000..4ba7307
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa-8f.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: getaa.s
+#source: a.s
+#as: -no-expand
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+   0+:	e3fd0001 	setl \$253,0x1
+
+0+4 <getaa>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	f47b0002 	geta \$123,10 <a>
+   c:	e3fd0003 	setl \$253,0x3
+
+0+10 <a>:
+  10:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa.s b/binutils-2.19/ld/testsuite/ld-mmix/getaa.s
new file mode 100644
index 0000000..cc4dfb7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa.s
@@ -0,0 +1,7 @@
+* Just geta an external symbol, with some padding.
+ .text
+ .global getaa
+getaa:
+ SET $253,2
+ GETA $123,a
+ SET $253,3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa12b.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa12b.d
new file mode 100644
index 0000000..c4e49e4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa12b.d
@@ -0,0 +1,26 @@
+#source: start.s
+#source: a.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: getaa.s
+#as: -no-expand
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+       4:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+
+0+40000 <getaa>:
+   40000:	e3fd0002 	setl \$253,0x2
+   40004:	f57b0000 	geta \$123,4 <a>
+   40008:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa12f.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa12f.d
new file mode 100644
index 0000000..d80a39c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa12f.d
@@ -0,0 +1,25 @@
+#source: start.s
+#source: getaa.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: a.s
+#as: -no-expand
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <getaa>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f47bffff 	geta \$123,40004 <a>
+       c:	e3fd0003 	setl \$253,0x3
+	\.\.\.
+
+0+40004 <a>:
+   40004:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa14b.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa14b.d
new file mode 100644
index 0000000..47f37b9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa14b.d
@@ -0,0 +1,11 @@
+#source: start.s
+#source: a.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: pad4.s
+#source: getaa.s
+#as: -no-expand
+#ld: -m mmo
+#error: relocation truncated to fit: R_MMIX_ADDR19 against `a'$
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/getaa14f.d b/binutils-2.19/ld/testsuite/ld-mmix/getaa14f.d
new file mode 100644
index 0000000..58eb70b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/getaa14f.d
@@ -0,0 +1,10 @@
+#source: start.s
+#source: getaa.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: a.s
+#as: -no-expand
+#ld: -m mmo
+#error: relocation truncated to fit: R_MMIX_ADDR19 against `a'$
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-1.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-1.d
new file mode 100644
index 0000000..d64ce0a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-1.d
@@ -0,0 +1,27 @@
+#source: greg-1.s
+#source: gregldo1.s
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -dt
+
+# Most simple greg usage: relocate to each possible location within an
+# insn.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+7f0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+c g       \.text	0+ _start
+0+fe g       \*REG\*	0+ areg
+#...
+
+Disassembly of section \.text:
+
+0+ <_start-0xc>:
+   0:	8c0c20fe 	ldo \$12,\$32,\$254
+   4:	8d7bfe22 	ldo \$123,\$254,34
+   8:	8dfeea38 	ldo \$254,\$234,56
+
+0+c <_start>:
+   c:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-1.s b/binutils-2.19/ld/testsuite/ld-mmix/greg-1.s
new file mode 100644
index 0000000..821460c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-1.s
@@ -0,0 +1,3 @@
+# Have a single GREG register allocation.
+ .global areg
+areg GREG 123456789101112
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-10.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-10.d
new file mode 100644
index 0000000..acc702d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-10.d
@@ -0,0 +1,25 @@
+#source: greg-1.s
+#source: gregldo1.s
+#source: start.s
+#ld: -m mmo
+#objdump: -dt
+
+# Most simple greg usage: relocate to each possible location within an
+# insn; mmo.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+c g       \.text Main
+0+c g       \.text _start
+0+fe g       \*REG\* areg
+
+Disassembly of section \.text:
+
+0+ <Main-0xc>:
+   0:	8c0c20fe 	ldo \$12,\$32,areg
+   4:	8d7bfe22 	ldo \$123,areg,34
+   8:	8dfeea38 	ldo areg,\$234,56
+
+0+c <(Main|_start)>:
+   c:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-11.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-11.d
new file mode 100644
index 0000000..5fc474b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-11.d
@@ -0,0 +1,39 @@
+#source: greg-1.s
+#source: gregldo1.s
+#source: gregget2.s
+#source: a.s
+#source: greg-3.s
+#source: start.s
+#source: greg-2.s
+#as: -x
+#ld: -m mmo
+#objdump: -dt
+
+# Have two used gregs and one unused, mmo.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+20 g       \.text Main
+0+fe g       \*REG\* b
+0+20 g       \.text _start
+0+fc g       \*REG\* areg
+0+fd g       \*REG\* c
+0+1c g       \.text a
+
+Disassembly of section \.text:
+
+0+ <a-0x1c>:
+   0:	8c0c20fc 	ldo \$12,\$32,areg
+   4:	8d7bfc22 	ldo \$123,areg,34
+   8:	8dfcea38 	ldo areg,\$234,56
+   c:	e3fe001c 	setl b,0x1c
+  10:	e6fe0000 	incml b,0x0
+  14:	e5fe0000 	incmh b,0x0
+  18:	e4fe0000 	inch b,0x0
+
+0+1c <a>:
+  1c:	e3fd0004 	setl c,0x4
+
+0+20 <(Main|_start)>:
+  20:	e3fd0001 	setl c,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-11b.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-11b.d
new file mode 100644
index 0000000..50665d0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-11b.d
@@ -0,0 +1,32 @@
+#source: greg-1.s
+#source: gregldo1.s
+#source: gregget2.s
+#source: a.s
+#source: greg-3.s
+#source: start.s
+#source: greg-2.s
+#as: -x
+#ld: -m mmo
+#objdump: -str
+
+# Have two used gregs and one unused, mmo; display contents to visualize
+# mmo bug with register contents.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+20 g       \.text Main
+0+fe g       \*REG\* b
+0+20 g       \.text _start
+0+fc g       \*REG\* areg
+0+fd g       \*REG\* c
+0+1c g       \.text a
+
+
+Contents of section \.text:
+ 0+ 8c0c20fc 8d7bfc22 8dfcea38 e3fe001c  .*
+ 0+10 e6fe0000 e5fe0000 e4fe0000 e3fd0004  .*
+ 0+20 e3fd0001                             .*
+Contents of section \.MMIX\.reg_contents:
+ 07e0 00007048 860f3a38 00000000 00000042  .*
+ 07f0 007acf50 505a30a2                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-12.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-12.d
new file mode 100644
index 0000000..b438632
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-12.d
@@ -0,0 +1,34 @@
+#source: greg-1.s
+#source: gregget1.s
+#source: start.s
+#source: a.s
+#as: -x
+#ld: -m mmo
+#objdump: -dt
+
+# A greg usage with an expanding insn.  The register reloc must be
+# evaluated before the expanding reloc.  Here, it doesn't appear in the
+# wrong order, and it doesn't seem like they would naturally appear in the
+# wrong order, but anyway; mmo.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+10 g       \.text Main
+0+10 g       \.text _start
+0+fe g       \*REG\* areg
+0+14 g       \.text a
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)-0x10>:
+   0:	e3fe0014 	setl areg,0x14
+   4:	e6fe0000 	incml areg,0x0
+   8:	e5fe0000 	incmh areg,0x0
+   c:	e4fe0000 	inch areg,0x0
+
+0+10 <(Main|_start)>:
+  10:	e3fd0001 	setl \$253,0x1
+
+0+14 <a>:
+  14:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-13.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-13.d
new file mode 100644
index 0000000..091cf46
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-13.d
@@ -0,0 +1,33 @@
+#source: greg-1.s
+#source: gregbza1.s
+#source: start.s
+#source: a.s
+#as: -x
+#ld: -m mmo
+#objdump: -dt
+
+# Like greg-3, but a different expanding insn, mmo.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+18 g       \.text Main
+0+18 g       \.text _start
+0+fe g       \*REG\* areg
+0+1c g       \.text a
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)-0x18>:
+   0:	5afe0006 	pbnz areg,18 <(Main|_start)>
+   4:	e3ff001c 	setl \$255,0x1c
+   8:	e6ff0000 	incml \$255,0x0
+   c:	e5ff0000 	incmh \$255,0x0
+  10:	e4ff0000 	inch \$255,0x0
+  14:	9fffff00 	go \$255,\$255,0
+
+0+18 <(Main|_start)>:
+  18:	e3fd0001 	setl \$253,0x1
+
+0+1c <a>:
+  1c:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-14.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-14.d
new file mode 100644
index 0000000..19cc451
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-14.d
@@ -0,0 +1,32 @@
+#source: greg-1.s
+#source: gregpsj1.s
+#source: start.s
+#source: a.s
+#as: -x --no-pushj-stubs
+#ld: -m mmo
+#objdump: -dt
+
+# Like greg-3, but a different expanding insn.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+14 g       \.text Main
+0+14 g       \.text _start
+0+fe g       \*REG\* areg
+0+18 g       \.text a
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)-0x14>:
+   0:	e3ff0018 	setl \$255,0x18
+   4:	e6ff0000 	incml \$255,0x0
+   8:	e5ff0000 	incmh \$255,0x0
+   c:	e4ff0000 	inch \$255,0x0
+  10:	bffeff00 	pushgo areg,\$255,0
+
+0+14 <(Main|_start)>:
+  14:	e3fd0001 	setl \$253,0x1
+
+0+18 <a>:
+  18:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-14s.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-14s.d
new file mode 100644
index 0000000..466661c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-14s.d
@@ -0,0 +1,23 @@
+#source: greg-1.s
+#source: gregpsj1.s
+#source: start.s
+#source: a.s
+#as: -x
+#ld: -m mmo
+#objdump: -dt
+
+# Like greg-14, but using PUSHJ stubs.
+
+.*:     file format mmo
+SYMBOL TABLE:
+0+4 g       \.text Main
+0+4 g       \.text _start
+0+fe g       \*REG\* areg
+0+8 g       \.text a
+Disassembly of section \.text:
+0+ <(Main|_start)-0x4>:
+   0:	f2fe0002 	pushj areg,8 <a>
+0+4 <(Main|_start)>:
+   4:	e3fd0001 	setl \$253,0x1
+0+8 <a>:
+   8:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-15.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-15.d
new file mode 100644
index 0000000..4b54153
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-15.d
@@ -0,0 +1,59 @@
+#source: gregget1.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-1.s
+#source: a.s
+#source: start.s
+#as: -x
+#ld: -m mmo
+#objdump: -dt
+
+# Allocating the maximum number of gregs and referring to one at the end
+# still works, mmo.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+14 g       \.text Main
+0+14 g       \.text _start
+0+fe g       \*REG\* areg
+0+10 g       \.text a
+
+Disassembly of section \.text:
+
+0+ <a-0x10>:
+   0:	e3fe0010 	setl areg,0x10
+   4:	e6fe0000 	incml areg,0x0
+   8:	e5fe0000 	incmh areg,0x0
+   c:	e4fe0000 	inch areg,0x0
+
+0+10 <a>:
+  10:	e3fd0004 	setl \$253,0x4
+
+0+14 <(Main|_start)>:
+  14:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-16.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-16.d
new file mode 100644
index 0000000..80b2338
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-16.d
@@ -0,0 +1,59 @@
+#source: gregget1.s
+#source: greg-1.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: a.s
+#source: start.s
+#as: -x
+#ld: -m mmo
+#objdump: -dt
+
+# Allocating the maximum number of gregs and referring to one at the
+# *other* end still works, mmo.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+14 g       \.text Main
+0+14 g       \.text _start
+0+20 g       \*REG\* areg
+0+10 g       \.text a
+
+Disassembly of section \.text:
+
+0+ <a-0x10>:
+   0:	e3200010 	setl areg,0x10
+   4:	e6200000 	incml areg,0x0
+   8:	e5200000 	incmh areg,0x0
+   c:	e4200000 	inch areg,0x0
+
+0+10 <a>:
+  10:	e3fd0004 	setl \$253,0x4
+
+0+14 <(Main|_start)>:
+  14:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-17.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-17.d
new file mode 100644
index 0000000..e1af4b5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-17.d
@@ -0,0 +1,37 @@
+#source: gregget1.s
+#source: greg-1.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: a.s
+#source: start.s
+#as: -x
+#ld: -m mmo
+#error: Too many global registers: 224, max 223
+
+# Allocating the maximum number of gregs *plus one* is an error, mmo.
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-18.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-18.d
new file mode 100644
index 0000000..ed1bbaf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-18.d
@@ -0,0 +1,39 @@
+#source: gregget1.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-1.s
+#source: a.s
+#source: start.s
+#as: -x
+#ld: -m mmo
+#objdump: -dt
+#error: Too many global registers: 224, max 223
+
+# Allocating the maximum number of gregs *plus one* is an error; other end
+# of the stick, mmo.
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-19.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-19.d
new file mode 100644
index 0000000..4468161
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-19.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: aregm.s
+#source: gregldo1.s
+#ld: -m elf64mmix
+#objdump: -str
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+7f0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+ g     F \.text	0+ Main
+0+ g       \.text	0+ _start
+0+fe g       \*REG\*	0+ areg
+#...
+
+Contents of section \.text:
+ 0+ e3fd0001 8f03fe10 8e0307fe 8f05fe04  .*
+ 0+10 8c0c20fe 8d7bfe22 8dfeea38           .*
+Contents of section \.MMIX\.reg_contents:
+ 07f0 00000000 00000004                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-2.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-2.d
new file mode 100644
index 0000000..ab8fbb2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-2.d
@@ -0,0 +1,41 @@
+#source: greg-1.s
+#source: gregldo1.s
+#source: gregget2.s
+#source: a.s
+#source: greg-3.s
+#source: start.s
+#source: greg-2.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dt
+
+# Have two used gregs and one unused.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+7e0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+fe g       \*REG\*	0+ b
+0+20 g       \.text	0+ _start
+0+fc g       \*REG\*	0+ areg
+0+fd g       \*REG\*	0+ c
+#...
+0+1c g       \.text	0+ a
+
+Disassembly of section \.text:
+
+0+ <a-0x1c>:
+   0:	8c0c20fc 	ldo \$12,\$32,\$252
+   4:	8d7bfc22 	ldo \$123,\$252,34
+   8:	8dfcea38 	ldo \$252,\$234,56
+   c:	e3fe001c 	setl \$254,0x1c
+  10:	e6fe0000 	incml \$254,0x0
+  14:	e5fe0000 	incmh \$254,0x0
+  18:	e4fe0000 	inch \$254,0x0
+
+0+1c <a>:
+  1c:	e3fd0004 	setl \$253,0x4
+
+0+20 <_start>:
+  20:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-2.s b/binutils-2.19/ld/testsuite/ld-mmix/greg-2.s
new file mode 100644
index 0000000..588cbf1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-2.s
@@ -0,0 +1,3 @@
+# Have another GREG register allocation.
+ .global b
+b GREG 34567891011121314
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-20.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-20.d
new file mode 100644
index 0000000..10daa08
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-20.d
@@ -0,0 +1,18 @@
+#source: start.s
+#source: aregm.s
+#source: gregldo1.s
+#ld: -m mmo
+#objdump: -str
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g       \.text Main
+0+ g       \.text _start
+0+fe g       \*REG\* areg
+
+Contents of section \.text:
+ 0+ e3fd0001 8f03fe10 8e0307fe 8f05fe04  .*
+ 0+10 8c0c20fe 8d7bfe22 8dfeea38           .*
+Contents of section \.MMIX\.reg_contents:
+ 07f0 00000000 00000004                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-3.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-3.d
new file mode 100644
index 0000000..25189c2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-3.d
@@ -0,0 +1,36 @@
+#source: greg-1.s
+#source: gregget1.s
+#source: start.s
+#source: a.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dt
+
+# A greg usage with an expanding insn.  The register reloc must be
+# evaluated before the expanding reloc.  Here, it doesn't appear in the
+# wrong order, and it doesn't seem like they would naturally appear in the
+# wrong order, but anyway.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+7f0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+10 g       \.text	0+ _start
+0+fe g       \*REG\*	0+ areg
+#...
+0+14 g       \.text	0+ a
+
+Disassembly of section \.text:
+
+0+ <_start-0x10>:
+   0:	e3fe0014 	setl \$254,0x14
+   4:	e6fe0000 	incml \$254,0x0
+   8:	e5fe0000 	incmh \$254,0x0
+   c:	e4fe0000 	inch \$254,0x0
+
+0+10 <_start>:
+  10:	e3fd0001 	setl \$253,0x1
+
+0+14 <a>:
+  14:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-3.s b/binutils-2.19/ld/testsuite/ld-mmix/greg-3.s
new file mode 100644
index 0000000..5248591
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-3.s
@@ -0,0 +1,3 @@
+# Have yet another GREG register allocation.
+ .global c
+c GREG #42
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-4.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-4.d
new file mode 100644
index 0000000..8b882c1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-4.d
@@ -0,0 +1,35 @@
+#source: greg-1.s
+#source: gregbza1.s
+#source: start.s
+#source: a.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dt
+
+# Like greg-3, but a different expanding insn.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+7f0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+18 g       \.text	0+ _start
+0+fe g       \*REG\*	0+ areg
+#...
+0+1c g       \.text	0+ a
+
+Disassembly of section \.text:
+
+0+ <_start-0x18>:
+   0:	5afe0006 	pbnz \$254,18 <_start>
+   4:	e3ff001c 	setl \$255,0x1c
+   8:	e6ff0000 	incml \$255,0x0
+   c:	e5ff0000 	incmh \$255,0x0
+  10:	e4ff0000 	inch \$255,0x0
+  14:	9fffff00 	go \$255,\$255,0
+
+0+18 <_start>:
+  18:	e3fd0001 	setl \$253,0x1
+
+0+1c <a>:
+  1c:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-4.s b/binutils-2.19/ld/testsuite/ld-mmix/greg-4.s
new file mode 100644
index 0000000..5e5a30f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-4.s
@@ -0,0 +1,2 @@
+# A single local greg.
+lsym GREG 78
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-5.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-5.d
new file mode 100644
index 0000000..67e50d2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-5.d
@@ -0,0 +1,34 @@
+#source: greg-1.s
+#source: gregpsj1.s
+#source: start.s
+#source: a.s
+#as: -x --no-pushj-stubs
+#ld: -m elf64mmix
+#objdump: -dt
+
+# Like greg-3, but a different expanding insn.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+7f0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+14 g       \.text	0+ _start
+0+fe g       \*REG\*	0+ areg
+#...
+0+18 g       \.text	0+ a
+
+Disassembly of section \.text:
+
+0+ <_start-0x14>:
+   0:	e3ff0018 	setl \$255,0x18
+   4:	e6ff0000 	incml \$255,0x0
+   8:	e5ff0000 	incmh \$255,0x0
+   c:	e4ff0000 	inch \$255,0x0
+  10:	bffeff00 	pushgo \$254,\$255,0
+
+0+14 <_start>:
+  14:	e3fd0001 	setl \$253,0x1
+
+0+18 <a>:
+  18:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-5.s b/binutils-2.19/ld/testsuite/ld-mmix/greg-5.s
new file mode 100644
index 0000000..65400af
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-5.s
@@ -0,0 +1,20 @@
+# 16 local gregs.
+A GREG
+B GREG
+C GREG
+D GREG
+
+E GREG
+F GREG
+G GREG
+H GREG
+
+I GREG
+J GREG
+K GREG
+L GREG
+
+M GREG
+N GREG
+O GREG
+P GREG
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-5s.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-5s.d
new file mode 100644
index 0000000..84f5951
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-5s.d
@@ -0,0 +1,25 @@
+#source: greg-1.s
+#source: gregpsj1.s
+#source: start.s
+#source: a.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dt
+
+# Like greg-3, but a different expanding insn.
+
+.*:     file format elf64-mmix
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+7f0 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+4 g       \.text	0+ _start
+0+fe g       \*REG\*	0+ areg
+#...
+0+8 g       \.text	0+ a
+Disassembly of section \.text:
+0+ <_start-0x4>:
+   0:	f2fe0002 	pushj \$254,8 <a>
+0+4 <_start>:
+   4:	e3fd0001 	setl \$253,0x1
+0+8 <a>:
+   8:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-6.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-6.d
new file mode 100644
index 0000000..e4df905
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-6.d
@@ -0,0 +1,286 @@
+#source: gregget1.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-1.s
+#source: a.s
+#source: start.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dt
+
+# Allocating the maximum number of gregs and referring to one at the end
+# still works.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+0 l    d  \.text	0+ (|\.text)
+0+100 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+20 l       \*REG\*	0+ P
+0+21 l       \*REG\*	0+ O
+0+22 l       \*REG\*	0+ N
+0+23 l       \*REG\*	0+ M
+0+24 l       \*REG\*	0+ L
+0+25 l       \*REG\*	0+ K
+0+26 l       \*REG\*	0+ J
+0+27 l       \*REG\*	0+ I
+0+28 l       \*REG\*	0+ H
+0+29 l       \*REG\*	0+ G
+0+2a l       \*REG\*	0+ F
+0+2b l       \*REG\*	0+ E
+0+2c l       \*REG\*	0+ D
+0+2d l       \*REG\*	0+ C
+0+2e l       \*REG\*	0+ B
+0+2f l       \*REG\*	0+ A
+0+30 l       \*REG\*	0+ P
+0+31 l       \*REG\*	0+ O
+0+32 l       \*REG\*	0+ N
+0+33 l       \*REG\*	0+ M
+0+34 l       \*REG\*	0+ L
+0+35 l       \*REG\*	0+ K
+0+36 l       \*REG\*	0+ J
+0+37 l       \*REG\*	0+ I
+0+38 l       \*REG\*	0+ H
+0+39 l       \*REG\*	0+ G
+0+3a l       \*REG\*	0+ F
+0+3b l       \*REG\*	0+ E
+0+3c l       \*REG\*	0+ D
+0+3d l       \*REG\*	0+ C
+0+3e l       \*REG\*	0+ B
+0+3f l       \*REG\*	0+ A
+0+40 l       \*REG\*	0+ P
+0+41 l       \*REG\*	0+ O
+0+42 l       \*REG\*	0+ N
+0+43 l       \*REG\*	0+ M
+0+44 l       \*REG\*	0+ L
+0+45 l       \*REG\*	0+ K
+0+46 l       \*REG\*	0+ J
+0+47 l       \*REG\*	0+ I
+0+48 l       \*REG\*	0+ H
+0+49 l       \*REG\*	0+ G
+0+4a l       \*REG\*	0+ F
+0+4b l       \*REG\*	0+ E
+0+4c l       \*REG\*	0+ D
+0+4d l       \*REG\*	0+ C
+0+4e l       \*REG\*	0+ B
+0+4f l       \*REG\*	0+ A
+0+50 l       \*REG\*	0+ P
+0+51 l       \*REG\*	0+ O
+0+52 l       \*REG\*	0+ N
+0+53 l       \*REG\*	0+ M
+0+54 l       \*REG\*	0+ L
+0+55 l       \*REG\*	0+ K
+0+56 l       \*REG\*	0+ J
+0+57 l       \*REG\*	0+ I
+0+58 l       \*REG\*	0+ H
+0+59 l       \*REG\*	0+ G
+0+5a l       \*REG\*	0+ F
+0+5b l       \*REG\*	0+ E
+0+5c l       \*REG\*	0+ D
+0+5d l       \*REG\*	0+ C
+0+5e l       \*REG\*	0+ B
+0+5f l       \*REG\*	0+ A
+0+60 l       \*REG\*	0+ P
+0+61 l       \*REG\*	0+ O
+0+62 l       \*REG\*	0+ N
+0+63 l       \*REG\*	0+ M
+0+64 l       \*REG\*	0+ L
+0+65 l       \*REG\*	0+ K
+0+66 l       \*REG\*	0+ J
+0+67 l       \*REG\*	0+ I
+0+68 l       \*REG\*	0+ H
+0+69 l       \*REG\*	0+ G
+0+6a l       \*REG\*	0+ F
+0+6b l       \*REG\*	0+ E
+0+6c l       \*REG\*	0+ D
+0+6d l       \*REG\*	0+ C
+0+6e l       \*REG\*	0+ B
+0+6f l       \*REG\*	0+ A
+0+70 l       \*REG\*	0+ P
+0+71 l       \*REG\*	0+ O
+0+72 l       \*REG\*	0+ N
+0+73 l       \*REG\*	0+ M
+0+74 l       \*REG\*	0+ L
+0+75 l       \*REG\*	0+ K
+0+76 l       \*REG\*	0+ J
+0+77 l       \*REG\*	0+ I
+0+78 l       \*REG\*	0+ H
+0+79 l       \*REG\*	0+ G
+0+7a l       \*REG\*	0+ F
+0+7b l       \*REG\*	0+ E
+0+7c l       \*REG\*	0+ D
+0+7d l       \*REG\*	0+ C
+0+7e l       \*REG\*	0+ B
+0+7f l       \*REG\*	0+ A
+0+80 l       \*REG\*	0+ P
+0+81 l       \*REG\*	0+ O
+0+82 l       \*REG\*	0+ N
+0+83 l       \*REG\*	0+ M
+0+84 l       \*REG\*	0+ L
+0+85 l       \*REG\*	0+ K
+0+86 l       \*REG\*	0+ J
+0+87 l       \*REG\*	0+ I
+0+88 l       \*REG\*	0+ H
+0+89 l       \*REG\*	0+ G
+0+8a l       \*REG\*	0+ F
+0+8b l       \*REG\*	0+ E
+0+8c l       \*REG\*	0+ D
+0+8d l       \*REG\*	0+ C
+0+8e l       \*REG\*	0+ B
+0+8f l       \*REG\*	0+ A
+0+90 l       \*REG\*	0+ P
+0+91 l       \*REG\*	0+ O
+0+92 l       \*REG\*	0+ N
+0+93 l       \*REG\*	0+ M
+0+94 l       \*REG\*	0+ L
+0+95 l       \*REG\*	0+ K
+0+96 l       \*REG\*	0+ J
+0+97 l       \*REG\*	0+ I
+0+98 l       \*REG\*	0+ H
+0+99 l       \*REG\*	0+ G
+0+9a l       \*REG\*	0+ F
+0+9b l       \*REG\*	0+ E
+0+9c l       \*REG\*	0+ D
+0+9d l       \*REG\*	0+ C
+0+9e l       \*REG\*	0+ B
+0+9f l       \*REG\*	0+ A
+0+a0 l       \*REG\*	0+ P
+0+a1 l       \*REG\*	0+ O
+0+a2 l       \*REG\*	0+ N
+0+a3 l       \*REG\*	0+ M
+0+a4 l       \*REG\*	0+ L
+0+a5 l       \*REG\*	0+ K
+0+a6 l       \*REG\*	0+ J
+0+a7 l       \*REG\*	0+ I
+0+a8 l       \*REG\*	0+ H
+0+a9 l       \*REG\*	0+ G
+0+aa l       \*REG\*	0+ F
+0+ab l       \*REG\*	0+ E
+0+ac l       \*REG\*	0+ D
+0+ad l       \*REG\*	0+ C
+0+ae l       \*REG\*	0+ B
+0+af l       \*REG\*	0+ A
+0+b0 l       \*REG\*	0+ P
+0+b1 l       \*REG\*	0+ O
+0+b2 l       \*REG\*	0+ N
+0+b3 l       \*REG\*	0+ M
+0+b4 l       \*REG\*	0+ L
+0+b5 l       \*REG\*	0+ K
+0+b6 l       \*REG\*	0+ J
+0+b7 l       \*REG\*	0+ I
+0+b8 l       \*REG\*	0+ H
+0+b9 l       \*REG\*	0+ G
+0+ba l       \*REG\*	0+ F
+0+bb l       \*REG\*	0+ E
+0+bc l       \*REG\*	0+ D
+0+bd l       \*REG\*	0+ C
+0+be l       \*REG\*	0+ B
+0+bf l       \*REG\*	0+ A
+0+c0 l       \*REG\*	0+ P
+0+c1 l       \*REG\*	0+ O
+0+c2 l       \*REG\*	0+ N
+0+c3 l       \*REG\*	0+ M
+0+c4 l       \*REG\*	0+ L
+0+c5 l       \*REG\*	0+ K
+0+c6 l       \*REG\*	0+ J
+0+c7 l       \*REG\*	0+ I
+0+c8 l       \*REG\*	0+ H
+0+c9 l       \*REG\*	0+ G
+0+ca l       \*REG\*	0+ F
+0+cb l       \*REG\*	0+ E
+0+cc l       \*REG\*	0+ D
+0+cd l       \*REG\*	0+ C
+0+ce l       \*REG\*	0+ B
+0+cf l       \*REG\*	0+ A
+0+d0 l       \*REG\*	0+ P
+0+d1 l       \*REG\*	0+ O
+0+d2 l       \*REG\*	0+ N
+0+d3 l       \*REG\*	0+ M
+0+d4 l       \*REG\*	0+ L
+0+d5 l       \*REG\*	0+ K
+0+d6 l       \*REG\*	0+ J
+0+d7 l       \*REG\*	0+ I
+0+d8 l       \*REG\*	0+ H
+0+d9 l       \*REG\*	0+ G
+0+da l       \*REG\*	0+ F
+0+db l       \*REG\*	0+ E
+0+dc l       \*REG\*	0+ D
+0+dd l       \*REG\*	0+ C
+0+de l       \*REG\*	0+ B
+0+df l       \*REG\*	0+ A
+0+e0 l       \*REG\*	0+ P
+0+e1 l       \*REG\*	0+ O
+0+e2 l       \*REG\*	0+ N
+0+e3 l       \*REG\*	0+ M
+0+e4 l       \*REG\*	0+ L
+0+e5 l       \*REG\*	0+ K
+0+e6 l       \*REG\*	0+ J
+0+e7 l       \*REG\*	0+ I
+0+e8 l       \*REG\*	0+ H
+0+e9 l       \*REG\*	0+ G
+0+ea l       \*REG\*	0+ F
+0+eb l       \*REG\*	0+ E
+0+ec l       \*REG\*	0+ D
+0+ed l       \*REG\*	0+ C
+0+ee l       \*REG\*	0+ B
+0+ef l       \*REG\*	0+ A
+0+f0 l       \*REG\*	0+ lsym
+0+f1 l       \*REG\*	0+ lsym
+0+f2 l       \*REG\*	0+ lsym
+0+f3 l       \*REG\*	0+ lsym
+0+f4 l       \*REG\*	0+ lsym
+0+f5 l       \*REG\*	0+ lsym
+0+f6 l       \*REG\*	0+ lsym
+0+f7 l       \*REG\*	0+ lsym
+0+f8 l       \*REG\*	0+ lsym
+0+f9 l       \*REG\*	0+ lsym
+0+fa l       \*REG\*	0+ lsym
+0+fb l       \*REG\*	0+ lsym
+0+fc l       \*REG\*	0+ lsym
+0+fd l       \*REG\*	0+ lsym
+0+14 g       \.text	0+ _start
+0+fe g       \*REG\*	0+ areg
+2000000000000000 g       \*ABS\*	0+ __bss_start
+2000000000000000 g       \*ABS\*	0+ _edata
+2000000000000000 g       \*ABS\*	0+ _end
+0+14 g       \.text	0+ _start\.
+0+10 g       \.text	0+ a
+
+Disassembly of section \.text:
+
+0+ <a-0x10>:
+   0:	e3fe0010 	setl \$254,0x10
+   4:	e6fe0000 	incml \$254,0x0
+   8:	e5fe0000 	incmh \$254,0x0
+   c:	e4fe0000 	inch \$254,0x0
+
+0+10 <a>:
+  10:	e3fd0004 	setl \$253,0x4
+
+0+14 <_start>:
+  14:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-7.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-7.d
new file mode 100644
index 0000000..a5d1692
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-7.d
@@ -0,0 +1,286 @@
+#source: gregget1.s
+#source: greg-1.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: a.s
+#source: start.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dt
+
+# Allocating the maximum number of gregs and referring to one at the
+# *other* end still works.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+100 l    d  \.MMIX\.reg_contents	0+ (|\.MMIX\.reg_contents)
+0+21 l       \*REG\*	0+ P
+0+22 l       \*REG\*	0+ O
+0+23 l       \*REG\*	0+ N
+0+24 l       \*REG\*	0+ M
+0+25 l       \*REG\*	0+ L
+0+26 l       \*REG\*	0+ K
+0+27 l       \*REG\*	0+ J
+0+28 l       \*REG\*	0+ I
+0+29 l       \*REG\*	0+ H
+0+2a l       \*REG\*	0+ G
+0+2b l       \*REG\*	0+ F
+0+2c l       \*REG\*	0+ E
+0+2d l       \*REG\*	0+ D
+0+2e l       \*REG\*	0+ C
+0+2f l       \*REG\*	0+ B
+0+30 l       \*REG\*	0+ A
+0+31 l       \*REG\*	0+ P
+0+32 l       \*REG\*	0+ O
+0+33 l       \*REG\*	0+ N
+0+34 l       \*REG\*	0+ M
+0+35 l       \*REG\*	0+ L
+0+36 l       \*REG\*	0+ K
+0+37 l       \*REG\*	0+ J
+0+38 l       \*REG\*	0+ I
+0+39 l       \*REG\*	0+ H
+0+3a l       \*REG\*	0+ G
+0+3b l       \*REG\*	0+ F
+0+3c l       \*REG\*	0+ E
+0+3d l       \*REG\*	0+ D
+0+3e l       \*REG\*	0+ C
+0+3f l       \*REG\*	0+ B
+0+40 l       \*REG\*	0+ A
+0+41 l       \*REG\*	0+ P
+0+42 l       \*REG\*	0+ O
+0+43 l       \*REG\*	0+ N
+0+44 l       \*REG\*	0+ M
+0+45 l       \*REG\*	0+ L
+0+46 l       \*REG\*	0+ K
+0+47 l       \*REG\*	0+ J
+0+48 l       \*REG\*	0+ I
+0+49 l       \*REG\*	0+ H
+0+4a l       \*REG\*	0+ G
+0+4b l       \*REG\*	0+ F
+0+4c l       \*REG\*	0+ E
+0+4d l       \*REG\*	0+ D
+0+4e l       \*REG\*	0+ C
+0+4f l       \*REG\*	0+ B
+0+50 l       \*REG\*	0+ A
+0+51 l       \*REG\*	0+ P
+0+52 l       \*REG\*	0+ O
+0+53 l       \*REG\*	0+ N
+0+54 l       \*REG\*	0+ M
+0+55 l       \*REG\*	0+ L
+0+56 l       \*REG\*	0+ K
+0+57 l       \*REG\*	0+ J
+0+58 l       \*REG\*	0+ I
+0+59 l       \*REG\*	0+ H
+0+5a l       \*REG\*	0+ G
+0+5b l       \*REG\*	0+ F
+0+5c l       \*REG\*	0+ E
+0+5d l       \*REG\*	0+ D
+0+5e l       \*REG\*	0+ C
+0+5f l       \*REG\*	0+ B
+0+60 l       \*REG\*	0+ A
+0+61 l       \*REG\*	0+ P
+0+62 l       \*REG\*	0+ O
+0+63 l       \*REG\*	0+ N
+0+64 l       \*REG\*	0+ M
+0+65 l       \*REG\*	0+ L
+0+66 l       \*REG\*	0+ K
+0+67 l       \*REG\*	0+ J
+0+68 l       \*REG\*	0+ I
+0+69 l       \*REG\*	0+ H
+0+6a l       \*REG\*	0+ G
+0+6b l       \*REG\*	0+ F
+0+6c l       \*REG\*	0+ E
+0+6d l       \*REG\*	0+ D
+0+6e l       \*REG\*	0+ C
+0+6f l       \*REG\*	0+ B
+0+70 l       \*REG\*	0+ A
+0+71 l       \*REG\*	0+ P
+0+72 l       \*REG\*	0+ O
+0+73 l       \*REG\*	0+ N
+0+74 l       \*REG\*	0+ M
+0+75 l       \*REG\*	0+ L
+0+76 l       \*REG\*	0+ K
+0+77 l       \*REG\*	0+ J
+0+78 l       \*REG\*	0+ I
+0+79 l       \*REG\*	0+ H
+0+7a l       \*REG\*	0+ G
+0+7b l       \*REG\*	0+ F
+0+7c l       \*REG\*	0+ E
+0+7d l       \*REG\*	0+ D
+0+7e l       \*REG\*	0+ C
+0+7f l       \*REG\*	0+ B
+0+80 l       \*REG\*	0+ A
+0+81 l       \*REG\*	0+ P
+0+82 l       \*REG\*	0+ O
+0+83 l       \*REG\*	0+ N
+0+84 l       \*REG\*	0+ M
+0+85 l       \*REG\*	0+ L
+0+86 l       \*REG\*	0+ K
+0+87 l       \*REG\*	0+ J
+0+88 l       \*REG\*	0+ I
+0+89 l       \*REG\*	0+ H
+0+8a l       \*REG\*	0+ G
+0+8b l       \*REG\*	0+ F
+0+8c l       \*REG\*	0+ E
+0+8d l       \*REG\*	0+ D
+0+8e l       \*REG\*	0+ C
+0+8f l       \*REG\*	0+ B
+0+90 l       \*REG\*	0+ A
+0+91 l       \*REG\*	0+ P
+0+92 l       \*REG\*	0+ O
+0+93 l       \*REG\*	0+ N
+0+94 l       \*REG\*	0+ M
+0+95 l       \*REG\*	0+ L
+0+96 l       \*REG\*	0+ K
+0+97 l       \*REG\*	0+ J
+0+98 l       \*REG\*	0+ I
+0+99 l       \*REG\*	0+ H
+0+9a l       \*REG\*	0+ G
+0+9b l       \*REG\*	0+ F
+0+9c l       \*REG\*	0+ E
+0+9d l       \*REG\*	0+ D
+0+9e l       \*REG\*	0+ C
+0+9f l       \*REG\*	0+ B
+0+a0 l       \*REG\*	0+ A
+0+a1 l       \*REG\*	0+ P
+0+a2 l       \*REG\*	0+ O
+0+a3 l       \*REG\*	0+ N
+0+a4 l       \*REG\*	0+ M
+0+a5 l       \*REG\*	0+ L
+0+a6 l       \*REG\*	0+ K
+0+a7 l       \*REG\*	0+ J
+0+a8 l       \*REG\*	0+ I
+0+a9 l       \*REG\*	0+ H
+0+aa l       \*REG\*	0+ G
+0+ab l       \*REG\*	0+ F
+0+ac l       \*REG\*	0+ E
+0+ad l       \*REG\*	0+ D
+0+ae l       \*REG\*	0+ C
+0+af l       \*REG\*	0+ B
+0+b0 l       \*REG\*	0+ A
+0+b1 l       \*REG\*	0+ P
+0+b2 l       \*REG\*	0+ O
+0+b3 l       \*REG\*	0+ N
+0+b4 l       \*REG\*	0+ M
+0+b5 l       \*REG\*	0+ L
+0+b6 l       \*REG\*	0+ K
+0+b7 l       \*REG\*	0+ J
+0+b8 l       \*REG\*	0+ I
+0+b9 l       \*REG\*	0+ H
+0+ba l       \*REG\*	0+ G
+0+bb l       \*REG\*	0+ F
+0+bc l       \*REG\*	0+ E
+0+bd l       \*REG\*	0+ D
+0+be l       \*REG\*	0+ C
+0+bf l       \*REG\*	0+ B
+0+c0 l       \*REG\*	0+ A
+0+c1 l       \*REG\*	0+ P
+0+c2 l       \*REG\*	0+ O
+0+c3 l       \*REG\*	0+ N
+0+c4 l       \*REG\*	0+ M
+0+c5 l       \*REG\*	0+ L
+0+c6 l       \*REG\*	0+ K
+0+c7 l       \*REG\*	0+ J
+0+c8 l       \*REG\*	0+ I
+0+c9 l       \*REG\*	0+ H
+0+ca l       \*REG\*	0+ G
+0+cb l       \*REG\*	0+ F
+0+cc l       \*REG\*	0+ E
+0+cd l       \*REG\*	0+ D
+0+ce l       \*REG\*	0+ C
+0+cf l       \*REG\*	0+ B
+0+d0 l       \*REG\*	0+ A
+0+d1 l       \*REG\*	0+ P
+0+d2 l       \*REG\*	0+ O
+0+d3 l       \*REG\*	0+ N
+0+d4 l       \*REG\*	0+ M
+0+d5 l       \*REG\*	0+ L
+0+d6 l       \*REG\*	0+ K
+0+d7 l       \*REG\*	0+ J
+0+d8 l       \*REG\*	0+ I
+0+d9 l       \*REG\*	0+ H
+0+da l       \*REG\*	0+ G
+0+db l       \*REG\*	0+ F
+0+dc l       \*REG\*	0+ E
+0+dd l       \*REG\*	0+ D
+0+de l       \*REG\*	0+ C
+0+df l       \*REG\*	0+ B
+0+e0 l       \*REG\*	0+ A
+0+e1 l       \*REG\*	0+ P
+0+e2 l       \*REG\*	0+ O
+0+e3 l       \*REG\*	0+ N
+0+e4 l       \*REG\*	0+ M
+0+e5 l       \*REG\*	0+ L
+0+e6 l       \*REG\*	0+ K
+0+e7 l       \*REG\*	0+ J
+0+e8 l       \*REG\*	0+ I
+0+e9 l       \*REG\*	0+ H
+0+ea l       \*REG\*	0+ G
+0+eb l       \*REG\*	0+ F
+0+ec l       \*REG\*	0+ E
+0+ed l       \*REG\*	0+ D
+0+ee l       \*REG\*	0+ C
+0+ef l       \*REG\*	0+ B
+0+f0 l       \*REG\*	0+ A
+0+f1 l       \*REG\*	0+ lsym
+0+f2 l       \*REG\*	0+ lsym
+0+f3 l       \*REG\*	0+ lsym
+0+f4 l       \*REG\*	0+ lsym
+0+f5 l       \*REG\*	0+ lsym
+0+f6 l       \*REG\*	0+ lsym
+0+f7 l       \*REG\*	0+ lsym
+0+f8 l       \*REG\*	0+ lsym
+0+f9 l       \*REG\*	0+ lsym
+0+fa l       \*REG\*	0+ lsym
+0+fb l       \*REG\*	0+ lsym
+0+fc l       \*REG\*	0+ lsym
+0+fd l       \*REG\*	0+ lsym
+0+fe l       \*REG\*	0+ lsym
+0+14 g       \.text	0+ _start
+0+20 g       \*REG\*	0+ areg
+2000000000000000 g       \*ABS\*	0+ __bss_start
+2000000000000000 g       \*ABS\*	0+ _edata
+2000000000000000 g       \*ABS\*	0+ _end
+0+14 g       \.text	0+ _start\.
+0+10 g       \.text	0+ a
+
+Disassembly of section \.text:
+
+0+ <a-0x10>:
+   0:	e3200010 	setl \$32,0x10
+   4:	e6200000 	incml \$32,0x0
+   8:	e5200000 	incmh \$32,0x0
+   c:	e4200000 	inch \$32,0x0
+
+0+10 <a>:
+  10:	e3fd0004 	setl \$253,0x4
+
+0+14 <_start>:
+  14:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-8.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-8.d
new file mode 100644
index 0000000..cb6b776
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-8.d
@@ -0,0 +1,37 @@
+#source: gregget1.s
+#source: greg-1.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: a.s
+#source: start.s
+#as: -x
+#ld: -m elf64mmix
+#error: Too many global registers: 224, max 223
+
+# Allocating the maximum number of gregs *plus one* is an error.
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/greg-9.d b/binutils-2.19/ld/testsuite/ld-mmix/greg-9.d
new file mode 100644
index 0000000..c9d9fcd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/greg-9.d
@@ -0,0 +1,39 @@
+#source: gregget1.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-1.s
+#source: a.s
+#source: start.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dt
+#error: Too many global registers: 224, max 223
+
+# Allocating the maximum number of gregs *plus one* is an error; other end
+# of the stick.
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/gregbza1.s b/binutils-2.19/ld/testsuite/ld-mmix/gregbza1.s
new file mode 100644
index 0000000..878c66f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/gregbza1.s
@@ -0,0 +1,4 @@
+# Use a symbolic register areg, presumably allocated by greg in another file.
+# The "BZ" will be expanded, and the reloc for areg must be resolved
+# before the other relocs for that insn.
+ BZ areg,a
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/gregget1.s b/binutils-2.19/ld/testsuite/ld-mmix/gregget1.s
new file mode 100644
index 0000000..49f97f0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/gregget1.s
@@ -0,0 +1,4 @@
+# Use a symbolic register areg, presumably allocated by greg in another file.
+# The "GETA" will be expanded, and the reloc for areg must be resolved
+# before the other relocs for that insn.
+ GETA areg,a
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/gregget2.s b/binutils-2.19/ld/testsuite/ld-mmix/gregget2.s
new file mode 100644
index 0000000..855136c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/gregget2.s
@@ -0,0 +1,4 @@
+# Use a symbolic register b, presumably allocated by greg in another file.
+# The "GETA" will be expanded, and the reloc for b must be resolved before
+# the other relocs for that insn.
+ GETA b,a
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/gregldo1.s b/binutils-2.19/ld/testsuite/ld-mmix/gregldo1.s
new file mode 100644
index 0000000..a69bd8c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/gregldo1.s
@@ -0,0 +1,4 @@
+# Use a symbolic register areg, presumably allocated by greg in another file.
+ LDO $12,$32,areg
+ LDO $123,areg,34
+ LDO areg,$234,56
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/gregpsj1.s b/binutils-2.19/ld/testsuite/ld-mmix/gregpsj1.s
new file mode 100644
index 0000000..87b68a3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/gregpsj1.s
@@ -0,0 +1,4 @@
+# Use a symbolic register areg, presumably allocated by greg in another file.
+# The "PUSHJ" will be expanded, and the reloc for areg must be resolved
+# before the other relocs for that insn.
+ PUSHJ areg,a
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/hdr-1.d b/binutils-2.19/ld/testsuite/ld-mmix/hdr-1.d
new file mode 100644
index 0000000..3cb8265
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/hdr-1.d
@@ -0,0 +1,19 @@
+#source: start.s
+#source: a.s
+#ld: -T $srcdir/$subdir/mmohdr1.ld
+#objdump: -sht
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+8  0+100  0+100  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+SYMBOL TABLE:
+0+100 g       \.text Main
+0+100 g       \.text _start
+0+104 g       \.text a
+
+
+Contents of section \.text:
+ 0100 e3fd0001 e3fd0004                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-1b.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-1b.d
new file mode 100644
index 0000000..3baff9b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-1b.d
@@ -0,0 +1,25 @@
+#source: start.s
+#source: a.s
+#source: jumpa.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <jumpa>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	f1fffffe 	jmp 4 <a>
+  10:	fd000000 	swym 0,0,0
+  14:	fd000000 	swym 0,0,0
+  18:	fd000000 	swym 0,0,0
+  1c:	fd000000 	swym 0,0,0
+  20:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-1f.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-1f.d
new file mode 100644
index 0000000..983d294
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-1f.d
@@ -0,0 +1,25 @@
+#source: start.s
+#source: jumpa.s
+#source: a.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <jumpa>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	f0000006 	jmp 20 <a>
+   c:	fd000000 	swym 0,0,0
+  10:	fd000000 	swym 0,0,0
+  14:	fd000000 	swym 0,0,0
+  18:	fd000000 	swym 0,0,0
+  1c:	e3fd0003 	setl \$253,0x3
+
+0+20 <a>:
+  20:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-2b.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-2b.d
new file mode 100644
index 0000000..f594055
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-2b.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: a.s
+#source: jumpa.s
+#as: -no-expand
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <jumpa>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	f1fffffe 	jmp 4 <a>
+  10:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-2f.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-2f.d
new file mode 100644
index 0000000..a923e21
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-2f.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: jumpa.s
+#source: a.s
+#as: -no-expand
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <jumpa>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	f0000002 	jmp 10 <a>
+   c:	e3fd0003 	setl \$253,0x3
+
+0+10 <a>:
+  10:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-3b.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-3b.d
new file mode 100644
index 0000000..d2f1b50
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-3b.d
@@ -0,0 +1,30 @@
+#source: start.s
+#source: a.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: jumpa.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+       4:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+
+0+4000000 <jumpa>:
+ 4000000:	e3fd0002 	setl \$253,0x2
+ 4000004:	f1000000 	jmp 4 <a>
+ 4000008:	fd000000 	swym 0,0,0
+ 400000c:	fd000000 	swym 0,0,0
+ 4000010:	fd000000 	swym 0,0,0
+ 4000014:	fd000000 	swym 0,0,0
+ 4000018:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-3f.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-3f.d
new file mode 100644
index 0000000..4a5e10d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-3f.d
@@ -0,0 +1,28 @@
+#source: start.s
+#source: jumpa.s
+#source: pad2p26m32.s
+#source: pad4.s
+#source: a.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <jumpa>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f0ffffff 	jmp 4000004 <a>
+       c:	fd000000 	swym 0,0,0
+      10:	fd000000 	swym 0,0,0
+      14:	fd000000 	swym 0,0,0
+      18:	fd000000 	swym 0,0,0
+      1c:	e3fd0003 	setl \$253,0x3
+	\.\.\.
+
+0+4000004 <a>:
+ 4000004:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-4b.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-4b.d
new file mode 100644
index 0000000..9d35932
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-4b.d
@@ -0,0 +1,26 @@
+#source: start.s
+#source: a.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: jumpa.s
+#as: -no-expand
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+       4:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+
+0+4000000 <jumpa>:
+ 4000000:	e3fd0002 	setl \$253,0x2
+ 4000004:	f1000000 	jmp 4 <a>
+ 4000008:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-4f.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-4f.d
new file mode 100644
index 0000000..3c0885b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-4f.d
@@ -0,0 +1,25 @@
+#source: start.s
+#source: jumpa.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: a.s
+#as: -no-expand
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <jumpa>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f0ffffff 	jmp 4000004 <a>
+       c:	e3fd0003 	setl \$253,0x3
+	\.\.\.
+
+0+4000004 <a>:
+ 4000004:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-5b.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-5b.d
new file mode 100644
index 0000000..b2fcaf4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-5b.d
@@ -0,0 +1,31 @@
+#source: start.s
+#source: a.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: pad4.s
+#source: jumpa.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+       4:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+
+0+4000004 <jumpa>:
+ 4000004:	e3fd0002 	setl \$253,0x2
+ 4000008:	e3ff0004 	setl \$255,0x4
+ 400000c:	e6ff0000 	incml \$255,0x0
+ 4000010:	e5ff0000 	incmh \$255,0x0
+ 4000014:	e4ff0000 	inch \$255,0x0
+ 4000018:	9fffff00 	go \$255,\$255,0
+ 400001c:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-5f.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-5f.d
new file mode 100644
index 0000000..bb91e70
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-5f.d
@@ -0,0 +1,29 @@
+#source: start.s
+#source: jumpa.s
+#source: pad2p26m32.s
+#source: pad4.s
+#source: pad4.s
+#source: a.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <jumpa>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	e3ff0008 	setl \$255,0x8
+       c:	e6ff0400 	incml \$255,0x400
+      10:	e5ff0000 	incmh \$255,0x0
+      14:	e4ff0000 	inch \$255,0x0
+      18:	9fffff00 	go \$255,\$255,0
+      1c:	e3fd0003 	setl \$253,0x3
+	\.\.\.
+
+0+4000008 <a>:
+ 4000008:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-6b.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-6b.d
new file mode 100644
index 0000000..e4ba8cd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-6b.d
@@ -0,0 +1,11 @@
+#source: start.s
+#source: a.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: pad4.s
+#source: jumpa.s
+#as: -no-expand
+#ld: -m elf64mmix
+#error: relocation truncated to fit: R_MMIX_ADDR27 against symbol `a'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-6f.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-6f.d
new file mode 100644
index 0000000..65c4ab0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-6f.d
@@ -0,0 +1,10 @@
+#source: start.s
+#source: jumpa.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: a.s
+#as: -no-expand
+#ld: -m elf64mmix
+#error: relocation truncated to fit: R_MMIX_ADDR27 against symbol `a'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-7b.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-7b.d
new file mode 100644
index 0000000..202d006
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-7b.d
@@ -0,0 +1,25 @@
+#source: start.s
+#source: a.s
+#source: jumpa.s
+#as: -x
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <jumpa>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	f1fffffe 	jmp 4 <a>
+  10:	fd000000 	swym 0,0,0
+  14:	fd000000 	swym 0,0,0
+  18:	fd000000 	swym 0,0,0
+  1c:	fd000000 	swym 0,0,0
+  20:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-7f.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-7f.d
new file mode 100644
index 0000000..b8345e1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-7f.d
@@ -0,0 +1,25 @@
+#source: start.s
+#source: jumpa.s
+#source: a.s
+#as: -x
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <jumpa>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	f0000006 	jmp 20 <a>
+   c:	fd000000 	swym 0,0,0
+  10:	fd000000 	swym 0,0,0
+  14:	fd000000 	swym 0,0,0
+  18:	fd000000 	swym 0,0,0
+  1c:	e3fd0003 	setl \$253,0x3
+
+0+20 <a>:
+  20:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-8b.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-8b.d
new file mode 100644
index 0000000..456c949
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-8b.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: a.s
+#source: jumpa.s
+#as: -no-expand
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <jumpa>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	f1fffffe 	jmp 4 <a>
+  10:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-8f.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-8f.d
new file mode 100644
index 0000000..05777ce
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-8f.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: jumpa.s
+#source: a.s
+#as: -no-expand
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <jumpa>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	f0000002 	jmp 10 <a>
+   c:	e3fd0003 	setl \$253,0x3
+
+0+10 <a>:
+  10:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-9b.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-9b.d
new file mode 100644
index 0000000..2a639d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-9b.d
@@ -0,0 +1,30 @@
+#source: start.s
+#source: a.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: jumpa.s
+#as: -x
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+       4:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+
+0+4000000 <jumpa>:
+ 4000000:	e3fd0002 	setl \$253,0x2
+ 4000004:	f1000000 	jmp 4 <a>
+ 4000008:	fd000000 	swym 0,0,0
+ 400000c:	fd000000 	swym 0,0,0
+ 4000010:	fd000000 	swym 0,0,0
+ 4000014:	fd000000 	swym 0,0,0
+ 4000018:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa-9f.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-9f.d
new file mode 100644
index 0000000..a4a2932
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa-9f.d
@@ -0,0 +1,28 @@
+#source: start.s
+#source: jumpa.s
+#source: pad2p26m32.s
+#source: pad4.s
+#source: a.s
+#as: -x
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <jumpa>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f0ffffff 	jmp 4000004 <a>
+       c:	fd000000 	swym 0,0,0
+      10:	fd000000 	swym 0,0,0
+      14:	fd000000 	swym 0,0,0
+      18:	fd000000 	swym 0,0,0
+      1c:	e3fd0003 	setl \$253,0x3
+	\.\.\.
+
+0+4000004 <a>:
+ 4000004:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa.s b/binutils-2.19/ld/testsuite/ld-mmix/jumpa.s
new file mode 100644
index 0000000..16ba54b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa.s
@@ -0,0 +1,7 @@
+* Just jump to an external symbol, with some padding.
+ .text
+ .global jumpa
+jumpa:
+ SET $253,2
+ JMP a
+ SET $253,3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa12b.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa12b.d
new file mode 100644
index 0000000..8efe690
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa12b.d
@@ -0,0 +1,26 @@
+#source: start.s
+#source: a.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: jumpa.s
+#as: -no-expand
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+       4:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+
+0+4000000 <jumpa>:
+ 4000000:	e3fd0002 	setl \$253,0x2
+ 4000004:	f1000000 	jmp 4 <a>
+ 4000008:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa12f.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa12f.d
new file mode 100644
index 0000000..6e2968f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa12f.d
@@ -0,0 +1,25 @@
+#source: start.s
+#source: jumpa.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: a.s
+#as: -no-expand
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <jumpa>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f0ffffff 	jmp 4000004 <a>
+       c:	e3fd0003 	setl \$253,0x3
+	\.\.\.
+
+0+4000004 <a>:
+ 4000004:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa13b.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa13b.d
new file mode 100644
index 0000000..bda81e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa13b.d
@@ -0,0 +1,31 @@
+#source: start.s
+#source: a.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: pad4.s
+#source: jumpa.s
+#as: -x
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+       4:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+
+0+4000004 <jumpa>:
+ 4000004:	e3fd0002 	setl \$253,0x2
+ 4000008:	e3ff0004 	setl \$255,0x4
+ 400000c:	e6ff0000 	incml \$255,0x0
+ 4000010:	e5ff0000 	incmh \$255,0x0
+ 4000014:	e4ff0000 	inch \$255,0x0
+ 4000018:	9fffff00 	go \$255,\$255,0
+ 400001c:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa13f.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa13f.d
new file mode 100644
index 0000000..335d7ab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa13f.d
@@ -0,0 +1,29 @@
+#source: start.s
+#source: jumpa.s
+#source: pad2p26m32.s
+#source: pad4.s
+#source: pad4.s
+#source: a.s
+#as: -x
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+       0:	e3fd0001 	setl \$253,0x1
+
+0+4 <jumpa>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	e3ff0008 	setl \$255,0x8
+       c:	e6ff0400 	incml \$255,0x400
+      10:	e5ff0000 	incmh \$255,0x0
+      14:	e4ff0000 	inch \$255,0x0
+      18:	9fffff00 	go \$255,\$255,0
+      1c:	e3fd0003 	setl \$253,0x3
+	\.\.\.
+
+0+4000008 <a>:
+ 4000008:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa14b.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa14b.d
new file mode 100644
index 0000000..006e1bd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa14b.d
@@ -0,0 +1,11 @@
+#source: start.s
+#source: a.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: pad4.s
+#source: jumpa.s
+#as: -no-expand
+#ld: -m mmo
+#error: relocation truncated to fit: R_MMIX_ADDR27 against `a'$
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/jumpa14f.d b/binutils-2.19/ld/testsuite/ld-mmix/jumpa14f.d
new file mode 100644
index 0000000..bcf7504
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/jumpa14f.d
@@ -0,0 +1,10 @@
+#source: start.s
+#source: jumpa.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: a.s
+#as: -no-expand
+#ld: -m mmo
+#error: relocation truncated to fit: R_MMIX_ADDR27 against `a'$
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc1.d b/binutils-2.19/ld/testsuite/ld-mmix/loc1.d
new file mode 100644
index 0000000..cac2689
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc1.d
@@ -0,0 +1,19 @@
+#source: loc1.s
+#ld: -e loc1 -m elf64mmix
+#objdump: -str
+
+# Single text file.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+1000 l    d  \.text	0+ (|\.text)
+0+1000 g       \.text	0+ loc1
+0+1000 g       \*ABS\*	0+ __\.MMIX\.start\.\.text
+2000000000000000 g       \*ABS\*	0+ __bss_start
+2000000000000000 g       \*ABS\*	0+ _edata
+2000000000000000 g       \*ABS\*	0+ _end
+0+1000 g       \.text	0+ _start\.
+
+Contents of section \.text:
+ 1000 fd030303                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc1.s b/binutils-2.19/ld/testsuite/ld-mmix/loc1.s
new file mode 100644
index 0000000..d420650
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc1.s
@@ -0,0 +1,3 @@
+ LOC #1000
+loc1 SWYM 3,3,3
+ .global loc1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc10.d b/binutils-2.19/ld/testsuite/ld-mmix/loc10.d
new file mode 100644
index 0000000..84180b4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc10.d
@@ -0,0 +1,13 @@
+#ld: -m elf64mmix --defsym __.MMIX.start..text=0x8000000000000000
+#objdump: -str
+
+# Setting file start through the special symbol.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+#...
+8000000000000000 g       \*ABS\*	0+ __\.MMIX\.start\.\.text
+#...
+Contents of section \.text:
+ 8000000000000000 f4000000                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc10.s b/binutils-2.19/ld/testsuite/ld-mmix/loc10.s
new file mode 100644
index 0000000..3d139d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc10.s
@@ -0,0 +1 @@
+Boot    GETA    $0,Boot        %set dynamic- and forced-trap  handler
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc10m.d b/binutils-2.19/ld/testsuite/ld-mmix/loc10m.d
new file mode 100644
index 0000000..509f151
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc10m.d
@@ -0,0 +1,10 @@
+#source: loc10.s
+#ld: -m mmo --defsym __.MMIX.start..text=0x8000000000000000
+#objdump: -str
+
+# Setting file start through the special symbol, mmo version.
+
+.*:     file format mmo
+#...
+Contents of section \.text:
+ 8000000000000000 f4000000                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc1m.d b/binutils-2.19/ld/testsuite/ld-mmix/loc1m.d
new file mode 100644
index 0000000..9721bcb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc1m.d
@@ -0,0 +1,14 @@
+#source: loc1.s
+#ld: -m mmo -e loc1
+#objdump: -str
+
+# err: two locs.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+1000 g       \.text Main
+0+1000 g       \.text loc1
+
+Contents of section \.text:
+ 1000 fd030303                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc2.d b/binutils-2.19/ld/testsuite/ld-mmix/loc2.d
new file mode 100644
index 0000000..7d44c22
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc2.d
@@ -0,0 +1,21 @@
+#source: loc1.s
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -str
+
+# Two text files.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+1000 l    d  \.text	0+ (|\.text)
+0+1004 g       \.text	0+ _start
+0+1000 g       \.text	0+ loc1
+0+1000 g       \*ABS\*	0+ __\.MMIX\.start\.\.text
+2000000000000000 g       \*ABS\*	0+ __bss_start
+2000000000000000 g       \*ABS\*	0+ _edata
+2000000000000000 g       \*ABS\*	0+ _end
+0+1004 g       \.text	0+ _start\.
+
+Contents of section \.text:
+ 1000 fd030303 e3fd0001                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc2.s b/binutils-2.19/ld/testsuite/ld-mmix/loc2.s
new file mode 100644
index 0000000..1c25693
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc2.s
@@ -0,0 +1,3 @@
+ LOC #2000
+loc2 SWYM 3,2,3
+ .global loc2
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc2m.d b/binutils-2.19/ld/testsuite/ld-mmix/loc2m.d
new file mode 100644
index 0000000..4d62b24
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc2m.d
@@ -0,0 +1,14 @@
+#source: loc1.s
+#source: start.s
+#ld: -m mmo
+#objdump: -str
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+1004 g       \.text Main
+0+1004 g       \.text _start
+0+1000 g       \.text loc1
+
+Contents of section \.text:
+ 1000 fd030303 e3fd0001                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc3.d b/binutils-2.19/ld/testsuite/ld-mmix/loc3.d
new file mode 100644
index 0000000..ff0fe8a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc3.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: loc1.s
+#ld: -m elf64mmix
+#objdump: -str
+
+# Two text files in opposite order.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+1000 l    d  \.text	0+ (|\.text)
+0+1000 g       \.text	0+ _start
+0+1004 g       \.text	0+ loc1
+0+1000 g       \*ABS\*	0+ __\.MMIX\.start\.\.text
+2000000000000000 g       \*ABS\*	0+ __bss_start
+2000000000000000 g       \*ABS\*	0+ _edata
+2000000000000000 g       \*ABS\*	0+ _end
+0+1000 g       \.text	0+ _start\.
+
+Contents of section \.text:
+ 1000 e3fd0001 fd030303                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc3m.d b/binutils-2.19/ld/testsuite/ld-mmix/loc3m.d
new file mode 100644
index 0000000..928ac9e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc3m.d
@@ -0,0 +1,14 @@
+#source: start.s
+#source: loc1.s
+#ld: -m mmo
+#objdump: -str
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+1000 g       \.text Main
+0+1000 g       \.text _start
+0+1004 g       \.text loc1
+
+Contents of section \.text:
+ 1000 e3fd0001 fd030303                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc4.d b/binutils-2.19/ld/testsuite/ld-mmix/loc4.d
new file mode 100644
index 0000000..34428a9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc4.d
@@ -0,0 +1,28 @@
+#source: loc1.s
+#source: data1.s
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -str
+
+# Two text files and one data.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+1000 l    d  \.text	0+ (|\.text)
+2000000000000000 l    d  \.data	0+ (|\.data)
+2000000000000000 l       \.data	0+ xx
+0+1004 g     F \.text	0+ Main
+2000000000000000 g       \*ABS\*	0+ __\.MMIX\.start\.\.data
+0+1004 g       \.text	0+ _start
+0+1000 g       \.text	0+ loc1
+0+1000 g       \*ABS\*	0+ __\.MMIX\.start\.\.text
+2000000000000008 g       \*ABS\*	0+ __bss_start
+2000000000000008 g       \*ABS\*	0+ _edata
+2000000000000008 g       \*ABS\*	0+ _end
+0+1004 g       \.text	0+ _start\.
+
+Contents of section \.text:
+ 1000 fd030303 e3fd0001                    .*
+Contents of section \.data:
+ 2000000000000000 00000000 00001030                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc4m.d b/binutils-2.19/ld/testsuite/ld-mmix/loc4m.d
new file mode 100644
index 0000000..40a4f97
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc4m.d
@@ -0,0 +1,17 @@
+#source: loc1.s
+#source: data1.s
+#source: start.s
+#ld: -m mmo
+#objdump: -str
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+1004 g       \.text Main
+0+1004 g       \.text _start
+0+1000 g       \.text loc1
+
+Contents of section \.text:
+ 1000 fd030303 e3fd0001                    .*
+Contents of section \.data:
+ 2000000000000004 00001030                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc5.d b/binutils-2.19/ld/testsuite/ld-mmix/loc5.d
new file mode 100644
index 0000000..089c155
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc5.d
@@ -0,0 +1,6 @@
+#source: loc1.s
+#source: start.s
+#source: loc2.s
+#ld: -m elf64mmix
+#objdump: -str
+#error: multiple definition of `__\.MMIX\.start\.\.text'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc5m.d b/binutils-2.19/ld/testsuite/ld-mmix/loc5m.d
new file mode 100644
index 0000000..8fedb1c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc5m.d
@@ -0,0 +1,6 @@
+#source: loc1.s
+#source: start.s
+#source: loc2.s
+#ld: -m mmo
+#objdump: -str
+#error: multiple definition of `__\.MMIX\.start\.\.text'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc6.d b/binutils-2.19/ld/testsuite/ld-mmix/loc6.d
new file mode 100644
index 0000000..425edae
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc6.d
@@ -0,0 +1,24 @@
+#source: dloc1.s
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -str
+
+# Text files and one loc:ed data at offset.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+2000000000000200 l    d  \.data	0+ (|\.data)
+2000000000000200 g       \.data	0+ dloc1
+2000000000000200 g       \*ABS\*	0+ __\.MMIX\.start\.\.data
+0+ g       \.text	0+ _start
+200000000000020c g       \*ABS\*	0+ __bss_start
+200000000000020c g       \*ABS\*	0+ _edata
+2000000000000210 g       \*ABS\*	0+ _end
+0+ g       \.text	0+ _start\.
+
+Contents of section \.text:
+ 0000 e3fd0001                             .*
+Contents of section \.data:
+ 2000000000000200 00000004 00000005 00000006           .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc6m.d b/binutils-2.19/ld/testsuite/ld-mmix/loc6m.d
new file mode 100644
index 0000000..b2a58a7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc6m.d
@@ -0,0 +1,18 @@
+#source: dloc1.s
+#source: start.s
+#ld: -m mmo
+#objdump: -str
+
+# Text files and one loc:ed data at offset.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g       \.text Main
+2000000000000200 g       \.data dloc1
+0+ g       \.text _start
+
+Contents of section \.text:
+ 0000 e3fd0001                             .*
+Contents of section \.data:
+ 2000000000000200 00000004 00000005 00000006           .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc7.d b/binutils-2.19/ld/testsuite/ld-mmix/loc7.d
new file mode 100644
index 0000000..b980f61
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc7.d
@@ -0,0 +1,6 @@
+#source: dloc1.s
+#source: start.s
+#source: dloc2.s
+#ld: -m elf64mmix
+#objdump: -str
+#error: multiple definition of `__\.MMIX\.start\.\.data'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc7m.d b/binutils-2.19/ld/testsuite/ld-mmix/loc7m.d
new file mode 100644
index 0000000..be8115f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc7m.d
@@ -0,0 +1,6 @@
+#source: dloc1.s
+#source: start.s
+#source: dloc2.s
+#ld: -m mmo
+#objdump: -str
+#error: multiple definition of `__\.MMIX\.start\.\.data'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc8.d b/binutils-2.19/ld/testsuite/ld-mmix/loc8.d
new file mode 100644
index 0000000..ac68990
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc8.d
@@ -0,0 +1,13 @@
+#ld: -m elf64mmix
+#objdump: -str
+
+# Setting file start through the special symbol, in-source.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+#...
+8000000000000000 g       \*ABS\*	0+ __\.MMIX\.start\.\.text
+#...
+Contents of section \.text:
+ 8000000000000000 f4000000                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc8.s b/binutils-2.19/ld/testsuite/ld-mmix/loc8.s
new file mode 100644
index 0000000..28592f9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc8.s
@@ -0,0 +1,3 @@
+ .globl __.MMIX.start..text
+ .set __.MMIX.start..text,0x8000000000000000
+Boot    GETA    $0,Boot        %set dynamic- and forced-trap  handler
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc8m.d b/binutils-2.19/ld/testsuite/ld-mmix/loc8m.d
new file mode 100644
index 0000000..52fb079
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc8m.d
@@ -0,0 +1,10 @@
+#source: loc8.s
+#ld: -m mmo
+#objdump: -str
+
+# Setting file start through the special symbol, in-source, mmo version.
+
+.*:     file format mmo
+#...
+Contents of section \.text:
+ 8000000000000000 f4000000                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc9.d b/binutils-2.19/ld/testsuite/ld-mmix/loc9.d
new file mode 100644
index 0000000..458fef6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc9.d
@@ -0,0 +1,13 @@
+#ld: -m elf64mmix
+#objdump: -str
+
+# Setting file start through the LOC pseudo, see PR 6607.
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+#...
+8000000000000000 g       \*ABS\*	0+ __\.MMIX\.start\.\.text
+#...
+Contents of section \.text:
+ 8000000000000000 f4000000                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc9.s b/binutils-2.19/ld/testsuite/ld-mmix/loc9.s
new file mode 100644
index 0000000..99a5c5d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc9.s
@@ -0,0 +1,3 @@
+	LOC     #8000000000000000
+Boot    GETA    $0,Boot        %set dynamic- and forced-trap  handler
+	.globl	Boot
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loc9m.d b/binutils-2.19/ld/testsuite/ld-mmix/loc9m.d
new file mode 100644
index 0000000..be2beff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loc9m.d
@@ -0,0 +1,14 @@
+#source: loc9.s
+#ld: -e Boot -m mmo
+#objdump: -str
+
+# Setting file start through the LOC pseudo, see PR 6607, mmo version.
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+#...
+8000000000000000 g       \.text Boot
+#...
+Contents of section \.text:
+ 8000000000000000 f4000000                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local1.d b/binutils-2.19/ld/testsuite/ld-mmix/local1.d
new file mode 100644
index 0000000..fc08da7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local1.d
@@ -0,0 +1,50 @@
+#source: greg-4.s
+#source: greg-4.s
+#source: local1.s
+#source: regext1.s
+#source: start.s
+#ld: -m elf64mmix
+#readelf: -Ssx1 -x2
+
+# We check that the externally visible symbol ext1 is a local register
+# (different meaning of "local" than for symbol), which can be seen as
+# somewhat twisted.
+
+There are 6 section headers, starting at offset 0xc8:
+
+Section Headers:
+  \[Nr\] Name              Type             Address           Offset
+       Size              EntSize          Flags  Link  Info  Align
+  \[ 0\]                   NULL             0+  0+
+       0+  0+           0     0     0
+  \[ 1\] \.text             PROGBITS         0+  0+78
+       0+8  0+  AX       0     0     4
+  \[ 2\] \.MMIX\.reg_content PROGBITS         0+7e8  0+80
+       0+10  0+   W       0     0     1
+  \[ 3\] \.shstrtab         STRTAB           0+  0+90
+       0+34  0+           0     0     1
+  \[ 4\] \.symtab           SYMTAB           0+  0+248
+       0+108  0+18           5     5     8
+  \[ 5\] \.strtab           STRTAB           0+  0+350
+       0+32  0+           0     0     1
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+Symbol table '\.symtab' contains 11 entries:
+   Num:    Value          Size Type    Bind   Vis      Ndx Name
+     0: 0+     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 0+     0 SECTION LOCAL  DEFAULT    1 
+     2: 0+7e8     0 SECTION LOCAL  DEFAULT    2 
+     3: 0+fd     0 NOTYPE  LOCAL  DEFAULT PRC\[0xff00\] lsym
+     4: 0+fe     0 NOTYPE  LOCAL  DEFAULT PRC\[0xff00\] lsym
+     5: 0+fc     0 NOTYPE  GLOBAL DEFAULT PRC\[0xff00\] ext1
+     6: 0+4     0 NOTYPE  GLOBAL DEFAULT    1 _start
+#...
+
+Hex dump of section '\.text':
+  0x0+ fd030201 e3fd0001                   .*
+
+Hex dump of section '\.MMIX\.reg_contents':
+  0x0+7e8 00000000 0000004e 00000000 0000004e .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local1.s b/binutils-2.19/ld/testsuite/ld-mmix/local1.s
new file mode 100644
index 0000000..47bf390
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local1.s
@@ -0,0 +1,2 @@
+ LOCAL ext1
+ SWYM 3,2,1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local10.d b/binutils-2.19/ld/testsuite/ld-mmix/local10.d
new file mode 100644
index 0000000..f276405
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local10.d
@@ -0,0 +1,5 @@
+#source: local1.s
+#source: ext1g.s
+#source: start.s
+#ld: -m elf64mmix
+#error: 254 is not a local register
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local10m.d b/binutils-2.19/ld/testsuite/ld-mmix/local10m.d
new file mode 100644
index 0000000..9095d74
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local10m.d
@@ -0,0 +1,5 @@
+#source: local1.s
+#source: ext1g.s
+#source: start.s
+#ld: -m mmo
+#error: 254 is not a local register
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local11.d b/binutils-2.19/ld/testsuite/ld-mmix/local11.d
new file mode 100644
index 0000000..761cea0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local11.d
@@ -0,0 +1,6 @@
+#source: local1.s
+#source: greg-1.s
+#source: ext1l.s
+#source: start.s
+#ld: -m elf64mmix
+#error: valid only with a register or absolute value
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local11m.d b/binutils-2.19/ld/testsuite/ld-mmix/local11m.d
new file mode 100644
index 0000000..b6952a7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local11m.d
@@ -0,0 +1,6 @@
+#source: local1.s
+#source: greg-1.s
+#source: ext1l.s
+#source: start.s
+#ld: -m mmo
+#error: valid only with a register or absolute value
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local12.d b/binutils-2.19/ld/testsuite/ld-mmix/local12.d
new file mode 100644
index 0000000..2dd1eb4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local12.d
@@ -0,0 +1,16 @@
+#source: local1.s
+#source: ext1-254.s
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -shr
+
+# Check that 254 is local when we don't have any registers.
+
+.*:     file format elf64-mmix
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+8  0+  0+  0+78  2\*\*2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+Contents of section \.text:
+ 0000 fd030201 e3fd0001                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local12m.d b/binutils-2.19/ld/testsuite/ld-mmix/local12m.d
new file mode 100644
index 0000000..2cfb701
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local12m.d
@@ -0,0 +1,16 @@
+#source: local1.s
+#source: ext1-254.s
+#source: start.s
+#ld: -m mmo
+#objdump: -shr
+
+# Check that 254 is local when we don't have any registers.
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+8  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+Contents of section \.text:
+ 0000 fd030201 e3fd0001                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local1m.d b/binutils-2.19/ld/testsuite/ld-mmix/local1m.d
new file mode 100644
index 0000000..a5c63e7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local1m.d
@@ -0,0 +1,19 @@
+#source: greg-4.s
+#source: greg-4.s
+#source: local1.s
+#source: regext1.s
+#source: start.s
+#ld: -m mmo
+#objdump: -str
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+4 g       \.text Main
+0+fc g       \*REG\* ext1
+0+4 g       \.text _start
+
+Contents of section \.text:
+ 0000 fd030201 e3fd0001                    .*
+Contents of section \.MMIX\.reg_contents:
+ 07e8 00000000 0000004e 00000000 0000004e  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local2.d b/binutils-2.19/ld/testsuite/ld-mmix/local2.d
new file mode 100644
index 0000000..e5ad203
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local2.d
@@ -0,0 +1,8 @@
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: local1.s
+#source: regext1.s
+#source: start.s
+#ld: -m elf64mmix
+#error: not a local register
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local2.s b/binutils-2.19/ld/testsuite/ld-mmix/local2.s
new file mode 100644
index 0000000..9d2c329
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local2.s
@@ -0,0 +1,2 @@
+ LOCAL 128
+ SWYM 2,2,2
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local2m.d b/binutils-2.19/ld/testsuite/ld-mmix/local2m.d
new file mode 100644
index 0000000..6e88936
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local2m.d
@@ -0,0 +1,8 @@
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: local1.s
+#source: regext1.s
+#source: start.s
+#ld: -m mmo
+#error: not a local register
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local3.d b/binutils-2.19/ld/testsuite/ld-mmix/local3.d
new file mode 100644
index 0000000..62db6c3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local3.d
@@ -0,0 +1,48 @@
+#source: greg-4.s
+#source: greg-4.s
+#source: local1.s
+#source: ext1.s
+#source: start.s
+#ld: -m elf64mmix
+#readelf:  -Ssx1 -x2
+
+# Like local1, but ext1 is here a constant, not a global register.
+
+There are 6 section headers, starting at offset 0xc8:
+
+Section Headers:
+  \[Nr\] Name              Type             Address           Offset
+       Size              EntSize          Flags  Link  Info  Align
+  \[ 0\]                   NULL             0+  0+
+       0+  0+           0     0     0
+  \[ 1\] \.text             PROGBITS         0+  0+78
+       0+8  0+  AX       0     0     4
+  \[ 2\] \.MMIX\.reg_content PROGBITS         0+7e8  0+80
+       0+10  0+   W       0     0     1
+  \[ 3\] \.shstrtab         STRTAB           0+  0+90
+       0+34  0+           0     0     1
+  \[ 4\] \.symtab           SYMTAB           0+  0+248
+       0+108  0+18           5     5     8
+  \[ 5\] \.strtab           STRTAB           0+  0+350
+       0+32  0+           0     0     1
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+Symbol table '\.symtab' contains 11 entries:
+   Num:    Value          Size Type    Bind   Vis      Ndx Name
+     0: 0+     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 0+     0 SECTION LOCAL  DEFAULT    1 
+     2: 0+7e8     0 SECTION LOCAL  DEFAULT    2 
+     3: 0+fd     0 NOTYPE  LOCAL  DEFAULT PRC\[0xff00\] lsym
+     4: 0+fe     0 NOTYPE  LOCAL  DEFAULT PRC\[0xff00\] lsym
+     5: 0+fc     0 NOTYPE  GLOBAL DEFAULT  ABS ext1
+     6: 0+4     0 NOTYPE  GLOBAL DEFAULT    1 _start
+#...
+
+Hex dump of section '\.text':
+  0x0+ fd030201 e3fd0001                   .*
+
+Hex dump of section '\.MMIX\.reg_contents':
+  0x0+7e8 00000000 0000004e 00000000 0000004e .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local3m.d b/binutils-2.19/ld/testsuite/ld-mmix/local3m.d
new file mode 100644
index 0000000..2143d70
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local3m.d
@@ -0,0 +1,19 @@
+#source: greg-4.s
+#source: greg-4.s
+#source: local1.s
+#source: ext1.s
+#source: start.s
+#ld: -m mmo
+#objdump: -str
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+4 g       \.text Main
+0+fc g       \*ABS\* ext1
+0+4 g       \.text _start
+
+Contents of section \.text:
+ 0000 fd030201 e3fd0001                    .*
+Contents of section \.MMIX\.reg_contents:
+ 07e8 00000000 0000004e 00000000 0000004e  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local4.d b/binutils-2.19/ld/testsuite/ld-mmix/local4.d
new file mode 100644
index 0000000..13fa8e6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local4.d
@@ -0,0 +1,8 @@
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: local1.s
+#source: ext1.s
+#source: start.s
+#ld: -m elf64mmix
+#error: not a local register
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local4m.d b/binutils-2.19/ld/testsuite/ld-mmix/local4m.d
new file mode 100644
index 0000000..d18cb20
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local4m.d
@@ -0,0 +1,8 @@
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: local1.s
+#source: ext1.s
+#source: start.s
+#ld: -m mmo
+#error: is not a local register
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local5.d b/binutils-2.19/ld/testsuite/ld-mmix/local5.d
new file mode 100644
index 0000000..955c3fa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local5.d
@@ -0,0 +1,49 @@
+#source: greg-4.s
+#source: greg-4.s
+#source: local2.s
+#source: local1.s
+#source: regext1.s
+#source: start.s
+#ld: -m elf64mmix
+#readelf:  -Ssx1 -x2
+
+# Like local1, but with two checks for a local register.
+
+There are 6 section headers, starting at offset 0xc8:
+
+Section Headers:
+  \[Nr\] Name              Type             Address           Offset
+       Size              EntSize          Flags  Link  Info  Align
+  \[ 0\]                   NULL             0+  0+
+       0+  0+           0     0     0
+  \[ 1\] \.text             PROGBITS         0+  0+78
+       0+c  0+  AX       0     0     4
+  \[ 2\] \.MMIX\.reg_content PROGBITS         0+7e8  0+84
+       0+10  0+   W       0     0     1
+  \[ 3\] \.shstrtab         STRTAB           0+  0+94
+       0+34  0+           0     0     1
+  \[ 4\] \.symtab           SYMTAB           0+  0+248
+       0+108  0+18           5     5     8
+  \[ 5\] \.strtab           STRTAB           0+  0+350
+       0+32  0+           0     0     1
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+Symbol table '\.symtab' contains 11 entries:
+   Num:    Value          Size Type    Bind   Vis      Ndx Name
+     0: 0+     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 0+     0 SECTION LOCAL  DEFAULT    1 
+     2: 0+7e8     0 SECTION LOCAL  DEFAULT    2 
+     3: 0+fd     0 NOTYPE  LOCAL  DEFAULT PRC\[0xff00\] lsym
+     4: 0+fe     0 NOTYPE  LOCAL  DEFAULT PRC\[0xff00\] lsym
+     5: 0+fc     0 NOTYPE  GLOBAL DEFAULT PRC\[0xff00\] ext1
+     6: 0+8     0 NOTYPE  GLOBAL DEFAULT    1 _start
+#...
+
+Hex dump of section '\.text':
+  0x0+ fd020202 fd030201 e3fd0001          .*
+
+Hex dump of section '\.MMIX\.reg_contents':
+  0x0+7e8 00000000 0000004e 00000000 0000004e .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local5m.d b/binutils-2.19/ld/testsuite/ld-mmix/local5m.d
new file mode 100644
index 0000000..6b4c89b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local5m.d
@@ -0,0 +1,21 @@
+#source: greg-4.s
+#source: greg-4.s
+#source: local2.s
+#source: local1.s
+#source: regext1.s
+#source: start.s
+#ld: -m mmo
+#objdump: -str
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+8 g       \.text Main
+0+fc g       \*REG\* ext1
+0+8 g       \.text _start
+
+
+Contents of section \.text:
+ 0000 fd020202 fd030201 e3fd0001           .*
+Contents of section \.MMIX\.reg_contents:
+ 07e8 00000000 0000004e 00000000 0000004e  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local6.d b/binutils-2.19/ld/testsuite/ld-mmix/local6.d
new file mode 100644
index 0000000..b2ed1ed
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local6.d
@@ -0,0 +1,9 @@
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: local1.s
+#source: local2.s
+#source: ext1.s
+#source: start.s
+#ld: -m elf64mmix
+#error: not a local register
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local6m.d b/binutils-2.19/ld/testsuite/ld-mmix/local6m.d
new file mode 100644
index 0000000..be64ca2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local6m.d
@@ -0,0 +1,9 @@
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: local1.s
+#source: local2.s
+#source: ext1.s
+#source: start.s
+#ld: -m mmo
+#error: not a local register
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local7.d b/binutils-2.19/ld/testsuite/ld-mmix/local7.d
new file mode 100644
index 0000000..0109d13
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local7.d
@@ -0,0 +1,50 @@
+#source: greg-4.s
+#source: greg-4.s
+#source: local1.s
+#source: local2.s
+#source: ext1.s
+#source: start.s
+#ld: -m elf64mmix
+#readelf:  -Ssx1 -x2
+
+# Like local1, but ext1 is here a constant, not a global register and two
+# local-register checks.
+
+There are 6 section headers, starting at offset 0xc8:
+
+Section Headers:
+  \[Nr\] Name              Type             Address           Offset
+       Size              EntSize          Flags  Link  Info  Align
+  \[ 0\]                   NULL             0+  0+
+       0+  0+           0     0     0
+  \[ 1\] \.text             PROGBITS         0+  0+78
+       0+c  0+  AX       0     0     4
+  \[ 2\] \.MMIX\.reg_content PROGBITS         0+7e8  0+84
+       0+10  0+   W       0     0     1
+  \[ 3\] \.shstrtab         STRTAB           0+  0+94
+       0+34  0+           0     0     1
+  \[ 4\] \.symtab           SYMTAB           0+  0+248
+       0+108  0+18           5     5     8
+  \[ 5\] \.strtab           STRTAB           0+  0+350
+       0+32  0+           0     0     1
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+Symbol table '\.symtab' contains 11 entries:
+   Num:    Value          Size Type    Bind   Vis      Ndx Name
+     0: 0+     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 0+     0 SECTION LOCAL  DEFAULT    1 
+     2: 0+7e8     0 SECTION LOCAL  DEFAULT    2 
+     3: 0+fd     0 NOTYPE  LOCAL  DEFAULT PRC\[0xff00\] lsym
+     4: 0+fe     0 NOTYPE  LOCAL  DEFAULT PRC\[0xff00\] lsym
+     5: 0+fc     0 NOTYPE  GLOBAL DEFAULT  ABS ext1
+     6: 0+8     0 NOTYPE  GLOBAL DEFAULT    1 _start
+#...
+
+Hex dump of section '\.text':
+  0x0+ fd030201 fd020202 e3fd0001          .*
+
+Hex dump of section '\.MMIX\.reg_contents':
+  0x0+7e8 00000000 0000004e 00000000 0000004e .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local7m.d b/binutils-2.19/ld/testsuite/ld-mmix/local7m.d
new file mode 100644
index 0000000..8277a94
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local7m.d
@@ -0,0 +1,20 @@
+#source: greg-4.s
+#source: greg-4.s
+#source: local1.s
+#source: local2.s
+#source: ext1.s
+#source: start.s
+#ld: -m mmo
+#objdump: -str
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+8 g       \.text Main
+0+fc g       \*ABS\* ext1
+0+8 g       \.text _start
+
+Contents of section \.text:
+ 0000 fd030201 fd020202 e3fd0001           .*
+Contents of section \.MMIX\.reg_contents:
+ 07e8 00000000 0000004e 00000000 0000004e  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local8.d b/binutils-2.19/ld/testsuite/ld-mmix/local8.d
new file mode 100644
index 0000000..f82e6d0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local8.d
@@ -0,0 +1,28 @@
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: local2.s
+#source: local1.s
+#source: ext1.s
+#source: start.s
+#ld: -m elf64mmix
+#error: 128 is not a local register
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local8m.d b/binutils-2.19/ld/testsuite/ld-mmix/local8m.d
new file mode 100644
index 0000000..4e07afe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local8m.d
@@ -0,0 +1,28 @@
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-5.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: greg-4.s
+#source: local2.s
+#source: local1.s
+#source: ext1.s
+#source: start.s
+#ld: -m mmo
+#error: 128 is not a local register
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local9.d b/binutils-2.19/ld/testsuite/ld-mmix/local9.d
new file mode 100644
index 0000000..cc4f8c7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local9.d
@@ -0,0 +1,5 @@
+#source: local1.s
+#source: ext1l.s
+#source: start.s
+#ld: -m elf64mmix
+#error: valid only with a register or absolute value
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/local9m.d b/binutils-2.19/ld/testsuite/ld-mmix/local9m.d
new file mode 100644
index 0000000..7842984
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/local9m.d
@@ -0,0 +1,5 @@
+#source: local1.s
+#source: ext1l.s
+#source: start.s
+#ld: -m mmo
+#error: valid only with a register or absolute value
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/locdo-1.d b/binutils-2.19/ld/testsuite/ld-mmix/locdo-1.d
new file mode 100644
index 0000000..4a16735
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/locdo-1.d
@@ -0,0 +1,23 @@
+#source: locdo.s -globalize-symbols
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -str
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+2000000000000008 l    d  \.data	0+ (|\.data)
+2000000000000008 g       \*ABS\*	0+ __\.MMIX\.start\.\.data
+2000000000000008 g       \.data	0+ od
+0+ g       \.text	0+ _start
+2000000000000010 g       \*ABS\*	0+ __bss_start
+2000000000000000 g       \*ABS\*	0+ Data_Segment
+2000000000000010 g       \*ABS\*	0+ _edata
+2000000000000010 g       \*ABS\*	0+ _end
+0+ g       \.text	0+ _start\.
+
+Contents of section \.text:
+ 0000 e3fd0001                             .*
+Contents of section \.data:
+ 2000000000000008 20000000 00000008                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/locdo.s b/binutils-2.19/ld/testsuite/ld-mmix/locdo.s
new file mode 100644
index 0000000..3402445
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/locdo.s
@@ -0,0 +1,2 @@
+ LOC  Data_Segment+2
+od OCTA od
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loct-1.d b/binutils-2.19/ld/testsuite/ld-mmix/loct-1.d
new file mode 100644
index 0000000..24f4112
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loct-1.d
@@ -0,0 +1,19 @@
+#source: loct.s
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -str
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+1004 l    d  \.text	0+ (|\.text)
+0+1004 l       \.text	0+ t
+0+100c g       \.text	0+ _start
+0+1004 g       \*ABS\*	0+ __\.MMIX\.start\.\.text
+2000000000000000 g       \*ABS\*	0+ __bss_start
+2000000000000000 g       \*ABS\*	0+ _edata
+2000000000000000 g       \*ABS\*	0+ _end
+0+100c g       \.text	0+ _start\.
+
+Contents of section \.text:
+ 1004 fd000000 00001004 e3fd0001           .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/loct.s b/binutils-2.19/ld/testsuite/ld-mmix/loct.s
new file mode 100644
index 0000000..5aaa406
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/loct.s
@@ -0,0 +1,3 @@
+ LOC  #1002
+t SWYM
+ TETRA t
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/locto-1.d b/binutils-2.19/ld/testsuite/ld-mmix/locto-1.d
new file mode 100644
index 0000000..5c5c391
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/locto-1.d
@@ -0,0 +1,19 @@
+#source: locto.s -globalize-symbols
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -str
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+1008 l    d  \.text	0+ (|\.text)
+0+1008 g       \.text	0+ od
+0+1010 g       \.text	0+ _start
+0+1008 g       \*ABS\*	0+ __\.MMIX\.start\.\.text
+2000000000000000 g       \*ABS\*	0+ __bss_start
+2000000000000000 g       \*ABS\*	0+ _edata
+2000000000000000 g       \*ABS\*	0+ _end
+0+1010 g       \.text	0+ _start\.
+
+Contents of section \.text:
+ 1008 00000000 00001008 e3fd0001           .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/locto.s b/binutils-2.19/ld/testsuite/ld-mmix/locto.s
new file mode 100644
index 0000000..5ffa445
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/locto.s
@@ -0,0 +1,2 @@
+ LOC  #1002
+od OCTA od
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/main1.s b/binutils-2.19/ld/testsuite/ld-mmix/main1.s
new file mode 100644
index 0000000..212d1ef
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/main1.s
@@ -0,0 +1,5 @@
+% For tests regarding the Main symbol and mmo.  Most tests use start.s as
+% a base file.
+ .text
+Main:
+ SET $253,1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/mmix.exp b/binutils-2.19/ld/testsuite/ld-mmix/mmix.exp
new file mode 100644
index 0000000..b4d87d0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/mmix.exp
@@ -0,0 +1,35 @@
+# Expect script for ld-mmix tests
+#   Copyright 2001, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Hans-Peter Nilsson (hp@bitrange.com)
+#
+
+# Test MMIX and mmo object format handling.
+
+if ![istarget mmix-*-*] {
+    return
+}
+
+set rd_test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach mmixtest $rd_test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname $mmixtest]
+    run_dump_test [file rootname $mmixtest]
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/mmohdr1.ld b/binutils-2.19/ld/testsuite/ld-mmix/mmohdr1.ld
new file mode 100644
index 0000000..716c3f4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/mmohdr1.ld
@@ -0,0 +1,11 @@
+OUTPUT_ARCH(mmix)
+OUTPUT_FORMAT("mmo")
+ENTRY(Main)
+SECTIONS
+{
+  .text 0x100 + sizeof_headers :
+  { *(.text); Main = _start; }
+
+  .MMIX.reg_contents :
+  { *(.MMIX.reg_contents); }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/mmosec1.ld b/binutils-2.19/ld/testsuite/ld-mmix/mmosec1.ld
new file mode 100644
index 0000000..4e7e799
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/mmosec1.ld
@@ -0,0 +1,16 @@
+OUTPUT_ARCH(mmix)
+ENTRY(Main)
+SECTIONS
+{
+   .text 0x100 :
+   { *(.text); Main = _start; }
+
+   .other 0x1000000000000000 :
+   { *(secname); *(anothersec); *(thirdsec); *(.a.fourth.section); }
+
+   .data 0x2000000000000000 :
+   { *(.data); }
+
+  .MMIX.reg_contents :
+  { *(.MMIX.reg_contents); }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/mmosec2.ld b/binutils-2.19/ld/testsuite/ld-mmix/mmosec2.ld
new file mode 100644
index 0000000..57025e2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/mmosec2.ld
@@ -0,0 +1,13 @@
+OUTPUT_ARCH(mmix)
+ENTRY(Main)
+SECTIONS
+{
+   .text 0x1000000000000000 :
+   { *(.text); Main = _start; }
+
+   .data 0x2000000000000000 :
+   { *(.data); }
+
+  .MMIX.reg_contents :
+  { *(.MMIX.reg_contents); }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/nop123.s b/binutils-2.19/ld/testsuite/ld-mmix/nop123.s
new file mode 100644
index 0000000..2d14f43
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/nop123.s
@@ -0,0 +1,3 @@
+# A nop to pad with an explicit insn.
+ .text
+ SWYM 1,2,3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pad16.s b/binutils-2.19/ld/testsuite/ld-mmix/pad16.s
new file mode 100644
index 0000000..7692337
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pad16.s
@@ -0,0 +1,4 @@
+* Padding 16 bytes, suitable for testing relocs together with the larger
+* padding files.
+ .text
+ .space 16,0
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pad2p18m32.s b/binutils-2.19/ld/testsuite/ld-mmix/pad2p18m32.s
new file mode 100644
index 0000000..ede581f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pad2p18m32.s
@@ -0,0 +1,4 @@
+* Padding (1 << 19)/2 - 32 bytes; that is, suitable for testing the
+* short-range relocs.
+ .text
+ .space (1 << 19)/2 - 32,0
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pad2p26m32.s b/binutils-2.19/ld/testsuite/ld-mmix/pad2p26m32.s
new file mode 100644
index 0000000..05f45c8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pad2p26m32.s
@@ -0,0 +1,4 @@
+* Padding (1 << 27)/2 - 32 bytes; that is, suitable for testing the
+* long-range relocs.
+ .text
+ .space (1 << 27)/2 - 32,0
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pad4.s b/binutils-2.19/ld/testsuite/ld-mmix/pad4.s
new file mode 100644
index 0000000..49dbe6d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pad4.s
@@ -0,0 +1,4 @@
+* Padding 16 bytes, suitable for testing relocs together with the larger
+* padding files.
+ .text
+ .space 4,0
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushja.s b/binutils-2.19/ld/testsuite/ld-mmix/pushja.s
new file mode 100644
index 0000000..857ca9d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushja.s
@@ -0,0 +1,7 @@
+* Just PUSHJs to an external symbol, with some padding.
+ .text
+ .global pushja
+pushja:
+ SET $253,2
+ PUSHJ $12,a
+ SET $253,3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushja1b-s.d b/binutils-2.19/ld/testsuite/ld-mmix/pushja1b-s.d
new file mode 100644
index 0000000..ac55651
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushja1b-s.d
@@ -0,0 +1,19 @@
+#source: start.s
+#source: a.s
+#source: pushja.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dr
+
+# Like pushja1b but with PUSHJ stub.
+
+.*:     file format elf64-mmix
+Disassembly of section \.text:
+0+ <_start>:
+   0:	e3fd0001 	setl \$253,0x1
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+0+8 <pushja>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	f30cfffe 	pushj \$12,4 <a>
+  10:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushja1b.d b/binutils-2.19/ld/testsuite/ld-mmix/pushja1b.d
new file mode 100644
index 0000000..b61162f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushja1b.d
@@ -0,0 +1,25 @@
+#source: start.s
+#source: a.s
+#source: pushja.s
+#as: -x --no-pushj-stubs
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <pushja>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	e3ff0004 	setl \$255,0x4
+  10:	e6ff0000 	incml \$255,0x0
+  14:	e5ff0000 	incmh \$255,0x0
+  18:	e4ff0000 	inch \$255,0x0
+  1c:	bf0cff00 	pushgo \$12,\$255,0
+  20:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushja1f-s.d b/binutils-2.19/ld/testsuite/ld-mmix/pushja1f-s.d
new file mode 100644
index 0000000..801ff22
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushja1f-s.d
@@ -0,0 +1,19 @@
+#source: start.s
+#source: pushja.s
+#source: a.s
+#as: -x
+#ld: -m elf64mmix
+#objdump: -dr
+
+# Like pushja1f, but with PUSHJ stub.
+
+.*:     file format elf64-mmix
+Disassembly of section \.text:
+0+ <_start>:
+   0:	e3fd0001 	setl \$253,0x1
+0+4 <pushja>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	f20c0002 	pushj \$12,10 <a>
+   c:	e3fd0003 	setl \$253,0x3
+0+10 <a>:
+  10:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushja1f.d b/binutils-2.19/ld/testsuite/ld-mmix/pushja1f.d
new file mode 100644
index 0000000..5f27400
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushja1f.d
@@ -0,0 +1,25 @@
+#source: start.s
+#source: pushja.s
+#source: a.s
+#as: -x --no-pushj-stubs
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <pushja>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	e3ff0020 	setl \$255,0x20
+   c:	e6ff0000 	incml \$255,0x0
+  10:	e5ff0000 	incmh \$255,0x0
+  14:	e4ff0000 	inch \$255,0x0
+  18:	bf0cff00 	pushgo \$12,\$255,0
+  1c:	e3fd0003 	setl \$253,0x3
+
+0+20 <a>:
+  20:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushja2b.d b/binutils-2.19/ld/testsuite/ld-mmix/pushja2b.d
new file mode 100644
index 0000000..623754f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushja2b.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: a.s
+#source: pushja.s
+#as: -no-expand
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <pushja>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	f30cfffe 	pushj \$12,4 <a>
+  10:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushja2f.d b/binutils-2.19/ld/testsuite/ld-mmix/pushja2f.d
new file mode 100644
index 0000000..687d559
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushja2f.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: pushja.s
+#source: a.s
+#as: -no-expand
+#ld: -m elf64mmix
+#objdump: -dr
+
+.*:     file format elf64-mmix
+
+Disassembly of section \.text:
+
+0+ <_start>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <pushja>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	f20c0002 	pushj \$12,10 <a>
+   c:	e3fd0003 	setl \$253,0x3
+
+0+10 <a>:
+  10:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushja7b-s.d b/binutils-2.19/ld/testsuite/ld-mmix/pushja7b-s.d
new file mode 100644
index 0000000..7835eda
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushja7b-s.d
@@ -0,0 +1,19 @@
+#source: start.s
+#source: a.s
+#source: pushja.s
+#as: -x
+#ld: -m mmo
+#objdump: -dr
+
+# Like pushja7b, but with PUSHJ stub.
+
+.*:     file format mmo
+Disassembly of section \.text:
+0+ <(Main|_start)>:
+   0:	e3fd0001 	setl \$253,0x1
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+0+8 <pushja>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	f30cfffe 	pushj \$12,4 <a>
+  10:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushja7b.d b/binutils-2.19/ld/testsuite/ld-mmix/pushja7b.d
new file mode 100644
index 0000000..5da05e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushja7b.d
@@ -0,0 +1,25 @@
+#source: start.s
+#source: a.s
+#source: pushja.s
+#as: -x --no-pushj-stubs
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <pushja>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	e3ff0004 	setl \$255,0x4
+  10:	e6ff0000 	incml \$255,0x0
+  14:	e5ff0000 	incmh \$255,0x0
+  18:	e4ff0000 	inch \$255,0x0
+  1c:	bf0cff00 	pushgo \$12,\$255,0
+  20:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushja7f-s.d b/binutils-2.19/ld/testsuite/ld-mmix/pushja7f-s.d
new file mode 100644
index 0000000..487d54a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushja7f-s.d
@@ -0,0 +1,19 @@
+#source: start.s
+#source: pushja.s
+#source: a.s
+#as: -x
+#ld: -m mmo
+#objdump: -dr
+
+# Like pushja7f, but with PUSHJ stub.
+
+.*:     file format mmo
+Disassembly of section \.text:
+0+ <(Main|_start)>:
+   0:	e3fd0001 	setl \$253,0x1
+0+4 <pushja>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	f20c0002 	pushj \$12,10 <a>
+   c:	e3fd0003 	setl \$253,0x3
+0+10 <a>:
+  10:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushja7f.d b/binutils-2.19/ld/testsuite/ld-mmix/pushja7f.d
new file mode 100644
index 0000000..83721c7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushja7f.d
@@ -0,0 +1,25 @@
+#source: start.s
+#source: pushja.s
+#source: a.s
+#as: -x --no-pushj-stubs
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <pushja>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	e3ff0020 	setl \$255,0x20
+   c:	e6ff0000 	incml \$255,0x0
+  10:	e5ff0000 	incmh \$255,0x0
+  14:	e4ff0000 	inch \$255,0x0
+  18:	bf0cff00 	pushgo \$12,\$255,0
+  1c:	e3fd0003 	setl \$253,0x3
+
+0+20 <a>:
+  20:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushja8b.d b/binutils-2.19/ld/testsuite/ld-mmix/pushja8b.d
new file mode 100644
index 0000000..da1f216
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushja8b.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: a.s
+#source: pushja.s
+#as: -no-expand
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <a>:
+   4:	e3fd0004 	setl \$253,0x4
+
+0+8 <pushja>:
+   8:	e3fd0002 	setl \$253,0x2
+   c:	f30cfffe 	pushj \$12,4 <a>
+  10:	e3fd0003 	setl \$253,0x3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushja8f.d b/binutils-2.19/ld/testsuite/ld-mmix/pushja8f.d
new file mode 100644
index 0000000..8ae45f9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushja8f.d
@@ -0,0 +1,21 @@
+#source: start.s
+#source: pushja.s
+#source: a.s
+#as: -no-expand
+#ld: -m mmo
+#objdump: -dr
+
+.*:     file format mmo
+
+Disassembly of section \.text:
+
+0+ <(Main|_start)>:
+   0:	e3fd0001 	setl \$253,0x1
+
+0+4 <pushja>:
+   4:	e3fd0002 	setl \$253,0x2
+   8:	f20c0002 	pushj \$12,10 <a>
+   c:	e3fd0003 	setl \$253,0x3
+
+0+10 <a>:
+  10:	e3fd0004 	setl \$253,0x4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs1.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs1.d
new file mode 100644
index 0000000..66892e0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs1.d
@@ -0,0 +1,27 @@
+#source: start4.s
+#source: pushja.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: a.s
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -dr
+
+# Check that PUSHJ with an offset just within the offset range gets no
+# stub expansion, ELF version.
+
+.*:     file format elf64-mmix
+Disassembly of section \.init:
+0+ <_start>:
+   0:	e37704a6 	setl \$119,0x4a6
+Disassembly of section \.text:
+0+4 <pushja>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f20cffff 	pushj \$12,40004 <a>
+       c:	e3fd0003 	setl \$253,0x3
+	\.\.\.
+0+40004 <a>:
+   40004:	e3fd0004 	setl \$253,0x4
+0+40008 <_start>:
+   40008:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs1b.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs1b.d
new file mode 100644
index 0000000..f9a2491
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs1b.d
@@ -0,0 +1,31 @@
+#source: start4.s
+#source: nop123.s
+#source: a.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: pushja.s
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -dr
+
+# Check that PUSHJ with an offset just within the offset range gets no
+# stub expansion, backwards, ELF version.
+
+.*:     file format elf64-mmix
+Disassembly of section \.init:
+0+ <_start>:
+   0:	e37704a6 	setl \$119,0x4a6
+Disassembly of section \.text:
+0+4 <a-0x4>:
+       4:	fd010203 	swym 1,2,3
+0+8 <a>:
+       8:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+0+40004 <pushja>:
+   40004:	e3fd0002 	setl \$253,0x2
+   40008:	f30c0000 	pushj \$12,8 <a>
+   4000c:	e3fd0003 	setl \$253,0x3
+0+40010 <_start>:
+   40010:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs1bm.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs1bm.d
new file mode 100644
index 0000000..d70da89
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs1bm.d
@@ -0,0 +1,29 @@
+#source: nop123.s
+#source: nop123.s
+#source: a.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: pushja.s
+#source: start.s
+#ld: -m mmo
+#objdump: -dr
+
+# Check that PUSHJ with an offset just within the offset range gets no
+# stub expansion, backwards, mmo version.
+
+.*:     file format mmo
+Disassembly of section \.text:
+0+ <a-0x8>:
+       0:	fd010203 	swym 1,2,3
+       4:	fd010203 	swym 1,2,3
+0+8 <a>:
+       8:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+0+40004 <pushja>:
+   40004:	e3fd0002 	setl \$253,0x2
+   40008:	f30c0000 	pushj \$12,8 <a>
+   4000c:	e3fd0003 	setl \$253,0x3
+0+40010 <Main>:
+   40010:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs1m.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs1m.d
new file mode 100644
index 0000000..0df80a2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs1m.d
@@ -0,0 +1,26 @@
+#source: nop123.s
+#source: pushja.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: a.s
+#source: start.s
+#ld: -m mmo
+#objdump: -dr
+
+# Check that PUSHJ with an offset just within the offset range gets no
+# stub expansion, mmo version.
+
+.*:     file format mmo
+Disassembly of section \.text:
+0+ <pushja-0x4>:
+       0:	fd010203 	swym 1,2,3
+0+4 <pushja>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f20cffff 	pushj \$12,40004 <a>
+       c:	e3fd0003 	setl \$253,0x3
+	\.\.\.
+0+40004 <a>:
+   40004:	e3fd0004 	setl \$253,0x4
+0+40008 <Main>:
+   40008:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs1r.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs1r.d
new file mode 100644
index 0000000..3083274
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs1r.d
@@ -0,0 +1,22 @@
+#source: nop123.s
+#source: pushja.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: nop123.s
+#ld: -r -m elf64mmix
+#objdump: -dr
+
+# When linking relocatable, check that PUSHJ with a distance to the end of
+# the section just within the offset range gets no stub expansion.
+
+.*:     file format elf64-mmix
+Disassembly of section \.text:
+0+ <pushja-0x4>:
+       0:	fd010203 	swym 1,2,3
+0+4 <pushja>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f20c0000 	pushj \$12,8 <pushja\+0x4>
+			8: R_MMIX_PUSHJ_STUBBABLE	a
+       c:	e3fd0003 	setl \$253,0x3
+	\.\.\.
+   40000:	fd010203 	swym 1,2,3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs2.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs2.d
new file mode 100644
index 0000000..c6b5829
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs2.d
@@ -0,0 +1,29 @@
+#source: start4.s
+#source: pushja.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: a.s
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -dr
+
+# Check that PUSHJ with an offset just outside the PUSHJ offset range gets
+# a JMP stub expansion, ELF version.
+
+.*:     file format elf64-mmix
+Disassembly of section \.init:
+0+ <_start>:
+   0:	e37704a6 	setl \$119,0x4a6
+Disassembly of section \.text:
+0+4 <pushja>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f20c0002 	pushj \$12,10 <pushja\+0xc>
+       c:	e3fd0003 	setl \$253,0x3
+      10:	f000ffff 	jmp 4000c <a>
+	\.\.\.
+0+4000c <a>:
+   4000c:	e3fd0004 	setl \$253,0x4
+0+40010 <_start>:
+   40010:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs2b.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs2b.d
new file mode 100644
index 0000000..a6f2299
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs2b.d
@@ -0,0 +1,33 @@
+#source: start4.s
+#source: nop123.s
+#source: a.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: pad4.s
+#source: pushja.s
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -dr
+
+# Check that PUSHJ with an offset just outside the offset range gets a JMP
+# stub expansion, backwards, ELF version.
+
+.*:     file format elf64-mmix
+Disassembly of section \.init:
+0+ <_start>:
+   0:	e37704a6 	setl \$119,0x4a6
+Disassembly of section \.text:
+0+4 <a-0x4>:
+       4:	fd010203 	swym 1,2,3
+0+8 <a>:
+       8:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+0+40008 <pushja>:
+   40008:	e3fd0002 	setl \$253,0x2
+   4000c:	f20c0002 	pushj \$12,40014 <pushja\+0xc>
+   40010:	e3fd0003 	setl \$253,0x3
+   40014:	f1fefffd 	jmp 8 <a>
+0+40018 <_start>:
+   40018:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs2bm.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs2bm.d
new file mode 100644
index 0000000..1f37c66
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs2bm.d
@@ -0,0 +1,31 @@
+#source: nop123.s
+#source: nop123.s
+#source: a.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: pad4.s
+#source: pushja.s
+#source: start.s
+#ld: -m mmo
+#objdump: -dr
+
+# Check that PUSHJ with an offset just outside the offset range gets a JMP
+# stub expansion, backwards, mmo version.
+
+.*:     file format mmo
+Disassembly of section \.text:
+0+ <a-0x8>:
+       0:	fd010203 	swym 1,2,3
+       4:	fd010203 	swym 1,2,3
+0+8 <a>:
+       8:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+0+40008 <pushja>:
+   40008:	e3fd0002 	setl \$253,0x2
+   4000c:	f20c0002 	pushj \$12,40014 <pushja\+0xc>
+   40010:	e3fd0003 	setl \$253,0x3
+   40014:	f1fefffd 	jmp 8 <a>
+0+40018 <Main>:
+   40018:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs2m.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs2m.d
new file mode 100644
index 0000000..8c7af13
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs2m.d
@@ -0,0 +1,28 @@
+#source: nop123.s
+#source: pushja.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: a.s
+#source: start.s
+#ld: -m mmo
+#objdump: -dr
+
+# Check that PUSHJ with an offset just outside the PUSHJ offset range gets
+# a JMP stub expansion, mmo version.
+
+.*:     file format mmo
+Disassembly of section \.text:
+0+ <pushja-0x4>:
+       0:	fd010203 	swym 1,2,3
+0+4 <pushja>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f20c0002 	pushj \$12,10 <pushja\+0xc>
+       c:	e3fd0003 	setl \$253,0x3
+      10:	f000ffff 	jmp 4000c <a>
+	\.\.\.
+0+4000c <a>:
+   4000c:	e3fd0004 	setl \$253,0x4
+0+40010 <Main>:
+   40010:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs2r.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs2r.d
new file mode 100644
index 0000000..df181e0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs2r.d
@@ -0,0 +1,27 @@
+#source: nop123.s
+#source: pushja.s
+#source: ext1l.s
+#source: pad2p18m32.s
+#source: pad16.s
+#source: nop123.s
+#ld: -r -m elf64mmix
+#objdump: -dr
+
+# When linking relocatably, check that PUSHJ with a distance to the end of
+# the section just outside the offset range gets expanded.
+
+.*:     file format elf64-mmix
+Disassembly of section \.text:
+0+ <pushja-0x4>:
+       0:	fd010203 	swym 1,2,3
+0+4 <pushja>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f20c0002 	pushj \$12,10 <pushja\+0xc>
+       c:	e3fd0003 	setl \$253,0x3
+      10:	f0000000 	jmp 10 <pushja\+0xc>
+			10: R_MMIX_JMP	a
+	\.\.\.
+0+24 <ext1>:
+      24:	fd040810 	swym 4,8,16
+	\.\.\.
+   40018:	fd010203 	swym 1,2,3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs3.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs3.d
new file mode 100644
index 0000000..75afe1b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs3.d
@@ -0,0 +1,29 @@
+#source: start4.s
+#source: pushja.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: a.s
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -dr
+
+# Check that PUSHJ with an offset just within reach of JMP gets it, ELF
+# version.
+
+.*:     file format elf64-mmix
+Disassembly of section \.init:
+0+ <_start>:
+   0:	e37704a6 	setl \$119,0x4a6
+Disassembly of section \.text:
+0+4 <pushja>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f20c0002 	pushj \$12,10 <pushja\+0xc>
+       c:	e3fd0003 	setl \$253,0x3
+      10:	f0ffffff 	jmp 400000c <a>
+	\.\.\.
+0+400000c <a>:
+ 400000c:	e3fd0004 	setl \$253,0x4
+0+4000010 <_start>:
+ 4000010:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs3b.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs3b.d
new file mode 100644
index 0000000..33812bb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs3b.d
@@ -0,0 +1,30 @@
+#source: start4.s
+#source: nop123.s
+#source: a.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pushja.s
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -dr
+
+# Check that PUSHJ with an offset just inside the offset range of a JMP
+# stub expansion works, backwards, ELF version.
+
+.*:     file format elf64-mmix
+Disassembly of section \.init:
+0+ <_start>:
+   0:	e37704a6 	setl \$119,0x4a6
+Disassembly of section \.text:
+0+4 <a-0x4>:
+       4:	fd010203 	swym 1,2,3
+0+8 <a>:
+       8:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+0+3fffffc <pushja>:
+ 3fffffc:	e3fd0002 	setl \$253,0x2
+ 4000000:	f20c0002 	pushj \$12,4000008 <pushja\+0xc>
+ 4000004:	e3fd0003 	setl \$253,0x3
+ 4000008:	f1000000 	jmp 8 <a>
+0+400000c <_start>:
+ 400000c:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs3bm.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs3bm.d
new file mode 100644
index 0000000..f485d14
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs3bm.d
@@ -0,0 +1,28 @@
+#source: nop123.s
+#source: nop123.s
+#source: a.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pushja.s
+#source: start.s
+#ld: -m mmo
+#objdump: -dr
+
+# Check that PUSHJ with an offset just inside the offset range of a JMP
+# stub expansion works, backwards, mmo version.
+
+.*:     file format mmo
+Disassembly of section \.text:
+0+ <a-0x8>:
+       0:	fd010203 	swym 1,2,3
+       4:	fd010203 	swym 1,2,3
+0+8 <a>:
+       8:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+0+3fffffc <pushja>:
+ 3fffffc:	e3fd0002 	setl \$253,0x2
+ 4000000:	f20c0002 	pushj \$12,4000008 <pushja\+0xc>
+ 4000004:	e3fd0003 	setl \$253,0x3
+ 4000008:	f1000000 	jmp 8 <a>
+0+400000c <Main>:
+ 400000c:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs3m.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs3m.d
new file mode 100644
index 0000000..35df726
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs3m.d
@@ -0,0 +1,28 @@
+#source: nop123.s
+#source: pushja.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: a.s
+#source: start.s
+#ld: -m mmo
+#objdump: -dr
+
+# Check that PUSHJ with an offset just within reach of JMP gets it, mmo
+# version.
+
+.*:     file format mmo
+Disassembly of section \.text:
+0+ <pushja-0x4>:
+       0:	fd010203 	swym 1,2,3
+0+4 <pushja>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f20c0002 	pushj \$12,10 <pushja\+0xc>
+       c:	e3fd0003 	setl \$253,0x3
+      10:	f0ffffff 	jmp 400000c <a>
+	\.\.\.
+0+400000c <a>:
+ 400000c:	e3fd0004 	setl \$253,0x4
+0+4000010 <Main>:
+ 4000010:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs3r.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs3r.d
new file mode 100644
index 0000000..537b3f9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs3r.d
@@ -0,0 +1,32 @@
+#source: nop123.s
+#source: pushja.s
+#source: undef-2.s
+#source: nop123.s
+#source: pad16.s
+#source: pad2p18m32.s
+#ld: -r -m elf64mmix
+#objdump: -dr
+
+# When linking relocatably, check two expanded stubbable PUSHJs.
+
+# With better relaxation support for relocatable links, both should be
+# able to pass through unexpanded.  Right now, we just check that they can
+# coexist peacefully.
+
+.*:     file format elf64-mmix
+Disassembly of section \.text:
+0+ <pushja-0x4>:
+       0:	fd010203 	swym 1,2,3
+0+4 <pushja>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f20c0002 	pushj \$12,10 <pushja\+0xc>
+       c:	e3fd0003 	setl \$253,0x3
+      10:	f0000000 	jmp 10 <pushja\+0xc>
+			10: R_MMIX_JMP	a
+	\.\.\.
+      24:	f2050001 	pushj \$5,28 <pushja\+0x24>
+      28:	f0000000 	jmp 28 <pushja\+0x24>
+			28: R_MMIX_JMP	undefd
+	\.\.\.
+      3c:	fd010203 	swym 1,2,3
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs4.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs4.d
new file mode 100644
index 0000000..e010449
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs4.d
@@ -0,0 +1,34 @@
+#source: start4.s
+#source: pushja.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: pad4.s
+#source: a.s
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -dr
+
+# Check that PUSHJ with an offset just outside reach of JMP works; it will
+# get the full expansion, ELF version.
+
+.*:     file format elf64-mmix
+Disassembly of section \.init:
+0+ <_start>:
+   0:	e37704a6 	setl \$119,0x4a6
+Disassembly of section \.text:
+0+4 <pushja>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f20c0002 	pushj \$12,10 <pushja\+0xc>
+       c:	e3fd0003 	setl \$253,0x3
+      10:	e3ff0020 	setl \$255,0x20
+      14:	e6ff0400 	incml \$255,0x400
+      18:	e5ff0000 	incmh \$255,0x0
+      1c:	e4ff0000 	inch \$255,0x0
+      20:	9f00ff00 	go \$0,\$255,0
+	\.\.\.
+0+4000020 <a>:
+ 4000020:	e3fd0004 	setl \$253,0x4
+0+4000024 <_start>:
+ 4000024:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs4b.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs4b.d
new file mode 100644
index 0000000..cef68d7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs4b.d
@@ -0,0 +1,35 @@
+#source: start4.s
+#source: nop123.s
+#source: a.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pushja.s
+#source: start.s
+#ld: -m elf64mmix
+#objdump: -dr
+
+# Check that PUSHJ with an offset just outside the offset range of a JMP
+# stub expansion works, backwards, ELF version.
+
+.*:     file format elf64-mmix
+Disassembly of section \.init:
+0+ <_start>:
+   0:	e37704a6 	setl \$119,0x4a6
+Disassembly of section \.text:
+0+4 <a-0x4>:
+       4:	fd010203 	swym 1,2,3
+0+8 <a>:
+       8:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+0+4000000 <pushja>:
+ 4000000:	e3fd0002 	setl \$253,0x2
+ 4000004:	f20c0002 	pushj \$12,400000c <pushja\+0xc>
+ 4000008:	e3fd0003 	setl \$253,0x3
+ 400000c:	e3ff0008 	setl \$255,0x8
+ 4000010:	e6ff0000 	incml \$255,0x0
+ 4000014:	e5ff0000 	incmh \$255,0x0
+ 4000018:	e4ff0000 	inch \$255,0x0
+ 400001c:	9f00ff00 	go \$0,\$255,0
+0+4000020 <_start>:
+ 4000020:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs4bm.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs4bm.d
new file mode 100644
index 0000000..53b74f1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs4bm.d
@@ -0,0 +1,33 @@
+#source: nop123.s
+#source: nop123.s
+#source: a.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pushja.s
+#source: start.s
+#ld: -m mmo
+#objdump: -dr
+
+# Check that PUSHJ with an offset just outside the offset range of a JMP
+# stub expansion works, backwards, mmo version.
+
+.*:     file format mmo
+Disassembly of section \.text:
+0+ <a-0x8>:
+       0:	fd010203 	swym 1,2,3
+       4:	fd010203 	swym 1,2,3
+0+8 <a>:
+       8:	e3fd0004 	setl \$253,0x4
+	\.\.\.
+0+4000000 <pushja>:
+ 4000000:	e3fd0002 	setl \$253,0x2
+ 4000004:	f20c0002 	pushj \$12,400000c <pushja\+0xc>
+ 4000008:	e3fd0003 	setl \$253,0x3
+ 400000c:	e3ff0008 	setl \$255,0x8
+ 4000010:	e6ff0000 	incml \$255,0x0
+ 4000014:	e5ff0000 	incmh \$255,0x0
+ 4000018:	e4ff0000 	inch \$255,0x0
+ 400001c:	9f00ff00 	go \$0,\$255,0
+0+4000020 <Main>:
+ 4000020:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs4m.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs4m.d
new file mode 100644
index 0000000..153e96c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs4m.d
@@ -0,0 +1,33 @@
+#source: nop123.s
+#source: pushja.s
+#source: pad2p26m32.s
+#source: pad16.s
+#source: pad4.s
+#source: pad4.s
+#source: pad4.s
+#source: a.s
+#source: start.s
+#ld: -m mmo
+#objdump: -dr
+
+# Check that PUSHJ with an offset just outside reach of JMP works; it will
+# get the full expansion, mmo version.
+
+.*:     file format mmo
+Disassembly of section \.text:
+0+ <pushja-0x4>:
+       0:	fd010203 	swym 1,2,3
+0+4 <pushja>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f20c0002 	pushj \$12,10 <pushja\+0xc>
+       c:	e3fd0003 	setl \$253,0x3
+      10:	e3ff0020 	setl \$255,0x20
+      14:	e6ff0400 	incml \$255,0x400
+      18:	e5ff0000 	incmh \$255,0x0
+      1c:	e4ff0000 	inch \$255,0x0
+      20:	9f00ff00 	go \$0,\$255,0
+	\.\.\.
+0+4000020 <a>:
+ 4000020:	e3fd0004 	setl \$253,0x4
+0+4000024 <Main>:
+ 4000024:	e3fd0001 	setl \$253,0x1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/pushjs4r.d b/binutils-2.19/ld/testsuite/ld-mmix/pushjs4r.d
new file mode 100644
index 0000000..e734dc6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/pushjs4r.d
@@ -0,0 +1,29 @@
+#source: nop123.s
+#source: pushja.s
+#source: undef-2.s
+#source: pad2p18m32.s
+#source: nop123.s
+#ld: -r -m elf64mmix
+#objdump: -dr
+
+# When linking relocatably, check two stubbable PUSHJ:s, one expanded.
+
+# With better relaxation support for relocatable links, both should be
+# able to pass through unexpanded.  Right now, we just check that they can
+# coexist peacefully.
+
+.*:     file format elf64-mmix
+Disassembly of section \.text:
+0+ <pushja-0x4>:
+       0:	fd010203 	swym 1,2,3
+0+4 <pushja>:
+       4:	e3fd0002 	setl \$253,0x2
+       8:	f20c0002 	pushj \$12,10 <pushja\+0xc>
+       c:	e3fd0003 	setl \$253,0x3
+      10:	f0000000 	jmp 10 <pushja\+0xc>
+			10: R_MMIX_JMP	a
+	\.\.\.
+      24:	f2050000 	pushj \$5,24 <pushja\+0x20>
+			24: R_MMIX_PUSHJ_STUBBABLE	undefd
+	\.\.\.
+   40008:	fd010203 	swym 1,2,3
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/reg-1.d b/binutils-2.19/ld/testsuite/ld-mmix/reg-1.d
new file mode 100644
index 0000000..125fa32
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/reg-1.d
@@ -0,0 +1,7 @@
+#source: areg-256.s
+#source: gregget1.s
+#source: start.s
+#source: a.s
+#as: -x
+#ld: -m elf64mmix
+#error: relocation truncated to fit: R_MMIX_REG against symbol `areg'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/reg-1m.d b/binutils-2.19/ld/testsuite/ld-mmix/reg-1m.d
new file mode 100644
index 0000000..73bdb1a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/reg-1m.d
@@ -0,0 +1,7 @@
+#source: areg-256.s
+#source: gregget1.s
+#source: start.s
+#source: a.s
+#as: -x
+#ld: -m mmo
+#error: relocation truncated to fit: R_MMIX_REG against `areg'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/reg-2.d b/binutils-2.19/ld/testsuite/ld-mmix/reg-2.d
new file mode 100644
index 0000000..09b0da4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/reg-2.d
@@ -0,0 +1,7 @@
+#source: areg-t.s
+#source: gregget1.s
+#source: start.s
+#source: a.s
+#as: -x
+#ld: -m elf64mmix
+#error: register relocation against non-register symbol: areg in \.text
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/reg-2m.d b/binutils-2.19/ld/testsuite/ld-mmix/reg-2m.d
new file mode 100644
index 0000000..f6edbef
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/reg-2m.d
@@ -0,0 +1,7 @@
+#source: areg-t.s
+#source: gregget1.s
+#source: start.s
+#source: a.s
+#as: -x
+#ld: -m mmo
+#error: register relocation against non-register symbol: areg in \.text
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/regext1.s b/binutils-2.19/ld/testsuite/ld-mmix/regext1.s
new file mode 100644
index 0000000..7703905
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/regext1.s
@@ -0,0 +1,2 @@
+ .global ext1
+ext1 IS $252
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-1.d b/binutils-2.19/ld/testsuite/ld-mmix/sec-1.d
new file mode 100644
index 0000000..eab62a2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-1.d
@@ -0,0 +1,35 @@
+#source: sec-1.s
+#source: start.s
+#ld: -m elf64mmix
+#objcopy_linked_file: -O mmo
+#objdump: -sh
+
+# Test conversion from ELF to mmo with non-mmo-sections present,
+# testing that support.
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+4  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 secname       0+19  0+4  0+4  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 \.a\.fourth\.section 0+10  0+20  0+20  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  3 anothersec    0+13  2000000000000000  2000000000000000  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, DATA
+  4 thirdsec      0+a  0+  0+  0+  2\*\*2
+                  CONTENTS, READONLY
+Contents of section \.text:
+ 0000 e3fd0001                             .*
+Contents of section secname:
+ 0004 00000001 00000002 00000003 00000004  .*
+ 0014 ffffffff fffff827 50                 .*
+Contents of section \.a\.fourth\.section:
+ 0020 00000000 0087a238 00000000 302a55a8  .*
+Contents of section anothersec:
+ 2000000000000000 0000000a 00000009 00000008 00000007  .*
+ 2000000000000010 252729                               .*
+Contents of section thirdsec:
+ 0000 00030d41 000186a2 2628               .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-1.s b/binutils-2.19/ld/testsuite/ld-mmix/sec-1.s
new file mode 100644
index 0000000..77e26e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-1.s
@@ -0,0 +1,14 @@
+ .section secname,"ax"
+ TETRA 1,2,3,4,-1,-2009
+ BYTE 80
+
+ .section anothersec,"aw"
+ TETRA 10,9,8,7
+ BYTE 37,39,41
+
+ .section thirdsec
+ TETRA 200001,100002
+ BYTE 38,40
+
+ .section .a.fourth.section,"a"
+ OCTA 8888888,808080808
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-2.d b/binutils-2.19/ld/testsuite/ld-mmix/sec-2.d
new file mode 100644
index 0000000..10623f3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-2.d
@@ -0,0 +1,26 @@
+#source: sec-1.s
+#source: start.s
+#source: data1.s
+#ld: -m mmo -T $srcdir/$subdir/mmosec1.ld
+#objdump: -sh
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+4  0+100  0+100  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 \.other        0+50  1000000000000000  1000000000000000  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE, DATA
+  2 \.data         0+4  2000000000000004  2000000000000004  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD
+Contents of section \.text:
+ 0100 e3fd0001                             .*
+Contents of section \.other:
+ 1000000000000000 00000001 00000002 00000003 00000004  .*
+ 1000000000000010 ffffffff fffff827 50000000 0000000a  .*
+ 1000000000000020 00000009 00000008 00000007 25272900  .*
+ 1000000000000030 00030d41 000186a2 26280000 00000000  .*
+ 1000000000000040 00000000 0087a238 00000000 302a55a8  .*
+Contents of section \.data:
+ 2000000000000004 0000012c                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-2.s b/binutils-2.19/ld/testsuite/ld-mmix/sec-2.s
new file mode 100644
index 0000000..3ac0555
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-2.s
@@ -0,0 +1,2 @@
+ .section .other,"ax"
+ TETRA 12,34,1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-3.d b/binutils-2.19/ld/testsuite/ld-mmix/sec-3.d
new file mode 100644
index 0000000..2469afa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-3.d
@@ -0,0 +1,36 @@
+#source: sec-1.s
+#source: start.s
+#source: data1.s
+#ld: -m mmo
+#objdump: -sh
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+4  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 secname       0+19  0+4  0+4  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 \.a\.fourth\.section 0+10  0+20  0+20  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  3 \.data         0+4  2000000000000004  2000000000000004  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD
+  4 anothersec    0+13  2000000000000008  2000000000000008  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, DATA
+  5 thirdsec      0+a  200000000000001c  200000000000001c  0+  2\*\*2
+                  CONTENTS, READONLY
+Contents of section \.text:
+ 0000 e3fd0001                             .*
+Contents of section secname:
+ 0004 00000001 00000002 00000003 00000004  .*
+ 0014 ffffffff fffff827 50                 .*
+Contents of section \.a\.fourth\.section:
+ 0020 00000000 0087a238 00000000 302a55a8  .*
+Contents of section \.data:
+ 2000000000000004 0000002c                             .*
+Contents of section anothersec:
+ 2000000000000008 0000000a 00000009 00000008 00000007  .*
+ 2000000000000018 252729                               .*
+Contents of section thirdsec:
+ 200000000000001c 00030d41 000186a2 2628               .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-4.d b/binutils-2.19/ld/testsuite/ld-mmix/sec-4.d
new file mode 100644
index 0000000..251f6a2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-4.d
@@ -0,0 +1,22 @@
+#source: sec-2.s
+#source: start.s
+#source: data1.s
+#ld: -m mmo -T $srcdir/$subdir/mmosec1.ld
+#objdump: -sh
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+4  0+100  0+100  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 \.data         0+4  2000000000000004  2000000000000004  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD
+  2 \.other        0+c  1000000000000000  1000000000000000  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+Contents of section \.text:
+ 0100 e3fd0001                             .*
+Contents of section \.data:
+ 2000000000000004 0000012c                             .*
+Contents of section \.other:
+ 1000000000000000 0000000c 00000022 00000001           .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-5.d b/binutils-2.19/ld/testsuite/ld-mmix/sec-5.d
new file mode 100644
index 0000000..24aa0e1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-5.d
@@ -0,0 +1,28 @@
+#source: b-twoinsn.s
+#source: b-offloc.s
+#source: b-post1.s
+#source: b-goodmain.s
+#ld: --oformat binary
+#objdump: -sh
+
+# Check that sections are automatically created to cope with contents at
+# unexpected addresses when an mmo is read in.  We used to do this by
+# e.g. linking .text at an unexpected address, like in sec-9.d.  That no
+# longer works, because .text and .data now gets section descriptors at
+# mmo output when the address and contents doesn't trivially reflect the
+# section contents at link time.  To test, we instead read in an mmo
+# formed from a link to binary format, like the b-*.d tests for mmo
+# execution paths.
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+8  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 \.MMIX\.sec\.0   0+10  789abcdef0123458  789abcdef0123458  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD
+Contents of section \.text:
+ 0+ e3fd0001 e3fd0004                  .*
+Contents of section \.MMIX\.sec\.0:
+ 789abcdef0123458 b045197d 2c1b03b2 e4dbf877 0fc766fb  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-6.d b/binutils-2.19/ld/testsuite/ld-mmix/sec-6.d
new file mode 100644
index 0000000..5b692e2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-6.d
@@ -0,0 +1,37 @@
+#source: start.s
+#source: sec-6.s
+#source: a.s
+#as: -x
+#ld: -m elf64mmix
+#objcopy_linked_file: -O mmo
+#objdump: -xs
+
+# A non-loaded section with relocs would have the SEC_RELOC bit set in the
+# output if we didn't clear it.  For reference, here's the ELF copied to
+# mmo, so we make sure no spurious flags are introduced.
+
+.*:     file format mmo
+.*
+architecture: mmix, flags 0x0+10:
+HAS_SYMS
+start address 0x0+
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+8  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 \.debug_frame  0+10  0+  0+  0+  2\*\*2
+                  CONTENTS, READONLY, DEBUGGING
+SYMBOL TABLE:
+0+ g       \.text Main
+0+ g       \.text _start
+0+8 g       \.text debugb
+2000000000000000 g       \*ABS\* __bss_start
+2000000000000000 g       \*ABS\* _edata
+2000000000000000 g       \*ABS\* _end
+0+4 g       \.text a
+
+Contents of section \.text:
+ 0000 e3fd0001 e3fd0004                    .*
+Contents of section \.debug_frame:
+ 0000 00000000 00000004 00000000 00000008  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-6.s b/binutils-2.19/ld/testsuite/ld-mmix/sec-6.s
new file mode 100644
index 0000000..7d83883
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-6.s
@@ -0,0 +1,5 @@
+ .global debugb
+ .section .debug_frame,"",@progbits
+ .8byte a
+debugb:
+ .8byte debugb
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-6m.d b/binutils-2.19/ld/testsuite/ld-mmix/sec-6m.d
new file mode 100644
index 0000000..8d12cfb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-6m.d
@@ -0,0 +1,32 @@
+#source: start.s
+#source: sec-6.s
+#source: a.s
+#as: -x
+#ld: -m mmo
+#objdump: -xs
+
+# A non-loaded section with relocs would have the SEC_RELOC bit set in the
+# output if we didn't clear it.
+
+.*:     file format mmo
+.*
+architecture: mmix, flags 0x0+10:
+HAS_SYMS
+start address 0x0+
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+8  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 \.debug_frame  0+10  0+  0+  0+  2\*\*2
+                  CONTENTS, READONLY, DEBUGGING
+SYMBOL TABLE:
+0+ g       \.text Main
+0+ g       \.text _start
+0+8 g       \.text debugb
+0+4 g       \.text a
+
+Contents of section \.text:
+ 0000 e3fd0001 e3fd0004                    .*
+Contents of section \.debug_frame:
+ 0000 00000000 00000004 00000000 00000008  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-7a.s b/binutils-2.19/ld/testsuite/ld-mmix/sec-7a.s
new file mode 100644
index 0000000..58cc7ab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-7a.s
@@ -0,0 +1,6 @@
+ .section .di
+ .byte 42
+ .rept 32763
+ .byte 0
+ .endr
+ .byte 43
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-7b.s b/binutils-2.19/ld/testsuite/ld-mmix/sec-7b.s
new file mode 100644
index 0000000..963ca47
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-7b.s
@@ -0,0 +1,6 @@
+ .section .di
+ .byte 44
+ .rept 32764
+ .byte 0
+ .endr
+ .byte 45
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-7c.s b/binutils-2.19/ld/testsuite/ld-mmix/sec-7c.s
new file mode 100644
index 0000000..f6faf85
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-7c.s
@@ -0,0 +1,6 @@
+ .section .di
+ .byte 46
+ .rept 32765
+ .byte 0
+ .endr
+ .byte 47
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-7d.s b/binutils-2.19/ld/testsuite/ld-mmix/sec-7d.s
new file mode 100644
index 0000000..4d73c5f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-7d.s
@@ -0,0 +1,6 @@
+ .section .di
+ .byte 48
+ .rept 32766
+ .byte 0
+ .endr
+ .byte 49
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-7e.s b/binutils-2.19/ld/testsuite/ld-mmix/sec-7e.s
new file mode 100644
index 0000000..2ffde13
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-7e.s
@@ -0,0 +1,6 @@
+ .section .di
+ .byte 50
+ .rept 32767
+ .byte 0
+ .endr
+ .byte 51
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-7m.d b/binutils-2.19/ld/testsuite/ld-mmix/sec-7m.d
new file mode 100644
index 0000000..0bba4f5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-7m.d
@@ -0,0 +1,38 @@
+#source: start.s
+#source: sec-7a.s
+#source: sec-7b.s
+#source: sec-7c.s
+#source: sec-7d.s
+#source: sec-7e.s
+#ld: -m mmo
+#objcopy_linked_file:
+#objdump: -hs
+
+# When producing mmo output: sections with an input length not a
+# multiple of 4, and whose total length in linked output
+# exceeded the "chunk size" (32768), would get to-4-padding
+# inserted at each chunk division.  Also check that section
+# sizes aren't rounded up at objcopy.
+
+.*:     file format mmo
+
+Sections:
+Idx Name[ ]+Size[ ]+VMA[ ]+LMA[ ]+File off  Algn
+  0 \.text[ ]+0+4  0+  0+  0+  2\*\*2
+[ ]+CONTENTS, ALLOC, LOAD, CODE
+  1 \.di +0+27ffb +0+4 +0+4 +0+ +2\*\*2
+[ ]+CONTENTS, READONLY
+Contents of section \.text:
+ 0000 e3fd0001[ ]+.*
+Contents of section \.di:
+ 00004 2a000000 00000000 00000000 00000000  .*
+#...
+ 07ff4 00000000 00000000 00000000 2b2c0000  .*
+#...
+ 0fff4 00000000 00000000 00002d2e 00000000  .*
+#...
+ 17ff4 00000000 00000000 002f3000 00000000  .*
+#...
+ 1fff4 00000000 00000000 00313200 00000000  .*
+#...
+ 27ff4 00000000 00000000 000033[ ]+.*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-8a.s b/binutils-2.19/ld/testsuite/ld-mmix/sec-8a.s
new file mode 100644
index 0000000..4ac94f7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-8a.s
@@ -0,0 +1,4 @@
+ .section .text.1
+ .byte 42
+ .space 32759
+ .byte 43
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-8b.s b/binutils-2.19/ld/testsuite/ld-mmix/sec-8b.s
new file mode 100644
index 0000000..17eb415
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-8b.s
@@ -0,0 +1,4 @@
+ .section .text.1
+ .byte 44
+ .space 32764
+ .byte 45
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-8d.s b/binutils-2.19/ld/testsuite/ld-mmix/sec-8d.s
new file mode 100644
index 0000000..0eb5b56
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-8d.s
@@ -0,0 +1,4 @@
+ .section .text.1
+ .byte 48
+ .space 32766
+ .byte 49
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-8m.d b/binutils-2.19/ld/testsuite/ld-mmix/sec-8m.d
new file mode 100644
index 0000000..fb06b04
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-8m.d
@@ -0,0 +1,30 @@
+#source: start.s
+#source: sec-8a.s
+#source: sec-8b.s
+#source: sec-8m.s
+#source: sec-8d.s
+#ld: -m mmo
+#objdump: -s
+
+# Distantly related to sec-7m.s in that section lengths mattered for the
+# bug.  When one input-section (seen in mmo.c as a chunk of data to
+# output) had a length not a multiple of four, the last bytes were saved
+# to be concatenated with the next chunk.  If it was followed by a chunk
+# with a leading multiple-of-four number of zero bytes, those zero bytes
+# would be omitted, and the "saved" bytes would be concatenated with the
+# following (not-all-zeros) bytes.  Hence a shift of the last bytes of the
+# first chunk.
+
+.*:     file format mmo
+
+Contents of section \.text:
+ 00000 e3fd0001 2a000000 00000000 00000000  .*
+#...
+ 07ff0 00000000 00000000 00000000 2b2c0000  .*
+#...
+ 0fff0 00000000 00000000 00002d00 00000000  .*
+ 10000 00000000 00000000 0000002e 2f303132  .*
+ 10010 33000000 00000000 00000000 00000000  .*
+ 10020 00300000 00000000 00000000 00000000  .*
+#...
+ 18020 31        .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-8m.s b/binutils-2.19/ld/testsuite/ld-mmix/sec-8m.s
new file mode 100644
index 0000000..dc695da
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-8m.s
@@ -0,0 +1,4 @@
+ .section .text.1
+ .byte 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0
+ .byte 46, 47, 48, 49, 50, 51
+ .byte 0,0,0,0, 0,0,0,0, 0,0,0,0, 0,0,0,0
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sec-9.d b/binutils-2.19/ld/testsuite/ld-mmix/sec-9.d
new file mode 100644
index 0000000..4bddc35
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sec-9.d
@@ -0,0 +1,19 @@
+#source: start.s
+#ld: -m mmo -T $srcdir/$subdir/mmosec2.ld
+#objdump: -sh
+
+# This is based on sec-5.d which used to link .text at an unexpected
+# address to check that a special section was created in objdump when
+# reading in contents at an unusual location without a proper section
+# descriptor.  As .text (like .data) now gets a section descriptor when
+# linked to an unexpected location, the old test is transformed into a
+# specific check that the section description for .text works.
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+4  1000000000000000  1000000000000000  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+Contents of section \.text:
+ 1000000000000000 e3fd0001                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/spec801.d b/binutils-2.19/ld/testsuite/ld-mmix/spec801.d
new file mode 100644
index 0000000..27918e9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/spec801.d
@@ -0,0 +1,21 @@
+#source: bspec801.s
+#source: start.s
+#ld: -m mmo
+#objdump: -sh
+
+# Check exceptional cases for LOP_SPEC 80, which we parse according to a
+# specific format: see documentation and mmo.c
+# #1: name length has LOP_QUOTE.
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         00000004  0000000000000000  0000000000000000  00000000  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 \.MMIX\.spec_data\.80 00000004  0000000000000000  0000000000000000  00000000  2\*\*2
+                  CONTENTS
+Contents of section \.text:
+ 0000 e3fd0001                             .*
+Contents of section \.MMIX\.spec_data\.80:
+ 0000 98000001                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/spec802.d b/binutils-2.19/ld/testsuite/ld-mmix/spec802.d
new file mode 100644
index 0000000..ea0ebc3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/spec802.d
@@ -0,0 +1,24 @@
+#source: bspec802.s
+#source: start.s
+#ld: -m mmo
+#objdump: -sh
+
+# See spec801.d.
+# #2: non-quote LOP in name.
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+4  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 \.data         0+4  2000000000000000  2000000000000000  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD
+  2 \.MMIX\.spec_data\.80 0+4  0+  0+  0+  2\*\*2
+                  CONTENTS
+Contents of section \.text:
+ 0000 e3fd0001                             .*
+Contents of section \.data:
+ 2000000000000000 00112233                             .*
+Contents of section \.MMIX\.spec_data\.80:
+ 0000 00000004                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/spec803.d b/binutils-2.19/ld/testsuite/ld-mmix/spec803.d
new file mode 100644
index 0000000..b933d6c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/spec803.d
@@ -0,0 +1,24 @@
+#source: bspec803.s
+#source: start.s
+#ld: -m mmo
+#objdump: -sh
+
+# See spec801.d.
+# #3: LOP_QUOTE in name and non-quote LOP in section flags.
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+4  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 \.data         0+4  2000000000000000  2000000000000000  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD
+  2 \.MMIX\.spec_data\.80 0+c  0+  0+  0+  2\*\*2
+                  CONTENTS
+Contents of section \.text:
+ 0000 e3fd0001                             .*
+Contents of section \.data:
+ 2000000000000000 00112233                             .*
+Contents of section \.MMIX\.spec_data\.80:
+ 0000 00000002 61616161 98616161           .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/spec804.d b/binutils-2.19/ld/testsuite/ld-mmix/spec804.d
new file mode 100644
index 0000000..170bc5e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/spec804.d
@@ -0,0 +1,24 @@
+#source: bspec804.s
+#source: start.s
+#ld: -m mmo
+#objdump: -sh
+
+# See spec801.d.
+# #4: non-quote LOP in section length, high part.
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+4  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 \.data         0+4  2000000000000000  2000000000000000  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD
+  2 \.MMIX\.spec_data\.80 0+10  0+  0+  0+  2\*\*2
+                  CONTENTS
+Contents of section \.text:
+ 0000 e3fd0001                             .*
+Contents of section \.data:
+ 2000000000000000 00112233                             .*
+Contents of section \.MMIX\.spec_data\.80:
+ 0000 00000002 61616161 61616161 00000011  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/spec805.d b/binutils-2.19/ld/testsuite/ld-mmix/spec805.d
new file mode 100644
index 0000000..c4cdd02
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/spec805.d
@@ -0,0 +1,25 @@
+#source: bspec805.s
+#source: start.s
+#ld: -m mmo
+#objdump: -sh
+
+# See spec801.d.
+# #5: non-quote LOP in section length, low part.
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+4  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 \.data         0+4  2000000000000000  2000000000000000  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD
+  2 \.MMIX\.spec_data\.80 0+14  0+  0+  0+  2\*\*2
+                  CONTENTS
+Contents of section \.text:
+ 0000 e3fd0001                             .*
+Contents of section \.data:
+ 2000000000000000 00112233                             .*
+Contents of section \.MMIX\.spec_data\.80:
+ 0000 00000002 61616161 61616161 00000011  .*
+ 0010 00000000                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/spec806.d b/binutils-2.19/ld/testsuite/ld-mmix/spec806.d
new file mode 100644
index 0000000..7f64948
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/spec806.d
@@ -0,0 +1,25 @@
+#source: bspec806.s
+#source: start.s
+#ld: -m mmo
+#objdump: -sh
+
+# See spec801.d.
+# #6: non-quote LOP in section vma, high part.
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+4  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 \.data         0+4  2000000000000000  2000000000000000  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD
+  2 \.MMIX\.spec_data\.80 0+18  0+  0+  0+  2\*\*2
+                  CONTENTS
+Contents of section \.text:
+ 0000 e3fd0001                             .*
+Contents of section \.data:
+ 2000000000000000 00112233                             .*
+Contents of section \.MMIX\.spec_data\.80:
+ 0000 00000002 61616161 61616161 00000011  .*
+ 0010 00000000 0000000c                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/spec807.d b/binutils-2.19/ld/testsuite/ld-mmix/spec807.d
new file mode 100644
index 0000000..f37e57a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/spec807.d
@@ -0,0 +1,25 @@
+#source: bspec807.s
+#source: start.s
+#ld: -m mmo
+#objdump: -sh
+
+# See spec801.d.
+# #7: non-quote LOP in section vma, low part.
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+4  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 \.data         0+4  2000000000000000  2000000000000000  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD
+  2 \.MMIX\.spec_data\.80 0+1c  0+  0+  0+  2\*\*2
+                  CONTENTS
+Contents of section \.text:
+ 0000 e3fd0001                             .*
+Contents of section \.data:
+ 2000000000000000 00112233                             .*
+Contents of section \.MMIX\.spec_data\.80:
+ 0000 00000002 61616161 61616161 00000011  .*
+ 0010 00000000 0000000c 00000000           .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/spec808.d b/binutils-2.19/ld/testsuite/ld-mmix/spec808.d
new file mode 100644
index 0000000..e1d6784
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/spec808.d
@@ -0,0 +1,25 @@
+#source: bspec808.s
+#source: start.s
+#ld: -m mmo
+#objdump: -sh
+
+# See spec801.d.
+# #8: Indecent section length.
+
+.*:     file format mmo
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+4  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+  1 \.data         0+4  2000000000000000  2000000000000000  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD
+  2 \.MMIX\.spec_data\.80 0+20  0+  0+  0+  2\*\*2
+                  CONTENTS
+Contents of section \.text:
+ 0000 e3fd0001                             .*
+Contents of section \.data:
+ 2000000000000000 00112233                             .*
+Contents of section \.MMIX\.spec_data\.80:
+ 0000 00000002 61616161 61616161 00000011  .*
+ 0010 0000ff00 00000000 000000ff 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/start-1.d b/binutils-2.19/ld/testsuite/ld-mmix/start-1.d
new file mode 100644
index 0000000..37c23d6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/start-1.d
@@ -0,0 +1,21 @@
+#source: start2.s
+#ld: -m elf64mmix
+#objdump: -td
+
+.*:     file format elf64-mmix
+
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|\.text)
+0+4 g       \.text	0+ _start
+2000000000000000 g       \*ABS\*	0+ __bss_start
+2000000000000000 g       \*ABS\*	0+ _edata
+2000000000000000 g       \*ABS\*	0+ _end
+0+4 g       \.text	0+ _start\.
+
+Disassembly of section \.text:
+
+0+ <_start-0x4>:
+   0:	fd000001 	swym 0,0,1
+
+0+4 <_start>:
+   4:	fd000002 	swym 0,0,2
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/start-2.d b/binutils-2.19/ld/testsuite/ld-mmix/start-2.d
new file mode 100644
index 0000000..e380dc0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/start-2.d
@@ -0,0 +1,4 @@
+#source: main1.s
+#source: a.s
+#ld: -m mmo -e a
+#error: Bad symbol definition: `Main' set to
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/start.s b/binutils-2.19/ld/testsuite/ld-mmix/start.s
new file mode 100644
index 0000000..b2e3c85
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/start.s
@@ -0,0 +1,5 @@
+* Just a start symbol and some non-NOP padding.
+ .text
+ .global _start
+_start:
+ SET $253,1
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/start2.s b/binutils-2.19/ld/testsuite/ld-mmix/start2.s
new file mode 100644
index 0000000..3398788
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/start2.s
@@ -0,0 +1,5 @@
+ .text
+ SWYM 1
+ .global _start
+_start:
+ SWYM 2
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/start3.s b/binutils-2.19/ld/testsuite/ld-mmix/start3.s
new file mode 100644
index 0000000..1055870
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/start3.s
@@ -0,0 +1,7 @@
+# When GC, all sections in each file must be referenced from within a kept
+# section.
+ .section .init,"ax",@progbits
+_start:
+ .quad x+41
+ .quad x2+42
+
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/start4.s b/binutils-2.19/ld/testsuite/ld-mmix/start4.s
new file mode 100644
index 0000000..4948d78
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/start4.s
@@ -0,0 +1,6 @@
+# When GC, all sections in each file must be referenced from within a kept
+# section (which .init is, which .text isn't).  Here, we don't refer to
+# anything so whatever is linked will be discarded.
+ .section .init,"ax",@progbits
+_start:
+ SETL $119,1190
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sym-1.d b/binutils-2.19/ld/testsuite/ld-mmix/sym-1.d
new file mode 100644
index 0000000..64d6376
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sym-1.d
@@ -0,0 +1,11 @@
+#source: start.s
+#source: a.s
+#ld: -m mmo
+#nm: -n
+
+# Test that nm can grok a simple mmo symbol table (or that mmo lets nm
+# grok it).
+
+0+ T Main
+0+ T _start
+0+4 T a
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sym-2.d b/binutils-2.19/ld/testsuite/ld-mmix/sym-2.d
new file mode 100644
index 0000000..61bae32
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sym-2.d
@@ -0,0 +1,142 @@
+#source: start.s
+#source: sym-2.s
+#source: a.s
+#as: -globalize-symbols
+#ld: -m mmo
+#objcopy_linked_file:
+#objdump: -t
+
+.*:     file format mmo
+
+SYMBOL TABLE:
+0+ g[ 	]+\.text Main
+0+4 g[ 	]+\.text a40
+0+4 g[ 	]+\.text a33
+0+4 g[ 	]+\.text a45
+0+4 g[ 	]+\.text a21
+0+4 g[ 	]+\.text a99
+0+4 g[ 	]+\.text a114
+0+4 g[ 	]+\.text a122
+0+4 g[ 	]+\.text a73
+0+4 g[ 	]+\.text a111
+0+4 g[ 	]+\.text a109
+0+4 g[ 	]+\.text a65
+0+4 g[ 	]+\.text a28
+0+4 g[ 	]+\.text a30
+0+4 g[ 	]+\.text a10
+0+4 g[ 	]+\.text a103
+0+4 g[ 	]+\.text a42
+0+4 g[ 	]+\.text a62
+0+4 g[ 	]+\.text a25
+0+4 g[ 	]+\.text a128
+0+4 g[ 	]+\.text a9
+0+4 g[ 	]+\.text a11
+0+4 g[ 	]+\.text a81
+0+4 g[ 	]+\.text a55
+0+4 g[ 	]+\.text a88
+0+4 g[ 	]+\.text a100
+0+4 g[ 	]+\.text a104
+0+4 g[ 	]+\.text a8
+0+4 g[ 	]+\.text a86
+0+4 g[ 	]+\.text a91
+0+4 g[ 	]+\.text a1
+0+4 g[ 	]+\.text a49
+0+4 g[ 	]+\.text a43
+0+4 g[ 	]+\.text a56
+0+4 g[ 	]+\.text a116
+0+4 g[ 	]+\.text a124
+0+4 g[ 	]+\.text a98
+0+4 g[ 	]+\.text a117
+0+4 g[ 	]+\.text a80
+0+4 g[ 	]+\.text a121
+0+4 g[ 	]+\.text a36
+0+4 g[ 	]+\.text a75
+0+4 g[ 	]+\.text a48
+0+4 g[ 	]+\.text a3
+0+4 g[ 	]+\.text a63
+0+4 g[ 	]+\.text a26
+0+4 g[ 	]+\.text a78
+0+4 g[ 	]+\.text a61
+0+4 g[ 	]+\.text a24
+0+4 g[ 	]+\.text a64
+0+4 g[ 	]+\.text a27
+0+4 g[ 	]+\.text a83
+0+4 g[ 	]+\.text a57
+0+4 g[ 	]+\.text a123
+0+4 g[ 	]+\.text a34
+0+4 g[ 	]+\.text a12
+0+4 g[ 	]+\.text a14
+0+4 g[ 	]+\.text a70
+0+4 g[ 	]+\.text a39
+0+4 g[ 	]+\.text a82
+0+4 g[ 	]+\.text a102
+0+4 g[ 	]+\.text a106
+0+4 g[ 	]+\.text a110
+0+ g[ 	]+\.text _start
+0+4 g[ 	]+\.text a41
+0+4 g[ 	]+\.text a85
+0+4 g[ 	]+\.text a58
+0+4 g[ 	]+\.text a89
+0+4 g[ 	]+\.text a54
+0+4 g[ 	]+\.text a19
+0+4 g[ 	]+\.text a93
+0+4 g[ 	]+\.text a126
+0+4 g[ 	]+\.text a22
+0+4 g[ 	]+\.text a96
+0+4 g[ 	]+\.text a7
+0+4 g[ 	]+\.text a35
+0+4 g[ 	]+\.text a31
+0+4 g[ 	]+\.text a5
+0+4 g[ 	]+\.text a44
+0+4 g[ 	]+\.text a105
+0+4 g[ 	]+\.text a90
+0+4 g[ 	]+\.text a97
+0+4 g[ 	]+\.text a92
+0+4 g[ 	]+\.text a2
+0+4 g[ 	]+\.text a120
+0+4 g[ 	]+\.text a113
+0+4 g[ 	]+\.text a77
+0+4 g[ 	]+\.text a125
+0+4 g[ 	]+\.text a118
+0+4 g[ 	]+\.text a32
+0+4 g[ 	]+\.text a108
+0+4 g[ 	]+\.text a47
+0+4 g[ 	]+\.text a112
+0+4 g[ 	]+\.text a59
+0+4 g[ 	]+\.text a87
+0+4 g[ 	]+\.text a94
+0+4 g[ 	]+\.text a20
+0+4 g[ 	]+\.text a51
+0+4 g[ 	]+\.text a16
+0+4 g[ 	]+\.text a53
+0+4 g[ 	]+\.text a18
+0+4 g[ 	]+\.text a66
+0+4 g[ 	]+\.text a29
+0+4 g[ 	]+\.text a72
+0+4 g[ 	]+\.text a79
+0+4 g[ 	]+\.text a74
+0+4 g[ 	]+\.text a68
+0+4 g[ 	]+\.text a95
+0+4 g[ 	]+\.text a60
+0+4 g[ 	]+\.text a23
+0+4 g[ 	]+\.text a67
+0+4 g[ 	]+\.text a
+0+4 g[ 	]+\.text a38
+0+4 g[ 	]+\.text a107
+0+4 g[ 	]+\.text a127
+0+4 g[ 	]+\.text a101
+0+4 g[ 	]+\.text a115
+0+4 g[ 	]+\.text a71
+0+4 g[ 	]+\.text a84
+0+4 g[ 	]+\.text a69
+0+4 g[ 	]+\.text a37
+0+4 g[ 	]+\.text a76
+0+4 g[ 	]+\.text a52
+0+4 g[ 	]+\.text a17
+0+4 g[ 	]+\.text a13
+0+4 g[ 	]+\.text a50
+0+4 g[ 	]+\.text a15
+0+4 g[ 	]+\.text a119
+0+4 g[ 	]+\.text a6
+0+4 g[ 	]+\.text a46
+0+4 g[ 	]+\.text a4
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/sym-2.s b/binutils-2.19/ld/testsuite/ld-mmix/sym-2.s
new file mode 100644
index 0000000..c8df27e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/sym-2.s
@@ -0,0 +1,130 @@
+% Just 128 symbols to test that we can handle it in mmo.  Assemble it with
+% -globalize-symbols.
+a1:
+a2:
+a3:
+a4:
+a5:
+a6:
+a7:
+a8:
+a9:
+a10:
+a11:
+a12:
+a13:
+a14:
+a15:
+a16:
+a17:
+a18:
+a19:
+a20:
+a21:
+a22:
+a23:
+a24:
+a25:
+a26:
+a27:
+a28:
+a29:
+a30:
+a31:
+a32:
+a33:
+a34:
+a35:
+a36:
+a37:
+a38:
+a39:
+a40:
+a41:
+a42:
+a43:
+a44:
+a45:
+a46:
+a47:
+a48:
+a49:
+a50:
+a51:
+a52:
+a53:
+a54:
+a55:
+a56:
+a57:
+a58:
+a59:
+a60:
+a61:
+a62:
+a63:
+a64:
+a65:
+a66:
+a67:
+a68:
+a69:
+a70:
+a71:
+a72:
+a73:
+a74:
+a75:
+a76:
+a77:
+a78:
+a79:
+a80:
+a81:
+a82:
+a83:
+a84:
+a85:
+a86:
+a87:
+a88:
+a89:
+a90:
+a91:
+a92:
+a93:
+a94:
+a95:
+a96:
+a97:
+a98:
+a99:
+a100:
+a101:
+a102:
+a103:
+a104:
+a105:
+a106:
+a107:
+a108:
+a109:
+a110:
+a111:
+a112:
+a113:
+a114:
+a115:
+a116:
+a117:
+a118:
+a119:
+a120:
+a121:
+a122:
+a123:
+a124:
+a125:
+a126:
+a127:
+a128:
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/undef-1.d b/binutils-2.19/ld/testsuite/ld-mmix/undef-1.d
new file mode 100644
index 0000000..fb8c7ee
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/undef-1.d
@@ -0,0 +1,4 @@
+#source: undef-1.s
+#source: start.s
+#ld: -m elf64mmix
+#error: undefined reference to `regvar'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/undef-1.s b/binutils-2.19/ld/testsuite/ld-mmix/undef-1.s
new file mode 100644
index 0000000..668cd15
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/undef-1.s
@@ -0,0 +1 @@
+ ADDU regvar,$8,$9
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/undef-1m.d b/binutils-2.19/ld/testsuite/ld-mmix/undef-1m.d
new file mode 100644
index 0000000..001d7f6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/undef-1m.d
@@ -0,0 +1,4 @@
+#source: undef-1.s
+#source: start.s
+#ld: -m mmo
+#error: undefined reference to `regvar'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/undef-2.d b/binutils-2.19/ld/testsuite/ld-mmix/undef-2.d
new file mode 100644
index 0000000..52844db
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/undef-2.d
@@ -0,0 +1,5 @@
+#source: undef-2.s
+#source: start.s
+#as: -x
+#ld: -m elf64mmix
+#error: undefined reference to `undefd'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/undef-2.s b/binutils-2.19/ld/testsuite/ld-mmix/undef-2.s
new file mode 100644
index 0000000..d912b15
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/undef-2.s
@@ -0,0 +1 @@
+ PUSHJ $5,undefd
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/undef-2m.d b/binutils-2.19/ld/testsuite/ld-mmix/undef-2m.d
new file mode 100644
index 0000000..aa0becc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/undef-2m.d
@@ -0,0 +1,5 @@
+#source: undef-2.s
+#source: start.s
+#as: -x
+#ld: -m mmo
+#error: undefined reference to `undefd'
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/undef-3.d b/binutils-2.19/ld/testsuite/ld-mmix/undef-3.d
new file mode 100644
index 0000000..5b3ce98
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/undef-3.d
@@ -0,0 +1,34 @@
+#source: start.s
+#ld: -u undefd -m elf64mmix
+#readelf: -S -s
+
+There are 5 section headers, starting at offset 0xa0:
+
+Section Headers:
+  \[Nr\] Name              Type             Address           Offset
+       Size              EntSize          Flags  Link  Info  Align
+  \[ 0\]                   NULL             0+  0+
+       0+  0+           0     0     0
+  \[ 1\] \.text             PROGBITS         0+  0+78
+       0+4  0+  AX       0     0     4
+  \[ 2\] \.shstrtab         STRTAB           0+  0+7c
+       0+21  0+           0     0     1
+  \[ 3\] \.symtab           SYMTAB           0+  0+1e0
+       0+c0  0+18           4     2     8
+  \[ 4\] \.strtab           STRTAB           0+  0+2a0
+       0+2f  0+           0     0     1
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+Symbol table '\.symtab' contains 8 entries:
+   Num:    Value          Size Type    Bind   Vis      Ndx Name
+     0: 0+     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 0+     0 SECTION LOCAL  DEFAULT    1 
+     2: 0+     0 NOTYPE  GLOBAL DEFAULT  UND undefd
+     3: 0+     0 NOTYPE  GLOBAL DEFAULT    1 _start
+     4: 2000000000000000     0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+     5: 2000000000000000     0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+     6: 2000000000000000     0 NOTYPE  GLOBAL DEFAULT  ABS _end
+     7: 0+     0 NOTYPE  GLOBAL DEFAULT    1 _start\.
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/undef-3m.d b/binutils-2.19/ld/testsuite/ld-mmix/undef-3m.d
new file mode 100644
index 0000000..08e1df1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/undef-3m.d
@@ -0,0 +1,18 @@
+#source: start.s
+#ld: -m mmo -u undefd
+#objdump: -x
+
+.*:     file format mmo
+.*
+architecture: mmix, flags 0x0+10:
+HAS_SYMS
+start address 0x0+
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+4  0+  0+  0+  2\*\*2
+                  CONTENTS, ALLOC, LOAD, CODE
+SYMBOL TABLE:
+0+ g       \.text Main
+0+ g       \*UND\* undefd
+0+ g       \.text _start
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/x.s b/binutils-2.19/ld/testsuite/ld-mmix/x.s
new file mode 100644
index 0000000..faf4073
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/x.s
@@ -0,0 +1,26 @@
+;# Main file, x.s, with the program (_start) referring to two
+;# linkonce functions fn and fn2.  The functions fn and fn2 are
+;# supposed to be equivalent of C++ template instantiations; the
+;# main file instantiates fn.  There's the equivalent of an FDE
+;# entry in .eh_frame, referring to fn via a local label.
+
+ .text
+ .global _start
+_start:
+ .long fn
+ .long fn2
+
+ .section .gnu.linkonce.t.fn,"ax",@progbits
+ .weak fn
+ .type fn,@function
+fn:
+L:a:
+ .long 1
+ .long 2
+L:b:
+ .size fn,L:b-L:a
+
+ .section .eh_frame,"aw",@progbits
+ .long 2
+ .long L:a
+ .long L:b-L:a
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/y.s b/binutils-2.19/ld/testsuite/ld-mmix/y.s
new file mode 100644
index 0000000..fcfcd35
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/y.s
@@ -0,0 +1,33 @@
+;# Library file y.s has linkonce entries for fn and fn2.  Note
+;# that this version of fn has different code, as if compiled
+;# with different optimization flags than the one in x.s (not
+;# important for this test, though).  The reference from
+;# .eh_frame to the linkonce-excluded fn2 must be zero, or g++
+;# EH will not work.
+
+ .section .gnu.linkonce.t.fn2,"ax",@progbits
+ .weak fn2
+ .type fn2,@function
+fn2:
+L:c:
+ .long 3
+L:d:
+ .size fn2,L:d-L:c
+
+ .section .gnu.linkonce.t.fn,"ax",@progbits
+ .weak fn
+ .type fn,@function
+fn:
+L:e:
+ .long 4
+L:f:
+ .size fn,L:f-L:e
+
+ .section .eh_frame,"aw",@progbits
+ .long 7
+ .long L:c
+ .long L:d-L:c
+
+ .long 0x6066
+ .long L:e
+ .long L:f-L:e
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/zeroeh.ld b/binutils-2.19/ld/testsuite/ld-mmix/zeroeh.ld
new file mode 100644
index 0000000..6550c17
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/zeroeh.ld
@@ -0,0 +1,4 @@
+SECTIONS {
+ .text 0xa00 : { *(.text); *(.gnu.linkonce.t.*) }
+ .eh_frame 0x2000 : { *(.eh_frame) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/zeroehelf.d b/binutils-2.19/ld/testsuite/ld-mmix/zeroehelf.d
new file mode 100644
index 0000000..ba17314
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/zeroehelf.d
@@ -0,0 +1,17 @@
+#source: x.s
+#source: y.s
+#ld: -m elf64mmix -Ttext 0xa00 -T $srcdir/$subdir/zeroeh.ld
+#objdump: -s
+
+# The word at address 201c, for the linkonce-excluded section, must be zero.
+
+.*:     file format elf64-mmix
+
+Contents of section \.text:
+ 0a00 00000a08 00000a10 00000001 00000002  .*
+ 0a10 00000003                             .*
+Contents of section \.eh_frame:
+ 2000 00000002 00000a08 00000008 00000007  .*
+ 2010 00000a10 00000004 00006066 00000000  .*
+ 2020 00000004                             .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mmix/zeroehmmo.d b/binutils-2.19/ld/testsuite/ld-mmix/zeroehmmo.d
new file mode 100644
index 0000000..2c47ff1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mmix/zeroehmmo.d
@@ -0,0 +1,16 @@
+#source: x.s
+#source: y.s
+#ld: -m mmo -Ttext 0xa00 -T $srcdir/$subdir/zeroeh.ld
+#objdump: -s
+
+# The word at address 201c, for the linkonce-excluded section, must be zero.
+
+.*:     file format mmo
+
+Contents of section \.text:
+ 0a00 00000a08 00000a10 00000001 00000002  .*
+ 0a10 00000003                             .*
+Contents of section \.eh_frame:
+ 2000 00000002 00000a08 00000008 00000007  .*
+ 2010 00000a10 00000004 00006066 00000000  .*
+ 2020 00000004                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i112045-1.d b/binutils-2.19/ld/testsuite/ld-mn10300/i112045-1.d
new file mode 100644
index 0000000..dcb5a41
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i112045-1.d
@@ -0,0 +1,22 @@
+
+tmpdir/i112045-1.x:     file format elf32-.*
+
+Disassembly of section .text:
+
+0+0 <_start>:
+   0:	fc d0 f8 0f[ 	]+add	4088,a0
+   4:	00 00 
+   6:	cb[ 	]+nop[ 	]+
+   7:	cb[ 	]+nop[ 	]+
+
+0+08 <L01>:
+   8:	fc d0 2b 01[ 	]+add	299,a0
+   c:	00 00 
+   e:	cb[ 	]+nop[ 	]+
+   f:	cb[ 	]+nop[ 	]+
+
+0+010 <L02>:
+  10:	fc d0 08 00[ 	]+add	8,a0
+  14:	00 00 
+  16:	cb[ 	]+nop[ 	]+
+  17:	cb[ 	]+nop[ 	]+
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i112045-1.s b/binutils-2.19/ld/testsuite/ld-mn10300/i112045-1.s
new file mode 100644
index 0000000..b9e0346
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i112045-1.s
@@ -0,0 +1,14 @@
+	.text
+	.global _start
+_start:
+	add     0x1000 - L01, A0
+	nop
+	nop
+L01:
+	add     L01 + 0x123, A0
+	nop
+	nop
+L02:
+	add     L02 - L01, A0
+	nop
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i112045-2.d b/binutils-2.19/ld/testsuite/ld-mn10300/i112045-2.d
new file mode 100644
index 0000000..9aa2d82
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i112045-2.d
@@ -0,0 +1,6 @@
+
+tmpdir/i112045-2.x:     file format elf32-.*
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+[0-9a-f]+ R_MN10300_RELATIVE  \*ABS\*\+0x[0-9a-f]+
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i112045-2.s b/binutils-2.19/ld/testsuite/ld-mn10300/i112045-2.s
new file mode 100644
index 0000000..90e942d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i112045-2.s
@@ -0,0 +1,12 @@
+	.section .data
+L01:
+	.long   L04 - L01
+L02:
+	.long   L04 - L02
+L03:
+	.long   L04 - L03
+L04:
+	.long   L04
+        .long   L00
+        .equ    L00, 0xff
+
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i112045-3.d b/binutils-2.19/ld/testsuite/ld-mn10300/i112045-3.d
new file mode 100644
index 0000000..c4b2f4b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i112045-3.d
@@ -0,0 +1,17 @@
+
+tmpdir/i112045-3.x:     file format elf32-.*
+
+Disassembly of section .text:
+
+0+0100 <L001>:
+ 100:[ 	]+24 00 01[ 	]+mov[ 	]+256,a0
+
+0+0103 <L002>:
+ 103:[ 	]+24 00 01[ 	]+mov[ 	]+256,a0
+Disassembly of section .rodata:
+
+0+0106 <L004>:
+ 106:[ 	]+06 00 00[ 	]+movbu[ 	]+d1,\(0 <L001-0x100>\)
+ 109:[ 	]+00[ 	]+clr[ 	]+d0
+ 10a:[ 	]+03 00 00[ 	]+movhu[ 	]+d0,\(0 <L001-0x100>\)
+[ 	]+...
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i112045-3.s b/binutils-2.19/ld/testsuite/ld-mn10300/i112045-3.s
new file mode 100644
index 0000000..b372a77
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i112045-3.s
@@ -0,0 +1,11 @@
+       .text
+L001:
+        mov     L001,A0
+L002:
+        mov     L001,A0
+L003:
+
+        .section        .rodata
+L004:
+        .long   L003-L001
+        .long   L003-L002
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i126256-1.c b/binutils-2.19/ld/testsuite/ld-mn10300/i126256-1.c
new file mode 100644
index 0000000..5907d87
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i126256-1.c
@@ -0,0 +1,7 @@
+void
+sub0 (int i)
+{
+  extern int sub (int);
+
+  sub (i);
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i126256-2.c b/binutils-2.19/ld/testsuite/ld-mn10300/i126256-2.c
new file mode 100644
index 0000000..2948e5b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i126256-2.c
@@ -0,0 +1,5 @@
+int
+sub (int i)
+{
+  return i + 10;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i127740.d b/binutils-2.19/ld/testsuite/ld-mn10300/i127740.d
new file mode 100644
index 0000000..456a75b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i127740.d
@@ -0,0 +1,17 @@
+
+tmpdir/i127740.x:     file format elf32-.*
+
+Disassembly of section .text:
+
+0+0100 <_main>:
+ 100:	2d 00 03[ 	]+mov	768,d1
+ 103:	cb[ 	]+nop	
+ 104:	cb[ 	]+nop	
+ 105:	cb[ 	]+nop	
+	...
+
+0+0200 <_dummy>:
+ 200:	00[ 	]+clr	d0
+ 201:	02 00 00[ 	]+movbu	d0,\(0 <_main-0x100>\)
+ 204:	df 00 00[ 	]+ret	\[\],0
+	...
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i127740.s b/binutils-2.19/ld/testsuite/ld-mn10300/i127740.s
new file mode 100644
index 0000000..358266b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i127740.s
@@ -0,0 +1,12 @@
+      .section .text
+       .global _main
+       .global _dummy
+_main:
+       mov     _g_label,d1     # instruction is changed by relaxations
+
+       .balign 0x100
+_dummy:
+       .long     _dummy
+       ret [],0
+       .size   _main, .-_main
+       .comm   _g_label,4,4
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i135409-1.d b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-1.d
new file mode 100644
index 0000000..2d64a42
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-1.d
@@ -0,0 +1,11 @@
+
+Symbol table '.symtab' contains .. entries:
+   Num:    Value  Size Type    Bind   Vis      Ndx Name
+#...
+    ..: 0[0-9a-f]+[ 	]+7 FUNC    LOCAL  DEFAULT    . _func
+#...
+    ..: 0[0-9a-f]+[ 	]+0 NOTYPE  LOCAL  DEFAULT    . A
+    ..: 0[0-9a-f]+[ 	]+7 FUNC    GLOBAL DEFAULT    . _func2
+#...
+    ..: 0[0-9a-f]+[ 	]+0 NOTYPE  GLOBAL DEFAULT    . BOTTOM
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i135409-1.s b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-1.s
new file mode 100644
index 0000000..b9faaf4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-1.s
@@ -0,0 +1,29 @@
+       .text
+
+       nop
+
+        .global _start
+_start:
+        .type   _func, @function
+_func:
+        mov     L001,A1
+        nop
+A:
+        mov     L001,A1
+        .size   _func, . - _func
+
+
+        .global _func2
+_func2:
+        .type   _func2, @function
+        mov     L001,A1
+        nop
+        mov     L001,A1
+        .size   _func2, . - _func2
+
+        .global BOTTOM
+BOTTOM:
+	
+        .data
+L001:
+
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i135409-2.d b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-2.d
new file mode 100644
index 0000000..59c07e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-2.d
@@ -0,0 +1,11 @@
+
+Symbol table '.symtab' contains .. entries:
+   Num:    Value  Size Type    Bind   Vis      Ndx Name
+#...
+    ..: 0[0-9a-f]+02[ 	]+0 NOTYPE  LOCAL  DEFAULT    . _A
+    ..: 0[0-9a-f]+08[ 	]+0 NOTYPE  LOCAL  DEFAULT    . _B
+    ..: 0[0-9a-f]+08[ 	]+0 NOTYPE  LOCAL  DEFAULT    . _C
+    ..: 0[0-9a-f]+10[ 	]+7 FUNC    LOCAL  DEFAULT    . _func
+    ..: 0[0-9a-f]+14[ 	]+0 NOTYPE  LOCAL  DEFAULT    . _D
+    ..: 0[0-9a-f]+17[ 	]+0 NOTYPE  LOCAL  DEFAULT    . BOTTOM
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i135409-2.s b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-2.s
new file mode 100644
index 0000000..36448ed
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-2.s
@@ -0,0 +1,23 @@
+     .text
+      .global _start
+_start:
+      add     A0, A1
+_A:
+      mov     L001, A0
+_B:
+      .balign 0x8
+_C:
+      nop
+      .balign 0x10
+
+       .type   _func, @function
+_func:
+       mov     L001, A1
+       nop
+_D:
+       mov     L001, A1
+BOTTOM:
+       .size   _func, . - _func
+
+      .data
+L001:
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i135409-3.d b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-3.d
new file mode 100644
index 0000000..1ea91ba
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-3.d
@@ -0,0 +1,16 @@
+
+tmpdir/i135409-3.x:     file format elf32-.*
+
+Disassembly of section .text:
+
+0+0 <_func>:
+   0:	25 1f 00[ 	]+mov	31,a1
+   3:	cb[ 	]+nop	
+
+0+04 <A>:
+   4:	25 1f 00[ 	]+mov	31,a1
+   7:	cb[ 	]+nop	
+
+0+08 <BOTTOM>:
+   8:	e1[ 	]+add	d0,d1
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i135409-3.s b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-3.s
new file mode 100644
index 0000000..e83ad96
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-3.s
@@ -0,0 +1,16 @@
+      .text
+      .global _start
+_start:
+      .type   _func, @function
+_func:
+      mov     L001,A1
+      nop
+A:
+      mov     L001,A1
+BOTTOM:
+      .balign 0x8
+      add     D0,D1
+      .size   _func, .-func
+
+      .data
+L001:
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i135409-4.d b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-4.d
new file mode 100644
index 0000000..f14ea7d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-4.d
@@ -0,0 +1,7 @@
+
+tmpdir/i135409-4.x:     file format elf32-.*
+
+Disassembly of section .text:
+
+0+0 <_start>:
+   0:[ 	]+cc 00 07[ 	]+jmp[ 	]+700 \<L001\>
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i135409-4.s b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-4.s
new file mode 100644
index 0000000..90badde
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-4.s
@@ -0,0 +1,8 @@
+	.text
+        .global _start
+_start:
+        jmp     L001
+
+        .section        .text1
+L001:
+        nop
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i135409-4.t b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-4.t
new file mode 100644
index 0000000..9d905cb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-4.t
@@ -0,0 +1,23 @@
+SECTIONS
+{
+        . = 0x0;
+        .text :
+        {
+                *(.text)
+        }
+
+        . = 0x700;
+        .text1 :
+        {
+                *(.text1)
+        }
+        . = 0x8100;
+        .bss :
+        {
+                *(.bss)
+        }
+        .data :
+        {
+                *(.data)
+        }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i135409-5.d b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-5.d
new file mode 100644
index 0000000..dbff701
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-5.d
@@ -0,0 +1,7 @@
+
+tmpdir/i135409-5.x:     file format elf32-.*
+
+Disassembly of section .text:
+
+0+0700 <_start>:
+ 700:[ 	]+cc 00 f9[ 	]+jmp[ 	]+0 \<L001\>
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i135409-5.s b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-5.s
new file mode 100644
index 0000000..23897e8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-5.s
@@ -0,0 +1,8 @@
+	.text
+       .global _start
+_start:
+       jmp     L001
+
+       .section        .text1
+L001:
+       nop
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i135409-5.t b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-5.t
new file mode 100644
index 0000000..8b42814
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i135409-5.t
@@ -0,0 +1,23 @@
+SECTIONS
+{
+       . = 0x0;
+       .text1 :
+       {
+               *(.text1)
+       }
+
+       . = 0x700;
+       .text :
+       {
+               *(.text)
+       }
+       . = 0x8100;
+       .bss :
+       {
+               *(.bss)
+       }
+       .data :
+       {
+               *(.data)
+       }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i143317.d b/binutils-2.19/ld/testsuite/ld-mn10300/i143317.d
new file mode 100644
index 0000000..ace2831
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i143317.d
@@ -0,0 +1,8 @@
+
+tmpdir/i143317.x:     file format elf32-.*
+
+Disassembly of section .text:
+
+0+100c <.text>:
+[ 	]+100c:[ 	]+fa 02 fe 7f[ 	]+mov[ 	]+\(32766,a2\),d0
+[ 	]+1010:[ 	]+fa 06 fe 7f[ 	]+mov[ 	]+\(32766,a2\),d1
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i143317.s b/binutils-2.19/ld/testsuite/ld-mn10300/i143317.s
new file mode 100644
index 0000000..abcc896
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i143317.s
@@ -0,0 +1,36 @@
+.section .rodata.str1.1 ,"aMS",@progbits,0x1
+_start:
+.string "abcdefgh"
+L001:
+.string "hogehoge"
+L002:
+.string "fooooooo"
+L003:
+
+.text
+.align  0x02
+mov (L001@GOTOFF,A2),D0
+mov (L004@GOTOFF,A2),D1
+
+
+.section .rodata.str1.1 ,"aMS",@progbits,0x1
+L006:
+.string ""
+.string ""
+.string ""
+.string "%"
+.string ""
+.string ""
+.string "s"
+.string ""
+L005:
+.string ""
+.string ""
+.string ""
+.string "%"
+.string ""
+.string ""
+.string "r"
+.string ""
+L004:
+.string "hogehoge"
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i143317.t b/binutils-2.19/ld/testsuite/ld-mn10300/i143317.t
new file mode 100644
index 0000000..47d9262
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i143317.t
@@ -0,0 +1,31 @@
+SECTIONS
+{
+.bss :
+{
+*(.bss)
+end = .;
+}
+. = 0x1000;
+.got : { *(.got.plt) *(.got) }
+.text :
+{
+*(.text)
+}
+. = 0x8ff5;
+.rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) }
+.data :
+{
+*(.data)
+}
+edata = .;
+.stac :
+{
+*(.stack)
+}
+.plt  :  { *(.plt) }
+.rela.plt : { *(.rela.plt) }
+.rela.dyn :
+{
+*(.rela.text)
+}
+}
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i36434-2.s b/binutils-2.19/ld/testsuite/ld-mn10300/i36434-2.s
new file mode 100644
index 0000000..cf31ce1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i36434-2.s
@@ -0,0 +1,16 @@
+	.section .text
+	.global _bar
+	.type	_bar,@function
+_bar:
+	mov	.LC1,d0
+	mov	.LC2,d1
+	nop
+
+	.section	.rodata.str1.1,"aMS",@progbits,1
+.LC1:
+	.rept	32768
+	.byte	'a'
+	.endr
+	.byte	0
+.LC2:
+	.string	"abc\n"
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i36434.d b/binutils-2.19/ld/testsuite/ld-mn10300/i36434.d
new file mode 100644
index 0000000..af37b3b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i36434.d
@@ -0,0 +1,16 @@
+
+tmpdir/i36434.x:     file format elf32-.*
+
+Disassembly of section .text:
+
+08000074 <_start>:
+ 8000074:	fc cd 8c 80 	mov	134250636,d1
+ 8000078:	00 08 
+ 800007a:	cb          	nop	
+
+0800007b <_bar>:
+ 800007b:	fc cc 88 00 	mov	134217864,d0
+ 800007f:	00 08 
+ 8000081:	fc cd 89 80 	mov	134250633,d1
+ 8000085:	00 08 
+ 8000087:	cb          	nop	
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/i36434.s b/binutils-2.19/ld/testsuite/ld-mn10300/i36434.s
new file mode 100644
index 0000000..84c1d83
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/i36434.s
@@ -0,0 +1,10 @@
+	.section .text
+	.global _start
+	.type	_start,@function
+_start:
+	mov	.LC2,d1
+	nop
+
+	.section	.rodata.str1.1,"aMS",@progbits,1
+.LC2:
+	.string	"\n"
diff --git a/binutils-2.19/ld/testsuite/ld-mn10300/mn10300.exp b/binutils-2.19/ld/testsuite/ld-mn10300/mn10300.exp
new file mode 100644
index 0000000..617ad8a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-mn10300/mn10300.exp
@@ -0,0 +1,163 @@
+# Expect script for ld-mn10300 tests
+#   Copyright (C) 2007 Free Software Foundation
+#
+# This file is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+
+if {!([istarget "am3*-*-*"]) && !([istarget "mn10300*-*-*"]) } {
+    return
+}
+
+# Set up a list as described in ld-lib.exp
+
+set mn10300_tests {
+    {
+	"am33 string merging"
+	"-relax -Ttext 0x8000074"
+	""
+	{ "i36434.s" "i36434-2.s" }
+	{ {objdump -dz i36434.d} }
+	"i36434.x"
+    }
+    {
+	"difference of two same-section symbols"
+	"-Ttext 0"
+	""
+	{ "i112045-1.s" }
+	{ {objdump -d i112045-1.d} }
+	"i112045-1.x"
+    }
+    {
+	"difference of two same-section symbols where the difference is held in another section"
+	"-relax -Ttext 100"
+	""
+	{ "i112045-3.s" }
+	{ {objdump -D i112045-3.d} }
+	"i112045-3.x"
+    }
+    {
+	"relaxation and alignment directives"
+	"-relax -Ttext 100 -Tbss 300"
+	""
+	{ "i127740.s" }
+	{ {objdump -d i127740.d} }
+	"i127740.x"
+    }
+    {
+	"adjustment of symbols due to relaxation"
+	"-Tdata 1f -Ttext 0 -relax"
+	""
+	{ "i135409-1.s" }
+	{ {readelf --syms i135409-1.d} }
+	"i135409-1.x"
+    }
+    {
+	"adjustment of symbols due to relaxation (with alignment directives)"
+	"-Tdata 1f -Ttext 0 -relax"
+	""
+	{ "i135409-2.s" }
+	{ {readelf --syms i135409-2.d} }
+	"i135409-2.x"
+    }
+    {
+	"adjustment of symbols due to relaxation (with a symbol in the deleted region)"
+	"-Tdata 1f -Ttext 0 -relax"
+	""
+	{ "i135409-3.s" }
+	{ {objdump -d i135409-3.d} }
+	"i135409-3.x"
+    }
+    {
+	"adjusting a 16-bit forward branch"
+	"-Ti135409-4.t -relax"
+	""
+	{ "i135409-4.s" }
+	{ {objdump -d i135409-4.d} }
+	"i135409-4.x"
+    }
+    {
+	"adjusting a 16-bit backward branch"
+	"-Ti135409-5.t -relax"
+	""
+	{ "i135409-5.s" }
+	{ {objdump -d i135409-5.d} }
+	"i135409-5.x"
+    }
+    {
+	"relaxing offsets into a merged string section"
+	"-Ti143317.t -shared -relax"
+	""
+	{ "i143317.s" }
+	{ {objdump -d i143317.d} }
+	"i143317.x"
+    }
+}
+
+run_ld_link_tests $mn10300_tests
+
+if {!([istarget "am3*-*-*"])} {
+    return
+}
+
+set am33_tests {
+    {
+	"difference of two same-section symbols (in a shared library)"
+	"-shared"
+	""
+	{ "i112045-2.s" }
+	{ {objdump -R i112045-2.d} }
+	"i112045-2.x"
+    }
+}
+
+run_ld_link_tests $am33_tests
+
+proc i126256-test { } {
+    global CC
+    global ld
+    global srcdir
+    global subdir
+
+    set tmpdir tmpdir
+    set testname "Seg fault whilst linking one shared library into another when relaxation is enabled."
+
+    if {![is_remote host] && [which $CC] == 0} then {
+	return
+    }
+
+    if { ![ld_compile "$CC -mrelax -fPIC" $srcdir/$subdir/i126256-1.c $tmpdir/i126256-1.o] } {
+	unresolved $testname
+    	return
+    }
+
+    if { ![ld_compile "$CC -mrelax -fPIC" $srcdir/$subdir/i126256-2.c $tmpdir/i126256-2.o] } {
+	unresolved $testname
+    	return
+    }
+    
+    if { ![ld_simple_link $ld $tmpdir/i126256-1.so "-shared $tmpdir/i126256-1.o -e 0"]} {
+        unresolved $testname
+    	return
+    }
+
+    if { ![ld_simple_link $ld $tmpdir/i126256-2.so "--relax -shared $tmpdir/i126256-2.o $tmpdir/i126256-1.so -e 0"]} {
+        fail $testname
+    	return
+    }
+
+    pass $testname
+}
+
+i126256-test
diff --git a/binutils-2.19/ld/testsuite/ld-pe/direct.exp b/binutils-2.19/ld/testsuite/ld-pe/direct.exp
new file mode 100644
index 0000000..2af2bf7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pe/direct.exp
@@ -0,0 +1,146 @@
+# Expect script for direct linking from dll tests
+#   Copyright 2006, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Pedro Alves <pedro_alves@portugalmail.pt>
+#
+ 
+# Note:
+# 
+# This test checks the "direct linking to a dll" functionality.
+# 
+# The test has 7 stages:
+# 
+# 1. compile and link a test dll with ".dll" extension.
+#
+# 2. compile and link a test dll with ".sl" (i.e. != ".dll") extension.
+#
+# 3. compile and link a client application linking directly to the ".dll" dll built in 1.
+#    This should produce no errors.
+#
+# 4. compile and link a client application linking directly to the ".sl" dll built in 2.
+#    This should produce no errors.
+#
+# 5. compile and link a client application linking directly to a symlink into 
+#    the ".dll" dll built in 1.
+#    This should produce no errors.
+#
+# 6. compile and link a client application linking directly to a symlink into 
+#    the ".sl" dll built in 1.
+#    This should produce no errors.
+#
+# 7. run the produced executables
+
+# This test can only be run on PE/COFF platforms.
+if {    ![istarget *-*-cygwin*]
+     && ![istarget *-*-mingw*]
+     && ![istarget *-*-pe] } {
+    return
+}
+
+# No compiler, no test.
+if { [which $CC] == 0 } {
+    untested "Direct linking to dll test"
+    return
+}
+
+set tmpdir tmpdir
+
+proc test_direct_link_dll {} {
+    global CC
+    global CFLAGS
+    global srcdir
+    global subdir
+    global tmpdir
+    
+    # Compile the dll.
+    if ![ld_compile "$CC $CFLAGS" $srcdir/$subdir/direct_dll.c $tmpdir/direct_dll.o ] {
+	fail "compiling shared lib"
+    } elseif ![ld_simple_link "$CC -shared" $tmpdir/direct_dll.dll "$tmpdir/direct_dll.o" ] {
+	fail "linking shared lib (.dll)"
+    } elseif ![ld_simple_link "$CC -shared" $tmpdir/direct_dll.sl "$tmpdir/direct_dll.o" ] {
+	fail "linking shared lib (.sl)"
+    } else {
+	# Compile and link the client program.
+	if ![ld_compile "$CC $CFLAGS" $srcdir/$subdir/direct_client.c $tmpdir/direct_client.o ] {
+	    fail "compiling client"
+	} else {
+	    # Check linking directly to direct_dll.dll.
+	    set msg "linking client (.dll)"
+	    if [ld_simple_link $CC $tmpdir/direct_client_dll.exe "$tmpdir/direct_client.o $tmpdir/direct_dll.dll" ] {
+		pass $msg
+	    } else {
+		fail $msg 
+	    }
+
+	    # Check linking directly to direct_dll.sl.
+	    set msg "linking client (.sl)"
+	    if [ld_simple_link $CC $tmpdir/direct_client_sl.exe "$tmpdir/direct_client.o $tmpdir/direct_dll.sl" ] {
+		pass $msg
+	    } else {
+		fail $msg 
+	    }
+
+	    # Check dll direct linking through symlink to .dll.
+	    # Create symbolic link.
+	    catch "exec ln -fs direct_dll.dll $tmpdir/libdirect_dll.dll.a" ln_catch
+	    set msg "linking client (symlink -> .dll)"
+	    if [ld_simple_link $CC $tmpdir/direct_client_symlink_dll.exe "$tmpdir/direct_client.o $tmpdir/libdirect_dll.dll.a" ] {
+	        pass $msg
+	    } else {
+		fail $msg
+	    }
+		
+	    # Check dll direct linking through symlink to .sl.
+	    # Create symbolic link.
+	    catch "exec ln -fs direct_dll.sl $tmpdir/libdirect_sl.dll.a" ln_catch
+	    set msg "linking client (symlink -> .sl)"
+	    if [ld_simple_link $CC $tmpdir/direct_client_symlink_sl.exe "$tmpdir/direct_client.o $tmpdir/libdirect_sl.dll.a" ] {
+		pass $msg
+	    } else {
+		fail $msg 
+	    }
+	}
+    }
+}
+
+proc directdll_execute {exe msg} {
+    set expected ""
+    catch "exec $exe" prog_output
+    if [string match $expected $prog_output] then {
+        pass $msg
+    } else {
+        verbose $prog_output
+        fail $msg
+    }
+}
+
+test_direct_link_dll
+
+# This is as far as we can go with a cross-compiler
+if ![isnative] then {
+    verbose "Not running natively, so cannot execute binaries"
+    return
+}
+
+directdll_execute "$tmpdir/direct_client_dll.exe" "running direct linked dll (.dll)"
+directdll_execute "$tmpdir/direct_client_sl.exe" "running direct linked dll (.sl)"
+directdll_execute "$tmpdir/direct_client_symlink_sl.exe" "running direct linked dll (symlink -> .sl)"
+directdll_execute "$tmpdir/direct_client_symlink_dll.exe" "running direct linked dll (symlink -> .dll)"
diff --git a/binutils-2.19/ld/testsuite/ld-pe/direct_client.c b/binutils-2.19/ld/testsuite/ld-pe/direct_client.c
new file mode 100644
index 0000000..6264a78
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pe/direct_client.c
@@ -0,0 +1,8 @@
+__declspec(dllimport) int dll_func (void);
+
+int
+main()
+{
+  dll_func ();
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-pe/direct_dll.c b/binutils-2.19/ld/testsuite/ld-pe/direct_dll.c
new file mode 100644
index 0000000..9863d1a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pe/direct_dll.c
@@ -0,0 +1,5 @@
+__declspec(dllexport) int
+dll_func (void)
+{
+  return 10;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-pe/image_size.d b/binutils-2.19/ld/testsuite/ld-pe/image_size.d
new file mode 100644
index 0000000..6d41fcc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pe/image_size.d
@@ -0,0 +1,9 @@
+#name: PE-COFF SizeOfImage
+#ld: -T image_size.t
+#objdump: -p
+#target: i*86-*-mingw32
+
+.*:     file format .*
+#...
+SizeOfImage		00004000
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-pe/image_size.s b/binutils-2.19/ld/testsuite/ld-pe/image_size.s
new file mode 100644
index 0000000..3b56d7f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pe/image_size.s
@@ -0,0 +1,8 @@
+	.text
+	.global _start
+_start:
+	.byte 1
+	.global data
+	.data
+data:
+	.byte 2
diff --git a/binutils-2.19/ld/testsuite/ld-pe/image_size.t b/binutils-2.19/ld/testsuite/ld-pe/image_size.t
new file mode 100644
index 0000000..f646eca
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pe/image_size.t
@@ -0,0 +1,15 @@
+SECTIONS
+{
+  . = SIZEOF_HEADERS;
+  . = ALIGN(__section_alignment__);
+  .text  __image_base__ + ( __section_alignment__ < 0x1000 ? . : __section_alignment__ ) :
+  {
+    *(.text)
+  }
+  . = . + 0x1000;
+  .data BLOCK(__section_alignment__) :
+  {
+    *(.data)
+  }
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-pe/pe.exp b/binutils-2.19/ld/testsuite/ld-pe/pe.exp
new file mode 100644
index 0000000..12b330d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pe/pe.exp
@@ -0,0 +1,46 @@
+# Expect script for export table in executables tests

+#   Copyright 2004, 2006, 2007

+#   Free Software Foundation, Inc.

+#

+# This file is part of the GNU Binutils.

+#

+# This program is free software; you can redistribute it and/or modify

+# it under the terms of the GNU General Public License as published by

+# the Free Software Foundation; either version 3 of the License, or

+# (at your option) any later version.

+#

+# This program is distributed in the hope that it will be useful,

+# but WITHOUT ANY WARRANTY; without even the implied warranty of

+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

+# GNU General Public License for more details.

+#

+# You should have received a copy of the GNU General Public License

+# along with this program; if not, write to the Free Software

+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,

+# MA 02110-1301, USA.

+#

+ 

+# This test can only be run on PE/COFF platforms that support .secrel32.

+if {    ![istarget i*86-*-cygwin*]

+     && ![istarget i*86-*-pe]

+     && ![istarget i*86-*-mingw*]

+     && ![istarget x86_64-*-mingw*]

+     && ![istarget arm-wince-pe] } {

+    return

+}

+

+if {[istarget x86_64-*-mingw*] } {

+  set pe_tests {

+    {".secrel32" "" "" {secrel1.s secrel2.s}

+    {{objdump -s secrel_64.d}} "secrel.x"}

+  }

+} else {

+  set pe_tests {

+    {".secrel32" "" "" {secrel1.s secrel2.s}

+     {{objdump -s secrel.d}} "secrel.x"}

+  }

+}

+

+run_ld_link_tests $pe_tests

+

+run_dump_test "image_size"

diff --git a/binutils-2.19/ld/testsuite/ld-pe/secrel.d b/binutils-2.19/ld/testsuite/ld-pe/secrel.d
new file mode 100644
index 0000000..b924f54
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pe/secrel.d
@@ -0,0 +1,27 @@
+

+tmpdir/secrel\.x: +file format pei-.*

+

+Contents of section \.text:

+ .*1000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c  >>>><<<<>>>>><<<

+ .*1010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c  >>>>>><<>>>>>>><

+ .*1020 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c  >>>><<<<>>>>><<<

+ .*1030 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c  >>>>>><<>>>>>>><

+ .*1040 ........ ........ ........ ........  ................

+Contents of section \.data:

+ .*2000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c  >>>><<<<>>>>><<<

+ .*2010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c  >>>>>><<>>>>>>><

+ .*2020 3e3e3e3e 04000000 110d0000 00111600  >>>>............

+ .*2030 0000111f 00000011 3c3c3c3c 3c3c3c3c  ........<<<<<<<<

+ .*2040 3e3e3e3e 04000000 110d0000 00111600  >>>>............

+ .*2050 0000111f 00000011 3c3c3c3c 3c3c3c3c  ........<<<<<<<<

+ .*2060 3e3e3e3e 04000000 110d0000 00111600  >>>>............

+ .*2070 0000111f 00000011 3c3c3c3c 3c3c3c3c  ........<<<<<<<<

+ .*2080 3e3e3e3e 24000000 112d0000 00113600  >>>>\$....-....6.

+ .*2090 0000113f 00000011 3c3c3c3c 3c3c3c3c  ...\?....<<<<<<<<

+Contents of section \.rdata:

+ .*3000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c  >>>><<<<>>>>><<<

+ .*3010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c  >>>>>><<>>>>>>><

+ .*3020 3e3e3e3e 00000000 00000000 00000000  >>>>............

+Contents of section \.idata:

+ .*4000 00000000 00000000 00000000 00000000  ................

+ .*4010 00000000                             ....            

diff --git a/binutils-2.19/ld/testsuite/ld-pe/secrel1.s b/binutils-2.19/ld/testsuite/ld-pe/secrel1.s
new file mode 100644
index 0000000..c162990
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pe/secrel1.s
@@ -0,0 +1,79 @@
+.text

+

+	.ascii ">>>>"

+pre04:	.ascii "<<<<"

+	.ascii ">>>>>"

+pre0d:	.ascii "<<<"

+	.ascii ">>>>>>"

+pre16:	.ascii "<<"

+	.ascii ">>>>>>>"

+pre1f:	.ascii "<"

+

+.data

+

+	.ascii ">>>>"

+sam04:	.ascii "<<<<"

+	.ascii ">>>>>"

+sam0d:	.ascii "<<<"

+	.ascii ">>>>>>"

+sam16:	.ascii "<<"

+	.ascii ">>>>>>>"

+sam1f:	.ascii "<"

+

+	.ascii ">>>>"

+	.secrel32 pre04

+	.byte 0x11

+	.secrel32 pre0d

+	.byte 0x11

+	.secrel32 pre16

+	.byte 0x11

+	.secrel32 pre1f

+	.byte 0x11

+	.ascii "<<<<<<<<"

+

+	.ascii ">>>>"

+	.secrel32 sam04

+	.byte 0x11

+	.secrel32 sam0d

+	.byte 0x11

+	.secrel32 sam16

+	.byte 0x11

+	.secrel32 sam1f

+	.byte 0x11

+	.ascii "<<<<<<<<"

+

+	.ascii ">>>>"

+	.secrel32 nex04

+	.byte 0x11

+	.secrel32 nex0d

+	.byte 0x11

+	.secrel32 nex16

+	.byte 0x11

+	.secrel32 nex1f

+	.byte 0x11

+	.ascii "<<<<<<<<"

+

+	.ascii ">>>>"

+	.secrel32 ext24

+	.byte 0x11

+	.secrel32 ext2d

+	.byte 0x11

+	.secrel32 ext36

+	.byte 0x11

+	.secrel32 ext3f

+	.byte 0x11

+	.ascii "<<<<<<<<"

+

+.section .rdata

+

+	.ascii ">>>>"

+nex04:	.ascii "<<<<"

+	.ascii ">>>>>"

+nex0d:	.ascii "<<<"

+	.ascii ">>>>>>"

+nex16:	.ascii "<<"

+	.ascii ">>>>>>>"

+nex1f:	.ascii "<"

+	.ascii ">>>>"

+

+	.p2align 4,0

diff --git a/binutils-2.19/ld/testsuite/ld-pe/secrel2.s b/binutils-2.19/ld/testsuite/ld-pe/secrel2.s
new file mode 100644
index 0000000..a1f871f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pe/secrel2.s
@@ -0,0 +1,14 @@
+.text

+

+	.ascii ">>>>"

+.global ext24

+ext24:	.ascii "<<<<"

+	.ascii ">>>>>"

+.global ext2d

+ext2d:	.ascii "<<<"

+	.ascii ">>>>>>"

+.global ext36

+ext36:	.ascii "<<"

+	.ascii ">>>>>>>"

+.global ext3f

+ext3f:	.ascii "<"

diff --git a/binutils-2.19/ld/testsuite/ld-pe/secrel_64.d b/binutils-2.19/ld/testsuite/ld-pe/secrel_64.d
new file mode 100644
index 0000000..aba1bf1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pe/secrel_64.d
@@ -0,0 +1,28 @@
+

+tmpdir/secrel\.x: +file format pei-.*

+

+Contents of section \.text:

+ .*1000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c  >>>><<<<>>>>><<<

+ .*1010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c  >>>>>><<>>>>>>><

+ .*1020 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c  >>>><<<<>>>>><<<

+ .*1030 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c  >>>>>><<>>>>>>><

+ .*1040 ffffffff ffffffff 00000000 00000000  ................

+ .*1050 ffffffff ffffffff 00000000 00000000  ................

+Contents of section \.data:

+ .*2000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c  >>>><<<<>>>>><<<

+ .*2010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c  >>>>>><<>>>>>>><

+ .*2020 3e3e3e3e 04000000 110d0000 00111600  >>>>............

+ .*2030 0000111f 00000011 3c3c3c3c 3c3c3c3c  ........<<<<<<<<

+ .*2040 3e3e3e3e 04000000 110d0000 00111600  >>>>............

+ .*2050 0000111f 00000011 3c3c3c3c 3c3c3c3c  ........<<<<<<<<

+ .*2060 3e3e3e3e 04000000 110d0000 00111600  >>>>............

+ .*2070 0000111f 00000011 3c3c3c3c 3c3c3c3c  ........<<<<<<<<

+ .*2080 3e3e3e3e 24000000 112d0000 00113600  >>>>\$....-....6.

+ .*2090 0000113f 00000011 3c3c3c3c 3c3c3c3c  ...\?....<<<<<<<<

+Contents of section \.rdata:

+ .*3000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c  >>>><<<<>>>>><<<

+ .*3010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c  >>>>>><<>>>>>>><

+ .*3020 3e3e3e3e 00000000 00000000 00000000  >>>>............

+Contents of section \.idata:

+ .*4000 00000000 00000000 00000000 00000000  ................

+ .*4010 00000000                             ....            

diff --git a/binutils-2.19/ld/testsuite/ld-pie/pie.c b/binutils-2.19/ld/testsuite/ld-pie/pie.c
new file mode 100644
index 0000000..a9bce4a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pie/pie.c
@@ -0,0 +1,5 @@
+int
+main ()
+{
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-pie/pie.exp b/binutils-2.19/ld/testsuite/ld-pie/pie.exp
new file mode 100644
index 0000000..064d9cd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pie/pie.exp
@@ -0,0 +1,43 @@
+# Expect script for various PIE tests.
+#   Copyright 2006, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# This test can only be run if ld generates native executables.
+if ![isnative] then {return}
+
+# Run on Linux only.
+if { ![istarget *-*-linux*] } {
+    return
+}
+
+# Check if -pie is supported or not.
+send_log "$CC -pie $srcdir/$subdir/pie.c -o tmpdir/pie"
+catch "exec $CC -pie $srcdir/$subdir/pie.c -o tmpdir/pie" exec_output
+send_log "$exec_output\n"
+if { ![string match "" $exec_output] } {
+    return
+}
+
+set array_tests {
+    {"weak undefined" "-pie" "" {weakundef.c} "weakundef" "weakundef.out" "-fPIC"}
+    {"weak undefined data" "-pie" "" {weakundef-data.c} "weakundef-data" "weakundef.out" "-fPIC"}
+}
+
+run_ld_link_exec_tests [] $array_tests
diff --git a/binutils-2.19/ld/testsuite/ld-pie/weakundef-data.c b/binutils-2.19/ld/testsuite/ld-pie/weakundef-data.c
new file mode 100644
index 0000000..af411bc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pie/weakundef-data.c
@@ -0,0 +1,15 @@
+#include <stdio.h>
+
+#pragma weak undef_data
+
+extern int undef_data;
+int *ptr_to_data = &undef_data;
+
+int
+main (void)
+{
+  if (ptr_to_data == NULL)
+    printf ("PASSED\n");
+
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-pie/weakundef.c b/binutils-2.19/ld/testsuite/ld-pie/weakundef.c
new file mode 100644
index 0000000..c206781
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pie/weakundef.c
@@ -0,0 +1,15 @@
+#include <stdio.h>
+
+#pragma weak undef_func
+
+extern int undef_func (void);
+int (*ptr_to_func)(void) = undef_func;
+
+int
+main (void)
+{
+  if (ptr_to_func == NULL)
+    printf ("PASSED\n");
+
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-pie/weakundef.out b/binutils-2.19/ld/testsuite/ld-pie/weakundef.out
new file mode 100644
index 0000000..53cdf1e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-pie/weakundef.out
@@ -0,0 +1 @@
+PASSED
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/apuinfo.rd b/binutils-2.19/ld/testsuite/ld-powerpc/apuinfo.rd
new file mode 100644
index 0000000..e6321cd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/apuinfo.rd
@@ -0,0 +1,10 @@
+#source: apuinfo1.s
+#source: apuinfo2.s
+#as: -me500
+#readelf: -x2
+#target: powerpc-eabi*
+
+Hex dump of section '.PPC.EMB.apuinfo':
+  0x00000000 00000008 0000001c 00000002 41505569 ............APUi
+  0x00000010 6e666f00 00420001 00430001 00410001 nfo..B...C...A..
+  0x00000020 01020001 01010001 00400001 01000001 .........@......
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/apuinfo1.s b/binutils-2.19/ld/testsuite/ld-powerpc/apuinfo1.s
new file mode 100644
index 0000000..fd42eac
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/apuinfo1.s
@@ -0,0 +1,9 @@
+	.text
+	.global apuinfo1
+apuinfo1:	
+	evstdd 29,8(1)
+	isellt 29, 28, 27
+	efsabs 29, 28
+	.global _start
+_start:
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/apuinfo2.s b/binutils-2.19/ld/testsuite/ld-powerpc/apuinfo2.s
new file mode 100644
index 0000000..7f4e7bb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/apuinfo2.s
@@ -0,0 +1,8 @@
+	.text
+	.global apuinfo2
+apuinfo2:	
+	evstdd 29,8(1)
+	mfbbear 29
+	mfpmr   29, 27
+	dcbtstls 1, 29, 28
+	rfmci
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-0.s b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-0.s
new file mode 100644
index 0000000..a143746
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-0.s
@@ -0,0 +1 @@
+.gnu_attribute 4,0
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-00.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-00.d
new file mode 100644
index 0000000..a4751a1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-00.d
@@ -0,0 +1,7 @@
+#source: attr-gnu-4-0.s
+#source: attr-gnu-4-0.s
+#as: -a32
+#ld: -r -melf32ppc
+#readelf: -A
+#target: powerpc*-*-*
+
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-01.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-01.d
new file mode 100644
index 0000000..212e0c4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-01.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-0.s
+#source: attr-gnu-4-1.s
+#as: -a32
+#ld: -r -melf32ppc
+#readelf: -A
+#target: powerpc*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_Power_ABI_FP: Hard float
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-02.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-02.d
new file mode 100644
index 0000000..9bd42b5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-02.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-0.s
+#source: attr-gnu-4-2.s
+#as: -a32
+#ld: -r -melf32ppc
+#readelf: -A
+#target: powerpc*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_Power_ABI_FP: Soft float
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-03.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-03.d
new file mode 100644
index 0000000..03b0c3c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-03.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-0.s
+#source: attr-gnu-4-3.s
+#as: -a32
+#ld: -r -melf32ppc
+#readelf: -A
+#target: powerpc*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_Power_ABI_FP: Single-precision hard float
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-1.s b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-1.s
new file mode 100644
index 0000000..e985a56
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-1.s
@@ -0,0 +1 @@
+.gnu_attribute 4,1
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-10.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-10.d
new file mode 100644
index 0000000..93297c2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-10.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-1.s
+#source: attr-gnu-4-0.s
+#as: -a32
+#ld: -r -melf32ppc
+#readelf: -A
+#target: powerpc*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_Power_ABI_FP: Hard float
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-11.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-11.d
new file mode 100644
index 0000000..fb2b76e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-11.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-1.s
+#source: attr-gnu-4-1.s
+#as: -a32
+#ld: -r -melf32ppc
+#readelf: -A
+#target: powerpc*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_Power_ABI_FP: Hard float
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-12.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-12.d
new file mode 100644
index 0000000..b7ffba0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-12.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-1.s
+#source: attr-gnu-4-2.s
+#as: -a32
+#ld: -r -melf32ppc
+#warning: Warning: .* uses hard float, .* uses soft float
+#target: powerpc*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-13.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-13.d
new file mode 100644
index 0000000..6bc3de4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-13.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-1.s
+#source: attr-gnu-4-3.s
+#as: -a32
+#ld: -r -melf32ppc
+#warning: Warning: .* uses double-precision hard float, .* uses single-precision hard float
+#target: powerpc*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-14.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-14.d
new file mode 100644
index 0000000..3bb6661
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-14.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-1.s
+#source: attr-gnu-4-4.s
+#as: -a32
+#ld: -r -melf32ppc
+#warning: Warning: .* uses unknown floating point ABI 4
+#target: powerpc*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-2.s b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-2.s
new file mode 100644
index 0000000..54ebf4e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-2.s
@@ -0,0 +1 @@
+.gnu_attribute 4,2
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-20.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-20.d
new file mode 100644
index 0000000..3d83893
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-20.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-2.s
+#source: attr-gnu-4-0.s
+#as: -a32
+#ld: -r -melf32ppc
+#readelf: -A
+#target: powerpc*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_Power_ABI_FP: Soft float
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-21.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-21.d
new file mode 100644
index 0000000..b38f248
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-21.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-2.s
+#source: attr-gnu-4-1.s
+#as: -a32
+#ld: -r -melf32ppc
+#warning: Warning: .* uses hard float, .* uses soft float
+#target: powerpc*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-22.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-22.d
new file mode 100644
index 0000000..f6bd198
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-22.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-2.s
+#source: attr-gnu-4-2.s
+#as: -a32
+#ld: -r -melf32ppc
+#readelf: -A
+#target: powerpc*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_Power_ABI_FP: Soft float
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-23.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-23.d
new file mode 100644
index 0000000..f72c258
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-23.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-2.s
+#source: attr-gnu-4-3.s
+#as: -a32
+#ld: -r -melf32ppc
+#warning: Warning: .* uses hard float, .* uses soft float
+#target: powerpc*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-24.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-24.d
new file mode 100644
index 0000000..fc17f91
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-24.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-2.s
+#source: attr-gnu-4-4.s
+#as: -a32
+#ld: -r -melf32ppc
+#warning: Warning: .* uses unknown floating point ABI 4
+#target: powerpc*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-3.s b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-3.s
new file mode 100644
index 0000000..32e5f5d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-3.s
@@ -0,0 +1 @@
+.gnu_attribute 4,3
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-31.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-31.d
new file mode 100644
index 0000000..8ee1874
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-31.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-3.s
+#source: attr-gnu-4-1.s
+#as: -a32
+#ld: -r -melf32ppc
+#warning: Warning: .* uses double-precision hard float, .* uses single-precision hard float
+#target: powerpc*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-32.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-32.d
new file mode 100644
index 0000000..3b7cb29
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-32.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-3.s
+#source: attr-gnu-4-2.s
+#as: -a32
+#ld: -r -melf32ppc
+#warning: Warning: .* uses soft float, .* uses single-precision hard float
+#target: powerpc*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-33.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-33.d
new file mode 100644
index 0000000..88367ae
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-33.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-4-3.s
+#source: attr-gnu-4-3.s
+#as: -a32
+#ld: -r -melf32ppc
+#readelf: -A
+#target: powerpc*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_Power_ABI_FP: Single-precision hard float
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-34.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-34.d
new file mode 100644
index 0000000..6f6e1fe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-34.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-3.s
+#source: attr-gnu-4-4.s
+#as: -a32
+#ld: -r -melf32ppc
+#warning: Warning: .* uses unknown floating point ABI 4
+#target: powerpc*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-4.s b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-4.s
new file mode 100644
index 0000000..3ff129a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-4.s
@@ -0,0 +1 @@
+.gnu_attribute 4,4
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-41.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-41.d
new file mode 100644
index 0000000..b909476
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-4-41.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-4-4.s
+#source: attr-gnu-4-1.s
+#as: -a32
+#ld: -r -melf32ppc
+#warning: Warning: .* uses unknown floating point ABI 4
+#target: powerpc*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-1.s b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-1.s
new file mode 100644
index 0000000..81c7b7f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-1.s
@@ -0,0 +1 @@
+.gnu_attribute 8,1
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-11.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-11.d
new file mode 100644
index 0000000..7e49d4a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-11.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-8-1.s
+#source: attr-gnu-8-1.s
+#as: -a32
+#ld: -r -melf32ppc
+#readelf: -A
+#target: powerpc*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_Power_ABI_Vector: Generic
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-2.s b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-2.s
new file mode 100644
index 0000000..0f18f5f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-2.s
@@ -0,0 +1 @@
+.gnu_attribute 8,2
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-23.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-23.d
new file mode 100644
index 0000000..b22e4bd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-23.d
@@ -0,0 +1,6 @@
+#source: attr-gnu-8-2.s
+#source: attr-gnu-8-3.s
+#as: -a32
+#ld: -r -melf32ppc
+#warning: Warning: .* uses vector ABI "SPE", .* uses "AltiVec"
+#target: powerpc*-*-*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-3.s b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-3.s
new file mode 100644
index 0000000..6a1cf4e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-3.s
@@ -0,0 +1 @@
+.gnu_attribute 8,3
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-31.d b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-31.d
new file mode 100644
index 0000000..53e8f99
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/attr-gnu-8-31.d
@@ -0,0 +1,10 @@
+#source: attr-gnu-8-3.s
+#source: attr-gnu-8-1.s
+#as: -a32
+#ld: -r -melf32ppc
+#readelf: -A
+#target: powerpc*-*-*
+
+Attribute Section: gnu
+File Attributes
+  Tag_GNU_Power_ABI_Vector: SPE
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/plt1.d b/binutils-2.19/ld/testsuite/ld-powerpc/plt1.d
new file mode 100644
index 0000000..d8d9d8d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/plt1.d
@@ -0,0 +1,20 @@
+#source: plt1.s
+#as: -a32
+#objdump: -dr
+#target: powerpc*-*-*
+
+.*:     file format elf32-powerpc
+
+Disassembly of section .text:
+
+0+ <_start>:
+   0:	42 9f 00 05 	bcl-    20,4\*cr7\+so,4 .*
+   4:	7f c8 02 a6 	mflr    r30
+   8:	3f de 00 00 	addis   r30,r30,0
+			a: R_PPC_REL16_HA	_GLOBAL_OFFSET_TABLE_\+0x6
+   c:	3b de 00 0a 	addi    r30,r30,10
+			e: R_PPC_REL16_LO	_GLOBAL_OFFSET_TABLE_\+0xa
+  10:	48 00 00 01 	bl      10 .*
+			10: R_PPC_PLTREL24	_exit
+  14:	48 00 00 00 	b       14 .*
+			14: R_PPC_REL24	_start
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/plt1.s b/binutils-2.19/ld/testsuite/ld-powerpc/plt1.s
new file mode 100644
index 0000000..c00c264
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/plt1.s
@@ -0,0 +1,9 @@
+	.text
+	.global _start
+_start:
+	bcl 20,31,1f
+1:	mflr 30
+	addis 30,30,(_GLOBAL_OFFSET_TABLE_-1b)@ha
+	addi 30,30,(_GLOBAL_OFFSET_TABLE_-1b)@l
+	bl _exit@plt
+	b _start
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/powerpc.exp b/binutils-2.19/ld/testsuite/ld-powerpc/powerpc.exp
new file mode 100644
index 0000000..4e03cf6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/powerpc.exp
@@ -0,0 +1,179 @@
+# Expect script for ld-powerpc tests
+#   Copyright 2002, 2003, 2005, 2006, 2007, 2008 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+if { ![istarget "powerpc*-*-*"]	} {
+    return
+}
+
+if {[istarget "*-*-vxworks"]} {
+    set ppcvxtests {
+	{"VxWorks shared library test 1 (default script)" "-shared"
+	 "-mregnames" {vxworks1-lib.s}
+	 {{readelf --segments vxworks1-lib.sd}}
+	 "libvxworks1.so"}
+	{"VxWorks shared library test 1" "-shared -Tvxworks1.ld"
+	 "-mregnames" {vxworks1-lib.s}
+	 {{readelf --relocs vxworks1-lib.rd} {objdump -dr vxworks1-lib.dd}
+	  {readelf --symbols vxworks1-lib.nd} {readelf -d vxworks1-lib.td}}
+	 "libvxworks1.so"}
+	{"VxWorks executable test 1 (dynamic)" \
+	 "tmpdir/libvxworks1.so -Tvxworks1.ld -q --force-dynamic"
+	 "-mregnames" {vxworks1.s}
+	 {{readelf --relocs vxworks1.rd} {objdump -dr vxworks1.dd}}
+	 "vxworks1"}
+	{"VxWorks executable test 2 (dynamic)" \
+	 "-Tvxworks1.ld -q --force-dynamic"
+	 "-mregnames" {vxworks2.s}
+	 {{readelf --segments vxworks2.sd}}
+	 "vxworks2"}
+	{"VxWorks executable test 2 (static)"
+	 "-Tvxworks1.ld"
+	 "-mregnames" {vxworks2.s}
+	 {{readelf --segments vxworks2-static.sd}}
+	 "vxworks2"}
+    }
+    run_ld_link_tests $ppcvxtests
+    run_dump_test "vxworks1-static"
+    return
+}
+
+# powerpc ELF only at the moment.  Disable for nto too, even though it
+# is ELF, because we pass -melf32ppc to ld and powerpc-nto-ld wants
+# -melf32ppcnto.
+
+if { [istarget "*-*-macos*"] || [istarget "*-*-netware*"]
+     || [istarget "*-*-pe"] || [istarget "*-*-winnt*"]
+     || [istarget "*-*-cygwin*"] || [istarget "*-*-aix*"]
+     || [istarget "*-*-beos*"] || [istarget "*-*-lynxos*"]
+     || [istarget "*-*-nto*"] } {
+    return
+}
+
+proc supports_ppc64 { } {
+    global ld
+
+    catch "exec $ld --help | grep emulations" tmp
+    if [ string match "*elf64ppc*" $tmp ] then {
+	return 1
+    } else {
+	return 0
+    }
+}
+
+# List contains test-items with 3 items followed by 2 lists:
+# 0:name 1:ld options 2:assembler options
+# 3:filenames of assembler files 4: action and options. 5: name of output file
+
+# Actions:
+# objdump: Apply objdump options on result.  Compare with regex (last arg).
+# nm: Apply nm options on result.  Compare with regex (last arg).
+# readelf: Apply readelf options on result.  Compare with regex (last arg).
+
+set ppcelftests {
+    {"Reloc section order" "-melf32ppc -shared -z nocombreloc" "-a32" {reloc.s}
+     {{objdump -hw reloc.d}} "reloc.so"}
+    {"APUinfo section processing" "-melf32ppc"
+     "-a32 -me500" {apuinfo1.s apuinfo2.s}
+    {{readelf -x2 apuinfo.rd}} "apuinfo"}
+    {"TLS32 static exec" "-melf32ppc" "-a32"  {tls32.s tlslib32.s}
+     {{objdump -dr tls32.d} {objdump -sj.got tls32.g}
+      {objdump -sj.tdata tls32.t}}
+     "tls32"}
+    {"TLS32 helper shared library" "-shared -melf32ppc tmpdir/tlslib32.o" "" {}
+     {} "libtlslib32.so"}
+    {"TLS32 dynamic exec" "-melf32ppc tmpdir/tls32.o tmpdir/libtlslib32.so" "" {}
+     {{readelf -WSsrl tlsexe32.r} {objdump -dr tlsexe32.d}
+      {objdump -sj.got tlsexe32.g} {objdump -sj.tdata tlsexe32.t}}
+      "tlsexe32"}
+    {"TLS32 shared" "-shared -melf32ppc tmpdir/tls32.o" "" {}
+     {{readelf -WSsrl tlsso32.r} {objdump -dr tlsso32.d}
+      {objdump -sj.got tlsso32.g} {objdump -sj.tdata tlsso32.t}}
+      "tls32.so"}
+    {"Shared library with global symbol" "-shared -melf32ppc" "-a32" {sdalib.s}
+     {} "sdalib.so"}
+    {"Dynamic application with SDA" "-melf32ppc tmpdir/sdalib.so" "-a32" {sdadyn.s}
+     {{objdump -R sdadyn.d}} "sdadyn"}
+}
+
+set ppc64elftests {
+    {"TLS static exec" "-melf64ppc" "-a64"  {tls.s tlslib.s}
+     {{objdump -dr tls.d} {objdump -sj.got tls.g} {objdump -sj.tdata tls.t}}
+      "tls"}
+    {"TLS helper shared library" "-shared -melf64ppc tmpdir/tlslib.o" "" {}
+     {} "libtlslib.so"}
+    {"TLS dynamic exec" "-melf64ppc tmpdir/tls.o tmpdir/libtlslib.so" "" {}
+     {{readelf -WSsrl tlsexe.r} {objdump -dr tlsexe.d}
+      {objdump -sj.got tlsexe.g} {objdump -sj.tdata tlsexe.t}}
+      "tlsexe"}
+    {"TLS shared" "-shared -melf64ppc tmpdir/tls.o" "" {}
+     {{readelf -WSsrl tlsso.r} {objdump -dr tlsso.d}
+      {objdump -sj.got tlsso.g} {objdump -sj.tdata tlsso.t}}
+      "tls.so"}
+    {"TLSTOC static exec" "-melf64ppc tmpdir/tlslib.o " "-a64"  {tlstoc.s}
+     {{objdump -dr tlstoc.d} {objdump -sj.got tlstoc.g}
+      {objdump -sj.tdata tlstoc.t}}
+      "tlstoc"}
+    {"TLSTOC dynamic exec" "-melf64ppc tmpdir/tlstoc.o tmpdir/libtlslib.so"
+     "" {}
+     {{readelf -WSsrl tlsexetoc.r} {objdump -dr tlsexetoc.d}
+      {objdump -sj.got tlsexetoc.g} {objdump -sj.tdata tlsexetoc.t}}
+      "tlsexetoc"}
+    {"TLSTOC shared" "-shared -melf64ppc tmpdir/tlstoc.o" "" {}
+     {{readelf -WSsrl tlstocso.r} {objdump -dr tlstocso.d}
+      {objdump -sj.got tlstocso.g} {objdump -sj.tdata tlstocso.t}}
+      "tlstoc.so"}
+    {"sym@tocbase" "-shared -melf64ppc" "-a64" {symtocbase-1.s symtocbase-2.s}
+	{{objdump -dj.data symtocbase.d}} "symtocbase.so"}
+}
+
+
+run_ld_link_tests $ppcelftests
+
+if [ supports_ppc64 ] then {
+    run_ld_link_tests $ppc64elftests
+    run_dump_test "relbrlt"
+}
+
+run_dump_test "plt1"
+
+run_dump_test "attr-gnu-4-00"
+run_dump_test "attr-gnu-4-01"
+run_dump_test "attr-gnu-4-02"
+run_dump_test "attr-gnu-4-03"
+run_dump_test "attr-gnu-4-10"
+run_dump_test "attr-gnu-4-11"
+run_dump_test "attr-gnu-4-12"
+run_dump_test "attr-gnu-4-13"
+run_dump_test "attr-gnu-4-14"
+run_dump_test "attr-gnu-4-20"
+run_dump_test "attr-gnu-4-21"
+run_dump_test "attr-gnu-4-22"
+run_dump_test "attr-gnu-4-23"
+run_dump_test "attr-gnu-4-24"
+run_dump_test "attr-gnu-4-31"
+run_dump_test "attr-gnu-4-32"
+run_dump_test "attr-gnu-4-33"
+run_dump_test "attr-gnu-4-34"
+run_dump_test "attr-gnu-4-41"
+
+run_dump_test "attr-gnu-8-11"
+run_dump_test "attr-gnu-8-23"
+run_dump_test "attr-gnu-8-31"
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/relbrlt.d b/binutils-2.19/ld/testsuite/ld-powerpc/relbrlt.d
new file mode 100644
index 0000000..69321eb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/relbrlt.d
@@ -0,0 +1,60 @@
+#source: relbrlt.s
+#as: -a64
+#ld: -melf64ppc --emit-relocs
+#objdump: -Dr
+
+.*:     file format elf64-powerpc
+
+Disassembly of section \.text:
+
+0*100000b0 <_start>:
+[0-9a-f	 ]*:	49 bf 00 2d 	bl      .*
+[0-9a-f	 ]*: R_PPC64_REL24	\.text\+0x37e003c
+[0-9a-f	 ]*:	60 00 00 00 	nop
+[0-9a-f	 ]*:	49 bf 00 19 	bl      .*
+[0-9a-f	 ]*: R_PPC64_REL24	\.text\+0x3bf0020
+[0-9a-f	 ]*:	60 00 00 00 	nop
+[0-9a-f	 ]*:	49 bf 00 21 	bl      .*
+[0-9a-f	 ]*: R_PPC64_REL24	\.text\+0x57e0024
+[0-9a-f	 ]*:	60 00 00 00 	nop
+[0-9a-f	 ]*:	00 00 00 00 	\.long 0x0
+[0-9a-f	 ]*:	4b ff ff e4 	b       .* <_start>
+	\.\.\.
+
+[0-9a-f	 ]*<.*plt_branch.*>:
+[0-9a-f	 ]*:	e9 62 80 00 	ld      r11,-32768\(r2\)
+[0-9a-f	 ]*: R_PPC64_TOC16_DS	\*ABS\*\+0x157f00d8
+[0-9a-f	 ]*:	7d 69 03 a6 	mtctr   r11
+[0-9a-f	 ]*:	4e 80 04 20 	bctr
+
+[0-9a-f	 ]*<.*long_branch.*>:
+[0-9a-f	 ]*:	49 bf 00 10 	b       .* <far>
+[0-9a-f	 ]*: R_PPC64_REL24	\*ABS\*\+0x137e00ec
+
+[0-9a-f	 ]*<.*plt_branch.*>:
+[0-9a-f	 ]*:	e9 62 80 08 	ld      r11,-32760\(r2\)
+[0-9a-f	 ]*: R_PPC64_TOC16_DS	\*ABS\*\+0x157f00e0
+[0-9a-f	 ]*:	7d 69 03 a6 	mtctr   r11
+[0-9a-f	 ]*:	4e 80 04 20 	bctr
+	\.\.\.
+
+0*137e00ec <far>:
+[0-9a-f	 ]*:	4e 80 00 20 	blr
+	\.\.\.
+
+0*13bf00d0 <far2far>:
+[0-9a-f	 ]*:	4e 80 00 20 	blr
+	\.\.\.
+
+0*157e00d4 <huge>:
+[0-9a-f	 ]*:	4e 80 00 20 	blr
+
+Disassembly of section \.branch_lt:
+
+0*157f00d8 <\.branch_lt>:
+[0-9a-f	 ]*:	00 00 00 00 .*
+[0-9a-f	 ]*: R_PPC64_RELATIVE	\*ABS\*\+0x13bf00d0
+[0-9a-f	 ]*:	13 bf 00 d0 .*
+[0-9a-f	 ]*:	00 00 00 00 .*
+[0-9a-f	 ]*: R_PPC64_RELATIVE	\*ABS\*\+0x157e00d4
+[0-9a-f	 ]*:	15 7e 00 d4 .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/relbrlt.s b/binutils-2.19/ld/testsuite/ld-powerpc/relbrlt.s
new file mode 100644
index 0000000..cee0cdd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/relbrlt.s
@@ -0,0 +1,34 @@
+ .text
+ .global _start
+_start:
+1:
+ bl far
+ nop
+ bl far2far
+ nop
+ bl huge
+ nop
+ .long 0
+ b 1b
+ .space 0x1bf0000
+
+ .section .text.pad1,"ax"
+ .space 0x1bf0000
+
+ .section .text.far,"ax"
+far:
+ blr
+
+ .section .text.pad2,"ax"
+ .space 0x40ffe0
+
+ .section .text.far2far,"ax"
+far2far:
+ blr
+
+ .section .text.pad3,"ax"
+ .space 0x1bf0000
+
+ .section .text.huge,"ax"
+huge:
+ blr
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/reloc.d b/binutils-2.19/ld/testsuite/ld-powerpc/reloc.d
new file mode 100644
index 0000000..1c7eb8a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/reloc.d
@@ -0,0 +1,13 @@
+# Test that orphan reloc sections are placed before .rela.plt even when
+# .rela.plt is the only reloc section.
+
+#source: reloc.s
+#ld: -shared -z nocombreloc
+#objdump: -hw
+
+.*: +file format elf.*
+#...
+.*\.relaplatypus.*
+#...
+.*\.rela\.plt.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/reloc.s b/binutils-2.19/ld/testsuite/ld-powerpc/reloc.s
new file mode 100644
index 0000000..4e66151
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/reloc.s
@@ -0,0 +1,9 @@
+ .section echidna
+ .long .text
+
+ .section platypus,"ax"
+ .long .text
+
+ .text
+ b _start@plt
+ nop
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/sdadyn.d b/binutils-2.19/ld/testsuite/ld-powerpc/sdadyn.d
new file mode 100644
index 0000000..42e389f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/sdadyn.d
@@ -0,0 +1,8 @@
+
+.*: +file format elf32-powerpc
+
+DYNAMIC RELOCATION RECORDS
+OFFSET   TYPE              VALUE 
+#...
+.* R_PPC_COPY        lib_var
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/sdadyn.s b/binutils-2.19/ld/testsuite/ld-powerpc/sdadyn.s
new file mode 100644
index 0000000..1b2d13f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/sdadyn.s
@@ -0,0 +1,3 @@
+	.globl _start
+_start:
+	lwz	3,lib_var@sda21(0)
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/sdalib.s b/binutils-2.19/ld/testsuite/ld-powerpc/sdalib.s
new file mode 100644
index 0000000..69b0391
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/sdalib.s
@@ -0,0 +1,5 @@
+	.globl lib_var
+	.type lib_var, @object
+	.size lib_var, 2
+lib_var:
+	.word	1
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/symtocbase-1.s b/binutils-2.19/ld/testsuite/ld-powerpc/symtocbase-1.s
new file mode 100644
index 0000000..ba6f073
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/symtocbase-1.s
@@ -0,0 +1,18 @@
+.section .toc,"aw",@progbits
+	.align 15
+	.globl x
+x:	.quad	.x,.x@tocbase,0
+.LCi:	.quad	i
+	.space	48 * 1024
+.data
+	.globl i
+i:	.long	0
+.L1bases:
+	.quad	.TOC.@tocbase
+	.quad	.x@tocbase
+	.quad	.y@tocbase
+.text
+	.globl .x
+.x:
+	ld 9,.LCi@toc(2)
+        blr
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/symtocbase-2.s b/binutils-2.19/ld/testsuite/ld-powerpc/symtocbase-2.s
new file mode 100644
index 0000000..1176cb8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/symtocbase-2.s
@@ -0,0 +1,16 @@
+.section .toc,"aw",@progbits
+	.align 15
+	.globl y
+y:	.quad	.y,.y@tocbase,0
+.LCi:	.quad	i
+	.space	48 * 1024
+.data
+.L2bases:
+	.quad	.TOC.@tocbase
+	.quad	.x@tocbase
+	.quad	.y@tocbase
+.text
+	.globl .y
+.y:
+	ld 9,.LCi@toc(2)
+	blr
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/symtocbase.d b/binutils-2.19/ld/testsuite/ld-powerpc/symtocbase.d
new file mode 100644
index 0000000..5ffab72
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/symtocbase.d
@@ -0,0 +1,24 @@
+#source: symtocbase-1.s
+#source: symtocbase-2.s
+#as: -a64
+#ld: -shared -melf64ppc
+#objdump: -dj.data
+#target: powerpc64*-*-*
+
+.*:     file format elf64-powerpc
+
+Disassembly of section \.data:
+
+.* <i>:
+	\.\.\.
+.*:	00 02 80 00 	\.long 0x28000
+.*:	00 00 00 00 	\.long 0x0
+.*:	00 02 80 00 	\.long 0x28000
+.*:	00 00 00 00 	\.long 0x0
+.*:	00 03 80 00 	\.long 0x38000
+.*:	00 00 00 00 	\.long 0x0
+.*:	00 03 80 00 	\.long 0x38000
+.*:	00 00 00 00 	\.long 0x0
+.*:	00 02 80 00 	\.long 0x28000
+.*:	00 00 00 00 	\.long 0x0
+.*:	00 03 80 00 	\.long 0x38000
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tls.d b/binutils-2.19/ld/testsuite/ld-powerpc/tls.d
new file mode 100644
index 0000000..abae98a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tls.d
@@ -0,0 +1,53 @@
+#source: tls.s
+#source: tlslib.s
+#as: -a64
+#ld: -melf64ppc
+#objdump: -dr
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Disassembly of section \.text:
+
+0+100000e8 <_start>:
+    100000e8:	3c 6d 00 00 	addis   r3,r13,0
+    100000ec:	60 00 00 00 	nop
+    100000f0:	38 63 90 78 	addi    r3,r3,-28552
+    100000f4:	3c 6d 00 00 	addis   r3,r13,0
+    100000f8:	60 00 00 00 	nop
+    100000fc:	38 63 10 00 	addi    r3,r3,4096
+    10000100:	3c 6d 00 00 	addis   r3,r13,0
+    10000104:	60 00 00 00 	nop
+    10000108:	38 63 90 40 	addi    r3,r3,-28608
+    1000010c:	3c 6d 00 00 	addis   r3,r13,0
+    10000110:	60 00 00 00 	nop
+    10000114:	38 63 10 00 	addi    r3,r3,4096
+    10000118:	39 23 80 48 	addi    r9,r3,-32696
+    1000011c:	3d 23 00 00 	addis   r9,r3,0
+    10000120:	81 49 80 50 	lwz     r10,-32688\(r9\)
+    10000124:	e9 22 80 10 	ld      r9,-32752\(r2\)
+    10000128:	7d 49 18 2a 	ldx     r10,r9,r3
+    1000012c:	3d 2d 00 00 	addis   r9,r13,0
+    10000130:	a1 49 90 60 	lhz     r10,-28576\(r9\)
+    10000134:	89 4d 90 68 	lbz     r10,-28568\(r13\)
+    10000138:	3d 2d 00 00 	addis   r9,r13,0
+    1000013c:	99 49 90 70 	stb     r10,-28560\(r9\)
+    10000140:	3c 6d 00 00 	addis   r3,r13,0
+    10000144:	60 00 00 00 	nop
+    10000148:	38 63 90 00 	addi    r3,r3,-28672
+    1000014c:	3c 6d 00 00 	addis   r3,r13,0
+    10000150:	60 00 00 00 	nop
+    10000154:	38 63 10 00 	addi    r3,r3,4096
+    10000158:	f9 43 80 08 	std     r10,-32760\(r3\)
+    1000015c:	3d 23 00 00 	addis   r9,r3,0
+    10000160:	91 49 80 10 	stw     r10,-32752\(r9\)
+    10000164:	e9 22 80 08 	ld      r9,-32760\(r2\)
+    10000168:	7d 49 19 2a 	stdx    r10,r9,r3
+    1000016c:	3d 2d 00 00 	addis   r9,r13,0
+    10000170:	b1 49 90 60 	sth     r10,-28576\(r9\)
+    10000174:	e9 4d 90 2a 	lwa     r10,-28632\(r13\)
+    10000178:	3d 2d 00 00 	addis   r9,r13,0
+    1000017c:	a9 49 90 30 	lha     r10,-28624\(r9\)
+
+0+10000180 <\.__tls_get_addr>:
+    10000180:	4e 80 00 20 	blr
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tls.g b/binutils-2.19/ld/testsuite/ld-powerpc/tls.g
new file mode 100644
index 0000000..051ddd1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tls.g
@@ -0,0 +1,12 @@
+#source: tls.s
+#source: tlslib.s
+#as: -a64
+#ld: -melf64ppc
+#objdump: -sj.got
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Contents of section \.got:
+ 100101e0 00000000 100181e0 ffffffff ffff8018  .*
+ 100101f0 ffffffff ffff8058                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tls.s b/binutils-2.19/ld/testsuite/ld-powerpc/tls.s
new file mode 100644
index 0000000..5ad9f3d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tls.s
@@ -0,0 +1,92 @@
+	.section ".tbss","awT",@nobits
+	.global _start,gd0,ld0,ld1,ld2,ie0,le0,le1
+	.align 3
+gd0:	.space 8
+ld0:	.space 8
+ld1:	.space 8
+ld2:	.space 8
+ie0:	.space 8
+le0:	.space 8
+le1:	.space 8
+
+	.section ".tdata","awT",@progbits
+	.align 3
+gd4:	.quad 0x123456789abcdef0
+ld4:	.quad 0x23456789abcdef01
+ld5:	.quad 0x3456789abcdef012
+ld6:	.quad 0x456789abcdef0123
+ie4:	.quad 0x56789abcdef01234
+le4:	.quad 0x6789abcdef012345
+le5:	.quad 0x789abcdef0123456
+
+	.text
+_start:
+#extern syms
+#GD
+ addi 3,2,gd@got@tlsgd		#R_PPC64_GOT_TLSGD16	gd
+ bl .__tls_get_addr		#R_PPC64_REL24		.__tls_get_addr
+ nop
+
+#LD
+ addi 3,2,ld@got@tlsld		#R_PPC64_GOT_TLSLD16	ld
+ bl .__tls_get_addr		#R_PPC64_REL24		.__tls_get_addr
+ nop
+
+#global syms
+#GD
+ addi 3,2,gd0@got@tlsgd		#R_PPC64_GOT_TLSGD16	gd0
+ bl .__tls_get_addr		#R_PPC64_REL24		.__tls_get_addr
+ nop
+
+#LD
+ addi 3,2,ld0@got@tlsld		#R_PPC64_GOT_TLSLD16	ld0
+ bl .__tls_get_addr		#R_PPC64_REL24		.__tls_get_addr
+ nop
+
+ addi 9,3,ld0@dtprel		#R_PPC64_DTPREL16	ld0
+
+ addis 9,3,ld1@dtprel@ha	#R_PPC64_DTPREL16_HA	ld1
+ lwz 10,ld1@dtprel@l(9)		#R_PPC64_DTPREL16_LO	ld1
+
+ ld 9,ld2@got@dtprel(2)		#R_PPC64_GOT_DTPREL16_DS ld2
+ ldx 10,9,3
+
+#IE
+ ld 9,ie0@got@tprel(2)		#R_PPC64_GOT_TPREL16_DS	ie0
+ lhzx 10,9,ie0@tls		#R_PPC64_TLS		ie0
+
+#LE
+ lbz 10,le0@tprel(13)		#R_PPC64_TPREL16	le0
+
+ addis 9,13,le1@tprel@ha	#R_PPC64_TPREL16_HA	le1
+ stb 10,le1@tprel@l(9)		#R_PPC64_TPREL16_LO	le1
+
+#local syms
+#GD
+ addi 3,2,gd4@got@tlsgd		#R_PPC64_GOT_TLSGD16	gd4
+ bl .__tls_get_addr		#R_PPC64_REL24		.__tls_get_addr
+ nop
+
+#LD
+ addi 3,2,ld4@got@tlsld		#R_PPC64_GOT_TLSLD16	ld4
+ bl .__tls_get_addr		#R_PPC64_REL24		.__tls_get_addr
+ nop
+
+ std 10,ld4@dtprel(3)		#R_PPC64_DTPREL16_DS	ld4
+
+ addis 9,3,ld5@dtprel@ha	#R_PPC64_DTPREL16_HA	ld5
+ stw 10,ld5@dtprel@l(9)		#R_PPC64_DTPREL16_LO	ld5
+
+ ld 9,ld6@got@dtprel(2)		#R_PPC64_GOT_DTPREL16_DS ld6
+ stdx 10,9,3
+
+#IE
+ ld 9,ie0@got@tprel(2)		#R_PPC64_GOT_TPREL16_DS	ie4
+ sthx 10,9,ie0@tls		#R_PPC64_TLS		ie4
+
+#LE
+ lwa 10,le4@tprel(13)		#R_PPC64_TPREL16	le4
+
+ addis 9,13,le5@tprel@ha	#R_PPC64_TPREL16_HA	le5
+ lha 10,le5@tprel@l(9)		#R_PPC64_TPREL16_LO	le5
+
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tls.t b/binutils-2.19/ld/testsuite/ld-powerpc/tls.t
new file mode 100644
index 0000000..32a909b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tls.t
@@ -0,0 +1,14 @@
+#source: tls.s
+#source: tlslib.s
+#as: -a64
+#ld: -melf64ppc
+#objdump: -sj.tdata
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Contents of section \.tdata:
+.* 12345678 9abcdef0 23456789 abcdef01  .*
+.* 3456789a bcdef012 456789ab cdef0123  .*
+.* 56789abc def01234 6789abcd ef012345  .*
+.* 789abcde f0123456 00c0ffee           .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tls32.d b/binutils-2.19/ld/testsuite/ld-powerpc/tls32.d
new file mode 100644
index 0000000..86fe04a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tls32.d
@@ -0,0 +1,50 @@
+#source: tls32.s
+#source: tlslib32.s
+#as: -a32
+#ld: -melf32ppc
+#objdump: -dr
+#target: powerpc*-*-*
+
+.*: +file format elf32-powerpc
+
+Disassembly of section \.text:
+
+0+1800094 <_start>:
+ 1800094:	3c 62 00 00 	addis   r3,r2,0
+ 1800098:	38 63 90 3c 	addi    r3,r3,-28612
+ 180009c:	3c 62 00 00 	addis   r3,r2,0
+ 18000a0:	38 63 10 00 	addi    r3,r3,4096
+ 18000a4:	3c 62 00 00 	addis   r3,r2,0
+ 18000a8:	38 63 90 20 	addi    r3,r3,-28640
+ 18000ac:	3c 62 00 00 	addis   r3,r2,0
+ 18000b0:	38 63 10 00 	addi    r3,r3,4096
+ 18000b4:	39 23 80 24 	addi    r9,r3,-32732
+ 18000b8:	3d 23 00 00 	addis   r9,r3,0
+ 18000bc:	81 49 80 28 	lwz     r10,-32728\(r9\)
+ 18000c0:	3d 22 00 00 	addis   r9,r2,0
+ 18000c4:	a1 49 90 30 	lhz     r10,-28624\(r9\)
+ 18000c8:	89 42 90 34 	lbz     r10,-28620\(r2\)
+ 18000cc:	3d 22 00 00 	addis   r9,r2,0
+ 18000d0:	99 49 90 38 	stb     r10,-28616\(r9\)
+ 18000d4:	3c 62 00 00 	addis   r3,r2,0
+ 18000d8:	38 63 90 00 	addi    r3,r3,-28672
+ 18000dc:	3c 62 00 00 	addis   r3,r2,0
+ 18000e0:	38 63 10 00 	addi    r3,r3,4096
+ 18000e4:	91 43 80 04 	stw     r10,-32764\(r3\)
+ 18000e8:	3d 23 00 00 	addis   r9,r3,0
+ 18000ec:	91 49 80 08 	stw     r10,-32760\(r9\)
+ 18000f0:	3d 22 00 00 	addis   r9,r2,0
+ 18000f4:	b1 49 90 30 	sth     r10,-28624\(r9\)
+ 18000f8:	a1 42 90 14 	lhz     r10,-28652\(r2\)
+ 18000fc:	3d 22 00 00 	addis   r9,r2,0
+ 1800100:	a9 49 90 18 	lha     r10,-28648\(r9\)
+
+0+1800104 <__tls_get_addr>:
+ 1800104:	4e 80 00 20 	blr
+Disassembly of section \.got:
+
+0+1810128 <_GLOBAL_OFFSET_TABLE_-0x4>:
+ 1810128:	4e 80 00 21 	blrl
+
+0+181012c <_GLOBAL_OFFSET_TABLE_>:
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tls32.g b/binutils-2.19/ld/testsuite/ld-powerpc/tls32.g
new file mode 100644
index 0000000..e8c72cc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tls32.g
@@ -0,0 +1,11 @@
+#source: tls32.s
+#source: tlslib32.s
+#as: -a32
+#ld: -melf32ppc
+#objdump: -sj.got
+#target: powerpc*-*-*
+
+.*: +file format elf32-powerpc
+
+Contents of section \.got:
+ 1810128 4e800021 00000000 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tls32.s b/binutils-2.19/ld/testsuite/ld-powerpc/tls32.s
new file mode 100644
index 0000000..1c3092d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tls32.s
@@ -0,0 +1,80 @@
+	.section ".tbss","awT",@nobits
+	.global _start,gd0,ld0,ld1,ld2,ie0,le0,le1
+	.align 2
+gd0:	.space 4
+ld0:	.space 4
+ld1:	.space 4
+ld2:	.space 4
+ie0:	.space 4
+le0:	.space 4
+le1:	.space 4
+
+	.section ".tdata","awT",@progbits
+	.align 2
+gd4:	.long 0x12345678
+ld4:	.long 0x23456789
+ld5:	.long 0x3456789a
+ld6:	.long 0x456789ab
+ie4:	.long 0x56789abc
+le4:	.long 0x6789abcd
+le5:	.long 0x789abcde
+
+	.text
+_start:
+#extern syms
+#GD
+ addi 3,31,gd@got@tlsgd		#R_PPC_GOT_TLSGD16	gd
+ bl __tls_get_addr		#R_PPC_REL24		__tls_get_addr
+
+#LD
+ addi 3,31,ld@got@tlsld		#R_PPC_GOT_TLSLD16	ld
+ bl __tls_get_addr		#R_PPC_REL24		__tls_get_addr
+
+#global syms
+#GD
+ addi 3,31,gd0@got@tlsgd	#R_PPC_GOT_TLSGD16	gd0
+ bl __tls_get_addr+0x8000@plt	#R_PPC_PLTREL24		__tls_get_addr
+
+#LD
+ addi 3,31,ld0@got@tlsld	#R_PPC_GOT_TLSLD16	ld0
+ bl __tls_get_addr+0x8000@plt	#R_PPC_PLTREL24		__tls_get_addr
+
+ addi 9,3,ld0@dtprel		#R_PPC_DTPREL16		ld0
+
+ addis 9,3,ld1@dtprel@ha	#R_PPC_DTPREL16_HA	ld1
+ lwz 10,ld1@dtprel@l(9)		#R_PPC_DTPREL16_LO	ld1
+
+#IE
+ lwz 9,ie0@got@tprel(31)	#R_PPC_GOT_TPREL16	ie0
+ lhzx 10,9,ie0@tls		#R_PPC_TLS		ie0
+
+#LE
+ lbz 10,le0@tprel(2)		#R_PPC_TPREL16		le0
+
+ addis 9,2,le1@tprel@ha		#R_PPC_TPREL16_HA	le1
+ stb 10,le1@tprel@l(9)		#R_PPC_TPREL16_LO	le1
+
+#local syms, use a different got reg too.
+#GD
+ addi 3,30,gd4@got@tlsgd	#R_PPC_GOT_TLSGD16	gd4
+ bl __tls_get_addr		#R_PPC_REL24		__tls_get_addr
+
+#LD
+ addi 3,30,ld4@got@tlsld	#R_PPC_GOT_TLSLD16	ld4
+ bl __tls_get_addr		#R_PPC_REL24		__tls_get_addr
+
+ stw 10,ld4@dtprel(3)		#R_PPC_DTPREL16	ld4
+
+ addis 9,3,ld5@dtprel@ha	#R_PPC_DTPREL16_HA	ld5
+ stw 10,ld5@dtprel@l(9)		#R_PPC_DTPREL16_LO	ld5
+
+#IE
+ lwz 9,ie0@got@tprel(30)	#R_PPC_GOT_TPREL16	ie4
+ sthx 10,9,ie0@tls		#R_PPC_TLS		ie4
+
+#LE
+ lhz 10,le4@tprel(2)		#R_PPC_TPREL16	le4
+
+ addis 9,2,le5@tprel@ha		#R_PPC_TPREL16_HA	le5
+ lha 10,le5@tprel@l(9)		#R_PPC_TPREL16_LO	le5
+
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tls32.t b/binutils-2.19/ld/testsuite/ld-powerpc/tls32.t
new file mode 100644
index 0000000..8149a28
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tls32.t
@@ -0,0 +1,12 @@
+#source: tls32.s
+#source: tlslib32.s
+#as: -a32
+#ld: -melf32ppc
+#objdump: -sj.tdata
+#target: powerpc*-*-*
+
+.*: +file format elf32-powerpc
+
+Contents of section \.tdata:
+ 1810108 12345678 23456789 3456789a 456789ab  .*
+ 1810118 56789abc 6789abcd 789abcde 00c0ffee  .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe.d b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe.d
new file mode 100644
index 0000000..825434e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe.d
@@ -0,0 +1,75 @@
+#source: tls.s
+#as: -a64
+#ld: -melf64ppc tmpdir/libtlslib.so
+#objdump: -dr
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Disassembly of section \.text:
+
+.* <_start-0x18>:
+.*	f8 41 00 28 	std     r2,40\(r1\)
+.*	e9 62 80 48 	ld      r11,-32696\(r2\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 62 80 58 	ld      r11,-32680\(r2\)
+.*	e8 42 80 50 	ld      r2,-32688\(r2\)
+.*	4e 80 04 20 	bctr
+
+.* <_start>:
+.*	e8 62 80 10 	ld      r3,-32752\(r2\)
+.*	60 00 00 00 	nop
+.*	7c 63 6a 14 	add     r3,r3,r13
+.*	38 62 80 18 	addi    r3,r2,-32744
+.*	4b ff ff d9 	bl      .*
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	3c 6d 00 00 	addis   r3,r13,0
+.*	60 00 00 00 	nop
+.*	38 63 90 38 	addi    r3,r3,-28616
+.*	3c 6d 00 00 	addis   r3,r13,0
+.*	60 00 00 00 	nop
+.*	38 63 10 00 	addi    r3,r3,4096
+.*	39 23 80 40 	addi    r9,r3,-32704
+.*	3d 23 00 00 	addis   r9,r3,0
+.*	81 49 80 48 	lwz     r10,-32696\(r9\)
+.*	e9 22 80 28 	ld      r9,-32728\(r2\)
+.*	7d 49 18 2a 	ldx     r10,r9,r3
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	a1 49 90 58 	lhz     r10,-28584\(r9\)
+.*	89 4d 90 60 	lbz     r10,-28576\(r13\)
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	99 49 90 68 	stb     r10,-28568\(r9\)
+.*	3c 6d 00 00 	addis   r3,r13,0
+.*	60 00 00 00 	nop
+.*	38 63 90 00 	addi    r3,r3,-28672
+.*	3c 6d 00 00 	addis   r3,r13,0
+.*	60 00 00 00 	nop
+.*	38 63 10 00 	addi    r3,r3,4096
+.*	f9 43 80 08 	std     r10,-32760\(r3\)
+.*	3d 23 00 00 	addis   r9,r3,0
+.*	91 49 80 10 	stw     r10,-32752\(r9\)
+.*	e9 22 80 08 	ld      r9,-32760\(r2\)
+.*	7d 49 19 2a 	stdx    r10,r9,r3
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	b1 49 90 58 	sth     r10,-28584\(r9\)
+.*	e9 4d 90 2a 	lwa     r10,-28632\(r13\)
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	a9 49 90 30 	lha     r10,-28624\(r9\)
+.*	00 00 00 00 .*
+.*	00 01 01 f0 .*
+.*	7d 88 02 a6 	mflr    r12
+.*	42 9f 00 05 	bcl-    20,4\*cr7\+so,.*
+.*	7d 68 02 a6 	mflr    r11
+.*	e8 4b ff f0 	ld      r2,-16\(r11\)
+.*	7d 88 03 a6 	mtlr    r12
+.*	7d 82 5a 14 	add     r12,r2,r11
+.*	e9 6c 00 00 	ld      r11,0\(r12\)
+.*	e8 4c 00 08 	ld      r2,8\(r12\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 6c 00 10 	ld      r11,16\(r12\)
+.*	4e 80 04 20 	bctr
+.*	60 00 00 00 	nop
+.*	60 00 00 00 	nop
+.*	60 00 00 00 	nop
+.*	38 00 00 00 	li      r0,0
+.*	4b ff ff c4 	b       .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe.g b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe.g
new file mode 100644
index 0000000..58280df
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe.g
@@ -0,0 +1,12 @@
+#source: tls.s
+#as: -a64
+#ld: -melf64ppc tmpdir/libtlslib.so
+#objdump: -sj.got
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Contents of section \.got:
+.* 00000000 100185c8 ffffffff ffff8018  .*
+.* 00000000 00000000 00000000 00000000  .*
+.* 00000000 00000000 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe.r b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe.r
new file mode 100644
index 0000000..b73aaf1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe.r
@@ -0,0 +1,113 @@
+#source: tls.s
+#source: tlslib.s
+#as: -a64
+#ld: -melf64ppc
+#readelf: -WSsrl
+#target: powerpc64*-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+ +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] \.interp +.*
+ +\[[ 0-9]+\] \.hash +.*
+ +\[[ 0-9]+\] \.dynsym +.*
+ +\[[ 0-9]+\] \.dynstr +.*
+ +\[[ 0-9]+\] \.rela\.dyn +.*
+ +\[[ 0-9]+\] \.rela\.plt +.*
+ +\[[ 0-9]+\] \.text +PROGBITS .* 0+f8 0+ +AX +0 +0 +8
+ +\[[ 0-9]+\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
+ +\[[ 0-9]+\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC .* 0+150 10 +WA +4 +0 +8
+ +\[[ 0-9]+\] \.branch_lt + PROGBITS .* 0+ 0+ +WA +0 +0 +8
+ +\[[ 0-9]+\] \.got +PROGBITS .* 0+30 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] \.plt +.*
+ +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
+#...
+
+Elf file type is EXEC \(Executable file\)
+Entry point .*
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+ +PHDR +0x0+40 0x0+10000040 0x0+10000040 0x0+150 0x0+150 R E 0x8
+ +INTERP +0x0+190 0x0+10000190 0x0+10000190 0x0+11 0x0+11 R +0x1
+ +\[Requesting program interpreter: .*\]
+ +LOAD .* R E 0x10000
+ +LOAD .* RW +0x10000
+ +DYNAMIC .* RW +0x8
+ +TLS .* 0x0+38 0x0+70 R +0x8
+
+ Section to Segment mapping:
+ +Segment Sections\.\.\.
+ +0+ +
+ +01 +\.interp 
+ +02 +\.interp \.hash \.dynsym \.dynstr \.rela\.dyn \.rela\.plt \.text 
+ +03 +\.tdata \.dynamic \.got \.plt 
+ +04 +\.dynamic 
+ +05 +\.tdata \.tbss 
+
+Relocation section '\.rela\.dyn' at offset .* contains 3 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_PPC64_TPREL64 +0+ gd \+ 0
+[0-9a-f ]+R_PPC64_DTPMOD64 +0+ ld \+ 0
+[0-9a-f ]+R_PPC64_DTPREL64 +0+50 ld2 \+ 0
+
+Relocation section '\.rela\.plt' at offset .* contains 1 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_PPC64_JMP_SLOT +0+ __tls_get_addr \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND 
+.* TLS +GLOBAL DEFAULT +UND gd
+.* FUNC +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +UND ld
+.* TLS +GLOBAL DEFAULT +9 ld2
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* 0+ +0 NOTYPE +LOCAL +DEFAULT +UND 
+.* SECTION LOCAL +DEFAULT +1 
+.* SECTION LOCAL +DEFAULT +2 
+.* SECTION LOCAL +DEFAULT +3 
+.* SECTION LOCAL +DEFAULT +4 
+.* SECTION LOCAL +DEFAULT +5 
+.* SECTION LOCAL +DEFAULT +6 
+.* SECTION LOCAL +DEFAULT +7 
+.* SECTION LOCAL +DEFAULT +8 
+.* SECTION LOCAL +DEFAULT +9 
+.* SECTION LOCAL +DEFAULT +10 
+.* SECTION LOCAL +DEFAULT +11 
+.* SECTION LOCAL +DEFAULT +12 
+.* SECTION LOCAL +DEFAULT +13 
+.* TLS +LOCAL +DEFAULT +8 gd4
+.* TLS +LOCAL +DEFAULT +8 ld4
+.* TLS +LOCAL +DEFAULT +8 ld5
+.* TLS +LOCAL +DEFAULT +8 ld6
+.* TLS +LOCAL +DEFAULT +8 ie4
+.* TLS +LOCAL +DEFAULT +8 le4
+.* TLS +LOCAL +DEFAULT +8 le5
+.* OBJECT +LOCAL +HIDDEN +10 _DYNAMIC
+.* FUNC +LOCAL +DEFAULT +UND \.__tls_get_addr
+.* GLOBAL DEFAULT +UND gd
+.* GLOBAL DEFAULT +9 le0
+.* GLOBAL DEFAULT +UND __tls_get_addr
+.* GLOBAL DEFAULT +9 ld0
+.* GLOBAL DEFAULT +9 le1
+.* GLOBAL DEFAULT +UND ld
+.* NOTYPE +GLOBAL DEFAULT +7 _start
+.* TLS +GLOBAL DEFAULT +9 ld2
+.* TLS +GLOBAL DEFAULT +9 ld1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* TLS +GLOBAL DEFAULT +9 gd0
+.* TLS +GLOBAL DEFAULT +9 ie0
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe.t b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe.t
new file mode 100644
index 0000000..bb512fd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe.t
@@ -0,0 +1,13 @@
+#source: tls.s
+#as: -a64
+#ld: -melf64ppc tmpdir/libtlslib.so
+#objdump: -sj.tdata
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Contents of section \.tdata:
+ .* 12345678 9abcdef0 23456789 abcdef01  .*
+ .* 3456789a bcdef012 456789ab cdef0123  .*
+ .* 56789abc def01234 6789abcd ef012345  .*
+ .* 789abcde f0123456                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe32.d b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe32.d
new file mode 100644
index 0000000..c69e335
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe32.d
@@ -0,0 +1,47 @@
+#source: tls32.s
+#as: -a32
+#ld: -melf32ppc tmpdir/libtlslib32.so
+#objdump: -dr
+#target: powerpc*-*-*
+
+.*: +file format elf32-powerpc
+
+Disassembly of section \.text:
+
+.* <_start>:
+.*:	80 7f ff f0 	lwz     r3,-16\(r31\)
+.*:	7c 63 12 14 	add     r3,r3,r2
+.*:	38 7f ff f4 	addi    r3,r31,-12
+.*:	48 01 01 85 	bl      .*<__tls_get_addr@plt>
+.*:	3c 62 00 00 	addis   r3,r2,0
+.*:	38 63 90 1c 	addi    r3,r3,-28644
+.*:	3c 62 00 00 	addis   r3,r2,0
+.*:	38 63 10 00 	addi    r3,r3,4096
+.*:	39 23 80 20 	addi    r9,r3,-32736
+.*:	3d 23 00 00 	addis   r9,r3,0
+.*:	81 49 80 24 	lwz     r10,-32732\(r9\)
+.*:	3d 22 00 00 	addis   r9,r2,0
+.*:	a1 49 90 2c 	lhz     r10,-28628\(r9\)
+.*:	89 42 90 30 	lbz     r10,-28624\(r2\)
+.*:	3d 22 00 00 	addis   r9,r2,0
+.*:	99 49 90 34 	stb     r10,-28620\(r9\)
+.*:	3c 62 00 00 	addis   r3,r2,0
+.*:	38 63 90 00 	addi    r3,r3,-28672
+.*:	3c 62 00 00 	addis   r3,r2,0
+.*:	38 63 10 00 	addi    r3,r3,4096
+.*:	91 43 80 04 	stw     r10,-32764\(r3\)
+.*:	3d 23 00 00 	addis   r9,r3,0
+.*:	91 49 80 08 	stw     r10,-32760\(r9\)
+.*:	3d 22 00 00 	addis   r9,r2,0
+.*:	b1 49 90 2c 	sth     r10,-28628\(r9\)
+.*:	a1 42 90 14 	lhz     r10,-28652\(r2\)
+.*:	3d 22 00 00 	addis   r9,r2,0
+.*:	a9 49 90 18 	lha     r10,-28648\(r9\)
+Disassembly of section \.got:
+
+.* <_GLOBAL_OFFSET_TABLE_-0x10>:
+	\.\.\.
+.*:	4e 80 00 21 	blrl
+
+.* <_GLOBAL_OFFSET_TABLE_>:
+.*:	01 81 02 b4 00 00 00 00 00 00 00 00  .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe32.g b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe32.g
new file mode 100644
index 0000000..14b7f8c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe32.g
@@ -0,0 +1,11 @@
+#source: tls32.s
+#as: -a32
+#ld: -melf32ppc tmpdir/libtlslib32.so
+#objdump: -sj.got
+#target: powerpc*-*-*
+
+.*: +file format elf32-powerpc
+
+Contents of section \.got:
+.* 00000000 00000000 00000000 4e800021  .*
+.* 018102b4 00000000 00000000           .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe32.r b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe32.r
new file mode 100644
index 0000000..86a0ab8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe32.r
@@ -0,0 +1,111 @@
+#source: tls32.s
+#source: tlslib32.s
+#as: -a32
+#ld: -melf32ppc
+#readelf: -WSsrl
+#target: powerpc*-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+ +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0
+ +\[[ 0-9]+\] \.interp +.*
+ +\[[ 0-9]+\] \.hash +.*
+ +\[[ 0-9]+\] \.dynsym +.*
+ +\[[ 0-9]+\] \.dynstr +.*
+ +\[[ 0-9]+\] \.rela\.dyn +.*
+ +\[[ 0-9]+\] \.rela\.plt +.*
+ +\[[ 0-9]+\] \.text +PROGBITS +[0-9a-f]+ [0-9a-f]+ 000070 00 +AX +0 +0 +1
+ +\[[ 0-9]+\] \.tdata +PROGBITS +[0-9a-f]+ [0-9a-f]+ 00001c 00 WAT +0 +0 +4
+ +\[[ 0-9]+\] \.tbss +NOBITS +[0-9a-f]+ [0-9a-f]+ 00001c 00 WAT +0 +0 +4
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 08 +WA +4 +0 +4
+ +\[[ 0-9]+\] \.got +PROGBITS +[0-9a-f]+ [0-9a-f]+ 00001c 04 WAX +0 +0 +4
+ +\[[ 0-9]+\] \.plt +NOBITS +.*
+ +\[[ 0-9]+\] \.shstrtab +STRTAB +.*
+ +\[[ 0-9]+\] \.symtab +SYMTAB +.*
+ +\[[ 0-9]+\] \.strtab +STRTAB +.*
+#...
+
+Elf file type is EXEC \(Executable file\)
+Entry point .*
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz MemSiz +Flg Align
+ +PHDR +0x000034 0x01800034 0x01800034 0x000c0 0x000c0 R E 0x4
+ +INTERP +0x0000f4 0x018000f4 0x018000f4 0x00011 0x00011 R +0x1
+ +\[Requesting program interpreter: .*\]
+ +LOAD .* R E 0x10000
+ +LOAD .* RWE 0x10000
+ +DYNAMIC .* RW +0x4
+ +TLS .* 0x0001c 0x00038 R +0x4
+
+ Section to Segment mapping:
+ +Segment Sections\.\.\.
+ +00 +
+ +01 +\.interp 
+ +02 +\.interp \.hash \.dynsym \.dynstr \.rela\.dyn \.rela\.plt \.text 
+ +03 +\.tdata \.dynamic \.got \.plt 
+ +04 +\.dynamic 
+ +05 +\.tdata \.tbss 
+
+Relocation section '\.rela\.dyn' at offset .* contains 2 entries:
+ Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_PPC_TPREL32 +00000000 +gd \+ 0
+[0-9a-f ]+R_PPC_DTPMOD32 +00000000 +ld \+ 0
+
+Relocation section '\.rela\.plt' at offset .* contains 1 entries:
+ Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_PPC_JMP_SLOT[0-9a-f ]+__tls_get_addr \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND 
+.* TLS +GLOBAL DEFAULT +UND gd
+.* FUNC +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +UND ld
+.* NOTYPE +GLOBAL DEFAULT +ABS __end
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND 
+.* SECTION LOCAL +DEFAULT +1 
+.* SECTION LOCAL +DEFAULT +2 
+.* SECTION LOCAL +DEFAULT +3 
+.* SECTION LOCAL +DEFAULT +4 
+.* SECTION LOCAL +DEFAULT +5 
+.* SECTION LOCAL +DEFAULT +6 
+.* SECTION LOCAL +DEFAULT +7 
+.* SECTION LOCAL +DEFAULT +8 
+.* SECTION LOCAL +DEFAULT +9 
+.* SECTION LOCAL +DEFAULT +10 
+.* SECTION LOCAL +DEFAULT +11 
+.* SECTION LOCAL +DEFAULT +12 
+.* TLS +LOCAL +DEFAULT +8 gd4
+.* TLS +LOCAL +DEFAULT +8 ld4
+.* TLS +LOCAL +DEFAULT +8 ld5
+.* TLS +LOCAL +DEFAULT +8 ld6
+.* TLS +LOCAL +DEFAULT +8 ie4
+.* TLS +LOCAL +DEFAULT +8 le4
+.* TLS +LOCAL +DEFAULT +8 le5
+.* OBJECT +LOCAL +HIDDEN +10 _DYNAMIC
+.* OBJECT +LOCAL +HIDDEN +11 _GLOBAL_OFFSET_TABLE_
+.* TLS +GLOBAL DEFAULT +UND gd
+.* TLS +GLOBAL DEFAULT +9 le0
+.* FUNC +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +9 ld0
+.* TLS +GLOBAL DEFAULT +9 le1
+.* TLS +GLOBAL DEFAULT +UND ld
+.* NOTYPE +GLOBAL DEFAULT +7 _start
+.* NOTYPE +GLOBAL DEFAULT +ABS __end
+.* TLS +GLOBAL DEFAULT +9 ld2
+.* TLS +GLOBAL DEFAULT +9 ld1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* TLS +GLOBAL DEFAULT +9 gd0
+.* TLS +GLOBAL DEFAULT +9 ie0
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe32.t b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe32.t
new file mode 100644
index 0000000..2312b33
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexe32.t
@@ -0,0 +1,11 @@
+#source: tls32.s
+#as: -a32
+#ld: -melf32ppc tmpdir/libtlslib32.so
+#objdump: -sj.tdata
+#target: powerpc*-*-*
+
+.*: +file format elf32-powerpc
+
+Contents of section \.tdata:
+.* 12345678 23456789 3456789a 456789ab  .*
+.* 56789abc 6789abcd 789abcde           .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsexetoc.d b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexetoc.d
new file mode 100644
index 0000000..d6a0388
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexetoc.d
@@ -0,0 +1,59 @@
+#source: tlstoc.s
+#as: -a64
+#ld: -melf64ppc tmpdir/libtlslib.so
+#objdump: -dr
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Disassembly of section \.text:
+
+.* <_start-0x18>:
+.*	f8 41 00 28 	std     r2,40\(r1\)
+.*	e9 62 80 70 	ld      r11,-32656\(r2\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 62 80 80 	ld      r11,-32640\(r2\)
+.*	e8 42 80 78 	ld      r2,-32648\(r2\)
+.*	4e 80 04 20 	bctr
+
+.* <_start>:
+.*	38 62 80 08 	addi    r3,r2,-32760
+.*	4b ff ff e5 	bl      .*
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 18 	addi    r3,r2,-32744
+.*	4b ff ff d9 	bl      .*
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	3c 6d 00 00 	addis   r3,r13,0
+.*	60 00 00 00 	nop
+.*	38 63 90 38 	addi    r3,r3,-28616
+.*	3c 6d 00 00 	addis   r3,r13,0
+.*	60 00 00 00 	nop
+.*	38 63 10 00 	addi    r3,r3,4096
+.*	39 23 80 40 	addi    r9,r3,-32704
+.*	3d 23 00 00 	addis   r9,r3,0
+.*	81 49 80 48 	lwz     r10,-32696\(r9\)
+.*	e9 22 80 48 	ld      r9,-32696\(r2\)
+.*	7d 49 18 2a 	ldx     r10,r9,r3
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	a1 49 90 58 	lhz     r10,-28584\(r9\)
+.*	89 4d 90 60 	lbz     r10,-28576\(r13\)
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	99 49 90 68 	stb     r10,-28568\(r9\)
+.*	00 00 00 00 .*
+.*	00 01 02 18 .*
+.*	7d 88 02 a6 	mflr    r12
+.*	42 9f 00 05 	bcl-    20,4\*cr7\+so,.*
+.*	7d 68 02 a6 	mflr    r11
+.*	e8 4b ff f0 	ld      r2,-16\(r11\)
+.*	7d 88 03 a6 	mtlr    r12
+.*	7d 82 5a 14 	add     r12,r2,r11
+.*	e9 6c 00 00 	ld      r11,0\(r12\)
+.*	e8 4c 00 08 	ld      r2,8\(r12\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 6c 00 10 	ld      r11,16\(r12\)
+.*	4e 80 04 20 	bctr
+.*	60 00 00 00 	nop
+.*	60 00 00 00 	nop
+.*	60 00 00 00 	nop
+.*	38 00 00 00 	li      r0,0
+.*	4b ff ff c4 	b       .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsexetoc.g b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexetoc.g
new file mode 100644
index 0000000..df3994c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexetoc.g
@@ -0,0 +1,15 @@
+#source: tlstoc.s
+#as: -a64
+#ld: -melf64ppc tmpdir/libtlslib.so
+#objdump: -sj.got
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Contents of section \.got:
+.* 00000000 10018568 00000000 00000000  .*
+.* 00000000 00000000 00000000 00000000  .*
+.* 00000000 00000000 00000000 00000001  .*
+.* 00000000 00000000 00000000 00000001  .*
+.* 00000000 00000000 ffffffff ffff8050  .*
+.* 00000000 00000000                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsexetoc.r b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexetoc.r
new file mode 100644
index 0000000..e16bbf4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexetoc.r
@@ -0,0 +1,113 @@
+#source: tlslib.s
+#source: tlstoc.s
+#as: -a64
+#ld: -melf64ppc
+#readelf: -WSsrl
+#target: powerpc64*-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+ +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] \.interp +.*
+ +\[[ 0-9]+\] \.hash +.*
+ +\[[ 0-9]+\] \.dynsym +.*
+ +\[[ 0-9]+\] \.dynstr +.*
+ +\[[ 0-9]+\] \.rela\.dyn +.*
+ +\[[ 0-9]+\] \.rela\.plt +.*
+ +\[[ 0-9]+\] \.text +PROGBITS .* 0+b8 0+ +AX +0 +0 +8
+ +\[[ 0-9]+\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
+ +\[[ 0-9]+\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC .* 0+150 10 +WA +4 +0 +8
+ +\[[ 0-9]+\] \.branch_lt +PROGBITS .* 0+ 0+ +WA +0 +0 +8
+ +\[[ 0-9]+\] \.got +PROGBITS .* 0+58 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] \.plt +.*
+ +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
+#...
+
+Elf file type is EXEC \(Executable file\)
+Entry point .*
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+ +PHDR +0x0+40 0x0+10000040 0x0+10000040 0x0+150 0x0+150 R E 0x8
+ +INTERP +0x0+190 0x0+10000190 0x0+10000190 0x0+11 0x0+11 R +0x1
+ +\[Requesting program interpreter: .*\]
+ +LOAD .* R E 0x10000
+ +LOAD .* RW +0x10000
+ +DYNAMIC .* RW +0x8
+ +TLS .* 0x0+38 0x0+70 R +0x8
+
+ Section to Segment mapping:
+ +Segment Sections\.\.\.
+ +0+ +
+ +01 +\.interp 
+ +02 +\.interp \.hash \.dynsym \.dynstr \.rela\.dyn \.rela\.plt \.text 
+ +03 +\.tdata \.dynamic \.got \.plt 
+ +04 +\.dynamic 
+ +05 +\.tdata \.tbss 
+
+Relocation section '\.rela\.dyn' at offset .* contains 3 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_PPC64_DTPMOD64 +0+ gd \+ 0
+[0-9a-f ]+R_PPC64_DTPREL64 +0+ gd \+ 0
+[0-9a-f ]+R_PPC64_DTPMOD64 +0+ ld \+ 0
+
+Relocation section '\.rela\.plt' at offset .* contains 1 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_PPC64_JMP_SLOT +0+ __tls_get_addr \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND 
+.* TLS +GLOBAL DEFAULT +UND gd
+.* FUNC +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +UND ld
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND 
+.* SECTION LOCAL +DEFAULT +1 
+.* SECTION LOCAL +DEFAULT +2 
+.* SECTION LOCAL +DEFAULT +3 
+.* SECTION LOCAL +DEFAULT +4 
+.* SECTION LOCAL +DEFAULT +5 
+.* SECTION LOCAL +DEFAULT +6 
+.* SECTION LOCAL +DEFAULT +7 
+.* SECTION LOCAL +DEFAULT +8 
+.* SECTION LOCAL +DEFAULT +9 
+.* SECTION LOCAL +DEFAULT +10 
+.* SECTION LOCAL +DEFAULT +11 
+.* SECTION LOCAL +DEFAULT +12 
+.* SECTION LOCAL +DEFAULT +13 
+.* TLS +LOCAL +DEFAULT +8 gd4
+.* TLS +LOCAL +DEFAULT +8 ld4
+.* TLS +LOCAL +DEFAULT +8 ld5
+.* TLS +LOCAL +DEFAULT +8 ld6
+.* TLS +LOCAL +DEFAULT +8 ie4
+.* TLS +LOCAL +DEFAULT +8 le4
+.* TLS +LOCAL +DEFAULT +8 le5
+.* NOTYPE +LOCAL +DEFAULT +12 \.Lie0
+.* OBJECT +LOCAL +HIDDEN +10 _DYNAMIC
+.* FUNC +LOCAL +DEFAULT +UND \.__tls_get_addr
+.* TLS +GLOBAL DEFAULT +UND gd
+.* TLS +GLOBAL DEFAULT +9 le0
+.* FUNC +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +9 ld0
+.* TLS +GLOBAL DEFAULT +9 le1
+.* TLS +GLOBAL DEFAULT +UND ld
+.* NOTYPE +GLOBAL DEFAULT +7 _start
+.* TLS +GLOBAL DEFAULT +9 ld2
+.* TLS +GLOBAL DEFAULT +9 ld1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* TLS +GLOBAL DEFAULT +9 gd0
+.* TLS +GLOBAL DEFAULT +9 ie0
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsexetoc.t b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexetoc.t
new file mode 100644
index 0000000..10bfaa4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsexetoc.t
@@ -0,0 +1,13 @@
+#source: tlstoc.s
+#as: -a64
+#ld: -melf64ppc tmpdir/libtlslib.so
+#objdump: -sj.tdata
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Contents of section \.tdata:
+.* 12345678 9abcdef0 23456789 abcdef01  .*
+.* 3456789a bcdef012 456789ab cdef0123  .*
+.* 56789abc def01234 6789abcd ef012345  .*
+.* 789abcde f0123456                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlslib.s b/binutils-2.19/ld/testsuite/ld-powerpc/tlslib.s
new file mode 100644
index 0000000..08f27a2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlslib.s
@@ -0,0 +1,21 @@
+	.global .__tls_get_addr,__tls_get_addr,gd,ld
+	.type .__tls_get_addr,@function
+
+	.section ".opd","aw",@progbits
+__tls_get_addr:
+	.align 3
+	.quad	.__tls_get_addr
+	.quad	.TOC.@tocbase
+	.quad	0
+
+	.section ".tbss","awT",@nobits
+	.align 3
+gd:	.space 8
+
+	.section ".tdata","awT",@progbits
+	.align 2
+ld:	.long 0xc0ffee
+
+	.text
+.__tls_get_addr:
+	blr
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlslib32.s b/binutils-2.19/ld/testsuite/ld-powerpc/tlslib32.s
new file mode 100644
index 0000000..98cd3e9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlslib32.s
@@ -0,0 +1,14 @@
+	.global __tls_get_addr,gd,ld
+	.type __tls_get_addr,@function
+
+	.section ".tbss","awT",@nobits
+	.align 2
+gd:	.space 4
+
+	.section ".tdata","awT",@progbits
+	.align 2
+ld:	.long 0xc0ffee
+
+	.text
+__tls_get_addr:
+	blr
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsso.d b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso.d
new file mode 100644
index 0000000..b1149ae
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso.d
@@ -0,0 +1,75 @@
+#source: tls.s
+#as: -a64
+#ld: -shared -melf64ppc
+#objdump: -dr
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Disassembly of section \.text:
+
+.* <\.__tls_get_addr>:
+.*	f8 41 00 28 	std     r2,40\(r1\)
+.*	e9 62 80 78 	ld      r11,-32648\(r2\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 62 80 88 	ld      r11,-32632\(r2\)
+.*	e8 42 80 80 	ld      r2,-32640\(r2\)
+.*	4e 80 04 20 	bctr
+
+.* <_start>:
+.*	38 62 80 20 	addi    r3,r2,-32736
+.*	4b ff ff e5 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 50 	addi    r3,r2,-32688
+.*	4b ff ff d9 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 38 	addi    r3,r2,-32712
+.*	4b ff ff cd 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 50 	addi    r3,r2,-32688
+.*	4b ff ff c1 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	39 23 80 40 	addi    r9,r3,-32704
+.*	3d 23 00 00 	addis   r9,r3,0
+.*	81 49 80 48 	lwz     r10,-32696\(r9\)
+.*	e9 22 80 30 	ld      r9,-32720\(r2\)
+.*	7d 49 18 2a 	ldx     r10,r9,r3
+.*	e9 22 80 48 	ld      r9,-32696\(r2\)
+.*	7d 49 6a 2e 	lhzx    r10,r9,r13
+.*	89 4d 00 00 	lbz     r10,0\(r13\)
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	99 49 00 00 	stb     r10,0\(r9\)
+.*	38 62 80 08 	addi    r3,r2,-32760
+.*	4b ff ff 8d 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 50 	addi    r3,r2,-32688
+.*	4b ff ff 81 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	f9 43 80 08 	std     r10,-32760\(r3\)
+.*	3d 23 00 00 	addis   r9,r3,0
+.*	91 49 80 10 	stw     r10,-32752\(r9\)
+.*	e9 22 80 18 	ld      r9,-32744\(r2\)
+.*	7d 49 19 2a 	stdx    r10,r9,r3
+.*	e9 22 80 48 	ld      r9,-32696\(r2\)
+.*	7d 49 6b 2e 	sthx    r10,r9,r13
+.*	e9 4d 00 02 	lwa     r10,0\(r13\)
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	a9 49 00 00 	lha     r10,0\(r9\)
+.*	00 00 00 00 .*
+.*	00 01 02 20 .*
+.*	7d 88 02 a6 	mflr    r12
+.*	42 9f 00 05 	bcl-    20,4\*cr7\+so,.*
+.*	7d 68 02 a6 	mflr    r11
+.*	e8 4b ff f0 	ld      r2,-16\(r11\)
+.*	7d 88 03 a6 	mtlr    r12
+.*	7d 82 5a 14 	add     r12,r2,r11
+.*	e9 6c 00 00 	ld      r11,0\(r12\)
+.*	e8 4c 00 08 	ld      r2,8\(r12\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 6c 00 10 	ld      r11,16\(r12\)
+.*	4e 80 04 20 	bctr
+.*	60 00 00 00 	nop
+.*	60 00 00 00 	nop
+.*	60 00 00 00 	nop
+.*	38 00 00 00 	li      r0,0
+.*	4b ff ff c4 	b       .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsso.g b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso.g
new file mode 100644
index 0000000..330cb18
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso.g
@@ -0,0 +1,15 @@
+#source: tls.s
+#as: -a64
+#ld: -shared -melf64ppc
+#objdump: -sj.got
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Contents of section \.got:
+.* 00000000 00018778 00000000 00000000  .*
+.* 00000000 00000000 00000000 00000000  .*
+.* 00000000 00000000 00000000 00000000  .*
+.* 00000000 00000000 00000000 00000000  .*
+.* 00000000 00000000 00000000 00000000  .*
+.* 00000000 00000000 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsso.r b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso.r
new file mode 100644
index 0000000..7b2ee14
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso.r
@@ -0,0 +1,127 @@
+#source: tls.s
+#as: -a64
+#ld: -shared -melf64ppc
+#readelf: -WSsrl
+#target: powerpc64*-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+ +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] \.hash .*
+ +\[[ 0-9]+\] \.dynsym .*
+ +\[[ 0-9]+\] \.dynstr .*
+ +\[[ 0-9]+\] \.rela\.dyn .*
+ +\[[ 0-9]+\] \.rela\.plt .*
+ +\[[ 0-9]+\] \.text .*
+ +\[[ 0-9]+\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
+ +\[[ 0-9]+\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
+ +\[[ 0-9]+\] \.dynamic .*
+ +\[[ 0-9]+\] \.branch_lt .*
+ +\[[ 0-9]+\] \.got .*
+ +\[[ 0-9]+\] \.plt .*
+ +\[[ 0-9]+\] \.shstrtab .*
+ +\[[ 0-9]+\] \.symtab .*
+ +\[[ 0-9]+\] \.strtab .*
+#...
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x[0-9a-f]+
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+ +LOAD .* R E 0x10000
+ +LOAD .* RW +0x10000
+ +DYNAMIC .* RW +0x8
+ +TLS .* 0x0+38 0x0+70 R +0x8
+
+ Section to Segment mapping:
+ +Segment Sections\.\.\.
+ +0+ +\.hash \.dynsym \.dynstr \.rela\.dyn \.rela\.plt \.text 
+ +01 +\.tdata \.dynamic \.got \.plt 
+ +02 +\.dynamic 
+ +03 +\.tdata \.tbss 
+
+Relocation section '\.rela\.dyn' at offset .* contains 16 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_PPC64_TPREL16 +0+60 le0 \+ 0
+[0-9a-f ]+R_PPC64_TPREL16_HA +0+68 le1 \+ 0
+[0-9a-f ]+R_PPC64_TPREL16_LO +0+68 le1 \+ 0
+[0-9a-f ]+R_PPC64_TPREL16_DS +0+105f0 \.tdata \+ 28
+[0-9a-f ]+R_PPC64_TPREL16_HA +0+105f0 \.tdata \+ 30
+[0-9a-f ]+R_PPC64_TPREL16_LO +0+105f0 \.tdata \+ 30
+[0-9a-f ]+R_PPC64_DTPMOD64 +0+
+[0-9a-f ]+R_PPC64_DTPREL64 +0+
+[0-9a-f ]+R_PPC64_DTPREL64 +0+18
+[0-9a-f ]+R_PPC64_DTPMOD64 +0+
+[0-9a-f ]+R_PPC64_DTPMOD64 +0+ gd \+ 0
+[0-9a-f ]+R_PPC64_DTPREL64 +0+ gd \+ 0
+[0-9a-f ]+R_PPC64_DTPREL64 +0+50 ld2 \+ 0
+[0-9a-f ]+R_PPC64_DTPMOD64 +0+38 gd0 \+ 0
+[0-9a-f ]+R_PPC64_DTPREL64 +0+38 gd0 \+ 0
+[0-9a-f ]+R_PPC64_TPREL64 +0+58 ie0 \+ 0
+
+Relocation section '\.rela\.plt' at offset .* contains 1 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_PPC64_JMP_SLOT +0+ __tls_get_addr \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND 
+.* SECTION LOCAL +DEFAULT +6 
+.* SECTION LOCAL +DEFAULT +7 
+.* TLS +GLOBAL DEFAULT +UND gd
+.* TLS +GLOBAL DEFAULT +8 le0
+.* NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +8 ld0
+.* TLS +GLOBAL DEFAULT +8 le1
+.* TLS +GLOBAL DEFAULT +UND ld
+.* NOTYPE +GLOBAL DEFAULT +6 _start
+.* TLS +GLOBAL DEFAULT +8 ld2
+.* TLS +GLOBAL DEFAULT +8 ld1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* TLS +GLOBAL DEFAULT +8 gd0
+.* TLS +GLOBAL DEFAULT +8 ie0
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND 
+.* SECTION LOCAL +DEFAULT +1 
+.* SECTION LOCAL +DEFAULT +2 
+.* SECTION LOCAL +DEFAULT +3 
+.* SECTION LOCAL +DEFAULT +4 
+.* SECTION LOCAL +DEFAULT +5 
+.* SECTION LOCAL +DEFAULT +6 
+.* SECTION LOCAL +DEFAULT +7 
+.* SECTION LOCAL +DEFAULT +8 
+.* SECTION LOCAL +DEFAULT +9 
+.* SECTION LOCAL +DEFAULT +10 
+.* SECTION LOCAL +DEFAULT +11 
+.* SECTION LOCAL +DEFAULT +12 
+.* TLS +LOCAL +DEFAULT +7 gd4
+.* TLS +LOCAL +DEFAULT +7 ld4
+.* TLS +LOCAL +DEFAULT +7 ld5
+.* TLS +LOCAL +DEFAULT +7 ld6
+.* TLS +LOCAL +DEFAULT +7 ie4
+.* TLS +LOCAL +DEFAULT +7 le4
+.* TLS +LOCAL +DEFAULT +7 le5
+.* OBJECT +LOCAL +HIDDEN +ABS _DYNAMIC
+.* NOTYPE +LOCAL +DEFAULT +6 \.__tls_get_addr
+.* TLS +GLOBAL DEFAULT +UND gd
+.* TLS +GLOBAL DEFAULT +8 le0
+.* NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +8 ld0
+.* TLS +GLOBAL DEFAULT +8 le1
+.* TLS +GLOBAL DEFAULT +UND ld
+.* NOTYPE +GLOBAL DEFAULT +6 _start
+.* TLS +GLOBAL DEFAULT +8 ld2
+.* TLS +GLOBAL DEFAULT +8 ld1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* TLS +GLOBAL DEFAULT +8 gd0
+.* TLS +GLOBAL DEFAULT +8 ie0
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsso.t b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso.t
new file mode 100644
index 0000000..63f92f6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso.t
@@ -0,0 +1,13 @@
+#source: tls.s
+#as: -a64
+#ld: -shared -melf64ppc
+#objdump: -sj.tdata
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Contents of section \.tdata:
+.* 12345678 9abcdef0 23456789 abcdef01  .*
+.* 3456789a bcdef012 456789ab cdef0123  .*
+.* 56789abc def01234 6789abcd ef012345  .*
+.* 789abcde f0123456                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsso32.d b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso32.d
new file mode 100644
index 0000000..b4e45d8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso32.d
@@ -0,0 +1,46 @@
+#source: tls32.s
+#as: -a32
+#ld: -shared -melf32ppc
+#objdump: -dr
+#target: powerpc*-*-*
+
+.*: +file format elf32-powerpc
+
+Disassembly of section \.text:
+
+.* <_start>:
+.*:	38 7f ff e0 	addi    r3,r31,-32
+.*:	48 00 00 01 	bl      .*
+.*:	38 7f ff f4 	addi    r3,r31,-12
+.*:	48 00 00 01 	bl      .*
+.*:	38 7f ff e8 	addi    r3,r31,-24
+.*:	48 01 01 95 	bl      .*<__tls_get_addr@plt>
+.*:	38 7f ff f4 	addi    r3,r31,-12
+.*:	48 01 01 8d 	bl      .*<__tls_get_addr@plt>
+.*:	39 23 80 20 	addi    r9,r3,-32736
+.*:	3d 23 00 00 	addis   r9,r3,0
+.*:	81 49 80 24 	lwz     r10,-32732\(r9\)
+.*:	81 3f ff f0 	lwz     r9,-16\(r31\)
+.*:	7d 49 12 2e 	lhzx    r10,r9,r2
+.*:	89 42 00 00 	lbz     r10,0\(r2\)
+.*:	3d 22 00 00 	addis   r9,r2,0
+.*:	99 49 00 00 	stb     r10,0\(r9\)
+.*:	38 7e ff d8 	addi    r3,r30,-40
+.*:	48 00 00 01 	bl      .*
+.*:	38 7e ff f4 	addi    r3,r30,-12
+.*:	48 00 00 01 	bl      .*
+.*:	91 43 80 04 	stw     r10,-32764\(r3\)
+.*:	3d 23 00 00 	addis   r9,r3,0
+.*:	91 49 80 08 	stw     r10,-32760\(r9\)
+.*:	81 3e ff f0 	lwz     r9,-16\(r30\)
+.*:	7d 49 13 2e 	sthx    r10,r9,r2
+.*:	a1 42 00 00 	lhz     r10,0\(r2\)
+.*:	3d 22 00 00 	addis   r9,r2,0
+.*:	a9 49 00 00 	lha     r10,0\(r9\)
+Disassembly of section \.got:
+
+.* <\.got>:
+	\.\.\.
+.*:	4e 80 00 21 	blrl
+.*:	00 01 03 ec 	.*
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsso32.g b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso32.g
new file mode 100644
index 0000000..028e869
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso32.g
@@ -0,0 +1,13 @@
+#source: tls32.s
+#as: -a32
+#ld: -shared -melf32ppc
+#objdump: -sj.got
+#target: powerpc*-*-*
+
+.*: +file format elf32-powerpc
+
+Contents of section \.got:
+.* 00000000 00000000 00000000 00000000  .*
+.* 00000000 00000000 00000000 00000000  .*
+.* 00000000 4e800021 000103ec 00000000  .*
+.* 00000000                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsso32.r b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso32.r
new file mode 100644
index 0000000..b29f2c4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso32.r
@@ -0,0 +1,129 @@
+#source: tls32.s
+#as: -a32
+#ld: -shared -melf32ppc
+#readelf: -WSsrl
+#target: powerpc*-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+ +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] \.hash +.*
+ +\[[ 0-9]+\] \.dynsym +.*
+ +\[[ 0-9]+\] \.dynstr +.*
+ +\[[ 0-9]+\] \.rela\.dyn +.*
+ +\[[ 0-9]+\] \.rela\.plt +.*
+ +\[[ 0-9]+\] \.text +PROGBITS .* 0+70 0+ +AX +0 +0 +1
+ +\[[ 0-9]+\] \.tdata +PROGBITS .* 0+1c 0+ WAT +0 +0 +4
+ +\[[ 0-9]+\] \.tbss +NOBITS .* 0+1c 0+ WAT +0 +0 +4
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC .* 08 +WA +3 +0 +4
+ +\[[ 0-9]+\] \.got +PROGBITS .* 0+34 04 WAX +0 +0 +4
+ +\[[ 0-9]+\] \.plt +.*
+ +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
+#...
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x[0-9a-f]+
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz MemSiz +Flg Align
+ +LOAD .* R E 0x10000
+ +LOAD .* RWE 0x10000
+ +DYNAMIC .* RW +0x4
+ +TLS .* 0x0+1c 0x0+38 R +0x4
+
+ Section to Segment mapping:
+ +Segment Sections\.\.\.
+ +0+ +\.hash \.dynsym \.dynstr \.rela\.dyn \.rela\.plt \.text 
+ +01 +\.tdata \.dynamic \.got \.plt 
+ +02 +\.dynamic 
+ +03 +\.tdata \.tbss 
+
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 18 entries:
+ Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_PPC_REL24 +0+ +__tls_get_addr \+ 0
+[0-9a-f ]+R_PPC_REL24 +0+ +__tls_get_addr \+ 0
+[0-9a-f ]+R_PPC_REL24 +0+ +__tls_get_addr \+ 0
+[0-9a-f ]+R_PPC_REL24 +0+ +__tls_get_addr \+ 0
+[0-9a-f ]+R_PPC_TPREL16 +0+30 +le0 \+ 0
+[0-9a-f ]+R_PPC_TPREL16_HA +0+34 +le1 \+ 0
+[0-9a-f ]+R_PPC_TPREL16_LO +0+34 +le1 \+ 0
+[0-9a-f ]+R_PPC_TPREL16 +0+103d0 +\.tdata \+ 103e4
+[0-9a-f ]+R_PPC_TPREL16_HA +0+103d0 +\.tdata \+ 103e8
+[0-9a-f ]+R_PPC_TPREL16_LO +0+103d0 +\.tdata \+ 103e8
+[0-9a-f ]+R_PPC_DTPMOD32 +0+
+[0-9a-f ]+R_PPC_DTPREL32 +0+
+[0-9a-f ]+R_PPC_DTPMOD32 +0+
+[0-9a-f ]+R_PPC_DTPMOD32 +0+ +gd \+ 0
+[0-9a-f ]+R_PPC_DTPREL32 +0+ +gd \+ 0
+[0-9a-f ]+R_PPC_DTPMOD32 +0+1c +gd0 \+ 0
+[0-9a-f ]+R_PPC_DTPREL32 +0+1c +gd0 \+ 0
+[0-9a-f ]+R_PPC_TPREL32 +0+2c +ie0 \+ 0
+
+Relocation section '\.rela\.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_PPC_JMP_SLOT +0+ +__tls_get_addr \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND 
+.* SECTION LOCAL +DEFAULT +6 
+.* SECTION LOCAL +DEFAULT +7 
+.* TLS +GLOBAL DEFAULT +UND gd
+.* TLS +GLOBAL DEFAULT +8 le0
+.* NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +8 ld0
+.* TLS +GLOBAL DEFAULT +8 le1
+.* TLS +GLOBAL DEFAULT +UND ld
+.* NOTYPE +GLOBAL DEFAULT +6 _start
+.* NOTYPE +GLOBAL DEFAULT +ABS __end
+.* TLS +GLOBAL DEFAULT +8 ld2
+.* TLS +GLOBAL DEFAULT +8 ld1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* TLS +GLOBAL DEFAULT +8 gd0
+.* TLS +GLOBAL DEFAULT +8 ie0
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND 
+.* SECTION LOCAL +DEFAULT +1 
+.* SECTION LOCAL +DEFAULT +2 
+.* SECTION LOCAL +DEFAULT +3 
+.* SECTION LOCAL +DEFAULT +4 
+.* SECTION LOCAL +DEFAULT +5 
+.* SECTION LOCAL +DEFAULT +6 
+.* SECTION LOCAL +DEFAULT +7 
+.* SECTION LOCAL +DEFAULT +8 
+.* SECTION LOCAL +DEFAULT +9 
+.* SECTION LOCAL +DEFAULT +10 
+.* SECTION LOCAL +DEFAULT +11 
+.* TLS +LOCAL +DEFAULT +7 gd4
+.* TLS +LOCAL +DEFAULT +7 ld4
+.* TLS +LOCAL +DEFAULT +7 ld5
+.* TLS +LOCAL +DEFAULT +7 ld6
+.* TLS +LOCAL +DEFAULT +7 ie4
+.* TLS +LOCAL +DEFAULT +7 le4
+.* TLS +LOCAL +DEFAULT +7 le5
+.* OBJECT +LOCAL +HIDDEN +ABS _DYNAMIC
+.* OBJECT +LOCAL +HIDDEN +ABS _GLOBAL_OFFSET_TABLE_
+.* TLS +GLOBAL DEFAULT +UND gd
+.* TLS +GLOBAL DEFAULT +8 le0
+.* NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +8 ld0
+.* TLS +GLOBAL DEFAULT +8 le1
+.* TLS +GLOBAL DEFAULT +UND ld
+.* NOTYPE +GLOBAL DEFAULT +6 _start
+.* NOTYPE +GLOBAL DEFAULT +ABS __end
+.* TLS +GLOBAL DEFAULT +8 ld2
+.* TLS +GLOBAL DEFAULT +8 ld1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* TLS +GLOBAL DEFAULT +8 gd0
+.* TLS +GLOBAL DEFAULT +8 ie0
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlsso32.t b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso32.t
new file mode 100644
index 0000000..4190a9a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlsso32.t
@@ -0,0 +1,11 @@
+#source: tls32.s
+#as: -a32
+#ld: -shared -melf32ppc
+#objdump: -sj.tdata
+#target: powerpc*-*-*
+
+.*: +file format elf32-powerpc
+
+Contents of section \.tdata:
+.* 12345678 23456789 3456789a 456789ab  .*
+.* 56789abc 6789abcd 789abcde           .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlstoc.d b/binutils-2.19/ld/testsuite/ld-powerpc/tlstoc.d
new file mode 100644
index 0000000..cfa8aba
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlstoc.d
@@ -0,0 +1,37 @@
+#source: tlslib.s
+#source: tlstoc.s
+#as: -a64
+#ld: -melf64ppc
+#objdump: -dr
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Disassembly of section \.text:
+
+.* <\.__tls_get_addr>:
+.*	4e 80 00 20 	blr
+
+.* <_start>:
+.*	3c 6d 00 00 	addis   r3,r13,0
+.*	60 00 00 00 	nop
+.*	38 63 90 40 	addi    r3,r3,-28608
+.*	3c 6d 00 00 	addis   r3,r13,0
+.*	60 00 00 00 	nop
+.*	38 63 10 00 	addi    r3,r3,4096
+.*	3c 6d 00 00 	addis   r3,r13,0
+.*	60 00 00 00 	nop
+.*	38 63 90 48 	addi    r3,r3,-28600
+.*	3c 6d 00 00 	addis   r3,r13,0
+.*	60 00 00 00 	nop
+.*	38 63 10 00 	addi    r3,r3,4096
+.*	39 23 80 50 	addi    r9,r3,-32688
+.*	3d 23 00 00 	addis   r9,r3,0
+.*	81 49 80 58 	lwz     r10,-32680\(r9\)
+.*	e9 22 80 40 	ld      r9,-32704\(r2\)
+.*	7d 49 18 2a 	ldx     r10,r9,r3
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	a1 49 90 68 	lhz     r10,-28568\(r9\)
+.*	89 4d 90 70 	lbz     r10,-28560\(r13\)
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	99 49 90 78 	stb     r10,-28552\(r9\)
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlstoc.g b/binutils-2.19/ld/testsuite/ld-powerpc/tlstoc.g
new file mode 100644
index 0000000..9ae4100
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlstoc.g
@@ -0,0 +1,15 @@
+#source: tlslib.s
+#source: tlstoc.s
+#as: -a64
+#ld: -melf64ppc
+#objdump: -sj.got
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Contents of section \.got:
+ 100101a0 00000000 00000001 00000000 00000000  .*
+ 100101b0 00000000 00000001 00000000 00000000  .*
+ 100101c0 00000000 00000001 00000000 00000000  .*
+ 100101d0 00000000 00000001 00000000 00000000  .*
+ 100101e0 ffffffff ffff8060 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlstoc.s b/binutils-2.19/ld/testsuite/ld-powerpc/tlstoc.s
new file mode 100644
index 0000000..5008d89
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlstoc.s
@@ -0,0 +1,88 @@
+	.section ".tbss","awT",@nobits
+	.global _start,gd0,ld0,ld1,ld2,ie0,le0,le1
+	.align 3
+gd0:	.space 8
+ld0:	.space 8
+ld1:	.space 8
+ld2:	.space 8
+ie0:	.space 8
+le0:	.space 8
+le1:	.space 8
+
+	.section ".tdata","awT",@progbits
+	.align 3
+gd4:	.quad 0x123456789abcdef0
+ld4:	.quad 0x23456789abcdef01
+ld5:	.quad 0x3456789abcdef012
+ld6:	.quad 0x456789abcdef0123
+ie4:	.quad 0x56789abcdef01234
+le4:	.quad 0x6789abcdef012345
+le5:	.quad 0x789abcdef0123456
+
+	.text
+_start:
+#extern syms
+#GD
+ addi 3,2,.Lgd@toc
+ bl .__tls_get_addr
+ nop
+ .section .toc,"aw",@progbits
+.Lgd:
+ .quad gd@dtpmod
+ .quad gd@dtprel
+ .text
+#LD
+ addi 3,2,.Lld@toc
+ bl .__tls_get_addr
+ nop
+ .section .toc,"aw",@progbits
+.Lld:
+ .quad ld@dtpmod
+ .quad 0
+ .text
+
+#global syms
+#GD
+ addi 3,2,.Lgd0@toc
+ bl .__tls_get_addr
+ nop
+ .section .toc,"aw",@progbits
+.Lgd0:
+ .quad gd0@dtpmod
+ .quad gd0@dtprel
+ .text
+#LD
+ addi 3,2,.Lld0@toc
+ bl .__tls_get_addr
+ nop
+ .section .toc,"aw",@progbits
+.Lld0:
+ .quad ld0@dtpmod
+ .quad 0
+ .text
+
+ addi 9,3,ld0@dtprel
+
+ addis 9,3,ld1@dtprel@ha
+ lwz 10,ld1@dtprel@l(9)
+
+ ld 9,.Lld2@toc(2)
+ ldx 10,9,3
+ .section .toc,"aw",@progbits
+.Lld2:
+ .quad ld2@dtprel
+ .text
+
+#IE
+ ld 9,.Lie0@toc(2)
+ lhzx 10,9,.Lie0@tls
+ .section .toc,"aw",@progbits
+.Lie0:
+ .quad ie0@tprel
+ .text
+
+#LE
+ lbz 10,le0@tprel(13)		#R_PPC64_TPREL16	le0
+
+ addis 9,13,le1@tprel@ha	#R_PPC64_TPREL16_HA	le1
+ stb 10,le1@tprel@l(9)		#R_PPC64_TPREL16_LO	le1
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlstoc.t b/binutils-2.19/ld/testsuite/ld-powerpc/tlstoc.t
new file mode 100644
index 0000000..5a8129a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlstoc.t
@@ -0,0 +1,14 @@
+#source: tlslib.s
+#source: tlstoc.s
+#as: -a64
+#ld: -melf64ppc
+#objdump: -sj.tdata
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Contents of section \.tdata:
+ 10010148 00c0ffee 00000000 12345678 9abcdef0  .*
+ 10010158 23456789 abcdef01 3456789a bcdef012  .*
+ 10010168 456789ab cdef0123 56789abc def01234  .*
+ 10010178 6789abcd ef012345 789abcde f0123456  .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlstocso.d b/binutils-2.19/ld/testsuite/ld-powerpc/tlstocso.d
new file mode 100644
index 0000000..deaf2a7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlstocso.d
@@ -0,0 +1,59 @@
+#source: tlstoc.s
+#as: -a64
+#ld: -shared -melf64ppc
+#objdump: -dr
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Disassembly of section \.text:
+
+.* <\.__tls_get_addr>:
+.*	f8 41 00 28 	std     r2,40\(r1\)
+.*	e9 62 80 70 	ld      r11,-32656\(r2\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 62 80 80 	ld      r11,-32640\(r2\)
+.*	e8 42 80 78 	ld      r2,-32648\(r2\)
+.*	4e 80 04 20 	bctr
+
+.* <_start>:
+.*	38 62 80 08 	addi    r3,r2,-32760
+.*	4b ff ff e5 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 18 	addi    r3,r2,-32744
+.*	4b ff ff d9 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 28 	addi    r3,r2,-32728
+.*	4b ff ff cd 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	38 62 80 38 	addi    r3,r2,-32712
+.*	4b ff ff c1 	bl      .* <\.__tls_get_addr>
+.*	e8 41 00 28 	ld      r2,40\(r1\)
+.*	39 23 80 40 	addi    r9,r3,-32704
+.*	3d 23 00 00 	addis   r9,r3,0
+.*	81 49 80 48 	lwz     r10,-32696\(r9\)
+.*	e9 22 80 48 	ld      r9,-32696\(r2\)
+.*	7d 49 18 2a 	ldx     r10,r9,r3
+.*	e9 22 80 50 	ld      r9,-32688\(r2\)
+.*	7d 49 6a 2e 	lhzx    r10,r9,r13
+.*	89 4d 00 00 	lbz     r10,0\(r13\)
+.*	3d 2d 00 00 	addis   r9,r13,0
+.*	99 49 00 00 	stb     r10,0\(r9\)
+.*	00 00 00 00 .*
+.*	00 01 02 18 .*
+.*	7d 88 02 a6 	mflr    r12
+.*	42 9f 00 05 	bcl-    20,4\*cr7\+so,.*
+.*	7d 68 02 a6 	mflr    r11
+.*	e8 4b ff f0 	ld      r2,-16\(r11\)
+.*	7d 88 03 a6 	mtlr    r12
+.*	7d 82 5a 14 	add     r12,r2,r11
+.*	e9 6c 00 00 	ld      r11,0\(r12\)
+.*	e8 4c 00 08 	ld      r2,8\(r12\)
+.*	7d 69 03 a6 	mtctr   r11
+.*	e9 6c 00 10 	ld      r11,16\(r12\)
+.*	4e 80 04 20 	bctr
+.*	60 00 00 00 	nop
+.*	60 00 00 00 	nop
+.*	60 00 00 00 	nop
+.*	38 00 00 00 	li      r0,0
+.*	4b ff ff c4 	b       .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlstocso.g b/binutils-2.19/ld/testsuite/ld-powerpc/tlstocso.g
new file mode 100644
index 0000000..d670a21
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlstocso.g
@@ -0,0 +1,15 @@
+#source: tlstoc.s
+#as: -a64
+#ld: -shared -melf64ppc
+#objdump: -sj.got
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Contents of section \.got:
+.* 00000000 000186c0 00000000 00000000  .*
+.* 00000000 00000000 00000000 00000000  .*
+.* 00000000 00000000 00000000 00000000  .*
+.* 00000000 00000000 00000000 00000000  .*
+.* 00000000 00000000 00000000 00000000  .*
+.* 00000000 00000000                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlstocso.r b/binutils-2.19/ld/testsuite/ld-powerpc/tlstocso.r
new file mode 100644
index 0000000..9c9e01c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlstocso.r
@@ -0,0 +1,123 @@
+#source: tlstoc.s
+#as: -a64
+#ld: -shared -melf64ppc
+#readelf: -WSsrl
+#target: powerpc64*-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+ +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] \.hash .*
+ +\[[ 0-9]+\] \.dynsym .*
+ +\[[ 0-9]+\] \.dynstr .*
+ +\[[ 0-9]+\] \.rela\.dyn .*
+ +\[[ 0-9]+\] \.rela\.plt .*
+ +\[[ 0-9]+\] \.text .*
+ +\[[ 0-9]+\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
+ +\[[ 0-9]+\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
+ +\[[ 0-9]+\] \.dynamic .*
+ +\[[ 0-9]+\] \.branch_lt .*
+ +\[[ 0-9]+\] \.got .*
+ +\[[ 0-9]+\] \.plt .*
+ +\[[ 0-9]+\] \.shstrtab .*
+ +\[[ 0-9]+\] \.symtab .*
+ +\[[ 0-9]+\] \.strtab .*
+#...
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x[0-9a-f]+
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+ +LOAD .* R E 0x10000
+ +LOAD .* RW +0x10000
+ +DYNAMIC .* RW +0x8
+ +TLS .* 0x0+38 0x0+70 R +0x8
+
+ Section to Segment mapping:
+ +Segment Sections\.\.\.
+ +0+ +\.hash \.dynsym \.dynstr \.rela\.dyn \.rela\.plt \.text 
+ +01 +\.tdata \.dynamic \.got \.plt 
+ +02 +\.dynamic 
+ +03 +\.tdata \.tbss 
+
+Relocation section '\.rela\.dyn' at offset .* contains 11 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_PPC64_TPREL16 +0+60 le0 \+ 0
+[0-9a-f ]+R_PPC64_TPREL16_HA +0+68 le1 \+ 0
+[0-9a-f ]+R_PPC64_TPREL16_LO +0+68 le1 \+ 0
+[0-9a-f ]+R_PPC64_DTPMOD64 +0+ gd \+ 0
+[0-9a-f ]+R_PPC64_DTPREL64 +0+ gd \+ 0
+[0-9a-f ]+R_PPC64_DTPMOD64 +0+ ld \+ 0
+[0-9a-f ]+R_PPC64_DTPMOD64 +0+38 gd0 \+ 0
+[0-9a-f ]+R_PPC64_DTPREL64 +0+38 gd0 \+ 0
+[0-9a-f ]+R_PPC64_DTPMOD64 +0+40 ld0 \+ 0
+[0-9a-f ]+R_PPC64_DTPREL64 +0+50 ld2 \+ 0
+[0-9a-f ]+R_PPC64_TPREL64 +0+58 ie0 \+ 0
+
+Relocation section '\.rela\.plt' at offset .* contains 1 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_PPC64_JMP_SLOT +0+ __tls_get_addr \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND 
+.* SECTION LOCAL +DEFAULT +6 
+.* SECTION LOCAL +DEFAULT +7 
+.* TLS +GLOBAL DEFAULT +UND gd
+.* TLS +GLOBAL DEFAULT +8 le0
+.* NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +8 ld0
+.* TLS +GLOBAL DEFAULT +8 le1
+.* TLS +GLOBAL DEFAULT +UND ld
+.* NOTYPE +GLOBAL DEFAULT +6 _start
+.* TLS +GLOBAL DEFAULT +8 ld2
+.* TLS +GLOBAL DEFAULT +8 ld1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* TLS +GLOBAL DEFAULT +8 gd0
+.* TLS +GLOBAL DEFAULT +8 ie0
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND 
+.* SECTION LOCAL +DEFAULT +1 
+.* SECTION LOCAL +DEFAULT +2 
+.* SECTION LOCAL +DEFAULT +3 
+.* SECTION LOCAL +DEFAULT +4 
+.* SECTION LOCAL +DEFAULT +5 
+.* SECTION LOCAL +DEFAULT +6 
+.* SECTION LOCAL +DEFAULT +7 
+.* SECTION LOCAL +DEFAULT +8 
+.* SECTION LOCAL +DEFAULT +9 
+.* SECTION LOCAL +DEFAULT +10 
+.* SECTION LOCAL +DEFAULT +11 
+.* SECTION LOCAL +DEFAULT +12 
+.* TLS +LOCAL +DEFAULT +7 gd4
+.* TLS +LOCAL +DEFAULT +7 ld4
+.* TLS +LOCAL +DEFAULT +7 ld5
+.* TLS +LOCAL +DEFAULT +7 ld6
+.* TLS +LOCAL +DEFAULT +7 ie4
+.* TLS +LOCAL +DEFAULT +7 le4
+.* TLS +LOCAL +DEFAULT +7 le5
+.* NOTYPE +LOCAL +DEFAULT +11 \.Lie0
+.* OBJECT +LOCAL +HIDDEN +ABS _DYNAMIC
+.* NOTYPE +LOCAL +DEFAULT +6 \.__tls_get_addr
+.* TLS +GLOBAL DEFAULT +UND gd
+.* TLS +GLOBAL DEFAULT +8 le0
+.* NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +8 ld0
+.* TLS +GLOBAL DEFAULT +8 le1
+.* TLS +GLOBAL DEFAULT +UND ld
+.* NOTYPE +GLOBAL DEFAULT +6 _start
+.* TLS +GLOBAL DEFAULT +8 ld2
+.* TLS +GLOBAL DEFAULT +8 ld1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* TLS +GLOBAL DEFAULT +8 gd0
+.* TLS +GLOBAL DEFAULT +8 ie0
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/tlstocso.t b/binutils-2.19/ld/testsuite/ld-powerpc/tlstocso.t
new file mode 100644
index 0000000..fe9def4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/tlstocso.t
@@ -0,0 +1,13 @@
+#source: tlstoc.s
+#as: -a64
+#ld: -shared -melf64ppc
+#objdump: -sj.tdata
+#target: powerpc64*-*-*
+
+.*: +file format elf64-powerpc
+
+Contents of section \.tdata:
+.* 12345678 9abcdef0 23456789 abcdef01  .*
+.* 3456789a bcdef012 456789ab cdef0123  .*
+.* 56789abc def01234 6789abcd ef012345  .*
+.* 789abcde f0123456                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.dd b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.dd
new file mode 100644
index 0000000..1c1861e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.dd
@@ -0,0 +1,56 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+00080800 <_PROCEDURE_LINKAGE_TABLE_>:
+   80800:	81 9e 00 08 	lwz     r12,8\(r30\)
+   80804:	7d 89 03 a6 	mtctr   r12
+   80808:	81 9e 00 04 	lwz     r12,4\(r30\)
+   8080c:	4e 80 04 20 	bctr
+   80810:	60 00 00 00 	nop
+   80814:	60 00 00 00 	nop
+   80818:	60 00 00 00 	nop
+   8081c:	60 00 00 00 	nop
+   80820:	3d 9e 00 00 	addis   r12,r30,0
+   80824:	81 8c 00 0c 	lwz     r12,12\(r12\)
+   80828:	7d 89 03 a6 	mtctr   r12
+   8082c:	4e 80 04 20 	bctr
+   80830:	39 60 00 00 	li      r11,0
+   80834:	4b ff ff cc 	b       80800 <_PROCEDURE_LINKAGE_TABLE_>
+   80838:	60 00 00 00 	nop
+   8083c:	60 00 00 00 	nop
+   80840:	3d 9e 00 00 	addis   r12,r30,0
+   80844:	81 8c 00 10 	lwz     r12,16\(r12\)
+   80848:	7d 89 03 a6 	mtctr   r12
+   8084c:	4e 80 04 20 	bctr
+   80850:	39 60 00 01 	li      r11,1
+   80854:	4b ff ff ac 	b       80800 <_PROCEDURE_LINKAGE_TABLE_>
+   80858:	60 00 00 00 	nop
+   8085c:	60 00 00 00 	nop
+Disassembly of section \.text:
+
+00080c00 <foo>:
+   80c00:	94 21 ff e8 	stwu    r1,-24\(r1\)
+   80c04:	7c 08 02 a6 	mflr    r0
+   80c08:	90 01 00 1c 	stw     r0,28\(r1\)
+   80c0c:	3f c0 00 00 	lis     r30,0
+   80c10:	83 de 00 00 	lwz     r30,0\(r30\)
+   80c14:	83 de 00 00 	lwz     r30,0\(r30\)
+   80c18:	80 3e 00 14 	lwz     r1,20\(r30\)
+   80c1c:	80 01 00 00 	lwz     r0,0\(r1\)
+   80c20:	38 00 00 01 	li      r0,1
+   80c24:	90 01 00 00 	stw     r0,0\(r1\)
+   80c28:	48 00 00 1d 	bl      80c44 <slocal>
+   80c2c:	4b ff fc 15 	bl      80840 <_PROCEDURE_LINKAGE_TABLE_\+0x40>
+   80c30:	4b ff fb f1 	bl      80820 <_PROCEDURE_LINKAGE_TABLE_\+0x20>
+   80c34:	80 01 00 1c 	lwz     r0,28\(r1\)
+   80c38:	7c 08 03 a6 	mtlr    r0
+   80c3c:	38 21 00 18 	addi    r1,r1,24
+   80c40:	4e 80 00 20 	blr
+
+00080c44 <slocal>:
+   80c44:	4e 80 00 20 	blr
+
+00080c48 <sglobal>:
+   80c48:	4e 80 00 20 	blr
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.nd b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.nd
new file mode 100644
index 0000000..cbc1c8c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.nd
@@ -0,0 +1,9 @@
+#...
+Symbol table '\.dynsym' .*:
+#...
+.*: 00090400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
+#...
+Symbol table '\.symtab' .*:
+#...
+.*: 00090400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.rd b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.rd
new file mode 100644
index 0000000..40a5d55
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.rd
@@ -0,0 +1,13 @@
+
+Relocation section '\.rela\.plt' at offset .* contains 2 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+0009040c  .*15 R_PPC_JMP_SLOT    00000000   sexternal \+ 0
+00090410  .*15 R_PPC_JMP_SLOT    00080c48   sglobal \+ 0
+
+Relocation section '\.rela\.dyn' at offset .* contains 5 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+00090800  00000016 R_PPC_RELATIVE * 00080c44
+00080c0e  .*06 R_PPC_ADDR16_HA   00000000   __GOTT_BASE__ \+ 0
+00080c12  .*04 R_PPC_ADDR16_LO   00000000   __GOTT_BASE__ \+ 0
+00080c16  .*03 R_PPC_ADDR16      00000000   __GOTT_INDEX__ \+ 0
+00090414  .*14 R_PPC_GLOB_DAT    00090c00   x \+ 0
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.s b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.s
new file mode 100644
index 0000000..9dfcb0f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.s
@@ -0,0 +1,38 @@
+	.text
+	.globl	foo
+	.type	foo, @function
+foo:
+	stwu	r1,-24(r1)
+	mflr	r0
+	stw	r0,28(r1)
+	lis	r30,__GOTT_BASE__@ha
+	lwz	r30,__GOTT_BASE__@l(r30)
+	lwz	r30,__GOTT_INDEX__(r30)
+	lwz	r1,x@got(r30)
+	lwz	r0,0(r1)
+	addi	r0,r0,1
+	stw	r0,0(r1)
+	bl	slocal
+	bl	sglobal@plt
+	bl	sexternal@plt
+	lwz	r0,28(r1)
+	mtlr	r0
+	addi	r1,r1,24
+	blr
+	.size	foo, .-foo
+
+	.type	slocal, @function
+slocal:
+	blr
+	.size	slocal, .-slocal
+
+	.globl	sglobal
+	.type	sglobal, @function
+sglobal:
+	blr
+	.size	sglobal, .-sglobal
+
+	.data
+	.4byte	slocal
+
+	.comm	x,4,4
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.sd b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.sd
new file mode 100644
index 0000000..1d2ed5c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.sd
@@ -0,0 +1,12 @@
+#...
+Program Headers:
+  Type .* Flg Align
+  LOAD .* R E 0x10000
+  LOAD .* RW  0x10000
+  DYNAMIC .* RW  0x4
+
+ Section to Segment mapping:
+  Segment Sections\.\.\.
+   00 .* \.plt .*
+   01 .* \.got .*
+   02 .* \.dynamic $
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.td b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.td
new file mode 100644
index 0000000..9f223e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-lib.td
@@ -0,0 +1,3 @@
+#...
+ 0x0+16 \(TEXTREL\) +0x0
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-static.d b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-static.d
new file mode 100644
index 0000000..4c2d1fd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1-static.d
@@ -0,0 +1,4 @@
+#name: VxWorks executable test 1 (static)
+#source: vxworks1.s -mregnames
+#ld: tmpdir/libvxworks1.so -Tvxworks1.ld
+#error: Dynamic sections created in non-dynamic link
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1.dd b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1.dd
new file mode 100644
index 0000000..09e5a6a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1.dd
@@ -0,0 +1,48 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+00080800 <_PROCEDURE_LINKAGE_TABLE_>:
+   80800:	3d 80 00 09 	lis     r12,9
+			80802: R_PPC_ADDR16_HA	_GLOBAL_OFFSET_TABLE_
+   80804:	39 8c 04 00 	addi    r12,r12,1024
+			80806: R_PPC_ADDR16_LO	_GLOBAL_OFFSET_TABLE_
+   80808:	80 0c 00 08 	lwz     r0,8\(r12\)
+   8080c:	7c 09 03 a6 	mtctr   r0
+   80810:	81 8c 00 04 	lwz     r12,4\(r12\)
+   80814:	4e 80 04 20 	bctr
+   80818:	60 00 00 00 	nop
+   8081c:	60 00 00 00 	nop
+   80820:	3d 80 00 09 	lis     r12,9
+			80822: R_PPC_ADDR16_HA	_GLOBAL_OFFSET_TABLE_\+0xc
+   80824:	81 8c 04 0c 	lwz     r12,1036\(r12\)
+			80826: R_PPC_ADDR16_LO	_GLOBAL_OFFSET_TABLE_\+0xc
+   80828:	7d 89 03 a6 	mtctr   r12
+   8082c:	4e 80 04 20 	bctr
+   80830:	39 60 00 00 	li      r11,0
+   80834:	4b ff ff cc 	b       80800 <_PROCEDURE_LINKAGE_TABLE_>
+   80838:	60 00 00 00 	nop
+   8083c:	60 00 00 00 	nop
+   80840:	3d 80 00 09 	lis     r12,9
+			80842: R_PPC_ADDR16_HA	_GLOBAL_OFFSET_TABLE_\+0x10
+   80844:	81 8c 04 10 	lwz     r12,1040\(r12\)
+			80846: R_PPC_ADDR16_LO	_GLOBAL_OFFSET_TABLE_\+0x10
+   80848:	7d 89 03 a6 	mtctr   r12
+   8084c:	4e 80 04 20 	bctr
+   80850:	39 60 00 01 	li      r11,1
+   80854:	4b ff ff ac 	b       80800 <_PROCEDURE_LINKAGE_TABLE_>
+   80858:	60 00 00 00 	nop
+   8085c:	60 00 00 00 	nop
+Disassembly of section \.text:
+
+00080c00 <_start>:
+   80c00:	4b ff fc 41 	bl      80840 <_PROCEDURE_LINKAGE_TABLE_\+0x40>
+			80c00: R_PPC_PLTREL24	\.plt\+0x40
+   80c04:	48 00 00 09 	bl      80c0c <sexternal>
+			80c04: R_PPC_PLTREL24	sexternal
+   80c08:	4b ff fc 19 	bl      80820 <_PROCEDURE_LINKAGE_TABLE_\+0x20>
+			80c08: R_PPC_PLTREL24	\.plt\+0x20
+
+00080c0c <sexternal>:
+   80c0c:	4e 80 00 20 	blr
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1.ld b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1.ld
new file mode 100644
index 0000000..ce750b0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1.ld
@@ -0,0 +1,30 @@
+SECTIONS
+{
+  . = 0x80000;
+  .interp : { *(.interp) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+
+  . = ALIGN (0x400);
+  .rela.dyn : { *(.rela.dyn) }
+  .rela.plt : { *(.rela.plt) }
+
+  . = ALIGN (0x400);
+  .plt : { *(.plt) }
+
+  . = ALIGN (0x400);
+  .text : { *(.text) }
+
+  . = ALIGN (0x10000);
+  .dynamic : { *(.dynamic) }
+
+  . = ALIGN (0x400);
+  .got : { *(.got.plt) *(.got) }
+
+  . = ALIGN (0x400);
+  .data : { *(.data) }
+
+  . = ALIGN (0x400);
+  .bss : { *(.bss) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1.rd b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1.rd
new file mode 100644
index 0000000..27d2404
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1.rd
@@ -0,0 +1,22 @@
+
+Relocation section '\.rela\.plt' at offset .* contains 2 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+0009040c  .*15 R_PPC_JMP_SLOT    00080820   sglobal \+ 0
+00090410  .*15 R_PPC_JMP_SLOT    00080840   foo \+ 0
+
+Relocation section '\.rela\.text' at offset .* contains 3 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+00080c00  .*12 R_PPC_PLTREL24    00080800   \.plt \+ 40
+00080c04  .*12 R_PPC_PLTREL24    00080c0c   sexternal \+ 0
+00080c08  .*12 R_PPC_PLTREL24    00080800   \.plt \+ 20
+
+Relocation section '\.rela\.plt\.unloaded' at offset .* contains 8 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+00080802  .*06 R_PPC_ADDR16_HA   00090400   _GLOBAL_OFFSET_TABLE_ \+ 0
+00080806  .*04 R_PPC_ADDR16_LO   00090400   _GLOBAL_OFFSET_TABLE_ \+ 0
+00080822  .*06 R_PPC_ADDR16_HA   00090400   _GLOBAL_OFFSET_TABLE_ \+ c
+00080826  .*04 R_PPC_ADDR16_LO   00090400   _GLOBAL_OFFSET_TABLE_ \+ c
+0009040c  .*01 R_PPC_ADDR32      00080800   _PROCEDURE_LINKAGE_TAB.* \+ 30
+00080842  .*06 R_PPC_ADDR16_HA   00090400   _GLOBAL_OFFSET_TABLE_ \+ 10
+00080846  .*04 R_PPC_ADDR16_LO   00090400   _GLOBAL_OFFSET_TABLE_ \+ 10
+00090410  .*01 R_PPC_ADDR32      00080800   _PROCEDURE_LINKAGE_TAB.* \+ 50
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1.s b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1.s
new file mode 100644
index 0000000..cd54d57
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks1.s
@@ -0,0 +1,14 @@
+	.text
+	.globl	_start
+	.type	_start,@function
+_start:
+	bl	foo@plt
+	bl	sexternal@plt
+	bl	sglobal@plt
+	.size	_start, .-_start
+
+	.globl	sexternal
+	.type	sexternal,@function
+sexternal:
+	blr
+	.size	sexternal, .-sexternal
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/vxworks2-static.sd b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks2-static.sd
new file mode 100644
index 0000000..55fc529
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks2-static.sd
@@ -0,0 +1,9 @@
+#...
+Elf file type is EXEC \(Executable file\)
+Entry point 0x80000
+#...
+Program Headers:
+  Type .*
+  LOAD .* 0x00080000 0x00080000 .* R E 0x10000
+
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/vxworks2.s b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks2.s
new file mode 100644
index 0000000..5e8d73a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks2.s
@@ -0,0 +1,5 @@
+	.globl	_start
+	.type	_start,@function
+_start:
+	blr
+	.end	_start
diff --git a/binutils-2.19/ld/testsuite/ld-powerpc/vxworks2.sd b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks2.sd
new file mode 100644
index 0000000..0876568
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-powerpc/vxworks2.sd
@@ -0,0 +1,13 @@
+#...
+Elf file type is EXEC \(Executable file\)
+Entry point 0x80400
+#...
+Program Headers:
+  Type .*
+  PHDR .*
+#...
+  LOAD .* 0x00080000 0x00080000 .* R E 0x10000
+  LOAD .* 0x00090000 0x00090000 .* RW  0x10000
+  DYNAMIC .*
+
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-s390/s390.exp b/binutils-2.19/ld/testsuite/ld-s390/s390.exp
new file mode 100644
index 0000000..47772ee
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/s390.exp
@@ -0,0 +1,75 @@
+# Expect script for ld-s390 tests
+#   Copyright (C) 2003, 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Test s390 linking; all types of relocs.  This tests the assembler and
+# tools like objdump as well as the linker.
+
+if { !([istarget "s390-*-*"] || [istarget "s390x-*-*"]) } {
+    return
+}
+
+# List contains test-items with 3 items followed by 2 lists:
+# 0:name 1:ld options 2:assembler options
+# 3:filenames of assembler files 4: action and options. 5: name of output file
+
+# Actions:
+# objdump: Apply objdump options on result.  Compare with regex (last arg).
+# nm: Apply nm options on result.  Compare with regex (last arg).
+# readelf: Apply readelf options on result.  Compare with regex (last arg).
+
+set s390tests {
+    {"TLS -fpic -shared transitions" "-shared -melf_s390"
+     "-m31" {tlspic1.s tlspic2.s}
+     {{readelf -Ssrl tlspic.rd} {objdump -dzrj.text tlspic.dd}
+      {objdump -sj.got tlspic.sd} {objdump -sj.tdata tlspic.td}}
+     "libtlspic.so"}
+    {"Helper shared library" "-shared -melf_s390"
+     "-m31" {tlslib.s} {} "libtlslib.so"}
+    {"TLS -fpic and -fno-pic exec transitions"
+     "-melf_s390 tmpdir/libtlslib.so" "-m31" {tlsbinpic.s tlsbin.s}
+     {{readelf -Ssrl tlsbin.rd} {objdump -dzrj.text tlsbin.dd}
+      {objdump -sj.got tlsbin.sd} {objdump -sj.tdata tlsbin.td}}
+     "tlsbin"}
+}
+
+set s390xtests {
+    {"TLS -fpic -shared transitions" "-shared -melf64_s390"
+     "-m64 -Aesame" {tlspic1_64.s tlspic2_64.s}
+     {{readelf -WSsrl tlspic_64.rd} {objdump -dzrj.text tlspic_64.dd}
+      {objdump -sj.got tlspic_64.sd} {objdump -sj.tdata tlspic_64.td}}
+     "libtlspic_64.so"}
+    {"Helper shared library" "-shared -melf64_s390"
+     "-m64 -Aesame" {tlslib_64.s} {} "libtlslib_64.so"}
+    {"TLS -fpic and -fno-pic exec transitions"
+     "-melf64_s390 tmpdir/libtlslib_64.so" "-m64 -Aesame"
+     {tlsbinpic_64.s tlsbin_64.s}
+     {{readelf -WSsrl tlsbin_64.rd} {objdump -dzrj.text tlsbin_64.dd}
+      {objdump -sj.got tlsbin_64.sd} {objdump -sj.tdata tlsbin_64.td}}
+     "tlsbin_64"}
+}
+
+if [istarget "s390-*-*"] {
+    run_ld_link_tests $s390tests
+}
+
+if [istarget "s390x-*-*"] {
+    run_ld_link_tests $s390xtests
+}
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlsbin.dd b/binutils-2.19/ld/testsuite/ld-s390/tlsbin.dd
new file mode 100644
index 0000000..6e49b1b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlsbin.dd
@@ -0,0 +1,193 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: -m31
+#ld: -shared -melf_s390
+#objdump: -dzrj.text
+#target: s390-*-*
+
+# PT_TLS layout is:
+# Offset from   Offset from     Name
+# TCB base      TCB end
+# 0x00          -0xa0           sg1..sg2
+# 0x20          -0x80           sl1..sl2
+# 0x40          -0x60           sh1..sh2
+# 0x60          -0x40           bg1..bg2
+# 0x80          -0x20           bl1..bl2
+
+.*: +file format elf32-s390
+
+Disassembly of section .text:
+
+0+[0-9a-f]+ <fn2>:
+# function prolog
+  +[0-9a-f]+:	90 6e f0 18       	stm	%r6,%r14,24\(%r15\)
+  +[0-9a-f]+:	a7 d5 00 24       	bras	%r13,[0-9a-f]+ <fn2\+0x4c>
+# _GLOBAL_OFFSET_TABLE_
+  +[0-9a-f]+:	[0-9a-f ]+       	.long	0x[0-9a-f]+
+# __tls_get_addr@plt-.LT1
+  +[0-9a-f]+:	[0-9a-f ]+       	.long	0x[0-9a-f]+
+# sG1@tlsgd
+  +[0-9a-f]+:	00 00 00 28       	.long	0x00000028
+# sG2@tlsgd
+  +[0-9a-f]+:	00 00 00 20       	.long	0x00000020
+# sg1@tlsgd
+  +[0-9a-f]+:	ff ff ff 60       	.long	0xffffff60
+# sl1@tlsgd
+  +[0-9a-f]+:	ff ff ff 80       	.long	0xffffff80
+# sh1@tlsgd
+  +[0-9a-f]+:	ff ff ff a0       	.long	0xffffffa0
+# sl1@tlsldm
+  +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+# sl1@dtpoff
+  +[0-9a-f]+:	ff ff ff 80       	.long	0xffffff80
+# sl2@dtpoff
+  +[0-9a-f]+:	ff ff ff 84       	.long	0xffffff84
+# sh1@tlsldm
+  +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+# sh1@dtpoff
+  +[0-9a-f]+:	ff ff ff a0       	.long	0xffffffa0
+# sh2@dtpoff
+  +[0-9a-f]+:	ff ff ff a4       	.long	0xffffffa4
+# sG2@gotntpoff
+  +[0-9a-f]+:	00 00 00 20       	.long	0x00000020
+# sg1@gotntpoff
+  +[0-9a-f]+:	ff ff ff 60       	.long	0xffffff60
+# sl1@gotntpoff
+  +[0-9a-f]+:	ff ff ff 80       	.long	0xffffff80
+# sh1@gotntpoff
+  +[0-9a-f]+:	ff ff ff a0       	.long	0xffffffa0
+# function prolog
+  +[0-9a-f]+:	18 ef             	lr	%r14,%r15
+  +[0-9a-f]+:	58 c0 d0 00       	l	%r12,0\(%r13\)
+  +[0-9a-f]+:	a7 fa ff a0       	ahi	%r15,-96
+  +[0-9a-f]+:	41 cc d0 00       	la	%r12,0\(%r12,%r13\)
+  +[0-9a-f]+:	50 e0 e0 00       	st	%r14,0\(%r14\)
+# Extract TCB and load branch offset
+  +[0-9a-f]+:	b2 4f 00 90       	ear	%r9,%a0
+  +[0-9a-f]+:	58 70 d0 04       	l	%r7,4\(%r13\)
+# GD -> IE because variable is not defined in executable
+  +[0-9a-f]+:	58 20 d0 08       	l	%r2,8\(%r13\)
+  +[0-9a-f]+:	58 22 c0 00       	l	%r2,0\(%r2,%r12\)
+  +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> IE because variable is not defined in executable where
+# the variable is referenced through IE too
+  +[0-9a-f]+:	58 20 d0 0c       	l	%r2,12\(%r13\)
+  +[0-9a-f]+:	58 22 c0 00       	l	%r2,0\(%r2,%r12\)
+  +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> LE with global variable defined in executable
+  +[0-9a-f]+:	58 20 d0 10       	l	%r2,16\(%r13\)
+  +[0-9a-f]+:	47 00 00 00       	bc	0,0
+  +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> LE with local variable defined in executable
+  +[0-9a-f]+:	58 20 d0 14       	l	%r2,20\(%r13\)
+  +[0-9a-f]+:	47 00 00 00       	bc	0,0
+  +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> LE with hidden variable defined in executable
+  +[0-9a-f]+:	58 20 d0 18       	l	%r2,24\(%r13\)
+  +[0-9a-f]+:	47 00 00 00       	bc	0,0
+  +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# LD -> LE
+  +[0-9a-f]+:	58 20 d0 1c       	l	%r2,28\(%r13\)
+  +[0-9a-f]+:	47 00 00 00       	bc	0,0
+  +[0-9a-f]+:	41 32 90 00       	la	%r3,0\(%r2,%r9\)
+  +[0-9a-f]+:	58 40 d0 20       	l	%r4,32\(%r13\)
+  +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+  +[0-9a-f]+:	58 40 d0 24       	l	%r4,36\(%r13\)
+  +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+# LD -> LE against hidden variables
+  +[0-9a-f]+:	58 20 d0 28       	l	%r2,40\(%r13\)
+  +[0-9a-f]+:	47 00 00 00       	bc	0,0
+  +[0-9a-f]+:	41 32 90 00       	la	%r3,0\(%r2,%r9\)
+  +[0-9a-f]+:	58 40 d0 2c       	l	%r4,44\(%r13\)
+  +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+  +[0-9a-f]+:	58 40 d0 30       	l	%r4,48\(%r13\)
+  +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+# IE against global var
+  +[0-9a-f]+:	58 30 d0 34       	l	%r3,52\(%r13\)
+  +[0-9a-f]+:	58 33 c0 00       	l	%r3,0\(%r3,%r12\)
+  +[0-9a-f]+:	58 33 90 00       	l	%r3,0\(%r3,%r9\)
+# IE -> LE against global var defined in exec
+  +[0-9a-f]+:	58 30 d0 38       	l	%r3,56\(%r13\)
+  +[0-9a-f]+:	18 43             	lr	%r4,%r3
+  +[0-9a-f]+:	07 00             	bcr	0,%r0
+  +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE -> LE against local var
+  +[0-9a-f]+:	58 30 d0 3c       	l	%r3,60\(%r13\)
+  +[0-9a-f]+:	18 43             	lr	%r4,%r3
+  +[0-9a-f]+:	07 00             	bcr	0,%r0
+  +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE -> LE against hidden var
+  +[0-9a-f]+:	58 30 d0 40       	l	%r3,64\(%r13\)
+  +[0-9a-f]+:	18 43             	lr	%r4,%r3
+  +[0-9a-f]+:	07 00             	bcr	0,%r0
+  +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE against global var with small got access (no optimization)
+  +[0-9a-f]+:	58 30 c0 14       	l	%r3,20\(%r12\)
+  +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE against global var defined in exec with small got access
+# (no optimization)
+  +[0-9a-f]+:	58 30 c0 18       	l	%r3,24\(%r12\)
+  +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE against local var with small got access (no optimization)
+  +[0-9a-f]+:	58 30 c0 10       	l	%r3,16\(%r12\)
+  +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE against hidden var with small got access (no optimization)
+  +[0-9a-f]+:	58 30 c0 1c       	l	%r3,28\(%r12\)
+  +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# function epilog
+  +[0-9a-f]+:	98 6e f0 78       	lm	%r6,%r14,120\(%r15\)
+  +[0-9a-f]+:	07 fe             	br	%r14
+  +[0-9a-f]+:	07 07             	bcr	0,%r7
+  +[0-9a-f]+:	07 07             	bcr	0,%r7
+  +[0-9a-f]+:	07 07             	bcr	0,%r7
+  +[0-9a-f]+:	07 07             	bcr	0,%r7
+  +[0-9a-f]+:	07 07             	bcr	0,%r7
+  +[0-9a-f]+:	07 07             	bcr	0,%r7
+  +[0-9a-f]+:	07 07             	bcr	0,%r7
+  +[0-9a-f]+:	07 07             	bcr	0,%r7
+
+0+[0-9a-f]+ <_start>:
+# function prolog
+  +[0-9a-f]+:	90 6e f0 18       	stm	%r6,%r14,24\(%r15\)
+  +[0-9a-f]+:	a7 d5 00 0c       	bras	%r13,[0-9a-f]+ <_start\+0x1c>
+# sG6@indntpoff
+  +[0-9a-f]+:	00 40 15 a4       	.long	0x004015a4
+# bg6@indntpoff
+  +[0-9a-f]+:	ff ff ff d4       	.long	0xffffffd4
+# bl6@indntpoff
+  +[0-9a-f]+:	ff ff ff f4       	.long	0xfffffff4
+# sh6@indntpoff
+  +[0-9a-f]+:	ff ff ff b4       	.long	0xffffffb4
+# sg3@indntpoff
+  +[0-9a-f]+:	ff ff ff 68       	.long	0xffffff68
+# function prolog
+  +[0-9a-f]+:	18 ef             	lr	%r14,%r15
+  +[0-9a-f]+:	a7 fa ff a0       	ahi	%r15,-96
+  +[0-9a-f]+:	50 e0 e0 00       	st	%r14,0\(%r14\)
+# Extract TCB
+  +[0-9a-f]+:	b2 4f 00 90       	ear	%r9,%a0
+# IE against global var
+  +[0-9a-f]+:	58 30 d0 00       	l	%r3,0\(%r13\)
+  +[0-9a-f]+:	58 33 c0 00       	l	%r3,0\(%r3,%r12\)
+  +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE -> LE against global var defined in exec
+  +[0-9a-f]+:	58 30 d0 04       	l	%r3,4\(%r13\)
+  +[0-9a-f]+:	18 43             	lr	%r4,%r3
+  +[0-9a-f]+:	07 00             	bcr	0,%r0
+  +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE -> LE against local var
+  +[0-9a-f]+:	58 30 d0 08       	l	%r3,8\(%r13\)
+  +[0-9a-f]+:	18 43             	lr	%r4,%r3
+  +[0-9a-f]+:	07 00             	bcr	0,%r0
+  +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE -> LE against hidden but not local var
+  +[0-9a-f]+:	58 30 d0 0c       	l	%r3,12\(%r13\)
+  +[0-9a-f]+:	18 43             	lr	%r4,%r3
+  +[0-9a-f]+:	07 00             	bcr	0,%r0
+  +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# LE, global var defined in exec
+  +[0-9a-f]+:	58 40 d0 10       	l	%r4,16\(%r13\)
+  +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# function epilog
+  +[0-9a-f]+:	98 6e f0 78       	lm	%r6,%r14,120\(%r15\)
+  +[0-9a-f]+:	07 fe             	br	%r14
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlsbin.rd b/binutils-2.19/ld/testsuite/ld-s390/tlsbin.rd
new file mode 100644
index 0000000..c6bfc5b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlsbin.rd
@@ -0,0 +1,145 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: -m31
+#ld: -shared -melf_s390
+#readelf: -Ssrl
+#target: s390-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0
+ +\[[ 0-9]+\] .interp .*
+ +\[[ 0-9]+\] .hash .*
+ +\[[ 0-9]+\] .dynsym .*
+ +\[[ 0-9]+\] .dynstr .*
+ +\[[ 0-9]+\] .rela.dyn .*
+ +\[[ 0-9]+\] .rela.plt .*
+ +\[[ 0-9]+\] .plt .*
+ +\[[ 0-9]+\] .text +PROGBITS .*
+ +\[[ 0-9]+\] .tdata +PROGBITS .* 0+60 00 WAT +0 +0 +32
+ +\[[ 0-9]+\] .tbss +NOBITS .* 0+40 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC .*
+ +\[[ 0-9]+\] .got +PROGBITS .*
+ +\[[ 0-9]+\] .shstrtab .*
+ +\[[ 0-9]+\] .symtab .*
+ +\[[ 0-9]+\] .strtab .*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x[0-9a-f]+
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  PHDR +0x0+34 0x0+400034 0x0+400034 0x0+c0 0x0+c0 R E 0x4
+  INTERP +0x0+f4 0x0+4000f4 0x0+4000f4 0x0+11 0x0+11 R +0x1
+.*Requesting program interpreter.*
+  LOAD .* R E 0x1000
+  LOAD .* RW  0x1000
+  DYNAMIC .* RW  0x4
+  TLS .* 0x0+60 0x0+a0 R +0x20
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 *
+   01 +.interp *
+   02 +.interp .hash .dynsym .dynstr .rela.dyn .rela.plt .plt .text *
+   03 +.tdata .dynamic .got *
+   04 +.dynamic *
+   05 +.tdata .tbss *
+
+Relocation section '.rela.dyn' at offset .* contains 4 entries:
+ Offset +Info +Type +Sym.Value  Sym. Name \+ Addend
+[0-9a-f ]+R_390_TLS_TPOFF +0+ +sG3 \+ 0
+[0-9a-f ]+R_390_TLS_TPOFF +0+ +sG2 \+ 0
+[0-9a-f ]+R_390_TLS_TPOFF +0+ +sG6 \+ 0
+[0-9a-f ]+R_390_TLS_TPOFF +0+ +sG1 \+ 0
+
+Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ Offset +Info +Type +Sym.Value  Sym. Name \+ Addend
+[0-9a-f ]+R_390_JMP_SLOT[0-9a-f ]+__tls_get_offset \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value  Size Type +Bind +Vis +Ndx Name
+.* NOTYPE  LOCAL  DEFAULT  UND 
+.* TLS +GLOBAL DEFAULT  UND sG3
+.* TLS +GLOBAL DEFAULT  UND sG2
+.* FUNC +GLOBAL DEFAULT  UND __tls_get_offset
+.* NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.* TLS +GLOBAL DEFAULT  UND sG6
+.* TLS +GLOBAL DEFAULT  UND sG1
+.* NOTYPE  GLOBAL DEFAULT  ABS _edata
+.* NOTYPE  GLOBAL DEFAULT  ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value  Size Type +Bind +Vis +Ndx Name
+.* NOTYPE  LOCAL  DEFAULT  UND 
+.* SECTION LOCAL  DEFAULT +1 
+.* SECTION LOCAL  DEFAULT +2 
+.* SECTION LOCAL  DEFAULT +3 
+.* SECTION LOCAL  DEFAULT +4 
+.* SECTION LOCAL  DEFAULT +5 
+.* SECTION LOCAL  DEFAULT +6 
+.* SECTION LOCAL  DEFAULT +7 
+.* SECTION LOCAL  DEFAULT +8 
+.* SECTION LOCAL  DEFAULT +9 
+.* SECTION LOCAL  DEFAULT +10 
+.* SECTION LOCAL  DEFAULT +11 
+.* SECTION LOCAL  DEFAULT +12 
+.* TLS +LOCAL  DEFAULT +9 sl1
+.* TLS +LOCAL  DEFAULT +9 sl2
+.* TLS +LOCAL  DEFAULT +9 sl3
+.* TLS +LOCAL  DEFAULT +9 sl4
+.* TLS +LOCAL  DEFAULT +9 sl5
+.* TLS +LOCAL  DEFAULT +9 sl6
+.* TLS +LOCAL  DEFAULT +9 sl7
+.* TLS +LOCAL  DEFAULT +9 sl8
+.* TLS +LOCAL  DEFAULT +10 bl1
+.* TLS +LOCAL  DEFAULT +10 bl2
+.* TLS +LOCAL  DEFAULT +10 bl3
+.* TLS +LOCAL  DEFAULT +10 bl4
+.* TLS +LOCAL  DEFAULT +10 bl5
+.* TLS +LOCAL  DEFAULT +10 bl6
+.* TLS +LOCAL  DEFAULT +10 bl7
+.* TLS +LOCAL  DEFAULT +10 bl8
+.* OBJECT  LOCAL  HIDDEN +11 _DYNAMIC
+.* OBJECT  LOCAL  HIDDEN +12 _GLOBAL_OFFSET_TABLE_
+.* TLS +GLOBAL DEFAULT  UND sG3
+.* TLS +GLOBAL DEFAULT +9 sg8
+.* TLS +GLOBAL DEFAULT +10 bg8
+.* TLS +GLOBAL DEFAULT +10 bg6
+.* TLS +GLOBAL DEFAULT +10 bg3
+.* TLS +GLOBAL DEFAULT +9 sg3
+.* TLS +GLOBAL HIDDEN +9 sh3
+.* TLS +GLOBAL DEFAULT  UND sG2
+.* TLS +GLOBAL DEFAULT +9 sg4
+.* TLS +GLOBAL DEFAULT +9 sg5
+.* TLS +GLOBAL DEFAULT +10 bg5
+.* TLS +GLOBAL HIDDEN +9 sh7
+.* TLS +GLOBAL HIDDEN +9 sh8
+.* FUNC +GLOBAL DEFAULT  UND __tls_get_offset
+.* TLS +GLOBAL DEFAULT +9 sg1
+.* FUNC +GLOBAL DEFAULT +8 _start
+.* TLS +GLOBAL HIDDEN +9 sh4
+.* TLS +GLOBAL DEFAULT +10 bg7
+.* TLS +GLOBAL HIDDEN +9 sh5
+.* NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.* TLS +GLOBAL DEFAULT  UND sG6
+.* FUNC +GLOBAL DEFAULT +8 fn2
+.* TLS +GLOBAL DEFAULT +9 sg2
+.* TLS +GLOBAL DEFAULT  UND sG1
+.* TLS +GLOBAL HIDDEN +9 sh1
+.* TLS +GLOBAL DEFAULT +9 sg6
+.* TLS +GLOBAL DEFAULT +9 sg7
+.* NOTYPE  GLOBAL DEFAULT  ABS _edata
+.* NOTYPE  GLOBAL DEFAULT  ABS _end
+.* TLS +GLOBAL HIDDEN +9 sh2
+.* TLS +GLOBAL HIDDEN +9 sh6
+.* TLS +GLOBAL DEFAULT +10 bg2
+.* TLS +GLOBAL DEFAULT +10 bg1
+.* TLS +GLOBAL DEFAULT +10 bg4
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlsbin.s b/binutils-2.19/ld/testsuite/ld-s390/tlsbin.s
new file mode 100644
index 0000000..4da50e7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlsbin.s
@@ -0,0 +1,73 @@
+	.section ".tbss", "awT", @nobits
+	.globl bg1, bg2, bg3, bg4, bg5, bg6, bg7, bg8
+bg1:	.space 4
+bg2:	.space 4
+bg3:	.space 4
+bg4:	.space 4
+bg5:	.space 4
+bg6:	.space 4
+bg7:	.space 4
+bg8:	.space 4
+bl1:	.space 4
+bl2:	.space 4
+bl3:	.space 4
+bl4:	.space 4
+bl5:	.space 4
+bl6:	.space 4
+bl7:	.space 4
+bl8:	.space 4
+	.text
+	.globl	_start
+	.type	_start,@function
+_start:
+	/* Function prolog */
+	stm	%r6,%r14,24(%r15)
+	bras	%r13,.LTN1
+	/* Literal pool */
+.LT1:
+.LC0:
+	.long	sG6@indntpoff
+.LC1:
+	.long	bg6@indntpoff
+.LC2:
+	.long	bl6@indntpoff
+.LC3:
+	.long	sh6@indntpoff
+.LC4:
+	.long	sg3@indntpoff
+.LTN1:
+	/* Function prolog */
+	lr	%r14,%r15
+	ahi	%r15,-96
+	st	%r14,0(%r14)
+
+	/* Extract TCB */
+	ear	%r9,%a0
+
+	/* IE against global var  */
+	l	%r3,.LC0-.LT1(%r13)
+	l	%r3,0(%r3,%r12):tls_load:sG6
+	la	%r3,0(%r3,%r9)
+
+	/* IE -> LE against global var defined in exec  */
+	l	%r3,.LC1-.LT1(%r13)
+	l	%r4,0(%r3,%r12):tls_load:bg6
+	la	%r5,0(%r4,%r9)
+
+	/* IE -> LE against local var  */
+	l	%r3,.LC2-.LT1(%r13)
+	l	%r4,0(%r3,%r12):tls_load:bl6
+	la	%r5,0(%r4,%r9)
+
+	/* IE -> LE against hidden but not local var  */
+	l	%r3,.LC3-.LT1(%r13)
+	l	%r4,0(%r3,%r12):tls_load:sh6
+	la	%r5,0(%r4,%r9)
+
+	/* LE, global var defined in exec  */
+	l	%r4,.LC4-.LT1(%r13)
+	la	%r5,0(%r4,%r9)
+
+	/* Function epilog */
+	lm	%r6,%r14,120(%r15)
+	br	%r14
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlsbin.sd b/binutils-2.19/ld/testsuite/ld-s390/tlsbin.sd
new file mode 100644
index 0000000..b1ecbf0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlsbin.sd
@@ -0,0 +1,13 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: -m31
+#ld: -shared -melf_s390
+#objdump: -sj.got
+#target: s390-*-*
+
+.*:     file format elf32-s390
+
+Contents of section .got:
+ [0-9a-f]+ [0-9a-f]+ 00000000 00000000 [0-9a-f]+  .@...........@..
+ [0-9a-f]+ ffffff88 00000000 ffffff68 ffffffa8  ...........h....
+ [0-9a-f]+ 00000000 00000000 00000000           ............    
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlsbin.td b/binutils-2.19/ld/testsuite/ld-s390/tlsbin.td
new file mode 100644
index 0000000..f0a61b8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlsbin.td
@@ -0,0 +1,16 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: -m31
+#ld: -shared -melf_s390
+#objdump: -sj.tdata
+#target: s390-*-*
+
+.*:     file format elf32-s390
+
+Contents of section .tdata:
+ [0-9a-f]+ 00000011 00000012 00000013 00000014  .*
+ [0-9a-f]+ 00000015 00000016 00000017 00000018  .*
+ [0-9a-f]+ 00000041 00000042 00000043 00000044  .*
+ [0-9a-f]+ 00000045 00000046 00000047 00000048  .*
+ [0-9a-f]+ 00000101 00000102 00000103 00000104  .*
+ [0-9a-f]+ 00000105 00000106 00000107 00000108  .*
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlsbin_64.dd b/binutils-2.19/ld/testsuite/ld-s390/tlsbin_64.dd
new file mode 100644
index 0000000..664991a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlsbin_64.dd
@@ -0,0 +1,223 @@
+#source: tlsbinpic_64.s
+#source: tlsbin_64.s
+#as: -m64 -Aesame
+#ld: -shared -melf64_s390
+#objdump: -dzrj.text
+#target: s390x-*-*
+
+# PT_TLS layout is:
+# Offset from   Offset from     Name
+# TCB base      TCB end
+# 0x00          -0xa0           sg1..sg2
+# 0x20          -0x80           sl1..sl2
+# 0x40          -0x60           sh1..sh2
+# 0x60          -0x40           bg1..bg2
+# 0x80          -0x20           bl1..bl2
+
+.*: +file format elf64-s390
+
+Disassembly of section .text:
+
+0+[0-9a-f]+ <fn2>:
+# function prolog
+ +[0-9a-f]+:	eb 6e f0 30 00 24 	stmg	%r6,%r14,48\(%r15\)
+ +[0-9a-f]+:	a7 d5 00 3e       	bras	%r13,[0-9a-f]+ <fn2\+0x82>
+# sG1@tlsgd
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 60       	.long	0x00000060
+# sG2@tlsgd
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 48       	.long	0x00000048
+# sg1@tlsgd
+ +[0-9a-f]+:	ff ff ff ff       	.long	0xffffffff
+ +[0-9a-f]+:	ff ff ff 60       	.long	0xffffff60
+# sl1@tlsgd
+ +[0-9a-f]+:	ff ff ff ff       	.long	0xffffffff
+ +[0-9a-f]+:	ff ff ff 80       	.long	0xffffff80
+# sh1@tlsgd
+ +[0-9a-f]+:	ff ff ff ff       	.long	0xffffffff
+ +[0-9a-f]+:	ff ff ff a0       	.long	0xffffffa0
+# sl1@tlsldm
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+# sl1@dtpoff
+ +[0-9a-f]+:	ff ff ff ff       	.long	0xffffffff
+ +[0-9a-f]+:	ff ff ff 80       	.long	0xffffff80
+# sl2@dtpoff
+ +[0-9a-f]+:	ff ff ff ff       	.long	0xffffffff
+ +[0-9a-f]+:	ff ff ff 84       	.long	0xffffff84
+# sh1@tlsldm
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+# sh1@dtpoff
+ +[0-9a-f]+:	ff ff ff ff       	.long	0xffffffff
+ +[0-9a-f]+:	ff ff ff a0       	.long	0xffffffa0
+# sh2@dtpoff
+ +[0-9a-f]+:	ff ff ff ff       	.long	0xffffffff
+ +[0-9a-f]+:	ff ff ff a4       	.long	0xffffffa4
+# sG2@gotntpoff
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 48       	.long	0x00000048
+# sg1@gotntpoff
+ +[0-9a-f]+:	ff ff ff ff       	.long	0xffffffff
+ +[0-9a-f]+:	ff ff ff 60       	.long	0xffffff60
+# sl1@gotntpoff
+ +[0-9a-f]+:	ff ff ff ff       	.long	0xffffffff
+ +[0-9a-f]+:	ff ff ff 80       	.long	0xffffff80
+# sh1@gotntpoff
+ +[0-9a-f]+:	ff ff ff ff       	.long	0xffffffff
+ +[0-9a-f]+:	ff ff ff a0       	.long	0xffffffa0
+# function prolog
+ +[0-9a-f]+:	b9 04 00 ef       	lgr	%r14,%r15
+ +[0-9a-f]+:	a7 fb ff 60       	aghi	%r15,-160
+ +[0-9a-f]+:	c0 c0 [0-9a-f ]+ 	larl	%r12,[0-9a-f]+ <_GLOBAL_OFFSET_TABLE_>
+ +[0-9a-f]+:	e3 e0 e0 00 00 24 	stg	%r14,0\(%r14\)
+# extract TCB
+ +[0-9a-f]+:	b2 4f 00 90       	ear	%r9,%a0
+ +[0-9a-f]+:	eb 94 00 20 00 0d 	sllg	%r9,%r4,32
+ +[0-9a-f]+:	b2 4f 00 91       	ear	%r9,%a1
+# GD -> IE because variable is not defined in executable
+ +[0-9a-f]+:	e3 c0 d0 00 00 04 	lg	%r12,0\(%r13\)
+ +[0-9a-f]+:	e3 22 c0 00 00 04 	lg	%r2,0\(%r2,%r12\)
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> IE because variable is not defined in executable where
+# the variable is referenced through IE too
+ +[0-9a-f]+:	e3 20 d0 08 00 04 	lg	%r2,8\(%r13\)
+ +[0-9a-f]+:	e3 22 c0 00 00 04 	lg	%r2,0\(%r2,%r12\)
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> LE with global variable defined in executable
+ +[0-9a-f]+:	e3 20 d0 10 00 04 	lg	%r2,16\(%r13\)
+ +[0-9a-f]+:	c0 04 00 00 00 00 	brcl	0,[0-9a-f]+ <fn2\+0xca>
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> LE with local variable defined in executable
+ +[0-9a-f]+:	e3 20 d0 18 00 04 	lg	%r2,24\(%r13\)
+ +[0-9a-f]+:	c0 04 00 00 00 00 	brcl	0,[0-9a-f]+ <fn2\+0xda>
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> LE with hidden variable defined in executable
+ +[0-9a-f]+:	e3 20 d0 20 00 04 	lg	%r2,32\(%r13\)
+ +[0-9a-f]+:	c0 04 00 00 00 00 	brcl	0,[0-9a-f]+ <fn2\+0xea>
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# LD -> LE
+ +[0-9a-f]+:	e3 20 d0 28 00 04 	lg	%r2,40\(%r13\)
+ +[0-9a-f]+:	c0 04 00 00 00 00 	brcl	0,[0-9a-f]+ <fn2\+0xfa>
+ +[0-9a-f]+:	41 32 90 00       	la	%r3,0\(%r2,%r9\)
+ +[0-9a-f]+:	e3 40 d0 30 00 04 	lg	%r4,48\(%r13\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+ +[0-9a-f]+:	e3 40 d0 38 00 04 	lg	%r4,56\(%r13\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+ +[0-9a-f]+:	e3 20 d0 40 00 04 	lg	%r2,64\(%r13\)
+ +[0-9a-f]+:	c0 04 00 00 00 00 	brcl	0,[0-9a-f]+ <fn2\+0x11e>
+ +[0-9a-f]+:	41 32 90 00       	la	%r3,0\(%r2,%r9\)
+ +[0-9a-f]+:	e3 40 d0 48 00 04 	lg	%r4,72\(%r13\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+ +[0-9a-f]+:	e3 40 d0 50 00 04 	lg	%r4,80\(%r13\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+# IE against global var
+ +[0-9a-f]+:	e3 30 d0 58 00 04 	lg	%r3,88\(%r13\)
+ +[0-9a-f]+:	e3 33 c0 00 00 04 	lg	%r3,0\(%r3,%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE -> LE against global var defined in exec
+ +[0-9a-f]+:	e3 30 d0 60 00 04 	lg	%r3,96\(%r13\)
+ +[0-9a-f]+:	eb 43 00 00 00 0d 	sllg	%r4,%r3,0
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE -> LE against local var
+ +[0-9a-f]+:	e3 30 d0 68 00 04 	lg	%r3,104\(%r13\)
+ +[0-9a-f]+:	eb 43 00 00 00 0d 	sllg	%r4,%r3,0
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE -> LE against hidden var
+ +[0-9a-f]+:	e3 30 d0 70 00 04 	lg	%r3,112\(%r13\)
+ +[0-9a-f]+:	eb 43 00 00 00 0d 	sllg	%r4,%r3,0
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE against global var with larl got access
+ +[0-9a-f]+:	c0 30 [0-9a-f ]+ 	larl	%r3,[0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x28>
+ +[0-9a-f]+:	e3 33 c0 00 00 04 	lg	%r3,0\(%r3,%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE against global var defined in exec with larl got access
+ +[0-9a-f]+:	c0 30 [0-9a-f ]+ 	larl	%r3,[0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x38>
+ +[0-9a-f]+:	eb 43 00 00 00 0d 	sllg	%r4,%r3,0
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE against local var with larl got access
+ +[0-9a-f]+:	c0 30 [0-9a-f ]+ 	larl	%r3,[0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x20>
+ +[0-9a-f]+:	eb 43 00 00 00 0d 	sllg	%r4,%r3,0
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE against hidden var with larl got access
+ +[0-9a-f]+:	c0 30 [0-9a-f ]+ 	larl	%r3,[0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x40>
+ +[0-9a-f]+:	eb 43 00 00 00 0d 	sllg	%r4,%r3,0
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE against global var with small got access (no optimization)
+ +[0-9a-f]+:	e3 30 c0 28 00 04 	lg	%r3,40\(%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE against global var defined in exec with small got access
+# (no optimization)
+ +[0-9a-f]+:	e3 30 c0 38 00 04 	lg	%r3,56\(%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE against local var with small got access (no optimization)
+ +[0-9a-f]+:	e3 30 c0 20 00 04 	lg	%r3,32\(%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE against hidden var with small got access (no optimization)
+ +[0-9a-f]+:	e3 30 c0 40 00 04 	lg	%r3,64\(%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# function epilog
+ +[0-9a-f]+:	eb 6e f0 d0 00 04 	lmg	%r6,%r14,208\(%r15\)
+ +[0-9a-f]+:	07 fe             	br	%r14
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+
+0+[0-9a-f]+ <_start>:
+# function prolog
+ +[0-9a-f]+:	90 6e f0 18       	stm	%r6,%r14,24\(%r15\)
+ +[0-9a-f]+:	a7 d5 00 16       	bras	%r13,[0-9a-f]+ <_start\+0x30>
+# sG6@indntpoff
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	80 00 [0-9a-f ]+       	ssm	[0-9]+\(%r1\)
+# bg6@indntpoff
+ +[0-9a-f]+:	ff ff ff ff       	.long	0xffffffff
+ +[0-9a-f]+:	ff ff ff d4       	.long	0xffffffd4
+# bl6@indntpoff
+ +[0-9a-f]+:	ff ff ff ff       	.long	0xffffffff
+ +[0-9a-f]+:	ff ff ff f4       	.long	0xfffffff4
+# sh6@indntpoff
+ +[0-9a-f]+:	ff ff ff ff       	.long	0xffffffff
+ +[0-9a-f]+:	ff ff ff b4       	.long	0xffffffb4
+# sg3@indntpoff
+ +[0-9a-f]+:	ff ff ff ff       	.long	0xffffffff
+ +[0-9a-f]+:	ff ff ff 68       	.long	0xffffff68
+# function prolog
+ +[0-9a-f]+:	b9 04 00 ef       	lgr	%r14,%r15
+ +[0-9a-f]+:	a7 fb ff 60       	aghi	%r15,-160
+ +[0-9a-f]+:	e3 e0 e0 00 00 24 	stg	%r14,0\(%r14\)
+# extract TCB
+ +[0-9a-f]+:	b2 4f 00 90       	ear	%r9,%a0
+ +[0-9a-f]+:	eb 94 00 20 00 0d 	sllg	%r9,%r4,32
+ +[0-9a-f]+:	b2 4f 00 91       	ear	%r9,%a1
+# IE against global var
+ +[0-9a-f]+:	e3 30 d0 00 00 04 	lg	%r3,0\(%r13\)
+ +[0-9a-f]+:	e3 33 c0 00 00 04 	lg	%r3,0\(%r3,%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE -> LE against global var defined in exec
+ +[0-9a-f]+:	e3 30 d0 08 00 04 	lg	%r3,8\(%r13\)
+ +[0-9a-f]+:	eb 43 00 00 00 0d 	sllg	%r4,%r3,0
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE -> LE against local var
+ +[0-9a-f]+:	e3 30 d0 10 00 04 	lg	%r3,16\(%r13\)
+ +[0-9a-f]+:	eb 43 00 00 00 0d 	sllg	%r4,%r3,0
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE -> LE against hidden but not local var
+ +[0-9a-f]+:	e3 30 d0 18 00 04 	lg	%r3,24\(%r13\)
+ +[0-9a-f]+:	eb 43 00 00 00 0d 	sllg	%r4,%r3,0
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# LE, global var defined in exec
+ +[0-9a-f]+:	e3 40 d0 20 00 04 	lg	%r4,32\(%r13\)
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# function epilog
+ +[0-9a-f]+:	eb 6e f0 d0 00 04 	lmg	%r6,%r14,208\(%r15\)
+ +[0-9a-f]+:	07 fe             	br	%r14
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlsbin_64.rd b/binutils-2.19/ld/testsuite/ld-s390/tlsbin_64.rd
new file mode 100644
index 0000000..62b240b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlsbin_64.rd
@@ -0,0 +1,145 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: -m64 -Aesame
+#ld: -shared -melf64_s390
+#readelf: -Ssrl
+#target: s390x-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0
+ +\[[ 0-9]+\] .interp .*
+ +\[[ 0-9]+\] .hash .*
+ +\[[ 0-9]+\] .dynsym .*
+ +\[[ 0-9]+\] .dynstr .*
+ +\[[ 0-9]+\] .rela.dyn .*
+ +\[[ 0-9]+\] .rela.plt .*
+ +\[[ 0-9]+\] .plt .*
+ +\[[ 0-9]+\] .text +PROGBITS .*
+ +\[[ 0-9]+\] .tdata +PROGBITS .* 0+60 00 WAT +0 +0 +32
+ +\[[ 0-9]+\] .tbss +NOBITS .* 0+40 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC .*
+ +\[[ 0-9]+\] .got +PROGBITS .*
+ +\[[ 0-9]+\] .shstrtab .*
+ +\[[ 0-9]+\] .symtab .*
+ +\[[ 0-9]+\] .strtab .*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x[0-9a-f]+
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  PHDR +0x0+40 0x0+80000040 0x0+80000040 0x0+150 0x0+150 R E 0x8
+  INTERP +0x0+190 0x0+80000190 0x0+80000190 0x0+11 0x0+11 R +0x1
+.*Requesting program interpreter.*
+  LOAD .* R E 0x1000
+  LOAD .* RW  0x1000
+  DYNAMIC .* RW  0x8
+  TLS .* 0x0+60 0x0+a0 R +0x20
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 *
+   01 +.interp *
+   02 +.interp .hash .dynsym .dynstr .rela.dyn .rela.plt .plt .text *
+   03 +.tdata .dynamic .got *
+   04 +.dynamic *
+   05 +.tdata .tbss *
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_390_TLS_TPOFF +0+ sG3 \+ 0
+[0-9a-f ]+R_390_TLS_TPOFF +0+ sG2 \+ 0
+[0-9a-f ]+R_390_TLS_TPOFF +0+ sG6 \+ 0
+[0-9a-f ]+R_390_TLS_TPOFF +0+ sG1 \+ 0
+
+Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_390_JMP_SLOT[0-9a-f ]+__tls_get_offset \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND 
+.* TLS +GLOBAL DEFAULT +UND sG3
+.* TLS +GLOBAL DEFAULT +UND sG2
+.* FUNC +GLOBAL DEFAULT +UND __tls_get_offset
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +UND sG6
+.* TLS +GLOBAL DEFAULT +UND sG1
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND 
+.* SECTION LOCAL +DEFAULT +1 
+.* SECTION LOCAL +DEFAULT +2 
+.* SECTION LOCAL +DEFAULT +3 
+.* SECTION LOCAL +DEFAULT +4 
+.* SECTION LOCAL +DEFAULT +5 
+.* SECTION LOCAL +DEFAULT +6 
+.* SECTION LOCAL +DEFAULT +7 
+.* SECTION LOCAL +DEFAULT +8 
+.* SECTION LOCAL +DEFAULT +9 
+.* SECTION LOCAL +DEFAULT +10 
+.* SECTION LOCAL +DEFAULT +11 
+.* SECTION LOCAL +DEFAULT +12 
+.* TLS +LOCAL +DEFAULT +9 sl1
+.* TLS +LOCAL +DEFAULT +9 sl2
+.* TLS +LOCAL +DEFAULT +9 sl3
+.* TLS +LOCAL +DEFAULT +9 sl4
+.* TLS +LOCAL +DEFAULT +9 sl5
+.* TLS +LOCAL +DEFAULT +9 sl6
+.* TLS +LOCAL +DEFAULT +9 sl7
+.* TLS +LOCAL +DEFAULT +9 sl8
+.* TLS +LOCAL +DEFAULT +10 bl1
+.* TLS +LOCAL +DEFAULT +10 bl2
+.* TLS +LOCAL +DEFAULT +10 bl3
+.* TLS +LOCAL +DEFAULT +10 bl4
+.* TLS +LOCAL +DEFAULT +10 bl5
+.* TLS +LOCAL +DEFAULT +10 bl6
+.* TLS +LOCAL +DEFAULT +10 bl7
+.* TLS +LOCAL +DEFAULT +10 bl8
+.* OBJECT +LOCAL +HIDDEN +11 _DYNAMIC
+.* OBJECT +LOCAL +HIDDEN +12 _GLOBAL_OFFSET_TABLE_
+.* TLS +GLOBAL DEFAULT +UND sG3
+.* TLS +GLOBAL DEFAULT +9 sg8
+.* TLS +GLOBAL DEFAULT +10 bg8
+.* TLS +GLOBAL DEFAULT +10 bg6
+.* TLS +GLOBAL DEFAULT +10 bg3
+.* TLS +GLOBAL DEFAULT +9 sg3
+.* TLS +GLOBAL HIDDEN +9 sh3
+.* TLS +GLOBAL DEFAULT +UND sG2
+.* TLS +GLOBAL DEFAULT +9 sg4
+.* TLS +GLOBAL DEFAULT +9 sg5
+.* TLS +GLOBAL DEFAULT +10 bg5
+.* TLS +GLOBAL HIDDEN +9 sh7
+.* TLS +GLOBAL HIDDEN +9 sh8
+.* FUNC +GLOBAL DEFAULT +UND __tls_get_offset
+.* TLS +GLOBAL DEFAULT +9 sg1
+.* FUNC +GLOBAL DEFAULT +8 _start
+.* TLS +GLOBAL HIDDEN +9 sh4
+.* TLS +GLOBAL DEFAULT +10 bg7
+.* TLS +GLOBAL HIDDEN +9 sh5
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +UND sG6
+.* FUNC +GLOBAL DEFAULT +8 fn2
+.* TLS +GLOBAL DEFAULT +9 sg2
+.* TLS +GLOBAL DEFAULT +UND sG1
+.* TLS +GLOBAL HIDDEN +9 sh1
+.* TLS +GLOBAL DEFAULT +9 sg6
+.* TLS +GLOBAL DEFAULT +9 sg7
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* TLS +GLOBAL HIDDEN +9 sh2
+.* TLS +GLOBAL HIDDEN +9 sh6
+.* TLS +GLOBAL DEFAULT +10 bg2
+.* TLS +GLOBAL DEFAULT +10 bg1
+.* TLS +GLOBAL DEFAULT +10 bg4
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlsbin_64.s b/binutils-2.19/ld/testsuite/ld-s390/tlsbin_64.s
new file mode 100644
index 0000000..c40fcfc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlsbin_64.s
@@ -0,0 +1,75 @@
+	.section ".tbss", "awT", @nobits
+	.globl bg1, bg2, bg3, bg4, bg5, bg6, bg7, bg8
+bg1:	.space 4
+bg2:	.space 4
+bg3:	.space 4
+bg4:	.space 4
+bg5:	.space 4
+bg6:	.space 4
+bg7:	.space 4
+bg8:	.space 4
+bl1:	.space 4
+bl2:	.space 4
+bl3:	.space 4
+bl4:	.space 4
+bl5:	.space 4
+bl6:	.space 4
+bl7:	.space 4
+bl8:	.space 4
+	.text
+	.globl	_start
+	.type	_start,@function
+_start:
+	/* Function prolog */
+	stm	%r6,%r14,24(%r15)
+	bras	%r13,.LTN1
+	/* Literal pool */
+.LT1:
+.LC0:
+	.quad	sG6@indntpoff
+.LC1:
+	.quad	bg6@indntpoff
+.LC2:
+	.quad	bl6@indntpoff
+.LC3:
+	.quad	sh6@indntpoff
+.LC4:
+	.quad	sg3@indntpoff
+.LTN1:
+	/* Function prolog */
+	lgr	%r14,%r15
+	aghi	%r15,-160
+	stg	%r14,0(%r14)
+
+	/* Extract TCB */
+	ear	%r9,%a0
+	sllg	%r9,%r4,32
+	ear	%r9,%a1
+
+	/* IE against global var  */
+	lg	%r3,.LC0-.LT1(%r13)
+	lg	%r3,0(%r3,%r12):tls_load:sG6
+	la	%r3,0(%r3,%r9)
+
+	/* IE -> LE against global var defined in exec  */
+	lg	%r3,.LC1-.LT1(%r13)
+	lg	%r4,0(%r3,%r12):tls_load:bg6
+	la	%r5,0(%r4,%r9)
+
+	/* IE -> LE against local var  */
+	lg	%r3,.LC2-.LT1(%r13)
+	lg	%r4,0(%r3,%r12):tls_load:bl6
+	la	%r5,0(%r4,%r9)
+
+	/* IE -> LE against hidden but not local var  */
+	lg	%r3,.LC3-.LT1(%r13)
+	lg	%r4,0(%r3,%r12):tls_load:sh6
+	la	%r5,0(%r4,%r9)
+
+	/* LE, global var defined in exec  */
+	lg	%r4,.LC4-.LT1(%r13)
+	la	%r5,0(%r4,%r9)
+
+	/* Function epilog */
+	lmg	%r6,%r14,208(%r15)
+	br	%r14
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlsbin_64.sd b/binutils-2.19/ld/testsuite/ld-s390/tlsbin_64.sd
new file mode 100644
index 0000000..6618e45
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlsbin_64.sd
@@ -0,0 +1,18 @@
+#source: tlsbinpic_64.s
+#source: tlsbin_64.s
+#as: -m64 -Aesame
+#ld: -shared -melf64_s390
+#objdump: -sj.got
+#target: s390x-*-*
+
+.*:     file format elf64-s390
+
+Contents of section .got:
+ [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 [0-9a-f]+ [0-9a-f]+  .*
+ [0-9a-f]+ ffffffff ffffff88 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 ffffffff ffffff68  .*
+ [0-9a-f]+ ffffffff ffffffa8 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlsbin_64.td b/binutils-2.19/ld/testsuite/ld-s390/tlsbin_64.td
new file mode 100644
index 0000000..dfa7e8d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlsbin_64.td
@@ -0,0 +1,16 @@
+#source: tlsbinpic_64.s
+#source: tlsbin_64.s
+#as: -m64 -Aesame
+#ld: -shared -melf64_s390
+#objdump: -sj.tdata
+#target: s390x-*-*
+
+.*:     file format elf64-s390
+
+Contents of section .tdata:
+ [0-9a-f]+ 00000011 00000012 00000013 00000014  .*
+ [0-9a-f]+ 00000015 00000016 00000017 00000018  .*
+ [0-9a-f]+ 00000041 00000042 00000043 00000044  .*
+ [0-9a-f]+ 00000045 00000046 00000047 00000048  .*
+ [0-9a-f]+ 00000101 00000102 00000103 00000104  .*
+ [0-9a-f]+ 00000105 00000106 00000107 00000108  .*
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlsbinpic.s b/binutils-2.19/ld/testsuite/ld-s390/tlsbinpic.s
new file mode 100644
index 0000000..e52e3a4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlsbinpic.s
@@ -0,0 +1,170 @@
+	.section ".tdata", "awT", @progbits
+	.balign 32
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+	.text
+	.globl	fn2
+	.type	fn2,@function
+	.balign	64
+fn2:
+	/* Function prolog */
+	stm	%r6,%r14,24(%r15)
+	bras	%r13,.LTN1
+	/* Literal pool */
+.LT1:
+.LC0:
+	.long	_GLOBAL_OFFSET_TABLE_-.LT1
+.LC1:
+	.long	__tls_get_offset@plt-.LT1
+.LC2:
+	.long	sG1@tlsgd
+.LC3:
+	.long	sG2@tlsgd
+.LC4:
+	.long	sg1@tlsgd
+.LC5:
+	.long	sl1@tlsgd
+.LC6:
+	.long	sh1@tlsgd
+.LC7:
+	.long	sl1@tlsldm
+.LC8:
+	.long	sl1@dtpoff
+.LC9:
+	.long	sl2@dtpoff
+.LC10:
+	.long	sh1@tlsldm
+.LC11:
+	.long	sh1@dtpoff
+.LC12:
+	.long	sh2@dtpoff
+.LC13:
+	.long	sG2@gotntpoff
+.LC14:
+	.long	sg1@gotntpoff
+.LC15:
+	.long	sl1@gotntpoff
+.LC16:
+	.long	sh1@gotntpoff
+.LTN1:
+	/* Function prolog */
+	lr	%r14,%r15
+	l	%r12,.LC0-.LT1(%r13)
+	ahi	%r15,-96
+	la	%r12,0(%r12,%r13)
+	st	%r14,0(%r14)
+
+	/* Extract TCB and load branch offset */
+	ear	%r9,%a0
+	l	%r7,.LC1-.LT1(%r13)
+	
+	/* GD -> IE because variable is not defined in executable */
+	l	%r2,.LC2-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_gdcall:sG1
+	la	%r2,0(%r2,%r9)
+
+	/* GD -> IE because variable is not defined in executable where
+	   the variable is referenced through IE too */
+	l	%r2,.LC3-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_gdcall:sG2
+	la	%r2,0(%r2,%r9)
+
+	/* GD -> LE with global variable defined in executable */
+	l	%r2,.LC4-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_gdcall:sg1
+	la	%r2,0(%r2,%r9)
+
+	/* GD -> LE with local variable defined in executable */
+	l	%r2,.LC5-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_gdcall:sl1
+	la	%r2,0(%r2,%r9)
+
+	/* GD -> LE with hidden variable defined in executable */
+	l	%r2,.LC6-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_gdcall:sh1
+	la	%r2,0(%r2,%r9)
+
+	/* LD -> LE */
+	l	%r2,.LC7-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_ldcall:sl1
+	la	%r3,0(%r2,%r9)
+	l	%r4,.LC8-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+	l	%r4,.LC9-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+
+	/* LD -> LE against hidden variables */
+	l	%r2,.LC10-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_ldcall:sh1
+	la	%r3,0(%r2,%r9)
+	l	%r4,.LC11-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+	l	%r4,.LC12-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+
+	/* IE against global var  */
+	l	%r3,.LC13-.LT1(%r13)
+	l	%r3,0(%r3,%r12):tls_load:sG2
+	l	%r3,0(%r3,%r9)
+
+	/* IE -> LE against global var defined in exec */
+	l	%r3,.LC14-.LT1(%r13)
+	l	%r4,0(%r3,%r12):tls_load:sg1
+	la	%r5,0(%r4,%r9)
+
+	/* IE -> LE against local var */
+	l	%r3,.LC15-.LT1(%r13)
+	l	%r4,0(%r3,%r12):tls_load:sl1
+	la	%r5,0(%r4,%r9)
+
+	/* IE -> LE against hidden var */
+	l	%r3,.LC16-.LT1(%r13)
+	l	%r4,0(%r3,%r12):tls_load:sh1
+	la	%r5,0(%r4,%r9)
+
+	/* IE against global var with small got access (no optimization) */
+	l	%r3,sG3@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+
+	/* IE against global var defined in exec with small got access
+	   (no optimization) */
+	l	%r3,sg3@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+
+	/* IE against local var with small got access (no optimization) */
+	l	%r3,sl3@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+
+	/* IE against hidden var with small got access (no optimization) */
+	l	%r3,sh3@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+
+	/* Function epilog */
+	lm	%r6,%r14,120(%r15)
+	br	%r14
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlsbinpic_64.s b/binutils-2.19/ld/testsuite/ld-s390/tlsbinpic_64.s
new file mode 100644
index 0000000..eeda6ca
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlsbinpic_64.s
@@ -0,0 +1,186 @@
+	.section ".tdata", "awT", @progbits
+	.balign 32
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+	.text
+	.globl	fn2
+	.type	fn2,@function
+	.balign	64
+fn2:
+	/* Function prolog */
+	stmg	%r6,%r14,48(%r15)
+	bras	%r13,.LTN1
+	/* Literal pool */
+.LT1:
+.LC2:
+	.quad	sG1@tlsgd
+.LC3:
+	.quad	sG2@tlsgd
+.LC4:
+	.quad	sg1@tlsgd
+.LC5:
+	.quad	sl1@tlsgd
+.LC6:
+	.quad	sh1@tlsgd
+.LC7:
+	.quad	sl1@tlsldm
+.LC8:
+	.quad	sl1@dtpoff
+.LC9:
+	.quad	sl2@dtpoff
+.LC10:
+	.quad	sh1@tlsldm
+.LC11:
+	.quad	sh1@dtpoff
+.LC12:
+	.quad	sh2@dtpoff
+.LC13:
+	.quad	sG2@gotntpoff
+.LC14:
+	.quad	sg1@gotntpoff
+.LC15:
+	.quad	sl1@gotntpoff
+.LC16:
+	.quad	sh1@gotntpoff
+.LTN1:
+	/* Function prolog */
+	lgr	%r14,%r15
+	aghi	%r15,-160
+	larl	%r12,_GLOBAL_OFFSET_TABLE_
+	stg	%r14,0(%r14)
+
+	/* Extract TCB */
+	ear	%r9,%a0
+	sllg	%r9,%r4,32
+	ear	%r9,%a1
+
+	/* GD -> IE because variable is not defined in executable */
+	lg	%r12,.LC2-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_gdcall:sG1
+	la	%r2,0(%r2,%r9)
+
+	/* GD -> IE because variable is not defined in executable where
+	   the variable is referenced through IE too */
+	lg	%r2,.LC3-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_gdcall:sG2
+	la	%r2,0(%r2,%r9)
+
+	/* GD -> LE with global variable defined in executable */
+	lg	%r2,.LC4-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_gdcall:sg1
+	la	%r2,0(%r2,%r9)
+
+	/* GD -> LE with local variable defined in executable */
+	lg	%r2,.LC5-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_gdcall:sl1
+	la	%r2,0(%r2,%r9)
+
+	/* GD -> LE with hidden variable defined in executable */
+	lg	%r2,.LC6-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_gdcall:sh1
+	la	%r2,0(%r2,%r9)
+
+	/* LD -> LE */
+	lg	%r2,.LC7-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_ldcall:sl1
+	la	%r3,0(%r2,%r9)
+	lg	%r4,.LC8-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+	lg	%r4,.LC9-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+
+	/* LD -> LE against hidden variables */
+	lg	%r2,.LC10-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_ldcall:sh1
+	la	%r3,0(%r2,%r9)
+	lg	%r4,.LC11-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+	lg	%r4,.LC12-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+
+	/* IE against global var  */
+	lg	%r3,.LC13-.LT1(%r13)
+	lg	%r3,0(%r3,%r12):tls_load:sG2
+	la	%r3,0(%r3,%r9)
+
+	/* IE -> LE against global var defined in exec */
+	lg	%r3,.LC14-.LT1(%r13)
+	lg	%r4,0(%r3,%r12):tls_load:sg1
+	la	%r5,0(%r4,%r9)
+
+	/* IE -> LE against local var */
+	lg	%r3,.LC15-.LT1(%r13)
+	lg	%r4,0(%r3,%r12):tls_load:sl2
+	la	%r5,0(%r4,%r9)
+
+	/* IE -> LE against hidden var */
+	lg	%r3,.LC16-.LT1(%r13)
+	lg	%r4,0(%r3,%r12):tls_load:sh1
+	la	%r5,0(%r4,%r9)
+
+	/* IE against global var with larl got access */
+	larl	%r3,sG3@indntpoff
+	lg	%r3,0(%r3,%r12):tls_load:sG3
+	la	%r3,0(%r3,%r9)
+
+	/* IE against global var defined in exec with larl got access */
+	larl	%r3,sg3@indntpoff
+	lg	%r4,0(%r3,%r12):tls_load:sg3
+	la	%r5,0(%r4,%r9)
+
+	/* IE against local var with larl got access */
+	larl	%r3,sl3@indntpoff
+	lg	%r4,0(%r3,%r12):tls_load:sl3
+	la	%r5,0(%r4,%r9)
+	
+	/* IE against hidden var with larl got access */
+	larl	%r3,sh3@indntpoff
+	lg	%r4,0(%r3,%r12):tls_load:sh3
+	la	%r5,0(%r4,%r9)
+
+	/* IE against global var with small got access (no optimization) */
+	lg	%r3,sG3@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+
+	/* IE against global var defined in exec with small got access
+	   (no optimization) */
+	lg	%r3,sg3@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+
+	/* IE against local var with small got access (no optimization) */
+	lg	%r3,sl3@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+
+	/* IE against hidden var with small got access (no optimization) */
+	lg	%r3,sh3@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+	
+	/* Function epilog */
+	lmg	%r6,%r14,208(%r15)
+	br	%r14
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlslib.s b/binutils-2.19/ld/testsuite/ld-s390/tlslib.s
new file mode 100644
index 0000000..3ec87c2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlslib.s
@@ -0,0 +1,17 @@
+	.section ".tdata", "awT", @progbits
+	.globl sG1, sG2, sG3, sG4, sG5, sG6, sG7, sG8,
+sG1:	.long 513
+sG2:	.long 514
+sG3:	.long 515
+sG4:	.long 516
+sG5:	.long 517
+sG6:	.long 518
+sG7:	.long 519
+sG8:	.long 520
+
+	.text
+	/* Dummy.  */
+	.globl __tls_get_offset
+	.type   __tls_get_offset,@function
+__tls_get_offset:
+	br	%r14
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlslib_64.s b/binutils-2.19/ld/testsuite/ld-s390/tlslib_64.s
new file mode 100644
index 0000000..3ec87c2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlslib_64.s
@@ -0,0 +1,17 @@
+	.section ".tdata", "awT", @progbits
+	.globl sG1, sG2, sG3, sG4, sG5, sG6, sG7, sG8,
+sG1:	.long 513
+sG2:	.long 514
+sG3:	.long 515
+sG4:	.long 516
+sG5:	.long 517
+sG6:	.long 518
+sG7:	.long 519
+sG8:	.long 520
+
+	.text
+	/* Dummy.  */
+	.globl __tls_get_offset
+	.type   __tls_get_offset,@function
+__tls_get_offset:
+	br	%r14
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlspic.dd b/binutils-2.19/ld/testsuite/ld-s390/tlspic.dd
new file mode 100644
index 0000000..6e9da5d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlspic.dd
@@ -0,0 +1,189 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: -m31
+#ld: -shared -melf_s390
+#objdump: -dzrj.text
+#target: s390-*-*
+
+.*: +file format elf32-s390
+
+Disassembly of section .text:
+
+0+[0-9a-f]+ <fn1>:
+# function prolog
+ +[0-9a-f]+:	90 6e f0 18       	stm	%r6,%r14,24\(%r15\)
+ +[0-9a-f]+:	a7 d5 00 30       	bras	%r13,[0-9a-f]+ <fn1\+0x64>
+# _GLOBAL_OFFSET_TABLE_-.LT1
+ +[0-9a-f]+:	[0-9a-f ]+       	.long	0x[0-9a-f]+
+# __tls_get_addr@plt-.LT1
+ +[0-9a-f]+:	[0-9a-f ]+       	.long	0x[0-9a-f]+
+# sg1@tlsgd
+ +[0-9a-f]+:	00 00 00 38       	.long	0x00000038
+# sg2@tlsgd
+ +[0-9a-f]+:	00 00 00 48       	.long	0x00000048
+# sl1@tlsgd
+ +[0-9a-f]+:	00 00 00 10       	.long	0x00000010
+# sl2@tlsgd
+ +[0-9a-f]+:	00 00 00 18       	.long	0x00000018
+# sh1@tlsgd
+ +[0-9a-f]+:	00 00 00 4c       	.long	0x0000004c
+# sh2@tlsgd
+ +[0-9a-f]+:	00 00 00 54       	.long	0x00000054
+# sH1@tlsgd
+ +[0-9a-f]+:	00 00 00 28       	.long	0x00000028
+# sH2@tlsgd
+ +[0-9a-f]+:	00 00 00 30       	.long	0x00000030
+# sl1@tlsldm
+ +[0-9a-f]+:	00 00 00 20       	.long	0x00000020
+# sl1@dtpoff
+ +[0-9a-f]+:	00 00 00 20       	.long	0x00000020
+# sl2@dtpoff
+ +[0-9a-f]+:	00 00 00 24       	.long	0x00000024
+# sh1@tlsldm
+ +[0-9a-f]+:	00 00 00 20       	.long	0x00000020
+# sh1@dtpoff
+ +[0-9a-f]+:	00 00 00 40       	.long	0x00000040
+# sh2@dtpoff
+ +[0-9a-f]+:	00 00 00 44       	.long	0x00000044
+# sH1@tlsldm
+ +[0-9a-f]+:	00 00 00 20       	.long	0x00000020
+# sH1@dtpoff
+ +[0-9a-f]+:	00 00 00 60       	.long	0x00000060
+# sH2@dtpoff
+ +[0-9a-f]+:	00 00 00 64       	.long	0x00000064
+# sg2@gotntpoff
+ +[0-9a-f]+:	00 00 00 48       	.long	0x00000048
+# sl2@gotntpoff
+ +[0-9a-f]+:	00 00 00 18       	.long	0x00000018
+# sh2@gotntpoff
+ +[0-9a-f]+:	00 00 00 54       	.long	0x00000054
+# sH2@gotntpoff
+ +[0-9a-f]+:	00 00 00 30       	.long	0x00000030
+# function prolog
+ +[0-9a-f]+:	18 ef             	lr	%r14,%r15
+ +[0-9a-f]+:	58 c0 d0 00       	l	%r12,0\(%r13\)
+ +[0-9a-f]+:	a7 fa ff a0       	ahi	%r15,-96
+ +[0-9a-f]+:	41 cc d0 00       	la	%r12,0\(%r12,%r13\)
+ +[0-9a-f]+:	50 e0 e0 00       	st	%r14,0\(%r14\)
+# Extract TCB and load branch offset
+ +[0-9a-f]+:	b2 4f 00 90       	ear	%r9,%a0
+ +[0-9a-f]+:	58 70 d0 04       	l	%r7,4\(%r13\)
+# GD
+ +[0-9a-f]+:	58 20 d0 08       	l	%r2,8\(%r13\)
+ +[0-9a-f]+:	4d e7 d0 00       	bas	%r14,0\(%r7,%r13\)
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> IE because variable is referenced through IE too
+ +[0-9a-f]+:	58 20 d0 0c       	l	%r2,12\(%r13\)
+ +[0-9a-f]+:	58 22 c0 00       	l	%r2,0\(%r2,%r12\)
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD against local variable
+ +[0-9a-f]+:	58 20 d0 10       	l	%r2,16\(%r13\)
+ +[0-9a-f]+:	4d e7 d0 00       	bas	%r14,0\(%r7,%r13\)
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> IE against local variable referenced through IE too
+ +[0-9a-f]+:	58 20 d0 14       	l	%r2,20\(%r13\)
+ +[0-9a-f]+:	58 22 c0 00       	l	%r2,0\(%r2,%r12\)
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD against hidden and local variable
+ +[0-9a-f]+:	58 20 d0 18       	l	%r2,24\(%r13\)
+ +[0-9a-f]+:	4d e7 d0 00       	bas	%r14,0\(%r7,%r13\)
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> IE against hidden and local variable referenced through
+# IE too
+ +[0-9a-f]+:	58 20 d0 1c       	l	%r2,28\(%r13\)
+ +[0-9a-f]+:	58 22 c0 00       	l	%r2,0\(%r2,%r12\)
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD against hidden but not local variable
+ +[0-9a-f]+:	58 20 d0 20       	l	%r2,32\(%r13\)
+ +[0-9a-f]+:	4d e7 d0 00       	bas	%r14,0\(%r7,%r13\)
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> IE against hidden but not local variable referenced through
+# IE too
+ +[0-9a-f]+:	58 20 d0 24       	l	%r2,36\(%r13\)
+ +[0-9a-f]+:	58 22 c0 00       	l	%r2,0\(%r2,%r12\)
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# LD
+ +[0-9a-f]+:	58 20 d0 28       	l	%r2,40\(%r13\)
+ +[0-9a-f]+:	4d e7 d0 00       	bas	%r14,0\(%r7,%r13\)
+ +[0-9a-f]+:	41 32 90 00       	la	%r3,0\(%r2,%r9\)
+ +[0-9a-f]+:	58 40 d0 2c       	l	%r4,44\(%r13\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+ +[0-9a-f]+:	58 40 d0 30       	l	%r4,48\(%r13\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+# LD against hidden and local variables
+ +[0-9a-f]+:	58 20 d0 34       	l	%r2,52\(%r13\)
+ +[0-9a-f]+:	4d e7 d0 00       	bas	%r14,0\(%r7,%r13\)
+ +[0-9a-f]+:	41 32 90 00       	la	%r3,0\(%r2,%r9\)
+ +[0-9a-f]+:	58 40 d0 38       	l	%r4,56\(%r13\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+ +[0-9a-f]+:	58 40 d0 34       	l	%r4,52\(%r13\)
+ +[0-9a-f]+:	41 55 30 00       	la	%r5,0\(%r5,%r3\)
+# LD against hidden but not local variables
+ +[0-9a-f]+:	58 20 d0 40       	l	%r2,64\(%r13\)
+ +[0-9a-f]+:	4d e7 d0 00       	bas	%r14,0\(%r7,%r13\)
+ +[0-9a-f]+:	41 32 90 00       	la	%r3,0\(%r2,%r9\)
+ +[0-9a-f]+:	58 30 d0 44       	l	%r3,68\(%r13\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+ +[0-9a-f]+:	58 40 d0 48       	l	%r4,72\(%r13\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+# IE against global var
+ +[0-9a-f]+:	58 30 d0 4c       	l	%r3,76\(%r13\)
+ +[0-9a-f]+:	58 33 c0 00       	l	%r3,0\(%r3,%r12\)
+ +[0-9a-f]+:	41 33 30 00       	la	%r3,0\(%r3,%r3\)
+# IE against local var
+ +[0-9a-f]+:	58 30 d0 50       	l	%r3,80\(%r13\)
+ +[0-9a-f]+:	58 43 c0 00       	l	%r4,0\(%r3,%r12\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+# IE against hidden and local var
+ +[0-9a-f]+:	58 30 d0 54       	l	%r3,84\(%r13\)
+ +[0-9a-f]+:	58 43 c0 00       	l	%r4,0\(%r3,%r12\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+# IE against hidden but not local var
+ +[0-9a-f]+:	58 30 d0 58       	l	%r3,88\(%r13\)
+ +[0-9a-f]+:	58 43 c0 00       	l	%r4,0\(%r3,%r12\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+# IE against global var with small got access (no optimization)
+ +[0-9a-f]+:	58 30 c0 34       	l	%r3,52\(%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE against local var with small got access (no optimization)
+ +[0-9a-f]+:	58 30 c0 1c       	l	%r3,28\(%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE against hidden and local var with small got access
+# (no optimization)
+ +[0-9a-f]+:	58 30 c0 40       	l	%r3,64\(%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE against hidden but not local var with small got access
+# (no optimization)
+ +[0-9a-f]+:	58 30 c0 44       	l	%r3,68\(%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# function prolog
+ +[0-9a-f]+:	98 6e f0 78       	lm	%r6,%r14,120\(%r15\)
+ +[0-9a-f]+:	07 fe             	br	%r14
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlspic.rd b/binutils-2.19/ld/testsuite/ld-s390/tlspic.rd
new file mode 100644
index 0000000..1e79a2e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlspic.rd
@@ -0,0 +1,142 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: -m31
+#ld: -shared -melf_s390
+#readelf: -Ssrl
+#target: s390-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0  0
+ +\[[ 0-9]+\] .hash .*
+ +\[[ 0-9]+\] .dynsym .*
+ +\[[ 0-9]+\] .dynstr .*
+ +\[[ 0-9]+\] .rela.dyn .*
+ +\[[ 0-9]+\] .rela.plt .*
+ +\[[ 0-9]+\] .plt .*
+ +\[[ 0-9]+\] .text +PROGBITS .*
+ +\[[ 0-9]+\] .tdata +PROGBITS .* 0+60 00 WAT  0 +0 32
+ +\[[ 0-9]+\] .tbss +NOBITS .* 0+20 00 WAT  0 +0  1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC .*
+ +\[[ 0-9]+\] .got +PROGBITS .*
+ +\[[ 0-9]+\] .shstrtab .*
+ +\[[ 0-9]+\] .symtab .*
+ +\[[ 0-9]+\] .strtab .*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x[0-9a-f]+
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz MemSiz  Flg Align
+  LOAD .* R E 0x1000
+  LOAD .* RW  0x1000
+  DYNAMIC .* RW  0x4
+  TLS .* 0x0+60 0x0+80 R +0x20
+
+ Section to Segment mapping:
+  Segment Sections...
+ +00 +.hash .dynsym .dynstr .rela.dyn .rela.plt .plt .text 
+ +01 +.tdata .dynamic .got 
+ +02 +.dynamic 
+ +03 +.tdata .tbss 
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
+ Offset +Info +Type +Sym.Value  Sym. Name \+ Addend
+[0-9a-f ]+R_390_TLS_DTPMOD +0+
+[0-9a-f ]+R_390_TLS_TPOFF +0+24
+[0-9a-f ]+R_390_TLS_TPOFF +0+30
+[0-9a-f ]+R_390_TLS_DTPMOD +0+
+[0-9a-f ]+R_390_TLS_DTPMOD +0+
+[0-9a-f ]+R_390_TLS_TPOFF +0+64
+[0-9a-f ]+R_390_TLS_TPOFF +0+50
+[0-9a-f ]+R_390_TLS_TPOFF +0+70
+[0-9a-f ]+R_390_TLS_DTPMOD +0+
+[0-9a-f ]+R_390_TLS_TPOFF +0+44
+[0-9a-f ]+R_390_TLS_TPOFF +0+10 +sg5 \+ 0
+[0-9a-f ]+R_390_TLS_DTPMOD  0+ +sg1 \+ 0
+[0-9a-f ]+R_390_TLS_DTPOFF  0+ +sg1 \+ 0
+[0-9a-f ]+R_390_TLS_TPOFF +0+4 +sg2 \+ 0
+
+Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ Offset +Info +Type +Sym.Value  Sym. Name \+ Addend
+[0-9a-f ]+R_390_JMP_SLOT +0+ +__tls_get_offset \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value  Size Type +Bind +Vis +Ndx Name
+.* NOTYPE  LOCAL  DEFAULT  UND 
+.* SECTION LOCAL  DEFAULT +7 
+.* SECTION LOCAL  DEFAULT +8 
+.* TLS +GLOBAL DEFAULT +8 sg8
+.* TLS +GLOBAL DEFAULT +8 sg3
+.* TLS +GLOBAL DEFAULT +8 sg4
+.* TLS +GLOBAL DEFAULT +8 sg5
+.* NOTYPE  GLOBAL DEFAULT  UND __tls_get_offset
+.* TLS +GLOBAL DEFAULT +8 sg1
+.* FUNC +GLOBAL DEFAULT +7 fn1
+.* NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.* TLS +GLOBAL DEFAULT +8 sg2
+.* TLS +GLOBAL DEFAULT +8 sg6
+.* TLS +GLOBAL DEFAULT +8 sg7
+.* NOTYPE  GLOBAL DEFAULT  ABS _edata
+.* NOTYPE  GLOBAL DEFAULT  ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value  Size Type +Bind +Vis +Ndx Name
+.* NOTYPE  LOCAL  DEFAULT  UND 
+.* SECTION LOCAL  DEFAULT +1 
+.* SECTION LOCAL  DEFAULT +2 
+.* SECTION LOCAL  DEFAULT +3 
+.* SECTION LOCAL  DEFAULT +4 
+.* SECTION LOCAL  DEFAULT +5 
+.* SECTION LOCAL  DEFAULT +6 
+.* SECTION LOCAL  DEFAULT +7 
+.* SECTION LOCAL  DEFAULT +8 
+.* SECTION LOCAL  DEFAULT +9 
+.* SECTION LOCAL  DEFAULT +10 
+.* SECTION LOCAL  DEFAULT +11 
+.* TLS +LOCAL  DEFAULT +8 sl1
+.* TLS +LOCAL  DEFAULT +8 sl2
+.* TLS +LOCAL  DEFAULT +8 sl3
+.* TLS +LOCAL  DEFAULT +8 sl4
+.* TLS +LOCAL  DEFAULT +8 sl5
+.* TLS +LOCAL  DEFAULT +8 sl6
+.* TLS +LOCAL  DEFAULT +8 sl7
+.* TLS +LOCAL  DEFAULT +8 sl8
+.* TLS +LOCAL  HIDDEN +9 sH1
+.* OBJECT  LOCAL  HIDDEN  ABS _DYNAMIC
+.* TLS +LOCAL  HIDDEN +8 sh3
+.* TLS +LOCAL  HIDDEN +9 sH2
+.* TLS +LOCAL  HIDDEN +9 sH7
+.* TLS +LOCAL  HIDDEN +8 sh7
+.* TLS +LOCAL  HIDDEN +8 sh8
+.* TLS +LOCAL  HIDDEN +9 sH4
+.* TLS +LOCAL  HIDDEN +8 sh4
+.* TLS +LOCAL  HIDDEN +9 sH3
+.* TLS +LOCAL  HIDDEN +8 sh5
+.* TLS +LOCAL  HIDDEN +9 sH5
+.* TLS +LOCAL  HIDDEN +9 sH6
+.* TLS +LOCAL  HIDDEN +9 sH8
+.* TLS +LOCAL  HIDDEN +8 sh1
+.* OBJECT  LOCAL  HIDDEN  ABS _GLOBAL_OFFSET_TABLE_
+.* TLS +LOCAL  HIDDEN +8 sh2
+.* TLS +LOCAL  HIDDEN +8 sh6
+.* TLS +GLOBAL DEFAULT +8 sg8
+.* TLS +GLOBAL DEFAULT +8 sg3
+.* TLS +GLOBAL DEFAULT +8 sg4
+.* TLS +GLOBAL DEFAULT +8 sg5
+.* NOTYPE  GLOBAL DEFAULT  UND __tls_get_offset
+.* TLS +GLOBAL DEFAULT +8 sg1
+.* FUNC +GLOBAL DEFAULT +7 fn1
+.* NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.* TLS +GLOBAL DEFAULT +8 sg2
+.* TLS +GLOBAL DEFAULT +8 sg6
+.* TLS +GLOBAL DEFAULT +8 sg7
+.* NOTYPE  GLOBAL DEFAULT  ABS _edata
+.* NOTYPE  GLOBAL DEFAULT  ABS _end
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlspic.sd b/binutils-2.19/ld/testsuite/ld-s390/tlspic.sd
new file mode 100644
index 0000000..6e32dea
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlspic.sd
@@ -0,0 +1,16 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: -m31
+#ld: -shared -melf_s390
+#objdump: -sj.got
+#target: s390-*-*
+
+.*: +file format elf32-s390
+
+Contents of section .got:
+ [0-9a-f]+ [0-9a-f]+ 00000000 00000000 [0-9a-f]+  .*
+ [0-9a-f]+ 00000000 00000020 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000060  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000000  .*
+ [0-9a-f]+ 00000040 00000000  +.*
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlspic.td b/binutils-2.19/ld/testsuite/ld-s390/tlspic.td
new file mode 100644
index 0000000..265dbe2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlspic.td
@@ -0,0 +1,16 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: -m31
+#ld: -shared -melf_s390
+#objdump: -sj.tdata
+#target: s390-*-*
+
+.*: +file format elf32-s390
+
+Contents of section .tdata:
+ [0-9a-f]+ 00000011 00000012 00000013 00000014  .*
+ [0-9a-f]+ 00000015 00000016 00000017 00000018  .*
+ [0-9a-f]+ 00000041 00000042 00000043 00000044  .*
+ [0-9a-f]+ 00000045 00000046 00000047 00000048  .*
+ [0-9a-f]+ 00000101 00000102 00000103 00000104  .*
+ [0-9a-f]+ 00000105 00000106 00000107 00000108  .*
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlspic1.s b/binutils-2.19/ld/testsuite/ld-s390/tlspic1.s
new file mode 100644
index 0000000..28b9c3a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlspic1.s
@@ -0,0 +1,208 @@
+	.section ".tdata", "awT", @progbits
+	.balign 32
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+	.text
+	.globl	fn1
+	.type	fn1,@function
+	.balign 64
+fn1:
+	/* Funtion prolog */
+	stm	%r6,%r14,24(%r15)
+	bras	%r13,.LTN1
+	/* Literal pool */
+.LT1:
+.LC0:
+	.long	_GLOBAL_OFFSET_TABLE_-.LT1
+.LC1:
+	.long	__tls_get_offset@plt-.LT1
+.LC2:
+	.long	sg1@tlsgd
+.LC3:
+	.long	sg2@tlsgd
+.LC4:
+	.long	sl1@tlsgd
+.LC5:
+	.long	sl2@tlsgd
+.LC6:
+	.long	sh1@tlsgd
+.LC7:
+	.long	sh2@tlsgd
+.LC8:
+	.long	sH1@tlsgd
+.LC9:
+	.long	sH2@tlsgd
+.LC10:
+	.long	sl1@tlsldm
+.LC11:
+	.long	sl1@dtpoff
+.LC12:
+	.long	sl2@dtpoff
+.LC13:
+	.long	sh1@tlsldm
+.LC14:
+	.long	sh1@dtpoff
+.LC15:
+	.long	sh2@dtpoff
+.LC16:
+	.long	sH1@tlsldm
+.LC17:
+	.long	sH1@dtpoff
+.LC18:
+	.long	sH2@dtpoff
+.LC19:
+	.long	sg2@gotntpoff
+.LC20:
+	.long	sl2@gotntpoff
+.LC21:
+	.long	sh2@gotntpoff
+.LC22:
+	.long	sH2@gotntpoff
+.LTN1:	
+	/* Funtion prolog */
+	lr	%r14,%r15
+	l	%r12,.LC0-.LT1(%r13)
+	ahi	%r15,-96
+	la	%r12,0(%r12,%r13)
+	st	%r14,0(%r14)
+
+	/* Extract TCB and load branch offset */
+	ear	%r9,%a0
+	l	%r7,.LC1-.LT1(%r13)
+
+	/* GD */
+	l	%r2,.LC2-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_gdcall:sg1
+	la	%r2,0(%r2,%r9)
+
+	/* GD -> IE because variable is referenced through IE too */
+	l	%r2,.LC3-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_gdcall:sg2
+	la	%r2,0(%r2,%r9)
+
+	/* GD against local variable */
+	l	%r2,.LC4-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_gdcall:sl1
+	la	%r2,0(%r2,%r9)
+	
+	/* GD -> IE against local variable referenced through IE too */
+	l	%r2,.LC5-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_gdcall:sl2
+	la	%r2,0(%r2,%r9)
+
+	/* GD against hidden and local variable */
+	l	%r2,.LC6-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_gdcall:sh1
+	la	%r2,0(%r2,%r9)
+		
+	/* GD -> IE against hidden and local variable referenced through
+	   IE too */
+	l	%r2,.LC7-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_gdcall:sh2
+	la	%r2,0(%r2,%r9)
+
+	/* GD against hidden but not local variable */
+	l	%r2,.LC8-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_gdcall:sH1
+	la	%r2,0(%r2,%r9)
+
+	/* GD -> IE against hidden but not local variable referenced through
+	   IE too */
+	l	%r2,.LC9-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_gdcall:sH2
+	la	%r2,0(%r2,%r9)
+
+	/* LD */
+	l	%r2,.LC10-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_ldcall:sl1
+	la	%r3,0(%r2,%r9)
+	l	%r4,.LC11-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+	l	%r4,.LC12-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+
+	/* LD against hidden and local variables */
+	l	%r2,.LC13-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_ldcall:sh1
+	la	%r3,0(%r2,%r9)
+	l	%r4,.LC14-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+	l	%r4,.LC13-.LT1(%r13)
+	la	%r5,0(%r5,%r3)
+	
+	/* LD against hidden but not local variables */
+	l	%r2,.LC16-.LT1(%r13)
+	bas	%r14,0(%r7,%r13):tls_ldcall:sH1
+	la	%r3,0(%r2,%r9)
+	l	%r3,.LC17-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+	l	%r4,.LC18-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+
+	/* IE against global var  */
+	l	%r3,.LC19-.LT1(%r13)
+	l	%r3,0(%r3,%r12):tls_load:sg2
+	la	%r3,0(%r3,%r3)
+
+	/* IE against local var  */
+	l	%r3,.LC20-.LT1(%r13)
+	l	%r4,0(%r3,%r12):tls_load:sl2
+	la	%r5,0(%r4,%r3)
+
+	/* IE against hidden and local var  */
+	l	%r3,.LC21-.LT1(%r13)
+	l	%r4,0(%r3,%r12):tls_load:sh2
+	la	%r5,0(%r4,%r3)
+	
+	/* IE against hidden but not local var  */
+	l	%r3,.LC22-.LT1(%r13)
+	l	%r4,0(%r3,%r12):tls_load:sH2
+	la	%r5,0(%r4,%r3)
+
+	/* IE against global var with small got access (no optimization) */
+	l	%r3,sg5@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+
+	/* IE against local var with small got access (no optimization) */
+	l	%r3,sl5@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+
+	/* IE against hidden and local var with small got access
+	   (no optimization) */
+	l	%r3,sh5@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+
+	/* IE against hidden but not local var with small got access
+	   (no optimization) */
+	l	%r3,sH5@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+
+	/* Function epilog */
+	lm	%r6,%r14,120(%r15)
+	br	%r14
+
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlspic1_64.s b/binutils-2.19/ld/testsuite/ld-s390/tlspic1_64.s
new file mode 100644
index 0000000..4e50008
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlspic1_64.s
@@ -0,0 +1,224 @@
+	.section ".tdata", "awT", @progbits
+	.balign 32
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+	.text
+	.globl	fn1
+	.type	fn1,@function
+	.balign	64
+fn1:
+	/* Funtion prolog */
+	stmg	%r6,%r14,48(%r15)
+	bras	%r13,.LTN1
+	/* Literal pool */
+.LT1:
+.LC2:
+	.quad	sg1@tlsgd
+.LC3:
+	.quad	sg2@tlsgd
+.LC4:
+	.quad	sl1@tlsgd
+.LC5:
+	.quad	sl2@tlsgd
+.LC6:
+	.quad	sh1@tlsgd
+.LC7:
+	.quad	sh2@tlsgd
+.LC8:
+	.quad	sH1@tlsgd
+.LC9:
+	.quad	sH2@tlsgd
+.LC10:
+	.quad	sl1@tlsldm
+.LC11:
+	.quad	sl1@dtpoff
+.LC12:
+	.quad	sl2@dtpoff
+.LC13:
+	.quad	sh1@tlsldm
+.LC14:
+	.quad	sh1@dtpoff
+.LC15:
+	.quad	sh2@dtpoff
+.LC16:
+	.quad	sH1@tlsldm
+.LC17:
+	.quad	sH1@dtpoff
+.LC18:
+	.quad	sH2@dtpoff
+.LC19:
+	.quad	sg2@gotntpoff
+.LC20:
+	.quad	sl2@gotntpoff
+.LC21:
+	.quad	sh2@gotntpoff
+.LC22:
+	.quad	sH2@gotntpoff
+.LTN1:	
+	/* Funtion prolog */
+	lgr	%r14,%r15
+	larl	%r12,_GLOBAL_OFFSET_TABLE_
+	aghi	%r15,-160
+	stg	%r14,0(%r14)
+
+	/* Extract TCB */
+	ear	%r9,%a0
+	sllg	%r9,%r4,32
+	ear	%r9,%a1
+
+	/* GD */
+	lg	%r2,.LC2-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_gdcall:sg1
+	la	%r2,0(%r2,%r9)
+
+	/* GD -> IE because variable is referenced through IE too */
+	lg	%r2,.LC3-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_gdcall:sg2
+	la	%r2,0(%r2,%r9)
+
+	/* GD against local variable */
+	lg	%r2,.LC4-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_gdcall:sl1
+	la	%r2,0(%r2,%r9)
+
+	/* GD -> IE against local variable referenced through IE too */
+	lg	%r2,.LC5-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_gdcall:sl2
+	la	%r2,0(%r2,%r9)
+
+	/* GD against hidden and local variable */
+	lg	%r2,.LC6-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_gdcall:sh1
+	la	%r2,0(%r2,%r9)
+	
+	/* GD -> IE against hidden and local variable referenced through
+	   IE too */
+	lg	%r2,.LC7-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_gdcall:sh2
+	la	%r2,0(%r2,%r9)
+
+	/* GD against hidden but not local variable */
+	lg	%r2,.LC8-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_gdcall:sH1
+	la	%r2,0(%r2,%r9)
+
+	/* GD -> IE against hidden but not local variable referenced through
+	   IE too */
+	lg	%r2,.LC9-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_gdcall:sH2
+	la	%r2,0(%r2,%r9)
+
+	/* LD */
+	lg	%r2,.LC10-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_ldcall:sl1
+	la	%r3,0(%r2,%r9)
+	lg	%r4,.LC11-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+	lg	%r4,.LC12-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+
+	/* LD against hidden and local variables */
+	lg	%r2,.LC13-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_ldcall:sh1
+	la	%r3,0(%r2,%r9)
+	lg	%r4,.LC14-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+	lg	%r4,.LC15-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+	
+	/* LD against hidden but not local variables */
+	lg	%r2,.LC16-.LT1(%r13)
+	brasl	%r14,__tls_get_offset@plt:tls_ldcall:sH1
+	la	%r3,0(%r2,%r9)
+	lg	%r4,.LC17-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+	lg	%r4,.LC18-.LT1(%r13)
+	la	%r5,0(%r4,%r3)
+
+	/* IE against global var  */
+	lg	%r3,.LC19-.LT1(%r13)
+	lg	%r3,0(%r3,%r12):tls_load:sg2
+	la	%r3,0(%r3,%r9)
+
+	/* IE against local var  */
+	lg	%r3,.LC20-.LT1(%r13)
+	lg	%r4,0(%r3,%r12):tls_load:sl2
+	la	%r5,0(%r4,%r9)
+
+	/* IE against hidden and local var  */
+	lg	%r3,.LC21-.LT1(%r13)
+	lg	%r4,0(%r3,%r12):tls_load:sh2
+	la	%r5,0(%r4,%r9)
+	
+	/* IE against hidden but not local var  */
+	lg	%r3,.LC22-.LT1(%r13)
+	lg	%r4,0(%r3,%r12):tls_load:sH2
+	la	%r5,0(%r4,%r9)
+
+	/* IE against global var with larl got access */
+	larl	%r3,sg5@indntpoff
+	lg	%r3,0(%r3,%r12):tls_load:sg2
+	la	%r3,0(%r3,%r9)
+
+	/* IE against local var with larl got access */
+	larl	%r3,sl5@indntpoff
+	lg	%r4,0(%r3,%r12):tls_load:sl2
+	la	%r5,0(%r4,%r9)
+
+	/* IE against hidden and local var with larl got access */
+	larl	%r3,sh5@indntpoff
+	lg	%r4,0(%r3,%r12):tls_load:sh2
+	la	%r5,0(%r4,%r9)
+	
+	/* IE against hidden but not local var with larl got access */
+	larl	%r3,sH5@indntpoff
+	lg	%r4,0(%r3,%r12):tls_load:sH2
+	la	%r5,0(%r4,%r9)
+
+	/* IE against global var with small got access (no optimization) */
+	lg	%r3,sg5@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+
+	/* IE against local var with small got access (no optimization) */
+	lg	%r3,sl5@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+
+	/* IE against hidden and local var with small got access
+	   (no optimization) */
+	lg	%r3,sh5@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+
+	/* IE against hidden but not local var with small got access
+	   (no optimization) */
+	lg	%r3,sH5@gotntpoff(%r12)
+	la	%r3,0(%r3,%r9)
+
+	/* Function epilog */
+	lmg	%r6,%r14,208(%r15)
+	br	%r14
+	
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlspic2.s b/binutils-2.19/ld/testsuite/ld-s390/tlspic2.s
new file mode 100644
index 0000000..5513f9b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlspic2.s
@@ -0,0 +1,11 @@
+	.section ".tbss", "awT", @nobits
+	.globl sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+	.hidden sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+sH1:	.space 4
+sH2:	.space 4
+sH3:	.space 4
+sH4:	.space 4
+sH5:	.space 4
+sH6:	.space 4
+sH7:	.space 4
+sH8:	.space 4
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlspic2_64.s b/binutils-2.19/ld/testsuite/ld-s390/tlspic2_64.s
new file mode 100644
index 0000000..5513f9b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlspic2_64.s
@@ -0,0 +1,11 @@
+	.section ".tbss", "awT", @nobits
+	.globl sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+	.hidden sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+sH1:	.space 4
+sH2:	.space 4
+sH3:	.space 4
+sH4:	.space 4
+sH5:	.space 4
+sH6:	.space 4
+sH7:	.space 4
+sH8:	.space 4
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlspic_64.dd b/binutils-2.19/ld/testsuite/ld-s390/tlspic_64.dd
new file mode 100644
index 0000000..fea1671
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlspic_64.dd
@@ -0,0 +1,202 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: -m64 -Aesame
+#ld: -shared -melf64_s390
+#objdump: -dzrj.text
+#target: s390x-*-*
+
+.*: +file format elf64-s390
+
+Disassembly of section .text:
+
+0+[0-9a-f]+ <fn1>:
+# function prolog
+ +[0-9a-f]+:	eb 6e f0 30 00 24 	stmg	%r6,%r14,48\(%r15\)
+ +[0-9a-f]+:	a7 d5 00 56       	bras	%r13,[0-9a-f]+ <fn1\+0xb2>
+# sg1@tlsgd
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 70       	.long	0x00000070
+# sg2@tlsgd
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 90       	.long	0x00000090
+# sl1@tlsgd
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 20       	.long	0x00000020
+# sl2@tlsgd
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 30       	.long	0x00000030
+# sh1@tlsgd
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 98       	.long	0x00000098
+# sh2@tlsgd
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 a8       	.long	0x000000a8
+# sH1@tlsgd
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 50       	.long	0x00000050
+# sH2@tlsgd
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 60       	.long	0x00000060
+# sl1@tlsldm
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 40       	.long	0x00000040
+# sl1@dtpoff
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 20       	.long	0x00000020
+# sl2@dtpoff
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 24       	.long	0x00000024
+# sh1@tlsldm
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 40       	.long	0x00000040
+# sh1@dtpoff
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 40       	.long	0x00000040
+# sh2@dtpoff
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 44       	.long	0x00000044
+# sH1@tlsldm
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 40       	.long	0x00000040
+# sH1@dtpoff
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 60       	.long	0x00000060
+# sH2@dtpoff
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 64       	.long	0x00000064
+# sg2@gotntpoff
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 90       	.long	0x00000090
+# sl2@gotntpoff
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 30       	.long	0x00000030
+# sh2@gotntpoff
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 a8       	.long	0x000000a8
+# sH2@gotntpoff
+ +[0-9a-f]+:	00 00 00 00       	.long	0x00000000
+ +[0-9a-f]+:	00 00 00 60       	.long	0x00000060
+# function prolog
+ +[0-9a-f]+:	b9 04 00 ef       	lgr	%r14,%r15
+ +[0-9a-f]+:	c0 c0 [0-9a-f ]+ 	larl	%r12,[0-9a-f]+ <_GLOBAL_OFFSET_TABLE_>
+ +[0-9a-f]+:	a7 fb ff 60       	aghi	%r15,-160
+ +[0-9a-f]+:	e3 e0 e0 00 00 24 	stg	%r14,0\(%r14\)
+# extract TCB
+ +[0-9a-f]+:	b2 4f 00 90       	ear	%r9,%a0
+ +[0-9a-f]+:	eb 94 00 20 00 0d 	sllg	%r9,%r4,32
+ +[0-9a-f]+:	b2 4f 00 91       	ear	%r9,%a1
+# GD
+ +[0-9a-f]+:	e3 20 d0 00 00 04 	lg	%r2,0\(%r13\)
+ +[0-9a-f]+:	c0 e5 [0-9a-f ]+ 	brasl	%r14,[0-9a-f]+ <.*>
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> IE because variable is referenced through IE too
+ +[0-9a-f]+:	e3 20 d0 08 00 04 	lg	%r2,8\(%r13\)
+ +[0-9a-f]+:	e3 22 c0 00 00 04 	lg	%r2,0\(%r2,%r12\)
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD against local variable
+ +[0-9a-f]+:	e3 20 d0 10 00 04 	lg	%r2,16\(%r13\)
+ +[0-9a-f]+:	c0 e5 [0-9a-f ]+ 	brasl	%r14,[0-9a-f]+ <.*>
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> IE against local variable referenced through IE too
+ +[0-9a-f]+:	e3 20 d0 18 00 04 	lg	%r2,24\(%r13\)
+ +[0-9a-f]+:	e3 22 c0 00 00 04 	lg	%r2,0\(%r2,%r12\)
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD against hidden and local variable
+ +[0-9a-f]+:	e3 20 d0 20 00 04 	lg	%r2,32\(%r13\)
+ +[0-9a-f]+:	c0 e5 [0-9a-f ]+ 	brasl	%r14,[0-9a-f]+ <.*>
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> IE against hidden and local variable referenced through
+# IE too
+ +[0-9a-f]+:	e3 20 d0 28 00 04 	lg	%r2,40\(%r13\)
+ +[0-9a-f]+:	e3 22 c0 00 00 04 	lg	%r2,0\(%r2,%r12\)
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD against hidden but not local variable
+ +[0-9a-f]+:	e3 20 d0 30 00 04 	lg	%r2,48\(%r13\)
+ +[0-9a-f]+:	c0 e5 [0-9a-f ]+ 	brasl	%r14,[0-9a-f]+ <.*>
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# GD -> IE against hidden but not local variable referenced through
+# IE too
+ +[0-9a-f]+:	e3 20 d0 38 00 04 	lg	%r2,56\(%r13\)
+ +[0-9a-f]+:	e3 22 c0 00 00 04 	lg	%r2,0\(%r2,%r12\)
+ +[0-9a-f]+:	41 22 90 00       	la	%r2,0\(%r2,%r9\)
+# LD
+ +[0-9a-f]+:	e3 20 d0 40 00 04 	lg	%r2,64\(%r13\)
+ +[0-9a-f]+:	c0 e5 [0-9a-f ]+ 	brasl	%r14,[0-9a-f]+ <.*>
+ +[0-9a-f]+:	41 32 90 00       	la	%r3,0\(%r2,%r9\)
+ +[0-9a-f]+:	e3 40 d0 48 00 04 	lg	%r4,72\(%r13\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+ +[0-9a-f]+:	e3 40 d0 50 00 04 	lg	%r4,80\(%r13\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+# LD against hidden and local variables
+ +[0-9a-f]+:	e3 20 d0 58 00 04 	lg	%r2,88\(%r13\)
+ +[0-9a-f]+:	c0 e5 [0-9a-f ]+ 	brasl	%r14,[0-9a-f]+ <.*>
+ +[0-9a-f]+:	41 32 90 00       	la	%r3,0\(%r2,%r9\)
+ +[0-9a-f]+:	e3 40 d0 60 00 04 	lg	%r4,96\(%r13\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+ +[0-9a-f]+:	e3 40 d0 68 00 04 	lg	%r4,104\(%r13\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+# LD against hidden but not local variables
+ +[0-9a-f]+:	e3 20 d0 70 00 04 	lg	%r2,112\(%r13\)
+ +[0-9a-f]+:	c0 e5 [0-9a-f ]+ 	brasl	%r14,[0-9a-f]+ <.*>
+ +[0-9a-f]+:	41 32 90 00       	la	%r3,0\(%r2,%r9\)
+ +[0-9a-f]+:	e3 40 d0 78 00 04 	lg	%r4,120\(%r13\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+ +[0-9a-f]+:	e3 40 d0 80 00 04 	lg	%r4,128\(%r13\)
+ +[0-9a-f]+:	41 54 30 00       	la	%r5,0\(%r4,%r3\)
+# IE against global var
+ +[0-9a-f]+:	e3 30 d0 88 00 04 	lg	%r3,136\(%r13\)
+ +[0-9a-f]+:	e3 33 c0 00 00 04 	lg	%r3,0\(%r3,%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE against local var
+ +[0-9a-f]+:	e3 30 d0 90 00 04 	lg	%r3,144\(%r13\)
+ +[0-9a-f]+:	e3 43 c0 00 00 04 	lg	%r4,0\(%r3,%r12\)
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE against hidden and local var
+ +[0-9a-f]+:	e3 30 d0 98 00 04 	lg	%r3,152\(%r13\)
+ +[0-9a-f]+:	e3 43 c0 00 00 04 	lg	%r4,0\(%r3,%r12\)
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE against hidden but not local var
+ +[0-9a-f]+:	e3 30 d0 a0 00 04 	lg	%r3,160\(%r13\)
+ +[0-9a-f]+:	e3 43 c0 00 00 04 	lg	%r4,0\(%r3,%r12\)
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE against global var with larl got access
+ +[0-9a-f]+:	c0 30 [0-9a-f ]+ 	larl	%r3,[0-9a-f]+ <\_GLOBAL\_OFFSET\_TABLE\_\+0x68>
+ +[0-9a-f]+:	e3 33 c0 00 00 04 	lg	%r3,0\(%r3,%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE against local var with larl got access
+ +[0-9a-f]+:	c0 30 [0-9a-f ]+ 	larl	%r3,[0-9a-f]+ <\_GLOBAL\_OFFSET\_TABLE\_\+0x38>
+ +[0-9a-f]+:	e3 43 c0 00 00 04 	lg	%r4,0\(%r3,%r12\)
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE against hidden and local var with larl got access
+ +[0-9a-f]+:	c0 30 [0-9a-f ]+ 	larl	%r3,[0-9a-f]+ <\_GLOBAL\_OFFSET\_TABLE\_\+0x80>
+ +[0-9a-f]+:	e3 43 c0 00 00 04 	lg	%r4,0\(%r3,%r12\)
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE against hidden but not local var with larl got access
+ +[0-9a-f]+:	c0 30 [0-9a-f ]+ 	larl	%r3,[0-9a-f]+ <\_GLOBAL\_OFFSET\_TABLE\_\+0x88>
+ +[0-9a-f]+:	e3 43 c0 00 00 04 	lg	%r4,0\(%r3,%r12\)
+ +[0-9a-f]+:	41 54 90 00       	la	%r5,0\(%r4,%r9\)
+# IE against global var with small got access (no optimization)
+ +[0-9a-f]+:	e3 30 c0 68 00 04 	lg	%r3,104\(%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE against local var with small got access (no optimization)
+ +[0-9a-f]+:	e3 30 c0 38 00 04 	lg	%r3,56\(%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE against hidden and local var with small got access
+# (no optimization)
+ +[0-9a-f]+:	e3 30 c0 80 00 04 	lg	%r3,128\(%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# IE against hidden but not local var with small got access
+# (no optimization)
+ +[0-9a-f]+:	e3 30 c0 88 00 04 	lg	%r3,136\(%r12\)
+ +[0-9a-f]+:	41 33 90 00       	la	%r3,0\(%r3,%r9\)
+# function epilog
+ +[0-9a-f]+:	eb 6e f0 d0 00 04 	lmg	%r6,%r14,208\(%r15\)
+ +[0-9a-f]+:	07 fe             	br	%r14
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
+ +[0-9a-f]+:	07 07             	bcr	0,%r7
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlspic_64.rd b/binutils-2.19/ld/testsuite/ld-s390/tlspic_64.rd
new file mode 100644
index 0000000..62c1a76
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlspic_64.rd
@@ -0,0 +1,142 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: -m64 -Aesame
+#ld: -shared -melf64_s390
+#readelf: -WSsrl
+#target: s390x-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] .hash .*
+ +\[[ 0-9]+\] .dynsym .*
+ +\[[ 0-9]+\] .dynstr .*
+ +\[[ 0-9]+\] .rela.dyn .*
+ +\[[ 0-9]+\] .rela.plt .*
+ +\[[ 0-9]+\] .plt .*
+ +\[[ 0-9]+\] .text +PROGBITS .*
+ +\[[ 0-9]+\] .tdata +PROGBITS .* 0+60 00 WAT +0 +0 +32
+ +\[[ 0-9]+\] .tbss +NOBITS .* 0+20 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC .*
+ +\[[ 0-9]+\] .got +PROGBITS .*
+ +\[[ 0-9]+\] .shstrtab .*
+ +\[[ 0-9]+\] .symtab .*
+ +\[[ 0-9]+\] .strtab .*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x[0-9a-f]+
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  LOAD .* R E 0x1000
+  LOAD .* RW +0x1000
+  DYNAMIC .* RW +0x8
+  TLS .* 0x0+60 0x0+80 R +0x20
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 +.hash .dynsym .dynstr .rela.dyn .rela.plt .plt .text *
+   01 +.tdata .dynamic .got *
+   02 +.dynamic *
+   03 +.tdata .tbss *
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
+ +Offset +Info +Type +Symbol's Value  Symbol's Name \+ Addend
+[0-9a-f ]+R_390_TLS_DTPMOD +0+
+[0-9a-f ]+R_390_TLS_TPOFF +0+24
+[0-9a-f ]+R_390_TLS_TPOFF +0+30
+[0-9a-f ]+R_390_TLS_DTPMOD +0+
+[0-9a-f ]+R_390_TLS_DTPMOD +0+
+[0-9a-f ]+R_390_TLS_TPOFF +0+64
+[0-9a-f ]+R_390_TLS_TPOFF +0+50
+[0-9a-f ]+R_390_TLS_TPOFF +0+70
+[0-9a-f ]+R_390_TLS_DTPMOD +0+
+[0-9a-f ]+R_390_TLS_TPOFF +0+44
+[0-9a-f ]+R_390_TLS_TPOFF +0+10 sg5 \+ 0
+[0-9a-f ]+R_390_TLS_DTPMOD +0+ sg1 \+ 0
+[0-9a-f ]+R_390_TLS_DTPOFF +0+ sg1 \+ 0
+[0-9a-f ]+R_390_TLS_TPOFF +0+4 sg2 \+ 0
+
+Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ +Offset +Info +Type +Symbol's Value  Symbol's Name \+ Addend
+[0-9a-f ]+R_390_JMP_SLOT +0+ __tls_get_offset \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE  LOCAL  DEFAULT  UND 
+.* SECTION LOCAL  DEFAULT +7 
+.* SECTION LOCAL  DEFAULT +8 
+.* TLS +GLOBAL DEFAULT +8 sg8
+.* TLS +GLOBAL DEFAULT +8 sg3
+.* TLS +GLOBAL DEFAULT +8 sg4
+.* TLS +GLOBAL DEFAULT +8 sg5
+.* NOTYPE  GLOBAL DEFAULT  UND __tls_get_offset
+.* TLS +GLOBAL DEFAULT +8 sg1
+.* FUNC +GLOBAL DEFAULT +7 fn1
+.* NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.* TLS +GLOBAL DEFAULT +8 sg2
+.* TLS +GLOBAL DEFAULT +8 sg6
+.* TLS +GLOBAL DEFAULT +8 sg7
+.* NOTYPE  GLOBAL DEFAULT  ABS _edata
+.* NOTYPE  GLOBAL DEFAULT  ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE  LOCAL  DEFAULT  UND 
+.* SECTION LOCAL  DEFAULT +1 
+.* SECTION LOCAL  DEFAULT +2 
+.* SECTION LOCAL  DEFAULT +3 
+.* SECTION LOCAL  DEFAULT +4 
+.* SECTION LOCAL  DEFAULT +5 
+.* SECTION LOCAL  DEFAULT +6 
+.* SECTION LOCAL  DEFAULT +7 
+.* SECTION LOCAL  DEFAULT +8 
+.* SECTION LOCAL  DEFAULT +9 
+.* SECTION LOCAL  DEFAULT +10 
+.* SECTION LOCAL  DEFAULT +11 
+.* TLS +LOCAL  DEFAULT +8 sl1
+.* TLS +LOCAL  DEFAULT +8 sl2
+.* TLS +LOCAL  DEFAULT +8 sl3
+.* TLS +LOCAL  DEFAULT +8 sl4
+.* TLS +LOCAL  DEFAULT +8 sl5
+.* TLS +LOCAL  DEFAULT +8 sl6
+.* TLS +LOCAL  DEFAULT +8 sl7
+.* TLS +LOCAL  DEFAULT +8 sl8
+.* TLS +LOCAL  HIDDEN +9 sH1
+.* OBJECT  LOCAL  HIDDEN  ABS _DYNAMIC
+.* TLS +LOCAL  HIDDEN +8 sh3
+.* TLS +LOCAL  HIDDEN +9 sH2
+.* TLS +LOCAL  HIDDEN +9 sH7
+.* TLS +LOCAL  HIDDEN +8 sh7
+.* TLS +LOCAL  HIDDEN +8 sh8
+.* TLS +LOCAL  HIDDEN +9 sH4
+.* TLS +LOCAL  HIDDEN +8 sh4
+.* TLS +LOCAL  HIDDEN +9 sH3
+.* TLS +LOCAL  HIDDEN +8 sh5
+.* TLS +LOCAL  HIDDEN +9 sH5
+.* TLS +LOCAL  HIDDEN +9 sH6
+.* TLS +LOCAL  HIDDEN +9 sH8
+.* TLS +LOCAL  HIDDEN +8 sh1
+.* OBJECT  LOCAL  HIDDEN  ABS _GLOBAL_OFFSET_TABLE_
+.* TLS +LOCAL  HIDDEN +8 sh2
+.* TLS +LOCAL  HIDDEN +8 sh6
+.* TLS +GLOBAL DEFAULT +8 sg8
+.* TLS +GLOBAL DEFAULT +8 sg3
+.* TLS +GLOBAL DEFAULT +8 sg4
+.* TLS +GLOBAL DEFAULT +8 sg5
+.* NOTYPE  GLOBAL DEFAULT  UND __tls_get_offset
+.* TLS +GLOBAL DEFAULT +8 sg1
+.* FUNC +GLOBAL DEFAULT +7 fn1
+.* NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.* TLS +GLOBAL DEFAULT +8 sg2
+.* TLS +GLOBAL DEFAULT +8 sg6
+.* TLS +GLOBAL DEFAULT +8 sg7
+.* NOTYPE  GLOBAL DEFAULT  ABS _edata
+.* NOTYPE  GLOBAL DEFAULT  ABS _end
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlspic_64.sd b/binutils-2.19/ld/testsuite/ld-s390/tlspic_64.sd
new file mode 100644
index 0000000..267416e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlspic_64.sd
@@ -0,0 +1,21 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: -m64 -Aesame
+#ld: -shared -melf64_s390
+#objdump: -sj.got
+#target: s390x-*-*
+
+.*: +file format elf64-s390
+
+Contents of section .got:
+ [0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 [0-9a-f]+ [0-9a-f]+  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000020  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000060  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000040 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-s390/tlspic_64.td b/binutils-2.19/ld/testsuite/ld-s390/tlspic_64.td
new file mode 100644
index 0000000..36623bb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-s390/tlspic_64.td
@@ -0,0 +1,16 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: -m64 -Aesame
+#ld: -shared -melf64_s390
+#objdump: -sj.tdata
+#target: s390x-*-*
+
+.*: +file format elf64-s390
+
+Contents of section .tdata:
+ [0-9a-f]+ 00000011 00000012 00000013 00000014  .*
+ [0-9a-f]+ 00000015 00000016 00000017 00000018  .*
+ [0-9a-f]+ 00000041 00000042 00000043 00000044  .*
+ [0-9a-f]+ 00000045 00000046 00000047 00000048  .*
+ [0-9a-f]+ 00000101 00000102 00000103 00000104  .*
+ [0-9a-f]+ 00000105 00000106 00000107 00000108  .*
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/align.exp b/binutils-2.19/ld/testsuite/ld-scripts/align.exp
new file mode 100644
index 0000000..b0fb962
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/align.exp
@@ -0,0 +1,57 @@
+# Test ALIGN in a linker script.
+# By Nathan Sidwell, CodeSourcery LLC
+#   Copyright 2004, 2005, 2006, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+if [istarget "rs6000-*-aix*"] {
+    # Target maps .text and .data to other sections.
+    return
+}
+
+set testname "align1"
+
+if ![ld_assemble $as $srcdir/$subdir/align.s tmpdir/align.o] {
+    unresolved $testname
+    return
+}
+
+# mingw on x86_64 targets need to set the image base to 0 to avoid auto image-basing.
+global LDFLAGS
+set saved_LDFLAGS "$LDFLAGS"
+if [istarget "x86_64-*-mingw*"] then {
+  set LDFLAGS "$LDFLAGS --image-base 0"
+}
+
+if ![ld_simple_link $ld tmpdir/align "$LDFLAGS -T $srcdir/$subdir/align.t tmpdir/align.o"] {
+    fail $testname
+} else {
+    pass $testname
+}
+
+if ![is_aout_format] {
+    # The z80-coff port defaults to a "binary" like output
+    # file format which does not include a data section.
+    setup_xfail "z80-*-coff"
+    run_dump_test align2a
+    setup_xfail "z80-*-coff"
+    run_dump_test align2b
+}
+run_dump_test align2c
+set LDFLAGS "$saved_LDFLAGS"
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/align.s b/binutils-2.19/ld/testsuite/ld-scripts/align.s
new file mode 100644
index 0000000..c9bad23
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/align.s
@@ -0,0 +1,2 @@
+	.text
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/align.t b/binutils-2.19/ld/testsuite/ld-scripts/align.t
new file mode 100644
index 0000000..49d6053
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/align.t
@@ -0,0 +1,8 @@
+SECTIONS
+{
+  .text : {*(.text)}
+  .data ALIGN(0x40) : AT (ALIGN (LOADADDR (.text) + SIZEOF (.text), 0x80))
+    {}
+  ASSERT (LOADADDR(.data) == 0x80, "dyadic ALIGN broken")
+  ASSERT (ADDR(.data) == 0x40, "monadic ALIGN broken")
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/align2.t b/binutils-2.19/ld/testsuite/ld-scripts/align2.t
new file mode 100644
index 0000000..d86f62a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/align2.t
@@ -0,0 +1,7 @@
+SECTIONS
+{
+  .text : {*(.text)}
+  . = ALIGN(data_align);
+  .data : {*(.data)}
+  /DISCARD/ : {*(*)}
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/align2a.d b/binutils-2.19/ld/testsuite/ld-scripts/align2a.d
new file mode 100644
index 0000000..96237dd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/align2a.d
@@ -0,0 +1,12 @@
+# ld: --defsym data_align=16 -T align2.t
+# objdump: --section-headers
+
+[^:]+: +file format.*
+
+Sections:
+Idx +Name +Size +VMA +LMA +File +off +Algn
+[	 ]+0 +\.text +[^ ]* +0+ +0+ .*
+[	 ]+CONTENTS, +ALLOC, +LOAD,.* CODE
+[	 ]+1 +\.data +[^ ]* +0+10 +0+10 .*
+[	 ]+CONTENTS, +ALLOC, +LOAD, +DATA
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/align2a.s b/binutils-2.19/ld/testsuite/ld-scripts/align2a.s
new file mode 100644
index 0000000..4e56d4a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/align2a.s
@@ -0,0 +1,4 @@
+	.text
+	.long 0
+	.data
+	.long 0x12345678
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/align2b.d b/binutils-2.19/ld/testsuite/ld-scripts/align2b.d
new file mode 100644
index 0000000..05d2a15
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/align2b.d
@@ -0,0 +1,12 @@
+# ld: --defsym data_align=32 -T align2.t
+# objdump: --section-headers
+
+[^:]+: +file +format.*
+
+Sections:
+Idx +Name +Size +VMA +LMA +File off +Algn
+ +0 +\.text +[^ ]* +0+ +0+ .*
+ +CONTENTS, +ALLOC, +LOAD,.* CODE
+ +1 +\.data +[^ ]* +0+20 +0+20 .*
+ +CONTENTS, +ALLOC, +LOAD, +DATA
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/align2b.s b/binutils-2.19/ld/testsuite/ld-scripts/align2b.s
new file mode 100644
index 0000000..4e56d4a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/align2b.s
@@ -0,0 +1,4 @@
+	.text
+	.long 0
+	.data
+	.long 0x12345678
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/align2c.d b/binutils-2.19/ld/testsuite/ld-scripts/align2c.d
new file mode 100644
index 0000000..16a4245
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/align2c.d
@@ -0,0 +1,2 @@
+# ld: -T align2.t
+# error: undefined symbol.*in expression
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/align2c.s b/binutils-2.19/ld/testsuite/ld-scripts/align2c.s
new file mode 100644
index 0000000..4e56d4a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/align2c.s
@@ -0,0 +1,4 @@
+	.text
+	.long 0
+	.data
+	.long 0x12345678
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/alignof.exp b/binutils-2.19/ld/testsuite/ld-scripts/alignof.exp
new file mode 100644
index 0000000..0f05aeb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/alignof.exp
@@ -0,0 +1,67 @@
+# Test ALIGNOF in a linker script.
+# Copyright 2007 Free Software Foundation, Inc.
+# Contributed by Nathan Sidwell <nathan@codesourcery.com>
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# Only ELF and PE-COFF targets record section alignment.
+
+if {![is_elf_format] && ![is_pecoff_format]} {
+    return
+}
+
+set testname "ALIGNOF"
+
+if ![ld_assemble $as $srcdir/$subdir/alignof.s tmpdir/alignof.o] {
+    unresolved $testname
+    return
+}
+
+if ![ld_simple_link $ld tmpdir/alignof "-T $srcdir/$subdir/alignof.t tmpdir/alignof.o"] {
+    fail $testname
+    return
+}
+
+if ![ld_nm $nm "" tmpdir/alignof] {
+    unresolved $testname
+    return
+}
+
+if {![info exists nm_output(alignof_text)] \
+     || ![info exists nm_output(alignof_data)]} {
+    send_log "bad output from nm\n"
+    verbose "bad output from nm"
+    fail $testname
+    return
+}
+
+if {$nm_output(alignof_text) != 64} {
+    send_log "alignof_text != 64\n"
+    verbose "alignof_text != 64"
+    fail $testname
+    return
+}
+
+if {$nm_output(alignof_data) != 16} {
+    send_log "alignof_data != 16\n"
+    verbose "alignof_data != 16"
+    fail $testname
+    return
+}
+
+pass $testname
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/alignof.s b/binutils-2.19/ld/testsuite/ld-scripts/alignof.s
new file mode 100644
index 0000000..d440d2e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/alignof.s
@@ -0,0 +1,9 @@
+
+	.text
+	.p2align 6
+	.long 0
+
+	.data
+	.p2align 4
+	.long 0
+	
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/alignof.t b/binutils-2.19/ld/testsuite/ld-scripts/alignof.t
new file mode 100644
index 0000000..1241112
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/alignof.t
@@ -0,0 +1,15 @@
+SECTIONS {
+	.text :
+	  {
+	    tmpdir/alignof.o (.text)
+	  }
+	.data : 
+	  { 
+	    tmpdir/alignof.o (.data)
+	    LONG (ALIGNOF(.text))
+	    LONG (ALIGNOF(.data))
+	  }
+}	
+
+alignof_text = ALIGNOF(.text);
+alignof_data = ALIGNOF(.data);
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/assert.exp b/binutils-2.19/ld/testsuite/ld-scripts/assert.exp
new file mode 100644
index 0000000..636f01c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/assert.exp
@@ -0,0 +1,34 @@
+# Test ASSERT in a linker script.
+# By Nathan Sidwell, CodeSourcery LLC
+#   Copyright 2004, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+set testname "ASSERT"
+
+if ![ld_assemble $as $srcdir/$subdir/assert.s tmpdir/assert.o] {
+    unresolved $testname
+    return
+}
+
+if ![ld_simple_link $ld tmpdir/assert "-T $srcdir/$subdir/assert.t tmpdir/assert.o"] {
+    fail $testname
+} else {
+    pass $testname
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/assert.s b/binutils-2.19/ld/testsuite/ld-scripts/assert.s
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/assert.s
@@ -0,0 +1 @@
+
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/assert.t b/binutils-2.19/ld/testsuite/ld-scripts/assert.t
new file mode 100644
index 0000000..9b4c641
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/assert.t
@@ -0,0 +1,10 @@
+SECTIONS
+{
+  .empty : {
+  here = . == ADDR(.empty);
+  ASSERT (. == ADDR(.empty), "dot is not ADDR");
+  ASSERT (here, "here is zero");
+  }
+  ASSERT (!SIZEOF(.empty), "Empty is not empty")
+  /DISCARD/ : { *(.reginfo) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/cross1.c b/binutils-2.19/ld/testsuite/ld-scripts/cross1.c
new file mode 100644
index 0000000..5678945
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/cross1.c
@@ -0,0 +1,6 @@
+extern int foo ();
+int
+func ()
+{
+  return foo ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/cross1.t b/binutils-2.19/ld/testsuite/ld-scripts/cross1.t
new file mode 100644
index 0000000..c20e473
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/cross1.t
@@ -0,0 +1,10 @@
+NOCROSSREFS ( .text .data )
+SECTIONS
+{
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+  .hash : { *(.hash) }
+  .toc  : { *(.toc) }
+  .text : { tmpdir/cross1.o }
+  .data : { tmpdir/cross2.o }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/cross2.c b/binutils-2.19/ld/testsuite/ld-scripts/cross2.c
new file mode 100644
index 0000000..4143177
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/cross2.c
@@ -0,0 +1,5 @@
+int
+foo ()
+{
+  return 1;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/cross2.t b/binutils-2.19/ld/testsuite/ld-scripts/cross2.t
new file mode 100644
index 0000000..a0cdcbb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/cross2.t
@@ -0,0 +1,6 @@
+NOCROSSREFS ( .text .data )
+SECTIONS
+{
+  .text : { *(.text) *(.text.*) *(.pr) }
+  .data : { *(.data) *(.data.*) *(.sdata) *(.rw) *(.tc0) *(.tc) *(.toc) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/cross3.c b/binutils-2.19/ld/testsuite/ld-scripts/cross3.c
new file mode 100644
index 0000000..1848c32
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/cross3.c
@@ -0,0 +1,7 @@
+int i = 4;
+
+int
+foo ()
+{
+  return i;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/cross3.t b/binutils-2.19/ld/testsuite/ld-scripts/cross3.t
new file mode 100644
index 0000000..5e32bb2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/cross3.t
@@ -0,0 +1,10 @@
+NOCROSSREFS(.nocrossrefs .text)
+
+SECTIONS
+{
+  .text : { *(.text) }
+  .nocrossrefs : { *(.nocrossrefs) }
+  .data : { *(.data) *(.opd) }
+  .bss : { *(.bss) *(COMMON) }
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/cross4.c b/binutils-2.19/ld/testsuite/ld-scripts/cross4.c
new file mode 100644
index 0000000..aef8dfd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/cross4.c
@@ -0,0 +1,7 @@
+__attribute__ ((section (".nocrossrefs")))
+static void
+foo ()
+{
+}
+
+void (*dummy) () = foo;
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/crossref.exp b/binutils-2.19/ld/testsuite/ld-scripts/crossref.exp
new file mode 100644
index 0000000..56a0f74
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/crossref.exp
@@ -0,0 +1,134 @@
+# Test NOCROSSREFS in a linker script.
+# By Ian Lance Taylor, Cygnus Support.
+#   Copyright 2000, 2001, 2002, 2003, 2004, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+set test1 "NOCROSSREFS 1"
+set test2 "NOCROSSREFS 2"
+set test3 "NOCROSSREFS 3"
+
+if { ![is_remote host] && [which $CC] == 0 } {
+    untested $test1
+    untested $test2
+    untested $test3
+    return
+}
+
+# Xtensa targets currently default to putting literal values in a separate
+# section and that requires linker script support, so put literals in text.
+global CFLAGS
+if [istarget xtensa*-*-*] {
+    set CFLAGS "$CFLAGS -mtext-section-literals"
+}
+
+# If we have a compiler that doesn't use/reference dot-symbols, then
+# calls to functions reference the .opd section function descriptor.
+# This makes NOCROSSREFS rather useless on powerpc64.
+if [istarget powerpc64*-*-*] {
+    set CFLAGS "$CFLAGS -mcall-aixdesc"
+}
+
+# Prevent the use of the MeP's small data area which references a symbol
+# called __sdabase which will not be defined by our test linker scripts.
+if [istarget mep*-*-elf] {
+    set CFLAGS "-mtiny=0"
+}
+
+if { ![ld_compile $CC "$srcdir/$subdir/cross1.c" tmpdir/cross1.o] \
+     || ![ld_compile $CC "$srcdir/$subdir/cross2.c" tmpdir/cross2.o] } {
+    unresolved $test1
+    unresolved $test2
+    return
+}
+
+set flags [big_or_little_endian]
+
+if [istarget sh64*-*-elf] {
+    # This is what gcc passes to ld by default.
+    set flags "-mshelf32"
+}
+
+# IA64 has both ordered and unordered sections in an input file.
+setup_xfail ia64-*-*
+
+set exec_output [run_host_cmd "$ld" "$flags -o tmpdir/cross1 -T $srcdir/$subdir/cross1.t tmpdir/cross1.o tmpdir/cross2.o"]
+
+set exec_output [prune_warnings $exec_output]
+
+regsub -all "(^|\n)($ld: warning: cannot find entry symbol\[^\n\]*\n?)" $exec_output "\\1" exec_output
+
+if [string match "" $exec_output] then {
+    fail $test1
+} else {
+    verbose -log "$exec_output"
+    if [regexp "prohibited cross reference from .* to `.*foo' in" $exec_output] {
+	pass $test1
+    } else {
+	fail $test1
+    }
+}
+
+# Check cross references within a single object.
+
+if { ![ld_compile $CC "$srcdir/$subdir/cross3.c" tmpdir/cross3.o] } {
+    unresolved $test2
+    return
+}
+
+set exec_output [run_host_cmd "$ld" "$flags -o tmpdir/cross2 -T $srcdir/$subdir/cross2.t tmpdir/cross3.o"]
+set exec_output [prune_warnings $exec_output]
+
+regsub -all "(^|\n)($ld: warning: cannot find entry symbol\[^\n\]*\n?)" $exec_output "\\1" exec_output
+
+if [string match "" $exec_output] then {
+    fail $test2
+} else {
+    verbose -log "$exec_output"
+    if [regexp "prohibited cross reference from .* to `.*' in" $exec_output] {
+	pass $test2
+    } else {
+	fail $test2
+    }
+}
+
+# Check cross references for ld -r
+
+if { ![ld_compile $CC "$srcdir/$subdir/cross4.c" tmpdir/cross4.o] } {
+    unresolved $test3
+    return
+}
+
+if ![ld_relocate $ld tmpdir/cross3-partial.o "tmpdir/cross1.o tmpdir/cross4.o"] {
+    unresolved $test3
+    return
+}
+
+set exec_output [run_host_cmd "$ld" "$flags -o tmpdir/cross3 -T $srcdir/$subdir/cross3.t tmpdir/cross3-partial.o tmpdir/cross2.o"]
+
+set exec_output [prune_warnings $exec_output]
+
+regsub -all "(^|\n)($ld: warning: cannot find entry symbol\[^\n\]*\n?)" $exec_output "\\1" exec_output
+
+if [string match "" $exec_output] then {
+    pass $test3
+} else {
+    verbose -log "$exec_output"
+    fail $test3
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/data.d b/binutils-2.19/ld/testsuite/ld-scripts/data.d
new file mode 100644
index 0000000..10b3d08
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/data.d
@@ -0,0 +1,9 @@
+#source: data.s
+#ld: -T data.t
+#objdump: -s -j .text
+
+.*:     file format .*
+
+Contents of section .text:
+ [0-9a-f]* (04)?000000(04)? (0020)?0000(2000)? .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/data.exp b/binutils-2.19/ld/testsuite/ld-scripts/data.exp
new file mode 100644
index 0000000..66b2a2f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/data.exp
@@ -0,0 +1,30 @@
+# Test DATA STATEMENT in a linker script.
+# By Nathan Sidwell, CodeSourcery LLC
+#   Copyright 2004, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# An a.out "objdump -s -j .text" has the file header visible inside the
+# text segment, confusing run_dump_test.
+if {[is_aout_format]} {
+	unsupported data
+	return
+}
+
+run_dump_test data
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/data.s b/binutils-2.19/ld/testsuite/ld-scripts/data.s
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/data.s
@@ -0,0 +1 @@
+
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/data.t b/binutils-2.19/ld/testsuite/ld-scripts/data.t
new file mode 100644
index 0000000..f56d10f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/data.t
@@ -0,0 +1,11 @@
+SECTIONS
+{
+  . = 0x1000 + SIZEOF_HEADERS;
+  .text ALIGN (0x20) :
+   {
+     LONG (label - .)
+     label = .;
+     LONG (ADDR (.other))
+   }
+   .other 0x2000 : {}
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/default-script.exp b/binutils-2.19/ld/testsuite/ld-scripts/default-script.exp
new file mode 100644
index 0000000..202f532
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/default-script.exp
@@ -0,0 +1,32 @@
+# Test --default-script/-dT
+#   Copyright 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+if { [istarget spu*-*-*] } {
+    set LDFLAGS "$LDFLAGS --local-store 0:0"
+}
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/default-script*.d]]
+foreach t $test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname $t]
+    run_dump_test [file rootname $t]
+}
+
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/default-script.s b/binutils-2.19/ld/testsuite/ld-scripts/default-script.s
new file mode 100644
index 0000000..494fb62
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/default-script.s
@@ -0,0 +1,3 @@
+	.text
+text:
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/default-script.t b/binutils-2.19/ld/testsuite/ld-scripts/default-script.t
new file mode 100644
index 0000000..fc70187
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/default-script.t
@@ -0,0 +1,7 @@
+_START = DEFINED(_START) ? _START : 0x9000000;
+SECTIONS
+{
+  . = _START;
+  .text : {*(.text)}
+  /DISCARD/ : {*(*)}
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/default-script1.d b/binutils-2.19/ld/testsuite/ld-scripts/default-script1.d
new file mode 100644
index 0000000..1a709ba
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/default-script1.d
@@ -0,0 +1,9 @@
+# source: default-script.s
+# ld: -defsym _START=0x8000000 -T default-script.t
+# nm: -n
+
+#...
+0*8000000 . _START
+#...
+0*8000000 t text
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/default-script2.d b/binutils-2.19/ld/testsuite/ld-scripts/default-script2.d
new file mode 100644
index 0000000..c29d733
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/default-script2.d
@@ -0,0 +1,9 @@
+# source: default-script.s
+# ld: -T default-script.t -defsym _START=0x8000000
+# nm: -n
+
+#...
+0*8000000 . _START
+#...
+0*9000000 t text
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/default-script3.d b/binutils-2.19/ld/testsuite/ld-scripts/default-script3.d
new file mode 100644
index 0000000..b41dcbf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/default-script3.d
@@ -0,0 +1,9 @@
+# source: default-script.s
+# ld: -defsym _START=0x8000000 -dT default-script.t
+# nm: -n
+
+#...
+0*8000000 . _START
+#...
+0*8000000 t text
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/default-script4.d b/binutils-2.19/ld/testsuite/ld-scripts/default-script4.d
new file mode 100644
index 0000000..ec097d6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/default-script4.d
@@ -0,0 +1,9 @@
+# source: default-script.s
+# ld: --default-script default-script.t -defsym _START=0x8000000
+# nm: -n
+
+#...
+0*8000000 . _START
+#...
+0*8000000 t text
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/defined.exp b/binutils-2.19/ld/testsuite/ld-scripts/defined.exp
new file mode 100644
index 0000000..d342728
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/defined.exp
@@ -0,0 +1,69 @@
+# Test DEFINED in a linker script.
+# By Ian Lance Taylor, Cygnus Support.
+#   Copyright 2001, 2003. 2006, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+set testname "DEFINED"
+set prms_id 5699
+
+if ![ld_assemble $as $srcdir/$subdir/defined.s tmpdir/def.o] {
+    unresolved $testname
+    return
+}
+
+global LDFLAGS
+set saved_LDFLAGS "$LDFLAGS"
+if [istarget "x86_64-*-mingw*"] then {
+  set LDFLAGS "$LDFLAGS --image-base 0"
+}
+
+if ![ld_simple_link $ld tmpdir/def "$LDFLAGS -T $srcdir/$subdir/defined.t tmpdir/def.o"] {
+    fail $testname
+} else {
+    if ![ld_nm $nm "" tmpdir/def] {
+	unresolved $testname
+    } else {
+	if {![info exists nm_output(value1)] \
+	     || ![info exists nm_output(value2)]} {
+	    send_log "bad output from nm\n"
+	    verbose "bad output from nm"
+	    fail $testname
+	} else {
+	    if {$nm_output(value1) != 1} {
+		send_log "value1 == $nm_output(value1)\n"
+		verbose "value1 == $nm_output(value1)"
+		fail $testname
+	    } else {
+		if {$nm_output(value2) != 2} {
+		    send_log "value2 == $nm_output(value2)\n"
+		    verbose "value2 == $nm_output(value2)"
+		    fail $testname
+		} else {
+		    pass $testname
+		}
+	    }
+	}
+    }
+}
+
+set prms_id 0
+run_dump_test "defined2"
+run_dump_test "defined3"
+set LDFLAGS "$saved_LDFLAGS"
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/defined.s b/binutils-2.19/ld/testsuite/ld-scripts/defined.s
new file mode 100644
index 0000000..a340ad4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/defined.s
@@ -0,0 +1,2 @@
+	.globl	defined
+	.set defined,	1
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/defined.t b/binutils-2.19/ld/testsuite/ld-scripts/defined.t
new file mode 100644
index 0000000..c1ef1b6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/defined.t
@@ -0,0 +1,7 @@
+SECTIONS {
+	.text : { *(.text) }
+	.data : { *(.data) }
+	.bss : { *(.bss) *(COMMON) }
+}
+value1 = DEFINED (defined) ? 1 : 2;
+value2 = DEFINED (undefined) ? 1 : 2;
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/defined2.d b/binutils-2.19/ld/testsuite/ld-scripts/defined2.d
new file mode 100644
index 0000000..40728bd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/defined2.d
@@ -0,0 +1,22 @@
+#ld: -Tdefined2.t
+#nm: -B
+#source: phdrs.s
+#xfail: "rs6000-*-aix*"
+
+# Check that arithmetic on DEFINED works.
+# Matching both A and T accounts for formats that can't tell a .text
+# symbol from an absolute symbol (mmo), but matches whatever section that
+# contains an address matching the value.  The symbol sym1 is supposed to
+# be in the .text section for all targets, though.
+
+#...
+0+1 [AT] defined1
+#...
+0+11 A defined2
+#...
+0+100 A defined3
+#...
+0+1ff A defined4
+#...
+0+3 T sym1
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/defined2.t b/binutils-2.19/ld/testsuite/ld-scripts/defined2.t
new file mode 100644
index 0000000..50ddad0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/defined2.t
@@ -0,0 +1,9 @@
+SECTIONS {
+	.text : { *(.text) sym1 = 3 - DEFINED (x); }
+	.data : { *(.data) }
+	.bss : { *(.bss) *(COMMON) }
+}
+defined1 = !DEFINED (x);
+defined2 = DEFINED (defined1) + 16;
+defined3 = DEFINED (defined2) * 256;
+defined4 = 0x200 - DEFINED (defined3);
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/defined3.d b/binutils-2.19/ld/testsuite/ld-scripts/defined3.d
new file mode 100644
index 0000000..61061b6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/defined3.d
@@ -0,0 +1,35 @@
+#ld: -Tdefined3.t
+#nm: -B
+#source: phdrs.s
+#source: defined.s
+#xfail: "rs6000-*-aix*"
+
+# Check that DEFINED matches only symbols defined before its location.
+# The ellipsis account for target-specific symbols.  Matching both A and T
+# accounts for formats that can't tell a .text symbol from an absolute
+# symbol (mmo), but matches whatever section that contains an address
+# matching the value.
+
+#...
+0+1 [AT] defined
+#...
+0+200 A defined1
+#...
+0+201 A defined2
+#...
+0+100 A defined3
+#...
+0+ [AT] defined4
+#...
+0+2a A defined5
+#...
+0+ [AT] defined6
+#...
+0+1 [AT] defined7
+#...
+0+1 [AT] defined8
+#...
+0+2a A sym1
+#...
+[0-9a-f]+ T sym2
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/defined3.t b/binutils-2.19/ld/testsuite/ld-scripts/defined3.t
new file mode 100644
index 0000000..1fe6eef
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/defined3.t
@@ -0,0 +1,15 @@
+defined6 = DEFINED (sym2) ? 1 : 0;
+SECTIONS {
+	.text : { *(.text) sym2 = .; }
+	.data : { *(.data) }
+	.bss : { *(.bss) *(COMMON) }
+}
+defined4 = DEFINED (sym1) ? 1 : 0;
+sym1 = 42;
+defined3 = DEFINED (defined1) ? defined1 + 1 : 256;
+defined1 = DEFINED (defined1) ? defined1 + 1 : 512;
+defined2 = DEFINED (defined1) ? defined1 + 1 : 1024;
+defined5 = DEFINED (sym1) ? sym1 : 0;
+defined7 = DEFINED (sym2);
+defined8 = !DEFINED (defined8);
+defined = DEFINED (defined) ? defined : 42;
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/dynamic-sections-1.s b/binutils-2.19/ld/testsuite/ld-scripts/dynamic-sections-1.s
new file mode 100644
index 0000000..9a72c96
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/dynamic-sections-1.s
@@ -0,0 +1,2 @@
+	.data
+	.4byte	foo
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/dynamic-sections-2.s b/binutils-2.19/ld/testsuite/ld-scripts/dynamic-sections-2.s
new file mode 100644
index 0000000..57cb02d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/dynamic-sections-2.s
@@ -0,0 +1,3 @@
+	.data
+	.global foo
+foo:	.4byte	0
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/dynamic-sections.d b/binutils-2.19/ld/testsuite/ld-scripts/dynamic-sections.d
new file mode 100644
index 0000000..279107d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/dynamic-sections.d
@@ -0,0 +1,6 @@
+# nm: -C
+# ld: -T dynamic-sections.t
+# name: dynamic sections
+# source: dynamic-sections-1.s
+# source: dynamic-sections-2.s
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/dynamic-sections.exp b/binutils-2.19/ld/testsuite/ld-scripts/dynamic-sections.exp
new file mode 100644
index 0000000..b1b3ae7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/dynamic-sections.exp
@@ -0,0 +1,27 @@
+# Copyright 2007  Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# Check for bug introduced on 2002-06-10.  See dynamic-sections.t for
+# more details
+
+if ![is_elf_format] {
+    return
+}
+
+run_dump_test dynamic-sections
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/dynamic-sections.t b/binutils-2.19/ld/testsuite/ld-scripts/dynamic-sections.t
new file mode 100644
index 0000000..f1f24c8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/dynamic-sections.t
@@ -0,0 +1,11 @@
+SECTIONS
+{
+  .data : { *(.data) }
+  .rodata : { *(.rodata) }
+
+  /* The .rel* sections are typically placed here, because of the way
+     elf32.em handles orphaned sections.  A bug introduced on 2002-06-10
+     would cause . to be 0 at this point.  */
+
+  _bar = ASSERT (. > 0, "Bad . value");
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address-1.d b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-1.d
new file mode 100644
index 0000000..99fac1e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-1.d
@@ -0,0 +1,8 @@
+#ld: -T empty-address-1.t
+#nm: -n
+#...
+0+0 T _start
+#...
+0+2000000 A __data_end
+0+2000000 [ADT] __data_start
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address-1.s b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-1.s
new file mode 100644
index 0000000..c5cc1a5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-1.s
@@ -0,0 +1,5 @@
+	.text
+	.global _start
+_start:
+	.long __data_start
+	.long __data_end
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address-1.t b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-1.t
new file mode 100644
index 0000000..57a8bed
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-1.t
@@ -0,0 +1,11 @@
+SECTIONS
+{
+  .text 0x0000000: { *(.text) }
+  .data 0x2000000:
+  {
+    __data_start = . ;
+    *(.data)
+  }
+  __data_end = .;
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address-2.s b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-2.s
new file mode 100644
index 0000000..79f58ea
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-2.s
@@ -0,0 +1,5 @@
+	.text
+	.global _start
+_start:
+	.long __data_end
+	.p2align 4
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address-2a.d b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-2a.d
new file mode 100644
index 0000000..d831d5f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-2a.d
@@ -0,0 +1,8 @@
+#source: empty-address-2.s
+#ld: -Ttext 0x0000000 -Tdata 0x2000000 -T empty-address-2a.t
+#nm: -n
+#...
+0+0 T _start
+#...
+0+10 A __data_end
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address-2a.t b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-2a.t
new file mode 100644
index 0000000..6a40ad8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-2a.t
@@ -0,0 +1,7 @@
+SECTIONS
+{
+  .text : { *(.text) }
+  .data : { *(.data) }
+  __data_end = .;
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address-2b.d b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-2b.d
new file mode 100644
index 0000000..514fd68
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-2b.d
@@ -0,0 +1,8 @@
+#source: empty-address-2.s
+#ld: -Ttext 0x0000000 -Tdata 0x2000000 -T empty-address-2b.t
+#nm: -n
+#...
+0+0 T _start
+#...
+0+10 A __data_end
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address-2b.t b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-2b.t
new file mode 100644
index 0000000..dcf264f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-2b.t
@@ -0,0 +1,11 @@
+SECTIONS
+{
+  .text 0x0000000: { *(.text) }
+  .data :
+  {
+    PROVIDE (__data_start = .);
+    *(.data)
+  }
+  __data_end = .;
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3.s b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3.s
new file mode 100644
index 0000000..6b07dd4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3.s
@@ -0,0 +1,5 @@
+	.text
+	.global _start
+_start:
+	.byte 0,0,0,0,0,0,0,0
+	.byte 0,0,0,0,0,0,0,0
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3a.d b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3a.d
new file mode 100644
index 0000000..bb12c80
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3a.d
@@ -0,0 +1,8 @@
+#source: empty-address-3.s
+#ld: -T empty-address-3a.t
+#nm: -n
+#...
+0+0 T _start
+#...
+0+10 A __data_end
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3a.t b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3a.t
new file mode 100644
index 0000000..2807e71
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3a.t
@@ -0,0 +1,10 @@
+SECTIONS
+{
+  .text 0x00000000: { *(.text) }
+  .data ALIGN(0x1000) + (. & (0x1000 - 1)):
+  {
+    *(.data)
+  }
+  __data_end = .;
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3b.d b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3b.d
new file mode 100644
index 0000000..b3e2a4b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3b.d
@@ -0,0 +1,8 @@
+#source: empty-address-3.s
+#ld: -T empty-address-3b.t
+#nm: -n
+#...
+0+0 T _start
+#...
+0+10 A __data_end
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3b.t b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3b.t
new file mode 100644
index 0000000..4f213af
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3b.t
@@ -0,0 +1,11 @@
+SECTIONS
+{
+  .text 0x00000000: { *(.text) }
+  .data ALIGN(0x1000) + (. & (0x1000 - 1)):
+  {
+    PROVIDE (__data_start = .);
+    *(.data)
+  }
+  __data_end = .;
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3c.d b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3c.d
new file mode 100644
index 0000000..6001885
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3c.d
@@ -0,0 +1,10 @@
+#source: empty-address-3.s
+#ld: -T empty-address-3c.t
+#nm: -n
+#...
+0+0 T _start
+#...
+0+1010 A __data_end
+#...
+0+1010 [ADT] __data_start
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3c.t b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3c.t
new file mode 100644
index 0000000..6de5198
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address-3c.t
@@ -0,0 +1,11 @@
+SECTIONS
+{
+  .text 0x00000000: { *(.text) }
+  .data ALIGN(0x1000) + (. & (0x1000 - 1)):
+  {
+    __data_start = .;
+    *(.data)
+  }
+  __data_end = .;
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-address.exp b/binutils-2.19/ld/testsuite/ld-scripts/empty-address.exp
new file mode 100644
index 0000000..e333ec1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-address.exp
@@ -0,0 +1,28 @@
+# Make sure that "dot" is updated for empty sections if their addresses
+# are set.
+#   Copyright 2006, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+run_dump_test empty-address-1
+run_dump_test empty-address-2a
+run_dump_test empty-address-2b
+run_dump_test empty-address-3a
+run_dump_test empty-address-3b
+run_dump_test empty-address-3c
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-aligned.d b/binutils-2.19/ld/testsuite/ld-scripts/empty-aligned.d
new file mode 100644
index 0000000..4b7b84b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-aligned.d
@@ -0,0 +1,13 @@
+#source: empty-aligned.s
+#ld: -T empty-aligned.t
+#readelf: -l --wide
+#xfail: "hppa64-*-*"
+
+#...
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg +Align
+ +LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ [RWE ]+ +0x[0-9a-f]+
+
+ Section to Segment mapping:
+ +Segment Sections\.\.\.
+ +00 +.text 
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-aligned.exp b/binutils-2.19/ld/testsuite/ld-scripts/empty-aligned.exp
new file mode 100644
index 0000000..70da61d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-aligned.exp
@@ -0,0 +1,29 @@
+# Make sure empty aligned sections do not change output layout.
+#   Copyright 2005, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# PHDRS is only meaningful for ELF.
+if ![is_elf_format] {
+    return
+}
+
+set testname "empty-aligned"
+
+run_dump_test empty-aligned
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-aligned.s b/binutils-2.19/ld/testsuite/ld-scripts/empty-aligned.s
new file mode 100644
index 0000000..2079aa7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-aligned.s
@@ -0,0 +1,2 @@
+	.text
+	.long 123
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-aligned.t b/binutils-2.19/ld/testsuite/ld-scripts/empty-aligned.t
new file mode 100644
index 0000000..e59bc20
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-aligned.t
@@ -0,0 +1,29 @@
+SECTIONS
+{
+  .text : { *(.text) }
+  /* Alignment at beginning shouldn't result in empty section being kept.  */
+  .text1 ALIGN (4096) :
+  {
+    *(.text1)
+  }
+  /* Same for alignment at beginning and end.  */
+  .text2 ALIGN (4096) :
+  {
+    *(.text2)
+    . = ALIGN (4096);
+  }
+  /* Same for alignment just at end, although we need to be careful in
+     the expression used to align.  */
+  .text3 :
+  {
+    *(.text3)
+    . = ALIGN (. != 0 ? 4096 : 1);
+  }
+  /* Same when setting vma and lma.  This also shouldn't result in
+     .text3 being kept.  */
+  .text4 ADDR (.text3) + SIZEOF (.text3) + 8192 : AT (LOADADDR (.text3))
+  {
+    *(.text4)
+  }
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-orphan.d b/binutils-2.19/ld/testsuite/ld-scripts/empty-orphan.d
new file mode 100644
index 0000000..7bd9b9a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-orphan.d
@@ -0,0 +1,6 @@
+#source: empty-orphan.s
+#ld: -T empty-orphan.t
+#readelf: -l --wide
+#...
+ +LOAD +[x0-9a-f]+ [x0]+70000000 [x0]+70000000 [x0]+(2|4|8|10|20|40|80) .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-orphan.exp b/binutils-2.19/ld/testsuite/ld-scripts/empty-orphan.exp
new file mode 100644
index 0000000..59a51a8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-orphan.exp
@@ -0,0 +1,34 @@
+# Make sure orphan sections do not lead to huge output files.
+# By David Heine, Tensilica, Inc.
+#   Copyright 2005, 2006, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# PHDRS is only meaningful for ELF.
+if ![is_elf_format] {
+    return
+}
+
+if { [istarget spu*-*-*] } {
+    set LDFLAGS "--local-store 0:0"
+}
+
+set testname "empty-orphan"
+
+run_dump_test empty-orphan
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-orphan.s b/binutils-2.19/ld/testsuite/ld-scripts/empty-orphan.s
new file mode 100644
index 0000000..c8fe675
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-orphan.s
@@ -0,0 +1,4 @@
+	.section .orphan_data, "a"
+	# empty but defined
+	.section .data
+	.word 0x1111
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/empty-orphan.t b/binutils-2.19/ld/testsuite/ld-scripts/empty-orphan.t
new file mode 100644
index 0000000..b57e164
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/empty-orphan.t
@@ -0,0 +1,22 @@
+MEMORY
+{
+  default_mem : ORIGIN = 0x0, LENGTH = 0x100000
+  text_mem : ORIGIN = 0x60000000, LENGTH = 0x100
+  data_mem : ORIGIN = 0x70000000, LENGTH = 0x100
+}
+
+PHDRS
+{
+  default_phdr PT_LOAD;
+  text_phdr PT_LOAD;
+  data_phdr PT_LOAD;
+}
+
+SECTIONS
+{
+   .text : { *(.text) } > text_mem : text_phdr
+   .data : { *(.data) } > data_mem : data_phdr
+   .bss : { *(.bss) } > data_mem : data_phdr
+   /DISCARD/ : { *(.reginfo) *(.glue*) }
+   /* .orphan_data is an orphan */
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/expr.exp b/binutils-2.19/ld/testsuite/ld-scripts/expr.exp
new file mode 100644
index 0000000..34829e5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/expr.exp
@@ -0,0 +1,23 @@
+# Test ALIGN in a linker script.
+# By Nathan Sidwell, CodeSourcery LLC
+#   Copyright 2006, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+run_dump_test expr1
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/expr1.d b/binutils-2.19/ld/testsuite/ld-scripts/expr1.d
new file mode 100644
index 0000000..d96dfc1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/expr1.d
@@ -0,0 +1,2 @@
+# ld: -T expr1.t
+# error: undefined section .* in expression
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/expr1.s b/binutils-2.19/ld/testsuite/ld-scripts/expr1.s
new file mode 100644
index 0000000..ec0ce90
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/expr1.s
@@ -0,0 +1,2 @@
+	.word 0
+
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/expr1.t b/binutils-2.19/ld/testsuite/ld-scripts/expr1.t
new file mode 100644
index 0000000..e0810ba
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/expr1.t
@@ -0,0 +1,12 @@
+ENTRY(RAM)
+
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0, LENGTH = 0x1000000
+}
+
+SECTIONS
+{
+.text : { } >ram
+}
+RAM = ADDR(ram);
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/extern.exp b/binutils-2.19/ld/testsuite/ld-scripts/extern.exp
new file mode 100644
index 0000000..f05cd35
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/extern.exp
@@ -0,0 +1,71 @@
+# Test EXTERN in a linker script.
+# By Nathan Sidwell, CodeSourcery LLC
+#   Copyright 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+set testname "EXTERN"
+
+if ![ld_assemble $as $srcdir/$subdir/extern.s tmpdir/extern.o] {
+    unresolved $testname
+    return
+}
+
+if ![ld_simple_link $ld tmpdir/extern "-T $srcdir/$subdir/extern.t tmpdir/extern.o"] {
+    fail $testname
+}
+
+if ![ld_nm $nm "" tmpdir/extern] {
+    unresolved $testname
+    return
+}
+
+if {![info exists nm_output(sym1)] || $nm_output(sym1) != 1} {
+    send_log "sym1 wrong\n"
+    verbose "sym1 wrong"
+    fail $testname
+    return
+}
+    
+if {![info exists nm_output(sym2)] || $nm_output(sym2) != 2} {
+    send_log "sym1 wrong\n"
+    verbose "sym1 wrong"
+    fail $testname
+    return
+}
+if {![info exists nm_output(sym3)] || $nm_output(sym3) != 3} {
+    send_log "sym1 wrong\n"
+    verbose "sym1 wrong"
+    fail $testname
+    return
+}
+if {![info exists nm_output(sym4)] || $nm_output(sym4) != 4} {
+    send_log "sym1 wrong\n"
+    verbose "sym1 wrong"
+    fail $testname
+    return
+}
+if {![info exists nm_output(sym5)] || $nm_output(sym5) != 5} {
+    send_log "sym1 wrong\n"
+    verbose "sym1 wrong"
+    fail $testname
+    return
+}
+
+pass $testname
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/extern.s b/binutils-2.19/ld/testsuite/ld-scripts/extern.s
new file mode 100644
index 0000000..09cc1e1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/extern.s
@@ -0,0 +1 @@
+	.text
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/extern.t b/binutils-2.19/ld/testsuite/ld-scripts/extern.t
new file mode 100644
index 0000000..b2a012a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/extern.t
@@ -0,0 +1,14 @@
+
+EXTERN(sym1)
+EXTERN(sym2, sym3)
+EXTERN(sym4 sym5)
+
+PROVIDE(sym1 = 1);
+PROVIDE(sym2 = 2);
+PROVIDE(sym3 = 3);
+PROVIDE(sym4 = 4);
+PROVIDE(sym5 = 5);
+
+SECTIONS
+{
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/include-1.d b/binutils-2.19/ld/testsuite/ld-scripts/include-1.d
new file mode 100644
index 0000000..4ad1fe8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/include-1.d
@@ -0,0 +1,13 @@
+# name: include-1
+# source: include.s
+# ld: -T include-1.t
+# objdump: -w -h
+# xfail: "*-aix*"
+# AIX targets rename the .text and .data sectons...
+
+.*:     file format .*
+
+Sections:
+Idx +Name +Size +VMA +LMA +File off +Algn +Flags
+  0 .text         0+0000020  0+0000000  0+0000000  [0-9a-f]+  2\*\*[0-9]+  CONTENTS, ALLOC, LOAD,.*CODE
+  1 .data         0+0000010  0+0100000  0+0100000  [0-9a-f]+  2\*\*[0-9]+  CONTENTS, ALLOC, LOAD, DATA
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/include-1.t b/binutils-2.19/ld/testsuite/ld-scripts/include-1.t
new file mode 100644
index 0000000..cf2f8cd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/include-1.t
@@ -0,0 +1,4 @@
+
+INCLUDE include-mem.t
+_start = 0x1000;
+INCLUDE include-sections.t
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/include-data.t b/binutils-2.19/ld/testsuite/ld-scripts/include-data.t
new file mode 100644
index 0000000..eddbbb3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/include-data.t
@@ -0,0 +1,4 @@
+.data : {
+INCLUDE include-subdata.t
+__end = .;
+}>ram
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/include-mem.t b/binutils-2.19/ld/testsuite/ld-scripts/include-mem.t
new file mode 100644
index 0000000..8aa65b1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/include-mem.t
@@ -0,0 +1,5 @@
+
+MEMORY {
+  rom (rwx) : ORIGIN = 0, LENGTH = 0x1000
+  INCLUDE include-ram.t
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/include-ram.t b/binutils-2.19/ld/testsuite/ld-scripts/include-ram.t
new file mode 100644
index 0000000..f7eaf0e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/include-ram.t
@@ -0,0 +1 @@
+ram (rw) : ORIGIN = 0x100000, LENGTH = 512
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/include-sections.t b/binutils-2.19/ld/testsuite/ld-scripts/include-sections.t
new file mode 100644
index 0000000..5d6ca1e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/include-sections.t
@@ -0,0 +1,5 @@
+SECTIONS {
+	 .text : { *(.text) } >rom
+	 INCLUDE include-data.t
+	 /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/include-subdata.t b/binutils-2.19/ld/testsuite/ld-scripts/include-subdata.t
new file mode 100644
index 0000000..136c9f4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/include-subdata.t
@@ -0,0 +1,2 @@
+ *(.data)
+
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/include.exp b/binutils-2.19/ld/testsuite/ld-scripts/include.exp
new file mode 100644
index 0000000..98fd55d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/include.exp
@@ -0,0 +1,39 @@
+# Test for proper diagnosis of overflowed memory regions.
+# Copyright 2008 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+load_lib ld-lib.exp
+
+if [is_aout_format] {
+    return
+}
+
+set old_ldflags $LDFLAGS
+if { [istarget spu*-*-*] } {
+    set LDFLAGS "$LDFLAGS --no-overlays"
+}
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/include*.d]]
+foreach test_file $test_list {
+    set test_name [file rootname $test_file]
+    set map_file "tmpdir/[file tail $test_name].map"
+    verbose $test_name
+    run_dump_test $test_name
+}
+set LDFLAGS $old_ldflags
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/include.s b/binutils-2.19/ld/testsuite/ld-scripts/include.s
new file mode 100644
index 0000000..e9fca05
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/include.s
@@ -0,0 +1,5 @@
+	.text
+	.fill 32,1,0x12
+
+	.data
+	.fill 16,1,0x34
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/map-address.d b/binutils-2.19/ld/testsuite/ld-scripts/map-address.d
new file mode 100644
index 0000000..7877ca4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/map-address.d
@@ -0,0 +1,12 @@
+#...
+Linker script and memory map
+#...
+ *0x0*000020 *def1 = .*
+ *0x0*000020 *def2 = def1
+ *0x0*010001 *\. = 0x10001
+ *0x0*010001 *foo = \.
+ *0x0*010201 *\. = \(\. \+ 0x200\)
+ *0x0*010201 *bar = \.
+ *0x0*010204 *\. = ALIGN \(0x4\)
+ *0x0*010204 *frob = \.
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/map-address.exp b/binutils-2.19/ld/testsuite/ld-scripts/map-address.exp
new file mode 100644
index 0000000..c8fe653
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/map-address.exp
@@ -0,0 +1,47 @@
+# Test address printed by --print-map
+# Copyright 2002, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+set testname "map addresses"
+
+# The source file doesn't matter.  Pinch one from the sizeof test.
+if {![ld_assemble $as $srcdir/$subdir/sizeof.s tmpdir/map-address.o]} {
+    unresolved $testname
+    return
+}
+
+if {![ld_simple_link $ld tmpdir/map-address \
+	 "-T $srcdir/$subdir/map-address.t \
+	  tmpdir/map-address.o \
+	  -Map tmpdir/map-address.map"]} {
+    fail $testname
+    return
+}
+
+if [is_remote host] then {
+    remote_upload host "tmpdir/map_address.map"
+}
+
+if {[regexp_diff \
+	       "tmpdir/map-address.map" \
+	       "$srcdir/$subdir/map-address.d"]} {
+    fail $testname
+} else {
+    pass $testname
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/map-address.t b/binutils-2.19/ld/testsuite/ld-scripts/map-address.t
new file mode 100644
index 0000000..e077ed1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/map-address.t
@@ -0,0 +1,11 @@
+SECTIONS
+{
+  def1 = DEFINED(foo) ? 0x10 : 0x20;
+  def2 = def1;
+  . = 0x10001;
+  foo = .;
+  . += 0x200;
+  bar = .;
+  . = ALIGN (4);
+  frob = .;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/memory.t b/binutils-2.19/ld/testsuite/ld-scripts/memory.t
new file mode 100644
index 0000000..8a73c58
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/memory.t
@@ -0,0 +1,39 @@
+MEMORY
+{
+  TEXTMEM (ARX) : ORIGIN = 0x100, LENGTH = 32K
+  DATAMEM (AW)  : org = 0x1000, l = (64 * 1024)
+}
+
+SECTIONS
+{
+  . = 0;
+  .text :
+  {
+    /* The value returned by the ORIGIN operator is a constant.
+       However it is being assigned to a symbol declared within
+       a section.  Therefore the symbol is section-relative and
+       its value will include the offset of that section from
+       the start of memory.  ie the declaration:
+          text_start = ORIGIN (TEXTMEM);
+       here will result in text_start having a value of 0x200.
+       Hence we need to subtract the absolute value of the
+       location counter at this point in order to give text_start
+       a value that is truely absolute, and which coincidentally
+       will allow the tests in script.exp to work.  */
+ 	
+    text_start = ORIGIN(TEXTMEM) - ABSOLUTE (.);
+    *(.text)
+    *(.pr)
+    text_end = .;
+  } > TEXTMEM
+  
+  data_start = ORIGIN (DATAMEM);
+  .data :
+  {
+    *(.data)
+    *(.rw)
+    data_end = .;
+  } >DATAMEM
+
+  fred = ORIGIN(DATAMEM) + LENGTH(DATAMEM);  
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/overlay-size-map.d b/binutils-2.19/ld/testsuite/ld-scripts/overlay-size-map.d
new file mode 100644
index 0000000..a72d359
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/overlay-size-map.d
@@ -0,0 +1,29 @@
+#...
+\.bss1 *0x0*20000 *0x10
+#...
+\.bss2 *0x0*20000 *0x30 load address 0x0*20010
+#...
+\.bss3 *0x0*20000 *0x20 load address 0x0*20040
+#...
+.*0x0+020030[ 	]*end_of_bss_overlays.*
+#...
+\.mtext *0x0*10000 *0x20 load address 0x0*30000
+#...
+\.mbss *0x0*20030 *0x230 load address 0x0*20060
+#...
+\.text1 *0x0*10020 *0x80 load address 0x0*30020
+#...
+\.text2 *0x0*10020 *0x40 load address 0x0*300a0
+#...
+\.text3 *0x0*10020 *0x20 load address 0x0*300e0
+#...
+.*0x0+0100a0[ 	]*end_of_text_overlays.*
+#...
+\.data1 *0x0*20260 *0x30 load address 0x0*30100
+#...
+\.data2 *0x0*20260 *0x40 load address 0x0*30130
+#...
+\.data3 *0x0*20260 *0x50 load address 0x0*30170
+#...
+.*0x0+0202b0[ 	]*end_of_data_overlays.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/overlay-size.d b/binutils-2.19/ld/testsuite/ld-scripts/overlay-size.d
new file mode 100644
index 0000000..9021aa4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/overlay-size.d
@@ -0,0 +1,29 @@
+# ld: -T overlay-size.t -Map tmpdir/overlay-size.map
+# name: overlay size
+# objdump: --headers
+#
+# The .bss[123] LMAs are deliberately blanked out.  We can't
+# reliably map overlaid sections to segments.
+#...
+ .. \.bss1 +0+010 +0+20000 .*
+#...
+ .. \.bss2 +0+030 +0+20000 .*
+#...
+ .. \.bss3 +0+020 +0+20000 .*
+#...
+ .. \.mtext +0+020 +0+10000 +0+30000 .*
+#...
+ .. \.mbss +0+230 +0+20030 .*
+#...
+ .. \.text1 +0+080 +0+10020 +0+30020 .*
+#...
+ .. \.text2 +0+040 +0+10020 +0+300a0 .*
+#...
+ .. \.text3 +0+020 +0+10020 +0+300e0 .*
+#...
+ .. \.data1 +0+030 +0+20260 +0+30100 .*
+#...
+ .. \.data2 +0+040 +0+20260 +0+30130 .*
+#...
+ .. \.data3 +0+050 +0+20260 +0+30170 .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/overlay-size.exp b/binutils-2.19/ld/testsuite/ld-scripts/overlay-size.exp
new file mode 100644
index 0000000..ce0c068
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/overlay-size.exp
@@ -0,0 +1,34 @@
+# Test the OVERLAY statement.
+# Copyright 2002, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+if ![is_elf_format] {
+    return
+}
+
+run_dump_test overlay-size
+
+set testname "overlay size (map check)"
+
+if [regexp_diff "tmpdir/overlay-size.map" \
+	        "$srcdir/$subdir/overlay-size-map.d"] {
+    fail $testname
+} else {
+    pass $testname
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/overlay-size.s b/binutils-2.19/ld/testsuite/ld-scripts/overlay-size.s
new file mode 100644
index 0000000..5428c97
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/overlay-size.s
@@ -0,0 +1,25 @@
+	.section .bss1, "aw", "nobits"
+	.space 0x10
+	.section .bss2, "aw", "nobits"
+	.space 0x30
+	.section .bss3, "aw", "nobits"
+	.space 0x20
+
+	.section .text1, "ax", "progbits"
+	.space 0x80
+	.section .text2, "ax", "progbits"
+	.space 0x40
+	.section .text3, "ax", "progbits"
+	.space 0x20
+
+	.section .data1, "aw", "progbits"
+	.space 0x30
+	.section .data2, "aw", "progbits"
+	.space 0x40
+	.section .data3, "aw", "progbits"
+	.space 0x50
+
+	.section .mtext, "ax", "progbits"
+	.space 0x20
+	.section .mbss, "aw", "nobits"
+	.space 0x30
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/overlay-size.t b/binutils-2.19/ld/testsuite/ld-scripts/overlay-size.t
new file mode 100644
index 0000000..0d9af35
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/overlay-size.t
@@ -0,0 +1,64 @@
+MEMORY
+{
+  TEXTMEM (ARX) : ORIGIN = 0x10000, LENGTH = 32K
+  DATAMEM (AW)  : ORIGIN = 0x20000, LENGTH = 32K
+  LOADMEM (AW)  : ORIGIN = 0x30000, LENGTH = 32K
+}
+
+/* Map should be:
+
+           SIZE    VMA    LMA
+   .bss1     10  20000  20000
+   .bss2     30  20000  20010
+   .bss3     20  20000  20040
+   .mbss    230  20030  20060
+
+   .mtext    20  10000  30000
+   .text1    80  10020  30020
+   .text2    40  10020  300a0
+   .text3    20  10020  300e0
+
+   .data1    30  20260  30100
+   .data2    40  20260  30130
+   .data3    50  20260  30170  */
+
+SECTIONS
+{
+  OVERLAY : 
+    {
+      .bss1 { *(.bss1) }
+      .bss2 { *(.bss2) }
+      .bss3 { *(.bss3) }
+    } > DATAMEM
+
+  end_of_bss_overlays = . ;
+    
+  .mtext : { *(.mtext) } > TEXTMEM AT > LOADMEM
+
+  .mbss : AT (__load_stop_bss3)
+    {
+      *(.mbss)
+      . += 0x200;
+    } > DATAMEM
+
+  OVERLAY :
+    {
+      .text1 { *(.text1) }
+      .text2 { *(.text2) }
+      .text3 { *(.text3) }
+    } > TEXTMEM AT > LOADMEM
+
+  end_of_text_overlays = . ;
+
+  OVERLAY :
+    {
+      .data1 { *(.data1) }
+      .data2 { *(.data2) }
+      .data3 { *(.data3) }
+    } > DATAMEM AT > LOADMEM
+
+  end_of_data_overlays = . ;
+  
+  . = 0x8000;
+  /DISCARD/ : { *(.reginfo) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/phdrs.exp b/binutils-2.19/ld/testsuite/ld-scripts/phdrs.exp
new file mode 100644
index 0000000..ad59cd1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/phdrs.exp
@@ -0,0 +1,68 @@
+# Test PHDRS in a linker script.
+# By Ian Lance Taylor, Cygnus Support.
+#   Copyright 1999, 2000, 2001, 2002, 2003, 2006, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# PHDRS is only meaningful for ELF.
+if ![is_elf_format] {
+    return
+}
+
+# This is a very simplistic test.
+
+set testname "PHDRS"
+
+set ldopt ""
+if { [istarget spu*-*-*] } {
+    set ldopt "--local-store 0:0"
+}
+
+if ![ld_assemble $as $srcdir/$subdir/phdrs.s tmpdir/phdrs.o] {
+    unresolved $testname
+    return
+}
+
+set phdrs_regexp \
+".*Program Header:.*PHDR *off *0x00*34 *vaddr *0x00*800034 *paddr *0x00*800034.*filesz *0x0\[0-9a-f\]* *memsz *0x0\[0-9a-f\]* flags r--.*LOAD *off *0x00* *vaddr *0x00*800000 *paddr *0x00*800000.*filesz *0x00*\[0-9a-f\]* *memsz *0x0\[0-9a-f\]* *flags r-x.*LOAD *off *0x0\[0-9a-f\]* *vaddr *0x00*80*\[0-9a-f\]* *paddr *0x00*80*\[0-9a-f\]*.*filesz *0x0\[0-9a-f\]* *memsz *0x0\[0-9a-f\]* *flags *rw-.*"
+
+# On a 64 bit ELF format, we need different numbers.
+if [is_elf64 tmpdir/phdrs.o] {
+    set phdrs_regexp \
+".*Program Header:.*PHDR *off *0x00*40 *vaddr *0x00*800040 *paddr *0x00*800040.*filesz *0x0\[0-9a-f\]* *memsz *0x0\[0-9a-f\]* flags r--.*LOAD *off *0x00* *vaddr *0x00*800000 *paddr *0x00*800000.*filesz *0x00*\[0-9a-f\]* *memsz *0x0\[0-9a-f\]* *flags r-x.*LOAD *off *0x0\[0-9a-f\]* *vaddr *0x00*80*\[0-9a-f\]* *paddr *0x00*80*\[0-9a-f\]*.*filesz *0x0\[0-9a-f\]* *memsz *0x0\[0-9a-f\]* *flags *rw-.*"
+}
+
+set ldopt "$ldopt -T $srcdir/$subdir/phdrs.t tmpdir/phdrs.o"
+if ![ld_simple_link $ld tmpdir/phdrs $ldopt] {
+    fail $testname
+} else {
+    if {![is_remote host] && [which $objdump] == 0} {
+	unresolved $testname
+	return
+    }
+    set exec_output [run_host_cmd "$objdump" "--private tmpdir/phdrs"]
+    set exec_output [prune_warnings $exec_output]
+    verbose -log $exec_output
+
+    if [regexp $phdrs_regexp $exec_output] {
+	pass $testname
+    } else {
+	fail $testname
+    }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/phdrs.s b/binutils-2.19/ld/testsuite/ld-scripts/phdrs.s
new file mode 100644
index 0000000..ec1f0d1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/phdrs.s
@@ -0,0 +1,8 @@
+	.text
+
+	.long	1
+
+	.data
+
+	.long	2
+	
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/phdrs.t b/binutils-2.19/ld/testsuite/ld-scripts/phdrs.t
new file mode 100644
index 0000000..283e30c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/phdrs.t
@@ -0,0 +1,16 @@
+PHDRS
+{
+  header PT_PHDR PHDRS ;
+  text PT_LOAD FILEHDR PHDRS ;
+  data PT_LOAD ;
+}
+
+SECTIONS
+{
+  /* This test will fail on architectures where the startaddress below
+     is less than the constant MAXPAGESIZE.  */
+  . = 0x800000 + SIZEOF_HEADERS;
+  .text : { *(.text) } :text
+  .data : { *(.data) } :data
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/phdrs2.exp b/binutils-2.19/ld/testsuite/ld-scripts/phdrs2.exp
new file mode 100644
index 0000000..5a4a8cc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/phdrs2.exp
@@ -0,0 +1,74 @@
+# Test PHDRS with empty sections in a linker script.
+# Copyright 2007  Free Software Foundation, Inc,
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# PHDRS2 is only meaningful for ELF.
+if {    ![istarget *-*-sysv4*] \
+     && ![istarget *-*-unixware*] \
+     && ![istarget *-*-elf*] \
+     && ![istarget *-*-eabi*] \
+     && ![istarget hppa*64*-*-hpux*] \
+     && ![istarget *-*-linux*] \
+     && ![istarget *-*-irix5*] \
+     && ![istarget *-*-irix6*] \
+     && ![istarget *-*-solaris2*] } {
+    return
+}
+
+if { [istarget *-*-linux*aout*] \
+     || [istarget *-*-linux*oldld*] } {
+    return
+}
+
+# This is a very simplistic test.
+
+set testname "PHDRS2"
+
+set ldopt ""
+if { [istarget spu*-*-*] } {
+    set ldopt "--local-store 0:0"
+}
+
+if ![ld_assemble $as $srcdir/$subdir/phdrs2.s tmpdir/phdrs2.o] {
+    unresolved $testname
+    return
+}
+
+set phdrs_regexp \
+    ".*Program Header:.*LOAD *off *0x00\[0-9a-f\]* *vaddr *0x00*800000 *paddr *0x00*800000.*filesz *0x0\[0-9a-f\]* *memsz *0x0\[0-9a-f\]*.*LOAD *off *0x00\[0-9a-f\]* *vaddr *0x00*800004 *paddr *0x00*800004.*filesz *0x00*\[0-9a-f\]* *memsz *0x0\[0-9a-f\]* *flags rw.*"
+
+set ldopt "$ldopt -T $srcdir/$subdir/phdrs2.t tmpdir/phdrs2.o"
+if ![ld_simple_link $ld tmpdir/phdrs2 $ldopt] {
+    fail $testname
+} else {
+    if {![is_remote host] && [which $objdump] == 0} {
+	unresolved $testname
+	return
+    }
+
+    set exec_output [run_host_cmd "$objdump" "--private tmpdir/phdrs2"]
+    set exec_output [prune_warnings $exec_output]
+    verbose -log $exec_output
+
+    if [regexp $phdrs_regexp $exec_output] {
+	pass $testname
+    } else {
+	fail $testname
+    }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/phdrs2.s b/binutils-2.19/ld/testsuite/ld-scripts/phdrs2.s
new file mode 100644
index 0000000..1e29ddc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/phdrs2.s
@@ -0,0 +1,7 @@
+	.section .foo, "ax"
+	.p2align 2
+	.long	1
+
+	.section .bar, "aw"
+	.p2align 2
+	.long	2
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/phdrs2.t b/binutils-2.19/ld/testsuite/ld-scripts/phdrs2.t
new file mode 100644
index 0000000..bccbcec
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/phdrs2.t
@@ -0,0 +1,23 @@
+PHDRS
+{
+  Foo PT_LOAD ;
+  Bar PT_LOAD ;
+}
+
+SECTIONS
+{
+  . = 0x800000 - 1;
+  /* The PHDRS generated should start at the aligned .foo section
+     address, not the unaligned .empty section address */
+  .empty : { 
+	EMPTY_START = ABSOLUTE(.) ;
+	*(.empty) 
+	EMPTY_END = ABSOLUTE(.) ;
+	} : Foo
+  .foo : { *(.foo) } : Foo
+  .bar : { *(.bar)
+	LONG(EMPTY_START) ;
+	 } : Bar
+	
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/provide-1.d b/binutils-2.19/ld/testsuite/ld-scripts/provide-1.d
new file mode 100644
index 0000000..ac8719a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/provide-1.d
@@ -0,0 +1,9 @@
+#source: provide-1.s
+#ld: -T provide-1.t
+#objdump: -s -j .data
+
+.*:     file format .*
+
+Contents of section .data:
+ [0-9a-f]* (1020)?0000(2010)? (2020)?0000(2020)? 00000000 .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/provide-1.s b/binutils-2.19/ld/testsuite/ld-scripts/provide-1.s
new file mode 100644
index 0000000..1e33540
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/provide-1.s
@@ -0,0 +1,4 @@
+	.data
+	.globl foo
+foo:	.long 0
+	.p2align 4
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/provide-1.t b/binutils-2.19/ld/testsuite/ld-scripts/provide-1.t
new file mode 100644
index 0000000..6b96b33
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/provide-1.t
@@ -0,0 +1,12 @@
+SECTIONS 
+{
+  .data 0x2000 :
+  {
+    LONG (foo)
+    LONG (bar)
+    . = ALIGN (0x10);
+    *(.data)
+  }
+  PROVIDE (foo = .);
+  PROVIDE (bar = .);
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/provide-2.d b/binutils-2.19/ld/testsuite/ld-scripts/provide-2.d
new file mode 100644
index 0000000..e151b30
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/provide-2.d
@@ -0,0 +1,7 @@
+#source: provide-2.s
+#ld: -T provide-2.t
+#nm: -B
+#...
+0+3 A baz
+0+2000 D foo
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/provide-2.s b/binutils-2.19/ld/testsuite/ld-scripts/provide-2.s
new file mode 100644
index 0000000..f9138db
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/provide-2.s
@@ -0,0 +1,8 @@
+	.data
+	.globl foo
+foo:	.long 0
+
+	.globl baz
+	.long baz
+
+	.p2align 4
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/provide-2.t b/binutils-2.19/ld/testsuite/ld-scripts/provide-2.t
new file mode 100644
index 0000000..fe30dd8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/provide-2.t
@@ -0,0 +1,10 @@
+SECTIONS 
+{
+  PROVIDE (foo = 1);
+  PROVIDE (bar = 2);
+  PROVIDE (baz = 3);
+  .data 0x2000 :
+  {
+    *(.data)
+  }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/provide-3.d b/binutils-2.19/ld/testsuite/ld-scripts/provide-3.d
new file mode 100644
index 0000000..c8b12da
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/provide-3.d
@@ -0,0 +1,3 @@
+#source: provide-3.s
+#ld: -T provide-3.t
+#error: symbol defined in linker script and object file
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/provide-3.s b/binutils-2.19/ld/testsuite/ld-scripts/provide-3.s
new file mode 100644
index 0000000..1e33540
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/provide-3.s
@@ -0,0 +1,4 @@
+	.data
+	.globl foo
+foo:	.long 0
+	.p2align 4
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/provide-3.t b/binutils-2.19/ld/testsuite/ld-scripts/provide-3.t
new file mode 100644
index 0000000..f6229d4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/provide-3.t
@@ -0,0 +1,11 @@
+SECTIONS 
+{
+  .data :
+  {
+    LONG (foo)
+    LONG (bar)
+    *(.data)
+  }
+  foo = .;
+  bar = .;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/provide.exp b/binutils-2.19/ld/testsuite/ld-scripts/provide.exp
new file mode 100644
index 0000000..5a489c1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/provide.exp
@@ -0,0 +1,45 @@
+# Test PROVIDE in a linker script.
+# By Nathan Sidwell, CodeSourcery LLC
+#   Copyright 2004, 2006, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# AIX maps .text and .data to other sections.
+# a.out objdump displays the file header inside the text segment,
+# confusing run_dump_test.
+
+if {[istarget "rs6000-*-aix*"] || [is_aout_format]} {
+    unsupported provide-1
+    unsupported provide-2
+    unsupported provide-3
+    return
+}
+
+global LDFLAGS
+set saved_LDFLAGS "$LDFLAGS"
+if [istarget "x86_64-*-mingw*"] then {
+  set LDFLAGS "$LDFLAGS --image-base 0"
+}
+
+run_dump_test provide-1
+run_dump_test provide-2
+setup_xfail *-*-*
+run_dump_test provide-3
+
+set LDFLAGS "$saved_LDFLAGS"
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over.exp b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over.exp
new file mode 100644
index 0000000..05a7071
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over.exp
@@ -0,0 +1,54 @@
+# Test for proper diagnosis of overflowed memory regions.
+# Copyright 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+if ![is_elf_format] {
+    return
+}
+
+load_lib ld-lib.exp
+
+set old_ldflags $LDFLAGS
+if { [istarget spu*-*-*] } {
+    set LDFLAGS "$LDFLAGS --no-overlays"
+}
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/rgn-over*.d]]
+foreach test_file $test_list {
+    set test_name [file rootname $test_file]
+    set map_file "tmpdir/[file tail $test_name].map"
+    verbose $test_name
+    run_dump_test $test_name
+
+    if { ! [regexp ".*-ok.d" $test_file] } {
+	set testname "[file tail $test_name] (map check)"
+	if [file exists $map_file] {
+	    # compare the map file to the expectations in the .d file
+	    # (run_dump_test can't do that).
+	    if [regexp_diff $map_file $test_file] {
+		fail $testname
+	    } else {
+		pass $testname
+	    }
+	} else {
+	    untested $testname
+	}
+    }
+}
+set LDFLAGS $old_ldflags
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over.s b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over.s
new file mode 100644
index 0000000..f651cce
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over.s
@@ -0,0 +1,9 @@
+	.section .txt, "ax", "progbits"
+	.4byte 0x11223344
+	.4byte 0x55667788
+	.4byte 0x99aabbcc
+
+	.section .dat, "aw", "progbits"
+	.4byte 0x01020304
+	.4byte 0x05060708
+	.4byte 0x090a0b0c
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over1.d b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over1.d
new file mode 100644
index 0000000..2ce7ffc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over1.d
@@ -0,0 +1,35 @@
+# name: rgn-over1
+# source: rgn-over.s
+# ld: -T rgn-over1.t -Map tmpdir/rgn-over1.map
+# error: \A[^ \n]*?ld[^:\n]*?: [^\n]*?section \.text will not fit in region r1\n[^ \n]*?ld[^:\n]*?: region r1 overflowed by 16 bytes\Z
+
+Discarded input sections
+#...
+Memory\s+Configuration
+
+Name\s+Origin\s+Length\s+Attributes
+bss\s+0x0+0000\s+0x0+0000\s+xrw
+r1\s+0x0+1000\s+0x0+0008\s+xrw
+\*default\*\s+0x0+0000\s+0xf+ffff
+
+Linker\s+script\s+and\s+memory\s+map
+
+\s*0x0+1000\s+_start\s+=\s+0x1000
+
+\s*\.bss\s+0x0+0000\s+0x0
+\s*\*\(\.bss\)
+\s*\.bss\s+0x0+0000\s+0x0\s+.*?
+
+\s*\.text\s+0x0+1000\s+0xc
+\s*\*\(\.txt\)
+\s*\.txt\s+0x0+1000\s+0xc\s+.*?
+
+\s*\.data\s+0x0+100c\s+0xc
+\s*\*\(\.dat\)
+\s*\.dat\s+0x0+100c\s+0xc\s+.*?
+
+/DISCARD/
+ \*\(\*\)
+LOAD\s+.*?
+OUTPUT\(.*?\)
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over1.t b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over1.t
new file mode 100644
index 0000000..9c14f70
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over1.t
@@ -0,0 +1,13 @@
+/* Memory region overflow tests: one region, first output sect doesn't fit. */
+
+MEMORY {
+  bss (rwx) : ORIGIN = 0, LENGTH = 0
+  r1  (rwx) : ORIGIN = 0x1000, LENGTH = 8
+}
+_start = 0x1000;
+SECTIONS {
+  .bss  : { *(.bss)  } > bss
+  .text : { *(.txt) } > r1
+  .data : { *(.dat) } > r1
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over2.d b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over2.d
new file mode 100644
index 0000000..ace0117
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over2.d
@@ -0,0 +1,35 @@
+# name: rgn-over2
+# source: rgn-over.s
+# ld: -T rgn-over2.t -Map tmpdir/rgn-over2.map
+# error: \A[^ \n]*?ld[^:\n]*?: [^\n]*?section \.data will not fit in region r1\n[^ \n]*?ld[^:\n]*?: region r1 overflowed by 4 bytes\Z
+
+Discarded input sections
+#...
+Memory\s+Configuration
+
+Name\s+Origin\s+Length\s+Attributes
+bss\s+0x0+0000\s+0x0+0000\s+xrw
+r1\s+0x0+1000\s+0x0+0014\s+xrw
+\*default\*\s+0x0+0000\s+0xf+ffff
+
+Linker\s+script\s+and\s+memory\s+map
+
+\s*0x0+1000\s+_start\s+=\s+0x1000
+
+\s*\.bss\s+0x0+0000\s+0x0
+\s*\*\(\.bss\)
+\s*\.bss\s+0x0+0000\s+0x0\s+.*?
+
+\s*\.text\s+0x0+1000\s+0xc
+\s*\*\(\.txt\)
+\s*\.txt\s+0x0+1000\s+0xc\s+.*?
+
+\s*\.data\s+0x0+100c\s+0xc
+\s*\*\(\.dat\)
+\s*\.dat\s+0x0+100c\s+0xc\s+.*?
+
+/DISCARD/
+ \*\(\*\)
+LOAD\s+.*?
+OUTPUT\(.*?\)
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over2.t b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over2.t
new file mode 100644
index 0000000..b38a9c1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over2.t
@@ -0,0 +1,14 @@
+/* Memory region overflow tests: one region, first output sect fits,
+   second doesn't. */
+
+MEMORY {
+  bss (rwx) : ORIGIN = 0, LENGTH = 0
+  r1 (rwx) : ORIGIN = 0x1000, LENGTH = 20
+}
+_start = 0x1000;
+SECTIONS {
+  .bss  : { *(.bss)  } > bss
+  .text : { *(.txt) } > r1
+  .data : { *(.dat) } > r1
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over3.d b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over3.d
new file mode 100644
index 0000000..9150417
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over3.d
@@ -0,0 +1,36 @@
+# name: rgn-over3
+# source: rgn-over.s
+# ld: -T rgn-over3.t -Map tmpdir/rgn-over3.map
+# error: \A[^ \n]*?ld[^:\n]*?: [^\n]*?section \.text will not fit in region r1\n[^ \n]*?ld[^:\n]*?: [^\n]*?section \.data will not fit in region r2\n[^ \n]*?ld[^:\n]*?: region r1 overflowed by 4 bytes\n[^ \n]*?ld[^:\n]*?: region r2 overflowed by 4 bytes\Z
+
+Discarded input sections
+#...
+Memory\s+Configuration
+
+Name\s+Origin\s+Length\s+Attributes
+bss\s+0x0+0000\s+0x0+0000\s+xrw
+r1\s+0x0+1000\s+0x0+0008\s+xrw
+r2\s+0x0+2000\s+0x0+0008\s+xrw
+\*default\*\s+0x0+0000\s+0xf+ffff
+
+Linker\s+script\s+and\s+memory\s+map
+
+\s*0x0+1000\s+_start\s+=\s+0x1000
+
+\s*\.bss\s+0x0+0000\s+0x0
+\s*\*\(\.bss\)
+\s*\.bss\s+0x0+0000\s+0x0\s+.*?
+
+\s*\.text\s+0x0+1000\s+0xc
+\s*\*\(\.txt\)
+\s*\.txt\s+0x0+1000\s+0xc\s+.*?
+
+\s*\.data\s+0x0+2000\s+0xc
+\s*\*\(\.dat\)
+\s*\.dat\s+0x0+2000\s+0xc\s+.*?
+
+/DISCARD/
+ \*\(\*\)
+LOAD\s+.*?
+OUTPUT\(.*?\)
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over3.t b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over3.t
new file mode 100644
index 0000000..5341fb5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over3.t
@@ -0,0 +1,15 @@
+/* Memory region overflow tests: two regions, each too small for the single
+   section placed there. */
+
+MEMORY {
+  bss (rwx) : ORIGIN = 0, LENGTH = 0
+  r1  (rwx) : ORIGIN = 0x1000, LENGTH = 8
+  r2  (rwx) : ORIGIN = 0x2000, LENGTH = 8
+}
+_start = 0x1000;
+SECTIONS {
+  .bss  : { *(.bss)  } > bss
+  .text : { *(.txt) } > r1
+  .data : { *(.dat) } > r2
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over4.d b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over4.d
new file mode 100644
index 0000000..e4e98c5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over4.d
@@ -0,0 +1,36 @@
+# name: rgn-over4
+# source: rgn-over.s
+# ld: -T rgn-over4.t -Map tmpdir/rgn-over4.map
+# error: \A[^ \n]*?ld[^:\n]*?: [^:\n]*?section \.text will not fit in region r1\n[^ \n]*?ld[^:\n]*?: region r1 overflowed by 16 bytes\Z
+
+Discarded input sections
+#...
+Memory\s+Configuration
+
+Name\s+Origin\s+Length\s+Attributes
+bss\s+0x0+0000\s+0x0+0000\s+xrw
+r1\s+0x0+1000\s+0x0+0008\s+xrw
+v1\s+0x0+2000\s+0x0+0018\s+xrw
+\*default\*\s+0x0+0000\s+0xf+ffff
+
+Linker\s+script\s+and\s+memory\s+map
+
+\s*0x0+1000\s+_start\s+=\s+0x1000
+
+\s*\.bss\s+0x0+0000\s+0x0
+\s*\*\(\.bss\)
+\s*\.bss\s+0x0+0000\s+0x0\s+.*?
+
+\s*\.text\s+0x0+1000\s+0xc\s+load\s+address\s+0x0+2000
+\s*\*\(\.txt\)
+\s*\.txt\s+0x0+1000\s+0xc\s+.*?
+
+\s*\.data\s+0x0+100c\s+0xc\s+load\s+address\s+0x0+200c
+\s*\*\(\.dat\)
+\s*\.dat\s+0x0+100c\s+0xc\s+.*?
+
+/DISCARD/
+ \*\(\*\)
+LOAD\s+.*?
+OUTPUT\(.*?\)
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over4.t b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over4.t
new file mode 100644
index 0000000..d2463e9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over4.t
@@ -0,0 +1,14 @@
+/* Memory region overflow tests: overflow VMA but not LMA.  */
+
+MEMORY {
+  bss (rwx) : ORIGIN = 0, LENGTH = 0
+  r1  (rwx) : ORIGIN = 0x1000, LENGTH = 8
+  v1  (rwx) : ORIGIN = 0x2000, LENGTH = 24
+}
+_start = 0x1000;
+SECTIONS {
+  .bss  : { *(.bss)  } > bss
+  .text : { *(.txt) } > r1 AT> v1
+  .data : { *(.dat) } > r1 AT> v1
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over5.d b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over5.d
new file mode 100644
index 0000000..abce4e1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over5.d
@@ -0,0 +1,36 @@
+# name: rgn-over5
+# source: rgn-over.s
+# ld: -T rgn-over5.t -Map tmpdir/rgn-over5.map
+# error: \A[^ \n]*?ld[^:\n]*?: [^\n]*?section \.text will not fit in region v1\n[^ \n]*?ld[^:\n]*?: region v1 overflowed by 16 bytes\Z
+
+Discarded input sections
+#...
+Memory\s+Configuration
+
+Name\s+Origin\s+Length\s+Attributes
+bss\s+0x0+0000\s+0x0+0000\s+xrw
+r1\s+0x0+1000\s+0x0+0018\s+xrw
+v1\s+0x0+2000\s+0x0+0008\s+xrw
+\*default\*\s+0x0+0000\s+0xf+ffff
+
+Linker\s+script\s+and\s+memory\s+map
+
+\s*0x0+1000\s+_start\s+=\s+0x1000
+
+\s*\.bss\s+0x0+0000\s+0x0
+\s*\*\(\.bss\)
+\s*\.bss\s+0x0+0000\s+0x0\s+.*?
+
+\s*\.text\s+0x0+1000\s+0xc\s+load\s+address\s+0x0+2000
+\s*\*\(\.txt\)
+\s*\.txt\s+0x0+1000\s+0xc\s+.*?
+
+\s*\.data\s+0x0+100c\s+0xc\s+load\s+address\s+0x0+200c
+\s*\*\(\.dat\)
+\s*\.dat\s+0x0+100c\s+0xc\s+.*?
+
+/DISCARD/
+ \*\(\*\)
+LOAD\s+.*?
+OUTPUT\(.*?\)
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over5.t b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over5.t
new file mode 100644
index 0000000..2b0ae68
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over5.t
@@ -0,0 +1,14 @@
+/* Memory region overflow tests: overflow LMA but not VMA.  */
+
+MEMORY {
+  bss (rwx) : ORIGIN = 0, LENGTH = 0
+  r1  (rwx) : ORIGIN = 0x1000, LENGTH = 24
+  v1  (rwx) : ORIGIN = 0x2000, LENGTH = 8
+}
+_start = 0x1000;
+SECTIONS {
+  .bss  : { *(.bss)  } > bss
+  .text : { *(.txt) } > r1 AT> v1
+  .data : { *(.dat) } > r1 AT> v1
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over6.d b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over6.d
new file mode 100644
index 0000000..d7088a0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over6.d
@@ -0,0 +1,36 @@
+# name: rgn-over6
+# source: rgn-over.s
+# ld: -T rgn-over6.t -Map tmpdir/rgn-over6.map
+# error: \A[^ \n]*?ld[^:\n]*?: [^\n]*?section \.text will not fit in region r1\n[^ \n]*?ld[^:\n]*?: [^\n]*?section \.text will not fit in region v1\n[^ \n]*?ld[^:\n]*?: region r1 overflowed by 16 bytes\n[^ \n]*?ld[^:\n]*?: region v1 overflowed by 16 bytes\Z
+
+Discarded input sections
+#...
+Memory\s+Configuration
+
+Name\s+Origin\s+Length\s+Attributes
+bss\s+0x0+0000\s+0x0+0000\s+xrw
+r1\s+0x0+1000\s+0x0+0008\s+xrw
+v1\s+0x0+2000\s+0x0+0008\s+xrw
+\*default\*\s+0x0+0000\s+0xf+ffff
+
+Linker\s+script\s+and\s+memory\s+map
+
+\s*0x0+1000\s+_start\s+=\s+0x1000
+
+\s*\.bss\s+0x0+0000\s+0x0
+\s*\*\(\.bss\)
+\s*\.bss\s+0x0+0000\s+0x0\s+.*?
+
+\s*\.text\s+0x0+1000\s+0xc\s+load\s+address\s+0x0+2000
+\s*\*\(\.txt\)
+\s*\.txt\s+0x0+1000\s+0xc\s+.*?
+
+\s*\.data\s+0x0+100c\s+0xc\s+load\s+address\s+0x0+200c
+\s*\*\(\.dat\)
+\s*\.dat\s+0x0+100c\s+0xc\s+.*?
+
+/DISCARD/
+ \*\(\*\)
+LOAD\s+.*?
+OUTPUT\(.*?\)
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over6.t b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over6.t
new file mode 100644
index 0000000..b78d184
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over6.t
@@ -0,0 +1,14 @@
+/* Memory region overflow tests: overflow LMA and VMA.  */
+
+MEMORY {
+  bss (rwx) : ORIGIN = 0, LENGTH = 0
+  r1  (rwx) : ORIGIN = 0x1000, LENGTH = 8
+  v1  (rwx) : ORIGIN = 0x2000, LENGTH = 8
+}
+_start = 0x1000;
+SECTIONS {
+  .bss  : { *(.bss)  } > bss
+  .text : { *(.txt) } > r1 AT> v1
+  .data : { *(.dat) } > r1 AT> v1
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over7.d b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over7.d
new file mode 100644
index 0000000..52442ba
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over7.d
@@ -0,0 +1,36 @@
+# name: rgn-over7
+# source: rgn-over.s
+# ld: -T rgn-over7.t -Map tmpdir/rgn-over7.map
+# error: \A[^ \n]*?ld[^:\n]*?: [^\n]*?section \.text will not fit in region r1\n[^ \n]*?ld[^:\n]*?: section \.data \[0+1008 -> 0+1013\] overlaps section \.text \[0+1000 -> 0+100b\]\n[^ \n]*?ld[^:\n]*?: region r1 overflowed by 4 bytes\Z
+
+Discarded input sections
+#...
+Memory\s+Configuration
+
+Name\s+Origin\s+Length\s+Attributes
+bss\s+0x0+0000\s+0x0+0000\s+xrw
+r1\s+0x0+1000\s+0x0+0008\s+xrw
+r2\s+0x0+1008\s+0x0+000c\s+xrw
+\*default\*\s+0x0+0000\s+0xf+ffff
+
+Linker\s+script\s+and\s+memory\s+map
+
+\s*0x0+1000\s+_start\s+=\s+0x1000
+
+\s*\.bss\s+0x0+0000\s+0x0
+\s*\*\(\.bss\)
+\s*\.bss\s+0x0+0000\s+0x0\s+.*?
+
+\s*\.text\s+0x0+1000\s+0xc
+\s*\*\(\.txt\)
+\s*\.txt\s+0x0+1000\s+0xc\s+.*?
+
+\s*\.data\s+0x0+1008\s+0xc
+\s*\*\(\.dat\)
+\s*\.dat\s+0x0+1008\s+0xc\s+.*?
+
+/DISCARD/
+ \*\(\*\)
+LOAD\s+.*?
+OUTPUT\(.*?\)
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over7.t b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over7.t
new file mode 100644
index 0000000..4288e84
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over7.t
@@ -0,0 +1,14 @@
+/* Memory region overflow tests: overflow r1 plus text/data collision.  */
+
+MEMORY {
+  bss (rwx) : ORIGIN = 0, LENGTH = 0
+  r1  (rwx) : ORIGIN = 0x1000, LENGTH = 8
+  r2  (rwx) : ORIGIN = 0x1008, LENGTH = 12
+}
+_start = 0x1000;
+SECTIONS {
+  .bss  : { *(.bss)  } > bss
+  .text : { *(.txt) } > r1
+  .data : { *(.dat) } > r2
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over8-ok.d b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over8-ok.d
new file mode 100644
index 0000000..657b15c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over8-ok.d
@@ -0,0 +1,12 @@
+# name: rgn-over8
+# source: rgn-over8.s
+# ld: -T rgn-over8.t
+# objdump: -w -h
+
+.*:     file format .*
+
+Sections:
+Idx +Name +Size +VMA +LMA +File off +Algn +Flags
+  0 .text         0+0000400  0+0000000  0+0000000  [0-9a-f]+  2\*\*[0-9]+  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .data         0+0000400  0+0001000  0+0000400  [0-9a-f]+  2\*\*[0-9]+  CONTENTS, ALLOC, LOAD, DATA
+  2 .bss          0+0000400  0+0001400  0+0000800  [0-9a-f]+  2\*\*[0-9]+  ALLOC
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over8.s b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over8.s
new file mode 100644
index 0000000..0077a4f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over8.s
@@ -0,0 +1,7 @@
+	.text
+	.globl main
+	.zero 1024
+	.data
+	.zero 1024
+	.section .bss, "aw", "nobits"
+	.zero 1024
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/rgn-over8.t b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over8.t
new file mode 100644
index 0000000..7623b19
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/rgn-over8.t
@@ -0,0 +1,13 @@
+/* Memory region overflow tests: bss to LMA doesn't cause overflow.  */
+
+MEMORY {
+  rom (rwx) : ORIGIN = 0, LENGTH = 2048
+  ram (rwx) : ORIGIN = 0x1000, LENGTH = 2048
+}
+_start = 0x0;
+SECTIONS {
+  .text : { *(.text) } >rom AT>rom
+  .data : { *(.data) } >ram AT>rom
+  .bss : { *(.bss) } >ram AT>rom
+  /DISCARD/ : { *(*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/script.exp b/binutils-2.19/ld/testsuite/ld-scripts/script.exp
new file mode 100644
index 0000000..62c98be
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/script.exp
@@ -0,0 +1,128 @@
+# Test basic linker script functionality
+# By Ian Lance Taylor, Cygnus Support
+#   Copyright 1999, 2000, 2001, 2002, 2004, 2006, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+set testname "script"
+
+if ![ld_assemble $as $srcdir/$subdir/script.s tmpdir/script.o] { 
+    unresolved $testname
+    return
+}
+
+proc check_script { } {
+    global nm
+    global testname
+    global nm_output
+
+    if ![ld_nm $nm "" tmpdir/script] {
+	unresolved $testname
+	return
+    } 
+
+    if {![info exists nm_output(text_start)] \
+	    || ![info exists nm_output(text_end)] \
+	    || ![info exists nm_output(data_start)] \
+	    || ![info exists nm_output(data_end)]} {
+	send_log "bad output from nm\n"
+	verbose "bad output from nm"
+	fail $testname
+	return
+    } 
+
+    set passes 1
+    set text_end 0x104
+    set data_end 0x1004
+
+    if [istarget *c4x*-*-*] then {
+	set text_end 0x101
+	set data_end 0x1001
+    }
+
+    if [istarget *c54x*-*-*] then {
+	set text_end 0x102
+	set data_end 0x1002
+    }
+
+    if {$nm_output(text_start) != 0x100} {
+	send_log "text_start == $nm_output(text_start)\n"
+	verbose "text_start == $nm_output(text_start)"
+	set passes 0
+    } 
+
+    if {$nm_output(text_end) < $text_end \
+	    || $nm_output(text_end) > 0x110} {
+	send_log "text_end == $nm_output(text_end)\n"
+	verbose "text_end == $nm_output(text_end)"
+	set passes 0
+    } 
+
+    if {$nm_output(data_start) != 0x1000} {
+	send_log "data_start == $nm_output(data_start)\n"
+	verbose "data_start == $nm_output(data_start)"
+	set passes 0
+    } 
+
+    if {$nm_output(data_end) < $data_end \
+	    || $nm_output(data_end) > 0x1010} {
+	send_log "data_end == $nm_output(data_end)\n"
+	verbose "data_end == $nm_output(data_end)"
+	set passes 0
+    } 
+
+    if { $passes } {
+	pass $testname
+    } else {
+	fail $testname
+    }
+}
+
+# PE targets need to set the image base to 0 to avoid complications from nm.
+set flags ""
+if {[istarget "*-*-pe*"] \
+    || [istarget "*-*-cygwin*"] \
+    || [istarget "*-*-mingw*"] \
+    || [istarget "*-*-winnt*"] \
+    || [istarget "*-*-nt"] \
+    || [istarget "*-*-interix*"] } then {
+  set flags "--image-base 0"
+}
+
+if ![ld_simple_link $ld tmpdir/script "$flags -T $srcdir/$subdir/script.t tmpdir/script.o"] {
+    fail $testname
+} else {
+    check_script
+}
+
+set testname "MRI script"
+
+if ![ld_simple_link $ld tmpdir/script "$flags -c $srcdir/$subdir/scriptm.t"] {
+    fail $testname
+} else {
+    check_script
+}
+
+set testname "MEMORY"
+
+if ![ld_simple_link $ld tmpdir/script "$flags -T $srcdir/$subdir/memory.t tmpdir/script.o"] {
+    fail $testname
+} else {
+    check_script
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/script.s b/binutils-2.19/ld/testsuite/ld-scripts/script.s
new file mode 100644
index 0000000..d7b65b0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/script.s
@@ -0,0 +1,8 @@
+	.text
+	.globl text_symbol
+text_symbol:	
+	.long	1
+	.data
+	.globl data_symbol
+data_symbol:	
+	.long	2
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/script.t b/binutils-2.19/ld/testsuite/ld-scripts/script.t
new file mode 100644
index 0000000..ee7a48a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/script.t
@@ -0,0 +1,16 @@
+SECTIONS
+{
+  .text 0x100 : { 
+    text_start = .;
+    *(.text)
+    *(.pr)
+    text_end = .;
+  }
+  . = 0x1000;
+  .data : {
+    data_start = .;
+    *(.data)
+    *(.rw)
+    data_end = .;
+  }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/scriptm.t b/binutils-2.19/ld/testsuite/ld-scripts/scriptm.t
new file mode 100644
index 0000000..57ccae1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/scriptm.t
@@ -0,0 +1,10 @@
+* MRI script
+sect .text = $100	; .text start address
+sect .data = 1000h	; .data start address
+public text_start = $100
+public text_end = # continuation line
+  text_start + 4
+public data_start = 1000h
+public data_end = data_start + 4
+
+load tmpdir/script.o
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/size-1.d b/binutils-2.19/ld/testsuite/ld-scripts/size-1.d
new file mode 100644
index 0000000..641fbca
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/size-1.d
@@ -0,0 +1,14 @@
+#source: size-1.s
+#ld: -T size-1.t
+#objdump: -s
+
+.*:     file format .*
+
+#...
+Contents of section \.text:
+ [0-9a-f]* (01)?000000(01)? (02)?000000(02)? .*
+#...
+Contents of section \.data:
+ [0-9a-f]* (03)?000000(03)? (04)?000000(04)? (05)?000000(05)? 00000000 .*
+ [0-9a-f]* (20)?000000(20)? (18)?000000(18)? .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/size-1.s b/binutils-2.19/ld/testsuite/ld-scripts/size-1.s
new file mode 100644
index 0000000..7f5a5fd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/size-1.s
@@ -0,0 +1,7 @@
+	.text
+	.long 1,2
+	.p2align 5
+
+	.data
+	.long 3,4,5
+	.p2align 4
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/size-1.t b/binutils-2.19/ld/testsuite/ld-scripts/size-1.t
new file mode 100644
index 0000000..bb48665
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/size-1.t
@@ -0,0 +1,10 @@
+SECTIONS
+{
+  . = 0x1000 + SIZEOF_HEADERS;
+  .text ALIGN (0x20) : { *(.text) }
+  .data 0x2000 : {
+    *(.data)
+    LONG (SIZEOF (.text))
+    LONG (SIZEOF (.data))
+  }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/size-2.d b/binutils-2.19/ld/testsuite/ld-scripts/size-2.d
new file mode 100644
index 0000000..beb18e4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/size-2.d
@@ -0,0 +1,18 @@
+#source: size-2.s
+#ld: -T size-2.t
+#readelf: -l --wide
+#xfail: "hppa64-*-*" "v850-*-*"
+
+#...
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg +Align
+ +PHDR +0x[0-9a-f]+ 0x0+0000 0x0+0000 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x[0-9a-f]+
+#...
+ +LOAD +0x[0-9a-f]+ 0x0+0100 0x0+0100 0x0+0030 0x0+0030 R E +0x[0-9a-f]+
+ +TLS +0x[0-9a-f]+ 0x0+0108 0x0+0108 0x0+0014 0x0+002c R +0x[0-9a-f]+
+
+ Section to Segment mapping:
+ +Segment Sections\.\.\.
+ +00 .*
+ +01.*\.text.*\.tdata.*
+ +02.*\.tdata.*
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/size-2.s b/binutils-2.19/ld/testsuite/ld-scripts/size-2.s
new file mode 100644
index 0000000..6b10250
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/size-2.s
@@ -0,0 +1,8 @@
+	.text
+	.long 1,2
+
+	.section .tdata
+	.long 6,7,8,9,10
+	
+	.section .tbss
+	.long 0,0,0,0,0,0
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/size-2.t b/binutils-2.19/ld/testsuite/ld-scripts/size-2.t
new file mode 100644
index 0000000..e67b3fa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/size-2.t
@@ -0,0 +1,21 @@
+PHDRS
+{
+  header PT_PHDR FILEHDR PHDRS ;
+	 
+  image PT_LOAD FLAGS (5);
+  tls PT_TLS FLAGS (4);
+  
+}
+SECTIONS
+{
+  .text 0x100 : { *(.text) } :image
+  .tdata : { *(.tdata) } :image :tls
+  .tbss : { *(.tbss) } :image : tls
+  .map : {
+    LONG (SIZEOF (.text))
+    LONG (SIZEOF (.data))
+    LONG (SIZEOF (.bss))
+    LONG (SIZEOF (.tdata))
+    LONG (SIZEOF (.tbss))
+  } :image
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/size.exp b/binutils-2.19/ld/testsuite/ld-scripts/size.exp
new file mode 100644
index 0000000..fc90dc1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/size.exp
@@ -0,0 +1,41 @@
+# Expect script for SIZEOF tests
+#   Copyright (C) 2004, 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# AIX maps .text and .data to other sections.
+# a.out objdump displays the file header inside the text segment,
+# confusing run_dump_test.
+
+if {[istarget "rs6000-*-aix*"] || [is_aout_format]} {
+    unsupported size-1
+    unsupported size-2
+    return
+}
+
+run_dump_test size-1
+
+# size-2 only works on ELF targets.
+# MIPS inserts a REGINFO PHDR
+if {![is_elf_format] || [istarget "mips*-*-*"]} {
+    unsupported size-2
+    return
+}
+
+run_dump_test size-2
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sizeof.exp b/binutils-2.19/ld/testsuite/ld-scripts/sizeof.exp
new file mode 100644
index 0000000..b9664ee
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sizeof.exp
@@ -0,0 +1,74 @@
+# Test SIZEOF in a linker script.
+# By Ian Lance Taylor, Cygnus Support
+# Based on a bug report from anders.blomdell@control.lth.se.
+#   Copyright 2001, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+set testname "SIZEOF"
+
+if ![ld_assemble $as $srcdir/$subdir/sizeof.s tmpdir/sizeof.o] {
+    unresolved $testname
+    return
+}
+
+if ![ld_simple_link $ld tmpdir/sizeof "-T $srcdir/$subdir/sizeof.t tmpdir/sizeof.o"] {
+    fail $testname
+    return
+}
+
+if ![ld_nm $nm "" tmpdir/sizeof] {
+    unresolved $testname
+    return
+}
+
+if {![info exists nm_output(text_start)] \
+     || ![info exists nm_output(text_end)] \
+     || ![info exists nm_output(data_start)] \
+     || ![info exists nm_output(data_end)] \
+     || ![info exists nm_output(sizeof_text)] \
+     || ![info exists nm_output(sizeof_data)]} {
+    send_log "bad output from nm\n"
+    verbose "bad output from nm"
+    fail $testname
+    return
+}
+
+if {$nm_output(text_end) - $nm_output(text_start) != $nm_output(sizeof_text)} {
+    send_log "text_end - text_start != sizeof_text\n"
+    verbose "text_end - text_start != sizeof_text"
+    fail $testname
+    return
+}
+
+if {$nm_output(data_end) - $nm_output(data_start) != $nm_output(sizeof_data)} {
+    send_log "data_end - data_start != sizeof_data\n"
+    verbose "data_end - data_start != sizeof_data"
+    fail $testname
+    return
+}
+
+if {$nm_output(sizeof_text) != $nm_output(sizeof_data)} {
+    send_log "sizeof_text != sizeof_data\n"
+    verbose "sizeof_text != sizeof_data"
+    fail $testname
+    return
+}
+
+pass $testname
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sizeof.s b/binutils-2.19/ld/testsuite/ld-scripts/sizeof.s
new file mode 100644
index 0000000..e221ca3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sizeof.s
@@ -0,0 +1 @@
+	.space	16
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sizeof.t b/binutils-2.19/ld/testsuite/ld-scripts/sizeof.t
new file mode 100644
index 0000000..6244a37
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sizeof.t
@@ -0,0 +1,17 @@
+SECTIONS {
+	.text :
+	  {
+	    text_start = .;
+	    tmpdir/sizeof.o 
+	    text_end = .;
+	  }
+	.data : 
+	  { 
+	    data_start = .;
+	    . = . + SIZEOF(.text);
+	    data_end = .;
+	  }
+}	
+
+sizeof_text = SIZEOF(.text);
+sizeof_data = SIZEOF(.data);
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort.exp b/binutils-2.19/ld/testsuite/ld-scripts/sort.exp
new file mode 100644
index 0000000..0563bfc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort.exp
@@ -0,0 +1,34 @@
+# Test SORT_BY_NAME/SORT_BY_ALIGNMENT/SORT in a linker script.
+# By H.J. Lu  <hongjiu.lu@intel.com>
+#   Copyright 2004, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# FIXME: The expected outputs are correct only for ELF.
+if ![is_elf_format] {
+    return
+}
+
+load_lib ld-lib.exp
+
+set sort_test_list [lsort [glob -nocomplain $srcdir/$subdir/sort*.d]]
+for { set i 0 } { $i < [llength $sort_test_list] } { incr i } {
+    verbose [file rootname [lindex $sort_test_list $i]]
+    run_dump_test [file rootname [lindex $sort_test_list $i]]
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort.t b/binutils-2.19/ld/testsuite/ld-scripts/sort.t
new file mode 100644
index 0000000..c53481f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort.t
@@ -0,0 +1,5 @@
+SECTIONS
+{
+  .text : {*(.text .text.*)}
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a-1.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a-1.d
new file mode 100644
index 0000000..eaa917d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a-1.d
@@ -0,0 +1,9 @@
+#source: sort_b_a-1.s
+#ld: -T sort.t --sort-section alignment
+#name: --sort-section alignment
+#nm: -n
+
+0[0-9a-f]* t text3
+0[0-9a-f]* t text1
+0[0-9a-f]* t text
+0[0-9a-f]* t text2
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a-1.s b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a-1.s
new file mode 100644
index 0000000..87d3613
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a-1.s
@@ -0,0 +1,16 @@
+	.section .text.2
+	.p2align 3
+text2:
+	.long 0
+	.section .text.3
+	.p2align 6
+text3:
+	.long 0
+	.section .text.1
+	.p2align 5
+text1:
+	.long 0
+	.text
+text:
+	.p2align 4
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a.d
new file mode 100644
index 0000000..78fe1f1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a.d
@@ -0,0 +1,9 @@
+#source: sort_b_a.s
+#ld: -T sort_b_a.t
+#name: SORT_BY_ALIGNMENT
+#nm: -n
+
+0[0-9a-f]* t text3
+0[0-9a-f]* t text1
+0[0-9a-f]* t text
+0[0-9a-f]* t text2
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a.s b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a.s
new file mode 100644
index 0000000..7b3851f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a.s
@@ -0,0 +1,16 @@
+	.section .text2
+	.p2align 3
+text2:
+	.long 0
+	.section .text3
+	.p2align 6
+text3:
+	.long 0
+	.section .text1
+	.p2align 5
+text1:
+	.long 0
+	.text
+text:
+	.p2align 4
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a.t b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a.t
new file mode 100644
index 0000000..cbfd3c3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a.t
@@ -0,0 +1,5 @@
+SECTIONS
+{
+  .text : {*(SORT_BY_ALIGNMENT(.text*))}
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_a-1.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_a-1.d
new file mode 100644
index 0000000..4f70646
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_a-1.d
@@ -0,0 +1,14 @@
+#source: sort_n_a-a.s
+#source: sort_n_a-b.s
+#ld: -T sort_b_a_a.t
+#name: SORT_BY_ALIGNMENT(SORT_BY_ALIGNMENT())
+#nm: -n
+
+0[0-9a-f]* t text3b
+0[0-9a-f]* t text3a
+0[0-9a-f]* t text1a
+0[0-9a-f]* t text1b
+0[0-9a-f]* t texta
+0[0-9a-f]* t textb
+0[0-9a-f]* t text2a
+0[0-9a-f]* t text2b
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_a-2.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_a-2.d
new file mode 100644
index 0000000..65919a4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_a-2.d
@@ -0,0 +1,14 @@
+#source: sort_n_a-a.s
+#source: sort_n_a-b.s
+#ld: -T sort_b_a_a.t --sort-section alignment
+#name: SORT_BY_ALIGNMENT(SORT_BY_ALIGNMENT()) --sort-section alignment
+#nm: -n
+
+0[0-9a-f]* t text3b
+0[0-9a-f]* t text3a
+0[0-9a-f]* t text1a
+0[0-9a-f]* t text1b
+0[0-9a-f]* t texta
+0[0-9a-f]* t textb
+0[0-9a-f]* t text2a
+0[0-9a-f]* t text2b
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_a-3.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_a-3.d
new file mode 100644
index 0000000..21b7732
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_a-3.d
@@ -0,0 +1,14 @@
+#source: sort_n_a-a.s
+#source: sort_n_a-b.s
+#ld: -T sort_b_a_a.t --sort-section name
+#name: SORT_BY_ALIGNMENT(SORT_BY_ALIGNMENT()) --sort-section name
+#nm: -n
+
+0[0-9a-f]* t text3b
+0[0-9a-f]* t text1a
+0[0-9a-f]* t text1b
+0[0-9a-f]* t text3a
+0[0-9a-f]* t texta
+0[0-9a-f]* t textb
+0[0-9a-f]* t text2a
+0[0-9a-f]* t text2b
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_a.t b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_a.t
new file mode 100644
index 0000000..359cdff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_a.t
@@ -0,0 +1,5 @@
+SECTIONS
+{
+  .text : {*(SORT_BY_ALIGNMENT(SORT_BY_ALIGNMENT(.text*)))}
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_n-1.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_n-1.d
new file mode 100644
index 0000000..62363bc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_n-1.d
@@ -0,0 +1,14 @@
+#source: sort_n_a-a.s
+#source: sort_n_a-b.s
+#ld: -T sort_b_a_n.t
+#name: SORT_BY_ALIGNMENT(SORT_BY_NAME())
+#nm: -n
+
+0[0-9a-f]* t text3b
+0[0-9a-f]* t text1a
+0[0-9a-f]* t text1b
+0[0-9a-f]* t text3a
+0[0-9a-f]* t texta
+0[0-9a-f]* t textb
+0[0-9a-f]* t text2a
+0[0-9a-f]* t text2b
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_n-2.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_n-2.d
new file mode 100644
index 0000000..7402836
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_n-2.d
@@ -0,0 +1,14 @@
+#source: sort_n_a-a.s
+#source: sort_n_a-b.s
+#ld: -T sort_b_a_n.t --sort-section name
+#name: SORT_BY_ALIGNMENT(SORT_BY_NAME()) --sort-section name
+#nm: -n
+
+0[0-9a-f]* t text3b
+0[0-9a-f]* t text1a
+0[0-9a-f]* t text1b
+0[0-9a-f]* t text3a
+0[0-9a-f]* t texta
+0[0-9a-f]* t textb
+0[0-9a-f]* t text2a
+0[0-9a-f]* t text2b
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_n-3.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_n-3.d
new file mode 100644
index 0000000..4421c77
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_n-3.d
@@ -0,0 +1,14 @@
+#source: sort_n_a-a.s
+#source: sort_n_a-b.s
+#ld: -T sort_b_a_n.t --sort-section alignment
+#name: SORT_BY_ALIGNMENT(SORT_BY_NAME()) --sort-section alignment
+#nm: -n
+
+0[0-9a-f]* t text3b
+0[0-9a-f]* t text1a
+0[0-9a-f]* t text1b
+0[0-9a-f]* t text3a
+0[0-9a-f]* t texta
+0[0-9a-f]* t textb
+0[0-9a-f]* t text2a
+0[0-9a-f]* t text2b
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_n.t b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_n.t
new file mode 100644
index 0000000..04c3917
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_a_n.t
@@ -0,0 +1,5 @@
+SECTIONS
+{
+  .text : {*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.text*)))}
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n-1.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n-1.d
new file mode 100644
index 0000000..42bdcf9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n-1.d
@@ -0,0 +1,9 @@
+#source: sort_b_n-1.s
+#ld: -T sort.t --sort-section name
+#name: --sort-section name
+#nm: -n
+
+0[0-9a-f]* t text
+0[0-9a-f]* t text1
+0[0-9a-f]* t text2
+0[0-9a-f]* t text3
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n-1.s b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n-1.s
new file mode 100644
index 0000000..5a49170
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n-1.s
@@ -0,0 +1,12 @@
+	.section .text.2
+text2:
+	.long 0
+	.section .text.3
+text3:
+	.long 0
+	.section .text.1
+text1:
+	.long 0
+	.text
+text:
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n.d
new file mode 100644
index 0000000..531a756
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n.d
@@ -0,0 +1,9 @@
+#source: sort_b_n.s
+#ld: -T sort_b_n.t
+#name: SORT_BY_NAME
+#nm: -n
+
+0[0-9a-f]* t text
+0[0-9a-f]* t text1
+0[0-9a-f]* t text2
+0[0-9a-f]* t text3
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n.s b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n.s
new file mode 100644
index 0000000..c99d75c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n.s
@@ -0,0 +1,12 @@
+	.section .text2
+text2:
+	.long 0
+	.section .text3
+text3:
+	.long 0
+	.section .text1
+text1:
+	.long 0
+	.text
+text:
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n.t b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n.t
new file mode 100644
index 0000000..26c2b6e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n.t
@@ -0,0 +1,5 @@
+SECTIONS
+{
+  .text : {*(SORT_BY_NAME(.text*))}
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_a-1.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_a-1.d
new file mode 100644
index 0000000..ee123bf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_a-1.d
@@ -0,0 +1,14 @@
+#source: sort_n_a-a.s
+#source: sort_n_a-b.s
+#ld: -T sort_b_n_a.t
+#name: SORT_BY_NAME(SORT_BY_ALIGNMENT())
+#nm: -n
+
+0[0-9a-f]* t texta
+0[0-9a-f]* t textb
+0[0-9a-f]* t text1a
+0[0-9a-f]* t text1b
+0[0-9a-f]* t text2a
+0[0-9a-f]* t text2b
+0[0-9a-f]* t text3b
+0[0-9a-f]* t text3a
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_a-2.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_a-2.d
new file mode 100644
index 0000000..82f1805
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_a-2.d
@@ -0,0 +1,14 @@
+#source: sort_n_a-a.s
+#source: sort_n_a-b.s
+#ld: -T sort_b_n_a.t --sort-section name
+#name: SORT_BY_NAME(SORT_BY_ALIGNMENT()) --sort-section alignment
+#nm: -n
+
+0[0-9a-f]* t texta
+0[0-9a-f]* t textb
+0[0-9a-f]* t text1a
+0[0-9a-f]* t text1b
+0[0-9a-f]* t text2a
+0[0-9a-f]* t text2b
+0[0-9a-f]* t text3b
+0[0-9a-f]* t text3a
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_a-3.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_a-3.d
new file mode 100644
index 0000000..5f3c863
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_a-3.d
@@ -0,0 +1,14 @@
+#source: sort_n_a-a.s
+#source: sort_n_a-b.s
+#ld: -T sort_b_n_a.t --sort-section alignment
+#name: SORT_BY_NAME(SORT_BY_ALIGNMENT()) --sort-section alignment
+#nm: -n
+
+0[0-9a-f]* t texta
+0[0-9a-f]* t textb
+0[0-9a-f]* t text1a
+0[0-9a-f]* t text1b
+0[0-9a-f]* t text2a
+0[0-9a-f]* t text2b
+0[0-9a-f]* t text3b
+0[0-9a-f]* t text3a
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_a.t b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_a.t
new file mode 100644
index 0000000..49cbdd3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_a.t
@@ -0,0 +1,5 @@
+SECTIONS
+{
+  .text : {*(SORT_BY_NAME(SORT_BY_ALIGNMENT(.text*)))}
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_n-1.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_n-1.d
new file mode 100644
index 0000000..0bc18ae
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_n-1.d
@@ -0,0 +1,14 @@
+#source: sort_n_a-a.s
+#source: sort_n_a-b.s
+#ld: -T sort_b_n_n.t
+#name: SORT_BY_NAME(SORT_BY_NAME())
+#nm: -n
+
+0[0-9a-f]* t texta
+0[0-9a-f]* t textb
+0[0-9a-f]* t text1a
+0[0-9a-f]* t text1b
+0[0-9a-f]* t text2a
+0[0-9a-f]* t text2b
+0[0-9a-f]* t text3a
+0[0-9a-f]* t text3b
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_n-2.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_n-2.d
new file mode 100644
index 0000000..834bf90
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_n-2.d
@@ -0,0 +1,14 @@
+#source: sort_n_a-a.s
+#source: sort_n_a-b.s
+#ld: -T sort_b_n_n.t --sort-section name
+#name: SORT_BY_NAME(SORT_BY_NAME()) --sort-section name
+#nm: -n
+
+0[0-9a-f]* t texta
+0[0-9a-f]* t textb
+0[0-9a-f]* t text1a
+0[0-9a-f]* t text1b
+0[0-9a-f]* t text2a
+0[0-9a-f]* t text2b
+0[0-9a-f]* t text3a
+0[0-9a-f]* t text3b
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_n-3.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_n-3.d
new file mode 100644
index 0000000..7ba8a8b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_n-3.d
@@ -0,0 +1,14 @@
+#source: sort_n_a-a.s
+#source: sort_n_a-b.s
+#ld: -T sort_b_n_n.t --sort-section alignment
+#name: SORT_BY_NAME(SORT_BY_NAME()) --sort-section alignment
+#nm: -n
+
+0[0-9a-f]* t texta
+0[0-9a-f]* t textb
+0[0-9a-f]* t text1a
+0[0-9a-f]* t text1b
+0[0-9a-f]* t text2a
+0[0-9a-f]* t text2b
+0[0-9a-f]* t text3b
+0[0-9a-f]* t text3a
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_n.t b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_n.t
new file mode 100644
index 0000000..b4eabfe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_b_n_n.t
@@ -0,0 +1,5 @@
+SECTIONS
+{
+  .text : {*(SORT_BY_NAME(SORT_BY_NAME(.text*)))}
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_n_a-a.s b/binutils-2.19/ld/testsuite/ld-scripts/sort_n_a-a.s
new file mode 100644
index 0000000..77dfc35
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_n_a-a.s
@@ -0,0 +1,16 @@
+	.section .text2
+	.p2align 3
+text2a:
+	.long 0
+	.section .text3
+	.p2align 5
+text3a:
+	.long 0
+	.section .text1
+	.p2align 5
+text1a:
+	.long 0
+	.text
+texta:
+	.p2align 4
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_n_a-b.s b/binutils-2.19/ld/testsuite/ld-scripts/sort_n_a-b.s
new file mode 100644
index 0000000..781ba4e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_n_a-b.s
@@ -0,0 +1,16 @@
+	.section .text2
+	.p2align 3
+text2b:
+	.long 0
+	.section .text3
+	.p2align 6
+text3b:
+	.long 0
+	.section .text1
+	.p2align 5
+text1b:
+	.long 0
+	.text
+textb:
+	.p2align 4
+	.long 0
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_no-1.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_no-1.d
new file mode 100644
index 0000000..aef7863
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_no-1.d
@@ -0,0 +1,9 @@
+#source: sort_b_n.s
+#ld: -T sort_no.t
+#name: no SORT_BY_NAME/SORT_BY_ALIGNMENT/SORT
+#nm: -n
+
+0[0-9a-f]* t text
+0[0-9a-f]* t text2
+0[0-9a-f]* t text3
+0[0-9a-f]* t text1
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_no-2.d b/binutils-2.19/ld/testsuite/ld-scripts/sort_no-2.d
new file mode 100644
index 0000000..ddcd1c1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_no-2.d
@@ -0,0 +1,9 @@
+#source: sort_b_a.s
+#ld: -T sort_no.t
+#name: no SORT_BY_NAME/SORT_BY_ALIGNMENT/SORT
+#nm: -n
+
+0[0-9a-f]* t text
+0[0-9a-f]* t text2
+0[0-9a-f]* t text3
+0[0-9a-f]* t text1
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/sort_no.t b/binutils-2.19/ld/testsuite/ld-scripts/sort_no.t
new file mode 100644
index 0000000..d797c79
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/sort_no.t
@@ -0,0 +1,5 @@
+SECTIONS
+{
+  .text : {*(.text*)}
+  /DISCARD/ : { *(.*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/weak.exp b/binutils-2.19/ld/testsuite/ld-scripts/weak.exp
new file mode 100644
index 0000000..5b5c00c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/weak.exp
@@ -0,0 +1,81 @@
+# Test weak symbols.
+# By Ian Lance Taylor, Cygnus Solutions.
+#   Copyright 1999, 2000, 2002, 2004, 2006, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+set testname "weak symbols"
+
+# This test only works for ELF targets.
+# It ought to work for some a.out targets, but it doesn't.
+if {! [is_elf_format] && ! [is_pecoff_format]} {
+    unsupported $testname
+    return
+}
+
+# Weak symbols are broken for non-i386 PE targets.
+if {! [istarget i?86-*-*]} {
+    setup_xfail *-*-pe*
+    setup_xfail x86_64-*-mingw*
+}
+
+# hppa64 and or32 are incredibly broken
+setup_xfail hppa64-*-* or32-*-*
+
+if {! [ld_assemble $as $srcdir/$subdir/weak1.s tmpdir/weak1.o]
+    || ! [ld_assemble $as $srcdir/$subdir/weak2.s tmpdir/weak2.o]} then {
+    # It's OK if .weak doesn't work on this target.
+    unresolved $testname
+    return
+}
+
+global LDFLAGS
+set saved_LDFLAGS "$LDFLAGS"
+if [istarget "x86_64-*-mingw*"] then {
+  set LDFLAGS "$LDFLAGS --image-base 0"
+}
+
+set weak_regexp_big \
+".*Contents of section .text:.*1000 00001008 0000200c 12121212 34343434.*Contents of section .data:.*2000 00001008 0000200c 56565656 78787878.*"
+
+set weak_regexp_little \
+".*Contents of section .text:.*1000 08100000 0c200000 12121212 34343434.*Contents of section .data:.*2000 08100000 0c200000 56565656 78787878.*"
+
+if {! [ld_simple_link $ld tmpdir/weak "$flags -T $srcdir/$subdir/weak.t tmpdir/weak1.o tmpdir/weak2.o"] } then {
+    fail $testname
+} else {
+    if {![is_remote host] && [which $objdump] == 0} then {
+	unresolved $testname
+	set LDFLAGS "$saved_LDFLAGS"
+	return
+    }
+
+    set exec_output [run_host_cmd "$objdump" "-s tmpdir/weak"]
+    set exec_output [prune_warnings $exec_output]
+    verbose -log $exec_output
+
+    if {[regexp $weak_regexp_big $exec_output] \
+	|| [regexp $weak_regexp_little $exec_output] } then {
+	pass $testname
+    } else {
+	fail $testname
+    }
+}
+
+set LDFLAGS "$saved_LDFLAGS"
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/weak.t b/binutils-2.19/ld/testsuite/ld-scripts/weak.t
new file mode 100644
index 0000000..6cd013e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/weak.t
@@ -0,0 +1,12 @@
+SECTIONS
+{
+  .text 0x1000 : {
+    tmpdir/weak1.o(.data)
+  }
+  .data 0x2000 : {
+    tmpdir/weak2.o(.data)
+  }
+  /DISCARD/ : {
+    *(*)
+  }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/weak1.s b/binutils-2.19/ld/testsuite/ld-scripts/weak1.s
new file mode 100644
index 0000000..26bffbd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/weak1.s
@@ -0,0 +1,11 @@
+	.data
+	.global	foo1
+	.global	sym1
+	.weak	sym2
+foo1:
+	.long	sym1
+	.long	sym2
+sym1:
+	.long	0x12121212
+sym2:
+	.long	0x34343434
diff --git a/binutils-2.19/ld/testsuite/ld-scripts/weak2.s b/binutils-2.19/ld/testsuite/ld-scripts/weak2.s
new file mode 100644
index 0000000..963b229
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-scripts/weak2.s
@@ -0,0 +1,11 @@
+	.data
+	.global	foo2
+	.weak	sym1
+	.global	sym2
+foo2:
+	.long	sym1
+	.long	sym2
+sym1:
+	.long	0x56565656
+sym2:
+	.long	0x78787878
diff --git a/binutils-2.19/ld/testsuite/ld-selective/1.c b/binutils-2.19/ld/testsuite/ld-selective/1.c
new file mode 100644
index 0000000..1202367
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-selective/1.c
@@ -0,0 +1,12 @@
+/* _start should be the only thing left after GC.  */
+
+void _start() __asm__("_start");
+void _start()
+{
+}
+
+void dropme1()
+{
+}
+
+int dropme2[102] = { 0 };
diff --git a/binutils-2.19/ld/testsuite/ld-selective/2.c b/binutils-2.19/ld/testsuite/ld-selective/2.c
new file mode 100644
index 0000000..7295887
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-selective/2.c
@@ -0,0 +1,19 @@
+/* Normally we should loose foo and keep _start and _init. 
+   With -u foo, we should keep that as well.  */
+
+void _start() __asm__("_start");
+void _start()
+{
+}
+
+void __attribute__((section(".init")))
+_init()
+{
+}
+
+int foo() __asm__("foo");
+int foo()
+{
+  static int x = 1;
+  return x++;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-selective/3.cc b/binutils-2.19/ld/testsuite/ld-selective/3.cc
new file mode 100644
index 0000000..c40bf35
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-selective/3.cc
@@ -0,0 +1,46 @@
+struct A
+{
+  virtual void foo();
+  virtual void bar();
+};
+
+void A::foo() { }			// keep
+void A::bar() { }			// lose
+
+struct B : public A
+{
+  virtual void foo();
+};
+
+void B::foo() { }			// keep
+
+void _start() __asm__("_start"); // keep
+void start() __asm__("start"); // some toolchains use this name.
+
+A a;					// keep
+B b;
+A *getme() { return &a; }		// keep
+
+void _start()
+{
+  getme()->foo();
+#ifdef __GNUC__
+#if (__GNUC__ == 2 && __GNUC_MINOR__ < 96)
+// gcc-2.95.2 gets this test wrong, and loses B::foo().
+// Cheat.  After all, we aren't trying to test the compiler here.
+  b.foo();
+#endif
+#endif
+}
+
+void start ()
+{
+  _start ();
+}
+
+// In addition, keep A's virtual table.
+
+// We'll wind up keeping `b' and thus B's virtual table because
+// `a' and `b' are both referenced from the constructor function.
+
+extern "C" void __main() { }
diff --git a/binutils-2.19/ld/testsuite/ld-selective/4.cc b/binutils-2.19/ld/testsuite/ld-selective/4.cc
new file mode 100644
index 0000000..f4fc21c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-selective/4.cc
@@ -0,0 +1,34 @@
+struct A
+{
+  virtual void foo();
+  virtual void bar();
+};
+
+void A::foo() { }			// lose
+void A::bar() { }			// keep
+
+struct B : public A
+{
+  virtual void foo();
+};
+
+void B::foo() { }			// lose
+
+void _start() __asm__("_start");	// keep
+void start() __asm__("start"); // some toolchains use this name.
+
+A a;					// keep
+B b;
+A *getme() { return &a; }		// keep
+
+void _start()
+{
+  getme()->bar();
+}
+
+void start ()
+{
+  _start ();
+}
+
+extern "C" void __main() { }
diff --git a/binutils-2.19/ld/testsuite/ld-selective/5.cc b/binutils-2.19/ld/testsuite/ld-selective/5.cc
new file mode 100644
index 0000000..2c974d9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-selective/5.cc
@@ -0,0 +1,38 @@
+struct A
+{
+  virtual void foo();
+  virtual void bar();
+};
+
+void A::foo() { }			// lose
+void A::bar() { }			// keep
+
+struct B : public A
+{
+  virtual void foo();
+};
+
+void B::foo() { }			// lose
+
+void _start() __asm__("_start");	// keep
+void start() __asm__("start"); // some toolchains use this name.
+
+A a;					// keep
+B b;
+A *getme() { return &a; }		// keep
+
+extern B* dropme2();
+void dropme1() { dropme2()->foo(); }	// lose
+B *dropme2() { return &b; }		// lose
+
+void _start()
+{
+  getme()->bar();
+}
+
+void start ()
+{
+  _start ();
+}
+
+extern "C" void __main() { }
diff --git a/binutils-2.19/ld/testsuite/ld-selective/keepdot.d b/binutils-2.19/ld/testsuite/ld-selective/keepdot.d
new file mode 100644
index 0000000..aadd5d4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-selective/keepdot.d
@@ -0,0 +1,9 @@
+#ld: --gc-sections -Bstatic -e _start -T keepdot.ld
+#name: Preserve default . = 0
+#objdump: -h
+
+# Check that GC:ing does not mess up the default value for dot.
+
+#...
+[ 	]+.[ 	]+\.myinit[ 	]+0+[48][ 	]+0+[ 	]+0+ .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-selective/keepdot.ld b/binutils-2.19/ld/testsuite/ld-selective/keepdot.ld
new file mode 100644
index 0000000..d8a2b38
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-selective/keepdot.ld
@@ -0,0 +1,5 @@
+SECTIONS
+{
+  .myinit : { KEEP (*(.myinit)) }
+  .mytext : { *(.mytext*) *(.text*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-selective/keepdot.s b/binutils-2.19/ld/testsuite/ld-selective/keepdot.s
new file mode 100644
index 0000000..42176e2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-selective/keepdot.s
@@ -0,0 +1,17 @@
+	.text
+	.stabs "int:t(0,1)=r(0,1);-2147483648;2147483647;",128,0,0,0
+	.stabs "char:t(0,2)=r(0,2);0;127;",128,0,0,0
+
+	.section	.myinit,"ax"
+	.stabs "barxfoo:F(0,20)",36,0,2,_bar
+	.global _bar
+	.global _start
+_start:
+_bar:
+	.long 123
+
+	.section	.mytext.baz,"ax"
+	.stabs "baz:F(0,20)",36,0,6,_baz
+	.global _baz
+_baz:
+	.long 456
diff --git a/binutils-2.19/ld/testsuite/ld-selective/keepdot0.d b/binutils-2.19/ld/testsuite/ld-selective/keepdot0.d
new file mode 100644
index 0000000..4432a01
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-selective/keepdot0.d
@@ -0,0 +1,11 @@
+#source: keepdot.s
+#ld: --gc-sections -Bstatic -e _start -T keepdot0.ld
+#name: Preserve explicit . = 0
+#objdump: -h
+
+# Check that GC:ing does not mess up the value for dot when specified
+# as 0.
+
+#...
+[ 	]+.[ 	]+\.myinit[ 	]+0+[48][ 	]+0+[ 	]+0+ .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-selective/keepdot0.ld b/binutils-2.19/ld/testsuite/ld-selective/keepdot0.ld
new file mode 100644
index 0000000..9f053d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-selective/keepdot0.ld
@@ -0,0 +1,6 @@
+SECTIONS
+{
+  . = 0x0;
+  .myinit : { KEEP (*(.myinit)) }
+  .mytext : { *(.mytext*) *(.text*) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-selective/sel-dump.exp b/binutils-2.19/ld/testsuite/ld-selective/sel-dump.exp
new file mode 100644
index 0000000..76a7577
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-selective/sel-dump.exp
@@ -0,0 +1,35 @@
+# Expect script for ld selective linking tests running run_dump_test
+#   Copyright 2002, 2004, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# Test for ELF here, so we don't have to qualify on ELF specifically
+# in every .d-file.
+if ![is_elf_format] {
+    return
+}
+
+set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+for { set i 0 } { $i < [llength $test_list] } { incr i } {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname [lindex $test_list $i]]
+    setup_xfail "alpha*-*" "am33*-*" "arc*-*" "d30v*-*" "dlx*-*"
+    setup_xfail "hppa*64-*-*" "i370*-*" "i860*-*" "i960*-*" "ia64*-*"
+    setup_xfail "m88*-*" "mn10200-*" "mep-*" "or32-*" "pj-*"
+    run_dump_test [file rootname [lindex $test_list $i]]
+}
diff --git a/binutils-2.19/ld/testsuite/ld-selective/selective.exp b/binutils-2.19/ld/testsuite/ld-selective/selective.exp
new file mode 100644
index 0000000..b698154
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-selective/selective.exp
@@ -0,0 +1,239 @@
+# Expect script for LD selective linking tests
+#   Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Catherine Moore (clm@cygnus.com)
+# Make sure that constructors are handled correctly.
+
+# Only ELF based ports support selective linking
+if ![is_elf_format] {
+    return
+}
+
+# These targets do not support selective linking
+if {[istarget "alpha*-*-*"] || [istarget "am33*-*-*"] ||
+    [istarget "arc-*-*"] || [istarget "d30v-*-*"] ||
+    [istarget "dlx-*-*"] || [istarget "hppa*64*-*-*"] ||
+    [istarget "i370-*-*"] || [istarget "i860-*-*"] ||
+    [istarget "i960-*-*"] || [istarget "ia64-*-*"] ||
+    [istarget "m88*-*-*"] || [istarget "mn10200-*-*"] ||
+    [istarget "mep-*-*"] || [istarget "or32-*-*"] ||
+    [istarget "pj*-*-*"]} {
+    return
+}
+
+# List contains test-items with three items followed by four lists:
+# 1:name 2:test-type (CC or C++; add as needed) 3:filename 4:ld-flags
+# 5:must-have-symbols 6:must-not-have-symbols 7:xfail-targets.
+#
+# If a must(-not)-have symbol is a list, then that list must have two
+# items; the symbol name and a value the symbol must (not) have.
+#
+# Note: ld_nm trims leading `_' from _start
+#
+# FIXME: Instead of table, read settings from each source-file.
+set seltests {
+  {selective1 C   1.c  {}       {}    {dropme1 dropme2} {}}
+  {selective2 C   2.c  {}       {}    {foo} {}}
+  {selective3 C   2.c  {-u foo} {foo} {{foo 0}} {}}
+  {selective4 C++ 3.cc {}       {start a A::foo() B::foo()} {A::bar()} {mips*-*}}
+  {selective5 C++ 4.cc {}       {start a A::bar()} {A::foo() B::foo()} {mips*-*}}
+  {selective6 C++ 5.cc {}       {start a A::bar()}
+    {A::foo() B::foo() dropme1() dropme2()} {*-*-*}}
+}
+
+set cflags "-w -O -ffunction-sections -fdata-sections"
+set cxxflags "-fvtable-gc -fno-exceptions -fno-rtti"
+set ldflags "--gc-sections -Bstatic"
+
+if [istarget mips*-*] {
+    # MIPS16 doesn't support PIC code.
+    set cflags "-mno-abicalls $cflags"
+    # MIPS ELF uses __start by default, we override it.
+    set ldflags "-e _start $ldflags"
+}
+
+if [istarget sh64*-*-elf] {
+    # This is what gcc passes to ld by default, plus switch to the
+    # "usual" ELF _start (shelf32 normally uses just `start' for COFF
+    # compatibility)
+    set ldflags "-e _start -mshelf32 $ldflags"
+}
+
+# If we don't have g++ for the target, mark all tests as untested.
+if { ![is_remote host] && [which $CXX] == 0 } {
+    foreach testitem $seltests {
+	untested "[lindex $testitem 0]"
+    }
+    return
+}
+
+foreach testitem $seltests {
+    set testname [lindex $testitem 0]
+    set testtype [lindex $testitem 1]
+    set testfile [lindex $testitem 2]
+    set objfile "tmpdir/[file rootname $testfile].o"
+    set ldfile "tmpdir/[file rootname $testfile].x"
+    set failed 0
+
+    set ldargs [lindex $testitem 3]
+    set mustsyms [lindex $testitem 4]
+    set mustnotsyms [lindex $testitem 5]
+    set xfails [lindex $testitem 6]
+
+    foreach xfail_target $xfails {
+	setup_xfail $xfail_target
+    }
+    setup_xfail "arc*-*" "d30v*-*" "dlx*-*" "i370*-*" "i860*-*"
+    setup_xfail "i960*-*" "mn10200-*" "or32-*" "pj-*"
+
+    # It's either C or C++ at the moment.
+    if { $testtype == "C++" } {
+	set testflags "$cflags $cxxflags"
+	set compiler "$CXX"
+	if [string match "*gcc*" [lindex $CC 0]] {
+	    # Starting with 3.4.0, -fvtable-gc is no longer supported and thus
+	    # the functionality we try to test for cannot be expected to work.
+	    set version [remote_exec host "$CC -dumpversion"]
+	    set version [lindex $version 1]
+	    if [regexp "^(\[1-9\]\[0-9\]+|\[4-9\]|3.(\[1-9\]\[0-9\]+|\[4-9\]))\\." $version] {
+		setup_xfail {*-*-*}
+	    }
+	}
+    } {
+	set testflags "$cflags"
+	set compiler "$CC"
+    }
+
+    # Note that we do not actually *use* CXX; we just add cxxflags for C++
+    # tests.  It might have been a buglet originally; now I think better
+    # leave as is.
+    if { ![ld_compile "$compiler $testflags" $srcdir/$subdir/$testfile $objfile] } {
+	unresolved $testname
+	continue
+    }
+
+    # V850 targets need libgcc.a
+    if [istarget v850*-*-elf] {
+	set libgcc [remote_exec host "$compiler -print-libgcc-file-name"]
+	set libgcc [lindex $libgcc 1]
+	regsub -all "\[\r\n\]" $libgcc "" libgcc
+	set objfile "$objfile $libgcc"
+    }
+
+    # ARM targets need libgcc.a in THUMB mode so that __call_via_r3 is provided
+    if {[istarget arm-*-*] || [istarget xscale-*-*]} {
+	set libgcc [remote_exec host "$compiler -print-libgcc-file-name"]
+	set libgcc [lindex $libgcc 1]
+	regsub -all "\[\r\n\]" $libgcc "" libgcc
+	set objfile "$objfile $libgcc"
+    }
+
+    # HPPA linux targets need libgcc.a for millicode routines ($$dyncall).
+    if [istarget hppa*-*-linux*] {
+	set libgcc [remote_exec host "$compiler -print-libgcc-file-name"]
+	set libgcc [lindex $libgcc 1]
+	regsub -all "\[\r\n\]" $libgcc "" libgcc
+	set objfile "$objfile $libgcc"
+    }
+
+    # m6811/m6812 code has references to soft registers.
+    if {[istarget m6811-*-*] || [istarget m6812-*-*]} {
+	set objfile "$objfile --defsym _.frame=0 --defsym _.d1=0"
+	set objfile "$objfile --defsym _.d2=0"
+    }
+
+    if ![ld_simple_link $ld $ldfile "$ldflags [join $ldargs] $objfile"] {
+	fail $testname
+	continue
+    }
+
+    if ![ld_nm $nm --demangle $ldfile] {
+	unresolved $testname
+	continue
+    }
+
+    # Must make V2 demangled names look like V3
+    foreach nm_output_key [array names nm_output] {
+	if [regsub \\(void\\) $nm_output_key () new_nm_output_key] {
+	    set nm_output($new_nm_output_key) nm_output($nm_output_key)
+	}
+    }
+
+    # Check each mandated symbol and optionally mandated values.
+    foreach mustsym $mustsyms {
+	if { [llength [concat $mustsym]] == 1 } {
+	    if { ![info exists nm_output($mustsym)] } {
+		verbose -log "$testname: missing $mustsym"
+		fail $testname
+		set failed 1
+		break
+	    }
+	} {
+	    set mustsymname [lindex $mustsym 0]
+	    set mustsymvalue [lindex $mustsym 1]
+	    if { ![info exists nm_output($mustsymname)] } {
+		verbose -log "$testname: missing $mustsymname"
+		fail $testname
+		set failed 1
+		break
+	    } {
+		if { $nm_output($mustsymname) != $mustsymvalue } {
+		    verbose -log "$testname: $mustsymname != $mustsymvalue"
+		    verbose -log "is instead $nm_output($mustsymname)"
+		    fail $testname
+		    set failed 1
+		    break
+		}
+	    }
+	}
+    }
+
+    if { $failed != 0 } {
+	continue
+    }
+
+    # Check each unwanted symbol, or that symbols do not have specific
+    # values.
+    foreach mustnotsym $mustnotsyms {
+	if { [llength [concat $mustnotsym]] == 1 } {
+	    if { [info exists nm_output($mustnotsym)] } {
+		verbose -log "$testname: $mustnotsym == $nm_output($mustnotsym)"
+		fail $testname
+		set failed 1
+		break
+	    }
+	} {
+	    set mustnotsymname [lindex $mustnotsym 0]
+	    set mustnotsymvalue [lindex $mustnotsym 1]
+	    if { [info exists nm_output($mustnotsymname)] \
+		    && $nm_output($mustnotsymname) == $mustnotsymvalue} {
+		verbose -log "$testname: $mustnotsymname == $mustnotsymvalue"
+		fail $testname
+		set failed 1
+		break
+	    }
+	}
+    }
+
+    if { $failed == 0 } {
+	pass $testname
+    }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/arch.exp b/binutils-2.19/ld/testsuite/ld-sh/arch/arch.exp
new file mode 100644
index 0000000..1c33b13
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/arch.exp
@@ -0,0 +1,257 @@
+# Copyright (C) 2004, 2005, 2007
+# Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+
+# Please email any bugs, comments, and/or additions to this file to:
+# binutils@sources.redhat.com
+
+# This scripts tests of all available SH architectures with all other SH
+# architectures. It ensures that those combinations which should not work
+# do not work, and that those that should work produce the correct output
+# architecture.
+#
+# It looks for files in the same directory as this file named sh*.s .
+# Each file must contain one or more instructions which uniquely identifies
+# that architecture. The architecture name is inferred from the file name.
+# It is best to use the same files used by the assembler testsuite.
+#
+# It also creates another architecture named 'sh-unknown' by modifying
+# another arch type (there is no way to assemble such an arch) in order
+# to test what the linker would do with an older object file.
+#
+# The script generates the architecture permutations automatically,
+# but it reads the expected results from the file arch_expected.txt (also
+# found in the same directory as this script).
+#
+# The arch_expected.txt file should NOT be hand edited. Whenever the script
+# is run (e.g. with 'make check') it creates a new (usually identical) file
+# named arch_results.txt in the <objdir>/ld/testsuite directory. When the
+# expected results change (or new architectures are added) this new file
+# can be used to replace arch_expected.txt with no modification required.
+
+
+# The procedure extracts the architecture name from the objdump output.
+# If there is no architecture name (or objdump output changes significantly)
+# then the behaviour is undefined, but it will most likely return junk.
+
+proc get_sh_arch { ofile } {
+    global OBJDUMP
+
+    set cmd "$OBJDUMP -f $ofile"
+    verbose -log $cmd
+    catch "exec $cmd" objdump_output
+    verbose -log $objdump_output
+
+    set objdump_output [string replace $objdump_output 0 \
+	    [expr [string first "architecture:" $objdump_output] + 13] ""]
+
+    return [string range $objdump_output 0 [expr [string first "," $objdump_output] - 1]]
+}
+
+
+# This procedure runs two tests:
+#   Test 1: Check the linker can link the given files.
+#   Test 2: Check that the resultant architecture is as expected.
+# It also writes an entry to the arch_results.txt file.
+
+proc test_arch { file1 file2 arch resultfile } {
+    global LD
+
+    set name1 [file tail $file1]
+    set rootname1 [file rootname $name1]
+
+    set name2 [file tail $file2]
+    set rootname2 [file rootname $name2]
+
+    set flags [big_or_little_endian]
+    
+    # This must use -r to prevent LD trying to relocate the (unrealistic) file
+    send_log "$LD $flags -r -o ${rootname1}_${rootname2}.o $file1 $file2\n"
+    catch "exec $LD $flags -r -o ${rootname1}_${rootname2}.o $file1 $file2" ld_output
+    send_log $ld_output
+
+    if {[string equal $ld_output ""] == 1} then {
+	pass "$rootname1 file should link with $rootname2 file"
+
+	set result [get_sh_arch "${rootname1}_${rootname2}.o"]
+	puts $resultfile [format "%-20s %-20s %s" $file1 $file2 $result]
+
+	if {$result == $arch} then {
+	    pass "$rootname1 file with $rootname2 file should link to arch $arch"
+	    file delete "${rootname1}_${rootname2}.o"
+	} else {
+	    fail "$rootname1 file with $rootname2 file should link to arch $arch"
+	}
+    } else {
+	fail "$rootname1 file should link with $rootname2 file"
+
+	puts $resultfile [format "%-20s %-20s ERROR" $file1 $file2]
+	untested "$rootname2 file with $rootname2 file should link to arch $arch"
+    }
+
+}
+
+
+
+# This procedure tests that a pair of files that are not
+# suposed to link does, in fact, not link.
+# It also writes an entry to the arch_results.txt file.
+
+proc test_arch_error { file1 file2 resultfile} {
+    global link_output LD
+
+    set name1 [file tail $file1]
+    set rootname1 [file rootname $name1]
+
+    set name2 [file tail $file2]
+    set rootname2 [file rootname $name2]
+
+    # This must use -r to prevent LD trying to relocate the (unrealistic) file
+    send_log "$LD -r -o ${rootname1}_${rootname2}.o $file1 $file2\n"
+    catch "exec $LD -r -o ${rootname1}_${rootname2}.o $file1 $file2" ld_output
+    send_log $ld_output
+
+    if {[string equal $ld_output ""] == 1} then {
+	fail "$rootname1 file should NOT link with $rootname2 file"
+	puts $resultfile [format "%-20s %-20s [get_sh_arch ${rootname1}_${rootname2}.o]" $file1 $file2]
+    } else {
+	pass "$rootname1 file should NOT link with $rootname2 file"
+	puts $resultfile [format "%-20s %-20s ERROR" $file1 $file2]
+    }
+}   
+
+# These tests are not suitable for sh-coff because
+# coff does not store the architecture information.
+
+if [istarget sh*-*-elf] then {
+    global subdir srcdir
+    global AS
+
+    # Find all the architectures and assemble all the files
+    # we will use for the linker tests.
+
+    set sfilelist [lsort -ascii [glob "$srcdir/$subdir/sh*.s"]]
+    set ofilelist {}
+    foreach sfile $sfilelist {
+	set ofile "[file rootname [file tail $sfile]].o"
+	lappend ofilelist $ofile
+
+	set endian "-big"
+	if [string equal [big_or_little_endian] " -EL"] then {
+	    set endian "-little"
+	}
+
+	set cmd "$AS $endian -isa=any $sfile -o $ofile"
+	verbose -log $cmd
+	catch "exec $cmd" as_output
+	if ![file exists $ofile] then {
+	    verbose -log $as_output
+	    perror "$sfile: assembly failed"
+	}
+    }
+
+    # Create the default arch ofile
+    # This cannot be created with the assembler
+    # sh4al-dsp is number 6, sh-unknown is 0
+
+    lappend ofilelist "sh-unknown.o"
+
+    if [string equal [big_or_little_endian] " -EL"] then {
+	set cmd {xxd sh4al-dsp.o | sed {s/\(^0000020: .... .... \)06/\100/} | xxd -r - sh-unknown.o}
+    } else {
+	set cmd {xxd sh4al-dsp.o | sed {s/\(^0000020: .... .... .... ..\)06/\100/} | xxd -r - sh-unknown.o}
+    }
+    verbose -log $cmd
+    catch "exec $cmd" xxd_output
+    verbose -log $xxd_output
+    if [string equal [get_sh_arch "sh-unknown.o"] "sh4al-dsp"] then {
+	perror "sh-unknown.o not generated correctly"
+    }
+
+
+    # Initialise the results file
+
+    set outfile [open "arch_results.txt" w 0666]
+    puts $outfile "# Generated file. DO NOT EDIT"
+    puts $outfile "#"
+    puts $outfile "# This file is generated by ld/testsuite/ld-sh/arch/arch.exp ."
+    puts $outfile "# It contains the expected results of the tests."
+    puts $outfile "# If the tests are failing because the expected results"
+    puts $outfile "# have changed then run 'make check' and copy the new file"
+    puts $outfile "# from <objdir>/ld/arch_results.txt"
+    puts $outfile "# to   <srcdir>/ld/testsuite/ld-sh/arch/arch_expected.txt ."
+    puts $outfile "# Make sure the new expected results are ALL correct."
+    puts $outfile "#"
+    puts $outfile [format "# %-18s %-20s %s" "FILE1" "FILE2" "OUTPUT"]
+    puts $outfile [format "# %-18s %-20s %s" "-----" "-----" "------"]
+
+    # Open the expected results file and skip the header
+
+    set infile [open "$srcdir/$subdir/arch_expected.txt" r]
+    while {[gets $infile line] >= 0 && [string match {\#*} $line]} {verbose -log "reading '$line'"}
+
+    foreach file1 $ofilelist {
+	foreach file2 $ofilelist {
+	    set name1 [file tail $file1]
+	    set rootname1 [file rootname $name1]
+
+	    set name2 [file tail $file2]
+	    set rootname2 [file rootname $name2]
+
+	    # Decode the expected result from the file
+
+	    scan $line "%s %s %s" exfile1 exfile2 exarch
+	    verbose -log "exfile1 = '$exfile1', exfile2 = '$exfile2', exarch = '$exarch'"
+	    verbose -log "  name1 = '$name1',   name2 = '$name2'"
+
+	    if {[string equal $exfile1 $name1] && [string equal $exfile2 $file2]} then {
+		# The expected result file makes sense and
+		# appears up-to-date (the file and options match)
+
+		if {[string equal $exarch "ERROR"]} then {
+		    test_arch_error $file1 $file2 $outfile
+		} else {
+		    test_arch $file1 $file2 $exarch $outfile
+		}
+	    } else {
+		# The expected result file isn't right somehow
+		# so just try any old test. This will cause
+		# many failures, but will genrate the results file.
+
+		test_arch $file1 $file2 $rootname1 $outfile
+	    }
+
+	    # Read the next line from the expected result file.
+	    # This is at the end because the process of skipping
+	    # the header reads the first real line
+
+	    if [gets $infile line] then {
+		verbose -log "reading '$line'"
+	    }
+	}
+    }
+
+    close $infile
+    close $outfile
+
+    foreach file $ofilelist {
+	file delete $file
+    }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/arch_expected.txt b/binutils-2.19/ld/testsuite/ld-sh/arch/arch_expected.txt
new file mode 100644
index 0000000..d11c43b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/arch_expected.txt
@@ -0,0 +1,453 @@
+# Generated file. DO NOT EDIT
+#
+# This file is generated by ld/testsuite/ld-sh/arch/arch.exp .
+# It contains the expected results of the tests.
+# If the tests are failing because the expected results
+# have changed then run 'make check' and copy the new file
+# from <objdir>/ld/arch_results.txt
+# to   <srcdir>/ld/testsuite/ld-sh/arch/arch_expected.txt .
+# Make sure the new expected results are ALL correct.
+#
+# FILE1              FILE2                OUTPUT
+# -----              -----                ------
+sh-dsp.o             sh-dsp.o             sh-dsp
+sh-dsp.o             sh.o                 sh-dsp
+sh-dsp.o             sh2.o                sh-dsp
+sh-dsp.o             sh2a-nofpu-or-sh3-nommu.o sh3-dsp
+sh-dsp.o             sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp
+sh-dsp.o             sh2a-nofpu.o         ERROR
+sh-dsp.o             sh2a-or-sh3e.o       ERROR
+sh-dsp.o             sh2a-or-sh4.o        ERROR
+sh-dsp.o             sh2a.o               ERROR
+sh-dsp.o             sh2e.o               ERROR
+sh-dsp.o             sh3-dsp.o            sh3-dsp
+sh-dsp.o             sh3-nommu.o          sh3-dsp
+sh-dsp.o             sh3.o                sh3-dsp
+sh-dsp.o             sh3e.o               ERROR
+sh-dsp.o             sh4-nofpu.o          sh4al-dsp
+sh-dsp.o             sh4-nommu-nofpu.o    sh4al-dsp
+sh-dsp.o             sh4.o                ERROR
+sh-dsp.o             sh4a-nofpu.o         sh4al-dsp
+sh-dsp.o             sh4a.o               ERROR
+sh-dsp.o             sh4al-dsp.o          sh4al-dsp
+sh-dsp.o             sh-unknown.o         sh-dsp
+sh.o                 sh-dsp.o             sh-dsp
+sh.o                 sh.o                 sh
+sh.o                 sh2.o                sh2
+sh.o                 sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu
+sh.o                 sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu
+sh.o                 sh2a-nofpu.o         sh2a-nofpu
+sh.o                 sh2a-or-sh3e.o       sh2a-or-sh3e
+sh.o                 sh2a-or-sh4.o        sh2a-or-sh4
+sh.o                 sh2a.o               sh2a
+sh.o                 sh2e.o               sh2e
+sh.o                 sh3-dsp.o            sh3-dsp
+sh.o                 sh3-nommu.o          sh3-nommu
+sh.o                 sh3.o                sh3
+sh.o                 sh3e.o               sh3e
+sh.o                 sh4-nofpu.o          sh4-nofpu
+sh.o                 sh4-nommu-nofpu.o    sh4-nommu-nofpu
+sh.o                 sh4.o                sh4
+sh.o                 sh4a-nofpu.o         sh4a-nofpu
+sh.o                 sh4a.o               sh4a
+sh.o                 sh4al-dsp.o          sh4al-dsp
+sh.o                 sh-unknown.o         sh
+sh2.o                sh-dsp.o             sh-dsp
+sh2.o                sh.o                 sh2
+sh2.o                sh2.o                sh2
+sh2.o                sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu
+sh2.o                sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu
+sh2.o                sh2a-nofpu.o         sh2a-nofpu
+sh2.o                sh2a-or-sh3e.o       sh2a-or-sh3e
+sh2.o                sh2a-or-sh4.o        sh2a-or-sh4
+sh2.o                sh2a.o               sh2a
+sh2.o                sh2e.o               sh2e
+sh2.o                sh3-dsp.o            sh3-dsp
+sh2.o                sh3-nommu.o          sh3-nommu
+sh2.o                sh3.o                sh3
+sh2.o                sh3e.o               sh3e
+sh2.o                sh4-nofpu.o          sh4-nofpu
+sh2.o                sh4-nommu-nofpu.o    sh4-nommu-nofpu
+sh2.o                sh4.o                sh4
+sh2.o                sh4a-nofpu.o         sh4a-nofpu
+sh2.o                sh4a.o               sh4a
+sh2.o                sh4al-dsp.o          sh4al-dsp
+sh2.o                sh-unknown.o         sh2
+sh2a-nofpu-or-sh3-nommu.o sh-dsp.o             sh3-dsp
+sh2a-nofpu-or-sh3-nommu.o sh.o                 sh2a-nofpu-or-sh3-nommu
+sh2a-nofpu-or-sh3-nommu.o sh2.o                sh2a-nofpu-or-sh3-nommu
+sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu
+sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu.o         sh2a-nofpu
+sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh3e.o       sh2a-or-sh3e
+sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh4.o        sh2a-or-sh4
+sh2a-nofpu-or-sh3-nommu.o sh2a.o               sh2a
+sh2a-nofpu-or-sh3-nommu.o sh2e.o               sh2a-or-sh3e
+sh2a-nofpu-or-sh3-nommu.o sh3-dsp.o            sh3-dsp
+sh2a-nofpu-or-sh3-nommu.o sh3-nommu.o          sh3-nommu
+sh2a-nofpu-or-sh3-nommu.o sh3.o                sh3
+sh2a-nofpu-or-sh3-nommu.o sh3e.o               sh3e
+sh2a-nofpu-or-sh3-nommu.o sh4-nofpu.o          sh4-nofpu
+sh2a-nofpu-or-sh3-nommu.o sh4-nommu-nofpu.o    sh4-nommu-nofpu
+sh2a-nofpu-or-sh3-nommu.o sh4.o                sh4
+sh2a-nofpu-or-sh3-nommu.o sh4a-nofpu.o         sh4a-nofpu
+sh2a-nofpu-or-sh3-nommu.o sh4a.o               sh4a
+sh2a-nofpu-or-sh3-nommu.o sh4al-dsp.o          sh4al-dsp
+sh2a-nofpu-or-sh3-nommu.o sh-unknown.o         sh2a-nofpu-or-sh3-nommu
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh-dsp.o             sh4al-dsp
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh.o                 sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh2.o                sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu.o         sh2a-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh3e.o       sh2a-or-sh4
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4.o        sh2a-or-sh4
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a.o               sh2a
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh2e.o               sh2a-or-sh4
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh3-dsp.o            sh4al-dsp
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh3-nommu.o          sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh3.o                sh4-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh3e.o               sh4
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nofpu.o          sh4-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nommu-nofpu.o    sh4-nommu-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh4.o                sh4
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a-nofpu.o         sh4a-nofpu
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a.o               sh4a
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp.o          sh4al-dsp
+sh2a-nofpu-or-sh4-nommu-nofpu.o sh-unknown.o         sh2a-nofpu-or-sh4-nommu-nofpu
+sh2a-nofpu.o         sh-dsp.o             ERROR
+sh2a-nofpu.o         sh.o                 sh2a-nofpu
+sh2a-nofpu.o         sh2.o                sh2a-nofpu
+sh2a-nofpu.o         sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu
+sh2a-nofpu.o         sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu
+sh2a-nofpu.o         sh2a-nofpu.o         sh2a-nofpu
+sh2a-nofpu.o         sh2a-or-sh3e.o       sh2a
+sh2a-nofpu.o         sh2a-or-sh4.o        sh2a
+sh2a-nofpu.o         sh2a.o               sh2a
+sh2a-nofpu.o         sh2e.o               sh2a
+sh2a-nofpu.o         sh3-dsp.o            ERROR
+sh2a-nofpu.o         sh3-nommu.o          ERROR
+sh2a-nofpu.o         sh3.o                ERROR
+sh2a-nofpu.o         sh3e.o               ERROR
+sh2a-nofpu.o         sh4-nofpu.o          ERROR
+sh2a-nofpu.o         sh4-nommu-nofpu.o    ERROR
+sh2a-nofpu.o         sh4.o                ERROR
+sh2a-nofpu.o         sh4a-nofpu.o         ERROR
+sh2a-nofpu.o         sh4a.o               ERROR
+sh2a-nofpu.o         sh4al-dsp.o          ERROR
+sh2a-nofpu.o         sh-unknown.o         sh2a-nofpu
+sh2a-or-sh3e.o       sh-dsp.o             ERROR
+sh2a-or-sh3e.o       sh.o                 sh2a-or-sh3e
+sh2a-or-sh3e.o       sh2.o                sh2a-or-sh3e
+sh2a-or-sh3e.o       sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh3e
+sh2a-or-sh3e.o       sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4
+sh2a-or-sh3e.o       sh2a-nofpu.o         sh2a
+sh2a-or-sh3e.o       sh2a-or-sh3e.o       sh2a-or-sh3e
+sh2a-or-sh3e.o       sh2a-or-sh4.o        sh2a-or-sh4
+sh2a-or-sh3e.o       sh2a.o               sh2a
+sh2a-or-sh3e.o       sh2e.o               sh2a-or-sh3e
+sh2a-or-sh3e.o       sh3-dsp.o            ERROR
+sh2a-or-sh3e.o       sh3-nommu.o          sh3e
+sh2a-or-sh3e.o       sh3.o                sh3e
+sh2a-or-sh3e.o       sh3e.o               sh3e
+sh2a-or-sh3e.o       sh4-nofpu.o          sh4
+sh2a-or-sh3e.o       sh4-nommu-nofpu.o    sh4
+sh2a-or-sh3e.o       sh4.o                sh4
+sh2a-or-sh3e.o       sh4a-nofpu.o         sh4a
+sh2a-or-sh3e.o       sh4a.o               sh4a
+sh2a-or-sh3e.o       sh4al-dsp.o          ERROR
+sh2a-or-sh3e.o       sh-unknown.o         sh2a-or-sh3e
+sh2a-or-sh4.o        sh-dsp.o             ERROR
+sh2a-or-sh4.o        sh.o                 sh2a-or-sh4
+sh2a-or-sh4.o        sh2.o                sh2a-or-sh4
+sh2a-or-sh4.o        sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh4
+sh2a-or-sh4.o        sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4
+sh2a-or-sh4.o        sh2a-nofpu.o         sh2a
+sh2a-or-sh4.o        sh2a-or-sh3e.o       sh2a-or-sh4
+sh2a-or-sh4.o        sh2a-or-sh4.o        sh2a-or-sh4
+sh2a-or-sh4.o        sh2a.o               sh2a
+sh2a-or-sh4.o        sh2e.o               sh2a-or-sh4
+sh2a-or-sh4.o        sh3-dsp.o            ERROR
+sh2a-or-sh4.o        sh3-nommu.o          sh4
+sh2a-or-sh4.o        sh3.o                sh4
+sh2a-or-sh4.o        sh3e.o               sh4
+sh2a-or-sh4.o        sh4-nofpu.o          sh4
+sh2a-or-sh4.o        sh4-nommu-nofpu.o    sh4
+sh2a-or-sh4.o        sh4.o                sh4
+sh2a-or-sh4.o        sh4a-nofpu.o         sh4a
+sh2a-or-sh4.o        sh4a.o               sh4a
+sh2a-or-sh4.o        sh4al-dsp.o          ERROR
+sh2a-or-sh4.o        sh-unknown.o         sh2a-or-sh4
+sh2a.o               sh-dsp.o             ERROR
+sh2a.o               sh.o                 sh2a
+sh2a.o               sh2.o                sh2a
+sh2a.o               sh2a-nofpu-or-sh3-nommu.o sh2a
+sh2a.o               sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a
+sh2a.o               sh2a-nofpu.o         sh2a
+sh2a.o               sh2a-or-sh3e.o       sh2a
+sh2a.o               sh2a-or-sh4.o        sh2a
+sh2a.o               sh2a.o               sh2a
+sh2a.o               sh2e.o               sh2a
+sh2a.o               sh3-dsp.o            ERROR
+sh2a.o               sh3-nommu.o          ERROR
+sh2a.o               sh3.o                ERROR
+sh2a.o               sh3e.o               ERROR
+sh2a.o               sh4-nofpu.o          ERROR
+sh2a.o               sh4-nommu-nofpu.o    ERROR
+sh2a.o               sh4.o                ERROR
+sh2a.o               sh4a-nofpu.o         ERROR
+sh2a.o               sh4a.o               ERROR
+sh2a.o               sh4al-dsp.o          ERROR
+sh2a.o               sh-unknown.o         sh2a
+sh2e.o               sh-dsp.o             ERROR
+sh2e.o               sh.o                 sh2e
+sh2e.o               sh2.o                sh2e
+sh2e.o               sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh3e
+sh2e.o               sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4
+sh2e.o               sh2a-nofpu.o         sh2a
+sh2e.o               sh2a-or-sh3e.o       sh2a-or-sh3e
+sh2e.o               sh2a-or-sh4.o        sh2a-or-sh4
+sh2e.o               sh2a.o               sh2a
+sh2e.o               sh2e.o               sh2e
+sh2e.o               sh3-dsp.o            ERROR
+sh2e.o               sh3-nommu.o          sh3e
+sh2e.o               sh3.o                sh3e
+sh2e.o               sh3e.o               sh3e
+sh2e.o               sh4-nofpu.o          sh4
+sh2e.o               sh4-nommu-nofpu.o    sh4
+sh2e.o               sh4.o                sh4
+sh2e.o               sh4a-nofpu.o         sh4a
+sh2e.o               sh4a.o               sh4a
+sh2e.o               sh4al-dsp.o          ERROR
+sh2e.o               sh-unknown.o         sh2e
+sh3-dsp.o            sh-dsp.o             sh3-dsp
+sh3-dsp.o            sh.o                 sh3-dsp
+sh3-dsp.o            sh2.o                sh3-dsp
+sh3-dsp.o            sh2a-nofpu-or-sh3-nommu.o sh3-dsp
+sh3-dsp.o            sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp
+sh3-dsp.o            sh2a-nofpu.o         ERROR
+sh3-dsp.o            sh2a-or-sh3e.o       ERROR
+sh3-dsp.o            sh2a-or-sh4.o        ERROR
+sh3-dsp.o            sh2a.o               ERROR
+sh3-dsp.o            sh2e.o               ERROR
+sh3-dsp.o            sh3-dsp.o            sh3-dsp
+sh3-dsp.o            sh3-nommu.o          sh3-dsp
+sh3-dsp.o            sh3.o                sh3-dsp
+sh3-dsp.o            sh3e.o               ERROR
+sh3-dsp.o            sh4-nofpu.o          sh4al-dsp
+sh3-dsp.o            sh4-nommu-nofpu.o    sh4al-dsp
+sh3-dsp.o            sh4.o                ERROR
+sh3-dsp.o            sh4a-nofpu.o         sh4al-dsp
+sh3-dsp.o            sh4a.o               ERROR
+sh3-dsp.o            sh4al-dsp.o          sh4al-dsp
+sh3-dsp.o            sh-unknown.o         sh3-dsp
+sh3-nommu.o          sh-dsp.o             sh3-dsp
+sh3-nommu.o          sh.o                 sh3-nommu
+sh3-nommu.o          sh2.o                sh3-nommu
+sh3-nommu.o          sh2a-nofpu-or-sh3-nommu.o sh3-nommu
+sh3-nommu.o          sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nommu-nofpu
+sh3-nommu.o          sh2a-nofpu.o         ERROR
+sh3-nommu.o          sh2a-or-sh3e.o       sh3e
+sh3-nommu.o          sh2a-or-sh4.o        sh4
+sh3-nommu.o          sh2a.o               ERROR
+sh3-nommu.o          sh2e.o               sh3e
+sh3-nommu.o          sh3-dsp.o            sh3-dsp
+sh3-nommu.o          sh3-nommu.o          sh3-nommu
+sh3-nommu.o          sh3.o                sh3
+sh3-nommu.o          sh3e.o               sh3e
+sh3-nommu.o          sh4-nofpu.o          sh4-nofpu
+sh3-nommu.o          sh4-nommu-nofpu.o    sh4-nommu-nofpu
+sh3-nommu.o          sh4.o                sh4
+sh3-nommu.o          sh4a-nofpu.o         sh4a-nofpu
+sh3-nommu.o          sh4a.o               sh4a
+sh3-nommu.o          sh4al-dsp.o          sh4al-dsp
+sh3-nommu.o          sh-unknown.o         sh3-nommu
+sh3.o                sh-dsp.o             sh3-dsp
+sh3.o                sh.o                 sh3
+sh3.o                sh2.o                sh3
+sh3.o                sh2a-nofpu-or-sh3-nommu.o sh3
+sh3.o                sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nofpu
+sh3.o                sh2a-nofpu.o         ERROR
+sh3.o                sh2a-or-sh3e.o       sh3e
+sh3.o                sh2a-or-sh4.o        sh4
+sh3.o                sh2a.o               ERROR
+sh3.o                sh2e.o               sh3e
+sh3.o                sh3-dsp.o            sh3-dsp
+sh3.o                sh3-nommu.o          sh3
+sh3.o                sh3.o                sh3
+sh3.o                sh3e.o               sh3e
+sh3.o                sh4-nofpu.o          sh4-nofpu
+sh3.o                sh4-nommu-nofpu.o    sh4-nofpu
+sh3.o                sh4.o                sh4
+sh3.o                sh4a-nofpu.o         sh4a-nofpu
+sh3.o                sh4a.o               sh4a
+sh3.o                sh4al-dsp.o          sh4al-dsp
+sh3.o                sh-unknown.o         sh3
+sh3e.o               sh-dsp.o             ERROR
+sh3e.o               sh.o                 sh3e
+sh3e.o               sh2.o                sh3e
+sh3e.o               sh2a-nofpu-or-sh3-nommu.o sh3e
+sh3e.o               sh2a-nofpu-or-sh4-nommu-nofpu.o sh4
+sh3e.o               sh2a-nofpu.o         ERROR
+sh3e.o               sh2a-or-sh3e.o       sh3e
+sh3e.o               sh2a-or-sh4.o        sh4
+sh3e.o               sh2a.o               ERROR
+sh3e.o               sh2e.o               sh3e
+sh3e.o               sh3-dsp.o            ERROR
+sh3e.o               sh3-nommu.o          sh3e
+sh3e.o               sh3.o                sh3e
+sh3e.o               sh3e.o               sh3e
+sh3e.o               sh4-nofpu.o          sh4
+sh3e.o               sh4-nommu-nofpu.o    sh4
+sh3e.o               sh4.o                sh4
+sh3e.o               sh4a-nofpu.o         sh4a
+sh3e.o               sh4a.o               sh4a
+sh3e.o               sh4al-dsp.o          ERROR
+sh3e.o               sh-unknown.o         sh3e
+sh4-nofpu.o          sh-dsp.o             sh4al-dsp
+sh4-nofpu.o          sh.o                 sh4-nofpu
+sh4-nofpu.o          sh2.o                sh4-nofpu
+sh4-nofpu.o          sh2a-nofpu-or-sh3-nommu.o sh4-nofpu
+sh4-nofpu.o          sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nofpu
+sh4-nofpu.o          sh2a-nofpu.o         ERROR
+sh4-nofpu.o          sh2a-or-sh3e.o       sh4
+sh4-nofpu.o          sh2a-or-sh4.o        sh4
+sh4-nofpu.o          sh2a.o               ERROR
+sh4-nofpu.o          sh2e.o               sh4
+sh4-nofpu.o          sh3-dsp.o            sh4al-dsp
+sh4-nofpu.o          sh3-nommu.o          sh4-nofpu
+sh4-nofpu.o          sh3.o                sh4-nofpu
+sh4-nofpu.o          sh3e.o               sh4
+sh4-nofpu.o          sh4-nofpu.o          sh4-nofpu
+sh4-nofpu.o          sh4-nommu-nofpu.o    sh4-nofpu
+sh4-nofpu.o          sh4.o                sh4
+sh4-nofpu.o          sh4a-nofpu.o         sh4a-nofpu
+sh4-nofpu.o          sh4a.o               sh4a
+sh4-nofpu.o          sh4al-dsp.o          sh4al-dsp
+sh4-nofpu.o          sh-unknown.o         sh4-nofpu
+sh4-nommu-nofpu.o    sh-dsp.o             sh4al-dsp
+sh4-nommu-nofpu.o    sh.o                 sh4-nommu-nofpu
+sh4-nommu-nofpu.o    sh2.o                sh4-nommu-nofpu
+sh4-nommu-nofpu.o    sh2a-nofpu-or-sh3-nommu.o sh4-nommu-nofpu
+sh4-nommu-nofpu.o    sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nommu-nofpu
+sh4-nommu-nofpu.o    sh2a-nofpu.o         ERROR
+sh4-nommu-nofpu.o    sh2a-or-sh3e.o       sh4
+sh4-nommu-nofpu.o    sh2a-or-sh4.o        sh4
+sh4-nommu-nofpu.o    sh2a.o               ERROR
+sh4-nommu-nofpu.o    sh2e.o               sh4
+sh4-nommu-nofpu.o    sh3-dsp.o            sh4al-dsp
+sh4-nommu-nofpu.o    sh3-nommu.o          sh4-nommu-nofpu
+sh4-nommu-nofpu.o    sh3.o                sh4-nofpu
+sh4-nommu-nofpu.o    sh3e.o               sh4
+sh4-nommu-nofpu.o    sh4-nofpu.o          sh4-nofpu
+sh4-nommu-nofpu.o    sh4-nommu-nofpu.o    sh4-nommu-nofpu
+sh4-nommu-nofpu.o    sh4.o                sh4
+sh4-nommu-nofpu.o    sh4a-nofpu.o         sh4a-nofpu
+sh4-nommu-nofpu.o    sh4a.o               sh4a
+sh4-nommu-nofpu.o    sh4al-dsp.o          sh4al-dsp
+sh4-nommu-nofpu.o    sh-unknown.o         sh4-nommu-nofpu
+sh4.o                sh-dsp.o             ERROR
+sh4.o                sh.o                 sh4
+sh4.o                sh2.o                sh4
+sh4.o                sh2a-nofpu-or-sh3-nommu.o sh4
+sh4.o                sh2a-nofpu-or-sh4-nommu-nofpu.o sh4
+sh4.o                sh2a-nofpu.o         ERROR
+sh4.o                sh2a-or-sh3e.o       sh4
+sh4.o                sh2a-or-sh4.o        sh4
+sh4.o                sh2a.o               ERROR
+sh4.o                sh2e.o               sh4
+sh4.o                sh3-dsp.o            ERROR
+sh4.o                sh3-nommu.o          sh4
+sh4.o                sh3.o                sh4
+sh4.o                sh3e.o               sh4
+sh4.o                sh4-nofpu.o          sh4
+sh4.o                sh4-nommu-nofpu.o    sh4
+sh4.o                sh4.o                sh4
+sh4.o                sh4a-nofpu.o         sh4a
+sh4.o                sh4a.o               sh4a
+sh4.o                sh4al-dsp.o          ERROR
+sh4.o                sh-unknown.o         sh4
+sh4a-nofpu.o         sh-dsp.o             sh4al-dsp
+sh4a-nofpu.o         sh.o                 sh4a-nofpu
+sh4a-nofpu.o         sh2.o                sh4a-nofpu
+sh4a-nofpu.o         sh2a-nofpu-or-sh3-nommu.o sh4a-nofpu
+sh4a-nofpu.o         sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a-nofpu
+sh4a-nofpu.o         sh2a-nofpu.o         ERROR
+sh4a-nofpu.o         sh2a-or-sh3e.o       sh4a
+sh4a-nofpu.o         sh2a-or-sh4.o        sh4a
+sh4a-nofpu.o         sh2a.o               ERROR
+sh4a-nofpu.o         sh2e.o               sh4a
+sh4a-nofpu.o         sh3-dsp.o            sh4al-dsp
+sh4a-nofpu.o         sh3-nommu.o          sh4a-nofpu
+sh4a-nofpu.o         sh3.o                sh4a-nofpu
+sh4a-nofpu.o         sh3e.o               sh4a
+sh4a-nofpu.o         sh4-nofpu.o          sh4a-nofpu
+sh4a-nofpu.o         sh4-nommu-nofpu.o    sh4a-nofpu
+sh4a-nofpu.o         sh4.o                sh4a
+sh4a-nofpu.o         sh4a-nofpu.o         sh4a-nofpu
+sh4a-nofpu.o         sh4a.o               sh4a
+sh4a-nofpu.o         sh4al-dsp.o          sh4al-dsp
+sh4a-nofpu.o         sh-unknown.o         sh4a-nofpu
+sh4a.o               sh-dsp.o             ERROR
+sh4a.o               sh.o                 sh4a
+sh4a.o               sh2.o                sh4a
+sh4a.o               sh2a-nofpu-or-sh3-nommu.o sh4a
+sh4a.o               sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a
+sh4a.o               sh2a-nofpu.o         ERROR
+sh4a.o               sh2a-or-sh3e.o       sh4a
+sh4a.o               sh2a-or-sh4.o        sh4a
+sh4a.o               sh2a.o               ERROR
+sh4a.o               sh2e.o               sh4a
+sh4a.o               sh3-dsp.o            ERROR
+sh4a.o               sh3-nommu.o          sh4a
+sh4a.o               sh3.o                sh4a
+sh4a.o               sh3e.o               sh4a
+sh4a.o               sh4-nofpu.o          sh4a
+sh4a.o               sh4-nommu-nofpu.o    sh4a
+sh4a.o               sh4.o                sh4a
+sh4a.o               sh4a-nofpu.o         sh4a
+sh4a.o               sh4a.o               sh4a
+sh4a.o               sh4al-dsp.o          ERROR
+sh4a.o               sh-unknown.o         sh4a
+sh4al-dsp.o          sh-dsp.o             sh4al-dsp
+sh4al-dsp.o          sh.o                 sh4al-dsp
+sh4al-dsp.o          sh2.o                sh4al-dsp
+sh4al-dsp.o          sh2a-nofpu-or-sh3-nommu.o sh4al-dsp
+sh4al-dsp.o          sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp
+sh4al-dsp.o          sh2a-nofpu.o         ERROR
+sh4al-dsp.o          sh2a-or-sh3e.o       ERROR
+sh4al-dsp.o          sh2a-or-sh4.o        ERROR
+sh4al-dsp.o          sh2a.o               ERROR
+sh4al-dsp.o          sh2e.o               ERROR
+sh4al-dsp.o          sh3-dsp.o            sh4al-dsp
+sh4al-dsp.o          sh3-nommu.o          sh4al-dsp
+sh4al-dsp.o          sh3.o                sh4al-dsp
+sh4al-dsp.o          sh3e.o               ERROR
+sh4al-dsp.o          sh4-nofpu.o          sh4al-dsp
+sh4al-dsp.o          sh4-nommu-nofpu.o    sh4al-dsp
+sh4al-dsp.o          sh4.o                ERROR
+sh4al-dsp.o          sh4a-nofpu.o         sh4al-dsp
+sh4al-dsp.o          sh4a.o               ERROR
+sh4al-dsp.o          sh4al-dsp.o          sh4al-dsp
+sh4al-dsp.o          sh-unknown.o         sh4al-dsp
+sh-unknown.o         sh-dsp.o             sh-dsp
+sh-unknown.o         sh.o                 sh
+sh-unknown.o         sh2.o                sh2
+sh-unknown.o         sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu
+sh-unknown.o         sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu
+sh-unknown.o         sh2a-nofpu.o         sh2a-nofpu
+sh-unknown.o         sh2a-or-sh3e.o       sh2a-or-sh3e
+sh-unknown.o         sh2a-or-sh4.o        sh2a-or-sh4
+sh-unknown.o         sh2a.o               sh2a
+sh-unknown.o         sh2e.o               sh2e
+sh-unknown.o         sh3-dsp.o            sh3-dsp
+sh-unknown.o         sh3-nommu.o          sh3-nommu
+sh-unknown.o         sh3.o                sh3
+sh-unknown.o         sh3e.o               sh3e
+sh-unknown.o         sh4-nofpu.o          sh4-nofpu
+sh-unknown.o         sh4-nommu-nofpu.o    sh4-nommu-nofpu
+sh-unknown.o         sh4.o                sh4
+sh-unknown.o         sh4a-nofpu.o         sh4a-nofpu
+sh-unknown.o         sh4a.o               sh4a
+sh-unknown.o         sh4al-dsp.o          sh4al-dsp
+sh-unknown.o         sh-unknown.o         sh
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh-dsp.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh-dsp.s
new file mode 100644
index 0000000..cd87a22
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh-dsp.s
@@ -0,0 +1,272 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh-dsp but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh-dsp.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh-dsp.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh_dsp:
+! Instructions introduced into sh-dsp
+	ldc r4,MOD                ;!/* 0100nnnn01011110 ldc <REG_N>,MOD     */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}
+	ldc r4,RE                 ;!/* 0100nnnn01111110 ldc <REG_N>,RE     */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}
+	ldc r4,RS                 ;!/* 0100nnnn01101110 ldc <REG_N>,RS     */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}
+	ldc.l @r4+,MOD            ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,RE             ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,RS             ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}
+	ldre @(8,PC)              ;!/* 10001110i8p2.... ldre @(<disp>,PC)	*/{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}
+	ldrs @(8,PC)              ;!/* 10001100i8p2.... ldrs @(<disp>,PC)	*/{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}
+	lds r4,DSR                ;!/* 0100nnnn01101010 lds <REG_N>,DSR	*/{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
+	lds r4,A0                 ;!/* 0100nnnn01111010 lds <REG_N>,A0	*/{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
+	lds r4,X0                 ;!/* 0100nnnn10001010 lds <REG_N>,X0	*/{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
+	lds r4,X1                 ;!/* 0100nnnn10011010 lds <REG_N>,X1	*/{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
+	lds r4,Y0                 ;!/* 0100nnnn10101010 lds <REG_N>,Y0	*/{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
+	lds r4,Y1                 ;!/* 0100nnnn10111010 lds <REG_N>,Y1	*/{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
+	lds.l @r4+,DSR            ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR	*/{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,A0             ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0	*/{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,X0             ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0	*/{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,X1             ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1	*/{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,Y0             ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0	*/{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,Y1             ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1	*/{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}
+	setrc r4                  ;!/* 0100nnnn00010100 setrc <REG_N>       */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
+	setrc #4                  ;!/* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
+	repeat 10 20 r4           ;!/* repeat start end <REG_N>       	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
+	repeat 10 20 #4           ;!/* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
+	stc MOD,r4                ;!/* 0000nnnn01010010 stc MOD,<REG_N>     */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}
+	stc RE,r4                 ;!/* 0000nnnn01110010 stc RE,<REG_N>     */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
+	stc RS,r4                 ;!/* 0000nnnn01100010 stc RS,<REG_N>     */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
+	stc.l MOD,@-r4            ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}
+	stc.l RE,@-r4             ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N>  */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}
+	stc.l RS,@-r4             ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N>  */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}
+	sts DSR,r4                ;!/* 0000nnnn01101010 sts DSR,<REG_N>	*/{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
+	sts A0,r4                 ;!/* 0000nnnn01111010 sts A0,<REG_N>	*/{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
+	sts X0,r4                 ;!/* 0000nnnn10001010 sts X0,<REG_N>	*/{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
+	sts X1,r4                 ;!/* 0000nnnn10011010 sts X1,<REG_N>	*/{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
+	sts Y0,r4                 ;!/* 0000nnnn10101010 sts Y0,<REG_N>	*/{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
+	sts Y1,r4                 ;!/* 0000nnnn10111010 sts Y1,<REG_N>	*/{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
+	sts.l DSR,@-r4            ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N>	*/{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
+	sts.l A0,@-r4             ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N>	*/{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
+	sts.l X0,@-r4             ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N>	*/{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}
+	sts.l X1,@-r4             ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N>	*/{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}
+	sts.l Y0,@-r4             ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N>	*/{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}
+	sts.l Y1,@-r4             ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N>	*/{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}
+	movs.w @-r4,a1            ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */   {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}
+	movs.w @r4,a1             ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */    {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}
+	movs.w @r4+,a1            ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */   {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}
+	movs.w @r4+r8,a1          ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}
+	movs.w a1,@-r4            ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */   {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}
+	movs.w a1,@r4             ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */    {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}
+	movs.w a1,@r4+            ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */   {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}
+	movs.w a1,@r4+r8          ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}
+	movs.l @-r4,a1            ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */   {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}
+	movs.l @r4,a1             ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */    {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}
+	movs.l @r4+,a1            ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */   {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}
+	movs.l @r4+r8,a1          ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}
+	movs.l a1,@-r4            ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */   {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}
+	movs.l a1,@r4             ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */    {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}
+	movs.l a1,@r4+            ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */   {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}
+	movs.l a1,@r4+r8          ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}
+	nopx                      ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}
+	nopy                      ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}
+	movx.w @r4,x1             ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */    {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}
+	movx.w @r4+,x1            ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */   {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}
+	movx.w @r4+r8,x1          ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}
+	movx.w a1,@r4             ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */    {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}
+	movx.w a1,@r4+            ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */   {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}
+	movx.w a1,@r4+r8          ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}
+	movy.w @r6,y0             ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */    {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}
+	movy.w @r6+,y0            ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */   {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}
+	movy.w @r6+r9,y0          ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}
+	movy.w a1,@r6             ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */    {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}
+	movy.w a1,@r6+            ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */   {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}
+	movy.w a1,@r6+r9          ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}
+	pmuls x0,y0,m0            ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}
+	psubc x1,y0,m0            ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}
+	paddc x1,y0,m0            ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}
+	pcmp x1,y0                ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */  {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}
+	pwsb x1,y0,m0             ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}
+	pwad x1,y0,m0             ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}
+	pabs x1,m0                ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */  {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}
+	pabs y0,m0                ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */  {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}
+	prnd x1,m0                ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */  {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}
+	prnd y0,m0                ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */  {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}
+	dct pshl x1,y0,m0         ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}
+	pshl #4,m0                ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}
+	dct psha x1,y0,m0         ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}
+	psha #4,m0                ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}
+	dct psub x1,y0,m0         ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}
+	dct padd x1,y0,m0         ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}
+	dct pand x1,y0,m0         ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}
+	dct pxor x1,y0,m0         ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}
+	dct por  x1,y0,m0         ;!/* 10110101xxyynnnn por  <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"por",  {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}
+	dct pdec x1,m0            ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */  {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}
+	dct pdec y0,m0            ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */  {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}
+	dct pinc x1,m0            ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */  {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}
+	dct pinc y0,m0            ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */  {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}
+	dct pclr m0               ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */  {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}
+	dct pdmsb x1,m0           ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */  {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}
+	dct pdmsb y0,m0           ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */  {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}
+	dct pneg  x1,m0           ;!/* 11001001xxyynnnn pneg  <DSP_REG_X>,<DSP_REG_N> */  {"pneg",  {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}
+	dct pneg  y0,m0           ;!/* 11101001xxyynnnn pneg  <DSP_REG_Y>,<DSP_REG_N> */  {"pneg",  {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}
+	dct pcopy x1,m0           ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */  {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}
+	dct pcopy y0,m0           ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */  {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}
+	dct psts MACH,m0          ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */  {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}
+	dct psts MACL,m0          ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */  {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}
+	dct plds m0,MACH          ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */  {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}
+	dct plds m0,MACL          ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */  {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}
+
+! Instructions inherited from ancestors: sh sh2
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh.s
new file mode 100644
index 0000000..86de648
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh.s
@@ -0,0 +1,155 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh:
+! Instructions introduced into sh
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+
+! Instructions inherited from ancestors: 
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh2.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2.s
new file mode 100644
index 0000000..3659942
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2.s
@@ -0,0 +1,166 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2 but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2:
+! Instructions introduced into sh2
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+
+! Instructions inherited from ancestors: sh
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s
new file mode 100644
index 0000000..ce93bc9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s
@@ -0,0 +1,168 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2a-nofpu-or-sh3-nommu but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2a-nofpu-or-sh3-nommu.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2a_nofpu_or_sh3_nommu:
+! Instructions introduced into sh2a-nofpu-or-sh3-nommu
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+
+! Instructions inherited from ancestors: sh sh2
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
new file mode 100644
index 0000000..cc350c0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
@@ -0,0 +1,169 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2a-nofpu-or-sh4-nommu-nofpu but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2a-nofpu-or-sh4-nommu-nofpu.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2a_nofpu_or_sh4_nommu_nofpu:
+! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a-nofpu.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a-nofpu.s
new file mode 100644
index 0000000..878a5a3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a-nofpu.s
@@ -0,0 +1,221 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2a-nofpu but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2a-nofpu.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2a-nofpu.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2a_nofpu:
+! Instructions introduced into sh2a-nofpu
+	ldc r5,TBR                ;!/* 0100mmmm01001010 ldc <REG_M>,TBR     */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
+	mov.b R0,@r4+             ;!/* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up}
+	mov.b @-r5,R0             ;!/* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up}
+	mov.b r5,@(2048,r4)       ;!/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */  {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	mov.b @(2048,r5),r4       ;!/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */  {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
+	mov.l R0,@r4+             ;!/* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up}
+	mov.l @-r5,R0             ;!/* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up}
+	mov.l r5,@(2048,r4)       ;!/* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */  {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32}
+	mov.l @(2048,r5),r4       ;!/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */  {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32}
+	mov.w R0,@r4+             ;!/* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up}
+	mov.w @-r5,R0             ;!/* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up}
+	mov.w r5,@(2048,r4)       ;!/* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */  {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32}
+	mov.w @(2048,r5),r4       ;!/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */  {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
+	stc TBR,r4                ;!/* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
+	bclr #4, r4               ;!/* 10000110nnnn0iii bclr #<imm>, <REG_N> */  {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
+	bclr.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */  {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bld #4, r4                ;!/* 10000111nnnn1iii bld #<imm>, <REG_N> */   {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
+	bld.b #4,@(2048,r4)       ;!/* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */  {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bset #4, r4               ;!/* 10000110nnnn1iii bset #<imm>, <REG_N> */  {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
+	bset.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */  {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bst #4, r4                ;!/* 10000111nnnn0iii bst #<imm>, <REG_N> */   {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
+	bst.b #4,@(2048,r4)       ;!/* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */  {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	clips.b r4                ;!/* 0100nnnn10010001 clips.b <REG_N> */       {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up}
+	clips.w r4                ;!/* 0100nnnn10010101 clips.w <REG_N> */       {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up}
+	clipu.b r4                ;!/* 0100nnnn10000001 clipu.b <REG_N> */       {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up}
+	clipu.w r4                ;!/* 0100nnnn10000101 clipu.w <REG_N> */       {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up}
+	divs R0,r4                ;!/* 0100nnnn10010100 divs R0,<REG_N> */       {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up}
+	divu R0,r4                ;!/* 0100nnnn10000100 divu R0,<REG_N> */       {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up}
+	jsr/n @r5                 ;!/* 0100mmmm01001011 jsr/n @<REG_M>  */       {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up}
+	jsr/n @@(8,TBR)           ;!/* 10000011dddddddd jsr/n @@(<disp>,TBR) */  {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up}
+	ldbank @r5,R0             ;!/* 0100mmmm11100101 ldbank @<REG_M>,R0 */    {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up}
+	movml.l r5,@-R15          ;!/* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up}
+	movml.l @R15+,r5          ;!/* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up}
+	movml.l r5,@-R15          ;!/* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up}
+	movml.l @R15+,r5          ;!/* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up}
+	movrt r4                  ;!/* 0000nnnn00111001 movrt <REG_N> */         {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up}
+	mulr R0,r4                ;!/* 0100nnnn10000000 mulr R0,<REG_N> */       {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up}
+	nott                      ;!/* 0000000001101000 nott */                  {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up}
+	resbank                   ;!/* 0000000001011011 resbank */               {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up}
+	rts/n                     ;!/* 0000000001101011 rts/n */                 {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up}
+	rtv/n r5                  ;!/* 0000mmmm01111011 rtv/n <REG_M>*/          {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up}
+	stbank R0,@r4             ;!/* 0100nnnn11100001 stbank R0,@<REG_N>*/     {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up}
+	band.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */  {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bandnot.b #4,@(2048,r4)   ;!/* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */  {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bldnot.b #4,@(2048,r4)    ;!/* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */  {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bor.b #4,@(2048,r4)       ;!/* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */  {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bornot.b #4,@(2048,r4)    ;!/* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */  {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bxor.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */  {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	movi20 #4,r4              ;!/* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */  {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32}
+	movi20s #1024,r4          ;!/* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */  {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32}
+	movu.b @(2048,r5),r4      ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */  {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
+	movu.w @(2048,r5),r4      ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */  {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a-or-sh3e.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a-or-sh3e.s
new file mode 100644
index 0000000..b7be336
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a-or-sh3e.s
@@ -0,0 +1,205 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2a-or-sh3e but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2a-or-sh3e.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2a_or_sh3e:
+! Instructions introduced into sh2a-or-sh3e
+	fsqrt fr1                 ;!/* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,FPUL               ;!/* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
+	lds r5,FPSCR              ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r5+,FPUL           ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
+	lds.l @r5+,FPSCR          ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts FPUL,r4               ;!/* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
+	sts FPSCR,r4              ;!/* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l FPUL,@-r4           ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
+	sts.l FPSCR,@-r4          ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	fabs fr1                  ;!/* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
+	fadd fr2,fr1              ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
+	fcmp/eq fr2,fr1           ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
+	fcmp/gt fr2,fr1           ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
+	fdiv fr2,fr1              ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
+	fldi0 fr1                 ;!/* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
+	fldi1 fr1                 ;!/* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
+	flds fr1,FPUL             ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
+	float FPUL,fr1            ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
+	fmac FR0,fr2,fr1          ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
+	fmov fr2,fr1              ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
+	fmov @r5,fr1              ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov fr2,@r4              ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov @r5+,fr1             ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov fr2,@-r4             ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov @(R0,r5),fr1         ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov fr2,@(R0,r4)         ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmov.s @r5,fr1            ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov.s fr2,@r4            ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov.s @r5+,fr1           ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov.s fr2,@-r4           ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov.s @(R0,r5),fr1       ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov.s fr2,@(R0,r4)       ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmul fr2,fr1              ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
+	fneg fr1                  ;!/* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
+	fsts FPUL,fr1             ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
+	fsub fr2,fr1              ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
+	ftrc fr1,FPUL             ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a-or-sh4.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a-or-sh4.s
new file mode 100644
index 0000000..0200796
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a-or-sh4.s
@@ -0,0 +1,233 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2a-or-sh4 but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2a-or-sh4.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2a_or_sh4:
+! Instructions introduced into sh2a-or-sh4
+	fabs dr2                  ;!/* 1111nnn001011101 fabs <D_REG_N>     */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
+	fadd dr4,dr2              ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
+	fcmp/eq dr4,dr2           ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
+	fcmp/gt dr4,dr2           ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
+	fcnvds dr2,FPUL           ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
+	fcnvsd FPUL,dr2           ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
+	fdiv dr4,dr2              ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
+	float FPUL,dr2            ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
+	fmov xd4,xd2              ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
+	fmov @r5,xd2              ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov xd4,@r4              ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov @r5+,xd2             ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov xd4,@-r4             ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov @(R0,r5),xd2         ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov xd4,@(R0,r4)         ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmov.d @r5,xd2            ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@r4            ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov.d @r5+,xd2           ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@-r4           ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov.d @(R0,r5),xd2       ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@(R0,r4)       ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmul dr4,dr2              ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
+	fneg dr2                  ;!/* 1111nnn001001101 fneg <D_REG_N>     */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
+	fschg                     ;!/* 1111001111111101 fschg               */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
+	fsqrt dr2                 ;!/* 1111nnn001101101 fsqrt <D_REG_N>    */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
+	fsub dr4,dr2              ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
+	ftrc dr2,FPUL             ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,FPUL               ;!/* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
+	lds r5,FPSCR              ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r5+,FPUL           ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
+	lds.l @r5+,FPSCR          ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts FPUL,r4               ;!/* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
+	sts FPSCR,r4              ;!/* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l FPUL,@-r4           ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
+	sts.l FPSCR,@-r4          ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	fabs fr1                  ;!/* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
+	fadd fr2,fr1              ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
+	fcmp/eq fr2,fr1           ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
+	fcmp/gt fr2,fr1           ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
+	fdiv fr2,fr1              ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
+	fldi0 fr1                 ;!/* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
+	fldi1 fr1                 ;!/* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
+	flds fr1,FPUL             ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
+	float FPUL,fr1            ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
+	fmac FR0,fr2,fr1          ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
+	fmov fr2,fr1              ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
+	fmov @r5,fr1              ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov fr2,@r4              ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov @r5+,fr1             ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov fr2,@-r4             ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov @(R0,r5),fr1         ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov fr2,@(R0,r4)         ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmov.s @r5,fr1            ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov.s fr2,@r4            ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov.s @r5+,fr1           ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov.s fr2,@-r4           ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov.s @(R0,r5),fr1       ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov.s fr2,@(R0,r4)       ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmul fr2,fr1              ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
+	fneg fr1                  ;!/* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
+	fsqrt fr1                 ;!/* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
+	fsts FPUL,fr1             ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
+	fsub fr2,fr1              ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
+	ftrc fr1,FPUL             ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a.s
new file mode 100644
index 0000000..04e10f0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2a.s
@@ -0,0 +1,289 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2a but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2a.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2a.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2a:
+! Instructions introduced into sh2a
+	fmov.d xd4,@(2048,r4)     ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <DX_REG_M>,@(<DISP12>,<REG_N>) */  {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32}
+	fmov.d @(2048,r5),xd2     ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),<DX_REG_N> */  {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32}
+	fmov.s fr2,@(2048,r4)     ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */  {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
+	fmov.s @(2048,r5),fr1     ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */  {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r5,TBR                ;!/* 0100mmmm01001010 ldc <REG_M>,TBR     */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,FPUL               ;!/* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
+	lds r5,FPSCR              ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r5+,FPUL           ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
+	lds.l @r5+,FPSCR          ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.b R0,@r4+             ;!/* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up}
+	mov.b @-r5,R0             ;!/* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up}
+	mov.b r5,@(2048,r4)       ;!/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */  {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	mov.b @(2048,r5),r4       ;!/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */  {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.l R0,@r4+             ;!/* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up}
+	mov.l @-r5,R0             ;!/* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up}
+	mov.l r5,@(2048,r4)       ;!/* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */  {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32}
+	mov.l @(2048,r5),r4       ;!/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */  {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	mov.w R0,@r4+             ;!/* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up}
+	mov.w @-r5,R0             ;!/* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up}
+	mov.w r5,@(2048,r4)       ;!/* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */  {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32}
+	mov.w @(2048,r5),r4       ;!/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */  {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc TBR,r4                ;!/* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts FPUL,r4               ;!/* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
+	sts FPSCR,r4              ;!/* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l FPUL,@-r4           ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
+	sts.l FPSCR,@-r4          ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	fabs fr1                  ;!/* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
+	fabs dr2                  ;!/* 1111nnn001011101 fabs <D_REG_N>     */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
+	fadd fr2,fr1              ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
+	fadd dr4,dr2              ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
+	fcmp/eq fr2,fr1           ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
+	fcmp/eq dr4,dr2           ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
+	fcmp/gt fr2,fr1           ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
+	fcmp/gt dr4,dr2           ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
+	fcnvds dr2,FPUL           ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
+	fcnvsd FPUL,dr2           ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
+	fdiv fr2,fr1              ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
+	fdiv dr4,dr2              ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
+	fldi0 fr1                 ;!/* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
+	fldi1 fr1                 ;!/* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
+	flds fr1,FPUL             ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
+	float FPUL,fr1            ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
+	float FPUL,dr2            ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
+	fmac FR0,fr2,fr1          ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
+	fmov fr2,fr1              ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
+	fmov xd4,xd2              ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
+	fmov @r5,fr1              ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov @r5,xd2              ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov fr2,@r4              ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov xd4,@r4              ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov @r5+,fr1             ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov @r5+,xd2             ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov fr2,@-r4             ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov xd4,@-r4             ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov @(R0,r5),fr1         ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov @(R0,r5),xd2         ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov fr2,@(R0,r4)         ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmov xd4,@(R0,r4)         ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmov.d @r5,xd2            ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@r4            ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov.d @r5+,xd2           ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@-r4           ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov.d @(R0,r5),xd2       ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@(R0,r4)       ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmov.s @r5,fr1            ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov.s fr2,@r4            ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov.s @r5+,fr1           ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov.s fr2,@-r4           ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov.s @(R0,r5),fr1       ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov.s fr2,@(R0,r4)       ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmul fr2,fr1              ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
+	fmul dr4,dr2              ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
+	fneg fr1                  ;!/* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
+	fneg dr2                  ;!/* 1111nnn001001101 fneg <D_REG_N>     */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
+	fschg                     ;!/* 1111001111111101 fschg               */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
+	fsqrt fr1                 ;!/* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
+	fsqrt dr2                 ;!/* 1111nnn001101101 fsqrt <D_REG_N>    */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
+	fsts FPUL,fr1             ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
+	fsub fr2,fr1              ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
+	fsub dr4,dr2              ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
+	ftrc fr1,FPUL             ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
+	ftrc dr2,FPUL             ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
+	bclr #4, r4               ;!/* 10000110nnnn0iii bclr #<imm>, <REG_N> */  {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
+	bclr.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */  {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bld #4, r4                ;!/* 10000111nnnn1iii bld #<imm>, <REG_N> */   {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
+	bld.b #4,@(2048,r4)       ;!/* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */  {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bset #4, r4               ;!/* 10000110nnnn1iii bset #<imm>, <REG_N> */  {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up}
+	bset.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */  {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bst #4, r4                ;!/* 10000111nnnn0iii bst #<imm>, <REG_N> */   {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up}
+	bst.b #4,@(2048,r4)       ;!/* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */  {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	clips.b r4                ;!/* 0100nnnn10010001 clips.b <REG_N> */       {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up}
+	clips.w r4                ;!/* 0100nnnn10010101 clips.w <REG_N> */       {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up}
+	clipu.b r4                ;!/* 0100nnnn10000001 clipu.b <REG_N> */       {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up}
+	clipu.w r4                ;!/* 0100nnnn10000101 clipu.w <REG_N> */       {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up}
+	divs R0,r4                ;!/* 0100nnnn10010100 divs R0,<REG_N> */       {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up}
+	divu R0,r4                ;!/* 0100nnnn10000100 divu R0,<REG_N> */       {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up}
+	jsr/n @r5                 ;!/* 0100mmmm01001011 jsr/n @<REG_M>  */       {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up}
+	jsr/n @@(8,TBR)           ;!/* 10000011dddddddd jsr/n @@(<disp>,TBR) */  {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up}
+	ldbank @r5,R0             ;!/* 0100mmmm11100101 ldbank @<REG_M>,R0 */    {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up}
+	movml.l r5,@-R15          ;!/* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up}
+	movml.l @R15+,r5          ;!/* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up}
+	movml.l r5,@-R15          ;!/* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up}
+	movml.l @R15+,r5          ;!/* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up}
+	movrt r4                  ;!/* 0000nnnn00111001 movrt <REG_N> */         {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up}
+	mulr R0,r4                ;!/* 0100nnnn10000000 mulr R0,<REG_N> */       {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up}
+	nott                      ;!/* 0000000001101000 nott */                  {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up}
+	resbank                   ;!/* 0000000001011011 resbank */               {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up}
+	rts/n                     ;!/* 0000000001101011 rts/n */                 {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up}
+	rtv/n r5                  ;!/* 0000mmmm01111011 rtv/n <REG_M>*/          {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up}
+	stbank R0,@r4             ;!/* 0100nnnn11100001 stbank R0,@<REG_N>*/     {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up}
+	band.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */  {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bandnot.b #4,@(2048,r4)   ;!/* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */  {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bldnot.b #4,@(2048,r4)    ;!/* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */  {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bor.b #4,@(2048,r4)       ;!/* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */  {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bornot.b #4,@(2048,r4)    ;!/* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */  {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	bxor.b #4,@(2048,r4)      ;!/* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */  {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32}
+	movi20 #4,r4              ;!/* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */  {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32}
+	movi20s #1024,r4          ;!/* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */  {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32}
+	movu.b @(2048,r5),r4      ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */  {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
+	movu.w @(2048,r5),r4      ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */  {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh2e.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2e.s
new file mode 100644
index 0000000..a62e3ab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh2e.s
@@ -0,0 +1,202 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh2e but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh2e.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh2e.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh2e:
+! Instructions introduced into sh2e
+	lds r4,FPUL               ;!/* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
+	lds r5,FPSCR              ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
+	lds.l @r5+,FPUL           ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
+	lds.l @r5+,FPSCR          ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
+	sts FPUL,r4               ;!/* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
+	sts FPSCR,r4              ;!/* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
+	sts.l FPUL,@-r4           ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
+	sts.l FPSCR,@-r4          ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
+	fabs fr1                  ;!/* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
+	fadd fr2,fr1              ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
+	fcmp/eq fr2,fr1           ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
+	fcmp/gt fr2,fr1           ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
+	fdiv fr2,fr1              ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
+	fldi0 fr1                 ;!/* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
+	fldi1 fr1                 ;!/* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
+	flds fr1,FPUL             ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
+	float FPUL,fr1            ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
+	fmac FR0,fr2,fr1          ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
+	fmov fr2,fr1              ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
+	fmov @r5,fr1              ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov fr2,@r4              ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov @r5+,fr1             ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov fr2,@-r4             ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov @(R0,r5),fr1         ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov fr2,@(R0,r4)         ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmov.s @r5,fr1            ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov.s fr2,@r4            ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov.s @r5+,fr1           ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov.s fr2,@-r4           ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov.s @(R0,r5),fr1       ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov.s fr2,@(R0,r4)       ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmul fr2,fr1              ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
+	fneg fr1                  ;!/* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
+	fsts FPUL,fr1             ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
+	fsub fr2,fr1              ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
+	ftrc fr1,FPUL             ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
+
+! Instructions inherited from ancestors: sh sh2
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh3-dsp.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh3-dsp.s
new file mode 100644
index 0000000..7000596
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh3-dsp.s
@@ -0,0 +1,287 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh3-dsp but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh3-dsp.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh3-dsp.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh3_dsp:
+! Instructions introduced into sh3-dsp
+
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,MOD                ;!/* 0100nnnn01011110 ldc <REG_N>,MOD     */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}
+	ldc r4,RE                 ;!/* 0100nnnn01111110 ldc <REG_N>,RE     */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}
+	ldc r4,RS                 ;!/* 0100nnnn01101110 ldc <REG_N>,RS     */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,MOD            ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,RE             ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,RS             ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	ldre @(8,PC)              ;!/* 10001110i8p2.... ldre @(<disp>,PC)	*/{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}
+	ldrs @(8,PC)              ;!/* 10001100i8p2.... ldrs @(<disp>,PC)	*/{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,DSR                ;!/* 0100nnnn01101010 lds <REG_N>,DSR	*/{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
+	lds r4,A0                 ;!/* 0100nnnn01111010 lds <REG_N>,A0	*/{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
+	lds r4,X0                 ;!/* 0100nnnn10001010 lds <REG_N>,X0	*/{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
+	lds r4,X1                 ;!/* 0100nnnn10011010 lds <REG_N>,X1	*/{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
+	lds r4,Y0                 ;!/* 0100nnnn10101010 lds <REG_N>,Y0	*/{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
+	lds r4,Y1                 ;!/* 0100nnnn10111010 lds <REG_N>,Y1	*/{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r4+,DSR            ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR	*/{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,A0             ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0	*/{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,X0             ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0	*/{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,X1             ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1	*/{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,Y0             ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0	*/{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,Y1             ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1	*/{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	setrc r4                  ;!/* 0100nnnn00010100 setrc <REG_N>       */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
+	setrc #4                  ;!/* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
+	repeat 10 20 r4           ;!/* repeat start end <REG_N>       	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
+	repeat 10 20 #4           ;!/* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc MOD,r4                ;!/* 0000nnnn01010010 stc MOD,<REG_N>     */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}
+	stc RE,r4                 ;!/* 0000nnnn01110010 stc RE,<REG_N>     */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
+	stc RS,r4                 ;!/* 0000nnnn01100010 stc RS,<REG_N>     */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l MOD,@-r4            ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}
+	stc.l RE,@-r4             ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N>  */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}
+	stc.l RS,@-r4             ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N>  */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts DSR,r4                ;!/* 0000nnnn01101010 sts DSR,<REG_N>	*/{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
+	sts A0,r4                 ;!/* 0000nnnn01111010 sts A0,<REG_N>	*/{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
+	sts X0,r4                 ;!/* 0000nnnn10001010 sts X0,<REG_N>	*/{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
+	sts X1,r4                 ;!/* 0000nnnn10011010 sts X1,<REG_N>	*/{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
+	sts Y0,r4                 ;!/* 0000nnnn10101010 sts Y0,<REG_N>	*/{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
+	sts Y1,r4                 ;!/* 0000nnnn10111010 sts Y1,<REG_N>	*/{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l DSR,@-r4            ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N>	*/{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
+	sts.l A0,@-r4             ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N>	*/{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
+	sts.l X0,@-r4             ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N>	*/{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}
+	sts.l X1,@-r4             ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N>	*/{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}
+	sts.l Y0,@-r4             ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N>	*/{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}
+	sts.l Y1,@-r4             ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N>	*/{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	movs.w @-r4,a1            ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */   {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}
+	movs.w @r4,a1             ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */    {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}
+	movs.w @r4+,a1            ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */   {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}
+	movs.w @r4+r8,a1          ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}
+	movs.w a1,@-r4            ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */   {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}
+	movs.w a1,@r4             ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */    {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}
+	movs.w a1,@r4+            ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */   {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}
+	movs.w a1,@r4+r8          ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}
+	movs.l @-r4,a1            ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */   {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}
+	movs.l @r4,a1             ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */    {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}
+	movs.l @r4+,a1            ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */   {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}
+	movs.l @r4+r8,a1          ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}
+	movs.l a1,@-r4            ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */   {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}
+	movs.l a1,@r4             ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */    {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}
+	movs.l a1,@r4+            ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */   {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}
+	movs.l a1,@r4+r8          ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}
+	nopx                      ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}
+	nopy                      ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}
+	movx.w @r4,x1             ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */    {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}
+	movx.w @r4+,x1            ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */   {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}
+	movx.w @r4+r8,x1          ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}
+	movx.w a1,@r4             ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */    {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}
+	movx.w a1,@r4+            ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */   {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}
+	movx.w a1,@r4+r8          ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}
+	movy.w @r6,y0             ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */    {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}
+	movy.w @r6+,y0            ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */   {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}
+	movy.w @r6+r9,y0          ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}
+	movy.w a1,@r6             ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */    {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}
+	movy.w a1,@r6+            ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */   {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}
+	movy.w a1,@r6+r9          ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}
+	pmuls x0,y0,m0            ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}
+	psubc x1,y0,m0            ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}
+	paddc x1,y0,m0            ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}
+	pcmp x1,y0                ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */  {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}
+	pwsb x1,y0,m0             ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}
+	pwad x1,y0,m0             ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}
+	pabs x1,m0                ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */  {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}
+	pabs y0,m0                ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */  {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}
+	prnd x1,m0                ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */  {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}
+	prnd y0,m0                ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */  {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}
+	dct pshl x1,y0,m0         ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}
+	pshl #4,m0                ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}
+	dct psha x1,y0,m0         ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}
+	psha #4,m0                ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}
+	dct psub x1,y0,m0         ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}
+	dct padd x1,y0,m0         ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}
+	dct pand x1,y0,m0         ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}
+	dct pxor x1,y0,m0         ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}
+	dct por  x1,y0,m0         ;!/* 10110101xxyynnnn por  <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"por",  {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}
+	dct pdec x1,m0            ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */  {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}
+	dct pdec y0,m0            ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */  {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}
+	dct pinc x1,m0            ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */  {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}
+	dct pinc y0,m0            ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */  {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}
+	dct pclr m0               ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */  {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}
+	dct pdmsb x1,m0           ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */  {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}
+	dct pdmsb y0,m0           ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */  {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}
+	dct pneg  x1,m0           ;!/* 11001001xxyynnnn pneg  <DSP_REG_X>,<DSP_REG_N> */  {"pneg",  {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}
+	dct pneg  y0,m0           ;!/* 11101001xxyynnnn pneg  <DSP_REG_Y>,<DSP_REG_N> */  {"pneg",  {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}
+	dct pcopy x1,m0           ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */  {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}
+	dct pcopy y0,m0           ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */  {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}
+	dct psts MACH,m0          ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */  {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}
+	dct psts MACL,m0          ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */  {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}
+	dct plds m0,MACH          ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */  {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}
+	dct plds m0,MACL          ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */  {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh3-nommu.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh3-nommu.s
new file mode 100644
index 0000000..bc6096e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh3-nommu.s
@@ -0,0 +1,180 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh3-nommu but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh3-nommu.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh3-nommu.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh3_nommu:
+! Instructions introduced into sh3-nommu
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh3.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh3.s
new file mode 100644
index 0000000..5e031c0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh3.s
@@ -0,0 +1,181 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh3 but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh3.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh3.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh3:
+! Instructions introduced into sh3
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh3e.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh3e.s
new file mode 100644
index 0000000..7076dfc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh3e.s
@@ -0,0 +1,218 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh3e but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh3e.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh3e.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh3e:
+! Instructions introduced into sh3e
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,FPUL               ;!/* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
+	lds r5,FPSCR              ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r5+,FPUL           ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
+	lds.l @r5+,FPSCR          ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts FPUL,r4               ;!/* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
+	sts FPSCR,r4              ;!/* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l FPUL,@-r4           ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
+	sts.l FPSCR,@-r4          ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	fabs fr1                  ;!/* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
+	fadd fr2,fr1              ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
+	fcmp/eq fr2,fr1           ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
+	fcmp/gt fr2,fr1           ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
+	fdiv fr2,fr1              ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
+	fldi0 fr1                 ;!/* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
+	fldi1 fr1                 ;!/* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
+	flds fr1,FPUL             ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
+	float FPUL,fr1            ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
+	fmac FR0,fr2,fr1          ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
+	fmov fr2,fr1              ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
+	fmov @r5,fr1              ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov fr2,@r4              ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov @r5+,fr1             ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov fr2,@-r4             ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov @(R0,r5),fr1         ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov fr2,@(R0,r4)         ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmov.s @r5,fr1            ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov.s fr2,@r4            ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov.s @r5+,fr1           ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov.s fr2,@-r4           ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov.s @(R0,r5),fr1       ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov.s fr2,@(R0,r4)       ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmul fr2,fr1              ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
+	fneg fr1                  ;!/* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
+	fsqrt fr1                 ;!/* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
+	fsts FPUL,fr1             ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
+	fsub fr2,fr1              ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
+	ftrc fr1,FPUL             ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh4-nofpu.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh4-nofpu.s
new file mode 100644
index 0000000..fb225a1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh4-nofpu.s
@@ -0,0 +1,194 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh4-nofpu but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh4-nofpu.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh4-nofpu.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh4_nofpu:
+! Instructions introduced into sh4-nofpu
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,SGR                ;!/* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,DBR                ;!/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SGR            ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,DBR            ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movca.l R0,@r4            ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	ocbi @r4                  ;!/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbp @r4                  ;!/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbwb @r4                 ;!/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc SGR,r4                ;!/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc DBR,r4                ;!/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l SGR,@-r4            ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l DBR,@-r4            ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh4-nommu-nofpu.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh4-nommu-nofpu.s
new file mode 100644
index 0000000..fc2877a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh4-nommu-nofpu.s
@@ -0,0 +1,193 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh4-nommu-nofpu but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh4-nommu-nofpu.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh4_nommu_nofpu:
+! Instructions introduced into sh4-nommu-nofpu
+	ldc r4,SGR                ;!/* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,DBR                ;!/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,SGR            ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,DBR            ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
+	movca.l R0,@r4            ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbi @r4                  ;!/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbp @r4                  ;!/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbwb @r4                 ;!/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
+	stc SGR,r4                ;!/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc DBR,r4                ;!/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc.l SGR,@-r4            ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l DBR,@-r4            ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh4.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh4.s
new file mode 100644
index 0000000..5b1c980
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh4.s
@@ -0,0 +1,263 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh4 but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh4.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh4.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh4:
+! Instructions introduced into sh4
+	fipr fv4,fv0              ;!/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}
+	frchg                     ;!/* 1111101111111101 frchg               */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}
+	fsca FPUL,dr2             ;!/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}
+	fsrra fr1                 ;!/* 1111nnnn01111101 fsrra <F_REG_N>    */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
+	ftrv xmtrx,fv0            ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,SGR                ;!/* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,DBR                ;!/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SGR            ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,DBR            ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,FPUL               ;!/* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
+	lds r5,FPSCR              ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r5+,FPUL           ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
+	lds.l @r5+,FPSCR          ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movca.l R0,@r4            ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	ocbi @r4                  ;!/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbp @r4                  ;!/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbwb @r4                 ;!/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc SGR,r4                ;!/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc DBR,r4                ;!/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l SGR,@-r4            ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l DBR,@-r4            ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts FPUL,r4               ;!/* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
+	sts FPSCR,r4              ;!/* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l FPUL,@-r4           ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
+	sts.l FPSCR,@-r4          ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	fabs fr1                  ;!/* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
+	fabs dr2                  ;!/* 1111nnn001011101 fabs <D_REG_N>     */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
+	fadd fr2,fr1              ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
+	fadd dr4,dr2              ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
+	fcmp/eq fr2,fr1           ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
+	fcmp/eq dr4,dr2           ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
+	fcmp/gt fr2,fr1           ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
+	fcmp/gt dr4,dr2           ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
+	fcnvds dr2,FPUL           ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
+	fcnvsd FPUL,dr2           ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
+	fdiv fr2,fr1              ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
+	fdiv dr4,dr2              ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
+	fldi0 fr1                 ;!/* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
+	fldi1 fr1                 ;!/* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
+	flds fr1,FPUL             ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
+	float FPUL,fr1            ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
+	float FPUL,dr2            ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
+	fmac FR0,fr2,fr1          ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
+	fmov fr2,fr1              ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
+	fmov xd4,xd2              ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
+	fmov @r5,fr1              ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov @r5,xd2              ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov fr2,@r4              ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov xd4,@r4              ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov @r5+,fr1             ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov @r5+,xd2             ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov fr2,@-r4             ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov xd4,@-r4             ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov @(R0,r5),fr1         ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov @(R0,r5),xd2         ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov fr2,@(R0,r4)         ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmov xd4,@(R0,r4)         ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmov.d @r5,xd2            ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@r4            ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov.d @r5+,xd2           ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@-r4           ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov.d @(R0,r5),xd2       ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@(R0,r4)       ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmov.s @r5,fr1            ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov.s fr2,@r4            ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov.s @r5+,fr1           ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov.s fr2,@-r4           ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov.s @(R0,r5),fr1       ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov.s fr2,@(R0,r4)       ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmul fr2,fr1              ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
+	fmul dr4,dr2              ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
+	fneg fr1                  ;!/* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
+	fneg dr2                  ;!/* 1111nnn001001101 fneg <D_REG_N>     */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
+	fschg                     ;!/* 1111001111111101 fschg               */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
+	fsqrt fr1                 ;!/* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
+	fsqrt dr2                 ;!/* 1111nnn001101101 fsqrt <D_REG_N>    */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
+	fsts FPUL,fr1             ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
+	fsub fr2,fr1              ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
+	fsub dr4,dr2              ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
+	ftrc fr1,FPUL             ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
+	ftrc dr2,FPUL             ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh4a-nofpu.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh4a-nofpu.s
new file mode 100644
index 0000000..202db6f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh4a-nofpu.s
@@ -0,0 +1,201 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh4a-nofpu but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh4a-nofpu.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh4a-nofpu.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh4a_nofpu:
+! Instructions introduced into sh4a-nofpu
+	icbi @r4                  ;!/* 0000nnnn11100011 icbi @<REG_N>       */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up}
+	movco.l r0,@r4            ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up}
+	movli.l @r5,r0            ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up}
+	movua.l @r5,r0            ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up}
+	movua.l @r5+,r0           ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up}
+	prefi @r4                 ;!/* 0000nnnn11010011 prefi @<REG_N>      */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
+	synco                     ;!/* 0000000010101011 synco               */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,SGR                ;!/* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,DBR                ;!/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SGR            ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,DBR            ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movca.l R0,@r4            ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	ocbi @r4                  ;!/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbp @r4                  ;!/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbwb @r4                 ;!/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc SGR,r4                ;!/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc DBR,r4                ;!/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l SGR,@-r4            ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l DBR,@-r4            ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh4a.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh4a.s
new file mode 100644
index 0000000..c710ddc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh4a.s
@@ -0,0 +1,271 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh4a but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh4a.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh4a.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh4a:
+! Instructions introduced into sh4a
+	fpchg                     ;!/* 1111011111111101 fpchg               */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
+
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	icbi @r4                  ;!/* 0000nnnn11100011 icbi @<REG_N>       */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,SGR                ;!/* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,DBR                ;!/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SGR            ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,DBR            ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,FPUL               ;!/* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}
+	lds r5,FPSCR              ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r5+,FPUL           ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}
+	lds.l @r5+,FPSCR          ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movca.l R0,@r4            ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
+	movco.l r0,@r4            ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up}
+	movli.l @r5,r0            ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	movua.l @r5,r0            ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up}
+	movua.l @r5+,r0           ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	ocbi @r4                  ;!/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbp @r4                  ;!/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbwb @r4                 ;!/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	prefi @r4                 ;!/* 0000nnnn11010011 prefi @<REG_N>      */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc SGR,r4                ;!/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc DBR,r4                ;!/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l SGR,@-r4            ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l DBR,@-r4            ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts FPUL,r4               ;!/* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}
+	sts FPSCR,r4              ;!/* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l FPUL,@-r4           ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}
+	sts.l FPSCR,@-r4          ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	synco                     ;!/* 0000000010101011 synco               */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	fabs fr1                  ;!/* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}
+	fabs dr2                  ;!/* 1111nnn001011101 fabs <D_REG_N>     */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up}
+	fadd fr2,fr1              ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}
+	fadd dr4,dr2              ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up}
+	fcmp/eq fr2,fr1           ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
+	fcmp/eq dr4,dr2           ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
+	fcmp/gt fr2,fr1           ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
+	fcmp/gt dr4,dr2           ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
+	fcnvds dr2,FPUL           ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up}
+	fcnvsd FPUL,dr2           ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up}
+	fdiv fr2,fr1              ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}
+	fdiv dr4,dr2              ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up}
+	fipr fv4,fv0              ;!/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}
+	fldi0 fr1                 ;!/* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}
+	fldi1 fr1                 ;!/* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}
+	flds fr1,FPUL             ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}
+	float FPUL,fr1            ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}
+	float FPUL,dr2            ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up}
+	fmac FR0,fr2,fr1          ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}
+	fmov fr2,fr1              ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}
+	fmov xd4,xd2              ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up}
+	fmov @r5,fr1              ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov @r5,xd2              ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov fr2,@r4              ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov xd4,@r4              ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov @r5+,fr1             ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov @r5+,xd2             ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov fr2,@-r4             ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov xd4,@-r4             ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov @(R0,r5),fr1         ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov @(R0,r5),xd2         ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov fr2,@(R0,r4)         ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmov xd4,@(R0,r4)         ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmov.d @r5,xd2            ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@r4            ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up}
+	fmov.d @r5+,xd2           ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@-r4           ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up}
+	fmov.d @(R0,r5),xd2       ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up}
+	fmov.d xd4,@(R0,r4)       ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up}
+	fmov.s @r5,fr1            ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}
+	fmov.s fr2,@r4            ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}
+	fmov.s @r5+,fr1           ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}
+	fmov.s fr2,@-r4           ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}
+	fmov.s @(R0,r5),fr1       ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}
+	fmov.s fr2,@(R0,r4)       ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}
+	fmul fr2,fr1              ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}
+	fmul dr4,dr2              ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up}
+	fneg fr1                  ;!/* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}
+	fneg dr2                  ;!/* 1111nnn001001101 fneg <D_REG_N>     */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up}
+	frchg                     ;!/* 1111101111111101 frchg               */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}
+	fsca FPUL,dr2             ;!/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}
+	fschg                     ;!/* 1111001111111101 fschg               */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up}
+	fsqrt fr1                 ;!/* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
+	fsqrt dr2                 ;!/* 1111nnn001101101 fsqrt <D_REG_N>    */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up}
+	fsrra fr1                 ;!/* 1111nnnn01111101 fsrra <F_REG_N>    */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
+	fsts FPUL,fr1             ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}
+	fsub fr2,fr1              ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}
+	fsub dr4,dr2              ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
+	ftrc fr1,FPUL             ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}
+	ftrc dr2,FPUL             ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
+	ftrv xmtrx,fv0            ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/arch/sh4al-dsp.s b/binutils-2.19/ld/testsuite/ld-sh/arch/sh4al-dsp.s
new file mode 100644
index 0000000..8d48962
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/arch/sh4al-dsp.s
@@ -0,0 +1,343 @@
+! Generated file. DO NOT EDIT.
+!
+! This file was generated by gas/testsuite/gas/sh/arch/arch.exp .
+! This file should contain every instruction valid on
+! architecture sh4al-dsp but no more.
+! If the tests are failing because the expected results
+! have changed then run 'make check' and copy the new file
+! from <objdir>/gas/testsuite/sh4al-dsp.s
+! to   <srcdir>/gas/testsuite/gas/sh/arch/sh4al-dsp.s .
+! Make sure there are no unexpected or missing instructions.
+
+	.section .text
+sh4al_dsp:
+! Instructions introduced into sh4al-dsp
+	clrdmxy                   ;!/* 0000000010001000 clrdmxy             */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up}
+	ldrc r5                   ;!/* 0100mmmm00110100 ldrc <REG_M>        */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up}
+	ldrc #4                   ;!/* 10001010i8*1.... ldrc #<imm>         */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up}
+	setdmx                    ;!/* 0000000010011000 setdmx              */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up}
+	setdmy                    ;!/* 0000000011001000 setdmy              */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up}
+	movx.w @r1,y1             ;!/* nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> */ {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up}
+	movx.w @r1+,y1            ;!/* nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> */{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up}
+	movx.w @r1+r8,y1          ;!/* nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up}
+	movx.w a0,@r1             ;!/* nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> */ {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up}
+	movx.w a0,@r1+            ;!/* nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ */{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up}
+	movx.w a0,@r1+r8          ;!/* nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up}
+	movx.l @r1,y1             ;!/* nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> */ {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up}
+	movx.l @r1+,y1            ;!/* nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> */{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up}
+	movx.l @r1+r8,y1          ;!/* nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up}
+	movx.l a0,@r1             ;!/* nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> */ {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up}
+	movx.l a0,@r1+            ;!/* nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ */{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up}
+	movx.l a0,@r1+r8          ;!/* nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up}
+	movy.w @r3,y1             ;!/* nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> */ {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up}
+	movy.w @r3+,y1            ;!/* nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> */{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up}
+	movy.w @r3+r9,y1          ;!/* nnmm000011 movy.w @<REG_Ayx>+r9,<DSP_REG_YX> */{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up}
+	movy.w a0,@r3             ;!/* nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> */ {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up}
+	movy.w a0,@r3+            ;!/* nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up}
+	movy.w a0,@r3+r9          ;!/* nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r9 */{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up}
+	movy.l @r3,y1             ;!/* nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> */ {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up}
+	movy.l @r3+,y1            ;!/* nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> */{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up}
+	movy.l @r3+r9,y1          ;!/* nnmm100011 movy.l @<REG_Ayx>+r9,<DSP_REG_YX> */{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up}
+	movy.l a0,@r3             ;!/* nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> */ {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up}
+	movy.l a0,@r3+            ;!/* nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up}
+	movy.l a0,@r3+r9          ;!/* nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r9 */{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up}
+	dct pabs x1,m0            ;!/* 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> */  {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up}
+	dct pabs y0,m0            ;!/* 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */  {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up}
+	dct prnd x1,m0            ;!/* 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> */  {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up}
+	dct prnd y0,m0            ;!/* 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */  {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up}
+	dct psub y0,x1,m0         ;!/* 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> */  {"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up}
+	dct pswap x1,m0           ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */  {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
+	dct pswap y0,m0           ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */  {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
+
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
+	add #4,r4                 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
+	add r5,r4                 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
+	addc r5,r4                ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
+	addv r5,r4                ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up}
+	and #4,R0                 ;!/* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up}
+	and r5,r4                 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up}
+	and.b #4,@(R0,GBR)        ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up}
+	bra .+8                   ;!/* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up}
+	bsr .+8                   ;!/* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up}
+	bt .+8                    ;!/* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up}
+	bf .+8                    ;!/* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up}
+	bt.s .+8                  ;!/* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bt/s .+8                  ;!/* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up}
+	bf.s .+8                  ;!/* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	bf/s .+8                  ;!/* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}
+	clrmac                    ;!/* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up}
+	clrs                      ;!/* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up}
+	clrt                      ;!/* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up}
+	cmp/eq #4,R0              ;!/* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up}
+	cmp/eq r5,r4              ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up}
+	cmp/ge r5,r4              ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up}
+	cmp/gt r5,r4              ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up}
+	cmp/hi r5,r4              ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up}
+	cmp/hs r5,r4              ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up}
+	cmp/pl r4                 ;!/* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up}
+	cmp/pz r4                 ;!/* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up}
+	cmp/str r5,r4             ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up}
+	div0s r5,r4               ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up}
+	div0u                     ;!/* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up}
+	div1 r5,r4                ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up}
+	exts.b r5,r4              ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up}
+	exts.w r5,r4              ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up}
+	extu.b r5,r4              ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up}
+	extu.w r5,r4              ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up}
+	icbi @r4                  ;!/* 0000nnnn11100011 icbi @<REG_N>       */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up}
+	jmp @r4                   ;!/* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up}
+	jsr @r4                   ;!/* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up}
+	ldc r4,SR                 ;!/* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up}
+	ldc r4,GBR                ;!/* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up}
+	ldc r4,SGR                ;!/* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,VBR                ;!/* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up}
+	ldc r4,MOD                ;!/* 0100nnnn01011110 ldc <REG_N>,MOD     */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up}
+	ldc r4,RE                 ;!/* 0100nnnn01111110 ldc <REG_N>,RE     */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up}
+	ldc r4,RS                 ;!/* 0100nnnn01101110 ldc <REG_N>,RS     */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up}
+	ldc r4,SSR                ;!/* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,SPC                ;!/* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up}
+	ldc r4,DBR                ;!/* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	ldc r4,r1_bank            ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up}
+	ldc.l @r4+,SR             ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up}
+	ldc.l @r4+,GBR            ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up}
+	ldc.l @r4+,VBR            ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up}
+	ldc.l @r4+,SGR            ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,MOD            ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,RE             ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,RS             ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up}
+	ldc.l @r4+,SSR            ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,SPC            ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up}
+	ldc.l @r4+,DBR            ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up}
+	ldc.l @r4+,r1_bank        ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up}
+	ldre @(8,PC)              ;!/* 10001110i8p2.... ldre @(<disp>,PC)	*/{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}
+	ldrs @(8,PC)              ;!/* 10001100i8p2.... ldrs @(<disp>,PC)	*/{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}
+	lds r4,MACH               ;!/* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	lds r4,MACL               ;!/* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	lds r4,PR                 ;!/* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	lds r4,DSR                ;!/* 0100nnnn01101010 lds <REG_N>,DSR	*/{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
+	lds r4,A0                 ;!/* 0100nnnn01111010 lds <REG_N>,A0	*/{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
+	lds r4,X0                 ;!/* 0100nnnn10001010 lds <REG_N>,X0	*/{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
+	lds r4,X1                 ;!/* 0100nnnn10011010 lds <REG_N>,X1	*/{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
+	lds r4,Y0                 ;!/* 0100nnnn10101010 lds <REG_N>,Y0	*/{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
+	lds r4,Y1                 ;!/* 0100nnnn10111010 lds <REG_N>,Y1	*/{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
+	lds.l @r4+,MACH           ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up}
+	lds.l @r4+,MACL           ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up}
+	lds.l @r4+,PR             ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up}
+	lds.l @r4+,DSR            ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR	*/{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,A0             ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0	*/{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,X0             ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0	*/{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,X1             ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1	*/{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,Y0             ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0	*/{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up}
+	lds.l @r4+,Y1             ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1	*/{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}
+	ldtlb                     ;!/* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
+	mac.w @r5+,@r4+           ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mov #4,r4                 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up}
+	mov r5,r4                 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up}
+	mov.b r5,@(R0,r4)         ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@-r4             ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b r5,@r4              ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b @(8,r5),R0          ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up}
+	mov.b @(8,GBR),R0         ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up}
+	mov.b @(R0,r5),r4         ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up}
+	mov.b @r5+,r4             ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up}
+	mov.b @r5,r4              ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up}
+	mov.b R0,@(8,r5)          ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up}
+	mov.b R0,@(8,GBR)         ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up}
+	mov.l r5,@(8,r4)          ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up}
+	mov.l r5,@(R0,r4)         ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@-r4             ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l r5,@r4              ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l @(8,r5),r4          ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up}
+	mov.l @(8,GBR),R0         ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up}
+	.align 2
+	mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up}
+	mov.l @(R0,r5),r4         ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mov.l @r5+,r4             ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up}
+	mov.l @r5,r4              ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up}
+	mov.l R0,@(8,GBR)         ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up}
+	mov.w r5,@(R0,r4)         ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@-r4             ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w r5,@r4              ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w @(8,r5),R0          ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up}
+	mov.w @(8,GBR),R0         ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up}
+	mov.w @(8,PC),r4          ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up}
+	mov.w @(R0,r5),r4         ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up}
+	mov.w @r5+,r4             ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up}
+	mov.w @r5,r4              ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up}
+	mov.w R0,@(8,r5)          ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up}
+	mov.w R0,@(8,GBR)         ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up}
+	.align 2
+	mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up}
+	movca.l R0,@r4            ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up}
+	movco.l r0,@r4            ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up}
+	movli.l @r5,r0            ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up}
+	movt r4                   ;!/* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	movua.l @r5,r0            ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up}
+	movua.l @r5+,r0           ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up}
+	muls.w r5,r4              ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	muls r5,r4                ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up}
+	mul.l r5,r4               ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up}
+	mulu.w r5,r4              ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	mulu r5,r4                ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up}
+	neg r5,r4                 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up}
+	negc r5,r4                ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up}
+	nop                       ;!/* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up}
+	not r5,r4                 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up}
+	ocbi @r4                  ;!/* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbp @r4                  ;!/* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up}
+	ocbwb @r4                 ;!/* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up}
+	or #4,R0                  ;!/* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up}
+	or r5,r4                  ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up}
+	or.b #4,@(R0,GBR)         ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up}
+	pref @r4                  ;!/* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up}
+	prefi @r4                 ;!/* 0000nnnn11010011 prefi @<REG_N>      */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
+	rotcl r4                  ;!/* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up}
+	rotcr r4                  ;!/* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up}
+	rotl r4                   ;!/* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up}
+	rotr r4                   ;!/* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up}
+	rte                       ;!/* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
+	rts                       ;!/* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
+	sets                      ;!/* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up}
+	sett                      ;!/* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
+	setrc r4                  ;!/* 0100nnnn00010100 setrc <REG_N>       */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
+	setrc #4                  ;!/* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
+	repeat 10 20 r4           ;!/* repeat start end <REG_N>       	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
+	repeat 10 20 #4           ;!/* repeat start end #<imm>        	*/{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
+	shad r5,r4                ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shld r5,r4                ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
+	shal r4                   ;!/* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
+	shar r4                   ;!/* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
+	shll r4                   ;!/* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
+	shll16 r4                 ;!/* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up}
+	shll2 r4                  ;!/* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up}
+	shll8 r4                  ;!/* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up}
+	shlr r4                   ;!/* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up}
+	shlr16 r4                 ;!/* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up}
+	shlr2 r4                  ;!/* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up}
+	shlr8 r4                  ;!/* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up}
+	sleep                     ;!/* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up}
+	stc SR,r4                 ;!/* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	stc GBR,r4                ;!/* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	stc VBR,r4                ;!/* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	stc MOD,r4                ;!/* 0000nnnn01010010 stc MOD,<REG_N>     */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up}
+	stc RE,r4                 ;!/* 0000nnnn01110010 stc RE,<REG_N>     */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
+	stc RS,r4                 ;!/* 0000nnnn01100010 stc RS,<REG_N>     */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
+	stc SSR,r4                ;!/* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up}
+	stc SPC,r4                ;!/* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up}
+	stc SGR,r4                ;!/* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc DBR,r4                ;!/* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up}
+	stc r1_bank,r4            ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up}
+	stc.l SR,@-r4             ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up}
+	stc.l VBR,@-r4            ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up}
+	stc.l MOD,@-r4            ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up}
+	stc.l RE,@-r4             ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N>  */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up}
+	stc.l RS,@-r4             ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N>  */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up}
+	stc.l SSR,@-r4            ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up}
+	stc.l SPC,@-r4            ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
+	stc.l GBR,@-r4            ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up}
+	stc.l SGR,@-r4            ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l DBR,@-r4            ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
+	stc.l r1_bank,@-r4        ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
+	sts MACH,r4               ;!/* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up}
+	sts MACL,r4               ;!/* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up}
+	sts PR,r4                 ;!/* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up}
+	sts DSR,r4                ;!/* 0000nnnn01101010 sts DSR,<REG_N>	*/{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up}
+	sts A0,r4                 ;!/* 0000nnnn01111010 sts A0,<REG_N>	*/{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up}
+	sts X0,r4                 ;!/* 0000nnnn10001010 sts X0,<REG_N>	*/{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up}
+	sts X1,r4                 ;!/* 0000nnnn10011010 sts X1,<REG_N>	*/{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up}
+	sts Y0,r4                 ;!/* 0000nnnn10101010 sts Y0,<REG_N>	*/{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up}
+	sts Y1,r4                 ;!/* 0000nnnn10111010 sts Y1,<REG_N>	*/{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}
+	sts.l MACH,@-r4           ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up}
+	sts.l MACL,@-r4           ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up}
+	sts.l PR,@-r4             ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up}
+	sts.l DSR,@-r4            ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N>	*/{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up}
+	sts.l A0,@-r4             ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N>	*/{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up}
+	sts.l X0,@-r4             ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N>	*/{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up}
+	sts.l X1,@-r4             ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N>	*/{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up}
+	sts.l Y0,@-r4             ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N>	*/{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up}
+	sts.l Y1,@-r4             ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N>	*/{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}
+	sub r5,r4                 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up}
+	subc r5,r4                ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up}
+	subv r5,r4                ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up}
+	swap.b r5,r4              ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up}
+	swap.w r5,r4              ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up}
+	synco                     ;!/* 0000000010101011 synco               */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
+	tas.b @r4                 ;!/* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up}
+	trapa #4                  ;!/* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up}
+	tst #4,R0                 ;!/* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up}
+	tst r5,r4                 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up}
+	tst.b #4,@(R0,GBR)        ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up}
+	xor #4,R0                 ;!/* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up}
+	xor r5,r4                 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up}
+	xor.b #4,@(R0,GBR)        ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up}
+	xtrct r5,r4               ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up}
+	dt r4                     ;!/* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up}
+	dmuls.l r5,r4             ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up}
+	dmulu.l r5,r4             ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up}
+	mac.l @r5+,@r4+           ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up}
+	braf r4                   ;!/* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up}
+	bsrf r4                   ;!/* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up}
+	movs.w @-r4,a1            ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */   {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up}
+	movs.w @r4,a1             ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */    {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up}
+	movs.w @r4+,a1            ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */   {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}
+	movs.w @r4+r8,a1          ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}
+	movs.w a1,@-r4            ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */   {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}
+	movs.w a1,@r4             ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */    {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up}
+	movs.w a1,@r4+            ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */   {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}
+	movs.w a1,@r4+r8          ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}
+	movs.l @-r4,a1            ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */   {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}
+	movs.l @r4,a1             ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */    {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up}
+	movs.l @r4+,a1            ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */   {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}
+	movs.l @r4+r8,a1          ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}
+	movs.l a1,@-r4            ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */   {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}
+	movs.l a1,@r4             ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */    {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up}
+	movs.l a1,@r4+            ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */   {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}
+	movs.l a1,@r4+r8          ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}
+	nopx                      ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}
+	nopy                      ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}
+	movx.w @r4,x1             ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */    {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}
+	movx.w @r4+,x1            ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */   {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}
+	movx.w @r4+r8,x1          ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}
+	movx.w a1,@r4             ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */    {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}
+	movx.w a1,@r4+            ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */   {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}
+	movx.w a1,@r4+r8          ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}
+	movy.w @r6,y0             ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */    {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}
+	movy.w @r6+,y0            ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */   {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}
+	movy.w @r6+r9,y0          ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}
+	movy.w a1,@r6             ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */    {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}
+	movy.w a1,@r6+            ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */   {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}
+	movy.w a1,@r6+r9          ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}
+	pmuls x0,y0,m0            ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}
+	psubc x1,y0,m0            ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up}
+	paddc x1,y0,m0            ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up}
+	pcmp x1,y0                ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */  {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up}
+	pwsb x1,y0,m0             ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up}
+	pwad x1,y0,m0             ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}
+	pabs x1,m0                ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */  {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}
+	pabs y0,m0                ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */  {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}
+	prnd x1,m0                ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */  {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}
+	prnd y0,m0                ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */  {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}
+	dct pshl x1,y0,m0         ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up}
+	pshl #4,m0                ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up}
+	dct psha x1,y0,m0         ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up}
+	psha #4,m0                ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}
+	dct psub x1,y0,m0         ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}
+	dct padd x1,y0,m0         ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}
+	dct pand x1,y0,m0         ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up}
+	dct pxor x1,y0,m0         ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up}
+	dct por  x1,y0,m0         ;!/* 10110101xxyynnnn por  <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */  {"por",  {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up}
+	dct pdec x1,m0            ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */  {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}
+	dct pdec y0,m0            ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */  {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}
+	dct pinc x1,m0            ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */  {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}
+	dct pinc y0,m0            ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */  {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}
+	dct pclr m0               ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */  {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}
+	dct pdmsb x1,m0           ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */  {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}
+	dct pdmsb y0,m0           ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */  {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}
+	dct pneg  x1,m0           ;!/* 11001001xxyynnnn pneg  <DSP_REG_X>,<DSP_REG_N> */  {"pneg",  {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}
+	dct pneg  y0,m0           ;!/* 11101001xxyynnnn pneg  <DSP_REG_Y>,<DSP_REG_N> */  {"pneg",  {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up}
+	dct pcopy x1,m0           ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */  {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up}
+	dct pcopy y0,m0           ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */  {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up}
+	dct psts MACH,m0          ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */  {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up}
+	dct psts MACL,m0          ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */  {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up}
+	dct plds m0,MACH          ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */  {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}
+	dct plds m0,MACL          ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */  {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/ld-r-1.d b/binutils-2.19/ld/testsuite/ld-sh/ld-r-1.d
new file mode 100644
index 0000000..1c629b3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/ld-r-1.d
@@ -0,0 +1,24 @@
+#source: ldr1.s
+#source: ldr2.s
+#as: -little
+#ld: -r -EL
+#readelf: -r -x1 -x2
+#target: sh*-*-elf sh*-*-linux*
+#notarget: sh64*-*-linux*
+
+# Make sure relocations against global and local symbols with relative and
+# absolute 32-bit relocs don't come out wrong after ld -r.  Remember that
+# SH uses partial_inplace (sort-of REL within RELA) with its confusion
+# where and which addends to use and how.  A file linked -r must have the
+# same layout as a plain assembly file: the addend is in the data only.
+
+Relocation section '\.rela\.text' at offset 0x[0-9a-f]+ contains 1 entries:
+.*
+00000008  00000101 R_SH_DIR32 +00000000 +\.text +\+ 0
+
+Hex dump of section '\.text':
+.*
+  0x00000000 09000900 09000900 0c000000 .*
+
+Hex dump of section '\.rela\.text':
+  0x00000000 08000000 01010000 00000000 .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/ldr1.s b/binutils-2.19/ld/testsuite/ld-sh/ldr1.s
new file mode 100644
index 0000000..9f49389
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/ldr1.s
@@ -0,0 +1,5 @@
+ .text
+ nop
+ nop
+ nop
+ nop
diff --git a/binutils-2.19/ld/testsuite/ld-sh/ldr2.s b/binutils-2.19/ld/testsuite/ld-sh/ldr2.s
new file mode 100644
index 0000000..94e0658
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/ldr2.s
@@ -0,0 +1,3 @@
+ .text
+ .long bar
+bar:
diff --git a/binutils-2.19/ld/testsuite/ld-sh/rd-sh.exp b/binutils-2.19/ld/testsuite/ld-sh/rd-sh.exp
new file mode 100644
index 0000000..cb0573e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/rd-sh.exp
@@ -0,0 +1,71 @@
+# Expect script for run_dump_test based ld-sh tests.
+#   Copyright 2001, 2002, 2003, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Hans-Peter Nilsson (hp@bitrange.com)
+#
+
+# This file is kept separate from sh.exp, because having it separate
+# simplifies selective testing, like in "make check-ld
+# RUNTESTFLAGS=rd-sh.exp=shared-1".  It is assumed that sh.exp is a place
+# for constructs where the name of the test is harder to extract and
+# select than here.
+
+if ![istarget sh*-*-*] {
+    return
+}
+
+global ASFLAGS
+global LDFLAGS
+set asflags_save "$ASFLAGS"
+set ldflags_save "$LDFLAGS"
+
+if {[istarget sh64*-*-*] || [istarget sh5*-*-*]} then {
+    set ASFLAGS "$ASFLAGS -isa=SHcompact"
+    if [istarget sh64*-*-linux*] {
+        set LDFLAGS "$LDFLAGS -mshlelf32_linux"
+    } elseif { [istarget sh64*-*-netbsd*] || [istarget sh5*-*-netbsd*] } {
+        set LDFLAGS "$LDFLAGS -mshlelf32_nbsd -e_start"
+    } else {
+        set LDFLAGS "$LDFLAGS -mshlelf32"
+    }
+}
+
+set rd_test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach shtest $rd_test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname $shtest]
+    # vxworks-static.d relies on files created by sh-vxworks.exp.
+    # We run it there instead of here.
+    if { [file tail $shtest] != "vxworks1-static.d" } {
+	run_dump_test [file rootname $shtest]
+    }
+    if [string match $srcdir/$subdir/*-dso.d $shtest] {
+	# Copy the output of the DSO-createing test to .so file.
+	# Notice that a DSO-creating test must preceed the tests
+	# which need that DSO in sort-order by name.
+	set cmd "cp tmpdir/dump tmpdir/[file rootname [file tail $shtest]].so"
+	send_log "$cmd\n"
+	set cmdret [catch "exec $cmd" comp_output]
+	send_log "$comp_output\n"
+	# FIXME: What if it fails?  Need we do something?
+    }
+}
+set ASFLAGS "$asflags_save"
+set LDFLAGS "$ldflags_save"
diff --git a/binutils-2.19/ld/testsuite/ld-sh/refdbg-0-dso.d b/binutils-2.19/ld/testsuite/ld-sh/refdbg-0-dso.d
new file mode 100644
index 0000000..c38fe3e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/refdbg-0-dso.d
@@ -0,0 +1,9 @@
+#source: refdbglib.s
+#as: -little
+#ld: -shared -EL
+#objdump: -drj.text
+#target: sh*-*-linux* sh*-*-netbsd*
+
+.*: +file format elf32-sh.*
+
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sh/refdbg-1.d b/binutils-2.19/ld/testsuite/ld-sh/refdbg-1.d
new file mode 100644
index 0000000..461788e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/refdbg-1.d
@@ -0,0 +1,10 @@
+#source: refdbg.s
+#as: -little
+#ld: -EL tmpdir/refdbg-0-dso.so
+#objdump: -sj.debug_info
+#target: sh*-*-linux* sh*-*-netbsd*
+
+.*: +file format elf32-sh.*
+
+Contents of section \.debug_info:
+ 0+0 0+0 +.*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/refdbg.s b/binutils-2.19/ld/testsuite/ld-sh/refdbg.s
new file mode 100644
index 0000000..268fa16
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/refdbg.s
@@ -0,0 +1,12 @@
+	.text
+	.align 2
+	.globl	_start
+	.type	_start,@function
+_start:
+	rts
+	nop
+
+	.comm	foo,4,4
+	.section	.debug_info,"",@progbits
+	.long	0
+	.ualong	foo
diff --git a/binutils-2.19/ld/testsuite/ld-sh/refdbglib.s b/binutils-2.19/ld/testsuite/ld-sh/refdbglib.s
new file mode 100644
index 0000000..31244ac
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/refdbglib.s
@@ -0,0 +1,8 @@
+	.text
+	.global	foo
+	.data
+	.align 2
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	1
diff --git a/binutils-2.19/ld/testsuite/ld-sh/reloc1.d b/binutils-2.19/ld/testsuite/ld-sh/reloc1.d
new file mode 100644
index 0000000..b56cd7d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/reloc1.d
@@ -0,0 +1,10 @@
+#source: reloc1.s
+#as: -big
+#ld: -shared -EB --defsym foo=0x9000
+#objdump: -sj.data
+#target: sh*-*-elf sh-*-vxworks
+
+.*:     file format elf32-sh.*
+
+Contents of section \.data:
+ .* 9123 .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/reloc1.s b/binutils-2.19/ld/testsuite/ld-sh/reloc1.s
new file mode 100644
index 0000000..e579034
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/reloc1.s
@@ -0,0 +1,2 @@
+	.data
+	.word	foo + 0x123
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh-vxworks.exp b/binutils-2.19/ld/testsuite/ld-sh/sh-vxworks.exp
new file mode 100644
index 0000000..4dcc49a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh-vxworks.exp
@@ -0,0 +1,62 @@
+# Expect script for VxWorks targeted SH linker tests
+#   Copyright 2007  Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+if { ![istarget "sh-*-vxworks"] } {
+    return
+}
+
+set endians { "--big" "-EB" "" "--little" "-EL" "-le" }
+
+foreach { gas_option ld_option suffix } $endians {
+    set vxworkstests {
+	{"VxWorks shared library test 1" "-shared -Tvxworks1.ld $ld_option"
+	 "$gas_option" {vxworks1-lib.s}
+	 {{readelf --relocs vxworks1-lib.rd}
+	  {objdump -dr vxworks1-lib$suffix.dd}
+	  {readelf --symbols vxworks1-lib.nd} {readelf -d vxworks1-lib.td}}
+	 "libvxworks1.so"}
+	{"VxWorks executable test 1 (dynamic)" \
+	 "tmpdir/libvxworks1.so -Tvxworks1.ld -q --force-dynamic $ld_option"
+	 "$gas_option" {vxworks1.s}
+	 {{readelf --relocs vxworks1.rd} {objdump -dr vxworks1$suffix.dd}}
+	 "vxworks1"}
+	{"VxWorks executable test 2 (dynamic)" \
+	 "-Tvxworks1.ld -q --force-dynamic $ld_option"
+	 "$gas_option" {vxworks2.s}
+	 {{readelf --segments vxworks2.sd}}
+	 "vxworks2"}
+	{"VxWorks executable test 2 (static)"
+	 "-Tvxworks1.ld $ld_option"
+	 "$gas_option" {vxworks2.s}
+	 {{readelf --segments vxworks2-static.sd}}
+	 "vxworks2"}
+	{"VxWorks shared library test 3" "-shared -Tvxworks1.ld $ld_option"
+	 "$gas_option" {vxworks3-lib.s}
+	    {{objdump -dr vxworks3-lib$suffix.dd}}
+	 "libvxworks3.so"}
+	{"VxWorks executable test 3 (dynamic)" \
+	 "tmpdir/libvxworks3.so -Tvxworks1.ld -q --force-dynamic $ld_option"
+	 "$gas_option" {vxworks3.s}
+	 {{objdump -d vxworks3$suffix.dd}}
+	 "vxworks3"}
+    }
+    run_ld_link_tests [subst $vxworkstests]
+}
+run_dump_test "vxworks1-static"
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh.exp b/binutils-2.19/ld/testsuite/ld-sh/sh.exp
new file mode 100644
index 0000000..66bdc39
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh.exp
@@ -0,0 +1,168 @@
+# Expect script for ld-sh tests
+#   Copyright 1995, 1996, 1997, 2001, 2002, 2003, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Ian Lance Taylor (ian@cygnus.com)
+#
+
+# Test SH relaxing.  This tests the compiler and assembler as well as
+# the linker.
+
+if ![istarget sh*-*-*] {
+    return
+}
+
+if { ([istarget sh64*-*-*] || [istarget sh5*-*-*])} {
+    # relaxing not supported on sh64 yet.
+    return
+}
+
+set testsimple "SH simple relaxing"
+
+if ![ld_assemble $as "-relax $srcdir/$subdir/sh1.s" tmpdir/sh1.o] {
+    unresolved $testsimple
+} else { if ![ld_simple_link $ld tmpdir/sh1 "-relax tmpdir/sh1.o"] {
+    fail $testsimple
+} else {
+    if ![ld_nm $nm "" tmpdir/sh1] {
+	unresolved $testsimple
+    } else {
+	if {![info exists nm_output(bar)] \
+	     || ![info exists nm_output(foo)]} {
+	    send_log "bad output from nm\n"
+	    verbose "bad output from nm"
+	    fail $testsimple
+	} else {
+	    if {$nm_output(bar) != $nm_output(foo) + 4} {
+		send_log "foo == $nm_output(foo)\n"
+		verbose "foo == $nm_output(foo)"
+		send_log "bar == $nm_output(bar)\n"
+		verbose "bar == $nm_output(bar)"
+		fail $testsimple
+	    } else {
+		pass $testsimple
+	    }
+	}
+    }
+} }
+
+set testsrec "SH relaxing to S-records"
+
+if { [istarget sh*-linux-*] || [istarget sh-*-vxworks] } {
+    # On these "non-embedded" targets, the default ELF and srec start
+    # addresses will be SIZEOF_HEADERS bytes apart.  Ensure consistency
+    # by feeding the ELF start address to the srec link line.
+    catch "exec $objdump -x tmpdir/sh1 | grep start\\ address | sed s/start\\ address//" entry_addr
+    set srec_relax_arg "-Ttext $entry_addr -relax --oformat srec tmpdir/sh1.o"
+} else {
+    set srec_relax_arg "-relax --oformat srec tmpdir/sh1.o"
+}
+if ![ld_simple_link $ld tmpdir/sh1.s1 $srec_relax_arg ] {
+    fail $testsrec
+} else {
+    # The file name is embedded in the S-records, so create both
+    # files with the same name.
+    catch "exec rm -f tmpdir/sh1.s2" exec_output
+    send_log "mv tmpdir/sh1.s1 tmpdir/sh1.s2\n"
+    verbose "mv tmpdir/sh1.s1 tmpdir/sh1.s2"
+    catch "exec mv tmpdir/sh1.s1 tmpdir/sh1.s2" exec_output
+    if ![string match "" $exec_output] {
+	send_log "$exec_output\n"
+	verbose "$exec_output"
+	unresolved $testsrec
+    } else {
+	send_log "$objcopy -O srec tmpdir/sh1 tmpdir/sh1.s1"
+	verbose "$objcopy -O srec tmpdir/sh1 tmpdir/sh1.s1"
+	catch "exec $objcopy -O srec tmpdir/sh1 tmpdir/sh1.s1" exec_output
+	if ![string match "" $exec_output] {
+	    send_log "$exec_output\n"
+	    verbose "$exec_output"
+	    unresolved $testsrec
+	} else {
+	    send_log "cmp tmpdir/sh1.s1 tmpdir/sh1.s2\n"
+	    verbose "cmp tmpdir/sh1.s1 tmpdir/sh1.s2"
+	    catch "exec cmp tmpdir/sh1.s1 tmpdir/sh1.s2" exec_output
+	    set exec_output [prune_warnings $exec_output]
+	    if ![string match "" $exec_output] {
+		send_log "$exec_output\n"
+		verbose "$exec_output"
+		fail $testsrec
+	    } else {
+		pass $testsrec
+	    }
+	}
+    }
+}
+
+set testlink "SH relaxing"
+set testjsr "SH confirm relaxing"
+set testrun "SH relaxing execution"
+
+if { [which $CC] == 0 } {
+    untested $testlink
+    untested $testjsr
+    untested $testrun
+    return
+}
+
+if [istarget sh*-linux-*] {
+    exec sed -e s/_main/main/ -e s/_trap/trap/ -e s/_stack/stack/ \
+	    < $srcdir/$subdir/start.s >tmpdir/start.s
+} else {
+    exec cp $srcdir/$subdir/start.s tmpdir/start.s
+}
+
+if {![ld_assemble $as "-relax tmpdir/start.s" tmpdir/start.o] \
+    || ![ld_compile $CC "-O -mrelax $srcdir/$subdir/sh2.c" tmpdir/sh2.o]} {
+    unresolved $testlink
+    unresolved $testjsr
+    unresolved $testrun
+    return
+}
+
+if ![ld_simple_link $ld tmpdir/sh2 "-relax tmpdir/start.o tmpdir/sh2.o"] {
+    fail $testlink
+    unresolved $testjsr
+    unresolved $testrun
+    return
+}
+
+pass $testlink
+
+send_log "$objdump -d tmpdir/sh2\n"
+verbose "$objdump -d tmpdir/sh2"
+catch "exec $objdump -d tmpdir/sh2" exec_output
+if [string match "*jsr*" $exec_output] {
+    fail $testjsr
+} else {
+    pass $testjsr
+}
+
+if { ![info exists SIM] || [which $SIM] == 0 } {
+    untested $testrun
+    return
+}
+
+set status [catch "exec $SIM tmpdir/sh2" exec_output]
+if { $status == 0 } {
+    pass $testrun
+} else {
+    fail $testrun
+}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh1.s b/binutils-2.19/ld/testsuite/ld-sh/sh1.s
new file mode 100644
index 0000000..d18e439
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh1.s
@@ -0,0 +1,13 @@
+	.text
+foo:
+L1:	
+	mov.l	L2,r0
+	.uses	L1
+	jsr	@r0
+	rts
+	.align	2
+L2:
+	.long	bar
+bar:
+	rts
+	.align	4
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh2.c b/binutils-2.19/ld/testsuite/ld-sh/sh2.c
new file mode 100644
index 0000000..527fe88
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh2.c
@@ -0,0 +1,120 @@
+int global;
+
+extern void trap (int, int);
+static void quit (int);
+static int foo (int);
+
+int
+main ()
+{
+  if (foo (0) != 0 || global != 0)
+    quit (1);
+  if (foo (1) != 1 || global != 1)
+    quit (1);
+  if (foo (2) != 2 || global != 2)
+    quit (1);
+  if (foo (3) != 3 || global != 3)
+    quit (1);
+  if (foo (4) != 4 || global != 4)
+    quit (1);
+  if (foo (5) != 5 || global != 5)
+    quit (1);
+  if (foo (6) != 6 || global != 6)
+    quit (1);
+  if (foo (7) != 7 || global != 7)
+    quit (1);
+  if (foo (8) != 8 || global != 8)
+    quit (1);
+  quit (0);
+}
+
+void
+__main ()
+{
+}
+
+static void
+quit (int status)
+{
+  trap (1, status);
+}
+
+int
+bar (int i)
+{
+  global = i;
+  return i;
+}
+
+int
+bar0 (int i)
+{
+  global = 0;
+  return i;
+}
+
+int
+bar1 (int i)
+{
+  global = 1;
+  return i;
+}
+
+int
+bar2 (int i)
+{
+  global = 2;
+  return i;
+}
+
+int
+bar3 (int i)
+{
+  global = 3;
+  return i;
+}
+
+int
+bar4 (int i)
+{
+  global = 4;
+  return i;
+}
+
+int
+bar5 (int i)
+{
+  global = 5;
+  return i;
+}
+
+int
+bar6 (int i)
+{
+  global = 6;
+  return i;
+}
+
+int
+bar7 (int i)
+{
+  global = 7;
+  return i;
+}
+
+int
+foo (int i)
+{
+  switch (i)
+    {
+    case 0: bar0 (0); return 0;
+    case 1: bar1 (1); return 1;
+    case 2: bar2 (2); return 2;
+    case 3: bar3 (3); return 3;
+    case 4: bar4 (4); return 4;
+    case 5: bar5 (5); return 5;
+    case 6: bar6 (6); return 6;
+    case 7: bar7 (7); return 7;
+    default: return bar (i);
+    }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/abi32.sd b/binutils-2.19/ld/testsuite/ld-sh/sh64/abi32.sd
new file mode 100644
index 0000000..8b22e46
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/abi32.sd
@@ -0,0 +1,16 @@
+
+.*:     file format .*-sh64.*
+
+Contents of section \.text:
+ 1000 cc000190 c8015590 6bf56630 6ff0fff0  .*
+ 1010 cc000210 c8400610 cc000150 c8403550  .*
+ 1020 cffffd90 cbff9590 6bf56630 cc0002b0  .*
+ 1030 c843e2b0 cc000350 c843c350 cc000040  .*
+ 1040 c843f040 cc000190 c8004590 6bf56650  .*
+ 1050 cc000190 c8002590 6bf56410 6ff0fff0  .*
+ 1060 6ff0fff0                             .*
+Contents of section \.data:
+ 10e8 000010f4 0000100d 0000105d 000010e8  .*
+ 10f8 000010e8 0000100d                    .*
+Contents of section \.stack:
+ 80000 deaddead                            .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/abi32.xd b/binutils-2.19/ld/testsuite/ld-sh/sh64/abi32.xd
new file mode 100644
index 0000000..94b1014
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/abi32.xd
@@ -0,0 +1,45 @@
+
+.*:     file format .*-sh64
+.*
+architecture: sh5, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x0+1011
+
+Program Header:
+    LOAD off    0x0+100 vaddr 0x0+1000 paddr 0x0+1000 align 2\*\*7
+         filesz 0x0+64 memsz 0x0+64 flags r-x
+    LOAD off    0x0+168 vaddr 0x0+10e8 paddr 0x0+10e8 align 2\*\*7
+         filesz 0x0+18 memsz 0x0+18 flags rw-
+    LOAD off    0x0+180 vaddr 0x0+80000 paddr 0x0+80000 align 2\*\*7
+         filesz 0x0+4 memsz 0x0+4 flags rw-
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 \.text         00000064  0+1000  0+1000  00000100  2\*\*0
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 \.data         00000018  0+10e8  0+10e8  00000168  2\*\*2
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 \.stack        00000004  0+80000  0+80000  00000180  2\*\*0
+                  CONTENTS, ALLOC, LOAD, DATA
+SYMBOL TABLE:
+0+1000 l    d  \.text	0+ (|\.text)
+0+10e8 l    d  \.data	0+ (|\.data)
+0+80000 l    d  \.stack	0+ (|\.stack)
+0+10f4 l       \.data	0+ foobar
+0+10fc l       \.data	0+ foobar2
+0+1060 l       \.text	0+ 0x04 plugh
+0+10f8 g       \.data	0+ foobar
+0+10e8 g       \.data	0+ baz
+0+10e8 g       .*	0+ ___dtors
+0+105c g       \.text	0+ 0x04 xyzzy
+0+1100 g       \*ABS\*	0+ __bss_start
+0+10e8 g       .*	0+ ___ctors_end
+0+10f0 g       \.data	0+ baz2
+0+10e8 g       .*	0+ ___ctors
+0+1000 g       \.text	0+ 0x04 foo
+0+1100 g       \*ABS\*	0+ _edata
+0+1100 g       \*ABS\*	0+ _end
+0+1010 g       \.text	0+ 0x04 start
+0+100c g       \.text	0+ 0x04 bar
+0+80000 g       \.stack	0+ _stack
+0+10e8 g       .*	0+ ___dtors_end
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/abi64.sd b/binutils-2.19/ld/testsuite/ld-sh/sh64/abi64.sd
new file mode 100644
index 0000000..ff26740
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/abi64.sd
@@ -0,0 +1,20 @@
+
+.*:     file format .*-sh64
+
+Contents of section \.text:
+ 1000 cc000190 c8000190 c8000190 c8025590  .*
+ 1010 6bf56630 6ff0fff0 cc000210 c8000210  .*
+ 1020 c8000210 c8400610 cc000150 c8000150  .*
+ 1030 c8000150 c8405550 cffffd90 cbfffd90  .*
+ 1040 cbfffd90 cbff3590 6bf56630 cc0002b0  .*
+ 1050 c80002b0 c80002b0 c84502b0 cc000350  .*
+ 1060 c8000350 c8000350 c844e350 cc000040  .*
+ 1070 c8000040 c8000040 c8451040 cc000190  .*
+ 1080 c8000190 c8000190 c8006590 6bf56650  .*
+ 1090 cc000190 c8000190 c8000190 c8002590  .*
+ 10a0 6bf56410 6ff0fff0 6ff0fff0           .*
+Contents of section \.data:
+ 1130 0000113c 00001015 000010a5 00001130  .*
+ 1140 00001130 00001015                    .*
+Contents of section \.stack:
+ 80000 deaddead                            .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/abi64.xd b/binutils-2.19/ld/testsuite/ld-sh/sh64/abi64.xd
new file mode 100644
index 0000000..9af5b47
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/abi64.xd
@@ -0,0 +1,44 @@
+.*:     file format .*-sh64
+.*
+architecture: sh5, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x0000000000001019
+
+Program Header:
+    LOAD off    0x0000000000000100 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2\*\*7
+         filesz 0x00000000000000ac memsz 0x00000000000000ac flags r-x
+    LOAD off    0x00000000000001b0 vaddr 0x0000000000001130 paddr 0x0000000000001130 align 2\*\*7
+         filesz 0x0000000000000018 memsz 0x0000000000000018 flags rw-
+    LOAD off    0x0000000000000200 vaddr 0x0000000000080000 paddr 0x0000000000080000 align 2\*\*7
+         filesz 0x0000000000000004 memsz 0x0000000000000004 flags rw-
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         000000ac  0000000000001000  0000000000001000  00000100  2\*\*0
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 \.data         00000018  0000000000001130  0000000000001130  000001b0  2\*\*2
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 \.stack        00000004  0000000000080000  0000000000080000  00000200  2\*\*0
+                  CONTENTS, ALLOC, LOAD, DATA
+SYMBOL TABLE:
+0000000000001000 l    d  \.text	0000000000000000 (|\.text)
+0000000000001130 l    d  \.data	0000000000000000 (|\.data)
+0000000000080000 l    d  \.stack	0000000000000000 (|\.stack)
+000000000000113c l       \.data	0000000000000000 foobar
+0000000000001144 l       \.data	0000000000000000 foobar2
+00000000000010a8 l       \.text	0000000000000000 0x04 plugh
+0000000000001140 g       \.data	0000000000000000 foobar
+0000000000001130 g       \.data	0000000000000000 baz
+0000000000001130 g       .*	0000000000000000 ___dtors
+00000000000010a4 g       \.text	0000000000000000 0x04 xyzzy
+0000000000001148 g       \*ABS\*	0000000000000000 __bss_start
+0000000000001130 g       .*	0000000000000000 ___ctors_end
+0000000000001138 g       \.data	0000000000000000 baz2
+0000000000001130 g       .*	0000000000000000 ___ctors
+0000000000001000 g       \.text	0000000000000000 0x04 foo
+0000000000001148 g       \*ABS\*	0000000000000000 _edata
+0000000000001148 g       \*ABS\*	0000000000000000 _end
+0000000000001018 g       \.text	0000000000000000 0x04 start
+0000000000001014 g       \.text	0000000000000000 0x04 bar
+0000000000080000 g       \.stack	0000000000000000 _stack
+0000000000001130 g       .*	0000000000000000 ___dtors_end
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/abixx-noexp.sd b/binutils-2.19/ld/testsuite/ld-sh/sh64/abixx-noexp.sd
new file mode 100644
index 0000000..ce11156
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/abixx-noexp.sd
@@ -0,0 +1,12 @@
+
+.*:     file format .*-sh64
+
+Contents of section \.text:
+ 1000 e8002a30 6ff0fff0 cc400610 cc401550  .*
+ 1010 ebfff630 cc4302b0 cc42e350 cc431040  .*
+ 1020 e8000a50 e8000810 6ff0fff0 6ff0fff0  .*
+Contents of section \.data:
+ 10b0 000010bc 00001005 00001029 000010b0  .*
+ 10c0 000010b0 00001005                    .*
+Contents of section \.stack:
+ 80000 deaddead                            .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/cmpct1.sd b/binutils-2.19/ld/testsuite/ld-sh/sh64/cmpct1.sd
new file mode 100644
index 0000000..1f7e8a1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/cmpct1.sd
@@ -0,0 +1,9 @@
+
+.*:     file format elf32-sh64
+
+Contents of section \.text:
+ 1000 c7000009 0009ea2a                    .*
+Contents of section \.rodata:
+ 1008 00001000 0000100c 00001004           .*
+Contents of section \.stack:
+ 80000 deaddead                            .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/cmpct1.xd b/binutils-2.19/ld/testsuite/ld-sh/sh64/cmpct1.xd
new file mode 100644
index 0000000..41f898e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/cmpct1.xd
@@ -0,0 +1,36 @@
+
+.*:     file format .*-sh64
+.*
+architecture: sh5, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x0+1000
+
+Program Header:
+    LOAD off    0x0+80 vaddr 0x0+1000 paddr 0x0+1000 align 2\*\*7
+         filesz 0x0+14 memsz 0x0+14 flags r-x
+    LOAD off    0x0+100 vaddr 0x0+80000 paddr 0x0+80000 align 2\*\*7
+         filesz 0x00000004 memsz 0x00000004 flags rw-
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 \.text         00000008  0+1000  0+1000  00000080  2\*\*0
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 \.rodata       0000000c  0+1008  0+1008  00000088  2\*\*2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  2 \.stack        00000004  0+80000  0+80000  00000100  2\*\*0
+                  CONTENTS, ALLOC, LOAD, DATA
+SYMBOL TABLE:
+0+1000 l    d  \.text	0+ (|\.text)
+0+1008 l    d  \.rodata	0+ (|\.rodata)
+0+80000 l    d  \.stack	0+ (|\.stack)
+0+1004 l       \.text	0+ next
+0+100c l       \.rodata	0+ here
+0+1098 g       .*	0+ ___dtors
+0+1098 g       \*ABS\*	0+ __bss_start
+0+1098 g       .*	0+ ___ctors_end
+0+1098 g       .*	0+ ___ctors
+0+1098 g       \*ABS\*	0+ _edata
+0+1098 g       \*ABS\*	0+ _end
+0+1000 g       \.text	0+ start
+0+80000 g       \.stack	0+ _stack
+0+1098 g       .*	0+ ___dtors_end
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-1.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-1.s
new file mode 100644
index 0000000..5dfae88
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-1.s
@@ -0,0 +1,8 @@
+! Support file for .cranges tests to resolve all references for
+! non-partial-link tests.
+	.section .init,"ax"
+	.mode SHmedia
+	.global start
+	.align 2
+start:
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2a.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2a.s
new file mode 100644
index 0000000..9af6bbe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2a.s
@@ -0,0 +1,22 @@
+! Simple example with assembler-generated .cranges that do not need more
+! .cranges added by the linker: A single section with SHmedia, constants
+! and SHcompact.
+	.section .text.mixed,"ax"
+	.align 2
+! Make sure this symbol does not have the expected type.
+	.mode SHcompact
+	.global diversion2
+diversion2:
+
+	.mode SHmedia
+start2:
+	nop
+	nop
+	nop
+
+	.long 42
+	.long 43
+
+	.mode SHcompact
+	nop
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2b.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2b.s
new file mode 100644
index 0000000..670a448
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2b.s
@@ -0,0 +1,39 @@
+! Initially three separate sections, one with SHmedia and constants, one with
+! SHcompact, and yet another with SHmedia.  Two .cranges sections
+! generated by the assembler; two more needed at link time, as they will be
+! consolidated into the same section, and mixed with a file with
+! assembler-generated .cranges only and one without any .cranges.
+
+	.section .text.shmedia,"ax"
+	.mode SHmedia
+	.align 2
+sec1:
+	nop
+	nop
+	nop
+	nop
+sec2:
+	.long 41
+	.long 43
+	.long 42
+	.long 43
+	.long 42
+
+	.section .text.shcompact,"ax"
+	.align 1
+	.mode SHcompact
+sec3:
+	nop
+	nop
+	nop
+
+	.section .text.shmedia2,"ax"
+	.align 2
+sec4:
+	.mode SHmedia
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2c.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2c.s
new file mode 100644
index 0000000..fcc350d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2c.s
@@ -0,0 +1,16 @@
+! First part of crange-2b.s, but in section .text.mixed.
+
+	.section .text.mixed,"ax"
+	.mode SHmedia
+	.align 2
+sec1:
+	nop
+	nop
+	nop
+	nop
+sec2:
+	.long 41
+	.long 43
+	.long 42
+	.long 43
+	.long 42
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2d.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2d.s
new file mode 100644
index 0000000..11f3d5b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2d.s
@@ -0,0 +1,9 @@
+! Second part of crange-2b.s, but in section .text.mixed.
+
+	.section .text.mixed,"ax"
+	.align 1
+	.mode SHcompact
+sec3:
+	nop
+	nop
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2e.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2e.s
new file mode 100644
index 0000000..3d7c997
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2e.s
@@ -0,0 +1,12 @@
+! Third part of crange-2b.s, but in section .text.mixed.
+
+	.section .text.mixed,"ax"
+	.align 2
+sec4:
+	.mode SHmedia
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2f.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2f.s
new file mode 100644
index 0000000..a8479c9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2f.s
@@ -0,0 +1,21 @@
+! Section with SHmedia in unique section.  Note the absence of a symbol to
+! key an ISA type.
+
+	.section .text.2f,"ax"
+	.align 2
+
+	.mode SHmedia
+	movi	0x2f,r20
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	movi	0x2f,r21
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2g.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2g.s
new file mode 100644
index 0000000..ac7aacb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2g.s
@@ -0,0 +1,26 @@
+! Section with SHmedia in unique section, similar to crange-2f.s
+
+	.section .text.2g,"ax"
+	.align 2
+
+	.mode SHmedia
+	movi 0x21,r12
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	movi 0x21,r13
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2h.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2h.s
new file mode 100644
index 0000000..99c6146
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2h.s
@@ -0,0 +1,17 @@
+! SHcompact in .text, similar to crange-2f.s and crange-2g.s
+	.section .text,"ax"
+	.align 2
+
+	.mode SHcompact
+	mov #0xf,r1
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	mov #0xe,r1
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2i.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2i.s
new file mode 100644
index 0000000..78c1ce9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange-2i.s
@@ -0,0 +1,8 @@
+! If this file comes before a file with a SHcompact .text section but with
+! no symbols, we will have a symbol of the "wrong kind" before the
+! SHcompact insns.
+	.section .text,"ax"
+	.mode SHmedia
+	.align 2
+	.global diversion
+diversion:
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange1.rd b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange1.rd
new file mode 100644
index 0000000..aa080dc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange1.rd
@@ -0,0 +1,48 @@
+.*
+
+Section Headers:
+  \[Nr\] Name              Type            Addr     Off    Size   ES Flg Lk Inf Al
+  \[ 0\]                   NULL            00000000 000000 000000 00      0   0  0
+  \[ 1\] \.init             PROGBITS        00001000 000080 000004 00 AXp  0   0  4
+  \[ 2\] \.text             PROGBITS        00001004 000084 000018 00 AXp  0   0  4
+  \[ 3\] \.stack            PROGBITS        00080000 000100 000004 00  WA  0   0  1
+  \[ 4\] \.cranges          LOUSER\+1        00000000 000104 00001e 00   W  0   0  1
+  \[ 5\] \.shstrtab         STRTAB          .*
+  \[ 6\] \.symtab           SYMTAB          .*
+  \[ 7\] \.strtab           STRTAB          .*
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+There are no relocations in this file\.
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+   Num:    Value  Size Type    Bind   Vis      Ndx Name
+.*: 00000000     0 NOTYPE  LOCAL  DEFAULT  UND 
+.*: 00001000     0 SECTION LOCAL  DEFAULT    1 
+.*: 00001004     0 SECTION LOCAL  DEFAULT    2 
+.*: 00080000     0 SECTION LOCAL  DEFAULT    3 
+.*: 00000000     0 SECTION LOCAL  DEFAULT    4 
+.*: 00001004     0 NOTYPE  LOCAL  DEFAULT \[<other>: 4\]     2 start2
+.*: 000010a0     0 NOTYPE  GLOBAL DEFAULT    .* ___dtors
+.*: 000010a0     0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.*: 000010a0     0 NOTYPE  GLOBAL DEFAULT    .* ___ctors_end
+.*: 00001004     0 NOTYPE  GLOBAL DEFAULT    2 diversion2
+.*: 000010a0     0 NOTYPE  GLOBAL DEFAULT    .* ___ctors
+.*: 000010a0     0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+.*: 000010a0     0 NOTYPE  GLOBAL DEFAULT  ABS _end
+.*: 00001000     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 start
+.*: 00080000     0 NOTYPE  GLOBAL DEFAULT    3 _stack
+.*: 000010a0     0 NOTYPE  GLOBAL DEFAULT    .* ___dtors_end
+
+Hex dump of section '\.init':
+  0x00001000 6ff0fff0                            .*
+
+Hex dump of section '\.text':
+  0x00001004 6ff0fff0 6ff0fff0 6ff0fff0 0000002a .*
+  0x00001014 0000002b 00090009                   .*
+
+Hex dump of section '\.cranges':
+  0x00000000 00001004 0000000c 00030000 10100000 .*
+  0x00000010 00080001 00001018 00000004 0002     .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange2.rd b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange2.rd
new file mode 100644
index 0000000..9690276
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange2.rd
@@ -0,0 +1,56 @@
+.*
+
+Section Headers:
+  \[Nr\] Name              Type            Addr     Off    Size   ES Flg Lk Inf Al
+  \[ 0\]                   NULL            00000000 000000 000000 00      0   0  0
+  \[ 1\] \.init             PROGBITS        00001000 000080 000004 00 AXp  0   0  4
+  \[ 2\] \.text             PROGBITS        00001004 000084 00005c 00 AXp  0   0  4
+  \[ 3\] \.stack            PROGBITS        00080000 000100 000004 00  WA  0   0  1
+  \[ 4\] \.cranges          LOUSER\+1        00000000 000104 000046 00   W  0   0  1
+  \[ 5\] \.shstrtab         STRTAB          .*
+  \[ 6\] \.symtab           SYMTAB          .*
+  \[ 7\] \.strtab           STRTAB          .*
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+There are no relocations in this file\.
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+   Num:    Value  Size Type    Bind   Vis      Ndx Name
+.*: 00000000     0 NOTYPE  LOCAL  DEFAULT  UND 
+.*: 00001000     0 SECTION LOCAL  DEFAULT    1 
+.*: 00001004     0 SECTION LOCAL  DEFAULT    2 
+.*: 00080000     0 SECTION LOCAL  DEFAULT    3 
+.*: 00000000     0 SECTION LOCAL  DEFAULT    4 
+.*: 00001004     0 NOTYPE  LOCAL  DEFAULT \[<other>: 4\]     2 start2
+.*: 0000101c     0 NOTYPE  LOCAL  DEFAULT \[<other>: 4\]     2 sec1
+.*: 0000102c     0 NOTYPE  LOCAL  DEFAULT \[<other>: 4\]     2 sec2
+.*: 00001040     0 NOTYPE  LOCAL  DEFAULT    2 sec3
+.*: 00001048     0 NOTYPE  LOCAL  DEFAULT    2 sec4
+.*: 000010e0     0 NOTYPE  GLOBAL DEFAULT    .* ___dtors
+.*: 000010e0     0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.*: 000010e0     0 NOTYPE  GLOBAL DEFAULT    .* ___ctors_end
+.*: 00001004     0 NOTYPE  GLOBAL DEFAULT    2 diversion2
+.*: 000010e0     0 NOTYPE  GLOBAL DEFAULT    .* ___ctors
+.*: 000010e0     0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+.*: 000010e0     0 NOTYPE  GLOBAL DEFAULT  ABS _end
+.*: 00001000     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 start
+.*: 00080000     0 NOTYPE  GLOBAL DEFAULT    3 _stack
+.*: 000010e0     0 NOTYPE  GLOBAL DEFAULT    .* ___dtors_end
+
+Hex dump of section '\.text':
+  0x00001004 6ff0fff0 6ff0fff0 6ff0fff0 0000002a .*
+  0x00001014 0000002b 00090009 6ff0fff0 6ff0fff0 .*
+  0x00001024 6ff0fff0 6ff0fff0 00000029 0000002b .*
+  0x00001034 0000002a 0000002b 0000002a 00090009 .*
+  0x00001044 00090000 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001054 6ff0fff0 6ff0fff0 6ff0fff0          .*
+
+Hex dump of section '\.cranges':
+  0x00000000 00001004 0000000c 00030000 10100000 .*
+  0x00000010 00080001 00001018 00000004 00020000 .*
+  0x00000020 101c0000 00100003 0000102c 00000014 .*
+  0x00000030 00010000 10400000 00060002 00001048 .*
+  0x00000040 00000018 0003                       .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange3-cmpct.rd b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange3-cmpct.rd
new file mode 100644
index 0000000..4d9197b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange3-cmpct.rd
@@ -0,0 +1,79 @@
+ELF Header:
+  Magic:   7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00 
+  Class:                             ELF32
+  Data:                              2's complement, big endian
+  Version:                           1 \(current\)
+  OS/ABI:                            UNIX - System V
+  ABI Version:                       0
+  Type:                              EXEC \(Executable file\)
+  Machine:                           Renesas / SuperH SH
+  Version:                           0x1
+  Entry point address:               0x10c4
+  Start of program headers:          52 \(bytes into file\)
+  Start of section headers:          504 \(bytes into file\)
+  Flags:                             0xa, sh5
+  Size of this header:               52 \(bytes\)
+  Size of program headers:           32 \(bytes\)
+  Number of program headers:         2
+  Size of section headers:           40 \(bytes\)
+  Number of section headers:         8
+  Section header string table index: 5
+
+Section Headers:
+  \[Nr\] Name              Type            Addr     Off    Size   ES Flg Lk Inf Al
+  \[ 0\]                   NULL            00000000 000000 000000 00      0   0  0
+  \[ 1\] \.init             PROGBITS        00001000 000080 000004 00 AXp  0   0  4
+  \[ 2\] \.text             PROGBITS        00001004 000084 0000d8 00 AXp  0   0  4
+  \[ 3\] \.stack            PROGBITS        00080000 000180 000004 00  WA  0   0  1
+  \[ 4\] \.cranges          LOUSER\+1        00000000 000184 00003c 00   W  0   0  1
+  \[ 5\] \.shstrtab         STRTAB          .*
+  \[ 6\] \.symtab           SYMTAB          .*
+  \[ 7\] \.strtab           STRTAB          .*
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+   Num:    Value  Size Type    Bind   Vis      Ndx Name
+.*: 00000000     0 NOTYPE  LOCAL  DEFAULT  UND 
+.*: 00001000     0 SECTION LOCAL  DEFAULT    1 
+.*: 00001004     0 SECTION LOCAL  DEFAULT    2 
+.*: 00080000     0 SECTION LOCAL  DEFAULT    3 
+.*: 00000000     0 SECTION LOCAL  DEFAULT    4 
+.*: 00001004     0 NOTYPE  LOCAL  DEFAULT    2 sec4
+.*: 000010a4     0 NOTYPE  LOCAL  DEFAULT \[<other>: 4\]     2 start2
+.*: 000010bc     0 NOTYPE  LOCAL  DEFAULT    2 sec3
+.*: 000010c4     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     2 diversion
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT    .* ___dtors
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT    .* ___ctors_end
+.*: 000010a4     0 NOTYPE  GLOBAL DEFAULT    2 diversion2
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT    .* ___ctors
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT  ABS _end
+.*: 00001000     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 start
+.*: 00080000     0 NOTYPE  GLOBAL DEFAULT    3 _stack
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT    .* ___dtors_end
+
+Hex dump of section '\.text':
+  0x00001004 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001014 6ff0fff0 6ff0fff0 cc00bd40 6ff0fff0 .*
+  0x00001024 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001034 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001044 6ff0fff0 6ff0fff0 6ff0fff0 cc00bd50 .*
+  0x00001054 cc0084c0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001064 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001074 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001084 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001094 6ff0fff0 6ff0fff0 6ff0fff0 cc0084d0 .*
+  0x000010a4 6ff0fff0 6ff0fff0 6ff0fff0 0000002a .*
+  0x000010b4 0000002b 00090009 00090009 00090000 .*
+  0x000010c4 e10f0009 00090009 00090009 00090009 .*
+  0x000010d4 00090009 0009e10e                   .*
+
+Hex dump of section '\.cranges':
+  0x00000000 00001004 000000a0 00030000 10a40000 .*
+  0x00000010 000c0003 000010b0 00000008 00010000 .*
+  0x00000020 10b80000 00040002 000010bc 00000006 .*
+  0x00000030 00020000 10c40000 00180002          .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange3-media.rd b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange3-media.rd
new file mode 100644
index 0000000..f1ba8e0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange3-media.rd
@@ -0,0 +1,79 @@
+ELF Header:
+  Magic:   7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00 
+  Class:                             ELF32
+  Data:                              2's complement, big endian
+  Version:                           1 \(current\)
+  OS/ABI:                            UNIX - System V
+  ABI Version:                       0
+  Type:                              EXEC \(Executable file\)
+  Machine:                           Renesas / SuperH SH
+  Version:                           0x1
+  Entry point address:               0x10a5
+  Start of program headers:          52 \(bytes into file\)
+  Start of section headers:          504 \(bytes into file\)
+  Flags:                             0xa, sh5
+  Size of this header:               52 \(bytes\)
+  Size of program headers:           32 \(bytes\)
+  Number of program headers:         2
+  Size of section headers:           40 \(bytes\)
+  Number of section headers:         8
+  Section header string table index: 5
+
+Section Headers:
+  \[Nr\] Name              Type            Addr     Off    Size   ES Flg Lk Inf Al
+  \[ 0\]                   NULL            00000000 000000 000000 00      0   0  0
+  \[ 1\] \.init             PROGBITS        00001000 000080 000004 00 AXp  0   0  4
+  \[ 2\] \.text             PROGBITS        00001004 000084 0000d8 00 AXp  0   0  4
+  \[ 3\] \.stack            PROGBITS        00080000 000180 000004 00  WA  0   0  1
+  \[ 4\] \.cranges          LOUSER\+1        00000000 000184 00003c 00   W  0   0  1
+  \[ 5\] \.shstrtab         STRTAB          .*
+  \[ 6\] \.symtab           SYMTAB          .*
+  \[ 7\] \.strtab           STRTAB          .*
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+   Num:    Value  Size Type    Bind   Vis      Ndx Name
+.*: 00000000     0 NOTYPE  LOCAL  DEFAULT  UND 
+.*: 00001000     0 SECTION LOCAL  DEFAULT    1 
+.*: 00001004     0 SECTION LOCAL  DEFAULT    2 
+.*: 00080000     0 SECTION LOCAL  DEFAULT    3 
+.*: 00000000     0 SECTION LOCAL  DEFAULT    4 
+.*: 00001004     0 NOTYPE  LOCAL  DEFAULT    2 sec4
+.*: 000010a4     0 NOTYPE  LOCAL  DEFAULT \[<other>: 4\]     2 start2
+.*: 000010bc     0 NOTYPE  LOCAL  DEFAULT    2 sec3
+.*: 000010c4     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     2 diversion
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT    .* ___dtors
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT    .* ___ctors_end
+.*: 000010a4     0 NOTYPE  GLOBAL DEFAULT    2 diversion2
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT    .* ___ctors
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT  ABS _end
+.*: 00001000     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 start
+.*: 00080000     0 NOTYPE  GLOBAL DEFAULT    3 _stack
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT    .* ___dtors_end
+
+Hex dump of section '\.text':
+  0x00001004 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001014 6ff0fff0 6ff0fff0 cc00bd40 6ff0fff0 .*
+  0x00001024 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001034 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001044 6ff0fff0 6ff0fff0 6ff0fff0 cc00bd50 .*
+  0x00001054 cc0084c0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001064 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001074 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001084 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001094 6ff0fff0 6ff0fff0 6ff0fff0 cc0084d0 .*
+  0x000010a4 6ff0fff0 6ff0fff0 6ff0fff0 0000002a .*
+  0x000010b4 0000002b 00090009 00090009 00090000 .*
+  0x000010c4 e10f0009 00090009 00090009 00090009 .*
+  0x000010d4 00090009 0009e10e                   .*
+
+Hex dump of section '\.cranges':
+  0x00000000 00001004 000000a0 00030000 10a40000 .*
+  0x00000010 000c0003 000010b0 00000008 00010000 .*
+  0x00000020 10b80000 00040002 000010bc 00000006 .*
+  0x00000030 00020000 10c40000 00180002          .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange3.dd b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange3.dd
new file mode 100644
index 0000000..135f1c9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange3.dd
@@ -0,0 +1,80 @@
+
+.*:     file format elf32-sh64
+
+Disassembly of section .init:
+
+00001000 <start>:
+    1000:	6ff0fff0 	nop	
+Disassembly of section .text:
+
+00001004 <sec4>:
+    1004:	6ff0fff0 	nop	
+    1008:	6ff0fff0 	nop	
+    100c:	6ff0fff0 	nop	
+    1010:	6ff0fff0 	nop	
+    1014:	6ff0fff0 	nop	
+    1018:	6ff0fff0 	nop	
+    101c:	cc00bd40 	movi	47,r20
+    1020:	6ff0fff0 	nop	
+    1024:	6ff0fff0 	nop	
+    1028:	6ff0fff0 	nop	
+    102c:	6ff0fff0 	nop	
+    1030:	6ff0fff0 	nop	
+    1034:	6ff0fff0 	nop	
+    1038:	6ff0fff0 	nop	
+    103c:	6ff0fff0 	nop	
+    1040:	6ff0fff0 	nop	
+    1044:	6ff0fff0 	nop	
+    1048:	6ff0fff0 	nop	
+    104c:	6ff0fff0 	nop	
+    1050:	cc00bd50 	movi	47,r21
+    1054:	cc0084c0 	movi	33,r12
+    1058:	6ff0fff0 	nop	
+    105c:	6ff0fff0 	nop	
+    1060:	6ff0fff0 	nop	
+    1064:	6ff0fff0 	nop	
+    1068:	6ff0fff0 	nop	
+    106c:	6ff0fff0 	nop	
+    1070:	6ff0fff0 	nop	
+    1074:	6ff0fff0 	nop	
+    1078:	6ff0fff0 	nop	
+    107c:	6ff0fff0 	nop	
+    1080:	6ff0fff0 	nop	
+    1084:	6ff0fff0 	nop	
+    1088:	6ff0fff0 	nop	
+    108c:	6ff0fff0 	nop	
+    1090:	6ff0fff0 	nop	
+    1094:	6ff0fff0 	nop	
+    1098:	6ff0fff0 	nop	
+    109c:	6ff0fff0 	nop	
+    10a0:	cc0084d0 	movi	33,r13
+
+000010a4 <diversion2>:
+    10a4:	6ff0fff0 	nop	
+    10a8:	6ff0fff0 	nop	
+    10ac:	6ff0fff0 	nop	
+    10b0:	00 00 00 2a 	\.long 0x0000002a
+    10b4:	00 00 00 2b 	\.long 0x0000002b
+    10b8:	00 09       	nop	
+    10ba:	00 09       	nop	
+
+000010bc <sec3>:
+    10bc:	00 09       	nop	
+    10be:	00 09       	nop	
+    10c0:	00 09       	nop	
+	\.\.\.
+
+000010c4 <diversion>:
+    10c4:	e1 0f       	mov	#15,r1
+    10c6:	00 09       	nop	
+    10c8:	00 09       	nop	
+    10ca:	00 09       	nop	
+    10cc:	00 09       	nop	
+    10ce:	00 09       	nop	
+    10d0:	00 09       	nop	
+    10d2:	00 09       	nop	
+    10d4:	00 09       	nop	
+    10d6:	00 09       	nop	
+    10d8:	00 09       	nop	
+    10da:	e1 0e       	mov	#14,r1
+
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crange3.rd b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange3.rd
new file mode 100644
index 0000000..7426dab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crange3.rd
@@ -0,0 +1,60 @@
+.*
+
+Section Headers:
+  \[Nr\] Name              Type            Addr     Off    Size   ES Flg Lk Inf Al
+  \[ 0\]                   NULL            00000000 000000 000000 00      0   0  0
+  \[ 1\] \.init             PROGBITS        00001000 000080 000004 00 AXp  0   0  4
+  \[ 2\] \.text             PROGBITS        00001004 000084 0000d8 00 AXp  0   0  4
+  \[ 3\] \.stack            PROGBITS        00080000 000180 000004 00  WA  0   0  1
+  \[ 4\] \.cranges          LOUSER\+1        00000000 000184 00003c 00   W  0   0  1
+  \[ 5\] \.shstrtab         STRTAB          .*
+  \[ 6\] \.symtab           SYMTAB          .*
+  \[ 7\] \.strtab           STRTAB          .*
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+   Num:    Value  Size Type    Bind   Vis      Ndx Name
+.*: 00000000     0 NOTYPE  LOCAL  DEFAULT  UND 
+.*: 00001000     0 SECTION LOCAL  DEFAULT    1 
+.*: 00001004     0 SECTION LOCAL  DEFAULT    2 
+.*: 00080000     0 SECTION LOCAL  DEFAULT    3 
+.*: 00000000     0 SECTION LOCAL  DEFAULT    4 
+.*: 00001004     0 NOTYPE  LOCAL  DEFAULT    2 sec4
+.*: 000010a4     0 NOTYPE  LOCAL  DEFAULT \[<other>: 4\]     2 start2
+.*: 000010bc     0 NOTYPE  LOCAL  DEFAULT    2 sec3
+.*: 000010c4     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     2 diversion
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT    .* ___dtors
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT    .* ___ctors_end
+.*: 000010a4     0 NOTYPE  GLOBAL DEFAULT    2 diversion2
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT    .* ___ctors
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT  ABS _end
+.*: 00001000     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 start
+.*: 00080000     0 NOTYPE  GLOBAL DEFAULT    3 _stack
+.*: 00001160     0 NOTYPE  GLOBAL DEFAULT    .* ___dtors_end
+
+Hex dump of section '\.text':
+  0x00001004 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001014 6ff0fff0 6ff0fff0 cc00bd40 6ff0fff0 .*
+  0x00001024 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001034 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001044 6ff0fff0 6ff0fff0 6ff0fff0 cc00bd50 .*
+  0x00001054 cc0084c0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001064 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001074 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001084 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00001094 6ff0fff0 6ff0fff0 6ff0fff0 cc0084d0 .*
+  0x000010a4 6ff0fff0 6ff0fff0 6ff0fff0 0000002a .*
+  0x000010b4 0000002b 00090009 00090009 00090000 .*
+  0x000010c4 e10f0009 00090009 00090009 00090009 .*
+  0x000010d4 00090009 0009e10e                   .*
+
+Hex dump of section '\.cranges':
+  0x00000000 00001004 000000a0 00030000 10a40000 .*
+  0x00000010 000c0003 000010b0 00000008 00010000 .*
+  0x00000020 10b80000 00040002 000010bc 00000006 .*
+  0x00000030 00020000 10c40000 00180002          .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crangerel1.rd b/binutils-2.19/ld/testsuite/ld-sh/sh64/crangerel1.rd
new file mode 100644
index 0000000..7b133c6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crangerel1.rd
@@ -0,0 +1,46 @@
+There are 11 section headers, starting at offset 0xbc:
+
+Section Headers:
+  \[Nr\] Name              Type            Addr     Off    Size   ES Flg Lk Inf Al
+  \[ 0\]                   NULL            00000000 000000 000000 00      0   0  0
+  \[ 1\] \.text             PROGBITS        00000000 000034 000000 00  AX  0   0  1
+  \[ 2\] \.text\.mixed       PROGBITS        00000000 000034 000018 00 AXp  0   0  4
+  \[ 3\] \.data             PROGBITS        00000000 00004c 000000 00  WA  0   0  1
+  \[ 4\] \.bss              NOBITS          00000000 00004c 000000 00  WA  0   0  1
+  \[ 5\] \.stack            PROGBITS        00000000 00004c 000004 00  WA  0   0  1
+  \[ 6\] \.cranges          PROGBITS        00000000 000050 00001e 00   W  0   0  1
+  \[ 7\] \.rela\.cranges     RELA            00000000 000274 000024 0c      9   6  4
+  \[ 8\] \.shstrtab         STRTAB          00000000 00006e 00004d 00      0   0  1
+  \[ 9\] \.symtab           SYMTAB          00000000 000298 000090 10     10   8  4
+  \[10\] \.strtab           STRTAB          00000000 000328 000013 00      0   0  1
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+Relocation section '\.rela\.cranges' at offset 0x[0-9a-f]+ contains 3 entries:
+.*
+0*00000000  0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0
+0*0000000a  0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0
+0*00000014  0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0
+
+Symbol table '\.symtab' contains 9 entries:
+   Num:    Value  Size Type    Bind   Vis      Ndx Name
+     0: 00000000     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 00000000     0 SECTION LOCAL  DEFAULT    1 
+     2: 00000000     0 SECTION LOCAL  DEFAULT    2 
+     3: 00000000     0 SECTION LOCAL  DEFAULT    3 
+     4: 00000000     0 SECTION LOCAL  DEFAULT    4 
+     5: 00000000     0 SECTION LOCAL  DEFAULT    5 
+     6: 00000000     0 SECTION LOCAL  DEFAULT    6 
+     7: 00000000     0 NOTYPE  LOCAL  DEFAULT \[<other>: 4\]     2 start2
+     8: 00000000     0 NOTYPE  GLOBAL DEFAULT    2 diversion2
+
+Hex dump of section '\.text\.mixed':
+  0x00000000 6ff0fff0 6ff0fff0 6ff0fff0 0000002a .*
+  0x00000010 0000002b 00090009                   .*
+
+Hex dump of section '\.cranges':
+.*
+  0x00000000 00000000 0000000c 00030000 000c0000 .*
+  0x00000010 00080001 00000014 00000004 0002     .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/crangerel2.rd b/binutils-2.19/ld/testsuite/ld-sh/sh64/crangerel2.rd
new file mode 100644
index 0000000..635acfc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/crangerel2.rd
@@ -0,0 +1,61 @@
+There are 11 section headers, starting at offset 0x128:
+
+Section Headers:
+  \[Nr\] Name              Type            Addr     Off    Size   ES Flg Lk Inf Al
+  \[ 0\]                   NULL            00000000 000000 000000 00      0   0  0
+  \[ 1\] \.text             PROGBITS        00000000 000034 000000 00  AX  0   0  1
+  \[ 2\] \.text\.mixed       PROGBITS        00000000 000034 00005c 00 AXp  0   0  4
+  \[ 3\] \.data             PROGBITS        00000000 000090 000000 00  WA  0   0  1
+  \[ 4\] \.bss              NOBITS          00000000 000090 000000 00  WA  0   0  1
+  \[ 5\] \.stack            PROGBITS        00000000 000090 000004 00  WA  0   0  1
+  \[ 6\] \.cranges          PROGBITS        00000000 000094 000046 00   W  0   0  1
+  \[ 7\] \.rela\.cranges     RELA            00000000 0002e0 000054 0c      9   6  4
+  \[ 8\] \.shstrtab         STRTAB          00000000 0000da 00004d 00      0   0  1
+  \[ 9\] \.symtab           SYMTAB          00000000 000334 0000d0 10     10  12  4
+  \[10\] \.strtab           STRTAB          00000000 000404 000027 00      0   0  1
+Key to Flags:
+  W \(write\), A \(alloc\), X \(execute\), M \(merge\), S \(strings\)
+  I \(info\), L \(link order\), G \(group\), x \(unknown\)
+  O \(extra OS processing required\) o \(OS specific\), p \(processor specific\)
+
+Relocation section '\.rela\.cranges' at offset 0x[0-9a-f]+ contains 7 entries:
+.*
+0*00000000 +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0
+0*0000000a +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0
+0*00000014 +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0
+0*0000001e +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0
+0*00000028 +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0
+0*00000032 +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0
+0*0000003c +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0
+
+Symbol table '\.symtab' contains 13 entries:
+   Num:    Value  Size Type    Bind   Vis      Ndx Name
+     0: 00000000     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 00000000     0 SECTION LOCAL  DEFAULT    1 
+     2: 00000000     0 SECTION LOCAL  DEFAULT    2 
+     3: 00000000     0 SECTION LOCAL  DEFAULT    3 
+     4: 00000000     0 SECTION LOCAL  DEFAULT    4 
+     5: 00000000     0 SECTION LOCAL  DEFAULT    5 
+     6: 00000000     0 SECTION LOCAL  DEFAULT    6 
+     7: 00000000     0 NOTYPE  LOCAL  DEFAULT \[<other>: 4\]     2 start2
+     8: 00000018     0 NOTYPE  LOCAL  DEFAULT \[<other>: 4\]     2 sec1
+     9: 00000028     0 NOTYPE  LOCAL  DEFAULT \[<other>: 4\]     2 sec2
+    10: 0000003c     0 NOTYPE  LOCAL  DEFAULT    2 sec3
+    11: 00000044     0 NOTYPE  LOCAL  DEFAULT    2 sec4
+    12: 00000000     0 NOTYPE  GLOBAL DEFAULT    2 diversion2
+
+Hex dump of section '\.text\.mixed':
+  0x00000000 6ff0fff0 6ff0fff0 6ff0fff0 0000002a .*
+  0x00000010 0000002b 00090009 6ff0fff0 6ff0fff0 .*
+  0x00000020 6ff0fff0 6ff0fff0 00000029 0000002b .*
+  0x00000030 0000002a 0000002b 0000002a 00090009 .*
+  0x00000040 00090000 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00000050 6ff0fff0 6ff0fff0 6ff0fff0          .*
+
+Hex dump of section '\.cranges':
+.*
+  0x00000000 00000000 0000000c 00030000 000c0000 .*
+  0x00000010 00080001 00000014 00000004 00020000 .*
+  0x00000020 00180000 00100003 00000028 00000014 .*
+  0x00000030 00010000 003c0000 00060002 00000044 .*
+  0x00000040 00000018 0003                       .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/dlsection-1.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/dlsection-1.s
new file mode 100644
index 0000000..d83e6e1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/dlsection-1.s
@@ -0,0 +1,17 @@
+! Test gc-sections and datalabel references.
+!
+! Datalabel reference to symbol in section .text2 should
+! prevent .text2 from being discarded.
+! Section .spurious can be discarded.
+	.mode SHmedia
+
+	.text
+	.global start
+	.global foo
+start:	.long datalabel foo
+
+	.section .text2,"ax"
+foo:	.long 23
+		
+	.section .spurious,"ax"
+	.long 17
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/dlsection.sd b/binutils-2.19/ld/testsuite/ld-sh/sh64/dlsection.sd
new file mode 100644
index 0000000..58bf965
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/dlsection.sd
@@ -0,0 +1,9 @@
+
+.*:     file format elf.*-sh64
+
+Contents of section \.text:
+ 1000 00001004  .*
+Contents of section \.text2:
+ 1004 00000017  .*
+Contents of section \.stack:
+ 80000 deaddead                            .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.dbd b/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.dbd
new file mode 100644
index 0000000..0369cbc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.dbd
@@ -0,0 +1,11 @@
+
+.*:[ 	]*file[ 	]*format[ 	]*elf64-sh64
+
+Disassembly[ 	]*of[ 	]*section[ 	]*.text:
+
+0000000000000000[ 	]*<start>:
+[ 	]*0:[ 	]*cc48d000[ 	]*movi[ 	]*4660,r0
+[ 	]*4:[ 	]*12345678[ 	]*.long[ 	]*0x12345678
+[ 	]*8:[ 	]*12340000[ 	]*.long[ 	]*0x12340000
+[ 	]*c:[ 	]*12345678[ 	]*.long[ 	]*0x12345678
+
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.dld b/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.dld
new file mode 100644
index 0000000..f3c5bd5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.dld
@@ -0,0 +1,11 @@
+
+.*:[ 	]*file[ 	]*format[ 	]*elf64-sh64l
+
+Disassembly[ 	]*of[ 	]*section[ 	]*.text:
+
+0000000000000000[ 	]*<start>:
+[ 	]*0:[ 	]*cc48d000[ 	]*movi[ 	]*4660,r0
+[ 	]*4:[ 	]*12345678[ 	]*.long[ 	]*0x12345678
+[ 	]*8:[ 	]*00001234[ 	]*.long[ 	]*0x00001234
+[ 	]*c:[ 	]*12345678[ 	]*.long[ 	]*0x12345678
+
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.ld b/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.ld
new file mode 100644
index 0000000..e9635e1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.ld
@@ -0,0 +1,6 @@
+SECTIONS {
+  .text : {
+     *(.text)
+     LONG(0x12345678);
+  }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.s
new file mode 100644
index 0000000..79bc9e4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.s
@@ -0,0 +1,7 @@
+	.text
+	.mode shmedia
+start:
+
+	movi	0x1234,r0
+	.long	0x12345678
+	.word	0x1234, 0
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.sbd b/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.sbd
new file mode 100644
index 0000000..462f66d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.sbd
@@ -0,0 +1,5 @@
+
+.*:     file format elf64-sh64
+
+Contents of section .text:
+ 0000 cc48d000 12345678 12340000 12345678.*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.sld b/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.sld
new file mode 100644
index 0000000..00975cb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/endian.sld
@@ -0,0 +1,6 @@
+
+.*:     file format elf64-sh64l
+
+Contents of section .text:
+ 0000 00d048cc 78563412 34120000 78563412.*
+
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/gotplt.d b/binutils-2.19/ld/testsuite/ld-sh/sh64/gotplt.d
new file mode 100644
index 0000000..5822326
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/gotplt.d
@@ -0,0 +1,12 @@
+#source: gotplt.s
+#as: --abi=32 --isa=SHmedia
+#ld: -shared -mshelf32 --version-script=$srcdir/$subdir/gotplt.map
+#readelf: -r
+#target: sh64-*-elf
+
+# Make sure that gotplt relocations of forced local symbols
+# use the GOT.
+
+Relocation section '\.rela\.dyn' at offset .* contains 1 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+[0-9a-f ]+R_SH_RELATIVE[0-9a-f ]+
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/gotplt.map b/binutils-2.19/ld/testsuite/ld-sh/sh64/gotplt.map
new file mode 100644
index 0000000..a27c22c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/gotplt.map
@@ -0,0 +1,4 @@
+GLIBC_2.2 {
+  local:
+    xxx;
+};
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/gotplt.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/gotplt.s
new file mode 100644
index 0000000..45ed0b2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/gotplt.s
@@ -0,0 +1,8 @@
+	.text
+	.global	xxx
+xxx:
+	ptabs	r18, tr0
+	blink	tr0, r63
+	.global	yyy
+yyy:
+	movi	((xxx@GOTPLT) & 65535), r1
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/init-cmpct.d b/binutils-2.19/ld/testsuite/ld-sh/sh64/init-cmpct.d
new file mode 100644
index 0000000..6f64bc4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/init-cmpct.d
@@ -0,0 +1,14 @@
+#source: init.s
+#as: --abi=32 --isa=SHcompact
+#ld: -shared -mshelf32
+#readelf: -d
+#target: sh64-*-elf
+
+# Make sure that the lsb of DT_INIT and DT_FINI entries is not set
+# when _init and _fini are SHcompact code.
+
+Dynamic section at offset .* contains 8 entries:
+  Tag        Type                         Name/Value
+ 0x0000000c \(INIT\) .*[02468ace]
+ 0x0000000d \(FINI\) .*[02468ace]
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/init-media.d b/binutils-2.19/ld/testsuite/ld-sh/sh64/init-media.d
new file mode 100644
index 0000000..56c6c19
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/init-media.d
@@ -0,0 +1,14 @@
+#source: init.s
+#as: --abi=32 --isa=SHmedia
+#ld: -shared -mshelf32
+#readelf: -d
+#target: sh64-*-elf
+
+# Make sure that the lsb of DT_INIT and DT_FINI entries is set
+# when _init and _fini are SHmedia code.
+
+.*
+  Tag        Type                         Name/Value
+ 0x0000000c \(INIT\) .*[13579bdf]
+ 0x0000000d \(FINI\) .*[13579bdf]
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/init.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/init.s
new file mode 100644
index 0000000..900e764
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/init.s
@@ -0,0 +1,18 @@
+	.section .text,"ax"
+	.global _init
+	.type _init,@function
+	.align 1
+_init:
+	nop
+	nop
+	nop
+	nop
+
+	.global _fini
+	.type _fini,@function
+	.align 1
+_fini:
+	nop
+	nop
+	nop
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/init64.d b/binutils-2.19/ld/testsuite/ld-sh/sh64/init64.d
new file mode 100644
index 0000000..01c8e97
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/init64.d
@@ -0,0 +1,14 @@
+#source: init.s
+#as: --abi=64
+#ld: -shared -mshelf64
+#readelf: -d
+#target: sh64-*-elf
+
+# Make sure that the lsb of DT_INIT and DT_FINI entries is set
+# when _init and _fini are SHmedia code.
+
+.*
+  Tag        Type                         Name/Value
+ 0x000000000000000c \(INIT\) .*[13579bdf]
+ 0x000000000000000d \(FINI\) .*[13579bdf]
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/mix1-noexp.sd b/binutils-2.19/ld/testsuite/ld-sh/sh64/mix1-noexp.sd
new file mode 100644
index 0000000..fe73136
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/mix1-noexp.sd
@@ -0,0 +1,14 @@
+
+.*:     file format .*-sh64
+
+Contents of section \.text:
+ 1000 8902c700 00090009 00090009 0000100c  .*
+ 1010 00001004 00001021 effff240 efffea50  .*
+ 1020 cc401360 cc4086d0 ebfffa70 6ff0fff0  .*
+Contents of section \.data:
+ 10b0 000010b0 00001004 00001021           .*
+Contents of section \.stack:
+ 80000 deaddead                            .*
+Contents of section \.cranges:
+ 0000 00001000 00000018 00020000 10180000  .*
+ 0010 00180003                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/mix1.sd b/binutils-2.19/ld/testsuite/ld-sh/sh64/mix1.sd
new file mode 100644
index 0000000..c5cc4b1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/mix1.sd
@@ -0,0 +1,16 @@
+
+.*:     file format .*-sh64
+
+Contents of section \.text:
+ 1000 8902c700 00090009 00090009 0000100c  .*
+ 1010 00001004 00001031 cffffd90 cbffa190  .*
+ 1020 6bf56640 cffffd90 cbff6190 6bf56650  .*
+ 1030 cc000360 c8401360 cc0002d0 c840c6d0  .*
+ 1040 ebfff270 6ff0fff0                    .*
+Contents of section \.data:
+ 10c8 000010c8 00001004 00001031           .*
+Contents of section \.stack:
+ 80000 deaddead                            .*
+Contents of section \.cranges:
+ 0000 00001000 00000018 00020000 10180000  .*
+ 0010 00300003                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/mix1.xd b/binutils-2.19/ld/testsuite/ld-sh/sh64/mix1.xd
new file mode 100644
index 0000000..de72ce0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/mix1.xd
@@ -0,0 +1,42 @@
+
+.*:     file format .*-sh64
+.*
+architecture: sh5, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x0+1000
+
+Program Header:
+    LOAD off    0x0+100 vaddr 0x0+1000 paddr 0x0+1000 align 2\*\*7
+         filesz 0x0+48 memsz 0x0+48 flags r-x
+    LOAD off    0x0+148 vaddr 0x0+10c8 paddr 0x0+10c8 align 2\*\*7
+         filesz 0x0+c memsz 0x0+c flags rw-
+    LOAD off    0x0+180 vaddr 0x0+80000 paddr 0x0+80000 align 2\*\*7
+         filesz 0x0+4 memsz 0x0+4 flags rw-
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 \.text         00000048  0+1000  0+1000  00000100  2\*\*2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 \.data         0000000c  0+10c8  0+10c8  00000148  2\*\*2
+                  CONTENTS, ALLOC, LOAD, DATA
+  2 \.stack        00000004  0+80000  0+80000  00000180  2\*\*0
+                  CONTENTS, ALLOC, LOAD, DATA
+  3 \.cranges      00000014  0+  0+  00000184  2\*\*0
+                  CONTENTS, DEBUGGING, SORT_ENTRIES
+SYMBOL TABLE:
+0+1000 l    d  \.text	0+ (|\.text)
+0+10c8 l    d  \.data	0+ (|\.data)
+0+80000 l    d  \.stack	0+ (|\.stack)
+0+ l    d  \.cranges	0+ (|\.cranges)
+0+1008 l       \.text	0+ forw
+0+1004 l       \.text	0+ start2
+0+1030 l       \.text	0+ 0x04 mediacode2
+0+1018 l       \.text	0+ 0x04 mediacode
+0+10c8 g       .*	0+ ___dtors
+0+10d8 g       \*ABS\*	0+ __bss_start
+0+10c8 g       .*	0+ ___ctors_end
+0+10c8 g       .*	0+ ___ctors
+0+10d8 g       \*ABS\*	0+ _edata
+0+10d8 g       \*ABS\*	0+ _end
+0+1000 g       \.text	0+ start
+0+80000 g       \.stack	0+ _stack
+0+10c8 g       .*	0+ ___dtors_end
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/mix2-noexp.sd b/binutils-2.19/ld/testsuite/ld-sh/sh64/mix2-noexp.sd
new file mode 100644
index 0000000..9112cfc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/mix2-noexp.sd
@@ -0,0 +1,16 @@
+
+.*:     file format .*-sh64
+
+Contents of section \.text:
+ 1000 cc4048e0 cc40c0e0 ec000e60 6ff0fff0  .*
+ 1010 0009c700 c7000009 00090009 00001009  .*
+ 1020 000010bc                             .*
+Contents of section \.rodata:
+ 1024 00001018 000010c4 0000100d 00001028  .*
+Contents of section \.data:
+ 10b8 00000000 00001014 00000000 000010bc  .*
+Contents of section \.stack:
+ 80000 deaddead                            .*
+Contents of section \.cranges:
+ 0000 00001000 00000010 00030000 10100000  .*
+ 0010 00140002                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/mix2.sd b/binutils-2.19/ld/testsuite/ld-sh/sh64/mix2.sd
new file mode 100644
index 0000000..122a472
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/mix2.sd
@@ -0,0 +1,17 @@
+
+.*:     file format .*-sh64
+
+Contents of section \.text:
+ 1000 cc0000e0 c84088e0 cc0000e0 c84100e0  .*
+ 1010 cc000190 c8003190 6bf56660 6ff0fff0  .*
+ 1020 0009c700 c7000009 00090009 00001011  .*
+ 1030 000010cc                             .*
+Contents of section \.rodata:
+ 1034 00001028 000010d4 0000101d 00001038  .*
+Contents of section \.data:
+ 10c8 00000000 00001024 00000000 000010cc  .*
+Contents of section \.stack:
+ 80000 deaddead                            .*
+Contents of section \.cranges:
+ 0000 00001000 00000020 00030000 10200000  .*
+ 0010 00140002                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/mix2.xd b/binutils-2.19/ld/testsuite/ld-sh/sh64/mix2.xd
new file mode 100644
index 0000000..5c72763
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/mix2.xd
@@ -0,0 +1,52 @@
+
+.*:     file format .*-sh64
+.*
+architecture: sh5, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x0+1001
+
+Program Header:
+    LOAD off    0x0+100 vaddr 0x0+1000 paddr 0x0+1000 align 2\*\*7
+         filesz 0x0+44 memsz 0x0+44 flags r-x
+    LOAD off    0x0+148 vaddr 0x0+10c8 paddr 0x0+10c8 align 2\*\*7
+         filesz 0x0+10 memsz 0x0+10 flags rw-
+    LOAD off    0x0+180 vaddr 0x0+80000 paddr 0x0+80000 align 2\*\*7
+         filesz 0x0+4 memsz 0x0+4 flags rw-
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 \.text         00000034  0+1000  0+1000  00000100  2\*\*2
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 \.rodata       00000010  0+1034  0+1034  00000134  2\*\*2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  2 \.data         00000010  0+10c8  0+10c8  00000148  2\*\*2
+                  CONTENTS, ALLOC, LOAD, DATA
+  3 \.stack        00000004  0+80000  0+80000  00000180  2\*\*0
+                  CONTENTS, ALLOC, LOAD, DATA
+  4 \.cranges      00000014  0+  0+  00000184  2\*\*0
+                  CONTENTS, DEBUGGING, SORT_ENTRIES
+SYMBOL TABLE:
+0+1000 l    d  \.text	0+ (|\.text)
+0+1034 l    d  \.rodata	0+ (|\.rodata)
+0+10c8 l    d  \.data	0+ (|\.data)
+0+80000 l    d  \.stack	0+ (|\.stack)
+0+ l    d  \.cranges	0+ (|\.cranges)
+0+1020 l       \.text	0+ locallabel
+0+1040 g       \.rodata	0+ compactlabel4
+0+101c g       \.text	0+ 0x04 medialabel2
+0+1038 g       \.rodata	0+ medialabel3
+0+1022 g       \.text	0+ compactlabel1
+0+1024 g       \.text	0+ compactlabel2
+0+1028 g       \.text	0+ compactlabel3
+0+1010 g       \.text	0+ 0x04 medialabel1
+0+10c8 g       .*	0+ ___dtors
+0+10cc g       \.data	0+ medialabel4
+0+10d8 g       \*ABS\*	0+ __bss_start
+0+10c8 g       .*	0+ ___ctors_end
+0+10d4 g       \.data	0+ compactlabel5
+0+10c8 g       .*	0+ ___ctors
+0+10d8 g       \*ABS\*	0+ _edata
+0+10d8 g       \*ABS\*	0+ _end
+0+1000 g       \.text	0+ 0x04 start
+0+80000 g       \.stack	0+ _stack
+0+10c8 g       .*	0+ ___dtors_end
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/rd-sh64.exp b/binutils-2.19/ld/testsuite/ld-sh/sh64/rd-sh64.exp
new file mode 100644
index 0000000..5d72369
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/rd-sh64.exp
@@ -0,0 +1,44 @@
+# Expect script for run_dump_test based ld-sh/sh64 tests.
+#   Copyright 2002, 2003, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Stephen Clarke (stephen.clarke@superh.com)
+#
+
+if ![istarget sh64-*-*] {
+    return
+}
+
+set rd_test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach sh64test $rd_test_list {
+    # We need to strip the ".d", but can leave the dirname.
+    verbose [file rootname $sh64test]
+    run_dump_test [file rootname $sh64test]
+    if [string match $srcdir/$subdir/*-dso.d $sh64test] {
+	# Copy the output of the DSO-createing test to .so file.
+	# Notice that a DSO-creating test must preceed the tests
+	# which need that DSO in sort-order by name.
+	set cmd "cp tmpdir/dump \
+		    tmpdir/[file rootname [file tail $sh64test]].so"
+	send_log "$cmd\n"
+	set cmdret [catch "exec $cmd" comp_output]
+	send_log "$comp_output\n"
+	# FIXME: What if it fails?  Need we do something?
+    }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/rel-1.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/rel-1.s
new file mode 100644
index 0000000..6cf18ca
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/rel-1.s
@@ -0,0 +1,48 @@
+! Relative linking, simple files with global symbols but nothing really
+! strange.  Reference from same and other file to .text and .data in
+! different combinations.
+
+! fileFsectionN, with F in rel-F.s, and N in:
+! 1 - Same file and section.
+! 2 - Same file, different section.
+! 3 - Other file, same section.
+! 4 - Other file, other section.
+
+	.mode SHmedia
+	.text
+	.global start
+start:
+	nop
+	.global file1text1
+file1text1:
+	nop
+	movi file1text1 & 65535,r10
+	.global file1text2
+file1text2:
+	movi file1data2 & 65535,r20
+	.global file1text3
+file1text3:
+	movi file2text3 & 65535,r20
+	.global file1text4
+file1text4:
+	movi file2data4 & 65535,r20
+	movi unresolved1 & 65535,r40
+	movi unresolved6 & 65535,r30
+
+	.data
+	.long 0
+	.global file1data1
+file1data1:
+	.long 0
+	.long file1data1
+	.global file1data2
+file1data2:
+	.long file1text2
+	.global file1data3
+file1data3:
+	.long file2data3
+	.global file1data4
+file1data4:
+	.long file2text4
+	.long unresolved2
+	.long unresolved5
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/rel-2.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/rel-2.s
new file mode 100644
index 0000000..b1931b5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/rel-2.s
@@ -0,0 +1,46 @@
+! Relative linking, second file.
+
+! fileFsectionN, with F in rel-F.s, and N in:
+! 1 - Same file and section.
+! 2 - Same file, different section.
+! 3 - Other file, same section.
+! 4 - Other file, other section.
+
+	.mode SHmedia
+	.text
+	.global start2
+start2:
+	nop
+	.global file2text1
+file2text1:
+	nop
+	movi file2text1 & 65535,r10
+	.global file2text2
+file2text2:
+	movi file2data2 & 65535,r20
+	.global file2text3
+file2text3:
+	movi file1text3 & 65535,r20
+	.global file2text4
+file2text4:
+	movi file1data4 & 65535,r20
+	movi unresolved1 & 65535,r30
+	movi unresolved3 & 65535,r30
+
+	.data
+	.long 0
+	.global file2data1
+file2data1:
+	.long 0
+	.long file2data1
+	.global file2data2
+file2data2:
+	.long file2text2
+	.global file2data3
+file2data3:
+	.long file1data3
+	.global file2data4
+file2data4:
+	.long file1text4
+	.long unresolved2
+	.long unresolved4
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/rel32.xd b/binutils-2.19/ld/testsuite/ld-sh/sh64/rel32.xd
new file mode 100644
index 0000000..65c00ac
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/rel32.xd
@@ -0,0 +1,92 @@
+
+.*:     file format .*-sh64
+.*
+architecture: sh5, flags 0x0+11:
+HAS_RELOC, HAS_SYMS
+start address 0x0+
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 \.text         0+40  0+  0+  0+34  2\*\*0
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  1 \.data         0+40  0+  0+  0+74  2\*\*2
+                  CONTENTS, ALLOC, LOAD, RELOC, DATA
+  2 \.bss          0+  0+  0+  0+b4  2\*\*0
+                  ALLOC
+  3 \.stack        0+4  0+  0+  0+b4  2\*\*0
+                  CONTENTS, ALLOC, LOAD, DATA
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|.text)
+0+ l    d  \.data	0+ (|.data)
+0+ l    d  \.bss	0+ (|.bss)
+0+ l    d  \.stack	0+ (|.stack)
+0+         \*UND\*	0+ unresolved5
+0+c g       \.text	0+ 0x04 file1text2
+0+24 g       \.text	0+ 0x04 file2text1
+0+4 g       \.data	0+ file1data1
+0+34 g       \.data	0+ file2data4
+0+10 g       \.text	0+ 0x04 file1text3
+0+2c g       \.data	0+ file2data2
+0+c g       \.data	0+ file1data2
+0+30 g       \.text	0+ 0x04 file2text3
+0+20 g       \.text	0+ 0x04 start2
+0+         \*UND\*	0+ unresolved1
+0+         \*UND\*	0+ unresolved6
+0+4 g       \.text	0+ 0x04 file1text1
+0+2c g       \.text	0+ 0x04 file2text2
+0+         \*UND\*	0+ unresolved3
+0+34 g       \.text	0+ 0x04 file2text4
+0+         \*UND\*	0+ unresolved2
+0+ g       \.text	0+ 0x04 start
+0+14 g       \.text	0+ 0x04 file1text4
+0+30 g       \.data	0+ file2data3
+0+         \*UND\*	0+ unresolved4
+0+24 g       \.data	0+ file2data1
+0+10 g       \.data	0+ file1data3
+0+14 g       \.data	0+ file1data4
+
+
+RELOCATION RECORDS FOR \[\.text\]:
+OFFSET  *TYPE  *VALUE 
+0+8 R_SH_IMM_LOW16    file1text1
+0+c R_SH_IMM_LOW16    file1data2
+0+10 R_SH_IMM_LOW16    file2text3
+0+14 R_SH_IMM_LOW16    file2data4
+0+18 R_SH_IMM_LOW16    unresolved1
+0+1c R_SH_IMM_LOW16    unresolved6
+0+28 R_SH_IMM_LOW16    file2text1
+0+2c R_SH_IMM_LOW16    file2data2
+0+30 R_SH_IMM_LOW16    file1text3
+0+34 R_SH_IMM_LOW16    file1data4
+0+38 R_SH_IMM_LOW16    unresolved1
+0+3c R_SH_IMM_LOW16    unresolved3
+
+
+RELOCATION RECORDS FOR \[\.data\]:
+OFFSET  *TYPE  *VALUE 
+0+8 R_SH_DIR32        file1data1
+0+c R_SH_DIR32        file1text2
+0+10 R_SH_DIR32        file2data3
+0+14 R_SH_DIR32        file2text4
+0+18 R_SH_DIR32        unresolved2
+0+1c R_SH_DIR32        unresolved5
+0+28 R_SH_DIR32        file2data1
+0+2c R_SH_DIR32        file2text2
+0+30 R_SH_DIR32        file1data3
+0+34 R_SH_DIR32        file1text4
+0+38 R_SH_DIR32        unresolved2
+0+3c R_SH_DIR32        unresolved4
+
+
+Contents of section \.text:
+ 0000 6ff0fff0 6ff0fff0 cc0000a0 cc000140  .*
+ 0010 cc000140 cc000140 cc000280 cc0001e0  .*
+ 0020 6ff0fff0 6ff0fff0 cc0000a0 cc000140  .*
+ 0030 cc000140 cc000140 cc0001e0 cc0001e0  .*
+Contents of section \.data:
+ 0000 00000000 00000000 00000000 00000000  .*
+ 0010 00000000 00000000 00000000 00000000  .*
+ 0020 00000000 00000000 00000000 00000000  .*
+ 0030 00000000 00000000 00000000 00000000  .*
+Contents of section .stack:
+ 0000 deaddead                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/rel64.xd b/binutils-2.19/ld/testsuite/ld-sh/sh64/rel64.xd
new file mode 100644
index 0000000..986e013
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/rel64.xd
@@ -0,0 +1,92 @@
+
+.*:     file format .*-sh64
+.*
+architecture: sh5, flags 0x0+11:
+HAS_RELOC, HAS_SYMS
+start address 0x0+
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+40  0+  0+  0+40  2\*\*0
+                  CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
+  1 \.data         0+40  0+  0+  0+80  2\*\*2
+                  CONTENTS, ALLOC, LOAD, RELOC, DATA
+  2 \.bss          0+  0+  0+  0+c0  2\*\*0
+                  ALLOC
+  3 \.stack        0+4  0+  0+  0+c0  2\*\*0
+                  CONTENTS, ALLOC, LOAD, DATA
+SYMBOL TABLE:
+0+ l    d  \.text	0+ (|.text)
+0+ l    d  \.data	0+ (|.data)
+0+ l    d  \.bss	0+ (|.bss)
+0+ l    d  \.stack	0+ (|.stack)
+0+         \*UND\*	0+ unresolved5
+0+c g       \.text	0+ 0x04 file1text2
+0+24 g       \.text	0+ 0x04 file2text1
+0+4 g       \.data	0+ file1data1
+0+34 g       \.data	0+ file2data4
+0+10 g       \.text	0+ 0x04 file1text3
+0+2c g       \.data	0+ file2data2
+0+c g       \.data	0+ file1data2
+0+30 g       \.text	0+ 0x04 file2text3
+0+20 g       \.text	0+ 0x04 start2
+0+         \*UND\*	0+ unresolved1
+0+         \*UND\*	0+ unresolved6
+0+4 g       \.text	0+ 0x04 file1text1
+0+2c g       \.text	0+ 0x04 file2text2
+0+         \*UND\*	0+ unresolved3
+0+34 g       \.text	0+ 0x04 file2text4
+0+         \*UND\*	0+ unresolved2
+0+ g       \.text	0+ 0x04 start
+0+14 g       \.text	0+ 0x04 file1text4
+0+30 g       \.data	0+ file2data3
+0+         \*UND\*	0+ unresolved4
+0+24 g       \.data	0+ file2data1
+0+10 g       \.data	0+ file1data3
+0+14 g       \.data	0+ file1data4
+
+
+RELOCATION RECORDS FOR \[\.text\]:
+OFFSET           TYPE              VALUE 
+0+8 R_SH_IMM_LOW16    file1text1
+0+c R_SH_IMM_LOW16    file1data2
+0+10 R_SH_IMM_LOW16    file2text3
+0+14 R_SH_IMM_LOW16    file2data4
+0+18 R_SH_IMM_LOW16    unresolved1
+0+1c R_SH_IMM_LOW16    unresolved6
+0+28 R_SH_IMM_LOW16    file2text1
+0+2c R_SH_IMM_LOW16    file2data2
+0+30 R_SH_IMM_LOW16    file1text3
+0+34 R_SH_IMM_LOW16    file1data4
+0+38 R_SH_IMM_LOW16    unresolved1
+0+3c R_SH_IMM_LOW16    unresolved3
+
+
+RELOCATION RECORDS FOR \[\.data\]:
+OFFSET           TYPE              VALUE 
+0+8 R_SH_DIR32        file1data1
+0+c R_SH_DIR32        file1text2
+0+10 R_SH_DIR32        file2data3
+0+14 R_SH_DIR32        file2text4
+0+18 R_SH_DIR32        unresolved2
+0+1c R_SH_DIR32        unresolved5
+0+28 R_SH_DIR32        file2data1
+0+2c R_SH_DIR32        file2text2
+0+30 R_SH_DIR32        file1data3
+0+34 R_SH_DIR32        file1text4
+0+38 R_SH_DIR32        unresolved2
+0+3c R_SH_DIR32        unresolved4
+
+
+Contents of section \.text:
+ 0000 6ff0fff0 6ff0fff0 cc0000a0 cc000140  .*
+ 0010 cc000140 cc000140 cc000280 cc0001e0  .*
+ 0020 6ff0fff0 6ff0fff0 cc0000a0 cc000140  .*
+ 0030 cc000140 cc000140 cc0001e0 cc0001e0  .*
+Contents of section \.data:
+ 0000 00000000 00000000 00000000 00000000  .*
+ 0010 00000000 00000000 00000000 00000000  .*
+ 0020 00000000 00000000 00000000 00000000  .*
+ 0030 00000000 00000000 00000000 00000000  .*
+Contents of section .stack:
+ 0000 deaddead                             .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/relax.exp b/binutils-2.19/ld/testsuite/ld-sh/sh64/relax.exp
new file mode 100644
index 0000000..1a03ed5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/relax.exp
@@ -0,0 +1,155 @@
+# Expect script for ld-sh tests
+#   Copyright (C) 2001, 2002, 2003, 2004, 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Test SH relaxing - that is, that it's disabled when SHmedia sections
+# are present.
+
+if ![istarget sh64-*-*] {
+    return
+}
+
+# There are four source files: the first is SHcompact only, the second
+# is SHmedia only, the third has both, and the fourth has only a
+# .cranges section.  The table below has:
+#   Title
+#   as flags for first source (else "n/a" to skip)
+#   ditto, other three files
+#   ld flags
+#   1/0 whether relaxing should have been done or not, or -1 if we expect
+#     the linker to not produce an output file.
+
+if [istarget sh64*-*-linux*] {
+    set emul32 "shlelf32_linux"
+} elseif { [istarget sh64*-*-netbsd*] || [istarget sh5*-*-netbsd*] } {
+    set emul32 "shelf32_nbsd"
+} else {
+    set emul32 "shelf32"
+}
+
+set sh64relaxtests {
+    {"SH64 not relaxing, shcompact"
+      {"-relax -isa shcompact" "n/a" "n/a" "n/a"} "-m$emul32" 0}
+    {"SH64 relaxing, shcompact"
+      {"-relax -isa shcompact" "n/a" "n/a" "n/a"} "-relax -m$emul32" 1}
+    {"SH64 relaxing, shcompacts"
+      {"-relax -isa shcompact" "-isa shcompact" "n/a" "n/a"} "-relax -m$emul32" 1}
+    {"SH64 relaxing disabled, shmedia"
+      {"-relax -isa shcompact" "-isa shmedia -no-mix" "n/a" "n/a"} "-relax -m$emul32" 0}
+    {"SH64 relaxing disabled, mixed"
+      {"-relax -isa shcompact" "n/a" "-isa shcompact" "n/a"} "-relax -m$emul32" 0}
+    {"SH64 relaxing disabled, cranges"
+      {"-relax -isa shcompact" "n/a" "n/a" ""} "-relax -m$emul32" 0}
+}
+
+proc run_sh64relaxtest {sh64relaxtests} {
+    global ld
+    global as
+    global nm
+    global objdump
+    global readelf
+    global srcdir
+    global subdir
+    global emul32
+
+    set testindex 0
+    
+    set sh64relaxfiles {
+	"relax1.s" "relax2.s" "relax3.s" "relax4.s"
+    }
+    
+    foreach testentry $sh64relaxtests {
+	set testname [lindex $testentry 0]
+	set as_options [lindex $testentry 1]
+	set ld_options [subst [lindex $testentry 2]]
+	set expect_relaxed [lindex $testentry 3]
+	
+	set is_unresolved 0
+	set objfiles {}
+	
+	incr testindex
+	
+	# Assemble each file in the test.
+	for {set i 0} {$i < 4} {incr i} {
+	    set as_file [lindex $sh64relaxfiles $i]
+	    set as_opt [lindex $as_options $i]
+	    if { [string compare $as_opt "n/a"] != 0 } {
+		set objfile "tmpdir/[file rootname $as_file]-$testindex.o"
+		lappend objfiles $objfile
+		
+		if ![ld_assemble $as "$as_opt $srcdir/$subdir/$as_file" $objfile] {
+		    set is_unresolved 1
+		    break
+		}
+	    }
+	}
+	
+	# Catch assembler errors.
+	if { $is_unresolved != 0 } {
+	    unresolved $testname
+	    continue
+	}
+	
+	set binfile "tmpdir/relax-$testindex.x"
+	
+	# We're not interested in the pass/fail of the linker as much
+	# as we're interested in whether or not relaxing got properly
+	# disabled.  Hence the lax checking here.
+	
+	file delete $binfile
+	set result [ld_simple_link $ld $binfile " --no-warn-mismatch $ld_options $objfiles"]
+	if ![file exists $binfile] {
+	    
+	    if {$expect_relaxed == -1} {
+		pass $testname
+		continue
+	    }
+	    
+	    verbose "$testname: file $binfile doesn't exist" 1
+	    fail $testname
+	    continue
+	}
+	
+	catch "exec $objdump -d $binfile" objdump_output
+	
+	regexp "\[ \t](jsr|bsr)\[ \t]" $objdump_output ignore calltype
+	
+	if [string match $calltype "bsr"] {
+	    set relaxed 1
+	} elseif [string match $calltype "jsr"] {
+	    set relaxed 0
+	} else {
+	    verbose "$testname: neither jsr nor bsr found" 1
+	    verbose $objdump_output 2
+	    fail $testname
+	    continue
+	}
+	
+	if {$relaxed != $expect_relaxed} {
+	    verbose $objdump_output 2
+	    fail $testname
+	    exit
+	} else {
+	    pass $testname
+	}
+    }
+}
+
+run_sh64relaxtest $sh64relaxtests
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/relax1.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/relax1.s
new file mode 100644
index 0000000..873954b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/relax1.s
@@ -0,0 +1,12 @@
+	.globl	start
+start:
+.L3:
+	mov.l	.L4,r1
+	.uses	.L3
+	jsr	@r1
+	nop
+	nop
+.L4:
+	.long	.L5
+.L5:
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/relax2.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/relax2.s
new file mode 100644
index 0000000..9bf0802
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/relax2.s
@@ -0,0 +1,3 @@
+	.text
+foo1:
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/relax3.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/relax3.s
new file mode 100644
index 0000000..964bacd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/relax3.s
@@ -0,0 +1,8 @@
+	.text
+	.mode shmedia
+foo1:
+	nop
+
+	.mode shcompact
+foo2:
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/relax4.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/relax4.s
new file mode 100644
index 0000000..904df7c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/relax4.s
@@ -0,0 +1,2 @@
+	.section .cranges
+	.word	0
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/reldl-1.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/reldl-1.s
new file mode 100644
index 0000000..0aeb332
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/reldl-1.s
@@ -0,0 +1,171 @@
+! Relative linking.  Like the simple test, but mixing in use of
+! "datalabel" and offsets to the global symbols into the previous
+! combinations.
+!
+! More systematic testing datalabel references,
+! igoring section difference, symbol definition type and offset presence:
+! Datalabel reference plus:
+! (datalabel other file, other file, same file, none)
+! = (1, 2, 3, 4, 12, 13, 23, 123)
+!
+! Definition:
+! (none, same file, other file) = (a, b, c)
+!
+! Combined: 
+! = (a1, a2, a3, a4, a12, a13, a23, a123, b1, b2, b3, b4, b12,
+!    b13, b23, b123, c1, c2, c3, c4, c12, c13, c23, c123)
+
+	.mode SHmedia
+	.text
+	.global start
+start:
+	nop
+	.global file1text1
+file1text1:
+	nop
+	movi file1text1 & 65535,r10
+	.global file1text2
+file1text2:
+	movi (datalabel file1data2) & 65535,r20
+	.global file1text3
+file1text3:
+	movi file2text3 & 65535,r20
+	.global file1text4
+file1text4:
+	movi file2data4 & 65535,r20
+	.global file1text5
+file1text5:
+	movi unresolved1 & 65535,r40
+	.global b1
+b1:
+	movi unresolved6 & 65535,r30
+	.global b2
+b2:
+	movi (datalabel file1text1) & 65535,r10
+	.global b3
+b3:
+	movi (datalabel file1text1 + 24) & 65535,r10
+	.global b4
+b4:
+	movi (datalabel file1text5 + 8) & 65535, r40
+	.global b12
+b12:
+	movi (datalabel file1data2 + 48) & 65535,r20
+	.global b13
+b13:
+	movi file1data2 & 65535,r20
+	.global b23
+b23:
+	movi (datalabel file2data4 + 16),r50
+	.global b123
+b123:
+	movi (datalabel unresolved7) & 65535,r60
+	.global oc1
+oc1:
+	movi (datalabel unresolved1) & 65535,r60
+	.global oc2
+oc2:
+	nop
+	.global oc3
+oc3:
+	nop
+	.global oc4
+oc4:
+	nop
+	.global oc12
+oc12:
+	nop
+	.global oc13
+oc13:
+	nop
+	.global oc23
+oc23:
+	nop
+	.global oc123
+oc123:
+	nop
+
+	.data
+	.long 0
+	.global file1data1
+file1data1:
+	.long 0
+	.long datalabel file1data1 + 8
+	.global file1data2
+file1data2:
+	.long file1text2
+	.global file1data3
+file1data3:
+	.long file2data3
+	.global file1data4
+file1data4:
+	.long file2text4
+	.global file1data5
+file1data5:
+	.long unresolved2
+	.long unresolved5
+	.long datalabel unresolved6 + 40
+	.long unresolved9
+
+	.long datalabel a1
+	.long a23
+	.long b123
+	.long c3
+	.long c13
+	.long datalabel a2
+	.long datalabel a3
+	.long datalabel a4
+	.long datalabel a12
+	.long datalabel a13
+	.long datalabel a23
+	.long datalabel a123
+	.long datalabel b1
+	.long datalabel b2
+	.long a3
+	.long a13
+	.long datalabel b3
+	.long datalabel b4
+	.long datalabel b12
+	.long datalabel b13
+	.long a123
+	.long b3
+	.long b13
+	.long b23
+	.long datalabel b23
+	.long datalabel b123
+	.long datalabel c1
+	.long datalabel c2
+	.long datalabel c3
+	.long c23
+	.long c123
+	.long datalabel c4
+	.long datalabel c12
+	.long datalabel c13
+	.long datalabel c23
+	.long datalabel c123
+
+
+	.long datalabel oa1
+	.long datalabel ob1
+	.long ob123
+	.long datalabel oc1
+	.long oa2
+	.long ob2
+	.long oc2
+	.long oa12
+	.long datalabel oa12
+	.long datalabel ob12
+	.long ob12
+	.long datalabel oc12
+	.long oc12
+	.long oa23
+	.long datalabel oa13
+	.long oc123
+	.long datalabel ob13
+	.long datalabel oc13
+	.long ob23
+	.long oc23
+	.long oa123
+	.long datalabel oa123
+	.long datalabel ob123
+	.long datalabel oc123
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/reldl-2.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/reldl-2.s
new file mode 100644
index 0000000..d632021
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/reldl-2.s
@@ -0,0 +1,156 @@
+! Relative linking with datalabel use, second file.  Much like rel-2.s
+
+	.mode SHmedia
+	.text
+	.global start2
+start2:
+	nop
+	.global file2text1
+file2text1:
+	nop
+	movi file2text1 & 65535,r10
+	.global file2text2
+file2text2:
+	movi file2data2 & 65535,r20
+	.global file2text3
+file2text3:
+	movi file1text3 & 65535,r20
+	.global file2text4
+file2text4:
+	movi file1data4 & 65535,r20
+	movi unresolved1 & 65535,r30
+	movi unresolved3 & 65535,r30
+	movi datalabel unresolved8 & 65535,r50
+	movi datalabel unresolved9 & 65535,r50
+	movi datalabel file1text1 & 65535,r40
+	movi datalabel file1data2 & 65535,r40
+	movi datalabel file1data3 & 65535,r40
+	.global c1
+c1:
+	nop
+	.global c2
+c2:
+	nop
+	.global c3
+c3:
+	nop
+	.global c4
+c4:
+	nop
+	.global c12
+c12:
+	nop
+	.global c13
+c13:
+	nop
+	.global c23
+c23:
+	nop
+	.global c123
+c123:
+	nop
+
+	.global ob1
+ob1:
+	nop
+	.global ob2
+ob2:
+	nop
+	.global ob3
+ob3:
+	nop
+	.global ob4
+ob4:
+	nop
+	.global ob12
+ob12:
+	nop
+	.global ob13
+ob13:
+	nop
+	.global ob23
+ob23:
+	nop
+	.global ob123
+ob123:
+	nop
+
+	.data
+	.long 0
+	.global file2data1
+file2data1:
+	.long 0
+	.long file2data1
+	.global file2data2
+file2data2:
+	.long file2text2
+	.global file2data3
+file2data3:
+	.long file1data3
+	.global file2data4
+file2data4:
+	.long file1text4
+	.long unresolved2
+	.long unresolved4
+
+	.long datalabel oa1
+	.long datalabel oa2
+	.long datalabel oa3
+	.long oa13
+	.long oc13
+	.long datalabel oa4
+	.long datalabel oa12
+	.long datalabel oa13
+	.long datalabel oa23
+	.long oa23
+	.long oa123
+	.long oc3
+	.long datalabel oa123
+	.long datalabel ob1
+	.long datalabel ob2
+	.long datalabel ob3
+	.long datalabel ob4
+	.long oa3
+	.long oc23
+	.long oc123
+	.long datalabel ob12
+	.long datalabel ob13
+	.long ob13
+	.long ob23
+	.long datalabel ob23
+	.long datalabel ob123
+	.long datalabel oc1
+	.long ob3
+	.long ob123
+	.long datalabel oc2
+	.long datalabel oc3
+	.long datalabel oc4
+	.long datalabel oc12
+	.long datalabel oc13
+	.long datalabel oc23
+	.long datalabel oc123
+
+	.long datalabel a1
+	.long c2
+	.long b23
+	.long datalabel b1
+	.long datalabel c1
+	.long datalabel a12
+	.long a2
+	.long b2
+	.long datalabel b12
+	.long datalabel c12
+	.long b123
+	.long c123
+	.long datalabel a13
+	.long datalabel b13
+	.long c23
+	.long a123
+	.long datalabel c13
+	.long datalabel a123
+	.long c12
+	.long a23
+	.long datalabel b123
+	.long a12
+	.long b12
+	.long datalabel c123
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/reldl32.rd b/binutils-2.19/ld/testsuite/ld-sh/sh64/reldl32.rd
new file mode 100644
index 0000000..98bbbed
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/reldl32.rd
@@ -0,0 +1,358 @@
+
+Relocation section '\.rela\.text' at offset 0x[0-9a-f]+ contains 26 entries:
+.*
+00000008  0+5bf6 R_SH_IMM_LOW16 +00000004 +file1text1 +\+ 0
+0000000c  0+2df6 R_SH_IMM_LOW16 +0000000c +file1data2 +\+ 0
+00000010  0+30f6 R_SH_IMM_LOW16 +00000070 +file2text3 +\+ 0
+00000014  0+0ff6 R_SH_IMM_LOW16 +0000012c +file2data4 +\+ 0
+00000018  0+4cf6 R_SH_IMM_LOW16 +00000000 +unresolved1 +\+ 0
+0000001c  0+51f6 R_SH_IMM_LOW16 +00000000 +unresolved6 +\+ 0
+00000020  0+5df6 R_SH_IMM_LOW16 +00000000 +file1text1 +\+ 0
+00000024  0+5df6 R_SH_IMM_LOW16 +00000000 +file1text1 +\+ 18
+00000028  0+21f6 R_SH_IMM_LOW16 +00000000 +file1text5 +\+ 8
+0000002c  0+2df6 R_SH_IMM_LOW16 +0000000c +file1data2 +\+ 30
+00000030  0+2df6 R_SH_IMM_LOW16 +0000000c +file1data2 +\+ 0
+0000003c  0+42f6 R_SH_IMM_LOW16 +00000000 +unresolved7 +\+ 0
+00000040  0+27f6 R_SH_IMM_LOW16 +00000000 +unresolved1 +\+ 0
+00000034  0+35f8 R_SH_IMM_MEDLOW16 +00000000 +file2data4 +\+ 10
+00000038  0+35f6 R_SH_IMM_LOW16 +00000000 +file2data4 +\+ 10
+00000068  0+08f6 R_SH_IMM_LOW16 +00000064 +file2text1 +\+ 0
+0000006c  0+24f6 R_SH_IMM_LOW16 +00000124 +file2data2 +\+ 0
+00000070  0+23f6 R_SH_IMM_LOW16 +00000010 +file1text3 +\+ 0
+00000074  0+81f6 R_SH_IMM_LOW16 +00000014 +file1data4 +\+ 0
+00000078  0+4cf6 R_SH_IMM_LOW16 +00000000 +unresolved1 +\+ 0
+0000007c  0+64f6 R_SH_IMM_LOW16 +00000000 +unresolved3 +\+ 0
+00000080  0+85f6 R_SH_IMM_LOW16 +00000000 +unresolved8 +\+ 0
+00000084  0+32f6 R_SH_IMM_LOW16 +00000000 +unresolved9 +\+ 0
+00000088  0+5df6 R_SH_IMM_LOW16 +00000000 +file1text1 +\+ 0
+0000008c  0+4bf6 R_SH_IMM_LOW16 +00000000 +file1data2 +\+ 0
+00000090  0+28f6 R_SH_IMM_LOW16 +00000000 +file1data3 +\+ 0
+
+Relocation section '\.rela\.data' at offset 0x[0-9a-f]+ contains 134 entries:
+.*
+00000008  0+0b01 R_SH_DIR32 +00000004 +file1data1 +\+ 0
+0000000c  0+0701 R_SH_DIR32 +0000000c +file1text2 +\+ 0
+00000010  0+7801 R_SH_DIR32 +00000128 +file2data3 +\+ 0
+00000014  0+6701 R_SH_DIR32 +00000074 +file2text4 +\+ 0
+00000018  0+7401 R_SH_DIR32 +00000000 +unresolved2 +\+ 0
+0000001c  0+0501 R_SH_DIR32 +00000000 +unresolved5 +\+ 0
+00000020  0+6c01 R_SH_DIR32 +00000000 +unresolved6 +\+ 0
+00000024  0+0601 R_SH_DIR32 +00000000 +unresolved9 +\+ 0
+00000028  0+7a01 R_SH_DIR32 +00000000 +a1 +\+ 0
+0000002c  0+7001 R_SH_DIR32 +00000000 +a23 +\+ 0
+00000030  0+5401 R_SH_DIR32 +0000003c +b123 +\+ 0
+00000034  0+6a01 R_SH_DIR32 +0000009c +c3 +\+ 0
+00000038  0+3c01 R_SH_DIR32 +000000a8 +c13 +\+ 0
+0000003c  0+2601 R_SH_DIR32 +00000000 +a2 +\+ 0
+00000040  0+4e01 R_SH_DIR32 +00000000 +a3 +\+ 0
+00000044  0+2501 R_SH_DIR32 +00000000 +a4 +\+ 0
+00000048  0+6901 R_SH_DIR32 +00000000 +a12 +\+ 0
+0000004c  0+1501 R_SH_DIR32 +00000000 +a13 +\+ 0
+00000050  0+7601 R_SH_DIR32 +00000000 +a23 +\+ 0
+00000054  0+6201 R_SH_DIR32 +00000000 +a123 +\+ 0
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+000000e0  0+4a01 R_SH_DIR32 +000000c4 +ob12 +\+ 0
+000000e4  0+5a01 R_SH_DIR32 +00000000 +oc12 +\+ 0
+000000e8  0+1201 R_SH_DIR32 +00000050 +oc12 +\+ 0
+000000ec  0+3f01 R_SH_DIR32 +00000000 +oa23 +\+ 0
+000000f0  0+4501 R_SH_DIR32 +00000000 +oa13 +\+ 0
+000000f4  0+0a01 R_SH_DIR32 +0000005c +oc123 +\+ 0
+000000f8  0+5501 R_SH_DIR32 +00000000 +ob13 +\+ 0
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+0000010c  0+5001 R_SH_DIR32 +00000000 +oa123 +\+ 0
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+00000114  0+3301 R_SH_DIR32 +00000000 +oc123 +\+ 0
+00000120  0+7c01 R_SH_DIR32 +0000011c +file2data1 +\+ 0
+00000124  0+5e01 R_SH_DIR32 +0000006c +file2text2 +\+ 0
+00000128  0+8001 R_SH_DIR32 +00000010 +file1data3 +\+ 0
+0000012c  0+7701 R_SH_DIR32 +00000014 +file1text4 +\+ 0
+00000130  0+7401 R_SH_DIR32 +00000000 +unresolved2 +\+ 0
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+00000160  0+5701 R_SH_DIR32 +00000000 +oa123 +\+ 0
+00000164  0+1601 R_SH_DIR32 +00000048 +oc3 +\+ 0
+00000168  0+5001 R_SH_DIR32 +00000000 +oa123 +\+ 0
+0000016c  0+1401 R_SH_DIR32 +00000000 +ob1 +\+ 0
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+00000198  0+5801 R_SH_DIR32 +00000000 +ob23 +\+ 0
+0000019c  0+6601 R_SH_DIR32 +00000000 +ob123 +\+ 0
+000001a0  0+5901 R_SH_DIR32 +00000000 +oc1 +\+ 0
+000001a4  0+1101 R_SH_DIR32 +000000bc +ob3 +\+ 0
+000001a8  0+4401 R_SH_DIR32 +000000d0 +ob123 +\+ 0
+000001ac  0+0901 R_SH_DIR32 +00000000 +oc2 +\+ 0
+000001b0  0+3701 R_SH_DIR32 +00000000 +oc3 +\+ 0
+000001b4  0+5301 R_SH_DIR32 +00000000 +oc4 +\+ 0
+000001b8  0+5a01 R_SH_DIR32 +00000000 +oc12 +\+ 0
+000001bc  0+5c01 R_SH_DIR32 +00000000 +oc13 +\+ 0
+000001c0  0+2a01 R_SH_DIR32 +00000000 +oc23 +\+ 0
+000001c4  0+3301 R_SH_DIR32 +00000000 +oc123 +\+ 0
+000001c8  0+7a01 R_SH_DIR32 +00000000 +a1 +\+ 0
+000001cc  0+1a01 R_SH_DIR32 +00000098 +c2 +\+ 0
+000001d0  0+6f01 R_SH_DIR32 +00000034 +b23 +\+ 0
+000001d4  0+3d01 R_SH_DIR32 +00000000 +b1 +\+ 0
+000001d8  0+8301 R_SH_DIR32 +00000000 +c1 +\+ 0
+000001dc  0+6901 R_SH_DIR32 +00000000 +a12 +\+ 0
+000001e0  0+5601 R_SH_DIR32 +00000000 +a2 +\+ 0
+000001e4  0+0d01 R_SH_DIR32 +00000020 +b2 +\+ 0
+000001e8  0+5201 R_SH_DIR32 +00000000 +b12 +\+ 0
+000001ec  0+2001 R_SH_DIR32 +00000000 +c12 +\+ 0
+000001f0  0+5401 R_SH_DIR32 +0000003c +b123 +\+ 0
+000001f4  0+7e01 R_SH_DIR32 +000000b0 +c123 +\+ 0
+000001f8  0+1501 R_SH_DIR32 +00000000 +a13 +\+ 0
+000001fc  0+2901 R_SH_DIR32 +00000000 +b13 +\+ 0
+00000200  0+3901 R_SH_DIR32 +000000ac +c23 +\+ 0
+00000204  0+3e01 R_SH_DIR32 +00000000 +a123 +\+ 0
+00000208  0+3101 R_SH_DIR32 +00000000 +c13 +\+ 0
+0000020c  0+6201 R_SH_DIR32 +00000000 +a123 +\+ 0
+00000210  0+6e01 R_SH_DIR32 +000000a4 +c12 +\+ 0
+00000214  0+7001 R_SH_DIR32 +00000000 +a23 +\+ 0
+00000218  0+0c01 R_SH_DIR32 +00000000 +b123 +\+ 0
+0000021c  0+4001 R_SH_DIR32 +00000000 +a12 +\+ 0
+00000220  0+7301 R_SH_DIR32 +0000002c +b12 +\+ 0
+00000224  0+3a01 R_SH_DIR32 +00000000 +c123 +\+ 0
+
+Symbol table '\.symtab' contains 134 entries:
+   Num:    Value  Size Type    Bind   Vis      Ndx Name
+     0: 00000000     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 00000000     0 SECTION LOCAL  DEFAULT    1 
+     2: 00000000     0 SECTION LOCAL  DEFAULT    3 
+     3: 00000000     0 SECTION LOCAL  DEFAULT    5 
+     4: 00000000     0 SECTION LOCAL  DEFAULT    6 
+     5: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND unresolved5
+     6: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND unresolved9
+     7: 0000000c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file1text2
+     8: 00000064     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file2text1
+     9: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc2
+    10: 0000005c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc123
+    11: 00000004     0 NOTYPE  GLOBAL DEFAULT    3 file1data1
+    12: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b123
+    13: 00000020     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b2
+    14: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c4
+    15: 0000012c     0 NOTYPE  GLOBAL DEFAULT    3 file2data4
+    16: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa4
+    17: 000000bc     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 ob3
+    18: 00000050     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc12
+    19: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob4
+    20: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob1
+    21: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a13
+    22: 00000048     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc3
+    23: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa2
+    24: 000000a0     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c4
+    25: 00000054     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc13
+    26: 00000098     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c2
+    27: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa12
+    28: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND oa13
+    29: 000000c0     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 ob4
+    30: 0000001c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b1
+    31: 00000018     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file1text5
+    32: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c12
+    33: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND file1text5
+    34: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob2
+    35: 00000010     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file1text3
+    36: 00000124     0 NOTYPE  GLOBAL DEFAULT    3 file2data2
+    37: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a4
+    38: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a2
+    39: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND unresolved1
+    40: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND file1data3
+    41: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b13
+    42: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc23
+    43: 00000058     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc23
+    44: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c2
+    45: 0000000c     0 NOTYPE  GLOBAL DEFAULT    3 file1data2
+    46: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b3
+    47: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND a3
+    48: 00000070     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file2text3
+    49: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c13
+    50: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND unresolved9
+    51: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc123
+    52: 00000028     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b4
+    53: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND file2data4
+    54: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c23
+    55: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc3
+    56: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa23
+    57: 000000ac     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c23
+    58: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c123
+    59: 00000030     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b13
+    60: 000000a8     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c13
+    61: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b1
+    62: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND a123
+    63: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND oa23
+    64: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND a12
+    65: 000000b4     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 ob1
+    66: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND unresolved7
+    67: 00000060     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 start2
+    68: 000000d0     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 ob123
+    69: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa13
+    70: 00000094     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c1
+    71: 0000004c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc4
+    72: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa1
+    73: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND oa12
+    74: 000000c4     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 ob12
+    75: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND file1data2
+    76: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND unresolved1
+    77: 000000c8     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 ob13
+    78: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a3
+    79: 00000018     0 NOTYPE  GLOBAL DEFAULT    3 file1data5
+    80: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa123
+    81: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND unresolved6
+    82: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b12
+    83: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc4
+    84: 0000003c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b123
+    85: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob13
+    86: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND a2
+    87: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND oa123
+    88: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob23
+    89: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc1
+    90: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc12
+    91: 00000004     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file1text1
+    92: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc13
+    93: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND file1text1
+    94: 0000006c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file2text2
+    95: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob3
+    96: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob12
+    97: 000000b8     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 ob2
+    98: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a123
+    99: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c3
+   100: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND unresolved3
+   101: 00000024     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b3
+   102: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob123
+   103: 00000074     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file2text4
+   104: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b4
+   105: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a12
+   106: 0000009c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c3
+   107: 00000040     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc1
+   108: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND unresolved6
+   109: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa3
+   110: 000000a4     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c12
+   111: 00000034     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b23
+   112: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND a23
+   113: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b2
+   114: 00000044     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc2
+   115: 0000002c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b12
+   116: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND unresolved2
+   117: 00000000     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 start
+   118: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a23
+   119: 00000014     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file1text4
+   120: 00000128     0 NOTYPE  GLOBAL DEFAULT    3 file2data3
+   121: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND oa2
+   122: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a1
+   123: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND unresolved4
+   124: 0000011c     0 NOTYPE  GLOBAL DEFAULT    3 file2data1
+   125: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b23
+   126: 000000b0     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c123
+   127: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND a13
+   128: 00000010     0 NOTYPE  GLOBAL DEFAULT    3 file1data3
+   129: 00000014     0 NOTYPE  GLOBAL DEFAULT    3 file1data4
+   130: 000000cc     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 ob23
+   131: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c1
+   132: 00000000     0 NOTYPE  GLOBAL DEFAULT  UND oa3
+   133: 00000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND unresolved8
+
+Hex dump of section '\.text':
+.*
+  0x00000000 6ff0fff0 6ff0fff0 cc0000a0 cc000140 .*
+  0x00000010 cc000140 cc000140 cc000280 cc0001e0 .*
+  0x00000020 cc0000a0 cc0000a0 cc000280 cc000140 .*
+  0x00000030 cc000140 cc000320 c8000320 cc0003c0 .*
+  0x00000040 cc0003c0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00000050 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00000060 6ff0fff0 6ff0fff0 cc0000a0 cc000140 .*
+  0x00000070 cc000140 cc000140 cc0001e0 cc0001e0 .*
+  0x00000080 cc000320 cc000320 cc000280 cc000280 .*
+  0x00000090 cc000280 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x000000a0 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x000000b0 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x000000c0 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x000000d0 6ff0fff0                            .*
+
+Hex dump of section '\.data':
+.*
+  0x00000000 00000000 00000000 00000008 00000000 .*
+  0x00000010 00000000 00000000 00000000 00000000 .*
+  0x00000020 00000028 00000000 00000000 00000000 .*
+  0x00000030 00000000 00000000 00000000 00000000 .*
+  0x00000040 00000000 00000000 00000000 00000000 .*
+  0x00000050 00000000 00000000 00000000 00000000 .*
+  0x00000060 00000000 00000000 00000000 00000000 .*
+  0x00000070 00000000 00000000 00000000 00000000 .*
+  0x00000080 00000000 00000000 00000000 00000000 .*
+  0x00000090 00000000 00000000 00000000 00000000 .*
+  0x000000a0 00000000 00000000 00000000 00000000 .*
+  0x000000b0 00000000 00000000 00000000 00000000 .*
+  0x000000c0 00000000 00000000 00000000 00000000 .*
+  0x000000d0 00000000 00000000 00000000 00000000 .*
+  0x000000e0 00000000 00000000 00000000 00000000 .*
+  0x000000f0 00000000 00000000 00000000 00000000 .*
+  0x00000100 00000000 00000000 00000000 00000000 .*
+  0x00000110 00000000 00000000 00000000 00000000 .*
+  0x00000120 00000000 00000000 00000000 00000000 .*
+  0x00000130 00000000 00000000 00000000 00000000 .*
+  0x00000140 00000000 00000000 00000000 00000000 .*
+  0x00000150 00000000 00000000 00000000 00000000 .*
+  0x00000160 00000000 00000000 00000000 00000000 .*
+  0x00000170 00000000 00000000 00000000 00000000 .*
+  0x00000180 00000000 00000000 00000000 00000000 .*
+  0x00000190 00000000 00000000 00000000 00000000 .*
+  0x000001a0 00000000 00000000 00000000 00000000 .*
+  0x000001b0 00000000 00000000 00000000 00000000 .*
+  0x000001c0 00000000 00000000 00000000 00000000 .*
+  0x000001d0 00000000 00000000 00000000 00000000 .*
+  0x000001e0 00000000 00000000 00000000 00000000 .*
+  0x000001f0 00000000 00000000 00000000 00000000 .*
+  0x00000200 00000000 00000000 00000000 00000000 .*
+  0x00000210 00000000 00000000 00000000 00000000 .*
+  0x00000220 00000000 00000000                   .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/reldl64.rd b/binutils-2.19/ld/testsuite/ld-sh/sh64/reldl64.rd
new file mode 100644
index 0000000..a34537b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/reldl64.rd
@@ -0,0 +1,360 @@
+
+Relocation section '\.rela\.text' at offset 0x[0-9a-f]+ contains 28 entries:
+.*
+0+8  0+5b000000f6 R_SH_IMM_LOW16[ ]+0+4 +file1text1[ ]+\+ 0
+0+c  0+2d000000f6 R_SH_IMM_LOW16[ ]+0+c +file1data2[ ]+\+ 0
+0+10  0+30000000f6 R_SH_IMM_LOW16[ ]+0+78 +file2text3[ ]+\+ 0
+0+14  0+0f000000f6 R_SH_IMM_LOW16[ ]+0+12c +file2data4[ ]+\+ 0
+0+18  0+4c000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved1[ ]+\+ 0
+0+1c  0+51000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved6[ ]+\+ 0
+0+20  0+5d000000f6 R_SH_IMM_LOW16[ ]+0+ +file1text1[ ]+\+ 0
+0+24  0+5d000000f6 R_SH_IMM_LOW16[ ]+0+ +file1text1[ ]+\+ 18
+0+28  0+21000000f6 R_SH_IMM_LOW16[ ]+0+ +file1text5[ ]+\+ 8
+0+2c  0+2d000000f6 R_SH_IMM_LOW16[ ]+0+c +file1data2[ ]+\+ 30
+0+30  0+2d000000f6 R_SH_IMM_LOW16[ ]+0+c +file1data2[ ]+\+ 0
+0+44  0+42000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved7[ ]+\+ 0
+0+48  0+27000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved1[ ]+\+ 0
+0+34  0+35000000fc R_SH_IMM_HI16[ ]+0+ +file2data4[ ]+\+ 10
+0+38  0+35000000fa R_SH_IMM_MEDHI16[ ]+0+ +file2data4[ ]+\+ 10
+0+3c  0+35000000f8 R_SH_IMM_MEDLOW16[ ]+0+ +file2data4[ ]+\+ 10
+0+40  0+35000000f6 R_SH_IMM_LOW16[ ]+0+ +file2data4[ ]+\+ 10
+0+70  0+08000000f6 R_SH_IMM_LOW16[ ]+0+6c +file2text1[ ]+\+ 0
+0+74  0+24000000f6 R_SH_IMM_LOW16[ ]+0+124 +file2data2[ ]+\+ 0
+0+78  0+23000000f6 R_SH_IMM_LOW16[ ]+0+10 +file1text3[ ]+\+ 0
+0+7c  0+81000000f6 R_SH_IMM_LOW16[ ]+0+14 +file1data4[ ]+\+ 0
+0+80  0+4c000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved1[ ]+\+ 0
+0+84  0+64000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved3[ ]+\+ 0
+0+88  0+85000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved8[ ]+\+ 0
+0+8c  0+32000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved9[ ]+\+ 0
+0+90  0+5d000000f6 R_SH_IMM_LOW16[ ]+0+ +file1text1[ ]+\+ 0
+0+94  0+4b000000f6 R_SH_IMM_LOW16[ ]+0+ +file1data2[ ]+\+ 0
+0+98  0+28000000f6 R_SH_IMM_LOW16[ ]+0+ +file1data3[ ]+\+ 0
+
+Relocation section '\.rela\.data' at offset 0x[0-9a-f]+ contains 134 entries:
+.*
+0+8  0+0b00000001 R_SH_DIR32[ ]+0+4 +file1data1[ ]+\+ 0
+0+c  0+700000001 R_SH_DIR32[ ]+0+c +file1text2[ ]+\+ 0
+0+10  0+7800000001 R_SH_DIR32[ ]+0+128 +file2data3[ ]+\+ 0
+0+14  0+6700000001 R_SH_DIR32[ ]+0+7c +file2text4[ ]+\+ 0
+0+18  0+7400000001 R_SH_DIR32[ ]+0+ +unresolved2[ ]+\+ 0
+0+1c  0+0500000001 R_SH_DIR32[ ]+0+ +unresolved5[ ]+\+ 0
+0+20  0+6c00000001 R_SH_DIR32[ ]+0+ +unresolved6[ ]+\+ 0
+0+24  0+0600000001 R_SH_DIR32[ ]+0+ +unresolved9[ ]+\+ 0
+0+28  0+7a00000001 R_SH_DIR32[ ]+0+ +a1[ ]+\+ 0
+0+2c  0+7000000001 R_SH_DIR32[ ]+0+ +a23[ ]+\+ 0
+0+30  0+5400000001 R_SH_DIR32[ ]+0+44 +b123[ ]+\+ 0
+0+34  0+6a00000001 R_SH_DIR32[ ]+0+a4 +c3[ ]+\+ 0
+0+38  0+3c00000001 R_SH_DIR32[ ]+0+b0 +c13[ ]+\+ 0
+0+3c  0+2600000001 R_SH_DIR32[ ]+0+ +a2[ ]+\+ 0
+0+40  0+4e00000001 R_SH_DIR32[ ]+0+ +a3[ ]+\+ 0
+0+44  0+2500000001 R_SH_DIR32[ ]+0+ +a4[ ]+\+ 0
+0+48  0+6900000001 R_SH_DIR32[ ]+0+ +a12[ ]+\+ 0
+0+4c  0+1500000001 R_SH_DIR32[ ]+0+ +a13[ ]+\+ 0
+0+50  0+7600000001 R_SH_DIR32[ ]+0+ +a23[ ]+\+ 0
+0+54  0+6200000001 R_SH_DIR32[ ]+0+ +a123[ ]+\+ 0
+0+58  0+3d00000001 R_SH_DIR32[ ]+0+ +b1[ ]+\+ 0
+0+5c  0+7100000001 R_SH_DIR32[ ]+0+ +b2[ ]+\+ 0
+0+60  0+2f00000001 R_SH_DIR32[ ]+0+ +a3[ ]+\+ 0
+0+64  0+7f00000001 R_SH_DIR32[ ]+0+ +a13[ ]+\+ 0
+0+68  0+2e00000001 R_SH_DIR32[ ]+0+ +b3[ ]+\+ 0
+0+6c  0+6800000001 R_SH_DIR32[ ]+0+ +b4[ ]+\+ 0
+0+70  0+5200000001 R_SH_DIR32[ ]+0+ +b12[ ]+\+ 0
+0+74  0+2900000001 R_SH_DIR32[ ]+0+ +b13[ ]+\+ 0
+0+78  0+3e00000001 R_SH_DIR32[ ]+0+ +a123[ ]+\+ 0
+0+7c  0+6500000001 R_SH_DIR32[ ]+0+24 +b3[ ]+\+ 0
+0+80  0+3b00000001 R_SH_DIR32[ ]+0+30 +b13[ ]+\+ 0
+0+84  0+6f00000001 R_SH_DIR32[ ]+0+34 +b23[ ]+\+ 0
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+0+8c  0+0c00000001 R_SH_DIR32[ ]+0+ +b123[ ]+\+ 0
+0+90  0+8300000001 R_SH_DIR32[ ]+0+ +c1[ ]+\+ 0
+0+94  0+2c00000001 R_SH_DIR32[ ]+0+ +c2[ ]+\+ 0
+0+98  0+6300000001 R_SH_DIR32[ ]+0+ +c3[ ]+\+ 0
+0+9c  0+3900000001 R_SH_DIR32[ ]+0+b4 +c23[ ]+\+ 0
+0+a0  0+7e00000001 R_SH_DIR32[ ]+0+b8 +c123[ ]+\+ 0
+0+a4  0+0e00000001 R_SH_DIR32[ ]+0+ +c4[ ]+\+ 0
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+0+ac  0+3100000001 R_SH_DIR32[ ]+0+ +c13[ ]+\+ 0
+0+b0  0+3600000001 R_SH_DIR32[ ]+0+ +c23[ ]+\+ 0
+0+b4  0+3a00000001 R_SH_DIR32[ ]+0+ +c123[ ]+\+ 0
+0+b8  0+4800000001 R_SH_DIR32[ ]+0+ +oa1[ ]+\+ 0
+0+bc  0+1400000001 R_SH_DIR32[ ]+0+ +ob1[ ]+\+ 0
+0+c0  0+4400000001 R_SH_DIR32[ ]+0+d8 +ob123[ ]+\+ 0
+0+c4  0+5900000001 R_SH_DIR32[ ]+0+ +oc1[ ]+\+ 0
+0+c8  0+7900000001 R_SH_DIR32[ ]+0+ +oa2[ ]+\+ 0
+0+cc  0+6100000001 R_SH_DIR32[ ]+0+c0 +ob2[ ]+\+ 0
+0+d0  0+7200000001 R_SH_DIR32[ ]+0+4c +oc2[ ]+\+ 0
+0+d4  0+4900000001 R_SH_DIR32[ ]+0+ +oa12[ ]+\+ 0
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+0+dc  0+6000000001 R_SH_DIR32[ ]+0+ +ob12[ ]+\+ 0
+0+e0  0+4a00000001 R_SH_DIR32[ ]+0+cc +ob12[ ]+\+ 0
+0+e4  0+5a00000001 R_SH_DIR32[ ]+0+ +oc12[ ]+\+ 0
+0+e8  0+1200000001 R_SH_DIR32[ ]+0+58 +oc12[ ]+\+ 0
+0+ec  0+3f00000001 R_SH_DIR32[ ]+0+ +oa23[ ]+\+ 0
+0+f0  0+4500000001 R_SH_DIR32[ ]+0+ +oa13[ ]+\+ 0
+0+f4  0+0a00000001 R_SH_DIR32[ ]+0+64 +oc123[ ]+\+ 0
+0+f8  0+5500000001 R_SH_DIR32[ ]+0+ +ob13[ ]+\+ 0
+0+fc  0+5c00000001 R_SH_DIR32[ ]+0+ +oc13[ ]+\+ 0
+0+100  0+8200000001 R_SH_DIR32[ ]+0+d4 +ob23[ ]+\+ 0
+0+104  0+2b00000001 R_SH_DIR32[ ]+0+60 +oc23[ ]+\+ 0
+0+108  0+5700000001 R_SH_DIR32[ ]+0+ +oa123[ ]+\+ 0
+0+10c  0+5000000001 R_SH_DIR32[ ]+0+ +oa123[ ]+\+ 0
+0+110  0+6600000001 R_SH_DIR32[ ]+0+ +ob123[ ]+\+ 0
+0+114  0+3300000001 R_SH_DIR32[ ]+0+ +oc123[ ]+\+ 0
+0+120  0+7c00000001 R_SH_DIR32[ ]+0+11c +file2data1[ ]+\+ 0
+0+124  0+5e00000001 R_SH_DIR32[ ]+0+74 +file2text2[ ]+\+ 0
+0+128  0+8000000001 R_SH_DIR32[ ]+0+10 +file1data3[ ]+\+ 0
+0+12c  0+7700000001 R_SH_DIR32[ ]+0+14 +file1text4[ ]+\+ 0
+0+130  0+7400000001 R_SH_DIR32[ ]+0+ +unresolved2[ ]+\+ 0
+0+134  0+7b00000001 R_SH_DIR32[ ]+0+ +unresolved4[ ]+\+ 0
+0+138  0+4800000001 R_SH_DIR32[ ]+0+ +oa1[ ]+\+ 0
+0+13c  0+1700000001 R_SH_DIR32[ ]+0+ +oa2[ ]+\+ 0
+0+140  0+6d00000001 R_SH_DIR32[ ]+0+ +oa3[ ]+\+ 0
+0+144  0+1c00000001 R_SH_DIR32[ ]+0+ +oa13[ ]+\+ 0
+0+148  0+1900000001 R_SH_DIR32[ ]+0+5c +oc13[ ]+\+ 0
+0+14c  0+1000000001 R_SH_DIR32[ ]+0+ +oa4[ ]+\+ 0
+0+150  0+1b00000001 R_SH_DIR32[ ]+0+ +oa12[ ]+\+ 0
+0+154  0+4500000001 R_SH_DIR32[ ]+0+ +oa13[ ]+\+ 0
+0+158  0+3800000001 R_SH_DIR32[ ]+0+ +oa23[ ]+\+ 0
+0+15c  0+3f00000001 R_SH_DIR32[ ]+0+ +oa23[ ]+\+ 0
+0+160  0+5700000001 R_SH_DIR32[ ]+0+ +oa123[ ]+\+ 0
+0+164  0+1600000001 R_SH_DIR32[ ]+0+50 +oc3[ ]+\+ 0
+0+168  0+5000000001 R_SH_DIR32[ ]+0+ +oa123[ ]+\+ 0
+0+16c  0+1400000001 R_SH_DIR32[ ]+0+ +ob1[ ]+\+ 0
+0+170  0+2200000001 R_SH_DIR32[ ]+0+ +ob2[ ]+\+ 0
+0+174  0+5f00000001 R_SH_DIR32[ ]+0+ +ob3[ ]+\+ 0
+0+178  0+1300000001 R_SH_DIR32[ ]+0+ +ob4[ ]+\+ 0
+0+17c  0+8400000001 R_SH_DIR32[ ]+0+ +oa3[ ]+\+ 0
+0+180  0+2b00000001 R_SH_DIR32[ ]+0+60 +oc23[ ]+\+ 0
+0+184  0+0a00000001 R_SH_DIR32[ ]+0+64 +oc123[ ]+\+ 0
+0+188  0+6000000001 R_SH_DIR32[ ]+0+ +ob12[ ]+\+ 0
+0+18c  0+5500000001 R_SH_DIR32[ ]+0+ +ob13[ ]+\+ 0
+0+190  0+4d00000001 R_SH_DIR32[ ]+0+d0 +ob13[ ]+\+ 0
+0+194  0+8200000001 R_SH_DIR32[ ]+0+d4 +ob23[ ]+\+ 0
+0+198  0+5800000001 R_SH_DIR32[ ]+0+ +ob23[ ]+\+ 0
+0+19c  0+6600000001 R_SH_DIR32[ ]+0+ +ob123[ ]+\+ 0
+0+1a0  0+5900000001 R_SH_DIR32[ ]+0+ +oc1[ ]+\+ 0
+0+1a4  0+1100000001 R_SH_DIR32[ ]+0+c4 +ob3[ ]+\+ 0
+0+1a8  0+4400000001 R_SH_DIR32[ ]+0+d8 +ob123[ ]+\+ 0
+0+1ac  0+0900000001 R_SH_DIR32[ ]+0+ +oc2[ ]+\+ 0
+0+1b0  0+3700000001 R_SH_DIR32[ ]+0+ +oc3[ ]+\+ 0
+0+1b4  0+5300000001 R_SH_DIR32[ ]+0+ +oc4[ ]+\+ 0
+0+1b8  0+5a00000001 R_SH_DIR32[ ]+0+ +oc12[ ]+\+ 0
+0+1bc  0+5c00000001 R_SH_DIR32[ ]+0+ +oc13[ ]+\+ 0
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+0+1c8  0+7a00000001 R_SH_DIR32[ ]+0+ +a1[ ]+\+ 0
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+0+1d0  0+6f00000001 R_SH_DIR32[ ]+0+34 +b23[ ]+\+ 0
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+0+1e8  0+5200000001 R_SH_DIR32[ ]+0+ +b12[ ]+\+ 0
+0+1ec  0+2000000001 R_SH_DIR32[ ]+0+ +c12[ ]+\+ 0
+0+1f0  0+5400000001 R_SH_DIR32[ ]+0+44 +b123[ ]+\+ 0
+0+1f4  0+7e00000001 R_SH_DIR32[ ]+0+b8 +c123[ ]+\+ 0
+0+1f8  0+1500000001 R_SH_DIR32[ ]+0+ +a13[ ]+\+ 0
+0+1fc  0+2900000001 R_SH_DIR32[ ]+0+ +b13[ ]+\+ 0
+0+200  0+3900000001 R_SH_DIR32[ ]+0+b4 +c23[ ]+\+ 0
+0+204  0+3e00000001 R_SH_DIR32[ ]+0+ +a123[ ]+\+ 0
+0+208  0+3100000001 R_SH_DIR32[ ]+0+ +c13[ ]+\+ 0
+0+20c  0+6200000001 R_SH_DIR32[ ]+0+ +a123[ ]+\+ 0
+0+210  0+6e00000001 R_SH_DIR32[ ]+0+ac +c12[ ]+\+ 0
+0+214  0+7000000001 R_SH_DIR32[ ]+0+ +a23[ ]+\+ 0
+0+218  0+0c00000001 R_SH_DIR32[ ]+0+ +b123[ ]+\+ 0
+0+21c  0+4000000001 R_SH_DIR32[ ]+0+ +a12[ ]+\+ 0
+0+220  0+7300000001 R_SH_DIR32[ ]+0+2c +b12[ ]+\+ 0
+0+224  0+3a00000001 R_SH_DIR32[ ]+0+ +c123[ ]+\+ 0
+
+Symbol table '\.symtab' contains 134 entries:
+   Num:    Value          Size Type    Bind   Vis      Ndx Name
+     0: 0000000000000000     0 NOTYPE  LOCAL  DEFAULT  UND 
+     1: 0000000000000000     0 SECTION LOCAL  DEFAULT    1 
+     2: 0000000000000000     0 SECTION LOCAL  DEFAULT    3 
+     3: 0000000000000000     0 SECTION LOCAL  DEFAULT    5 
+     4: 0000000000000000     0 SECTION LOCAL  DEFAULT    6 
+     5: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND unresolved5
+     6: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND unresolved9
+     7: 000000000000000c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file1text2
+     8: 000000000000006c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file2text1
+     9: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc2
+    10: 0000000000000064     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc123
+    11: 0000000000000004     0 NOTYPE  GLOBAL DEFAULT    3 file1data1
+    12: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b123
+    13: 0000000000000020     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b2
+    14: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c4
+    15: 000000000000012c     0 NOTYPE  GLOBAL DEFAULT    3 file2data4
+    16: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa4
+    17: 00000000000000c4     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 ob3
+    18: 0000000000000058     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc12
+    19: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob4
+    20: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob1
+    21: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a13
+    22: 0000000000000050     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc3
+    23: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa2
+    24: 00000000000000a8     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c4
+    25: 000000000000005c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc13
+    26: 00000000000000a0     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c2
+    27: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa12
+    28: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND oa13
+    29: 00000000000000c8     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 ob4
+    30: 000000000000001c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b1
+    31: 0000000000000018     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file1text5
+    32: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c12
+    33: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND file1text5
+    34: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob2
+    35: 0000000000000010     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file1text3
+    36: 0000000000000124     0 NOTYPE  GLOBAL DEFAULT    3 file2data2
+    37: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a4
+    38: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a2
+    39: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND unresolved1
+    40: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND file1data3
+    41: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b13
+    42: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc23
+    43: 0000000000000060     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc23
+    44: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c2
+    45: 000000000000000c     0 NOTYPE  GLOBAL DEFAULT    3 file1data2
+    46: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b3
+    47: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND a3
+    48: 0000000000000078     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file2text3
+    49: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c13
+    50: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND unresolved9
+    51: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc123
+    52: 0000000000000028     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b4
+    53: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND file2data4
+    54: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c23
+    55: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc3
+    56: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa23
+    57: 00000000000000b4     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c23
+    58: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c123
+    59: 0000000000000030     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b13
+    60: 00000000000000b0     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c13
+    61: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b1
+    62: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND a123
+    63: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND oa23
+    64: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND a12
+    65: 00000000000000bc     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 ob1
+    66: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND unresolved7
+    67: 0000000000000068     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 start2
+    68: 00000000000000d8     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 ob123
+    69: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa13
+    70: 000000000000009c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c1
+    71: 0000000000000054     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc4
+    72: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa1
+    73: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND oa12
+    74: 00000000000000cc     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 ob12
+    75: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND file1data2
+    76: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND unresolved1
+    77: 00000000000000d0     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 ob13
+    78: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a3
+    79: 0000000000000018     0 NOTYPE  GLOBAL DEFAULT    3 file1data5
+    80: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa123
+    81: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND unresolved6
+    82: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b12
+    83: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc4
+    84: 0000000000000044     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b123
+    85: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob13
+    86: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND a2
+    87: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND oa123
+    88: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob23
+    89: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc1
+    90: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc12
+    91: 0000000000000004     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file1text1
+    92: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oc13
+    93: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND file1text1
+    94: 0000000000000074     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file2text2
+    95: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob3
+    96: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob12
+    97: 00000000000000c0     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 ob2
+    98: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a123
+    99: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c3
+   100: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND unresolved3
+   101: 0000000000000024     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b3
+   102: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND ob123
+   103: 000000000000007c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file2text4
+   104: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b4
+   105: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a12
+   106: 00000000000000a4     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c3
+   107: 0000000000000048     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc1
+   108: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND unresolved6
+   109: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND oa3
+   110: 00000000000000ac     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c12
+   111: 0000000000000034     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b23
+   112: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND a23
+   113: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b2
+   114: 000000000000004c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 oc2
+   115: 000000000000002c     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 b12
+   116: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND unresolved2
+   117: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 start
+   118: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a23
+   119: 0000000000000014     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 file1text4
+   120: 0000000000000128     0 NOTYPE  GLOBAL DEFAULT    3 file2data3
+   121: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND oa2
+   122: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND a1
+   123: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND unresolved4
+   124: 000000000000011c     0 NOTYPE  GLOBAL DEFAULT    3 file2data1
+   125: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND b23
+   126: 00000000000000b8     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4\]     1 c123
+   127: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND a13
+   128: 0000000000000010     0 NOTYPE  GLOBAL DEFAULT    3 file1data3
+   129: 0000000000000014     0 NOTYPE  GLOBAL DEFAULT    3 file1data4
+   130: 00000000000000d4     0 NOTYPE  GLOBAL DEFAULT \[<other>: 4]     1 ob23
+   131: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND c1
+   132: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT  UND oa3
+   133: 0000000000000000     0 <processor specific>: 13 GLOBAL DEFAULT  UND unresolved8
+
+Hex dump of section '\.text':
+.*
+  0x00000000 6ff0fff0 6ff0fff0 cc0000a0 cc000140 .*
+  0x00000010 cc000140 cc000140 cc000280 cc0001e0 .*
+  0x00000020 cc0000a0 cc0000a0 cc000280 cc000140 .*
+  0x00000030 cc000140 cc000320 c8000320 c8000320 .*
+  0x00000040 c8000320 cc0003c0 cc0003c0 6ff0fff0 .*
+  0x00000050 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00000060 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x00000070 cc0000a0 cc000140 cc000140 cc000140 .*
+  0x00000080 cc0001e0 cc0001e0 cc000320 cc000320 .*
+  0x00000090 cc000280 cc000280 cc000280 6ff0fff0 .*
+  0x000000a0 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x000000b0 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x000000c0 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .*
+  0x000000d0 6ff0fff0 6ff0fff0 6ff0fff0          .*
+
+Hex dump of section '\.data':
+.*
+  0x00000000 00000000 00000000 00000008 00000000 .*
+  0x00000010 00000000 00000000 00000000 00000000 .*
+  0x00000020 00000028 00000000 00000000 00000000 .*
+  0x00000030 00000000 00000000 00000000 00000000 .*
+  0x00000040 00000000 00000000 00000000 00000000 .*
+  0x00000050 00000000 00000000 00000000 00000000 .*
+  0x00000060 00000000 00000000 00000000 00000000 .*
+  0x00000070 00000000 00000000 00000000 00000000 .*
+  0x00000080 00000000 00000000 00000000 00000000 .*
+  0x00000090 00000000 00000000 00000000 00000000 .*
+  0x000000a0 00000000 00000000 00000000 00000000 .*
+  0x000000b0 00000000 00000000 00000000 00000000 .*
+  0x000000c0 00000000 00000000 00000000 00000000 .*
+  0x000000d0 00000000 00000000 00000000 00000000 .*
+  0x000000e0 00000000 00000000 00000000 00000000 .*
+  0x000000f0 00000000 00000000 00000000 00000000 .*
+  0x00000100 00000000 00000000 00000000 00000000 .*
+  0x00000110 00000000 00000000 00000000 00000000 .*
+  0x00000120 00000000 00000000 00000000 00000000 .*
+  0x00000130 00000000 00000000 00000000 00000000 .*
+  0x00000140 00000000 00000000 00000000 00000000 .*
+  0x00000150 00000000 00000000 00000000 00000000 .*
+  0x00000160 00000000 00000000 00000000 00000000 .*
+  0x00000170 00000000 00000000 00000000 00000000 .*
+  0x00000180 00000000 00000000 00000000 00000000 .*
+  0x00000190 00000000 00000000 00000000 00000000 .*
+  0x000001a0 00000000 00000000 00000000 00000000 .*
+  0x000001b0 00000000 00000000 00000000 00000000 .*
+  0x000001c0 00000000 00000000 00000000 00000000 .*
+  0x000001d0 00000000 00000000 00000000 00000000 .*
+  0x000001e0 00000000 00000000 00000000 00000000 .*
+  0x000001f0 00000000 00000000 00000000 00000000 .*
+  0x00000200 00000000 00000000 00000000 00000000 .*
+  0x00000210 00000000 00000000 00000000 00000000 .*
+  0x00000220 00000000 00000000                   .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/relfail.exp b/binutils-2.19/ld/testsuite/ld-sh/sh64/relfail.exp
new file mode 100644
index 0000000..87f8c7b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/relfail.exp
@@ -0,0 +1,219 @@
+# Expect script for ld-sh tests
+#   Copyright (C) 2001, 2002, 2003, 2004, 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Test SH reloc failures - that is, cases that ld must not allow.
+
+if ![istarget sh64-*-*] {
+    return
+}
+
+if [istarget sh64-*-linux*] {
+    set emul32 "shlelf32_linux"
+    set oformat32 "elf32-sh64-linux"
+    set startsym "_start"
+    set doabi64 0
+} elseif { [istarget sh64*-*-netbsd*] || [istarget sh5*-*-netbsd*] } then {
+    set emul32 "shelf32_nbsd"
+    set oformat32 "elf32-sh64-nbsd"
+    set startsym "__start"
+    set doabi64 1
+    set emul64 "shelf64_nbsd"
+    set oformat64 "elf64-sh64-nbsd"
+} else {
+    set emul32 "shelf32"
+    set oformat32 "elf32-sh64"
+    set startsym "start"
+    set doabi64 1
+    set emul64 "shelf64"
+    set oformat64 "elf64-sh64"
+}
+
+# opcode, asflags, ldflags, expected or "" for fail
+# opcode blank means rebuild relfail.o and set default as/ld options
+
+set sh64abi32relfailtests {
+
+    { "" "-isa=shcompact -abi=32" "-m $emul32 -Ttext 0x1000 --oformat $oformat32" "" }
+    { "mov.l lab,r0;.align 3;lab:nop" "" "" "mov.l 1008" }
+    { "mov.l to0,r0" "" "" "mov.l 1010" }
+    { "mov.l to1,r0" "" "" "" }
+    { "mov.l to2,r0" "" "" "" }
+    { "mov.l to3,r0" "" "" "" }
+    { "mov.l to4,r0" "" "" "mov.l 1014" }
+
+    { "" "-isa=shmedia -abi=32 -no-expand" "-m $emul32 -Ttext 0x1000 --oformat $oformat32" "" }
+    { "pta lab,tr0;.align 3;lab:nop" "" "" "pta.*1008" }
+
+    { "ld.q r0,datalabel to0 - 0x1000,r0" "" "" "ld.q.*,16," }
+    { "ld.q r0,datalabel to1 - 0x1000,r0" "" "" "" }
+    { "ld.q r0,datalabel to2 - 0x1000,r0" "" "" "" }
+    { "ld.q r0,datalabel to3 - 0x1000,r0" "" "" "" }
+    { "ld.q r0,datalabel to4 - 0x1000,r0" "" "" "" }
+
+    { "ld.l r0,datalabel to0 - 0x1000,r0" "" "" "ld.l.*,16," }
+    { "ld.l r0,datalabel to1 - 0x1000,r0" "" "" "" }
+    { "ld.l r0,datalabel to2 - 0x1000,r0" "" "" "" }
+    { "ld.l r0,datalabel to3 - 0x1000,r0" "" "" "" }
+    { "ld.l r0,datalabel to4 - 0x1000,r0" "" "" "ld.l.*,20," }
+
+    { "ld.w r0,datalabel to0 - 0x1000,r0" "" "" "ld.w.*,16," }
+    { "ld.w r0,datalabel to1 - 0x1000,r0" "" "" "" }
+    { "ld.w r0,datalabel to2 - 0x1000,r0" "" "" "ld.w.*,18," }
+    { "ld.w r0,datalabel to3 - 0x1000,r0" "" "" "" }
+    { "ld.w r0,datalabel to4 - 0x1000,r0" "" "" "ld.w.*,20," }
+
+}
+
+set sh64abi64relfailtests {
+
+    { "" "-isa=shmedia -abi=64 -no-expand" "-m $emul64 -Ttext 0x1000 --oformat $oformat64" "" }
+    { "pta lab,tr0;.align 3;lab:nop" "" "" "pta.*1008" }
+    { "pta datalabel to0,tr0" "" "" "pta.*1010" }
+    { "pta datalabel to1,tr0" "" "" "pta.*1011" }
+    { "pta datalabel to2,tr0" "" "" "" }
+    { "pta datalabel to3,tr0" "" "" "" }
+    { "pta datalabel to4,tr0" "" "" "pta.*1014" }
+
+    { "ld.q r0,datalabel to0 - 0x1000,r0" "" "" "ld.q.*,16," }
+    { "ld.q r0,datalabel to1 - 0x1000,r0" "" "" "" }
+    { "ld.q r0,datalabel to2 - 0x1000,r0" "" "" "" }
+    { "ld.q r0,datalabel to3 - 0x1000,r0" "" "" "" }
+    { "ld.q r0,datalabel to4 - 0x1000,r0" "" "" "" }
+
+    { "ld.l r0,datalabel to0 - 0x1000,r0" "" "" "ld.l.*,16," }
+    { "ld.l r0,datalabel to1 - 0x1000,r0" "" "" "" }
+    { "ld.l r0,datalabel to2 - 0x1000,r0" "" "" "" }
+    { "ld.l r0,datalabel to3 - 0x1000,r0" "" "" "" }
+    { "ld.l r0,datalabel to4 - 0x1000,r0" "" "" "ld.l.*,20," }
+
+    { "ld.w r0,datalabel to0 - 0x1000,r0" "" "" "ld.w.*,16," }
+    { "ld.w r0,datalabel to1 - 0x1000,r0" "" "" "" }
+    { "ld.w r0,datalabel to2 - 0x1000,r0" "" "" "ld.w.*,18," }
+    { "ld.w r0,datalabel to3 - 0x1000,r0" "" "" "" }
+    { "ld.w r0,datalabel to4 - 0x1000,r0" "" "" "ld.w.*,20," }
+
+}
+
+proc run_sh64relfailtests {sh64relfailtests} {
+    global ld
+    global as
+    global nm
+    global objdump
+    global readelf
+    global srcdir
+    global subdir
+    global emul32
+    global emul64
+    global oformat32
+    global oformat64
+    global startsym
+
+    set testindex 0
+    set is_unresolved 0
+
+    foreach testentry $sh64relfailtests {
+	set opcode [lindex $testentry 0]
+	set as_options [lindex $testentry 1]
+	set ld_options [subst [lindex $testentry 2]]
+	set expect_fail [lindex $testentry 3]
+	
+	set testname "SH64 relfail $opcode $as_options $ld_options"
+	
+	set objfiles {}
+	
+	incr testindex
+	
+	if {$opcode == ""} {
+	    set def_as_options $as_options
+	    set def_ld_options $ld_options
+	    set is_unresolved 0
+	    set baseobj "tmpdir/relfail-$testindex.o"
+	    if ![ld_assemble $as "$as_options $srcdir/$subdir/relfail.s" $baseobj] {
+		set is_unresolved 1
+	    }
+	    continue
+	}
+	
+	if {$as_options == ""} {
+	    set as_options $def_as_options
+	}
+	if {$ld_options == ""} {
+	    set ld_options $def_ld_options
+	}
+	
+	if { $is_unresolved } {
+	    unresolved $testname
+	    continue
+	}
+	
+	set asm [open "tmpdir/relfail-$testindex.s" "w"]
+	puts $asm " .text"
+	puts $asm " .global $startsym"
+	puts $asm "$startsym:"
+	puts $asm " $opcode"
+	close $asm
+	
+	if ![ld_assemble $as "$as_options tmpdir/relfail-$testindex.s" "tmpdir/relfail-$testindex.o"] {
+	    unresolved $testname
+	    continue
+	}
+	
+	set binfile "tmpdir/relfail-$testindex.x"
+	
+	file delete $binfile
+	set objects "tmpdir/relfail-$testindex.o $baseobj"
+	set result [ld_simple_link $ld $binfile "--no-warn-mismatch $ld_options $objects"]
+	
+	set exists [file exists $binfile]
+	if {$exists && $expect_fail == ""} {
+	    verbose "$testname: file $binfile exists when it shouldn't" 1
+	    catch "exec $objdump -d $binfile" objdump_output
+	    verbose $objdump_output 1
+	    fail "$testname (file exists)"
+	    continue
+	}
+	if {!$exists && $expect_fail != ""} {
+	    verbose "$testname: file $binfile doesn't exist when it should" 1
+	    fail "$testname (file missing)"
+	    continue
+	}
+	
+	if {$exists} {
+	    catch "exec $objdump -d $binfile" objdump_output
+	    regsub -all {[ 	][ 	]*} $objdump_output " " objdump_short
+	    if ![regexp $expect_fail $objdump_short junk] {
+		verbose $objdump_output 1
+		fail "$testname (incorrect reloc)"
+		continue
+	    }
+	}
+	
+	file delete "tmpdir/relfail-$testindex.s"
+	file delete "tmpdir/relfail-$testindex.o"
+	file delete $binfile
+	pass $testname
+    }
+}
+
+run_sh64relfailtests $sh64abi32relfailtests
+if {$doabi64} {
+    run_sh64relfailtests $sh64abi64relfailtests
+}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/relfail.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/relfail.s
new file mode 100644
index 0000000..5f5d171
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/relfail.s
@@ -0,0 +1,36 @@
+	.text
+	.align 4
+	.global	to0
+to0:
+	.byte 0
+	.global	to1
+to1:
+	.byte 0
+	.global	to2
+to2:
+	.byte 0
+	.global	to3
+to3:
+	.byte 0
+	.global	to4
+to4:
+	.byte 0
+	.byte 0
+
+	.data
+	.align 4
+	.global	do0
+do0:
+	.byte 0
+	.global	do1
+do1:
+	.byte 0
+	.global	do2
+do2:
+	.byte 0
+	.global	do3
+do3:
+	.byte 0
+	.global	do4
+do4:
+	.byte 0
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/sh64-1.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/sh64-1.s
new file mode 100644
index 0000000..3e488db
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/sh64-1.s
@@ -0,0 +1,20 @@
+! Test that all common kinds of relocs get right for simple use.
+! Auxiliary part.
+	.text
+	.mode SHmedia
+	.global foo
+	.global bar
+foo:
+	pt/l xyzzy,tr3
+bar:
+	nop
+
+	.data
+	.global baz
+baz:
+	.long foobar
+	.long bar
+	.global baz2
+baz2:
+	.long xyzzy
+foobar:	.long	baz
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/sh64-2.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/sh64-2.s
new file mode 100644
index 0000000..8ca24c0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/sh64-2.s
@@ -0,0 +1,27 @@
+! Test that all common kinds of relocs get right for simple cases.
+! Main part.
+	.text
+	.global start
+	.mode SHmedia
+start:
+	movi	foo,r33
+	movi	bar,r21
+	pt/l	bar,tr3
+	movi	foobar,r43
+	movi	baz2,r53
+	movi	foobar2,r4
+	pta	xyzzy,tr5
+	pt/u	plugh,tr1
+
+	.data
+	.global foobar
+foobar:	.long	baz
+foobar2:
+	.long	bar
+
+	.section .text.other,"ax"
+	.global xyzzy
+xyzzy:
+	nop
+plugh:
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/sh64.exp b/binutils-2.19/ld/testsuite/ld-sh/sh64/sh64.exp
new file mode 100644
index 0000000..57cc8a7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/sh64.exp
@@ -0,0 +1,137 @@
+# Expect script for ld-sh tests
+#   Copyright (C) 2000, 2001, 2002, 2003, 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Test SH linking; all types of relocs.  This tests the assembler and
+# tools like objdump as well as the linker.
+
+if ![istarget sh64-*-*] {
+    return
+}
+
+if [istarget sh64*-*-linux*] {
+    return
+}
+
+if { [istarget sh64*-*-netbsd*] || [istarget sh5*-*-netbsd*] } then {
+	return
+}
+
+# List contains test-items with 3 items followed by 2 lists:
+# 0:name 1:ld options 2:assembler options
+# 3:filenames of assembler files 4: action and options. 5: name of output file
+
+# Actions:
+# objdump: Apply objdump options on result.  Compare with regex (last arg).
+# nm: Apply nm options on result.  Compare with regex (last arg).
+# readelf: Apply readelf options on result.  Compare with regex (last arg).
+
+# Note that the contents dump is the same for "inter-file datalabel
+# references, 64-bit ABI" as for 32-bit ABI and ELF so we re-use it.
+
+set sh64tests {
+    {"SH64 linking, 64-bit ABI" "-mshelf64"
+     "--abi=64" {sh64-1.s sh64-2.s}
+     {{objdump -sr abi64.sd} {objdump -x abi64.xd}} "abi64.bin" }
+    {"SH64 linking, 64-bit ABI, -no-expand" "-mshelf64"
+     "--abi=64 -no-expand" {sh64-1.s sh64-2.s}
+     {{objdump -sr abixx-noexp.sd}} "abi64-noexp.bin" }
+    {"SH64 linking, 32-bit ABI" "-mshelf32"
+     "--abi=32" {sh64-1.s sh64-2.s}
+     {{objdump -sr abi32.sd} {objdump -x abi32.xd}} "abi32.bin" }
+    {"SH64 linking, 32-bit ABI, -no-expand" "-mshelf32"
+     "--abi=32 -no-expand" {sh64-1.s sh64-2.s}
+     {{objdump -sr abixx-noexp.sd}} "abi32-noexp.bin" }
+    {"SH64 linking, single multi-ISA object" "-mshelf32"
+     "--abi=32" {shmix-1.s}
+     {{objdump -sr mix1.sd} {objdump -x mix1.xd}} "mix1.bin" }
+    {"SH64 linking, single multi-ISA object, -no-expand" "-mshelf32"
+     "--abi=32 -no-expand" {shmix-1.s}
+     {{objdump -sr mix1-noexp.sd}} "mix1-noexp.bin" }
+    {"SH64 linking, two different-ISA objects" "-mshelf32"
+     "--abi=32" {shmix-2.s shmix-3.s}
+     {{objdump -sr mix2.sd} {objdump -x mix2.xd}} "mix2.bin" }
+    {"SH64 linking, two different-ISA objects, -no-expand" "-mshelf32"
+     "--abi=32 -no-expand" {shmix-2.s shmix-3.s}
+     {{objdump -sr mix2-noexp.sd}} "mix2-noexp.bin" }
+    {"SH64 linking, single SHcompact" "-mshelf32"
+     "--isa=SHcompact" {shcmp-1.s}
+     {{objdump -sr cmpct1.sd} {objdump -x cmpct1.xd}} "cmpct1.bin" }
+    {"SH64 inter-file datalabel references, 64-bit ABI" "-mshelf64"
+     "--abi=64" {shdl-1.s shdl-2.s}
+     {{objdump -sr shdl64.sd} {objdump -x shdl64.xd}} "shdl64.bin" }
+    {"SH64 inter-file datalabel references, 32-bit ABI" "-mshelf32"
+     "--abi=32" {shdl-1.s shdl-2.s}
+     {{objdump -sr shdl64.sd} {objdump -x shdl32.xd}} "shdl32.bin" }
+    {"SH64 inter-file datalabel references and gc-sections, 32-bit ABI" "-mshelf32 --gc-sections"
+     "--abi=32" {dlsection-1.s }
+     {{objdump -sr dlsection.sd}} "dlsection32.bin" }
+    {"SH64 inter-file datalabel references and gc-sections, 64-bit ABI" "-mshelf64 --gc-sections"
+     "--abi=64" {dlsection-1.s }
+     {{objdump -sr dlsection.sd}} "dlsection64.bin" }
+    {"SH64 simple partial linking, 32-bit ABI" "-mshelf32 -r"
+     "--abi=32" {rel-1.s rel-2.s}
+     {{objdump -sx rel32.xd}} "rel32.bin" }
+    {"SH64 simple partial linking, 64-bit ABI" "-mshelf64 -r"
+     "--abi=64" {rel-1.s rel-2.s}
+     {{objdump -sx rel64.xd}} "rel64.bin" }
+    {"SH64 partial linking with datalabel references, 32-bit ABI" "-mshelf32 -r"
+     "--abi=32" {reldl-1.s reldl-2.s}
+     {{readelf {-s -r -x 1 -x 3} reldl32.rd}} "reldl32.bin" }
+    {"SH64 partial linking with datalabel references, 64-bit ABI" "-mshelf64 -r"
+     "--abi=64" {reldl-1.s reldl-2.s}
+     {{readelf {-s -r -x 1 -x 3} reldl64.rd}} "reldl64.bin" }
+    {"Handling SH64 assembler-generated .cranges" "-mshelf32"
+     "--abi=32" {crange-2a.s crange-1.s}
+     {{readelf {-S -s -r -x 1 -x 2 -x 4} crange1.rd}} "crange1.bin" }
+    {"Handling SH64 assembler-generated .cranges, partial linking" "-mshelf32 -r"
+     "--abi=32" {crange-2a.s}
+     {{readelf {-S -s -r -x 2 -x 6} crangerel1.rd}} "crangerel1.bin" }
+    {"Mixing SH64 assembler-generated with linker-generated .cranges" "-mshelf32"
+     "--abi=32" {crange-2a.s crange-2b.s crange-1.s}
+     {{readelf {-S -s -r -x 2 -x 4} crange2.rd}} "crange2.bin" }
+    {"Mixing SH64 assembler-generated with linker-generated .cranges, partial linking"
+     "-mshelf32 -r"
+     "--abi=32" {crange-2a.s crange-2c.s crange-2d.s crange-2e.s}
+     {{readelf {-S -s -r -x 2 -x 6} crangerel2.rd}} "crangerel2.bin" }
+    {"Merge and use of SH64 .cranges, some not originally in order" "-mshelf32"
+     "--abi=32"
+     {crange-2e.s crange-2f.s crange-2g.s crange-2a.s crange-2d.s crange-2i.s
+      crange-2h.s crange-1.s}
+      {{readelf {-S -s -x 2 -x 4} crange3.rd} {objdump -d crange3.dd}} "crange3.bin" }
+    {"Sorted SH64 .cranges, entry at SHcompact code" "-mshelf32 --entry diversion"
+     "--abi=32"
+     {crange-2e.s crange-2f.s crange-2g.s crange-2a.s crange-2d.s crange-2i.s
+      crange-2h.s crange-1.s}
+      {{readelf {-h -S -s -x 2 -x 4} crange3-cmpct.rd}} "crange3-cmpct.bin" }
+    {"Sorted SH64 .cranges, entry at SHmedia code" "-mshelf32 --entry diversion2"
+     "--abi=32"
+     {crange-2e.s crange-2f.s crange-2g.s crange-2a.s crange-2d.s crange-2i.s
+      crange-2h.s crange-1.s}
+      {{readelf {-h -S -s -x 2 -x 4} crange3-media.rd}} "crange3-media.bin" }
+    {"SH64 Big Endianness" "-mshelf64 -Tendian.ld"
+     "--abi=64" {endian.s}
+     {{objdump -s endian.sbd} {objdump -d endian.dbd}} "endianb.bin" }
+    {"SH64 Little Endianness" "-mshlelf64 -Tendian.ld"
+     "--abi=64 --little" {endian.s}
+     {{objdump -s endian.sld} {objdump -d endian.dld}} "endinanl.bin" }
+}
+
+run_ld_link_tests $sh64tests
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/shcmp-1.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/shcmp-1.s
new file mode 100644
index 0000000..f915af4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/shcmp-1.s
@@ -0,0 +1,15 @@
+! A single SHcompact file, that should link correctly.
+	.text
+	.global start
+start:
+	mova next,r0
+	nop
+next:
+	nop
+	mov #42,r10
+
+	.section .rodata
+	.long start
+here:
+	.long here
+	.long next
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/shdl-1.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/shdl-1.s
new file mode 100644
index 0000000..0f2803c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/shdl-1.s
@@ -0,0 +1,359 @@
+! Test inter-file DataLabel support.
+!
+! We need to test symbols that are:
+! * Global, defined in this file, with/without/both-with-without datalabel
+!   references.
+! * The above in combinations where the reference is/is not from within
+!   the same section.  The implementation is currently indifferent to that
+!   fact, but it seems likely to be something that can change.
+! * Extern with/without/both-with-without datalabel-qualified references.
+! * The above with reference from same *and* other file.
+! * The above in combinations for where the symbol is/is not a
+!   STO_SH5_ISA32-marked symbol.
+
+! There will be omissions and overlap in combinations.  Add spotted
+! omissions with complementary tests in other files.
+
+	.text
+	.mode SHmedia
+
+! For good measure, we start with a nop to get a non-zero offset within
+! the .text section.
+
+	.global start
+start:
+	nop
+
+! Referenced from the same file, same section, is ISA32, only referenced
+! with datalabel qualifier.
+	.global foo
+foo:
+	nop
+	movi (datalabel foo + 8) & 65535,r30
+
+! Referenced from same file, same section, both with and without
+! datalabel qualifier, is ISA32.
+	.global fooboth
+fooboth:
+	nop
+	movi (datalabel fooboth + 16) & 65535,r40
+	movi (fooboth + 12) & 65535,r40
+
+! Same as above, but in different order.
+	.global fooboth2
+fooboth2:
+	nop
+	movi (fooboth2 + 12) & 65535,r40
+	movi (datalabel fooboth2 + 16) & 65535,r40
+
+! Referenced from this file and another, same section, is ISA32.
+	.global foowithout
+foowithout:
+	nop
+	movi (foowithout + 24) & 65535,r30
+
+! Same as above, different section than definition.
+
+	.global foo_other
+foo_other:
+	nop
+	.global foo_otherboth
+foo_otherboth:
+	nop
+	.global foo_otherboth2
+foo_otherboth2:
+	nop
+	.global foo_otherwithout
+foo_otherwithout:
+	nop
+
+	.section .rodata
+	.long datalabel foo_other + 4
+	.long datalabel foo_otherboth + 40
+	.long foo_otherboth + 24
+	.long foo_otherboth2 + 24
+	.long datalabel foo_otherboth2 + 40
+	.long foo_otherwithout
+
+	.text
+
+! Same as above, mixing references from same and other section.
+	.global foo_mix
+foo_mix:
+	nop
+	movi (datalabel foo_mix + 8) & 65535,r30
+	.global foo_mix2
+foo_mix2:
+	nop
+	movi (foo_mix2 + 8) & 65535,r30
+	.global foo_mixboth
+foo_mixboth:
+	nop
+	movi (datalabel foo_mixboth + 80) & 65535,r30
+	movi (foo_mixboth + 80) & 65535,r30
+	.global foo_mixboth2
+foo_mixboth2:
+	nop
+	movi (foo_mixboth2 + 64) & 65535,r30
+	movi (datalabel foo_mixboth2 + 64) & 65535,r30
+	.global foo_mixwithout
+foo_mixwithout:
+	nop
+	movi (foo_mixwithout + 42) & 65535,r30
+	.global foo_mixwithout2
+foo_mixwithout2:
+	nop
+	movi (foo_mixwithout2 + 24) & 65535,r30
+
+	.section .rodata
+	.long foo_mix + 4
+	.long datalabel foo_mix2 + 48
+	.long datalabel foo_mixboth + 400
+	.long foo_mixboth + 420
+	.long foo_mixboth2 + 248
+	.long datalabel foo_mixboth2 + 240
+	.long foo_mixwithout
+
+! Same as above, referencing symbol in other file (reference only from
+! this to other file).
+
+	.text
+	nop
+	movi (datalabel bar + 8) & 65535,r30
+
+	movi (datalabel barboth + 16) & 65535,r40
+	movi (barboth + 12) & 65535,r40
+
+	movi (barboth2 + 12) & 65535,r40
+	movi (datalabel barboth2 + 16) & 65535,r40
+
+	movi (barwithout + 24) & 65535,r30
+
+	.section .rodata
+	.long datalabel bar_other + 4
+	.long datalabel bar_otherboth + 40
+	.long bar_otherboth + 24
+	.long bar_otherboth2 + 24
+	.long datalabel bar_otherboth2 + 40
+	.long bar_otherwithout
+
+	.text
+	movi (datalabel bar_mix + 8) & 65535,r30
+	movi (bar_mix2 + 8) & 65535,r30
+	movi (datalabel bar_mixboth + 80) & 65535,r30
+	movi (bar_mixboth + 80) & 65535,r30
+	movi (bar_mixboth2 + 64) & 65535,r30
+	movi (datalabel bar_mixboth2 + 64) & 65535,r30
+	movi (bar_mixwithout + 42) & 65535,r30
+	movi (bar_mixwithout2 + 24) & 65535,r30
+
+	.section .rodata
+	.long bar_mix + 4
+	.long datalabel bar_mix2 + 48
+	.long datalabel bar_mixboth + 400
+	.long bar_mixboth + 420
+	.long bar_mixboth2 + 248
+	.long datalabel bar_mixboth2 + 240
+	.long bar_mixwithout
+
+! Same as above, referencing symbol in other file *and* within that file.
+
+	.text
+	movi (datalabel baz + 8) & 65535,r30
+
+	movi (datalabel bazboth + 16) & 65535,r40
+	movi (bazboth + 12) & 65535,r40
+
+	movi (bazboth2 + 12) & 65535,r40
+	movi (datalabel bazboth2 + 16) & 65535,r40
+
+	movi (bazwithout + 24) & 65535,r30
+
+	.section .rodata
+	.long datalabel baz_other + 4
+	.long datalabel baz_otherboth + 40
+	.long baz_otherboth + 24
+	.long baz_otherboth2 + 24
+	.long datalabel baz_otherboth2 + 40
+	.long baz_otherwithout
+
+	.text
+	movi (datalabel baz_mix + 8) & 65535,r30
+	movi (baz_mix2 + 8) & 65535,r30
+	movi (datalabel baz_mixboth + 80) & 65535,r30
+	movi (baz_mixboth + 80) & 65535,r30
+	movi (baz_mixboth2 + 64) & 65535,r30
+	movi (datalabel baz_mixboth2 + 64) & 65535,r30
+	movi (baz_mixwithout + 42) & 65535,r30
+	movi (baz_mixwithout2 + 24) & 65535,r30
+
+	.section .rodata
+	.long baz_mix + 4
+	.long datalabel baz_mix2 + 48
+	.long datalabel baz_mixboth + 400
+	.long baz_mixboth + 420
+	.long baz_mixboth2 + 248
+	.long datalabel baz_mixboth2 + 240
+	.long baz_mixwithout
+
+! Same as all of the above, but where the symbol is not an ISA32 one.
+
+	.data
+	.global dfoo
+dfoo:
+	.long 0
+	.long (datalabel dfoo + 8)
+
+	.global dfooboth
+dfooboth:
+	.long 0
+	.long (datalabel dfooboth + 16)
+	.long (dfooboth + 12)
+
+	.global dfooboth2
+dfooboth2:
+	.long 0
+	.long (dfooboth2 + 12)
+	.long (datalabel dfooboth2 + 16)
+
+	.global dfoowithout
+dfoowithout:
+	.long 0
+	.long (dfoowithout + 24)
+
+	.global dfoo_other
+dfoo_other:
+	.long 0
+	.global dfoo_otherboth
+dfoo_otherboth:
+	.long 0
+	.global dfoo_otherboth2
+dfoo_otherboth2:
+	.long 0
+	.global dfoo_otherwithout
+dfoo_otherwithout:
+	.long 0
+
+	.section .rodata
+	.long datalabel dfoo_other + 4
+	.long datalabel dfoo_otherboth + 40
+	.long dfoo_otherboth + 24
+	.long dfoo_otherboth2 + 24
+	.long datalabel dfoo_otherboth2 + 40
+	.long dfoo_otherwithout
+
+	.data
+
+! Same as above, mixing references from same and other section.
+	.global dfoo_mix
+dfoo_mix:
+	.long 0
+	.long (datalabel dfoo_mix + 8)
+	.global dfoo_mix2
+dfoo_mix2:
+	.long 0
+	.long (dfoo_mix2 + 8)
+	.global dfoo_mixboth
+dfoo_mixboth:
+	.long 0
+	.long (datalabel dfoo_mixboth + 80)
+	.long (dfoo_mixboth + 80)
+	.global dfoo_mixboth2
+dfoo_mixboth2:
+	.long 0
+	.long (dfoo_mixboth2 + 64)
+	.long (datalabel dfoo_mixboth2 + 64)
+	.global dfoo_mixwithout
+dfoo_mixwithout:
+	.long 0
+	.long (dfoo_mixwithout + 42)
+	.global dfoo_mixwithout2
+dfoo_mixwithout2:
+	.long 0
+	.long (dfoo_mixwithout2 + 24)
+
+	.section .rodata
+	.long dfoo_mix + 4
+	.long datalabel dfoo_mix2 + 48
+	.long datalabel dfoo_mixboth + 400
+	.long dfoo_mixboth + 420
+	.long dfoo_mixboth2 + 248
+	.long datalabel dfoo_mixboth2 + 240
+	.long dfoo_mixwithout
+
+! Same as above, referencing symbol in other file (reference only from
+! this to other file).
+
+	.text
+	movi (datalabel dbarboth + 16) & 65535,r40
+	movi (dbarboth + 12) & 65535,r40
+	movi (dbarboth2 + 12) & 65535,r40
+	movi (datalabel dbarboth2 + 16) & 65535,r40
+	movi (dbarwithout + 24) & 65535,r30
+
+	.data
+	.long (datalabel dbar + 8)
+	.long datalabel dbar_other + 4
+	.long datalabel dbar_otherboth + 40
+	.long dbar_otherboth + 24
+	.long dbar_otherboth2 + 24
+	.long datalabel dbar_otherboth2 + 40
+	.long dbar_otherwithout
+
+	.text
+	movi (datalabel dbar_mix + 8) & 65535,r30
+	movi (dbar_mix2 + 8) & 65535,r30
+	movi (datalabel dbar_mixboth + 80) & 65535,r30
+	movi (dbar_mixboth + 80) & 65535,r30
+	movi (dbar_mixboth2 + 64) & 65535,r30
+	movi (datalabel dbar_mixboth2 + 64) & 65535,r30
+	movi (dbar_mixwithout + 42) & 65535,r30
+	movi (dbar_mixwithout2 + 24) & 65535,r30
+
+	.data
+	.long dbar_mix + 4
+	.long datalabel dbar_mix2 + 48
+	.long datalabel dbar_mixboth + 400
+	.long dbar_mixboth + 420
+	.long dbar_mixboth2 + 248
+	.long datalabel dbar_mixboth2 + 240
+	.long dbar_mixwithout
+
+! Same as above, referencing symbol in other file *and* within that file.
+
+	.text
+	movi (datalabel dbazboth + 16) & 65535,r40
+	movi (dbazboth + 12) & 65535,r40
+
+	movi (dbazboth2 + 12) & 65535,r40
+	movi (datalabel dbazboth2 + 16) & 65535,r40
+
+	movi (dbazwithout + 24) & 65535,r30
+
+	.data
+	.long (datalabel dbaz + 8)
+	.long datalabel dbaz_other + 4
+	.long datalabel dbaz_otherboth + 40
+	.long dbaz_otherboth + 24
+	.long dbaz_otherboth2 + 24
+	.long datalabel dbaz_otherboth2 + 40
+	.long dbaz_otherwithout
+
+	.text
+	movi (datalabel dbaz_mix + 8) & 65535,r30
+	movi (dbaz_mix2 + 8) & 65535,r30
+	movi (datalabel dbaz_mixboth + 80) & 65535,r30
+	movi (dbaz_mixboth + 80) & 65535,r30
+	movi (dbaz_mixboth2 + 64) & 65535,r30
+	movi (datalabel dbaz_mixboth2 + 64) & 65535,r30
+	movi (dbaz_mixwithout + 42) & 65535,r30
+	movi (dbaz_mixwithout2 + 24) & 65535,r30
+
+	.data
+	.long dbaz_mix + 4
+	.long datalabel dbaz_mix2 + 48
+	.long datalabel dbaz_mixboth + 400
+	.long dbaz_mixboth + 420
+	.long dbaz_mixboth2 + 248
+	.long datalabel dbaz_mixboth2 + 240
+	.long dbaz_mixwithout
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/shdl-2.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/shdl-2.s
new file mode 100644
index 0000000..a41fd52
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/shdl-2.s
@@ -0,0 +1,286 @@
+! Part two of test for inter-file DataLabel support.
+
+	.mode SHmedia
+	.text
+part2:
+	movi (datalabel foowithout + 16) & 65535, r24
+
+	.section .rodata
+	.long datalabel foo_otherwithout + 32
+
+	.text
+	movi (datalabel foo_mixwithout + 1024) & 65535, r24
+	.section .rodata
+	.long datalabel foo_mixwithout + 32
+
+	.text
+	movi (datalabel foo_mixwithout2 + 1024) & 65535, r24
+	.section .rodata
+	.long foo_mixwithout2 + 32
+
+	.text
+	.global bar
+bar:
+	nop
+
+	.global barboth
+barboth:
+	nop
+
+	.global barboth2
+barboth2:
+	nop
+
+	.global barwithout
+barwithout:
+	nop
+
+	.global bar_other
+bar_other:
+	nop
+	.global bar_otherboth
+bar_otherboth:
+	nop
+	.global bar_otherboth2
+bar_otherboth2:
+	nop
+	.global bar_otherwithout
+bar_otherwithout:
+	nop
+
+	.text
+
+	.global bar_mix
+bar_mix:
+	nop
+	.global bar_mix2
+bar_mix2:
+	nop
+	.global bar_mixboth
+bar_mixboth:
+	nop
+	.global bar_mixboth2
+bar_mixboth2:
+	nop
+	.global bar_mixwithout
+bar_mixwithout:
+	nop
+	.global bar_mixwithout2
+bar_mixwithout2:
+	nop
+
+! Almost-copy of "foo" in primary file.
+
+	.global baz
+baz:
+	nop
+	movi (datalabel baz + 8) & 65535,r30
+
+	.global bazboth
+bazboth:
+	nop
+	movi (datalabel bazboth + 16) & 65535,r40
+	movi (bazboth + 12) & 65535,r40
+
+	.global bazboth2
+bazboth2:
+	nop
+	movi (bazboth2 + 12) & 65535,r40
+	movi (datalabel bazboth2 + 16) & 65535,r40
+
+	.global bazwithout
+bazwithout:
+	nop
+	movi (datalabel bazwithout + 24) & 65535,r30
+
+	.global baz_other
+baz_other:
+	nop
+	.global baz_otherboth
+baz_otherboth:
+	nop
+	.global baz_otherboth2
+baz_otherboth2:
+	nop
+	.global baz_otherwithout
+baz_otherwithout:
+	nop
+
+	.section .rodata
+	.long datalabel baz_other + 4
+	.long datalabel baz_otherboth + 40
+	.long baz_otherboth + 24
+	.long baz_otherboth2 + 24
+	.long datalabel baz_otherboth2 + 40
+	.long baz_otherwithout
+
+	.text
+
+	.global baz_mix
+baz_mix:
+	nop
+	movi (datalabel baz_mix + 8) & 65535,r30
+	.global baz_mix2
+baz_mix2:
+	nop
+	movi (baz_mix2 + 8) & 65535,r30
+	.global baz_mixboth
+baz_mixboth:
+	nop
+	movi (datalabel baz_mixboth + 80) & 65535,r30
+	movi (baz_mixboth + 80) & 65535,r30
+	.global baz_mixboth2
+baz_mixboth2:
+	nop
+	movi (baz_mixboth2 + 64) & 65535,r30
+	movi (datalabel baz_mixboth2 + 64) & 65535,r30
+	.global baz_mixwithout
+baz_mixwithout:
+	nop
+	movi (baz_mixwithout + 42) & 65535,r30
+	.global baz_mixwithout2
+baz_mixwithout2:
+	nop
+	movi (baz_mixwithout2 + 24) & 65535,r30
+
+	.section .rodata
+	.long baz_mix + 4
+	.long datalabel baz_mix2 + 48
+	.long datalabel baz_mixboth + 400
+	.long baz_mixboth + 420
+	.long baz_mixboth2 + 248
+	.long datalabel baz_mixboth2 + 240
+	.long baz_mixwithout
+
+	.data
+	.long datalabel dfoowithout + 44
+	.long datalabel dfoo_mixwithout + 48
+	.long datalabel dfoo_mixwithout2 + 84
+
+	.global dbar
+dbar:
+	.long 0
+	.global dbarboth
+dbarboth:
+	.long 0
+	.global dbarboth2
+dbarboth2:
+	.long 0
+	.global dbarwithout
+dbarwithout:
+	.long 0
+	.global dbar_other
+dbar_other:
+	.long 0
+	.global dbar_otherboth
+dbar_otherboth:
+	.long 0
+	.global dbar_otherboth2
+dbar_otherboth2:
+	.long 0
+	.global dbar_otherwithout
+dbar_otherwithout:
+	.long 0
+
+	.global dbar_mix
+dbar_mix:
+	.long 0
+	.global dbar_mix2
+dbar_mix2:
+	.long 0
+	.global dbar_mixboth
+dbar_mixboth:
+	.long 0
+	.global dbar_mixboth2
+dbar_mixboth2:
+	.long 0
+	.global dbar_mixwithout
+dbar_mixwithout:
+	.long 0
+	.global dbar_mixwithout2
+dbar_mixwithout2:
+	.long 0
+
+! Almost-copy of "dfoo" in primary file.
+
+	.data
+	.global dbaz
+dbaz:
+	.long 0
+	.long (datalabel dbaz + 8)
+
+	.global dbazboth
+dbazboth:
+	.long 0
+	.long (datalabel dbazboth + 16)
+	.long (dbazboth + 12)
+
+	.global dbazboth2
+dbazboth2:
+	.long 0
+	.long (dbazboth2 + 12)
+	.long (datalabel dbazboth2 + 16)
+
+	.global dbazwithout
+dbazwithout:
+	.long 0
+	.long (dbazwithout + 24)
+
+	.global dbaz_other
+dbaz_other:
+	.long 0
+	.global dbaz_otherboth
+dbaz_otherboth:
+	.long 0
+	.global dbaz_otherboth2
+dbaz_otherboth2:
+	.long 0
+	.global dbaz_otherwithout
+dbaz_otherwithout:
+	.long 0
+
+	.section .rodata
+	.long datalabel dbaz_other + 4
+	.long datalabel dbaz_otherboth + 40
+	.long dbaz_otherboth + 24
+	.long dbaz_otherboth2 + 24
+	.long datalabel dbaz_otherboth2 + 40
+	.long dbaz_otherwithout
+
+	.data
+
+	.global dbaz_mix
+dbaz_mix:
+	.long 0
+	.long (datalabel dbaz_mix + 8)
+	.global dbaz_mix2
+dbaz_mix2:
+	.long 0
+	.long (dbaz_mix2 + 8)
+	.global dbaz_mixboth
+dbaz_mixboth:
+	.long 0
+	.long (datalabel dbaz_mixboth + 80)
+	.long (dbaz_mixboth + 80)
+	.global dbaz_mixboth2
+dbaz_mixboth2:
+	.long 0
+	.long (dbaz_mixboth2 + 64)
+	.long (datalabel dbaz_mixboth2 + 64)
+	.global dbaz_mixwithout
+dbaz_mixwithout:
+	.long 0
+	.long (dbaz_mixwithout + 42)
+	.global dbaz_mixwithout2
+dbaz_mixwithout2:
+	.long 0
+	.long (dbaz_mixwithout2 + 24)
+
+	.section .rodata
+	.long dbaz_mix + 4
+	.long datalabel dbaz_mix2 + 48
+	.long datalabel dbaz_mixboth + 400
+	.long dbaz_mixboth + 420
+	.long dbaz_mixboth2 + 248
+	.long datalabel dbaz_mixboth2 + 240
+	.long dbaz_mixwithout
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/shdl32.xd b/binutils-2.19/ld/testsuite/ld-sh/sh64/shdl32.xd
new file mode 100644
index 0000000..56773e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/shdl32.xd
@@ -0,0 +1,123 @@
+.*:     file format .*-sh64
+.*
+architecture: sh5, flags 0x0+112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x0+1001
+
+Program Header:
+    LOAD off    0x0+100 vaddr 0x0+1000 paddr 0x0+1000 align 2\*\*7
+         filesz 0x0+348 memsz 0x0+348 flags r-x
+    LOAD off    0x0+448 vaddr 0x0+13c8 paddr 0x0+13c8 align 2\*\*7
+         filesz 0x0+194 memsz 0x0+194 flags rw-
+    LOAD off    0x0+600 vaddr 0x0+80000 paddr 0x0+80000 align 2\*\*7
+         filesz 0x00000004 memsz 0x00000004 flags rw-
+
+Sections:
+Idx Name          Size      VMA       LMA       File off  Algn
+  0 \.text         0+204  0+1000  0+1000  0+100  2\*\*0
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 \.rodata       0+144  0+1204  0+1204  0+304  2\*\*2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  2 \.data         0+194  0+13c8  0+13c8  0+448  2\*\*2
+                  CONTENTS, ALLOC, LOAD, DATA
+  3 \.stack        0+4  0+80000  0+80000  0+600  2\*\*0
+                  CONTENTS, ALLOC, LOAD, DATA
+SYMBOL TABLE:
+0+1000 l    d  \.text	0+ (|\.text)
+0+1204 l    d  \.rodata	0+ (|\.rodata)
+0+13c8 l    d  \.data	0+ (|\.data)
+0+80000 l    d  \.stack	0+ (|\.stack)
+0+1150 l       \.text	0+ 0x04 part2
+0+13f8 g       \.data	0+ dfoo_otherboth2
+0+1178 g       \.text	0+ 0x04 bar_otherwithout
+0+11b4 g       \.text	0+ 0x04 bazwithout
+0+1428 g       \.data	0+ dfoo_mixwithout
+0+1554 g       \.data	0+ dbaz_mixwithout2
+0+11bc g       \.text	0+ 0x04 baz_other
+0+11cc g       \.text	0+ 0x04 baz_mix
+0+11c0 g       \.text	0+ 0x04 baz_otherboth
+0+13e8 g       \.data	0+ dfoowithout
+0+14b4 g       \.data	0+ dbar
+0+106c g       \.text	0+ 0x04 foo_mixwithout2
+0+11a8 g       \.text	0+ 0x04 bazboth2
+0+13fc g       \.data	0+ dfoo_otherwithout
+0+11c4 g       \.text	0+ 0x04 baz_otherboth2
+0+1174 g       \.text	0+ 0x04 bar_otherboth2
+0+1194 g       \.text	0+ 0x04 baz
+0+13c8 g       \.data	0+ dfoo
+0+14e8 g       \.data	0+ dbar_mixwithout2
+0+13dc g       \.data	0+ dfooboth2
+0+1408 g       \.data	0+ dfoo_mix2
+0+154c g       \.data	0+ dbaz_mixwithout
+0+1044 g       \.text	0+ 0x04 foo_mix2
+0+1018 g       \.text	0+ 0x04 fooboth2
+0+14cc g       \.data	0+ dbar_otherboth2
+0+117c g       \.text	0+ 0x04 bar_mix
+0+14d0 g       \.data	0+ dbar_otherwithout
+0+11dc g       \.text	0+ 0x04 baz_mixboth
+0+14c8 g       \.data	0+ dbar_otherboth
+0+150c g       \.data	0+ dbazwithout
+0+152c g       \.data	0+ dbaz_mix2
+0+1184 g       \.text	0+ 0x04 bar_mixboth
+0+13f4 g       \.data	0+ dfoo_otherboth
+0+14dc g       \.data	0+ dbar_mixboth
+0+1024 g       \.text	0+ 0x04 foowithout
+0+14e4 g       \.data	0+ dbar_mixwithout
+0+11fc g       \.text	0+ 0x04 baz_mixwithout2
+0+1030 g       \.text	0+ 0x04 foo_otherboth
+0+1540 g       \.data	0+ dbaz_mixboth2
+0+104c g       \.text	0+ 0x04 foo_mixboth
+0+1534 g       \.data	0+ dbaz_mixboth
+0+103c g       \.text	0+ 0x04 foo_mix
+0+1518 g       \.data	0+ dbaz_otherboth
+0+14e0 g       \.data	0+ dbar_mixboth2
+0+14ec g       \.data	0+ dbaz
+0+1524 g       \.data	0+ dbaz_mix
+0+13c8 g       .*	0+ ___dtors
+0+141c g       \.data	0+ dfoo_mixboth2
+0+119c g       \.text	0+ 0x04 bazboth
+0+13f0 g       \.data	0+ dfoo_other
+0+11e8 g       \.text	0+ 0x04 baz_mixboth2
+0+1514 g       \.data	0+ dbaz_other
+0+1164 g       \.text	0+ 0x04 barboth2
+0+1168 g       \.text	0+ 0x04 barwithout
+0+14d8 g       \.data	0+ dbar_mix2
+0+1560 g       \*ABS\*	0+ __bss_start
+0+1410 g       \.data	0+ dfoo_mixboth
+0+14c4 g       \.data	0+ dbar_other
+0+1180 g       \.text	0+ 0x04 bar_mix2
+0+14f4 g       \.data	0+ dbazboth
+0+1038 g       \.text	0+ 0x04 foo_otherwithout
+0+1190 g       \.text	0+ 0x04 bar_mixwithout2
+0+13c8 g       .*	0+ ___ctors_end
+0+1064 g       \.text	0+ 0x04 foo_mixwithout
+0+116c g       \.text	0+ 0x04 bar_other
+0+13d0 g       \.data	0+ dfooboth
+0+1034 g       \.text	0+ 0x04 foo_otherboth2
+0+1400 g       \.data	0+ dfoo_mix
+0+13c8 g       .*	0+ ___ctors
+0+14d4 g       \.data	0+ dbar_mix
+0+100c g       \.text	0+ 0x04 fooboth
+0+1170 g       \.text	0+ 0x04 bar_otherboth
+0+14c0 g       \.data	0+ dbarwithout
+0+1004 g       \.text	0+ 0x04 foo
+0+102c g       \.text	0+ 0x04 foo_other
+0+1560 g       \*ABS\*	0+ _edata
+0+1560 g       \*ABS\*	0+ _end
+0+1430 g       \.data	0+ dfoo_mixwithout2
+0+1058 g       \.text	0+ 0x04 foo_mixboth2
+0+11d4 g       \.text	0+ 0x04 baz_mix2
+0+11c8 g       \.text	0+ 0x04 baz_otherwithout
+0+1000 g       \.text	0+ 0x04 start
+0+14bc g       \.data	0+ dbarboth2
+0+118c g       \.text	0+ 0x04 bar_mixwithout
+0+115c g       \.text	0+ 0x04 bar
+0+80000 g       \.stack	0+ _stack
+0+1520 g       \.data	0+ dbaz_otherwithout
+0+11f4 g       \.text	0+ 0x04 baz_mixwithout
+0+1160 g       \.text	0+ 0x04 barboth
+0+14b8 g       \.data	0+ dbarboth
+0+1188 g       \.text	0+ 0x04 bar_mixboth2
+0+13c8 g       .*	0+ ___dtors_end
+0+151c g       \.data	0+ dbaz_otherboth2
+0+1500 g       \.data	0+ dbazboth2
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/shdl64.sd b/binutils-2.19/ld/testsuite/ld-sh/sh64/shdl64.sd
new file mode 100644
index 0000000..abe257a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/shdl64.sd
@@ -0,0 +1,87 @@
+.*:     file format .*-sh64
+
+Contents of section \.text:
+ 1000 6ff0fff0 6ff0fff0 cc4031e0 6ff0fff0  .*
+ 1010 cc407280 cc406680 6ff0fff0 cc409680  .*
+ 1020 cc40a280 6ff0fff0 cc40f5e0 6ff0fff0  .*
+ 1030 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0  .*
+ 1040 cc4111e0 6ff0fff0 cc4135e0 6ff0fff0  .*
+ 1050 cc4271e0 cc4275e0 6ff0fff0 cc4265e0  .*
+ 1060 cc4261e0 6ff0fff0 cc423de0 6ff0fff0  .*
+ 1070 cc4215e0 6ff0fff0 cc4591e0 cc45c280  .*
+ 1080 cc45b680 cc45c680 cc45d280 cc4605e0  .*
+ 1090 cc4611e0 cc4625e0 cc4751e0 cc4755e0  .*
+ 10a0 cc4725e0 cc4721e0 cc46dde0 cc46a5e0  .*
+ 10b0 cc4671e0 cc46b280 cc46a680 cc46d680  .*
+ 10c0 cc46e280 cc4735e0 cc4751e0 cc4775e0  .*
+ 10d0 cc48b1e0 cc48b5e0 cc48a5e0 cc48a1e0  .*
+ 10e0 cc487de0 cc4855e0 cc532280 cc531280  .*
+ 10f0 cc532280 cc533280 cc5361e0 cc5371e0  .*
+ 1100 cc5381e0 cc54b1e0 cc54b1e0 cc5481e0  .*
+ 1110 cc5481e0 cc5439e0 cc5401e0 cc541280  .*
+ 1120 cc540280 cc543280 cc544280 cc5491e0  .*
+ 1130 cc54b1e0 cc54d1e0 cc5611e0 cc5611e0  .*
+ 1140 cc5601e0 cc5601e0 cc55d9e0 cc55b1e0  .*
+ 1150 cc40d180 cc519180 cc51b180 6ff0fff0  .*
+ 1160 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0  .*
+ 1170 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0  .*
+ 1180 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0  .*
+ 1190 6ff0fff0 6ff0fff0 cc4671e0 6ff0fff0  .*
+ 11a0 cc46b280 cc46a680 6ff0fff0 cc46d680  .*
+ 11b0 cc46e280 6ff0fff0 cc4731e0 6ff0fff0  .*
+ 11c0 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0  .*
+ 11d0 cc4751e0 6ff0fff0 cc4775e0 6ff0fff0  .*
+ 11e0 cc48b1e0 cc48b5e0 6ff0fff0 cc48a5e0  .*
+ 11f0 cc48a1e0 6ff0fff0 cc487de0 6ff0fff0  .*
+ 1200 cc4855e0                             .*
+Contents of section \.rodata:
+ 1204 00001030 00001058 00001049 0000104d  .*
+ 1214 0000105c 00001039 00001041 00001074  .*
+ 1224 000011dc 000011f1 00001151 00001148  .*
+ 1234 00001065 00001170 00001198 00001189  .*
+ 1244 0000118d 0000119c 00001179 00001181  .*
+ 1254 000011b0 00001314 00001329 00001281  .*
+ 1264 00001278 0000118d 000011c0 000011e8  .*
+ 1274 000011d9 000011dd 000011ec 000011c9  .*
+ 1284 000011d1 00001204 0000136c 00001381  .*
+ 1294 000012e1 000012d8 000011f5 000013f4  .*
+ 12a4 0000141c 0000140c 00001410 00001420  .*
+ 12b4 000013fc 00001404 00001438 000015a0  .*
+ 12c4 000015b4 00001514 0000150c 00001428  .*
+ 12d4 00001058 00001084 0000108d 000011c0  .*
+ 12e4 000011e8 000011d9 000011dd 000011ec  .*
+ 12f4 000011c9 000011d1 00001204 0000136c  .*
+ 1304 00001381 000012e1 000012d8 000011f5  .*
+ 1314 00001518 00001540 00001530 00001534  .*
+ 1324 00001544 00001520 00001528 0000155c  .*
+ 1334 000016c4 000016d8 00001638 00001630  .*
+ 1344 0000154c                             .*
+Contents of section \.data:
+ 13c8 00000000 000013d0 00000000 000013e0  .*
+ 13d8 000013dc 00000000 000013e8 000013ec  .*
+ 13e8 00000000 00001400 00000000 00000000  .*
+ 13f8 00000000 00000000 00000000 00001408  .*
+ 1408 00000000 00001410 00000000 00001460  .*
+ 1418 00001460 00000000 0000145c 0000145c  .*
+ 1428 00000000 00001452 00000000 00001448  .*
+ 1438 000014bc 000014c8 000014f0 000014e0  .*
+ 1448 000014e4 000014f4 000014d0 000014d8  .*
+ 1458 00001508 0000166c 00001680 000015d8  .*
+ 1468 000015d0 000014e4 000014f4 00001518  .*
+ 1478 00001540 00001530 00001534 00001544  .*
+ 1488 00001520 00001528 0000155c 000016c4  .*
+ 1498 000016d8 00001638 00001630 0000154c  .*
+ 14a8 00001414 00001458 00001484 00000000  .*
+ 14b8 00000000 00000000 00000000 00000000  .*
+ 14c8 00000000 00000000 00000000 00000000  .*
+ 14d8 00000000 00000000 00000000 00000000  .*
+ 14e8 00000000 00000000 000014f4 00000000  .*
+ 14f8 00001504 00001500 00000000 0000150c  .*
+ 1508 00001510 00000000 00001524 00000000  .*
+ 1518 00000000 00000000 00000000 00000000  .*
+ 1528 0000152c 00000000 00001534 00000000  .*
+ 1538 00001584 00001584 00000000 00001580  .*
+ 1548 00001580 00000000 00001576 00000000  .*
+ 1558 0000156c                             .*
+Contents of section \.stack:
+ 80000 deaddead                            .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/shdl64.xd b/binutils-2.19/ld/testsuite/ld-sh/sh64/shdl64.xd
new file mode 100644
index 0000000..142ca96
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/shdl64.xd
@@ -0,0 +1,123 @@
+.*:     file format .*-sh64
+.*
+architecture: sh5, flags 0x0+112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x0+1001
+
+Program Header:
+    LOAD off    0x0+100 vaddr 0x0+1000 paddr 0x0+1000 align 2\*\*7
+         filesz 0x0+348 memsz 0x0+348 flags r-x
+    LOAD off    0x0+448 vaddr 0x0+13c8 paddr 0x0+13c8 align 2\*\*7
+         filesz 0x0+194 memsz 0x0+194 flags rw-
+    LOAD off    0x0+600 vaddr 0x0+80000 paddr 0x0+80000 align 2\*\*7
+         filesz 0x0+4 memsz 0x0+4 flags rw-
+
+Sections:
+Idx Name          Size      VMA               LMA               File off  Algn
+  0 \.text         0+204  0+1000  0+1000  0+100  2\*\*0
+                  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 \.rodata       0+144  0+1204  0+1204  0+304  2\*\*2
+                  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  2 \.data         0+194  0+13c8  0+13c8  0+448  2\*\*2
+                  CONTENTS, ALLOC, LOAD, DATA
+  3 \.stack        0+4  0+80000  0+80000  0+600  2\*\*0
+                  CONTENTS, ALLOC, LOAD, DATA
+SYMBOL TABLE:
+0+1000 l    d  \.text	0+ (|\.text)
+0+1204 l    d  \.rodata	0+ (|\.rodata)
+0+13c8 l    d  \.data	0+ (|\.data)
+0+80000 l    d  \.stack	0+ (|\.stack)
+0+1150 l       \.text	0+ 0x04 part2
+0+13f8 g       \.data	0+ dfoo_otherboth2
+0+1178 g       \.text	0+ 0x04 bar_otherwithout
+0+11b4 g       \.text	0+ 0x04 bazwithout
+0+1428 g       \.data	0+ dfoo_mixwithout
+0+1554 g       \.data	0+ dbaz_mixwithout2
+0+11bc g       \.text	0+ 0x04 baz_other
+0+11cc g       \.text	0+ 0x04 baz_mix
+0+11c0 g       \.text	0+ 0x04 baz_otherboth
+0+13e8 g       \.data	0+ dfoowithout
+0+14b4 g       \.data	0+ dbar
+0+106c g       \.text	0+ 0x04 foo_mixwithout2
+0+11a8 g       \.text	0+ 0x04 bazboth2
+0+13fc g       \.data	0+ dfoo_otherwithout
+0+11c4 g       \.text	0+ 0x04 baz_otherboth2
+0+1174 g       \.text	0+ 0x04 bar_otherboth2
+0+1194 g       \.text	0+ 0x04 baz
+0+13c8 g       \.data	0+ dfoo
+0+14e8 g       \.data	0+ dbar_mixwithout2
+0+13dc g       \.data	0+ dfooboth2
+0+1408 g       \.data	0+ dfoo_mix2
+0+154c g       \.data	0+ dbaz_mixwithout
+0+1044 g       \.text	0+ 0x04 foo_mix2
+0+1018 g       \.text	0+ 0x04 fooboth2
+0+14cc g       \.data	0+ dbar_otherboth2
+0+117c g       \.text	0+ 0x04 bar_mix
+0+14d0 g       \.data	0+ dbar_otherwithout
+0+11dc g       \.text	0+ 0x04 baz_mixboth
+0+14c8 g       \.data	0+ dbar_otherboth
+0+150c g       \.data	0+ dbazwithout
+0+152c g       \.data	0+ dbaz_mix2
+0+1184 g       \.text	0+ 0x04 bar_mixboth
+0+13f4 g       \.data	0+ dfoo_otherboth
+0+14dc g       \.data	0+ dbar_mixboth
+0+1024 g       \.text	0+ 0x04 foowithout
+0+14e4 g       \.data	0+ dbar_mixwithout
+0+11fc g       \.text	0+ 0x04 baz_mixwithout2
+0+1030 g       \.text	0+ 0x04 foo_otherboth
+0+1540 g       \.data	0+ dbaz_mixboth2
+0+104c g       \.text	0+ 0x04 foo_mixboth
+0+1534 g       \.data	0+ dbaz_mixboth
+0+103c g       \.text	0+ 0x04 foo_mix
+0+1518 g       \.data	0+ dbaz_otherboth
+0+14e0 g       \.data	0+ dbar_mixboth2
+0+14ec g       \.data	0+ dbaz
+0+1524 g       \.data	0+ dbaz_mix
+0+13c8 g       .*	0+ ___dtors
+0+141c g       \.data	0+ dfoo_mixboth2
+0+119c g       \.text	0+ 0x04 bazboth
+0+13f0 g       \.data	0+ dfoo_other
+0+11e8 g       \.text	0+ 0x04 baz_mixboth2
+0+1514 g       \.data	0+ dbaz_other
+0+1164 g       \.text	0+ 0x04 barboth2
+0+1168 g       \.text	0+ 0x04 barwithout
+0+14d8 g       \.data	0+ dbar_mix2
+0+1560 g       \*ABS\*	0+ __bss_start
+0+1410 g       \.data	0+ dfoo_mixboth
+0+14c4 g       \.data	0+ dbar_other
+0+1180 g       \.text	0+ 0x04 bar_mix2
+0+14f4 g       \.data	0+ dbazboth
+0+1038 g       \.text	0+ 0x04 foo_otherwithout
+0+1190 g       \.text	0+ 0x04 bar_mixwithout2
+0+13c8 g       .*	0+ ___ctors_end
+0+1064 g       \.text	0+ 0x04 foo_mixwithout
+0+116c g       \.text	0+ 0x04 bar_other
+0+13d0 g       \.data	0+ dfooboth
+0+1034 g       \.text	0+ 0x04 foo_otherboth2
+0+1400 g       \.data	0+ dfoo_mix
+0+13c8 g       .*	0+ ___ctors
+0+14d4 g       \.data	0+ dbar_mix
+0+100c g       \.text	0+ 0x04 fooboth
+0+1170 g       \.text	0+ 0x04 bar_otherboth
+0+14c0 g       \.data	0+ dbarwithout
+0+1004 g       \.text	0+ 0x04 foo
+0+102c g       \.text	0+ 0x04 foo_other
+0+1560 g       \*ABS\*	0+ _edata
+0+1560 g       \*ABS\*	0+ _end
+0+1430 g       \.data	0+ dfoo_mixwithout2
+0+1058 g       \.text	0+ 0x04 foo_mixboth2
+0+11d4 g       \.text	0+ 0x04 baz_mix2
+0+11c8 g       \.text	0+ 0x04 baz_otherwithout
+0+1000 g       \.text	0+ 0x04 start
+0+14bc g       \.data	0+ dbarboth2
+0+118c g       \.text	0+ 0x04 bar_mixwithout
+0+115c g       \.text	0+ 0x04 bar
+0+80000 g       \.stack	0+ _stack
+0+1520 g       \.data	0+ dbaz_otherwithout
+0+11f4 g       \.text	0+ 0x04 baz_mixwithout
+0+1160 g       \.text	0+ 0x04 barboth
+0+14b8 g       \.data	0+ dbarboth
+0+1188 g       \.text	0+ 0x04 bar_mixboth2
+0+13c8 g       .*	0+ ___dtors_end
+0+151c g       \.data	0+ dbaz_otherboth2
+0+1500 g       \.data	0+ dbazboth2
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/shmix-1.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/shmix-1.s
new file mode 100644
index 0000000..e078ac2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/shmix-1.s
@@ -0,0 +1,33 @@
+! Check mixed-mode objects; different sections holding different ISA:s.
+	.mode SHcompact
+	.text
+	.global start
+start:
+	bt forw
+	mova start2,r0
+start2:
+	nop
+	nop
+forw:
+	nop
+	.align 2
+	.long $
+	.long start2
+	.long mediacode2
+
+	.data
+	.long $
+	.long start2
+	.long mediacode2
+
+	.section .text.media,"ax"
+	.mode SHmedia
+	.align 2
+mediacode:
+	ptb forw,tr4
+	pt start2,tr5
+mediacode2:
+	movi start2,r54
+	movi mediacode2,r45
+	pta mediacode2,tr7
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/shmix-2.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/shmix-2.s
new file mode 100644
index 0000000..2ea7344
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/shmix-2.s
@@ -0,0 +1,28 @@
+! A SHmedia object, that we will link to a SHcompact object.
+! We will be using .text for the SHmedia code and .text.compact for the
+! SHcompact code, so we don't get two ISA in the same section.
+	.text
+	.mode SHmedia
+
+	.global start
+	.global medialabel1
+	.global medialabel2
+	.global medialabel3
+start:
+	movi compactlabel1,r14
+	movi compactlabel4,r14
+medialabel1:
+	pt  compactlabel2,tr6
+medialabel2:
+	nop
+
+	.section .rodata
+	.long compactlabel3
+medialabel3:
+	.long compactlabel5
+
+	.data
+	.global medialabel4
+	.long 0
+medialabel4:
+	.long compactlabel2
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/shmix-3.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/shmix-3.s
new file mode 100644
index 0000000..42d1212
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/shmix-3.s
@@ -0,0 +1,32 @@
+! A SHcompact object, that we will link to a SHmedia object.
+! We will be using .text for the SHmedia code and .text.compact for the
+! SHcompact code, so we don't get two ISA in the same section.
+	.section .text.compact,"ax"
+	.mode SHcompact
+	.global compactlabel1
+	.global compactlabel2
+	.global compactlabel3
+	.global compactlabel4
+	.global compactlabel5
+locallabel:
+	nop
+compactlabel1:
+	mova compactlabel2,r0
+compactlabel2:
+	mova compactlabel3,r0
+	nop
+compactlabel3:
+	nop
+	.align 2
+	.long medialabel1
+	.long medialabel4
+
+	.section .rodata
+	.long medialabel2
+compactlabel4:
+	.long medialabel3
+
+	.data
+	.long 0
+compactlabel5:
+	.long medialabel4
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/stobin-0-dso.d b/binutils-2.19/ld/testsuite/ld-sh/sh64/stobin-0-dso.d
new file mode 100644
index 0000000..405c05a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/stobin-0-dso.d
@@ -0,0 +1,9 @@
+#source: stolib.s
+#as: --abi=32 --isa=SHmedia
+#ld: -shared -mshelf32
+#objdump: -drj.text
+#target: sh64-*-elf
+
+.*: +file format elf32-sh64.*
+
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/stobin-1.d b/binutils-2.19/ld/testsuite/ld-sh/sh64/stobin-1.d
new file mode 100644
index 0000000..e0f8b27
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/stobin-1.d
@@ -0,0 +1,15 @@
+#source: stobin.s
+#as: --abi=32 --isa=SHmedia
+#ld: -mshelf32 tmpdir/stobin-0-dso.so
+#objdump: -drj.text
+#target: sh64-*-elf
+
+.*: +file format elf32-sh64.*
+
+Disassembly of section \.text:
+
+0+[0-9a-f]+ <start>:
+    [0-9a-f]+:	cffffd90 	movi	-1,r25
+    [0-9a-f]+:	cbfee590 	shori	65465,r25	! 0xffffffb9 .*
+    [0-9a-f]+:	6bf56600 	ptrel/l	r25,tr0
+    [0-9a-f]+:	4401fff0 	blink	tr0,r63
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/stobin.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/stobin.s
new file mode 100644
index 0000000..30d3597
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/stobin.s
@@ -0,0 +1,5 @@
+	.text
+	.globl	start
+start:
+	pt	bar, tr0
+	blink	tr0, r63
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sh64/stolib.s b/binutils-2.19/ld/testsuite/ld-sh/sh64/stolib.s
new file mode 100644
index 0000000..587faa6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sh64/stolib.s
@@ -0,0 +1,7 @@
+	.text
+	.globl	bar
+	.type bar,@function
+bar:
+	ptabs	r18, tr0
+	blink	tr0, r63
+	.Lfe_bar: .size bar,.Lfe_bar-X
diff --git a/binutils-2.19/ld/testsuite/ld-sh/shared-1.d b/binutils-2.19/ld/testsuite/ld-sh/shared-1.d
new file mode 100644
index 0000000..940195d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/shared-1.d
@@ -0,0 +1,23 @@
+#source: ldr1.s
+#source: ldr2.s
+#as: -little
+#ld: -shared -EL -z nocombreloc
+#readelf: -r -x4 -x5
+#target: sh*-*-elf
+
+# Make sure relocations against global and local symbols with relative and
+# absolute 32-bit relocs don't come out wrong after ld -r.  Remember that
+# SH uses partial_inplace (sort-of REL within RELA) with related confusion
+# about how, when, where and which addends to use.  A DSO must have the
+# same value in the addend as in the data, so either can be used.
+
+Relocation section '\.rela\.text' at offset 0x[0-9a-f]+ contains 1 entries:
+.*
+0000019c +[0-9a-f]+ R_SH_RELATIVE +000001a0
+
+Hex dump of section '\.rela\.text':
+  0x00000188 9c010000 a5000000 a0010000 .*
+
+Hex dump of section '\.text':
+.*
+  0x00000194 09000900 09000900 a0010000 .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/shared-2.d b/binutils-2.19/ld/testsuite/ld-sh/shared-2.d
new file mode 100644
index 0000000..e65fea4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/shared-2.d
@@ -0,0 +1,20 @@
+#source: textrel1.s
+#source: textrel2.s
+#as: -little
+#ld: -shared -EL
+#readelf: -d
+#target: sh*-*-elf sh*-*-linux* sh*-*-netbsd*
+
+# Make sure that there is no unnecessary DT_TEXTREL entry.
+
+Dynamic section at offset 0x[0-9a-f]+ contains 9 entries:
+  Tag        Type                         Name/Value
+ 0x00000004 \(HASH\)                       0x[0-9a-f]+
+ 0x00000005 \(STRTAB\)                     0x[0-9a-f]+
+ 0x00000006 \(SYMTAB\)                     0x[0-9a-f]+
+ 0x0000000a \(STRSZ\)                      [0-9]+ \(bytes\)
+ 0x0000000b \(SYMENT\)                     16 \(bytes\)
+ 0x00000007 \(RELA\)                       0x[0-9a-f]+
+ 0x00000008 \(RELASZ\)                     12 \(bytes\)
+ 0x00000009 \(RELAENT\)                    12 \(bytes\)
+ 0x00000000 \(NULL\)                       0x0
diff --git a/binutils-2.19/ld/testsuite/ld-sh/start.s b/binutils-2.19/ld/testsuite/ld-sh/start.s
new file mode 100644
index 0000000..2af4c79
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/start.s
@@ -0,0 +1,27 @@
+	.section .text
+	.global	start
+start:
+
+	mov.l	stack_k,r15
+
+	! call the mainline	
+L1:	
+	mov.l	main_k,r0
+	.uses	L1
+	jsr	@r0
+	nop
+
+	.align 2
+stack_k:
+	.long	_stack	
+main_k:
+	.long	_main
+
+	.global _trap
+_trap:	
+	trapa #3
+	rts
+	nop
+
+	.section .stack
+_stack:	.long	0xdeaddead
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sub2l-1.d b/binutils-2.19/ld/testsuite/ld-sh/sub2l-1.d
new file mode 100644
index 0000000..40d4e08
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sub2l-1.d
@@ -0,0 +1,23 @@
+#source: sub2l.s
+#as: -little
+#ld: -EL -e 0x1000
+#objdump: -st
+#target: sh*-*-elf
+
+.*/dump:     file format elf32-sh.*
+
+SYMBOL TABLE:
+#...
+0+1000 l       .text	00000000 f
+0+1002 l       .text	00000000 f2
+0+1028 l       .text	00000000 L
+0+1020 g       .text	00000000 ff
+#...
+
+Contents of section \.text:
+ 1000 0b000900 09000900 09000900 09000900  .*
+ 1010 09000900 09000900 09000900 09000900  .*
+ 1020 09000900 09000900 0b000900 d8ffffff  .*
+ 1030 daffffff 02100000 28100000 24100000  .*
+Contents of section \..*:
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sh/sub2l.s b/binutils-2.19/ld/testsuite/ld-sh/sub2l.s
new file mode 100644
index 0000000..1a077d0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/sub2l.s
@@ -0,0 +1,26 @@
+! "The subtraction of two symbols".
+ .little
+ .text
+ .align 5
+f:
+ rts
+f2:
+ nop
+
+ .section .text.foo,"ax",@progbits
+ .align 5
+ .global ff
+ff:
+ nop
+ nop
+ nop
+ nop
+L:
+ rts
+ nop
+ .align 2
+ .long f-L
+ .long f2-L
+ .long f2
+ .long L
+ .long ff+4
diff --git a/binutils-2.19/ld/testsuite/ld-sh/textrel1.s b/binutils-2.19/ld/testsuite/ld-sh/textrel1.s
new file mode 100644
index 0000000..eda4804
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/textrel1.s
@@ -0,0 +1,11 @@
+	.text
+	.align 5
+	.globl	f
+f:
+	mov.l	.L1,r0
+	rts
+	nop
+	.align 2
+.L1:	.long	g - f
+	.long	foo@GOT
+
diff --git a/binutils-2.19/ld/testsuite/ld-sh/textrel2.s b/binutils-2.19/ld/testsuite/ld-sh/textrel2.s
new file mode 100644
index 0000000..1846a6b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/textrel2.s
@@ -0,0 +1,7 @@
+	.text
+	.align 5
+	.globl	g 
+	.hidden	g
+g:
+	rts
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlsbin-0-dso.d b/binutils-2.19/ld/testsuite/ld-sh/tlsbin-0-dso.d
new file mode 100644
index 0000000..dc3eaa6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlsbin-0-dso.d
@@ -0,0 +1,9 @@
+#source: tlslib.s
+#as: -little
+#ld: -shared -EL
+#objdump: -drj.text
+#target: sh*-*-linux* sh*-*-netbsd*
+
+.*: +file format elf32-sh.*
+
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlsbin-1.d b/binutils-2.19/ld/testsuite/ld-sh/tlsbin-1.d
new file mode 100644
index 0000000..9f5a086
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlsbin-1.d
@@ -0,0 +1,308 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: -little
+#ld: -EL tmpdir/tlsbin-0-dso.so
+#objdump: -drj.text
+#target: sh*-*-linux* sh*-*-netbsd*
+
+.*: +file format elf32-sh.*
+
+Disassembly of section \.text:
+
+0+401000 <fn2>:
+  401000:	c6 2f       	mov\.l	r12,@-r15
+  401002:	e6 2f       	mov\.l	r14,@-r15
+  401004:	22 4f       	sts\.l	pr,@-r15
+  401006:	5f c7       	mova	401184 <fn2\+0x184>,r0
+  401008:	5e dc       	mov\.l	401184 <fn2\+0x184>,r12	! [0-9a-f]+
+  40100a:	0c 3c       	add	r0,r12
+  40100c:	f3 6e       	mov	r15,r14
+  40100e:	09 00       	nop	
+  401010:	09 00       	nop	
+  401012:	09 00       	nop	
+  401014:	09 00       	nop	
+  401016:	04 d0       	mov\.l	401028 <fn2\+0x28>,r0	! 1c .*
+  401018:	12 04       	stc	gbr,r4
+  40101a:	ce 00       	mov\.l	@\(r0,r12\),r0
+  40101c:	4c 30       	add	r4,r0
+  40101e:	09 00       	nop	
+  401020:	09 00       	nop	
+  401022:	05 a0       	bra	401030 <fn2\+0x30>
+  401024:	09 00       	nop	
+  401026:	09 00       	nop	
+  401028:	1c 00       	.*[ 	]*.*
+  40102a:	00 00       	.*[ 	]*.*
+  40102c:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  40102e:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  401030:	09 00       	nop	
+  401032:	09 00       	nop	
+  401034:	09 00       	nop	
+  401036:	09 00       	nop	
+  401038:	03 d0       	mov\.l	401048 <fn2\+0x48>,r0	! 14 .*
+  40103a:	12 04       	stc	gbr,r4
+  40103c:	ce 00       	mov\.l	@\(r0,r12\),r0
+  40103e:	4c 30       	add	r4,r0
+  401040:	09 00       	nop	
+  401042:	09 00       	nop	
+  401044:	04 a0       	bra	401050 <fn2\+0x50>
+  401046:	09 00       	nop	
+  401048:	14 00       	.*[ 	]*.*
+  40104a:	00 00       	.*[ 	]*.*
+  40104c:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  40104e:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  401050:	09 00       	nop	
+  401052:	09 00       	nop	
+  401054:	09 00       	nop	
+  401056:	09 00       	nop	
+  401058:	03 d4       	mov\.l	401068 <fn2\+0x68>,r4	! 8 .*
+  40105a:	12 00       	stc	gbr,r0
+  40105c:	4c 30       	add	r4,r0
+  40105e:	09 00       	nop	
+  401060:	09 00       	nop	
+  401062:	09 00       	nop	
+  401064:	04 a0       	bra	401070 <fn2\+0x70>
+  401066:	09 00       	nop	
+  401068:	08 00       	.*[ 	]*.*
+  40106a:	00 00       	.*[ 	]*.*
+  40106c:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  40106e:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  401070:	09 00       	nop	
+  401072:	09 00       	nop	
+  401074:	09 00       	nop	
+  401076:	09 00       	nop	
+  401078:	03 d4       	mov\.l	401088 <fn2\+0x88>,r4	! 10 .*
+  40107a:	12 00       	stc	gbr,r0
+  40107c:	4c 30       	add	r4,r0
+  40107e:	09 00       	nop	
+  401080:	09 00       	nop	
+  401082:	09 00       	nop	
+  401084:	04 a0       	bra	401090 <fn2\+0x90>
+  401086:	09 00       	nop	
+  401088:	10 00       	.*[ 	]*.*
+  40108a:	00 00       	.*[ 	]*.*
+  40108c:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  40108e:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  401090:	09 00       	nop	
+  401092:	09 00       	nop	
+  401094:	09 00       	nop	
+  401096:	09 00       	nop	
+  401098:	03 d4       	mov\.l	4010a8 <fn2\+0xa8>,r4	! 18 .*
+  40109a:	12 00       	stc	gbr,r0
+  40109c:	4c 30       	add	r4,r0
+  40109e:	09 00       	nop	
+  4010a0:	09 00       	nop	
+  4010a2:	09 00       	nop	
+  4010a4:	04 a0       	bra	4010b0 <fn2\+0xb0>
+  4010a6:	09 00       	nop	
+  4010a8:	18 00       	.*[ 	]*.*
+  4010aa:	00 00       	.*[ 	]*.*
+  4010ac:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  4010ae:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  4010b0:	09 00       	nop	
+  4010b2:	09 00       	nop	
+  4010b4:	09 00       	nop	
+  4010b6:	09 00       	nop	
+  4010b8:	12 00       	stc	gbr,r0
+  4010ba:	09 00       	nop	
+  4010bc:	09 00       	nop	
+  4010be:	09 00       	nop	
+  4010c0:	09 00       	nop	
+  4010c2:	09 00       	nop	
+  4010c4:	04 a0       	bra	4010d0 <fn2\+0xd0>
+  4010c6:	09 00       	nop	
+  4010c8:	00 00       	.*[ 	]*.*
+  4010ca:	00 00       	.*[ 	]*.*
+  4010cc:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  4010ce:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  4010d0:	09 00       	nop	
+  4010d2:	09 00       	nop	
+  4010d4:	2c d1       	mov\.l	401188 <fn2\+0x188>,r1	! 10 .*
+  4010d6:	0c 31       	add	r0,r1
+  4010d8:	09 00       	nop	
+  4010da:	09 00       	nop	
+  4010dc:	2b d2       	mov\.l	40118c <fn2\+0x18c>,r2	! 14 .*
+  4010de:	0c 32       	add	r0,r2
+  4010e0:	09 00       	nop	
+  4010e2:	09 00       	nop	
+  4010e4:	09 00       	nop	
+  4010e6:	09 00       	nop	
+  4010e8:	12 00       	stc	gbr,r0
+  4010ea:	09 00       	nop	
+  4010ec:	09 00       	nop	
+  4010ee:	09 00       	nop	
+  4010f0:	09 00       	nop	
+  4010f2:	09 00       	nop	
+  4010f4:	04 a0       	bra	401100 <fn2\+0x100>
+  4010f6:	09 00       	nop	
+  4010f8:	00 00       	.*[ 	]*.*
+  4010fa:	00 00       	.*[ 	]*.*
+  4010fc:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  4010fe:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  401100:	09 00       	nop	
+  401102:	09 00       	nop	
+  401104:	22 d1       	mov\.l	401190 <fn2\+0x190>,r1	! 18 .*
+  401106:	0c 31       	add	r0,r1
+  401108:	09 00       	nop	
+  40110a:	09 00       	nop	
+  40110c:	21 d2       	mov\.l	401194 <fn2\+0x194>,r2	! 1c .*
+  40110e:	0c 32       	add	r0,r2
+  401110:	09 00       	nop	
+  401112:	09 00       	nop	
+  401114:	09 00       	nop	
+  401116:	09 00       	nop	
+  401118:	02 d0       	mov\.l	401124 <fn2\+0x124>,r0	! 14 .*
+  40111a:	12 01       	stc	gbr,r1
+  40111c:	ce 00       	mov\.l	@\(r0,r12\),r0
+  40111e:	03 a0       	bra	401128 <fn2\+0x128>
+  401120:	0c 31       	add	r0,r1
+  401122:	09 00       	nop	
+  401124:	14 00       	.*[ 	]*.*
+  401126:	00 00       	.*[ 	]*.*
+  401128:	09 00       	nop	
+  40112a:	09 00       	nop	
+  40112c:	09 00       	nop	
+  40112e:	09 00       	nop	
+  401130:	02 d0       	mov\.l	40113c <fn2\+0x13c>,r0	! 18 .*
+  401132:	12 01       	stc	gbr,r1
+  401134:	ce 00       	mov\.l	@\(r0,r12\),r0
+  401136:	03 a0       	bra	401140 <fn2\+0x140>
+  401138:	1c 30       	add	r1,r0
+  40113a:	09 00       	nop	
+  40113c:	18 00       	.*[ 	]*.*
+  40113e:	00 00       	.*[ 	]*.*
+  401140:	09 00       	nop	
+  401142:	09 00       	nop	
+  401144:	09 00       	nop	
+  401146:	09 00       	nop	
+  401148:	02 d0       	mov\.l	401154 <fn2\+0x154>,r0	! 8 .*
+  40114a:	12 01       	stc	gbr,r1
+  40114c:	09 00       	nop	
+  40114e:	03 a0       	bra	401158 <fn2\+0x158>
+  401150:	0c 31       	add	r0,r1
+  401152:	09 00       	nop	
+  401154:	08 00       	.*[ 	]*.*
+  401156:	00 00       	.*[ 	]*.*
+  401158:	09 00       	nop	
+  40115a:	09 00       	nop	
+  40115c:	09 00       	nop	
+  40115e:	09 00       	nop	
+  401160:	02 d0       	mov\.l	40116c <fn2\+0x16c>,r0	! 18 .*
+  401162:	12 01       	stc	gbr,r1
+  401164:	09 00       	nop	
+  401166:	03 a0       	bra	401170 <fn2\+0x170>
+  401168:	0c 31       	add	r0,r1
+  40116a:	09 00       	nop	
+  40116c:	18 00       	.*[ 	]*.*
+  40116e:	00 00       	.*[ 	]*.*
+  401170:	09 00       	nop	
+  401172:	09 00       	nop	
+  401174:	09 00       	nop	
+  401176:	09 00       	nop	
+  401178:	e3 6f       	mov	r14,r15
+  40117a:	26 4f       	lds\.l	@r15\+,pr
+  40117c:	f6 6e       	mov\.l	@r15\+,r14
+  40117e:	0b 00       	rts	
+  401180:	f6 6c       	mov\.l	@r15\+,r12
+  401182:	09 00       	nop	
+  401184:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  401186:	01 00       	.*[ 	]*.*
+  401188:	10 00       	.*[ 	]*.*
+  40118a:	00 00       	.*[ 	]*.*
+  40118c:	14 00       	.*[ 	]*.*
+  40118e:	00 00       	.*[ 	]*.*
+  401190:	18 00       	.*[ 	]*.*
+  401192:	00 00       	.*[ 	]*.*
+  401194:	1c 00       	.*[ 	]*.*
+	\.\.\.
+
+00402000 <_start>:
+  402000:	c6 2f       	mov\.l	r12,@-r15
+  402002:	e6 2f       	mov\.l	r14,@-r15
+  402004:	f3 6e       	mov	r15,r14
+  402006:	27 c7       	mova	4020a4 <_start\+0xa4>,r0
+  402008:	26 dc       	mov\.l	4020a4 <_start\+0xa4>,r12	! [0-9a-f]+
+  40200a:	0c 3c       	add	r0,r12
+  40200c:	09 00       	nop	
+  40200e:	09 00       	nop	
+  402010:	09 00       	nop	
+  402012:	09 00       	nop	
+  402014:	02 d0       	mov\.l	402020 <_start\+0x20>,r0	! 10 .*
+  402016:	12 01       	stc	gbr,r1
+  402018:	ce 00       	mov\.l	@\(r0,r12\),r0
+  40201a:	03 a0       	bra	402024 <_start\+0x24>
+  40201c:	0c 31       	add	r0,r1
+  40201e:	09 00       	nop	
+  402020:	10 00       	.*[ 	]*.*
+  402022:	00 00       	.*[ 	]*.*
+  402024:	09 00       	nop	
+  402026:	09 00       	nop	
+  402028:	09 00       	nop	
+  40202a:	09 00       	nop	
+  40202c:	02 d0       	mov\.l	402038 <_start\+0x38>,r0	! 20 .*
+  40202e:	12 01       	stc	gbr,r1
+  402030:	09 00       	nop	
+  402032:	03 a0       	bra	40203c <_start\+0x3c>
+  402034:	0c 31       	add	r0,r1
+  402036:	09 00       	nop	
+  402038:	20 00       	.*[ 	]*.*
+  40203a:	00 00       	.*[ 	]*.*
+  40203c:	09 00       	nop	
+  40203e:	09 00       	nop	
+  402040:	09 00       	nop	
+  402042:	09 00       	nop	
+  402044:	02 d0       	mov\.l	402050 <_start\+0x50>,r0	! 2c
+  402046:	12 01       	stc	gbr,r1
+  402048:	09 00       	nop	
+  40204a:	03 a0       	bra	402054 <_start\+0x54>
+  40204c:	0c 31       	add	r0,r1
+  40204e:	09 00       	nop	
+  402050:	2c 00       	.*[ 	]*.*
+  402052:	00 00       	.*[ 	]*.*
+  402054:	09 00       	nop	
+  402056:	09 00       	nop	
+  402058:	09 00       	nop	
+  40205a:	09 00       	nop	
+  40205c:	02 d0       	mov\.l	402068 <_start\+0x68>,r0	! 1c .*
+  40205e:	12 01       	stc	gbr,r1
+  402060:	09 00       	nop	
+  402062:	03 a0       	bra	40206c <_start\+0x6c>
+  402064:	0c 31       	add	r0,r1
+  402066:	09 00       	nop	
+  402068:	1c 00       	.*[ 	]*.*
+  40206a:	00 00       	.*[ 	]*.*
+  40206c:	09 00       	nop	
+  40206e:	09 00       	nop	
+  402070:	09 00       	nop	
+  402072:	09 00       	nop	
+  402074:	12 01       	stc	gbr,r1
+  402076:	0c d0       	mov\.l	4020a8 <_start\+0xa8>,r0	! 8 .*
+  402078:	1c 30       	add	r1,r0
+  40207a:	09 00       	nop	
+  40207c:	09 00       	nop	
+  40207e:	09 00       	nop	
+  402080:	09 00       	nop	
+  402082:	12 01       	stc	gbr,r1
+  402084:	09 d0       	mov\.l	4020ac <_start\+0xac>,r0	! 28
+  402086:	1c 30       	add	r1,r0
+  402088:	09 00       	nop	
+  40208a:	09 00       	nop	
+  40208c:	09 00       	nop	
+  40208e:	09 00       	nop	
+  402090:	12 01       	stc	gbr,r1
+  402092:	07 d0       	mov\.l	4020b0 <_start\+0xb0>,r0	! 18 .*
+  402094:	1c 30       	add	r1,r0
+  402096:	09 00       	nop	
+  402098:	09 00       	nop	
+  40209a:	09 00       	nop	
+  40209c:	09 00       	nop	
+  40209e:	e3 6f       	mov	r14,r15
+  4020a0:	0b 00       	rts	
+  4020a2:	f6 6e       	mov\.l	@r15\+,r14
+  4020a4:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+  4020a6:	01 00       	.*[ 	]*.*
+  4020a8:	08 00       	.*[ 	]*.*
+  4020aa:	00 00       	.*[ 	]*.*
+  4020ac:	28 00       	.*[ 	]*.*
+  4020ae:	00 00       	.*[ 	]*.*
+  4020b0:	18 00       	.*[ 	]*.*
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlsbin-2.d b/binutils-2.19/ld/testsuite/ld-sh/tlsbin-2.d
new file mode 100644
index 0000000..6118071
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlsbin-2.d
@@ -0,0 +1,79 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: -little
+#ld: -EL tmpdir/tlsbin-0-dso.so
+#readelf: -Ssrl
+#target: sh*-*-linux* sh*-*-netbsd*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+  \[ 0\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+  \[ 1\] \.interp .*
+  \[ 2\] \.hash .*
+  \[ 3\] \.dynsym .*
+  \[ 4\] \.dynstr .*
+  \[ 5\] \.rela\.dyn .*
+  \[ 6\] \.rela\.plt .*
+  \[ 7\] \.plt .*
+  \[ 8\] \.text +PROGBITS .*
+  \[ 9\] \.tdata +PROGBITS .* 0+018 00 WAT  0   0  4
+  \[10\] \.tbss +NOBITS .* 0+010 00 WAT  0   0  1
+#...
+  \[[0-9a-f]+\] \.got +PROGBITS .*
+#...
+  \[[0-9a-f]+\] \.shstrtab .*
+  \[[0-9a-f]+\] \.symtab .*
+  \[[0-9a-f]+\] \.strtab .*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x402000
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  PHDR.*
+  INTERP.*
+.*Requesting program interpreter.*
+  LOAD.*
+  LOAD.*
+  DYNAMIC.*
+  TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+18 0x0+28 R +0x4
+
+ Section to Segment mapping:
+  Segment Sections\.\.\.
+   00 +
+   01 +\.interp *
+   02 +\.interp \.hash \.dynsym \.dynstr \.rela\.dyn \.rela\.plt \.plt \.text *
+   03 +\.tdata \.dynamic \.got *
+   04 +\.dynamic *
+   05 +\.tdata \.tbss *
+
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
+ Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend
+[0-9a-f ]+R_SH_TLS_TPOFF32 +0+ +sG3 \+ 0
+[0-9a-f ]+R_SH_TLS_TPOFF32 +0+ +sG2 \+ 0
+[0-9a-f ]+R_SH_TLS_TPOFF32 +0+ +sG4 \+ 0
+[0-9a-f ]+R_SH_TLS_TPOFF32 +0+ +sG1 \+ 0
+
+Relocation section '\.rela\.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend
+[0-9a-f ]+R_SH_JMP_SLOT[0-9a-f ]+__tls_get_addr \+ [0-9a-f]+
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT  UND *
+.* TLS +GLOBAL DEFAULT  UND sG3
+.* TLS +GLOBAL DEFAULT  UND sG2
+.* TLS +GLOBAL DEFAULT  UND sG4
+.* FUNC +GLOBAL DEFAULT  UND __tls_get_addr
+#...
+.* TLS +GLOBAL DEFAULT  UND sG1
+#...
+
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlsbin-3.d b/binutils-2.19/ld/testsuite/ld-sh/tlsbin-3.d
new file mode 100644
index 0000000..618ae59
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlsbin-3.d
@@ -0,0 +1,12 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: -little
+#ld: -EL tmpdir/tlsbin-0-dso.so
+#objdump: -sj.got
+#target: sh*-*-linux* sh*-*-netbsd*
+
+.*: +file format elf32-sh.*
+
+Contents of section \.got:
+ [0-9a-f]+ [0-9a-f]+ 00000000 00000000 [0-9a-f]+  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlsbin-4.d b/binutils-2.19/ld/testsuite/ld-sh/tlsbin-4.d
new file mode 100644
index 0000000..b1683b8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlsbin-4.d
@@ -0,0 +1,12 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: -little
+#ld: -EL tmpdir/tlsbin-0-dso.so
+#objdump: -sj.tdata
+#target: sh*-*-linux* sh*-*-netbsd*
+
+.*: +file format elf32-sh.*
+
+Contents of section .tdata:
+ [0-9a-f]+ 11000000 12000000 41000000 42000000  .*
+ [0-9a-f]+ 01010000 02010000 +.*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlsbin.s b/binutils-2.19/ld/testsuite/ld-sh/tlsbin.s
new file mode 100644
index 0000000..642eb3d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlsbin.s
@@ -0,0 +1,90 @@
+	.section ".tbss", "awT", @nobits
+	.globl bg1, bg2
+bg1:	.space 4
+bg2:	.space 4
+bl1:	.space 4
+bl2:	.space 4
+	.text
+	.globl	_start
+	.type	_start,@function
+_start:
+	mov.l	r12,@-r15
+	mov.l	r14,@-r15
+	mov	r15,r14
+	! Set up .GOT pointer for non-pic @gottpoff sequences
+	mova	.L3,r0
+	mov.l	.L3,r12
+	add	r0,r12
+	nop;nop;nop;nop
+
+	! @GOTTPOFF IE against global var
+	mov.l	1f,r0
+	stc	gbr,r1
+	mov.l	@(r0,r12),r0
+	bra	2f
+	add	r0,r1
+	.align	2
+1:	.long	sG3@GOTTPOFF
+2:
+	nop;nop;nop;nop
+
+	! @GOTTPOFF IE -> LE against global var defined in exec
+	mov.l	1f,r0
+	stc	gbr,r1
+	mov.l	@(r0,r12),r0
+	bra	2f
+	add	r0,r1
+	.align	2
+1:	.long	bg1@GOTTPOFF
+2:
+	nop;nop;nop;nop
+
+	! @GOTTPOFF IE -> LE against local var
+	mov.l	1f,r0
+	stc	gbr,r1
+	mov.l	@(r0,r12),r0
+	bra	2f
+	add	r0,r1
+	.align	2
+1:	.long	bl2@GOTTPOFF
+2:
+	nop;nop;nop;nop
+
+	! @GOTTPOFF IE -> LE against hidden but not local var
+	mov.l	1f,r0
+	stc	gbr,r1
+	mov.l	@(r0,r12),r0
+	bra	2f
+	add	r0,r1
+	.align	2
+1:	.long	sh2@GOTTPOFF
+2:
+	nop;nop;nop;nop
+
+	! LE @TPOFF, global var defined in exec
+	stc	gbr,r1
+	mov.l	.L4,r0
+	add	r1,r0
+	nop;nop;nop;nop
+
+	! LE @TPOFF, local var
+	stc	gbr,r1
+	mov.l	.L5,r0
+	add	r1,r0
+	nop;nop;nop;nop
+
+	! LE @TPOFF, hidden var defined in exec
+	stc	gbr,r1
+	mov.l	.L6,r0
+	add	r1,r0
+	nop;nop;nop;nop
+
+	mov	r14,r15
+	rts	
+	mov.l	@r15+,r14
+
+	.align	2
+.L3:	.long	_GLOBAL_OFFSET_TABLE_
+.L4:	.long	sg1@TPOFF
+.L5:	.long	bl1@TPOFF
+.L6:	.long	sh1@TPOFF
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlsbinpic.s b/binutils-2.19/ld/testsuite/ld-sh/tlsbinpic.s
new file mode 100644
index 0000000..cb8b361
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlsbinpic.s
@@ -0,0 +1,206 @@
+	! Force .got aligned to 4K, so it very likely gets at 0x413000
+	.data
+	.balign	4096
+	.section ".tdata", "awT", @progbits
+	.globl sg1, sg2
+	.globl sh1, sh2
+	.hidden sh1, sh2
+sg1:	.long 17
+sg2:	.long 18
+sl1:	.long 65
+sl2:	.long 66
+sh1:	.long 257
+sh2:	.long 258
+	! Force .text aligned to 4K, so it very likely gets at 0x401000.
+	.text
+	.balign	4096
+	.globl	fn2
+	.type	fn2,@function
+fn2:
+	mov.l	r12,@-r15
+	mov.l	r14,@-r15
+	sts.l	pr,@-r15
+	mova	.L3,r0
+	mov.l	.L3,r12
+	add	r0,r12
+	mov	r15,r14
+	nop;nop;nop;nop
+
+	! GD -> IE because variable is not defined in executable
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sG1@TLSGD
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop;nop;nop
+
+	! GD -> IE because variable is not defined in executable where
+	!   the variable is referenced through @gottpoff too
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sG2@TLSGD
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop;nop;nop
+
+	! GD -> LE with global variable defined in executable
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sg1@TLSGD
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop;nop;nop
+
+	! GD -> LE with local variable defined in executable
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sl1@TLSGD
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop;nop;nop
+
+	! GD -> LE with hidden variable defined in executable
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sh1@TLSGD
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop;nop;nop
+
+	! LD -> LE with local variable defined in executable
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sl1@TLSLDM
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop
+	mov.l	.L4,r1
+	add	r0,r1
+	nop;nop
+	mov.l	.L5,r2
+	add	r0,r2
+	nop;nop;nop;nop
+
+	! LD -> LE against hidden variables
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sh1@TLSLDM
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop
+	mov.l	.L6,r1
+	add	r0,r1
+	nop;nop
+	mov.l	.L7,r2
+	add	r0,r2
+	nop;nop;nop;nop
+
+	! @GOTTPOFF IE against global var
+	mov.l	1f,r0
+	stc	gbr,r1
+	mov.l	@(r0,r12),r0
+	bra	2f
+	add	r0,r1
+	.align	2
+1:	.long	sG2@GOTTPOFF
+2:
+	nop;nop;nop;nop
+
+	! @GOTTPOFF IE against global var
+	mov.l	1f,r0
+	stc	gbr,r1
+	mov.l	@(r0,r12),r0
+	bra	2f
+	add	r1,r0
+	.align	2
+1:	.long	sG4@GOTTPOFF
+2:
+	nop;nop;nop;nop
+
+	! @GOTTPOFF IE -> LE against global var defined in exec
+	mov.l	1f,r0
+	stc	gbr,r1
+	mov.l	@(r0,r12),r0
+	bra	2f
+	add	r0,r1
+	.align	2
+1:	.long	sg1@GOTTPOFF
+2:
+	nop;nop;nop;nop
+
+	! @GOTTPOFF IE -> LE against hidden var
+	mov.l	1f,r0
+	stc	gbr,r1
+	mov.l	@(r0,r12),r0
+	bra	2f
+	add	r0,r1
+	.align	2
+1:	.long	sh1@GOTTPOFF
+2:
+	nop;nop;nop;nop
+
+	mov	r14,r15
+	lds.l	@r15+,pr
+	mov.l	@r15+,r14
+	rts	
+	mov.l	@r15+,r12
+
+	.align 2
+.L3:	.long	_GLOBAL_OFFSET_TABLE_
+.L4:	.long	sl1@DTPOFF
+.L5:	.long	sl2@DTPOFF
+.L6:	.long	sh1@DTPOFF
+.L7:	.long	sh2@DTPOFF
+	! Fill page with 0.
+	.space	.L8-.
+	.balign	4096
+.L8:
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlslib.s b/binutils-2.19/ld/testsuite/ld-sh/tlslib.s
new file mode 100644
index 0000000..35b6c70
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlslib.s
@@ -0,0 +1,20 @@
+	.section ".tdata", "awT", @progbits
+	.globl sG1, sG2, sG3, sG4, sG5, sG6, sG7, sG8
+sG1:	.long 513
+sG2:	.long 514
+sG3:	.long 515
+sG4:	.long 516
+sG5:	.long 517
+sG6:	.long 518
+sG7:	.long 519
+sG8:	.long 520
+
+	.text
+	.align	1
+	! Dummy.
+	.globl __tls_get_addr
+	.type   __tls_get_addr,@function
+__tls_get_addr:
+	rts
+	nop
+
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlspic-1.d b/binutils-2.19/ld/testsuite/ld-sh/tlspic-1.d
new file mode 100644
index 0000000..6638eda
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlspic-1.d
@@ -0,0 +1,292 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: -little
+#ld: -shared -EL
+#objdump: -drj.text
+#target: sh*-*-linux* sh*-*-netbsd*
+
+.*: +file format elf32-sh.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <fn1>:
+ [0-9a-f]+:	c6 2f       	mov\.l	r12,@-r15
+ [0-9a-f]+:	e6 2f       	mov\.l	r14,@-r15
+ [0-9a-f]+:	22 4f       	sts\.l	pr,@-r15
+ [0-9a-f]+:	83 c7       	mova	[0-9a-f]+ <fn1\+0x214>,r0
+ [0-9a-f]+:	82 dc       	mov\.l	[0-9a-f]+ <fn1\+0x214>,r12	! [0-9a-f]+
+ [0-9a-f]+:	0c 3c       	add	r0,r12
+ [0-9a-f]+:	f3 6e       	mov	r15,r14
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	04 d4       	mov\.l	[0-9a-f]+ <fn1\+0x28>,r4	! 30
+ [0-9a-f]+:	04 c7       	mova	[0-9a-f]+ <fn1\+0x2c>,r0
+ [0-9a-f]+:	04 d1       	mov\.l	[0-9a-f]+ <fn1\+0x2c>,r1	! [0-9a-f]+
+ [0-9a-f]+:	0c 31       	add	r0,r1
+ [0-9a-f]+:	0b 41       	jsr	@r1
+ [0-9a-f]+:	cc 34       	add	r12,r4
+ [0-9a-f]+:	05 a0       	bra	[0-9a-f]+ <fn1\+0x30>
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	30 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	03 d0       	mov\.l	[0-9a-f]+ <fn1\+0x48>,r0	! 38
+ [0-9a-f]+:	12 04       	stc	gbr,r4
+ [0-9a-f]+:	ce 00       	mov\.l	@\(r0,r12\),r0
+ [0-9a-f]+:	4c 30       	add	r4,r0
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	04 a0       	bra	[0-9a-f]+ <fn1\+0x50>
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	38 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	03 d4       	mov\.l	[0-9a-f]+ <fn1\+0x68>,r4	! 10 .*
+ [0-9a-f]+:	04 c7       	mova	[0-9a-f]+ <fn1\+0x6c>,r0
+ [0-9a-f]+:	03 d1       	mov\.l	[0-9a-f]+ <fn1\+0x6c>,r1	! [0-9a-f]+
+ [0-9a-f]+:	0c 31       	add	r0,r1
+ [0-9a-f]+:	0b 41       	jsr	@r1
+ [0-9a-f]+:	cc 34       	add	r12,r4
+ [0-9a-f]+:	04 a0       	bra	[0-9a-f]+ <fn1\+0x70>
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	10 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	03 d0       	mov\.l	[0-9a-f]+ <fn1\+0x88>,r0	! 18 .*
+ [0-9a-f]+:	12 04       	stc	gbr,r4
+ [0-9a-f]+:	ce 00       	mov\.l	@\(r0,r12\),r0
+ [0-9a-f]+:	4c 30       	add	r4,r0
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	04 a0       	bra	[0-9a-f]+ <fn1\+0x90>
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	18 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	03 d4       	mov\.l	[0-9a-f]+ <fn1\+0xa8>,r4	! 3c
+ [0-9a-f]+:	04 c7       	mova	[0-9a-f]+ <fn1\+0xac>,r0
+ [0-9a-f]+:	03 d1       	mov\.l	[0-9a-f]+ <fn1\+0xac>,r1	! [0-9a-f]+
+ [0-9a-f]+:	0c 31       	add	r0,r1
+ [0-9a-f]+:	0b 41       	jsr	@r1
+ [0-9a-f]+:	cc 34       	add	r12,r4
+ [0-9a-f]+:	04 a0       	bra	[0-9a-f]+ <fn1\+0xb0>
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	3c 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	03 d0       	mov\.l	[0-9a-f]+ <fn1\+0xc8>,r0	! 44
+ [0-9a-f]+:	12 04       	stc	gbr,r4
+ [0-9a-f]+:	ce 00       	mov\.l	@\(r0,r12\),r0
+ [0-9a-f]+:	4c 30       	add	r4,r0
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	04 a0       	bra	[0-9a-f]+ <fn1\+0xd0>
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	44 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	03 d4       	mov\.l	[0-9a-f]+ <fn1\+0xe8>,r4	! 24
+ [0-9a-f]+:	04 c7       	mova	[0-9a-f]+ <fn1\+0xec>,r0
+ [0-9a-f]+:	03 d1       	mov\.l	[0-9a-f]+ <fn1\+0xec>,r1	! [0-9a-f]+
+ [0-9a-f]+:	0c 31       	add	r0,r1
+ [0-9a-f]+:	0b 41       	jsr	@r1
+ [0-9a-f]+:	cc 34       	add	r12,r4
+ [0-9a-f]+:	04 a0       	bra	[0-9a-f]+ <fn1\+0xf0>
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	24 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	03 d0       	mov\.l	[0-9a-f]+ <fn1\+0x108>,r0	! 2c
+ [0-9a-f]+:	12 04       	stc	gbr,r4
+ [0-9a-f]+:	ce 00       	mov\.l	@\(r0,r12\),r0
+ [0-9a-f]+:	4c 30       	add	r4,r0
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	04 a0       	bra	[0-9a-f]+ <fn1\+0x110>
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	2c 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	03 d4       	mov\.l	[0-9a-f]+ <fn1\+0x128>,r4	! 1c .*
+ [0-9a-f]+:	04 c7       	mova	[0-9a-f]+ <fn1\+0x12c>,r0
+ [0-9a-f]+:	03 d1       	mov\.l	[0-9a-f]+ <fn1\+0x12c>,r1	! [0-9a-f]+
+ [0-9a-f]+:	0c 31       	add	r0,r1
+ [0-9a-f]+:	0b 41       	jsr	@r1
+ [0-9a-f]+:	cc 34       	add	r12,r4
+ [0-9a-f]+:	04 a0       	bra	[0-9a-f]+ <fn1\+0x130>
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	1c 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	38 d1       	mov\.l	[0-9a-f]+ <fn1\+0x218>,r1	! 8 .*
+ [0-9a-f]+:	0c 31       	add	r0,r1
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	37 d2       	mov\.l	[0-9a-f]+ <fn1\+0x21c>,r2	! c .*
+ [0-9a-f]+:	0c 32       	add	r0,r2
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	03 d4       	.*[ 	]*.*
+ [0-9a-f]+:	04 c7       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	0b 41       	jsr	@r1
+ [0-9a-f]+:	cc 34       	add	r12,r4
+ [0-9a-f]+:	04 a0       	bra	[0-9a-f]+ <fn1\+0x160>
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	1c 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	2e d1       	mov\.l	[0-9a-f]+ <fn1\+0x220>,r1	! 10 .*
+ [0-9a-f]+:	0c 31       	add	r0,r1
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	2d d2       	mov\.l	[0-9a-f]+ <fn1\+0x224>,r2	! 14 .*
+ [0-9a-f]+:	0c 32       	add	r0,r2
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	03 d4       	mov\.l	[0-9a-f]+ <fn1\+0x188>,r4	! 1c .*
+ [0-9a-f]+:	04 c7       	mova	[0-9a-f]+ <fn1\+0x18c>,r0
+ [0-9a-f]+:	03 d1       	mov\.l	[0-9a-f]+ <fn1\+0x18c>,r1	! [0-9a-f]+
+ [0-9a-f]+:	0c 31       	add	r0,r1
+ [0-9a-f]+:	0b 41       	jsr	@r1
+ [0-9a-f]+:	cc 34       	add	r12,r4
+ [0-9a-f]+:	04 a0       	bra	[0-9a-f]+ <fn1\+0x190>
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	1c 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	24 d1       	mov\.l	[0-9a-f]+ <fn1\+0x228>,r1	! 18 .*
+ [0-9a-f]+:	0c 31       	add	r0,r1
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	23 d2       	mov\.l	[0-9a-f]+ <fn1\+0x22c>,r2	! 1c .*
+ [0-9a-f]+:	0c 32       	add	r0,r2
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	02 d0       	mov\.l	[0-9a-f]+ <fn1\+0x1b4>,r0	! 38
+ [0-9a-f]+:	12 01       	stc	gbr,r1
+ [0-9a-f]+:	ce 00       	mov\.l	@\(r0,r12\),r0
+ [0-9a-f]+:	03 a0       	bra	[0-9a-f]+ <fn1\+0x1b8>
+ [0-9a-f]+:	0c 31       	add	r0,r1
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	38 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	02 d0       	mov\.l	[0-9a-f]+ <fn1\+0x1cc>,r0	! 18 .*
+ [0-9a-f]+:	12 01       	stc	gbr,r1
+ [0-9a-f]+:	ce 00       	mov\.l	@\(r0,r12\),r0
+ [0-9a-f]+:	03 a0       	bra	[0-9a-f]+ <fn1\+0x1d0>
+ [0-9a-f]+:	0c 31       	add	r0,r1
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	18 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	02 d0       	mov\.l	[0-9a-f]+ <fn1\+0x1e4>,r0	! 44
+ [0-9a-f]+:	12 01       	stc	gbr,r1
+ [0-9a-f]+:	ce 00       	mov\.l	@\(r0,r12\),r0
+ [0-9a-f]+:	03 a0       	bra	[0-9a-f]+ <fn1\+0x1e8>
+ [0-9a-f]+:	0c 31       	add	r0,r1
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	44 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	02 d0       	mov\.l	[0-9a-f]+ <fn1\+0x1fc>,r0	! 2c
+ [0-9a-f]+:	12 01       	stc	gbr,r1
+ [0-9a-f]+:	ce 00       	mov\.l	@\(r0,r12\),r0
+ [0-9a-f]+:	03 a0       	bra	[0-9a-f]+ <fn1\+0x200>
+ [0-9a-f]+:	0c 31       	add	r0,r1
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	2c 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	e3 6f       	mov	r14,r15
+ [0-9a-f]+:	26 4f       	lds\.l	@r15\+,pr
+ [0-9a-f]+:	f6 6e       	mov\.l	@r15\+,r14
+ [0-9a-f]+:	0b 00       	rts	
+ [0-9a-f]+:	f6 6c       	mov\.l	@r15\+,r12
+ [0-9a-f]+:	09 00       	nop	
+ [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[ 	]*.*
+ [0-9a-f]+:	01 00       	.*[ 	]*.*
+ [0-9a-f]+:	08 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	0c 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	10 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	14 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	18 00       	.*[ 	]*.*
+ [0-9a-f]+:	00 00       	.*[ 	]*.*
+ [0-9a-f]+:	1c 00       	.*[ 	]*.*
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlspic-2.d b/binutils-2.19/ld/testsuite/ld-sh/tlspic-2.d
new file mode 100644
index 0000000..942fb2d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlspic-2.d
@@ -0,0 +1,79 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: -little
+#ld: -shared -EL
+#readelf: -Ssrl
+#target: sh*-*-linux* sh*-*-netbsd*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+  \[ 0\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+  \[ 1\] \.hash .*
+  \[ 2\] \.dynsym .*
+  \[ 3\] \.dynstr .*
+  \[ 4\] \.rela\.dyn .*
+  \[ 5\] \.rela\.plt .*
+  \[ 6\] \.plt .*
+  \[ 7\] \.text +PROGBITS .*
+  \[ 8\] \.tdata +PROGBITS .* 0+18 00 WAT  0   0  4
+  \[ 9\] \.tbss +NOBITS .* 0+08 00 WAT  0   0  1
+#...
+  \[[0-9a-f]+\] \.got +PROGBITS .*
+#...
+  \[[0-9a-f]+\] \.shstrtab .*
+  \[[0-9a-f]+\] \.symtab .*
+  \[[0-9a-f]+\] \.strtab .*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x[0-9a-f]+
+There are 4 program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  LOAD.*
+  LOAD.*
+  DYNAMIC.*
+  TLS .* 0x0+18 0x0+20 R +0x4
+
+ Section to Segment mapping:
+  Segment Sections\.\.\.
+   00 +\.hash \.dynsym \.dynstr \.rela\.dyn \.rela\.plt \.plt \.text *
+   01 +\.tdata \.dynamic \.got *
+   02 +\.dynamic *
+   03 +\.tdata \.tbss *
+
+Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 10 entries:
+ Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend
+[0-9a-f ]+R_SH_TLS_DTPMOD32 +0+00
+[0-9a-f ]+R_SH_TLS_TPOFF32 +0+0c
+[0-9a-f ]+R_SH_TLS_DTPMOD32 +0+00
+[0-9a-f ]+R_SH_TLS_DTPMOD32 +0+00
+[0-9a-f ]+R_SH_TLS_TPOFF32 +0+1c
+[0-9a-f ]+R_SH_TLS_DTPMOD32 +0+00
+[0-9a-f ]+R_SH_TLS_TPOFF32 +0+14
+[0-9a-f ]+R_SH_TLS_DTPMOD32 +0+ +sg1 \+ 0
+[0-9a-f ]+R_SH_TLS_DTPOFF32 +0+ +sg1 \+ 0
+[0-9a-f ]+R_SH_TLS_TPOFF32 +0+04 +sg2 \+ 0
+
+Relocation section '\.rela\.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend
+[0-9a-f ]+R_SH_JMP_SLOT[0-9a-f ]+__tls_get_addr \+ [0-9a-f]+
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT  UND *
+.* NOTYPE  GLOBAL DEFAULT  UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +8 sg1
+#...
+.* FUNC +GLOBAL DEFAULT +7 fn1
+#...
+.* TLS +GLOBAL DEFAULT +8 sg2
+#...
+
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlspic-3.d b/binutils-2.19/ld/testsuite/ld-sh/tlspic-3.d
new file mode 100644
index 0000000..6e79989
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlspic-3.d
@@ -0,0 +1,15 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: -little
+#ld: -shared -EL
+#objdump: -sj.got
+#target: sh*-*-linux* sh*-*-netbsd*
+
+.*: +file format elf32-sh.*
+
+Contents of section \.got:
+ [0-9a-f]+ [0-9a-f]+ 00000000 00000000 [0-9a-f]+  .*
+ [0-9a-f]+ 00000000 08000000 00000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 18000000 00000000  .*
+ [0-9a-f]+ 00000000 00000000 00000000 00000000  .*
+ [0-9a-f]+ 10000000 00000000 +.*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlspic-4.d b/binutils-2.19/ld/testsuite/ld-sh/tlspic-4.d
new file mode 100644
index 0000000..263c5d6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlspic-4.d
@@ -0,0 +1,12 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: -little
+#ld: -shared -EL
+#objdump: -sj.tdata
+#target: sh*-*-linux* sh*-*-netbsd*
+
+.*: +file format elf32-sh.*
+
+Contents of section \.tdata:
+ [0-9a-f]+ 11000000 12000000 41000000 42000000  .*
+ [0-9a-f]+ 01010000 02010000 +.*
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlspic1.s b/binutils-2.19/ld/testsuite/ld-sh/tlspic1.s
new file mode 100644
index 0000000..153709a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlspic1.s
@@ -0,0 +1,267 @@
+	.section ".tdata", "awT", @progbits
+	.globl sg1, sg2
+	.globl sh1, sh2
+	.hidden sh1, sh2
+sg1:	.long 17
+sg2:	.long 18
+sl1:	.long 65
+sl2:	.long 66
+sh1:	.long 257
+sh2:	.long 258
+	.text
+	.align	1
+	.globl	fn1
+	.type	fn1,@function
+fn1:
+	mov.l	r12,@-r15
+	mov.l	r14,@-r15
+	sts.l	pr,@-r15
+	mova	.L3,r0
+	mov.l	.L3,r12
+	add	r0,r12
+	mov	r15,r14
+	nop;nop;nop;nop
+
+	! GD
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sg1@TLSGD
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop;nop;nop
+
+	! GD -> IE because variable is referenced through @GOTTPOFF too
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sg2@TLSGD
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop;nop;nop
+
+	! GD against local variable
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sl1@TLSGD
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop;nop;nop
+
+	! GD -> IE against local variable referenced through @GOTTPOFF too
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sl2@TLSGD
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop;nop;nop
+
+	! GD against hidden and local variable
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sh1@TLSGD
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop;nop;nop
+
+	! GD -> IE against hidden and local variable referenced through
+	! @GOTTPOFF too
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sh2@TLSGD
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop;nop;nop
+
+	! GD against hidden but not local variable
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sH1@TLSGD
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop;nop;nop
+
+	! GD -> IE against hidden but not local variable referenced through
+	! @GOTTPOFF too
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sH2@TLSGD
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop;nop;nop
+
+	! LD
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sl1@TLSLDM
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop
+	mov.l	.L4,r1
+	add	r0,r1
+	nop;nop
+	mov.l	.L5,r2
+	add	r0,r2
+	nop;nop;nop;nop
+
+	! LD against hidden and local variables
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sl1@TLSLDM
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop
+	mov.l	.L6,r1
+	add	r0,r1
+	nop;nop
+	mov.l	.L7,r2
+	add	r0,r2
+	nop;nop;nop;nop
+
+	! LD against hidden but not local variables
+	mov.l	1f,r4
+	mova	2f,r0
+	mov.l	2f,r1
+	add	r0,r1
+	jsr	@r1
+	add	r12,r4
+	bra	3f
+	nop
+	.align	2
+1:	.long	sH1@TLSLDM
+2:	.long	__tls_get_addr@PLT
+3:
+	nop;nop
+	mov.l	.L8,r1
+	add	r0,r1
+	nop;nop
+	mov.l	.L9,r2
+	add	r0,r2
+	nop;nop;nop;nop
+
+	! @GOTTPOFF IE against global var
+	mov.l	1f,r0
+	stc	gbr,r1
+	mov.l	@(r0,r12),r0
+	bra	2f
+	add	r0,r1
+	.align	2
+1:	.long	sg2@GOTTPOFF
+2:
+	nop;nop;nop;nop
+
+	! @GOTTPOFF IE against local var
+	mov.l	1f,r0
+	stc	gbr,r1
+	mov.l	@(r0,r12),r0
+	bra	2f
+	add	r0,r1
+	.align	2
+1:	.long	sl2@GOTTPOFF
+2:
+	nop;nop;nop;nop
+
+	! @GOTTPOFF IE against hidden and local var
+	mov.l	1f,r0
+	stc	gbr,r1
+	mov.l	@(r0,r12),r0
+	bra	2f
+	add	r0,r1
+	.align	2
+1:	.long	sh2@GOTTPOFF
+2:
+	nop;nop;nop;nop
+
+	! @GOTTPOFF IE against hidden but not local var
+	mov.l	1f,r0
+	stc	gbr,r1
+	mov.l	@(r0,r12),r0
+	bra	2f
+	add	r0,r1
+	.align	2
+1:	.long	sH2@GOTTPOFF
+2:
+	nop;nop;nop;nop
+
+	mov	r14,r15
+	lds.l	@r15+,pr
+	mov.l	@r15+,r14
+	rts	
+	mov.l	@r15+,r12
+
+	.align 2
+.L3:	.long	_GLOBAL_OFFSET_TABLE_
+.L4:	.long	sl1@DTPOFF
+.L5:	.long	sl1@DTPOFF + 4
+.L6:	.long	sh1@DTPOFF
+.L7:	.long	sh2@DTPOFF
+.L8:	.long	sH1@DTPOFF
+.L9:	.long	sH2@DTPOFF
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlspic2.s b/binutils-2.19/ld/testsuite/ld-sh/tlspic2.s
new file mode 100644
index 0000000..35319ba
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlspic2.s
@@ -0,0 +1,5 @@
+	.section ".tbss", "awT", @nobits
+	.globl sH1, sH2
+	.hidden sH1, sH2
+sH1:	.space 4
+sH2:	.space 4
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlstpoff-1.d b/binutils-2.19/ld/testsuite/ld-sh/tlstpoff-1.d
new file mode 100644
index 0000000..a678596
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlstpoff-1.d
@@ -0,0 +1,31 @@
+#source: tlstpoff1.s
+#source: tlstpoff2.s
+#as: -little
+#ld: -EL -e foo
+#objdump: -drj.text
+#target: sh*-*-linux* sh*-*-netbsd*
+
+.*: +file format elf32-sh.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <foo>:
+  [0-9a-f]+:	c6 2f       	mov.l	r12,@-r15
+  [0-9a-f]+:	07 c7       	mova	[0-9a-f]+ <foo\+0x20>,r0
+  [0-9a-f]+:	06 dc       	mov.l	[0-9a-f]+ <foo\+0x20>,r12	! [0-9a-f]+
+  [0-9a-f]+:	0c 3c       	add	r0,r12
+  [0-9a-f]+:	02 d0       	mov.l	[0-9a-f]+ <foo\+0x14>,r0	! c
+  [0-9a-f]+:	12 01       	stc	gbr,r1
+  [0-9a-f]+:	09 00       	nop	
+  [0-9a-f]+:	03 a0       	bra	[0-9a-f]+ <foo\+0x18>
+  [0-9a-f]+:	0c 31       	add	r0,r1
+  [0-9a-f]+:	09 00       	nop	
+  [0-9a-f]+:	0c 00       	.*[	]*.*
+  [0-9a-f]+:	00 00       	.*[	]*.*
+  [0-9a-f]+:	12 60       	mov.l	@r1,r0
+  [0-9a-f]+:	0b 00       	rts	
+  [0-9a-f]+:	f6 6c       	mov.l	@r15\+,r12
+  [0-9a-f]+:	09 00       	nop	
+  [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[	]*.*
+  [0-9a-f]+:	[0-9a-f]+ [0-9a-f]+       	.*[	]*.*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlstpoff-2.d b/binutils-2.19/ld/testsuite/ld-sh/tlstpoff-2.d
new file mode 100644
index 0000000..519c6ef
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlstpoff-2.d
@@ -0,0 +1,8 @@
+#source: tlstpoff1.s
+#source: tlstpoff2.s
+#as: -little
+#ld: -EL -e foo
+#readelf: -r
+#target: sh*-*-linux* sh*-*-netbsd*
+
+There are no relocations in this file.
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlstpoff1.s b/binutils-2.19/ld/testsuite/ld-sh/tlstpoff1.s
new file mode 100644
index 0000000..754f3c1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlstpoff1.s
@@ -0,0 +1,23 @@
+	.text
+	.align 5
+	.global	foo
+	.type	foo, @function
+foo:
+	mov.l	r12,@-r15
+	mova	.L1,r0
+	mov.l	.L1,r12
+	add	r0,r12
+	mov.l	1f,r0
+	stc	gbr,r1
+	mov.l	@(r0,r12),r0
+	bra	2f
+	 add	r0,r1
+	.align 2
+1:	.long	x@GOTTPOFF
+2:	
+	mov.l	@r1,r0
+	rts	
+	mov.l	@r15+,r12
+
+	.align 2
+.L1:	.long	_GLOBAL_OFFSET_TABLE_
diff --git a/binutils-2.19/ld/testsuite/ld-sh/tlstpoff2.s b/binutils-2.19/ld/testsuite/ld-sh/tlstpoff2.s
new file mode 100644
index 0000000..6ae9e92
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/tlstpoff2.s
@@ -0,0 +1,26 @@
+	.section .tbss,"awT",@nobits
+	.global	x
+y:	.space	4
+x:	.space	4
+
+	.section barfn,"ax",@progbits
+	.align	1
+	.type	bar, @function
+bar:	
+	mova	.L1,r0
+	mov.l	.L1,r12
+	add	r0,r12
+	mov.l	1f,r0
+	stc	gbr,r1
+	mov.l	@(r0,r12),r0
+	bra	2f
+	add	r0,r1
+	.align	2
+1:	.long	x@GOTTPOFF
+2:
+	mov.l	@r1,r0
+	rts	
+	mov.l	@r15+,r12
+
+	.align 2
+.L1:	.long	_GLOBAL_OFFSET_TABLE_
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks1-le.dd b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-le.dd
new file mode 100644
index 0000000..03c817c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-le.dd
@@ -0,0 +1,73 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+00080800 <_PROCEDURE_LINKAGE_TABLE_>:
+   80800:	01 d1       	mov\.l	80808 <_PROCEDURE_LINKAGE_TABLE_\+0x8>,r1	! 81408
+   80802:	12 61       	mov\.l	@r1,r1
+   80804:	2b 41       	jmp	@r1
+   80806:	09 00       	nop	
+   80808:	08 14 .*
+			80808: R_SH_DIR32	_GLOBAL_OFFSET_TABLE_\+0x8
+   8080a:	08 00 .*
+
+0008080c <_sglobal@plt>:
+   8080c:	01 d0       	mov\.l	80814 <_sglobal@plt\+0x8>,r0	! 8140c
+   8080e:	02 60       	mov\.l	@r0,r0
+   80810:	2b 40       	jmp	@r0
+   80812:	09 00       	nop	
+   80814:	0c 14 .*
+			80814: R_SH_DIR32	_GLOBAL_OFFSET_TABLE_\+0xc
+   80816:	08 00 .*
+   80818:	01 d0       	mov\.l	80820 <_sglobal@plt\+0x14>,r0	! 0
+   8081a:	f1 af       	bra	80800 <_PROCEDURE_LINKAGE_TABLE_>
+   8081c:	09 00       	nop	
+   8081e:	09 00       	nop	
+   80820:	00 00 .*
+	\.\.\.
+
+00080824 <_foo@plt>:
+   80824:	01 d0       	mov\.l	8082c <_foo@plt\+0x8>,r0	! 81410
+   80826:	02 60       	mov\.l	@r0,r0
+   80828:	2b 40       	jmp	@r0
+   8082a:	09 00       	nop	
+   8082c:	10 14 .*
+			8082c: R_SH_DIR32	_GLOBAL_OFFSET_TABLE_\+0x10
+   8082e:	08 00 .*
+   80830:	01 d0       	mov\.l	80838 <_foo@plt\+0x14>,r0	! c
+   80832:	e5 af       	bra	80800 <_PROCEDURE_LINKAGE_TABLE_>
+   80834:	09 00       	nop	
+   80836:	09 00       	nop	
+   80838:	0c 00 .*
+	\.\.\.
+Disassembly of section \.text:
+
+00080c00 <__start>:
+   80c00:	22 4f       	sts\.l	pr,@-r15
+   80c02:	06 d0       	mov\.l	80c1c <__start\+0x1c>,r0	! 80824 <_foo@plt>
+   80c04:	0b 40       	jsr	@r0
+   80c06:	09 00       	nop	
+   80c08:	05 d0       	mov\.l	80c20 <__start\+0x20>,r0	! 8080c <_sglobal@plt>
+   80c0a:	0b 40       	jsr	@r0
+   80c0c:	09 00       	nop	
+   80c0e:	05 d0       	mov\.l	80c24 <__start\+0x24>,r0	! 80c28 <_sexternal>
+   80c10:	0b 40       	jsr	@r0
+   80c12:	09 00       	nop	
+   80c14:	26 4f       	lds\.l	@r15\+,pr
+   80c16:	0b 00       	rts	
+   80c18:	09 00       	nop	
+   80c1a:	09 00       	nop	
+   80c1c:	24 08 .*
+			80c1c: R_SH_DIR32	\.plt\+0x24
+   80c1e:	08 00 .*
+   80c20:	0c 08 .*
+			80c20: R_SH_DIR32	\.plt\+0xc
+   80c22:	08 00 .*
+   80c24:	28 0c .*
+			80c24: R_SH_DIR32	_sexternal
+   80c26:	08 00 .*
+
+00080c28 <_sexternal>:
+   80c28:	0b 00       	rts	
+   80c2a:	09 00       	nop	
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib-le.dd b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib-le.dd
new file mode 100644
index 0000000..6511c16
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib-le.dd
@@ -0,0 +1,76 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+00080800 <_PROCEDURE_LINKAGE_TABLE_>:
+   80800:	01 d0       	mov\.l	80808 <_PROCEDURE_LINKAGE_TABLE_\+0x8>,r0	! c
+   80802:	ce 00       	mov\.l	@\(r0,r12\),r0
+   80804:	2b 40       	jmp	@r0
+   80806:	09 00       	nop	
+   80808:	0c 00 .*
+   8080a:	00 00 .*
+   8080c:	01 d0       	mov\.l	80814 <_PROCEDURE_LINKAGE_TABLE_\+0x14>,r0	! 0
+   8080e:	c2 51       	mov\.l	@\(8,r12\),r1
+   80810:	2b 41       	jmp	@r1
+   80812:	09 00       	nop	
+   80814:	00 00 .*
+	\.\.\.
+
+00080818 <_sexternal@plt>:
+   80818:	01 d0       	mov\.l	80820 <_sexternal@plt\+0x8>,r0	! 10
+   8081a:	ce 00       	mov\.l	@\(r0,r12\),r0
+   8081c:	2b 40       	jmp	@r0
+   8081e:	09 00       	nop	
+   80820:	10 00 .*
+   80822:	00 00 .*
+   80824:	01 d0       	mov\.l	8082c <_sexternal@plt\+0x14>,r0	! c
+   80826:	c2 51       	mov\.l	@\(8,r12\),r1
+   80828:	2b 41       	jmp	@r1
+   8082a:	09 00       	nop	
+   8082c:	0c 00 .*
+	\.\.\.
+Disassembly of section \.text:
+
+00080c00 <_foo>:
+   80c00:	c6 2f       	mov\.l	r12,@-r15
+   80c02:	22 4f       	sts\.l	pr,@-r15
+   80c04:	0a dc       	mov\.l	80c30 <_foo\+0x30>,r12	! 0
+   80c06:	c2 6c       	mov\.l	@r12,r12
+   80c08:	0a d0       	mov\.l	80c34 <_foo\+0x34>,r0	! 0
+   80c0a:	ce 0c       	mov\.l	@\(r0,r12\),r12
+   80c0c:	0a d0       	mov\.l	80c38 <_foo\+0x38>,r0	! 14
+   80c0e:	ce 01       	mov\.l	@\(r0,r12\),r1
+   80c10:	12 62       	mov\.l	@r1,r2
+   80c12:	01 72       	add	#1,r2
+   80c14:	22 21       	mov\.l	r2,@r1
+   80c16:	09 d0       	mov\.l	80c3c <_foo\+0x3c>,r0	! 2c
+   80c18:	03 00       	bsrf	r0
+   80c1a:	09 00       	nop	
+   80c1c:	08 d0       	mov\.l	80c40 <_foo\+0x40>,r0	! fffffbde
+   80c1e:	03 00       	bsrf	r0
+   80c20:	09 00       	nop	
+   80c22:	08 d0       	mov\.l	80c44 <_foo\+0x44>,r0	! fffffbf0
+   80c24:	03 00       	bsrf	r0
+   80c26:	09 00       	nop	
+   80c28:	26 4f       	lds\.l	@r15\+,pr
+   80c2a:	0b 00       	rts	
+   80c2c:	f6 6c       	mov\.l	@r15\+,r12
+   80c2e:	09 00       	nop	
+	...
+   80c38:	14 00 .*
+   80c3a:	00 00 .*
+   80c3c:	2c 00 .*
+   80c3e:	00 00 .*
+   80c40:	de fb .*
+   80c42:	ff ff .*
+   80c44:	f0 fb .*
+   80c46:	ff ff .*
+
+00080c48 <_slocal>:
+   80c48:	0b 00       	rts	
+   80c4a:	09 00       	nop	
+
+00080c4c <_sglobal>:
+   80c4c:	0b 00       	rts	
+   80c4e:	09 00       	nop	
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib.dd b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib.dd
new file mode 100644
index 0000000..e20f334
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib.dd
@@ -0,0 +1,76 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+00080800 <_PROCEDURE_LINKAGE_TABLE_>:
+   80800:	d0 01       	mov\.l	80808 <_PROCEDURE_LINKAGE_TABLE_\+0x8>,r0	! c
+   80802:	00 ce       	mov\.l	@\(r0,r12\),r0
+   80804:	40 2b       	jmp	@r0
+   80806:	00 09       	nop	
+   80808:	00 00 .*
+   8080a:	00 0c .*
+   8080c:	d0 01       	mov\.l	80814 <_PROCEDURE_LINKAGE_TABLE_\+0x14>,r0	! 0
+   8080e:	51 c2       	mov\.l	@\(8,r12\),r1
+   80810:	41 2b       	jmp	@r1
+   80812:	00 09       	nop	
+   80814:	00 00 .*
+	\.\.\.
+
+00080818 <_sexternal@plt>:
+   80818:	d0 01       	mov\.l	80820 <_sexternal@plt\+0x8>,r0	! 10
+   8081a:	00 ce       	mov\.l	@\(r0,r12\),r0
+   8081c:	40 2b       	jmp	@r0
+   8081e:	00 09       	nop	
+   80820:	00 00 .*
+   80822:	00 10 .*
+   80824:	d0 01       	mov\.l	8082c <_sexternal@plt\+0x14>,r0	! c
+   80826:	51 c2       	mov\.l	@\(8,r12\),r1
+   80828:	41 2b       	jmp	@r1
+   8082a:	00 09       	nop	
+   8082c:	00 00 .*
+   8082e:	00 0c .*
+Disassembly of section \.text:
+
+00080c00 <_foo>:
+   80c00:	2f c6       	mov\.l	r12,@-r15
+   80c02:	4f 22       	sts\.l	pr,@-r15
+   80c04:	dc 0a       	mov\.l	80c30 <_foo\+0x30>,r12	! 0
+   80c06:	6c c2       	mov\.l	@r12,r12
+   80c08:	d0 0a       	mov\.l	80c34 <_foo\+0x34>,r0	! 0
+   80c0a:	0c ce       	mov\.l	@\(r0,r12\),r12
+   80c0c:	d0 0a       	mov\.l	80c38 <_foo\+0x38>,r0	! 14
+   80c0e:	01 ce       	mov\.l	@\(r0,r12\),r1
+   80c10:	62 12       	mov\.l	@r1,r2
+   80c12:	72 01       	add	#1,r2
+   80c14:	21 22       	mov\.l	r2,@r1
+   80c16:	d0 09       	mov\.l	80c3c <_foo\+0x3c>,r0	! 2c
+   80c18:	00 03       	bsrf	r0
+   80c1a:	00 09       	nop	
+   80c1c:	d0 08       	mov\.l	80c40 <_foo\+0x40>,r0	! fffffbde
+   80c1e:	00 03       	bsrf	r0
+   80c20:	00 09       	nop	
+   80c22:	d0 08       	mov\.l	80c44 <_foo\+0x44>,r0	! fffffbf0
+   80c24:	00 03       	bsrf	r0
+   80c26:	00 09       	nop	
+   80c28:	4f 26       	lds\.l	@r15\+,pr
+   80c2a:	00 0b       	rts	
+   80c2c:	6c f6       	mov\.l	@r15\+,r12
+   80c2e:	00 09       	nop	
+	...
+   80c38:	00 00 .*
+   80c3a:	00 14 .*
+   80c3c:	00 00 .*
+   80c3e:	00 2c .*
+   80c40:	ff ff .*
+   80c42:	fb de .*
+   80c44:	ff ff .*
+   80c46:	fb f0 .*
+
+00080c48 <_slocal>:
+   80c48:	00 0b       	rts	
+   80c4a:	00 09       	nop	
+
+00080c4c <_sglobal>:
+   80c4c:	00 0b       	rts	
+   80c4e:	00 09       	nop	
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib.nd b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib.nd
new file mode 100644
index 0000000..edf3db3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib.nd
@@ -0,0 +1,9 @@
+#...
+Symbol table '\.dynsym' .*:
+#...
+.*: 00081400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
+#...
+Symbol table '\.symtab' .*:
+#...
+.*: 00081400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib.rd b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib.rd
new file mode 100644
index 0000000..d9c56a0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib.rd
@@ -0,0 +1,12 @@
+
+Relocation section '\.rela\.plt' at offset .* contains 2 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+0008140c  .*a4 R_SH_JMP_SLOT     00080c4c   _sglobal \+ 0
+00081410  .*a4 R_SH_JMP_SLOT     00000000   _sexternal \+ 0
+
+Relocation section '\.rela\.dyn' at offset .* contains 4 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+00081800  000000a5 R_SH_RELATIVE * 00080c48
+00080c30  .*01 R_SH_DIR32        00000000   ___GOTT_BASE__ \+ 0
+00080c34  .*01 R_SH_DIR32        00000000   ___GOTT_INDEX__ \+ 0
+00081414  .*a3 R_SH_GLOB_DAT     00081c00   x \+ 0
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib.s b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib.s
new file mode 100644
index 0000000..ff21564
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib.s
@@ -0,0 +1,61 @@
+	.text
+	.globl	_foo
+	.type	_foo, %function
+_foo:
+	mov.l	r12,@-r15
+	sts.l	pr,@-r15
+	mov.l	1f,r12
+	mov.l	@r12,r12
+	mov.l	2f,r0
+	mov.l	@(r0,r12),r12
+
+	mov.l	3f,r0
+	mov.l	@(r0,r12),r1
+	mov.l	@r1,r2
+	add	#1,r2
+	mov.l	r2,@r1
+
+	mov.l	4f,r0
+	bsrf	r0
+	nop
+.Lb4:
+
+	mov.l	5f,r0
+	bsrf	r0
+	nop
+.Lb5:
+
+	mov.l	6f,r0
+	bsrf	r0
+	nop
+.Lb6:
+
+	lds.l	@r15+,pr
+	rts
+	mov.l	@r15+,r12
+	.align	2
+1:	.long	___GOTT_BASE__
+2:	.long	___GOTT_INDEX__
+3:	.long	x@GOT
+4:	.long	_slocal - .Lb4
+5:	.long	_sglobal@PLT - (.Lb5 - .)
+6:	.long	_sexternal@PLT - (.Lb6 - .)
+	.size	_foo, .-_foo
+
+	.type	_slocal, %function
+_slocal:
+	rts
+	nop
+	.size	_slocal, .-_slocal
+
+	.globl	_sglobal
+	.type	_sglobal, %function
+_sglobal:
+	rts
+	nop
+	.size	_sglobal, .-_sglobal
+
+	.data
+	.4byte	_slocal
+
+	.comm	x,4,4
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib.td b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib.td
new file mode 100644
index 0000000..9f223e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-lib.td
@@ -0,0 +1,3 @@
+#...
+ 0x0+16 \(TEXTREL\) +0x0
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks1-static.d b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-static.d
new file mode 100644
index 0000000..dffc45b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks1-static.d
@@ -0,0 +1,4 @@
+#name: VxWorks executable test 1 (static)
+#source: vxworks1.s
+#ld: tmpdir/libvxworks1.so -Tvxworks1.ld -EL
+#error: Dynamic sections created in non-dynamic link
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks1.dd b/binutils-2.19/ld/testsuite/ld-sh/vxworks1.dd
new file mode 100644
index 0000000..4bb3b47
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks1.dd
@@ -0,0 +1,73 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+00080800 <_PROCEDURE_LINKAGE_TABLE_>:
+   80800:	d1 01       	mov\.l	80808 <_PROCEDURE_LINKAGE_TABLE_\+0x8>,r1	! 81408
+   80802:	61 12       	mov\.l	@r1,r1
+   80804:	41 2b       	jmp	@r1
+   80806:	00 09       	nop	
+   80808:	00 08 .*
+			80808: R_SH_DIR32	_GLOBAL_OFFSET_TABLE_\+0x8
+   8080a:	14 08 .*
+
+0008080c <_sglobal@plt>:
+   8080c:	d0 01       	mov\.l	80814 <_sglobal@plt\+0x8>,r0	! 8140c
+   8080e:	60 02       	mov\.l	@r0,r0
+   80810:	40 2b       	jmp	@r0
+   80812:	00 09       	nop	
+   80814:	00 08 .*
+			80814: R_SH_DIR32	_GLOBAL_OFFSET_TABLE_\+0xc
+   80816:	14 0c .*
+   80818:	d0 01       	mov\.l	80820 <_sglobal@plt\+0x14>,r0	! 0
+   8081a:	af f1       	bra	80800 <_PROCEDURE_LINKAGE_TABLE_>
+   8081c:	00 09       	nop	
+   8081e:	00 09       	nop	
+   80820:	00 00 .*
+	\.\.\.
+
+00080824 <_foo@plt>:
+   80824:	d0 01       	mov\.l	8082c <_foo@plt\+0x8>,r0	! 81410
+   80826:	60 02       	mov\.l	@r0,r0
+   80828:	40 2b       	jmp	@r0
+   8082a:	00 09       	nop	
+   8082c:	00 08 .*
+			8082c: R_SH_DIR32	_GLOBAL_OFFSET_TABLE_\+0x10
+   8082e:	14 10 .*
+   80830:	d0 01       	mov\.l	80838 <_foo@plt\+0x14>,r0	! c
+   80832:	af e5       	bra	80800 <_PROCEDURE_LINKAGE_TABLE_>
+   80834:	00 09       	nop	
+   80836:	00 09       	nop	
+   80838:	00 00 .*
+   8083a:	00 0c .*
+Disassembly of section \.text:
+
+00080c00 <__start>:
+   80c00:	4f 22       	sts\.l	pr,@-r15
+   80c02:	d0 06       	mov\.l	80c1c <__start\+0x1c>,r0	! 80824 <_foo@plt>
+   80c04:	40 0b       	jsr	@r0
+   80c06:	00 09       	nop	
+   80c08:	d0 05       	mov\.l	80c20 <__start\+0x20>,r0	! 8080c <_sglobal@plt>
+   80c0a:	40 0b       	jsr	@r0
+   80c0c:	00 09       	nop	
+   80c0e:	d0 05       	mov\.l	80c24 <__start\+0x24>,r0	! 80c28 <_sexternal>
+   80c10:	40 0b       	jsr	@r0
+   80c12:	00 09       	nop	
+   80c14:	4f 26       	lds\.l	@r15\+,pr
+   80c16:	00 0b       	rts	
+   80c18:	00 09       	nop	
+   80c1a:	00 09       	nop	
+   80c1c:	00 08 .*
+			80c1c: R_SH_DIR32	\.plt\+0x24
+   80c1e:	08 24 .*
+   80c20:	00 08 .*
+			80c20: R_SH_DIR32	\.plt\+0xc
+   80c22:	08 0c .*
+   80c24:	00 08 .*
+			80c24: R_SH_DIR32	_sexternal
+   80c26:	0c 28 .*
+
+00080c28 <_sexternal>:
+   80c28:	00 0b       	rts	
+   80c2a:	00 09       	nop	
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks1.ld b/binutils-2.19/ld/testsuite/ld-sh/vxworks1.ld
new file mode 100644
index 0000000..65bf65d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks1.ld
@@ -0,0 +1,30 @@
+SECTIONS
+{
+  . = 0x80000;
+  .interp : { *(.interp) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+
+  . = ALIGN (0x400);
+  .rela.dyn : { *(.rela.dyn) }
+  .rela.plt : { *(.rela.plt) }
+
+  . = ALIGN (0x400);
+  .plt : { *(.plt) }
+
+  . = ALIGN (0x400);
+  .text : { *(.text) }
+
+  . = ALIGN (0x1000);
+  .dynamic : { *(.dynamic) }
+
+  . = ALIGN (0x400);
+  .got : { *(.got.plt) *(.got) }
+
+  . = ALIGN (0x400);
+  .data : { *(.data) }
+
+  . = ALIGN (0x400);
+  .bss : { *(.bss) *(.dynbss) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks1.rd b/binutils-2.19/ld/testsuite/ld-sh/vxworks1.rd
new file mode 100644
index 0000000..ee50c74
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks1.rd
@@ -0,0 +1,19 @@
+
+Relocation section '\.rela\.plt' at offset .* contains 2 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+0008140c  .*a4 R_SH_JMP_SLOT     0008080c   _sglobal \+ 0
+00081410  .*a4 R_SH_JMP_SLOT     00080824   _foo \+ 0
+
+Relocation section '\.rela\.text' at offset .* contains 3 entries:
+ Offset     Info    Type            Sym.Value  Sym. Name \+ Addend
+00080c1c  .*01 R_SH_DIR32        00080800   \.plt \+ 24
+00080c20  .*01 R_SH_DIR32        00080800   \.plt \+ c
+00080c24  .*01 R_SH_DIR32        00080c28   _sexternal \+ 0
+
+Relocation section '\.rela\.plt\.unloaded' at offset .* contains 5 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+00080808  .*01 R_SH_DIR32        00081400   _GLOBAL_OFFSET_TABLE_ \+ 8
+00080814  .*01 R_SH_DIR32        00081400   _GLOBAL_OFFSET_TABLE_ \+ c
+0008140c  .*01 R_SH_DIR32        00080800   _PROCEDURE_LINKAGE_TAB.* \+ 0
+0008082c  .*01 R_SH_DIR32        00081400   _GLOBAL_OFFSET_TABLE_ \+ 10
+00081410  .*01 R_SH_DIR32        00080800   _PROCEDURE_LINKAGE_TAB.* \+ 0
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks1.s b/binutils-2.19/ld/testsuite/ld-sh/vxworks1.s
new file mode 100644
index 0000000..3ae2373
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks1.s
@@ -0,0 +1,32 @@
+	.text
+	.globl	__start
+	.type	__start, %function
+__start:
+	sts.l	pr,@-r15
+	mov.l	1f,r0
+	jsr	@r0
+	nop
+
+	mov.l	2f,r0
+	jsr	@r0
+	nop
+
+	mov.l	3f,r0
+	jsr	@r0
+	nop
+
+	lds.l	@r15+,pr
+	rts
+	nop
+	.align	2
+1:	.long	_foo
+2:	.long	_sglobal
+3:	.long	_sexternal
+	.size	__start, .-__start
+
+	.globl	_sexternal
+	.type	_sexternal, %function
+_sexternal:
+	rts
+	nop
+	.size	_sexternal, .-_sexternal
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks2-static.sd b/binutils-2.19/ld/testsuite/ld-sh/vxworks2-static.sd
new file mode 100644
index 0000000..912755b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks2-static.sd
@@ -0,0 +1,9 @@
+#...
+Elf file type is EXEC \(Executable file\)
+Entry point 0x80000
+#...
+Program Headers:
+  Type .*
+  LOAD .* 0x00080000 0x00080000 .* R E 0x1000
+
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks2.s b/binutils-2.19/ld/testsuite/ld-sh/vxworks2.s
new file mode 100644
index 0000000..f680a58
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks2.s
@@ -0,0 +1,6 @@
+	.globl	__start
+	.type	__start, %function
+__start:
+	rts
+	nop
+	.end	__start
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks2.sd b/binutils-2.19/ld/testsuite/ld-sh/vxworks2.sd
new file mode 100644
index 0000000..5ff87d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks2.sd
@@ -0,0 +1,13 @@
+#...
+Elf file type is EXEC \(Executable file\)
+Entry point 0x80400
+#...
+Program Headers:
+  Type .*
+  PHDR .*
+#...
+  LOAD .* 0x00080000 0x00080000 .* R E 0x1000
+  LOAD .* 0x00081000 0x00081000 .* RW  0x1000
+  DYNAMIC .*
+
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks3-le.dd b/binutils-2.19/ld/testsuite/ld-sh/vxworks3-le.dd
new file mode 100644
index 0000000..6a0fc2d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks3-le.dd
@@ -0,0 +1,34 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+#...
+.*:	01 d0       	mov\.l	.*,r0	! 0
+.*:	f1 af       	bra	.* <_PROCEDURE_LINKAGE_TABLE_>
+.*:	09 00       	nop	
+#...
+.*:	01 d0       	mov\.l	.*,r0	! 7ec
+.*:	05 a8       	bra	.* <_PROCEDURE_LINKAGE_TABLE_>
+.*:	09 00       	nop	
+#...
+.*:	01 d0       	mov\.l	.*,r0	! 7f8
+.*:	f2 af       	bra	.*
+.*:	09 00       	nop	
+#...
+.*:	01 d0       	mov\.l	.*,r0	! fe4
+.*:	06 a8       	bra	.*
+.*:	09 00       	nop	
+#...
+.*:	01 d0       	mov\.l	.*,r0	! ff0
+.*:	f2 af       	bra	.*
+.*:	09 00       	nop	
+#...
+.*:	01 d0       	mov\.l	.*,r0	! 17dc
+.*:	06 a8       	bra	.*
+.*:	09 00       	nop	
+#...
+.*:	01 d0       	mov\.l	.*,r0	! 17e8
+.*:	f2 af       	bra	.*
+.*:	09 00       	nop	
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks3-lib-le.dd b/binutils-2.19/ld/testsuite/ld-sh/vxworks3-lib-le.dd
new file mode 100644
index 0000000..011d20c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks3-lib-le.dd
@@ -0,0 +1,12 @@
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+.* <foo0>:
+.*:	0b 00       	rts	
+.*:	09 00       	nop	
+#...
+.* <foo510>:
+.*:	0b 00       	rts	
+.*:	09 00       	nop	
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks3-lib.dd b/binutils-2.19/ld/testsuite/ld-sh/vxworks3-lib.dd
new file mode 100644
index 0000000..555be00
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks3-lib.dd
@@ -0,0 +1,12 @@
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+.* <foo0>:
+.*:	00 0b       	rts	
+.*:	00 09       	nop	
+#...
+.* <foo510>:
+.*:	00 0b       	rts	
+.*:	00 09       	nop	
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks3-lib.s b/binutils-2.19/ld/testsuite/ld-sh/vxworks3-lib.s
new file mode 100644
index 0000000..6e10331
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks3-lib.s
@@ -0,0 +1,12 @@
+	.macro	entry
+	.globl	foo\@
+	.size	foo\@,4
+	.type	foo\@,@function
+foo\@:
+	rts
+	nop
+	.endm
+	
+	.rept	511
+	entry
+	.endr
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks3.dd b/binutils-2.19/ld/testsuite/ld-sh/vxworks3.dd
new file mode 100644
index 0000000..f0593b6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks3.dd
@@ -0,0 +1,34 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+#...
+.*:	d0 01       	mov\.l	.*,r0	! 0
+.*:	af f1       	bra	.* <_PROCEDURE_LINKAGE_TABLE_>
+.*:	00 09       	nop	
+#...
+.*:	d0 01       	mov\.l	.*,r0	! 7ec
+.*:	a8 05       	bra	.* <_PROCEDURE_LINKAGE_TABLE_>
+.*:	00 09       	nop	
+#...
+.*:	d0 01       	mov\.l	.*,r0	! 7f8
+.*:	af f2       	bra	.*
+.*:	00 09       	nop	
+#...
+.*:	d0 01       	mov\.l	.*,r0	! fe4
+.*:	a8 06       	bra	.*
+.*:	00 09       	nop	
+#...
+.*:	d0 01       	mov\.l	.*,r0	! ff0
+.*:	af f2       	bra	.*
+.*:	00 09       	nop	
+#...
+.*:	d0 01       	mov\.l	.*,r0	! 17dc
+.*:	a8 06       	bra	.*
+.*:	00 09       	nop	
+#...
+.*:	d0 01       	mov\.l	.*,r0	! 17e8
+.*:	af f2       	bra	.*
+.*:	00 09       	nop	
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks3.s b/binutils-2.19/ld/testsuite/ld-sh/vxworks3.s
new file mode 100644
index 0000000..86d6310
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks3.s
@@ -0,0 +1,7 @@
+	.macro	entry
+	.long	foo\@
+	.endm
+	
+	.rept	511
+	entry
+	.endr
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks4.d b/binutils-2.19/ld/testsuite/ld-sh/vxworks4.d
new file mode 100644
index 0000000..c5721dd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks4.d
@@ -0,0 +1,11 @@
+#source: vxworks4a.s
+#source: vxworks4b.s
+#ld: -shared -Tvxworks1.ld
+#target: sh-*-vxworks
+#readelf: --relocs
+
+Relocation section '\.rela\.dyn' at offset .* contains 3 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+00081810  000000a5 R_SH_RELATIVE                                0008181c
+00081814  .*01 R_SH_DIR32        00000000   global \+ 1234
+00081818  .*02 R_SH_REL32        00000000   global \+ 1234
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks4a.s b/binutils-2.19/ld/testsuite/ld-sh/vxworks4a.s
new file mode 100644
index 0000000..2785567
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks4a.s
@@ -0,0 +1,2 @@
+	.data
+	.fill	0x10
diff --git a/binutils-2.19/ld/testsuite/ld-sh/vxworks4b.s b/binutils-2.19/ld/testsuite/ld-sh/vxworks4b.s
new file mode 100644
index 0000000..6c0228a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/vxworks4b.s
@@ -0,0 +1,4 @@
+	.data
+	.long	. + 0xc
+	.long	global + 0x1234
+	.long	global + 0x1234 - .
diff --git a/binutils-2.19/ld/testsuite/ld-sh/weak1.d b/binutils-2.19/ld/testsuite/ld-sh/weak1.d
new file mode 100644
index 0000000..d248bb9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/weak1.d
@@ -0,0 +1,21 @@
+#source: weak1.s
+#as: -little
+#ld: -e 0x1000 -EL
+#objdump: -ts
+#target: sh*-*-elf
+
+.*:     file format elf32-sh.*
+
+SYMBOL TABLE:
+#...
+0+10a0 l       .data	0+ d0
+0+1000 l       .text	0+ f
+0+10a4  w      .data	0+ w0
+#...
+
+Contents of section .text:
+ 1000 01d11260 0b000900 a4100000 09000900  .*
+ 1010 09000900 09000900 09000900 09000900  .*
+Contents of section .data:
+ 10a0 01000000 00000000                    .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sh/weak1.s b/binutils-2.19/ld/testsuite/ld-sh/weak1.s
new file mode 100644
index 0000000..79192af
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sh/weak1.s
@@ -0,0 +1,19 @@
+ .data
+ .align 2
+d0:
+ .long 1
+ .global w0
+w0:
+ .long 0
+ .weak w0
+ .text
+ .align 5
+f:
+ mov.l .L3,r1
+ mov.l @r1,r0
+ rts 
+ nop
+ .align 2
+.L3:
+ .long w0
+
diff --git a/binutils-2.19/ld/testsuite/ld-shared/elf-offset.ld b/binutils-2.19/ld/testsuite/ld-shared/elf-offset.ld
new file mode 100644
index 0000000..5e6611a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-shared/elf-offset.ld
@@ -0,0 +1,170 @@
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = 0x100000;
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .gnu.version   : { *(.gnu.version)	}
+  .gnu.version_d   : { *(.gnu.version_d)	}
+  .gnu.version_r   : { *(.gnu.version_r)	}
+  .rel.text      :
+    {
+      *(.rel.text)
+      *(.rel.text.*)
+      *(.rel.gnu.linkonce.t*)
+    }
+  .rela.text     :
+    {
+      *(.rela.text)
+      *(.rela.text.*)
+      *(.rela.gnu.linkonce.t*)
+    }
+  .rel.data      :
+    {
+      *(.rel.data)
+      *(.rel.data.*)
+      *(.rel.gnu.linkonce.d*)
+    }
+  .rela.data     :
+    {
+      *(.rela.data)
+      *(.rela.data.*)
+      *(.rela.gnu.linkonce.d*)
+    }
+  .rel.rodata    :
+    {
+      *(.rel.rodata)
+      *(.rel.rodata.*)
+      *(.rel.gnu.linkonce.r*)
+    }
+  .rela.rodata   :
+    {
+      *(.rela.rodata)
+      *(.rela.rodata.*)
+      *(.rela.gnu.linkonce.r*)
+    }
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.init      : { *(.rel.init)	}
+  .rela.init     : { *(.rela.init)	}
+  .rel.fini      : { *(.rel.fini)	}
+  .rela.fini     : { *(.rela.fini)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .rel.eh_frame  : { *(.rel.eh_frame)		}
+  .rela.eh_frame : { *(.rela.eh_frame)		}
+  .init          : { KEEP (*(.init))	}
+  .plt      : { *(.plt)	}
+  .text      :
+  {
+    *(.text)
+    *(.text.*)
+    *(.stub)
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.gnu.linkonce.t*)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .fini      : { KEEP (*(.fini))		} =0x9090
+  .rodata    :
+  {
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r*)
+  }
+  .rodata1   : { *(.rodata1) }
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN(0x1000) + (. & (0x1000 - 1));
+  .data    :
+  {
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d*)
+    SORT(CONSTRUCTORS)
+  }
+  .data1   : { *(.data1) }
+  .ctors         :
+  {
+    /* gcc uses crtbegin.o to find the start of the constructors, so
+       we make sure it is first.  Because this is a wildcard, it
+       doesn't matter if the user does not actually link against
+       crtbegin.o; the linker won't look for a file to match a
+       wildcard.  The wildcard also means that it doesn't matter which
+       directory crtbegin.o is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  }
+  .dtors         :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  }
+  .got           : { *(.got.plt) *(.got) }
+  .dynamic       : { *(.dynamic) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata     : { *(.sdata) *(.sdata.*) }
+  _edata  =  .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .sbss      : { *(.sbss) *(.scommon) }
+  .bss       :
+  {
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   . = ALIGN(32 / 8);
+  }
+  . = ALIGN(32 / 8);
+  _end = . ;
+  PROVIDE (end = .);
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment 0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  /* These must appear regardless of  .  */
+}
diff --git a/binutils-2.19/ld/testsuite/ld-shared/main.c b/binutils-2.19/ld/testsuite/ld-shared/main.c
new file mode 100644
index 0000000..ce06261
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-shared/main.c
@@ -0,0 +1,84 @@
+/* This is the main program for the shared library test.  */
+
+#include <stdio.h>
+
+int mainvar = 1;
+int overriddenvar = 2;
+extern int shlibvar1;
+
+extern int shlib_mainvar ();
+extern int shlib_overriddenvar ();
+extern int shlib_shlibvar1 ();
+extern int shlib_shlibvar2 ();
+extern int shlib_shlibcall ();
+extern int shlib_maincall ();
+extern int shlib_checkfunptr1 ();
+extern int shlib_checkfunptr2 ();
+extern int (*shlib_getfunptr1 ()) ();
+extern int (*shlib_getfunptr2 ()) ();
+extern int shlib_check ();
+extern int shlib_shlibcall2 ();
+
+/* This function is called by the shared library.  */
+
+int
+main_called ()
+{
+  return 6;
+}
+
+/* This function overrides a function in the shared library.  */
+
+int
+shlib_overriddencall2 ()
+{
+  return 8;
+}
+
+int
+main ()
+{
+  int (*p) ();
+
+  printf ("mainvar == %d\n", mainvar);
+  printf ("overriddenvar == %d\n", overriddenvar);
+  printf ("shlibvar1 == %d\n", shlibvar1);
+#ifndef XCOFF_TEST
+  printf ("shlib_mainvar () == %d\n", shlib_mainvar ());
+  printf ("shlib_overriddenvar () == %d\n", shlib_overriddenvar ());
+#endif
+  printf ("shlib_shlibvar1 () == %d\n", shlib_shlibvar1 ());
+  printf ("shlib_shlibvar2 () == %d\n", shlib_shlibvar2 ());
+  printf ("shlib_shlibcall () == %d\n", shlib_shlibcall ());
+#ifndef XCOFF_TEST
+  printf ("shlib_shlibcall2 () == %d\n", shlib_shlibcall2 ());
+  printf ("shlib_maincall () == %d\n", shlib_maincall ());
+#endif
+  printf ("main_called () == %d\n", main_called ());
+#ifndef SYMBOLIC_TEST
+  printf ("shlib_checkfunptr1 (shlib_shlibvar1) == %d\n",
+	  shlib_checkfunptr1 (shlib_shlibvar1));
+#ifndef XCOFF_TEST
+  printf ("shlib_checkfunptr2 (main_called) == %d\n",
+	  shlib_checkfunptr2 (main_called));
+#endif
+  p = shlib_getfunptr1 ();
+  printf ("shlib_getfunptr1 () ");
+  if (p == shlib_shlibvar1)
+    printf ("==");
+  else
+    printf ("!=");
+  printf (" shlib_shlibvar1\n");
+#ifndef XCOFF_TEST
+  p = shlib_getfunptr2 ();
+  printf ("shlib_getfunptr2 () ");
+  if (p == main_called)
+    printf ("==");
+  else
+    printf ("!=");
+  printf (" main_called\n");
+#endif
+#endif
+  printf ("shlib_check () == %d\n", shlib_check ());
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-shared/sh1.c b/binutils-2.19/ld/testsuite/ld-shared/sh1.c
new file mode 100644
index 0000000..c8e5232
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-shared/sh1.c
@@ -0,0 +1,160 @@
+/* This is part of the shared library ld test.  This file becomes part
+   of a shared library.  */
+
+/* This variable is supplied by the main program.  */
+#ifndef XCOFF_TEST
+extern int mainvar;
+#endif
+
+/* This variable is defined in the shared library, and overridden by
+   the main program.  */
+#ifndef XCOFF_TEST
+int overriddenvar = -1;
+#endif
+
+/* This variable is defined in the shared library.  */
+int shlibvar1 = 3;
+
+/* This variable is defined by another object in the shared library.  */
+extern int shlibvar2;
+
+/* These functions return the values of the above variables as seen in
+   the shared library.  */
+
+#ifndef XCOFF_TEST
+int
+shlib_mainvar ()
+{
+  return mainvar;
+}
+#endif
+
+#ifndef XCOFF_TEST
+int
+shlib_overriddenvar ()
+{
+  return overriddenvar;
+}
+#endif
+
+int
+shlib_shlibvar1 ()
+{
+  return shlibvar1;
+}
+
+int
+shlib_shlibvar2 ()
+{
+  return shlibvar2;
+}
+
+/* This function calls a function defined by another object in the
+   shared library.  */
+
+extern int shlib_shlibcalled ();
+
+int
+shlib_shlibcall ()
+{
+  return shlib_shlibcalled ();
+}
+
+#ifndef XCOFF_TEST
+/* This function calls a function defined in this object in the shared
+   library.  The main program will override the called function.  */
+
+extern int shlib_overriddencall2 ();
+
+int
+shlib_shlibcall2 ()
+{
+  return shlib_overriddencall2 ();
+}
+#endif
+
+/* This function calls a function defined by the main program.  */
+
+#ifndef XCOFF_TEST
+extern int main_called ();
+
+int
+shlib_maincall ()
+{
+  return main_called ();
+}
+#endif
+
+/* This function is passed a function pointer to shlib_mainvar.  It
+   confirms that the pointer compares equally.  */
+
+int 
+shlib_checkfunptr1 (p)
+     int (*p) ();
+{
+  return p == shlib_shlibvar1;
+}
+
+/* This function is passed a function pointer to main_called.  It
+   confirms that the pointer compares equally.  */
+
+#ifndef XCOFF_TEST
+int
+shlib_checkfunptr2 (p)
+     int (*p) ();
+{
+  return p == main_called;
+}
+#endif
+
+/* This function returns a pointer to shlib_mainvar.  */
+
+int
+(*shlib_getfunptr1 ()) ()
+{
+  return shlib_shlibvar1;
+}
+
+/* This function returns a pointer to main_called.  */
+
+#ifndef XCOFF_TEST
+int
+(*shlib_getfunptr2 ()) ()
+{
+  return main_called;
+}
+#endif
+
+/* This function makes sure that constant data and local functions
+   work.  */
+
+#ifndef __STDC__
+#define const
+#endif
+
+static int i = 6;
+static const char *str = "Hello, world\n";
+
+int
+shlib_check ()
+{
+  const char *s1, *s2;
+
+  if (i != 6)
+    return 0;
+
+  /* To isolate the test, don't rely on any external functions, such
+     as strcmp.  */
+  s1 = "Hello, world\n";
+  s2 = str;
+  while (*s1 != '\0')
+    if (*s1++ != *s2++)
+      return 0;
+  if (*s2 != '\0')
+    return 0;
+
+  if (shlib_shlibvar1 () != 3)
+    return 0;
+
+  return 1;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-shared/sh2.c b/binutils-2.19/ld/testsuite/ld-shared/sh2.c
new file mode 100644
index 0000000..7cd1db3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-shared/sh2.c
@@ -0,0 +1,22 @@
+/* This is part of the shared library ld test.  This file becomes part
+   of a shared library.  */
+
+/* This variable is defined here, and referenced by another file in
+   the shared library.  */
+int shlibvar2 = 4;
+
+/* This function is called by another file in the shared library.  */
+
+int
+shlib_shlibcalled ()
+{
+  return 5;
+}
+
+#ifndef XCOFF_TEST
+int
+shlib_overriddencall2 ()
+{
+  return 7;
+}
+#endif
diff --git a/binutils-2.19/ld/testsuite/ld-shared/shared.dat b/binutils-2.19/ld/testsuite/ld-shared/shared.dat
new file mode 100644
index 0000000..40ee37f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-shared/shared.dat
@@ -0,0 +1,16 @@
+mainvar == 1
+overriddenvar == 2
+shlibvar1 == 3
+shlib_mainvar () == 1
+shlib_overriddenvar () == 2
+shlib_shlibvar1 () == 3
+shlib_shlibvar2 () == 4
+shlib_shlibcall () == 5
+shlib_shlibcall2 () == 8
+shlib_maincall () == 6
+main_called () == 6
+shlib_checkfunptr1 (shlib_shlibvar1) == 1
+shlib_checkfunptr2 (main_called) == 1
+shlib_getfunptr1 () == shlib_shlibvar1
+shlib_getfunptr2 () == main_called
+shlib_check () == 1
diff --git a/binutils-2.19/ld/testsuite/ld-shared/shared.exp b/binutils-2.19/ld/testsuite/ld-shared/shared.exp
new file mode 100644
index 0000000..90e9f7b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-shared/shared.exp
@@ -0,0 +1,304 @@
+# Expect script for ld-shared tests
+#   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+#   2004, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Ian Lance Taylor (ian@cygnus.com)
+#
+
+# Make sure that ld can generate ELF shared libraries.
+# Note that linking against ELF shared libraries is tested by the
+# bootstrap test.
+
+# This test can only be run if ld generates native executables.
+if ![isnative] then {return}
+
+# This test can only be run on a couple of ELF platforms.
+# Square bracket expressions seem to confuse istarget.
+if { ![istarget hppa*64*-*-hpux*] \
+     && ![istarget hppa*-*-linux*] \
+     && ![istarget i?86-*-sysv4*] \
+     && ![istarget i?86-*-unixware] \
+     && ![istarget i?86-*-elf*] \
+     && ![istarget i?86-*-linux*] \
+     && ![istarget ia64-*-elf*] \
+     && ![istarget ia64-*-linux*] \
+     && ![istarget m68k-*-linux*] \
+     && ![istarget mips*-*-irix5*] \
+     && ![istarget mips*-*-linux*] \
+     && ![istarget powerpc-*-elf*] \
+     && ![istarget powerpc-*-linux*] \
+     && ![istarget powerpc-*-sysv4*] \
+     && ![istarget sparc*-*-elf] \
+     && ![istarget sparc*-*-solaris2*] \
+     && ![istarget sparc*-*-sunos4*] \
+     && ![istarget sparc*-*-linux*] \
+     && ![istarget arm*-*-linux*] \
+     && ![istarget alpha*-*-linux*] \
+     && ![istarget rs6000*-*-aix*] \
+     && ![istarget powerpc*-*-aix*] \
+     && ![istarget s390*-*-linux*] \
+     && ![istarget x86_64-*-linux*] } {
+    return
+}
+
+if { [istarget *-*-linux*aout*] \
+     || [istarget *-*-linux*oldld*] } {
+    return
+}
+
+set tmpdir tmpdir
+set SHCFLAG ""
+
+if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+
+    # AIX shared libraries do not seem to support useful features,
+    # like overriding the shared library function or letting the
+    # shared library refer to objects defined in the main program.  We
+    # avoid testing those features.
+    set SHCFLAG "-DXCOFF_TEST"
+
+    # The AIX 3.2.5 loader appears to randomly fail when loading
+    # shared libraries from NSF mounted partitions, so we avoid any
+    # potential problems by using a local directory.
+    catch {exec /bin/sh -c "echo $$"} pid
+    set tmpdir /usr/tmp/ld.$pid
+    catch "exec mkdir $tmpdir" exec_status
+
+    # On AIX, we need to explicitly export the symbols the shared
+    # library is going to provide, and need.
+    set file [open $tmpdir/xcoff.exp w]
+    puts $file shlibvar1
+    puts $file shlibvar2
+    puts $file shlib_shlibvar1
+    puts $file shlib_shlibvar2
+    puts $file shlib_shlibcall
+    puts $file shlib_shlibcalled
+    puts $file shlib_checkfunptr1
+    puts $file shlib_getfunptr1
+    puts $file shlib_check
+    close $file
+}
+
+# The test procedure.
+proc shared_test { progname testname main sh1 sh2 dat args } {
+    global CC
+    global srcdir
+    global subdir
+    global exec_output
+    global host_triplet
+    global tmpdir
+
+    if [llength $args] { set shldflags [lindex $args 0] } else { set shldflags "" }
+
+    # Build the shared library.
+    # On AIX, we need to use an export file.
+    set shared -shared
+    if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+	set shared "-bM:SRE -bE:$tmpdir/xcoff.exp"
+    }
+    if {![ld_simple_link $CC $tmpdir/$progname.so "$shared $shldflags $tmpdir/$sh1 $tmpdir/$sh2"]} {
+        fail "$testname"
+    	return
+    }
+
+    # Link against the shared library.  Use -rpath so that the
+    # dynamic linker can locate the shared library at runtime.
+    # On AIX, we must include /lib in -rpath, as otherwise the loader
+    # can not find -lc.
+    set rpath $tmpdir
+    if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+	set rpath /lib:$tmpdir
+    }
+    if ![ld_simple_link $CC $tmpdir/$progname "-Wl,-rpath,$rpath $tmpdir/$main $tmpdir/$progname.so"] {
+    	fail "$testname"
+    	return
+    }
+
+    # Run the resulting program
+    send_log "$tmpdir/$progname >$tmpdir/$progname.out\n"
+    verbose "$tmpdir/$progname >$tmpdir/$progname.out"
+    catch "exec $tmpdir/$progname >$tmpdir/$progname.out" exec_output
+    if ![string match "" $exec_output] then {
+	send_log "$exec_output\n"
+	verbose "$exec_output"
+	fail "$testname"
+    	return
+    }
+
+    send_log "diff $tmpdir/$progname.out $srcdir/$subdir/$dat.dat\n"
+    verbose "diff $tmpdir/$progname.out $srcdir/$subdir/$dat.dat"
+    catch "exec diff $tmpdir/$progname.out $srcdir/$subdir/$dat.dat" exec_output
+    set exec_output [prune_warnings $exec_output]
+
+    if {![string match "" $exec_output]} then {
+	send_log "$exec_output\n"
+	verbose "$exec_output"
+	fail "$testname"
+        return
+    }
+
+    pass "$testname"
+}
+
+if [istarget mips*-*-*] {
+    set picflag ""
+} else {
+    # Unfortunately, the gcc argument is -fpic and the cc argument is
+    # -KPIC.  We have to try both.
+    set picflag "-fpic"
+    send_log "$CC $picflag\n"
+    verbose "$CC $picflag"
+    catch "exec $CC $picflag" exec_output
+    send_log "$exec_output\n"
+    verbose "--" "$exec_output"
+    if { [string match "*illegal option*" $exec_output] \
+	 || [string match "*option ignored*" $exec_output] \
+	 || [string match "*unrecognized option*" $exec_output] \
+	 || [string match "*passed to ld*" $exec_output] } {
+	if [istarget *-*-sunos4*] {
+	    set picflag "-pic"
+	} else {
+	    set picflag "-KPIC"
+	}
+    }
+}
+verbose "Using $picflag to compile PIC code"
+
+# Compile the main program.
+if ![ld_compile "$CC $CFLAGS $SHCFLAG" $srcdir/$subdir/main.c $tmpdir/mainnp.o] {
+    unresolved "shared (non PIC)"
+    unresolved "shared"
+} else {
+    # The shared library is composed of two files.  First compile them
+    # without using -fpic.  That should work on an ELF system,
+    # although it will be less efficient because the dynamic linker
+    # will need to do more relocation work.  However, note that not
+    # using -fpic will cause some of the tests to return different
+    # results.
+    if { ![ld_compile "$CC $CFLAGS $SHCFLAG" $srcdir/$subdir/sh1.c $tmpdir/sh1np.o]
+	 || ![ld_compile "$CC $CFLAGS $SHCFLAG" $srcdir/$subdir/sh2.c $tmpdir/sh2np.o] } {
+	unresolved "shared (non PIC)"
+    } else { if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+	shared_test shnp "shared (nonPIC)" mainnp.o sh1np.o sh2np.o xcoff
+    } else {
+	# SunOS non PIC shared libraries don't permit some cases of
+	# overriding.
+	setup_xfail "*-*-sunos4*"
+	setup_xfail "ia64-*-linux*"
+	setup_xfail "alpha*-*-linux*"
+	if { ![istarget hppa*64*-*-linux*] } {
+	    setup_xfail "hppa*-*-linux*"
+	}
+	if { [istarget sparc*-*-linux*] && [is_elf64 $tmpdir/mainnp.o] } {
+	    setup_xfail "sparc*-*-linux*"
+	}
+	setup_xfail "x86_64-*-linux*"
+	setup_xfail "s390x-*-linux*"
+	shared_test shnp "shared (non PIC)" mainnp.o sh1np.o sh2np.o shared
+
+	# Test ELF shared library relocations with a non-zero load
+	# address for the library.  Near as I can tell, the R_*_RELATIVE
+	# relocations for various targets are broken in the case where
+	# the load address is not zero (which is the default).
+	setup_xfail "*-*-sunos4*"
+	setup_xfail "*-*-linux*libc1"
+	setup_xfail "powerpc-*-linux*"
+	setup_xfail "ia64-*-linux*"
+	setup_xfail "alpha*-*-linux*"
+	setup_xfail "mips*-*-linux*"
+	if { ![istarget hppa*64*-*-linux*] } {
+	    setup_xfail "hppa*-*-linux*"
+	}
+	if { [istarget sparc*-*-linux*] && [is_elf64 $tmpdir/mainnp.o] } {
+	    setup_xfail "sparc*-*-linux*"
+	}
+	setup_xfail "x86_64-*-linux*"
+	setup_xfail "s390x-*-linux*"
+	shared_test shnp "shared (non PIC, load offset)" \
+		mainnp.o sh1np.o sh2np.o shared \
+		"-T $srcdir/$subdir/elf-offset.ld"
+    } }
+
+    # Now compile the code using -fpic.
+
+    if { ![ld_compile "$CC $CFLAGS $SHCFLAG $picflag" $srcdir/$subdir/sh1.c $tmpdir/sh1p.o] 
+	 || ![ld_compile "$CC $CFLAGS $SHCFLAG $picflag" $srcdir/$subdir/sh2.c $tmpdir/sh2p.o] } {
+	unresolved "shared"
+    } else {
+	# SunOS can not compare function pointers correctly
+	if [istarget "*-*-sunos4*"] {
+	    shared_test shp "shared" mainnp.o sh1p.o sh2p.o sun4
+	} else { if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+	    shared_test shp "shared" mainnp.o sh1p.o sh2p.o xcoff
+	} else {
+	    shared_test shp "shared" mainnp.o sh1p.o sh2p.o shared
+	    ld_compile "$CC $CFLAGS -DSYMBOLIC_TEST -DXCOFF_TEST $SHCFLAG" $srcdir/$subdir/main.c $tmpdir/mainnp.o
+	    ld_compile "$CC $CFLAGS -DSYMBOLIC_TEST -DXCOFF_TEST $SHCFLAG $picflag" $srcdir/$subdir/sh1.c $tmpdir/sh1p.o
+	    shared_test shp "shared -Bsymbolic" mainnp.o sh1p.o sh2p.o symbolic "-Bsymbolic" 
+	    ld_compile "$CC $CFLAGS $SHCFLAG" $srcdir/$subdir/main.c $tmpdir/mainnp.o
+	    ld_compile "$CC $CFLAGS $SHCFLAG $picflag" $srcdir/$subdir/sh1.c $tmpdir/sh1p.o
+	} }
+    }
+}
+
+# Now do the same tests again, but this time compile main.c PIC.
+if ![ld_compile "$CC $CFLAGS $SHCFLAG $picflag" $srcdir/$subdir/main.c $tmpdir/mainp.o] {
+    unresolved "shared (PIC main, non PIC so)"
+    unresolved "shared (PIC main)"
+} else {
+    if { [file exists $tmpdir/sh1np.o ] && [ file exists $tmpdir/sh2np.o ] } {
+        if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+	    shared_test shmpnp "shared (PIC main, non PIC so)" mainp.o sh1np.o sh2np.o xcoff
+	} else {
+	    # SunOS non PIC shared libraries don't permit some cases of
+	    # overriding.
+	    setup_xfail "*-*-sunos4*"
+	    setup_xfail "ia64-*-linux*"
+	    setup_xfail "alpha*-*-linux*"
+	    if { ![istarget hppa*64*-*-linux*] } {
+		setup_xfail "hppa*-*-linux*"
+	    }
+	    if { [istarget sparc*-*-linux*] && [is_elf64 $tmpdir/mainp.o] } {
+		setup_xfail "sparc*-*-linux*"
+	    }
+	    setup_xfail "x86_64-*-linux*"
+	    setup_xfail "s390x-*-linux*"
+	    shared_test shmpnp "shared (PIC main, non PIC so)" mainp.o sh1np.o sh2np.o shared
+	}
+    } else {
+	unresolved "shared (PIC main, non PIC so)"
+    }
+
+    if { [file exists $tmpdir/sh1p.o ] && [ file exists $tmpdir/sh2p.o ] } {
+        if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+	    shared_test shmpp "shared (PIC main)" mainp.o sh1p.o sh2p.o xcoff
+	} else {
+	    shared_test shmpp "shared (PIC main)" mainp.o sh1p.o sh2p.o shared
+	}
+    } else {
+	unresolved "shared (PIC main)"
+    }
+}
+
+if { [istarget rs6000*-*-aix*] || [istarget powerpc*-*-aix*] } {
+    # Remove the temporary directory.
+    catch "exec rm -rf $tmpdir" exec_status
+}
diff --git a/binutils-2.19/ld/testsuite/ld-shared/sun4.dat b/binutils-2.19/ld/testsuite/ld-shared/sun4.dat
new file mode 100644
index 0000000..be0d87d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-shared/sun4.dat
@@ -0,0 +1,16 @@
+mainvar == 1
+overriddenvar == 2
+shlibvar1 == 3
+shlib_mainvar () == 1
+shlib_overriddenvar () == 2
+shlib_shlibvar1 () == 3
+shlib_shlibvar2 () == 4
+shlib_shlibcall () == 5
+shlib_shlibcall2 () == 8
+shlib_maincall () == 6
+main_called () == 6
+shlib_checkfunptr1 (shlib_shlibvar1) == 0
+shlib_checkfunptr2 (main_called) == 1
+shlib_getfunptr1 () != shlib_shlibvar1
+shlib_getfunptr2 () == main_called
+shlib_check () == 1
diff --git a/binutils-2.19/ld/testsuite/ld-shared/symbolic.dat b/binutils-2.19/ld/testsuite/ld-shared/symbolic.dat
new file mode 100644
index 0000000..7146486
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-shared/symbolic.dat
@@ -0,0 +1,8 @@
+mainvar == 1
+overriddenvar == 2
+shlibvar1 == 3
+shlib_shlibvar1 () == 3
+shlib_shlibvar2 () == 4
+shlib_shlibcall () == 5
+main_called () == 6
+shlib_check () == 1
diff --git a/binutils-2.19/ld/testsuite/ld-shared/xcoff.dat b/binutils-2.19/ld/testsuite/ld-shared/xcoff.dat
new file mode 100644
index 0000000..a409d96
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-shared/xcoff.dat
@@ -0,0 +1,10 @@
+mainvar == 1
+overriddenvar == 2
+shlibvar1 == 3
+shlib_shlibvar1 () == 3
+shlib_shlibvar2 () == 4
+shlib_shlibcall () == 5
+main_called () == 6
+shlib_checkfunptr1 (shlib_shlibvar1) == 1
+shlib_getfunptr1 () == shlib_shlibvar1
+shlib_check () == 1
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/gotop32.dd b/binutils-2.19/ld/testsuite/ld-sparc/gotop32.dd
new file mode 100644
index 0000000..9f6b1f6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/gotop32.dd
@@ -0,0 +1,28 @@
+#source: gotop32.s
+#as: --32 -K PIC
+#ld: -shared -melf32_sparc
+#objdump: -drj.text
+#target: sparc*-*-*
+
+.*: +file format elf32-sparc
+
+Disassembly of section .text:
+00001000 <foo-0x8>:
+ +1000:	81 c3 e0 08 	retl *
+ +1004:	ae 03 c0 17 	add  %o7, %l7, %l7
+
+00001008 <foo>:
+ +1008:	9d e3 bf 98 	save  %sp, -104, %sp
+ +100c:	2f 00 00 44 	sethi  %hi\(0x11000\), %l7
+ +1010:	7f ff ff fc 	call  1000 <_.*>
+ +1014:	ae 05 e0 60 	add  %l7, 0x60, %l7	! 11060 <.*>
+ +1018:	01 00 00 00 	nop *
+ +101c:	23 00 00 04 	sethi  %hi\(0x1000\), %l1
+ +1020:	01 00 00 00 	nop *
+ +1024:	a2 1c 60 04 	xor  %l1, 4, %l1
+ +1028:	01 00 00 00 	nop *
+ +102c:	f0 05 c0 11 	ld  \[ %l7 \+ %l1 \], %i0
+ +1030:	01 00 00 00 	nop *
+ +1034:	81 c7 e0 08 	ret 
+ +1038:	81 e8 00 00 	restore 
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/gotop32.rd b/binutils-2.19/ld/testsuite/ld-sparc/gotop32.rd
new file mode 100644
index 0000000..e4b4295
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/gotop32.rd
@@ -0,0 +1,70 @@
+#source: gotop32.s
+#as: --32 -K PIC
+#ld: -shared -melf32_sparc
+#readelf: -WSsrl
+#target: sparc*-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+ +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .text +PROGBITS +0+1000 0+1000 0+1000 0+ +AX +0 +0 4096
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+12000 0+2000 0+70 08 +WA +3 +0 +4
+ +\[[ 0-9]+\] .got +PROGBITS +0+12070 0+2070 0+8 04 +WA +0 +0 +4
+ +\[[ 0-9]+\] .data +PROGBITS +0+13000 0+3000 0+1000 00 +WA +0 +0 4096
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+#...
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x1000
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz MemSiz +Flg Align
+ +LOAD +0x0+ 0x0+ 0x0+ 0x0+2000 0x0+2000 R E 0x10000
+ +LOAD +0x0+2000 0x0+12000 0x0+12000 0x0+2000 0x0+2000 RW +0x10000
+ +DYNAMIC +0x0+2000 0x0+12000 0x0+12000 0x0+70 0x0+70 RW +0x4
+#...
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 1 entries:
+ Offset +Info +Type +Sym. Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_SPARC_GLOB_DAT +0+13000 +sym \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +5 *
+.* SECTION LOCAL +DEFAULT +7 *
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* FUNC +GLOBAL DEFAULT +5 foo
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* NOTYPE +GLOBAL DEFAULT +8 sym
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +1 *
+.* SECTION LOCAL +DEFAULT +2 *
+.* SECTION LOCAL +DEFAULT +3 *
+.* SECTION LOCAL +DEFAULT +4 *
+.* SECTION LOCAL +DEFAULT +5 *
+.* SECTION LOCAL +DEFAULT +6 *
+.* SECTION LOCAL +DEFAULT +7 *
+.* SECTION LOCAL +DEFAULT +8 *
+.* OBJECT +LOCAL +HIDDEN +ABS _DYNAMIC
+.* OBJECT +LOCAL +HIDDEN +ABS _PROCEDURE_LINKAGE_TABLE_
+.* OBJECT +LOCAL +HIDDEN +ABS _GLOBAL_OFFSET_TABLE_
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* FUNC +GLOBAL DEFAULT +5 foo
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* NOTYPE +GLOBAL DEFAULT +8 sym
+
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/gotop32.s b/binutils-2.19/ld/testsuite/ld-sparc/gotop32.s
new file mode 100644
index 0000000..ac01d6f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/gotop32.s
@@ -0,0 +1,28 @@
+	.data
+	.align	4096
+	.globl	sym
+sym:	.word	0x12345678
+
+	.text
+	.align	4096
+.LLGETPC0:
+	retl
+	add	%o7, %l7, %l7
+
+	.globl	foo
+	.type	foo,#function
+	.proc	04
+foo:
+	save	%sp, -104, %sp
+	sethi	%hi(_GLOBAL_OFFSET_TABLE_-4), %l7
+	call	.LLGETPC0
+	add	%l7, %lo(_GLOBAL_OFFSET_TABLE_+4), %l7
+	nop
+	sethi	%gdop_hix22(sym), %l1
+	nop
+	xor	%l1, %gdop_lox10(sym), %l1
+	nop
+	ld	[%l7 + %l1], %i0, %gdop(sym)
+	nop
+	ret
+	restore
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/gotop32.sd b/binutils-2.19/ld/testsuite/ld-sparc/gotop32.sd
new file mode 100644
index 0000000..fc16756
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/gotop32.sd
@@ -0,0 +1,10 @@
+#source: gotop32.s
+#as: --32 -K PIC
+#ld: -shared -melf32_sparc
+#objdump: -sj.got
+#target: sparc*-*-*
+
+.*: +file format elf32-sparc
+
+Contents of section .got:
+ 12070 00012000 00000000                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/gotop32.td b/binutils-2.19/ld/testsuite/ld-sparc/gotop32.td
new file mode 100644
index 0000000..e73482d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/gotop32.td
@@ -0,0 +1,12 @@
+#source: gotop32.s
+#as: --32 -K PIC
+#ld: -shared -melf32_sparc
+#objdump: -sj.data
+#target: sparc*-*-*
+
+.*: +file format elf32-sparc
+
+Contents of section .data:
+ 13000 12345678 00000000 00000000 00000000  .*
+ 13010 00000000 00000000 00000000 00000000  .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/gotop64.dd b/binutils-2.19/ld/testsuite/ld-sparc/gotop64.dd
new file mode 100644
index 0000000..a78f55a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/gotop64.dd
@@ -0,0 +1,28 @@
+#source: gotop64.s
+#as: --64 -K PIC
+#ld: -shared -melf64_sparc
+#objdump: -drj.text
+#target: sparc*-*-*
+
+.*: +file format elf64-sparc
+
+Disassembly of section .text:
+0000000000001000 <foo-0x8>:
+ +1000:	81 c3 e0 08 	retl *
+ +1004:	ae 03 c0 17 	add  %o7, %l7, %l7
+
+0000000000001008 <foo>:
+ +1008:	9d e3 bf 60 	save  %sp, -160, %sp
+ +100c:	2f 00 04 04 	sethi  %hi\(0x101000\), %l7
+ +1010:	7f ff ff fc 	call  1000 <_.*>
+ +1014:	ae 05 e0 d0 	add  %l7, 0xd0, %l7	! 1010d0 <.*>
+ +1018:	01 00 00 00 	nop *
+ +101c:	23 00 00 08 	sethi  %hi\(0x2000\), %l1
+ +1020:	01 00 00 00 	nop *
+ +1024:	a2 1c 60 08 	xor  %l1, 8, %l1
+ +1028:	01 00 00 00 	nop *
+ +102c:	f0 5d c0 11 	ldx  \[ %l7 \+ %l1 \], %i0
+ +1030:	01 00 00 00 	nop *
+ +1034:	81 c7 e0 08 	ret 
+ +1038:	81 e8 00 00 	restore 
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/gotop64.rd b/binutils-2.19/ld/testsuite/ld-sparc/gotop64.rd
new file mode 100644
index 0000000..24cf94f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/gotop64.rd
@@ -0,0 +1,70 @@
+#source: gotop64.s
+#as: --64 -K PIC
+#ld: -shared -melf64_sparc
+#readelf: -WSsrl
+#target: sparc*-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+ +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .text +PROGBITS +0+1000 0+1000 0+1000 0+ +AX +0 +0 4096
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+102000 0+2000 0+e0 10 +WA +3 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+1020e0 0+20e0 0+10 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .data +PROGBITS +0+103000 0+3000 0+1000 00 +WA +0 +0 4096
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+#...
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x1000
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+ +LOAD +0x0+ 0x0+ 0x0+ 0x0+2000 0x0+2000 R E 0x100000
+ +LOAD +0x0+2000 0x0+102000 0x0+102000 0x0+2000 0x0+2000 RW +0x100000
+ +DYNAMIC +0x0+2000 0x0+102000 0x0+102000 0x0+e0 0x0+e0 RW +0x8
+#...
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 1 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_SPARC_GLOB_DAT +0+103000 +sym \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +5 *
+.* SECTION LOCAL +DEFAULT +7 *
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* FUNC +GLOBAL DEFAULT +5 foo
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* NOTYPE +GLOBAL DEFAULT +8 sym
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +1 *
+.* SECTION LOCAL +DEFAULT +2 *
+.* SECTION LOCAL +DEFAULT +3 *
+.* SECTION LOCAL +DEFAULT +4 *
+.* SECTION LOCAL +DEFAULT +5 *
+.* SECTION LOCAL +DEFAULT +6 *
+.* SECTION LOCAL +DEFAULT +7 *
+.* SECTION LOCAL +DEFAULT +8 *
+.* OBJECT +LOCAL +HIDDEN +ABS _DYNAMIC
+.* OBJECT +LOCAL +HIDDEN +ABS _PROCEDURE_LINKAGE_TABLE_
+.* OBJECT +LOCAL +HIDDEN +ABS _GLOBAL_OFFSET_TABLE_
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* FUNC +GLOBAL DEFAULT +5 foo
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* NOTYPE +GLOBAL DEFAULT +8 sym
+
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/gotop64.s b/binutils-2.19/ld/testsuite/ld-sparc/gotop64.s
new file mode 100644
index 0000000..8a8ff82
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/gotop64.s
@@ -0,0 +1,28 @@
+	.data
+	.align	4096
+	.globl	sym
+sym:	.word	0x12345678
+
+	.text
+	.align	4096
+.LLGETPC0:
+	retl
+	add	%o7, %l7, %l7
+
+	.globl	foo
+	.type	foo,#function
+	.proc	04
+foo:
+	save	%sp, -160, %sp
+	sethi	%hi(_GLOBAL_OFFSET_TABLE_-4), %l7
+	call	.LLGETPC0
+	add	%l7, %lo(_GLOBAL_OFFSET_TABLE_+4), %l7
+	nop
+	sethi	%gdop_hix22(sym), %l1
+	nop
+	xor	%l1, %gdop_lox10(sym), %l1
+	nop
+	ldx	[%l7 + %l1], %i0, %gdop(sym)
+	nop
+	ret
+	restore
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/gotop64.sd b/binutils-2.19/ld/testsuite/ld-sparc/gotop64.sd
new file mode 100644
index 0000000..9ab0f61
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/gotop64.sd
@@ -0,0 +1,10 @@
+#source: gotop64.s
+#as: --64 -K PIC
+#ld: -shared -melf64_sparc
+#objdump: -sj.got
+#target: sparc*-*-*
+
+.*: +file format elf64-sparc
+
+Contents of section .got:
+ 1020e0 00000000 00102000 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/gotop64.td b/binutils-2.19/ld/testsuite/ld-sparc/gotop64.td
new file mode 100644
index 0000000..f16cf50
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/gotop64.td
@@ -0,0 +1,12 @@
+#source: gotop64.s
+#as: --64 -K PIC
+#ld: -shared -melf64_sparc
+#objdump: -sj.data
+#target: sparc*-*-*
+
+.*: +file format elf64-sparc
+
+Contents of section .data:
+ 103000 12345678 00000000 00000000 00000000  .*
+ 103010 00000000 00000000 00000000 00000000  .*
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/sparc.exp b/binutils-2.19/ld/testsuite/ld-sparc/sparc.exp
new file mode 100644
index 0000000..e41dfe5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/sparc.exp
@@ -0,0 +1,135 @@
+# Expect script for ld-sparc tests
+#   Copyright (C) 2002, 2003, 2005, 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Test SPARC linking; all types of relocs.  This tests the assembler and
+# tools like objdump as well as the linker.
+
+if {[istarget "sparc-*-vxworks"]} {
+    set sparcvxworkstests {
+	{"VxWorks shared library test 1" "-shared -Tvxworks1.ld"
+	 "-KPIC" {vxworks1-lib.s}
+	 {{readelf --relocs vxworks1-lib.rd} {objdump -dr vxworks1-lib.dd}
+	  {readelf --symbols vxworks1-lib.nd} {readelf -d vxworks1-lib.td}}
+	 "libvxworks1.so"}
+	{"VxWorks executable test 1 (dynamic)" \
+	 "tmpdir/libvxworks1.so -Tvxworks1.ld -q --force-dynamic"
+	 "" {vxworks1.s}
+	 {{readelf --relocs vxworks1.rd} {objdump -dr vxworks1.dd}}
+	 "vxworks1"}
+	{"VxWorks executable test 2 (dynamic)" \
+	 "-Tvxworks1.ld -q --force-dynamic"
+	 "" {vxworks2.s}
+	 {{readelf --segments vxworks2.sd}}
+	 "vxworks2"}
+	{"VxWorks executable test 2 (static)"
+	 "-Tvxworks1.ld"
+	 "" {vxworks2.s}
+	 {{readelf --segments vxworks2-static.sd}}
+	 "vxworks2"}
+    }
+    run_ld_link_tests $sparcvxworkstests
+    run_dump_test "vxworks1-static"
+}
+
+if { !([istarget "sparc*-*-elf*"]
+       || [istarget "sparc*-sun-solaris*"]
+       || ([istarget "sparc*-*-linux*"]
+	   && ![istarget "*-*-*aout*"]
+	   && ![istarget "*-*-*oldld*"])) } {
+    return
+}
+
+# List contains test-items with 3 items followed by 2 lists:
+# 0:name 1:ld options 2:assembler options
+# 3:filenames of assembler files 4: action and options. 5: name of output file
+
+# Actions:
+# objdump: Apply objdump options on result.  Compare with regex (last arg).
+# nm: Apply nm options on result.  Compare with regex (last arg).
+# readelf: Apply readelf options on result.  Compare with regex (last arg).
+
+set sparctests {
+    {"32-bit: TLS -fpic -shared transitions" "-shared -melf32_sparc"
+     "--32 -K PIC" {tlssunpic32.s tlspic.s}
+     {{readelf -WSsrl tlssunpic32.rd} {objdump -drj.text tlssunpic32.dd}
+      {objdump -sj.got tlssunpic32.sd} {objdump -sj.tdata tlssunpic32.td}}
+      "libtlssunpic32.so"}
+    {"32-bit: Helper shared library" "-shared -melf32_sparc"
+     "--32 -K PIC" {tlslib.s} {} "libtlslib32.so"}
+    {"32-bit: Another helper shared library" "-shared -melf32_sparc"
+     "--32 -K PIC" {tlssunbinpic32.s} {} "libtlssunbinpic32.so"}
+    {"32-bit: TLS -fpic and -fno-pic exec transitions"
+     "-melf32_sparc tmpdir/libtlslib32.so tmpdir/tlssunbinpic32.o"
+     "--32" {tlssunbin32.s}
+     {{readelf -WSsrl tlssunbin32.rd} {objdump -drj.text tlssunbin32.dd}
+      {objdump -sj.got tlssunbin32.sd} {objdump -sj.tdata tlssunbin32.td}}
+      "tlssunbin32"}
+    {"32-bit: TLS -fno-pic -shared" "-shared -melf32_sparc"
+     "--32" {tlssunnopic32.s tlsnopic.s}
+     {{readelf -WSsrl tlssunnopic32.rd} {objdump -drj.text tlssunnopic32.dd}
+      {objdump -sj.got tlssunnopic32.sd}} "libtlssunnopic32.so"}
+    {"32-bit: TLS in debug sections" "-melf32_sparc"
+     "--32" {tlsg32.s}
+     {{objdump -sj.debug_foobar tlsg32.sd}} "tlsg32"}
+    {"32-bit: GOTDATA relocations" "-shared -melf32_sparc"
+     "--32 -K PIC" {gotop32.s}
+     {{readelf -WSsrl gotop32.rd} {objdump -drj.text gotop32.dd}
+      {objdump -sj.got gotop32.sd} {objdump -sj.data gotop32.td}}
+     "libgotop32.so"}
+}
+set sparc64tests {
+    {"64-bit: TLS -fpic -shared transitions" "-shared -melf64_sparc"
+     "--64 -Av9 -K PIC" {tlssunpic64.s tlspic.s}
+     {{readelf -WSsrl tlssunpic64.rd} {objdump -drj.text tlssunpic64.dd}
+      {objdump -sj.got tlssunpic64.sd} {objdump -sj.tdata tlssunpic64.td}}
+      "libtlssunpic64.so"}
+    {"64-bit: Helper shared library" "-shared -melf64_sparc"
+     "--64 -Av9 -K PIC" {tlslib.s} {} "libtlslib64.so"}
+    {"64-bit: Another helper shared library" "-shared -melf64_sparc"
+     "--64 -Av9 -K PIC" {tlssunbinpic64.s} {} "libtlssunbinpic64.so"}
+    {"64-bit: TLS -fpic and -fno-pic exec transitions"
+     "-melf64_sparc tmpdir/libtlslib64.so tmpdir/tlssunbinpic64.o"
+     "--64 -Av9" {tlssunbin64.s}
+     {{readelf -WSsrl tlssunbin64.rd} {objdump -drj.text tlssunbin64.dd}
+      {objdump -sj.got tlssunbin64.sd} {objdump -sj.tdata tlssunbin64.td}}
+      "tlssunbin64"}
+    {"64-bit: TLS -fno-pic -shared" "-shared -melf64_sparc"
+     "--64 -Av9" {tlssunnopic64.s tlsnopic.s}
+     {{readelf -WSsrl tlssunnopic64.rd} {objdump -drj.text tlssunnopic64.dd}
+      {objdump -sj.got tlssunnopic64.sd}} "libtlssunnopic64.so"}
+    {"64-bit: TLS in debug sections" "-melf64_sparc"
+     "--64 -Av9" {tlsg64.s}
+     {{objdump -sj.debug_foobar tlsg64.sd}} "tlsg64"}
+    {"64-bit: GOTDATA relocations" "-shared -melf64_sparc"
+     "--64 -K PIC" {gotop64.s}
+     {{readelf -WSsrl gotop64.rd} {objdump -drj.text gotop64.dd}
+      {objdump -sj.got gotop64.sd} {objdump -sj.data gotop64.td}}
+     "libgotop64.so"}
+}
+
+if { ![istarget "sparc64-*-elf*"] } {
+    run_ld_link_tests $sparctests
+}
+if { !([istarget "sparc-*-elf*"]
+       || [istarget "sparc-sun-solaris2.5*"]
+       || [istarget "sparc-sun-solaris2.6"]) } {
+    run_ld_link_tests $sparc64tests
+}
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlsg32.s b/binutils-2.19/ld/testsuite/ld-sparc/tlsg32.s
new file mode 100644
index 0000000..0339f50
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlsg32.s
@@ -0,0 +1,12 @@
+	.section .tbss
+	.align	4
+	.word	0, 0, 0, 0, 0, 0
+	.type	a,#tls_object
+	.size	a,4
+a:
+	.word	0
+	.text
+	.globl	_start
+_start:
+	.section .debug_foobar
+	.word	%r_tls_dtpoff32(a)
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlsg32.sd b/binutils-2.19/ld/testsuite/ld-sparc/tlsg32.sd
new file mode 100644
index 0000000..861ac2e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlsg32.sd
@@ -0,0 +1,10 @@
+#source: tlsg.s
+#as: --32
+#ld: -melf32_sparc
+#objdump: -sj.debug_foobar
+#target: sparc*-*-*
+
+.*: +file format elf32-sparc
+
+Contents of section .debug_foobar:
+ 0+ 0+18  .*
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlsg64.s b/binutils-2.19/ld/testsuite/ld-sparc/tlsg64.s
new file mode 100644
index 0000000..4419974
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlsg64.s
@@ -0,0 +1,12 @@
+	.section .tbss
+	.align	4
+	.word	0, 0, 0, 0, 0, 0
+	.type	a,#tls_object
+	.size	a,4
+a:
+	.word	0
+	.text
+	.globl	_start
+_start:
+	.section .debug_foobar
+	.xword	%r_tls_dtpoff64(a)
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlsg64.sd b/binutils-2.19/ld/testsuite/ld-sparc/tlsg64.sd
new file mode 100644
index 0000000..4181dde
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlsg64.sd
@@ -0,0 +1,10 @@
+#source: tlsg.s
+#as: --64 -Av9
+#ld: -melf64_sparc
+#objdump: -sj.debug_foobar
+#target: sparc*-*-*
+
+.*: +file format elf64-sparc
+
+Contents of section .debug_foobar:
+ 0+ 0+ 0+18  .*
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlslib.s b/binutils-2.19/ld/testsuite/ld-sparc/tlslib.s
new file mode 100644
index 0000000..6b62e09
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlslib.s
@@ -0,0 +1,20 @@
+	.section ".tdata", #alloc, #write, #tls
+	.align	4
+	.globl sG1, sG2, sG3, sG4, sG5, sG6, sG7, sG8
+sG1:	.word 513
+sG2:	.word 514
+sG3:	.word 515
+sG4:	.word 516
+sG5:	.word 517
+sG6:	.word 518
+sG7:	.word 519
+sG8:	.word 520
+
+	.text
+	/* Dummy.  */
+	.globl	__tls_get_addr
+	.type   __tls_get_addr,#function
+	.proc	04
+__tls_get_addr:
+	ret
+	restore
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlsnopic.s b/binutils-2.19/ld/testsuite/ld-sparc/tlsnopic.s
new file mode 100644
index 0000000..648660a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlsnopic.s
@@ -0,0 +1,8 @@
+	.section ".tbss"
+	.align	4
+	.globl sh1, sh2, sh3, sh4
+	.hidden sh1, sh2, sh3, sh4
+sh1:	.word 0
+sh2:	.word 0
+sh3:	.word 0
+sh4:	.word 0
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlspic.s b/binutils-2.19/ld/testsuite/ld-sparc/tlspic.s
new file mode 100644
index 0000000..7c806d0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlspic.s
@@ -0,0 +1,12 @@
+	.section ".tbss"
+	.align	4
+	.globl sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+	.hidden sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+sH1:	.word 0
+sH2:	.word 0
+sH3:	.word 0
+sH4:	.word 0
+sH5:	.word 0
+sH6:	.word 0
+sH7:	.word 0
+sH8:	.word 0
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin32.dd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin32.dd
new file mode 100644
index 0000000..37c1d04
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin32.dd
@@ -0,0 +1,273 @@
+#source: tlssunbin32.s
+#as: --32
+#ld: -shared -melf32_sparc tmpdir/libtlslib32.so tmpdir/tlssunbinpic32.o
+#objdump: -drj.text
+#target: sparc*-*-*
+
+.*: +file format elf32-sparc
+
+Disassembly of section .text:
+
+0+11000 <fn2-0x8>:
+ +11000:	81 c3 e0 08 	retl *
+ +11004:	ae 03 c0 17 	add  %o7, %l7, %l7
+
+0+11008 <fn2>:
+ +11008:	9d e3 bf 98 	save  %sp, -104, %sp
+ +1100c:	2f 00 00 48 	sethi  %hi\(0x12000\), %l7
+ +11010:	7f ff ff fc 	call  11000 <.*>
+ +11014:	ae 05 e2 64 	add  %l7, 0x264, %l7	! 12264 <.*>
+ +11018:	01 00 00 00 	nop *
+ +1101c:	01 00 00 00 	nop *
+ +11020:	01 00 00 00 	nop *
+ +11024:	01 00 00 00 	nop *
+ +11028:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +1102c:	01 00 00 00 	nop *
+ +11030:	a4 04 60 10 	add  %l1, 0x10, %l2
+ +11034:	01 00 00 00 	nop *
+ +11038:	d0 05 c0 12 	ld  \[ %l7 \+ %l2 \], %o0
+ +1103c:	01 00 00 00 	nop *
+ +11040:	90 01 c0 08 	add  %g7, %o0, %o0
+ +11044:	01 00 00 00 	nop *
+ +11048:	01 00 00 00 	nop *
+ +1104c:	01 00 00 00 	nop *
+ +11050:	01 00 00 00 	nop *
+ +11054:	01 00 00 00 	nop *
+ +11058:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +1105c:	92 02 20 08 	add  %o0, 8, %o1	! 8 <.*>
+ +11060:	d0 05 c0 09 	ld  \[ %l7 \+ %o1 \], %o0
+ +11064:	90 01 c0 08 	add  %g7, %o0, %o0
+ +11068:	01 00 00 00 	nop *
+ +1106c:	01 00 00 00 	nop *
+ +11070:	01 00 00 00 	nop *
+ +11074:	01 00 00 00 	nop *
+ +11078:	01 00 00 00 	nop *
+ +1107c:	21 00 00 04 	sethi  %hi\(0x1000\), %l0
+ +11080:	aa 1c 3f 60 	xor  %l0, -160, %l5
+ +11084:	90 01 c0 15 	add  %g7, %l5, %o0
+ +11088:	01 00 00 00 	nop *
+ +1108c:	01 00 00 00 	nop *
+ +11090:	01 00 00 00 	nop *
+ +11094:	01 00 00 00 	nop *
+ +11098:	01 00 00 00 	nop *
+ +1109c:	01 00 00 00 	nop *
+ +110a0:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +110a4:	92 1a 3f 80 	xor  %o0, -128, %o1
+ +110a8:	90 01 c0 09 	add  %g7, %o1, %o0
+ +110ac:	01 00 00 00 	nop *
+ +110b0:	01 00 00 00 	nop *
+ +110b4:	01 00 00 00 	nop *
+ +110b8:	01 00 00 00 	nop *
+ +110bc:	01 00 00 00 	nop *
+ +110c0:	01 00 00 00 	nop *
+ +110c4:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +110c8:	92 1a 3f a0 	xor  %o0, -96, %o1
+ +110cc:	90 01 c0 09 	add  %g7, %o1, %o0
+ +110d0:	01 00 00 00 	nop *
+ +110d4:	01 00 00 00 	nop *
+ +110d8:	01 00 00 00 	nop *
+ +110dc:	01 00 00 00 	nop *
+ +110e0:	01 00 00 00 	nop *
+ +110e4:	01 00 00 00 	nop *
+ +110e8:	01 00 00 00 	nop *
+ +110ec:	01 00 00 00 	nop *
+ +110f0:	01 00 00 00 	nop *
+ +110f4:	01 00 00 00 	nop *
+ +110f8:	01 00 00 00 	nop *
+ +110fc:	01 00 00 00 	nop *
+ +11100:	90 10 00 00 	mov  %g0, %o0
+ +11104:	01 00 00 00 	nop *
+ +11108:	27 00 00 00 	sethi  %hi\(0\), %l3
+ +1110c:	01 00 00 00 	nop *
+ +11110:	a8 1c ff 80 	xor  %l3, -128, %l4
+ +11114:	01 00 00 00 	nop *
+ +11118:	aa 01 c0 14 	add  %g7, %l4, %l5
+ +1111c:	01 00 00 00 	nop *
+ +11120:	25 00 00 00 	sethi  %hi\(0\), %l2
+ +11124:	01 00 00 00 	nop *
+ +11128:	a6 1c bf 86 	xor  %l2, -122, %l3
+ +1112c:	01 00 00 00 	nop *
+ +11130:	ec 11 c0 13 	lduh  \[ %g7 \+ %l3 \], %l6
+ +11134:	01 00 00 00 	nop *
+ +11138:	01 00 00 00 	nop *
+ +1113c:	01 00 00 00 	nop *
+ +11140:	01 00 00 00 	nop *
+ +11144:	01 00 00 00 	nop *
+ +11148:	27 00 00 00 	sethi  %hi\(0\), %l3
+ +1114c:	01 00 00 00 	nop *
+ +11150:	25 00 00 00 	sethi  %hi\(0\), %l2
+ +11154:	01 00 00 00 	nop *
+ +11158:	a8 1c ff a0 	xor  %l3, -96, %l4
+ +1115c:	90 10 00 00 	mov  %g0, %o0
+ +11160:	a6 1c bf a5 	xor  %l2, -91, %l3
+ +11164:	aa 01 c0 14 	add  %g7, %l4, %l5
+ +11168:	ec 09 c0 13 	ldub  \[ %g7 \+ %l3 \], %l6
+ +1116c:	01 00 00 00 	nop *
+ +11170:	01 00 00 00 	nop *
+ +11174:	01 00 00 00 	nop *
+ +11178:	01 00 00 00 	nop *
+ +1117c:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +11180:	01 00 00 00 	nop *
+ +11184:	a4 04 60 08 	add  %l1, 8, %l2
+ +11188:	01 00 00 00 	nop *
+ +1118c:	e4 05 c0 12 	ld  \[ %l7 \+ %l2 \], %l2
+ +11190:	01 00 00 00 	nop *
+ +11194:	a4 01 c0 12 	add  %g7, %l2, %l2
+ +11198:	01 00 00 00 	nop *
+ +1119c:	01 00 00 00 	nop *
+ +111a0:	01 00 00 00 	nop *
+ +111a4:	01 00 00 00 	nop *
+ +111a8:	17 00 00 04 	sethi  %hi\(0x1000\), %o3
+ +111ac:	96 1a ff 60 	xor  %o3, -160, %o3
+ +111b0:	01 00 00 00 	nop *
+ +111b4:	98 01 c0 0b 	add  %g7, %o3, %o4
+ +111b8:	01 00 00 00 	nop *
+ +111bc:	01 00 00 00 	nop *
+ +111c0:	01 00 00 00 	nop *
+ +111c4:	01 00 00 00 	nop *
+ +111c8:	29 00 00 00 	sethi  %hi\(0\), %l4
+ +111cc:	a2 1d 3f 80 	xor  %l4, -128, %l1
+ +111d0:	a6 10 00 11 	mov  %l1, %l3
+ +111d4:	a6 01 c0 13 	add  %g7, %l3, %l3
+ +111d8:	01 00 00 00 	nop *
+ +111dc:	01 00 00 00 	nop *
+ +111e0:	01 00 00 00 	nop *
+ +111e4:	01 00 00 00 	nop *
+ +111e8:	13 00 00 00 	sethi  %hi\(0\), %o1
+ +111ec:	96 1a 7f a0 	xor  %o1, -96, %o3
+ +111f0:	90 10 00 0b 	mov  %o3, %o0
+ +111f4:	96 01 c0 08 	add  %g7, %o0, %o3
+ +111f8:	01 00 00 00 	nop *
+ +111fc:	01 00 00 00 	nop *
+ +11200:	01 00 00 00 	nop *
+ +11204:	01 00 00 00 	nop *
+ +11208:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +1120c:	96 02 e0 04 	add  %o3, 4, %o3	! 4 <.*>
+ +11210:	d4 05 c0 0b 	ld  \[ %l7 \+ %o3 \], %o2
+ +11214:	d8 01 c0 0a 	ld  \[ %g7 \+ %o2 \], %o4
+ +11218:	01 00 00 00 	nop *
+ +1121c:	01 00 00 00 	nop *
+ +11220:	01 00 00 00 	nop *
+ +11224:	01 00 00 00 	nop *
+ +11228:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +1122c:	96 1a ff 90 	xor  %o3, -112, %o3
+ +11230:	94 10 00 0b 	mov  %o3, %o2
+ +11234:	d8 29 c0 0a 	stb  %o4, \[ %g7 \+ %o2 \]
+ +11238:	01 00 00 00 	nop *
+ +1123c:	01 00 00 00 	nop *
+ +11240:	01 00 00 00 	nop *
+ +11244:	01 00 00 00 	nop *
+ +11248:	1b 00 00 00 	sethi  %hi\(0\), %o5
+ +1124c:	96 1b 7f b0 	xor  %o5, -80, %o3
+ +11250:	94 10 00 0b 	mov  %o3, %o2
+ +11254:	d8 49 c0 0a 	ldsb  \[ %g7 \+ %o2 \], %o4
+ +11258:	01 00 00 00 	nop *
+ +1125c:	01 00 00 00 	nop *
+ +11260:	01 00 00 00 	nop *
+ +11264:	01 00 00 00 	nop *
+ +11268:	81 c7 e0 08 	ret *
+ +1126c:	81 e8 00 00 	restore *
+#...
+
+00012000 <_start>:
+ +12000:	9d e3 bf 98 	save  %sp, -104, %sp
+ +12004:	29 00 00 8c 	sethi  %hi\(0x23000\), %l4
+ +12008:	a8 15 22 74 	or  %l4, 0x274, %l4	! 23274 <.*>
+ +1200c:	01 00 00 00 	nop *
+ +12010:	01 00 00 00 	nop *
+ +12014:	01 00 00 00 	nop *
+ +12018:	01 00 00 00 	nop *
+ +1201c:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +12020:	96 02 e0 0c 	add  %o3, 0xc, %o3	! c <.*>
+ +12024:	d4 05 00 0b 	ld  \[ %l4 \+ %o3 \], %o2
+ +12028:	98 01 c0 0a 	add  %g7, %o2, %o4
+ +1202c:	01 00 00 00 	nop *
+ +12030:	01 00 00 00 	nop *
+ +12034:	01 00 00 00 	nop *
+ +12038:	01 00 00 00 	nop *
+ +1203c:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +12040:	9a 1a ff d4 	xor  %o3, -44, %o5
+ +12044:	94 10 00 0d 	mov  %o5, %o2
+ +12048:	98 01 c0 0a 	add  %g7, %o2, %o4
+ +1204c:	01 00 00 00 	nop *
+ +12050:	01 00 00 00 	nop *
+ +12054:	01 00 00 00 	nop *
+ +12058:	01 00 00 00 	nop *
+ +1205c:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +12060:	9a 1a ff f4 	xor  %o3, -12, %o5
+ +12064:	a4 10 00 0d 	mov  %o5, %l2
+ +12068:	a4 01 c0 12 	add  %g7, %l2, %l2
+ +1206c:	01 00 00 00 	nop *
+ +12070:	01 00 00 00 	nop *
+ +12074:	01 00 00 00 	nop *
+ +12078:	01 00 00 00 	nop *
+ +1207c:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +12080:	9a 1a ff fc 	xor  %o3, -4, %o5
+ +12084:	a4 10 00 0d 	mov  %o5, %l2
+ +12088:	e4 01 c0 12 	ld  \[ %g7 \+ %l2 \], %l2
+ +1208c:	01 00 00 00 	nop *
+ +12090:	01 00 00 00 	nop *
+ +12094:	01 00 00 00 	nop *
+ +12098:	01 00 00 00 	nop *
+ +1209c:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +120a0:	9a 1a ff b4 	xor  %o3, -76, %o5
+ +120a4:	a4 10 00 0d 	mov  %o5, %l2
+ +120a8:	a4 01 c0 12 	add  %g7, %l2, %l2
+ +120ac:	01 00 00 00 	nop *
+ +120b0:	01 00 00 00 	nop *
+ +120b4:	01 00 00 00 	nop *
+ +120b8:	01 00 00 00 	nop *
+ +120bc:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +120c0:	9a 1a ff fc 	xor  %o3, -4, %o5
+ +120c4:	a4 10 00 0d 	mov  %o5, %l2
+ +120c8:	e2 29 c0 12 	stb  %l1, \[ %g7 \+ %l2 \]
+ +120cc:	01 00 00 00 	nop *
+ +120d0:	01 00 00 00 	nop *
+ +120d4:	01 00 00 00 	nop *
+ +120d8:	01 00 00 00 	nop *
+ +120dc:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +120e0:	01 00 00 00 	nop *
+ +120e4:	a4 1c 7f 64 	xor  %l1, -156, %l2
+ +120e8:	01 00 00 00 	nop *
+ +120ec:	a6 01 c0 12 	add  %g7, %l2, %l3
+ +120f0:	01 00 00 00 	nop *
+ +120f4:	01 00 00 00 	nop *
+ +120f8:	01 00 00 00 	nop *
+ +120fc:	01 00 00 00 	nop *
+ +12100:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +12104:	90 1a 3f e6 	xor  %o0, -26, %o0
+ +12108:	90 01 c0 08 	add  %g7, %o0, %o0
+ +1210c:	01 00 00 00 	nop *
+ +12110:	01 00 00 00 	nop *
+ +12114:	01 00 00 00 	nop *
+ +12118:	01 00 00 00 	nop *
+ +1211c:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +12120:	9a 1c 7f a5 	xor  %l1, -91, %o5
+ +12124:	92 01 c0 0d 	add  %g7, %o5, %o1
+ +12128:	01 00 00 00 	nop *
+ +1212c:	01 00 00 00 	nop *
+ +12130:	01 00 00 00 	nop *
+ +12134:	01 00 00 00 	nop *
+ +12138:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +1213c:	9a 1c 7f 68 	xor  %l1, -152, %o5
+ +12140:	d2 01 c0 0d 	ld  \[ %g7 \+ %o5 \], %o1
+ +12144:	01 00 00 00 	nop *
+ +12148:	01 00 00 00 	nop *
+ +1214c:	01 00 00 00 	nop *
+ +12150:	01 00 00 00 	nop *
+ +12154:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +12158:	90 1a 3f eb 	xor  %o0, -21, %o0
+ +1215c:	d2 29 c0 08 	stb  %o1, \[ %g7 \+ %o0 \]
+ +12160:	01 00 00 00 	nop *
+ +12164:	01 00 00 00 	nop *
+ +12168:	01 00 00 00 	nop *
+ +1216c:	01 00 00 00 	nop *
+ +12170:	15 00 00 00 	sethi  %hi\(0\), %o2
+ +12174:	98 1a bf ab 	xor  %o2, -85, %o4
+ +12178:	da 69 c0 0c 	ldstub  \[ %g7 \+ %o4 \], %o5
+ +1217c:	01 00 00 00 	nop *
+ +12180:	01 00 00 00 	nop *
+ +12184:	01 00 00 00 	nop *
+ +12188:	01 00 00 00 	nop *
+ +1218c:	81 c7 e0 08 	ret *
+ +12190:	81 e8 00 00 	restore *
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin32.rd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin32.rd
new file mode 100644
index 0000000..3af973e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin32.rd
@@ -0,0 +1,126 @@
+#source: tlssunbin32.s
+#as: --32
+#ld: -shared -melf32_sparc tmpdir/libtlslib32.so tmpdir/tlssunbinpic32.o
+#readelf: -WSsrl
+#target: sparc*-*-*
+
+.*
+
+Section Headers:
+ +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0
+ +\[[ 0-9]+\] .interp +.*
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .text +PROGBITS +0+11000 0+1000 0+1194 00 +AX +0 +0 4096
+ +\[[ 0-9]+\] .tdata +PROGBITS +0+22194 0+2194 0+1060 00 WAT +0 +0 +4
+ +\[[ 0-9]+\] .tbss +NOBITS +0+231f4 0+31f4 0+40 00 WAT +0 +0 +4
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+231f4 0+31f4 0+80 08 +WA +4 +0 +4
+ +\[[ 0-9]+\] .got +PROGBITS +0+23274 0+3274 0+14 04 +WA +0 +0 +4
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+#...
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x12000
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz MemSiz +Flg Align
+ +PHDR +0x0+34 0x0+10034 0x0+10034 0x0+c0 0x0+c0 R E 0x4
+ +INTERP +0x0+f4 0x0+100f4 0x0+100f4 0x0+11 0x0+11 R +0x1
+.*Requesting program interpreter.*
+ +LOAD .* R E 0x10000
+ +LOAD .* RW +0x10000
+ +DYNAMIC .* RW +0x4
+ +TLS .* 0x0+1060 0x0+10a0 R +0x4
+#...
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
+ Offset +Info +Type +Sym. Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +00000000 +sG5 \+ 0
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +00000000 +sG2 \+ 0
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +00000000 +sG6 \+ 0
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +00000000 +sG1 \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* TLS +GLOBAL DEFAULT +UND sG5
+.* TLS +GLOBAL DEFAULT +UND sG2
+.* FUNC +GLOBAL DEFAULT +UND __tls_get_addr
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +UND sG6
+.* TLS +GLOBAL DEFAULT +UND sG1
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +1 *
+.* SECTION LOCAL +DEFAULT +2 *
+.* SECTION LOCAL +DEFAULT +3 *
+.* SECTION LOCAL +DEFAULT +4 *
+.* SECTION LOCAL +DEFAULT +5 *
+.* SECTION LOCAL +DEFAULT +6 *
+.* SECTION LOCAL +DEFAULT +7 *
+.* SECTION LOCAL +DEFAULT +8 *
+.* SECTION LOCAL +DEFAULT +9 *
+.* SECTION LOCAL +DEFAULT +10 *
+.* TLS +LOCAL +DEFAULT +7 sl1
+.* TLS +LOCAL +DEFAULT +7 sl2
+.* TLS +LOCAL +DEFAULT +7 sl3
+.* TLS +LOCAL +DEFAULT +7 sl4
+.* TLS +LOCAL +DEFAULT +7 sl5
+.* TLS +LOCAL +DEFAULT +7 sl6
+.* TLS +LOCAL +DEFAULT +7 sl7
+.* TLS +LOCAL +DEFAULT +7 sl8
+.* TLS +LOCAL +DEFAULT +8 bl1
+.* TLS +LOCAL +DEFAULT +8 bl2
+.* TLS +LOCAL +DEFAULT +8 bl3
+.* TLS +LOCAL +DEFAULT +8 bl4
+.* TLS +LOCAL +DEFAULT +8 bl5
+.* TLS +LOCAL +DEFAULT +8 bl6
+.* TLS +LOCAL +DEFAULT +8 bl7
+.* TLS +LOCAL +DEFAULT +8 bl8
+.* OBJECT +LOCAL +HIDDEN +9 _DYNAMIC
+.* OBJECT +LOCAL +HIDDEN +10 _PROCEDURE_LINKAGE_TABLE_
+.* OBJECT +LOCAL +HIDDEN +10 _GLOBAL_OFFSET_TABLE_
+.* TLS +GLOBAL DEFAULT +7 sg8
+.* TLS +GLOBAL DEFAULT +8 bg8
+.* TLS +GLOBAL DEFAULT +8 bg6
+.* TLS +GLOBAL DEFAULT +UND sG5
+.* TLS +GLOBAL DEFAULT +8 bg3
+.* TLS +GLOBAL DEFAULT +7 sg3
+.* TLS +GLOBAL HIDDEN +7 sh3
+.* TLS +GLOBAL DEFAULT +UND sG2
+.* TLS +GLOBAL DEFAULT +7 sg4
+.* TLS +GLOBAL DEFAULT +7 sg5
+.* TLS +GLOBAL DEFAULT +8 bg5
+.* FUNC +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL HIDDEN +7 sh7
+.* TLS +GLOBAL HIDDEN +7 sh8
+.* TLS +GLOBAL DEFAULT +7 sg1
+.* FUNC +GLOBAL DEFAULT +6 _start
+.* TLS +GLOBAL HIDDEN +7 sh4
+.* TLS +GLOBAL DEFAULT +8 bg7
+.* TLS +GLOBAL HIDDEN +7 sh5
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +UND sG6
+.* FUNC +GLOBAL DEFAULT +6 fn2
+.* TLS +GLOBAL DEFAULT +7 sg2
+.* TLS +GLOBAL DEFAULT +UND sG1
+.* TLS +GLOBAL HIDDEN +7 sh1
+.* TLS +GLOBAL DEFAULT +7 sg6
+.* TLS +GLOBAL DEFAULT +7 sg7
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* TLS +GLOBAL HIDDEN +7 sh2
+.* TLS +GLOBAL HIDDEN +7 sh6
+.* TLS +GLOBAL DEFAULT +8 bg2
+.* TLS +GLOBAL DEFAULT +8 bg1
+.* TLS +GLOBAL DEFAULT +8 bg4
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin32.s b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin32.s
new file mode 100644
index 0000000..21716f3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin32.s
@@ -0,0 +1,114 @@
+	.section ".tbss"
+	.align	4
+	.globl bg1, bg2, bg3, bg4, bg5, bg6, bg7, bg8
+bg1:	.word 0
+bg2:	.word 0
+bg3:	.word 0
+bg4:	.word 0
+bg5:	.word 0
+bg6:	.word 0
+bg7:	.word 0
+bg8:	.word 0
+bl1:	.word 0
+bl2:	.word 0
+bl3:	.word 0
+bl4:	.word 0
+bl5:	.word 0
+bl6:	.word 0
+bl7:	.word 0
+bl8:	.word 0
+	.text
+	.globl	_start
+	.type	_start,#function
+	.proc	04
+_start:
+	save	%sp, -104, %sp
+	.hidden	_GLOBAL_OFFSET_TABLE_
+	sethi	%hi(_GLOBAL_OFFSET_TABLE_), %l4
+	or	%l4, %lo(_GLOBAL_OFFSET_TABLE_), %l4
+	nop;nop;nop;nop
+
+	/* IE against global var  */
+	sethi	%tie_hi22(sG6), %o3
+	add	%o3, %tie_lo10(sG6), %o3
+	ld	[%l4 + %o3], %o2, %tie_ld(sG6)
+	add	%g7, %o2, %o4, %tie_add(sG6)
+	nop;nop;nop;nop
+
+	/* IE -> LE against global var defined in exec  */
+	sethi	%tie_hi22(bg6), %o3
+	add	%o3, %tie_lo10(bg6), %o5
+	ld	[%l4 + %o5], %o2, %tie_ld(bg6)
+	add	%g7, %o2, %o4, %tie_add(bg6)
+	nop;nop;nop;nop
+
+	/* IE -> LE against local var  */
+	sethi	%tie_hi22(bl6), %o3
+	add	%o3, %tie_lo10(bl6), %o5
+	ld	[%l4 + %o5], %l2, %tie_ld(bl6)
+	add	%g7, %l2, %l2, %tie_add(bl6)
+	nop;nop;nop;nop
+
+	/* direct %g7 access IE -> LE against local var  */
+	sethi	%tie_hi22(bl8), %o3
+	add	%o3, %tie_lo10(bl8), %o5
+	ld	[%l4 + %o5], %l2, %tie_ld(bl8)
+	ld	[%g7 + %l2], %l2, %tie_add(bl8)
+	nop;nop;nop;nop
+
+	/* IE -> LE against hidden but not local var  */
+	sethi	%tie_hi22(sh6), %o3
+	add	%o3, %tie_lo10(sh6), %o5
+	ld	[%l4 + %o5], %l2, %tie_ld(sh6)
+	add	%g7, %l2, %l2, %tie_add(sh6)
+	nop;nop;nop;nop
+
+	/* direct %g7 access IE -> LE against hidden but not local var  */
+	sethi	%tie_hi22(bl8), %o3
+	add	%o3, %tie_lo10(bl8), %o5
+	ld	[%l4 + %o5], %l2, %tie_ld(bl8)
+	stb	%l1, [%g7 + %l2], %tie_add(bl8)
+	nop;nop;nop;nop
+
+	/* LE, global var defined in exec  */
+	sethi	%tle_hix22(sg2), %l1
+	nop
+	xor	%l1, %tle_lox10(sg2), %l2
+	nop
+	add	%g7, %l2, %l3
+	nop;nop;nop;nop
+
+	/* LE, local var  */
+	sethi	%tle_hix22(bl2+2), %o0
+	xor	%o0, %tle_lox10(bl2+2), %o0
+	add	%g7, %o0, %o0
+	nop;nop;nop;nop
+
+	/* LE, hidden var defined in exec */
+	sethi	%tle_hix22(sh2+1), %l1
+	xor	%l1, %tle_lox10(sh2+1), %o5
+	add	%g7, %o5, %o1
+	nop;nop;nop;nop
+
+	/* Direct %g7 access  */
+
+	/* LE, global var defined in exec  */
+	sethi	%tle_hix22(sg3), %l1
+	xor	%l1, %tle_lox10(sg3), %o5
+	ld	[%g7 + %o5], %o1
+	nop;nop;nop;nop
+
+	/* LE, local var  */
+	sethi	%tle_hix22(bl3 + 3), %o0
+	xor	%o0, %tle_lox10(bl3 + 3), %o0
+	stb	%o1, [%g7 + %o0]
+	nop;nop;nop;nop
+
+	/* LE, hidden var defined in exec  */
+	sethi	%tle_hix22(sh3 + 3), %o2
+	xor	%o2, %tle_lox10(sh3 + 3), %o4
+	ldstub	[%g7 + %o4], %o5
+	nop;nop;nop;nop
+
+	ret
+	restore
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin32.sd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin32.sd
new file mode 100644
index 0000000..7db88c9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin32.sd
@@ -0,0 +1,11 @@
+#source: tlssunbin32.s
+#as: --32
+#ld: -shared -melf32_sparc tmpdir/libtlslib32.so tmpdir/tlssunbinbin32.o
+#objdump: -sj.got
+#target: sparc*-*-*
+
+.*: +file format elf32-sparc
+
+Contents of section .got:
+ 23274 000231f4 0+ 0+ 0+  .*
+ 23284 0+  .*
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin32.td b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin32.td
new file mode 100644
index 0000000..f5974e7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin32.td
@@ -0,0 +1,19 @@
+#source: tlssunbin32.s
+#as: --32
+#ld: -shared -melf32_sparc tmpdir/libtlslib32.so tmpdir/tlssunbinpic32.o
+#objdump: -sj.tdata
+#target: sparc*-*-*
+
+.*: +file format elf32-sparc
+
+Contents of section .tdata:
+ 22194 00000011 00000000 00000000 00000000  .*
+ 221a4 00000000 00000000 00000000 00000000  .*
+#...
+ 23184 00000000 00000000 00000000 00000000  .*
+ 23194 00000000 00000012 00000013 00000014  .*
+ 231a4 00000015 00000016 00000017 00000018  .*
+ 231b4 00000041 00000042 00000043 00000044  .*
+ 231c4 00000045 00000046 00000047 00000048  .*
+ 231d4 00000101 00000102 00000103 00000104  .*
+ 231e4 00000105 00000106 00000107 00000108  .*
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin64.dd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin64.dd
new file mode 100644
index 0000000..0585ae6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin64.dd
@@ -0,0 +1,277 @@
+#source: tlssunbin64.s
+#as: --64
+#ld: -shared -melf64_sparc tmpdir/libtlslib64.so tmpdir/tlssunbinpic64.o
+#objdump: -drj.text
+#target: sparc*-*-*
+
+.*: +file format elf64-sparc
+
+Disassembly of section .text:
+
+0+101000 <fn2-0x8>:
+ +101000:	81 c3 e0 08 	retl *
+ +101004:	ae 03 c0 17 	add  %o7, %l7, %l7
+
+0+101008 <fn2>:
+ +101008:	9d e3 bf 60 	save  %sp, -160, %sp
+ +10100c:	2f 00 04 04 	sethi  %hi\(0x101000\), %l7
+ +101010:	7f ff ff fc 	call  101000 <.*>
+ +101014:	ae 05 e2 f8 	add  %l7, 0x2f8, %l7	! 1012f8 <.*>
+ +101018:	01 00 00 00 	nop *
+ +10101c:	01 00 00 00 	nop *
+ +101020:	01 00 00 00 	nop *
+ +101024:	01 00 00 00 	nop *
+ +101028:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +10102c:	01 00 00 00 	nop *
+ +101030:	a4 04 60 20 	add  %l1, 0x20, %l2
+ +101034:	01 00 00 00 	nop *
+ +101038:	d0 5d c0 12 	ldx  \[ %l7 \+ %l2 \], %o0
+ +10103c:	01 00 00 00 	nop *
+ +101040:	90 01 c0 08 	add  %g7, %o0, %o0
+ +101044:	01 00 00 00 	nop *
+ +101048:	01 00 00 00 	nop *
+ +10104c:	01 00 00 00 	nop *
+ +101050:	01 00 00 00 	nop *
+ +101054:	01 00 00 00 	nop *
+ +101058:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +10105c:	92 02 20 10 	add  %o0, 0x10, %o1	! 10 <.*>
+ +101060:	d0 5d c0 09 	ldx  \[ %l7 \+ %o1 \], %o0
+ +101064:	90 01 c0 08 	add  %g7, %o0, %o0
+ +101068:	01 00 00 00 	nop *
+ +10106c:	01 00 00 00 	nop *
+ +101070:	01 00 00 00 	nop *
+ +101074:	01 00 00 00 	nop *
+ +101078:	01 00 00 00 	nop *
+ +10107c:	21 00 00 00 	sethi  %hi\(0\), %l0
+ +101080:	aa 1c 3f 60 	xor  %l0, -160, %l5
+ +101084:	90 01 c0 15 	add  %g7, %l5, %o0
+ +101088:	01 00 00 00 	nop *
+ +10108c:	01 00 00 00 	nop *
+ +101090:	01 00 00 00 	nop *
+ +101094:	01 00 00 00 	nop *
+ +101098:	01 00 00 00 	nop *
+ +10109c:	01 00 00 00 	nop *
+ +1010a0:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +1010a4:	92 1a 3f 80 	xor  %o0, -128, %o1
+ +1010a8:	90 01 c0 09 	add  %g7, %o1, %o0
+ +1010ac:	01 00 00 00 	nop *
+ +1010b0:	01 00 00 00 	nop *
+ +1010b4:	01 00 00 00 	nop *
+ +1010b8:	01 00 00 00 	nop *
+ +1010bc:	01 00 00 00 	nop *
+ +1010c0:	01 00 00 00 	nop *
+ +1010c4:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +1010c8:	92 1a 3f a0 	xor  %o0, -96, %o1
+ +1010cc:	90 01 c0 09 	add  %g7, %o1, %o0
+ +1010d0:	01 00 00 00 	nop *
+ +1010d4:	01 00 00 00 	nop *
+ +1010d8:	01 00 00 00 	nop *
+ +1010dc:	01 00 00 00 	nop *
+ +1010e0:	01 00 00 00 	nop *
+ +1010e4:	01 00 00 00 	nop *
+ +1010e8:	01 00 00 00 	nop *
+ +1010ec:	01 00 00 00 	nop *
+ +1010f0:	01 00 00 00 	nop *
+ +1010f4:	01 00 00 00 	nop *
+ +1010f8:	01 00 00 00 	nop *
+ +1010fc:	01 00 00 00 	nop *
+ +101100:	90 10 00 00 	mov  %g0, %o0
+ +101104:	01 00 00 00 	nop *
+ +101108:	27 00 00 00 	sethi  %hi\(0\), %l3
+ +10110c:	01 00 00 00 	nop *
+ +101110:	a8 1c ff 80 	xor  %l3, -128, %l4
+ +101114:	01 00 00 00 	nop *
+ +101118:	aa 01 c0 14 	add  %g7, %l4, %l5
+ +10111c:	01 00 00 00 	nop *
+ +101120:	25 00 00 00 	sethi  %hi\(0\), %l2
+ +101124:	01 00 00 00 	nop *
+ +101128:	a6 1c bf 86 	xor  %l2, -122, %l3
+ +10112c:	01 00 00 00 	nop *
+ +101130:	ec 11 c0 13 	lduh  \[ %g7 \+ %l3 \], %l6
+ +101134:	01 00 00 00 	nop *
+ +101138:	01 00 00 00 	nop *
+ +10113c:	01 00 00 00 	nop *
+ +101140:	01 00 00 00 	nop *
+ +101144:	01 00 00 00 	nop *
+ +101148:	27 00 00 00 	sethi  %hi\(0\), %l3
+ +10114c:	01 00 00 00 	nop *
+ +101150:	25 00 00 00 	sethi  %hi\(0\), %l2
+ +101154:	01 00 00 00 	nop *
+ +101158:	a8 1c ff a0 	xor  %l3, -96, %l4
+ +10115c:	90 10 00 00 	mov  %g0, %o0
+ +101160:	a6 1c bf a5 	xor  %l2, -91, %l3
+ +101164:	aa 01 c0 14 	add  %g7, %l4, %l5
+ +101168:	ec 09 c0 13 	ldub  \[ %g7 \+ %l3 \], %l6
+ +10116c:	01 00 00 00 	nop *
+ +101170:	01 00 00 00 	nop *
+ +101174:	01 00 00 00 	nop *
+ +101178:	01 00 00 00 	nop *
+ +10117c:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +101180:	01 00 00 00 	nop *
+ +101184:	a4 04 60 10 	add  %l1, 0x10, %l2
+ +101188:	01 00 00 00 	nop *
+ +10118c:	e4 5d c0 12 	ldx  \[ %l7 \+ %l2 \], %l2
+ +101190:	01 00 00 00 	nop *
+ +101194:	a4 01 c0 12 	add  %g7, %l2, %l2
+ +101198:	01 00 00 00 	nop *
+ +10119c:	01 00 00 00 	nop *
+ +1011a0:	01 00 00 00 	nop *
+ +1011a4:	01 00 00 00 	nop *
+ +1011a8:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +1011ac:	96 1a ff 60 	xor  %o3, -160, %o3
+ +1011b0:	94 10 00 0b 	mov  %o3, %o2
+ +1011b4:	98 01 c0 0a 	add  %g7, %o2, %o4
+ +1011b8:	01 00 00 00 	nop *
+ +1011bc:	01 00 00 00 	nop *
+ +1011c0:	01 00 00 00 	nop *
+ +1011c4:	01 00 00 00 	nop *
+ +1011c8:	29 00 00 00 	sethi  %hi\(0\), %l4
+ +1011cc:	a2 1d 3f 80 	xor  %l4, -128, %l1
+ +1011d0:	a6 10 00 11 	mov  %l1, %l3
+ +1011d4:	a6 01 c0 13 	add  %g7, %l3, %l3
+ +1011d8:	01 00 00 00 	nop *
+ +1011dc:	01 00 00 00 	nop *
+ +1011e0:	01 00 00 00 	nop *
+ +1011e4:	01 00 00 00 	nop *
+ +1011e8:	13 00 00 00 	sethi  %hi\(0\), %o1
+ +1011ec:	96 1a 7f a0 	xor  %o1, -96, %o3
+ +1011f0:	90 10 00 0b 	mov  %o3, %o0
+ +1011f4:	96 01 c0 08 	add  %g7, %o0, %o3
+ +1011f8:	01 00 00 00 	nop *
+ +1011fc:	01 00 00 00 	nop *
+ +101200:	01 00 00 00 	nop *
+ +101204:	01 00 00 00 	nop *
+ +101208:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +10120c:	96 02 e0 08 	add  %o3, 8, %o3	! 8 <.*>
+ +101210:	d4 5d c0 0b 	ldx  \[ %l7 \+ %o3 \], %o2
+ +101214:	d8 59 c0 0a 	ldx  \[ %g7 \+ %o2 \], %o4
+ +101218:	01 00 00 00 	nop *
+ +10121c:	01 00 00 00 	nop *
+ +101220:	01 00 00 00 	nop *
+ +101224:	01 00 00 00 	nop *
+ +101228:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +10122c:	96 1a ff 90 	xor  %o3, -112, %o3
+ +101230:	94 10 00 0b 	mov  %o3, %o2
+ +101234:	d8 29 c0 0a 	stb  %o4, \[ %g7 \+ %o2 \]
+ +101238:	01 00 00 00 	nop *
+ +10123c:	01 00 00 00 	nop *
+ +101240:	01 00 00 00 	nop *
+ +101244:	01 00 00 00 	nop *
+ +101248:	1b 00 00 00 	sethi  %hi\(0\), %o5
+ +10124c:	96 1b 7f b0 	xor  %o5, -80, %o3
+ +101250:	94 10 00 0b 	mov  %o3, %o2
+ +101254:	d8 49 c0 0a 	ldsb  \[ %g7 \+ %o2 \], %o4
+ +101258:	01 00 00 00 	nop *
+ +10125c:	01 00 00 00 	nop *
+ +101260:	01 00 00 00 	nop *
+ +101264:	01 00 00 00 	nop *
+ +101268:	81 cf e0 08 	rett  %i7 \+ 8
+ +10126c:	01 00 00 00 	nop *
+#...
+
+0+102000 <_start>:
+ +102000:	9d e3 bf 60 	save  %sp, -160, %sp
+ +102004:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +102008:	25 00 08 08 	sethi  %hi\(0x202000\), %l2
+ +10200c:	a2 14 60 00 	mov  %l1, %l1
+ +102010:	a4 14 a3 08 	or  %l2, 0x308, %l2
+ +102014:	a3 2c 70 20 	sllx  %l1, 0x20, %l1
+ +102018:	a8 04 40 12 	add  %l1, %l2, %l4
+ +10201c:	01 00 00 00 	nop *
+ +102020:	01 00 00 00 	nop *
+ +102024:	01 00 00 00 	nop *
+ +102028:	01 00 00 00 	nop *
+ +10202c:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +102030:	96 02 e0 18 	add  %o3, 0x18, %o3	! 18 <.*>
+ +102034:	d4 5d 00 0b 	ldx  \[ %l4 \+ %o3 \], %o2
+ +102038:	98 01 c0 0a 	add  %g7, %o2, %o4
+ +10203c:	01 00 00 00 	nop *
+ +102040:	01 00 00 00 	nop *
+ +102044:	01 00 00 00 	nop *
+ +102048:	01 00 00 00 	nop *
+ +10204c:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +102050:	9a 1a ff d4 	xor  %o3, -44, %o5
+ +102054:	94 10 00 0d 	mov  %o5, %o2
+ +102058:	98 01 c0 0a 	add  %g7, %o2, %o4
+ +10205c:	01 00 00 00 	nop *
+ +102060:	01 00 00 00 	nop *
+ +102064:	01 00 00 00 	nop *
+ +102068:	01 00 00 00 	nop *
+ +10206c:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +102070:	9a 1a ff f4 	xor  %o3, -12, %o5
+ +102074:	a4 10 00 0d 	mov  %o5, %l2
+ +102078:	a4 01 c0 12 	add  %g7, %l2, %l2
+ +10207c:	01 00 00 00 	nop *
+ +102080:	01 00 00 00 	nop *
+ +102084:	01 00 00 00 	nop *
+ +102088:	01 00 00 00 	nop *
+ +10208c:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +102090:	9a 1a ff fc 	xor  %o3, -4, %o5
+ +102094:	a4 10 00 0d 	mov  %o5, %l2
+ +102098:	e4 41 c0 12 	ldsw  \[ %g7 \+ %l2 \], %l2
+ +10209c:	01 00 00 00 	nop *
+ +1020a0:	01 00 00 00 	nop *
+ +1020a4:	01 00 00 00 	nop *
+ +1020a8:	01 00 00 00 	nop *
+ +1020ac:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +1020b0:	9a 1a ff b4 	xor  %o3, -76, %o5
+ +1020b4:	a4 10 00 0d 	mov  %o5, %l2
+ +1020b8:	a4 01 c0 12 	add  %g7, %l2, %l2
+ +1020bc:	01 00 00 00 	nop *
+ +1020c0:	01 00 00 00 	nop *
+ +1020c4:	01 00 00 00 	nop *
+ +1020c8:	01 00 00 00 	nop *
+ +1020cc:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +1020d0:	9a 1a ff fc 	xor  %o3, -4, %o5
+ +1020d4:	a4 10 00 0d 	mov  %o5, %l2
+ +1020d8:	e2 29 c0 12 	stb  %l1, \[ %g7 \+ %l2 \]
+ +1020dc:	01 00 00 00 	nop *
+ +1020e0:	01 00 00 00 	nop *
+ +1020e4:	01 00 00 00 	nop *
+ +1020e8:	01 00 00 00 	nop *
+ +1020ec:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +1020f0:	01 00 00 00 	nop *
+ +1020f4:	a4 1c 7f 64 	xor  %l1, -156, %l2
+ +1020f8:	01 00 00 00 	nop *
+ +1020fc:	a6 01 c0 12 	add  %g7, %l2, %l3
+ +102100:	01 00 00 00 	nop *
+ +102104:	01 00 00 00 	nop *
+ +102108:	01 00 00 00 	nop *
+ +10210c:	01 00 00 00 	nop *
+ +102110:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +102114:	90 1a 3f e6 	xor  %o0, -26, %o0
+ +102118:	90 01 c0 08 	add  %g7, %o0, %o0
+ +10211c:	01 00 00 00 	nop *
+ +102120:	01 00 00 00 	nop *
+ +102124:	01 00 00 00 	nop *
+ +102128:	01 00 00 00 	nop *
+ +10212c:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +102130:	9a 1c 7f a5 	xor  %l1, -91, %o5
+ +102134:	92 01 c0 0d 	add  %g7, %o5, %o1
+ +102138:	01 00 00 00 	nop *
+ +10213c:	01 00 00 00 	nop *
+ +102140:	01 00 00 00 	nop *
+ +102144:	01 00 00 00 	nop *
+ +102148:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +10214c:	9a 1c 7f 68 	xor  %l1, -152, %o5
+ +102150:	d2 59 c0 0d 	ldx  \[ %g7 \+ %o5 \], %o1
+ +102154:	01 00 00 00 	nop *
+ +102158:	01 00 00 00 	nop *
+ +10215c:	01 00 00 00 	nop *
+ +102160:	01 00 00 00 	nop *
+ +102164:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +102168:	90 1a 3f eb 	xor  %o0, -21, %o0
+ +10216c:	d2 29 c0 08 	stb  %o1, \[ %g7 \+ %o0 \]
+ +102170:	01 00 00 00 	nop *
+ +102174:	01 00 00 00 	nop *
+ +102178:	01 00 00 00 	nop *
+ +10217c:	01 00 00 00 	nop *
+ +102180:	15 00 00 00 	sethi  %hi\(0\), %o2
+ +102184:	98 1a bf ab 	xor  %o2, -85, %o4
+ +102188:	da 69 c0 0c 	ldstub  \[ %g7 \+ %o4 \], %o5
+ +10218c:	01 00 00 00 	nop *
+ +102190:	01 00 00 00 	nop *
+ +102194:	01 00 00 00 	nop *
+ +102198:	01 00 00 00 	nop *
+ +10219c:	81 c7 e0 08 	ret 
+ +1021a0:	81 e8 00 00 	restore 
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin64.rd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin64.rd
new file mode 100644
index 0000000..1738639
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin64.rd
@@ -0,0 +1,126 @@
+#source: tlssunbin64.s
+#as: --64
+#ld: -shared -melf64_sparc tmpdir/libtlslib64.so tmpdir/tlssunbinpic64.o
+#readelf: -WSsrl
+#target: sparc*-*-*
+
+.*
+
+Section Headers:
+ +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0
+ +\[[ 0-9]+\] .interp +.*
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .text +PROGBITS +0+101000 0+1000 0+11a4 00 +AX +0 +0 4096
+ +\[[ 0-9]+\] .tdata +PROGBITS +0+2021a4 0+21a4 0+0060 00 WAT +0 +0 +4
+ +\[[ 0-9]+\] .tbss +NOBITS +0+202204 0+2204 0+40 00 WAT +0 +0 +4
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+202208 0+2208 0+100 10 +WA +4 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+202308 0+2308 0+28 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+#...
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x102000
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+ +PHDR +0x0+40 0x0+100040 0x0+100040 0x0+150 0x0+150 R E 0x8
+ +INTERP +0x0+190 0x0+100190 0x0+100190 0x0+19 0x0+19 R +0x1
+.*Requesting program interpreter.*
+ +LOAD .* R E 0x100000
+ +LOAD .* RW +0x100000
+ +DYNAMIC .* RW +0x8
+ +TLS .* 0x0+60 0x0+a0 R +0x4
+#...
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+ +sG5 \+ 0
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+ +sG2 \+ 0
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+ +sG6 \+ 0
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+ +sG1 \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* TLS +GLOBAL DEFAULT +UND sG5
+.* TLS +GLOBAL DEFAULT +UND sG2
+.* FUNC +GLOBAL DEFAULT +UND __tls_get_addr
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +UND sG6
+.* TLS +GLOBAL DEFAULT +UND sG1
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +1 *
+.* SECTION LOCAL +DEFAULT +2 *
+.* SECTION LOCAL +DEFAULT +3 *
+.* SECTION LOCAL +DEFAULT +4 *
+.* SECTION LOCAL +DEFAULT +5 *
+.* SECTION LOCAL +DEFAULT +6 *
+.* SECTION LOCAL +DEFAULT +7 *
+.* SECTION LOCAL +DEFAULT +8 *
+.* SECTION LOCAL +DEFAULT +9 *
+.* SECTION LOCAL +DEFAULT +10 *
+.* TLS +LOCAL +DEFAULT +7 sl1
+.* TLS +LOCAL +DEFAULT +7 sl2
+.* TLS +LOCAL +DEFAULT +7 sl3
+.* TLS +LOCAL +DEFAULT +7 sl4
+.* TLS +LOCAL +DEFAULT +7 sl5
+.* TLS +LOCAL +DEFAULT +7 sl6
+.* TLS +LOCAL +DEFAULT +7 sl7
+.* TLS +LOCAL +DEFAULT +7 sl8
+.* TLS +LOCAL +DEFAULT +8 bl1
+.* TLS +LOCAL +DEFAULT +8 bl2
+.* TLS +LOCAL +DEFAULT +8 bl3
+.* TLS +LOCAL +DEFAULT +8 bl4
+.* TLS +LOCAL +DEFAULT +8 bl5
+.* TLS +LOCAL +DEFAULT +8 bl6
+.* TLS +LOCAL +DEFAULT +8 bl7
+.* TLS +LOCAL +DEFAULT +8 bl8
+.* OBJECT +LOCAL +HIDDEN +9 _DYNAMIC
+.* OBJECT +LOCAL +HIDDEN +10 _PROCEDURE_LINKAGE_TABLE_
+.* OBJECT +LOCAL +HIDDEN +10 _GLOBAL_OFFSET_TABLE_
+.* TLS +GLOBAL DEFAULT +7 sg8
+.* TLS +GLOBAL DEFAULT +8 bg8
+.* TLS +GLOBAL DEFAULT +8 bg6
+.* TLS +GLOBAL DEFAULT +UND sG5
+.* TLS +GLOBAL DEFAULT +8 bg3
+.* TLS +GLOBAL DEFAULT +7 sg3
+.* TLS +GLOBAL HIDDEN +7 sh3
+.* TLS +GLOBAL DEFAULT +UND sG2
+.* TLS +GLOBAL DEFAULT +7 sg4
+.* TLS +GLOBAL DEFAULT +7 sg5
+.* TLS +GLOBAL DEFAULT +8 bg5
+.* FUNC +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL HIDDEN +7 sh7
+.* TLS +GLOBAL HIDDEN +7 sh8
+.* TLS +GLOBAL DEFAULT +7 sg1
+.* FUNC +GLOBAL DEFAULT +6 _start
+.* TLS +GLOBAL HIDDEN +7 sh4
+.* TLS +GLOBAL DEFAULT +8 bg7
+.* TLS +GLOBAL HIDDEN +7 sh5
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +UND sG6
+.* FUNC +GLOBAL DEFAULT +6 fn2
+.* TLS +GLOBAL DEFAULT +7 sg2
+.* TLS +GLOBAL DEFAULT +UND sG1
+.* TLS +GLOBAL HIDDEN +7 sh1
+.* TLS +GLOBAL DEFAULT +7 sg6
+.* TLS +GLOBAL DEFAULT +7 sg7
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+.* TLS +GLOBAL HIDDEN +7 sh2
+.* TLS +GLOBAL HIDDEN +7 sh6
+.* TLS +GLOBAL DEFAULT +8 bg2
+.* TLS +GLOBAL DEFAULT +8 bg1
+.* TLS +GLOBAL DEFAULT +8 bg4
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin64.s b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin64.s
new file mode 100644
index 0000000..bb62610
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin64.s
@@ -0,0 +1,118 @@
+	.section ".tbss"
+	.align	4
+	.globl bg1, bg2, bg3, bg4, bg5, bg6, bg7, bg8
+bg1:	.word 0
+bg2:	.word 0
+bg3:	.word 0
+bg4:	.word 0
+bg5:	.word 0
+bg6:	.word 0
+bg7:	.word 0
+bg8:	.word 0
+bl1:	.word 0
+bl2:	.word 0
+bl3:	.word 0
+bl4:	.word 0
+bl5:	.word 0
+bl6:	.word 0
+bl7:	.word 0
+bl8:	.word 0
+	.text
+	.globl	_start
+	.type	_start,#function
+	.proc	04
+_start:
+	save	%sp, -160, %sp
+	.hidden	_GLOBAL_OFFSET_TABLE_
+	sethi	%hh(_GLOBAL_OFFSET_TABLE_), %l1
+	sethi	%lm(_GLOBAL_OFFSET_TABLE_), %l2
+	or	%l1, %hm(_GLOBAL_OFFSET_TABLE_), %l1
+	or	%l2, %lo(_GLOBAL_OFFSET_TABLE_), %l2
+	sllx	%l1, 32, %l1
+	add	%l1, %l2, %l4
+	nop;nop;nop;nop
+
+	/* IE against global var  */
+	sethi	%tie_hi22(sG6), %o3
+	add	%o3, %tie_lo10(sG6), %o3
+	ldx	[%l4 + %o3], %o2, %tie_ldx(sG6)
+	add	%g7, %o2, %o4, %tie_add(sG6)
+	nop;nop;nop;nop
+
+	/* IE -> LE against global var defined in exec  */
+	sethi	%tie_hi22(bg6), %o3
+	add	%o3, %tie_lo10(bg6), %o5
+	ldx	[%l4 + %o5], %o2, %tie_ldx(bg6)
+	add	%g7, %o2, %o4, %tie_add(bg6)
+	nop;nop;nop;nop
+
+	/* IE -> LE against local var  */
+	sethi	%tie_hi22(bl6), %o3
+	add	%o3, %tie_lo10(bl6), %o5
+	ldx	[%l4 + %o5], %l2, %tie_ldx(bl6)
+	add	%g7, %l2, %l2, %tie_add(bl6)
+	nop;nop;nop;nop
+
+	/* direct %g7 access IE -> LE against local var  */
+	sethi	%tie_hi22(bl8), %o3
+	add	%o3, %tie_lo10(bl8), %o5
+	ldx	[%l4 + %o5], %l2, %tie_ldx(bl8)
+	ldsw [%g7 + %l2], %l2, %tie_add(bl8)
+	nop;nop;nop;nop
+
+	/* IE -> LE against hidden but not local var  */
+	sethi	%tie_hi22(sh6), %o3
+	add	%o3, %tie_lo10(sh6), %o5
+	ldx	[%l4 + %o5], %l2, %tie_ldx(sh6)
+	add	%g7, %l2, %l2, %tie_add(sh6)
+	nop;nop;nop;nop
+
+	/* direct %g7 access IE -> LE against hidden but not local var  */
+	sethi	%tie_hi22(bl8), %o3
+	add	%o3, %tie_lo10(bl8), %o5
+	ldx	[%l4 + %o5], %l2, %tie_ldx(bl8)
+	stb	%l1, [%g7 + %l2], %tie_add(bl8)
+	nop;nop;nop;nop
+
+	/* LE, global var defined in exec  */
+	sethi	%tle_hix22(sg2), %l1
+	nop
+	xor	%l1, %tle_lox10(sg2), %l2
+	nop
+	add	%g7, %l2, %l3
+	nop;nop;nop;nop
+
+	/* LE, local var  */
+	sethi	%tle_hix22(bl2+2), %o0
+	xor	%o0, %tle_lox10(bl2+2), %o0
+	add	%g7, %o0, %o0
+	nop;nop;nop;nop
+
+	/* LE, hidden var defined in exec */
+	sethi	%tle_hix22(sh2+1), %l1
+	xor	%l1, %tle_lox10(sh2+1), %o5
+	add	%g7, %o5, %o1
+	nop;nop;nop;nop
+
+	/* Direct %g7 access  */
+
+	/* LE, global var defined in exec  */
+	sethi	%tle_hix22(sg3), %l1
+	xor	%l1, %tle_lox10(sg3), %o5
+	ldx	[%g7 + %o5], %o1
+	nop;nop;nop;nop
+
+	/* LE, local var  */
+	sethi	%tle_hix22(bl3 + 3), %o0
+	xor	%o0, %tle_lox10(bl3 + 3), %o0
+	stb	%o1, [%g7 + %o0]
+	nop;nop;nop;nop
+
+	/* LE, hidden var defined in exec  */
+	sethi	%tle_hix22(sh3 + 3), %o2
+	xor	%o2, %tle_lox10(sh3 + 3), %o4
+	ldstub	[%g7 + %o4], %o5
+	nop;nop;nop;nop
+
+	ret
+	restore
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin64.sd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin64.sd
new file mode 100644
index 0000000..73a87e0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin64.sd
@@ -0,0 +1,12 @@
+#source: tlssunbin64.s
+#as: --64
+#ld: -shared -melf64_sparc tmpdir/libtlslib64.so tmpdir/tlssunbinpic64.o
+#objdump: -sj.got
+#target: sparc*-*-*
+
+.*: +file format elf64-sparc
+
+Contents of section .got:
+ 202308 0+ 0+202208 0+ 0+  .*
+ 202318 0+ 0+ 0+ 0+  .*
+ 202328 0+ 0+ +.*
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin64.td b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin64.td
new file mode 100644
index 0000000..f7eef83
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbin64.td
@@ -0,0 +1,15 @@
+#source: tlssunbin64.s
+#as: --64
+#ld: -shared -melf64_sparc tmpdir/libtlslib64.so tmpdir/tlssunbinpic64.o
+#objdump: -sj.tdata
+#target: sparc*-*-*
+
+.*: +file format elf64-sparc
+
+Contents of section .tdata:
+ 2021a4 00000011 00000012 00000013 00000014  .*
+ 2021b4 00000015 00000016 00000017 00000018  .*
+ 2021c4 00000041 00000042 00000043 00000044  .*
+ 2021d4 00000045 00000046 00000047 00000048  .*
+ 2021e4 00000101 00000102 00000103 00000104  .*
+ 2021f4 00000105 00000106 00000107 00000108  .*
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunbinpic32.s b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbinpic32.s
new file mode 100644
index 0000000..60fb585
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbinpic32.s
@@ -0,0 +1,183 @@
+	.data
+	.align	4096
+	.section ".tdata", #alloc, #write, #tls
+	.align	4
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.word 17
+	.skip	4096
+sg2:	.word 18
+sg3:	.word 19
+sg4:	.word 20
+sg5:	.word 21
+sg6:	.word 22
+sg7:	.word 23
+sg8:	.word 24
+sl1:	.word 65
+sl2:	.word 66
+sl3:	.word 67
+sl4:	.word 68
+sl5:	.word 69
+sl6:	.word 70
+sl7:	.word 71
+sl8:	.word 72
+sh1:	.word 257
+sh2:	.word 258
+sh3:	.word 259
+sh4:	.word 260
+sh5:	.word 261
+sh6:	.word 262
+sh7:	.word 263
+sh8:	.word 264
+	.text
+	.align	4096
+.LLGETPC0:
+        retl
+        add     %o7, %l7, %l7
+
+	.globl	fn2
+	.type	fn2,#function
+	.proc	04
+fn2:
+	save	%sp, -104, %sp
+	sethi	%hi(_GLOBAL_OFFSET_TABLE_-4), %l7
+	call	.LLGETPC0
+	add	%l7, %lo(_GLOBAL_OFFSET_TABLE_+4), %l7
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is not defined in executable */
+	sethi	%tgd_hi22(sG1), %l1
+	nop
+	add	%l1, %tgd_lo10(sG1), %l2
+	nop
+	add	%l7, %l2, %o0, %tgd_add(sG1)
+	nop
+	call	__tls_get_addr, %tgd_call(sG1)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is not defined in executable where
+	   the variable is referenced through IE too */
+	sethi	%tgd_hi22(sG2), %o0
+	add	%o0, %tgd_lo10(sG2), %o1
+	add	%l7, %o1, %o0, %tgd_add(sG2)
+	call	__tls_get_addr, %tgd_call(sG2)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> LE with global variable defined in executable */
+	sethi	%tgd_hi22(sg1), %l0
+	add	%l0, %tgd_lo10(sg1), %l5
+	add	%l7, %l5, %o0, %tgd_add(sg1)
+	call	__tls_get_addr, %tgd_call(sg1)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> LE with local variable defined in executable */
+	sethi	%tgd_hi22(sl1), %o0
+	add	%o0, %tgd_lo10(sl1), %o1
+	add	%l7, %o1, %o0, %tgd_add(sl1)
+	call	__tls_get_addr, %tgd_call(sl1)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> LE with hidden variable defined in executable */
+	sethi	%tgd_hi22(sh1), %o0
+	add	%o0, %tgd_lo10(sh1), %o1
+	add	%l7, %o1, %o0, %tgd_add(sh1)
+	call	__tls_get_addr, %tgd_call(sh1)
+	nop
+	nop;nop;nop;nop
+
+	/* LD -> LE */
+	sethi	%tldm_hi22(sl1), %l1
+	nop
+	add	%l1, %tldm_lo10(sl1), %l2
+	nop
+	add	%l7, %l2, %o0, %tldm_add(sl1)
+	nop
+	call	__tls_get_addr, %tldm_call(sl1)
+	nop
+	sethi	%tldo_hix22(sl1), %l3
+	nop
+	xor	%l3, %tldo_lox10(sl1), %l4
+	nop
+	add	%o0, %l4, %l5, %tldo_add(sl1)
+	nop
+	sethi	%tldo_hix22(sl2 + 2), %l2
+	nop
+	xor	%l2, %tldo_lox10(sl2 + 2), %l3
+	nop
+	lduh	[%o0 + %l3], %l6, %tldo_add(sl2 + 2)
+	nop;nop;nop;nop
+
+	/* LD -> LE against hidden variables */
+	sethi	%tldm_hi22(sh1), %o1
+	sethi	%tldo_hix22(sh1), %l3
+	add	%o1, %tldm_lo10(sh1), %o2
+	sethi	%tldo_hix22(sh2 + 1), %l2
+	add	%l7, %o2, %o0, %tldm_add(sh1)
+	xor	%l3, %tldo_lox10(sh1), %l4
+	call	__tls_get_addr, %tldm_call(sh1)
+	xor	%l2, %tldo_lox10(sh2 + 1), %l3
+	add	%o0, %l4, %l5, %tldo_add(sh1)
+	ldub	[%o0 + %l3], %l6, %tldo_add(sh2 + 1)
+	nop;nop;nop;nop
+
+	/* IE against global var  */
+	sethi	%tie_hi22(sG2), %l1
+	nop
+	add	%l1, %tie_lo10(sG2), %l2
+	nop
+	ld	[%l7 + %l2], %l2, %tie_ld(sG2)
+	nop
+	add	%g7, %l2, %l2, %tie_add(sG2)
+	nop;nop;nop;nop
+
+	/* IE -> LE against global var defined in exec */
+	sethi	%tie_hi22(sg1), %o3
+	add	%o3, %tie_lo10(sg1), %o3
+	ld	[%l7 + %o3], %o3, %tie_ld(sg1)
+	add	%g7, %o3, %o4, %tie_add(sg1)
+	nop;nop;nop;nop
+
+	/* IE -> LE against local var */
+	sethi	%tie_hi22(sl1), %l4
+	add	%l4, %tie_lo10(sl1), %l1
+	ld	[%l7 + %l1], %l3, %tie_ld(sl1)
+	add	%g7, %l3, %l3, %tie_add(sl1)
+	nop;nop;nop;nop
+
+	/* IE -> LE against hidden var */
+	sethi	%tie_hi22(sh1), %o1
+	add	%o1, %tie_lo10(sh1), %o3
+	ld	[%l7 + %o3], %o0, %tie_ld(sh1)
+	add	%g7, %o0, %o3, %tie_add(sh1)
+	nop;nop;nop;nop
+
+	/* Direct access through %g7  */
+
+	/* IE against global var  */
+	sethi	%tie_hi22(sG5), %o3
+	add	%o3, %tie_lo10(sG5), %o3
+	ld	[%l7 + %o3], %o2, %tie_ld(sG5)
+	ld	[%g7 + %o2], %o4, %tie_add(sG5)
+	nop;nop;nop;nop
+
+	/* IE->LE against local var  */
+	sethi	%tie_hi22(sl5), %o3
+	add	%o3, %tie_lo10(sl5), %o3
+	ld	[%l7 + %o3], %o2, %tie_ld(sl5)
+	stb	%o4, [%g7 + %o2], %tie_add(sl5)
+	nop;nop;nop;nop
+
+	/* IE->LE against hidden var  */
+	sethi	%tie_hi22(sh5), %o5
+	add	%o5, %tie_lo10(sh5), %o3
+	ld	[%l7 + %o3], %o2, %tie_ld(sh5)
+	ldsb	[%g7 + %o2], %o4, %tie_add(sh5)
+	nop;nop;nop;nop
+
+	ret
+	restore
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunbinpic64.s b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbinpic64.s
new file mode 100644
index 0000000..a13d2d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunbinpic64.s
@@ -0,0 +1,182 @@
+	.data
+	.align	4096
+	.section ".tdata", #alloc, #write, #tls
+	.align	4
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.word 17
+sg2:	.word 18
+sg3:	.word 19
+sg4:	.word 20
+sg5:	.word 21
+sg6:	.word 22
+sg7:	.word 23
+sg8:	.word 24
+sl1:	.word 65
+sl2:	.word 66
+sl3:	.word 67
+sl4:	.word 68
+sl5:	.word 69
+sl6:	.word 70
+sl7:	.word 71
+sl8:	.word 72
+sh1:	.word 257
+sh2:	.word 258
+sh3:	.word 259
+sh4:	.word 260
+sh5:	.word 261
+sh6:	.word 262
+sh7:	.word 263
+sh8:	.word 264
+	.text
+	.align	4096
+.LLGETPC0:
+        retl
+        add     %o7, %l7, %l7
+
+	.globl	fn2
+	.type	fn2,#function
+	.proc	04
+fn2:
+	save	%sp, -160, %sp
+	sethi	%hi(_GLOBAL_OFFSET_TABLE_-4), %l7
+	call	.LLGETPC0
+	add	%l7, %lo(_GLOBAL_OFFSET_TABLE_+4), %l7
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is not defined in executable */
+	sethi	%tgd_hi22(sG1), %l1
+	nop
+	add	%l1, %tgd_lo10(sG1), %l2
+	nop
+	add	%l7, %l2, %o0, %tgd_add(sG1)
+	nop
+	call	__tls_get_addr, %tgd_call(sG1)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is not defined in executable where
+	   the variable is referenced through IE too */
+	sethi	%tgd_hi22(sG2), %o0
+	add	%o0, %tgd_lo10(sG2), %o1
+	add	%l7, %o1, %o0, %tgd_add(sG2)
+	call	__tls_get_addr, %tgd_call(sG2)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> LE with global variable defined in executable */
+	sethi	%tgd_hi22(sg1), %l0
+	add	%l0, %tgd_lo10(sg1), %l5
+	add	%l7, %l5, %o0, %tgd_add(sg1)
+	call	__tls_get_addr, %tgd_call(sg1)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> LE with local variable defined in executable */
+	sethi	%tgd_hi22(sl1), %o0
+	add	%o0, %tgd_lo10(sl1), %o1
+	add	%l7, %o1, %o0, %tgd_add(sl1)
+	call	__tls_get_addr, %tgd_call(sl1)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> LE with hidden variable defined in executable */
+	sethi	%tgd_hi22(sh1), %o0
+	add	%o0, %tgd_lo10(sh1), %o1
+	add	%l7, %o1, %o0, %tgd_add(sh1)
+	call	__tls_get_addr, %tgd_call(sh1)
+	nop
+	nop;nop;nop;nop
+
+	/* LD -> LE */
+	sethi	%tldm_hi22(sl1), %l1
+	nop
+	add	%l1, %tldm_lo10(sl1), %l2
+	nop
+	add	%l7, %l2, %o0, %tldm_add(sl1)
+	nop
+	call	__tls_get_addr, %tldm_call(sl1)
+	nop
+	sethi	%tldo_hix22(sl1), %l3
+	nop
+	xor	%l3, %tldo_lox10(sl1), %l4
+	nop
+	add	%o0, %l4, %l5, %tldo_add(sl1)
+	nop
+	sethi	%tldo_hix22(sl2 + 2), %l2
+	nop
+	xor	%l2, %tldo_lox10(sl2 + 2), %l3
+	nop
+	lduh	[%o0 + %l3], %l6, %tldo_add(sl2 + 2)
+	nop;nop;nop;nop
+
+	/* LD -> LE against hidden variables */
+	sethi	%tldm_hi22(sh1), %o1
+	sethi	%tldo_hix22(sh1), %l3
+	add	%o1, %tldm_lo10(sh1), %o2
+	sethi	%tldo_hix22(sh2 + 1), %l2
+	add	%l7, %o2, %o0, %tldm_add(sh1)
+	xor	%l3, %tldo_lox10(sh1), %l4
+	call	__tls_get_addr, %tldm_call(sh1)
+	xor	%l2, %tldo_lox10(sh2 + 1), %l3
+	add	%o0, %l4, %l5, %tldo_add(sh1)
+	ldub	[%o0 + %l3], %l6, %tldo_add(sh2 + 1)
+	nop;nop;nop;nop
+
+	/* IE against global var  */
+	sethi	%tie_hi22(sG2), %l1
+	nop
+	add	%l1, %tie_lo10(sG2), %l2
+	nop
+	ldx	[%l7 + %l2], %l2, %tie_ldx(sG2)
+	nop
+	add	%g7, %l2, %l2, %tie_add(sG2)
+	nop;nop;nop;nop
+
+	/* IE -> LE against global var defined in exec */
+	sethi	%tie_hi22(sg1), %o3
+	add	%o3, %tie_lo10(sg1), %o3
+	ldx	[%l7 + %o3], %o2, %tie_ldx(sg1)
+	add	%g7, %o2, %o4, %tie_add(sg1)
+	nop;nop;nop;nop
+
+	/* IE -> LE against local var */
+	sethi	%tie_hi22(sl1), %l4
+	add	%l4, %tie_lo10(sl1), %l1
+	ldx	[%l7 + %l1], %l3, %tie_ldx(sl1)
+	add	%g7, %l3, %l3, %tie_add(sl1)
+	nop;nop;nop;nop
+
+	/* IE -> LE against hidden var */
+	sethi	%tie_hi22(sh1), %o1
+	add	%o1, %tie_lo10(sh1), %o3
+	ldx	[%l7 + %o3], %o0, %tie_ldx(sh1)
+	add	%g7, %o0, %o3, %tie_add(sh1)
+	nop;nop;nop;nop
+
+	/* Direct access through %g7  */
+
+	/* IE against global var  */
+	sethi	%tie_hi22(sG5), %o3
+	add	%o3, %tie_lo10(sG5), %o3
+	ldx	[%l7 + %o3], %o2, %tie_ldx(sG5)
+	ldx	[%g7 + %o2], %o4, %tie_add(sG5)
+	nop;nop;nop;nop
+
+	/* IE->LE against local var  */
+	sethi	%tie_hi22(sl5), %o3
+	add	%o3, %tie_lo10(sl5), %o3
+	ldx	[%l7 + %o3], %o2, %tie_ldx(sl5)
+	stb	%o4, [%g7 + %o2], %tie_add(sl5)
+	nop;nop;nop;nop
+
+	/* IE->LE against hidden var  */
+	sethi	%tie_hi22(sh5), %o5
+	add	%o5, %tie_lo10(sh5), %o3
+	ldx	[%l7 + %o3], %o2, %tie_ldx(sh5)
+	ldsb	[%g7 + %o2], %o4, %tie_add(sh5)
+	nop;nop;nop;nop
+
+	return	%i7 + 8
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic32.dd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic32.dd
new file mode 100644
index 0000000..4f47c7a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic32.dd
@@ -0,0 +1,84 @@
+#source: tlssunnopic32.s
+#source: tlsnopic.s
+#as: --32
+#ld: -shared -melf32_sparc
+#objdump: -drj.text
+#target: sparc*-*-*
+
+.*: +file format elf32-sparc
+
+Disassembly of section .text:
+
+00001000 <fn3>:
+ +1000:	9d e3 bf 98 	save  %sp, -104, %sp
+ +1004:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +1008:	a2 14 60 00 	mov  %l1, %l1	! 0 <.*>
+ +100c:	01 00 00 00 	nop *
+ +1010:	01 00 00 00 	nop *
+ +1014:	01 00 00 00 	nop *
+ +1018:	01 00 00 00 	nop *
+ +101c:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +1020:	96 02 e0 0c 	add  %o3, 0xc, %o3	! c <.*>
+ +1024:	d4 04 40 0b 	ld  \[ %l1 \+ %o3 \], %o2
+ +1028:	98 01 c0 0a 	add  %g7, %o2, %o4
+ +102c:	01 00 00 00 	nop *
+ +1030:	01 00 00 00 	nop *
+ +1034:	01 00 00 00 	nop *
+ +1038:	01 00 00 00 	nop *
+ +103c:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +1040:	90 02 20 10 	add  %o0, 0x10, %o0	! 10 <.*>
+ +1044:	d0 04 40 08 	ld  \[ %l1 \+ %o0 \], %o0
+ +1048:	d0 01 c0 08 	ld  \[ %g7 \+ %o0 \], %o0
+ +104c:	01 00 00 00 	nop *
+ +1050:	01 00 00 00 	nop *
+ +1054:	01 00 00 00 	nop *
+ +1058:	01 00 00 00 	nop *
+ +105c:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +1060:	90 02 20 14 	add  %o0, 0x14, %o0	! 14 <.*>
+ +1064:	d0 04 40 08 	ld  \[ %l1 \+ %o0 \], %o0
+ +1068:	90 01 c0 08 	add  %g7, %o0, %o0
+ +106c:	01 00 00 00 	nop *
+ +1070:	01 00 00 00 	nop *
+ +1074:	01 00 00 00 	nop *
+ +1078:	01 00 00 00 	nop *
+ +107c:	1b 00 00 00 	sethi  %hi\(0\), %o5
+ +1080:	92 03 60 18 	add  %o5, 0x18, %o1	! 18 <.*>
+ +1084:	d4 04 40 09 	ld  \[ %l1 \+ %o1 \], %o2
+ +1088:	d6 29 c0 0a 	stb  %o3, \[ %g7 \+ %o2 \]
+ +108c:	01 00 00 00 	nop *
+ +1090:	01 00 00 00 	nop *
+ +1094:	01 00 00 00 	nop *
+ +1098:	01 00 00 00 	nop *
+ +109c:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +10a0:	90 02 20 04 	add  %o0, 4, %o0	! 4 <.*>
+ +10a4:	d0 04 40 08 	ld  \[ %l1 \+ %o0 \], %o0
+ +10a8:	90 01 c0 08 	add  %g7, %o0, %o0
+ +10ac:	01 00 00 00 	nop *
+ +10b0:	01 00 00 00 	nop *
+ +10b4:	01 00 00 00 	nop *
+ +10b8:	01 00 00 00 	nop *
+ +10bc:	1b 00 00 00 	sethi  %hi\(0\), %o5
+ +10c0:	92 03 60 08 	add  %o5, 8, %o1	! 8 <.*>
+ +10c4:	d4 04 40 09 	ld  \[ %l1 \+ %o1 \], %o2
+ +10c8:	d6 29 c0 0a 	stb  %o3, \[ %g7 \+ %o2 \]
+ +10cc:	01 00 00 00 	nop *
+ +10d0:	01 00 00 00 	nop *
+ +10d4:	01 00 00 00 	nop *
+ +10d8:	01 00 00 00 	nop *
+ +10dc:	15 00 00 00 	sethi  %hi\(0\), %o2
+ +10e0:	98 1a a0 00 	xor  %o2, 0, %o4
+ +10e4:	90 01 c0 0c 	add  %g7, %o4, %o0
+ +10e8:	01 00 00 00 	nop *
+ +10ec:	01 00 00 00 	nop *
+ +10f0:	01 00 00 00 	nop *
+ +10f4:	01 00 00 00 	nop *
+ +10f8:	15 00 00 00 	sethi  %hi\(0\), %o2
+ +10fc:	94 1a a0 00 	xor  %o2, 0, %o2
+ +1100:	d4 01 c0 0a 	ld  \[ %g7 \+ %o2 \], %o2
+ +1104:	01 00 00 00 	nop *
+ +1108:	01 00 00 00 	nop *
+ +110c:	01 00 00 00 	nop *
+ +1110:	01 00 00 00 	nop *
+ +1114:	81 c7 e0 08 	ret *
+ +1118:	81 e8 00 00 	restore *
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic32.rd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic32.rd
new file mode 100644
index 0000000..01876d7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic32.rd
@@ -0,0 +1,93 @@
+#source: tlssunnopic32.s
+#source: tlsnopic.s
+#as: --32
+#ld: -shared -melf32_sparc
+#readelf: -WSsrl
+#target: sparc*-*-*
+
+.*
+
+Section Headers:
+ +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .text +PROGBITS +0+1000 0+1000 0+1000 0+ +AX +0 +0 4096
+ +\[[ 0-9]+\] .tbss +NOBITS +0+12000 0+2000 0+24 0+ WAT +0 +0 +4
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+12000 0+2000 0+80 08 +WA +3 +0 +4
+ +\[[ 0-9]+\] .got +PROGBITS +0+12080 0+2080 0+1c 04 +WA +0 +0 +4
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+#...
+Elf file type is DYN \(Shared object file\)
+Entry point 0x1000
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz MemSiz +Flg Align
+ +LOAD .* R E 0x10000
+ +LOAD .* RW +0x10000
+ +DYNAMIC .* RW +0x4
+ +TLS .* 0x0+ 0x0+24 R +0x4
+#...
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 12 entries:
+ Offset +Info +Type +Sym. Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_SPARC_HI22 +0+12080 +\.got \+ 12080
+[0-9a-f ]+R_SPARC_LO10 +0+12080 +\.got \+ 12080
+[0-9a-f ]+R_SPARC_TLS_LE_HIX22 +0+9
+[0-9a-f ]+R_SPARC_TLS_LE_LOX10 +0+9
+[0-9a-f ]+R_SPARC_TLS_LE_HIX22 +0+1c
+[0-9a-f ]+R_SPARC_TLS_LE_LOX10 +0+1c
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +0+
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +0+4
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +0+14
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +0+18
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +0+ +sg1 \+ 0
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +0+ +sg2 \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +5 *
+.* SECTION LOCAL +DEFAULT +6 *
+.* SECTION LOCAL +DEFAULT +8 *
+.* FUNC +GLOBAL DEFAULT +5 fn3
+.* TLS +GLOBAL DEFAULT +UND sg1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +UND sg2
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +1 *
+.* SECTION LOCAL +DEFAULT +2 *
+.* SECTION LOCAL +DEFAULT +3 *
+.* SECTION LOCAL +DEFAULT +4 *
+.* SECTION LOCAL +DEFAULT +5 *
+.* SECTION LOCAL +DEFAULT +6 *
+.* SECTION LOCAL +DEFAULT +7 *
+.* SECTION LOCAL +DEFAULT +8 *
+.* TLS +LOCAL +DEFAULT +6 bl1
+.* TLS +LOCAL +DEFAULT +6 bl2
+.* TLS +LOCAL +DEFAULT +6 bl3
+.* TLS +LOCAL +DEFAULT +6 bl4
+.* TLS +LOCAL +DEFAULT +6 bl5
+.* OBJECT +LOCAL +HIDDEN +ABS _DYNAMIC
+.* TLS +LOCAL +HIDDEN +6 sh3
+.* OBJECT +LOCAL +HIDDEN +ABS _PROCEDURE_LINKAGE_TABLE_
+.* TLS +LOCAL +HIDDEN +6 sh4
+.* TLS +LOCAL +HIDDEN +6 sh1
+.* OBJECT +LOCAL +HIDDEN +ABS _GLOBAL_OFFSET_TABLE_
+.* TLS +LOCAL +HIDDEN +6 sh2
+.* FUNC +GLOBAL DEFAULT +5 fn3
+.* TLS +GLOBAL DEFAULT +UND sg1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +UND sg2
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic32.s b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic32.s
new file mode 100644
index 0000000..6c0ec33
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic32.s
@@ -0,0 +1,77 @@
+	.data
+	.align	4096
+	.section ".tbss"
+	.align	4
+bl1:	.word 0
+bl2:	.word 0
+bl3:	.word 0
+bl4:	.word 0
+bl5:	.word 0
+	.text
+	.align	4096
+	.globl	fn3
+	.type	fn3,#function
+	.proc	04
+fn3:
+	save	%sp, -104, %sp
+	.hidden	_GLOBAL_OFFSET_TABLE_
+	sethi	%hi(_GLOBAL_OFFSET_TABLE_), %l1
+	or	%l1, %lo(_GLOBAL_OFFSET_TABLE_), %l1
+	nop;nop;nop;nop
+
+	/* IE against global var  */
+	sethi	%tie_hi22(sg1), %o3
+	add	%o3, %tie_lo10(sg1), %o3
+	ld	[%l1 + %o3], %o2, %tie_ld(sg1)
+	add	%g7, %o2, %o4, %tie_add(sg1)
+	nop;nop;nop;nop
+
+	/* direct %g7 access IE against global var  */
+	sethi	%tie_hi22(sg2), %o0
+	add	%o0, %tie_lo10(sg2), %o0
+	ld	[%l1 + %o0], %o0, %tie_ld(sg2)
+	ld	[%g7 + %o0], %o0, %tie_add(sg2)
+	nop;nop;nop;nop
+
+	/* IE against hidden var */
+	sethi	%tie_hi22(sh1), %o0
+	add	%o0, %tie_lo10(sh1), %o0
+	ld	[%l1 + %o0], %o0, %tie_ld(sh1)
+	add	%g7, %o0, %o0, %tie_add(sh1)
+	nop;nop;nop;nop
+
+	/* direct %g7 access IE against hidden var */
+	sethi	%tie_hi22(sh2), %o5
+	add	%o5, %tie_lo10(sh2), %o1
+	ld	[%l1 + %o1], %o2, %tie_ld(sh2)
+	stb	%o3, [%g7 + %o2], %tie_add(sh2)
+	nop;nop;nop;nop
+
+	/* IE against local var  */
+	sethi	%tie_hi22(bl1), %o0
+	add	%o0, %tie_lo10(bl1), %o0
+	ld	[%l1 + %o0], %o0, %tie_ld(bl1)
+	add	%g7, %o0, %o0, %tie_add(bl1)
+	nop;nop;nop;nop
+
+	/* direct %g7 access IE against local var  */
+	sethi	%tie_hi22(bl2), %o5
+	add	%o5, %tie_lo10(bl2), %o1
+	ld	[%l1 + %o1], %o2, %tie_ld(bl2)
+	stb	%o3, [%g7 + %o2], %tie_add(bl2)
+	nop;nop;nop;nop
+
+	/* LE, local var  */
+	sethi	%tle_hix22(bl3+1), %o2
+	xor     %o2, %tle_lox10(bl3+1), %o4
+	add	%g7, %o4, %o0
+	nop;nop;nop;nop
+
+	/* LE, hidden var, direct %g7 access  */
+	sethi	%tle_hix22(sh3), %o2
+	xor     %o2, %tle_lox10(sh3), %o2
+	ld	[%g7 + %o2], %o2
+	nop;nop;nop;nop
+
+	ret
+	restore
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic32.sd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic32.sd
new file mode 100644
index 0000000..0d1beac
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic32.sd
@@ -0,0 +1,12 @@
+#source: tlssunnopic32.s
+#source: tlsnopic.s
+#as: --32
+#ld: -shared -melf32_sparc
+#objdump: -sj.got
+#target: sparc*-*-*
+
+.*:     file format elf32-sparc
+
+Contents of section \.got:
+ 12080 0+12000 0+ 0+ 0+  .*
+ 12090 0+ 0+ 0+  .*
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic64.dd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic64.dd
new file mode 100644
index 0000000..af4918c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic64.dd
@@ -0,0 +1,88 @@
+#source: tlssunnopic64.s
+#source: tlsnopic.s
+#as: --64 -Av9
+#ld: -shared -melf64_sparc
+#objdump: -drj.text
+#target: sparc*-*-*
+
+.*: +file format elf64-sparc
+
+Disassembly of section .text:
+
+0+1000 <fn3>:
+ +1000:	9d e3 bf 60 	save  %sp, -160, %sp
+ +1004:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +1008:	25 00 00 00 	sethi  %hi\(0\), %l2
+ +100c:	a2 14 60 00 	mov  %l1, %l1
+ +1010:	a4 14 a0 00 	mov  %l2, %l2
+ +1014:	a3 2c 70 20 	sllx  %l1, 0x20, %l1
+ +1018:	a2 04 40 12 	add  %l1, %l2, %l1
+ +101c:	01 00 00 00 	nop *
+ +1020:	01 00 00 00 	nop *
+ +1024:	01 00 00 00 	nop *
+ +1028:	01 00 00 00 	nop *
+ +102c:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +1030:	96 02 e0 18 	add  %o3, 0x18, %o3	! 18 <.*>
+ +1034:	d4 5c 40 0b 	ldx  \[ %l1 \+ %o3 \], %o2
+ +1038:	98 01 c0 0a 	add  %g7, %o2, %o4
+ +103c:	01 00 00 00 	nop *
+ +1040:	01 00 00 00 	nop *
+ +1044:	01 00 00 00 	nop *
+ +1048:	01 00 00 00 	nop *
+ +104c:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +1050:	90 02 20 20 	add  %o0, 0x20, %o0	! 20 <.*>
+ +1054:	d0 5c 40 08 	ldx  \[ %l1 \+ %o0 \], %o0
+ +1058:	d0 01 c0 08 	ld  \[ %g7 \+ %o0 \], %o0
+ +105c:	01 00 00 00 	nop *
+ +1060:	01 00 00 00 	nop *
+ +1064:	01 00 00 00 	nop *
+ +1068:	01 00 00 00 	nop *
+ +106c:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +1070:	90 02 20 28 	add  %o0, 0x28, %o0	! 28 <.*>
+ +1074:	d0 5c 40 08 	ldx  \[ %l1 \+ %o0 \], %o0
+ +1078:	90 01 c0 08 	add  %g7, %o0, %o0
+ +107c:	01 00 00 00 	nop *
+ +1080:	01 00 00 00 	nop *
+ +1084:	01 00 00 00 	nop *
+ +1088:	01 00 00 00 	nop *
+ +108c:	1b 00 00 00 	sethi  %hi\(0\), %o5
+ +1090:	92 03 60 30 	add  %o5, 0x30, %o1	! 30 <.*>
+ +1094:	d4 5c 40 09 	ldx  \[ %l1 \+ %o1 \], %o2
+ +1098:	d6 29 c0 0a 	stb  %o3, \[ %g7 \+ %o2 \]
+ +109c:	01 00 00 00 	nop *
+ +10a0:	01 00 00 00 	nop *
+ +10a4:	01 00 00 00 	nop *
+ +10a8:	01 00 00 00 	nop *
+ +10ac:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +10b0:	90 02 20 08 	add  %o0, 8, %o0	! 8 <.*>
+ +10b4:	d0 5c 40 08 	ldx  \[ %l1 \+ %o0 \], %o0
+ +10b8:	90 01 c0 08 	add  %g7, %o0, %o0
+ +10bc:	01 00 00 00 	nop *
+ +10c0:	01 00 00 00 	nop *
+ +10c4:	01 00 00 00 	nop *
+ +10c8:	01 00 00 00 	nop *
+ +10cc:	1b 00 00 00 	sethi  %hi\(0\), %o5
+ +10d0:	92 03 60 10 	add  %o5, 0x10, %o1	! 10 <.*>
+ +10d4:	d4 5c 40 09 	ldx  \[ %l1 \+ %o1 \], %o2
+ +10d8:	d6 29 c0 0a 	stb  %o3, \[ %g7 \+ %o2 \]
+ +10dc:	01 00 00 00 	nop *
+ +10e0:	01 00 00 00 	nop *
+ +10e4:	01 00 00 00 	nop *
+ +10e8:	01 00 00 00 	nop *
+ +10ec:	15 00 00 00 	sethi  %hi\(0\), %o2
+ +10f0:	98 1a a0 00 	xor  %o2, 0, %o4
+ +10f4:	90 01 c0 0c 	add  %g7, %o4, %o0
+ +10f8:	01 00 00 00 	nop *
+ +10fc:	01 00 00 00 	nop *
+ +1100:	01 00 00 00 	nop *
+ +1104:	01 00 00 00 	nop *
+ +1108:	15 00 00 00 	sethi  %hi\(0\), %o2
+ +110c:	94 1a a0 00 	xor  %o2, 0, %o2
+ +1110:	d4 01 c0 0a 	ld  \[ %g7 \+ %o2 \], %o2
+ +1114:	01 00 00 00 	nop *
+ +1118:	01 00 00 00 	nop *
+ +111c:	01 00 00 00 	nop *
+ +1120:	01 00 00 00 	nop *
+ +1124:	81 cf e0 08 	rett  %i7 \+ 8
+ +1128:	01 00 00 00 	nop *
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic64.rd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic64.rd
new file mode 100644
index 0000000..96a426c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic64.rd
@@ -0,0 +1,95 @@
+#source: tlssunnopic64.s
+#source: tlsnopic.s
+#as: --64 -Av9
+#ld: -shared -melf64_sparc
+#readelf: -WSsrl
+#target: sparc*-*-*
+
+.*
+
+Section Headers:
+ +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .text +PROGBITS +0+1000 0+1000 0+1000 0+ +AX +0 +0 4096
+ +\[[ 0-9]+\] .tbss +NOBITS +0+102000 0+2000 0+24 0+ WAT +0 +0 +4
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+102000 0+2000 0+100 10 +WA +3 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+102100 0+2100 0+38 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+#...
+Elf file type is DYN \(Shared object file\)
+Entry point 0x1000
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+ +LOAD .* R E 0x100000
+ +LOAD .* RW +0x100000
+ +DYNAMIC .* RW +0x8
+ +TLS .* 0x0+ 0x0+24 R +0x4
+#...
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_SPARC_HH22 +0+102100 +\.got \+ 102100
+[0-9a-f ]+R_SPARC_LM22 +0+102100 +\.got \+ 102100
+[0-9a-f ]+R_SPARC_HM10 +0+102100 +\.got \+ 102100
+[0-9a-f ]+R_SPARC_LO10 +0+102100 +\.got \+ 102100
+[0-9a-f ]+R_SPARC_TLS_LE_HIX22 +0+9
+[0-9a-f ]+R_SPARC_TLS_LE_LOX10 +0+9
+[0-9a-f ]+R_SPARC_TLS_LE_HIX22 +0+1c
+[0-9a-f ]+R_SPARC_TLS_LE_LOX10 +0+1c
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+4
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+14
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+18
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+ +sg1 \+ 0
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+ +sg2 \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +5 *
+.* SECTION LOCAL +DEFAULT +6 *
+.* SECTION LOCAL +DEFAULT +8 *
+.* FUNC +GLOBAL DEFAULT +5 fn3
+.* TLS +GLOBAL DEFAULT +UND sg1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +UND sg2
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +1 *
+.* SECTION LOCAL +DEFAULT +2 *
+.* SECTION LOCAL +DEFAULT +3 *
+.* SECTION LOCAL +DEFAULT +4 *
+.* SECTION LOCAL +DEFAULT +5 *
+.* SECTION LOCAL +DEFAULT +6 *
+.* SECTION LOCAL +DEFAULT +7 *
+.* SECTION LOCAL +DEFAULT +8 *
+.* TLS +LOCAL +DEFAULT +6 bl1
+.* TLS +LOCAL +DEFAULT +6 bl2
+.* TLS +LOCAL +DEFAULT +6 bl3
+.* TLS +LOCAL +DEFAULT +6 bl4
+.* TLS +LOCAL +DEFAULT +6 bl5
+.* OBJECT +LOCAL +HIDDEN +ABS _DYNAMIC
+.* TLS +LOCAL +HIDDEN +6 sh3
+.* OBJECT +LOCAL +HIDDEN +ABS _PROCEDURE_LINKAGE_TABLE_
+.* TLS +LOCAL +HIDDEN +6 sh4
+.* TLS +LOCAL +HIDDEN +6 sh1
+.* OBJECT +LOCAL +HIDDEN +ABS _GLOBAL_OFFSET_TABLE_
+.* TLS +LOCAL +HIDDEN +6 sh2
+.* FUNC +GLOBAL DEFAULT +5 fn3
+.* TLS +GLOBAL DEFAULT +UND sg1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +UND sg2
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic64.s b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic64.s
new file mode 100644
index 0000000..3d0a4d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic64.s
@@ -0,0 +1,81 @@
+	.data
+	.align	4096
+	.section ".tbss"
+	.align	4
+bl1:	.word 0
+bl2:	.word 0
+bl3:	.word 0
+bl4:	.word 0
+bl5:	.word 0
+	.text
+	.align	4096
+	.globl	fn3
+	.type	fn3,#function
+	.proc	04
+fn3:
+	save	%sp, -160, %sp
+	.hidden	_GLOBAL_OFFSET_TABLE_
+	sethi	%hh(_GLOBAL_OFFSET_TABLE_), %l1
+	sethi	%lm(_GLOBAL_OFFSET_TABLE_), %l2
+	or	%l1, %hm(_GLOBAL_OFFSET_TABLE_), %l1
+	or	%l2, %lo(_GLOBAL_OFFSET_TABLE_), %l2
+	sllx	%l1, 32, %l1
+	add	%l1, %l2, %l1
+	nop;nop;nop;nop
+
+	/* IE against global var  */
+	sethi	%tie_hi22(sg1), %o3
+	add	%o3, %tie_lo10(sg1), %o3
+	ldx	[%l1 + %o3], %o2, %tie_ldx(sg1)
+	add	%g7, %o2, %o4, %tie_add(sg1)
+	nop;nop;nop;nop
+
+	/* direct %g7 access IE against global var  */
+	sethi	%tie_hi22(sg2), %o0
+	add	%o0, %tie_lo10(sg2), %o0
+	ldx	[%l1 + %o0], %o0, %tie_ldx(sg2)
+	lduw [%g7 + %o0], %o0, %tie_add(sg2)
+	nop;nop;nop;nop
+
+	/* IE against hidden var */
+	sethi	%tie_hi22(sh1), %o0
+	add	%o0, %tie_lo10(sh1), %o0
+	ldx	[%l1 + %o0], %o0, %tie_ldx(sh1)
+	add	%g7, %o0, %o0, %tie_add(sh1)
+	nop;nop;nop;nop
+
+	/* direct %g7 access IE against hidden var */
+	sethi	%tie_hi22(sh2), %o5
+	add	%o5, %tie_lo10(sh2), %o1
+	ldx	[%l1 + %o1], %o2, %tie_ldx(sh2)
+	stb	%o3, [%g7 + %o2], %tie_add(sh2)
+	nop;nop;nop;nop
+
+	/* IE against local var  */
+	sethi	%tie_hi22(bl1), %o0
+	add	%o0, %tie_lo10(bl1), %o0
+	ldx	[%l1 + %o0], %o0, %tie_ldx(bl1)
+	add	%g7, %o0, %o0, %tie_add(bl1)
+	nop;nop;nop;nop
+
+	/* direct %g7 access IE against local var  */
+	sethi	%tie_hi22(bl2), %o5
+	add	%o5, %tie_lo10(bl2), %o1
+	ldx	[%l1 + %o1], %o2, %tie_ldx(bl2)
+	stb	%o3, [%g7 + %o2], %tie_add(bl2)
+	nop;nop;nop;nop
+
+	/* LE, local var  */
+	sethi	%tle_hix22(bl3+1), %o2
+	xor     %o2, %tle_lox10(bl3+1), %o4
+	add	%g7, %o4, %o0
+	nop;nop;nop;nop
+
+	/* LE, hidden var, direct %g7 access  */
+	sethi	%tle_hix22(sh3), %o2
+	xor     %o2, %tle_lox10(sh3), %o2
+	ld	[%g7 + %o2], %o2
+	nop;nop;nop;nop
+
+	return	%i7 + 8
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic64.sd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic64.sd
new file mode 100644
index 0000000..45c77e7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunnopic64.sd
@@ -0,0 +1,14 @@
+#source: tlssunnopic64.s
+#source: tlsnopic.s
+#as: --64 -Av9
+#ld: -shared -melf64_sparc
+#objdump: -sj.got
+#target: sparc*-*-*
+
+.*:     file format elf64-sparc
+
+Contents of section \.got:
+ 102100 0+ 0+102000 0+ 0+  .*
+ 102110 0+ 0+ 0+ 0+  .*
+ 102120 0+ 0+ 0+ 0+  .*
+ 102130 0+ 0+  .*
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic32.dd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic32.dd
new file mode 100644
index 0000000..c34d514
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic32.dd
@@ -0,0 +1,220 @@
+#source: tlssunpic32.s
+#source: tlspic.s
+#as: --32 -K PIC
+#ld: -shared -melf32_sparc
+#objdump: -drj.text
+#target: sparc*-*-*
+
+.*: +file format elf32-sparc
+
+Disassembly of section .text:
+
+00001000 <fn1-0x8>:
+ +1000:	81 c3 e0 08 	retl *
+ +1004:	ae 03 c0 17 	add  %o7, %l7, %l7
+
+00001008 <fn1>:
+ +1008:	9d e3 bf 98 	save  %sp, -104, %sp
+ +100c:	2f 00 00 44 	sethi  %hi\(0x11000\), %l7
+ +1010:	7f ff ff fc 	call  1000 <.*>
+ +1014:	ae 05 e0 e8 	add  %l7, 0xe8, %l7	! 110e8 <.*>
+ +1018:	01 00 00 00 	nop *
+ +101c:	01 00 00 00 	nop *
+ +1020:	01 00 00 00 	nop *
+ +1024:	01 00 00 00 	nop *
+ +1028:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +102c:	01 00 00 00 	nop *
+ +1030:	a4 04 60 2c 	add  %l1, 0x2c, %l2
+ +1034:	01 00 00 00 	nop *
+ +1038:	90 05 c0 12 	add  %l7, %l2, %o0
+ +103c:	01 00 00 00 	nop *
+ +1040:	40 00 44 4d 	call  [0-9a-f]+ <__tls_get_addr@plt>
+ +1044:	01 00 00 00 	nop *
+ +1048:	01 00 00 00 	nop *
+ +104c:	01 00 00 00 	nop *
+ +1050:	01 00 00 00 	nop *
+ +1054:	01 00 00 00 	nop *
+ +1058:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +105c:	92 02 20 3c 	add  %o0, 0x3c, %o1	! 3c <.*>
+ +1060:	d0 05 c0 09 	ld  \[ %l7 \+ %o1 \], %o0
+ +1064:	90 01 c0 08 	add  %g7, %o0, %o0
+ +1068:	01 00 00 00 	nop *
+ +106c:	01 00 00 00 	nop *
+ +1070:	01 00 00 00 	nop *
+ +1074:	01 00 00 00 	nop *
+ +1078:	01 00 00 00 	nop *
+ +107c:	19 00 00 00 	sethi  %hi\(0\), %o4
+ +1080:	98 03 20 04 	add  %o4, 4, %o4	! 4 <.*>
+ +1084:	90 05 c0 0c 	add  %l7, %o4, %o0
+ +1088:	40 00 44 3b 	call  [0-9a-f]+ <__tls_get_addr@plt>
+ +108c:	01 00 00 00 	nop *
+ +1090:	01 00 00 00 	nop *
+ +1094:	01 00 00 00 	nop *
+ +1098:	01 00 00 00 	nop *
+ +109c:	01 00 00 00 	nop *
+ +10a0:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +10a4:	90 02 20 0c 	add  %o0, 0xc, %o0	! c <.*>
+ +10a8:	d0 05 c0 08 	ld  \[ %l7 \+ %o0 \], %o0
+ +10ac:	90 01 c0 08 	add  %g7, %o0, %o0
+ +10b0:	01 00 00 00 	nop *
+ +10b4:	01 00 00 00 	nop *
+ +10b8:	01 00 00 00 	nop *
+ +10bc:	01 00 00 00 	nop *
+ +10c0:	01 00 00 00 	nop *
+ +10c4:	19 00 00 00 	sethi  %hi\(0\), %o4
+ +10c8:	98 03 20 40 	add  %o4, 0x40, %o4	! 40 <.*>
+ +10cc:	90 05 c0 0c 	add  %l7, %o4, %o0
+ +10d0:	40 00 44 29 	call  [0-9a-f]+ <__tls_get_addr@plt>
+ +10d4:	01 00 00 00 	nop *
+ +10d8:	01 00 00 00 	nop *
+ +10dc:	01 00 00 00 	nop *
+ +10e0:	01 00 00 00 	nop *
+ +10e4:	01 00 00 00 	nop *
+ +10e8:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +10ec:	90 02 20 48 	add  %o0, 0x48, %o0	! 48 <.*>
+ +10f0:	d0 05 c0 08 	ld  \[ %l7 \+ %o0 \], %o0
+ +10f4:	90 01 c0 08 	add  %g7, %o0, %o0
+ +10f8:	01 00 00 00 	nop *
+ +10fc:	01 00 00 00 	nop *
+ +1100:	01 00 00 00 	nop *
+ +1104:	01 00 00 00 	nop *
+ +1108:	01 00 00 00 	nop *
+ +110c:	19 00 00 00 	sethi  %hi\(0\), %o4
+ +1110:	98 03 20 1c 	add  %o4, 0x1c, %o4	! 1c <.*>
+ +1114:	90 05 c0 0c 	add  %l7, %o4, %o0
+ +1118:	40 00 44 17 	call  [0-9a-f]+ <__tls_get_addr@plt>
+ +111c:	01 00 00 00 	nop *
+ +1120:	01 00 00 00 	nop *
+ +1124:	01 00 00 00 	nop *
+ +1128:	01 00 00 00 	nop *
+ +112c:	01 00 00 00 	nop *
+ +1130:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +1134:	90 02 20 24 	add  %o0, 0x24, %o0	! 24 <.*>
+ +1138:	d0 05 c0 08 	ld  \[ %l7 \+ %o0 \], %o0
+ +113c:	90 01 c0 08 	add  %g7, %o0, %o0
+ +1140:	01 00 00 00 	nop *
+ +1144:	01 00 00 00 	nop *
+ +1148:	01 00 00 00 	nop *
+ +114c:	01 00 00 00 	nop *
+ +1150:	01 00 00 00 	nop *
+ +1154:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +1158:	01 00 00 00 	nop *
+ +115c:	a4 04 60 14 	add  %l1, 0x14, %l2
+ +1160:	01 00 00 00 	nop *
+ +1164:	90 05 c0 12 	add  %l7, %l2, %o0
+ +1168:	01 00 00 00 	nop *
+ +116c:	40 00 44 02 	call  [0-9a-f]+ <__tls_get_addr@plt>
+ +1170:	01 00 00 00 	nop *
+ +1174:	27 00 00 00 	sethi  %hi\(0\), %l3
+ +1178:	01 00 00 00 	nop *
+ +117c:	a8 1c e0 20 	xor  %l3, 0x20, %l4
+ +1180:	01 00 00 00 	nop *
+ +1184:	aa 02 00 14 	add  %o0, %l4, %l5
+ +1188:	01 00 00 00 	nop *
+ +118c:	25 00 00 00 	sethi  %hi\(0\), %l2
+ +1190:	01 00 00 00 	nop *
+ +1194:	a6 1c a0 26 	xor  %l2, 0x26, %l3
+ +1198:	01 00 00 00 	nop *
+ +119c:	ec 12 00 13 	lduh  \[ %o0 \+ %l3 \], %l6
+ +11a0:	01 00 00 00 	nop *
+ +11a4:	01 00 00 00 	nop *
+ +11a8:	01 00 00 00 	nop *
+ +11ac:	01 00 00 00 	nop *
+ +11b0:	13 00 00 00 	sethi  %hi\(0\), %o1
+ +11b4:	27 00 00 00 	sethi  %hi\(0\), %l3
+ +11b8:	94 02 60 14 	add  %o1, 0x14, %o2
+ +11bc:	25 00 00 00 	sethi  %hi\(0\), %l2
+ +11c0:	90 05 c0 0a 	add  %l7, %o2, %o0
+ +11c4:	a8 1c e0 40 	xor  %l3, 0x40, %l4
+ +11c8:	40 00 43 eb 	call  [0-9a-f]+ <__tls_get_addr@plt>
+ +11cc:	a6 1c a0 45 	xor  %l2, 0x45, %l3
+ +11d0:	aa 02 00 14 	add  %o0, %l4, %l5
+ +11d4:	ec 0a 00 13 	ldub  \[ %o0 \+ %l3 \], %l6
+ +11d8:	01 00 00 00 	nop *
+ +11dc:	01 00 00 00 	nop *
+ +11e0:	01 00 00 00 	nop *
+ +11e4:	01 00 00 00 	nop *
+ +11e8:	13 00 00 00 	sethi  %hi\(0\), %o1
+ +11ec:	27 00 00 00 	sethi  %hi\(0\), %l3
+ +11f0:	94 02 60 14 	add  %o1, 0x14, %o2
+ +11f4:	25 00 00 00 	sethi  %hi\(0\), %l2
+ +11f8:	90 05 c0 0a 	add  %l7, %o2, %o0
+ +11fc:	a8 1c e0 63 	xor  %l3, 0x63, %l4
+ +1200:	40 00 43 dd 	call  [0-9a-f]+ <__tls_get_addr@plt>
+ +1204:	a6 1c a0 64 	xor  %l2, 0x64, %l3
+ +1208:	aa 02 00 14 	add  %o0, %l4, %l5
+ +120c:	ec 02 00 13 	ld  \[ %o0 \+ %l3 \], %l6
+ +1210:	01 00 00 00 	nop *
+ +1214:	01 00 00 00 	nop *
+ +1218:	01 00 00 00 	nop *
+ +121c:	01 00 00 00 	nop *
+ +1220:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +1224:	01 00 00 00 	nop *
+ +1228:	a4 04 60 3c 	add  %l1, 0x3c, %l2
+ +122c:	01 00 00 00 	nop *
+ +1230:	e4 05 c0 12 	ld  \[ %l7 \+ %l2 \], %l2
+ +1234:	01 00 00 00 	nop *
+ +1238:	a4 01 c0 12 	add  %g7, %l2, %l2
+ +123c:	01 00 00 00 	nop *
+ +1240:	01 00 00 00 	nop *
+ +1244:	01 00 00 00 	nop *
+ +1248:	01 00 00 00 	nop *
+ +124c:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +1250:	96 02 e0 0c 	add  %o3, 0xc, %o3	! c <.*>
+ +1254:	d4 05 c0 0b 	ld  \[ %l7 \+ %o3 \], %o2
+ +1258:	98 01 c0 0a 	add  %g7, %o2, %o4
+ +125c:	01 00 00 00 	nop *
+ +1260:	01 00 00 00 	nop *
+ +1264:	01 00 00 00 	nop *
+ +1268:	01 00 00 00 	nop *
+ +126c:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +1270:	a4 04 60 48 	add  %l1, 0x48, %l2	! 48 <.*>
+ +1274:	e4 05 c0 12 	ld  \[ %l7 \+ %l2 \], %l2
+ +1278:	a4 01 c0 12 	add  %g7, %l2, %l2
+ +127c:	01 00 00 00 	nop *
+ +1280:	01 00 00 00 	nop *
+ +1284:	01 00 00 00 	nop *
+ +1288:	01 00 00 00 	nop *
+ +128c:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +1290:	a4 04 60 24 	add  %l1, 0x24, %l2	! 24 <.*>
+ +1294:	e4 05 c0 12 	ld  \[ %l7 \+ %l2 \], %l2
+ +1298:	a4 01 c0 12 	add  %g7, %l2, %l2
+ +129c:	01 00 00 00 	nop *
+ +12a0:	01 00 00 00 	nop *
+ +12a4:	01 00 00 00 	nop *
+ +12a8:	01 00 00 00 	nop *
+ +12ac:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +12b0:	a4 04 60 28 	add  %l1, 0x28, %l2	! 28 <.*>
+ +12b4:	e4 05 c0 12 	ld  \[ %l7 \+ %l2 \], %l2
+ +12b8:	e4 01 c0 12 	ld  \[ %g7 \+ %l2 \], %l2
+ +12bc:	01 00 00 00 	nop *
+ +12c0:	01 00 00 00 	nop *
+ +12c4:	01 00 00 00 	nop *
+ +12c8:	01 00 00 00 	nop *
+ +12cc:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +12d0:	98 02 e0 10 	add  %o3, 0x10, %o4	! 10 <.*>
+ +12d4:	da 05 c0 0c 	ld  \[ %l7 \+ %o4 \], %o5
+ +12d8:	e4 29 c0 0d 	stb  %l2, \[ %g7 \+ %o5 \]
+ +12dc:	01 00 00 00 	nop *
+ +12e0:	01 00 00 00 	nop *
+ +12e4:	01 00 00 00 	nop *
+ +12e8:	01 00 00 00 	nop *
+ +12ec:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +12f0:	98 02 e0 34 	add  %o3, 0x34, %o4	! 34 <.*>
+ +12f4:	da 05 c0 0c 	ld  \[ %l7 \+ %o4 \], %o5
+ +12f8:	e4 11 c0 0d 	lduh  \[ %g7 \+ %o5 \], %l2
+ +12fc:	01 00 00 00 	nop *
+ +1300:	01 00 00 00 	nop *
+ +1304:	01 00 00 00 	nop *
+ +1308:	01 00 00 00 	nop *
+ +130c:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +1310:	98 02 e0 38 	add  %o3, 0x38, %o4	! 38 <.*>
+ +1314:	da 05 c0 0c 	ld  \[ %l7 \+ %o4 \], %o5
+ +1318:	e4 21 c0 0d 	st  %l2, \[ %g7 \+ %o5 \]
+ +131c:	01 00 00 00 	nop *
+ +1320:	01 00 00 00 	nop *
+ +1324:	01 00 00 00 	nop *
+ +1328:	01 00 00 00 	nop *
+ +132c:	81 c7 e0 08 	ret *
+ +1330:	81 e8 00 00 	restore *
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic32.rd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic32.rd
new file mode 100644
index 0000000..f947a3c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic32.rd
@@ -0,0 +1,135 @@
+#source: tlssunpic32.s
+#source: tlspic.s
+#as: --32 -K PIC
+#ld: -shared -melf32_sparc
+#readelf: -WSsrl
+#target: sparc*-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+ +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .rela.plt +.*
+ +\[[ 0-9]+\] .text +PROGBITS +0+1000 0+1000 0+1000 0+ +AX +0 +0 4096
+ +\[[ 0-9]+\] .tdata +PROGBITS +0+12000 0+2000 0+60 0+ WAT +0 +0 +4
+ +\[[ 0-9]+\] .tbss +NOBITS +0+12060 0+2060 0+20 0+ WAT +0 +0 +4
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+12060 0+2060 0+98 08 +WA +3 +0 +4
+ +\[[ 0-9]+\] .got +PROGBITS +0+120f8 0+20f8 0+4c 04 +WA +0 +0 +4
+ +\[[ 0-9]+\] .plt +.*
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+#...
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x1000
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz MemSiz +Flg Align
+ +LOAD +0x0+ 0x0+ 0x0+ 0x0+2000 0x0+2000 R E 0x10000
+ +LOAD +0x0+2000 0x0+12000 0x0+12000 0x0+184 0x0+184 RWE 0x10000
+ +DYNAMIC +0x0+2060 0x0+12060 0x0+12060 0x0+98 0x0+98 RW +0x4
+ +TLS +0x0+2000 0x0+12000 0x0+12000 0x0+60 0x0+80 R +0x4
+#...
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
+ Offset +Info +Type +Sym. Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_SPARC_TLS_DTPMOD32 +0+
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +0+24
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +0+30
+[0-9a-f ]+R_SPARC_TLS_DTPMOD32 +0+
+[0-9a-f ]+R_SPARC_TLS_DTPMOD32 +0+
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +0+64
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +0+50
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +0+70
+[0-9a-f ]+R_SPARC_TLS_DTPMOD32 +0+
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +0+44
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +0+10 +sg5 \+ 0
+[0-9a-f ]+R_SPARC_TLS_DTPMOD32 +0+ +sg1 \+ 0
+[0-9a-f ]+R_SPARC_TLS_DTPOFF32 +0+ +sg1 \+ 0
+[0-9a-f ]+R_SPARC_TLS_TPOFF32 +0+4 +sg2 \+ 0
+
+Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ Offset +Info +Type +Sym. Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_SPARC_JMP_SLOT +0+ +__tls_get_addr \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +6 *
+.* SECTION LOCAL +DEFAULT +7 *
+.* SECTION LOCAL +DEFAULT +10 *
+.* TLS +GLOBAL DEFAULT +7 sg8
+.* TLS +GLOBAL DEFAULT +7 sg3
+.* TLS +GLOBAL DEFAULT +7 sg4
+.* TLS +GLOBAL DEFAULT +7 sg5
+.* NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +7 sg1
+.* FUNC +GLOBAL DEFAULT +6 fn1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +7 sg2
+.* TLS +GLOBAL DEFAULT +7 sg6
+.* TLS +GLOBAL DEFAULT +7 sg7
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +1 *
+.* SECTION LOCAL +DEFAULT +2 *
+.* SECTION LOCAL +DEFAULT +3 *
+.* SECTION LOCAL +DEFAULT +4 *
+.* SECTION LOCAL +DEFAULT +5 *
+.* SECTION LOCAL +DEFAULT +6 *
+.* SECTION LOCAL +DEFAULT +7 *
+.* SECTION LOCAL +DEFAULT +8 *
+.* SECTION LOCAL +DEFAULT +9 *
+.* SECTION LOCAL +DEFAULT +10 *
+.* SECTION LOCAL +DEFAULT +11 *
+.* TLS +LOCAL +DEFAULT +7 sl1
+.* TLS +LOCAL +DEFAULT +7 sl2
+.* TLS +LOCAL +DEFAULT +7 sl3
+.* TLS +LOCAL +DEFAULT +7 sl4
+.* TLS +LOCAL +DEFAULT +7 sl5
+.* TLS +LOCAL +DEFAULT +7 sl6
+.* TLS +LOCAL +DEFAULT +7 sl7
+.* TLS +LOCAL +DEFAULT +7 sl8
+.* TLS +LOCAL +HIDDEN +8 sH1
+.* OBJECT +LOCAL +HIDDEN +ABS _DYNAMIC
+.* TLS +LOCAL +HIDDEN +7 sh3
+.* TLS +LOCAL +HIDDEN +8 sH2
+.* TLS +LOCAL +HIDDEN +8 sH7
+.* OBJECT +LOCAL +HIDDEN +ABS _PROCEDURE_LINKAGE_TABLE_
+.* TLS +LOCAL +HIDDEN +7 sh7
+.* TLS +LOCAL +HIDDEN +7 sh8
+.* TLS +LOCAL +HIDDEN +8 sH4
+.* TLS +LOCAL +HIDDEN +7 sh4
+.* TLS +LOCAL +HIDDEN +8 sH3
+.* TLS +LOCAL +HIDDEN +7 sh5
+.* TLS +LOCAL +HIDDEN +8 sH5
+.* TLS +LOCAL +HIDDEN +8 sH6
+.* TLS +LOCAL +HIDDEN +8 sH8
+.* TLS +LOCAL +HIDDEN +7 sh1
+.* OBJECT +LOCAL +HIDDEN +ABS _GLOBAL_OFFSET_TABLE_
+.* TLS +LOCAL +HIDDEN +7 sh2
+.* TLS +LOCAL +HIDDEN +7 sh6
+.* TLS +GLOBAL DEFAULT +7 sg8
+.* TLS +GLOBAL DEFAULT +7 sg3
+.* TLS +GLOBAL DEFAULT +7 sg4
+.* TLS +GLOBAL DEFAULT +7 sg5
+.* NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +7 sg1
+.* FUNC +GLOBAL DEFAULT +6 fn1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +7 sg2
+.* TLS +GLOBAL DEFAULT +7 sg6
+.* TLS +GLOBAL DEFAULT +7 sg7
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic32.s b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic32.s
new file mode 100644
index 0000000..9e8a235
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic32.s
@@ -0,0 +1,228 @@
+	.data
+	.align	4096
+	.section ".tdata", #alloc, #write, #tls
+	.align	4
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.word 17
+sg2:	.word 18
+sg3:	.word 19
+sg4:	.word 20
+sg5:	.word 21
+sg6:	.word 22
+sg7:	.word 23
+sg8:	.word 24
+sl1:	.word 65
+sl2:	.word 66
+sl3:	.word 67
+sl4:	.word 68
+sl5:	.word 69
+sl6:	.word 70
+sl7:	.word 71
+sl8:	.word 72
+sh1:	.word 257
+sh2:	.word 258
+sh3:	.word 259
+sh4:	.word 260
+sh5:	.word 261
+sh6:	.word 262
+sh7:	.word 263
+sh8:	.word 264
+
+	.text
+	.align	4096
+.LLGETPC0:
+	retl
+	add	%o7, %l7, %l7
+
+	.globl	fn1
+	.type	fn1,#function
+	.proc	04
+fn1:
+	save	%sp, -104, %sp
+	sethi	%hi(_GLOBAL_OFFSET_TABLE_-4), %l7
+	call	.LLGETPC0
+	add	%l7, %lo(_GLOBAL_OFFSET_TABLE_+4), %l7
+	nop;nop;nop;nop
+
+	/* GD */
+	sethi	%tgd_hi22(sg1), %l1
+	nop
+	add	%l1, %tgd_lo10(sg1), %l2
+	nop
+	add	%l7, %l2, %o0, %tgd_add(sg1)
+	nop
+	call	__tls_get_addr, %tgd_call(sg1)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is referenced through IE too */
+	sethi	%tgd_hi22(sg2), %o0
+	add	%o0, %tgd_lo10(sg2), %o1
+	add	%l7, %o1, %o0, %tgd_add(sg2)
+	call	__tls_get_addr, %tgd_call(sg2)
+	nop
+	nop;nop;nop;nop
+
+	/* GD against local variable */
+	sethi	%tgd_hi22(sl1), %o4
+	add	%o4, %tgd_lo10(sl1), %o4
+	add	%l7, %o4, %o0, %tgd_add(sl1)
+	call	__tls_get_addr, %tgd_call(sl1)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> IE against local variable referenced through IE too */
+	sethi	%tgd_hi22(sl2), %o0
+	add	%o0, %tgd_lo10(sl2), %o0
+	add	%l7, %o0, %o0, %tgd_add(sl2)
+	call	__tls_get_addr, %tgd_call(sl2)
+	nop
+	nop;nop;nop;nop
+
+	/* GD against hidden and local variable */
+	sethi	%tgd_hi22(sh1), %o4
+	add	%o4, %tgd_lo10(sh1), %o4
+	add	%l7, %o4, %o0, %tgd_add(sh1)
+	call	__tls_get_addr, %tgd_call(sh1)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden and local variable referenced through
+	   IE too */
+	sethi	%tgd_hi22(sh2), %o0
+	add	%o0, %tgd_lo10(sh2), %o0
+	add	%l7, %o0, %o0, %tgd_add(sh2)
+	call	__tls_get_addr, %tgd_call(sh2)
+	nop
+	nop;nop;nop;nop
+
+	/* GD against hidden but not local variable */
+	sethi	%tgd_hi22(sH1), %o4
+	add	%o4, %tgd_lo10(sH1), %o4
+	add	%l7, %o4, %o0, %tgd_add(sH1)
+	call	__tls_get_addr, %tgd_call(sH1)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden but not local variable referenced through
+	   IE too */
+	sethi	%tgd_hi22(sH2), %o0
+	add	%o0, %tgd_lo10(sH2), %o0
+	add	%l7, %o0, %o0, %tgd_add(sH2)
+	call	__tls_get_addr, %tgd_call(sH2)
+	nop
+	nop;nop;nop;nop
+
+	/* LD */
+	sethi	%tldm_hi22(sl1), %l1
+	nop
+	add	%l1, %tldm_lo10(sl1), %l2
+	nop
+	add	%l7, %l2, %o0, %tldm_add(sl1)
+	nop
+	call	__tls_get_addr, %tldm_call(sl1)
+	nop
+	sethi	%tldo_hix22(sl1), %l3
+	nop
+	xor	%l3, %tldo_lox10(sl1), %l4
+	nop
+	add	%o0, %l4, %l5, %tldo_add(sl1)
+	nop
+	sethi	%tldo_hix22(sl2 + 2), %l2
+	nop
+	xor	%l2, %tldo_lox10(sl2 + 2), %l3
+	nop
+	lduh	[%o0 + %l3], %l6, %tldo_add(sl2 + 2)
+	nop;nop;nop;nop
+
+	/* LD against hidden and local variables */
+	sethi	%tldm_hi22(sh1), %o1
+	sethi	%tldo_hix22(sh1), %l3
+	add	%o1, %tldm_lo10(sh1), %o2
+	sethi	%tldo_hix22(sh2 + 1), %l2
+	add	%l7, %o2, %o0, %tldm_add(sh1)
+	xor	%l3, %tldo_lox10(sh1), %l4
+	call	__tls_get_addr, %tldm_call(sh1)
+	xor	%l2, %tldo_lox10(sh2 + 1), %l3
+	add	%o0, %l4, %l5, %tldo_add(sh1)
+	ldub	[%o0 + %l3], %l6, %tldo_add(sh2 + 1)
+	nop;nop;nop;nop
+
+	/* LD against hidden but not local variables */
+	sethi	%tldm_hi22(sH1), %o1
+	sethi	%tldo_hix22(sH1 + 3), %l3
+	add	%o1, %tldm_lo10(sH1), %o2
+	sethi	%tldo_hix22(sH2), %l2
+	add	%l7, %o2, %o0, %tldm_add(sH1)
+	xor	%l3, %tldo_lox10(sH1 + 3), %l4
+	call	__tls_get_addr, %tldm_call(sH1)
+	xor	%l2, %tldo_lox10(sH2), %l3
+	add	%o0, %l4, %l5, %tldo_add(sH1 + 3)
+	ld	[%o0 + %l3], %l6, %tldo_add(sH2)
+	nop;nop;nop;nop
+
+	/* IE against global var  */
+	sethi	%tie_hi22(sg2), %l1
+	nop
+	add	%l1, %tie_lo10(sg2), %l2
+	nop
+	ld	[%l7 + %l2], %l2, %tie_ld(sg2)
+	nop
+	add	%g7, %l2, %l2, %tie_add(sg2)
+	nop;nop;nop;nop
+
+	/* IE against local var  */
+	sethi	%tie_hi22(sl2), %o3
+	add	%o3, %tie_lo10(sl2), %o3
+	ld	[%l7 + %o3], %o2, %tie_ld(sl2)
+	add	%g7, %o2, %o4, %tie_add(sl2)
+	nop;nop;nop;nop
+
+	/* IE against hidden and local var  */
+	sethi	%tie_hi22(sh2), %l1
+	add	%l1, %tie_lo10(sh2), %l2
+	ld	[%l7 + %l2], %l2, %tie_ld(sh2)
+	add	%g7, %l2, %l2, %tie_add(sh2)
+	nop;nop;nop;nop
+
+	/* IE against hidden but not local var  */
+	sethi	%tie_hi22(sH2), %l1
+	add	%l1, %tie_lo10(sH2), %l2
+	ld	[%l7 + %l2], %l2, %tie_ld(sH2)
+	add	%g7, %l2, %l2, %tie_add(sH2)
+	nop;nop;nop;nop
+
+	/* Direct access through %g7  */
+
+	/* IE against global var  */
+	sethi	%tie_hi22(sg5), %l1
+	add	%l1, %tie_lo10(sg5), %l2
+	ld	[%l7 + %l2], %l2, %tie_ld(sg5)
+	ld	[%g7 + %l2], %l2, %tie_add(sg5)
+	nop;nop;nop;nop
+
+	/* IE against local var  */
+	sethi	%tie_hi22(sl5), %o3
+	add	%o3, %tie_lo10(sl5), %o4
+	ld	[%l7 + %o4], %o5, %tie_ld(sl5)
+	stb	%l2, [%g7 + %o5], %tie_add(sl5)
+	nop;nop;nop;nop
+
+	/* IE against hidden and local var  */
+	sethi	%tie_hi22(sh5), %o3
+	add	%o3, %tie_lo10(sh5), %o4
+	ld	[%l7 + %o4], %o5, %tie_ld(sh5)
+	lduh	[%g7 + %o5], %l2, %tie_add(sh5)
+	nop;nop;nop;nop
+
+	/* IE against hidden but not local var  */
+	sethi	%tie_hi22(sH5), %o3
+	add	%o3, %tie_lo10(sH5), %o4
+	ld	[%l7 + %o4], %o5, %tie_ld(sH5)
+	st	%l2, [%g7 + %o5], %tie_add(sH5)
+	nop;nop;nop;nop
+
+	ret
+	restore
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic32.sd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic32.sd
new file mode 100644
index 0000000..4aecfd7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic32.sd
@@ -0,0 +1,15 @@
+#source: tlssunpic32.s
+#source: tlspic.s
+#as: --32 -K PIC
+#ld: -shared -melf32_sparc
+#objdump: -sj.got
+#target: sparc*-*-*
+
+.*: +file format elf32-sparc
+
+Contents of section .got:
+ 120f8 00012060 00000000 00000020 00000000  .*
+ 12108 00000000 00000000 00000000 00000000  .*
+ 12118 00000060 00000000 00000000 00000000  .*
+ 12128 00000000 00000000 00000000 00000000  .*
+ 12138 00000000 00000040 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic32.td b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic32.td
new file mode 100644
index 0000000..eb4e344
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic32.td
@@ -0,0 +1,16 @@
+#source: tlssunpic32.s
+#source: tlspic.s
+#as: --32 -K PIC
+#ld: -shared -melf32_sparc
+#objdump: -sj.tdata
+#target: sparc*-*-*
+
+.*: +file format elf32-sparc
+
+Contents of section .tdata:
+ 12000 00000011 00000012 00000013 00000014  .*
+ 12010 00000015 00000016 00000017 00000018  .*
+ 12020 00000041 00000042 00000043 00000044  .*
+ 12030 00000045 00000046 00000047 00000048  .*
+ 12040 00000101 00000102 00000103 00000104  .*
+ 12050 00000105 00000106 00000107 00000108  .*
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic64.dd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic64.dd
new file mode 100644
index 0000000..0b41b68
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic64.dd
@@ -0,0 +1,220 @@
+#source: tlssunpic64.s
+#source: tlspic.s
+#as: --64 -Av9 -K PIC
+#ld: -shared -melf64_sparc
+#objdump: -drj.text
+#target: sparc*-*-*
+
+.*: +file format elf64-sparc
+
+Disassembly of section .text:
+
+0+1000 <fn1-0x8>:
+ +1000:	81 c3 e0 08 	retl *
+ +1004:	ae 03 c0 17 	add  %o7, %l7, %l7
+
+0+1008 <fn1>:
+ +1008:	9d e3 bf 60 	save  %sp, -160, %sp
+ +100c:	2f 00 04 04 	sethi  %hi\(0x101000\), %l7
+ +1010:	7f ff ff fc 	call  1000 <.*>
+ +1014:	ae 05 e1 80 	add  %l7, 0x180, %l7	! 101180 <.*>
+ +1018:	01 00 00 00 	nop *
+ +101c:	01 00 00 00 	nop *
+ +1020:	01 00 00 00 	nop *
+ +1024:	01 00 00 00 	nop *
+ +1028:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +102c:	01 00 00 00 	nop *
+ +1030:	a4 04 60 58 	add  %l1, 0x58, %l2
+ +1034:	01 00 00 00 	nop *
+ +1038:	90 05 c0 12 	add  %l7, %l2, %o0
+ +103c:	01 00 00 00 	nop *
+ +1040:	40 04 04 d0 	call  [0-9a-f]+ <__tls_get_addr@plt>
+ +1044:	01 00 00 00 	nop *
+ +1048:	01 00 00 00 	nop *
+ +104c:	01 00 00 00 	nop *
+ +1050:	01 00 00 00 	nop *
+ +1054:	01 00 00 00 	nop *
+ +1058:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +105c:	92 02 20 78 	add  %o0, 0x78, %o1	! 78 <.*>
+ +1060:	d0 5d c0 09 	ldx  \[ %l7 \+ %o1 \], %o0
+ +1064:	90 01 c0 08 	add  %g7, %o0, %o0
+ +1068:	01 00 00 00 	nop *
+ +106c:	01 00 00 00 	nop *
+ +1070:	01 00 00 00 	nop *
+ +1074:	01 00 00 00 	nop *
+ +1078:	01 00 00 00 	nop *
+ +107c:	19 00 00 00 	sethi  %hi\(0\), %o4
+ +1080:	98 03 20 08 	add  %o4, 8, %o4	! 8 <.*>
+ +1084:	90 05 c0 0c 	add  %l7, %o4, %o0
+ +1088:	40 04 04 be 	call  [0-9a-f]+ <__tls_get_addr@plt>
+ +108c:	01 00 00 00 	nop *
+ +1090:	01 00 00 00 	nop *
+ +1094:	01 00 00 00 	nop *
+ +1098:	01 00 00 00 	nop *
+ +109c:	01 00 00 00 	nop *
+ +10a0:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +10a4:	90 02 20 18 	add  %o0, 0x18, %o0	! 18 <.*>
+ +10a8:	d0 5d c0 08 	ldx  \[ %l7 \+ %o0 \], %o0
+ +10ac:	90 01 c0 08 	add  %g7, %o0, %o0
+ +10b0:	01 00 00 00 	nop *
+ +10b4:	01 00 00 00 	nop *
+ +10b8:	01 00 00 00 	nop *
+ +10bc:	01 00 00 00 	nop *
+ +10c0:	01 00 00 00 	nop *
+ +10c4:	19 00 00 00 	sethi  %hi\(0\), %o4
+ +10c8:	98 03 20 80 	add  %o4, 0x80, %o4	! 80 <.*>
+ +10cc:	90 05 c0 0c 	add  %l7, %o4, %o0
+ +10d0:	40 04 04 ac 	call  [0-9a-f]+ <__tls_get_addr@plt>
+ +10d4:	01 00 00 00 	nop *
+ +10d8:	01 00 00 00 	nop *
+ +10dc:	01 00 00 00 	nop *
+ +10e0:	01 00 00 00 	nop *
+ +10e4:	01 00 00 00 	nop *
+ +10e8:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +10ec:	90 02 20 90 	add  %o0, 0x90, %o0	! 90 <.*>
+ +10f0:	d0 5d c0 08 	ldx  \[ %l7 \+ %o0 \], %o0
+ +10f4:	90 01 c0 08 	add  %g7, %o0, %o0
+ +10f8:	01 00 00 00 	nop *
+ +10fc:	01 00 00 00 	nop *
+ +1100:	01 00 00 00 	nop *
+ +1104:	01 00 00 00 	nop *
+ +1108:	01 00 00 00 	nop *
+ +110c:	19 00 00 00 	sethi  %hi\(0\), %o4
+ +1110:	98 03 20 38 	add  %o4, 0x38, %o4	! 38 <.*>
+ +1114:	90 05 c0 0c 	add  %l7, %o4, %o0
+ +1118:	40 04 04 9a 	call  [0-9a-f]+ <__tls_get_addr@plt>
+ +111c:	01 00 00 00 	nop *
+ +1120:	01 00 00 00 	nop *
+ +1124:	01 00 00 00 	nop *
+ +1128:	01 00 00 00 	nop *
+ +112c:	01 00 00 00 	nop *
+ +1130:	11 00 00 00 	sethi  %hi\(0\), %o0
+ +1134:	90 02 20 48 	add  %o0, 0x48, %o0	! 48 <.*>
+ +1138:	d0 5d c0 08 	ldx  \[ %l7 \+ %o0 \], %o0
+ +113c:	90 01 c0 08 	add  %g7, %o0, %o0
+ +1140:	01 00 00 00 	nop *
+ +1144:	01 00 00 00 	nop *
+ +1148:	01 00 00 00 	nop *
+ +114c:	01 00 00 00 	nop *
+ +1150:	01 00 00 00 	nop *
+ +1154:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +1158:	01 00 00 00 	nop *
+ +115c:	a4 04 60 28 	add  %l1, 0x28, %l2
+ +1160:	01 00 00 00 	nop *
+ +1164:	90 05 c0 12 	add  %l7, %l2, %o0
+ +1168:	01 00 00 00 	nop *
+ +116c:	40 04 04 85 	call  [0-9a-f]+ <__tls_get_addr@plt>
+ +1170:	01 00 00 00 	nop *
+ +1174:	27 00 00 00 	sethi  %hi\(0\), %l3
+ +1178:	01 00 00 00 	nop *
+ +117c:	a8 1c e0 20 	xor  %l3, 0x20, %l4
+ +1180:	01 00 00 00 	nop *
+ +1184:	aa 02 00 14 	add  %o0, %l4, %l5
+ +1188:	01 00 00 00 	nop *
+ +118c:	25 00 00 00 	sethi  %hi\(0\), %l2
+ +1190:	01 00 00 00 	nop *
+ +1194:	a6 1c a0 26 	xor  %l2, 0x26, %l3
+ +1198:	01 00 00 00 	nop *
+ +119c:	ec 12 00 13 	lduh  \[ %o0 \+ %l3 \], %l6
+ +11a0:	01 00 00 00 	nop *
+ +11a4:	01 00 00 00 	nop *
+ +11a8:	01 00 00 00 	nop *
+ +11ac:	01 00 00 00 	nop *
+ +11b0:	13 00 00 00 	sethi  %hi\(0\), %o1
+ +11b4:	27 00 00 00 	sethi  %hi\(0\), %l3
+ +11b8:	94 02 60 28 	add  %o1, 0x28, %o2
+ +11bc:	25 00 00 00 	sethi  %hi\(0\), %l2
+ +11c0:	90 05 c0 0a 	add  %l7, %o2, %o0
+ +11c4:	a8 1c e0 40 	xor  %l3, 0x40, %l4
+ +11c8:	40 04 04 6e 	call  [0-9a-f]+ <__tls_get_addr@plt>
+ +11cc:	a6 1c a0 45 	xor  %l2, 0x45, %l3
+ +11d0:	ea 5a 00 14 	ldx  \[ %o0 \+ %l4 \], %l5
+ +11d4:	ac 02 00 13 	add  %o0, %l3, %l6
+ +11d8:	01 00 00 00 	nop *
+ +11dc:	01 00 00 00 	nop *
+ +11e0:	01 00 00 00 	nop *
+ +11e4:	01 00 00 00 	nop *
+ +11e8:	13 00 00 00 	sethi  %hi\(0\), %o1
+ +11ec:	27 00 00 00 	sethi  %hi\(0\), %l3
+ +11f0:	94 02 60 28 	add  %o1, 0x28, %o2
+ +11f4:	25 00 00 00 	sethi  %hi\(0\), %l2
+ +11f8:	90 05 c0 0a 	add  %l7, %o2, %o0
+ +11fc:	a8 1c e0 63 	xor  %l3, 0x63, %l4
+ +1200:	40 04 04 60 	call  [0-9a-f]+ <__tls_get_addr@plt>
+ +1204:	a6 1c a0 64 	xor  %l2, 0x64, %l3
+ +1208:	aa 02 00 14 	add  %o0, %l4, %l5
+ +120c:	ec 02 00 13 	ld  \[ %o0 \+ %l3 \], %l6
+ +1210:	01 00 00 00 	nop *
+ +1214:	01 00 00 00 	nop *
+ +1218:	01 00 00 00 	nop *
+ +121c:	01 00 00 00 	nop *
+ +1220:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +1224:	01 00 00 00 	nop *
+ +1228:	a4 04 60 78 	add  %l1, 0x78, %l2
+ +122c:	01 00 00 00 	nop *
+ +1230:	e4 5d c0 12 	ldx  \[ %l7 \+ %l2 \], %l2
+ +1234:	01 00 00 00 	nop *
+ +1238:	a4 01 c0 12 	add  %g7, %l2, %l2
+ +123c:	01 00 00 00 	nop *
+ +1240:	01 00 00 00 	nop *
+ +1244:	01 00 00 00 	nop *
+ +1248:	01 00 00 00 	nop *
+ +124c:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +1250:	96 02 e0 18 	add  %o3, 0x18, %o3	! 18 <.*>
+ +1254:	d4 5d c0 0b 	ldx  \[ %l7 \+ %o3 \], %o2
+ +1258:	98 01 c0 0a 	add  %g7, %o2, %o4
+ +125c:	01 00 00 00 	nop *
+ +1260:	01 00 00 00 	nop *
+ +1264:	01 00 00 00 	nop *
+ +1268:	01 00 00 00 	nop *
+ +126c:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +1270:	a4 04 60 90 	add  %l1, 0x90, %l2	! 90 <.*>
+ +1274:	e4 5d c0 12 	ldx  \[ %l7 \+ %l2 \], %l2
+ +1278:	a4 01 c0 12 	add  %g7, %l2, %l2
+ +127c:	01 00 00 00 	nop *
+ +1280:	01 00 00 00 	nop *
+ +1284:	01 00 00 00 	nop *
+ +1288:	01 00 00 00 	nop *
+ +128c:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +1290:	a4 04 60 48 	add  %l1, 0x48, %l2	! 48 <.*>
+ +1294:	e4 5d c0 12 	ldx  \[ %l7 \+ %l2 \], %l2
+ +1298:	a4 01 c0 12 	add  %g7, %l2, %l2
+ +129c:	01 00 00 00 	nop *
+ +12a0:	01 00 00 00 	nop *
+ +12a4:	01 00 00 00 	nop *
+ +12a8:	01 00 00 00 	nop *
+ +12ac:	23 00 00 00 	sethi  %hi\(0\), %l1
+ +12b0:	a4 04 60 50 	add  %l1, 0x50, %l2	! 50 <.*>
+ +12b4:	e4 5d c0 12 	ldx  \[ %l7 \+ %l2 \], %l2
+ +12b8:	e4 59 c0 12 	ldx  \[ %g7 \+ %l2 \], %l2
+ +12bc:	01 00 00 00 	nop *
+ +12c0:	01 00 00 00 	nop *
+ +12c4:	01 00 00 00 	nop *
+ +12c8:	01 00 00 00 	nop *
+ +12cc:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +12d0:	98 02 e0 20 	add  %o3, 0x20, %o4	! 20 <.*>
+ +12d4:	da 5d c0 0c 	ldx  \[ %l7 \+ %o4 \], %o5
+ +12d8:	e4 29 c0 0d 	stb  %l2, \[ %g7 \+ %o5 \]
+ +12dc:	01 00 00 00 	nop *
+ +12e0:	01 00 00 00 	nop *
+ +12e4:	01 00 00 00 	nop *
+ +12e8:	01 00 00 00 	nop *
+ +12ec:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +12f0:	98 02 e0 68 	add  %o3, 0x68, %o4	! 68 <.*>
+ +12f4:	da 5d c0 0c 	ldx  \[ %l7 \+ %o4 \], %o5
+ +12f8:	e4 71 c0 0d 	stx  %l2, \[ %g7 \+ %o5 \]
+ +12fc:	01 00 00 00 	nop *
+ +1300:	01 00 00 00 	nop *
+ +1304:	01 00 00 00 	nop *
+ +1308:	01 00 00 00 	nop *
+ +130c:	17 00 00 00 	sethi  %hi\(0\), %o3
+ +1310:	98 02 e0 70 	add  %o3, 0x70, %o4	! 70 <.*>
+ +1314:	da 5d c0 0c 	ldx  \[ %l7 \+ %o4 \], %o5
+ +1318:	e4 21 c0 0d 	st  %l2, \[ %g7 \+ %o5 \]
+ +131c:	01 00 00 00 	nop *
+ +1320:	01 00 00 00 	nop *
+ +1324:	01 00 00 00 	nop *
+ +1328:	01 00 00 00 	nop *
+ +132c:	81 cf e0 08 	rett  %i7 \+ 8
+ +1330:	01 00 00 00 	nop *
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic64.rd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic64.rd
new file mode 100644
index 0000000..e063358
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic64.rd
@@ -0,0 +1,135 @@
+#source: tlssunpic64.s
+#source: tlspic.s
+#as: --64 -Av9 -K PIC
+#ld: -shared -melf64_sparc
+#readelf: -WSsrl
+#target: sparc*-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+ +\[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .rela.plt +.*
+ +\[[ 0-9]+\] .text +PROGBITS +0+1000 0+1000 0+1000 0+ +AX +0 +0 4096
+ +\[[ 0-9]+\] .tdata +PROGBITS +0+102000 0+2000 0+60 0+ WAT +0 +0 +4
+ +\[[ 0-9]+\] .tbss +NOBITS +0+102060 0+2060 0+20 0+ WAT +0 +0 +4
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+102060 0+2060 0+130 10 +WA +3 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+102190 0+2190 0+98 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .plt +.*
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+#...
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x1000
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+ +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+ +LOAD +0x0+ 0x0+ 0x0+ 0x0+2000 0x0+2000 R E 0x100000
+ +LOAD +0x0+2000 0x0+102000 0x0+102000 0x0+3a0 0x0+3a0 RWE 0x100000
+ +DYNAMIC +0x0+2060 0x0+102060 0x0+102060 0x0+130 0x0+130 RW +0x8
+ +TLS +0x0+2000 0x0+102000 0x0+102000 0x0+60 0x0+80 R +0x4
+#...
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_SPARC_TLS_DTPMOD64 +0+
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+24
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+30
+[0-9a-f ]+R_SPARC_TLS_DTPMOD64 +0+
+[0-9a-f ]+R_SPARC_TLS_DTPMOD64 +0+
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+64
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+50
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+70
+[0-9a-f ]+R_SPARC_TLS_DTPMOD64 +0+
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+44
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+10 +sg5 \+ 0
+[0-9a-f ]+R_SPARC_TLS_DTPMOD64 +0+ +sg1 \+ 0
+[0-9a-f ]+R_SPARC_TLS_DTPOFF64 +0+ +sg1 \+ 0
+[0-9a-f ]+R_SPARC_TLS_TPOFF64 +0+4 +sg2 \+ 0
+
+Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_SPARC_JMP_SLOT +0+ +__tls_get_addr \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +6 *
+.* SECTION LOCAL +DEFAULT +7 *
+.* SECTION LOCAL +DEFAULT +10 *
+.* TLS +GLOBAL DEFAULT +7 sg8
+.* TLS +GLOBAL DEFAULT +7 sg3
+.* TLS +GLOBAL DEFAULT +7 sg4
+.* TLS +GLOBAL DEFAULT +7 sg5
+.* NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +7 sg1
+.* FUNC +GLOBAL DEFAULT +6 fn1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +7 sg2
+.* TLS +GLOBAL DEFAULT +7 sg6
+.* TLS +GLOBAL DEFAULT +7 sg7
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE +LOCAL +DEFAULT +UND *
+.* SECTION LOCAL +DEFAULT +1 *
+.* SECTION LOCAL +DEFAULT +2 *
+.* SECTION LOCAL +DEFAULT +3 *
+.* SECTION LOCAL +DEFAULT +4 *
+.* SECTION LOCAL +DEFAULT +5 *
+.* SECTION LOCAL +DEFAULT +6 *
+.* SECTION LOCAL +DEFAULT +7 *
+.* SECTION LOCAL +DEFAULT +8 *
+.* SECTION LOCAL +DEFAULT +9 *
+.* SECTION LOCAL +DEFAULT +10 *
+.* SECTION LOCAL +DEFAULT +11 *
+.* TLS +LOCAL +DEFAULT +7 sl1
+.* TLS +LOCAL +DEFAULT +7 sl2
+.* TLS +LOCAL +DEFAULT +7 sl3
+.* TLS +LOCAL +DEFAULT +7 sl4
+.* TLS +LOCAL +DEFAULT +7 sl5
+.* TLS +LOCAL +DEFAULT +7 sl6
+.* TLS +LOCAL +DEFAULT +7 sl7
+.* TLS +LOCAL +DEFAULT +7 sl8
+.* TLS +LOCAL +HIDDEN +8 sH1
+.* OBJECT +LOCAL +HIDDEN +ABS _DYNAMIC
+.* TLS +LOCAL +HIDDEN +7 sh3
+.* TLS +LOCAL +HIDDEN +8 sH2
+.* TLS +LOCAL +HIDDEN +8 sH7
+.* OBJECT +LOCAL +HIDDEN +ABS _PROCEDURE_LINKAGE_TABLE_
+.* TLS +LOCAL +HIDDEN +7 sh7
+.* TLS +LOCAL +HIDDEN +7 sh8
+.* TLS +LOCAL +HIDDEN +8 sH4
+.* TLS +LOCAL +HIDDEN +7 sh4
+.* TLS +LOCAL +HIDDEN +8 sH3
+.* TLS +LOCAL +HIDDEN +7 sh5
+.* TLS +LOCAL +HIDDEN +8 sH5
+.* TLS +LOCAL +HIDDEN +8 sH6
+.* TLS +LOCAL +HIDDEN +8 sH8
+.* TLS +LOCAL +HIDDEN +7 sh1
+.* OBJECT +LOCAL  HIDDEN +ABS _GLOBAL_OFFSET_TABLE_
+.* TLS +LOCAL +HIDDEN +7 sh2
+.* TLS +LOCAL +HIDDEN +7 sh6
+.* TLS +GLOBAL DEFAULT +7 sg8
+.* TLS +GLOBAL DEFAULT +7 sg3
+.* TLS +GLOBAL DEFAULT +7 sg4
+.* TLS +GLOBAL DEFAULT +7 sg5
+.* NOTYPE +GLOBAL DEFAULT +UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +7 sg1
+.* FUNC +GLOBAL DEFAULT +6 fn1
+.* NOTYPE +GLOBAL DEFAULT +ABS __bss_start
+.* TLS +GLOBAL DEFAULT +7 sg2
+.* TLS +GLOBAL DEFAULT +7 sg6
+.* TLS +GLOBAL DEFAULT +7 sg7
+.* NOTYPE +GLOBAL DEFAULT +ABS _edata
+.* NOTYPE +GLOBAL DEFAULT +ABS _end
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic64.s b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic64.s
new file mode 100644
index 0000000..14e110d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic64.s
@@ -0,0 +1,228 @@
+	.data
+	.align	4096
+	.section ".tdata", #alloc, #write, #tls
+	.align	4
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.word 17
+sg2:	.word 18
+sg3:	.word 19
+sg4:	.word 20
+sg5:	.word 21
+sg6:	.word 22
+sg7:	.word 23
+sg8:	.word 24
+sl1:	.word 65
+sl2:	.word 66
+sl3:	.word 67
+sl4:	.word 68
+sl5:	.word 69
+sl6:	.word 70
+sl7:	.word 71
+sl8:	.word 72
+sh1:	.word 257
+sh2:	.word 258
+sh3:	.word 259
+sh4:	.word 260
+sh5:	.word 261
+sh6:	.word 262
+sh7:	.word 263
+sh8:	.word 264
+
+	.text
+	.align	4096
+.LLGETPC0:
+	retl
+	add	%o7, %l7, %l7
+
+	.globl	fn1
+	.type	fn1,#function
+	.proc	04
+fn1:
+	save	%sp, -160, %sp
+	sethi	%hi(_GLOBAL_OFFSET_TABLE_-4), %l7
+	call	.LLGETPC0
+	add	%l7, %lo(_GLOBAL_OFFSET_TABLE_+4), %l7
+	nop;nop;nop;nop
+
+	/* GD */
+	sethi	%tgd_hi22(sg1), %l1
+	nop
+	add	%l1, %tgd_lo10(sg1), %l2
+	nop
+	add	%l7, %l2, %o0, %tgd_add(sg1)
+	nop
+	call	__tls_get_addr, %tgd_call(sg1)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is referenced through IE too */
+	sethi	%tgd_hi22(sg2), %o0
+	add	%o0, %tgd_lo10(sg2), %o1
+	add	%l7, %o1, %o0, %tgd_add(sg2)
+	call	__tls_get_addr, %tgd_call(sg2)
+	nop
+	nop;nop;nop;nop
+
+	/* GD against local variable */
+	sethi	%tgd_hi22(sl1), %o4
+	add	%o4, %tgd_lo10(sl1), %o4
+	add	%l7, %o4, %o0, %tgd_add(sl1)
+	call	__tls_get_addr, %tgd_call(sl1)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> IE against local variable referenced through IE too */
+	sethi	%tgd_hi22(sl2), %o0
+	add	%o0, %tgd_lo10(sl2), %o0
+	add	%l7, %o0, %o0, %tgd_add(sl2)
+	call	__tls_get_addr, %tgd_call(sl2)
+	nop
+	nop;nop;nop;nop
+
+	/* GD against hidden and local variable */
+	sethi	%tgd_hi22(sh1), %o4
+	add	%o4, %tgd_lo10(sh1), %o4
+	add	%l7, %o4, %o0, %tgd_add(sh1)
+	call	__tls_get_addr, %tgd_call(sh1)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden and local variable referenced through
+	   IE too */
+	sethi	%tgd_hi22(sh2), %o0
+	add	%o0, %tgd_lo10(sh2), %o0
+	add	%l7, %o0, %o0, %tgd_add(sh2)
+	call	__tls_get_addr, %tgd_call(sh2)
+	nop
+	nop;nop;nop;nop
+
+	/* GD against hidden but not local variable */
+	sethi	%tgd_hi22(sH1), %o4
+	add	%o4, %tgd_lo10(sH1), %o4
+	add	%l7, %o4, %o0, %tgd_add(sH1)
+	call	__tls_get_addr, %tgd_call(sH1)
+	nop
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden but not local variable referenced through
+	   IE too */
+	sethi	%tgd_hi22(sH2), %o0
+	add	%o0, %tgd_lo10(sH2), %o0
+	add	%l7, %o0, %o0, %tgd_add(sH2)
+	call	__tls_get_addr, %tgd_call(sH2)
+	nop
+	nop;nop;nop;nop
+
+	/* LD */
+	sethi	%tldm_hi22(sl1), %l1
+	nop
+	add	%l1, %tldm_lo10(sl1), %l2
+	nop
+	add	%l7, %l2, %o0, %tldm_add(sl1)
+	nop
+	call	__tls_get_addr, %tldm_call(sl1)
+	nop
+	sethi	%tldo_hix22(sl1), %l3
+	nop
+	xor	%l3, %tldo_lox10(sl1), %l4
+	nop
+	add	%o0, %l4, %l5, %tldo_add(sl1)
+	nop
+	sethi	%tldo_hix22(sl2 + 2), %l2
+	nop
+	xor	%l2, %tldo_lox10(sl2 + 2), %l3
+	nop
+	lduh	[%o0 + %l3], %l6, %tldo_add(sl2 + 2)
+	nop;nop;nop;nop
+
+	/* LD against hidden and local variables */
+	sethi	%tldm_hi22(sh1), %o1
+	sethi	%tldo_hix22(sh1), %l3
+	add	%o1, %tldm_lo10(sh1), %o2
+	sethi	%tldo_hix22(sh2 + 1), %l2
+	add	%l7, %o2, %o0, %tldm_add(sh1)
+	xor	%l3, %tldo_lox10(sh1), %l4
+	call	__tls_get_addr, %tldm_call(sh1)
+	xor	%l2, %tldo_lox10(sh2 + 1), %l3
+	ldx	[%o0 + %l4], %l5, %tldo_add(sh1)
+	add	%o0, %l3, %l6, %tldo_add(sh2 + 1)
+	nop;nop;nop;nop
+
+	/* LD against hidden but not local variables */
+	sethi	%tldm_hi22(sH1), %o1
+	sethi	%tldo_hix22(sH1 + 3), %l3
+	add	%o1, %tldm_lo10(sH1), %o2
+	sethi	%tldo_hix22(sH2), %l2
+	add	%l7, %o2, %o0, %tldm_add(sH1)
+	xor	%l3, %tldo_lox10(sH1 + 3), %l4
+	call	__tls_get_addr, %tldm_call(sH1)
+	xor	%l2, %tldo_lox10(sH2), %l3
+	add	%o0, %l4, %l5, %tldo_add(sH1 + 3)
+	ld	[%o0 + %l3], %l6, %tldo_add(sH2)
+	nop;nop;nop;nop
+
+	/* IE against global var  */
+	sethi	%tie_hi22(sg2), %l1
+	nop
+	add	%l1, %tie_lo10(sg2), %l2
+	nop
+	ldx	[%l7 + %l2], %l2, %tie_ldx(sg2)
+	nop
+	add	%g7, %l2, %l2, %tie_add(sg2)
+	nop;nop;nop;nop
+
+	/* IE against local var  */
+	sethi	%tie_hi22(sl2), %o3
+	add	%o3, %tie_lo10(sl2), %o3
+	ldx	[%l7 + %o3], %o2, %tie_ldx(sl2)
+	add	%g7, %o2, %o4, %tie_add(sl2)
+	nop;nop;nop;nop
+
+	/* IE against hidden and local var  */
+	sethi	%tie_hi22(sh2), %l1
+	add	%l1, %tie_lo10(sh2), %l2
+	ldx	[%l7 + %l2], %l2, %tie_ldx(sh2)
+	add	%g7, %l2, %l2, %tie_add(sh2)
+	nop;nop;nop;nop
+
+	/* IE against hidden but not local var  */
+	sethi	%tie_hi22(sH2), %l1
+	add	%l1, %tie_lo10(sH2), %l2
+	ldx	[%l7 + %l2], %l2, %tie_ldx(sH2)
+	add	%g7, %l2, %l2, %tie_add(sH2)
+	nop;nop;nop;nop
+
+	/* Direct access through %g7  */
+
+	/* IE against global var  */
+	sethi	%tie_hi22(sg5), %l1
+	add	%l1, %tie_lo10(sg5), %l2
+	ldx	[%l7 + %l2], %l2, %tie_ldx(sg5)
+	ldx	[%g7 + %l2], %l2, %tie_add(sg5)
+	nop;nop;nop;nop
+
+	/* IE against local var  */
+	sethi	%tie_hi22(sl5), %o3
+	add	%o3, %tie_lo10(sl5), %o4
+	ldx	[%l7 + %o4], %o5, %tie_ldx(sl5)
+	stb	%l2, [%g7 + %o5], %tie_add(sl5)
+	nop;nop;nop;nop
+
+	/* IE against hidden and local var  */
+	sethi	%tie_hi22(sh5), %o3
+	add	%o3, %tie_lo10(sh5), %o4
+	ldx	[%l7 + %o4], %o5, %tie_ldx(sh5)
+	stx	%l2, [%g7 + %o5], %tie_add(sh5)
+	nop;nop;nop;nop
+
+	/* IE against hidden but not local var  */
+	sethi	%tie_hi22(sH5), %o3
+	add	%o3, %tie_lo10(sH5), %o4
+	ldx	[%l7 + %o4], %o5, %tie_ldx(sH5)
+	st	%l2, [%g7 + %o5], %tie_add(sH5)
+	nop;nop;nop;nop
+
+	return	%i7 + 8
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic64.sd b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic64.sd
new file mode 100644
index 0000000..9061c2e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic64.sd
@@ -0,0 +1,20 @@
+#source: tlssunpic64.s
+#source: tlspic.s
+#as: --64 -K PIC
+#ld: -shared -melf64_sparc
+#objdump: -sj.got
+#target: sparc*-*-*
+
+.*: +file format elf64-sparc
+
+Contents of section .got:
+ 102190 00000000 00102060 00000000 00000000  .*
+ 1021a0 00000000 00000020 00000000 00000000  .*
+ 1021b0 00000000 00000000 00000000 00000000  .*
+ 1021c0 00000000 00000000 00000000 00000000  .*
+ 1021d0 00000000 00000060 00000000 00000000  .*
+ 1021e0 00000000 00000000 00000000 00000000  .*
+ 1021f0 00000000 00000000 00000000 00000000  .*
+ 102200 00000000 00000000 00000000 00000000  .*
+ 102210 00000000 00000000 00000000 00000040  .*
+ 102220 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic64.td b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic64.td
new file mode 100644
index 0000000..1e82d2b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/tlssunpic64.td
@@ -0,0 +1,16 @@
+#source: tlssunpic64.s
+#source: tlspic.s
+#as: --64 -K PIC
+#ld: -shared -melf64_sparc
+#objdump: -sj.tdata
+#target: sparc*-*-*
+
+.*: +file format elf64-sparc
+
+Contents of section .tdata:
+ 102000 00000011 00000012 00000013 00000014  .*
+ 102010 00000015 00000016 00000017 00000018  .*
+ 102020 00000041 00000042 00000043 00000044  .*
+ 102030 00000045 00000046 00000047 00000048  .*
+ 102040 00000101 00000102 00000103 00000104  .*
+ 102050 00000105 00000106 00000107 00000108  .*
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-lib.dd b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-lib.dd
new file mode 100644
index 0000000..49dab7b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-lib.dd
@@ -0,0 +1,45 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+00080800 <_PROCEDURE_LINKAGE_TABLE_>:
+   80800:	c4 05 e0 08 	ld  \[ %l7 \+ 8 \], %g2
+   80804:	81 c0 80 00 	jmp  %g2
+   80808:	01 00 00 00 	nop 
+   8080c:	03 00 00 00 	sethi  %hi\(0\), %g1
+   80810:	82 10 60 0c 	or  %g1, 0xc, %g1	! c <_PROCEDURE_LINKAGE_TABLE_-0x807f4>
+   80814:	c2 05 c0 01 	ld  \[ %l7 \+ %g1 \], %g1
+   80818:	81 c0 40 00 	jmp  %g1
+   8081c:	01 00 00 00 	nop 
+   80820:	03 00 00 00 	sethi  %hi\(0\), %g1
+   80824:	10 bf ff f7 	b  80800 <_PROCEDURE_LINKAGE_TABLE_>
+   80828:	82 10 60 00 	mov  %g1, %g1	! 0 <_PROCEDURE_LINKAGE_TABLE_-0x80800>
+Disassembly of section \.text:
+
+00080c00 <foo>:
+   80c00:	9d e3 bf 98 	save  %sp, -104, %sp
+   80c04:	2f 00 00 00 	sethi  %hi\(0\), %l7
+   80c08:	ee 05 e0 00 	ld  \[ %l7 \], %l7
+   80c0c:	ee 05 e0 00 	ld  \[ %l7 \], %l7
+   80c10:	03 00 00 00 	sethi  %hi\(0\), %g1
+   80c14:	82 10 60 10 	or  %g1, 0x10, %g1	! 10 <_PROCEDURE_LINKAGE_TABLE_-0x807f0>
+   80c18:	c2 05 c0 01 	ld  \[ %l7 \+ %g1 \], %g1
+   80c1c:	c4 00 40 00 	ld  \[ %g1 \], %g2
+   80c20:	84 00 a0 01 	inc  %g2
+   80c24:	40 00 00 08 	call  80c44 <slocal>
+   80c28:	c4 20 40 00 	st  %g2, \[ %g1 \]
+   80c2c:	7f ff fe f8 	call  8080c <_PROCEDURE_LINKAGE_TABLE_\+0xc>
+   80c30:	01 00 00 00 	nop 
+   80c34:	7f ff fe f6 	call  8080c <_PROCEDURE_LINKAGE_TABLE_\+0xc>
+   80c38:	01 00 00 00 	nop 
+   80c3c:	81 c7 e0 08 	ret 
+   80c40:	81 e8 00 00 	restore 
+
+00080c44 <slocal>:
+   80c44:	81 c3 e0 08 	retl 
+   80c48:	01 00 00 00 	nop 
+
+00080c4c <sglobal>:
+   80c4c:	81 c3 e0 08 	retl 
+   80c50:	01 00 00 00 	nop 
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-lib.nd b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-lib.nd
new file mode 100644
index 0000000..cbc1c8c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-lib.nd
@@ -0,0 +1,9 @@
+#...
+Symbol table '\.dynsym' .*:
+#...
+.*: 00090400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
+#...
+Symbol table '\.symtab' .*:
+#...
+.*: 00090400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-lib.rd b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-lib.rd
new file mode 100644
index 0000000..3604528
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-lib.rd
@@ -0,0 +1,12 @@
+
+Relocation section '\.rela\.plt' at offset .* contains 1 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+0009040c  .*15 R_SPARC_JMP_SLOT  00000000   sexternal \+ 0
+
+Relocation section '\.rela\.dyn' at offset .* contains 5 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+00090800  00000016 R_SPARC_RELATIVE                             00080c44
+00080c04  .*09 R_SPARC_HI22      00000000   __GOTT_BASE__ \+ 0
+00080c08  .*0c R_SPARC_LO10      00000000   __GOTT_BASE__ \+ 0
+00080c0c  .*0c R_SPARC_LO10      00000000   __GOTT_INDEX__ \+ 0
+00090410  .*14 R_SPARC_GLOB_DAT  00090c00   x \+ 0
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-lib.s b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-lib.s
new file mode 100644
index 0000000..e1221a2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-lib.s
@@ -0,0 +1,44 @@
+	.text
+	.globl	foo
+	.type	foo, %function
+foo:
+	save	%sp, -104, %sp
+	sethi	%hi(__GOTT_BASE__), %l7
+	ld	[%l7+%lo(__GOTT_BASE__)],%l7
+	ld	[%l7+%lo(__GOTT_INDEX__)],%l7
+	sethi	%hi(x), %g1
+	or	%g1, %lo(x), %g1
+	ld	[%l7+%g1], %g1
+	ld	[%g1], %g2
+	add	%g2, 1, %g2
+
+	call	slocal, 0
+	st	%g2, [%g1]
+
+	call	sexternal, 0
+	nop
+
+	call	sexternal, 0
+	nop
+
+	ret
+	restore
+	.size	foo, .-foo
+
+	.type	slocal, %function
+slocal:
+	retl
+	nop
+	.size	slocal, .-slocal
+
+	.globl	sglobal
+	.type	sglobal, %function
+sglobal:
+	retl
+	nop
+	.size	sglobal, .-sglobal
+
+	.data
+	.4byte	slocal
+
+	.comm	x,4,4
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-lib.td b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-lib.td
new file mode 100644
index 0000000..9f223e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-lib.td
@@ -0,0 +1,3 @@
+#...
+ 0x0+16 \(TEXTREL\) +0x0
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-static.d b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-static.d
new file mode 100644
index 0000000..88c0baf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1-static.d
@@ -0,0 +1,4 @@
+#name: VxWorks executable test 1 (static)
+#source: vxworks1.s
+#ld: tmpdir/libvxworks1.so -Tvxworks1.ld
+#error: Dynamic sections created in non-dynamic link
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/vxworks1.dd b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1.dd
new file mode 100644
index 0000000..16e72fd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1.dd
@@ -0,0 +1,52 @@
+
+.*:     file format .*
+
+Disassembly of section \.plt:
+
+00080800 <_PROCEDURE_LINKAGE_TABLE_>:
+   80800:	05 00 02 41 	sethi  %hi\(0x90400\), %g2
+			80800: R_SPARC_HI22	_GLOBAL_OFFSET_TABLE_\+0x8
+   80804:	84 10 a0 08 	or  %g2, 8, %g2	! 90408 <_GLOBAL_OFFSET_TABLE_\+0x8>
+			80804: R_SPARC_LO10	_GLOBAL_OFFSET_TABLE_\+0x8
+   80808:	c4 00 80 00 	ld  \[ %g2 \], %g2
+   8080c:	81 c0 80 00 	jmp  %g2
+   80810:	01 00 00 00 	nop 
+   80814:	03 00 02 41 	sethi  %hi\(0x90400\), %g1
+			80814: R_SPARC_HI22	_GLOBAL_OFFSET_TABLE_\+0xc
+   80818:	82 10 60 0c 	or  %g1, 0xc, %g1	! 9040c <sglobal@plt>
+			80818: R_SPARC_LO10	_GLOBAL_OFFSET_TABLE_\+0xc
+   8081c:	c2 00 40 00 	ld  \[ %g1 \], %g1
+   80820:	81 c0 40 00 	jmp  %g1
+   80824:	01 00 00 00 	nop 
+   80828:	03 00 00 00 	sethi  %hi\(0\), %g1
+   8082c:	10 bf ff f5 	b  80800 <_PROCEDURE_LINKAGE_TABLE_>
+   80830:	82 10 60 00 	mov  %g1, %g1	! 0 <_PROCEDURE_LINKAGE_TABLE_-0x80800>
+   80834:	03 00 02 41 	sethi  %hi\(0x90400\), %g1
+			80834: R_SPARC_HI22	_GLOBAL_OFFSET_TABLE_\+0x10
+   80838:	82 10 60 10 	or  %g1, 0x10, %g1	! 90410 <foo@plt>
+			80838: R_SPARC_LO10	_GLOBAL_OFFSET_TABLE_\+0x10
+   8083c:	c2 00 40 00 	ld  \[ %g1 \], %g1
+   80840:	81 c0 40 00 	jmp  %g1
+   80844:	01 00 00 00 	nop 
+   80848:	03 00 00 00 	sethi  %hi\(0\), %g1
+   8084c:	10 bf ff ed 	b  80800 <_PROCEDURE_LINKAGE_TABLE_>
+   80850:	82 10 60 01 	or  %g1, 1, %g1	! 1 <_PROCEDURE_LINKAGE_TABLE_-0x807ff>
+Disassembly of section \.text:
+
+00080c00 <_start>:
+   80c00:	9d e3 bf 98 	save  %sp, -104, %sp
+   80c04:	7f ff ff 0c 	call  80834 <_PROCEDURE_LINKAGE_TABLE_\+0x34>
+			80c04: R_SPARC_WDISP30	\.plt\+0x34
+   80c08:	01 00 00 00 	nop 
+   80c0c:	40 00 00 06 	call  80c24 <sexternal>
+			80c0c: R_SPARC_WDISP30	sexternal
+   80c10:	01 00 00 00 	nop 
+   80c14:	7f ff ff 00 	call  80814 <_PROCEDURE_LINKAGE_TABLE_\+0x14>
+			80c14: R_SPARC_WDISP30	\.plt\+0x14
+   80c18:	01 00 00 00 	nop 
+   80c1c:	81 c7 e0 08 	ret 
+   80c20:	81 e8 00 00 	restore 
+
+00080c24 <sexternal>:
+   80c24:	81 c3 e0 08 	retl 
+   80c28:	01 00 00 00 	nop 
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/vxworks1.ld b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1.ld
new file mode 100644
index 0000000..ce750b0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1.ld
@@ -0,0 +1,30 @@
+SECTIONS
+{
+  . = 0x80000;
+  .interp : { *(.interp) }
+  .hash : { *(.hash) }
+  .dynsym : { *(.dynsym) }
+  .dynstr : { *(.dynstr) }
+
+  . = ALIGN (0x400);
+  .rela.dyn : { *(.rela.dyn) }
+  .rela.plt : { *(.rela.plt) }
+
+  . = ALIGN (0x400);
+  .plt : { *(.plt) }
+
+  . = ALIGN (0x400);
+  .text : { *(.text) }
+
+  . = ALIGN (0x10000);
+  .dynamic : { *(.dynamic) }
+
+  . = ALIGN (0x400);
+  .got : { *(.got.plt) *(.got) }
+
+  . = ALIGN (0x400);
+  .data : { *(.data) }
+
+  . = ALIGN (0x400);
+  .bss : { *(.bss) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/vxworks1.rd b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1.rd
new file mode 100644
index 0000000..e02146b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1.rd
@@ -0,0 +1,22 @@
+
+Relocation section '\.rela\.plt' at offset .* contains 2 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+0009040c  .*15 R_SPARC_JMP_SLOT  00080814   sglobal \+ 0
+00090410  .*15 R_SPARC_JMP_SLOT  00080834   foo \+ 0
+
+Relocation section '\.rela\.text' at offset .* contains 3 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+00080c04  .*07 R_SPARC_WDISP30   00080800   \.plt \+ 34
+00080c0c  .*07 R_SPARC_WDISP30   00080c24   sexternal \+ 0
+00080c14  .*07 R_SPARC_WDISP30   00080800   \.plt \+ 14
+
+Relocation section '\.rela\.plt\.unloaded' at offset .* contains 8 entries:
+ Offset     Info    Type            Sym\.Value  Sym\. Name \+ Addend
+00080800  .*09 R_SPARC_HI22      00090400   _GLOBAL_OFFSET_TABLE_ \+ 8
+00080804  .*0c R_SPARC_LO10      00090400   _GLOBAL_OFFSET_TABLE_ \+ 8
+00080814  .*09 R_SPARC_HI22      00090400   _GLOBAL_OFFSET_TABLE_ \+ c
+00080818  .*0c R_SPARC_LO10      00090400   _GLOBAL_OFFSET_TABLE_ \+ c
+0009040c  .*03 R_SPARC_32        00080800   _PROCEDURE_LINKAGE_TAB.* \+ 28
+00080834  .*09 R_SPARC_HI22      00090400   _GLOBAL_OFFSET_TABLE_ \+ 10
+00080838  .*0c R_SPARC_LO10      00090400   _GLOBAL_OFFSET_TABLE_ \+ 10
+00090410  .*03 R_SPARC_32        00080800   _PROCEDURE_LINKAGE_TAB.* \+ 48
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/vxworks1.s b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1.s
new file mode 100644
index 0000000..82106c8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/vxworks1.s
@@ -0,0 +1,25 @@
+	.text
+	.globl	_start
+	.type	_start, %function
+_start:
+	save	%sp, -104, %sp
+
+	call	foo, 0
+	nop
+
+	call	sexternal, 0
+	nop
+
+	call	sglobal, 0
+	nop
+
+	ret
+	restore
+	.size	_start, .-_start
+
+	.globl	sexternal
+	.type	sexternal, %function
+sexternal:
+	retl
+	nop
+	.size	sexternal, .-sexternal
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/vxworks2-static.sd b/binutils-2.19/ld/testsuite/ld-sparc/vxworks2-static.sd
new file mode 100644
index 0000000..55fc529
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/vxworks2-static.sd
@@ -0,0 +1,9 @@
+#...
+Elf file type is EXEC \(Executable file\)
+Entry point 0x80000
+#...
+Program Headers:
+  Type .*
+  LOAD .* 0x00080000 0x00080000 .* R E 0x10000
+
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/vxworks2.s b/binutils-2.19/ld/testsuite/ld-sparc/vxworks2.s
new file mode 100644
index 0000000..0a883a9
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/vxworks2.s
@@ -0,0 +1,6 @@
+	.globl	_start
+	.type	_start, %function
+_start:
+	retl
+	nop
+	.end	_start
diff --git a/binutils-2.19/ld/testsuite/ld-sparc/vxworks2.sd b/binutils-2.19/ld/testsuite/ld-sparc/vxworks2.sd
new file mode 100644
index 0000000..0876568
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-sparc/vxworks2.sd
@@ -0,0 +1,13 @@
+#...
+Elf file type is EXEC \(Executable file\)
+Entry point 0x80400
+#...
+Program Headers:
+  Type .*
+  PHDR .*
+#...
+  LOAD .* 0x00080000 0x00080000 .* R E 0x10000
+  LOAD .* 0x00090000 0x00090000 .* RW  0x10000
+  DYNAMIC .*
+
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-spu/ear.d b/binutils-2.19/ld/testsuite/ld-spu/ear.d
new file mode 100644
index 0000000..df5546f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-spu/ear.d
@@ -0,0 +1,30 @@
+#as:
+#objdump: -Dr
+#name: ear
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+00 <_start>:
+   0:	32 00 00 00 	br	0
+			0: SPU_REL16	_start
+
+Disassembly of section \.data:
+
+0+00 <_EAR_main>:
+	\.\.\.
+
+0+20 <_EAR_foo>:
+	\.\.\.
+Disassembly of section \.toe:
+
+0+00 <_EAR_>:
+	\.\.\.
+
+0+10 <_EAR_bar>:
+	\.\.\.
+Disassembly of section \.data\.blah:
+
+0+00 <_EAR_blah>:
+	\.\.\.
diff --git a/binutils-2.19/ld/testsuite/ld-spu/ear.s b/binutils-2.19/ld/testsuite/ld-spu/ear.s
new file mode 100644
index 0000000..724a525
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-spu/ear.s
@@ -0,0 +1,28 @@
+ .text
+ .global _start
+_start:
+ br _start
+
+#test old-style toe _EAR_ syms
+ .section .toe,"a",@nobits
+ .p2align 4
+_EAR_:
+ .space 16
+_EAR_bar:
+ .space 16
+
+#test new-style _EAR_ syms
+ .data
+ .p2align 4
+_EAR_main:
+ .space 16
+
+#new ones don't need to be 16 bytes apart
+ .space 16
+_EAR_foo:
+ .space 16
+
+ .section .data.blah,"aw",@progbits
+ .p2align 4
+_EAR_blah:
+ .space 16
diff --git a/binutils-2.19/ld/testsuite/ld-spu/embed.rd b/binutils-2.19/ld/testsuite/ld-spu/embed.rd
new file mode 100644
index 0000000..4fcfe2a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-spu/embed.rd
@@ -0,0 +1,16 @@
+
+Relocation section '\.rela\.rodata\.speelf' at .* contains 3 entries:
+ Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend
+0+184 .* R_PPC_ADDR32 +0+0 +main \+ 0
+0+1a4 .* R_PPC_ADDR32 +0+0 +foo \+ 0
+0+1b4 .* R_PPC_ADDR32 +0+0 +blah \+ 0
+
+Relocation section '\.rela\.data\.spetoe' at .* contains 2 entries:
+ Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend
+0+004 .* R_PPC_ADDR32 +0+0 +\.rodata\.speelf \+ 0
+0+014 .* R_PPC_ADDR32 +0+0 +bar \+ 0
+
+Relocation section '\.rela\.data\.spehandle' at .* contains 2 entries:
+ Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend
+0+004 .* R_PPC_ADDR32 +0+0 +\.rodata\.speelf \+ 0
+0+008 .* R_PPC_ADDR32 +0+0 +\.data\.spetoe \+ 0
diff --git a/binutils-2.19/ld/testsuite/ld-spu/ovl.d b/binutils-2.19/ld/testsuite/ld-spu/ovl.d
new file mode 100644
index 0000000..9d34a11
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-spu/ovl.d
@@ -0,0 +1,182 @@
+#source: ovl.s
+#ld: -N -T ovl1.lnk -T ovl.lnk --emit-relocs
+#objdump: -D -r
+
+.*elf32-spu
+
+Disassembly of section \.text:
+
+00000100 <_start>:
+.*	ai	\$1,\$1,-32
+.*	xor	\$0,\$0,\$0
+.*	stqd	\$0,0\(\$1\)
+.*	stqd	\$0,16\(\$1\)
+.*	brsl	\$0,.* <00000000\.ovl_call\.f1_a1>.*
+.*SPU_REL16	f1_a1
+.*	brsl	\$0,.* <00000000\.ovl_call\.f2_a1>.*
+.*SPU_REL16	f2_a1
+.*	brsl	\$0,.* <00000000\.ovl_call\.f1_a2>.*
+.*SPU_REL16	f1_a2
+#.*	ila	\$9,328	# 148
+.*	ila	\$9,352	# 160
+.*SPU_ADDR18	f2_a2
+.*	bisl	\$0,\$9
+.*	ai	\$1,\$1,32	# 20
+.*	br	100 <_start>	# 100
+.*SPU_REL16	_start
+
+0000012c <f0>:
+.*	bi	\$0
+
+#00000130 <00000000\.ovl_call\.f1_a1>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 04 04 00.*
+#
+#00000138 <00000000\.ovl_call\.f2_a1>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 04 04 04.*
+#
+#00000140 <00000000\.ovl_call\.f1_a2>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 08 04 00.*
+#
+#00000148 <00000000\.ovl_call\.f2_a2>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 08 04 24.*
+#
+#00000150 <00000000\.ovl_call\.f4_a1>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 04 04 10.*
+#
+#00000158 <00000000.ovl_call.14:8>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 08 04 34.*
+
+00000130 <00000000\.ovl_call\.f1_a1>:
+.*	ila	\$78,1
+.*	lnop
+.*	ila	\$79,1024	# 400
+.*	br	.* <__ovly_load>.*
+
+00000140 <00000000\.ovl_call\.f2_a1>:
+.*	ila	\$78,1
+.*	lnop
+.*	ila	\$79,1028	# 404
+.*	br	.* <__ovly_load>.*
+
+00000150 <00000000.ovl_call.f1_a2>:
+.*	ila	\$78,2
+.*	lnop
+.*	ila	\$79,1024	# 400
+.*	br	.* <__ovly_load>.*
+
+00000160 <00000000\.ovl_call\.f2_a2>:
+.*	ila	\$78,2
+.*	lnop
+.*	ila	\$79,1060	# 424
+.*	br	.* <__ovly_load>.*
+
+00000170 <00000000\.ovl_call\.f4_a1>:
+.*	ila	\$78,1
+.*	lnop
+.*	ila	\$79,1040	# 410
+.*	br	.* <__ovly_load>.*
+
+00000180 <00000000.ovl_call.14:8>:
+.*	ila	\$78,2
+.*	lnop
+.*	ila	\$79,1076	# 434
+.*	br	.* <__ovly_load>.*
+
+#...
+[0-9a-f]+ <__ovly_return>:
+#...
+[0-9a-f]+ <__ovly_load>:
+#...
+[0-9a-f]+ <_ovly_debug_event>:
+#...
+Disassembly of section \.ov_a1:
+
+00000400 <f1_a1>:
+.*	br	.* <f3_a1>.*
+.*SPU_REL16	f3_a1
+
+00000404 <f2_a1>:
+#.*	ila	\$3,336	# 150
+.*	ila	\$3,368	# 170
+.*SPU_ADDR18	f4_a1
+.*	bi	\$0
+
+0000040c <f3_a1>:
+.*	bi	\$0
+
+00000410 <f4_a1>:
+.*	bi	\$0
+	\.\.\.
+Disassembly of section \.ov_a2:
+
+00000400 <f1_a2>:
+.*	stqd	\$0,16\(\$1\)
+.*	stqd	\$1,-32\(\$1\)
+.*	ai	\$1,\$1,-32
+.*	brsl	\$0,12c <f0>	# 12c
+.*SPU_REL16	f0
+.*	brsl	\$0,130 <00000000\.ovl_call\.f1_a1>	# 130
+.*SPU_REL16	f1_a1
+.*	brsl	\$0,430 <f3_a2>	# 430
+.*SPU_REL16	f3_a2
+.*	lqd	\$0,48\(\$1\)	# 30
+.*	ai	\$1,\$1,32	# 20
+.*	bi	\$0
+
+00000424 <f2_a2>:
+.*	ilhu	\$3,0
+.*SPU_ADDR16_HI	f4_a2
+#.*	iohl	\$3,344	# 158
+.*	iohl	\$3,384	# 180
+.*SPU_ADDR16_LO	f4_a2
+.*	bi	\$0
+
+00000430 <f3_a2>:
+.*	bi	\$0
+
+00000434 <f4_a2>:
+.*	br	.* <f3_a2>.*
+.*SPU_REL16	f3_a2
+	\.\.\.
+Disassembly of section .data:
+
+00000440 <_ovly_table-0x10>:
+ 440:	00 00 00 00 .*
+ 444:	00 00 00 01 .*
+	\.\.\.
+00000450 <_ovly_table>:
+ 450:	00 00 04 00 .*
+ 454:	00 00 00 20 .*
+# 458:	00 00 03 40 .*
+ 458:	00 00 03 90 .*
+ 45c:	00 00 00 01 .*
+ 460:	00 00 04 00 .*
+ 464:	00 00 00 40 .*
+# 468:	00 00 03 60 .*
+ 468:	00 00 03 b0 .*
+ 46c:	00 00 00 01 .*
+
+00000470 <_ovly_buf_table>:
+ 470:	00 00 00 00 .*
+
+Disassembly of section \.toe:
+
+00000480 <_EAR_>:
+	\.\.\.
+Disassembly of section \.note\.spu_name:
+
+.* <\.note\.spu_name>:
+.*:	00 00 00 08 .*
+.*:	00 00 00 0c .*
+.*:	00 00 00 01 .*
+.*:	53 50 55 4e .*
+.*:	41 4d 45 00 .*
+.*:	74 6d 70 64 .*
+.*:	69 72 2f 64 .*
+.*:	75 6d 70 00 .*
diff --git a/binutils-2.19/ld/testsuite/ld-spu/ovl.lnk b/binutils-2.19/ld/testsuite/ld-spu/ovl.lnk
new file mode 100644
index 0000000..0015652
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-spu/ovl.lnk
@@ -0,0 +1,7 @@
+SECTIONS
+{
+  . = SIZEOF_HEADERS;
+  .text : { *(.text) *(.stub) }
+  .data : { *(.data) *(.ovtab) }
+  .bss : { *(.bss) }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-spu/ovl.s b/binutils-2.19/ld/testsuite/ld-spu/ovl.s
new file mode 100644
index 0000000..2ca380a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-spu/ovl.s
@@ -0,0 +1,82 @@
+ .text
+ .p2align 2
+ .globl _start
+_start:
+ ai sp,sp,-32
+ xor lr,lr,lr
+ stqd lr,0(sp)
+ stqd lr,16(sp)
+ brsl lr,f1_a1
+ brsl lr,f2_a1
+ brsl lr,f1_a2
+ ila 9,f2_a2
+ bisl lr,9
+ ai sp,sp,32
+ br _start
+
+ .type f0,@function
+f0:
+ bi lr
+ .size f0,.-f0
+
+ .section .ov_a1,"ax",@progbits
+ .p2align 2
+ .global f1_a1
+ .type f1_a1,@function
+f1_a1:
+ br f3_a1
+ .size f1_a1,.-f1_a1
+
+ .global f2_a1
+ .type f2_a1,@function
+f2_a1:
+ ila 3,f4_a1
+ bi lr
+ .size f2_a1,.-f2_a1
+
+ .global f3_a1
+ .type f3_a1,@function
+f3_a1:
+ bi lr
+ .size f3_a1,.-f3_a1
+
+ .global f4_a1
+ .type f4_a1,@function
+f4_a1:
+ bi lr
+ .size f4_a1,.-f4_a1
+
+
+ .section .ov_a2,"ax",@progbits
+ .p2align 2
+ .global f1_a2
+ .type f1_a2,@function
+f1_a2:
+ stqd lr,16(sp)
+ stqd sp,-32(sp)
+ ai sp,sp,-32
+ brsl lr,f0
+ brsl lr,f1_a1
+ brsl lr,f3_a2
+ lqd lr,48(sp)
+ ai sp,sp,32
+ bi lr
+ .size f1_a2,.-f1_a2
+
+ .global f2_a2
+ .type f2_a2,@function
+f2_a2:
+ ilhu 3,f4_a2@h
+ iohl 3,f4_a2@l
+ bi lr
+ .size f2_a2,.-f2_a2
+
+ .type f3_a2,@function
+f3_a2:
+ bi lr
+ .size f3_a2,.-f3_a2
+
+ .type f4_a2,@function
+f4_a2:
+ br f3_a2
+ .size f4_a2,.-f4_a2
diff --git a/binutils-2.19/ld/testsuite/ld-spu/ovl1.lnk b/binutils-2.19/ld/testsuite/ld-spu/ovl1.lnk
new file mode 100644
index 0000000..5fd4844
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-spu/ovl1.lnk
@@ -0,0 +1,9 @@
+SECTIONS
+{
+  OVERLAY 0x400 :
+  {
+    .ov_a1 { *(.ov_a1) }
+    .ov_a2 { *(.ov_a2) }
+  }
+}
+INSERT AFTER .text;
diff --git a/binutils-2.19/ld/testsuite/ld-spu/ovl2.d b/binutils-2.19/ld/testsuite/ld-spu/ovl2.d
new file mode 100644
index 0000000..f9dca19
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-spu/ovl2.d
@@ -0,0 +1,145 @@
+#source: ovl2.s
+#ld: -N -T ovl2.lnk -T ovl.lnk --emit-relocs
+#objdump: -D -r
+
+.*elf32-spu
+
+Disassembly of section \.text:
+
+00000100 <_start>:
+.*	brsl	\$0,.* <00000000\.ovl_call\.f1_a1>.*
+.*SPU_REL16	f1_a1
+.*	brsl	\$0,.* <00000000\.ovl_call\.setjmp>.*
+.*SPU_REL16	setjmp
+.*	br	100 <_start>	# 100
+.*SPU_REL16	_start
+
+0000010c <setjmp>:
+.*	bi	\$0
+
+00000110 <longjmp>:
+.*	bi	\$0
+.*00 00 01 40.*
+.*SPU_ADDR32	\.ov_a1\+0x14
+	\.\.\.
+
+#00000118 <00000000\.ovl_call.f1_a1>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 04 04 00.*
+#
+#00000120 <00000000\.ovl_call.setjmp>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 00 01 0c.*
+#
+#00000128 <_SPUEAR_f1_a2>:
+#.*	brsl	\$75,.* <__ovly_load>.*
+#.*00 08 04 00.*
+
+00000120 <00000000\.ovl_call.f1_a1>:
+.*	ila	\$78,1
+.*	lnop
+.*	ila	\$79,1040	# 410
+.*	br	.* <__ovly_load>.*
+
+00000130 <00000000\.ovl_call.setjmp>:
+.*	ila	\$78,0
+.*	lnop
+.*	ila	\$79,268	# 10c
+.*	br	.* <__ovly_load>.*
+
+00000140 <00000000\.ovl_call\.13:5>:
+.* 	ila	\$78,1
+.* 	lnop
+.* 	ila	\$79,1044	# 414
+.* 	br	.* <__ovly_load>.*
+
+00000150 <_SPUEAR_f1_a2>:
+.*	ila	\$78,2
+.*	lnop
+.*	ila	\$79,1040	# 410
+.*	br	.* <__ovly_load>.*
+
+#...
+Disassembly of section \.ov_a1:
+
+00000400 <00000001\.ovl_call\.14:6>:
+.* 	ila	\$78,2
+.* 	lnop
+.* 	ila	\$79,1044	# 414
+.* 	br	.* <__ovly_load>.*
+
+00000410 <f1_a1>:
+.*	bi	\$0
+.*00 00 04 14.*
+.*SPU_ADDR32	\.ov_a1\+0x14
+.*00 00 04 20.*
+.*SPU_ADDR32	\.ov_a1\+0x20
+.*00 00 04 00.*
+.*SPU_ADDR32	\.ov_a2\+0x14
+
+Disassembly of section \.ov_a2:
+
+00000400 <00000002\.ovl_call\.13:5>:
+.*	ila	\$78,1
+.*	lnop
+.*	ila	\$79,1056	# 420
+.*	br	.* <__ovly_load>.*
+
+00000410 <f1_a2>:
+.*	br	.* <longjmp>.*
+.*SPU_REL16	longjmp
+.*00 00 04 00.*
+.*SPU_ADDR32	\.ov_a1\+0x20
+.*00 00 04 1c.*
+.*SPU_ADDR32	\.ov_a2\+0x1c
+.*00 00 00 00.*
+
+Disassembly of section \.data:
+
+00000420 <_ovly_table-0x10>:
+.*00 00 00 00 .*
+.*00 00 00 01 .*
+	\.\.\.
+00000430 <_ovly_table>:
+.*00 00 04 00 .*
+.*00 00 00 20 .*
+#.*00 00 03 10 .*
+.*00 00 03 60 .*
+.*00 00 00 01 .*
+.*00 00 04 00 .*
+.*00 00 00 20 .*
+#.*00 00 03 20 .*
+.*00 00 03 80 .*
+.*00 00 00 01 .*
+
+00000450 <_ovly_buf_table>:
+.*00 00 00 00 .*
+
+Disassembly of section \.toe:
+
+00000460 <_EAR_>:
+	\.\.\.
+
+Disassembly of section .nonalloc:
+
+00000000 <.nonalloc>:
+.*00 00 04 14.*
+.*SPU_ADDR32	\.ov_a1\+0x14
+.*00 00 04 20.*
+.*SPU_ADDR32	\.ov_a1\+0x20
+.*00 00 04 14.*
+.*SPU_ADDR32	\.ov_a2\+0x14
+.*00 00 04 1c.*
+.*SPU_ADDR32	\.ov_a2\+0x1c
+
+Disassembly of section \.note\.spu_name:
+
+.* <\.note\.spu_name>:
+.*:	00 00 00 08 .*
+.*:	00 00 00 0c .*
+.*:	00 00 00 01 .*
+.*:	53 50 55 4e .*
+.*:	41 4d 45 00 .*
+.*:	74 6d 70 64 .*
+.*:	69 72 2f 64 .*
+.*:	75 6d 70 00 .*
diff --git a/binutils-2.19/ld/testsuite/ld-spu/ovl2.lnk b/binutils-2.19/ld/testsuite/ld-spu/ovl2.lnk
new file mode 100644
index 0000000..9916ab2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-spu/ovl2.lnk
@@ -0,0 +1,10 @@
+SECTIONS
+{
+  OVERLAY 0x400 :
+  {
+    .ov_a1 { *(.ov_a1) }
+    .ov_a2 { *(.ov_a2) }
+    .empty { empty.o?(.text) }
+  }
+}
+INSERT BEFORE .data;
diff --git a/binutils-2.19/ld/testsuite/ld-spu/ovl2.s b/binutils-2.19/ld/testsuite/ld-spu/ovl2.s
new file mode 100644
index 0000000..9147a78
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-spu/ovl2.s
@@ -0,0 +1,52 @@
+ .text
+ .p2align 2
+ .global _start
+_start:
+ brsl lr,f1_a1
+ brsl lr,setjmp
+ br _start
+
+ .type setjmp,@function
+ .global setjmp
+setjmp:
+ bi lr
+ .size setjmp,.-setjmp
+
+ .type longjmp,@function
+longjmp:
+ bi lr
+ .size longjmp,.-longjmp
+
+ .word .L1
+
+ .section .ov_a1,"ax",@progbits
+ .p2align 2
+ .global f1_a1
+ .type f1_a1,@function
+f1_a1:
+ bi lr
+ .size f1_a1,.-f1_a1
+
+.L1:
+ .word .L1, .L2, .L3
+.L2:
+
+ .section .ov_a2,"ax",@progbits
+ .p2align 2
+ .type f1_a2,@function
+f1_a2:
+ br longjmp
+ .size f1_a2,.-f1_a2
+
+.L3:
+ .word .L2, .L4
+.L4:
+
+ .section .nonalloc,"",@progbits
+ .word .L1,.L2,.L3,.L4
+
+_SPUEAR_f1_a2 = f1_a2
+ .global _SPUEAR_f1_a2
+
+_SPUEAR_version=3
+ .global _SPUEAR_version
diff --git a/binutils-2.19/ld/testsuite/ld-spu/spu.exp b/binutils-2.19/ld/testsuite/ld-spu/spu.exp
new file mode 100644
index 0000000..39d1c96
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-spu/spu.exp
@@ -0,0 +1,94 @@
+# Expect script for ld-spu tests
+#   Copyright (C) 2006, 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+if { ![istarget "spu-*-*"] } {
+    return
+}
+
+proc embed_test { } {
+    global subdir srcdir
+    global AS ASFLAGS LD LDFLAGS READELF READELFFLAGS
+
+    set cmd "$AS $ASFLAGS -o tmpdir/ear.o $srcdir/$subdir/ear.s"
+    send_log "$cmd\n"
+    set cmdret [catch "exec $cmd" comp_output]
+    set comp_output [prune_warnings $comp_output]
+    if { $cmdret != 0 || $comp_output != ""} then {
+	send_log "$comp_output\n"
+	verbose "$comp_output" 3
+	fail "ear assembly"
+	return
+    }
+
+    set cmd "$LD $LDFLAGS -o tmpdir/ear tmpdir/ear.o"
+    send_log "$cmd\n"
+    set cmdret [catch "exec $cmd" comp_output]
+    set comp_output [prune_warnings $comp_output]
+    if { $cmdret != 0 || $comp_output != ""} then {
+	send_log "$comp_output\n"
+	verbose "$comp_output" 3
+	fail "ear link"
+	return
+    }
+
+    set cmd "sh $srcdir/../../binutils/embedspu.sh -m32 ear tmpdir/ear tmpdir/embed.o"
+    send_log "$cmd\n"
+    set cmdret [catch "exec $cmd" comp_output]
+    set comp_output [prune_warnings $comp_output]
+    if { $cmdret != 0 || $comp_output != ""} then {
+	send_log "$comp_output\n"
+	verbose "$comp_output" 3
+	if { [regexp "unknown pseudo-op: `.reloc'" $comp_output] } {
+	    untested "ear embedspu"
+	    return
+	}
+	fail "ear embedspu"
+	return
+    }
+
+    set cmd "$READELF $READELFFLAGS -r --wide tmpdir/embed.o > tmpdir/embed.out"
+    send_log "$cmd\n"
+    set cmdret [catch "exec $cmd" comp_output]
+    set comp_output [prune_warnings $comp_output]
+    if { $cmdret != 0 || $comp_output != ""} then {
+	send_log "$comp_output\n"
+	verbose "$comp_output" 3
+	fail "ear embed readelf"
+	return
+    }
+
+    if { [regexp_diff "tmpdir/embed.out" $srcdir/$subdir/embed.rd] } then {
+	fail "ear embed output"
+	return
+    }
+
+    pass "ear embed"
+}
+
+set rd_test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach sputest $rd_test_list {
+    verbose [file rootname $sputest]
+    run_dump_test [file rootname $sputest]
+}
+
+if { [isbuild "powerpc*-*-linux*"] } {
+    embed_test
+}
diff --git a/binutils-2.19/ld/testsuite/ld-srec/sr1.c b/binutils-2.19/ld/testsuite/ld-srec/sr1.c
new file mode 100644
index 0000000..d7de977
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-srec/sr1.c
@@ -0,0 +1,25 @@
+/* This file is compiled and linked into the S-record format.  */
+
+extern int e1;
+extern int e2;
+int i;
+int j = 1;
+static int k;
+static int l = 1;
+static char ab[] = "This is a string constant";
+
+extern int fn1 ();
+extern int fn2 ();
+
+int
+main ()
+{
+  fn1 (ab);
+  fn2 ("static string constant");
+  return e1 + e2 + i + j + k + l;
+}
+
+void
+__main ()
+{
+}
diff --git a/binutils-2.19/ld/testsuite/ld-srec/sr2.c b/binutils-2.19/ld/testsuite/ld-srec/sr2.c
new file mode 100644
index 0000000..5736cfa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-srec/sr2.c
@@ -0,0 +1,18 @@
+/* This file is compiled and linked into the S-record format.  */
+
+int e1;
+int e2 = 1;
+
+int
+fn1 (s)
+     char *s;
+{
+  return s[e1];
+}
+
+int
+fn2 (s)
+     char *s;
+{
+  return s[e2];
+}
diff --git a/binutils-2.19/ld/testsuite/ld-srec/sr3.cc b/binutils-2.19/ld/testsuite/ld-srec/sr3.cc
new file mode 100644
index 0000000..0b5fa7e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-srec/sr3.cc
@@ -0,0 +1,127 @@
+// This file is compiled and linked into the S-record format.
+
+#define FOO_MSG_LEN 80
+
+class Foo {
+    static int foos;
+    int i;
+    static const int len = FOO_MSG_LEN;
+    char message[len];
+public:
+    static void init_foo ();
+    static int nb_foos() { return foos; }
+    Foo();
+    Foo(const char* message);
+    Foo(const Foo&);
+    Foo & operator= (const Foo&);
+    ~Foo ();
+};
+
+static Foo static_foo( "static_foo");
+
+int
+main ()
+{
+  Foo automatic_foo( "automatic_foo");
+  return 0;
+}
+
+void
+terminate(void)
+{
+  /* This recursive call prevents a compiler warning that the noreturn
+     function terminate actually does return.  */
+  terminate ();
+}
+
+extern "C" {
+void
+__main ()
+{
+}
+
+void
+__builtin_delete ()
+{
+}
+
+void
+__builtin_new ()
+{
+}
+
+void
+__throw ()
+{
+}
+
+void
+__rethrow ()
+{
+}
+
+void
+__terminate ()
+{
+}
+
+void *__eh_pc;
+
+void ***
+__get_dynamic_handler_chain ()
+{
+  return 0;
+}
+
+void *
+__get_eh_context ()
+{
+  return 0;
+}
+
+}
+
+int Foo::foos = 0;
+
+void Foo::init_foo ()
+{
+  foos = 80;
+}
+
+Foo::Foo ()
+{
+  i = ++foos;
+}
+
+Foo::Foo (const char*)
+{
+  i = ++foos;
+}
+
+Foo::Foo (const Foo& foo)
+{
+  i = ++foos;
+  for (int k = 0; k < FOO_MSG_LEN; k++)
+    message[k] = foo.message[k];
+}
+
+Foo& Foo::operator= (const Foo& foo)
+{
+  for (int k = 0; k < FOO_MSG_LEN; k++)
+    message[k] = foo.message[k];
+  return *this;
+}
+
+Foo::~Foo ()
+{
+  foos--;
+}
+
+void *__dso_handle;
+
+extern "C"
+int
+__cxa_atexit (void)
+{
+  return 0;
+}
diff --git a/binutils-2.19/ld/testsuite/ld-srec/srec.exp b/binutils-2.19/ld/testsuite/ld-srec/srec.exp
new file mode 100644
index 0000000..652ee6f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-srec/srec.exp
@@ -0,0 +1,428 @@
+# Test linking directly to S-records.
+# By Ian Lance Taylor, Cygnus Support.
+#   Copyright 1999, 2000, 2001, 2002, 2003, 2006, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# Get the offset from an S-record line to the start of the data.
+
+proc srec_off { l } {
+    if [string match "S1*" $l] {
+	return 8
+    } else { if [string match "S2*" $l] {
+	return 10
+    } else { if [string match "S3*" $l] {
+	return 12
+    } else {
+	return -1
+    } } }
+}
+
+# See if an S-record line contains only zero data.
+
+proc srec_zero { l } {
+    if [string match "S\[0789\]*" $l] {
+	return 1
+    }
+
+    # Strip the address and checksum.
+    if [string match "S\[123\]*" $l] {
+	set l [string range $l [srec_off $l] [expr [string length $l] - 3]]
+    } else {
+	return 0
+    }
+
+    # The rest must be zero.
+    return [string match "" [string trim $l "0"]]
+}
+
+# Get the address of an S-record line.
+
+proc srec_addr { l } {
+    if [string match "S\[123\]*" $l] {
+	set addr [string range $l 4 [expr [srec_off $l] - 1]]
+    } else {
+	return -1
+    }
+
+    return "0x$addr"
+}
+
+# Get the number of data bytes in an S-record line.
+
+proc srec_len { l } {
+    if ![string match "S\[123\]*" $l] {
+	return 0
+    }
+
+    return [expr "0x[string range $l 2 3]" - ([srec_off $l] - 4) / 2 - 1]
+}
+
+# Extract bytes from an S-record line.
+
+proc srec_extract { l start len } {
+    set off [srec_off $l]
+    set rlen [srec_len $l]
+    set stop [expr $start + $len]
+    if { $stop > $rlen } {
+	set stop [expr $rlen]
+    }
+    set start [expr $start * 2 + $off]
+    set stop [expr $stop * 2 + $off - 1]
+    return [string range $l $start $stop]
+}
+
+# See if a range of bytes in an S-record line is all zeroes.
+
+proc srec_zero_range { l start len } {
+    return [string match "" [string trim [srec_extract $l $start $len] "0"]]
+}
+
+# Trim an S-record line such that the specified number of bytes remain
+# at the end.
+
+proc srec_trim { l leave } {
+    set off [srec_off $l]
+    set addr [srec_addr $l]
+    set len [srec_len $l]
+
+    if { $leave >= $len } {
+	return $l
+    }
+
+    set s1 [string range $l 0 1]
+    set s2 [format "%02x" [expr ($off - 4) / 2 + $leave + 1]]
+    set s3 [format "%0[expr $off - 4]x" [expr $addr + $len - $leave]]
+    set s4 [string range $l [expr [string length $l] - ($leave * 2) - 2] end]
+    set s "${s1}${s2}${s3}${s4}"
+
+    verbose "srec_trim { '$l' $leave } returning '$s'" 2
+
+    return $s
+}
+
+# Report failure when comparing S-record lines
+
+proc srec_compare_fail { which l1 l2 } {
+    send_log "comparison failure $which:\n$l1\n$l2\n"
+    verbose "comparison failure $which:\n$l1\n$l2"
+}
+
+# Compare S-record files.  We don't want to fuss about things like
+# extra zeroes.  Note that BFD always sorts S-records by address.
+
+proc srec_compare { f1 f2 } {
+    set e1 [gets $f1 l1]
+    set e2 [gets $f2 l2]
+
+    while { $e1 != -1 } {
+	set l1 [string trimright $l1 "\r\n"]
+	set l2 [string trimright $l2 "\r\n"]
+	if { $e2 == -1 } {
+	    # If l1 contains data, it must be zero.
+	    if ![srec_zero $l1] {
+		send_log "data after EOF: $l1\n"
+		verbose "data after EOF: $l1"
+		return 0
+	    }
+	} else { if { [string compare $l1 $l2] == 0 } {
+	    set e1 [gets $f1 l1]
+	    set e2 [gets $f2 l2]
+	} else { if { [srec_zero $l1] } {
+	    set e1 [gets $f1 l1]
+	} else { if { [srec_zero $l2] } {
+	    set e2 [gets $f2 l2]
+	} else {
+	    # The strings are not the same, and neither is all zeroes.
+	    set a1 [srec_addr $l1]
+	    set n1 [srec_len $l1]
+	    set a2 [srec_addr $l2]
+	    set n2 [srec_len $l2]
+
+	    if { $a1 < $a2 && ![srec_zero_range $l1 0 [expr $a2 - $a1]] } {
+		verbose "$a1 $a2 [srec_extract $l1 0 [expr $a2 - $a1]]" 2
+		srec_compare_fail 1 $l1 $l2
+		return 0
+	    }
+	    if { $a2 < $a1 && ![srec_zero_range $l2 0 [expr $a1 - $a2]] } {
+		srec_compare_fail 2 $l1 $l2
+		return 0
+	    }
+
+	    # Here we know that any initial data in both lines is
+	    # zero.  Now make sure that any overlapping data matches.
+	    if { $a1 < $a2 } {
+		set os1 [expr $a2 - $a1]
+		set os2 0
+	    } else {
+		set os1 0
+		set os2 [expr $a1 - $a2]
+	    }
+	    if { $a1 + $n1 < $a2 + $n2 } {
+		set ol [expr $n1 - $os1]
+	    } else {
+		set ol [expr $n2 - $os2]
+	    }
+
+	    set x1 [srec_extract $l1 $os1 $ol]
+	    set x2 [srec_extract $l2 $os2 $ol]
+	    if { [string compare $x1 $x2] != 0 } {
+		verbose "$os1 $ol $x1" 2
+		verbose "$os2 $ol $x2" 2
+		srec_compare_fail 3 $l1 $l2
+		return 0
+	    }
+
+	    # These strings match.  Trim the data from the larger
+	    # string, read a new copy of the smaller string, and
+	    # continue.
+	    if { $a1 + $n1 < $a2 + $n2 } {
+		set l2 [srec_trim $l2 [expr ($a2 + $n2) - ($a1 + $n1)]]
+		set e1 [gets $f1 l1]
+	    } else { if { $a1 + $n1 > $a2 + $n2 } {
+		set l1 [srec_trim $l1 [expr ($a1 + $n1) - ($a2 + $n2)]]
+		set e2 [gets $f2 l2]
+	    } else {
+		set e1 [gets $f1 l1]
+		set e2 [gets $f2 l2]
+	    } }
+	} } } }
+    }
+
+    # We've reached the end of the first file.  The remainder of the
+    # second file must contain only zeroes.
+    while { $e2 != -1 } {
+	set l2 [string trimright $l2 "\r\n"]
+	if ![srec_zero $l2] {
+	    send_log "data after EOF: $l2\n"
+	    verbose "data after EOF: $l2"
+	    return 0
+	}
+	set e2 [gets $f2 l2]
+    }
+
+    return 1
+}
+
+# Link twice, objcopy, and compare
+
+proc run_srec_test { test objs } {
+    global ld
+    global objcopy
+    global sizeof_headers
+    global host_triplet
+
+    # Tell the ELF linker to not do anything clever with .eh_frame,
+    # not to put anything in small data, and define a symbol referenced
+    # by gcc -fstack-protector code.
+    set flags "--traditional-format -G 0 --defsym __stack_chk_fail=0"
+
+    # If the linker script uses SIZEOF_HEADERS, use a -Ttext argument
+    # to force both the normal link and the S-record link to be put in
+    # the same place.  We don't always use -Ttext because it interacts
+    # poorly with a.out.
+
+    if { $sizeof_headers } {
+	set flags "$flags -Ttext 0x1000"
+    }
+
+    if [istarget sh64*-*-elf] {
+        # This is what gcc passes to ld by default.
+        set flags "-mshelf32"
+        # SH64 targets cannot convert format in the linker 
+        # using the -oformat command line switch.
+	setup_xfail "sh64*-*-*"
+    }
+
+    if {[istarget arm*-*-*]       || \
+        [istarget strongarm*-*-*] || \
+        [istarget xscale*-*-*]    || \
+        [istarget thumb-*-*] } {
+    
+        # ARM targets call __gccmain
+        set flags "$flags --defsym __gccmain=0"
+
+        # ARM targets cannot convert format in the linker 
+        # using the --oformat command line switch
+	setup_xfail "*arm*-*-*"
+	setup_xfail "xscale-*-*"
+	setup_xfail "thumb-*-*"
+    }
+
+    # PowerPC EABI code calls __eabi.
+    if [istarget powerpc*-*-eabi*] {
+	set flags "$flags --defsym __eabi=0"
+    }
+
+    # mn10200 code calls __truncsipsi2_d0_d2.
+    if {[istarget mn10200*-*-*]} then {
+	set flags "$flags --defsym __truncsipsi2_d0_d2=0"
+    }
+
+    # m6811/m6812 code has references to soft registers.
+    if {[istarget m6811-*-*] || [istarget m6812-*-*]} {
+	set flags "$flags --defsym _.frame=0 --defsym _.d1=0 --defsym _.d2=0"
+	set flags "$flags --defsym _.d3=0 --defsym _.d4=0"
+	set flags "$flags --defsym _.tmp=0 --defsym _.xy=0 --defsym _.z=0"
+    }
+
+    # V850 targets need libgcc.a
+    if [istarget v850*-*-elf] {
+	set objs "$objs -L ../gcc -lgcc"
+    }
+
+    # Xtensa ELF targets relax by default; S-Record linker does not
+    if [istarget xtensa*-*-*] {
+	set flags "$flags -no-relax"
+    }
+
+    # Some OpenBSD targets have ProPolice and reference __guard and
+    # __stack_smash_handler.
+    if [istarget *-*-openbsd*] {
+	set flags "$flags --defsym __guard=0"
+	set flags "$flags --defsym __stack_smash_handler=0"
+    }
+
+    if { ![ld_simple_link $ld tmpdir/sr1 "$flags $objs"] \
+	 || ![ld_simple_link $ld tmpdir/sr2.sr "$flags --oformat srec $objs"] } {
+	fail $test
+	return
+    }
+
+    send_log "$objcopy -O srec tmpdir/sr1 tmpdir/sr1.sr\n"
+    set exec_output [run_host_cmd "$objcopy" "-O srec tmpdir/sr1 tmpdir/sr1.sr"]
+    set exec_output [prune_warnings $exec_output]
+    if ![string match "" $exec_output] {
+	send_log "$exec_output\n"
+	verbose "$exec_output"
+	unresolved $test
+	return
+    }
+
+    set f1 [open tmpdir/sr1.sr r]
+    set f2 [open tmpdir/sr2.sr r]
+    if [srec_compare $f1 $f2] {
+	pass $test
+    } else {
+	fail $test
+    }
+    close $f1
+    close $f2
+}
+
+set test1 "S-records"
+set test2 "S-records with constructors"
+
+# See whether the default linker script uses SIZEOF_HEADERS.
+set exec_output [run_host_cmd "$ld" "--verbose"]
+set sizeof_headers [string match "*SIZEOF_HEADERS*" $exec_output]
+
+# First test linking a C program.  We don't require any libraries.  We
+# link it normally, and objcopy to the S-record format, and then link
+# directly to the S-record format, and require that the two files
+# contain the same data.
+
+if { ![is_remote host] && [which $CC] == 0 } {
+    untested $test1
+    untested $test2
+    return
+}
+
+if { ![ld_compile $CC $srcdir/$subdir/sr1.c tmpdir/sr1.o] \
+     || ![ld_compile $CC $srcdir/$subdir/sr2.c tmpdir/sr2.o] } {
+    unresolved $test1
+    unresolved $test2
+    return
+}
+
+# The i386-aout target is confused: the linker does not put the
+# sections where objdump finds them.  I don't know which is wrong.
+setup_xfail "i*86-*-aout*"
+
+# These tests fail on the native MIPS ELF targets because the GP value
+# in the .reginfo section is not updated when the S-record version is
+# written out.  The mips-elf target itself does not use a .reginfo section.
+setup_xfail "mips*-*-irix5*" "mips*-*-irix6*" "mips*-*-linux*"
+
+# The S-record linker doesn't do the magic TOC handling that XCOFF
+# linkers do.
+setup_xfail "*-*-aix*" "*-*-xcoff*"
+
+# The S-record linker doesn't build ARM/Thumb stubs.
+setup_xfail "arm-*-coff"
+setup_xfail "strongarm*-*-coff"
+setup_xfail "xscale*-*-coff"
+setup_xfail "arm-*-pe*"
+# setup_xfail "arm-*elf*"
+setup_xfail "thumb-*-coff*"
+setup_xfail "thumb-*-pe*"
+setup_xfail "thumb-*-elf*"
+setup_xfail "arm*-*-linux*"
+
+# The S-record linker doesn't include the .{zda} sections.
+setup_xfail "v850*-*-elf"
+
+# The S-record linker doesn't handle Alpha Elf relaxation.
+setup_xfail "alpha*-*-elf*" "alpha*-*-linux-*" "alpha*-*-gnu*"
+setup_xfail "alpha*-*-netbsd*"
+
+# The S-record linker hasn't any hope of coping with HPPA relocs.
+setup_xfail "hppa*-*-*"
+
+# The S-record linker doesn't handle IA64 Elf relaxation.
+setup_xfail "ia64-*-*"
+
+# The S-record linker doesn't support the special PE headers - the PE
+# emulation tries to write pe-specific information to the PE headers
+# in the output bfd, but it's not a PE bfd (it's an srec bfd)
+setup_xfail "*-*-cygwin*" "*-*-mingw*" "*-*-pe*" "*-*-winnt*"
+setup_xfail "score-*-*"
+
+run_srec_test $test1 "tmpdir/sr1.o tmpdir/sr2.o"
+
+# Now try linking a C++ program with global constructors and
+# destructors.  Note that since we are not linking against any
+# libraries, this program won't actually work or anything.
+
+if { ![is_remote host] && [which $CXX] == 0 } {
+    untested $test2
+    return
+}
+
+if ![ld_compile "$CXX $CXXFLAGS -fno-exceptions" $srcdir/$subdir/sr3.cc tmpdir/sr3.o] {
+    unresolved $test2
+    return
+}
+
+# See above.
+setup_xfail "i*86-*-aout*"
+setup_xfail "mips*-*-irix5*" "mips*-*-irix6*" "mips*-*-linux*"
+setup_xfail "*-*-aix*" "*-*-xcoff*"
+setup_xfail "arm*-*-*"
+setup_xfail "strongarm*-*-*"
+setup_xfail "thumb-*-*"
+setup_xfail "v850*-*-elf"
+setup_xfail "alpha*-*-elf*" "alpha*-*-linux-*" "alpha*-*-gnu*"
+setup_xfail "alpha*-*-netbsd*"
+setup_xfail "hppa*-*-*"
+setup_xfail "ia64-*-*"
+setup_xfail "*-*-cygwin*" "*-*-mingw*" "*-*-pe*" "*-*-winnt*"
+setup_xfail "score-*-*"
+
+run_srec_test $test2 "tmpdir/sr3.o"
diff --git a/binutils-2.19/ld/testsuite/ld-undefined/undefined.c b/binutils-2.19/ld/testsuite/ld-undefined/undefined.c
new file mode 100644
index 0000000..ef2aec6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-undefined/undefined.c
@@ -0,0 +1,10 @@
+/* This file is used to test the linker's reporting of undefined
+   symbols.  */
+
+extern int this_function_is_not_defined ();
+
+int
+function ()
+{
+  return this_function_is_not_defined ();
+}
diff --git a/binutils-2.19/ld/testsuite/ld-undefined/undefined.exp b/binutils-2.19/ld/testsuite/ld-undefined/undefined.exp
new file mode 100644
index 0000000..dc9c47c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-undefined/undefined.exp
@@ -0,0 +1,144 @@
+# Test that the linker reports undefined symbol errors correctly.
+# By Ian Lance Taylor, Cygnus Support
+#
+#   Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
+#   2007  Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+set testund "undefined"
+set testfn "undefined function"
+set testline "undefined line"
+
+if { ![is_remote host] && [which $CC] == 0 } {
+    verbose "Could not find C compiler!" 1
+    untested $testund
+    untested $testfn
+    untested $testline
+    return
+}
+
+if ![ld_compile "$CC -g" $srcdir/$subdir/undefined.c tmpdir/undefined.o] {
+    verbose "Unable to compile test file!" 1
+    unresolved $testund
+    unresolved $testfn
+    unresolved $testline
+    return
+}
+
+remote_file host delete "tmpdir/undefined"
+
+set flags [big_or_little_endian]
+
+# Using -e start prevents the SunOS linker from trying to build a
+# shared library.
+send_log "$ld -e start $flags -o tmpdir/undefined tmpdir/undefined.o\n"
+set exec_output [run_host_cmd "$ld" "-e start $flags -o tmpdir/undefined tmpdir/undefined.o"]
+
+send_log "$exec_output\n"
+verbose "$exec_output"
+
+proc checkund { string testname } {
+    global exec_output
+
+    if [string match "*$string*" $exec_output] {
+	pass $testname
+    } else {
+	fail $testname
+    }
+}
+
+set mu "undefined reference to `*this_function_is_not_defined'"
+checkund $mu $testund
+
+# ARM PE defaults to using stabs debugging, which we can't handle for
+# a COFF file.
+#setup_xfail "arm*-*-pe*"
+#setup_xfail "thumb*-*-pe*"
+
+# For Xtensa on GNU Linux systems (or any other system where PIC code is
+# always used), the address of the undefined function is in a literal pool
+# outside the function, so that both the "undefined function" and "undefined
+# line" tests fail.
+setup_xfail xtensa*-*-linux*
+
+set mf "tmpdir/undefined.o* In function `function':"
+checkund $mf $testfn
+
+if ![is_elf_format] {
+    # COFF SH gets this test wrong--it reports line 10, because although
+    # the jump is at line 9, the function address, and the reloc, is
+    # stored at the end of the function.
+    setup_xfail "sh-*-*"
+
+    # ARM PE defaults to using stabs debugging, which we can't handle for
+    # a COFF file.
+    #setup_xfail "arm*-*-pe*"
+    #setup_xfail "thumb*-*-pe*"
+}
+
+set ml "undefined.c:9: undefined reference to `*this_function_is_not_defined'"
+# With targets that use elf/dwarf2, such as the arm-elf and thumb-elf
+# toolchains, the code in bfd/elf.c:_bfd_elf_find_nearest_line() is called
+# in order to locate the file name/line number where the undefined
+# reference occurs.  Unfortunately this tries to use the dwarf2 debug
+# information held in the .debug_info section.  This section contains a series
+# of comp_unit structures, each of which has a low/high address range
+# representing the span of memory locations covered by that structure.  The
+# structures also index into other structures held in the .debug_line section
+# and together they can translate memory locations back into file/function/line
+# number addresses in the source code.  Since the information about the memory
+# region covered by a comp_unit is only determined at link time, the low/high
+# addresses in the .debug_info section and the line addresses in the .debug_line
+# section are computed by generating relocs against known symbols in the object
+# code.
+#
+# When the undefined reference is detected, the relocs in the dwarf2
+# debug sections have not yet been resolved, so the low/high addresses and the
+# line number address are all set at zero.  Thus when _bfd_elf_find_nearest_line()
+# calls _bfd_dwarf2_find_nearest_line() no comp_unit can be found which
+# actually covers the address where the reference occured, and so
+# _bfd_elf_find_nearest_line() fails.
+#
+# The upshot of all of this, is that the error message reported by the
+# linker, instead of having a source file name & line number as in:
+#
+#   undefined.c:9: undefined reference to `this_function_is_not_defined'
+#
+# has an object file & section address instead:
+#
+#   undefined.0(.text+0xc): undefined reference to `this_function_is_not_defined'
+#
+# hence the xfails below.
+
+setup_xfail mcore-*-elf
+setup_xfail mep-*-*
+setup_xfail mips-sgi-irix6*
+setup_xfail "sh64-*-*"
+
+# The undefined test fails on 31 bit s/390 because the address of the 
+# function `this_function_is_not_defined' is stored in the literal pool of
+# the function. Therefore the line number in the error message is 8 instead
+# of 9. On 64 bit s/390 this works because of the new brasl instruction that
+# doesn't need a literal pool entry.
+setup_xfail s390-*-*
+
+# See comments above for Xtensa.
+setup_xfail xtensa*-*-linux*
+
+checkund $ml $testline
diff --git a/binutils-2.19/ld/testsuite/ld-undefined/weak-undef.exp b/binutils-2.19/ld/testsuite/ld-undefined/weak-undef.exp
new file mode 100644
index 0000000..e3f109b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-undefined/weak-undef.exp
@@ -0,0 +1,83 @@
+# Test handling of weak undefined symbols
+#   Copyright 2001, 2002, 2004, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+set testname "weak undefined symbols"
+
+# This test only works for ELF targets.  It ought to work for some
+# a.out targets, but it doesn't.
+
+if { ![istarget *-*-sysv4*] \
+     && ![istarget *-*-unixware*] \
+     && ![istarget *-*-elf*] \
+     && ![istarget *-*-eabi*] \
+     && ![istarget hppa*64*-*-hpux*] \
+     && ![istarget *-*-linux*] \
+     && ![istarget *-*-irix5*] \
+     && ![istarget *-*-irix6*] \
+     && ![is_pecoff_format] \
+     && ![istarget *-*-solaris2*] } then {
+    unsupported $testname
+    return
+}
+
+if { [istarget *-*-linux*aout*] \
+     || [istarget *-*-linux*oldld*] } {
+    unsupported $testname
+    return
+}
+
+# Weak symbols are broken for non-i386 PE targets.
+if {! [istarget i?86-*-*]} {
+    setup_xfail *-*-pe*
+}
+
+setup_xfail hppa64-*-* pj-*-*
+
+if {! [ld_assemble $as $srcdir/$subdir/weak-undef.s tmpdir/weak-undef.o]} then {
+    # It's OK if .weak doesn't work on this target.
+    unresolved $testname
+    return
+}
+
+# The linker should accept references to undefined weaks without error,
+# and resolve them to zero.
+
+set output_regexp \
+".*Contents of section .data:.*0000 00000000 11111111.*"
+
+if {! [ld_simple_link $ld tmpdir/weak-undef "$flags tmpdir/weak-undef.o -T $srcdir/$subdir/weak-undef.t"] } then {
+    fail $testname
+} else {
+    if {![is_remote host] && [which $objdump] == 0} then {
+	unresolved $testname
+	return
+    }
+
+    set exec_output [run_host_cmd "$objdump" "-s tmpdir/weak-undef"]
+    set exec_output [prune_warnings $exec_output]
+    verbose -log $exec_output
+
+    if {[regexp $output_regexp $exec_output]} then {
+	pass $testname
+    } else {
+	fail $testname
+    }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-undefined/weak-undef.s b/binutils-2.19/ld/testsuite/ld-undefined/weak-undef.s
new file mode 100644
index 0000000..dbdbaa2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-undefined/weak-undef.s
@@ -0,0 +1,4 @@
+	.data
+	.weak foo
+	.long foo
+	.long 0x11111111
diff --git a/binutils-2.19/ld/testsuite/ld-undefined/weak-undef.t b/binutils-2.19/ld/testsuite/ld-undefined/weak-undef.t
new file mode 100644
index 0000000..a95bbcf
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-undefined/weak-undef.t
@@ -0,0 +1,9 @@
+SECTIONS
+{
+  .data : {
+    tmpdir/weak-undef.o(.data)
+  }
+  /DISCARD/ : {
+    *(*)
+  }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-v850/split-lo16.d b/binutils-2.19/ld/testsuite/ld-v850/split-lo16.d
new file mode 100644
index 0000000..c5668ff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-v850/split-lo16.d
@@ -0,0 +1,26 @@
+#source: split-lo16.s -mv850e
+#ld: -Tsplit-lo16.ld
+#objdump: -d
+#...
+00010000 <.*>:
+   10000:	40 0e 34 12 	movhi	4660, r0, r1
+   10004:	01 16 78 56 	addi	22136, r1, r2
+   10008:	81 17 79 56 	ld\.bu	22136\[r1\],r2
+   1000c:	40 0e 36 12 	movhi	4662, r0, r1
+   10010:	01 16 78 d8 	addi	-10120, r1, r2
+   10014:	81 17 79 d8 	ld\.bu	-10120\[r1\],r2
+   10018:	40 0e 12 00 	movhi	18, r0, r1
+   1001c:	81 17 57 34 	ld\.bu	13398\[r1\],r2
+   10020:	01 16 56 34 	addi	13398, r1, r2
+   10024:	40 0e 14 00 	movhi	20, r0, r1
+   10028:	81 17 57 b6 	ld\.bu	-18858\[r1\],r2
+   1002c:	01 16 56 b6 	addi	-18858, r1, r2
+   10030:	40 0e 79 56 	movhi	22137, r0, r1
+   10034:	01 16 bc 9a 	addi	-25924, r1, r2
+   10038:	81 17 bd 9a 	ld\.bu	-25924\[r1\],r2
+   1003c:	40 0e 9b 78 	movhi	30875, r0, r1
+   10040:	81 17 df bc 	ld\.bu	-17186\[r1\],r2
+   10044:	01 16 de bc 	addi	-17186, r1, r2
+   10048:	40 0e 45 23 	movhi	9029, r0, r1
+   1004c:	a1 17 89 67 	ld\.bu	26505\[r1\],r2
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-v850/split-lo16.ld b/binutils-2.19/ld/testsuite/ld-v850/split-lo16.ld
new file mode 100644
index 0000000..bde9063
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-v850/split-lo16.ld
@@ -0,0 +1,11 @@
+SECTIONS
+{
+  lo16_carry = 0x56789abc;
+  lo16_nocarry = 0x12345678;
+  split_lo16_carry = 0x789abcde;
+  split_lo16_nocarry = 0x00123456;
+  odd = 0x23456789;
+  . = 0x10000;
+  .text : { *(.text); }
+  /DISCARD/ : { *(*); }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-v850/split-lo16.s b/binutils-2.19/ld/testsuite/ld-v850/split-lo16.s
new file mode 100644
index 0000000..7eaae41
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-v850/split-lo16.s
@@ -0,0 +1,20 @@
+	movhi	hi(lo16_nocarry),r0,r1
+	addi	lo(lo16_nocarry),r1,r2
+	ld.bu	lo(lo16_nocarry)[r1],r2
+	movhi	hi(lo16_nocarry + 0x18200),r0,r1
+	addi	lo(lo16_nocarry + 0x18200),r1,r2
+	ld.bu	lo(lo16_nocarry + 0x18200)[r1],r2
+	movhi	hi(split_lo16_nocarry),r0,r1
+	ld.bu	lo(split_lo16_nocarry)[r1],r2
+	addi	lo(split_lo16_nocarry),r1,r2
+	movhi	hi(split_lo16_nocarry + 0x18200),r0,r1
+	ld.bu	lo(split_lo16_nocarry + 0x18200)[r1],r2
+	addi	lo(split_lo16_nocarry + 0x18200),r1,r2
+	movhi	hi(lo16_carry),r0,r1
+	addi	lo(lo16_carry),r1,r2
+	ld.bu	lo(lo16_carry)[r1],r2
+	movhi	hi(split_lo16_carry),r0,r1
+	ld.bu	lo(split_lo16_carry)[r1],r2
+	addi	lo(split_lo16_carry),r1,r2
+	movhi	hi(odd),r0,r1
+	ld.bu	lo(odd)[r1],r2
diff --git a/binutils-2.19/ld/testsuite/ld-v850/v850.exp b/binutils-2.19/ld/testsuite/ld-v850/v850.exp
new file mode 100644
index 0000000..2a2f9ae
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-v850/v850.exp
@@ -0,0 +1,21 @@
+# Copyright 2007  Free Software Foundtaion, Inc.
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+if [istarget v850*-*-*] {
+    run_dump_test "split-lo16"
+}
diff --git a/binutils-2.19/ld/testsuite/ld-versados/t1-1.ro b/binutils-2.19/ld/testsuite/ld-versados/t1-1.ro
new file mode 100644
index 0000000..1d70d80
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-versados/t1-1.ro
diff --git a/binutils-2.19/ld/testsuite/ld-versados/t1-2.ro b/binutils-2.19/ld/testsuite/ld-versados/t1-2.ro
new file mode 100644
index 0000000..8d4dc59
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-versados/t1-2.ro
diff --git a/binutils-2.19/ld/testsuite/ld-versados/t1.ld b/binutils-2.19/ld/testsuite/ld-versados/t1.ld
new file mode 100644
index 0000000..1a5c4e3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-versados/t1.ld
@@ -0,0 +1,281 @@
+OUTPUT_FORMAT("srec")
+SECTIONS
+{
+
+
+.text 0 : { *("9") *("10") *("11") *("12") *("13") *("14") *("15")
+		*("7") *("8") *("0") *("1") *("2") *("3") *("4") }
+.bss (NOLOAD)  : {  *("5") *("6") }
+
+.PAFI    =0x00000050 ;
+.PCHIO   =0x000000D0 ;
+.PCLO    =0x00000054 ;
+.PCVBSV  =0x0000000E ;
+.PCVTSU  =0x00000012 ;
+.PCVTSV  =0x00000016 ;
+.PCVTSVL =0x0000001A ;
+.PCVTUS  =0x0000001E ;
+.PDIS    =0x00000022 ;
+.PDISL   =0x00000026 ;
+.PDVJ    =0x0000002A ;
+.PEIO    =0x000000CC ;
+.PEOF    =0x00000058 ;
+.PEOL    =0x0000005C ;
+.PEQUS   =0x0000002E ;
+.PEQUV   =0x00000032 ;
+.PEQUVL  =0x00000036 ;
+.PEQUW   =0x000000DE ;
+.PGCM    =0x00000064 ;
+.PGEQS   =0x0000003A ;
+.PGEQV   =0x0000003E ;
+.PGEQVL  =0x00000042 ;
+.PGET    =0x00000060 ;
+.PGRTS   =0x00000046 ;
+.PGRTV   =0x0000004A ;
+.PGRTVL  =0x0000004E ;
+.PIACT   =0x0000006C ;
+.PIFD    =0x00000068 ;
+.PINDS   =0x00000052 ;
+.PINDV   =0x00000056 ;
+.PINDVL  =0x0000005A ;
+.PINDW   =0x000000D6 ;
+.PLDCS   =0x0000005E ;
+.PLDCV   =0x00000062 ;
+.PLEQS   =0x00000066 ;
+.PLEQV   =0x0000006A ;
+.PLEQVL  =0x0000006E ;
+.PLESS   =0x00000072 ;
+.PLESV   =0x00000076 ;
+.PLESVL  =0x0000007A ;
+.PLODS   =0x0000007E ;
+.PLODV   =0x00000082 ;
+.PLODVL  =0x00000086 ;
+.PMODJ   =0x0000008A ;
+.PMOV    =0x000000E2 ;
+.PMPJ    =0x0000008E ;
+.PNEQS   =0x00000092 ;
+.PNEQV   =0x00000096 ;
+.PNEQVL  =0x0000009A ;
+.PNEQW   =0x000000DA ;
+.PPAGE   =0x000000D4 ;
+.PPEE    =0x00000070 ;
+.PPUT    =0x00000074 ;
+.PRDB    =0x00000078 ;
+.PRDC    =0x0000007C ;
+.PRDH    =0x00000080 ;
+.PRDI    =0x00000084 ;
+.PRDJ    =0x00000088 ;
+.PRDRS   =0x000000C8 ;
+.PRDS    =0x0000008C ;
+.PRDV    =0x00000090 ;
+.PRLN    =0x00000094 ;
+.PRRAN   =0x00000098 ;
+.PRST    =0x0000009C ;
+.PRWT    =0x000000A0 ;
+.PSCON   =0x0000009E ;
+.PSCOP   =0x000000A2 ;
+.PSDEL   =0x000000A6 ;
+.PSINS   =0x000000AA ;
+.PSLEN   =0x000000AE ;
+.PSPOS   =0x000000B2 ;
+.PSTCV   =0x000000B6 ;
+.PSTCVL  =0x000000BA ;
+.PSTOS   =0x000000BE ;
+.PSTOV   =0x000000C2 ;
+.PSTOVL  =0x000000C6 ;
+.PSTRS   =0x000000CA ;
+.PSTRV   =0x000000CE ;
+.PSTRVL  =0x000000D2 ;
+.PWLN    =0x000000A4 ;
+.PWRAN   =0x000000A8 ;
+.PWRB    =0x000000AC ;
+.PWRC    =0x000000B0 ;
+.PWRH    =0x000000B4 ;
+.PWRI    =0x000000B8 ;
+.PWRJ    =0x000000BC ;
+.PWRS    =0x000000C0 ;
+.PWRV    =0x000000C4 ;
+
+/*
+.PAFI=0x   = 0x00;
+.PCHIO   =0x 0x000000;
+.PCLO    =0x 64 ;
+.PC;
+.PCVTSU  =0x 0x000000;
+.PCVTSV  =0x 0x000000;
+.PCVTSVL =0x 0x000000;
+.PCVTUS  =0x 158 ;
+.P;
+.PDISL   =0x 0x000000;
+.PDVJ    =0x 0x000000;
+.PEIO    =0x 0x000000;
+.PEOF    =0x 0x000000;
+.PEOL    =0x 0x000000;
+.PEQUS   =0x 0x000000;
+.PEQUV   =0x 0x000000;
+.PEQUVL  =0x 0x000000;
+.PEQUW   =0x 0x000000;
+.PGCM    =0x 0x000000;
+.PGEQS   =0x 0x000000;
+.PGEQV   =0x 0x000000;
+.PGEQVL  =0x 0x000000;
+.PGET    =0x 0x000000;
+.PGRTS   =0x 0x000000;
+.PGRTV   =0x 0x000000;
+.PGRTVL  =0x 0x000000;
+.PIACT   =0x 0x000000;
+.PIFD    =0x 126 ;
+.P;
+.PINDV   =0x 0x000000;
+.PINDVL  =0x 0x000000;
+.PINDW   =0x 0x000000;
+.PLDCS   =0x 0x000000;
+.PLDCV   =0x 0x000000;
+.PLEQS   =0x 0x000000;
+.PLEQV   =0x 0x000000;
+.PLEQVL  =0x 0x000000;
+.PLESS   =0x 0x000000;
+.PLESV   =0x 0x000000;
+.PLESVL  =0x 0x000000;
+.PLODS   =0x 0x000000;
+.PLODV   =0x 0x000000;
+.PLODVL  =0x 0x000000;
+.PMODJ   =0x 0x000000;
+.PMOV    =0x 0x000000;
+.PMPJ    =0x 0x000000;
+.PNEQS   =0x 0x000000;
+.PNEQV   =0x 0x000000;
+.PNEQVL  =0x 0x000000;
+.PNEQW   =0x 0x000000;
+.PPAGE   =0x 0x000000;
+.PPEE    =0x 0x000000;
+.PPUT    =0x 0x000000;
+.PRDB    =0x 0x000000;
+.PRDC    =0x 0x000000;
+.PRDH    =0x 0x000000;
+.PRDI    =0x 0x000000;
+.PRDJ    =0x 0x000000;
+.PRDRS   =0x 0x000000;
+.PRDS    =0x 0x000000;
+.PRDV    =0x 0x000000;
+.PRLN    =0x 0x000000;
+.PRRAN   =0x 0x000000;
+.PRST    =0x 0x000000;
+.PRWT    =0x 0x000000;
+.PSCON   =0x 0x000000;
+.PSCOP   =0x 0x000000;
+.PSDEL   =0x 0x000000;
+.PSINS   =0x 0x000000;
+.PSLEN   =0x 0x000000;
+.PSPOS   =0x 0x000000;
+.PSTCV   =0x 0x000000;
+.PSTCVL  =0x 0x000000;
+.PSTOS   =0x 0x000000;
+.PSTOV   =0x 0x000000;
+.PSTOVL  =0x 0x000000;
+.PSTRS   =0x 0x000000;
+.PSTRV   =0x 0x000000;
+.PSTRVL  =0x 0x000000;
+.PWLN    =0x 0x000000;
+.PWRAN   =0x 0x000000;
+.PWRB    =0x 0x000000;
+.PWRC    =0x 0x000000;
+.PWRH    =0x 0x000000;
+.PWRI    =0x 0x000000;
+.PWRJ    =0x 0x000000;
+.PWRS    =0x 0x000000;
+.PWRV    =0x 0x000000;
+
+*/
+/*
+.P=0x      = 0;
+.PCHIO   =0x 0xfeedfa;
+.PCLO    =0x 0xfeedfa;
+.PCVBSV  =0x 0xfeedfa;
+.PCVTSU  =0x 0xfeedfa;
+.PCVTSV  =0x 0xfeedfa;
+.PCVTSVL =0x 0xfeedfa;
+.PCVTUS  =0x 0xfeedfa;
+.PDIS    =0x 0xfeedfa;
+.PDISL   =0x 0xfeedfa;
+.PDVJ    =0x 0xfeedfa;
+.PEIO    =0x 0xfeedfa;
+.PEOF    =0x 0xfeedfa;
+.PEOL    =0x 0xfeedfa;
+.PEQUS   =0x 0xfeedfa;
+.PEQUV   =0x 0xfeedfa;
+.PEQUVL  =0x 0xfeedfa;
+.PEQUW   =0x 0xfeedfa;
+.PGCM    =0x 0xfeedfa;
+.PGEQS   =0x 0xfeedfa;
+.PGEQV   =0x 0xfeedfa;
+.PGEQVL  =0x 0xfeedfa;
+.PGET    =0x 0xfeedfa;
+.PGRTS   =0x 0xfeedfa;
+.PGRTV   =0x 0xfeedfa;
+.PGRTVL  =0x 0xfeedfa;
+.PIACT   =0x 0xfeedfa;
+.PIFD    =0x 0xfeedfa;
+.PINDS   =0x 0xfeedfa;
+.PINDV   =0x 0xfeedfa;
+.PINDVL  =0x 0xfeedfa;
+.PINDW   =0x 0xfeedfa;
+.PLDCS   =0x 0xfeedfa;
+.PLDCV   =0x 0xfeedfa;
+.PLEQS   =0x 0xfeedfa;
+.PLEQV   =0x 0xfeedfa;
+.PLEQVL  =0x 0xfeedfa;
+.PLESS   =0x 0xfeedfa;
+.PLESV   =0x 0xfeedfa;
+.PLESVL  =0x 0xfeedfa;
+.PLODS   =0x 0xfeedfa;
+.PLODV   =0x 0xfeedfa;
+.PLODVL  =0x 0xfeedfa;
+.PMODJ   =0x 0xfeedfa;
+.PMOV    =0x 0xfeedfa;
+.PMPJ    =0x 0xfeedfa;
+.PNEQS   =0x 0xfeedfa;
+.PNEQV   =0x 0xfeedfa;
+.PNEQVL    = 0xfeedface;
+.PNEQW     = 0xfeedface;
+.PPAGE     = 0xfeedface;
+.PPEE      = 0xfeedface;
+.PPUT      = 0xfeedface;
+.PRDB      = 0xfeedface;
+.PRDC      = 0xfeedface;
+.PRDH      = 0xfeedface;
+.PRDI      = 0xfeedface;
+.PRDJ      = 0xfeedface;
+.PRDRS     = 0xfeedface;
+.PRDS      = 0xfeedface;
+.PRDV      = 0xfeedface;
+.PRLN      = 0xfeedface;
+.PRRAN     = 0xfeedface;
+.PRST      = 0xfeedface;
+.PRWT      = 0xfeedface;
+.PSCON     = 0xfeedface;
+.PSCOP     = 0xfeedface;
+.PSDEL     = 0xfeedface;
+.PSINS     = 0xfeedface;
+.PSLEN     = 0xfeedface;
+.PSPOS     = 0xfeedface;
+.PSTCV     = 0xfeedface;
+.PSTCVL    = 0xfeedface;
+.PSTOS     = 0xfeedface;
+.PSTOV     = 0xfeedface;
+.PSTOVL    = 0xfeedface;
+.PSTRS     = 0xfeedface;
+.PSTRV     = 0xfeedface;
+.PSTRVL    = 0xfeedface;
+.PWLN      = 0xfeedface;
+.PWRAN     = 0xfeedface;
+.PWRB      = 0xfeedface;
+.PWRC      = 0xfeedface;
+.PWRH      = 0xfeedface;
+.PWRI      = 0xfeedface;
+.PWRJ      = 0xfeedface;
+.PWRS      = 0xfeedface;
+.PWRV      = 0xfeedface;
+*/
+
+}
diff --git a/binutils-2.19/ld/testsuite/ld-versados/t1.ook b/binutils-2.19/ld/testsuite/ld-versados/t1.ook
new file mode 100644
index 0000000..3984b94
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-versados/t1.ook
@@ -0,0 +1,133 @@
+S00C000074312E6F75742E6F6BC0

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diff --git a/binutils-2.19/ld/testsuite/ld-versados/t2-1.ro b/binutils-2.19/ld/testsuite/ld-versados/t2-1.ro
new file mode 100644
index 0000000..633a7cc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-versados/t2-1.ro
diff --git a/binutils-2.19/ld/testsuite/ld-versados/t2-2.ro b/binutils-2.19/ld/testsuite/ld-versados/t2-2.ro
new file mode 100644
index 0000000..704a79d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-versados/t2-2.ro
diff --git a/binutils-2.19/ld/testsuite/ld-versados/t2-3.ro b/binutils-2.19/ld/testsuite/ld-versados/t2-3.ro
new file mode 100644
index 0000000..d959342
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-versados/t2-3.ro
diff --git a/binutils-2.19/ld/testsuite/ld-versados/t2.ld b/binutils-2.19/ld/testsuite/ld-versados/t2.ld
new file mode 100644
index 0000000..5e1e413
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-versados/t2.ld
@@ -0,0 +1,281 @@
+OUTPUT_FORMAT("srec")
+SECTIONS
+{
+
+
+.text 0 : { *("9") *("10") *("11") *("12") *("13") *("14") *("15")
+		*("7") *("8") *("0") *("1") *("2") *("3") *("4") }
+.bss   : {  *("5") *("6") }
+
+.PAFI    =0x00000050 ;
+.PCHIO   =0x000000D0 ;
+.PCLO    =0x00000054 ;
+.PCVBSV  =0x0000000E ;
+.PCVTSU  =0x00000012 ;
+.PCVTSV  =0x00000016 ;
+.PCVTSVL =0x0000001A ;
+.PCVTUS  =0x0000001E ;
+.PDIS    =0x00000022 ;
+.PDISL   =0x00000026 ;
+.PDVJ    =0x0000002A ;
+.PEIO    =0x000000CC ;
+.PEOF    =0x00000058 ;
+.PEOL    =0x0000005C ;
+.PEQUS   =0x0000002E ;
+.PEQUV   =0x00000032 ;
+.PEQUVL  =0x00000036 ;
+.PEQUW   =0x000000DE ;
+.PGCM    =0x00000064 ;
+.PGEQS   =0x0000003A ;
+.PGEQV   =0x0000003E ;
+.PGEQVL  =0x00000042 ;
+.PGET    =0x00000060 ;
+.PGRTS   =0x00000046 ;
+.PGRTV   =0x0000004A ;
+.PGRTVL  =0x0000004E ;
+.PIACT   =0x0000006C ;
+.PIFD    =0x00000068 ;
+.PINDS   =0x00000052 ;
+.PINDV   =0x00000056 ;
+.PINDVL  =0x0000005A ;
+.PINDW   =0x000000D6 ;
+.PLDCS   =0x0000005E ;
+.PLDCV   =0x00000062 ;
+.PLEQS   =0x00000066 ;
+.PLEQV   =0x0000006A ;
+.PLEQVL  =0x0000006E ;
+.PLESS   =0x00000072 ;
+.PLESV   =0x00000076 ;
+.PLESVL  =0x0000007A ;
+.PLODS   =0x0000007E ;
+.PLODV   =0x00000082 ;
+.PLODVL  =0x00000086 ;
+.PMODJ   =0x0000008A ;
+.PMOV    =0x000000E2 ;
+.PMPJ    =0x0000008E ;
+.PNEQS   =0x00000092 ;
+.PNEQV   =0x00000096 ;
+.PNEQVL  =0x0000009A ;
+.PNEQW   =0x000000DA ;
+.PPAGE   =0x000000D4 ;
+.PPEE    =0x00000070 ;
+.PPUT    =0x00000074 ;
+.PRDB    =0x00000078 ;
+.PRDC    =0x0000007C ;
+.PRDH    =0x00000080 ;
+.PRDI    =0x00000084 ;
+.PRDJ    =0x00000088 ;
+.PRDRS   =0x000000C8 ;
+.PRDS    =0x0000008C ;
+.PRDV    =0x00000090 ;
+.PRLN    =0x00000094 ;
+.PRRAN   =0x00000098 ;
+.PRST    =0x0000009C ;
+.PRWT    =0x000000A0 ;
+.PSCON   =0x0000009E ;
+.PSCOP   =0x000000A2 ;
+.PSDEL   =0x000000A6 ;
+.PSINS   =0x000000AA ;
+.PSLEN   =0x000000AE ;
+.PSPOS   =0x000000B2 ;
+.PSTCV   =0x000000B6 ;
+.PSTCVL  =0x000000BA ;
+.PSTOS   =0x000000BE ;
+.PSTOV   =0x000000C2 ;
+.PSTOVL  =0x000000C6 ;
+.PSTRS   =0x000000CA ;
+.PSTRV   =0x000000CE ;
+.PSTRVL  =0x000000D2 ;
+.PWLN    =0x000000A4 ;
+.PWRAN   =0x000000A8 ;
+.PWRB    =0x000000AC ;
+.PWRC    =0x000000B0 ;
+.PWRH    =0x000000B4 ;
+.PWRI    =0x000000B8 ;
+.PWRJ    =0x000000BC ;
+.PWRS    =0x000000C0 ;
+.PWRV    =0x000000C4 ;
+
+/*
+.PAFI=0x   = 0x00;
+.PCHIO   =0x 0x000000;
+.PCLO    =0x 64 ;
+.PC;
+.PCVTSU  =0x 0x000000;
+.PCVTSV  =0x 0x000000;
+.PCVTSVL =0x 0x000000;
+.PCVTUS  =0x 158 ;
+.P;
+.PDISL   =0x 0x000000;
+.PDVJ    =0x 0x000000;
+.PEIO    =0x 0x000000;
+.PEOF    =0x 0x000000;
+.PEOL    =0x 0x000000;
+.PEQUS   =0x 0x000000;
+.PEQUV   =0x 0x000000;
+.PEQUVL  =0x 0x000000;
+.PEQUW   =0x 0x000000;
+.PGCM    =0x 0x000000;
+.PGEQS   =0x 0x000000;
+.PGEQV   =0x 0x000000;
+.PGEQVL  =0x 0x000000;
+.PGET    =0x 0x000000;
+.PGRTS   =0x 0x000000;
+.PGRTV   =0x 0x000000;
+.PGRTVL  =0x 0x000000;
+.PIACT   =0x 0x000000;
+.PIFD    =0x 126 ;
+.P;
+.PINDV   =0x 0x000000;
+.PINDVL  =0x 0x000000;
+.PINDW   =0x 0x000000;
+.PLDCS   =0x 0x000000;
+.PLDCV   =0x 0x000000;
+.PLEQS   =0x 0x000000;
+.PLEQV   =0x 0x000000;
+.PLEQVL  =0x 0x000000;
+.PLESS   =0x 0x000000;
+.PLESV   =0x 0x000000;
+.PLESVL  =0x 0x000000;
+.PLODS   =0x 0x000000;
+.PLODV   =0x 0x000000;
+.PLODVL  =0x 0x000000;
+.PMODJ   =0x 0x000000;
+.PMOV    =0x 0x000000;
+.PMPJ    =0x 0x000000;
+.PNEQS   =0x 0x000000;
+.PNEQV   =0x 0x000000;
+.PNEQVL  =0x 0x000000;
+.PNEQW   =0x 0x000000;
+.PPAGE   =0x 0x000000;
+.PPEE    =0x 0x000000;
+.PPUT    =0x 0x000000;
+.PRDB    =0x 0x000000;
+.PRDC    =0x 0x000000;
+.PRDH    =0x 0x000000;
+.PRDI    =0x 0x000000;
+.PRDJ    =0x 0x000000;
+.PRDRS   =0x 0x000000;
+.PRDS    =0x 0x000000;
+.PRDV    =0x 0x000000;
+.PRLN    =0x 0x000000;
+.PRRAN   =0x 0x000000;
+.PRST    =0x 0x000000;
+.PRWT    =0x 0x000000;
+.PSCON   =0x 0x000000;
+.PSCOP   =0x 0x000000;
+.PSDEL   =0x 0x000000;
+.PSINS   =0x 0x000000;
+.PSLEN   =0x 0x000000;
+.PSPOS   =0x 0x000000;
+.PSTCV   =0x 0x000000;
+.PSTCVL  =0x 0x000000;
+.PSTOS   =0x 0x000000;
+.PSTOV   =0x 0x000000;
+.PSTOVL  =0x 0x000000;
+.PSTRS   =0x 0x000000;
+.PSTRV   =0x 0x000000;
+.PSTRVL  =0x 0x000000;
+.PWLN    =0x 0x000000;
+.PWRAN   =0x 0x000000;
+.PWRB    =0x 0x000000;
+.PWRC    =0x 0x000000;
+.PWRH    =0x 0x000000;
+.PWRI    =0x 0x000000;
+.PWRJ    =0x 0x000000;
+.PWRS    =0x 0x000000;
+.PWRV    =0x 0x000000;
+
+*/
+/*
+.P=0x      = 0;
+.PCHIO   =0x 0xfeedfa;
+.PCLO    =0x 0xfeedfa;
+.PCVBSV  =0x 0xfeedfa;
+.PCVTSU  =0x 0xfeedfa;
+.PCVTSV  =0x 0xfeedfa;
+.PCVTSVL =0x 0xfeedfa;
+.PCVTUS  =0x 0xfeedfa;
+.PDIS    =0x 0xfeedfa;
+.PDISL   =0x 0xfeedfa;
+.PDVJ    =0x 0xfeedfa;
+.PEIO    =0x 0xfeedfa;
+.PEOF    =0x 0xfeedfa;
+.PEOL    =0x 0xfeedfa;
+.PEQUS   =0x 0xfeedfa;
+.PEQUV   =0x 0xfeedfa;
+.PEQUVL  =0x 0xfeedfa;
+.PEQUW   =0x 0xfeedfa;
+.PGCM    =0x 0xfeedfa;
+.PGEQS   =0x 0xfeedfa;
+.PGEQV   =0x 0xfeedfa;
+.PGEQVL  =0x 0xfeedfa;
+.PGET    =0x 0xfeedfa;
+.PGRTS   =0x 0xfeedfa;
+.PGRTV   =0x 0xfeedfa;
+.PGRTVL  =0x 0xfeedfa;
+.PIACT   =0x 0xfeedfa;
+.PIFD    =0x 0xfeedfa;
+.PINDS   =0x 0xfeedfa;
+.PINDV   =0x 0xfeedfa;
+.PINDVL  =0x 0xfeedfa;
+.PINDW   =0x 0xfeedfa;
+.PLDCS   =0x 0xfeedfa;
+.PLDCV   =0x 0xfeedfa;
+.PLEQS   =0x 0xfeedfa;
+.PLEQV   =0x 0xfeedfa;
+.PLEQVL  =0x 0xfeedfa;
+.PLESS   =0x 0xfeedfa;
+.PLESV   =0x 0xfeedfa;
+.PLESVL  =0x 0xfeedfa;
+.PLODS   =0x 0xfeedfa;
+.PLODV   =0x 0xfeedfa;
+.PLODVL  =0x 0xfeedfa;
+.PMODJ   =0x 0xfeedfa;
+.PMOV    =0x 0xfeedfa;
+.PMPJ    =0x 0xfeedfa;
+.PNEQS   =0x 0xfeedfa;
+.PNEQV   =0x 0xfeedfa;
+.PNEQVL    = 0xfeedface;
+.PNEQW     = 0xfeedface;
+.PPAGE     = 0xfeedface;
+.PPEE      = 0xfeedface;
+.PPUT      = 0xfeedface;
+.PRDB      = 0xfeedface;
+.PRDC      = 0xfeedface;
+.PRDH      = 0xfeedface;
+.PRDI      = 0xfeedface;
+.PRDJ      = 0xfeedface;
+.PRDRS     = 0xfeedface;
+.PRDS      = 0xfeedface;
+.PRDV      = 0xfeedface;
+.PRLN      = 0xfeedface;
+.PRRAN     = 0xfeedface;
+.PRST      = 0xfeedface;
+.PRWT      = 0xfeedface;
+.PSCON     = 0xfeedface;
+.PSCOP     = 0xfeedface;
+.PSDEL     = 0xfeedface;
+.PSINS     = 0xfeedface;
+.PSLEN     = 0xfeedface;
+.PSPOS     = 0xfeedface;
+.PSTCV     = 0xfeedface;
+.PSTCVL    = 0xfeedface;
+.PSTOS     = 0xfeedface;
+.PSTOV     = 0xfeedface;
+.PSTOVL    = 0xfeedface;
+.PSTRS     = 0xfeedface;
+.PSTRV     = 0xfeedface;
+.PSTRVL    = 0xfeedface;
+.PWLN      = 0xfeedface;
+.PWRAN     = 0xfeedface;
+.PWRB      = 0xfeedface;
+.PWRC      = 0xfeedface;
+.PWRH      = 0xfeedface;
+.PWRI      = 0xfeedface;
+.PWRJ      = 0xfeedface;
+.PWRS      = 0xfeedface;
+.PWRV      = 0xfeedface;
+*/
+
+}
diff --git a/binutils-2.19/ld/testsuite/ld-versados/t2.ook b/binutils-2.19/ld/testsuite/ld-versados/t2.ook
new file mode 100644
index 0000000..03f24a5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-versados/t2.ook
@@ -0,0 +1,99 @@
+S0120000696E6974746573745F6570632E7372CF

+S118000000000000494E495454455354202050413035202052AB

+S118001531332E33202020202020205231332E32202020202077

+S118002A202000934B5B00B5E6C11B089DD600005400000005F9

+S118003F5A00000048005C00A60000010A0126000400010002CB

+S1180054009000000000000000000002004020200000494F5F8A

+S11800695245534552564152544C4942434F4E0040484501003B

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+S11800FC54520010A4A852544C494246494C000100B5E6C049EC

+S11801114E495454455354202000000616020008000000023210

+S11801260048000000004E56FFF0BA8F63062E4E610000BC4159

+S118013BFA00F443EEFFF032D82D7C00000001FFFC206E000858

+S118015020086604610000BA222EFFFC53814A816C046100002E

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+S11801E3EE000C22D822D822D84E5E205F588F4ED02B57FFF278

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+S1180540293A000000142020202020204361736520202020521D

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diff --git a/binutils-2.19/ld/testsuite/ld-versados/versados.exp b/binutils-2.19/ld/testsuite/ld-versados/versados.exp
new file mode 100644
index 0000000..2a263ed
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-versados/versados.exp
@@ -0,0 +1,102 @@
+# Expect script for ld-versados tests
+#   Copyright 1995, 1997, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+# Written by Steve Chamberlain (sac@cygnus.com)
+#
+
+# Make sure that ld can read versados images and
+# generate binaries which are identical to the customer's
+# old method.
+
+# This test can only be run if ld generates native executables.
+
+# This test can only be run on 68k coff targets
+# Square bracket expressions seem to confuse istarget.
+if { ![istarget m68k-*-coff*] } then {
+    return
+}
+
+set testname "LD VERSADOS"
+
+
+proc inspect { whichone } {
+    global objdump
+    global exec_output
+    global srcdir
+    global subdir
+    global testname
+
+    send_log "$objdump -s tmpdir/$whichone.out >tmpdir/$whichone.dump\n"
+    catch "exec $objdump -s tmpdir/$whichone.out | grep -v srec >tmpdir/$whichone.dump" exec_output
+
+    if ![string match "" $exec_output] {
+	send_log "$exec_output\n"
+	verbose $exec_output
+	unresolved $testname
+	return 0
+    }
+
+    send_log "$objdump -s $srcdir/$subdir/$whichone.ook >tmpdir/$whichone.dok\n"
+    catch "exec $objdump -s $srcdir/$subdir/$whichone.ook | grep -v srec >tmpdir/$whichone.dok" exec_output
+
+    if ![string match "" $exec_output] {
+	send_log "$exec_output\n"
+	verbose $exec_output
+	unresolved $testname
+	return 0
+    }
+
+    # compare it with the correct output
+    catch "exec diff tmpdir/$whichone.dump tmpdir/$whichone.dok" exec_output
+    if ![string match "" $exec_output] {
+	send_log "$exec_output\n"
+	verbose $exec_output
+	fail $testname
+	return 0
+    }
+
+    return 1
+}
+
+if ![ld_simple_link $ld tmpdir/t1.out \
+	" -T $srcdir/$subdir/t1.ld $srcdir/$subdir/t1-1.ro  $srcdir/$subdir/t1-2.ro"] {
+    fail $testname
+    return
+} else {
+    # Get a dump of what we've got, and what we should have
+    if ![inspect t1] {
+	return
+    }
+}
+
+
+if ![ld_simple_link $ld  tmpdir/t2.out \
+	" -T $srcdir/$subdir/t2.ld $srcdir/$subdir/t2-2.ro \
+	$srcdir/$subdir/t2-1.ro  $srcdir/$subdir/t2-3.ro"] {
+    fail $testname
+    return
+} else {
+    # Get a dump of what we've got, and what we should have
+    if ![inspect t2] {
+	return
+    }
+}
+
+pass $testname
diff --git a/binutils-2.19/ld/testsuite/ld-vxworks/plt-mips1.d b/binutils-2.19/ld/testsuite/ld-vxworks/plt-mips1.d
new file mode 100644
index 0000000..d580df2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-vxworks/plt-mips1.d
@@ -0,0 +1,10 @@
+# target: mips*-*-*
+# source: plt-mips1.s
+# ld: -shared -z now
+# readelf: -s
+
+#...
+    [0-9]*: 00000000     0 FUNC    GLOBAL DEFAULT  UND Foo
+#...
+    [0-9]*: 00000000     0 FUNC    GLOBAL DEFAULT  UND Foo
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-vxworks/plt-mips1.s b/binutils-2.19/ld/testsuite/ld-vxworks/plt-mips1.s
new file mode 100644
index 0000000..2f79504
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-vxworks/plt-mips1.s
@@ -0,0 +1 @@
+        lw      $25,%call16(Foo)($28)
diff --git a/binutils-2.19/ld/testsuite/ld-vxworks/rpath-1.d b/binutils-2.19/ld/testsuite/ld-vxworks/rpath-1.d
new file mode 100644
index 0000000..df67a03
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-vxworks/rpath-1.d
@@ -0,0 +1,6 @@
+# source: rpath-1.s
+# ld: --entry foo --rpath /dir1 --rpath /dir2 --rpath net:/dir4 --rpath /dir2 --rpath /dir1 --rpath /dir3 --force-dynamic -q
+# readelf: -d
+#...
+ 0x0+f \(RPATH\).*Library rpath: \[/dir1;/dir2;net:/dir4;/dir3\]
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-vxworks/rpath-1.s b/binutils-2.19/ld/testsuite/ld-vxworks/rpath-1.s
new file mode 100644
index 0000000..6218588
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-vxworks/rpath-1.s
@@ -0,0 +1,2 @@
+	.global	foo
+foo:
diff --git a/binutils-2.19/ld/testsuite/ld-vxworks/tls-1.d b/binutils-2.19/ld/testsuite/ld-vxworks/tls-1.d
new file mode 100644
index 0000000..cb5e695
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-vxworks/tls-1.d
@@ -0,0 +1,25 @@
+# source: tls-1.s
+# ld: --entry foo -q
+# nm: -r
+
+#...
+[0-9a-f]+ N __wrs_rtp_tls_vars_start
+#...
+0000000c A __wrs_rtp_tls_vars_size
+#...
+[0-9a-f]+ N __wrs_rtp_tls_data_start
+#...
+00000004 A __wrs_rtp_tls_data_size
+#...
+00000004 A __wrs_rtp_tls_data_align
+#...
+[0-9a-f]+ N ___wrs_rtp_tls_vars_start
+#...
+0000000c A ___wrs_rtp_tls_vars_size
+#...
+[0-9a-f]+ N ___wrs_rtp_tls_data_start
+#...
+00000004 A ___wrs_rtp_tls_data_size
+#...
+00000004 A ___wrs_rtp_tls_data_align
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-vxworks/tls-1.s b/binutils-2.19/ld/testsuite/ld-vxworks/tls-1.s
new file mode 100644
index 0000000..8fa97ab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-vxworks/tls-1.s
@@ -0,0 +1,19 @@
+	.globl	foo
+foo:
+
+	.section	.tls_data
+	.p2align	2
+	.type	i,%object
+	.size	i,4
+i:
+	.space	4
+	.globl	__tls__i
+	.section	.tls_vars
+	.p2align	2
+	.type	__tls__i,%object
+	.size	__tls__i,12
+__tls__i:
+	.4byte	i
+	.4byte	0
+	.4byte	4
+
diff --git a/binutils-2.19/ld/testsuite/ld-vxworks/tls-2.d b/binutils-2.19/ld/testsuite/ld-vxworks/tls-2.d
new file mode 100644
index 0000000..4278355
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-vxworks/tls-2.d
@@ -0,0 +1,11 @@
+# source: tls-2.s
+# ld: --entry foo -q --force-dynamic
+# readelf: -d
+
+#...
+ 0x60000010 \(Operating System specific: 60000010\)        0x[0-9a-f]+
+ 0x60000011 \(Operating System specific: 60000011\)        0x4
+ 0x60000015 \(Operating System specific: 60000015\)        0x4
+ 0x60000012 \(Operating System specific: 60000012\)        0x[0-9a-f]+
+ 0x60000013 \(Operating System specific: 60000013\)        0xc
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-vxworks/tls-2.s b/binutils-2.19/ld/testsuite/ld-vxworks/tls-2.s
new file mode 100644
index 0000000..8fa97ab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-vxworks/tls-2.s
@@ -0,0 +1,19 @@
+	.globl	foo
+foo:
+
+	.section	.tls_data
+	.p2align	2
+	.type	i,%object
+	.size	i,4
+i:
+	.space	4
+	.globl	__tls__i
+	.section	.tls_vars
+	.p2align	2
+	.type	__tls__i,%object
+	.size	__tls__i,12
+__tls__i:
+	.4byte	i
+	.4byte	0
+	.4byte	4
+
diff --git a/binutils-2.19/ld/testsuite/ld-vxworks/tls-3.d b/binutils-2.19/ld/testsuite/ld-vxworks/tls-3.d
new file mode 100644
index 0000000..53f7e81
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-vxworks/tls-3.d
@@ -0,0 +1,7 @@
+# source: tls-3.s
+# ld: -shared -z now
+# objdump: -R
+
+#...
+DYNAMIC RELOCATION RECORDS \(none\)
+
diff --git a/binutils-2.19/ld/testsuite/ld-vxworks/tls-3.s b/binutils-2.19/ld/testsuite/ld-vxworks/tls-3.s
new file mode 100644
index 0000000..39420c2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-vxworks/tls-3.s
@@ -0,0 +1,34 @@
+	.globl	foo
+foo:
+
+	.section	.tls_data,"a"
+	.p2align	2
+	
+	.type	i,%object
+	.size	i,4
+i:
+	.space	4
+	
+	.globl	j
+	.type	j,%object
+	.size	j,4
+j:
+	.space	4
+	
+	.section	.tls_vars,"a"
+	.p2align	2
+	.type	__tls__i,%object
+	.size	__tls__i,12
+__tls__i:
+	.4byte	i
+	.4byte	0
+	.4byte	4
+	
+	.globl	__tls__j
+	.type	__tls__j,%object
+	.size	__tls__j,12
+__tls__j:
+	.4byte	j
+	.4byte	0
+	.4byte	4
+
diff --git a/binutils-2.19/ld/testsuite/ld-vxworks/vxworks.exp b/binutils-2.19/ld/testsuite/ld-vxworks/vxworks.exp
new file mode 100644
index 0000000..a305265
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-vxworks/vxworks.exp
@@ -0,0 +1,27 @@
+# Expect script for VxWorks tests
+#   Copyright 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+if { [istarget *-*-vxworks*] } {
+    foreach test [lsort [glob -nocomplain $srcdir/$subdir/*.d]] {
+	if { [runtest_file_p $runtests $test] } {
+	    run_dump_test [file rootname $test]
+	}
+    }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/abs.d b/binutils-2.19/ld/testsuite/ld-x86-64/abs.d
new file mode 100644
index 0000000..b24b018
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/abs.d
@@ -0,0 +1,10 @@
+#name: Absolute non-overflowing relocs
+#source: ../ld-i386/abs.s
+#source: ../ld-i386/zero.s
+#ld:
+#objdump: -rs
+
+.*:     file format .*
+
+Contents of section \.text:
+[ 	][0-9a-f]+ c800fff0 c8000110 c9c3.*
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/dwarfreloc.exp b/binutils-2.19/ld/testsuite/ld-x86-64/dwarfreloc.exp
new file mode 100644
index 0000000..8137a3d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/dwarfreloc.exp
@@ -0,0 +1,86 @@
+# Expect script for DWARF relocation test.
+#   Copyright 2008  Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+#
+# Written by Jan Kratochvil (jan.kratochvil@redhat.com)
+#
+# Test PR ld/3290 Comment 8+9.  DW_FORM_ref_addr used in dwarfreloc2.s was left
+# unrelocated as its target symbol from dwarfreloc1.s became LOCAL due to its
+# `ld -r'.
+#
+#  <1><57>: Abbrev Number: 2 (DW_TAG_variable)
+#     <58>   DW_AT_name        : i2	
+#  ...
+#     <5d>   DW_AT_type        : <0x32>	
+# vs.
+#     <5d>   DW_AT_type        : <0x0>	
+
+# Only the testcase .s files are arch-dependent, the relocations are cross-arch.
+if { !([istarget "x86_64-*-elf*"]
+       || [istarget "x86_64-*-linux*"]) } {
+    return
+}
+
+set build_tests_ld {
+  {"Build dwarfreloc1x.o"
+   "-r" ""
+   {dwarfreloc1.s} {} "dwarfreloc1x.o"}
+  {"Build dwarfreloc2.o"
+   "-r" ""
+   {dwarfreloc2.s} {} "dwarfreloc2x.o"}
+}
+
+run_ld_link_tests $build_tests_ld
+
+set testname "Link dwarfreloc1x.o and dwarfreloc2x.o to dwarfreloc.o"
+if [ld_simple_link $ld "tmpdir/dwarfreloc.o" "-r tmpdir/dwarfreloc1x.o tmpdir/dwarfreloc2x.o"] {
+    pass $testname
+} else {
+    fail $testname
+}
+
+# The code is copied from `ld-lib.exp'.  We cannot use the functions there as
+# they expect source (.s or .c) files while we to check a `ld -r' output (.o).
+
+set testname "Check dwarfreloc.o readelf"
+set dumpfile "dwarfreloc.rd"
+set cmd "$READELF --debug-dump=info tmpdir/dwarfreloc.o"
+set status [remote_exec host [concat sh -c [list "$cmd >dump.out 2>ld.stderr"]] "" "/dev/null"]
+send_log "$cmd\n"
+remote_upload host "ld.stderr"
+set comp_output [prune_warnings [file_contents "ld.stderr"]]
+remote_file host delete "ld.stderr"
+remote_file build delete "ld.stderr"
+
+if ![string match "" $comp_output] then {
+    send_log "$comp_output\n"
+    fail $testname
+} else {
+    remote_upload host "dump.out"
+    if { [regexp_diff "dump.out" "$srcdir/$subdir/$dumpfile"] } then {
+	verbose "output is [file_contents "dump.out"]" 2
+	fail $testname
+    } else {
+	pass $testname
+    }
+    remote_file build delete "dump.out"
+    remote_file host delete "dump.out"
+}
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/dwarfreloc.rd b/binutils-2.19/ld/testsuite/ld-x86-64/dwarfreloc.rd
new file mode 100644
index 0000000..84798ce
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/dwarfreloc.rd
@@ -0,0 +1,17 @@
+# Parenthesized `(...)' is the offset we cross-check.
+# The third parenthesized value was left unrelocated (0x0) before.
+#...
+.*Abbrev Number: .* \(DW_TAG_variable\).*
+#...
+.*DW_AT_type *: *<0x(32)>.*
+#...
+.*<(32)>: Abbrev Number: .* \(DW_TAG_base_type\).*
+#...
+.*Compilation Unit.*
+#...
+.*Abbrev Number: .* \(DW_TAG_compile_unit\).*
+#...
+.*Abbrev Number: .* \(DW_TAG_variable\).*
+#...
+.*DW_AT_type        : <0x(32)>.*
+#...
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/dwarfreloc1.s b/binutils-2.19/ld/testsuite/ld-x86-64/dwarfreloc1.s
new file mode 100644
index 0000000..2f46ae2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/dwarfreloc1.s
@@ -0,0 +1,101 @@
+	.file	1 "dwarfreloc1.c"
+	.comm   i1,4,4
+	.section	.debug_line,"",@progbits
+.Ldebug_line0:
+	.section	.debug_info
+.Ldebug_info0:
+	.long	.Ldebug_info_end - .Ldebug_info_start
+.Ldebug_info_start:
+	.value	0x2
+	.long	.Ldebug_abbrev0
+	.byte	0x8
+
+	.uleb128 0x1		/* DW_TAG_compile_unit */
+	.long	.LASF0		/* DW_AT_producer */
+	.byte	0x1		/* DW_AT_language */
+	.long	.LASF1		/* DW_AT_name */
+	.long	.LASF2		/* DW_AT_comp_dir */
+	.long	.Ldebug_line0	/* DW_AT_stmt_list */
+
+	.uleb128 0x2		/* DW_TAG_variable */
+	.string	"i1"		/* DW_AT_name */
+	.byte	0x1		/* DW_AT_decl_file */
+	.byte	0x1		/* DW_AT_decl_line */
+	.long	.dwarfreloc1.0.2 - .Ldebug_info0 /* DW_AT_type (DW_FORM_ref4) */
+	.byte	0x1		/* DW_AT_external */
+	.byte	0x9		/* DW_AT_location: length */
+	.byte	0x3		/* DW_AT_location: DW_OP_addr */
+	.quad	i1		/* DW_AT_location: DW_OP_addr: address */
+
+	/* DWARF3 Page 224 (236/267)
+	<prefix>.<file-designator>.<gid-number>.<die-number>  */
+	.globl .dwarfreloc1.0.2
+.dwarfreloc1.0.2:
+	.uleb128 0x3		/* DW_TAG_base_type */
+	.byte	0x4		/* DW_AT_byte_size */
+	.byte	0x5		/* DW_AT_encoding */
+	.string	"int"		/* DW_AT_name */
+
+	.byte	0x0
+.Ldebug_info_end:
+
+	.section	.debug_abbrev
+.Ldebug_abbrev0:
+	.uleb128 0x1
+	.uleb128 0x11
+
+	.byte	0x1
+	.uleb128 0x25	/* DW_AT_producer */
+	.uleb128 0xe	/* DW_FORM_strp */
+	.uleb128 0x13	/* DW_AT_language */
+	.uleb128 0xb	/* DW_FORM_data1 */
+	.uleb128 0x3	/* DW_AT_name */
+	.uleb128 0xe	/* DW_FORM_strp */
+	.uleb128 0x1b	/* DW_AT_comp_dir */
+	.uleb128 0xe	/* DW_FORM_strp */
+	.uleb128 0x10	/* DW_AT_stmt_list */
+	.uleb128 0x6	/* DW_FORM_data4 */
+	.byte	0x0
+	.byte	0x0
+
+	.uleb128 0x2
+	.uleb128 0x34	/* DW_TAG_variable */
+	.byte	0x0
+	.uleb128 0x3	/* DW_AT_name */
+	.uleb128 0x8	/* DW_FORM_string */
+	.uleb128 0x3a	/* DW_AT_decl_file */
+	.uleb128 0xb	/* DW_FORM_data1 */
+	.uleb128 0x3b	/* DW_AT_decl_line */
+	.uleb128 0xb	/* DW_FORM_data1 */
+	.uleb128 0x49	/* DW_AT_type */
+	.uleb128 0x13	/* DW_FORM_ref4 */
+	.uleb128 0x3f	/* DW_AT_external */
+	.uleb128 0xc	/* DW_FORM_flag */
+	.uleb128 0x2	/* DW_AT_location */
+	.uleb128 0xa	/* DW_FORM_block1 */
+	.byte	0x0
+	.byte	0x0
+
+	.uleb128 0x3
+	.uleb128 0x24	/* DW_TAG_base_type */
+	.byte	0x0
+	.uleb128 0xb	/* DW_AT_byte_size */
+	.uleb128 0xb	/* DW_FORM_data1 */
+	.uleb128 0x3e	/* DW_AT_encoding */
+	.uleb128 0xb	/* DW_FORM_data1 */
+	.uleb128 0x3	/* DW_AT_name */
+	.uleb128 0x8	/* DW_FORM_string */
+	.byte	0x0
+	.byte	0x0
+
+	.byte	0x0
+
+	.section	.debug_str,"MS",@progbits,1
+.LASF1:
+	.string	"dwarfreloc1.c"
+.LASF0:
+	.string	"GNU C 4.3.1 20080801 (Red Hat 4.3.1-6)"
+.LASF2:
+	.string	"/"
+	.ident	"GCC: (GNU) 4.3.1 20080801 (Red Hat 4.3.1-6)"
+	.section	.note.GNU-stack,"",@progbits
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/dwarfreloc2.s b/binutils-2.19/ld/testsuite/ld-x86-64/dwarfreloc2.s
new file mode 100644
index 0000000..dee3b87
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/dwarfreloc2.s
@@ -0,0 +1,94 @@
+	.file	1 "dwarfreloc2.c"
+	.comm   i2,4,4
+	.section	.debug_line,"",@progbits
+.Ldebug_line0:
+	.section	.debug_info
+.Ldebug_info0:
+	.long	.Ldebug_info_end - .Ldebug_info_start
+.Ldebug_info_start:
+	.value	0x2
+	.long	.Ldebug_abbrev0
+	.byte	0x8
+
+	.uleb128 0x1		/* DW_TAG_compile_unit */
+	.long	.LASF0		/* DW_AT_producer */
+	.byte	0x1		/* DW_AT_language */
+	.long	.LASF1		/* DW_AT_name */
+	.long	.LASF2		/* DW_AT_comp_dir */
+	.long	.Ldebug_line0	/* DW_AT_stmt_list */
+
+	.uleb128 0x2		/* DW_TAG_variable */
+	.string	"i2"		/* DW_AT_name */
+	.byte	0x1		/* DW_AT_decl_file */
+	.byte	0x1		/* DW_AT_decl_line */
+	/* DWARF3 Page 224 (236/267)
+	<prefix>.<file-designator>.<gid-number>.<die-number>  */
+	.quad	.dwarfreloc1.0.2 /* DW_AT_type (DW_FORM_ref_addr) */
+	.byte	0x1		/* DW_AT_external */
+	.byte	0x9		/* DW_AT_location: length */
+	.byte	0x3		/* DW_AT_location: DW_OP_addr */
+	.quad	i2		/* DW_AT_location: DW_OP_addr: address */
+
+	.byte	0x0
+.Ldebug_info_end:
+
+	.section	.debug_abbrev
+.Ldebug_abbrev0:
+	.uleb128 0x1
+	.uleb128 0x11
+
+	.byte	0x1
+	.uleb128 0x25	/* DW_AT_producer */
+	.uleb128 0xe	/* DW_FORM_strp */
+	.uleb128 0x13	/* DW_AT_language */
+	.uleb128 0xb	/* DW_FORM_data1 */
+	.uleb128 0x3	/* DW_AT_name */
+	.uleb128 0xe	/* DW_FORM_strp */
+	.uleb128 0x1b	/* DW_AT_comp_dir */
+	.uleb128 0xe	/* DW_FORM_strp */
+	.uleb128 0x10	/* DW_AT_stmt_list */
+	.uleb128 0x6	/* DW_FORM_data4 */
+	.byte	0x0
+	.byte	0x0
+
+	.uleb128 0x2
+	.uleb128 0x34	/* DW_TAG_variable */
+	.byte	0x0
+	.uleb128 0x3	/* DW_AT_name */
+	.uleb128 0x8	/* DW_FORM_string */
+	.uleb128 0x3a	/* DW_AT_decl_file */
+	.uleb128 0xb	/* DW_FORM_data1 */
+	.uleb128 0x3b	/* DW_AT_decl_line */
+	.uleb128 0xb	/* DW_FORM_data1 */
+	.uleb128 0x49	/* DW_AT_type */
+	.uleb128 0x10	/* DW_FORM_ref_addr */
+	.uleb128 0x3f	/* DW_AT_external */
+	.uleb128 0xc	/* DW_FORM_flag */
+	.uleb128 0x2	/* DW_AT_location */
+	.uleb128 0xa	/* DW_FORM_block1 */
+	.byte	0x0
+	.byte	0x0
+
+	.uleb128 0x3
+	.uleb128 0x24	/* DW_TAG_base_type */
+	.byte	0x0
+	.uleb128 0xb	/* DW_AT_byte_size */
+	.uleb128 0xb	/* DW_FORM_data1 */
+	.uleb128 0x3e	/* DW_AT_encoding */
+	.uleb128 0xb	/* DW_FORM_data1 */
+	.uleb128 0x3	/* DW_AT_name */
+	.uleb128 0x8	/* DW_FORM_string */
+	.byte	0x0
+	.byte	0x0
+
+	.byte	0x0
+
+	.section	.debug_str,"MS",@progbits,1
+.LASF1:
+	.string	"dwarfreloc2.c"
+.LASF0:
+	.string	"GNU C 4.3.1 20080801 (Red Hat 4.3.1-6)"
+.LASF2:
+	.string	"/"
+	.ident	"GCC: (GNU) 4.3.1 20080801 (Red Hat 4.3.1-6)"
+	.section	.note.GNU-stack,"",@progbits
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/hidden1.d b/binutils-2.19/ld/testsuite/ld-x86-64/hidden1.d
new file mode 100644
index 0000000..c4c843b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/hidden1.d
@@ -0,0 +1,3 @@
+#as: --64
+#ld: -shared -melf_x86_64
+#error: .*relocation R_X86_64_PC32 against undefined hidden symbol `foo' can not be used when making a shared object
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/hidden1.s b/binutils-2.19/ld/testsuite/ld-x86-64/hidden1.s
new file mode 100644
index 0000000..ba7f88b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/hidden1.s
@@ -0,0 +1,9 @@
+	.text
+.globl bar
+	.type	bar, @function
+bar:
+	leaq	foo(%rip), %rax
+	ret
+	.size	bar, .-bar
+	.weak	foo
+	.hidden	foo
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/hidden2.d b/binutils-2.19/ld/testsuite/ld-x86-64/hidden2.d
new file mode 100644
index 0000000..0d89e6e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/hidden2.d
@@ -0,0 +1,13 @@
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -drw
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+[a-f0-9]+ <bar>:
+[ 	]*[a-f0-9]+:	e8 33 fe ff ff       	callq  0 <bar-0x[a-f0-9]+>
+[ 	]*[a-f0-9]+:	c3                   	retq   
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/hidden2.s b/binutils-2.19/ld/testsuite/ld-x86-64/hidden2.s
new file mode 100644
index 0000000..03e2ce7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/hidden2.s
@@ -0,0 +1,9 @@
+	.text
+.globl bar
+	.type	bar, @function
+bar:
+	call	foo
+	ret
+	.size	bar, .-bar
+	.weak	foo
+	.hidden	foo
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/hidden3.d b/binutils-2.19/ld/testsuite/ld-x86-64/hidden3.d
new file mode 100644
index 0000000..c4c843b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/hidden3.d
@@ -0,0 +1,3 @@
+#as: --64
+#ld: -shared -melf_x86_64
+#error: .*relocation R_X86_64_PC32 against undefined hidden symbol `foo' can not be used when making a shared object
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/hidden3.s b/binutils-2.19/ld/testsuite/ld-x86-64/hidden3.s
new file mode 100644
index 0000000..75482aa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/hidden3.s
@@ -0,0 +1,8 @@
+	.text
+.globl bar
+	.type	bar, @function
+bar:
+	leaq	foo(%rip), %rax
+	ret
+	.size	bar, .-bar
+	.hidden	foo
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/line.exp b/binutils-2.19/ld/testsuite/ld-x86-64/line.exp
new file mode 100644
index 0000000..c68daaa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/line.exp
@@ -0,0 +1,57 @@
+# Test that the linker reports undefined symbol line number correctly.
+#
+#   Copyright 2007  Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+if { !([istarget "x86_64-*-elf*"]
+       || [istarget "x86_64-*-linux*"]) } {
+    return
+}
+
+set testline "undefined line"
+
+if ![ld_assemble $as "--64 $srcdir/$subdir/undefined.s" tmpdir/undefined.o] {
+    verbose "Unable to assemble test file!" 1
+    unresolved $testline
+    return
+}
+
+remote_file host delete "tmpdir/undefined"
+
+# Using -e start prevents the SunOS linker from trying to build a
+# shared library.
+send_log "$ld -e start -melf_x86_64 -o tmpdir/undefined tmpdir/undefined.o\n"
+set exec_output [run_host_cmd "$ld" "-e start -melf_x86_64 -o tmpdir/undefined tmpdir/undefined.o"]
+
+send_log "$exec_output\n"
+verbose "$exec_output"
+
+proc checkund { string testname } {
+    global exec_output
+
+    if [string match "*$string*" $exec_output] {
+	pass $testname
+    } else {
+	fail $testname
+    }
+}
+
+set ml "undefined.c:9: undefined reference to `*this_function_is_not_defined'"
+
+checkund $ml $testline
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/pcrel16.d b/binutils-2.19/ld/testsuite/ld-x86-64/pcrel16.d
new file mode 100644
index 0000000..f593657
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/pcrel16.d
@@ -0,0 +1,15 @@
+#name: PCREL16 overflow
+#source: ../ld-i386/pcrel16.s
+#ld: -Ttext 0x0
+#objdump: -drj.text -m i8086
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+ <_start>:
+	...
+     420:	cd 42[ 	]+int    \$0x42
+     422:	ca 02 00[ 	]+lret   \$0x2
+	...
+    f065:	e9 b8 13[ 	]+jmp    420 <_start\+0x420>
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/pcrel8.d b/binutils-2.19/ld/testsuite/ld-x86-64/pcrel8.d
new file mode 100644
index 0000000..17a3bba
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/pcrel8.d
@@ -0,0 +1,4 @@
+#name: PCREL8 overflow
+#source: ../ld-i386/pcrel8.s
+#ld:
+#error: .*relocation truncated to fit: R_X86_64_PC8 .*
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/protected1.d b/binutils-2.19/ld/testsuite/ld-x86-64/protected1.d
new file mode 100644
index 0000000..783b85a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/protected1.d
@@ -0,0 +1,3 @@
+#as: --64
+#ld: -shared -melf_x86_64
+#error: .*relocation R_X86_64_PC32 against protected symbol `foo' can not be used when making a shared object
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/protected1.s b/binutils-2.19/ld/testsuite/ld-x86-64/protected1.s
new file mode 100644
index 0000000..31368aa
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/protected1.s
@@ -0,0 +1,13 @@
+	.text
+.globl foo
+	.protected	foo
+	.type	foo, @function
+foo:
+	ret
+	.size	foo, .-foo
+.globl bar
+	.type	bar, @function
+bar:
+	leaq	foo(%rip), %rax
+	ret
+	.size	bar, .-bar
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/protected2.d b/binutils-2.19/ld/testsuite/ld-x86-64/protected2.d
new file mode 100644
index 0000000..2e91b17
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/protected2.d
@@ -0,0 +1,16 @@
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -drw
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+[a-f0-9]+ <foo>:
+[ 	]*[a-f0-9]+:	c3                   	retq   
+
+0+[a-f0-9]+ <bar>:
+[ 	]*[a-f0-9]+:	e8 fa ff ff ff       	callq  [a-f0-9]+ <foo>
+[ 	]*[a-f0-9]+:	c3                   	retq   
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/protected2.s b/binutils-2.19/ld/testsuite/ld-x86-64/protected2.s
new file mode 100644
index 0000000..61e5aec
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/protected2.s
@@ -0,0 +1,13 @@
+	.text
+.globl foo
+	.protected	foo
+	.type	foo, @function
+foo:
+	ret
+	.size	foo, .-foo
+.globl bar
+	.type	bar, @function
+bar:
+	call	foo
+	ret
+	.size	bar, .-bar
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/protected3.d b/binutils-2.19/ld/testsuite/ld-x86-64/protected3.d
new file mode 100644
index 0000000..09556ce
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/protected3.d
@@ -0,0 +1,13 @@
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -drw
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+[a-f0-9]+ <bar>:
+[ 	]*[a-f0-9]+:	8b 05 ce 00 20 00    	mov    0x[a-f0-9]+\(%rip\),%eax        # [a-f0-9]+ <foo>
+[ 	]*[a-f0-9]+:	c3                   	retq   
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/protected3.s b/binutils-2.19/ld/testsuite/ld-x86-64/protected3.s
new file mode 100644
index 0000000..e4af6e7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/protected3.s
@@ -0,0 +1,15 @@
+	.protected	foo
+.globl foo
+	.data
+	.align 4
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	1
+	.text
+.globl bar
+	.type	bar, @function
+bar:
+	movl	foo(%rip), %eax
+	ret
+	.size	bar, .-bar
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsbin.dd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbin.dd
new file mode 100644
index 0000000..1ea00d0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbin.dd
@@ -0,0 +1,310 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -drj.text
+#target: x86_64-*-*
+
+# PT_TLS layout is:
+# Offset from   Offset from     Name
+# TCB base      TCB end
+# 0x00          -0xa0           sg1..sg8
+# 0x20          -0x80           sl1..sl8
+# 0x40          -0x60           sh1..sh8
+# 0x60          -0x40           bg1..bg8
+# 0x80          -0x20           bl1..bl8
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+401000 <fn2>:
+  401000:	55[ 	]+push   %rbp
+  401001:	48 89 e5[ 	]+mov    %rsp,%rbp
+#  GD -> IE because variable is not defined in executable
+  401004:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+  40100b:	00 00 *
+  40100d:	48 03 05 d4 03 20 00[ 	]+add    0x2003d4\(%rip\),%rax +# 6013e8 <.*>
+#				-> R_X86_64_TPOFF64	sG1
+  401014:	90[ 	]+nop *
+  401015:	90[ 	]+nop *
+  401016:	90[ 	]+nop *
+  401017:	90[ 	]+nop *
+#  GD -> IE because variable is not defined in executable where
+#  the variable is referenced through IE too
+  401018:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+  40101f:	00 00 *
+  401021:	48 03 05 b0 03 20 00[ 	]+add    0x2003b0\(%rip\),%rax +# 6013d8 <.*>
+#				-> R_X86_64_TPOFF64	sG2
+  401028:	90[ 	]+nop *
+  401029:	90[ 	]+nop *
+  40102a:	90[ 	]+nop *
+  40102b:	90[ 	]+nop *
+#  GD -> LE with global variable defined in executable
+  40102c:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+  401033:	00 00 *
+  401035:	48 8d 80 60 ff ff ff[ 	]+lea    -0xa0\(%rax\),%rax
+#							sg1
+  40103c:	90[ 	]+nop *
+  40103d:	90[ 	]+nop *
+  40103e:	90[ 	]+nop *
+  40103f:	90[ 	]+nop *
+#  GD -> LE with local variable defined in executable
+  401040:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+  401047:	00 00 *
+  401049:	48 8d 80 80 ff ff ff[ 	]+lea    -0x80\(%rax\),%rax
+#							sl1
+  401050:	90[ 	]+nop *
+  401051:	90[ 	]+nop *
+  401052:	90[ 	]+nop *
+  401053:	90[ 	]+nop *
+#  GD -> LE with hidden variable defined in executable
+  401054:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+  40105b:	00 00 *
+  40105d:	48 8d 80 a0 ff ff ff[ 	]+lea    -0x60\(%rax\),%rax
+#							sh1
+  401064:	90[ 	]+nop *
+  401065:	90[ 	]+nop *
+  401066:	90[ 	]+nop *
+  401067:	90[ 	]+nop *
+#  LD -> LE
+  401068:	66 66 66 64 48 8b 04[ 	]+mov    %fs:0x0,%rax
+  40106f:	25 00 00 00 00 *
+  401074:	90[ 	]+nop *
+  401075:	90[ 	]+nop *
+  401076:	48 8d 90 81 ff ff ff[ 	]+lea    -0x7f\(%rax\),%rdx
+#							sl1+1
+  40107d:	90[ 	]+nop *
+  40107e:	90[ 	]+nop *
+  40107f:	4c 8d 88 86 ff ff ff[ 	]+lea    -0x7a\(%rax\),%r9
+#							sl2+2
+  401086:	90[ 	]+nop *
+  401087:	90[ 	]+nop *
+  401088:	90[ 	]+nop *
+  401089:	90[ 	]+nop *
+#  LD -> LE against hidden variables
+  40108a:	66 66 66 64 48 8b 04[ 	]+mov    %fs:0x0,%rax
+  401091:	25 00 00 00 00 *
+  401096:	90[ 	]+nop *
+  401097:	90[ 	]+nop *
+  401098:	48 8d 90 a0 ff ff ff[ 	]+lea    -0x60\(%rax\),%rdx
+#							sh1
+  40109f:	90[ 	]+nop *
+  4010a0:	90[ 	]+nop *
+  4010a1:	48 8d 88 a7 ff ff ff[ 	]+lea    -0x59\(%rax\),%rcx
+#							sh2+3
+  4010a8:	90[ 	]+nop *
+  4010a9:	90[ 	]+nop *
+  4010aa:	90[ 	]+nop *
+  4010ab:	90[ 	]+nop *
+#  IE against global var
+  4010ac:	64 4c 8b 0c 25 00 00[ 	]+mov    %fs:0x0,%r9
+  4010b3:	00 00 *
+  4010b5:	90[ 	]+nop *
+  4010b6:	90[ 	]+nop *
+  4010b7:	4c 03 0d 1a 03 20 00[ 	]+add    0x20031a\(%rip\),%r9 +# 6013d8 <.*>
+#				-> R_X86_64_TPOFF64	sG2
+  4010be:	90[ 	]+nop *
+  4010bf:	90[ 	]+nop *
+  4010c0:	90[ 	]+nop *
+  4010c1:	90[ 	]+nop *
+#  IE -> LE against global var defined in exec
+  4010c2:	64 4c 8b 14 25 00 00[ 	]+mov    %fs:0x0,%r10
+  4010c9:	00 00 *
+  4010cb:	90[ 	]+nop *
+  4010cc:	90[ 	]+nop *
+  4010cd:	4d 8d 92 60 ff ff ff[ 	]+lea    -0xa0\(%r10\),%r10
+#							sg1
+  4010d4:	90[ 	]+nop *
+  4010d5:	90[ 	]+nop *
+  4010d6:	90[ 	]+nop *
+  4010d7:	90[ 	]+nop *
+#  IE -> LE against local var
+  4010d8:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+  4010df:	00 00 *
+  4010e1:	90[ 	]+nop *
+  4010e2:	90[ 	]+nop *
+  4010e3:	48 8d 80 80 ff ff ff[ 	]+lea    -0x80\(%rax\),%rax
+#							sl1
+  4010ea:	90[ 	]+nop *
+  4010eb:	90[ 	]+nop *
+  4010ec:	90[ 	]+nop *
+  4010ed:	90[ 	]+nop *
+#  IE -> LE against hidden var
+  4010ee:	64 48 8b 0c 25 00 00[ 	]+mov    %fs:0x0,%rcx
+  4010f5:	00 00 *
+  4010f7:	90[ 	]+nop *
+  4010f8:	90[ 	]+nop *
+  4010f9:	48 8d 89 a0 ff ff ff[ 	]+lea    -0x60\(%rcx\),%rcx
+#							sh1
+  401100:	90[ 	]+nop *
+  401101:	90[ 	]+nop *
+  401102:	90[ 	]+nop *
+  401103:	90[ 	]+nop *
+#  Direct access through %fs
+#  IE against global var
+  401104:	48 8b 0d c5 02 20 00[ 	]+mov    0x2002c5\(%rip\),%rcx +# 6013d0 <.*>
+#				-> R_X86_64_TPOFF64	sG5
+  40110b:	90[ 	]+nop *
+  40110c:	90[ 	]+nop *
+  40110d:	64 48 8b 11[ 	]+mov    %fs:\(%rcx\),%rdx
+  401111:	90[ 	]+nop *
+  401112:	90[ 	]+nop *
+  401113:	90[ 	]+nop *
+  401114:	90[ 	]+nop *
+#  IE->LE against local var
+  401115:	49 c7 c3 90 ff ff ff[ 	]+mov    \$0xf+90,%r11
+#							sl5
+  40111c:	90[ 	]+nop *
+  40111d:	90[ 	]+nop *
+  40111e:	64 4d 8b 23[ 	]+mov    %fs:\(%r11\),%r12
+  401122:	90[ 	]+nop *
+  401123:	90[ 	]+nop *
+  401124:	90[ 	]+nop *
+  401125:	90[ 	]+nop *
+#  IE->LE against hidden var
+  401126:	48 c7 c2 b0 ff ff ff[ 	]+mov    \$0xf+b0,%rdx
+  40112d:	90[ 	]+nop *
+  40112e:	90[ 	]+nop *
+  40112f:	64 48 8b 12[ 	]+mov    %fs:\(%rdx\),%rdx
+#							sh5
+  401133:	90[ 	]+nop *
+  401134:	90[ 	]+nop *
+  401135:	90[ 	]+nop *
+  401136:	90[ 	]+nop *
+  401137:	c9[ 	]+leaveq *
+  401138:	c3[ 	]+retq *
+  401139:	90[ 	]+nop *
+  40113a:	90[ 	]+nop *
+  40113b:	90[ 	]+nop *
+
+0+40113c <_start>:
+  40113c:	55[ 	]+push   %rbp
+  40113d:	48 89 e5[ 	]+mov    %rsp,%rbp
+#  IE against global var
+  401140:	64 4c 8b 1c 25 00 00[ 	]+mov    %fs:0x0,%r11
+  401147:	00 00 *
+  401149:	90[ 	]+nop *
+  40114a:	90[ 	]+nop *
+  40114b:	4c 03 1d 8e 02 20 00[ 	]+add    0x20028e\(%rip\),%r11 +# 6013e0 <.*>
+#				-> R_X86_64_TPOFF64	sG6
+  401152:	90[ 	]+nop *
+  401153:	90[ 	]+nop *
+  401154:	90[ 	]+nop *
+  401155:	90[ 	]+nop *
+#  IE -> LE against global var defined in exec
+  401156:	64 48 8b 14 25 00 00[ 	]+mov    %fs:0x0,%rdx
+  40115d:	00 00 *
+  40115f:	90[ 	]+nop *
+  401160:	90[ 	]+nop *
+  401161:	48 8d 92 d4 ff ff ff[ 	]+lea    -0x2c\(%rdx\),%rdx
+#							bg6
+  401168:	90[ 	]+nop *
+  401169:	90[ 	]+nop *
+  40116a:	90[ 	]+nop *
+  40116b:	90[ 	]+nop *
+#  IE -> LE against local var
+  40116c:	64 4c 8b 24 25 00 00[ 	]+mov    %fs:0x0,%r12
+  401173:	00 00 *
+  401175:	90[ 	]+nop *
+  401176:	90[ 	]+nop *
+  401177:	49 81 c4 f4 ff ff ff[ 	]+add    \$0xf+f4,%r12
+#							bl6
+  40117e:	90[ 	]+nop *
+  40117f:	90[ 	]+nop *
+  401180:	90[ 	]+nop *
+  401181:	90[ 	]+nop *
+#  direct %fs access IE -> LE against local var
+  401182:	48 c7 c2 fc ff ff ff[ 	]+mov    \$0xf+fc,%rdx
+#							bl8
+  401189:	90[ 	]+nop *
+  40118a:	90[ 	]+nop *
+  40118b:	64 48 8b 02[ 	]+mov    %fs:\(%rdx\),%rax
+  40118f:	90[ 	]+nop *
+  401190:	90[ 	]+nop *
+  401191:	90[ 	]+nop *
+  401192:	90[ 	]+nop *
+#  IE -> LE against hidden but not local var
+  401193:	64 48 8b 14 25 00 00[ 	]+mov    %fs:0x0,%rdx
+  40119a:	00 00 *
+  40119c:	90[ 	]+nop *
+  40119d:	90[ 	]+nop *
+  40119e:	48 8d 92 b4 ff ff ff[ 	]+lea    -0x4c\(%rdx\),%rdx
+#							sh6
+  4011a5:	90[ 	]+nop *
+  4011a6:	90[ 	]+nop *
+  4011a7:	90[ 	]+nop *
+  4011a8:	90[ 	]+nop *
+#  direct %fs access IE -> LE against hidden but not local var
+  4011a9:	48 c7 c2 bc ff ff ff[ 	]+mov    \$0xf+bc,%rdx
+#							sh8
+  4011b0:	90[ 	]+nop *
+  4011b1:	90[ 	]+nop *
+  4011b2:	64 48 8b 02[ 	]+mov    %fs:\(%rdx\),%rax
+  4011b6:	90[ 	]+nop *
+  4011b7:	90[ 	]+nop *
+  4011b8:	90[ 	]+nop *
+  4011b9:	90[ 	]+nop *
+#  LE, global var defined in exec
+  4011ba:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+  4011c1:	00 00 *
+  4011c3:	90[ 	]+nop *
+  4011c4:	90[ 	]+nop *
+  4011c5:	48 8d 90 64 ff ff ff[ 	]+lea    -0x9c\(%rax\),%rdx
+#							sg2
+  4011cc:	90[ 	]+nop *
+  4011cd:	90[ 	]+nop *
+  4011ce:	90[ 	]+nop *
+  4011cf:	90[ 	]+nop *
+#  LE, local var, non-canonical sequence
+  4011d0:	49 c7 c1 e6 ff ff ff[ 	]+mov    \$0xf+e6,%r9
+#							bl2+2
+  4011d7:	90[ 	]+nop *
+  4011d8:	90[ 	]+nop *
+  4011d9:	64 48 8b 14 25 00 00[ 	]+mov    %fs:0x0,%rdx
+  4011e0:	00 00 *
+  4011e2:	90[ 	]+nop *
+  4011e3:	90[ 	]+nop *
+  4011e4:	4c 01 ca[ 	]+add    %r9,%rdx
+  4011e7:	90[ 	]+nop *
+  4011e8:	90[ 	]+nop *
+  4011e9:	90[ 	]+nop *
+  4011ea:	90[ 	]+nop *
+#  LE, hidden var defined in exec, non-canonical sequence
+  4011eb:	64 48 8b 14 25 00 00[ 	]+mov    %fs:0x0,%rdx
+  4011f2:	00 00 *
+  4011f4:	90[ 	]+nop *
+  4011f5:	90[ 	]+nop *
+  4011f6:	48 81 c2 a5 ff ff ff[ 	]+add    \$0xf+a5,%rdx
+#							sh2+1
+  4011fd:	90[ 	]+nop *
+  4011fe:	90[ 	]+nop *
+  4011ff:	90[ 	]+nop *
+  401200:	90[ 	]+nop *
+#  Direct %fs access
+#  LE, global var defined in exec
+  401201:	64 48 8b 04 25 68 ff[ 	]+mov    %fs:0xf+68,%rax
+  401208:	ff ff *
+#							sg3
+  40120a:	90[ 	]+nop *
+  40120b:	90[ 	]+nop *
+  40120c:	90[ 	]+nop *
+  40120d:	90[ 	]+nop *
+#  LE, local var
+  40120e:	64 4c 8b 14 25 eb ff[ 	]+mov    %fs:0xf+eb,%r10
+  401215:	ff ff *
+#							bl3+3
+  401217:	90[ 	]+nop *
+  401218:	90[ 	]+nop *
+  401219:	90[ 	]+nop *
+  40121a:	90[ 	]+nop *
+#  LE, hidden var defined in exec
+  40121b:	64 48 8b 14 25 a9 ff[ 	]+mov    %fs:0xf+a9,%rdx
+  401222:	ff ff *
+#							sh3+1
+  401224:	90[ 	]+nop *
+  401225:	90[ 	]+nop *
+  401226:	90[ 	]+nop *
+  401227:	90[ 	]+nop *
+  401228:	c9[ 	]+leaveq *
+  401229:	c3[ 	]+retq *
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsbin.rd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbin.rd
new file mode 100644
index 0000000..cf47b4e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbin.rd
@@ -0,0 +1,147 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: --64
+#ld: -shared -melf_x86_64
+#readelf: -WSsrl
+#target: x86_64-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0
+ +\[[ 0-9]+\] .interp +.*
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .rela.plt +.*
+ +\[[ 0-9]+\] .plt +.*
+ +\[[ 0-9]+\] .text +PROGBITS +0+401000 0+1000 0+22a 00 +AX +0 +0 +4096
+ +\[[ 0-9]+\] .tdata +PROGBITS +0+60122a 0+122a 0+60 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .tbss +NOBITS +0+60128a 0+128a 0+40 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+601290 0+1290 0+140 10 +WA +4 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+6013d0 0+13d0 0+20 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+6013f0 0+13f0 0+20 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x40113c
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  PHDR.*
+  INTERP.*
+.*Requesting program interpreter.*
+  LOAD +0x0+ 0x0+400000 0x0+400000 0x0+122a 0x0+122a R E 0x200000
+  LOAD +0x0+122a 0x0+60122a 0x0+60122a 0x0+1e6 0x0+1e6 RW  0x200000
+  DYNAMIC +0x0+1290 0x0+601290 0x0+601290 0x0+140 0x0+140 RW  0x8
+  TLS +0x0+122a 0x0+60122a 0x0+60122a 0x0+60 0x0+a0 R +0x1
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 *
+   01 +.interp *
+   02 +.interp .hash .dynsym .dynstr .rela.dyn .rela.plt .plt .text *
+   03 +.tdata .dynamic .got .got.plt *
+   04 +.dynamic *
+   05 +.tdata .tbss *
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
+ +Offset +Info +Type +Symbol's Value  Symbol's Name \+ Addend
+[0-9a-f ]+R_X86_64_TPOFF64 +0+ sG5 \+ 0
+[0-9a-f ]+R_X86_64_TPOFF64 +0+ sG2 \+ 0
+[0-9a-f ]+R_X86_64_TPOFF64 +0+ sG6 \+ 0
+[0-9a-f ]+R_X86_64_TPOFF64 +0+ sG1 \+ 0
+
+Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ +Offset +Info +Type +Symbol's Value  Symbol's Name \+ Addend
+[0-9a-f ]+R_X86_64_JUMP_SLOT[0-9a-f ]+__tls_get_addr \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE  LOCAL  DEFAULT  UND *
+.* TLS +GLOBAL DEFAULT  UND sG5
+.* TLS +GLOBAL DEFAULT  UND sG2
+.* FUNC +GLOBAL DEFAULT  UND __tls_get_addr
+.* NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.* TLS +GLOBAL DEFAULT  UND sG6
+.* TLS +GLOBAL DEFAULT  UND sG1
+.* NOTYPE  GLOBAL DEFAULT  ABS _edata
+.* NOTYPE  GLOBAL DEFAULT  ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE  LOCAL  DEFAULT  UND *
+.* SECTION LOCAL  DEFAULT +1 *
+.* SECTION LOCAL  DEFAULT +2 *
+.* SECTION LOCAL  DEFAULT +3 *
+.* SECTION LOCAL  DEFAULT +4 *
+.* SECTION LOCAL  DEFAULT +5 *
+.* SECTION LOCAL  DEFAULT +6 *
+.* SECTION LOCAL  DEFAULT +7 *
+.* SECTION LOCAL  DEFAULT +8 *
+.* SECTION LOCAL  DEFAULT +9 *
+.* SECTION LOCAL  DEFAULT +10 *
+.* SECTION LOCAL  DEFAULT +11 *
+.* SECTION LOCAL  DEFAULT +12 *
+.* SECTION LOCAL  DEFAULT +13 *
+.* TLS +LOCAL  DEFAULT +9 sl1
+.* TLS +LOCAL  DEFAULT +9 sl2
+.* TLS +LOCAL  DEFAULT +9 sl3
+.* TLS +LOCAL  DEFAULT +9 sl4
+.* TLS +LOCAL  DEFAULT +9 sl5
+.* TLS +LOCAL  DEFAULT +9 sl6
+.* TLS +LOCAL  DEFAULT +9 sl7
+.* TLS +LOCAL  DEFAULT +9 sl8
+.* TLS +LOCAL  DEFAULT +10 bl1
+.* TLS +LOCAL  DEFAULT +10 bl2
+.* TLS +LOCAL  DEFAULT +10 bl3
+.* TLS +LOCAL  DEFAULT +10 bl4
+.* TLS +LOCAL  DEFAULT +10 bl5
+.* TLS +LOCAL  DEFAULT +10 bl6
+.* TLS +LOCAL  DEFAULT +10 bl7
+.* TLS +LOCAL  DEFAULT +10 bl8
+.* OBJECT  LOCAL  HIDDEN +11 _DYNAMIC
+.* OBJECT  LOCAL  HIDDEN +13 _GLOBAL_OFFSET_TABLE_
+.* TLS +GLOBAL DEFAULT +9 sg8
+.* TLS +GLOBAL DEFAULT +10 bg8
+.* TLS +GLOBAL DEFAULT +10 bg6
+.* TLS +GLOBAL DEFAULT  UND sG5
+.* TLS +GLOBAL DEFAULT +10 bg3
+.* TLS +GLOBAL DEFAULT +9 sg3
+.* TLS +GLOBAL HIDDEN +9 sh3
+.* TLS +GLOBAL DEFAULT  UND sG2
+.* TLS +GLOBAL DEFAULT +9 sg4
+.* TLS +GLOBAL DEFAULT +9 sg5
+.* TLS +GLOBAL DEFAULT +10 bg5
+.* FUNC +GLOBAL DEFAULT  UND __tls_get_addr
+.* TLS +GLOBAL HIDDEN +9 sh7
+.* TLS +GLOBAL HIDDEN +9 sh8
+.* TLS +GLOBAL DEFAULT +9 sg1
+.* FUNC +GLOBAL DEFAULT +8 _start
+.* TLS +GLOBAL HIDDEN +9 sh4
+.* TLS +GLOBAL DEFAULT +10 bg7
+.* TLS +GLOBAL HIDDEN +9 sh5
+.* NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.* TLS +GLOBAL DEFAULT  UND sG6
+.* FUNC +GLOBAL DEFAULT +8 fn2
+.* TLS +GLOBAL DEFAULT +9 sg2
+.* TLS +GLOBAL DEFAULT  UND sG1
+.* TLS +GLOBAL HIDDEN +9 sh1
+.* TLS +GLOBAL DEFAULT +9 sg6
+.* TLS +GLOBAL DEFAULT +9 sg7
+.* NOTYPE  GLOBAL DEFAULT  ABS _edata
+.* NOTYPE  GLOBAL DEFAULT  ABS _end
+.* TLS +GLOBAL HIDDEN +9 sh2
+.* TLS +GLOBAL HIDDEN +9 sh6
+.* TLS +GLOBAL DEFAULT +10 bg2
+.* TLS +GLOBAL DEFAULT +10 bg1
+.* TLS +GLOBAL DEFAULT +10 bg4
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsbin.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbin.s
new file mode 100644
index 0000000..eb9bfbc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbin.s
@@ -0,0 +1,97 @@
+	.section ".tbss", "awT", @nobits
+	.globl bg1, bg2, bg3, bg4, bg5, bg6, bg7, bg8
+bg1:	.space 4
+bg2:	.space 4
+bg3:	.space 4
+bg4:	.space 4
+bg5:	.space 4
+bg6:	.space 4
+bg7:	.space 4
+bg8:	.space 4
+bl1:	.space 4
+bl2:	.space 4
+bl3:	.space 4
+bl4:	.space 4
+bl5:	.space 4
+bl6:	.space 4
+bl7:	.space 4
+bl8:	.space 4
+	.text
+	.globl	_start
+	.type	_start,@function
+_start:
+	pushq	%rbp
+	movq	%rsp, %rbp
+
+	/* IE against global var  */
+	movq	%fs:0, %r11
+	nop;nop
+	addq	sG6@gottpoff(%rip), %r11
+	nop;nop;nop;nop
+
+	/* IE -> LE against global var defined in exec  */
+	movq	%fs:0, %rdx
+	nop;nop
+	addq	bg6@gottpoff(%rip), %rdx
+	nop;nop;nop;nop
+
+	/* IE -> LE against local var  */
+	movq	%fs:0, %r12
+	nop;nop
+	addq	bl6@gottpoff(%rip), %r12
+	nop;nop;nop;nop
+
+	/* direct %fs access IE -> LE against local var  */
+	movq	bl8@gottpoff(%rip), %rdx
+	nop;nop
+	movq	%fs:(%rdx), %rax
+	nop;nop;nop;nop
+
+	/* IE -> LE against hidden but not local var  */
+	movq	%fs:0, %rdx
+	nop;nop
+	addq	sh6@gottpoff(%rip), %rdx
+	nop;nop;nop;nop
+
+	/* direct %fs access IE -> LE against hidden but not local var  */
+	movq	sh8@gottpoff(%rip), %rdx
+	nop;nop
+	movq	%fs:(%rdx), %rax
+	nop;nop;nop;nop
+
+	/* LE, global var defined in exec  */
+	movq	%fs:0, %rax
+	nop;nop
+	leaq	sg2@tpoff(%rax), %rdx
+	nop;nop;nop;nop
+
+	/* LE, local var, non-canonical sequence  */
+	movq	$2+bl2@tpoff, %r9
+	nop;nop
+	movq	%fs:0, %rdx
+	nop;nop
+	addq	%r9, %rdx
+	nop;nop;nop;nop
+
+	/* LE, hidden var defined in exec, non-canonical sequence */
+	movq	%fs:0, %rdx
+	nop;nop
+	addq	$sh2@tpoff+1, %rdx
+	nop;nop;nop;nop
+
+	/* Direct %fs access  */
+
+	/* LE, global var defined in exec  */
+	movq	%fs:sg3@tpoff, %rax
+	nop;nop;nop;nop
+
+	/* LE, local var  */
+	movq	%fs:bl3@tpoff+3, %r10
+	nop;nop;nop;nop
+
+	/* LE, hidden var defined in exec  */
+	movq	%fs:1+sh3@tpoff, %rdx
+	nop;nop;nop;nop
+
+	leave
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsbin.sd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbin.sd
new file mode 100644
index 0000000..7fbc565
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbin.sd
@@ -0,0 +1,12 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -sj.got
+#target: x86_64-*-*
+
+.*: +file format elf64-x86-64
+
+Contents of section .got:
+ 6013d0 00000000 00000000 00000000 00000000  .*
+ 6013e0 00000000 00000000 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsbin.td b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbin.td
new file mode 100644
index 0000000..b3851de
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbin.td
@@ -0,0 +1,16 @@
+#source: tlsbinpic.s
+#source: tlsbin.s
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -sj.tdata
+#target: x86_64-*-*
+
+.*: +file format elf64-x86-64
+
+Contents of section .tdata:
+ 60122a 11000000 12000000 13000000 14000000  .*
+ 60123a 15000000 16000000 17000000 18000000  .*
+ 60124a 41000000 42000000 43000000 44000000  .*
+ 60125a 45000000 46000000 47000000 48000000  .*
+ 60126a 01010000 02010000 03010000 04010000  .*
+ 60127a 05010000 06010000 07010000 08010000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsbindesc.dd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbindesc.dd
new file mode 100644
index 0000000..9e82eab
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbindesc.dd
@@ -0,0 +1,301 @@
+#source: tlsbindesc.s
+#source: tlsbin.s
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -drj.text
+#target: x86_64-*-*
+
+# PT_TLS layout is:
+# Offset from   Offset from     Name
+# TCB base      TCB end
+# 0x00          -0xa0           sg1..sg8
+# 0x20          -0x80           sl1..sl8
+# 0x40          -0x60           sh1..sh8
+# 0x60          -0x40           bg1..bg8
+# 0x80          -0x20           bl1..bl8
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+401000 <fn2>:
+  [0-9a-f]+:	55[ 	]+push   %rbp
+  [0-9a-f]+:	48 89 e5[ 	]+mov    %rsp,%rbp
+#  GD -> IE because variable is not defined in executable
+  [0-9a-f]+:	48 8b 05 65 03 20 00[ 	]+mov    0x200365\(%rip\),%rax +# 601370 <.*>
+#				-> R_X86_64_TPOFF64	sG1
+  [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is not defined in executable where
+#  the variable is referenced through IE too
+  [0-9a-f]+:	48 8b 05 48 03 20 00[ 	]+mov    0x200348\(%rip\),%rax +# 601360 <.*>
+#				-> R_X86_64_TPOFF64	sG2
+  [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  GD -> LE with global variable defined in executable
+  [0-9a-f]+:	48 c7 c0 60 ff ff ff[ 	]+mov    \$0xf+60,%rax
+#							sg1
+  [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  GD -> LE with local variable defined in executable
+  [0-9a-f]+:	48 c7 c0 80 ff ff ff[ 	]+mov    \$0xf+80,%rax
+#							sl1
+  [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  GD -> LE with hidden variable defined in executable
+  [0-9a-f]+:	48 c7 c0 a0 ff ff ff[ 	]+mov    \$0xf+a0,%rax
+#							sh1
+  [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  LD -> LE
+  [0-9a-f]+:	48 c7 c0 00 00 00 00[ 	]+mov    \$0x0,%rax
+  [0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	48 8d 90 81 ff ff ff[ 	]+lea    -0x7f\(%rax\),%rdx
+#							sl1+1
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	4c 8d 88 86 ff ff ff[ 	]+lea    -0x7a\(%rax\),%r9
+#							sl2+2
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  LD -> LE against hidden variables
+  [0-9a-f]+:	48 8d 90 a0 ff ff ff[ 	]+lea    -0x60\(%rax\),%rdx
+#							sh1
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	48 8d 88 a7 ff ff ff[ 	]+lea    -0x59\(%rax\),%rcx
+#							sh2+3
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  IE against global var
+  [0-9a-f]+:	64 4c 8b 0c 25 00 00[ 	]+mov    %fs:0x0,%r9
+  [0-9a-f]+:	00 00 *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	4c 03 0d d6 02 20 00[ 	]+add    0x2002d6\(%rip\),%r9 +# 601360 <.*>
+#				-> R_X86_64_TPOFF64	sG2
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  IE -> LE against global var defined in exec
+  [0-9a-f]+:	64 4c 8b 14 25 00 00[ 	]+mov    %fs:0x0,%r10
+  [0-9a-f]+:	00 00 *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	4d 8d 92 60 ff ff ff[ 	]+lea    -0xa0\(%r10\),%r10
+#							sg1
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  IE -> LE against local var
+  [0-9a-f]+:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+  [0-9a-f]+:	00 00 *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	48 8d 80 80 ff ff ff[ 	]+lea    -0x80\(%rax\),%rax
+#							sl1
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  IE -> LE against hidden var
+  [0-9a-f]+:	64 48 8b 0c 25 00 00[ 	]+mov    %fs:0x0,%rcx
+  [0-9a-f]+:	00 00 *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	48 8d 89 a0 ff ff ff[ 	]+lea    -0x60\(%rcx\),%rcx
+#							sh1
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  Direct access through %fs
+#  IE against global var
+  [0-9a-f]+:	48 8b 0d 81 02 20 00[ 	]+mov    0x200281\(%rip\),%rcx +# 601358 <.*>
+#				-> R_X86_64_TPOFF64	sG5
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	64 48 8b 11[ 	]+mov    %fs:\(%rcx\),%rdx
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  IE->LE against local var
+  [0-9a-f]+:	49 c7 c3 90 ff ff ff[ 	]+mov    \$0xf+90,%r11
+#							sl5
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	64 4d 8b 23[ 	]+mov    %fs:\(%r11\),%r12
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  IE->LE against hidden var
+  [0-9a-f]+:	48 c7 c2 b0 ff ff ff[ 	]+mov    \$0xf+b0,%rdx
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	64 48 8b 12[ 	]+mov    %fs:\(%rdx\),%rdx
+#							sh5
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	c9[ 	]+leaveq *
+  [0-9a-f]+:	c3[ 	]+retq *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+
+[0-9a-f]+ <_start>:
+  [0-9a-f]+:	55[ 	]+push   %rbp
+  [0-9a-f]+:	48 89 e5[ 	]+mov    %rsp,%rbp
+#  IE against global var
+  [0-9a-f]+:	64 4c 8b 1c 25 00 00[ 	]+mov    %fs:0x0,%r11
+  [0-9a-f]+:	00 00 *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	4c 03 1d 4a 02 20 00[ 	]+add    0x20024a\(%rip\),%r11 +# 601368 <.*>
+#				-> R_X86_64_TPOFF64	sG6
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  IE -> LE against global var defined in exec
+  [0-9a-f]+:	64 48 8b 14 25 00 00[ 	]+mov    %fs:0x0,%rdx
+  [0-9a-f]+:	00 00 *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	48 8d 92 d4 ff ff ff[ 	]+lea    -0x2c\(%rdx\),%rdx
+#							bg6
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  IE -> LE against local var
+  [0-9a-f]+:	64 4c 8b 24 25 00 00[ 	]+mov    %fs:0x0,%r12
+  [0-9a-f]+:	00 00 *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	49 81 c4 f4 ff ff ff[ 	]+add    \$0xf+f4,%r12
+#							bl6
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  direct %fs access IE -> LE against local var
+  [0-9a-f]+:	48 c7 c2 fc ff ff ff[ 	]+mov    \$0xf+fc,%rdx
+#							bl8
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	64 48 8b 02[ 	]+mov    %fs:\(%rdx\),%rax
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  IE -> LE against hidden but not local var
+  [0-9a-f]+:	64 48 8b 14 25 00 00[ 	]+mov    %fs:0x0,%rdx
+  [0-9a-f]+:	00 00 *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	48 8d 92 b4 ff ff ff[ 	]+lea    -0x4c\(%rdx\),%rdx
+#							sh6
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  direct %fs access IE -> LE against hidden but not local var
+  [0-9a-f]+:	48 c7 c2 bc ff ff ff[ 	]+mov    \$0xf+bc,%rdx
+#							sh8
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	64 48 8b 02[ 	]+mov    %fs:\(%rdx\),%rax
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  LE, global var defined in exec
+  [0-9a-f]+:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+  [0-9a-f]+:	00 00 *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	48 8d 90 64 ff ff ff[ 	]+lea    -0x9c\(%rax\),%rdx
+#							sg2
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  LE, local var, non-canonical sequence
+  [0-9a-f]+:	49 c7 c1 e6 ff ff ff[ 	]+mov    \$0xf+e6,%r9
+#							bl2+2
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	64 48 8b 14 25 00 00[ 	]+mov    %fs:0x0,%rdx
+  [0-9a-f]+:	00 00 *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	4c 01 ca[ 	]+add    %r9,%rdx
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  LE, hidden var defined in exec, non-canonical sequence
+  [0-9a-f]+:	64 48 8b 14 25 00 00[ 	]+mov    %fs:0x0,%rdx
+  [0-9a-f]+:	00 00 *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	48 81 c2 a5 ff ff ff[ 	]+add    \$0xf+a5,%rdx
+#							sh2+1
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  Direct %fs access
+#  LE, global var defined in exec
+  [0-9a-f]+:	64 48 8b 04 25 68 ff[ 	]+mov    %fs:0xf+68,%rax
+  [0-9a-f]+:	ff ff *
+#							sg3
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  LE, local var
+  [0-9a-f]+:	64 4c 8b 14 25 eb ff[ 	]+mov    %fs:0xf+eb,%r10
+  [0-9a-f]+:	ff ff *
+#							bl3+3
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+#  LE, hidden var defined in exec
+  [0-9a-f]+:	64 48 8b 14 25 a9 ff[ 	]+mov    %fs:0xf+a9,%rdx
+  [0-9a-f]+:	ff ff *
+#							sh3+1
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	90[ 	]+nop *
+  [0-9a-f]+:	c9[ 	]+leaveq *
+  [0-9a-f]+:	c3[ 	]+retq *
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsbindesc.rd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbindesc.rd
new file mode 100644
index 0000000..b70d78f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbindesc.rd
@@ -0,0 +1,138 @@
+#source: tlsbindesc.s
+#source: tlsbin.s
+#as: --64
+#ld: -shared -melf_x86_64
+#readelf: -WSsrl
+#target: x86_64-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0
+ +\[[ 0-9]+\] .interp +.*
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .text +PROGBITS +0+401000 0+1000 0+1f6 00 +AX +0 +0 +4096
+ +\[[ 0-9]+\] .tdata +PROGBITS +0+6011f6 0+11f6 0+60 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .tbss +NOBITS +0+601256 0+1256 0+40 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+601258 0+1258 0+100 10 +WA +4 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+601358 0+1358 0+20 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+601378 0+1378 0+18 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x401108
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  PHDR.*
+  INTERP.*
+.*Requesting program interpreter.*
+  LOAD +0x0+ 0x0+400000 0x0+400000 0x0+11f6 0x0+11f6 R E 0x200000
+  LOAD +0x0+11f6 0x0+6011f6 0x0+6011f6 0x0+19a 0x0+19a RW  0x200000
+  DYNAMIC +0x0+1258 0x0+601258 0x0+601258 0x0+100 0x0+100 RW  0x8
+  TLS +0x0+11f6 0x0+6011f6 0x0+6011f6 0x0+60 0x0+a0 R +0x1
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 *
+   01 +.interp *
+   02 +.interp .hash .dynsym .dynstr .rela.dyn .text *
+   03 +.tdata .dynamic .got .got.plt *
+   04 +.dynamic *
+   05 +.tdata .tbss *
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 4 entries:
+ +Offset +Info +Type +Symbol's Value  Symbol's Name \+ Addend
+0+601358  0+100000012 R_X86_64_TPOFF64 +0+ sG5 \+ 0
+0+601360  0+200000012 R_X86_64_TPOFF64 +0+ sG2 \+ 0
+0+601368  0+400000012 R_X86_64_TPOFF64 +0+ sG6 \+ 0
+0+601370  0+500000012 R_X86_64_TPOFF64 +0+ sG1 \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG2
+ +[0-9]+: 0+[0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG6
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG1
+ +[0-9]+: 0+[0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: 0+[0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +1 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +2 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +3 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +4 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +5 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +6 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +7 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +8 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +9 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +10 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +11 *
+ +[0-9]+: 0+20 +0 TLS +LOCAL  DEFAULT +7 sl1
+ +[0-9]+: 0+24 +0 TLS +LOCAL  DEFAULT +7 sl2
+ +[0-9]+: 0+28 +0 TLS +LOCAL  DEFAULT +7 sl3
+ +[0-9]+: 0+2c +0 TLS +LOCAL  DEFAULT +7 sl4
+ +[0-9]+: 0+30 +0 TLS +LOCAL  DEFAULT +7 sl5
+ +[0-9]+: 0+34 +0 TLS +LOCAL  DEFAULT +7 sl6
+ +[0-9]+: 0+38 +0 TLS +LOCAL  DEFAULT +7 sl7
+ +[0-9]+: 0+3c +0 TLS +LOCAL  DEFAULT +7 sl8
+ +[0-9]+: 0+80 +0 TLS +LOCAL  DEFAULT +8 bl1
+ +[0-9]+: 0+84 +0 TLS +LOCAL  DEFAULT +8 bl2
+ +[0-9]+: 0+88 +0 TLS +LOCAL  DEFAULT +8 bl3
+ +[0-9]+: 0+8c +0 TLS +LOCAL  DEFAULT +8 bl4
+ +[0-9]+: 0+90 +0 TLS +LOCAL  DEFAULT +8 bl5
+ +[0-9]+: 0+94 +0 TLS +LOCAL  DEFAULT +8 bl6
+ +[0-9]+: 0+98 +0 TLS +LOCAL  DEFAULT +8 bl7
+ +[0-9]+: 0+9c +0 TLS +LOCAL  DEFAULT +8 bl8
+ +[0-9]+: 0+a0 +0 TLS +LOCAL  HIDDEN +7 _TLS_MODULE_BASE_
+ +[0-9]+: 0+601258 +0 OBJECT  LOCAL  HIDDEN    9 _DYNAMIC
+ +[0-9]+: 0+601378 +0 OBJECT  LOCAL  HIDDEN   11 _GLOBAL_OFFSET_TABLE_
+ +[0-9]+: 0+1c +0 TLS +GLOBAL DEFAULT +7 sg8
+ +[0-9]+: 0+7c +0 TLS +GLOBAL DEFAULT +8 bg8
+ +[0-9]+: 0+74 +0 TLS +GLOBAL DEFAULT +8 bg6
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG5
+ +[0-9]+: 0+68 +0 TLS +GLOBAL DEFAULT +8 bg3
+ +[0-9]+: 0+8 +0 TLS +GLOBAL DEFAULT +7 sg3
+ +[0-9]+: 0+48 +0 TLS +GLOBAL HIDDEN +7 sh3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG2
+ +[0-9]+: 0+c +0 TLS +GLOBAL DEFAULT +7 sg4
+ +[0-9]+: 0+10 +0 TLS +GLOBAL DEFAULT +7 sg5
+ +[0-9]+: 0+70 +0 TLS +GLOBAL DEFAULT +8 bg5
+ +[0-9]+: 0+58 +0 TLS +GLOBAL HIDDEN +7 sh7
+ +[0-9]+: 0+5c +0 TLS +GLOBAL HIDDEN +7 sh8
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +7 sg1
+ +[0-9]+: 0+401108 +0 FUNC +GLOBAL DEFAULT +6 _start
+ +[0-9]+: 0+4c +0 TLS +GLOBAL HIDDEN +7 sh4
+ +[0-9]+: 0+78 +0 TLS +GLOBAL DEFAULT +8 bg7
+ +[0-9]+: 0+50 +0 TLS +GLOBAL HIDDEN +7 sh5
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG6
+ +[0-9]+: 0+401000 +0 FUNC +GLOBAL DEFAULT +6 fn2
+ +[0-9]+: 0+4 +0 TLS +GLOBAL DEFAULT +7 sg2
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG1
+ +[0-9]+: 0+40 +0 TLS +GLOBAL HIDDEN +7 sh1
+ +[0-9]+: 0+14 +0 TLS +GLOBAL DEFAULT +7 sg6
+ +[0-9]+: 0+18 +0 TLS +GLOBAL DEFAULT +7 sg7
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+ +[0-9]+: 0+44 +0 TLS +GLOBAL HIDDEN +7 sh2
+ +[0-9]+: 0+54 +0 TLS +GLOBAL HIDDEN +7 sh6
+ +[0-9]+: 0+64 +0 TLS +GLOBAL DEFAULT +8 bg2
+ +[0-9]+: 0+60 +0 TLS +GLOBAL DEFAULT +8 bg1
+ +[0-9]+: 0+6c +0 TLS +GLOBAL DEFAULT +8 bg4
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsbindesc.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbindesc.s
new file mode 100644
index 0000000..cbebf02
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbindesc.s
@@ -0,0 +1,128 @@
+	/* Force .data aligned to 4K, so that .got very likely gets at
+	   0x5021a0 (0x60 bytes .tdata and 0x140 bytes .dynamic)  */
+	.data
+	.balign	4096
+	.section ".tdata", "awT", @progbits
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+	/* Force .text aligned to 4K, so it very likely gets at 0x401000.  */
+	.text
+	.balign	4096
+	.globl	fn2
+	.type	fn2,@function
+fn2:
+	pushq	%rbp
+	movq	%rsp, %rbp
+
+	/* GD -> IE because variable is not defined in executable */
+	leaq	sG1@tlsdesc(%rip), %rax
+	call	*sG1@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is not defined in executable where
+	   the variable is referenced through IE too */
+	leaq	sG2@tlsdesc(%rip), %rax
+	call	*sG2@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* GD -> LE with global variable defined in executable */
+	leaq	sg1@tlsdesc(%rip), %rax
+	call	*sg1@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* GD -> LE with local variable defined in executable */
+	leaq	sl1@tlsdesc(%rip), %rax
+	call	*sl1@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* GD -> LE with hidden variable defined in executable */
+	leaq	sh1@tlsdesc(%rip), %rax
+	call	*sh1@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* LD -> LE */
+	leaq	_TLS_MODULE_BASE_@tlsdesc(%rip), %rax
+	call	*_TLS_MODULE_BASE_@tlscall(%rax)
+	nop;nop
+	leaq	1+sl1@dtpoff(%rax), %rdx
+	nop;nop
+	leaq	sl2@dtpoff+2(%rax), %r9
+	nop;nop;nop;nop
+
+	/* LD -> LE against hidden variables */
+	leaq	sh1@dtpoff(%rax), %rdx
+	nop;nop
+	leaq	3+sh2@dtpoff(%rax), %rcx
+	nop;nop;nop;nop
+
+	/* IE against global var  */
+	movq	%fs:0, %r9
+	nop;nop
+	addq	sG2@gottpoff(%rip), %r9
+	nop;nop;nop;nop
+
+	/* IE -> LE against global var defined in exec */
+	movq	%fs:0, %r10
+	nop;nop
+	addq	sg1@gottpoff(%rip), %r10
+	nop;nop;nop;nop
+
+	/* IE -> LE against local var */
+	movq	%fs:0, %rax
+	nop;nop
+	addq	sl1@gottpoff(%rip), %rax
+	nop;nop;nop;nop
+
+	/* IE -> LE against hidden var */
+	movq	%fs:0, %rcx
+	nop;nop
+	addq	sh1@gottpoff(%rip), %rcx
+	nop;nop;nop;nop
+
+	/* Direct access through %fs  */
+
+	/* IE against global var  */
+	movq	sG5@gottpoff(%rip), %rcx
+	nop;nop
+	movq	%fs:(%rcx), %rdx
+	nop;nop;nop;nop
+
+	/* IE->LE against local var  */
+	movq	sl5@gottpoff(%rip), %r11
+	nop;nop
+	movq	%fs:(%r11), %r12
+	nop;nop;nop;nop
+
+	/* IE->LE against hidden var  */
+	movq	sh5@gottpoff(%rip), %rdx
+	nop;nop
+	movq	%fs:(%rdx), %rdx
+	nop;nop;nop;nop
+
+	leave
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsbindesc.sd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbindesc.sd
new file mode 100644
index 0000000..f622bc4
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbindesc.sd
@@ -0,0 +1,12 @@
+#source: tlsbindesc.s
+#source: tlsbin.s
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -sj.got
+#target: x86_64-*-*
+
+.*: +file format elf64-x86-64
+
+Contents of section .got:
+ 601358 00000000 00000000 00000000 00000000  .*
+ 601368 00000000 00000000 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsbindesc.td b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbindesc.td
new file mode 100644
index 0000000..b2a3ebe
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbindesc.td
@@ -0,0 +1,16 @@
+#source: tlsbindesc.s
+#source: tlsbin.s
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -sj.tdata
+#target: x86_64-*-*
+
+.*: +file format elf64-x86-64
+
+Contents of section .tdata:
+ 6011f6 11000000 12000000 13000000 14000000  .*
+ 601206 15000000 16000000 17000000 18000000  .*
+ 601216 41000000 42000000 43000000 44000000  .*
+ 601226 45000000 46000000 47000000 48000000  .*
+ 601236 01010000 02010000 03010000 04010000  .*
+ 601246 05010000 06010000 07010000 08010000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsbinpic.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbinpic.s
new file mode 100644
index 0000000..2819a8f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsbinpic.s
@@ -0,0 +1,146 @@
+	/* Force .data aligned to 4K, so that .got very likely gets at
+	   0x5021a0 (0x60 bytes .tdata and 0x140 bytes .dynamic)  */
+	.data
+	.balign	4096
+	.section ".tdata", "awT", @progbits
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+	/* Force .text aligned to 4K, so it very likely gets at 0x401000.  */
+	.text
+	.balign	4096
+	.globl	fn2
+	.type	fn2,@function
+fn2:
+	pushq	%rbp
+	movq	%rsp, %rbp
+
+	/* GD -> IE because variable is not defined in executable */
+	.byte	0x66
+	leaq	sG1@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is not defined in executable where
+	   the variable is referenced through IE too */
+	.byte	0x66
+	leaq	sG2@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> LE with global variable defined in executable */
+	.byte	0x66
+	leaq	sg1@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> LE with local variable defined in executable */
+	.byte	0x66
+	leaq	sl1@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> LE with hidden variable defined in executable */
+	.byte	0x66
+	leaq	sh1@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* LD -> LE */
+	leaq	sl1@tlsld(%rip), %rdi
+	call	__tls_get_addr@plt
+	nop;nop
+	leaq	1+sl1@dtpoff(%rax), %rdx
+	nop;nop
+	leaq	sl2@dtpoff+2(%rax), %r9
+	nop;nop;nop;nop
+
+	/* LD -> LE against hidden variables */
+	leaq	sh1@tlsld(%rip), %rdi
+	call	__tls_get_addr@plt
+	nop;nop
+	leaq	sh1@dtpoff(%rax), %rdx
+	nop;nop
+	leaq	3+sh2@dtpoff(%rax), %rcx
+	nop;nop;nop;nop
+
+	/* IE against global var  */
+	movq	%fs:0, %r9
+	nop;nop
+	addq	sG2@gottpoff(%rip), %r9
+	nop;nop;nop;nop
+
+	/* IE -> LE against global var defined in exec */
+	movq	%fs:0, %r10
+	nop;nop
+	addq	sg1@gottpoff(%rip), %r10
+	nop;nop;nop;nop
+
+	/* IE -> LE against local var */
+	movq	%fs:0, %rax
+	nop;nop
+	addq	sl1@gottpoff(%rip), %rax
+	nop;nop;nop;nop
+
+	/* IE -> LE against hidden var */
+	movq	%fs:0, %rcx
+	nop;nop
+	addq	sh1@gottpoff(%rip), %rcx
+	nop;nop;nop;nop
+
+	/* Direct access through %fs  */
+
+	/* IE against global var  */
+	movq	sG5@gottpoff(%rip), %rcx
+	nop;nop
+	movq	%fs:(%rcx), %rdx
+	nop;nop;nop;nop
+
+	/* IE->LE against local var  */
+	movq	sl5@gottpoff(%rip), %r11
+	nop;nop
+	movq	%fs:(%r11), %r12
+	nop;nop;nop;nop
+
+	/* IE->LE against hidden var  */
+	movq	sh5@gottpoff(%rip), %rdx
+	nop;nop
+	movq	%fs:(%rdx), %rdx
+	nop;nop;nop;nop
+
+	leave
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.dd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.dd
new file mode 100644
index 0000000..9b0ae61
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.dd
@@ -0,0 +1,200 @@
+#source: tlsdesc.s
+#source: tlspic2.s
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -drj.text
+#target: x86_64-*-*
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+[0-9a-f]+ <fn1>:
+ +[0-9a-f]+:	55[ 	]+push   %rbp
+ +[0-9a-f]+:	48 89 e5[ 	]+mov    %rsp,%rbp
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  GD
+ +[0-9a-f]+:	48 8d 05 89 03 20 00[ 	]+lea    0x200389\(%rip\),%rax +# 201398 <.*>
+#				-> R_X86_64_TLSDESC	sg1
+ +[0-9a-f]+:	ff 10[ 	]+callq  \*\(%rax\)
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE because variable is referenced through IE too
+ +[0-9a-f]+:	48 8b 05 1c 03 20 00[ 	]+mov    0x20031c\(%rip\),%rax +# 201338 <.*>
+#				-> R_X86_64_TPOFF64	sg2
+ +[0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  GD against local variable
+ +[0-9a-f]+:	48 8d 05 3f 03 20 00[ 	]+lea    0x20033f\(%rip\),%rax +# 201368 <.*>
+#				-> R_X86_64_TLSDESC	[0 0x2000000000000000]
+ +[0-9a-f]+:	ff 10[ 	]+callq  \*\(%rax\)
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against local variable referenced through IE too
+ +[0-9a-f]+:	48 8b 05 d2 02 20 00[ 	]+mov    0x2002d2\(%rip\),%rax +# 201308 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x24
+ +[0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  GD against hidden and local variable
+ +[0-9a-f]+:	48 8d 05 65 03 20 00[ 	]+lea    0x200365\(%rip\),%rax +# 2013a8 <.*>
+#				-> R_X86_64_TLSDESC	[0 0x4000000000000000]
+ +[0-9a-f]+:	ff 10[ 	]+callq  \*\(%rax\)
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against hidden and local variable referenced through IE too
+ +[0-9a-f]+:	48 8b 05 f0 02 20 00[ 	]+mov    0x2002f0\(%rip\),%rax +# 201340 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x44
+ +[0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  GD against hidden but not local variable
+ +[0-9a-f]+:	48 8d 05 1b 03 20 00[ 	]+lea    0x20031b\(%rip\),%rax +# 201378 <.*>
+#				-> R_X86_64_TLSDESC	[0 0x6000000000000000]
+ +[0-9a-f]+:	ff 10[ 	]+callq  \*\(%rax\)
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  GD -> IE against hidden but not local variable referenced through IE too
+ +[0-9a-f]+:	48 8b 05 ae 02 20 00[ 	]+mov    0x2002ae\(%rip\),%rax +# 201318 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x64
+ +[0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  LD
+ +[0-9a-f]+:	48 8d 05 11 03 20 00[ 	]+lea    0x200311\(%rip\),%rax +# 201388 <.*>
+#				-> R_X86_64_TLSDESC	[0 0x000000000000000]
+ +[0-9a-f]+:	ff 10[ 	]+callq  \*\(%rax\)
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	48 8d 90 20 00 00 00[ 	]+lea    0x20\(%rax\),%rdx
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	4c 8d 88 26 00 00 00[ 	]+lea    0x26\(%rax\),%r9
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  LD against hidden and local variables
+ +[0-9a-f]+:	48 8d 90 40 00 00 00[ 	]+lea    0x40\(%rax\),%rdx
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	48 8d 88 47 00 00 00[ 	]+lea    0x47\(%rax\),%rcx
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  LD against hidden but not local variables
+ +[0-9a-f]+:	4c 8d a0 60 00 00 00[ 	]+lea    0x60\(%rax\),%r12
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	48 8d 88 65 00 00 00[ 	]+lea    0x65\(%rax\),%rcx
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  IE against global var
+ +[0-9a-f]+:	64 48 8b 0c 25 00 00[ 	]+mov    %fs:0x0,%rcx
+ +[0-9a-f]+:	00 00 *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	48 03 0d 71 02 20 00[ 	]+add    0x200271\(%rip\),%rcx +# 201338 <.*>
+#				-> R_X86_64_TPOFF64	sg2
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  IE against local var
+ +[0-9a-f]+:	64 4c 8b 34 25 00 00[ 	]+mov    %fs:0x0,%r14
+ +[0-9a-f]+:	00 00 *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	4c 03 35 2b 02 20 00[ 	]+add    0x20022b\(%rip\),%r14 +# 201308 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x24
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  IE against hidden and local var
+ +[0-9a-f]+:	64 48 8b 0c 25 00 00[ 	]+mov    %fs:0x0,%rcx
+ +[0-9a-f]+:	00 00 *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	48 03 0d 4d 02 20 00[ 	]+add    0x20024d\(%rip\),%rcx +# 201340 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x44
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  IE against hidden but not local var
+ +[0-9a-f]+:	64 48 8b 0c 25 00 00[ 	]+mov    %fs:0x0,%rcx
+ +[0-9a-f]+:	00 00 *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	48 03 0d 0f 02 20 00[ 	]+add    0x20020f\(%rip\),%rcx +# 201318 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x64
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  Direct access through %fs
+#  IE against global var
+ +[0-9a-f]+:	48 8b 0d 0c 02 20 00[ 	]+mov    0x20020c\(%rip\),%rcx +# 201320 <.*>
+#				-> R_X86_64_TPOFF64	sg5
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	64 48 8b 11[ 	]+mov    %fs:\(%rcx\),%rdx
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  IE against local var
+ +[0-9a-f]+:	4c 8b 15 eb 01 20 00[ 	]+mov    0x2001eb\(%rip\),%r10 +# 201310 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x30
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	64 4d 8b 22[ 	]+mov    %fs:\(%r10\),%r12
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  IE against hidden and local var
+ +[0-9a-f]+:	48 8b 15 f2 01 20 00[ 	]+mov    0x2001f2\(%rip\),%rdx +# 201328 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x50
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	64 48 8b 12[ 	]+mov    %fs:\(%rdx\),%rdx
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+#  IE against hidden but not local var
+ +[0-9a-f]+:	48 8b 0d e9 01 20 00[ 	]+mov    0x2001e9\(%rip\),%rcx +# 201330 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x70
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	64 48 8b 11[ 	]+mov    %fs:\(%rcx\),%rdx
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	c9[ 	]+leaveq *
+ +[0-9a-f]+:	c3[ 	]+retq *
+ +[0-9a-f]+:	90[ 	]+nop *
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.pd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.pd
new file mode 100644
index 0000000..bf3bc2f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.pd
@@ -0,0 +1,20 @@
+#source: tlsdesc.s
+#source: tlspic2.s
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -drj.plt
+#target: x86_64-*-*
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .plt:
+
+[0-9a-f]+ <.*@plt-0x10>:
+ [0-9a-f]+:	ff 35 .. .. 20 00    	pushq  .*\(%rip\)        # 201358 <_GLOBAL_OFFSET_TABLE_\+0x8>
+ [0-9a-f]+:	ff 25 .. .. 20 00    	jmpq   \*.*\(%rip\)        # 201360 <_GLOBAL_OFFSET_TABLE_\+0x10>
+ [0-9a-f]+:	0f 1f 40 00          	nopl   0x0\(%rax\)
+[0-9a-f]+ <.*@plt>:
+ [0-9a-f]+:	ff 35 .. .. 20 00    	pushq  .*\(%rip\)        # 201358 <_GLOBAL_OFFSET_TABLE_\+0x8>
+ [0-9a-f]+:	ff 25 .. .. 20 00    	jmpq   \*.*\(%rip\)        # 201348 <_DYNAMIC\+0x190>
+ [0-9a-f]+:	0f 1f 40 00          	nopl   0x0\(%rax\)
+
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.rd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.rd
new file mode 100644
index 0000000..a69bde1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.rd
@@ -0,0 +1,160 @@
+#source: tlsdesc.s
+#source: tlspic2.s
+#as: --64
+#ld: -shared -melf_x86_64
+#readelf: -WSsrld
+#target: x86_64-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .rela.plt +.*
+ +\[[ 0-9]+\] .plt +PROGBITS +0+450 0+450 0+20 10 +AX +0 +0 +4
+ +\[[ 0-9]+\] .text +PROGBITS +0+1000 0+1000 0+154 00 +AX +0 +0 4096
+ +\[[ 0-9]+\] .tdata +PROGBITS +0+201154 0+1154 0+60 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .tbss +NOBITS +0+2011b4 0+11b4 0+20 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+2011b8 0+11b8 0+150 10 +WA +3 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+201308 0+1308 0+48 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+201350 0+1350 0+68 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x1000
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  LOAD +0x0+ 0x0+ 0x0+ 0x[0-9a-f]+ 0x[0-9a-f]+ R E 0x200000
+  LOAD +0x0+1154 0x0+201154 0x0+201154 0x0+264 0x0+264 RW +0x200000
+  DYNAMIC +0x0+11b8 0x0+2011b8 0x0+2011b8 0x0+150 0x0+150 RW +0x8
+  TLS +0x0+1154 0x0+201154 0x0+201154 0x0+60 0x0+80 R +0x1
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 +.hash .dynsym .dynstr .rela.dyn .rela.plt .plt .text *
+   01 +.tdata .dynamic .got .got.plt *
+   02 +.dynamic *
+   03 +.tdata .tbss *
+
+Dynamic section at offset 0x[0-9a-f]+ contains 16 entries:
+ +Tag +Type +Name/Value
+ 0x[0-9a-f]+ +\(HASH\).*
+ 0x[0-9a-f]+ +\(STRTAB\).*
+ 0x[0-9a-f]+ +\(SYMTAB\).*
+ 0x[0-9a-f]+ +\(STRSZ\).*
+ 0x[0-9a-f]+ +\(SYMENT\).*
+ 0x[0-9a-f]+ +\(PLTGOT\).*
+ 0x[0-9a-f]+ +\(PLTRELSZ\).*
+ 0x[0-9a-f]+ +\(PLTREL\).*
+ 0x[0-9a-f]+ +\(JMPREL\).*
+ 0x[0-9a-f]+ +\(TLSDESC_PLT\) +0x460
+ 0x[0-9a-f]+ +\(TLSDESC_GOT\) +0x201348
+ 0x[0-9a-f]+ +\(RELA\).*
+ 0x[0-9a-f]+ +\(RELASZ\).*
+ 0x[0-9a-f]+ +\(RELAENT\).*
+ 0x[0-9a-f]+ +\(FLAGS\).*
+ 0x[0-9a-f]+ +\(NULL\).*
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 8 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+0+201308  [0-9a-f]+ R_X86_64_TPOFF64 +0+24
+0+201310  [0-9a-f]+ R_X86_64_TPOFF64 +0+30
+0+201318  [0-9a-f]+ R_X86_64_TPOFF64 +0+64
+0+201328  [0-9a-f]+ R_X86_64_TPOFF64 +0+50
+0+201330  [0-9a-f]+ R_X86_64_TPOFF64 +0+70
+0+201340  [0-9a-f]+ R_X86_64_TPOFF64 +0+44
+0+201320  [0-9a-f]+ R_X86_64_TPOFF64 +0+10 sg5 \+ 0
+0+201338  [0-9a-f]+ R_X86_64_TPOFF64 +0+4 sg2 \+ 0
+
+Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 5 entries:
+ +Offset +Info +Type +Symbol's Value  Symbol's Name \+ Addend
+0+201398  [0-9a-f]+ R_X86_64_TLSDESC +0+ sg1 \+ 0
+0+201368  [0-9a-f]+ R_X86_64_TLSDESC +0+20
+0+2013a8  [0-9a-f]+ R_X86_64_TLSDESC +0+40
+0+201378  [0-9a-f]+ R_X86_64_TLSDESC +0+60
+0+201388  [0-9a-f]+ R_X86_64_TLSDESC +0+
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +7 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +8 *
+ +[0-9]+: 0+1c +0 TLS +GLOBAL DEFAULT +8 sg8
+ +[0-9]+: 0+8 +0 TLS +GLOBAL DEFAULT +8 sg3
+ +[0-9]+: 0+c +0 TLS +GLOBAL DEFAULT +8 sg4
+ +[0-9]+: 0+10 +0 TLS +GLOBAL DEFAULT +8 sg5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +8 sg1
+ +[0-9]+: 0+1000 +0 FUNC +GLOBAL DEFAULT +7 fn1
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+4 +0 TLS +GLOBAL DEFAULT +8 sg2
+ +[0-9]+: 0+14 +0 TLS +GLOBAL DEFAULT +8 sg6
+ +[0-9]+: 0+18 +0 TLS +GLOBAL DEFAULT +8 sg7
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +1 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +2 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +3 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +4 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +5 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +6 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +7 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +8 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +9 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +10 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +11 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +12 *
+ +[0-9]+: 0+20 +0 TLS +LOCAL  DEFAULT +8 sl1
+ +[0-9]+: 0+24 +0 TLS +LOCAL  DEFAULT +8 sl2
+ +[0-9]+: 0+28 +0 TLS +LOCAL  DEFAULT +8 sl3
+ +[0-9]+: 0+2c +0 TLS +LOCAL  DEFAULT +8 sl4
+ +[0-9]+: 0+30 +0 TLS +LOCAL  DEFAULT +8 sl5
+ +[0-9]+: 0+34 +0 TLS +LOCAL  DEFAULT +8 sl6
+ +[0-9]+: 0+38 +0 TLS +LOCAL  DEFAULT +8 sl7
+ +[0-9]+: 0+3c +0 TLS +LOCAL  DEFAULT +8 sl8
+ +[0-9]+: 0+60 +0 TLS +LOCAL  HIDDEN +9 sH1
+ +[0-9]+: 0+ +0 TLS +LOCAL  HIDDEN +8 _TLS_MODULE_BASE_
+ +[0-9]+: 0+2011b8 +0 OBJECT  LOCAL  HIDDEN  ABS _DYNAMIC
+ +[0-9]+: 0+48 +0 TLS +LOCAL  HIDDEN +8 sh3
+ +[0-9]+: 0+64 +0 TLS +LOCAL  HIDDEN +9 sH2
+ +[0-9]+: 0+78 +0 TLS +LOCAL  HIDDEN +9 sH7
+ +[0-9]+: 0+58 +0 TLS +LOCAL  HIDDEN +8 sh7
+ +[0-9]+: 0+5c +0 TLS +LOCAL  HIDDEN +8 sh8
+ +[0-9]+: 0+6c +0 TLS +LOCAL  HIDDEN +9 sH4
+ +[0-9]+: 0+4c +0 TLS +LOCAL  HIDDEN +8 sh4
+ +[0-9]+: 0+68 +0 TLS +LOCAL  HIDDEN +9 sH3
+ +[0-9]+: 0+50 +0 TLS +LOCAL  HIDDEN +8 sh5
+ +[0-9]+: 0+70 +0 TLS +LOCAL  HIDDEN +9 sH5
+ +[0-9]+: 0+74 +0 TLS +LOCAL  HIDDEN +9 sH6
+ +[0-9]+: 0+7c +0 TLS +LOCAL  HIDDEN +9 sH8
+ +[0-9]+: 0+40 +0 TLS +LOCAL  HIDDEN +8 sh1
+ +[0-9]+: 0+201350 +0 OBJECT  LOCAL  HIDDEN  ABS _GLOBAL_OFFSET_TABLE_
+ +[0-9]+: 0+44 +0 TLS +LOCAL  HIDDEN +8 sh2
+ +[0-9]+: 0+54 +0 TLS +LOCAL  HIDDEN +8 sh6
+ +[0-9]+: 0+1c +0 TLS +GLOBAL DEFAULT +8 sg8
+ +[0-9]+: 0+8 +0 TLS +GLOBAL DEFAULT +8 sg3
+ +[0-9]+: 0+c +0 TLS +GLOBAL DEFAULT +8 sg4
+ +[0-9]+: 0+10 +0 TLS +GLOBAL DEFAULT +8 sg5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +8 sg1
+ +[0-9]+: 0+1000 +0 FUNC +GLOBAL DEFAULT +7 fn1
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+4 +0 TLS +GLOBAL DEFAULT +8 sg2
+ +[0-9]+: 0+14 +0 TLS +GLOBAL DEFAULT +8 sg6
+ +[0-9]+: 0+18 +0 TLS +GLOBAL DEFAULT +8 sg7
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.s
new file mode 100644
index 0000000..ec6d190
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.s
@@ -0,0 +1,157 @@
+	/* Force .data aligned to 4K, so .got very likely gets at 0x102190
+	   (0x60 bytes .tdata and 0x130 bytes .dynamic)  */
+        .data
+        .balign 4096
+	.section ".tdata", "awT", @progbits
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+	/* Force .text aligned to 4K, so it very likely gets at 0x1000.  */
+	.text
+	.balign	4096
+	.globl	fn1
+	.type	fn1,@function
+fn1:
+	pushq	%rbp
+	movq	%rsp, %rbp
+	nop;nop;nop;nop
+
+	/* GD */
+	leaq	sg1@tlsdesc(%rip), %rax
+	call	*sg1@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is referenced through IE too */
+	leaq	sg2@tlsdesc(%rip), %rax
+	call	*sg2@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* GD against local variable */
+	leaq	sl1@tlsdesc(%rip), %rax
+	call	*sl1@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* GD -> IE against local variable referenced through IE too */
+	leaq	sl2@tlsdesc(%rip), %rax
+	call	*sl2@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* GD against hidden and local variable */
+	leaq	sh1@tlsdesc(%rip), %rax
+	call	*sh1@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden and local variable referenced through
+	   IE too */
+	leaq	sh2@tlsdesc(%rip), %rax
+	call	*sh2@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* GD against hidden but not local variable */
+	leaq	sH1@tlsdesc(%rip), %rax
+	call	*sH1@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden but not local variable referenced through
+	   IE too */
+	leaq	sH2@tlsdesc(%rip), %rax
+	call	*sH2@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* LD */
+	leaq	_TLS_MODULE_BASE_@tlsdesc(%rip), %rax
+	call	*_TLS_MODULE_BASE_@tlscall(%rax)
+	nop;nop
+	leaq	sl1@dtpoff(%rax), %rdx
+	nop;nop
+	leaq	2+sl2@dtpoff(%rax), %r9
+	nop;nop;nop;nop
+
+	/* LD against hidden and local variables */
+	leaq	sh1@dtpoff(%rax), %rdx
+	nop;nop
+	leaq	sh2@dtpoff+3(%rax), %rcx
+	nop;nop;nop;nop
+
+	/* LD against hidden but not local variables */
+	leaq	sH1@dtpoff(%rax), %r12
+	nop;nop
+	leaq	sH2@dtpoff+1(%rax), %rcx
+	nop;nop
+
+	/* IE against global var  */
+	movq	%fs:0, %rcx
+	nop;nop
+	addq	sg2@gottpoff(%rip), %rcx
+	nop;nop;nop;nop
+
+	/* IE against local var  */
+	movq	%fs:0, %r14
+	nop;nop
+	addq	sl2@gottpoff(%rip), %r14
+	nop;nop;nop;nop
+
+	/* IE against hidden and local var  */
+	movq	%fs:0, %rcx
+	nop;nop
+	addq	sh2@gottpoff(%rip), %rcx
+	nop;nop;nop;nop
+
+	/* IE against hidden but not local var  */
+	movq	%fs:0, %rcx
+	nop;nop
+	addq	sH2@gottpoff(%rip), %rcx
+	nop;nop;nop;nop
+
+	/* Direct access through %fs  */
+
+	/* IE against global var  */
+	movq	sg5@gottpoff(%rip), %rcx
+	nop;nop
+	movq	%fs:(%rcx), %rdx
+	nop;nop;nop;nop
+
+	/* IE against local var  */
+	movq	sl5@gottpoff(%rip), %r10
+	nop;nop
+	movq	%fs:(%r10), %r12
+	nop;nop;nop;nop
+
+	/* IE against hidden and local var  */
+	movq	sh5@gottpoff(%rip), %rdx
+	nop;nop
+	movq	%fs:(%rdx), %rdx
+	nop;nop;nop;nop
+
+	/* IE against hidden but not local var  */
+	movq	sH5@gottpoff(%rip), %rcx
+	nop;nop
+	movq	%fs:(%rcx), %rdx
+	nop;nop;nop;nop
+
+	leave
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.sd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.sd
new file mode 100644
index 0000000..7eb474a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.sd
@@ -0,0 +1,23 @@
+#source: tlsdesc.s
+#source: tlspic2.s
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -s -j.got -j.got.plt
+#target: x86_64-*-*
+
+.*: +file format elf64-x86-64
+
+Contents of section \.got:
+ 201308 00000000 00000000 00000000 00000000  .*
+ 201318 00000000 00000000 00000000 00000000  .*
+ 201328 00000000 00000000 00000000 00000000  .*
+ 201338 00000000 00000000 00000000 00000000  .*
+ 201348 00000000 00000000                    .*
+Contents of section \.got\.plt:
+ 201350 b8112000 00000000 00000000 00000000  .*
+ 201360 00000000 00000000 00000000 00000000  .*
+ 201370 00000000 00000000 00000000 00000000  .*
+ 201380 00000000 00000000 00000000 00000000  .*
+ 201390 00000000 00000000 00000000 00000000  .*
+ 2013a0 00000000 00000000 00000000 00000000  .*
+ 2013b0 00000000 00000000                    .*
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.td b/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.td
new file mode 100644
index 0000000..6b8098c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsdesc.td
@@ -0,0 +1,16 @@
+#source: tlsdesc.s
+#source: tlspic2.s
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -sj.tdata
+#target: x86_64-*-*
+
+.*: +file format elf64-x86-64
+
+Contents of section .tdata:
+ 201154 11000000 12000000 13000000 14000000  .*
+ 201164 15000000 16000000 17000000 18000000  .*
+ 201174 41000000 42000000 43000000 44000000  .*
+ 201184 45000000 46000000 47000000 48000000  .*
+ 201194 01010000 02010000 03010000 04010000  .*
+ 2011a4 05010000 06010000 07010000 08010000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsg.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlsg.s
new file mode 100644
index 0000000..048e98f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsg.s
@@ -0,0 +1,12 @@
+	.section	.tbss,"awT",@nobits
+	.align 4
+	.skip	24
+	.type	a,@object
+	.size	a,4
+a:
+	.zero	4
+	.text
+	.globl	_start
+_start:
+	.section	.debug_foobar
+	.long	a@dtpoff, 0
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsg.sd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsg.sd
new file mode 100644
index 0000000..4eaf3cd
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsg.sd
@@ -0,0 +1,10 @@
+#source: tlsg.s
+#as: --64
+#ld: -melf_x86_64
+#objdump: -sj.debug_foobar
+#target: x86_64-*-*
+
+.*: +file format elf64-x86-64
+
+Contents of section .debug_foobar:
+ 0+ 18000000 0+  +.*
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd1.dd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd1.dd
new file mode 100644
index 0000000..b4f3c99
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd1.dd
@@ -0,0 +1,14 @@
+#source: tlsgd1.s
+#as: --64
+#ld: -melf_x86_64 tmpdir/tlsgd1
+#objdump: -drw
+#target: x86_64-*-linux*
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+[a-f0-9]+ <_start>:
+[ 	]*[a-f0-9]+:	64 48 8b 04 25 00 00 00 00 	mov    %fs:0x0,%rax
+[ 	]*[a-f0-9]+:	48 8d 80 fc ff ff ff 	lea    -0x4\(%rax\),%rax
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd1.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd1.s
new file mode 100644
index 0000000..e5f52ed
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd1.s
@@ -0,0 +1,15 @@
+	.text
+	.globl _start
+_start:
+	.byte	0x66
+	leaq	foo@TLSGD(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr
+	.globl foo
+	.section	.tdata,"awT",@progbits
+	.align 4
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	100
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd2.d b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd2.d
new file mode 100644
index 0000000..494560b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd2.d
@@ -0,0 +1,4 @@
+#name: TLS GD->IE transition check
+#as: --64
+#ld: -melf_x86_64
+#error: .*TLS transition from R_X86_64_TLSGD to R_X86_64_GOTTPOFF against `foo'.*failed.*
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd2.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd2.s
new file mode 100644
index 0000000..f583c85
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd2.s
@@ -0,0 +1,5 @@
+	.text
+	.globl _start
+_start:
+	leaq	foo@TLSGD(%rip), %rdi
+	call	__tls_get_addr
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd3.d b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd3.d
new file mode 100644
index 0000000..40f8e3d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd3.d
@@ -0,0 +1,4 @@
+#name: TLS GD->LE transition check
+#as: --64
+#ld: -melf_x86_64
+#error: .*TLS transition from R_X86_64_TLSGD to R_X86_64_TPOFF32 against `a local symbol'.*failed.*
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd3.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd3.s
new file mode 100644
index 0000000..e1e7e60
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgd3.s
@@ -0,0 +1,11 @@
+	.text
+	.globl _start
+_start:
+	leaq	foo@TLSGD(%rip), %rdi
+	call	__tls_get_addr
+	.section	.tdata,"awT",@progbits
+	.align 4
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	100
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsgdesc.dd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgdesc.dd
new file mode 100644
index 0000000..fab88e7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgdesc.dd
@@ -0,0 +1,163 @@
+#source: tlsgdesc.s
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -drj.text
+#target: x86_64-*-*
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+[0-9a-f]+ <fc1>:
+ +[0-9a-f]+:	55[ 	]+push   %rbp
+ +[0-9a-f]+:	48 89 e5[ 	]+mov    %rsp,%rbp
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+# IE
+ +[0-9a-f]+:	64 48 8b 0c 25 00 00[ 	]+mov    %fs:0x0,%rcx
+ +[0-9a-f]+:	00 00 *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	48 03 0d 5e 02 20 00[ 	]+add    0x20025e\(%rip\),%rcx +# 200660 <.*>
+#				-> R_X86_64_TPOFF64	sG3
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+# IE
+ +[0-9a-f]+:	64 48 8b 0c 25 00 00[ 	]+mov    %fs:0x0,%rcx
+ +[0-9a-f]+:	00 00 *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	48 03 0d 68 02 20 00[ 	]+add    0x200268\(%rip\),%rcx +# 200680 <.*>
+#				-> R_X86_64_TPOFF64	sG4
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+# GD, gd first
+ +[0-9a-f]+:	66 48 8d 3d 6c 02 20[ 	]+lea    0x20026c\(%rip\),%rdi +# 200690 <.*>
+ +[0-9a-f]+:	00 *
+#				-> R_X86_64_DTPMOD64	sG1
+ +[0-9a-f]+:	66 66 48 e8 9c ff ff[ 	]+callq  [0-9a-f]+ <.*>
+ +[0-9a-f]+:	ff[ 	]+
+#				-> R_X86_64_JUMP_SLOT	__tls_get_addr
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	48 8d 05 a1 02 20 00[ 	]+lea    0x2002a1\(%rip\),%rax +# 2006d8 <.*>
+#				-> R_X86_64_TLSDESC	sG1
+ +[0-9a-f]+:	ff 10[ 	]+callq  \*\(%rax\)
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+# GD, desc first
+ +[0-9a-f]+:	48 8d 05 84 02 20 00[ 	]+lea    0x200284\(%rip\),%rax +# 2006c8 <.*>
+#				-> R_X86_64_TLSDESC	sG2
+ +[0-9a-f]+:	ff 10[ 	]+callq  \*\(%rax\)
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	66 48 8d 3d 1e 02 20[ 	]+lea    0x20021e\(%rip\),%rdi +# 200670 <.*>
+ +[0-9a-f]+:	00 *
+#				-> R_X86_64_DTPMOD64	sG2
+ +[0-9a-f]+:	66 66 48 e8 6e ff ff[ 	]+callq  [0-9a-f]+ <.*>
+ +[0-9a-f]+:	ff[ 	]+
+#				-> R_X86_64_JUMP_SLOT	__tls_get_addr
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+# GD -> IE, gd first, after IE use
+ +[0-9a-f]+:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+ +[0-9a-f]+:	00 00 *
+ +[0-9a-f]+:	48 03 05 f2 01 20 00[ 	]+add    0x2001f2\(%rip\),%rax +# 200660 <.*>
+#				-> R_X86_64_TPOFF64	sG3
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	48 8b 05 e7 01 20 00[ 	]+mov    0x2001e7\(%rip\),%rax +# 200660 <.*>
+#				-> R_X86_64_TPOFF64	sG3
+ +[0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+# GD -> IE, desc first, after IE use
+ +[0-9a-f]+:	48 8b 05 fa 01 20 00[ 	]+mov    0x2001fa\(%rip\),%rax +# 200680 <.*>
+#				-> R_X86_64_TPOFF64	sG4
+ +[0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+ +[0-9a-f]+:	00 00 *
+ +[0-9a-f]+:	48 03 05 e4 01 20 00[ 	]+add    0x2001e4\(%rip\),%rax +# 200680 <.*>
+#				-> R_X86_64_TPOFF64	sG4
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+# GD -> IE, gd first, before IE use
+ +[0-9a-f]+:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+ +[0-9a-f]+:	00 00 *
+ +[0-9a-f]+:	48 03 05 b8 01 20 00[ 	]+add    0x2001b8\(%rip\),%rax +# 200668 <.*>
+#				-> R_X86_64_TPOFF64	sG5
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	48 8b 05 ad 01 20 00[ 	]+mov    0x2001ad\(%rip\),%rax +# 200668 <.*>
+#				-> R_X86_64_TPOFF64	sG5
+ +[0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+# GD -> IE, desc first, before IE use
+ +[0-9a-f]+:	48 8b 05 c0 01 20 00[ 	]+mov    0x2001c0\(%rip\),%rax +# 200688 <.*>
+#				-> R_X86_64_TPOFF64	sG6
+ +[0-9a-f]+:	66 90[ 	]+xchg   %ax,%ax
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+ +[0-9a-f]+:	00 00 *
+ +[0-9a-f]+:	48 03 05 aa 01 20 00[ 	]+add    0x2001aa\(%rip\),%rax +# 200688 <.*>
+#				-> R_X86_64_TPOFF64	sG6
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+# IE
+ +[0-9a-f]+:	64 48 8b 0c 25 00 00[ 	]+mov    %fs:0x0,%rcx
+ +[0-9a-f]+:	00 00 *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	48 03 0d 74 01 20 00[ 	]+add    0x200174\(%rip\),%rcx +# 200668 <.*>
+#				-> R_X86_64_TPOFF64	sG5
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+# IE
+ +[0-9a-f]+:	64 48 8b 0c 25 00 00[ 	]+mov    %fs:0x0,%rcx
+ +[0-9a-f]+:	00 00 *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	48 03 0d 7e 01 20 00[ 	]+add    0x20017e\(%rip\),%rcx +# 200688 <.*>
+#				-> R_X86_64_TPOFF64	sG6
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	90[ 	]+nop *
+ +[0-9a-f]+:	c9[ 	]+leaveq *
+ +[0-9a-f]+:	c3[ 	]+retq *
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsgdesc.rd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgdesc.rd
new file mode 100644
index 0000000..7806a97
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgdesc.rd
@@ -0,0 +1,104 @@
+#source: tlsgdesc.s
+#as: --64
+#ld: -shared -melf64_x86_64
+#readelf: -WSsrl
+#target: x86_64-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0
+ +\[[ 0-9]+\] \.hash +.*
+ +\[[ 0-9]+\] \.dynsym +.*
+ +\[[ 0-9]+\] \.dynstr +.*
+ +\[[ 0-9]+\] \.rela.dyn +.*
+ +\[[ 0-9]+\] \.rela.plt +.*
+ +\[[ 0-9]+\] \.plt +.*
+ +\[[ 0-9]+\] \.text +.*
+ +\[[ 0-9]+\] \.dynamic +.*
+ +\[[ 0-9]+\] \.got +.*
+ +\[[ 0-9]+\] \.got.plt +.*
+ +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x[0-9a-f]+
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  LOAD.*
+  LOAD.*
+  DYNAMIC.*
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 +.hash .dynsym .dynstr .rela.dyn .rela.plt .plt .text *
+   01 +.dynamic .got .got.plt *
+   02 +.dynamic *
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 8 entries:
+ +Offset +Info +Type +Symbol's Value  Symbol's Name \+ Addend
+[0-9a-f]+  0+200000012 R_X86_64_TPOFF64 +0+ sG3 \+ 0
+[0-9a-f]+  0+300000012 R_X86_64_TPOFF64 +0+ sG5 \+ 0
+[0-9a-f]+  0+400000010 R_X86_64_DTPMOD64 +0+ sG2 \+ 0
+[0-9a-f]+  0+400000011 R_X86_64_DTPOFF64 +0+ sG2 \+ 0
+[0-9a-f]+  0+500000012 R_X86_64_TPOFF64 +0+ sG4 \+ 0
+[0-9a-f]+  0+800000012 R_X86_64_TPOFF64 +0+ sG6 \+ 0
+[0-9a-f]+  0+a00000010 R_X86_64_DTPMOD64 +0+ sG1 \+ 0
+[0-9a-f]+  0+a00000011 R_X86_64_DTPOFF64 +0+ sG1 \+ 0
+
+Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 3 entries:
+ +Offset +Info +Type +Symbol's Value  Symbol's Name \+ Addend
+[0-9a-f]+  0+600000007 R_X86_64_JUMP_SLOT +0+ __tls_get_addr \+ 0
+[0-9a-f]+  0+a00000024 R_X86_64_TLSDESC +0+ sG1 \+ 0
+[0-9a-f]+  0+400000024 R_X86_64_TLSDESC +0+ sG2 \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +7 *
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG2
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG4
+ +[0-9]+: 0+ +0 NOTYPE  GLOBAL DEFAULT  UND __tls_get_addr
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG6
+ +[0-9]+: [0-9a-f]+ +0 FUNC +GLOBAL DEFAULT +7 fc1
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG1
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +1 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +2 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +3 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +4 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +5 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +6 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +7 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +8 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +9 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +10 *
+ +[0-9]+: [0-9a-f]+ +0 OBJECT  LOCAL  HIDDEN  ABS _DYNAMIC
+ +[0-9]+: [0-9a-f]+ +0 OBJECT  LOCAL  HIDDEN  ABS _GLOBAL_OFFSET_TABLE_
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG2
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG4
+ +[0-9]+: 0+ +0 NOTYPE  GLOBAL DEFAULT  UND __tls_get_addr
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG6
+ +[0-9]+: [0-9a-f]+ +0 FUNC +GLOBAL DEFAULT +7 fc1
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG1
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsgdesc.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgdesc.s
new file mode 100644
index 0000000..6657e72
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsgdesc.s
@@ -0,0 +1,106 @@
+	.text
+	.globl	fc1
+	.type	fc1,@function
+fc1:
+	pushq	%rbp
+	movq	%rsp, %rbp
+	nop;nop;nop;nop
+
+	/* IE against global var.  */
+	movq	%fs:0, %rcx
+	nop;nop
+	addq	sG3@gottpoff(%rip), %rcx
+	nop;nop;nop;nop
+
+	/* IE against global var.  */
+	movq	%fs:0, %rcx
+	nop;nop
+	addq	sG4@gottpoff(%rip), %rcx
+	nop;nop;nop;nop
+
+	/* GD, gd first.  */
+	.byte	0x66
+	leaq	sG1@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	leaq	sG1@tlsdesc(%rip), %rax
+	call	*sG1@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* GD, desc first.  */
+	leaq	sG2@tlsdesc(%rip), %rax
+	call	*sG2@tlscall(%rax)
+	nop;nop;nop;nop
+
+	.byte	0x66
+	leaq	sG2@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE, gd first, after IE use.  */
+	.byte	0x66
+	leaq	sG3@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	leaq	sG3@tlsdesc(%rip), %rax
+	call	*sG3@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* GD -> IE, desc first, after IE use.  */
+	leaq	sG4@tlsdesc(%rip), %rax
+	call	*sG4@tlscall(%rax)
+	nop;nop;nop;nop
+
+	.byte	0x66
+	leaq	sG4@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE, gd first, before IE use.  */
+	.byte	0x66
+	leaq	sG5@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	leaq	sG5@tlsdesc(%rip), %rax
+	call	*sG5@tlscall(%rax)
+	nop;nop;nop;nop
+
+	/* GD -> IE, desc first, before IE use.  */
+	leaq	sG6@tlsdesc(%rip), %rax
+	call	*sG6@tlscall(%rax)
+	nop;nop;nop;nop
+
+	.byte	0x66
+	leaq	sG6@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* IE against global var.  */
+	movq	%fs:0, %rcx
+	nop;nop
+	addq	sG5@gottpoff(%rip), %rcx
+	nop;nop;nop;nop
+
+	/* IE against global var.  */
+	movq	%fs:0, %rcx
+	nop;nop
+	addq	sG6@gottpoff(%rip), %rcx
+	nop;nop;nop;nop
+
+	leave
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsie1.dd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsie1.dd
new file mode 100644
index 0000000..74dc39b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsie1.dd
@@ -0,0 +1,16 @@
+#source: tlsie1.s
+#as: --64
+#ld: -melf_x86_64 tmpdir/tlsie1
+#objdump: -drw
+#target: x86_64-*-linux*
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+[a-f0-9]+ <_start>:
+[ 	]*[a-f0-9]+:	48 c7 c0 fc ff ff ff 	mov    \$0xfffffffffffffffc,%rax
+[ 	]*[a-f0-9]+:	48 8d 80 fc ff ff ff 	lea    -0x4\(%rax\),%rax
+[ 	]*[a-f0-9]+:	49 c7 c4 fc ff ff ff 	mov    \$0xfffffffffffffffc,%r12
+[ 	]*[a-f0-9]+:	49 81 c4 fc ff ff ff 	add    \$0xfffffffffffffffc,%r12
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsie1.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlsie1.s
new file mode 100644
index 0000000..c7722b1
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsie1.s
@@ -0,0 +1,14 @@
+	.text
+	.globl _start
+_start:
+	movq	foo@GOTTPOFF(%rip), %rax
+	addq	foo@GOTTPOFF(%rip), %rax
+	movq	foo@GOTTPOFF(%rip), %r12
+	addq	foo@GOTTPOFF(%rip), %r12
+	.globl	foo
+	.section	.tdata,"awT",@progbits
+	.align 4
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	100
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsie2.d b/binutils-2.19/ld/testsuite/ld-x86-64/tlsie2.d
new file mode 100644
index 0000000..97dcc28
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsie2.d
@@ -0,0 +1,4 @@
+#name: TLS IE->LE transition check
+#as: --64
+#ld: -melf_x86_64
+#error: .*TLS transition from R_X86_64_GOTTPOFF to R_X86_64_TPOFF32 against `foo'.*failed.*
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsie2.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlsie2.s
new file mode 100644
index 0000000..c9b9bfb
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsie2.s
@@ -0,0 +1,12 @@
+	.text
+	.globl _start
+_start:
+	leaq	foo@GOTTPOFF(%rip), %rax
+	movq	(%rax), %rax
+	.globl	foo
+	.section	.tdata,"awT",@progbits
+	.align 4
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	100
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsie3.d b/binutils-2.19/ld/testsuite/ld-x86-64/tlsie3.d
new file mode 100644
index 0000000..8c982a6
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsie3.d
@@ -0,0 +1,4 @@
+#name: TLS IE->LE transition check (%r12)
+#as: --64
+#ld: -melf_x86_64
+#error: .*TLS transition from R_X86_64_GOTTPOFF to R_X86_64_TPOFF32 against `foo'.*failed.*
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsie3.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlsie3.s
new file mode 100644
index 0000000..13faf34
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsie3.s
@@ -0,0 +1,12 @@
+	.text
+	.globl _start
+_start:
+	leaq	foo@GOTTPOFF(%rip), %r12
+	movq	(%r12), %r12
+	.globl	foo
+	.section	.tdata,"awT",@progbits
+	.align 4
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	100
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsld1.dd b/binutils-2.19/ld/testsuite/ld-x86-64/tlsld1.dd
new file mode 100644
index 0000000..c10f7ff
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsld1.dd
@@ -0,0 +1,13 @@
+#source: tlsld1.s
+#as: --64
+#ld: -melf_x86_64 tmpdir/tlsld1
+#objdump: -drw
+#target: x86_64-*-linux*
+
+.*: +file format .*
+
+Disassembly of section .text:
+
+[a-f0-9]+ <_start>:
+[ 	]*[a-f0-9]+:	66 66 66 64 48 8b 04 25 00 00 00 00 	mov    %fs:0x0,%rax
+#pass
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlsld1.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlsld1.s
new file mode 100644
index 0000000..6dcdd69
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlsld1.s
@@ -0,0 +1,12 @@
+	.text
+	.globl _start
+_start:
+	leaq    foo@TLSLD(%rip), %rdi
+	call    __tls_get_addr
+	.globl foo
+	.section	.tdata,"awT",@progbits
+	.align 4
+	.type	foo, @object
+	.size	foo, 4
+foo:
+	.long	100
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlslib.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlslib.s
new file mode 100644
index 0000000..9eccc08
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlslib.s
@@ -0,0 +1,18 @@
+	.section ".tdata", "awT", @progbits
+	.globl sG1, sG2, sG3, sG4, sG5, sG6, sG7, sG8
+sG1:	.long 513
+sG2:	.long 514
+sG3:	.long 515
+sG4:	.long 516
+sG5:	.long 517
+sG6:	.long 518
+sG7:	.long 519
+sG8:	.long 520
+
+	.text
+	/* Dummy.  */
+	.globl __tls_get_addr
+	.type   __tls_get_addr,@function
+__tls_get_addr:
+	movq	%rdi, %rax
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlspic.dd b/binutils-2.19/ld/testsuite/ld-x86-64/tlspic.dd
new file mode 100644
index 0000000..230d188
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlspic.dd
@@ -0,0 +1,230 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -drj.text
+#target: x86_64-*-*
+
+.*: +file format elf64-x86-64
+
+Disassembly of section .text:
+
+0+1000 <fn1>:
+ +1000:	55[ 	]+push   %rbp
+ +1001:	48 89 e5[ 	]+mov    %rsp,%rbp
+ +1004:	90[ 	]+nop *
+ +1005:	90[ 	]+nop *
+ +1006:	90[ 	]+nop *
+ +1007:	90[ 	]+nop *
+#  GD
+ +1008:	66 48 8d 3d 80 03 20[ 	]+lea    0x200380\(%rip\),%rdi +# 201390 <.*>
+ +100f:	00 *
+#				-> R_X86_64_DTPMOD64	sg1
+ +1010:	66 66 48 e8 [0-9a-f 	]+callq  [0-9a-f]+ <.*>
+#				-> R_X86_64_JUMP_SLOT	__tls_get_addr
+ +1017:	[0-9a-f 	]+
+ +1018:	90[ 	]+nop *
+ +1019:	90[ 	]+nop *
+ +101a:	90[ 	]+nop *
+ +101b:	90[ 	]+nop *
+#  GD -> IE because variable is referenced through IE too
+ +101c:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+ +1023:	00 00 *
+ +1025:	48 03 05 84 03 20 00[ 	]+add    0x200384\(%rip\),%rax +# 2013b0 <.*>
+#				-> R_X86_64_TPOFF64	sg2
+ +102c:	90[ 	]+nop *
+ +102d:	90[ 	]+nop *
+ +102e:	90[ 	]+nop *
+ +102f:	90[ 	]+nop *
+#  GD against local variable
+ +1030:	66 48 8d 3d 08 03 20[ 	]+lea    0x200308\(%rip\),%rdi +# 201340 <.*>
+ +1037:	00 *
+#				-> R_X86_64_DTPMOD64	[0 0x2000000000000000]
+ +1038:	66 66 48 e8 [0-9a-f 	]+callq  [0-9a-f]+ <.*>
+#				-> R_X86_64_JUMP_SLOT	__tls_get_addr
+ +103f:	[0-9a-f 	]+
+ +1040:	90[ 	]+nop *
+ +1041:	90[ 	]+nop *
+ +1042:	90[ 	]+nop *
+ +1043:	90[ 	]+nop *
+#  GD -> IE against local variable referenced through IE too
+ +1044:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+ +104b:	00 00 *
+ +104d:	48 03 05 fc 02 20 00[ 	]+add    0x2002fc\(%rip\),%rax +# 201350 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x24
+ +1054:	90[ 	]+nop *
+ +1055:	90[ 	]+nop *
+ +1056:	90[ 	]+nop *
+ +1057:	90[ 	]+nop *
+#  GD against hidden and local variable
+ +1058:	66 48 8d 3d 58 03 20[ 	]+lea    0x200358\(%rip\),%rdi +# 2013b8 <.*>
+ +105f:	00 *
+#				-> R_X86_64_DTPMOD64	[0 0x4000000000000000]
+ +1060:	66 66 48 e8 [0-9a-f 	]+callq  [0-9a-f]+ <.*>
+#				-> R_X86_64_JUMP_SLOT	__tls_get_addr
+ +1067:	[0-9a-f 	]+
+ +1068:	90[ 	]+nop *
+ +1069:	90[ 	]+nop *
+ +106a:	90[ 	]+nop *
+ +106b:	90[ 	]+nop *
+#  GD -> IE against hidden and local variable referenced through IE too
+ +106c:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+ +1073:	00 00 *
+ +1075:	48 03 05 4c 03 20 00[ 	]+add    0x20034c\(%rip\),%rax +# 2013c8 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x44
+ +107c:	90[ 	]+nop *
+ +107d:	90[ 	]+nop *
+ +107e:	90[ 	]+nop *
+ +107f:	90[ 	]+nop *
+#  GD against hidden but not local variable
+ +1080:	66 48 8d 3d e8 02 20[ 	]+lea    0x2002e8\(%rip\),%rdi +# 201370 <.*>
+ +1087:	00 *
+#				-> R_X86_64_DTPMOD64	[0 0x6000000000000000]
+ +1088:	66 66 48 e8 [0-9a-f 	]+callq  [0-9a-f]+ <.*>
+#				-> R_X86_64_JUMP_SLOT	__tls_get_addr
+ +108f:	[0-9a-f 	]+
+ +1090:	90[ 	]+nop *
+ +1091:	90[ 	]+nop *
+ +1092:	90[ 	]+nop *
+ +1093:	90[ 	]+nop *
+#  GD -> IE against hidden but not local variable referenced through IE too
+ +1094:	64 48 8b 04 25 00 00[ 	]+mov    %fs:0x0,%rax
+ +109b:	00 00 *
+ +109d:	48 03 05 dc 02 20 00[ 	]+add    0x2002dc\(%rip\),%rax +# 201380 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x64
+ +10a4:	90[ 	]+nop *
+ +10a5:	90[ 	]+nop *
+ +10a6:	90[ 	]+nop *
+ +10a7:	90[ 	]+nop *
+#  LD
+ +10a8:	48 8d 3d b1 02 20 00[ 	]+lea    0x2002b1\(%rip\),%rdi +# 201360 <.*>
+#				-> R_X86_64_DTPMOD64	[0 0x000000000000000]
+ +10af:	e8 [0-9a-f 	]+callq  [0-9a-f]+ <.*>
+#				-> R_X86_64_JUMP_SLOT	__tls_get_addr
+ +10b4:	90[ 	]+nop *
+ +10b5:	90[ 	]+nop *
+ +10b6:	48 8d 90 20 00 00 00[ 	]+lea    0x20\(%rax\),%rdx
+ +10bd:	90[ 	]+nop *
+ +10be:	90[ 	]+nop *
+ +10bf:	4c 8d 88 26 00 00 00[ 	]+lea    0x26\(%rax\),%r9
+ +10c6:	90[ 	]+nop *
+ +10c7:	90[ 	]+nop *
+ +10c8:	90[ 	]+nop *
+ +10c9:	90[ 	]+nop *
+#  LD against hidden and local variables
+ +10ca:	48 8d 3d 8f 02 20 00[ 	]+lea    0x20028f\(%rip\),%rdi +# 201360 <.*>
+#				-> R_X86_64_DTPMOD64	[0 0x000000000000000]
+ +10d1:	e8 [0-9a-f 	]+callq  [0-9a-f]+ <.*>
+#				-> R_X86_64_JUMP_SLOT	__tls_get_addr
+ +10d6:	90[ 	]+nop *
+ +10d7:	90[ 	]+nop *
+ +10d8:	48 8d 90 40 00 00 00[ 	]+lea    0x40\(%rax\),%rdx
+ +10df:	90[ 	]+nop *
+ +10e0:	90[ 	]+nop *
+ +10e1:	48 8d 88 47 00 00 00[ 	]+lea    0x47\(%rax\),%rcx
+ +10e8:	90[ 	]+nop *
+ +10e9:	90[ 	]+nop *
+ +10ea:	90[ 	]+nop *
+ +10eb:	90[ 	]+nop *
+#  LD against hidden but not local variables
+ +10ec:	48 8d 3d 6d 02 20 00[ 	]+lea    0x20026d\(%rip\),%rdi +# 201360 <.*>
+#				-> R_X86_64_DTPMOD64	[0 0x000000000000000]
+ +10f3:	e8 [0-9a-f 	]+callq  [0-9a-f]+ <.*>
+#				-> R_X86_64_JUMP_SLOT	__tls_get_addr
+ +10f8:	90[ 	]+nop *
+ +10f9:	90[ 	]+nop *
+ +10fa:	4c 8d a0 60 00 00 00[ 	]+lea    0x60\(%rax\),%r12
+ +1101:	90[ 	]+nop *
+ +1102:	90[ 	]+nop *
+ +1103:	48 8d 88 65 00 00 00[ 	]+lea    0x65\(%rax\),%rcx
+ +110a:	90[ 	]+nop *
+ +110b:	90[ 	]+nop *
+#  IE against global var
+ +110c:	64 48 8b 0c 25 00 00[ 	]+mov    %fs:0x0,%rcx
+ +1113:	00 00 *
+ +1115:	90[ 	]+nop *
+ +1116:	90[ 	]+nop *
+ +1117:	48 03 0d 92 02 20 00[ 	]+add    0x200292\(%rip\),%rcx +# 2013b0 <.*>
+#				-> R_X86_64_TPOFF64	sg2
+ +111e:	90[ 	]+nop *
+ +111f:	90[ 	]+nop *
+ +1120:	90[ 	]+nop *
+ +1121:	90[ 	]+nop *
+#  IE against local var
+ +1122:	64 4c 8b 34 25 00 00[ 	]+mov    %fs:0x0,%r14
+ +1129:	00 00 *
+ +112b:	90[ 	]+nop *
+ +112c:	90[ 	]+nop *
+ +112d:	4c 03 35 1c 02 20 00[ 	]+add    0x20021c\(%rip\),%r14 +# 201350 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x24
+ +1134:	90[ 	]+nop *
+ +1135:	90[ 	]+nop *
+ +1136:	90[ 	]+nop *
+ +1137:	90[ 	]+nop *
+#  IE against hidden and local var
+ +1138:	64 48 8b 0c 25 00 00[ 	]+mov    %fs:0x0,%rcx
+ +113f:	00 00 *
+ +1141:	90[ 	]+nop *
+ +1142:	90[ 	]+nop *
+ +1143:	48 03 0d 7e 02 20 00[ 	]+add    0x20027e\(%rip\),%rcx +# 2013c8 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x44
+ +114a:	90[ 	]+nop *
+ +114b:	90[ 	]+nop *
+ +114c:	90[ 	]+nop *
+ +114d:	90[ 	]+nop *
+#  IE against hidden but not local var
+ +114e:	64 48 8b 0c 25 00 00[ 	]+mov    %fs:0x0,%rcx
+ +1155:	00 00 *
+ +1157:	90[ 	]+nop *
+ +1158:	90[ 	]+nop *
+ +1159:	48 03 0d 20 02 20 00[ 	]+add    0x200220\(%rip\),%rcx +# 201380 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x64
+ +1160:	90[ 	]+nop *
+ +1161:	90[ 	]+nop *
+ +1162:	90[ 	]+nop *
+ +1163:	90[ 	]+nop *
+#  Direct access through %fs
+#  IE against global var
+ +1164:	48 8b 0d 1d 02 20 00[ 	]+mov    0x20021d\(%rip\),%rcx +# 201388 <.*>
+#				-> R_X86_64_TPOFF64	sg5
+ +116b:	90[ 	]+nop *
+ +116c:	90[ 	]+nop *
+ +116d:	64 48 8b 11[ 	]+mov    %fs:\(%rcx\),%rdx
+ +1171:	90[ 	]+nop *
+ +1172:	90[ 	]+nop *
+ +1173:	90[ 	]+nop *
+ +1174:	90[ 	]+nop *
+#  IE against local var
+ +1175:	4c 8b 15 dc 01 20 00[ 	]+mov    0x2001dc\(%rip\),%r10 +# 201358 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x30
+ +117c:	90[ 	]+nop *
+ +117d:	90[ 	]+nop *
+ +117e:	64 4d 8b 22[ 	]+mov    %fs:\(%r10\),%r12
+ +1182:	90[ 	]+nop *
+ +1183:	90[ 	]+nop *
+ +1184:	90[ 	]+nop *
+ +1185:	90[ 	]+nop *
+#  IE against hidden and local var
+ +1186:	48 8b 15 13 02 20 00[ 	]+mov    0x200213\(%rip\),%rdx +# 2013a0 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x50
+ +118d:	90[ 	]+nop *
+ +118e:	90[ 	]+nop *
+ +118f:	64 48 8b 12[ 	]+mov    %fs:\(%rdx\),%rdx
+ +1193:	90[ 	]+nop *
+ +1194:	90[ 	]+nop *
+ +1195:	90[ 	]+nop *
+ +1196:	90[ 	]+nop *
+#  IE against hidden but not local var
+ +1197:	48 8b 0d 0a 02 20 00[ 	]+mov    0x20020a\(%rip\),%rcx +# 2013a8 <.*>
+#				-> R_X86_64_TPOFF64	*ABS*+0x70
+ +119e:	90[ 	]+nop *
+ +119f:	90[ 	]+nop *
+ +11a0:	64 48 8b 11[ 	]+mov    %fs:\(%rcx\),%rdx
+ +11a4:	90[ 	]+nop *
+ +11a5:	90[ 	]+nop *
+ +11a6:	90[ 	]+nop *
+ +11a7:	90[ 	]+nop *
+ +11a8:	c9[ 	]+leaveq *
+ +11a9:	c3[ 	]+retq *
+ +11aa:	90[ 	]+nop *
+ +11ab:	90[ 	]+nop *
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlspic.rd b/binutils-2.19/ld/testsuite/ld-x86-64/tlspic.rd
new file mode 100644
index 0000000..f62901c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlspic.rd
@@ -0,0 +1,144 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: --64
+#ld: -shared -melf_x86_64
+#readelf: -WSsrl
+#target: x86_64-*-*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Address +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .rela.plt +.*
+ +\[[ 0-9]+\] .plt +.*
+ +\[[ 0-9]+\] .text +PROGBITS +0+1000 0+1000 0+1ac 00 +AX +0 +0 4096
+ +\[[ 0-9]+\] .tdata +PROGBITS +0+2011ac 0+11ac 0+60 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .tbss +NOBITS +0+20120c 0+120c 0+20 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+201210 0+1210 0+130 10 +WA +3 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+201340 0+1340 0+90 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+2013d0 0+13d0 0+20 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x1000
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  LOAD +0x0+ 0x0+ 0x0+ 0x[0-9a-f]+ 0x[0-9a-f]+ R E 0x200000
+  LOAD +0x0+11ac 0x0+2011ac 0x0+2011ac 0x0+244 0x0+244 RW +0x200000
+  DYNAMIC +0x0+1210 0x0+201210 0x0+201210 0x0+130 0x0+130 RW +0x8
+  TLS +0x0+11ac 0x0+2011ac 0x0+2011ac 0x0+60 0x0+80 R +0x1
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 +.hash .dynsym .dynstr .rela.dyn .rela.plt .plt .text *
+   01 +.tdata .dynamic .got .got.plt *
+   02 +.dynamic *
+   03 +.tdata .tbss *
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 14 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+[0-9a-f ]+R_X86_64_DTPMOD64 +0+
+[0-9a-f ]+R_X86_64_TPOFF64 +0+24
+[0-9a-f ]+R_X86_64_TPOFF64 +0+30
+[0-9a-f ]+R_X86_64_DTPMOD64 +0+
+[0-9a-f ]+R_X86_64_DTPMOD64 +0+
+[0-9a-f ]+R_X86_64_TPOFF64 +0+64
+[0-9a-f ]+R_X86_64_TPOFF64 +0+50
+[0-9a-f ]+R_X86_64_TPOFF64 +0+70
+[0-9a-f ]+R_X86_64_DTPMOD64 +0+
+[0-9a-f ]+R_X86_64_TPOFF64 +0+44
+[0-9a-f ]+R_X86_64_TPOFF64 +0+10 sg5 \+ 0
+[0-9a-f ]+R_X86_64_DTPMOD64 +0+ sg1 \+ 0
+[0-9a-f ]+R_X86_64_DTPOFF64 +0+ sg1 \+ 0
+[0-9a-f ]+R_X86_64_TPOFF64 +0+4 sg2 \+ 0
+
+Relocation section '.rela.plt' at offset 0x[0-9a-f]+ contains 1 entries:
+ +Offset +Info +Type +Symbol's Value  Symbol's Name \+ Addend
+[0-9a-f ]+R_X86_64_JUMP_SLOT +0+ __tls_get_addr \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE  LOCAL  DEFAULT  UND *
+.* SECTION LOCAL  DEFAULT +7 *
+.* SECTION LOCAL  DEFAULT +8 *
+.* TLS +GLOBAL DEFAULT +8 sg8
+.* TLS +GLOBAL DEFAULT +8 sg3
+.* TLS +GLOBAL DEFAULT +8 sg4
+.* TLS +GLOBAL DEFAULT +8 sg5
+.* NOTYPE  GLOBAL DEFAULT  UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +8 sg1
+.* FUNC +GLOBAL DEFAULT +7 fn1
+.* NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.* TLS +GLOBAL DEFAULT +8 sg2
+.* TLS +GLOBAL DEFAULT +8 sg6
+.* TLS +GLOBAL DEFAULT +8 sg7
+.* NOTYPE  GLOBAL DEFAULT  ABS _edata
+.* NOTYPE  GLOBAL DEFAULT  ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+.* NOTYPE  LOCAL  DEFAULT  UND *
+.* SECTION LOCAL  DEFAULT +1 *
+.* SECTION LOCAL  DEFAULT +2 *
+.* SECTION LOCAL  DEFAULT +3 *
+.* SECTION LOCAL  DEFAULT +4 *
+.* SECTION LOCAL  DEFAULT +5 *
+.* SECTION LOCAL  DEFAULT +6 *
+.* SECTION LOCAL  DEFAULT +7 *
+.* SECTION LOCAL  DEFAULT +8 *
+.* SECTION LOCAL  DEFAULT +9 *
+.* SECTION LOCAL  DEFAULT +10 *
+.* SECTION LOCAL  DEFAULT +11 *
+.* SECTION LOCAL  DEFAULT +12 *
+.* TLS +LOCAL  DEFAULT +8 sl1
+.* TLS +LOCAL  DEFAULT +8 sl2
+.* TLS +LOCAL  DEFAULT +8 sl3
+.* TLS +LOCAL  DEFAULT +8 sl4
+.* TLS +LOCAL  DEFAULT +8 sl5
+.* TLS +LOCAL  DEFAULT +8 sl6
+.* TLS +LOCAL  DEFAULT +8 sl7
+.* TLS +LOCAL  DEFAULT +8 sl8
+.* TLS +LOCAL  HIDDEN +9 sH1
+.* OBJECT +LOCAL +HIDDEN +ABS _DYNAMIC
+.* TLS +LOCAL  HIDDEN +8 sh3
+.* TLS +LOCAL  HIDDEN +9 sH2
+.* TLS +LOCAL  HIDDEN +9 sH7
+.* TLS +LOCAL  HIDDEN +8 sh7
+.* TLS +LOCAL  HIDDEN +8 sh8
+.* TLS +LOCAL  HIDDEN +9 sH4
+.* TLS +LOCAL  HIDDEN +8 sh4
+.* TLS +LOCAL  HIDDEN +9 sH3
+.* TLS +LOCAL  HIDDEN +8 sh5
+.* TLS +LOCAL  HIDDEN +9 sH5
+.* TLS +LOCAL  HIDDEN +9 sH6
+.* TLS +LOCAL  HIDDEN +9 sH8
+.* TLS +LOCAL  HIDDEN +8 sh1
+.* OBJECT  LOCAL  HIDDEN  ABS _GLOBAL_OFFSET_TABLE_
+.* TLS +LOCAL  HIDDEN +8 sh2
+.* TLS +LOCAL  HIDDEN +8 sh6
+.* TLS +GLOBAL DEFAULT +8 sg8
+.* TLS +GLOBAL DEFAULT +8 sg3
+.* TLS +GLOBAL DEFAULT +8 sg4
+.* TLS +GLOBAL DEFAULT +8 sg5
+.* NOTYPE  GLOBAL DEFAULT  UND __tls_get_addr
+.* TLS +GLOBAL DEFAULT +8 sg1
+.* FUNC +GLOBAL DEFAULT +7 fn1
+.* NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+.* TLS +GLOBAL DEFAULT +8 sg2
+.* TLS +GLOBAL DEFAULT +8 sg6
+.* TLS +GLOBAL DEFAULT +8 sg7
+.* NOTYPE  GLOBAL DEFAULT  ABS _edata
+.* NOTYPE  GLOBAL DEFAULT  ABS _end
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlspic.sd b/binutils-2.19/ld/testsuite/ld-x86-64/tlspic.sd
new file mode 100644
index 0000000..666c774
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlspic.sd
@@ -0,0 +1,19 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -sj.got
+#target: x86_64-*-*
+
+.*: +file format elf64-x86-64
+
+Contents of section .got:
+ 201340 00000000 00000000 20000000 00000000  .*
+ 201350 00000000 00000000 00000000 00000000  .*
+ 201360 00000000 00000000 00000000 00000000  .*
+ 201370 00000000 00000000 60000000 00000000  .*
+ 201380 00000000 00000000 00000000 00000000  .*
+ 201390 00000000 00000000 00000000 00000000  .*
+ 2013a0 00000000 00000000 00000000 00000000  .*
+ 2013b0 00000000 00000000 00000000 00000000  .*
+ 2013c0 40000000 00000000 00000000 00000000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlspic.td b/binutils-2.19/ld/testsuite/ld-x86-64/tlspic.td
new file mode 100644
index 0000000..67eb4f2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlspic.td
@@ -0,0 +1,16 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as: --64
+#ld: -shared -melf_x86_64
+#objdump: -sj.tdata
+#target: x86_64-*-*
+
+.*: +file format elf64-x86-64
+
+Contents of section .tdata:
+ 2011ac 11000000 12000000 13000000 14000000  .*
+ 2011bc 15000000 16000000 17000000 18000000  .*
+ 2011cc 41000000 42000000 43000000 44000000  .*
+ 2011dc 45000000 46000000 47000000 48000000  .*
+ 2011ec 01010000 02010000 03010000 04010000  .*
+ 2011fc 05010000 06010000 07010000 08010000  .*
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlspic1.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlspic1.s
new file mode 100644
index 0000000..5e26f26
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlspic1.s
@@ -0,0 +1,187 @@
+	/* Force .data aligned to 4K, so .got very likely gets at 0x102190
+	   (0x60 bytes .tdata and 0x130 bytes .dynamic)  */
+        .data
+        .balign 4096
+	.section ".tdata", "awT", @progbits
+	.globl sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.globl sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+sg1:	.long 17
+sg2:	.long 18
+sg3:	.long 19
+sg4:	.long 20
+sg5:	.long 21
+sg6:	.long 22
+sg7:	.long 23
+sg8:	.long 24
+sl1:	.long 65
+sl2:	.long 66
+sl3:	.long 67
+sl4:	.long 68
+sl5:	.long 69
+sl6:	.long 70
+sl7:	.long 71
+sl8:	.long 72
+sh1:	.long 257
+sh2:	.long 258
+sh3:	.long 259
+sh4:	.long 260
+sh5:	.long 261
+sh6:	.long 262
+sh7:	.long 263
+sh8:	.long 264
+	/* Force .text aligned to 4K, so it very likely gets at 0x1000.  */
+	.text
+	.balign	4096
+	.globl	fn1
+	.type	fn1,@function
+fn1:
+	pushq	%rbp
+	movq	%rsp, %rbp
+	nop;nop;nop;nop
+
+	/* GD */
+	.byte	0x66
+	leaq	sg1@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE because variable is referenced through IE too */
+	.byte	0x66
+	leaq	sg2@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD against local variable */
+	.byte	0x66
+	leaq	sl1@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE against local variable referenced through IE too */
+	.byte	0x66
+	leaq	sl2@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD against hidden and local variable */
+	.byte	0x66
+	leaq	sh1@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden and local variable referenced through
+	   IE too */
+	.byte	0x66
+	leaq	sh2@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD against hidden but not local variable */
+	.byte	0x66
+	leaq	sH1@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* GD -> IE against hidden but not local variable referenced through
+	   IE too */
+	.byte	0x66
+	leaq	sH2@tlsgd(%rip), %rdi
+	.word	0x6666
+	rex64
+	call	__tls_get_addr@plt
+	nop;nop;nop;nop
+
+	/* LD */
+	leaq	sl1@tlsld(%rip), %rdi
+	call	__tls_get_addr@plt
+	nop;nop
+	leaq	sl1@dtpoff(%rax), %rdx
+	nop;nop
+	leaq	2+sl2@dtpoff(%rax), %r9
+	nop;nop;nop;nop
+
+	/* LD against hidden and local variables */
+	leaq	sh1@tlsld(%rip), %rdi
+	call	__tls_get_addr@plt
+	nop;nop
+	leaq	sh1@dtpoff(%rax), %rdx
+	nop;nop
+	leaq	sh2@dtpoff+3(%rax), %rcx
+	nop;nop;nop;nop
+
+	/* LD against hidden but not local variables */
+	leaq	sH1@tlsld(%rip), %rdi
+	call	__tls_get_addr@plt
+	nop;nop
+	leaq	sH1@dtpoff(%rax), %r12
+	nop;nop
+	leaq	sH2@dtpoff+1(%rax), %rcx
+	nop;nop
+
+	/* IE against global var  */
+	movq	%fs:0, %rcx
+	nop;nop
+	addq	sg2@gottpoff(%rip), %rcx
+	nop;nop;nop;nop
+
+	/* IE against local var  */
+	movq	%fs:0, %r14
+	nop;nop
+	addq	sl2@gottpoff(%rip), %r14
+	nop;nop;nop;nop
+
+	/* IE against hidden and local var  */
+	movq	%fs:0, %rcx
+	nop;nop
+	addq	sh2@gottpoff(%rip), %rcx
+	nop;nop;nop;nop
+
+	/* IE against hidden but not local var  */
+	movq	%fs:0, %rcx
+	nop;nop
+	addq	sH2@gottpoff(%rip), %rcx
+	nop;nop;nop;nop
+
+	/* Direct access through %fs  */
+
+	/* IE against global var  */
+	movq	sg5@gottpoff(%rip), %rcx
+	nop;nop
+	movq	%fs:(%rcx), %rdx
+	nop;nop;nop;nop
+
+	/* IE against local var  */
+	movq	sl5@gottpoff(%rip), %r10
+	nop;nop
+	movq	%fs:(%r10), %r12
+	nop;nop;nop;nop
+
+	/* IE against hidden and local var  */
+	movq	sh5@gottpoff(%rip), %rdx
+	nop;nop
+	movq	%fs:(%rdx), %rdx
+	nop;nop;nop;nop
+
+	/* IE against hidden but not local var  */
+	movq	sH5@gottpoff(%rip), %rcx
+	nop;nop
+	movq	%fs:(%rcx), %rdx
+	nop;nop;nop;nop
+
+	leave
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/tlspic2.s b/binutils-2.19/ld/testsuite/ld-x86-64/tlspic2.s
new file mode 100644
index 0000000..5513f9b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/tlspic2.s
@@ -0,0 +1,11 @@
+	.section ".tbss", "awT", @nobits
+	.globl sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+	.hidden sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+sH1:	.space 4
+sH2:	.space 4
+sH3:	.space 4
+sH4:	.space 4
+sH5:	.space 4
+sH6:	.space 4
+sH7:	.space 4
+sH8:	.space 4
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/undefined.s b/binutils-2.19/ld/testsuite/ld-x86-64/undefined.s
new file mode 100644
index 0000000..60c1c94
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/undefined.s
@@ -0,0 +1,154 @@
+	.file	"undefined.c"
+	.section	.debug_abbrev,"",@progbits
+.Ldebug_abbrev0:
+	.section	.debug_info,"",@progbits
+.Ldebug_info0:
+	.section	.debug_line,"",@progbits
+.Ldebug_line0:
+	.text
+.Ltext0:
+	.p2align 4,,15
+.globl function
+	.type	function, @function
+function:
+.LFB2:
+	.file 1 "undefined.c"
+	.loc 1 8 0
+	.loc 1 9 0
+	xorl	%eax, %eax
+	jmp	this_function_is_not_defined
+.LFE2:
+	.size	function, .-function
+	.section	.debug_frame,"",@progbits
+.Lframe0:
+	.long	.LECIE0-.LSCIE0
+.LSCIE0:
+	.long	0xffffffff
+	.byte	0x1
+	.string	""
+	.uleb128 0x1
+	.sleb128 -8
+	.byte	0x10
+	.byte	0xc
+	.uleb128 0x7
+	.uleb128 0x8
+	.byte	0x90
+	.uleb128 0x1
+	.align 8
+.LECIE0:
+.LSFDE0:
+	.long	.LEFDE0-.LASFDE0
+.LASFDE0:
+	.long	.Lframe0
+	.quad	.LFB2
+	.quad	.LFE2-.LFB2
+	.align 8
+.LEFDE0:
+	.text
+.Letext0:
+	.section	.debug_info
+	.long	0x4c
+	.value	0x2
+	.long	.Ldebug_abbrev0
+	.byte	0x8
+	.uleb128 0x1
+	.long	.Ldebug_line0
+	.quad	.Letext0
+	.quad	.Ltext0
+	.long	.LASF0
+	.byte	0x1
+	.long	.LASF1
+	.uleb128 0x2
+	.byte	0x1
+	.long	.LASF2
+	.byte	0x1
+	.byte	0x8
+	.long	0x48
+	.quad	.LFB2
+	.quad	.LFE2
+	.byte	0x2
+	.byte	0x77
+	.sleb128 8
+	.uleb128 0x3
+	.string	"int"
+	.byte	0x4
+	.byte	0x5
+	.byte	0x0
+	.section	.debug_abbrev
+	.uleb128 0x1
+	.uleb128 0x11
+	.byte	0x1
+	.uleb128 0x10
+	.uleb128 0x6
+	.uleb128 0x12
+	.uleb128 0x1
+	.uleb128 0x11
+	.uleb128 0x1
+	.uleb128 0x25
+	.uleb128 0xe
+	.uleb128 0x13
+	.uleb128 0xb
+	.uleb128 0x3
+	.uleb128 0xe
+	.byte	0x0
+	.byte	0x0
+	.uleb128 0x2
+	.uleb128 0x2e
+	.byte	0x0
+	.uleb128 0x3f
+	.uleb128 0xc
+	.uleb128 0x3
+	.uleb128 0xe
+	.uleb128 0x3a
+	.uleb128 0xb
+	.uleb128 0x3b
+	.uleb128 0xb
+	.uleb128 0x49
+	.uleb128 0x13
+	.uleb128 0x11
+	.uleb128 0x1
+	.uleb128 0x12
+	.uleb128 0x1
+	.uleb128 0x40
+	.uleb128 0xa
+	.byte	0x0
+	.byte	0x0
+	.uleb128 0x3
+	.uleb128 0x24
+	.byte	0x0
+	.uleb128 0x3
+	.uleb128 0x8
+	.uleb128 0xb
+	.uleb128 0xb
+	.uleb128 0x3e
+	.uleb128 0xb
+	.byte	0x0
+	.byte	0x0
+	.byte	0x0
+	.section	.debug_pubnames,"",@progbits
+	.long	0x1b
+	.value	0x2
+	.long	.Ldebug_info0
+	.long	0x50
+	.long	0x29
+	.string	"function"
+	.long	0x0
+	.section	.debug_aranges,"",@progbits
+	.long	0x2c
+	.value	0x2
+	.long	.Ldebug_info0
+	.byte	0x8
+	.byte	0x0
+	.value	0x0
+	.value	0x0
+	.quad	.Ltext0
+	.quad	.Letext0-.Ltext0
+	.quad	0x0
+	.quad	0x0
+	.section	.debug_str,"MS",@progbits,1
+.LASF0:
+	.string	"GNU C 3.4.6"
+.LASF1:
+	.string	"undefined.c"
+.LASF2:
+	.string	"function"
diff --git a/binutils-2.19/ld/testsuite/ld-x86-64/x86-64.exp b/binutils-2.19/ld/testsuite/ld-x86-64/x86-64.exp
new file mode 100644
index 0000000..eeeea43
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-x86-64/x86-64.exp
@@ -0,0 +1,94 @@
+# Expect script for ld-x86_64 tests
+#   Copyright (C) 2002, 2005, 2006, 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Test x86_64 linking; all types of relocs.  This tests the assembler and
+# tools like objdump as well as the linker.
+
+if { !([istarget "x86_64-*-elf*"]
+       || [istarget "x86_64-*-linux*"]) } {
+    return
+}
+
+# List contains test-items with 3 items followed by 2 lists:
+# 0:name 1:ld options 2:assembler options
+# 3:filenames of assembler files 4: action and options. 5: name of output file
+
+# Actions:
+# objdump: Apply objdump options on result.  Compare with regex (last arg).
+# nm: Apply nm options on result.  Compare with regex (last arg).
+# readelf: Apply readelf options on result.  Compare with regex (last arg).
+
+set x86_64tests {
+    {"TLS -fpic -shared transitions" "-shared -melf_x86_64"
+     "--64" {tlspic1.s tlspic2.s}
+     {{readelf -WSsrl tlspic.rd} {objdump -drj.text tlspic.dd}
+      {objdump -sj.got tlspic.sd} {objdump -sj.tdata tlspic.td}}
+      "libtlspic.so"}
+    {"TLS descriptor -fpic -shared transitions" "-shared -melf_x86_64"
+     "--64" {tlsdesc.s tlspic2.s}
+     {{readelf -WSsrld tlsdesc.rd} {objdump -drj.text tlsdesc.dd}
+      {objdump "-s -j.got -j.got.plt" tlsdesc.sd} {objdump -sj.tdata tlsdesc.td}
+      {objdump -drj.plt tlsdesc.pd}} "libtlsdesc.so"}
+    {"Helper shared library" "-shared -melf_x86_64"
+     "--64" {tlslib.s} {} "libtlslib.so"}
+    {"TLS -fpic and -fno-pic exec transitions"
+     "-melf_x86_64 tmpdir/libtlslib.so" "--64" {tlsbinpic.s tlsbin.s}
+     {{readelf -WSsrl tlsbin.rd} {objdump -drj.text tlsbin.dd}
+      {objdump -sj.got tlsbin.sd} {objdump -sj.tdata tlsbin.td}}
+      "tlsbin"}
+    {"TLS descriptor -fpic and -fno-pic exec transitions"
+     "-melf_x86_64 tmpdir/libtlslib.so" "--64" {tlsbindesc.s tlsbin.s}
+     {{readelf -WSsrl tlsbindesc.rd} {objdump -drj.text tlsbindesc.dd}
+      {objdump -sj.got tlsbindesc.sd} {objdump -sj.tdata tlsbindesc.td}}
+      "tlsbindesc"}
+    {"TLS with global dynamic and descriptors"
+	"-shared -melf_x86_64" "--64" {tlsgdesc.s}
+     {{readelf -WSsrl tlsgdesc.rd} {objdump -drj.text tlsgdesc.dd}}
+      "libtlsgdesc.so"}
+    {"TLS in debug sections" "-melf_x86_64"
+     "--64" {tlsg.s}
+     {{objdump -sj.debug_foobar tlsg.sd}} "tlsg"}
+    {"TLS GD->LE transition" "-melf_x86_64"
+     "--64" {tlsgd1.s}
+     {{objdump -dwr tlsgd1.dd}} "tlsgd1"}
+    {"TLS LD->LE transition" "-melf_x86_64"
+     "--64" {tlsld1.s}
+     {{objdump -dwr tlsld1.dd}} "tlsld1"}
+    {"TLS IE->LE transition" "-melf_x86_64"
+     "--64" {tlsie1.s}
+     {{objdump -dwr tlsie1.dd}} "tlsie1"}
+}
+
+run_ld_link_tests $x86_64tests
+
+run_dump_test "abs"
+run_dump_test "pcrel8"
+run_dump_test "pcrel16"
+run_dump_test "tlsgd2"
+run_dump_test "tlsgd3"
+run_dump_test "tlsie2"
+run_dump_test "tlsie3"
+run_dump_test "hidden1"
+run_dump_test "hidden2"
+run_dump_test "hidden3"
+run_dump_test "protected1"
+run_dump_test "protected2"
+run_dump_test "protected3"
diff --git a/binutils-2.19/ld/testsuite/ld-xc16x/absrel.d b/binutils-2.19/ld/testsuite/ld-xc16x/absrel.d
new file mode 100644
index 0000000..a6941c2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xc16x/absrel.d
@@ -0,0 +1,28 @@
+
+.*:     file format elf32-xc16x
+
+Disassembly of section .text:
+
+00000400 <_start>:
+ 400:	e0 f5       	mov r5,#0xf
+ 402:	e0 f6       	mov r6,#0xf
+
+00000404 <.12>:
+ 404:	f2 f5 1c 04 	mov r5,0x41c
+ 408:	e0 d6       	mov r6,#0xd
+ 40a:	f2 f7 1c 04 	mov r7,0x41c
+ 40e:	e0 d8       	mov r8,#0xd
+
+00000410 <.13>:
+ 410:	f2 f5 1c 04 	mov r5,0x41c
+ 414:	e0 f6       	mov r6,#0xf
+ 416:	f2 f7 1c 04 	mov r7,0x41c
+ 41a:	e0 f8       	mov r8,#0xf
+
+0000041c <.end>:
+.*:	ca 09 04 04 	calla- cc_nusr0,404 <.12>
+.*:	ca 19 04 04 	calla- cc_nusr1,404 <.12>
+.*:	ca 29 04 04 	calla- cc_usr0,404 <.12>
+.*:	ea 09 04 04 	jmpa- cc_nusr0,404 <.12>
+.*:	ea 19 04 04 	jmpa- cc_nusr1,404 <.12>
+.*:	ea 29 04 04 	jmpa- cc_usr0,404 <.12>
diff --git a/binutils-2.19/ld/testsuite/ld-xc16x/absrel.s b/binutils-2.19/ld/testsuite/ld-xc16x/absrel.s
new file mode 100644
index 0000000..3bfe70e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xc16x/absrel.s
@@ -0,0 +1,31 @@
+	.global _start
+_start:
+	mov r5,#0xf
+	mov r6,#0xf
+
+.12:
+	mov r5,.end
+	mov r6,#0xd
+	mov r7,.end
+	mov r8,#0xd
+.13:
+	mov r5,.end
+	mov r6,#0xf
+	mov r7,.end
+	mov r8,#0xf
+.end:
+	;calla cc_UC,.13
+	;calla cc_usr1,.12
+
+	;calla+ cc_UGT,.12
+	calla- cc_nusr0,.12
+	calla- cc_nusr1,.12
+	calla- cc_usr0,.12
+
+	;jmpa cc_UGT,.end
+	;jmpa cc_nusr0,.end
+
+	;jmpa+ cc_UGT,.12
+	jmpa- cc_nusr0,.12
+	jmpa- cc_nusr1,.12
+	jmpa- cc_usr0,.12
diff --git a/binutils-2.19/ld/testsuite/ld-xc16x/offset.d b/binutils-2.19/ld/testsuite/ld-xc16x/offset.d
new file mode 100644
index 0000000..a879c44
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xc16x/offset.d
@@ -0,0 +1,18 @@
+
+.*:     file format elf32-xc16x
+
+Disassembly of section .text:
+
+00000400 <_start>:
+ 400:	e0 f8       	mov r8,#0xf
+ 402:	fa 00 08 04 	jmps #seg:0x0,#sof:0x408
+ 406:	e0 f9       	mov r9,#0xf
+
+00000408 <.12>:
+ 408:	e0 f5       	mov r5,#0xf
+ 40a:	e0 f7       	mov r7,#0xf
+ 40c:	da 00 10 04 	calls #seg:0x0,#sof:0x410
+
+00000410 <.13>:
+ 410:	e0 f6       	mov r6,#0xf
+ 412:	e0 f8       	mov r8,#0xf
diff --git a/binutils-2.19/ld/testsuite/ld-xc16x/offset.s b/binutils-2.19/ld/testsuite/ld-xc16x/offset.s
new file mode 100644
index 0000000..b3aad19
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xc16x/offset.s
@@ -0,0 +1,13 @@
+	.global _start
+_start:
+	mov r8,#0xf
+	jmps #seg:.12,#sof:.12
+	mov r9,#0xf
+.12:
+	mov r5,#0xf
+	mov r7,#0xf
+	calls #seg:.13,#sof:.13
+.13:
+	mov r6,#0xf
+	mov r8,#0xf
+	
\ No newline at end of file
diff --git a/binutils-2.19/ld/testsuite/ld-xc16x/pcreloc.d b/binutils-2.19/ld/testsuite/ld-xc16x/pcreloc.d
new file mode 100644
index 0000000..8f363b5
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xc16x/pcreloc.d
@@ -0,0 +1,34 @@
+
+.*:     file format elf32-xc16x
+
+Disassembly of section .text:
+
+00000400 <_start>:
+ 400:	e0 f5       	mov r5,#0xf
+ 402:	e0 f6       	mov r6,#0xf
+ 404:	e0 f7       	mov r7,#0xf
+ 406:	e0 f8       	mov r8,#0xf
+ 408:	e0 f9       	mov r9,#0xf
+ 40a:	e0 fa       	mov r10,#0xf
+ 40c:	e0 fb       	mov r11,#0xf
+ 40e:	e0 fc       	mov r12,#0xf
+
+00000410 <.12>:
+ 410:	2d 07       	jmpr cc_Z,7
+ 412:	3d fe       	jmpr cc_NZ,254
+ 414:	8d fd       	jmpr cc_ULT,253
+ 416:	8d 45       	jmpr cc_ULT,69
+ 418:	9d 06       	jmpr cc_UGE,6
+ 41a:	0d 05       	jmpr cc_UC,5
+ 41c:	2d 04       	jmpr cc_Z,4
+ 41e:	3d 03       	jmpr cc_NZ,3
+
+00000420 <.13>:
+ 420:	fd 02       	jmpr cc_ULE,2
+ 422:	dd 01       	jmpr cc_SGE,1
+ 424:	bd 00       	jmpr cc_SLE,0
+
+00000426 <.end>:
+ 426:	1d f4       	jmpr cc_NET,244
+ 428:	bb fe       	callr 254
+ 42a:	bb fd       	callr 253
diff --git a/binutils-2.19/ld/testsuite/ld-xc16x/pcreloc.s b/binutils-2.19/ld/testsuite/ld-xc16x/pcreloc.s
new file mode 100644
index 0000000..ed77101
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xc16x/pcreloc.s
@@ -0,0 +1,27 @@
+	.global _start
+_start:
+	mov r5,#0xf
+	mov r6,#0xf
+	mov r7,#0xf
+	mov r8,#0xf
+	mov r9,#0xf
+	mov r10,#0xf
+	mov r11,#0xf
+	mov r12,#0xf
+.12:
+	jmpr cc_Z,.13
+	jmpr cc_NZ,.12
+	jmpr cc_C,.12
+	jmpr cc_C,0x45
+	jmpr cc_NC,.end
+	jmpr cc_UC,.end
+	jmpr cc_EQ,.end
+	jmpr cc_NE,.end
+.13:
+	jmpr cc_ULE,.end
+	jmpr cc_SGE,.end
+	jmpr cc_SLE,.end
+.end:
+	jmpr cc_NET,.12
+	callr .end
+	callr .end
diff --git a/binutils-2.19/ld/testsuite/ld-xc16x/pcrelocl.d b/binutils-2.19/ld/testsuite/ld-xc16x/pcrelocl.d
new file mode 100644
index 0000000..48d9c82
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xc16x/pcrelocl.d
@@ -0,0 +1,34 @@
+
+.*:     file format elf32-xc16x
+
+Disassembly of section .text:
+
+00c00300 <_start>:
+  c00300:	e0 f5       	mov r5,#0xf
+  c00302:	e0 f6       	mov r6,#0xf
+  c00304:	e0 f7       	mov r7,#0xf
+  c00306:	e0 f8       	mov r8,#0xf
+  c00308:	e0 f9       	mov r9,#0xf
+  c0030a:	e0 fa       	mov r10,#0xf
+  c0030c:	e0 fb       	mov r11,#0xf
+  c0030e:	e0 fc       	mov r12,#0xf
+
+00c00310 <.12>:
+  c00310:	2d 07       	jmpr cc_Z,7
+  c00312:	3d fe       	jmpr cc_NZ,254
+  c00314:	8d fd       	jmpr cc_ULT,253
+  c00316:	8d 45       	jmpr cc_ULT,69
+  c00318:	9d 06       	jmpr cc_UGE,6
+  c0031a:	0d 05       	jmpr cc_UC,5
+  c0031c:	2d 04       	jmpr cc_Z,4
+  c0031e:	3d 03       	jmpr cc_NZ,3
+
+00c00320 <.13>:
+  c00320:	fd 02       	jmpr cc_ULE,2
+  c00322:	dd 01       	jmpr cc_SGE,1
+  c00324:	bd 00       	jmpr cc_SLE,0
+
+00c00326 <.end>:
+  c00326:	1d f4       	jmpr cc_NET,244
+  c00328:	bb fe       	callr 254
+  c0032a:	bb fd       	callr 253
diff --git a/binutils-2.19/ld/testsuite/ld-xc16x/xc16x.exp b/binutils-2.19/ld/testsuite/ld-xc16x/xc16x.exp
new file mode 100644
index 0000000..58ef977
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xc16x/xc16x.exp
@@ -0,0 +1,68 @@
+# Expect script for ld-xstormy16 tests
+#   Copyright (C) 2003, 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Test xc16x linking of pc-relative relocs.  This tests the assembler and
+# tools like objdump as well as the linker.
+
+if {!([istarget "xc16x*-*-*"]) } {
+    return
+}
+
+# Set up a list as described in ld-lib.exp
+
+set xc16x_tests {
+    {   
+	"xc16x pc-relative relocs linker test"
+	""
+	""
+	{ "pcreloc.s" }
+	{ {objdump -Dz pcreloc.d} } 	
+	"pcreloc"
+    }
+}
+
+set xc16xabs_tests {
+    {   
+	"xc16x absolute relative address linker test"
+	""
+	""
+	{ "absrel.s" }
+	{ {objdump -Dz absrel.d} } 	
+	"absrel"
+    }
+}
+
+set xc16xoffset_tests {
+    {   
+	"xc16x offset linker test"
+	""
+	""
+	{ "offset.s" }
+	{ {objdump -Dz offset.d} } 	
+	"offset"
+    }
+}
+
+ run_ld_link_tests $xc16x_tests
+ run_ld_link_tests $xc16xabs_tests
+ run_ld_link_tests $xc16xoffset_tests
+
+
diff --git a/binutils-2.19/ld/testsuite/ld-xstormy16/external.s b/binutils-2.19/ld/testsuite/ld-xstormy16/external.s
new file mode 100644
index 0000000..2907e9e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xstormy16/external.s
@@ -0,0 +1,5 @@
+	.text
+	.global external
+external:
+	nop
+	
\ No newline at end of file
diff --git a/binutils-2.19/ld/testsuite/ld-xstormy16/pcrel.d b/binutils-2.19/ld/testsuite/ld-xstormy16/pcrel.d
new file mode 100644
index 0000000..4eac7b2
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xstormy16/pcrel.d
@@ -0,0 +1,33 @@
+
+.*:     file format elf32-xstormy16
+
+Disassembly of section .text:
+
+00008000 <_start>:
+    8000:	00 79 46 80 	mov.w 0x0,#0x8046
+    8004:	00 79 42 80 	mov.w 0x0,#0x8042
+    8008:	00 79 44 80 	mov.w 0x0,#0x8044
+    800c:	00 79 2c 00 	mov.w 0x0,#0x2c
+    8010:	00 79 32 00 	mov.w 0x0,#0x32
+    8014:	00 79 30 00 	mov.w 0x0,#0x30
+    8018:	2c d3       	bc 0x8046
+    801a:	26 d3       	bc 0x8042
+    801c:	26 d3       	bc 0x8044
+    801e:	24 c3 00 00 	bc Rx,#0x0,0x8046
+    8022:	1c c3 00 00 	bc Rx,#0x0,0x8042
+    8026:	1a c3 00 00 	bc Rx,#0x0,0x8044
+    802a:	00 20 18 30 	bc r0,#0x0,0x8046
+    802e:	00 20 10 30 	bc r0,#0x0,0x8042
+    8032:	00 20 0e 30 	bc r0,#0x0,0x8044
+    8036:	10 0d 0c 30 	bc r0,r1,0x8046
+    803a:	10 0d 04 30 	bc r0,r1,0x8042
+    803e:	10 0d 02 30 	bc r0,r1,0x8044
+
+00008042 <global>:
+    8042:	00 00       	nop
+
+00008044 <local>:
+    8044:	00 00       	nop
+
+00008046 <external>:
+    8046:	00 00       	nop
diff --git a/binutils-2.19/ld/testsuite/ld-xstormy16/pcrel.s b/binutils-2.19/ld/testsuite/ld-xstormy16/pcrel.s
new file mode 100644
index 0000000..6128e51
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xstormy16/pcrel.s
@@ -0,0 +1,31 @@
+	.text
+	.global _start
+_start:	
+	mov 0, # external
+	mov 0, # global
+	mov 0, # local
+	
+	mov 0, # external - .
+	mov 0, # global - .
+	mov 0, # local - .
+
+	bc            external
+	bc            global
+	bc            local
+	
+	bc rx, #0,    external
+	bc rx, #0,    global
+	bc rx, #0,    local
+
+	bc r0, #0,    external
+	bc r0, #0,    global
+	bc r0, #0,    local
+	
+	bc  r0, r1,   external
+	bc  r0, r1,   global
+	bc  r0, r1,   local
+	.global global
+global:
+	nop
+local:
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-xstormy16/xstormy16.exp b/binutils-2.19/ld/testsuite/ld-xstormy16/xstormy16.exp
new file mode 100644
index 0000000..5229493
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xstormy16/xstormy16.exp
@@ -0,0 +1,41 @@
+# Expect script for ld-xstormy16 tests
+#   Copyright (C) 2003, 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Test xstormy16 linking of pc-relative relocs.  This tests the assembler and
+# tools like objdump as well as the linker.
+
+if {!([istarget "xstormy16*-*-*"]) } {
+    return
+}
+
+# Set up a list as described in ld-lib.exp
+
+set xstormy16_tests {
+    {   "xstormy16 pc-relative relocs linker test"
+	""
+	""
+	{ "pcrel.s" "external.s" }
+	{ {objdump -Dz pcrel.d} }
+	"pcrel"
+    }
+}
+
+run_ld_link_tests $xstormy16_tests
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/coalesce.exp b/binutils-2.19/ld/testsuite/ld-xtensa/coalesce.exp
new file mode 100644
index 0000000..c54e276
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/coalesce.exp
@@ -0,0 +1,100 @@
+# Test literal coaslescing for Xtensa targets.
+# By David Heine, Tensilica, Inc.
+#   Copyright 2002, 2003, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+if ![istarget "xtensa*-*-*"] {
+    return
+}
+
+set testname "COALESCE"
+
+set OBJDUMPFLAGS "-dr"
+
+#
+# default_ld_objdump
+#	run objdump on a file
+#
+proc default_ld_objdump { objdump object outputfile } {
+    global OBJDUMPFLAGS
+    global objdump_output
+    global host_triplet
+
+    if {[which $objdump] == 0} then {
+	perror "$objdump does not exist"
+	return 0
+    }
+
+    if ![info exists OBJDUMPFLAGS] { set OBJDUMPFLAGS "" }
+
+    verbose -log "$objdump $OBJDUMPFLAGS $object >$outputfile"
+
+    catch "exec $objdump $OBJDUMPFLAGS $object >$outputfile" exec_output
+    set exec_output [prune_warnings $exec_output]
+    if [string match "" $exec_output] then {
+	return 1
+    } else {
+	verbose -log "$exec_output"
+	perror "$object: objdump failed"
+	return 0
+    }
+}
+
+
+if ![ld_assemble $as $srcdir/$subdir/coalesce1.s tmpdir/coalesce1.o] {
+    unresolved $testname
+    return
+}
+if ![ld_assemble $as $srcdir/$subdir/coalesce2.s tmpdir/coalesce2.o] {
+    unresolved $testname
+    return
+}
+
+set object "tmpdir/coalesce"
+set outputfile "$object.txt"
+
+if ![ld_simple_link $ld $object "-T $srcdir/$subdir/coalesce.t tmpdir/coalesce1.o tmpdir/coalesce2.o"] {
+    verbose -log "failure in ld"
+    fail $testname
+    return
+} 
+
+if ![default_ld_objdump $objdump $object $outputfile ] {
+    verbose -log "failure in objdump"
+    fail $testname
+    return
+} 
+
+set file [open $outputfile r]
+set found 0
+
+while { [gets $file line] != -1 } {
+    #	verbose "$line" 2
+    if [regexp "^0000000c <main>:" $line] {
+	set found 1
+    }
+}
+close $file
+if  $found  {
+   pass $testname
+} else {
+   fail $testname
+}
+
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/coalesce.t b/binutils-2.19/ld/testsuite/ld-xtensa/coalesce.t
new file mode 100644
index 0000000..7bff69f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/coalesce.t
@@ -0,0 +1,6 @@
+SECTIONS
+{
+  .text 0x00000000 : { 
+    *(.literal .text)
+  }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/coalesce1.s b/binutils-2.19/ld/testsuite/ld-xtensa/coalesce1.s
new file mode 100644
index 0000000..4374463
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/coalesce1.s
@@ -0,0 +1,15 @@
+	.global foo
+	.data
+	.global g_name
+	.align 4
+g_name:
+	.word 0xffffffff
+	.text
+	.global main
+	.align 4
+main:
+	entry a5,16
+	movi a5,20000
+	movi a6,g_name
+	call8 foo
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/coalesce2.s b/binutils-2.19/ld/testsuite/ld-xtensa/coalesce2.s
new file mode 100644
index 0000000..7c9a83d
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/coalesce2.s
@@ -0,0 +1,10 @@
+	.text
+	.global foo
+	.global g_name
+	.align 4
+foo:
+	entry a5,16
+	movi a5,20000
+	movi a6,g_name
+	movi a7,50000
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/lcall.exp b/binutils-2.19/ld/testsuite/ld-xtensa/lcall.exp
new file mode 100644
index 0000000..6ab19b8
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/lcall.exp
@@ -0,0 +1,114 @@
+# Test Xtensa longcall optimization.
+# By David Heine, Tensilica, Inc.
+#   Copyright 2002, 2003, 2007
+#   Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+if ![istarget "xtensa*-*-*"] {
+    return
+}
+
+set testname "LCALL"
+
+set OBJDUMPFLAGS "-dr"
+
+#
+# default_ld_objdump
+#	run objdump on a file
+#
+proc default_ld_objdump { objdump object outputfile } {
+    global OBJDUMPFLAGS
+    global objdump_output
+    global host_triplet
+
+    if {[which $objdump] == 0} then {
+	perror "$objdump does not exist"
+	return 0
+    }
+
+    if ![info exists OBJDUMPFLAGS] { set OBJDUMPFLAGS "" }
+
+    verbose -log "$objdump $OBJDUMPFLAGS $object >$outputfile"
+
+    catch "exec $objdump $OBJDUMPFLAGS $object >$outputfile" exec_output
+    set exec_output [prune_warnings $exec_output]
+    if [string match "" $exec_output] then {
+	return 1
+    } else {
+	verbose -log "$exec_output"
+	perror "$object: objdump failed"
+	return 0
+    }
+}
+
+
+if ![ld_assemble $as $srcdir/$subdir/lcall1.s tmpdir/lcall1.o] {
+    unresolved $testname
+    return
+}
+if ![ld_assemble $as $srcdir/$subdir/lcall2.s tmpdir/lcall2.o] {
+    unresolved $testname
+    return
+}
+
+set object "tmpdir/lcall"
+set outputfile "$object.txt"
+
+if ![ld_simple_link $ld $object "-T $srcdir/$subdir/lcall.t tmpdir/lcall1.o tmpdir/lcall2.o"] {
+    verbose -log "failure in ld"
+    fail $testname
+    return
+} 
+
+if ![default_ld_objdump $objdump $object $outputfile ] {
+    verbose -log "failure in objdump"
+    fail $testname
+    return
+} 
+
+set file [open $outputfile r]
+while { [gets $file line] != -1 } {
+    #	verbose "$line" 2
+    if [regexp "l32r" $line] {
+	verbose -log "Found an l32r in the linked object"
+	verbose -log "$line"
+	fail $testname
+    }
+}
+close $file
+pass $testname
+
+
+set testname "LCALL2"
+set file [open $outputfile r]
+set found 0
+
+while { [gets $file line] != -1 } {
+    #	verbose "$line" 2
+    if [regexp "^00000004 <label1>:" $line] {
+	set found 1
+    }
+}
+close $file
+if  $found  {
+   pass $testname
+} else {
+   fail $testname
+}
+
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/lcall.t b/binutils-2.19/ld/testsuite/ld-xtensa/lcall.t
new file mode 100644
index 0000000..7bff69f
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/lcall.t
@@ -0,0 +1,6 @@
+SECTIONS
+{
+  .text 0x00000000 : { 
+    *(.literal .text)
+  }
+}
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/lcall1.s b/binutils-2.19/ld/testsuite/ld-xtensa/lcall1.s
new file mode 100644
index 0000000..3439319
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/lcall1.s
@@ -0,0 +1,10 @@
+.global foo
+.text
+	.align 4
+label1:
+	.literal .Lunused, 0xffffffff
+	entry a5,16
+.begin longcalls
+	call4  foo
+.end longcalls
+	nop
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/lcall2.s b/binutils-2.19/ld/testsuite/ld-xtensa/lcall2.s
new file mode 100644
index 0000000..d697096
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/lcall2.s
@@ -0,0 +1,6 @@
+	.global foo
+	.align 4
+foo:
+	entry a5,16
+	nop
+	ret
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/tlsbin.dd b/binutils-2.19/ld/testsuite/ld-xtensa/tlsbin.dd
new file mode 100644
index 0000000..c3fad8b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/tlsbin.dd
@@ -0,0 +1,65 @@
+#source: tlsbin.s
+#as:
+#ld: -melf32xtensa
+#objdump: -drj.text --start-address=0x400238
+#target: xtensa*-*-linux*
+
+.*: +file format elf32-xtensa-.e
+
+Disassembly of section \.text:
+
+0+400238 <_start>:
+  [0-9a-f]+:	[0-9a-f]+[ 	]+entry	a1, 32
+#  GD -> IE because variable is not defined in executable
+  [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a8
+  [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a10, 4001ec <.*>
+  [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a10, a10, a8
+#  GD -> IE because variable is not defined in executable where
+#  the variable is referenced through IE too
+  [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a8
+  [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a10, 4001f4 <.*>
+  [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a10, a10, a8
+#  GD -> LE with global variable defined in executable
+  [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a8
+  [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a10, 4001fc <.*>
+  [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a10, a10, a8
+#  GD -> LE with local variable defined in executable
+  [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a8
+  [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a10, 400204 <.*>
+  [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a10, a10, a8
+#  GD -> LE with hidden variable defined in executable
+  [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a8
+  [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a10, 40020c <.*>
+  [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a10, a10, a8
+#  LD -> LE
+  [0-9a-f]+:	[0-9a-f]+[ 	]+nop.*
+  [0-9a-f]+:	[0-9a-f]+[ 	]+nop.*
+  [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a10
+  [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a12, 400218 <.*>
+  [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a12, a12, a10
+  [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a13, 40021c <.*>
+  [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a13, a13, a10
+#  LD -> LE against hidden variables
+  [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a12, 400220 <.*>
+  [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a12, a12, a10
+  [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a13, 400224 <.*>
+  [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a13, a13, a10
+#
+#  IE against global var
+  [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a2
+  [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a3, 400228 <.*>
+  [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a3, a3, a2
+#  IE -> LE against global var defined in exec
+  [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a4
+  [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a5, 40022c <.*>
+  [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a5, a5, a4
+#  IE -> LE against local var
+  [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a6
+  [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a7, 400230 <.*>
+  [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a7, a7, a6
+#  IE -> LE against hidden var
+  [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a8
+  [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a9, 400234 <.*>
+  [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a9, a9, a8
+#
+  [0-9a-f]+:	[0-9a-f]+[ 	]+retw.*
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/tlsbin.rd b/binutils-2.19/ld/testsuite/ld-xtensa/tlsbin.rd
new file mode 100644
index 0000000..b2e8726
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/tlsbin.rd
@@ -0,0 +1,118 @@
+#source: tlsbin.s
+#as:
+#ld: -melf32xtensa
+#readelf: -WSsrl
+#target: xtensa*-*-linux*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0
+ +\[[ 0-9]+\] .interp +.*
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .text +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +AX +0 +0 +4
+ +\[[ 0-9]+\] .got.loc +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +A +0 +0 +4
+ +\[[ 0-9]+\] .tdata +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +WAT +0 +0 +4
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 08 +WA +4 +0 +4
+ +\[[ 0-9]+\] .got +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +WA +0 +0 +4
+ +\[[ 0-9]+\] .xt.lit +PROGBITS +0+ .*
+ +\[[ 0-9]+\] .xt.prop +PROGBITS +0+ .*
+ +\[[ 0-9]+\] .xtensa.info +NOTE +0+ .*
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is EXEC \(Executable file\)
+Entry point 0x[0-9a-f]+
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  PHDR.*
+  INTERP.*
+.*Requesting program interpreter.*
+  LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R E 0x1000
+  LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW  0x1000
+  DYNAMIC +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW +0x4
+  TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x4
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 *
+   01 +.interp *
+   02 +.interp .hash .dynsym .dynstr .rela.dyn .text .got.loc *
+   03 +.tdata .dynamic .got *
+   04 +.dynamic *
+   05 +.tdata *
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 3 entries:
+ +Offset +Info +Type +Sym\. Value  Symbol's Name \+ Addend
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLS_TPOFF +0+ +sG1 \+ 0
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLS_TPOFF +0+ +sG2 \+ 0
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLS_TPOFF +0+ +sG2 \+ 0
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG2
+ +[0-9]+: 0+[0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG1
+ +[0-9]+: 0+[0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: 0+[0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +1 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +2 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +3 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +4 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +5 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +6 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +7 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +8 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +9 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +10 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +11 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +12 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +13 *
+ +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL  DEFAULT +8 sl1
+ +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL  DEFAULT +8 sl2
+ +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL  DEFAULT +8 sl3
+ +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL  DEFAULT +8 sl4
+ +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL  DEFAULT +8 sl5
+ +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL  DEFAULT +8 sl6
+ +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL  DEFAULT +8 sl7
+ +[0-9]+: [0-9a-f]+ +0 TLS +LOCAL  DEFAULT +8 sl8
+ +[0-9]+: 0+ +0 TLS +LOCAL  HIDDEN +8 _TLS_MODULE_BASE_
+ +[0-9]+: [0-9a-f]+ +0 OBJECT +LOCAL +HIDDEN +9 _DYNAMIC
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg8
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg3
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh3
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG2
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg4
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg5
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh7
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh8
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg1
+ +[0-9]+: [0-9a-f]+ +0 FUNC +GLOBAL DEFAULT +6 _start
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh4
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh5
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg2
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT  UND sG1
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh1
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg6
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL DEFAULT +8 sg7
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh2
+ +[0-9]+: [0-9a-f]+ +0 TLS +GLOBAL HIDDEN +8 sh6
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/tlsbin.s b/binutils-2.19/ld/testsuite/ld-xtensa/tlsbin.s
new file mode 100644
index 0000000..2220cfc
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/tlsbin.s
@@ -0,0 +1,98 @@
+	.section ".tdata", "awT", @progbits
+	.global sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.global sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.align	4
+sg1:	.long	17
+sg2:	.long	18
+sg3:	.long	19
+sg4:	.long	20
+sg5:	.long	21
+sg6:	.long	22
+sg7:	.long	23
+sg8:	.long	24
+sl1:	.long	65
+sl2:	.long	66
+sl3:	.long	67
+sl4:	.long	68
+sl5:	.long	69
+sl6:	.long	70
+sl7:	.long	71
+sl8:	.long	72
+sh1:	.long	157
+sh2:	.long	158
+sh3:	.long	159
+sh4:	.long	160
+sh5:	.long	161
+sh6:	.long	162
+sh7:	.long	163
+sh8:	.long	164
+
+	.text
+	.global	_start
+	.type	_start, @function
+_start:
+	entry	sp, 32
+
+	/* GD -> IE because variable is not defined in executable */
+	movi	a8, sG1@tlsfunc
+	movi	a10, sG1@tlsarg
+	callx8.tls a8, sG1@tlscall
+	
+	/* GD -> IE because variable is not defined in executable where
+	   the variable is referenced through IE too */
+	movi	a8, sG2@tlsfunc
+	movi	a10, sG2@tlsarg
+	callx8.tls a8, sG2@tlscall
+
+	/* GD -> LE with global variable defined in executable */
+	movi	a8, sg1@tlsfunc
+	movi	a10, sg1@tlsarg
+	callx8.tls a8, sg1@tlscall
+
+	/* GD -> LE with local variable defined in executable */
+	movi	a8, sl1@tlsfunc
+	movi	a10, sl1@tlsarg
+	callx8.tls a8, sl1@tlscall
+
+	/* GD -> LE with hidden variable defined in executable */
+	movi	a8, sh1@tlsfunc
+	movi	a10, sh1@tlsarg
+	callx8.tls a8, sh1@tlscall
+
+	/* LD -> LE */
+	movi   a8, _TLS_MODULE_BASE_@tlsfunc
+	movi   a10, _TLS_MODULE_BASE_@tlsarg
+	callx8.tls a8, _TLS_MODULE_BASE_@tlscall
+	movi   a12, 1+sl1@dtpoff
+	add    a12, a12, a10
+	movi   a13, sl2@dtpoff+2
+	add    a13, a13, a10
+	
+	/* LD -> LE against hidden variables */
+	movi   a12, sh1@dtpoff
+	add    a12, a12, a10
+	movi   a13, 3+sh2@dtpoff
+	add    a13, a13, a10
+
+	/* IE against global var */
+	rur	a2, THREADPTR
+	movi	a3, sG2@tpoff
+	add	a3, a3, a2
+
+	/* IE -> LE against global var defined in exec */
+	rur	a4, THREADPTR
+	movi	a5, sg1@tpoff
+	add	a5, a5, a4
+
+	/* IE -> LE against local var */
+	rur	a6, THREADPTR
+	movi	a7, sl1@tpoff
+	add	a7, a7, a6
+
+	/* IE -> LE against hidden var */
+	rur	a8, THREADPTR
+	movi	a9, sh1@tpoff
+	add	a9, a9, a8
+
+	retw
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/tlsbin.sd b/binutils-2.19/ld/testsuite/ld-xtensa/tlsbin.sd
new file mode 100644
index 0000000..484db07
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/tlsbin.sd
@@ -0,0 +1,14 @@
+#source: tlsbin.s
+#as:
+#ld: -melf32xtensa
+#objdump: -sj.text --stop-address=0x400238
+#target: xtensa*-*-linux*
+
+.*: +file format elf32-xtensa-.e
+
+Contents of section .text:
+ *[0-9a-f]+ 0+ 0+ 0+ 0+  .*
+ *[0-9a-f]+ 0+ 0*080* 0+ 0*280*  .*
+ *[0-9a-f]+ 0+ 0*480* 0+ 0*080*  .*
+ *[0-9a-f]+ 0*290* 0*2e0* 0*480* 0*4f0*  .*
+ *[0-9a-f]+ 0+ 0*080* 0*280* 0*480*  .*
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/tlsbin.td b/binutils-2.19/ld/testsuite/ld-xtensa/tlsbin.td
new file mode 100644
index 0000000..efef45c
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/tlsbin.td
@@ -0,0 +1,14 @@
+#source: tlsbin.s
+#ld: -melf32xtensa
+#objdump: -sj.tdata
+#target: xtensa*-*-linux*
+
+.*: +file format elf32-xtensa-.e
+
+Contents of section .tdata:
+ *[0-9a-f]+ 0*110* 0*120* 0*130* 0*140*  .*
+ *[0-9a-f]+ 0*150* 0*160* 0*170* 0*180*  .*
+ *[0-9a-f]+ 0*410* 0*420* 0*430* 0*440*  .*
+ *[0-9a-f]+ 0*450* 0*460* 0*470* 0*480*  .*
+ *[0-9a-f]+ 0*9d0* 0*9e0* 0*9f0* 0*a00*  .*
+ *[0-9a-f]+ 0*a10* 0*a20* 0*a30* 0*a40*  .*
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/tlslib.s b/binutils-2.19/ld/testsuite/ld-xtensa/tlslib.s
new file mode 100644
index 0000000..a2c430b
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/tlslib.s
@@ -0,0 +1,18 @@
+	.section ".tdata", "awT", @progbits
+	.global	sG1, sG2, sG3, sG4, sG5, sG6, sG7, sG8
+sG1:	.long	513
+sG2:	.long	514
+sG3:	.long	515
+sG4:	.long	516
+sG5:	.long	517
+sG6:	.long	518
+sG7:	.long	519
+sG8:	.long	520
+
+	.text
+	/* Dummy.  */
+	.global	__tls_get_addr
+	.type	__tls_get_addr, @function
+__tls_get_addr:
+	entry	sp, 16
+	retw
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/tlspic.dd b/binutils-2.19/ld/testsuite/ld-xtensa/tlspic.dd
new file mode 100644
index 0000000..9f6e20a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/tlspic.dd
@@ -0,0 +1,81 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as:
+#ld: -shared -melf32xtensa
+#objdump: -drj.text --start-address=0x350
+#target: xtensa*-*-linux*
+
+.*: +file format elf32-xtensa-.e
+
+Disassembly of section \.text:
+
+0+350 <_start>:
+ [0-9a-f]+:	[0-9a-f]+[ 	]+entry	a1, 32
+#  GD
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a8, 2e0 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a10, 2e4 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+callx8	a8
+#  GD -> IE because variable is referenced through IE too
+ [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a8
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a10, 2ec <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a10, a10, a8
+#  GD against local variable
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a8, 2f0 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a10, 2f4 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+callx8	a8
+#  GD -> IE against local variable referenced through IE too
+ [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a8
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a10, 2fc <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a10, a10, a8
+#  GD against hidden and local variable
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a8, 300 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a10, 304 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+callx8	a8
+#  GD -> IE against hidden and local variable referenced through IE too
+ [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a8
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a10, 30c <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a10, a10, a8
+#  GD against hidden but not local variable
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a8, 310 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a10, 314 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+callx8	a8
+#  GD -> IE against hidden but not local variable referenced through IE too
+ [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a8
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a10, 31c <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a10, a10, a8
+#  LD
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a8, 320 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a10, 324 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+callx8	a8
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a12, 328 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a12, a12, a10
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a13, 32c <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a13, a13, a10
+#  LD against hidden and local variables
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a12, 330 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a12, a12, a10
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a13, 334 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a13, a13, a10
+#  LD against hidden but not local variables
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a12, 338 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a12, a12, a10
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a13, 33c <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a13, a13, a10
+#  IE against global var
+ [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a2
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a3, 340 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a3, a3, a2
+#  IE against local var
+ [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a4
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a5, 344 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a5, a5, a4
+#  IE against hidden and local var
+ [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a6
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a7, 348 <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a7, a7, a6
+#  IE against hidden but not local var
+ [0-9a-f]+:	[0-9a-f]+[ 	]+rur.threadptr	a8
+ [0-9a-f]+:	[0-9a-f]+[ 	]+l32r	a9, 34c <.*>
+ [0-9a-f]+:	[0-9a-f]+[ 	]+add.*	a9, a9, a8
+#
+ [0-9a-f]+:	[0-9a-f]+[ 	]+retw.*
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/tlspic.rd b/binutils-2.19/ld/testsuite/ld-xtensa/tlspic.rd
new file mode 100644
index 0000000..54dd71a
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/tlspic.rd
@@ -0,0 +1,142 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as:
+#ld: -shared -melf32xtensa
+#readelf: -WSsrl
+#target: xtensa*-*-linux*
+
+There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+:
+
+Section Headers:
+  \[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+ +\[[ 0-9]+\] +NULL +0+ 0+ 0+ 00 +0 +0 +0
+ +\[[ 0-9]+\] .hash +.*
+ +\[[ 0-9]+\] .dynsym +.*
+ +\[[ 0-9]+\] .dynstr +.*
+ +\[[ 0-9]+\] .rela.dyn +.*
+ +\[[ 0-9]+\] .text +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +AX +0 +0 +4
+ +\[[ 0-9]+\] .got.loc +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +A +0 +0 +4
+ +\[[ 0-9]+\] .tdata +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +WAT +0 +0 +4
+ +\[[ 0-9]+\] .tbss +NOBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +WAT +0 +0 +4
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 08 +WA +3 +0 +4
+ +\[[ 0-9]+\] .got +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +WA +0 +0 +4
+ +\[[ 0-9]+\] .xt.lit +PROGBITS +0+ .*
+ +\[[ 0-9]+\] .xt.prop +PROGBITS +0+ .*
+ +\[[ 0-9]+\] .xtensa.info +NOTE +0+ .*
+ +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
+Key to Flags:
+.*
+.*
+.*
+
+Elf file type is DYN \(Shared object file\)
+Entry point 0x[0-9a-f]+
+There are [0-9]+ program headers, starting at offset [0-9]+
+
+Program Headers:
+  Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align
+  LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R E 0x1000
+  LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW  0x1000
+  DYNAMIC +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ RW +0x4
+  TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ R +0x4
+
+ Section to Segment mapping:
+  Segment Sections...
+   00 +.hash .dynsym .dynstr .rela.dyn .text .got.loc *
+   01 +.tdata .dynamic .got *
+   02 +.dynamic *
+   03 +.tdata .tbss *
+
+Relocation section '.rela.dyn' at offset 0x[0-9a-f]+ contains 18 entries:
+ +Offset +Info +Type +Sym\. Value  Symbol's Name \+ Addend
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLSDESC_FN +0+ +sg1 \+ 0
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLSDESC_ARG +0+ +sg1 \+ 0
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLS_TPOFF +0+4 +sg2 \+ 0
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLS_TPOFF +0+4 +sg2 \+ 0
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLSDESC_FN +0+20
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLSDESC_ARG +0+20
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLS_TPOFF +0+24
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLSDESC_FN +0+40
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLSDESC_ARG +0+40
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLS_TPOFF +0+44
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLSDESC_FN +0+60
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLSDESC_ARG +0+60
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLS_TPOFF +0+64
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLSDESC_FN +0+
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLSDESC_ARG +0+
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLS_TPOFF +0+24
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLS_TPOFF +0+44
+[0-9a-f]+  [0-9a-f]+ R_XTENSA_TLS_TPOFF +0+64
+
+Symbol table '\.dynsym' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: 0+1c +0 TLS +GLOBAL DEFAULT +7 sg8
+ +[0-9]+: 0+8 +0 TLS +GLOBAL DEFAULT +7 sg3
+ +[0-9]+: 0+c +0 TLS +GLOBAL DEFAULT +7 sg4
+ +[0-9]+: 0+10 +0 TLS +GLOBAL DEFAULT +7 sg5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +7 sg1
+ +[0-9]+: 0+350 +0 FUNC +GLOBAL DEFAULT +5 _start
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+4 +0 TLS +GLOBAL DEFAULT +7 sg2
+ +[0-9]+: 0+14 +0 TLS +GLOBAL DEFAULT +7 sg6
+ +[0-9]+: 0+18 +0 TLS +GLOBAL DEFAULT +7 sg7
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
+
+Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size Type +Bind +Vis +Ndx Name
+ +[0-9]+: 0+ +0 NOTYPE  LOCAL  DEFAULT  UND *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +1 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +2 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +3 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +4 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +5 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +6 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +7 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +8 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +9 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +10 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +11 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +12 *
+ +[0-9]+: [0-9a-f]+ +0 SECTION LOCAL  DEFAULT +13 *
+ +[0-9]+: 0+20 +0 TLS +LOCAL  DEFAULT +7 sl1
+ +[0-9]+: 0+24 +0 TLS +LOCAL  DEFAULT +7 sl2
+ +[0-9]+: 0+28 +0 TLS +LOCAL  DEFAULT +7 sl3
+ +[0-9]+: 0+2c +0 TLS +LOCAL  DEFAULT +7 sl4
+ +[0-9]+: 0+30 +0 TLS +LOCAL  DEFAULT +7 sl5
+ +[0-9]+: 0+34 +0 TLS +LOCAL  DEFAULT +7 sl6
+ +[0-9]+: 0+38 +0 TLS +LOCAL  DEFAULT +7 sl7
+ +[0-9]+: 0+3c +0 TLS +LOCAL  DEFAULT +7 sl8
+ +[0-9]+: 0+60 +0 TLS +LOCAL  HIDDEN +8 sH1
+ +[0-9]+: 0+ +0 TLS +LOCAL  HIDDEN +7 _TLS_MODULE_BASE_
+ +[0-9]+: 0+144c +0 OBJECT  LOCAL  HIDDEN  ABS _DYNAMIC
+ +[0-9]+: 0+48 +0 TLS +LOCAL  HIDDEN +7 sh3
+ +[0-9]+: 0+64 +0 TLS +LOCAL  HIDDEN +8 sH2
+ +[0-9]+: 0+78 +0 TLS +LOCAL  HIDDEN +8 sH7
+ +[0-9]+: 0+58 +0 TLS +LOCAL  HIDDEN +7 sh7
+ +[0-9]+: 0+5c +0 TLS +LOCAL  HIDDEN +7 sh8
+ +[0-9]+: 0+6c +0 TLS +LOCAL  HIDDEN +8 sH4
+ +[0-9]+: 0+4c +0 TLS +LOCAL  HIDDEN +7 sh4
+ +[0-9]+: 0+68 +0 TLS +LOCAL  HIDDEN +8 sH3
+ +[0-9]+: 0+50 +0 TLS +LOCAL  HIDDEN +7 sh5
+ +[0-9]+: 0+70 +0 TLS +LOCAL  HIDDEN +8 sH5
+ +[0-9]+: 0+74 +0 TLS +LOCAL  HIDDEN +8 sH6
+ +[0-9]+: 0+7c +0 TLS +LOCAL  HIDDEN +8 sH8
+ +[0-9]+: 0+40 +0 TLS +LOCAL  HIDDEN +7 sh1
+ +[0-9]+: 0+44 +0 TLS +LOCAL  HIDDEN +7 sh2
+ +[0-9]+: 0+54 +0 TLS +LOCAL  HIDDEN +7 sh6
+ +[0-9]+: 0+1c +0 TLS +GLOBAL DEFAULT +7 sg8
+ +[0-9]+: 0+8 +0 TLS +GLOBAL DEFAULT +7 sg3
+ +[0-9]+: 0+c +0 TLS +GLOBAL DEFAULT +7 sg4
+ +[0-9]+: 0+10 +0 TLS +GLOBAL DEFAULT +7 sg5
+ +[0-9]+: 0+ +0 TLS +GLOBAL DEFAULT +7 sg1
+ +[0-9]+: 0+350 +0 FUNC +GLOBAL DEFAULT +5 _start
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS __bss_start
+ +[0-9]+: 0+4 +0 TLS +GLOBAL DEFAULT +7 sg2
+ +[0-9]+: 0+14 +0 TLS +GLOBAL DEFAULT +7 sg6
+ +[0-9]+: 0+18 +0 TLS +GLOBAL DEFAULT +7 sg7
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _edata
+ +[0-9]+: [0-9a-f]+ +0 NOTYPE  GLOBAL DEFAULT  ABS _end
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/tlspic.sd b/binutils-2.19/ld/testsuite/ld-xtensa/tlspic.sd
new file mode 100644
index 0000000..57dafc0
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/tlspic.sd
@@ -0,0 +1,17 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as:
+#ld: -shared -melf32xtensa
+#objdump: -sj.text --stop-address=0x350
+#target: xtensa*-*-linux*
+
+.*: +file format elf32-xtensa-.e
+
+Contents of section .text:
+ 0+2e0 0+ 0+ 0+ 0+  .*
+ 0+2f0 0+ 0+ 0+ 0+  .*
+ 0+300 0+ 0+ 0+ 0+  .*
+ 0+310 0+ 0+ 0+ 0+  .*
+ 0+320 0+ 0+ 0*200* 0*260*  .*
+ 0+330 0*400* 0*470* 0*600* 0*650*  .*
+ 0+340 0+ 0+ 0+ 0+  .*
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/tlspic.td b/binutils-2.19/ld/testsuite/ld-xtensa/tlspic.td
new file mode 100644
index 0000000..d3e11d3
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/tlspic.td
@@ -0,0 +1,16 @@
+#source: tlspic1.s
+#source: tlspic2.s
+#as:
+#ld: -shared -melf32xtensa
+#objdump: -sj.tdata
+#target: xtensa*-*-linux*
+
+.*: +file format elf32-xtensa-.e
+
+Contents of section .tdata:
+ *[0-9a-f]+ 0*110* 0*120* 0*130* 0*140*  .*
+ *[0-9a-f]+ 0*150* 0*160* 0*170* 0*180*  .*
+ *[0-9a-f]+ 0*410* 0*420* 0*430* 0*440*  .*
+ *[0-9a-f]+ 0*450* 0*460* 0*470* 0*480*  .*
+ *[0-9a-f]+ 0*9d0* 0*9e0* 0*9f0* 0*a00*  .*
+ *[0-9a-f]+ 0*a10* 0*a20* 0*a30* 0*a40*  .*
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/tlspic1.s b/binutils-2.19/ld/testsuite/ld-xtensa/tlspic1.s
new file mode 100644
index 0000000..9ecde66
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/tlspic1.s
@@ -0,0 +1,120 @@
+	.section ".tdata", "awT", @progbits
+	.global sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8
+	.global sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.hidden sh1, sh2, sh3, sh4, sh5, sh6, sh7, sh8
+	.align	4
+sg1:	.long	17
+sg2:	.long	18
+sg3:	.long	19
+sg4:	.long	20
+sg5:	.long	21
+sg6:	.long	22
+sg7:	.long	23
+sg8:	.long	24
+sl1:	.long	65
+sl2:	.long	66
+sl3:	.long	67
+sl4:	.long	68
+sl5:	.long	69
+sl6:	.long	70
+sl7:	.long	71
+sl8:	.long	72
+sh1:	.long	157
+sh2:	.long	158
+sh3:	.long	159
+sh4:	.long	160
+sh5:	.long	161
+sh6:	.long	162
+sh7:	.long	163
+sh8:	.long	164
+
+	.text
+	.global	_start
+	.type	_start, @function
+_start:
+	entry	sp, 32
+
+	/* GD */
+	movi	a8, sg1@tlsfunc
+	movi	a10, sg1@tlsarg
+	callx8.tls a8, sg1@tlscall
+
+	/* GD -> IE because variable is referenced through IE too */
+	movi	a8, sg2@tlsfunc
+	movi	a10, sg2@tlsarg
+	callx8.tls a8, sg2@tlscall
+
+	/* GD against local variable */
+	movi	a8, sl1@tlsfunc
+	movi	a10, sl1@tlsarg
+	callx8.tls a8, sl1@tlscall
+
+	/* GD -> IE against local variable referenced through IE too */
+	movi	a8, sl2@tlsfunc
+	movi	a10, sl2@tlsarg
+	callx8.tls a8, sl2@tlscall
+
+	/* GD against hidden and local variable */
+	movi	a8, sh1@tlsfunc
+	movi	a10, sh1@tlsarg
+	callx8.tls a8, sh1@tlscall
+
+	/* GD -> IE against hidden and local variable referenced through
+	   IE too */
+	movi	a8, sh2@tlsfunc
+	movi	a10, sh2@tlsarg
+	callx8.tls a8, sh2@tlscall
+
+	/* GD against hidden but not local variable */
+	movi	a8, sH1@tlsfunc
+	movi	a10, sH1@tlsarg
+	callx8.tls a8, sH1@tlscall
+
+	/* GD -> IE against hidden but not local variable referenced through
+	   IE too */
+	movi	a8, sH2@tlsfunc
+	movi	a10, sH2@tlsarg
+	callx8.tls a8, sH2@tlscall
+
+	/* LD */
+	movi   a8, _TLS_MODULE_BASE_@tlsfunc
+	movi   a10, _TLS_MODULE_BASE_@tlsarg
+	callx8.tls a8, _TLS_MODULE_BASE_@tlscall
+	movi   a12, sl1@dtpoff
+	add    a12, a12, a10
+	movi   a13, 2+sl2@dtpoff
+	add    a13, a13, a10
+
+	/* LD against hidden and local variables */
+	movi   a12, sh1@dtpoff
+	add    a12, a12, a10
+	movi   a13, sh2@dtpoff+3
+	add    a13, a13, a10
+
+	/* LD against hidden but not local variables */
+	movi   a12, sH1@dtpoff
+	add    a12, a12, a10
+	movi   a13, sH2@dtpoff+1
+	add    a13, a13, a10
+
+	/* IE against global var */
+	rur	a2, THREADPTR
+	movi	a3, sg2@tpoff
+	add	a3, a3, a2
+
+	/* IE against local var  */
+	rur	a4, THREADPTR
+	movi	a5, sl2@tpoff
+	add	a5, a5, a4
+
+	/* IE against hidden and local var  */
+	rur	a6, THREADPTR
+	movi	a7, sh2@tpoff
+	add	a7, a7, a6
+
+	/* IE against hidden but not local var  */
+	rur	a8, THREADPTR
+	movi	a9, sH2@tpoff
+	add	a9, a9, a8
+
+	retw
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/tlspic2.s b/binutils-2.19/ld/testsuite/ld-xtensa/tlspic2.s
new file mode 100644
index 0000000..9f337e7
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/tlspic2.s
@@ -0,0 +1,12 @@
+	.section ".tbss", "awT", @nobits
+	.global	sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+	.hidden	sH1, sH2, sH3, sH4, sH5, sH6, sH7, sH8
+	.align	4
+sH1:	.space	4
+sH2:	.space	4
+sH3:	.space	4
+sH4:	.space	4
+sH5:	.space	4
+sH6:	.space	4
+sH7:	.space	4
+sH8:	.space	4
diff --git a/binutils-2.19/ld/testsuite/ld-xtensa/xtensa.exp b/binutils-2.19/ld/testsuite/ld-xtensa/xtensa.exp
new file mode 100644
index 0000000..e6dc827
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/ld-xtensa/xtensa.exp
@@ -0,0 +1,54 @@
+# Expect script for ld-xtensa tests
+#   Copyright (C) 2008 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+if { !([istarget "xtensa*-*-linux*"]) } {
+    return
+}
+
+# List contains test-items with 3 items followed by 2 lists:
+# 0:name 1:ld options 2:assembler options
+# 3:filenames of assembler files 4: action and options. 5: name of output file
+
+# Actions:
+# objdump: Apply objdump options on result.  Compare with regex (last arg).
+# nm: Apply nm options on result.  Compare with regex (last arg).
+# readelf: Apply readelf options on result.  Compare with regex (last arg).
+
+set xtensatests {
+    {"TLS -shared transitions"
+     "-shared -melf32xtensa" "" {tlspic1.s tlspic2.s}
+     {{readelf -WSsrl tlspic.rd}
+      {objdump "-drj.text --start-address=0x350" tlspic.dd}
+      {objdump "-sj.text --stop-address=0x350" tlspic.sd}
+      {objdump -sj.tdata tlspic.td}}
+      "libtlspic.so"}
+    {"Helper shared library" "-shared -melf32xtensa"
+     "" {tlslib.s} {} "libtlslib.so"}
+    {"TLS exec transitions"
+     "-melf32xtensa tmpdir/libtlslib.so" "" {tlsbin.s}
+     {{readelf -WSsrl tlsbin.rd}
+      {objdump "-drj.text --start-address=0x400238" tlsbin.dd}
+      {objdump "-sj.text --stop-address=0x400238" tlsbin.sd}
+      {objdump -sj.tdata tlsbin.td}}
+      "tlsbin"}
+}
+
+run_ld_link_tests $xtensatests
diff --git a/binutils-2.19/ld/testsuite/lib/ld-lib.exp b/binutils-2.19/ld/testsuite/lib/ld-lib.exp
new file mode 100644
index 0000000..d4e996e
--- /dev/null
+++ b/binutils-2.19/ld/testsuite/lib/ld-lib.exp
@@ -0,0 +1,1608 @@
+# Support routines for LD testsuite.
+#   Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
+#    2004, 2005, 2006, 2007 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This file is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+
+# Extract and print the version number of ld.
+#
+proc default_ld_version { ld } {
+    global host_triplet
+
+    if { ![is_remote host] && [which $ld] == 0 } then {
+	perror "$ld does not exist"
+	exit 1
+    }
+
+    remote_exec host "$ld --version" "" "/dev/null" "ld.version"
+    remote_upload host "ld.version"
+    set tmp [prune_warnings [file_contents "ld.version"]]
+    remote_file build delete "ld.version"
+    remote_file host delete "ld.version"
+
+    regexp "\[^\n\]* (cygnus-|)(\[-0-9.a-zA-Z-\]+)\[\r\n\].*" $tmp version cyg number
+    if [info exists number] then {
+	clone_output "$ld $number\n"
+    }
+}
+
+proc run_host_cmd { prog command } {
+    global link_output
+
+    if { ![is_remote host] && [which "$prog"] == 0 } then {
+	perror "$prog does not exist"
+	return 0
+    }
+
+    verbose -log "$prog $command"
+    set status [remote_exec host [concat sh -c [list "$prog $command 2>&1"]] "" "/dev/null" "ld.tmp"]
+    remote_upload host "ld.tmp"
+    set link_output [file_contents "ld.tmp"]
+    regsub "\n$" $link_output "" link_output
+    if { [lindex $status 0] != 0 && [string match "" $link_output] } then {
+	append link_output "child process exited abnormally"
+    }
+    remote_file build delete ld.tmp
+    remote_file host delete ld.tmp
+
+    if [string match "" $link_output] then {
+	return ""
+    }
+
+    verbose -log "$link_output"
+    return "$link_output"
+}
+
+proc run_host_cmd_yesno { prog command } {
+    global exec_output
+
+    set exec_output [prune_warnings [run_host_cmd "$prog" "$command"]]
+    if [string match "" $exec_output] then {
+	return 1;
+    }
+    return 0;
+}
+
+# Link an object using relocation.
+#
+proc default_ld_relocate { ld target objects } {
+    global HOSTING_EMU
+
+    remote_file host delete $target
+    return [run_host_cmd_yesno "$ld" "$HOSTING_EMU -o $target -r $objects"]
+}
+
+# Check to see if ld is being invoked with a non-endian output format
+#
+proc is_endian_output_format { object_flags } {
+
+    if {[string match "*-oformat binary*" $object_flags] ||      \
+        [string match "*-oformat ieee*" $object_flags] ||        \
+	[string match "*-oformat ihex*" $object_flags] ||        \
+	[string match "*-oformat netbsd-core*" $object_flags] || \
+	[string match "*-oformat srec*" $object_flags] ||        \
+	[string match "*-oformat tekhex*" $object_flags] ||      \
+	[string match "*-oformat trad-core*" $object_flags] } then {
+        return 0
+    } else {
+	return 1
+    }
+}
+
+# Look for big-endian or little-endian switches in the multlib
+# options and translate these into a -EB or -EL switch.  Note
+# we cannot rely upon proc process_multilib_options to do this
+# for us because for some targets the compiler does not support
+# -EB/-EL but it does support -mbig-endian/-mlittle-endian, and
+# the site.exp file will include the switch "-mbig-endian"
+# (rather than "big-endian") which is not detected by proc
+# process_multilib_options.
+#
+proc big_or_little_endian {} {
+
+    if [board_info [target_info name] exists multilib_flags] {
+	set tmp_flags " [board_info [target_info name] multilib_flags]"
+
+	foreach x $tmp_flags {
+	    case $x in {
+		{*big*endian eb EB -eb -EB -mb -meb} {
+		    set flags " -EB"
+		    return $flags
+		}
+		{*little*endian el EL -el -EL -ml -mel} {
+		    set flags " -EL"
+		    return $flags
+		}
+	    }
+	}
+    }
+
+    set flags ""
+    return $flags
+}
+
+# Link a program using ld.
+#
+proc default_ld_link { ld target objects } {
+    global HOSTING_EMU
+    global HOSTING_CRT0
+    global HOSTING_LIBS
+    global LIBS
+    global host_triplet
+    global link_output
+    global exec_output
+
+    set objs "$HOSTING_CRT0 $objects"
+    set libs "$LIBS $HOSTING_LIBS"
+
+    if [is_endian_output_format $objects] then {
+	set flags [big_or_little_endian]
+    } else {
+	set flags ""
+    }
+
+    remote_file host delete $target
+
+    return [run_host_cmd_yesno "$ld" "$HOSTING_EMU $flags -o $target $objs $libs"]
+}
+
+# Link a program using ld, without including any libraries.
+#
+proc default_ld_simple_link { ld target objects } {
+    global host_triplet
+    global gcc_ld_flag
+    global exec_output
+
+    if [is_endian_output_format $objects] then {
+	set flags [big_or_little_endian]
+    } else {
+	set flags ""
+    }
+
+    # If we are compiling with gcc, we want to add gcc_ld_flag to
+    # flags.  Rather than determine this in some complex way, we guess
+    # based on the name of the compiler.
+    set ldexe $ld
+    set ldparm [string first " " $ld]
+    if { $ldparm > 0 } then {
+	set ldexe [string range $ld 0 $ldparm]
+    }
+    set ldexe [string replace $ldexe 0 [string last "/" $ldexe] ""]
+    if {[string match "*gcc*" $ldexe] || [string match "*++*" $ldexe]} then {
+	set flags "$gcc_ld_flag $flags"
+    }
+
+    remote_file host delete $target
+
+    set exec_output [run_host_cmd "$ld" "$flags -o $target $objects"]
+    set exec_output [prune_warnings $exec_output]
+
+    # We don't care if we get a warning about a non-existent start
+    # symbol, since the default linker script might use ENTRY.
+    regsub -all "(^|\n)(\[^\n\]*: warning: cannot find entry symbol\[^\n\]*\n?)" $exec_output "\\1" exec_output
+
+    if [string match "" $exec_output] then {
+	return 1
+    } else {
+	return 0
+    }
+}
+
+# Compile an object using cc.
+#
+proc default_ld_compile { cc source object } {
+    global CFLAGS
+    global CXXFLAGS
+    global srcdir
+    global subdir
+    global host_triplet
+    global gcc_gas_flag
+
+    set cc_prog $cc
+    if {[llength $cc_prog] > 1} then {
+	set cc_prog [lindex $cc_prog 0]
+    }
+    if {![is_remote host] && [which $cc_prog] == 0} then {
+	perror "$cc_prog does not exist"
+	return 0
+    }
+
+    remote_file build delete "$object"
+    remote_file host delete "$object"
+
+    set flags "-I$srcdir/$subdir"
+
+    # If we are compiling with gcc, we want to add gcc_gas_flag to
+    # flags.  Rather than determine this in some complex way, we guess
+    # based on the name of the compiler.
+    set ccexe $cc
+    set ccparm [string first " " $cc]
+    set ccflags ""
+    if { $ccparm > 0 } then {
+	set ccflags [string range $cc $ccparm end]
+	set ccexe [string range $cc 0 $ccparm]
+	set cc $ccexe
+    }
+    set ccexe [string replace $ccexe 0 [string last "/" $ccexe] ""]
+    if {[string match "*gcc*" $ccexe] || [string match "*++*" $ccexe]} then {
+	set flags "$gcc_gas_flag $flags"
+    }
+
+    if {[string match "*++*" $ccexe]} {
+	set flags "$flags $CXXFLAGS"
+    } else {
+	set flags "$flags $CFLAGS"
+    }
+
+    if [board_info [target_info name] exists multilib_flags] {
+	append flags " [board_info [target_info name] multilib_flags]"
+    }
+
+    verbose -log "$cc $flags $ccflags -c $source -o $object"
+
+    set status [remote_exec host [concat sh -c [list "$cc $flags $ccflags -c $source -o $object 2>&1"]] "" "/dev/null" "ld.tmp"]
+    remote_upload host "ld.tmp"
+    set exec_output [file_contents "ld.tmp"]
+    remote_file build delete "ld.tmp"
+    remote_file host delete "ld.tmp"
+    set exec_output [prune_warnings $exec_output]
+    if [string match "" $exec_output] then {
+	if {![file exists $object]} then {
+	    regexp ".*/(\[^/\]*)$" $source all dobj
+	    regsub "\\.c" $dobj ".o" realobj
+	    verbose "looking for $realobj"
+	    if {[remote_file host exists $realobj]} then {
+		verbose -log "mv $realobj $object"
+		remote_upload "$realobj" "$object"
+	    } else {
+		perror "$object not found after compilation"
+		return 0
+	    }
+	}
+	return 1
+    } else {
+	verbose -log "$exec_output"
+	perror "$source: compilation failed"
+	return 0
+    }
+}
+
+# Assemble a file.
+#
+proc default_ld_assemble { as source object } {
+    global ASFLAGS
+    global host_triplet
+
+    if ![info exists ASFLAGS] { set ASFLAGS "" }
+
+    set flags [big_or_little_endian]
+    set exec_output [run_host_cmd "$as" "$flags $ASFLAGS -o $object $source"]
+    set exec_output [prune_warnings $exec_output]
+    if [string match "" $exec_output] then {
+	return 1
+    } else {
+	perror "$source: assembly failed"
+	return 0
+    }
+}
+
+# Run nm on a file, putting the result in the array nm_output.
+#
+proc default_ld_nm { nm nmflags object } {
+    global NMFLAGS
+    global nm_output
+    global host_triplet
+
+    if {[info exists nm_output]} {
+      unset nm_output
+    }
+
+    if ![info exists NMFLAGS] { set NMFLAGS "" }
+
+    # Ensure consistent sorting of symbols
+    if {[info exists env(LC_ALL)]} {
+	set old_lc_all $env(LC_ALL)
+    }
+    set env(LC_ALL) "C"
+
+    verbose -log "$nm $NMFLAGS $nmflags $object >tmpdir/nm.out"
+
+    set status [remote_exec host [concat sh -c [list "$nm $NMFLAGS $nmflags $object 2>ld.stderr"]] "" "/dev/null" "tmpdir/nm.out"]
+    if {[info exists old_lc_all]} {
+	set env(LC_ALL) $old_lc_all
+    } else {
+	unset env(LC_ALL)
+    }
+    remote_upload host "ld.stderr"
+    remote_upload host "tmpdir/nm.out" "tmpdir/nm.out"
+    set exec_output [prune_warnings [file_contents "ld.stderr"]]
+    remote_file host delete "ld.stderr"
+    remote_file build delete "ld.stderr"
+    if [string match "" $exec_output] then {
+	set file [open tmpdir/nm.out r]
+	while { [gets $file line] != -1 } {
+	    verbose "$line" 2
+	    if [regexp "^(\[0-9a-fA-F\]+) \[a-zA-Z0-9\] \\.*(.+)$" $line whole value name] {
+                set name [string trimleft $name "_"]
+		verbose "Setting nm_output($name) to 0x$value" 2
+		set nm_output($name) 0x$value
+	    }
+	}
+	close $file
+	return 1
+    } else {
+	verbose -log "$exec_output"
+	perror "$object: nm failed"
+	return 0
+    }
+}
+
+# True if the object format is known to be ELF.
+#
+proc is_elf_format {} {
+    if { ![istarget *-*-sysv4*] \
+	 && ![istarget *-*-unixware*] \
+	 && ![istarget *-*-elf*] \
+	 && ![istarget *-*-eabi*] \
+	 && ![istarget hppa*64*-*-hpux*] \
+	 && ![istarget *-*-linux*] \
+	 && ![istarget frv-*-uclinux*] \
+	 && ![istarget *-*-irix5*] \
+	 && ![istarget *-*-irix6*] \
+	 && ![istarget *-*-netbsd*] \
+	 && ![istarget *-*-solaris2*] } {
+	return 0
+    }
+
+    if { [istarget *-*-linux*aout*] \
+	 || [istarget *-*-linux*oldld*] } {
+	return 0
+    }
+
+    if { ![istarget *-*-netbsdelf*] \
+	 && ([istarget *-*-netbsd*aout*] \
+	     || [istarget *-*-netbsdpe*] \
+	     || [istarget arm*-*-netbsd*] \
+	     || [istarget sparc-*-netbsd*] \
+	     || [istarget i*86-*-netbsd*] \
+	     || [istarget m68*-*-netbsd*] \
+	     || [istarget vax-*-netbsd*] \
+	     || [istarget ns32k-*-netbsd*]) } {
+    	return 0
+    }
+    return 1
+}
+
+# True if the object format is known to be 64-bit ELF.
+#
+proc is_elf64 { binary_file } {
+    global READELF
+    global READELFFLAGS
+
+    set readelf_size ""
+    catch "exec $READELF $READELFFLAGS -h $binary_file > readelf.out" got
+
+    if ![string match "" $got] then {
+	return 0
+    }
+
+    if { ![regexp "\n\[ \]*Class:\[ \]*ELF(\[0-9\]+)\n" \
+	   [file_contents readelf.out] nil readelf_size] } {
+	return 0
+    }
+
+    if { $readelf_size == "64" } {
+	return 1
+    }
+
+    return 0
+}
+
+# True if the object format is known to be a.out.
+#
+proc is_aout_format {} {
+    if { [istarget *-*-*\[ab\]out*] \
+	     || [istarget *-*-linux*oldld*] \
+	     || [istarget *-*-msdos*] \
+	     || [istarget arm-*-netbsd] \
+	     || [istarget i?86-*-netbsd] \
+	     || [istarget i?86-*-mach*] \
+	     || [istarget i?86-*-vsta] \
+	     || [istarget pdp11-*-*] \
+	     || [istarget m68*-ericsson-ose] \
+	     || [istarget m68k-hp-bsd*] \
+	     || [istarget m68*-*-hpux*] \
+	     || [istarget m68*-*-netbsd] \
+	     || [istarget m68*-*-netbsd*4k*] \
+	     || [istarget m68k-sony-*] \
+	     || [istarget m68*-sun-sunos\[34\]*] \
+	     || [istarget m68*-wrs-vxworks*] \
+	     || [istarget ns32k-*-*] \
+	     || [istarget sparc*-*-netbsd] \
+	     || [istarget sparc-sun-sunos4*] \
+	     || [istarget vax-dec-ultrix*] \
+	     || [istarget vax-*-netbsd] } {
+	return 1
+    }
+    return 0
+}
+
+# True if the object format is known to be PE COFF.
+#
+proc is_pecoff_format {} {
+    if { ![istarget *-*-mingw*] \
+	 && ![istarget *-*-cygwin*] \
+	 && ![istarget *-*-pe*] } {
+	return 0
+    }
+
+    return 1
+}
+
+# Compares two files line-by-line.
+#   Returns differences if exist.
+#   Returns null if file(s) cannot be opened.
+#
+proc simple_diff { file_1 file_2 } {
+    global target
+
+    set eof -1
+    set differences 0
+
+    if [file exists $file_1] then {
+	set file_a [open $file_1 r]
+    } else {
+	warning "$file_1 doesn't exist"
+	return
+    }
+
+    if [file exists $file_2] then {
+	set file_b [open $file_2 r]
+    } else {
+	fail "$file_2 doesn't exist"
+	return
+    }
+
+    verbose "# Diff'ing: $file_1 $file_2\n" 2
+
+    while { [gets $file_a line] != $eof } {
+	if [regexp "^#.*$" $line] then {
+	    continue
+	} else {
+	    lappend list_a $line
+	}
+    }
+    close $file_a
+
+    while { [gets $file_b line] != $eof } {
+	if [regexp "^#.*$" $line] then {
+	    continue
+	} else {
+	    lappend list_b $line
+	}
+    }
+    close $file_b
+
+    for { set i 0 } { $i < [llength $list_a] } { incr i } {
+	set line_a [lindex $list_a $i]
+	set line_b [lindex $list_b $i]
+
+	verbose "\t$file_1: $i: $line_a\n" 3
+	verbose "\t$file_2: $i: $line_b\n" 3
+	if [string compare $line_a $line_b] then {
+	    verbose -log "\t$file_1: $i: $line_a\n"
+	    verbose -log "\t$file_2: $i: $line_b\n"
+
+	    fail "Test: $target"
+	    return
+	}
+    }
+
+    if { [llength $list_a] != [llength $list_b] } {
+	fail "Test: $target"
+	return
+    }
+
+    if $differences<1 then {
+	pass "Test: $target"
+    }
+}
+
+# run_dump_test FILE
+# Copied from gas testsuite, tweaked and further extended.
+#
+# Assemble a .s file, then run some utility on it and check the output.
+#
+# There should be an assembly language file named FILE.s in the test
+# suite directory, and a pattern file called FILE.d.  `run_dump_test'
+# will assemble FILE.s, run some tool like `objdump', `objcopy', or
+# `nm' on the .o file to produce textual output, and then analyze that
+# with regexps.  The FILE.d file specifies what program to run, and
+# what to expect in its output.
+#
+# The FILE.d file begins with zero or more option lines, which specify
+# flags to pass to the assembler, the program to run to dump the
+# assembler's output, and the options it wants.  The option lines have
+# the syntax:
+#
+#         # OPTION: VALUE
+#
+# OPTION is the name of some option, like "name" or "objdump", and
+# VALUE is OPTION's value.  The valid options are described below.
+# Whitespace is ignored everywhere, except within VALUE.  The option
+# list ends with the first line that doesn't match the above syntax
+# (hmm, not great for error detection).
+#
+# The interesting options are:
+#
+#   name: TEST-NAME
+#	The name of this test, passed to DejaGNU's `pass' and `fail'
+#       commands.  If omitted, this defaults to FILE, the root of the
+#       .s and .d files' names.
+#
+#   as: FLAGS
+#	When assembling, pass FLAGS to the assembler.
+#       If assembling several files, you can pass different assembler
+#       options in the "source" directives.  See below.
+#
+#   ld: FLAGS
+#       Link assembled files using FLAGS, in the order of the "source"
+#       directives, when using multiple files.
+#
+#   objcopy_linked_file: FLAGS
+#	Run objcopy on the linked file with the specified flags.
+#	This lets you transform the linked file using objcopy, before the
+#	result is analyzed by an analyzer program specified below (which
+#	may in turn *also* be objcopy).
+#
+#   PROG: PROGRAM-NAME
+#       The name of the program to run to analyze the .o file produced
+#       by the assembler or the linker output.  This can be omitted;
+#       run_dump_test will guess which program to run by seeing which of
+#       the flags options below is present.
+#
+#   objdump: FLAGS
+#   nm: FLAGS
+#   objcopy: FLAGS
+#	Use the specified program to analyze the assembler or linker
+#       output file, and pass it FLAGS, in addition to the output name.
+#	Note that they are run with LC_ALL=C in the environment to give
+#	consistent sorting of symbols.
+#
+#   source: SOURCE [FLAGS]
+#	Assemble the file SOURCE.s using the flags in the "as" directive
+#       and the (optional) FLAGS.  If omitted, the source defaults to
+#       FILE.s.
+#       This is useful if several .d files want to share a .s file.
+#       More than one "source" directive can be given, which is useful
+#       when testing linking.
+#
+#   xfail: TARGET
+#       The test is expected to fail on TARGET.  This may occur more than
+#       once.
+#
+#   target: TARGET
+#       Only run the test for TARGET.  This may occur more than once; the
+#       target being tested must match at least one.  You may provide target
+#       name "cfi" for any target supporting the CFI statements.
+#
+#   notarget: TARGET
+#       Do not run the test for TARGET.  This may occur more than once;
+#       the target being tested must not match any of them.
+#
+#   error: REGEX
+#	An error with message matching REGEX must be emitted for the test
+#	to pass.  The PROG, objdump, nm and objcopy options have no
+#	meaning and need not supplied if this is present.
+#
+#   warning: REGEX
+#	Expect a linker warning matching REGEX.  It is an error to issue
+#	both "error" and "warning".
+#
+# Each option may occur at most once unless otherwise mentioned.
+#
+# After the option lines come regexp lines.  `run_dump_test' calls
+# `regexp_diff' to compare the output of the dumping tool against the
+# regexps in FILE.d.  `regexp_diff' is defined later in this file; see
+# further comments there.
+#
+proc run_dump_test { name } {
+    global subdir srcdir
+    global OBJDUMP NM AS OBJCOPY READELF LD
+    global OBJDUMPFLAGS NMFLAGS ASFLAGS OBJCOPYFLAGS READELFFLAGS LDFLAGS
+    global host_triplet runtests
+    global env
+
+    if [string match "*/*" $name] {
+	set file $name
+	set name [file tail $name]
+    } else {
+	set file "$srcdir/$subdir/$name"
+    }
+
+    if ![runtest_file_p $runtests $name] then {
+	return
+    }
+
+    set opt_array [slurp_options "${file}.d"]
+    if { $opt_array == -1 } {
+	perror "error reading options from $file.d"
+	unresolved $subdir/$name
+	return
+    }
+    set dumpfile tmpdir/dump.out
+    set run_ld 0
+    set run_objcopy 0
+    set opts(as) {}
+    set opts(ld) {}
+    set opts(xfail) {}
+    set opts(target) {}
+    set opts(notarget) {}
+    set opts(objdump) {}
+    set opts(nm) {}
+    set opts(objcopy) {}
+    set opts(readelf) {}
+    set opts(name) {}
+    set opts(PROG) {}
+    set opts(source) {}
+    set opts(error) {}
+    set opts(warning) {}
+    set opts(objcopy_linked_file) {}
+    set asflags(${file}.s) {}
+
+    foreach i $opt_array {
+	set opt_name [lindex $i 0]
+	set opt_val [lindex $i 1]
+	if ![info exists opts($opt_name)] {
+	    perror "unknown option $opt_name in file $file.d"
+	    unresolved $subdir/$name
+	    return
+	}
+
+	switch -- $opt_name {
+	    xfail {}
+	    target {}
+	    notarget {}
+	    source {
+		# Move any source-specific as-flags to a separate array to
+		# simplify processing.
+		if { [llength $opt_val] > 1 } {
+		    set asflags([lindex $opt_val 0]) [lrange $opt_val 1 end]
+		    set opt_val [lindex $opt_val 0]
+		} else {
+		    set asflags($opt_val) {}
+		}
+	    }
+	    default {
+		if [string length $opts($opt_name)] {
+		    perror "option $opt_name multiply set in $file.d"
+		    unresolved $subdir/$name
+		    return
+		}
+
+		# A single "# ld:" with no options should do the right thing.
+		if { $opt_name == "ld" } {
+		    set run_ld 1
+		}
+		# Likewise objcopy_linked_file.
+		if { $opt_name == "objcopy_linked_file" } {
+		    set run_objcopy 1
+		}
+	    }
+	}
+	if { $opt_name == "as" || $opt_name == "ld" } {
+	    set opt_val [subst $opt_val]
+	}
+	set opts($opt_name) [concat $opts($opt_name) $opt_val]
+    }
+    foreach opt { as ld } {
+	regsub {\[big_or_little_endian\]} $opts($opt) \
+	    [big_or_little_endian] opts($opt)
+    }
+
+    # Decide early whether we should run the test for this target.
+    if { [llength $opts(target)] > 0 } {
+	set targmatch 0
+	foreach targ $opts(target) {
+	    if [istarget $targ] {
+		set targmatch 1
+		break
+	    }
+	}
+	if { $targmatch == 0 } {
+	    return
+	}
+    }
+    foreach targ $opts(notarget) {
+	if [istarget $targ] {
+	    return
+	}
+    }
+
+    set program ""
+    # It's meaningless to require an output-testing method when we
+    # expect an error.
+    if { $opts(error) == "" } {
+	if {$opts(PROG) != ""} {
+	    switch -- $opts(PROG) {
+		objdump	{ set program objdump }
+		nm	{ set program nm }
+		objcopy	{ set program objcopy }
+		readelf	{ set program readelf }
+		default
+		{ perror "unrecognized program option $opts(PROG) in $file.d"
+		  unresolved $subdir/$name
+		  return }
+	    }
+	} else {
+	# Guess which program to run, by seeing which option was specified.
+	    foreach p {objdump objcopy nm readelf} {
+		if {$opts($p) != ""} {
+		    if {$program != ""} {
+			perror "ambiguous dump program in $file.d"
+			unresolved $subdir/$name
+			return
+		    } else {
+			set program $p
+		    }
+		}
+	    }
+	}
+	if { $program == "" && $opts(warning) == "" } {
+	    perror "dump program unspecified in $file.d"
+	    unresolved $subdir/$name
+	    return
+	}
+    }
+
+    if { $opts(name) == "" } {
+	set testname "$subdir/$name"
+    } else {
+	set testname $opts(name)
+    }
+
+    if { $opts(source) == "" } {
+	set sourcefiles [list ${file}.s]
+    } else {
+	set sourcefiles {}
+	foreach sf $opts(source) {
+	    if { [string match "/*" $sf] } {
+		lappend sourcefiles "$sf"
+	    } else {
+		lappend sourcefiles "$srcdir/$subdir/$sf"
+	    }
+	    # Must have asflags indexed on source name.
+	    set asflags($srcdir/$subdir/$sf) $asflags($sf)
+	}
+    }
+
+    # Time to setup xfailures.
+    foreach targ $opts(xfail) {
+	setup_xfail $targ
+    }
+
+    # Assemble each file.
+    set objfiles {}
+    for { set i 0 } { $i < [llength $sourcefiles] } { incr i } {
+	set sourcefile [lindex $sourcefiles $i]
+
+	set objfile "tmpdir/dump$i.o"
+	catch "exec rm -f $objfile" exec_output
+	lappend objfiles $objfile
+	set cmd "$AS $ASFLAGS $opts(as) $asflags($sourcefile) -o $objfile $sourcefile"
+
+	send_log "$cmd\n"
+	set cmdret [remote_exec host [concat sh -c [list "$cmd 2>&1"]] "" "/dev/null" "ld.tmp"]
+	remote_upload host "ld.tmp"
+	set comp_output [prune_warnings [file_contents "ld.tmp"]]
+	remote_file host delete "ld.tmp"
+	remote_file build delete "ld.tmp"
+
+	if { [lindex $cmdret 0] != 0 || ![string match "" $comp_output] } then {
+	    send_log "$comp_output\n"
+	    verbose "$comp_output" 3
+
+	    set exitstat "succeeded"
+	    if { $cmdret != 0 } { set exitstat "failed" }
+	    verbose -log "$exitstat with: <$comp_output>"
+	    fail $testname
+	    return
+	}
+    }
+
+    set expmsg $opts(error)
+    if { $opts(warning) != "" } {
+	if { $expmsg != "" } {
+	    perror "$testname: mixing error and warning test-directives"
+	    return
+	}
+	set expmsg $opts(warning)
+    }
+
+    # Perhaps link the file(s).
+    if { $run_ld } {
+	set objfile "tmpdir/dump"
+	catch "exec rm -f $objfile" exec_output
+
+	# Add -L$srcdir/$subdir so that the linker command can use
+	# linker scripts in the source directory.
+	set cmd "$LD $LDFLAGS -L$srcdir/$subdir \
+		   $opts(ld) -o $objfile $objfiles"
+
+	send_log "$cmd\n"
+	set cmdret [remote_exec host [concat sh -c [list "$cmd 2>&1"]] "" "/dev/null" "ld.tmp"]
+	remote_upload host "ld.tmp"
+	set comp_output [file_contents "ld.tmp"]
+	remote_file host delete "ld.tmp"
+	remote_file build delete "ld.tmp"
+	set cmdret [lindex $cmdret 0]
+
+	if { $cmdret == 0 && $run_objcopy } {
+	    set infile $objfile
+	    set objfile "tmpdir/dump1"
+	    remote_file host delete $objfile
+
+	    # Note that we don't use OBJCOPYFLAGS here; any flags must be
+	    # explicitly specified.
+	    set cmd "$OBJCOPY $opts(objcopy_linked_file) $infile $objfile"
+
+	    send_log "$cmd\n"
+	    set cmdret [remote_exec host [concat sh -c [list "$cmd 2>&1"]] "" "/dev/null" "ld.tmp"]
+	    remote_upload host "ld.tmp"
+	    append comp_output [file_contents "ld.tmp"]
+	    remote_file host delete "ld.tmp"
+	    remote_file build delete "ld.tmp"
+	    set cmdret [lindex $cmdret 0]
+	}
+
+	regsub "\n$" $comp_output "" comp_output
+	if { $cmdret != 0 || $comp_output != "" || $expmsg != "" } then {
+	    set exitstat "succeeded"
+	    if { $cmdret != 0 } { set exitstat "failed" }
+	    verbose -log "$exitstat with: <$comp_output>, expected: <$expmsg>"
+	    send_log "$comp_output\n"
+	    verbose "$comp_output" 3
+
+	    if { [regexp $expmsg $comp_output] \
+		    && (($cmdret == 0) == ($opts(warning) != "")) } {
+		# We have the expected output from ld.
+		if { $opts(error) != "" || $program == "" } {
+		    pass $testname
+		    return
+		}
+	    } else {
+		verbose -log "$exitstat with: <$comp_output>, expected: <$expmsg>"
+		fail $testname
+		return
+	    }
+	}
+    } else {
+	set objfile "tmpdir/dump0.o"
+    }
+
+    # We must not have expected failure if we get here.
+    if { $opts(error) != "" } {
+	fail $testname
+	return
+    }
+
+    set progopts1 $opts($program)
+    eval set progopts \$[string toupper $program]FLAGS
+    eval set binary \$[string toupper $program]
+
+    if { ![is_remote host] && [which $binary] == 0 } {
+	untested $testname
+	return
+    }
+
+    if { $progopts1 == "" } { set $progopts1 "-r" }
+    verbose "running $binary $progopts $progopts1" 3
+
+    # Objcopy, unlike the other two, won't send its output to stdout,
+    # so we have to run it specially.
+    set cmd "$binary $progopts $progopts1 $objfile > $dumpfile"
+    if { $program == "objcopy" } {
+	set cmd "$binary $progopts $progopts1 $objfile $dumpfile"
+    }
+
+    # Ensure consistent sorting of symbols
+    if {[info exists env(LC_ALL)]} {
+	set old_lc_all $env(LC_ALL)
+    }
+    set env(LC_ALL) "C"
+    send_log "$cmd\n"
+    set cmdret [remote_exec host [concat sh -c [list "$cmd 2>ld.tmp"]] "" "/dev/null"]
+    remote_upload host "ld.tmp"
+    set comp_output [prune_warnings [file_contents "ld.tmp"]]
+    remote_file host delete "ld.tmp"
+    remote_file build delete "ld.tmp"
+    if {[info exists old_lc_all]} {
+	set env(LC_ALL) $old_lc_all
+    } else {
+	unset env(LC_ALL)
+    }
+    if ![string match "" $comp_output] then {
+	send_log "$comp_output\n"
+	fail $testname
+	return
+    }
+
+    verbose_eval {[file_contents $dumpfile]} 3
+    if { [regexp_diff $dumpfile "${file}.d"] } then {
+	fail $testname
+	verbose "output is [file_contents $dumpfile]" 2
+	return
+    }
+
+    pass $testname
+}
+
+proc slurp_options { file } {
+    if [catch { set f [open $file r] } x] {
+	#perror "couldn't open `$file': $x"
+	perror "$x"
+	return -1
+    }
+    set opt_array {}
+    # whitespace expression
+    set ws  {[ 	]*}
+    set nws {[^ 	]*}
+    # whitespace is ignored anywhere except within the options list;
+    # option names are alphabetic plus underscore only.
+    set pat "^#${ws}(\[a-zA-Z_\]*)$ws:${ws}(.*)$ws\$"
+    while { [gets $f line] != -1 } {
+	set line [string trim $line]
+	# Whitespace here is space-tab.
+	if [regexp $pat $line xxx opt_name opt_val] {
+	    # match!
+	    lappend opt_array [list $opt_name $opt_val]
+	} else {
+	    break
+	}
+    }
+    close $f
+    return $opt_array
+}
+
+# regexp_diff, copied from gas, based on simple_diff above.
+#	compares two files line-by-line
+#	file1 contains strings, file2 contains regexps and #-comments
+#	blank lines are ignored in either file
+#	returns non-zero if differences exist
+#
+proc regexp_diff { file_1 file_2 } {
+
+    set eof -1
+    set end_1 0
+    set end_2 0
+    set differences 0
+    set diff_pass 0
+
+    if [file exists $file_1] then {
+	set file_a [open $file_1 r]
+    } else {
+	warning "$file_1 doesn't exist"
+	return 1
+    }
+
+    if [file exists $file_2] then {
+	set file_b [open $file_2 r]
+    } else {
+	fail "$file_2 doesn't exist"
+	close $file_a
+	return 1
+    }
+
+    verbose " Regexp-diff'ing: $file_1 $file_2" 2
+
+    while { 1 } {
+	set line_a ""
+	set line_b ""
+	while { [string length $line_a] == 0 } {
+	    if { [gets $file_a line_a] == $eof } {
+		set end_1 1
+		break
+	    }
+	}
+	while { [string length $line_b] == 0 || [string match "#*" $line_b] } {
+	    if [ string match "#pass" $line_b ] {
+		set end_2 1
+		set diff_pass 1
+		break
+	    } elseif [ string match "#..." $line_b ] {
+		if { [gets $file_b line_b] == $eof } {
+		    set end_2 1
+		    set diff_pass 1
+		    break
+		}
+		verbose "looking for \"^$line_b$\"" 3
+		while { ![regexp "^$line_b$" "$line_a"] } {
+		    verbose "skipping    \"$line_a\"" 3
+		    if { [gets $file_a line_a] == $eof } {
+			set end_1 1
+			break
+		    }
+		}
+		break
+	    }
+	    if { [gets $file_b line_b] == $eof } {
+		set end_2 1
+		break
+	    }
+	}
+
+        if { $diff_pass } {
+            break
+        } elseif { $end_1 && $end_2 } {
+            break
+        } elseif { $end_1 } {
+            send_log "extra regexps in $file_2 starting with \"^$line_b$\"\nEOF from $file_1\n"
+            verbose "extra regexps in $file_2 starting with \"^$line_b$\"\nEOF from $file_1" 3
+            set differences 1
+            break
+        } elseif { $end_2 } {
+            send_log "extra lines in $file_1 starting with \"^$line_a$\"\nEOF from $file_2\n"
+            verbose "extra lines in $file_1 starting with \"^$line_a$\"\nEOF from $file_2\n" 3
+            set differences 1
+            break
+        } else {
+            verbose "regexp \"^$line_b$\"\nline   \"$line_a\"" 3
+            if ![regexp "^$line_b$" "$line_a"] {
+		send_log "regexp_diff match failure\n"
+		send_log "regexp \"^$line_b$\"\nline   \"$line_a\"\n"
+		set differences 1
+            }
+        }
+    }
+
+    if { $differences == 0 && !$diff_pass && [eof $file_a] != [eof $file_b] } {
+	send_log "$file_1 and $file_2 are different lengths\n"
+	verbose "$file_1 and $file_2 are different lengths" 3
+	set differences 1
+    }
+
+    close $file_a
+    close $file_b
+
+    return $differences
+}
+
+proc file_contents { filename } {
+    set file [open $filename r]
+    set contents [read $file]
+    close $file
+    return $contents
+}
+
+# List contains test-items with 3 items followed by 2 lists, one item and
+# one optional item:
+# 0:name 1:ld options 2:assembler options
+# 3:filenames of assembler files 4: action and options. 5: name of output file
+# 6:compiler flags (optional)
+#
+# Actions:
+# objdump: Apply objdump options on result.  Compare with regex (last arg).
+# nm: Apply nm options on result.  Compare with regex (last arg).
+# readelf: Apply readelf options on result.  Compare with regex (last arg).
+#
+proc run_ld_link_tests { ldtests } {
+    global ld
+    global as
+    global nm
+    global objdump
+    global READELF
+    global srcdir
+    global subdir
+    global env
+    global CC
+    global CFLAGS
+
+    foreach testitem $ldtests {
+	set testname [lindex $testitem 0]
+	set ld_options [lindex $testitem 1]
+	set as_options [lindex $testitem 2]
+	set src_files  [lindex $testitem 3]
+	set actions [lindex $testitem 4]
+	set binfile tmpdir/[lindex $testitem 5]
+	set cflags [lindex $testitem 6]
+	set objfiles {}
+	set is_unresolved 0
+	set failed 0
+
+#	verbose -log "Testname is $testname"
+#	verbose -log "ld_options is $ld_options"
+#	verbose -log "as_options is $as_options"
+#	verbose -log "src_files is $src_files"
+#	verbose -log "actions is $actions"
+#	verbose -log "binfile is $binfile"
+
+	# Assemble each file in the test.
+	foreach src_file $src_files {
+	    set objfile "tmpdir/[file rootname $src_file].o"
+	    lappend objfiles $objfile
+
+	    if { [file extension $src_file] == ".c" } {
+		set as_file "tmpdir/[file rootname $src_file].s"
+		if ![ld_compile "$CC -S $CFLAGS $cflags" $srcdir/$subdir/$src_file $as_file] {
+		    set is_unresolved 1
+		    break
+		}
+	    } else {
+		set as_file "$srcdir/$subdir/$src_file"
+	    }
+	    if ![ld_assemble $as "$as_options $as_file" $objfile] {
+		set is_unresolved 1
+		break
+	    }
+	}
+
+	# Catch assembler errors.
+	if { $is_unresolved != 0 } {
+	    unresolved $testname
+	    continue
+	}
+
+	if ![ld_simple_link $ld $binfile "-L$srcdir/$subdir $ld_options $objfiles"] {
+	    fail $testname
+	} else {
+	    set failed 0
+	    foreach actionlist $actions {
+		set action [lindex $actionlist 0]
+		set progopts [lindex $actionlist 1]
+
+		# There are actions where we run regexp_diff on the
+		# output, and there are other actions (presumably).
+		# Handling of the former look the same.
+		set dump_prog ""
+		switch -- $action {
+		    objdump
+		        { set dump_prog $objdump }
+		    nm
+		        { set dump_prog $nm }
+		    readelf
+		        { set dump_prog $READELF }
+		    default
+			{
+			    perror "Unrecognized action $action"
+			    set is_unresolved 1
+			    break
+			}
+		    }
+
+		if { $dump_prog != "" } {
+		    set dumpfile [lindex $actionlist 2]
+		    set binary $dump_prog
+
+		    # Ensure consistent sorting of symbols
+		    if {[info exists env(LC_ALL)]} {
+			set old_lc_all $env(LC_ALL)
+		    }
+		    set env(LC_ALL) "C"
+		    set cmd "$binary $progopts $binfile"
+    		    set status [remote_exec host [concat sh -c [list "$cmd >dump.out 2>ld.stderr"]] "" "/dev/null"]
+		    send_log "$cmd\n"
+    		    remote_upload host "ld.stderr"
+    		    set comp_output [prune_warnings [file_contents "ld.stderr"]]
+    		    remote_file host delete "ld.stderr"
+    		    remote_file build delete "ld.stderr"
+                    
+		    if {[info exists old_lc_all]} {
+			set env(LC_ALL) $old_lc_all
+		    } else {
+			unset env(LC_ALL)
+		    }
+
+		    if ![string match "" $comp_output] then {
+			send_log "$comp_output\n"
+			set failed 1
+			break
+		    }
+
+		    remote_upload host "dump.out"
+
+		    if { [regexp_diff "dump.out" "$srcdir/$subdir/$dumpfile"] } then {
+			verbose "output is [file_contents "dump.out"]" 2
+			set failed 1
+		   	remote_file build delete "dump.out"
+		   	remote_file host delete "dump.out"
+			break
+		    }
+		    remote_file build delete "dump.out"
+		    remote_file host delete "dump.out"
+		}
+	    }
+
+	    if { $failed != 0 } {
+		fail $testname
+	    } else { if { $is_unresolved == 0 } {
+		pass $testname
+	    } }
+	}
+
+	# Catch action errors.
+	if { $is_unresolved != 0 } {
+	    unresolved $testname
+	    continue
+	}
+    }
+}
+
+
+proc verbose_eval { expr { level 1 } } {
+    global verbose
+    if $verbose>$level then { eval verbose "$expr" $level }
+}
+
+# This definition is taken from an unreleased version of DejaGnu.  Once
+# that version gets released, and has been out in the world for a few
+# months at least, it may be safe to delete this copy.
+if ![string length [info proc prune_warnings]] {
+    #
+    # prune_warnings -- delete various system verbosities from TEXT
+    #
+    # An example is:
+    # ld.so: warning: /usr/lib/libc.so.1.8.1 has older revision than expected 9
+    #
+    # Sites with particular verbose os's may wish to override this in site.exp.
+    #
+    proc prune_warnings { text } {
+	# This is from sun4's.  Do it for all machines for now.
+	# The "\\1" is to try to preserve a "\n" but only if necessary.
+	regsub -all "(^|\n)(ld.so: warning:\[^\n\]*\n?)+" $text "\\1" text
+
+	# It might be tempting to get carried away and delete blank lines, etc.
+	# Just delete *exactly* what we're ask to, and that's it.
+	return $text
+    }
+}
+
+# targets_to_xfail is a list of target triplets to be xfailed.
+# ldtests contains test-items with 3 items followed by 1 lists, 2 items
+# and 3 optional items:
+#   0:name
+#   1:ld options
+#   2:assembler options
+#   3:filenames of source files
+#   4:name of output file
+#   5:expected output
+#   6:compiler flags (optional)
+#   7:language (optional)
+#   8:linker warning (optional)
+
+proc run_ld_link_exec_tests { targets_to_xfail ldtests } {
+    global ld
+    global as
+    global srcdir
+    global subdir
+    global env
+    global CC
+    global CXX
+    global CFLAGS
+    global CXXFLAGS
+    global errcnt
+    global exec_output
+
+    foreach testitem $ldtests {
+	foreach target $targets_to_xfail {
+	    setup_xfail $target
+	}
+	set testname [lindex $testitem 0]
+	set ld_options [lindex $testitem 1]
+	set as_options [lindex $testitem 2]
+	set src_files  [lindex $testitem 3]
+	set binfile tmpdir/[lindex $testitem 4]
+	set expfile [lindex $testitem 5]
+	set cflags [lindex $testitem 6]
+	set lang [lindex $testitem 7]
+	set warning [lindex $testitem 8]
+	set objfiles {}
+	set failed 0
+
+#	verbose -log "Testname is $testname"
+#	verbose -log "ld_options is $ld_options"
+#	verbose -log "as_options is $as_options"
+#	verbose -log "src_files is $src_files"
+#	verbose -log "actions is $actions"
+#	verbose -log "binfile is $binfile"
+
+	# Assemble each file in the test.
+	foreach src_file $src_files {
+	    set objfile "tmpdir/[file rootname $src_file].o"
+	    lappend objfiles $objfile
+
+	    # We ignore warnings since some compilers may generate
+	    # incorrect section attributes and the assembler will warn
+	    # them.
+	    if { [ string match "c++" $lang ] } {
+		ld_compile "$CXX -c $CXXFLAGS $cflags" $srcdir/$subdir/$src_file $objfile
+	    } else {
+		ld_compile "$CC -c $CFLAGS $cflags" $srcdir/$subdir/$src_file $objfile
+	    }
+
+	    # We have to use $CC to build PIE and shared library.
+	    if { [ string match "c" $lang ] } {
+		set link_proc ld_simple_link
+		set link_cmd $CC
+	    } elseif { [ string match "c++" $lang ] } {
+		set link_proc ld_simple_link
+		set link_cmd $CXX
+	    } elseif { [ string match "-shared" $ld_options ] \
+		 || [ string match "-pie" $ld_options ] } {
+		set link_proc ld_simple_link
+		set link_cmd $CC
+	    } else {
+		set link_proc ld_link
+		set link_cmd $ld
+	    }
+
+	    if ![$link_proc $link_cmd $binfile "-L$srcdir/$subdir $ld_options $objfiles"] {
+		set failed 1
+	    } else {
+		set failed 0
+	    }
+
+	    # Check if exec_output is expected.
+	    if { $warning != "" } then {
+		verbose -log "returned with: <$exec_output>, expected: <$warning>"
+		if { [regexp $warning $exec_output] } then {
+		    set failed 0
+		} else {
+		    set failed 1
+		}
+	    }
+
+	    if { $failed == 0 } {
+		send_log "Running: $binfile > $binfile.out\n"
+		verbose "Running: $binfile > $binfile.out"
+		catch "exec $binfile > $binfile.out" exec_output
+	    
+		if ![string match "" $exec_output] then {
+		    send_log "$exec_output\n"
+		    verbose "$exec_output" 1
+		    set failed 1
+		} else {
+		    send_log "diff $binfile.out $srcdir/$subdir/$expfile\n"
+		    verbose "diff $binfile.out $srcdir/$subdir/$expfile"
+		    catch "exec diff $binfile.out $srcdir/$subdir/$expfile" exec_output
+		    set exec_output [prune_warnings $exec_output]
+
+		    if ![string match "" $exec_output] then {
+			send_log "$exec_output\n"
+			verbose "$exec_output" 1
+			set failed 1
+		    }
+		}
+	    }
+
+	    if { $failed != 0 } {
+		fail $testname
+	    } else {
+		set errcnt 0
+		pass $testname
+	    }
+	}
+    }
+}
+
+# List contains test-items with 3 items followed by 2 lists, one item and
+# one optional item:
+#  0:name
+#  1:link options
+#  2:compile options
+#  3:filenames of source files
+#  4:action and options.
+#  5:name of output file
+#  6:language (optional)
+#
+# Actions:
+# objdump: Apply objdump options on result.  Compare with regex (last arg).
+# nm: Apply nm options on result.  Compare with regex (last arg).
+# readelf: Apply readelf options on result.  Compare with regex (last arg).
+#
+proc run_cc_link_tests { ldtests } {
+    global nm
+    global objdump
+    global READELF
+    global srcdir
+    global subdir
+    global env
+    global CC
+    global CXX
+    global CFLAGS
+    global CXXFLAGS
+
+    foreach testitem $ldtests {
+	set testname [lindex $testitem 0]
+	set ldflags [lindex $testitem 1]
+	set cflags [lindex $testitem 2]
+	set src_files  [lindex $testitem 3]
+	set actions [lindex $testitem 4]
+	set binfile tmpdir/[lindex $testitem 5]
+	set lang [lindex $testitem 6]
+	set objfiles {}
+	set is_unresolved 0
+	set failed 0
+
+	# Compile each file in the test.
+	foreach src_file $src_files {
+	    set objfile "tmpdir/[file rootname $src_file].o"
+	    lappend objfiles $objfile
+
+	    # We ignore warnings since some compilers may generate
+	    # incorrect section attributes and the assembler will warn
+	    # them.
+	    if { [ string match "c++" $lang ] } {
+		ld_compile "$CXX -c $CXXFLAGS $cflags" $srcdir/$subdir/$src_file $objfile
+	    } else {
+		ld_compile "$CC -c $CFLAGS $cflags" $srcdir/$subdir/$src_file $objfile
+	    }
+	}
+
+	# Clear error and warning counts.
+	reset_vars
+
+	if { [ string match "c++" $lang ] } {
+	    set cc_cmd $CXX
+	} else {
+	    set cc_cmd $CC
+	}
+
+	if ![ld_simple_link $cc_cmd $binfile "-L$srcdir/$subdir $ldflags $objfiles"] {
+	    fail $testname
+	} else {
+	    set failed 0
+	    foreach actionlist $actions {
+		set action [lindex $actionlist 0]
+		set progopts [lindex $actionlist 1]
+
+		# There are actions where we run regexp_diff on the
+		# output, and there are other actions (presumably).
+		# Handling of the former look the same.
+		set dump_prog ""
+		switch -- $action {
+		    objdump
+		        { set dump_prog $objdump }
+		    nm
+		        { set dump_prog $nm }
+		    readelf
+		        { set dump_prog $READELF }
+		    default
+			{
+			    perror "Unrecognized action $action"
+			    set is_unresolved 1
+			    break
+			}
+		    }
+
+		if { $dump_prog != "" } {
+		    set dumpfile [lindex $actionlist 2]
+		    set binary $dump_prog
+
+		    # Ensure consistent sorting of symbols
+		    if {[info exists env(LC_ALL)]} {
+			set old_lc_all $env(LC_ALL)
+		    }
+		    set env(LC_ALL) "C"
+		    set cmd "$binary $progopts $binfile > dump.out"
+		    send_log "$cmd\n"
+		    catch "exec $cmd" comp_output
+		    if {[info exists old_lc_all]} {
+			set env(LC_ALL) $old_lc_all
+		    } else {
+			unset env(LC_ALL)
+		    }
+		    set comp_output [prune_warnings $comp_output]
+
+		    if ![string match "" $comp_output] then {
+			send_log "$comp_output\n"
+			set failed 1
+			break
+		    }
+
+		    if { [regexp_diff "dump.out" "$srcdir/$subdir/$dumpfile"] } then {
+			verbose "output is [file_contents "dump.out"]" 2
+			set failed 1
+			break
+		    }
+		}
+	    }
+
+	    if { $failed != 0 } {
+		fail $testname
+	    } else { if { $is_unresolved == 0 } {
+		pass $testname
+	    } }
+	}
+
+	# Catch action errors.
+	if { $is_unresolved != 0 } {
+	    unresolved $testname
+	    continue
+	}
+    }
+}
+
+# Returns true if --gc-sections is supported on the target.
+
+proc check_gc_sections_available { } {
+    global gc_sections_available_saved
+    global ld
+    
+    if {![info exists gc_sections_available_saved]} {
+	# Some targets don't support gc-sections despite whatever's
+	# advertised by ld's options.
+	if { [istarget alpha*-*-*]
+	     || [istarget ia64-*-*] } {
+	    set gc_sections_available_saved 0
+	    return 0
+	}
+
+	# elf2flt uses -q (--emit-relocs), which is incompatible with
+	# --gc-sections.
+	if { [board_info target exists ldflags]
+	     && [regexp " -elf2flt\[ =\]" " [board_info target ldflags] "] } {
+	    set gc_sections_available_saved 0
+	    return 0
+	}
+
+	# Check if the ld used by gcc supports --gc-sections.
+	set ld_output [remote_exec host $ld "--help"]
+	if { [ string first "--gc-sections" $ld_output ] >= 0 } {
+	    set gc_sections_available_saved 1
+	} else {
+	    set gc_sections_available_saved 0
+	}
+    }
+    return $gc_sections_available_saved
+}
+
+# Check if the assembler supports CFI statements.
+
+proc check_as_cfi { } {
+    global check_as_cfi_result
+    global as
+    if [info exists check_as_cfi_result] {
+	return $check_as_cfi_result
+    }
+    set as_file "tmpdir/check_as_cfi.s"
+    set as_fh [open $as_file w 0666]
+    puts $as_fh "# Generated file. DO NOT EDIT"
+    puts $as_fh "\t.cfi_startproc"
+    puts $as_fh "\t.cfi_endproc"
+    close $as_fh
+    remote_download host $as_file
+    verbose -log "Checking CFI support:"
+    rename "perror" "check_as_cfi_perror"
+    proc perror { args } { }
+    set success [ld_assemble $as $as_file "/dev/null"]
+    rename "perror" ""
+    rename "check_as_cfi_perror" "perror"
+    #remote_file host delete $as_file
+    set check_as_cfi_result $success
+    return $success
+}
+
+# Provide virtual target "cfi" for targets supporting CFI.
+
+rename "istarget" "istarget_ld"
+proc istarget { target } {
+    if {$target == "cfi"} {
+	return [check_as_cfi]
+    }
+    return [istarget_ld $target]
+}