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author | Jing Yu <jingyu@google.com> | 2011-12-20 10:27:58 -0800 |
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committer | Jing Yu <jingyu@google.com> | 2011-12-20 10:27:58 -0800 |
commit | cf3cdbf8b3cda61a619299e7966a83df66244036 (patch) | |
tree | 201e2bcfc955f16802d3257112d29736cb3a3ce8 /binutils-2.21/ld/testsuite/ld-alpha/tlspic.dd | |
parent | e4df3e0a5bb640ccfa2f30ee67fe9b3146b152d6 (diff) | |
download | toolchain_binutils-cf3cdbf8b3cda61a619299e7966a83df66244036.zip toolchain_binutils-cf3cdbf8b3cda61a619299e7966a83df66244036.tar.gz toolchain_binutils-cf3cdbf8b3cda61a619299e7966a83df66244036.tar.bz2 |
Add binutils-2.21.
Use --enable-gold=default for dual linker support.
Change-Id: Id1a744c7db58a0b5e7a3be174cdfa875f2f86e49
Diffstat (limited to 'binutils-2.21/ld/testsuite/ld-alpha/tlspic.dd')
-rw-r--r-- | binutils-2.21/ld/testsuite/ld-alpha/tlspic.dd | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/binutils-2.21/ld/testsuite/ld-alpha/tlspic.dd b/binutils-2.21/ld/testsuite/ld-alpha/tlspic.dd new file mode 100644 index 0000000..63f150c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-alpha/tlspic.dd @@ -0,0 +1,56 @@ +#source: align.s +#source: tlspic1.s +#source: tlspic2.s +#as: +#ld: -shared -melf64alpha +#objdump: -drj.text +#target: alpha*-*-* + +.*: +file format elf64-alpha + +Disassembly of section .text: + +0+1000 <fn1>: + 1000: 02 00 bb 27 ldah gp,2\(t12\) + 1004: a0 82 bd 23 lda gp,-32096\(gp\) + 1008: 3e 15 c2 43 subq sp,0x10,sp + 100c: 00 00 5e b7 stq ra,0\(sp\) + 1010: 08 00 3e b5 stq s0,8\(sp\) + 1014: 9e 00 00 00 rduniq + 1018: 09 04 e0 47 mov v0,s0 + 101c: 08 80 1d 22 lda a0,-32760\(gp\) + 1020: 00 80 7d a7 ldq t12,-32768\(gp\) + 1024: 00 40 5b 6b jsr ra,\(t12\),1028 <.*> + 1028: 02 00 ba 27 ldah gp,2\(ra\) + 102c: 78 82 bd 23 lda gp,-32136\(gp\) + 1030: 30 80 1d 22 lda a0,-32720\(gp\) + 1034: 00 80 7d a7 ldq t12,-32768\(gp\) + 1038: 00 40 5b 6b jsr ra,\(t12\),103c <.*> + 103c: 02 00 ba 27 ldah gp,2\(ra\) + 1040: 64 82 bd 23 lda gp,-32156\(gp\) + 1044: 40 80 1d 22 lda a0,-32704\(gp\) + 1048: 00 80 7d a7 ldq t12,-32768\(gp\) + 104c: 00 40 5b 6b jsr ra,\(t12\),1050 <.*> + 1050: 02 00 ba 27 ldah gp,2\(ra\) + 1054: 50 82 bd 23 lda gp,-32176\(gp\) + 1058: 21 00 20 20 lda t0,33\(v0\) + 105c: 40 80 1d 22 lda a0,-32704\(gp\) + 1060: 00 80 7d a7 ldq t12,-32768\(gp\) + 1064: 00 40 5b 6b jsr ra,\(t12\),1068 <.*> + 1068: 02 00 ba 27 ldah gp,2\(ra\) + 106c: 38 82 bd 23 lda gp,-32200\(gp\) + 1070: 40 00 20 20 lda t0,64\(v0\) + 1074: 62 00 20 20 lda t0,98\(v0\) + 1078: 00 00 20 24 ldah t0,0\(v0\) + 107c: 53 00 21 20 lda t0,83\(t0\) + 1080: 18 80 3d a4 ldq t0,-32744\(gp\) + 1084: 01 04 20 40 addq t0,v0,t0 + 1088: 20 80 3d a4 ldq t0,-32736\(gp\) + 108c: 01 04 29 40 addq t0,s0,t0 + 1090: 50 80 3d a4 ldq t0,-32688\(gp\) + 1094: 28 80 5d a4 ldq t1,-32728\(gp\) + 1098: 01 04 29 40 addq t0,s0,t0 + 109c: 02 04 49 40 addq t1,s0,t1 + 10a0: 00 00 5e a7 ldq ra,0\(sp\) + 10a4: 1e 14 c2 43 addq sp,0x10,sp + 10a8: 01 80 fa 6b ret |