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author | Jing Yu <jingyu@google.com> | 2011-12-20 10:27:58 -0800 |
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committer | Jing Yu <jingyu@google.com> | 2011-12-20 10:27:58 -0800 |
commit | cf3cdbf8b3cda61a619299e7966a83df66244036 (patch) | |
tree | 201e2bcfc955f16802d3257112d29736cb3a3ce8 /binutils-2.21/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd | |
parent | e4df3e0a5bb640ccfa2f30ee67fe9b3146b152d6 (diff) | |
download | toolchain_binutils-cf3cdbf8b3cda61a619299e7966a83df66244036.zip toolchain_binutils-cf3cdbf8b3cda61a619299e7966a83df66244036.tar.gz toolchain_binutils-cf3cdbf8b3cda61a619299e7966a83df66244036.tar.bz2 |
Add binutils-2.21.
Use --enable-gold=default for dual linker support.
Change-Id: Id1a744c7db58a0b5e7a3be174cdfa875f2f86e49
Diffstat (limited to 'binutils-2.21/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd')
-rw-r--r-- | binutils-2.21/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd | 101 |
1 files changed, 101 insertions, 0 deletions
diff --git a/binutils-2.21/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd b/binutils-2.21/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd new file mode 100644 index 0000000..1e0dbcb --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd @@ -0,0 +1,101 @@ +# GOT layout: +# +# -32752: lazy resolution function +# -32748: reserved for module pointer +# -32744: extf2's GOT entry (undefined 0) +# -32740: extf3's GOT entry (PLT entry) +# -32736: extd2's GOT entry (copy reloc) +# -32732: extf1's GOT entry (.MIPS.stubs entry) +# -32728: extd1's GOT entry (undefined 0) +# -32724: extf4's GOT entry (PLT entry) +# -32620: extd4's GOT entry (undefined 0, reloc only) + +.* + +Disassembly of section \.plt: + +00043040 <.*>: +.*: 3c0e0008 lui t2,0x8 +.*: 8dd91000 lw t9,4096\(t2\) +.*: 25ce1000 addiu t2,t2,4096 +.*: 030ec023 subu t8,t8,t2 +.*: 03e07821 move t3,ra +.*: 0018c082 srl t8,t8,0x2 +.*: 0320f809 jalr t9 +.*: 2718fffe addiu t8,t8,-2 + +00043060 <extf4@plt>: +.*: 3c0f0008 lui t3,0x8 +.*: 8df91008 lw t9,4104\(t3\) +.*: 03200008 jr t9 +.*: 25f81008 addiu t8,t3,4104 + +00043070 <extf5@plt>: +.*: 3c0f0008 lui t3,0x8 +.*: 8df9100c lw t9,4108\(t3\) +.*: 03200008 jr t9 +.*: 25f8100c addiu t8,t3,4108 + +00043080 <extf3@plt>: +.*: 3c0f0008 lui t3,0x8 +.*: 8df91010 lw t9,4112\(t3\) +.*: 03200008 jr t9 +.*: 25f81010 addiu t8,t3,4112 + +Disassembly of section \.text: + +00044000 <.*>: + \.\.\. + +00044008 <\.pic\.f1>: + 44008: 3c190004 lui t9,0x4 + 4400c: 27394010 addiu t9,t9,16400 + +00044010 <f1>: + 44010: 0c011013 jal 4404c <f3> + 44014: 3c020004 lui v0,0x4 + 44018: 03e00008 jr ra + 4401c: 24424020 addiu v0,v0,16416 + +00044020 <f2>: + 44020: 3c1c0006 lui gp,0x6 + 44024: 0399e021 addu gp,gp,t9 + 44028: 279c3fd0 addiu gp,gp,16336 + 4402c: 8f998024 lw t9,-32732\(gp\) + 44030: 8f848018 lw a0,-32744\(gp\) + 44034: 8f858028 lw a1,-32728\(gp\) + 44038: 0320f809 jalr t9 + 4403c: 8f868020 lw a2,-32736\(gp\) + 44040: 8f99801c lw t9,-32740\(gp\) + 44044: 03200008 jr t9 + 44048: 8f84802c lw a0,-32724\(gp\) + +0004404c <f3>: + 4404c: 03e00008 jr ra + 44050: 00000000 nop + \.\.\. + +00044060 <__start>: + 44060: 0c011002 jal 44008 <\.pic\.f1> + 44064: 00000000 nop + 44068: 3c020004 lui v0,0x4 + 4406c: 24424020 addiu v0,v0,16416 + 44070: 0c010c20 jal 43080 <extf3@plt> + 44074: 00000000 nop + 44078: 0c010c18 jal 43060 <extf4@plt> + 4407c: 00000000 nop + 44080: 0c010c1c jal 43070 <extf5@plt> + 44084: 00000000 nop + 44088: 3c02000a lui v0,0xa + 4408c: 24422000 addiu v0,v0,8192 + 44090: 3c02000a lui v0,0xa + 44094: 24422018 addiu v0,v0,8216 + \.\.\. +Disassembly of section \.MIPS\.stubs: + +000440a0 <\.MIPS\.stubs>: + 440a0: 8f998010 lw t9,-32752\(gp\) + 440a4: 03e07821 move t3,ra + 440a8: 0320f809 jalr t9 + 440ac: 2418000a li t8,10 + \.\.\. |