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| author | Jing Yu <jingyu@google.com> | 2011-12-20 10:27:58 -0800 |
|---|---|---|
| committer | Jing Yu <jingyu@google.com> | 2011-12-20 10:27:58 -0800 |
| commit | cf3cdbf8b3cda61a619299e7966a83df66244036 (patch) | |
| tree | 201e2bcfc955f16802d3257112d29736cb3a3ce8 /binutils-2.21/ld/testsuite/ld-sh | |
| parent | e4df3e0a5bb640ccfa2f30ee67fe9b3146b152d6 (diff) | |
| download | toolchain_binutils-cf3cdbf8b3cda61a619299e7966a83df66244036.zip toolchain_binutils-cf3cdbf8b3cda61a619299e7966a83df66244036.tar.gz toolchain_binutils-cf3cdbf8b3cda61a619299e7966a83df66244036.tar.bz2 | |
Add binutils-2.21.
Use --enable-gold=default for dual linker support.
Change-Id: Id1a744c7db58a0b5e7a3be174cdfa875f2f86e49
Diffstat (limited to 'binutils-2.21/ld/testsuite/ld-sh')
201 files changed, 13045 insertions, 0 deletions
diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/arch.exp b/binutils-2.21/ld/testsuite/ld-sh/arch/arch.exp new file mode 100644 index 0000000..acc322e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/arch.exp @@ -0,0 +1,257 @@ +# Copyright (C) 2004, 2005, 2006, 2007, 2008 +# Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. + + +# Please email any bugs, comments, and/or additions to this file to: +# binutils@sources.redhat.com + +# This scripts tests of all available SH architectures with all other SH +# architectures. It ensures that those combinations which should not work +# do not work, and that those that should work produce the correct output +# architecture. +# +# It looks for files in the same directory as this file named sh*.s . +# Each file must contain one or more instructions which uniquely identifies +# that architecture. The architecture name is inferred from the file name. +# It is best to use the same files used by the assembler testsuite. +# +# It also creates another architecture named 'sh-unknown' by modifying +# another arch type (there is no way to assemble such an arch) in order +# to test what the linker would do with an older object file. +# +# The script generates the architecture permutations automatically, +# but it reads the expected results from the file arch_expected.txt (also +# found in the same directory as this script). +# +# The arch_expected.txt file should NOT be hand edited. Whenever the script +# is run (e.g. with 'make check') it creates a new (usually identical) file +# named arch_results.txt in the <objdir>/ld/testsuite directory. When the +# expected results change (or new architectures are added) this new file +# can be used to replace arch_expected.txt with no modification required. + + +# The procedure extracts the architecture name from the objdump output. +# If there is no architecture name (or objdump output changes significantly) +# then the behaviour is undefined, but it will most likely return junk. + +proc get_sh_arch { ofile } { + global OBJDUMP + + set cmd "$OBJDUMP -f $ofile" + verbose -log $cmd + catch "exec $cmd" objdump_output + verbose -log $objdump_output + + set objdump_output [string replace $objdump_output 0 \ + [expr [string first "architecture:" $objdump_output] + 13] ""] + + return [string range $objdump_output 0 [expr [string first "," $objdump_output] - 1]] +} + + +# This procedure runs two tests: +# Test 1: Check the linker can link the given files. +# Test 2: Check that the resultant architecture is as expected. +# It also writes an entry to the arch_results.txt file. + +proc test_arch { file1 file2 arch resultfile } { + global LD + + set name1 [file tail $file1] + set rootname1 [file rootname $name1] + + set name2 [file tail $file2] + set rootname2 [file rootname $name2] + + set flags [big_or_little_endian] + + # This must use -r to prevent LD trying to relocate the (unrealistic) file + send_log "$LD $flags -r -o ${rootname1}_${rootname2}.o $file1 $file2\n" + catch "exec $LD $flags -r -o ${rootname1}_${rootname2}.o $file1 $file2" ld_output + send_log $ld_output + + if {[string equal $ld_output ""] == 1} then { + pass "$rootname1 file should link with $rootname2 file" + + set result [get_sh_arch "${rootname1}_${rootname2}.o"] + puts $resultfile [format "%-20s %-20s %s" $file1 $file2 $result] + + if {$result == $arch} then { + pass "$rootname1 file with $rootname2 file should link to arch $arch" + file delete "${rootname1}_${rootname2}.o" + } else { + fail "$rootname1 file with $rootname2 file should link to arch $arch" + } + } else { + fail "$rootname1 file should link with $rootname2 file" + + puts $resultfile [format "%-20s %-20s ERROR" $file1 $file2] + untested "$rootname2 file with $rootname2 file should link to arch $arch" + } + +} + + + +# This procedure tests that a pair of files that are not +# suposed to link does, in fact, not link. +# It also writes an entry to the arch_results.txt file. + +proc test_arch_error { file1 file2 resultfile} { + global link_output LD + + set name1 [file tail $file1] + set rootname1 [file rootname $name1] + + set name2 [file tail $file2] + set rootname2 [file rootname $name2] + + # This must use -r to prevent LD trying to relocate the (unrealistic) file + send_log "$LD -r -o ${rootname1}_${rootname2}.o $file1 $file2\n" + catch "exec $LD -r -o ${rootname1}_${rootname2}.o $file1 $file2" ld_output + send_log $ld_output + + if {[string equal $ld_output ""] == 1} then { + fail "$rootname1 file should NOT link with $rootname2 file" + puts $resultfile [format "%-20s %-20s [get_sh_arch ${rootname1}_${rootname2}.o]" $file1 $file2] + } else { + pass "$rootname1 file should NOT link with $rootname2 file" + puts $resultfile [format "%-20s %-20s ERROR" $file1 $file2] + } +} + +# These tests are not suitable for sh-coff because +# coff does not store the architecture information. + +if [istarget sh*-*-elf] then { + global subdir srcdir + global AS + + # Find all the architectures and assemble all the files + # we will use for the linker tests. + + set sfilelist [lsort -ascii [glob "$srcdir/$subdir/sh*.s"]] + set ofilelist {} + foreach sfile $sfilelist { + set ofile "[file rootname [file tail $sfile]].o" + lappend ofilelist $ofile + + set endian "-big" + if [string equal [big_or_little_endian] " -EL"] then { + set endian "-little" + } + + set cmd "$AS $endian -isa=any $sfile -o $ofile" + verbose -log $cmd + catch "exec $cmd" as_output + if ![file exists $ofile] then { + verbose -log $as_output + perror "$sfile: assembly failed" + } + } + + # Create the default arch ofile + # This cannot be created with the assembler + # sh4al-dsp is number 6, sh-unknown is 0 + + lappend ofilelist "sh-unknown.o" + + if [string equal [big_or_little_endian] " -EL"] then { + set cmd {xxd sh4al-dsp.o | sed {s/\(^0000020: .... .... \)06/\100/} | xxd -r - sh-unknown.o} + } else { + set cmd {xxd sh4al-dsp.o | sed {s/\(^0000020: .... .... .... ..\)06/\100/} | xxd -r - sh-unknown.o} + } + verbose -log $cmd + catch "exec $cmd" xxd_output + verbose -log $xxd_output + if [string equal [get_sh_arch "sh-unknown.o"] "sh4al-dsp"] then { + perror "sh-unknown.o not generated correctly" + } + + + # Initialise the results file + + set outfile [open "arch_results.txt" w 0666] + puts $outfile "# Generated file. DO NOT EDIT" + puts $outfile "#" + puts $outfile "# This file is generated by ld/testsuite/ld-sh/arch/arch.exp ." + puts $outfile "# It contains the expected results of the tests." + puts $outfile "# If the tests are failing because the expected results" + puts $outfile "# have changed then run 'make check' and copy the new file" + puts $outfile "# from <objdir>/ld/arch_results.txt" + puts $outfile "# to <srcdir>/ld/testsuite/ld-sh/arch/arch_expected.txt ." + puts $outfile "# Make sure the new expected results are ALL correct." + puts $outfile "#" + puts $outfile [format "# %-18s %-20s %s" "FILE1" "FILE2" "OUTPUT"] + puts $outfile [format "# %-18s %-20s %s" "-----" "-----" "------"] + + # Open the expected results file and skip the header + + set infile [open "$srcdir/$subdir/arch_expected.txt" r] + while {[gets $infile line] >= 0 && [string match {\#*} $line]} {verbose -log "reading '$line'"} + + foreach file1 $ofilelist { + foreach file2 $ofilelist { + set name1 [file tail $file1] + set rootname1 [file rootname $name1] + + set name2 [file tail $file2] + set rootname2 [file rootname $name2] + + # Decode the expected result from the file + + scan $line "%s %s %s" exfile1 exfile2 exarch + verbose -log "exfile1 = '$exfile1', exfile2 = '$exfile2', exarch = '$exarch'" + verbose -log " name1 = '$name1', name2 = '$name2'" + + if {[string equal $exfile1 $name1] && [string equal $exfile2 $file2]} then { + # The expected result file makes sense and + # appears up-to-date (the file and options match) + + if {[string equal $exarch "ERROR"]} then { + test_arch_error $file1 $file2 $outfile + } else { + test_arch $file1 $file2 $exarch $outfile + } + } else { + # The expected result file isn't right somehow + # so just try any old test. This will cause + # many failures, but will genrate the results file. + + test_arch $file1 $file2 $rootname1 $outfile + } + + # Read the next line from the expected result file. + # This is at the end because the process of skipping + # the header reads the first real line + + if [gets $infile line] then { + verbose -log "reading '$line'" + } + } + } + + close $infile + close $outfile + + foreach file $ofilelist { + file delete $file + } +} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/arch_expected.txt b/binutils-2.21/ld/testsuite/ld-sh/arch/arch_expected.txt new file mode 100644 index 0000000..d11c43b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/arch_expected.txt @@ -0,0 +1,453 @@ +# Generated file. DO NOT EDIT +# +# This file is generated by ld/testsuite/ld-sh/arch/arch.exp . +# It contains the expected results of the tests. +# If the tests are failing because the expected results +# have changed then run 'make check' and copy the new file +# from <objdir>/ld/arch_results.txt +# to <srcdir>/ld/testsuite/ld-sh/arch/arch_expected.txt . +# Make sure the new expected results are ALL correct. +# +# FILE1 FILE2 OUTPUT +# ----- ----- ------ +sh-dsp.o sh-dsp.o sh-dsp +sh-dsp.o sh.o sh-dsp +sh-dsp.o sh2.o sh-dsp +sh-dsp.o sh2a-nofpu-or-sh3-nommu.o sh3-dsp +sh-dsp.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp +sh-dsp.o sh2a-nofpu.o ERROR +sh-dsp.o sh2a-or-sh3e.o ERROR +sh-dsp.o sh2a-or-sh4.o ERROR +sh-dsp.o sh2a.o ERROR +sh-dsp.o sh2e.o ERROR +sh-dsp.o sh3-dsp.o sh3-dsp +sh-dsp.o sh3-nommu.o sh3-dsp +sh-dsp.o sh3.o sh3-dsp +sh-dsp.o sh3e.o ERROR +sh-dsp.o sh4-nofpu.o sh4al-dsp +sh-dsp.o sh4-nommu-nofpu.o sh4al-dsp +sh-dsp.o sh4.o ERROR +sh-dsp.o sh4a-nofpu.o sh4al-dsp +sh-dsp.o sh4a.o ERROR +sh-dsp.o sh4al-dsp.o sh4al-dsp +sh-dsp.o sh-unknown.o sh-dsp +sh.o sh-dsp.o sh-dsp +sh.o sh.o sh +sh.o sh2.o sh2 +sh.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu +sh.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu +sh.o sh2a-nofpu.o sh2a-nofpu +sh.o sh2a-or-sh3e.o sh2a-or-sh3e +sh.o sh2a-or-sh4.o sh2a-or-sh4 +sh.o sh2a.o sh2a +sh.o sh2e.o sh2e +sh.o sh3-dsp.o sh3-dsp +sh.o sh3-nommu.o sh3-nommu +sh.o sh3.o sh3 +sh.o sh3e.o sh3e +sh.o sh4-nofpu.o sh4-nofpu +sh.o sh4-nommu-nofpu.o sh4-nommu-nofpu +sh.o sh4.o sh4 +sh.o sh4a-nofpu.o sh4a-nofpu +sh.o sh4a.o sh4a +sh.o sh4al-dsp.o sh4al-dsp +sh.o sh-unknown.o sh +sh2.o sh-dsp.o sh-dsp +sh2.o sh.o sh2 +sh2.o sh2.o sh2 +sh2.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu +sh2.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu +sh2.o sh2a-nofpu.o sh2a-nofpu +sh2.o sh2a-or-sh3e.o sh2a-or-sh3e +sh2.o sh2a-or-sh4.o sh2a-or-sh4 +sh2.o sh2a.o sh2a +sh2.o sh2e.o sh2e +sh2.o sh3-dsp.o sh3-dsp +sh2.o sh3-nommu.o sh3-nommu +sh2.o sh3.o sh3 +sh2.o sh3e.o sh3e +sh2.o sh4-nofpu.o sh4-nofpu +sh2.o sh4-nommu-nofpu.o sh4-nommu-nofpu +sh2.o sh4.o sh4 +sh2.o sh4a-nofpu.o sh4a-nofpu +sh2.o sh4a.o sh4a +sh2.o sh4al-dsp.o sh4al-dsp +sh2.o sh-unknown.o sh2 +sh2a-nofpu-or-sh3-nommu.o sh-dsp.o sh3-dsp +sh2a-nofpu-or-sh3-nommu.o sh.o sh2a-nofpu-or-sh3-nommu +sh2a-nofpu-or-sh3-nommu.o sh2.o sh2a-nofpu-or-sh3-nommu +sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu +sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu +sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu.o sh2a-nofpu +sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh3e.o sh2a-or-sh3e +sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh4.o sh2a-or-sh4 +sh2a-nofpu-or-sh3-nommu.o sh2a.o sh2a +sh2a-nofpu-or-sh3-nommu.o sh2e.o sh2a-or-sh3e +sh2a-nofpu-or-sh3-nommu.o sh3-dsp.o sh3-dsp +sh2a-nofpu-or-sh3-nommu.o sh3-nommu.o sh3-nommu +sh2a-nofpu-or-sh3-nommu.o sh3.o sh3 +sh2a-nofpu-or-sh3-nommu.o sh3e.o sh3e +sh2a-nofpu-or-sh3-nommu.o sh4-nofpu.o sh4-nofpu +sh2a-nofpu-or-sh3-nommu.o sh4-nommu-nofpu.o sh4-nommu-nofpu +sh2a-nofpu-or-sh3-nommu.o sh4.o sh4 +sh2a-nofpu-or-sh3-nommu.o sh4a-nofpu.o sh4a-nofpu +sh2a-nofpu-or-sh3-nommu.o sh4a.o sh4a +sh2a-nofpu-or-sh3-nommu.o sh4al-dsp.o sh4al-dsp +sh2a-nofpu-or-sh3-nommu.o sh-unknown.o sh2a-nofpu-or-sh3-nommu +sh2a-nofpu-or-sh4-nommu-nofpu.o sh-dsp.o sh4al-dsp +sh2a-nofpu-or-sh4-nommu-nofpu.o sh.o sh2a-nofpu-or-sh4-nommu-nofpu +sh2a-nofpu-or-sh4-nommu-nofpu.o sh2.o sh2a-nofpu-or-sh4-nommu-nofpu +sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh4-nommu-nofpu +sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu +sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu.o sh2a-nofpu +sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh3e.o sh2a-or-sh4 +sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4.o sh2a-or-sh4 +sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a.o sh2a +sh2a-nofpu-or-sh4-nommu-nofpu.o sh2e.o sh2a-or-sh4 +sh2a-nofpu-or-sh4-nommu-nofpu.o sh3-dsp.o sh4al-dsp +sh2a-nofpu-or-sh4-nommu-nofpu.o sh3-nommu.o sh4-nommu-nofpu +sh2a-nofpu-or-sh4-nommu-nofpu.o sh3.o sh4-nofpu +sh2a-nofpu-or-sh4-nommu-nofpu.o sh3e.o sh4 +sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nofpu.o sh4-nofpu +sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nommu-nofpu.o sh4-nommu-nofpu +sh2a-nofpu-or-sh4-nommu-nofpu.o sh4.o sh4 +sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a-nofpu.o sh4a-nofpu +sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a.o sh4a +sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp.o sh4al-dsp +sh2a-nofpu-or-sh4-nommu-nofpu.o sh-unknown.o sh2a-nofpu-or-sh4-nommu-nofpu +sh2a-nofpu.o sh-dsp.o ERROR +sh2a-nofpu.o sh.o sh2a-nofpu +sh2a-nofpu.o sh2.o sh2a-nofpu +sh2a-nofpu.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu +sh2a-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu +sh2a-nofpu.o sh2a-nofpu.o sh2a-nofpu +sh2a-nofpu.o sh2a-or-sh3e.o sh2a +sh2a-nofpu.o sh2a-or-sh4.o sh2a +sh2a-nofpu.o sh2a.o sh2a +sh2a-nofpu.o sh2e.o sh2a +sh2a-nofpu.o sh3-dsp.o ERROR +sh2a-nofpu.o sh3-nommu.o ERROR +sh2a-nofpu.o sh3.o ERROR +sh2a-nofpu.o sh3e.o ERROR +sh2a-nofpu.o sh4-nofpu.o ERROR +sh2a-nofpu.o sh4-nommu-nofpu.o ERROR +sh2a-nofpu.o sh4.o ERROR +sh2a-nofpu.o sh4a-nofpu.o ERROR +sh2a-nofpu.o sh4a.o ERROR +sh2a-nofpu.o sh4al-dsp.o ERROR +sh2a-nofpu.o sh-unknown.o sh2a-nofpu +sh2a-or-sh3e.o sh-dsp.o ERROR +sh2a-or-sh3e.o sh.o sh2a-or-sh3e +sh2a-or-sh3e.o sh2.o sh2a-or-sh3e +sh2a-or-sh3e.o sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh3e +sh2a-or-sh3e.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4 +sh2a-or-sh3e.o sh2a-nofpu.o sh2a +sh2a-or-sh3e.o sh2a-or-sh3e.o sh2a-or-sh3e +sh2a-or-sh3e.o sh2a-or-sh4.o sh2a-or-sh4 +sh2a-or-sh3e.o sh2a.o sh2a +sh2a-or-sh3e.o sh2e.o sh2a-or-sh3e +sh2a-or-sh3e.o sh3-dsp.o ERROR +sh2a-or-sh3e.o sh3-nommu.o sh3e +sh2a-or-sh3e.o sh3.o sh3e +sh2a-or-sh3e.o sh3e.o sh3e +sh2a-or-sh3e.o sh4-nofpu.o sh4 +sh2a-or-sh3e.o sh4-nommu-nofpu.o sh4 +sh2a-or-sh3e.o sh4.o sh4 +sh2a-or-sh3e.o sh4a-nofpu.o sh4a +sh2a-or-sh3e.o sh4a.o sh4a +sh2a-or-sh3e.o sh4al-dsp.o ERROR +sh2a-or-sh3e.o sh-unknown.o sh2a-or-sh3e +sh2a-or-sh4.o sh-dsp.o ERROR +sh2a-or-sh4.o sh.o sh2a-or-sh4 +sh2a-or-sh4.o sh2.o sh2a-or-sh4 +sh2a-or-sh4.o sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh4 +sh2a-or-sh4.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4 +sh2a-or-sh4.o sh2a-nofpu.o sh2a +sh2a-or-sh4.o sh2a-or-sh3e.o sh2a-or-sh4 +sh2a-or-sh4.o sh2a-or-sh4.o sh2a-or-sh4 +sh2a-or-sh4.o sh2a.o sh2a +sh2a-or-sh4.o sh2e.o sh2a-or-sh4 +sh2a-or-sh4.o sh3-dsp.o ERROR +sh2a-or-sh4.o sh3-nommu.o sh4 +sh2a-or-sh4.o sh3.o sh4 +sh2a-or-sh4.o sh3e.o sh4 +sh2a-or-sh4.o sh4-nofpu.o sh4 +sh2a-or-sh4.o sh4-nommu-nofpu.o sh4 +sh2a-or-sh4.o sh4.o sh4 +sh2a-or-sh4.o sh4a-nofpu.o sh4a +sh2a-or-sh4.o sh4a.o sh4a +sh2a-or-sh4.o sh4al-dsp.o ERROR +sh2a-or-sh4.o sh-unknown.o sh2a-or-sh4 +sh2a.o sh-dsp.o ERROR +sh2a.o sh.o sh2a +sh2a.o sh2.o sh2a +sh2a.o sh2a-nofpu-or-sh3-nommu.o sh2a +sh2a.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a +sh2a.o sh2a-nofpu.o sh2a +sh2a.o sh2a-or-sh3e.o sh2a +sh2a.o sh2a-or-sh4.o sh2a +sh2a.o sh2a.o sh2a +sh2a.o sh2e.o sh2a +sh2a.o sh3-dsp.o ERROR +sh2a.o sh3-nommu.o ERROR +sh2a.o sh3.o ERROR +sh2a.o sh3e.o ERROR +sh2a.o sh4-nofpu.o ERROR +sh2a.o sh4-nommu-nofpu.o ERROR +sh2a.o sh4.o ERROR +sh2a.o sh4a-nofpu.o ERROR +sh2a.o sh4a.o ERROR +sh2a.o sh4al-dsp.o ERROR +sh2a.o sh-unknown.o sh2a +sh2e.o sh-dsp.o ERROR +sh2e.o sh.o sh2e +sh2e.o sh2.o sh2e +sh2e.o sh2a-nofpu-or-sh3-nommu.o sh2a-or-sh3e +sh2e.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-or-sh4 +sh2e.o sh2a-nofpu.o sh2a +sh2e.o sh2a-or-sh3e.o sh2a-or-sh3e +sh2e.o sh2a-or-sh4.o sh2a-or-sh4 +sh2e.o sh2a.o sh2a +sh2e.o sh2e.o sh2e +sh2e.o sh3-dsp.o ERROR +sh2e.o sh3-nommu.o sh3e +sh2e.o sh3.o sh3e +sh2e.o sh3e.o sh3e +sh2e.o sh4-nofpu.o sh4 +sh2e.o sh4-nommu-nofpu.o sh4 +sh2e.o sh4.o sh4 +sh2e.o sh4a-nofpu.o sh4a +sh2e.o sh4a.o sh4a +sh2e.o sh4al-dsp.o ERROR +sh2e.o sh-unknown.o sh2e +sh3-dsp.o sh-dsp.o sh3-dsp +sh3-dsp.o sh.o sh3-dsp +sh3-dsp.o sh2.o sh3-dsp +sh3-dsp.o sh2a-nofpu-or-sh3-nommu.o sh3-dsp +sh3-dsp.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp +sh3-dsp.o sh2a-nofpu.o ERROR +sh3-dsp.o sh2a-or-sh3e.o ERROR +sh3-dsp.o sh2a-or-sh4.o ERROR +sh3-dsp.o sh2a.o ERROR +sh3-dsp.o sh2e.o ERROR +sh3-dsp.o sh3-dsp.o sh3-dsp +sh3-dsp.o sh3-nommu.o sh3-dsp +sh3-dsp.o sh3.o sh3-dsp +sh3-dsp.o sh3e.o ERROR +sh3-dsp.o sh4-nofpu.o sh4al-dsp +sh3-dsp.o sh4-nommu-nofpu.o sh4al-dsp +sh3-dsp.o sh4.o ERROR +sh3-dsp.o sh4a-nofpu.o sh4al-dsp +sh3-dsp.o sh4a.o ERROR +sh3-dsp.o sh4al-dsp.o sh4al-dsp +sh3-dsp.o sh-unknown.o sh3-dsp +sh3-nommu.o sh-dsp.o sh3-dsp +sh3-nommu.o sh.o sh3-nommu +sh3-nommu.o sh2.o sh3-nommu +sh3-nommu.o sh2a-nofpu-or-sh3-nommu.o sh3-nommu +sh3-nommu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nommu-nofpu +sh3-nommu.o sh2a-nofpu.o ERROR +sh3-nommu.o sh2a-or-sh3e.o sh3e +sh3-nommu.o sh2a-or-sh4.o sh4 +sh3-nommu.o sh2a.o ERROR +sh3-nommu.o sh2e.o sh3e +sh3-nommu.o sh3-dsp.o sh3-dsp +sh3-nommu.o sh3-nommu.o sh3-nommu +sh3-nommu.o sh3.o sh3 +sh3-nommu.o sh3e.o sh3e +sh3-nommu.o sh4-nofpu.o sh4-nofpu +sh3-nommu.o sh4-nommu-nofpu.o sh4-nommu-nofpu +sh3-nommu.o sh4.o sh4 +sh3-nommu.o sh4a-nofpu.o sh4a-nofpu +sh3-nommu.o sh4a.o sh4a +sh3-nommu.o sh4al-dsp.o sh4al-dsp +sh3-nommu.o sh-unknown.o sh3-nommu +sh3.o sh-dsp.o sh3-dsp +sh3.o sh.o sh3 +sh3.o sh2.o sh3 +sh3.o sh2a-nofpu-or-sh3-nommu.o sh3 +sh3.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nofpu +sh3.o sh2a-nofpu.o ERROR +sh3.o sh2a-or-sh3e.o sh3e +sh3.o sh2a-or-sh4.o sh4 +sh3.o sh2a.o ERROR +sh3.o sh2e.o sh3e +sh3.o sh3-dsp.o sh3-dsp +sh3.o sh3-nommu.o sh3 +sh3.o sh3.o sh3 +sh3.o sh3e.o sh3e +sh3.o sh4-nofpu.o sh4-nofpu +sh3.o sh4-nommu-nofpu.o sh4-nofpu +sh3.o sh4.o sh4 +sh3.o sh4a-nofpu.o sh4a-nofpu +sh3.o sh4a.o sh4a +sh3.o sh4al-dsp.o sh4al-dsp +sh3.o sh-unknown.o sh3 +sh3e.o sh-dsp.o ERROR +sh3e.o sh.o sh3e +sh3e.o sh2.o sh3e +sh3e.o sh2a-nofpu-or-sh3-nommu.o sh3e +sh3e.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4 +sh3e.o sh2a-nofpu.o ERROR +sh3e.o sh2a-or-sh3e.o sh3e +sh3e.o sh2a-or-sh4.o sh4 +sh3e.o sh2a.o ERROR +sh3e.o sh2e.o sh3e +sh3e.o sh3-dsp.o ERROR +sh3e.o sh3-nommu.o sh3e +sh3e.o sh3.o sh3e +sh3e.o sh3e.o sh3e +sh3e.o sh4-nofpu.o sh4 +sh3e.o sh4-nommu-nofpu.o sh4 +sh3e.o sh4.o sh4 +sh3e.o sh4a-nofpu.o sh4a +sh3e.o sh4a.o sh4a +sh3e.o sh4al-dsp.o ERROR +sh3e.o sh-unknown.o sh3e +sh4-nofpu.o sh-dsp.o sh4al-dsp +sh4-nofpu.o sh.o sh4-nofpu +sh4-nofpu.o sh2.o sh4-nofpu +sh4-nofpu.o sh2a-nofpu-or-sh3-nommu.o sh4-nofpu +sh4-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nofpu +sh4-nofpu.o sh2a-nofpu.o ERROR +sh4-nofpu.o sh2a-or-sh3e.o sh4 +sh4-nofpu.o sh2a-or-sh4.o sh4 +sh4-nofpu.o sh2a.o ERROR +sh4-nofpu.o sh2e.o sh4 +sh4-nofpu.o sh3-dsp.o sh4al-dsp +sh4-nofpu.o sh3-nommu.o sh4-nofpu +sh4-nofpu.o sh3.o sh4-nofpu +sh4-nofpu.o sh3e.o sh4 +sh4-nofpu.o sh4-nofpu.o sh4-nofpu +sh4-nofpu.o sh4-nommu-nofpu.o sh4-nofpu +sh4-nofpu.o sh4.o sh4 +sh4-nofpu.o sh4a-nofpu.o sh4a-nofpu +sh4-nofpu.o sh4a.o sh4a +sh4-nofpu.o sh4al-dsp.o sh4al-dsp +sh4-nofpu.o sh-unknown.o sh4-nofpu +sh4-nommu-nofpu.o sh-dsp.o sh4al-dsp +sh4-nommu-nofpu.o sh.o sh4-nommu-nofpu +sh4-nommu-nofpu.o sh2.o sh4-nommu-nofpu +sh4-nommu-nofpu.o sh2a-nofpu-or-sh3-nommu.o sh4-nommu-nofpu +sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4-nommu-nofpu +sh4-nommu-nofpu.o sh2a-nofpu.o ERROR +sh4-nommu-nofpu.o sh2a-or-sh3e.o sh4 +sh4-nommu-nofpu.o sh2a-or-sh4.o sh4 +sh4-nommu-nofpu.o sh2a.o ERROR +sh4-nommu-nofpu.o sh2e.o sh4 +sh4-nommu-nofpu.o sh3-dsp.o sh4al-dsp +sh4-nommu-nofpu.o sh3-nommu.o sh4-nommu-nofpu +sh4-nommu-nofpu.o sh3.o sh4-nofpu +sh4-nommu-nofpu.o sh3e.o sh4 +sh4-nommu-nofpu.o sh4-nofpu.o sh4-nofpu +sh4-nommu-nofpu.o sh4-nommu-nofpu.o sh4-nommu-nofpu +sh4-nommu-nofpu.o sh4.o sh4 +sh4-nommu-nofpu.o sh4a-nofpu.o sh4a-nofpu +sh4-nommu-nofpu.o sh4a.o sh4a +sh4-nommu-nofpu.o sh4al-dsp.o sh4al-dsp +sh4-nommu-nofpu.o sh-unknown.o sh4-nommu-nofpu +sh4.o sh-dsp.o ERROR +sh4.o sh.o sh4 +sh4.o sh2.o sh4 +sh4.o sh2a-nofpu-or-sh3-nommu.o sh4 +sh4.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4 +sh4.o sh2a-nofpu.o ERROR +sh4.o sh2a-or-sh3e.o sh4 +sh4.o sh2a-or-sh4.o sh4 +sh4.o sh2a.o ERROR +sh4.o sh2e.o sh4 +sh4.o sh3-dsp.o ERROR +sh4.o sh3-nommu.o sh4 +sh4.o sh3.o sh4 +sh4.o sh3e.o sh4 +sh4.o sh4-nofpu.o sh4 +sh4.o sh4-nommu-nofpu.o sh4 +sh4.o sh4.o sh4 +sh4.o sh4a-nofpu.o sh4a +sh4.o sh4a.o sh4a +sh4.o sh4al-dsp.o ERROR +sh4.o sh-unknown.o sh4 +sh4a-nofpu.o sh-dsp.o sh4al-dsp +sh4a-nofpu.o sh.o sh4a-nofpu +sh4a-nofpu.o sh2.o sh4a-nofpu +sh4a-nofpu.o sh2a-nofpu-or-sh3-nommu.o sh4a-nofpu +sh4a-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a-nofpu +sh4a-nofpu.o sh2a-nofpu.o ERROR +sh4a-nofpu.o sh2a-or-sh3e.o sh4a +sh4a-nofpu.o sh2a-or-sh4.o sh4a +sh4a-nofpu.o sh2a.o ERROR +sh4a-nofpu.o sh2e.o sh4a +sh4a-nofpu.o sh3-dsp.o sh4al-dsp +sh4a-nofpu.o sh3-nommu.o sh4a-nofpu +sh4a-nofpu.o sh3.o sh4a-nofpu +sh4a-nofpu.o sh3e.o sh4a +sh4a-nofpu.o sh4-nofpu.o sh4a-nofpu +sh4a-nofpu.o sh4-nommu-nofpu.o sh4a-nofpu +sh4a-nofpu.o sh4.o sh4a +sh4a-nofpu.o sh4a-nofpu.o sh4a-nofpu +sh4a-nofpu.o sh4a.o sh4a +sh4a-nofpu.o sh4al-dsp.o sh4al-dsp +sh4a-nofpu.o sh-unknown.o sh4a-nofpu +sh4a.o sh-dsp.o ERROR +sh4a.o sh.o sh4a +sh4a.o sh2.o sh4a +sh4a.o sh2a-nofpu-or-sh3-nommu.o sh4a +sh4a.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4a +sh4a.o sh2a-nofpu.o ERROR +sh4a.o sh2a-or-sh3e.o sh4a +sh4a.o sh2a-or-sh4.o sh4a +sh4a.o sh2a.o ERROR +sh4a.o sh2e.o sh4a +sh4a.o sh3-dsp.o ERROR +sh4a.o sh3-nommu.o sh4a +sh4a.o sh3.o sh4a +sh4a.o sh3e.o sh4a +sh4a.o sh4-nofpu.o sh4a +sh4a.o sh4-nommu-nofpu.o sh4a +sh4a.o sh4.o sh4a +sh4a.o sh4a-nofpu.o sh4a +sh4a.o sh4a.o sh4a +sh4a.o sh4al-dsp.o ERROR +sh4a.o sh-unknown.o sh4a +sh4al-dsp.o sh-dsp.o sh4al-dsp +sh4al-dsp.o sh.o sh4al-dsp +sh4al-dsp.o sh2.o sh4al-dsp +sh4al-dsp.o sh2a-nofpu-or-sh3-nommu.o sh4al-dsp +sh4al-dsp.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh4al-dsp +sh4al-dsp.o sh2a-nofpu.o ERROR +sh4al-dsp.o sh2a-or-sh3e.o ERROR +sh4al-dsp.o sh2a-or-sh4.o ERROR +sh4al-dsp.o sh2a.o ERROR +sh4al-dsp.o sh2e.o ERROR +sh4al-dsp.o sh3-dsp.o sh4al-dsp +sh4al-dsp.o sh3-nommu.o sh4al-dsp +sh4al-dsp.o sh3.o sh4al-dsp +sh4al-dsp.o sh3e.o ERROR +sh4al-dsp.o sh4-nofpu.o sh4al-dsp +sh4al-dsp.o sh4-nommu-nofpu.o sh4al-dsp +sh4al-dsp.o sh4.o ERROR +sh4al-dsp.o sh4a-nofpu.o sh4al-dsp +sh4al-dsp.o sh4a.o ERROR +sh4al-dsp.o sh4al-dsp.o sh4al-dsp +sh4al-dsp.o sh-unknown.o sh4al-dsp +sh-unknown.o sh-dsp.o sh-dsp +sh-unknown.o sh.o sh +sh-unknown.o sh2.o sh2 +sh-unknown.o sh2a-nofpu-or-sh3-nommu.o sh2a-nofpu-or-sh3-nommu +sh-unknown.o sh2a-nofpu-or-sh4-nommu-nofpu.o sh2a-nofpu-or-sh4-nommu-nofpu +sh-unknown.o sh2a-nofpu.o sh2a-nofpu +sh-unknown.o sh2a-or-sh3e.o sh2a-or-sh3e +sh-unknown.o sh2a-or-sh4.o sh2a-or-sh4 +sh-unknown.o sh2a.o sh2a +sh-unknown.o sh2e.o sh2e +sh-unknown.o sh3-dsp.o sh3-dsp +sh-unknown.o sh3-nommu.o sh3-nommu +sh-unknown.o sh3.o sh3 +sh-unknown.o sh3e.o sh3e +sh-unknown.o sh4-nofpu.o sh4-nofpu +sh-unknown.o sh4-nommu-nofpu.o sh4-nommu-nofpu +sh-unknown.o sh4.o sh4 +sh-unknown.o sh4a-nofpu.o sh4a-nofpu +sh-unknown.o sh4a.o sh4a +sh-unknown.o sh4al-dsp.o sh4al-dsp +sh-unknown.o sh-unknown.o sh diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh-dsp.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh-dsp.s new file mode 100644 index 0000000..cd87a22 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh-dsp.s @@ -0,0 +1,272 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh-dsp but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh-dsp.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh-dsp.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh_dsp: +! Instructions introduced into sh-dsp + ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up} + ldc r4,RE ;!/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up} + ldc r4,RS ;!/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up} + ldc.l @r4+,MOD ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up} + ldc.l @r4+,RE ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up} + ldc.l @r4+,RS ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up} + ldre @(8,PC) ;!/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up} + ldrs @(8,PC) ;!/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up} + lds r4,DSR ;!/* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} + lds r4,A0 ;!/* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} + lds r4,X0 ;!/* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} + lds r4,X1 ;!/* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} + lds r4,Y0 ;!/* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} + lds r4,Y1 ;!/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} + lds.l @r4+,DSR ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up} + lds.l @r4+,A0 ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up} + lds.l @r4+,X0 ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up} + lds.l @r4+,X1 ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up} + lds.l @r4+,Y0 ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up} + lds.l @r4+,Y1 ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up} + setrc r4 ;!/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} + stc MOD,r4 ;!/* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up} + stc RE,r4 ;!/* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} + stc RS,r4 ;!/* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} + stc.l MOD,@-r4 ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up} + stc.l RE,@-r4 ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up} + stc.l RS,@-r4 ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up} + sts DSR,r4 ;!/* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} + sts A0,r4 ;!/* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} + sts X0,r4 ;!/* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} + sts X1,r4 ;!/* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} + sts Y0,r4 ;!/* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} + sts Y1,r4 ;!/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} + sts.l DSR,@-r4 ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} + sts.l A0,@-r4 ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} + sts.l X0,@-r4 ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up} + sts.l X1,@-r4 ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up} + sts.l Y0,@-r4 ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up} + sts.l Y1,@-r4 ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up} + movs.w @-r4,a1 ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up} + movs.w @r4,a1 ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up} + movs.w @r4+,a1 ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up} + movs.w @r4+r8,a1 ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up} + movs.w a1,@-r4 ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up} + movs.w a1,@r4 ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up} + movs.w a1,@r4+ ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up} + movs.w a1,@r4+r8 ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up} + movs.l @-r4,a1 ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up} + movs.l @r4,a1 ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up} + movs.l @r4+,a1 ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up} + movs.l @r4+r8,a1 ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up} + movs.l a1,@-r4 ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up} + movs.l a1,@r4 ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up} + movs.l a1,@r4+ ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up} + movs.l a1,@r4+r8 ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up} + nopx ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up} + nopy ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up} + movx.w @r4,x1 ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up} + movx.w @r4+,x1 ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up} + movx.w @r4+r8,x1 ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up} + movx.w a1,@r4 ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up} + movx.w a1,@r4+ ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up} + movx.w a1,@r4+r8 ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up} + movy.w @r6,y0 ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up} + movy.w @r6+,y0 ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up} + movy.w @r6+r9,y0 ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up} + movy.w a1,@r6 ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up} + movy.w a1,@r6+ ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up} + movy.w a1,@r6+r9 ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up} + pmuls x0,y0,m0 ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up} + psubc x1,y0,m0 ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up} + paddc x1,y0,m0 ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up} + pcmp x1,y0 ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */ {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up} + pwsb x1,y0,m0 ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up} + pwad x1,y0,m0 ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up} + pabs x1,m0 ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up} + pabs y0,m0 ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up} + prnd x1,m0 ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up} + prnd y0,m0 ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up} + dct pshl x1,y0,m0 ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up} + pshl #4,m0 ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up} + dct psha x1,y0,m0 ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up} + psha #4,m0 ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up} + dct psub x1,y0,m0 ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up} + dct padd x1,y0,m0 ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up} + dct pand x1,y0,m0 ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up} + dct pxor x1,y0,m0 ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up} + dct por x1,y0,m0 ;!/* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up} + dct pdec x1,m0 ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */ {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up} + dct pdec y0,m0 ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up} + dct pinc x1,m0 ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */ {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up} + dct pinc y0,m0 ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up} + dct pclr m0 ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */ {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up} + dct pdmsb x1,m0 ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up} + dct pdmsb y0,m0 ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up} + dct pneg x1,m0 ;!/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up} + dct pneg y0,m0 ;!/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up} + dct pcopy x1,m0 ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */ {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up} + dct pcopy y0,m0 ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */ {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up} + dct psts MACH,m0 ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */ {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up} + dct psts MACL,m0 ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */ {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up} + dct plds m0,MACH ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */ {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up} + dct plds m0,MACL ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up} + +! Instructions inherited from ancestors: sh sh2 + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh.s new file mode 100644 index 0000000..86de648 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh.s @@ -0,0 +1,155 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh: +! Instructions introduced into sh + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + +! Instructions inherited from ancestors: diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh2.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2.s new file mode 100644 index 0000000..3659942 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2.s @@ -0,0 +1,166 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh2 but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh2.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh2.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh2: +! Instructions introduced into sh2 + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} + +! Instructions inherited from ancestors: sh + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s new file mode 100644 index 0000000..ce93bc9 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh3-nommu.s @@ -0,0 +1,168 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh2a-nofpu-or-sh3-nommu but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh2a-nofpu-or-sh3-nommu.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh2a_nofpu_or_sh3_nommu: +! Instructions introduced into sh2a-nofpu-or-sh3-nommu + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + +! Instructions inherited from ancestors: sh sh2 + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s new file mode 100644 index 0000000..cc350c0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s @@ -0,0 +1,169 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh2a-nofpu-or-sh4-nommu-nofpu but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh2a-nofpu-or-sh4-nommu-nofpu.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh2a_nofpu_or_sh4_nommu_nofpu: +! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu + pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up} + +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a-nofpu.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a-nofpu.s new file mode 100644 index 0000000..878a5a3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a-nofpu.s @@ -0,0 +1,221 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh2a-nofpu but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh2a-nofpu.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh2a-nofpu.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh2a_nofpu: +! Instructions introduced into sh2a-nofpu + ldc r5,TBR ;!/* 0100mmmm01001010 ldc <REG_M>,TBR */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up} + mov.b R0,@r4+ ;!/* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up} + mov.b @-r5,R0 ;!/* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up} + mov.b r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + mov.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */ {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} + mov.l R0,@r4+ ;!/* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up} + mov.l @-r5,R0 ;!/* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up} + mov.l r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32} + mov.l @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */ {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32} + mov.w R0,@r4+ ;!/* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up} + mov.w @-r5,R0 ;!/* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up} + mov.w r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32} + mov.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */ {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} + stc TBR,r4 ;!/* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up} + bclr #4, r4 ;!/* 10000110nnnn0iii bclr #<imm>, <REG_N> */ {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up} + bclr.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */ {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bld #4, r4 ;!/* 10000111nnnn1iii bld #<imm>, <REG_N> */ {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up} + bld.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */ {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bset #4, r4 ;!/* 10000110nnnn1iii bset #<imm>, <REG_N> */ {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up} + bset.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */ {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bst #4, r4 ;!/* 10000111nnnn0iii bst #<imm>, <REG_N> */ {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up} + bst.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */ {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + clips.b r4 ;!/* 0100nnnn10010001 clips.b <REG_N> */ {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up} + clips.w r4 ;!/* 0100nnnn10010101 clips.w <REG_N> */ {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up} + clipu.b r4 ;!/* 0100nnnn10000001 clipu.b <REG_N> */ {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up} + clipu.w r4 ;!/* 0100nnnn10000101 clipu.w <REG_N> */ {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up} + divs R0,r4 ;!/* 0100nnnn10010100 divs R0,<REG_N> */ {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up} + divu R0,r4 ;!/* 0100nnnn10000100 divu R0,<REG_N> */ {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up} + jsr/n @r5 ;!/* 0100mmmm01001011 jsr/n @<REG_M> */ {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up} + jsr/n @@(8,TBR) ;!/* 10000011dddddddd jsr/n @@(<disp>,TBR) */ {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up} + ldbank @r5,R0 ;!/* 0100mmmm11100101 ldbank @<REG_M>,R0 */ {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up} + movml.l r5,@-R15 ;!/* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up} + movml.l @R15+,r5 ;!/* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up} + movml.l r5,@-R15 ;!/* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up} + movml.l @R15+,r5 ;!/* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up} + movrt r4 ;!/* 0000nnnn00111001 movrt <REG_N> */ {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up} + mulr R0,r4 ;!/* 0100nnnn10000000 mulr R0,<REG_N> */ {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up} + nott ;!/* 0000000001101000 nott */ {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up} + resbank ;!/* 0000000001011011 resbank */ {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up} + rts/n ;!/* 0000000001101011 rts/n */ {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up} + rtv/n r5 ;!/* 0000mmmm01111011 rtv/n <REG_M>*/ {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up} + stbank R0,@r4 ;!/* 0100nnnn11100001 stbank R0,@<REG_N>*/ {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up} + band.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */ {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bandnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bldnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bornot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bxor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + movi20 #4,r4 ;!/* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */ {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32} + movi20s #1024,r4 ;!/* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */ {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32} + movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} + movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} + +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a-or-sh3e.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a-or-sh3e.s new file mode 100644 index 0000000..b7be336 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a-or-sh3e.s @@ -0,0 +1,205 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh2a-or-sh3e but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh2a-or-sh3e.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh2a_or_sh3e: +! Instructions introduced into sh2a-or-sh3e + fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} + +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} + lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} + lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} + sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} + sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} + fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} + fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} + fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} + fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} + fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} + fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} + fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} + flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} + float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} + fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} + fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} + fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} + fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} + fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} + fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} + fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} + fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} + fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} + fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} + fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} + fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} + fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} + fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} + fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} + fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} + fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} + fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} + ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a-or-sh4.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a-or-sh4.s new file mode 100644 index 0000000..0200796 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a-or-sh4.s @@ -0,0 +1,233 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh2a-or-sh4 but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh2a-or-sh4.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh2a_or_sh4: +! Instructions introduced into sh2a-or-sh4 + fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up} + fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up} + fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up} + fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up} + fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up} + fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up} + fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up} + float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up} + fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up} + fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} + fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} + fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} + fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} + fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} + fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} + fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} + fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} + fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} + fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} + fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} + fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} + fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up} + fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up} + fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up} + fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up} + fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} + ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} + +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} + lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} + lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} + sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} + sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} + fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} + fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} + fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} + fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} + fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} + fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} + fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} + flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} + float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} + fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} + fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} + fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} + fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} + fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} + fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} + fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} + fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} + fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} + fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} + fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} + fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} + fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} + fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} + fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} + fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} + fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} + fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} + fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} + ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a.s new file mode 100644 index 0000000..04e10f0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2a.s @@ -0,0 +1,289 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh2a but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh2a.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh2a.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh2a: +! Instructions introduced into sh2a + fmov.d xd4,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <DX_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32} + fmov.d @(2048,r5),xd2 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),<DX_REG_N> */ {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32} + fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32} + fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32} + +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r5,TBR ;!/* 0100mmmm01001010 ldc <REG_M>,TBR */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} + lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} + lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.b R0,@r4+ ;!/* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up} + mov.b @-r5,R0 ;!/* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up} + mov.b r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + mov.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */ {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.l R0,@r4+ ;!/* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up} + mov.l @-r5,R0 ;!/* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up} + mov.l r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32} + mov.l @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */ {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + mov.w R0,@r4+ ;!/* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up} + mov.w @-r5,R0 ;!/* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up} + mov.w r5,@(2048,r4) ;!/* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */ {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32} + mov.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */ {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc TBR,r4 ;!/* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} + sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} + sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} + fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} + fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up} + fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} + fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up} + fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} + fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up} + fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} + fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up} + fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up} + fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up} + fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} + fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up} + fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} + fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} + flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} + float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} + float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up} + fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} + fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} + fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up} + fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} + fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} + fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} + fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} + fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} + fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} + fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} + fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} + fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} + fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} + fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} + fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} + fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} + fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} + fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} + fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} + fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} + fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} + fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} + fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} + fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} + fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} + fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} + fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} + fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} + fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up} + fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} + fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up} + fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up} + fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} + fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up} + fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} + fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} + fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} + ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up} + ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} + bclr #4, r4 ;!/* 10000110nnnn0iii bclr #<imm>, <REG_N> */ {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up} + bclr.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */ {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bld #4, r4 ;!/* 10000111nnnn1iii bld #<imm>, <REG_N> */ {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up} + bld.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */ {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bset #4, r4 ;!/* 10000110nnnn1iii bset #<imm>, <REG_N> */ {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up} + bset.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */ {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bst #4, r4 ;!/* 10000111nnnn0iii bst #<imm>, <REG_N> */ {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up} + bst.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */ {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + clips.b r4 ;!/* 0100nnnn10010001 clips.b <REG_N> */ {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up} + clips.w r4 ;!/* 0100nnnn10010101 clips.w <REG_N> */ {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up} + clipu.b r4 ;!/* 0100nnnn10000001 clipu.b <REG_N> */ {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up} + clipu.w r4 ;!/* 0100nnnn10000101 clipu.w <REG_N> */ {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up} + divs R0,r4 ;!/* 0100nnnn10010100 divs R0,<REG_N> */ {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up} + divu R0,r4 ;!/* 0100nnnn10000100 divu R0,<REG_N> */ {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up} + jsr/n @r5 ;!/* 0100mmmm01001011 jsr/n @<REG_M> */ {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up} + jsr/n @@(8,TBR) ;!/* 10000011dddddddd jsr/n @@(<disp>,TBR) */ {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up} + ldbank @r5,R0 ;!/* 0100mmmm11100101 ldbank @<REG_M>,R0 */ {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up} + movml.l r5,@-R15 ;!/* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up} + movml.l @R15+,r5 ;!/* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up} + movml.l r5,@-R15 ;!/* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up} + movml.l @R15+,r5 ;!/* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up} + movrt r4 ;!/* 0000nnnn00111001 movrt <REG_N> */ {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up} + mulr R0,r4 ;!/* 0100nnnn10000000 mulr R0,<REG_N> */ {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up} + nott ;!/* 0000000001101000 nott */ {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up} + resbank ;!/* 0000000001011011 resbank */ {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up} + rts/n ;!/* 0000000001101011 rts/n */ {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up} + rtv/n r5 ;!/* 0000mmmm01111011 rtv/n <REG_M>*/ {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up} + stbank R0,@r4 ;!/* 0100nnnn11100001 stbank R0,@<REG_N>*/ {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up} + band.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */ {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bandnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bldnot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bornot.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */ {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + bxor.b #4,@(2048,r4) ;!/* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */ {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32} + movi20 #4,r4 ;!/* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */ {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32} + movi20s #1024,r4 ;!/* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */ {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32} + movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32} + movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh2e.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2e.s new file mode 100644 index 0000000..a62e3ab --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh2e.s @@ -0,0 +1,202 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh2e but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh2e.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh2e.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh2e: +! Instructions introduced into sh2e + lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} + lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} + lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} + lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} + sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} + sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} + sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} + sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} + fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} + fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} + fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} + fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} + fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} + fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} + fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} + flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} + float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} + fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} + fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} + fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} + fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} + fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} + fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} + fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} + fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} + fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} + fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} + fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} + fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} + fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} + fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} + fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} + fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} + fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} + fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} + ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up} + +! Instructions inherited from ancestors: sh sh2 + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh3-dsp.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh3-dsp.s new file mode 100644 index 0000000..7000596 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh3-dsp.s @@ -0,0 +1,287 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh3-dsp but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh3-dsp.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh3-dsp.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh3_dsp: +! Instructions introduced into sh3-dsp + +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up} + ldc r4,RE ;!/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up} + ldc r4,RS ;!/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up} + ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} + ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} + ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + ldc.l @r4+,MOD ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up} + ldc.l @r4+,RE ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up} + ldc.l @r4+,RS ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up} + ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} + ldre @(8,PC) ;!/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up} + ldrs @(8,PC) ;!/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds r4,DSR ;!/* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} + lds r4,A0 ;!/* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} + lds r4,X0 ;!/* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} + lds r4,X1 ;!/* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} + lds r4,Y0 ;!/* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} + lds r4,Y1 ;!/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + lds.l @r4+,DSR ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up} + lds.l @r4+,A0 ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up} + lds.l @r4+,X0 ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up} + lds.l @r4+,X1 ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up} + lds.l @r4+,Y0 ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up} + lds.l @r4+,Y1 ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up} + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + setrc r4 ;!/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc MOD,r4 ;!/* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up} + stc RE,r4 ;!/* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} + stc RS,r4 ;!/* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} + stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} + stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} + stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l MOD,@-r4 ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up} + stc.l RE,@-r4 ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up} + stc.l RS,@-r4 ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up} + stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts DSR,r4 ;!/* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} + sts A0,r4 ;!/* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} + sts X0,r4 ;!/* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} + sts X1,r4 ;!/* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} + sts Y0,r4 ;!/* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} + sts Y1,r4 ;!/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sts.l DSR,@-r4 ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} + sts.l A0,@-r4 ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} + sts.l X0,@-r4 ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up} + sts.l X1,@-r4 ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up} + sts.l Y0,@-r4 ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up} + sts.l Y1,@-r4 ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} + movs.w @-r4,a1 ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up} + movs.w @r4,a1 ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up} + movs.w @r4+,a1 ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up} + movs.w @r4+r8,a1 ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up} + movs.w a1,@-r4 ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up} + movs.w a1,@r4 ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up} + movs.w a1,@r4+ ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up} + movs.w a1,@r4+r8 ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up} + movs.l @-r4,a1 ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up} + movs.l @r4,a1 ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up} + movs.l @r4+,a1 ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up} + movs.l @r4+r8,a1 ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up} + movs.l a1,@-r4 ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up} + movs.l a1,@r4 ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up} + movs.l a1,@r4+ ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up} + movs.l a1,@r4+r8 ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up} + nopx ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up} + nopy ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up} + movx.w @r4,x1 ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up} + movx.w @r4+,x1 ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up} + movx.w @r4+r8,x1 ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up} + movx.w a1,@r4 ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up} + movx.w a1,@r4+ ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up} + movx.w a1,@r4+r8 ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up} + movy.w @r6,y0 ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up} + movy.w @r6+,y0 ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up} + movy.w @r6+r9,y0 ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up} + movy.w a1,@r6 ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up} + movy.w a1,@r6+ ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up} + movy.w a1,@r6+r9 ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up} + pmuls x0,y0,m0 ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up} + psubc x1,y0,m0 ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up} + paddc x1,y0,m0 ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up} + pcmp x1,y0 ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */ {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up} + pwsb x1,y0,m0 ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up} + pwad x1,y0,m0 ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up} + pabs x1,m0 ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up} + pabs y0,m0 ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up} + prnd x1,m0 ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up} + prnd y0,m0 ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up} + dct pshl x1,y0,m0 ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up} + pshl #4,m0 ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up} + dct psha x1,y0,m0 ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up} + psha #4,m0 ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up} + dct psub x1,y0,m0 ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up} + dct padd x1,y0,m0 ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up} + dct pand x1,y0,m0 ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up} + dct pxor x1,y0,m0 ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up} + dct por x1,y0,m0 ;!/* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up} + dct pdec x1,m0 ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */ {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up} + dct pdec y0,m0 ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up} + dct pinc x1,m0 ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */ {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up} + dct pinc y0,m0 ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up} + dct pclr m0 ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */ {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up} + dct pdmsb x1,m0 ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up} + dct pdmsb y0,m0 ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up} + dct pneg x1,m0 ;!/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up} + dct pneg y0,m0 ;!/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up} + dct pcopy x1,m0 ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */ {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up} + dct pcopy y0,m0 ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */ {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up} + dct psts MACH,m0 ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */ {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up} + dct psts MACL,m0 ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */ {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up} + dct plds m0,MACH ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */ {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up} + dct plds m0,MACL ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh3-nommu.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh3-nommu.s new file mode 100644 index 0000000..bc6096e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh3-nommu.s @@ -0,0 +1,180 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh3-nommu but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh3-nommu.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh3-nommu.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh3_nommu: +! Instructions introduced into sh3-nommu + ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} + ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} + ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} + ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} + stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} + stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} + stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} + stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh3.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh3.s new file mode 100644 index 0000000..5e031c0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh3.s @@ -0,0 +1,181 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh3 but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh3.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh3.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh3: +! Instructions introduced into sh3 + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} + ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} + ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} + stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} + stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh3e.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh3e.s new file mode 100644 index 0000000..7076dfc --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh3e.s @@ -0,0 +1,218 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh3e but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh3e.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh3e.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh3e: +! Instructions introduced into sh3e + +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} + ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} + ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} + lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} + lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} + stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} + stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} + sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} + sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} + fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} + fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} + fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} + fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} + fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} + fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} + fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} + flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} + float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} + fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} + fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} + fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} + fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} + fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} + fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} + fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} + fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} + fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} + fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} + fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} + fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} + fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} + fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} + fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} + fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} + fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} + fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} + fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} + ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh4-nofpu.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh4-nofpu.s new file mode 100644 index 0000000..fb225a1 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh4-nofpu.s @@ -0,0 +1,194 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh4-nofpu but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh4-nofpu.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh4-nofpu.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh4_nofpu: +! Instructions introduced into sh4-nofpu + +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} + ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} + ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} + ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} + ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} + ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} + ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} + ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} + stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} + stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} + stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} + stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh4-nommu-nofpu.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh4-nommu-nofpu.s new file mode 100644 index 0000000..fc2877a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh4-nommu-nofpu.s @@ -0,0 +1,193 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh4-nommu-nofpu but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh4-nommu-nofpu.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh4_nommu_nofpu: +! Instructions introduced into sh4-nommu-nofpu + ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} + ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} + ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} + ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} + movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} + ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} + ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} + ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} + stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} + stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} + stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} + +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} + ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} + ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} + stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} + stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh4.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh4.s new file mode 100644 index 0000000..5b1c980 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh4.s @@ -0,0 +1,263 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh4 but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh4.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh4.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh4: +! Instructions introduced into sh4 + fipr fv4,fv0 ;!/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up} + frchg ;!/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up} + fsca FPUL,dr2 ;!/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up} + fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} + ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up} + +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} + ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} + ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} + ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} + ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} + ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} + lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} + lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} + ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} + ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} + stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} + stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} + stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} + stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} + sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} + sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} + fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} + fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up} + fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} + fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up} + fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} + fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up} + fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} + fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up} + fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up} + fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up} + fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} + fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up} + fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} + fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} + flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} + float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} + float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up} + fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} + fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} + fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up} + fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} + fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} + fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} + fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} + fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} + fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} + fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} + fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} + fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} + fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} + fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} + fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} + fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} + fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} + fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} + fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} + fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} + fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} + fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} + fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} + fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} + fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} + fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} + fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} + fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} + fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up} + fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} + fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up} + fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up} + fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} + fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up} + fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} + fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} + fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} + ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up} + ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh4a-nofpu.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh4a-nofpu.s new file mode 100644 index 0000000..202db6f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh4a-nofpu.s @@ -0,0 +1,201 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh4a-nofpu but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh4a-nofpu.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh4a-nofpu.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh4a_nofpu: +! Instructions introduced into sh4a-nofpu + icbi @r4 ;!/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up} + movco.l r0,@r4 ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up} + movli.l @r5,r0 ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up} + movua.l @r5,r0 ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up} + movua.l @r5+,r0 ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up} + prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} + synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} + +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} + ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} + ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} + ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} + ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} + ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} + ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} + ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} + stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} + stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} + stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} + stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh4a.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh4a.s new file mode 100644 index 0000000..c710ddc --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh4a.s @@ -0,0 +1,271 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh4a but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh4a.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh4a.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh4a: +! Instructions introduced into sh4a + fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up} + +! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + icbi @r4 ;!/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} + ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} + ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} + ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} + ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} + ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds r4,FPUL ;!/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up} + lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + lds.l @r5+,FPUL ;!/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up} + lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up} + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} + movco.l r0,@r4 ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up} + movli.l @r5,r0 ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + movua.l @r5,r0 ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up} + movua.l @r5+,r0 ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} + ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} + ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up} + prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} + stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} + stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} + stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} + stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts FPUL,r4 ;!/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up} + sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sts.l FPUL,@-r4 ;!/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up} + sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} + fabs fr1 ;!/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up} + fabs dr2 ;!/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2a_or_sh4_up} + fadd fr2,fr1 ;!/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up} + fadd dr4,dr2 ;!/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2a_or_sh4_up} + fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up} + fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up} + fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up} + fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up} + fcnvds dr2,FPUL ;!/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh2a_or_sh4_up} + fcnvsd FPUL,dr2 ;!/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh2a_or_sh4_up} + fdiv fr2,fr1 ;!/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up} + fdiv dr4,dr2 ;!/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2a_or_sh4_up} + fipr fv4,fv0 ;!/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up} + fldi0 fr1 ;!/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up} + fldi1 fr1 ;!/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up} + flds fr1,FPUL ;!/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up} + float FPUL,fr1 ;!/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up} + float FPUL,dr2 ;!/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2a_or_sh4_up} + fmac FR0,fr2,fr1 ;!/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up} + fmov fr2,fr1 ;!/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up} + fmov xd4,xd2 ;!/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2a_or_sh4_up} + fmov @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} + fmov @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} + fmov fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} + fmov xd4,@r4 ;!/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} + fmov @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} + fmov @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} + fmov fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} + fmov xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} + fmov @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} + fmov @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} + fmov fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} + fmov xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} + fmov.d @r5,xd2 ;!/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2a_or_sh4_up} + fmov.d xd4,@r4 ;!/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2a_or_sh4_up} + fmov.d @r5+,xd2 ;!/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2a_or_sh4_up} + fmov.d xd4,@-r4 ;!/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2a_or_sh4_up} + fmov.d @(R0,r5),xd2 ;!/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2a_or_sh4_up} + fmov.d xd4,@(R0,r4) ;!/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2a_or_sh4_up} + fmov.s @r5,fr1 ;!/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up} + fmov.s fr2,@r4 ;!/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up} + fmov.s @r5+,fr1 ;!/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up} + fmov.s fr2,@-r4 ;!/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up} + fmov.s @(R0,r5),fr1 ;!/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up} + fmov.s fr2,@(R0,r4) ;!/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up} + fmul fr2,fr1 ;!/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up} + fmul dr4,dr2 ;!/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2a_or_sh4_up} + fneg fr1 ;!/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up} + fneg dr2 ;!/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2a_or_sh4_up} + frchg ;!/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up} + fsca FPUL,dr2 ;!/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up} + fschg ;!/* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh2a_or_sh4_up} + fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up} + fsqrt dr2 ;!/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh4_up} + fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up} + fsts FPUL,fr1 ;!/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up} + fsub fr2,fr1 ;!/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up} + fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up} + ftrc fr1,FPUL ;!/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up} + ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up} + ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/arch/sh4al-dsp.s b/binutils-2.21/ld/testsuite/ld-sh/arch/sh4al-dsp.s new file mode 100644 index 0000000..8d48962 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/arch/sh4al-dsp.s @@ -0,0 +1,343 @@ +! Generated file. DO NOT EDIT. +! +! This file was generated by gas/testsuite/gas/sh/arch/arch.exp . +! This file should contain every instruction valid on +! architecture sh4al-dsp but no more. +! If the tests are failing because the expected results +! have changed then run 'make check' and copy the new file +! from <objdir>/gas/testsuite/sh4al-dsp.s +! to <srcdir>/gas/testsuite/gas/sh/arch/sh4al-dsp.s . +! Make sure there are no unexpected or missing instructions. + + .section .text +sh4al_dsp: +! Instructions introduced into sh4al-dsp + clrdmxy ;!/* 0000000010001000 clrdmxy */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up} + ldrc r5 ;!/* 0100mmmm00110100 ldrc <REG_M> */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up} + ldrc #4 ;!/* 10001010i8*1.... ldrc #<imm> */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up} + setdmx ;!/* 0000000010011000 setdmx */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up} + setdmy ;!/* 0000000011001000 setdmy */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up} + movx.w @r1,y1 ;!/* nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> */ {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up} + movx.w @r1+,y1 ;!/* nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> */{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up} + movx.w @r1+r8,y1 ;!/* nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up} + movx.w a0,@r1 ;!/* nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> */ {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up} + movx.w a0,@r1+ ;!/* nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ */{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up} + movx.w a0,@r1+r8 ;!/* nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up} + movx.l @r1,y1 ;!/* nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> */ {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up} + movx.l @r1+,y1 ;!/* nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> */{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up} + movx.l @r1+r8,y1 ;!/* nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up} + movx.l a0,@r1 ;!/* nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> */ {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up} + movx.l a0,@r1+ ;!/* nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ */{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up} + movx.l a0,@r1+r8 ;!/* nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up} + movy.w @r3,y1 ;!/* nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> */ {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up} + movy.w @r3+,y1 ;!/* nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> */{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up} + movy.w @r3+r9,y1 ;!/* nnmm000011 movy.w @<REG_Ayx>+r9,<DSP_REG_YX> */{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up} + movy.w a0,@r3 ;!/* nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> */ {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up} + movy.w a0,@r3+ ;!/* nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up} + movy.w a0,@r3+r9 ;!/* nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r9 */{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up} + movy.l @r3,y1 ;!/* nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> */ {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up} + movy.l @r3+,y1 ;!/* nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> */{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up} + movy.l @r3+r9,y1 ;!/* nnmm100011 movy.l @<REG_Ayx>+r9,<DSP_REG_YX> */{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up} + movy.l a0,@r3 ;!/* nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> */ {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up} + movy.l a0,@r3+ ;!/* nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up} + movy.l a0,@r3+r9 ;!/* nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r9 */{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up} + dct pabs x1,m0 ;!/* 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> */ {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up} + dct pabs y0,m0 ;!/* 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up} + dct prnd x1,m0 ;!/* 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> */ {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up} + dct prnd y0,m0 ;!/* 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up} + dct psub y0,x1,m0 ;!/* 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> */ {"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up} + dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up} + dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up} + +! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu + add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up} + add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up} + addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up} + addv r5,r4 ;!/* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh_up} + and #4,R0 ;!/* 11001001i8*1.... and #<imm>,R0 */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh_up} + and r5,r4 ;!/* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh_up} + and.b #4,@(R0,GBR) ;!/* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh_up} + bra .+8 ;!/* 1010i12......... bra <bdisp12> */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh_up} + bsr .+8 ;!/* 1011i12......... bsr <bdisp12> */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh_up} + bt .+8 ;!/* 10001001i8p1.... bt <bdisp8> */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh_up} + bf .+8 ;!/* 10001011i8p1.... bf <bdisp8> */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh_up} + bt.s .+8 ;!/* 10001101i8p1.... bt.s <bdisp8> */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bt/s .+8 ;!/* 10001101i8p1.... bt/s <bdisp8> */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up} + bf.s .+8 ;!/* 10001111i8p1.... bf.s <bdisp8> */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + bf/s .+8 ;!/* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up} + clrmac ;!/* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh_up} + clrs ;!/* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh_up} + clrt ;!/* 0000000000001000 clrt */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh_up} + cmp/eq #4,R0 ;!/* 10001000i8*1.... cmp/eq #<imm>,R0 */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh_up} + cmp/eq r5,r4 ;!/* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh_up} + cmp/ge r5,r4 ;!/* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh_up} + cmp/gt r5,r4 ;!/* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh_up} + cmp/hi r5,r4 ;!/* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh_up} + cmp/hs r5,r4 ;!/* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh_up} + cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} + cmp/pz r4 ;!/* 0100nnnn00010001 cmp/pz <REG_N> */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} + cmp/str r5,r4 ;!/* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh_up} + div0s r5,r4 ;!/* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh_up} + div0u ;!/* 0000000000011001 div0u */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh_up} + div1 r5,r4 ;!/* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh_up} + exts.b r5,r4 ;!/* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh_up} + exts.w r5,r4 ;!/* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh_up} + extu.b r5,r4 ;!/* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh_up} + extu.w r5,r4 ;!/* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh_up} + icbi @r4 ;!/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofpu_up} + jmp @r4 ;!/* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} + jsr @r4 ;!/* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} + ldc r4,SR ;!/* 0100nnnn00001110 ldc <REG_N>,SR */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} + ldc r4,GBR ;!/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} + ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} + ldc r4,VBR ;!/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} + ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up} + ldc r4,RE ;!/* 0100nnnn01111110 ldc <REG_N>,RE */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up} + ldc r4,RS ;!/* 0100nnnn01101110 ldc <REG_N>,RS */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up} + ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} + ldc r4,SPC ;!/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} + ldc r4,DBR ;!/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} + ldc r4,r1_bank ;!/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} + ldc.l @r4+,SR ;!/* 0100nnnn00000111 ldc.l @<REG_N>+,SR */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh_up} + ldc.l @r4+,GBR ;!/* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh_up} + ldc.l @r4+,VBR ;!/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh_up} + ldc.l @r4+,SGR ;!/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} + ldc.l @r4+,MOD ;!/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up} + ldc.l @r4+,RE ;!/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up} + ldc.l @r4+,RS ;!/* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up} + ldc.l @r4+,SSR ;!/* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,SPC ;!/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} + ldc.l @r4+,DBR ;!/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} + ldc.l @r4+,r1_bank ;!/* 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} + ldre @(8,PC) ;!/* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up} + ldrs @(8,PC) ;!/* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up} + lds r4,MACH ;!/* 0100nnnn00001010 lds <REG_N>,MACH */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh_up} + lds r4,MACL ;!/* 0100nnnn00011010 lds <REG_N>,MACL */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh_up} + lds r4,PR ;!/* 0100nnnn00101010 lds <REG_N>,PR */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh_up} + lds r4,DSR ;!/* 0100nnnn01101010 lds <REG_N>,DSR */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} + lds r4,A0 ;!/* 0100nnnn01111010 lds <REG_N>,A0 */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} + lds r4,X0 ;!/* 0100nnnn10001010 lds <REG_N>,X0 */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} + lds r4,X1 ;!/* 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} + lds r4,Y0 ;!/* 0100nnnn10101010 lds <REG_N>,Y0 */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} + lds r4,Y1 ;!/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} + lds.l @r4+,MACH ;!/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh_up} + lds.l @r4+,MACL ;!/* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh_up} + lds.l @r4+,PR ;!/* 0100nnnn00100110 lds.l @<REG_N>+,PR */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh_up} + lds.l @r4+,DSR ;!/* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up} + lds.l @r4+,A0 ;!/* 0100nnnn01110110 lds.l @<REG_N>+,A0 */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up} + lds.l @r4+,X0 ;!/* 0100nnnn10000110 lds.l @<REG_N>+,X0 */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up} + lds.l @r4+,X1 ;!/* 0100nnnn10010110 lds.l @<REG_N>+,X1 */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up} + lds.l @r4+,Y0 ;!/* 0100nnnn10100110 lds.l @<REG_N>+,Y0 */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up} + lds.l @r4+,Y1 ;!/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up} + ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up} + mac.w @r5+,@r4+ ;!/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh_up} + mov #4,r4 ;!/* 1110nnnni8*1.... mov #<imm>,<REG_N> */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh_up} + mov r5,r4 ;!/* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh_up} + mov.b r5,@(R0,r4) ;!/* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@-r4 ;!/* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b r5,@r4 ;!/* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b @(8,r5),R0 ;!/* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh_up} + mov.b @(8,GBR),R0 ;!/* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh_up} + mov.b @(R0,r5),r4 ;!/* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh_up} + mov.b @r5+,r4 ;!/* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh_up} + mov.b @r5,r4 ;!/* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh_up} + mov.b R0,@(8,r5) ;!/* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh_up} + mov.b R0,@(8,GBR) ;!/* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh_up} + mov.l r5,@(8,r4) ;!/* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh_up} + mov.l r5,@(R0,r4) ;!/* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@-r4 ;!/* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l r5,@r4 ;!/* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l @(8,r5),r4 ;!/* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh_up} + mov.l @(8,GBR),R0 ;!/* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh_up} + .align 2 + mov.l @(8,PC),r4 ;!/* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh_up} + mov.l @(R0,r5),r4 ;!/* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh_up} + mov.l @r5+,r4 ;!/* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh_up} + mov.l @r5,r4 ;!/* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh_up} + mov.l R0,@(8,GBR) ;!/* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh_up} + mov.w r5,@(R0,r4) ;!/* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@-r4 ;!/* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w r5,@r4 ;!/* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w @(8,r5),R0 ;!/* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh_up} + mov.w @(8,GBR),R0 ;!/* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh_up} + mov.w @(8,PC),r4 ;!/* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh_up} + mov.w @(R0,r5),r4 ;!/* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh_up} + mov.w @r5+,r4 ;!/* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh_up} + mov.w @r5,r4 ;!/* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh_up} + mov.w R0,@(8,r5) ;!/* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh_up} + mov.w R0,@(8,GBR) ;!/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh_up} + .align 2 + mova @(8,PC),R0 ;!/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh_up} + movca.l R0,@r4 ;!/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up} + movco.l r0,@r4 ;!/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofpu_up} + movli.l @r5,r0 ;!/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofpu_up} + movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up} + movua.l @r5,r0 ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up} + movua.l @r5+,r0 ;!/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up} + muls.w r5,r4 ;!/* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + muls r5,r4 ;!/* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh_up} + mul.l r5,r4 ;!/* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up} + mulu.w r5,r4 ;!/* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + mulu r5,r4 ;!/* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh_up} + neg r5,r4 ;!/* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh_up} + negc r5,r4 ;!/* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh_up} + nop ;!/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh_up} + not r5,r4 ;!/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh_up} + ocbi @r4 ;!/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up} + ocbp @r4 ;!/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up} + ocbwb @r4 ;!/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up} + or #4,R0 ;!/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh_up} + or r5,r4 ;!/* 0010nnnnmmmm1011 or <REG_M>,<REG_N> */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh_up} + or.b #4,@(R0,GBR) ;!/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh_up} + pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh4_nommu_nofpu_up} + prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up} + rotcl r4 ;!/* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh_up} + rotcr r4 ;!/* 0100nnnn00100101 rotcr <REG_N> */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh_up} + rotl r4 ;!/* 0100nnnn00000100 rotl <REG_N> */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh_up} + rotr r4 ;!/* 0100nnnn00000101 rotr <REG_N> */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh_up} + rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up} + rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up} + sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh_up} + sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up} + setrc r4 ;!/* 0100nnnn00010100 setrc <REG_N> */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up} + repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up} + repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up} + shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up} + shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up} + shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up} + shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up} + shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up} + shll16 r4 ;!/* 0100nnnn00101000 shll16 <REG_N> */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh_up} + shll2 r4 ;!/* 0100nnnn00001000 shll2 <REG_N> */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh_up} + shll8 r4 ;!/* 0100nnnn00011000 shll8 <REG_N> */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh_up} + shlr r4 ;!/* 0100nnnn00000001 shlr <REG_N> */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh_up} + shlr16 r4 ;!/* 0100nnnn00101001 shlr16 <REG_N> */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh_up} + shlr2 r4 ;!/* 0100nnnn00001001 shlr2 <REG_N> */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh_up} + shlr8 r4 ;!/* 0100nnnn00011001 shlr8 <REG_N> */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh_up} + sleep ;!/* 0000000000011011 sleep */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh_up} + stc SR,r4 ;!/* 0000nnnn00000010 stc SR,<REG_N> */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh_up} + stc GBR,r4 ;!/* 0000nnnn00010010 stc GBR,<REG_N> */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh_up} + stc VBR,r4 ;!/* 0000nnnn00100010 stc VBR,<REG_N> */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh_up} + stc MOD,r4 ;!/* 0000nnnn01010010 stc MOD,<REG_N> */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up} + stc RE,r4 ;!/* 0000nnnn01110010 stc RE,<REG_N> */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} + stc RS,r4 ;!/* 0000nnnn01100010 stc RS,<REG_N> */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} + stc SSR,r4 ;!/* 0000nnnn00110010 stc SSR,<REG_N> */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up} + stc SPC,r4 ;!/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up} + stc SGR,r4 ;!/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} + stc DBR,r4 ;!/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} + stc r1_bank,r4 ;!/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up} + stc.l SR,@-r4 ;!/* 0100nnnn00000011 stc.l SR,@-<REG_N> */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh_up} + stc.l VBR,@-r4 ;!/* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh_up} + stc.l MOD,@-r4 ;!/* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up} + stc.l RE,@-r4 ;!/* 0100nnnn01110011 stc.l RE,@-<REG_N> */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up} + stc.l RS,@-r4 ;!/* 0100nnnn01100011 stc.l RS,@-<REG_N> */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up} + stc.l SSR,@-r4 ;!/* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} + stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} + stc.l GBR,@-r4 ;!/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh_up} + stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} + stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} + sts MACH,r4 ;!/* 0000nnnn00001010 sts MACH,<REG_N> */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh_up} + sts MACL,r4 ;!/* 0000nnnn00011010 sts MACL,<REG_N> */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh_up} + sts PR,r4 ;!/* 0000nnnn00101010 sts PR,<REG_N> */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh_up} + sts DSR,r4 ;!/* 0000nnnn01101010 sts DSR,<REG_N> */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} + sts A0,r4 ;!/* 0000nnnn01111010 sts A0,<REG_N> */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} + sts X0,r4 ;!/* 0000nnnn10001010 sts X0,<REG_N> */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} + sts X1,r4 ;!/* 0000nnnn10011010 sts X1,<REG_N> */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up} + sts Y0,r4 ;!/* 0000nnnn10101010 sts Y0,<REG_N> */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up} + sts Y1,r4 ;!/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up} + sts.l MACH,@-r4 ;!/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh_up} + sts.l MACL,@-r4 ;!/* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh_up} + sts.l PR,@-r4 ;!/* 0100nnnn00100010 sts.l PR,@-<REG_N> */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh_up} + sts.l DSR,@-r4 ;!/* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up} + sts.l A0,@-r4 ;!/* 0100nnnn01110110 sts.l A0,@-<REG_N> */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up} + sts.l X0,@-r4 ;!/* 0100nnnn10000110 sts.l X0,@-<REG_N> */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up} + sts.l X1,@-r4 ;!/* 0100nnnn10010110 sts.l X1,@-<REG_N> */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up} + sts.l Y0,@-r4 ;!/* 0100nnnn10100110 sts.l Y0,@-<REG_N> */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up} + sts.l Y1,@-r4 ;!/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up} + sub r5,r4 ;!/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh_up} + subc r5,r4 ;!/* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh_up} + subv r5,r4 ;!/* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh_up} + swap.b r5,r4 ;!/* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh_up} + swap.w r5,r4 ;!/* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh_up} + synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up} + tas.b @r4 ;!/* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh_up} + trapa #4 ;!/* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh_up} + tst #4,R0 ;!/* 11001000i8*1.... tst #<imm>,R0 */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh_up} + tst r5,r4 ;!/* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh_up} + tst.b #4,@(R0,GBR) ;!/* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh_up} + xor #4,R0 ;!/* 11001010i8*1.... xor #<imm>,R0 */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh_up} + xor r5,r4 ;!/* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh_up} + xor.b #4,@(R0,GBR) ;!/* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh_up} + xtrct r5,r4 ;!/* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh_up} + dt r4 ;!/* 0100nnnn00010000 dt <REG_N> */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up} + dmuls.l r5,r4 ;!/* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up} + dmulu.l r5,r4 ;!/* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up} + mac.l @r5+,@r4+ ;!/* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up} + braf r4 ;!/* 0000nnnn00100011 braf <REG_N> */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up} + bsrf r4 ;!/* 0000nnnn00000011 bsrf <REG_N> */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up} + movs.w @-r4,a1 ;!/* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */ {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up} + movs.w @r4,a1 ;!/* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */ {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up} + movs.w @r4+,a1 ;!/* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up} + movs.w @r4+r8,a1 ;!/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up} + movs.w a1,@-r4 ;!/* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up} + movs.w a1,@r4 ;!/* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */ {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up} + movs.w a1,@r4+ ;!/* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up} + movs.w a1,@r4+r8 ;!/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up} + movs.l @-r4,a1 ;!/* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up} + movs.l @r4,a1 ;!/* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */ {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up} + movs.l @r4+,a1 ;!/* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up} + movs.l @r4+r8,a1 ;!/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up} + movs.l a1,@-r4 ;!/* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up} + movs.l a1,@r4 ;!/* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */ {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up} + movs.l a1,@r4+ ;!/* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up} + movs.l a1,@r4+r8 ;!/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up} + nopx ;!/* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up} + nopy ;!/* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up} + movx.w @r4,x1 ;!/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up} + movx.w @r4+,x1 ;!/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up} + movx.w @r4+r8,x1 ;!/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up} + movx.w a1,@r4 ;!/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up} + movx.w a1,@r4+ ;!/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up} + movx.w a1,@r4+r8 ;!/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up} + movy.w @r6,y0 ;!/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up} + movy.w @r6+,y0 ;!/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up} + movy.w @r6+r9,y0 ;!/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up} + movy.w a1,@r6 ;!/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up} + movy.w a1,@r6+ ;!/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up} + movy.w a1,@r6+r9 ;!/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up} + pmuls x0,y0,m0 ;!/* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up} + psubc x1,y0,m0 ;!/* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up} + paddc x1,y0,m0 ;!/* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up} + pcmp x1,y0 ;!/* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */ {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up} + pwsb x1,y0,m0 ;!/* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up} + pwad x1,y0,m0 ;!/* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up} + pabs x1,m0 ;!/* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up} + pabs y0,m0 ;!/* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up} + prnd x1,m0 ;!/* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up} + prnd y0,m0 ;!/* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up} + dct pshl x1,y0,m0 ;!/* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up} + pshl #4,m0 ;!/* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up} + dct psha x1,y0,m0 ;!/* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up} + psha #4,m0 ;!/* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up} + dct psub x1,y0,m0 ;!/* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up} + dct padd x1,y0,m0 ;!/* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up} + dct pand x1,y0,m0 ;!/* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up} + dct pxor x1,y0,m0 ;!/* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up} + dct por x1,y0,m0 ;!/* 10110101xxyynnnn por <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"por", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up} + dct pdec x1,m0 ;!/* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */ {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up} + dct pdec y0,m0 ;!/* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up} + dct pinc x1,m0 ;!/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */ {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up} + dct pinc y0,m0 ;!/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up} + dct pclr m0 ;!/* 10001101xxyynnnn pclr <DSP_REG_N> */ {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up} + dct pdmsb x1,m0 ;!/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up} + dct pdmsb y0,m0 ;!/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up} + dct pneg x1,m0 ;!/* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up} + dct pneg y0,m0 ;!/* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ {"pneg", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up} + dct pcopy x1,m0 ;!/* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */ {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up} + dct pcopy y0,m0 ;!/* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */ {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up} + dct psts MACH,m0 ;!/* 11001101xxyynnnn psts MACH,<DSP_REG_N> */ {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up} + dct psts MACL,m0 ;!/* 11011101xxyynnnn psts MACL,<DSP_REG_N> */ {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up} + dct plds m0,MACH ;!/* 11101101xxyynnnn plds <DSP_REG_N>,MACH */ {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up} + dct plds m0,MACL ;!/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up} diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-funcdesc-shared.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-funcdesc-shared.d new file mode 100644 index 0000000..899c5ae --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-funcdesc-shared.d @@ -0,0 +1,32 @@ +#source: fdpic-funcdesc-shared.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd -shared +#objdump: -dsR -j.text -j.data -j.got +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.text: + [0-9a-f]+ 0009[ \t]+.* +Contents of section \.data: + [0-9a-f]+ 00000000[ \t]+.* +Contents of section \.got: + [0-9a-f]+ 00000000 00000000 00000000 00000000[ \t]+.* + [0-9a-f]+ 00000000[ \t]+.* + +Disassembly of section \.text: + +[0-9a-f]+ <foo>: + [0-9a-f]+:[ \t]+00 09[ \t]+nop[ \t]+ + +Disassembly of section \.data: + +[0-9a-f]+ <bar>: +[ \t]+[0-9a-f]+:[ \t]+00 00 00 00[ \t]+\.\.\.\. +[ \t]+[0-9a-f]+: R_SH_DIR32[ \t]+\.got + +Disassembly of section \.got: + +[0-9a-f]+ <\.got>: +[ \t]+\.\.\. +[ \t]+[0-9a-f]+: R_SH_FUNCDESC_VALUE[ \t]+\.text diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-funcdesc-shared.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-funcdesc-shared.s new file mode 100644 index 0000000..87d600d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-funcdesc-shared.s @@ -0,0 +1,10 @@ + .data + .globl bar + .type bar,@object + .size bar,4 +bar: + .long foo@FUNCDESC + .text + .type foo,@function +foo: + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-funcdesc-static.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-funcdesc-static.d new file mode 100644 index 0000000..cb09b90 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-funcdesc-static.d @@ -0,0 +1,25 @@ +#source: fdpic-funcdesc-static.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd +#objdump: -ds +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.text: + 400094 00090009[ \t]+.* +Contents of section \.rofixup: + 400098 004100ac 004100b0 004100a8 004100b4[ \t]+.* +Contents of section \.data: + 4100a8 004100ac[ \t]+.* +Contents of section \.got: + 4100ac 00400094 004100b4 00000000 00000000[ \t]+.* + 4100bc 00000000[ \t]+.* + +Disassembly of section \.text: + +00400094 <foo>: +[ \t]+400094:[ \t]+00 09[ \t]+nop[ \t]+ + +00400096 <_start>: +[ \t]+400096:[ \t]+00 09[ \t]+nop[ \t]+ diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-funcdesc-static.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-funcdesc-static.s new file mode 100644 index 0000000..f59e0d9 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-funcdesc-static.s @@ -0,0 +1,14 @@ + .data + .globl bar + .type bar,@object + .size bar,4 +bar: + .long foo@FUNCDESC + .text + .type foo,@function +foo: + nop + .globl _start + .type _start,@function +_start: + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesc-shared.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesc-shared.d new file mode 100644 index 0000000..c86b424 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesc-shared.d @@ -0,0 +1,25 @@ +#source: fdpic-gotfuncdesc-shared.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd -shared +#objdump: -dsR -j.text -j.got +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.text: + [0-9a-f]+ d00001ce 0000000c[ \t]+.* +Contents of section \.got: + [0-9a-f]+ 00000000 00000000 00000000 00000000[ \t]+.* + +Disassembly of section \.text: + +[0-9a-f]+ <f>: + [0-9a-f]+:[ \t]+d0 00[ \t]+mov\.l[ \t]+[0-9a-f]+ <f\+0x4>,r0[ \t]+! c + [0-9a-f]+:[ \t]+01 ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 + [0-9a-f]+:[ \t]+00 00 00 0c[ \t]+movi20[ \t]+#12,r0 + +Disassembly of section \.got: + +[0-9a-f]+ <\.got>: +[ \t]+\.\.\. +[ \t]+[0-9a-f]+: R_SH_FUNCDESC[ \t]+foo diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesc-shared.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesc-shared.s new file mode 100644 index 0000000..d75a061 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesc-shared.s @@ -0,0 +1,9 @@ + .text + .globl f + .type f,@function +f: + mov.l .L1, r0 + mov.l @(r0,r12), r1 + .align 2 +.L1: + .long foo@GOTFUNCDESC diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesc-static.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesc-static.d new file mode 100644 index 0000000..3da8c40 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesc-static.d @@ -0,0 +1,26 @@ +#source: fdpic-gotfuncdesc-static.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd +#objdump: -ds +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.text: + 400094 d00001ce 0000000c 00090009[ \t]+.* +Contents of section \.rofixup: + 4000a0 004100b0 004100b4 004100c4 004100b8[ \t]+.* +Contents of section \.got: + 4100b0 0040009c 004100b8 00000000 00000000[ \t]+.* + 4100c0 00000000 004100b0[ \t]+.* + +Disassembly of section \.text: + +00400094 <_start>: +[ \t]+400094:[ \t]+d0 00[ \t]+mov\.l[ \t]+400098 <_start\+0x4>,r0[ \t]+! c +[ \t]+400096:[ \t]+01 ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 +[ \t]+400098:[ \t]+00 00 00 0c[ \t]+movi20[ \t]+#12,r0 + +0040009c <foo>: +[ \t]+40009c:[ \t]+00 09[ \t]+nop[ \t]+ +[ \t]+40009e:[ \t]+00 09[ \t]+nop[ \t]+ diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesc-static.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesc-static.s new file mode 100644 index 0000000..fc403b7 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesc-static.s @@ -0,0 +1,12 @@ + .text + .globl _start + .type _start,@function +_start: + mov.l .L1, r0 + mov.l @(r0,r12), r1 + .align 2 +.L1: + .long foo@GOTFUNCDESC + .type foo,@function +foo: + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesci20-shared.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesci20-shared.d new file mode 100644 index 0000000..39eb610 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesci20-shared.d @@ -0,0 +1,24 @@ +#source: fdpic-gotfuncdesci20-shared.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd -shared +#objdump: -dsR -j.text -j.got +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.text: + [0-9a-f]+ 0000000c 01ce[ \t]+.* +Contents of section \.got: + [0-9a-f]+ 00000000 00000000 00000000 00000000[ \t]+.* + +Disassembly of section \.text: + +[0-9a-f]+ <f>: + [0-9a-f]+:[ \t]+00 00 00 0c[ \t]+movi20[ \t]+#12,r0 + [0-9a-f]+:[ \t]+01 ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 + +Disassembly of section \.got: + +[0-9a-f]+ <\.got>: +[ \t]+\.\.\. +[ \t]+[0-9a-f]+: R_SH_FUNCDESC[ \t]+foo diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesci20-shared.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesci20-shared.s new file mode 100644 index 0000000..736d30d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesci20-shared.s @@ -0,0 +1,6 @@ + .text + .globl f + .type f,@function +f: + movi20 #foo@GOTFUNCDESC, r0 + mov.l @(r0,r12), r1 diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesci20-static.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesci20-static.d new file mode 100644 index 0000000..246e8f3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesci20-static.d @@ -0,0 +1,24 @@ +#source: fdpic-gotfuncdesci20-static.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd +#objdump: -ds +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.text: + 400094 0000000c 01ce0009[ \t]+.* +Contents of section \.rofixup: + 40009c 004100ac 004100b0 004100c0 004100b4[ \t]+.* +Contents of section \.got: + 4100ac 0040009a 004100b4 00000000 00000000[ \t]+.* + 4100bc 00000000 004100ac[ \t]+.* + +Disassembly of section \.text: + +00400094 <_start>: +[ \t]+400094:[ \t]+00 00 00 0c[ \t]+movi20[ \t]+#12,r0 +[ \t]+400098:[ \t]+01 ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 + +0040009a <foo>: +[ \t]+40009a:[ \t]+00 09[ \t]+nop[ \t]+ diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesci20-static.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesci20-static.s new file mode 100644 index 0000000..76930f5 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotfuncdesci20-static.s @@ -0,0 +1,9 @@ + .text + .globl _start + .type _start,@function +_start: + movi20 #foo@GOTFUNCDESC, r0 + mov.l @(r0,r12), r1 + .type foo,@function +foo: + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-goti20-shared.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-goti20-shared.d new file mode 100644 index 0000000..0955770 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-goti20-shared.d @@ -0,0 +1,24 @@ +#source: fdpic-goti20-shared.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd -shared +#objdump: -dsR -j.text -j.got +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.text: + [0-9a-f]+ 0000000c 01ce[ \t]+.* +Contents of section \.got: + [0-9a-f]+ 00000000 00000000 00000000 00000000[ \t]+.* + +Disassembly of section \.text: + +[0-9a-f]+ <f>: + [0-9a-f]+:[ \t]+00 00 00 0c[ \t]+movi20[ \t]+#12,r0 + [0-9a-f]+:[ \t]+01 ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 + +Disassembly of section \.got: + +[0-9a-f]+ <\.got>: +[ \t]+\.\.\. +[ \t]+[0-9a-f]+: R_SH_GLOB_DAT[ \t]+foo diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-goti20-shared.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-goti20-shared.s new file mode 100644 index 0000000..08f5446 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-goti20-shared.s @@ -0,0 +1,6 @@ + .text + .globl f + .type f,@function +f: + movi20 #foo@GOT, r0 + mov.l @(r0,r12), r1 diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-goti20-static.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-goti20-static.d new file mode 100644 index 0000000..91f5299 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-goti20-static.d @@ -0,0 +1,22 @@ +#source: fdpic-goti20-static.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd +#objdump: -ds +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.text: + 400094 0000000c 01ce[ \t]+.* +Contents of section \.rofixup: + 40009c 004100b4 004100a8[ \t]+.* +Contents of section \.data: + 4100a4 00000001[ \t]+.* +Contents of section \.got: + 4100a8 00000000 00000000 00000000 004100a4[ \t]+.* + +Disassembly of section \.text: + +00400094 <_start>: +[ \t]+400094:[ \t]+00 00 00 0c[ \t]+movi20[ \t]+#12,r0 +[ \t]+400098:[ \t]+01 ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-goti20-static.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-goti20-static.s new file mode 100644 index 0000000..172a680 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-goti20-static.s @@ -0,0 +1,11 @@ + .text + .globl _start + .type _start,@function +_start: + movi20 #foo@GOT, r0 + mov.l @(r0,r12), r1 + .data + .type foo,@object + .size foo,4 +foo: + .long 1 diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesc-shared.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesc-shared.d new file mode 100644 index 0000000..c43721d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesc-shared.d @@ -0,0 +1,32 @@ +#source: fdpic-gotofffuncdesc-shared.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd -shared +#objdump: -dsR -j.text -j.got +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.text: + [0-9a-f]+ d10031cc fffffff8 00090009[ \t]+.* +Contents of section \.got: + [0-9a-f]+ 00000008 00000000 00000000 00000000[ \t]+.* + [0-9a-f]+ 00000000[ \t]+.* + +Disassembly of section \.text: + +[0-9a-f]+ <f>: + [0-9a-f]+:[ \t]+d1 00[ \t]+mov\.l[ \t]+[0-9a-f]+ <f\+0x4>,r1[ \t]+! fffffff8 + [0-9a-f]+:[ \t]+31 cc[ \t]+add[ \t]+r12,r1 + [0-9a-f]+:[ \t]+ff ff[ \t]+\.word 0xffff + [0-9a-f]+:[ \t]+ff f8[ \t]+fmov[ \t]+@r15,fr15 + +[0-9a-f]+ <foo>: + [0-9a-f]+:[ \t]+00 09[ \t]+nop[ \t]+ + [0-9a-f]+:[ \t]+00 09[ \t]+nop[ \t]+ + +Disassembly of section \.got: + +[0-9a-f]+ <\.got>: +[ \t]+[0-9a-f]+:[ \t]+00 00 00 08[ \t]+movi20[ \t]+#8,r0 +[ \t]+[0-9a-f]+: R_SH_FUNCDESC_VALUE[ \t]+\.text +[ \t]+\.\.\. diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesc-shared.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesc-shared.s new file mode 100644 index 0000000..daf1c84 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesc-shared.s @@ -0,0 +1,12 @@ + .text + .globl f + .type f,@function +f: + mov.l .L1, r1 + add r12, r1 + .align 2 +.L1: + .long foo@GOTOFFFUNCDESC + .type foo,@function +foo: + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesc-static.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesc-static.d new file mode 100644 index 0000000..5ff417f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesc-static.d @@ -0,0 +1,27 @@ +#source: fdpic-gotofffuncdesc-static.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd +#objdump: -ds +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.text: + 400094 d10031cc fffffff8 00090009[ \t]+.* +Contents of section \.rofixup: + 4000a0 004100ac 004100b0 004100b4[ \t]+.* +Contents of section \.got: + 4100ac 0040009c 004100b4 00000000 00000000[ \t]+.* + 4100bc 00000000[ \t]+.* + +Disassembly of section \.text: + +00400094 <_start>: +[ \t]+400094:[ \t]+d1 00[ \t]+mov\.l[ \t]+400098 <_start\+0x4>,r1[ \t]+! fffffff8 +[ \t]+400096:[ \t]+31 cc[ \t]+add[ \t]+r12,r1 +[ \t]+400098:[ \t]+ff ff[ \t]+\.word 0xffff +[ \t]+40009a:[ \t]+ff f8[ \t]+fmov[ \t]+@r15,fr15 + +0040009c <foo>: +[ \t]+40009c:[ \t]+00 09[ \t]+nop[ \t]+ +[ \t]+40009e:[ \t]+00 09[ \t]+nop[ \t]+ diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesc-static.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesc-static.s new file mode 100644 index 0000000..307ff1d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesc-static.s @@ -0,0 +1,12 @@ + .text + .globl _start + .type _start,@function +_start: + mov.l .L1, r1 + add r12, r1 + .align 2 +.L1: + .long foo@GOTOFFFUNCDESC + .type foo,@function +foo: + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesci20-shared.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesci20-shared.d new file mode 100644 index 0000000..c19abe6 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesci20-shared.d @@ -0,0 +1,29 @@ +#source: fdpic-gotofffuncdesci20-shared.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd -shared +#objdump: -dsR -j.text -j.got +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.text: + [0-9a-f]+ 01f0fff8 31cc0009[ \t]+.* +Contents of section \.got: + [0-9a-f]+ 00000006 00000000 00000000 00000000[ \t]+.* + [0-9a-f]+ 00000000[ \t]+.* + +Disassembly of section \.text: + +[0-9a-f]+ <f>: + [0-9a-f]+:[ \t]+01 f0 ff f8[ \t]+movi20[ \t]+#-8,r1 + [0-9a-f]+:[ \t]+31 cc[ \t]+add[ \t]+r12,r1 + +[0-9a-f]+ <foo>: + [0-9a-f]+:[ \t]+00 09[ \t]+nop[ \t]+ + +Disassembly of section \.got: + +[0-9a-f]+ <\.got>: +[ \t]+[0-9a-f]+:[ \t]+00 00 00 06[ \t]+movi20[ \t]+#6,r0 +[ \t]+[0-9a-f]+: R_SH_FUNCDESC_VALUE[ \t]+\.text +[ \t]+\.\.\. diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesci20-shared.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesci20-shared.s new file mode 100644 index 0000000..bf16011 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesci20-shared.s @@ -0,0 +1,9 @@ + .text + .globl f + .type f,@function +f: + movi20 #foo@GOTOFFFUNCDESC, r1 + add r12, r1 + .type foo,@function +foo: + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesci20-static.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesci20-static.d new file mode 100644 index 0000000..3b96f7e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesci20-static.d @@ -0,0 +1,24 @@ +#source: fdpic-gotofffuncdesci20-static.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd +#objdump: -ds +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.text: + 400094 01f0fff8 31cc0009[ \t]+.* +Contents of section \.rofixup: + 40009c 004100a8 004100ac 004100b0[ \t]+.* +Contents of section \.got: + 4100a8 0040009a 004100b0 00000000 00000000[ \t]+.* + 4100b8 00000000[ \t]+.* + +Disassembly of section \.text: + +00400094 <_start>: +[ \t]+400094:[ \t]+01 f0 ff f8[ \t]+movi20[ \t]+#-8,r1 +[ \t]+400098:[ \t]+31 cc[ \t]+add[ \t]+r12,r1 + +0040009a <foo>: +[ \t]+40009a:[ \t]+00 09[ \t]+nop[ \t]+ diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesci20-static.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesci20-static.s new file mode 100644 index 0000000..7017e0a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotofffuncdesci20-static.s @@ -0,0 +1,9 @@ + .text + .globl _start + .type _start,@function +_start: + movi20 #foo@GOTOFFFUNCDESC, r1 + add r12, r1 + .type foo,@function +foo: + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotoffi20-shared.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotoffi20-shared.d new file mode 100644 index 0000000..8b57e11 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotoffi20-shared.d @@ -0,0 +1,30 @@ +#source: fdpic-gotoffi20-shared.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd -shared +#objdump: -dsR -j.text -j.data -j.got +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.text: + [0-9a-f]+ 00f0fffc 01ce[ \t]+.* +Contents of section \.data: + [0-9a-f]+ 00000001[ \t]+.* +Contents of section \.got: + [0-9a-f]+ 00000000 00000000 00000000[ \t]+.* + +Disassembly of section \.text: + +[0-9a-f]+ <f>: + [0-9a-f]+:[ \t]+00 f0 ff fc[ \t]+movi20[ \t]+#-4,r0 + [0-9a-f]+:[ \t]+01 ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 + +Disassembly of section \.data: + +[0-9a-f]+ <foo>: +[ \t]+[0-9a-f]+:[ \t]+00 00 00 01[ \t]+\.\.\.\. + +Disassembly of section \.got: + +[0-9a-f]+ <\.got>: +[ \t]+\.\.\. diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotoffi20-shared.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotoffi20-shared.s new file mode 100644 index 0000000..fc8213c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotoffi20-shared.s @@ -0,0 +1,11 @@ + .text + .globl f + .type f,@function +f: + movi20 #foo@GOTOFF, r0 + mov.l @(r0,r12), r1 + .data + .type foo,@object + .size foo,4 +foo: + .long 1 diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotoffi20-static.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotoffi20-static.d new file mode 100644 index 0000000..9390720 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotoffi20-static.d @@ -0,0 +1,22 @@ +#source: fdpic-gotoffi20-static.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd +#objdump: -ds +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.text: + 400094 00f0fffc 01ce[ \t]+.* +Contents of section \.rofixup: + 40009c 004100a4[ \t]+.* +Contents of section \.data: + 4100a0 00000001[ \t]+.* +Contents of section \.got: + 4100a4 00000000 00000000 00000000[ \t]+.* + +Disassembly of section \.text: + +00400094 <_start>: +[ \t]+400094:[ \t]+00 f0 ff fc[ \t]+movi20[ \t]+#-4,r0 +[ \t]+400098:[ \t]+01 ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotoffi20-static.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotoffi20-static.s new file mode 100644 index 0000000..079255b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-gotoffi20-static.s @@ -0,0 +1,11 @@ + .text + .globl _start + .type _start,@function +_start: + movi20 #foo@GOTOFF, r0 + mov.l @(r0,r12), r1 + .data + .type foo,@object + .size foo,4 +foo: + .long 1 diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-plt-be.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-plt-be.d new file mode 100644 index 0000000..375e088 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-plt-be.d @@ -0,0 +1,75 @@ +#source: fdpic-plt.s +#as: --isa=sh4a -big --fdpic +#ld: -EB -mshelf_fd -shared +#objdump: -dsR -j.plt -j.text -j.got +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.plt: + [0-9a-f]+ d00201ce 7004412b 0cce0009 fffffff0[ \t]+.* + [0-9a-f]+ 00000000 60c2402b 53c10009 d00201ce[ \t]+.* + [0-9a-f]+ 7004412b 0cce0009 fffffff8 0000000c[ \t]+.* + [0-9a-f]+ 60c2402b 53c10009[ \t]+.* +Contents of section \.text: + [0-9a-f]+ d000d101 ffffffc4 ffffffdc[ \t]+.* +Contents of section \.got: + [0-9a-f]+ 0000023c 00000000 00000258 00000000[ \t]+.* + [0-9a-f]+ 00000000 00000000 00000000[ \t]+.* + +Disassembly of section \.plt: + +[0-9a-f]+ <foo@plt>: + [0-9a-f]+:[ \t]+d0 02[ \t]+mov\.l[ \t]+[0-9a-f]+ <foo@plt\+0xc>,r0[ \t]+! fffffff0 + [0-9a-f]+:[ \t]+01 ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 + [0-9a-f]+:[ \t]+70 04[ \t]+add[ \t]+#4,r0 + [0-9a-f]+:[ \t]+41 2b[ \t]+jmp[ \t]+@r1 + [0-9a-f]+:[ \t]+0c ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r12 + [0-9a-f]+:[ \t]+00 09[ \t]+nop[ \t]+ + [0-9a-f]+:[ \t]+ff ff[ \t]+\.word 0xffff + [0-9a-f]+:[ \t]+ff f0[ \t]+fadd[ \t]+fr15,fr15 + [0-9a-f]+:[ \t]+00 00[ \t]+\.word 0x0000 + [0-9a-f]+:[ \t]+00 00[ \t]+\.word 0x0000 + [0-9a-f]+:[ \t]+60 c2[ \t]+mov\.l[ \t]+@r12,r0 + [0-9a-f]+:[ \t]+40 2b[ \t]+jmp[ \t]+@r0 + [0-9a-f]+:[ \t]+53 c1[ \t]+mov\.l[ \t]+@\(4,r12\),r3 + [0-9a-f]+:[ \t]+00 09[ \t]+nop[ \t]+ + +[0-9a-f]+ <bar@plt>: + [0-9a-f]+:[ \t]+d0 02[ \t]+mov\.l[ \t]+[0-9a-f]+ <bar@plt\+0xc>,r0[ \t]+! fffffff8 + [0-9a-f]+:[ \t]+01 ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 + [0-9a-f]+:[ \t]+70 04[ \t]+add[ \t]+#4,r0 + [0-9a-f]+:[ \t]+41 2b[ \t]+jmp[ \t]+@r1 + [0-9a-f]+:[ \t]+0c ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r12 + [0-9a-f]+:[ \t]+00 09[ \t]+nop[ \t]+ + [0-9a-f]+:[ \t]+ff ff[ \t]+\.word 0xffff + [0-9a-f]+:[ \t]+ff f8[ \t]+fmov[ \t]+@r15,fr15 + [0-9a-f]+:[ \t]+00 00[ \t]+\.word 0x0000 + [0-9a-f]+:[ \t]+00 0c[ \t]+mov\.b[ \t]+@\(r0,r0\),r0 + [0-9a-f]+:[ \t]+60 c2[ \t]+mov\.l[ \t]+@r12,r0 + [0-9a-f]+:[ \t]+40 2b[ \t]+jmp[ \t]+@r0 + [0-9a-f]+:[ \t]+53 c1[ \t]+mov\.l[ \t]+@\(4,r12\),r3 + [0-9a-f]+:[ \t]+00 09[ \t]+nop[ \t]+ + +Disassembly of section \.text: + +[0-9a-f]+ <f>: + [0-9a-f]+:[ \t]+d0 00[ \t]+mov\.l[ \t]+[0-9a-f]+ <f\+0x4>,r0[ \t]+! ffffffc4 + [0-9a-f]+:[ \t]+d1 01[ \t]+mov\.l[ \t]+[0-9a-f]+ <f\+0x8>,r1[ \t]+! ffffffdc + [0-9a-f]+:[ \t]+ff ff[ \t]+\.word 0xffff + [0-9a-f]+:[ \t]+ff c4[ \t]+fcmp/eq[ \t]+fr12,fr15 + [0-9a-f]+:[ \t]+ff ff[ \t]+\.word 0xffff + [0-9a-f]+:[ \t]+ff dc[ \t]+fmov[ \t]+fr13,fr15 + +Disassembly of section \.got: + +[0-9a-f]+ <\.got>: +[ \t]+[0-9a-f]+:[ \t]+00 00[ \t]+\.word 0x0000 +[ \t]+[0-9a-f]+: R_SH_FUNCDESC_VALUE[ \t]+foo +[ \t]+[0-9a-f]+:[ \t]+02 3c[ \t]+mov.b[ \t]+@\(r0,r3\),r2 +[ \t]+[0-9a-f]+:[ \t]+00 00[ \t]+\.word 0x0000 +[ \t]+[0-9a-f]+:[ \t]+00 00[ \t]+\.word 0x0000 +[ \t]+[0-9a-f]+:[ \t]+00 00[ \t]+\.word 0x0000 +[ \t]+[0-9a-f]+: R_SH_FUNCDESC_VALUE[ \t]+bar +[ \t]+[0-9a-f]+:[ \t]+02 58[ \t]+\.word 0x0258 +[ \t]+\.\.\. diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-plt-le.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-plt-le.d new file mode 100644 index 0000000..4a3e55b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-plt-le.d @@ -0,0 +1,74 @@ +#source: fdpic-plt.s +#as: --isa=sh4a -little --fdpic +#ld: -EL -mshlelf_fd -shared +#objdump: -dsR -j.plt -j.text -j.got +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-sh-fdpic + +Contents of section \.plt: + [0-9a-f]+ 02d0ce01 04702b41 ce0c0900 f0ffffff[ \t]+.* + [0-9a-f]+ 00000000 c2602b40 c1530900 02d0ce01[ \t]+.* + [0-9a-f]+ 04702b41 ce0c0900 f8ffffff 0c000000[ \t]+.* + [0-9a-f]+ c2602b40 c1530900[ \t]+.* +Contents of section \.text: + [0-9a-f]+ 00d001d1 c4ffffff dcffffff[ \t]+.* +Contents of section \.got: + [0-9a-f]+ 3c020000 00000000 58020000 00000000[ \t]+.* + [0-9a-f]+ 00000000 00000000 00000000[ \t]+.* + +Disassembly of section \.plt: + +[0-9a-f]+ <foo@plt>: + [0-9a-f]+:[ \t]+02 d0[ \t]+mov\.l[ \t]+[0-9a-f]+ <foo@plt\+0xc>,r0[ \t]+! fffffff0 + [0-9a-f]+:[ \t]+ce 01[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 + [0-9a-f]+:[ \t]+04 70[ \t]+add[ \t]+#4,r0 + [0-9a-f]+:[ \t]+2b 41[ \t]+jmp[ \t]+@r1 + [0-9a-f]+:[ \t]+ce 0c[ \t]+mov\.l[ \t]+@\(r0,r12\),r12 + [0-9a-f]+:[ \t]+09 00[ \t]+nop[ \t]+ + [0-9a-f]+:[ \t]+f0 ff[ \t]+fadd[ \t]+fr15,fr15 + [0-9a-f]+:[ \t]+ff ff[ \t]+\.word 0xffff + [0-9a-f]+:[ \t]+00 00[ \t]+\.word 0x0000 + [0-9a-f]+:[ \t]+00 00[ \t]+\.word 0x0000 + [0-9a-f]+:[ \t]+c2 60[ \t]+mov\.l[ \t]+@r12,r0 + [0-9a-f]+:[ \t]+2b 40[ \t]+jmp[ \t]+@r0 + [0-9a-f]+:[ \t]+c1 53[ \t]+mov\.l[ \t]+@\(4,r12\),r3 + [0-9a-f]+:[ \t]+09 00[ \t]+nop[ \t]+ + +[0-9a-f]+ <bar@plt>: + [0-9a-f]+:[ \t]+02 d0[ \t]+mov\.l[ \t]+[0-9a-f]+ <bar@plt\+0xc>,r0[ \t]+! fffffff8 + [0-9a-f]+:[ \t]+ce 01[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 + [0-9a-f]+:[ \t]+04 70[ \t]+add[ \t]+#4,r0 + [0-9a-f]+:[ \t]+2b 41[ \t]+jmp[ \t]+@r1 + [0-9a-f]+:[ \t]+ce 0c[ \t]+mov\.l[ \t]+@\(r0,r12\),r12 + [0-9a-f]+:[ \t]+09 00[ \t]+nop[ \t]+ + [0-9a-f]+:[ \t]+f8 ff[ \t]+fmov[ \t]+@r15,fr15 + [0-9a-f]+:[ \t]+ff ff[ \t]+\.word 0xffff + [0-9a-f]+:[ \t]+0c 00[ \t]+mov\.b[ \t]+@\(r0,r0\),r0 + [0-9a-f]+:[ \t]+00 00[ \t]+\.word 0x0000 + [0-9a-f]+:[ \t]+c2 60[ \t]+mov\.l[ \t]+@r12,r0 + [0-9a-f]+:[ \t]+2b 40[ \t]+jmp[ \t]+@r0 + [0-9a-f]+:[ \t]+c1 53[ \t]+mov\.l[ \t]+@\(4,r12\),r3 + [0-9a-f]+:[ \t]+09 00[ \t]+nop[ \t]+ + +Disassembly of section \.text: + +[0-9a-f]+ <f>: + [0-9a-f]+:[ \t]+00 d0[ \t]+mov\.l[ \t]+[0-9a-f]+ <f\+0x4>,r0[ \t]+! ffffffc4 + [0-9a-f]+:[ \t]+01 d1[ \t]+mov\.l[ \t]+[0-9a-f]+ <f\+0x8>,r1[ \t]+! ffffffdc + [0-9a-f]+:[ \t]+c4 ff[ \t]+fcmp/eq[ \t]+fr12,fr15 + [0-9a-f]+:[ \t]+ff ff[ \t]+\.word 0xffff + [0-9a-f]+:[ \t]+dc ff[ \t]+fmov[ \t]+fr13,fr15 + [0-9a-f]+:[ \t]+ff ff[ \t]+\.word 0xffff + +Disassembly of section \.got: + +[0-9a-f]+ <\.got>: +[ \t]+[0-9a-f]+:[ \t]+3c 02[ \t]+mov.b[ \t]+@\(r0,r3\),r2 +[ \t]+[0-9a-f]+: R_SH_FUNCDESC_VALUE[ \t]+foo +[ \t]+[0-9a-f]+:[ \t]+00 00[ \t]+\.word 0x0000 +[ \t]+[0-9a-f]+:[ \t]+00 00[ \t]+\.word 0x0000 +[ \t]+[0-9a-f]+:[ \t]+00 00[ \t]+\.word 0x0000 +[ \t]+[0-9a-f]+:[ \t]+58 02[ \t]+\.word 0x0258 +[ \t]+[0-9a-f]+: R_SH_FUNCDESC_VALUE[ \t]+bar +[ \t]+\.\.\. diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-plt.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-plt.s new file mode 100644 index 0000000..e873d3e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-plt.s @@ -0,0 +1,11 @@ + .text + .globl f + .type f,@function +f: + mov.l .L1, r0 + mov.l .L2, r1 + .align 2 +.L1: + .long foo@PLT +.L2: + .long bar@PLT diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-plti20-be.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-plti20-be.d new file mode 100644 index 0000000..282b34b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-plti20-be.d @@ -0,0 +1,63 @@ +#source: fdpic-plt.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd -shared +#objdump: -dsR -j.plt -j.text -j.got +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-shbig-fdpic + +Contents of section \.plt: + [0-9a-f]+ 00f0fff0 01ce7004 412b0cce 00000000[ \t]+.* + [0-9a-f]+ 60c2402b 53c10009 00f0fff8 01ce7004[ \t]+.* + [0-9a-f]+ 412b0cce 0000000c 60c2402b 53c10009[ \t]+.* +Contents of section \.text: + [0-9a-f]+ d000d101 ffffffcc ffffffe0[ \t]+.* +Contents of section \.got: + [0-9a-f]+ 00000238 00000000 00000250 00000000[ \t]+.* + [0-9a-f]+ 00000000 00000000 00000000[ \t]+.* + +Disassembly of section \.plt: + +[0-9a-f]+ <foo@plt>: + [0-9a-f]+:[ \t]+00 f0 ff f0[ \t]+movi20[ \t]+#-16,r0 + [0-9a-f]+:[ \t]+01 ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 + [0-9a-f]+:[ \t]+70 04[ \t]+add[ \t]+#4,r0 + [0-9a-f]+:[ \t]+41 2b[ \t]+jmp[ \t]+@r1 + [0-9a-f]+:[ \t]+0c ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r12 + [0-9a-f]+:[ \t]+00 00 00 00[ \t]+movi20[ \t]+#0,r0 + [0-9a-f]+:[ \t]+60 c2[ \t]+mov\.l[ \t]+@r12,r0 + [0-9a-f]+:[ \t]+40 2b[ \t]+jmp[ \t]+@r0 + [0-9a-f]+:[ \t]+53 c1[ \t]+mov\.l[ \t]+@\(4,r12\),r3 + [0-9a-f]+:[ \t]+00 09[ \t]+nop[ \t]+ + +[0-9a-f]+ <bar@plt>: + [0-9a-f]+:[ \t]+00 f0 ff f8[ \t]+movi20[ \t]+#-8,r0 + [0-9a-f]+:[ \t]+01 ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 + [0-9a-f]+:[ \t]+70 04[ \t]+add[ \t]+#4,r0 + [0-9a-f]+:[ \t]+41 2b[ \t]+jmp[ \t]+@r1 + [0-9a-f]+:[ \t]+0c ce[ \t]+mov\.l[ \t]+@\(r0,r12\),r12 + [0-9a-f]+:[ \t]+00 00 00 0c[ \t]+movi20[ \t]+#12,r0 + [0-9a-f]+:[ \t]+60 c2[ \t]+mov\.l[ \t]+@r12,r0 + [0-9a-f]+:[ \t]+40 2b[ \t]+jmp[ \t]+@r0 + [0-9a-f]+:[ \t]+53 c1[ \t]+mov\.l[ \t]+@\(4,r12\),r3 + [0-9a-f]+:[ \t]+00 09[ \t]+nop[ \t]+ + +Disassembly of section \.text: + +[0-9a-f]+ <f>: + [0-9a-f]+:[ \t]+d0 00[ \t]+mov\.l[ \t]+[0-9a-f]+ <f\+0x4>,r0[ \t]+! ffffffcc + [0-9a-f]+:[ \t]+d1 01[ \t]+mov\.l[ \t]+[0-9a-f]+ <f\+0x8>,r1[ \t]+! ffffffe0 + [0-9a-f]+:[ \t]+ff ff[ \t]+\.word 0xffff + [0-9a-f]+:[ \t]+ff cc[ \t]+fmov[ \t]+fr12,fr15 + [0-9a-f]+:[ \t]+ff ff[ \t]+\.word 0xffff + [0-9a-f]+:[ \t]+ff e0[ \t]+fadd[ \t]+fr14,fr15 + +Disassembly of section \.got: + +[0-9a-f]+ <\.got>: +[ \t]+[0-9a-f]+:[ \t]+00 00 02 38[ \t]+movi20[ \t]+#568,r0 +[ \t]+[0-9a-f]+: R_SH_FUNCDESC_VALUE[ \t]+foo +[ \t]+[0-9a-f]+:[ \t]+00 00 00 00[ \t]+movi20[ \t]+#0,r0 +[ \t]+[0-9a-f]+:[ \t]+00 00 02 50[ \t]+movi20[ \t]+#592,r0 +[ \t]+[0-9a-f]+: R_SH_FUNCDESC_VALUE[ \t]+bar +[ \t]+\.\.\. diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-plti20-le.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-plti20-le.d new file mode 100644 index 0000000..74e1e9b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-plti20-le.d @@ -0,0 +1,63 @@ +#source: fdpic-plt.s +#as: --isa=sh2a -little --fdpic +#ld: -EL -mshlelf_fd -shared +#objdump: -dsR -j.plt -j.text -j.got +#target: sh*-*-uclinux* + +.*:[ \t]+file format elf32-sh-fdpic + +Contents of section \.plt: + [0-9a-f]+ f000f0ff ce010470 2b41ce0c 00000000[ \t]+.* + [0-9a-f]+ c2602b40 c1530900 f000f8ff ce010470[ \t]+.* + [0-9a-f]+ 2b41ce0c 0c000000 c2602b40 c1530900[ \t]+.* +Contents of section \.text: + [0-9a-f]+ 00d001d1 ccffffff e0ffffff[ \t]+.* +Contents of section \.got: + [0-9a-f]+ 38020000 00000000 50020000 00000000[ \t]+.* + [0-9a-f]+ 00000000 00000000 00000000[ \t]+.* + +Disassembly of section \.plt: + +[0-9a-f]+ <foo@plt>: + [0-9a-f]+:[ \t]+f0 00 f0 ff[ \t]+movi20[ \t]+#-16,r0 + [0-9a-f]+:[ \t]+ce 01[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 + [0-9a-f]+:[ \t]+04 70[ \t]+add[ \t]+#4,r0 + [0-9a-f]+:[ \t]+2b 41[ \t]+jmp[ \t]+@r1 + [0-9a-f]+:[ \t]+ce 0c[ \t]+mov\.l[ \t]+@\(r0,r12\),r12 + [0-9a-f]+:[ \t]+00 00 00 00[ \t]+movi20[ \t]+#0,r0 + [0-9a-f]+:[ \t]+c2 60[ \t]+mov\.l[ \t]+@r12,r0 + [0-9a-f]+:[ \t]+2b 40[ \t]+jmp[ \t]+@r0 + [0-9a-f]+:[ \t]+c1 53[ \t]+mov\.l[ \t]+@\(4,r12\),r3 + [0-9a-f]+:[ \t]+09 00[ \t]+nop[ \t]+ + +[0-9a-f]+ <bar@plt>: + [0-9a-f]+:[ \t]+f0 00 f8 ff[ \t]+movi20[ \t]+#-8,r0 + [0-9a-f]+:[ \t]+ce 01[ \t]+mov\.l[ \t]+@\(r0,r12\),r1 + [0-9a-f]+:[ \t]+04 70[ \t]+add[ \t]+#4,r0 + [0-9a-f]+:[ \t]+2b 41[ \t]+jmp[ \t]+@r1 + [0-9a-f]+:[ \t]+ce 0c[ \t]+mov\.l[ \t]+@\(r0,r12\),r12 + [0-9a-f]+:[ \t]+0c 00[ \t]+mov\.b[ \t]+@\(r0,r0\),r0 + [0-9a-f]+:[ \t]+00 00 c2 60[ \t]+movi20[ \t]+#24770,r0 + [0-9a-f]+:[ \t]+2b 40[ \t]+jmp[ \t]+@r0 + [0-9a-f]+:[ \t]+c1 53[ \t]+mov\.l[ \t]+@\(4,r12\),r3 + [0-9a-f]+:[ \t]+09 00[ \t]+nop[ \t]+ + +Disassembly of section \.text: + +[0-9a-f]+ <f>: + [0-9a-f]+:[ \t]+00 d0[ \t]+mov\.l[ \t]+[0-9a-f]+ <f\+0x4>,r0[ \t]+! ffffffcc + [0-9a-f]+:[ \t]+01 d1[ \t]+mov\.l[ \t]+[0-9a-f]+ <f\+0x8>,r1[ \t]+! ffffffe0 + [0-9a-f]+:[ \t]+cc ff[ \t]+fmov[ \t]+fr12,fr15 + [0-9a-f]+:[ \t]+ff ff[ \t]+\.word 0xffff + [0-9a-f]+:[ \t]+e0 ff[ \t]+fadd[ \t]+fr14,fr15 + [0-9a-f]+:[ \t]+ff ff[ \t]+\.word 0xffff + +Disassembly of section \.got: + +[0-9a-f]+ <\.got>: +[ \t]+[0-9a-f]+:[ \t]+38 02[ \t]+\.word[ \t]+0x0238 +[ \t]+[0-9a-f]+: R_SH_FUNCDESC_VALUE[ \t]+foo +[ \t]+[0-9a-f]+:[ \t]+00 00 00 00[ \t]+movi20[ \t]+#0,r0 +[ \t]+[0-9a-f]+:[ \t]+00 00 50 02[ \t]+movi20[ \t]+#592,r0 +[ \t]+[0-9a-f]+: R_SH_FUNCDESC_VALUE[ \t]+bar +[ \t]+\.\.\. diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-stack-default.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-stack-default.d new file mode 100644 index 0000000..8f9fd92 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-stack-default.d @@ -0,0 +1,19 @@ +#source: fdpic-stack.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd +#readelf: -l +#target: sh*-*-uclinux* + +Elf file type is EXEC \(Executable file\) +Entry point 0x400074 +There are 2 program headers, starting at offset 52 + +Program Headers: +[ \t]+Type[ \t]+Offset[ \t]+VirtAddr[ \t]+PhysAddr[ \t]+FileSiz MemSiz[ \t]+Flg Align +[ \t]+LOAD[ \t]+0x000000 0x00400000 0x00400000 0x00076 0x00076 R E 0x10000 +[ \t]+GNU_STACK[ \t]+0x000000 0x00000000 0x00000000 0x00000 0x20000 RWE 0x8 + + Section to Segment mapping: +[ \t]+Segment Sections\.\.\. +[ \t]+00[ \t]+\.text +[ \t]+01[ \t]+ diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-stack-size.d b/binutils-2.21/ld/testsuite/ld-sh/fdpic-stack-size.d new file mode 100644 index 0000000..f993a2a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-stack-size.d @@ -0,0 +1,19 @@ +#source: fdpic-stack.s +#as: --isa=sh2a -big --fdpic +#ld: -EB -mshelf_fd --defsym __stacksize=0x40000 +#readelf: -l +#target: sh*-*-uclinux* + +Elf file type is EXEC \(Executable file\) +Entry point 0x400074 +There are 2 program headers, starting at offset 52 + +Program Headers: +[ \t]+Type[ \t]+Offset[ \t]+VirtAddr[ \t]+PhysAddr[ \t]+FileSiz MemSiz[ \t]+Flg Align +[ \t]+LOAD[ \t]+0x000000 0x00400000 0x00400000 0x00076 0x00076 R E 0x10000 +[ \t]+GNU_STACK[ \t]+0x000000 0x00000000 0x00000000 0x00000 0x40000 RWE 0x8 + + Section to Segment mapping: +[ \t]+Segment Sections\.\.\. +[ \t]+00[ \t]+\.text +[ \t]+01[ \t]+ diff --git a/binutils-2.21/ld/testsuite/ld-sh/fdpic-stack.s b/binutils-2.21/ld/testsuite/ld-sh/fdpic-stack.s new file mode 100644 index 0000000..b0421ea --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/fdpic-stack.s @@ -0,0 +1,5 @@ + .text + .globl _start + .type _start,@function +_start: + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/ld-r-1.d b/binutils-2.21/ld/testsuite/ld-sh/ld-r-1.d new file mode 100644 index 0000000..1c629b3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/ld-r-1.d @@ -0,0 +1,24 @@ +#source: ldr1.s +#source: ldr2.s +#as: -little +#ld: -r -EL +#readelf: -r -x1 -x2 +#target: sh*-*-elf sh*-*-linux* +#notarget: sh64*-*-linux* + +# Make sure relocations against global and local symbols with relative and +# absolute 32-bit relocs don't come out wrong after ld -r. Remember that +# SH uses partial_inplace (sort-of REL within RELA) with its confusion +# where and which addends to use and how. A file linked -r must have the +# same layout as a plain assembly file: the addend is in the data only. + +Relocation section '\.rela\.text' at offset 0x[0-9a-f]+ contains 1 entries: +.* +00000008 00000101 R_SH_DIR32 +00000000 +\.text +\+ 0 + +Hex dump of section '\.text': +.* + 0x00000000 09000900 09000900 0c000000 .* + +Hex dump of section '\.rela\.text': + 0x00000000 08000000 01010000 00000000 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/ldr1.s b/binutils-2.21/ld/testsuite/ld-sh/ldr1.s new file mode 100644 index 0000000..9f49389 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/ldr1.s @@ -0,0 +1,5 @@ + .text + nop + nop + nop + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/ldr2.s b/binutils-2.21/ld/testsuite/ld-sh/ldr2.s new file mode 100644 index 0000000..94e0658 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/ldr2.s @@ -0,0 +1,3 @@ + .text + .long bar +bar: diff --git a/binutils-2.21/ld/testsuite/ld-sh/rd-sh.exp b/binutils-2.21/ld/testsuite/ld-sh/rd-sh.exp new file mode 100644 index 0000000..b600961 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/rd-sh.exp @@ -0,0 +1,71 @@ +# Expect script for run_dump_test based ld-sh tests. +# Copyright 2001, 2002, 2003, 2005, 2006, 2007 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. +# +# Written by Hans-Peter Nilsson (hp@bitrange.com) +# + +# This file is kept separate from sh.exp, because having it separate +# simplifies selective testing, like in "make check-ld +# RUNTESTFLAGS=rd-sh.exp=shared-1". It is assumed that sh.exp is a place +# for constructs where the name of the test is harder to extract and +# select than here. + +if ![istarget sh*-*-*] { + return +} + +global ASFLAGS +global LDFLAGS +set asflags_save "$ASFLAGS" +set ldflags_save "$LDFLAGS" + +if {[istarget sh64*-*-*] || [istarget sh5*-*-*]} then { + set ASFLAGS "$ASFLAGS -isa=SHcompact" + if [istarget sh64*-*-linux*] { + set LDFLAGS "$LDFLAGS -mshlelf32_linux" + } elseif { [istarget sh64*-*-netbsd*] || [istarget sh5*-*-netbsd*] } { + set LDFLAGS "$LDFLAGS -mshlelf32_nbsd -e_start" + } else { + set LDFLAGS "$LDFLAGS -mshlelf32" + } +} + +set rd_test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]] +foreach shtest $rd_test_list { + # We need to strip the ".d", but can leave the dirname. + verbose [file rootname $shtest] + # vxworks-static.d relies on files created by sh-vxworks.exp. + # We run it there instead of here. + if { [file tail $shtest] != "vxworks1-static.d" } { + run_dump_test [file rootname $shtest] + } + if [string match $srcdir/$subdir/*-dso.d $shtest] { + # Copy the output of the DSO-createing test to .so file. + # Notice that a DSO-creating test must preceed the tests + # which need that DSO in sort-order by name. + set cmd "cp tmpdir/dump tmpdir/[file rootname [file tail $shtest]].so" + send_log "$cmd\n" + set cmdret [catch "exec $cmd" comp_output] + send_log "$comp_output\n" + # FIXME: What if it fails? Need we do something? + } +} +set ASFLAGS "$asflags_save" +set LDFLAGS "$ldflags_save" diff --git a/binutils-2.21/ld/testsuite/ld-sh/refdbg-0-dso.d b/binutils-2.21/ld/testsuite/ld-sh/refdbg-0-dso.d new file mode 100644 index 0000000..a8ec206 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/refdbg-0-dso.d @@ -0,0 +1,9 @@ +#source: refdbglib.s +#as: -little +#ld: -shared -EL +#objdump: -dr +#target: sh*-*-linux* sh*-*-netbsd* + +.*: +file format elf32-sh.* + +#pass diff --git a/binutils-2.21/ld/testsuite/ld-sh/refdbg-1.d b/binutils-2.21/ld/testsuite/ld-sh/refdbg-1.d new file mode 100644 index 0000000..461788e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/refdbg-1.d @@ -0,0 +1,10 @@ +#source: refdbg.s +#as: -little +#ld: -EL tmpdir/refdbg-0-dso.so +#objdump: -sj.debug_info +#target: sh*-*-linux* sh*-*-netbsd* + +.*: +file format elf32-sh.* + +Contents of section \.debug_info: + 0+0 0+0 +.* diff --git a/binutils-2.21/ld/testsuite/ld-sh/refdbg.s b/binutils-2.21/ld/testsuite/ld-sh/refdbg.s new file mode 100644 index 0000000..268fa16 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/refdbg.s @@ -0,0 +1,12 @@ + .text + .align 2 + .globl _start + .type _start,@function +_start: + rts + nop + + .comm foo,4,4 + .section .debug_info,"",@progbits + .long 0 + .ualong foo diff --git a/binutils-2.21/ld/testsuite/ld-sh/refdbglib.s b/binutils-2.21/ld/testsuite/ld-sh/refdbglib.s new file mode 100644 index 0000000..31244ac --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/refdbglib.s @@ -0,0 +1,8 @@ + .text + .global foo + .data + .align 2 + .type foo, @object + .size foo, 4 +foo: + .long 1 diff --git a/binutils-2.21/ld/testsuite/ld-sh/reloc1.d b/binutils-2.21/ld/testsuite/ld-sh/reloc1.d new file mode 100644 index 0000000..b56cd7d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/reloc1.d @@ -0,0 +1,10 @@ +#source: reloc1.s +#as: -big +#ld: -shared -EB --defsym foo=0x9000 +#objdump: -sj.data +#target: sh*-*-elf sh-*-vxworks + +.*: file format elf32-sh.* + +Contents of section \.data: + .* 9123 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/reloc1.s b/binutils-2.21/ld/testsuite/ld-sh/reloc1.s new file mode 100644 index 0000000..e579034 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/reloc1.s @@ -0,0 +1,2 @@ + .data + .word foo + 0x123 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh-vxworks.exp b/binutils-2.21/ld/testsuite/ld-sh/sh-vxworks.exp new file mode 100644 index 0000000..09e2cee --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh-vxworks.exp @@ -0,0 +1,62 @@ +# Expect script for VxWorks targeted SH linker tests +# Copyright 2006, 2007 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. + +if { ![istarget "sh-*-vxworks"] } { + return +} + +set endians { "--big" "-EB" "" "--little" "-EL" "-le" } + +foreach { gas_option ld_option suffix } $endians { + set vxworkstests { + {"VxWorks shared library test 1" "-shared -Tvxworks1.ld $ld_option" + "$gas_option" {vxworks1-lib.s} + {{readelf --relocs vxworks1-lib.rd} + {objdump -dr vxworks1-lib$suffix.dd} + {readelf --symbols vxworks1-lib.nd} {readelf -d vxworks1-lib.td}} + "libvxworks1.so"} + {"VxWorks executable test 1 (dynamic)" \ + "tmpdir/libvxworks1.so -Tvxworks1.ld -q --force-dynamic $ld_option" + "$gas_option" {vxworks1.s} + {{readelf --relocs vxworks1.rd} {objdump -dr vxworks1$suffix.dd}} + "vxworks1"} + {"VxWorks executable test 2 (dynamic)" \ + "-Tvxworks1.ld -q --force-dynamic $ld_option" + "$gas_option" {vxworks2.s} + {{readelf --segments vxworks2.sd}} + "vxworks2"} + {"VxWorks executable test 2 (static)" + "-Tvxworks1.ld $ld_option" + "$gas_option" {vxworks2.s} + {{readelf --segments vxworks2-static.sd}} + "vxworks2"} + {"VxWorks shared library test 3" "-shared -Tvxworks1.ld $ld_option" + "$gas_option" {vxworks3-lib.s} + {{objdump -dr vxworks3-lib$suffix.dd}} + "libvxworks3.so"} + {"VxWorks executable test 3 (dynamic)" \ + "tmpdir/libvxworks3.so -Tvxworks1.ld -q --force-dynamic $ld_option" + "$gas_option" {vxworks3.s} + {{objdump -d vxworks3$suffix.dd}} + "vxworks3"} + } + run_ld_link_tests [subst $vxworkstests] +} +run_dump_test "vxworks1-static" diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh.exp b/binutils-2.21/ld/testsuite/ld-sh/sh.exp new file mode 100644 index 0000000..90afaee --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh.exp @@ -0,0 +1,168 @@ +# Expect script for ld-sh tests +# Copyright 1995, 1996, 1997, 2001, 2002, 2003, 2005, 2006, 2007, 2010 +# Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. +# +# Written by Ian Lance Taylor (ian@cygnus.com) +# + +# Test SH relaxing. This tests the compiler and assembler as well as +# the linker. + +if ![istarget sh*-*-*] { + return +} + +if { ([istarget sh64*-*-*] || [istarget sh5*-*-*])} { + # relaxing not supported on sh64 yet. + return +} + +set testsimple "SH simple relaxing" + +if ![ld_assemble $as "-relax $srcdir/$subdir/sh1.s" tmpdir/sh1.o] { + unresolved $testsimple +} else { if ![ld_simple_link $ld tmpdir/sh1 "-relax tmpdir/sh1.o"] { + fail $testsimple +} else { + if ![ld_nm $nm "" tmpdir/sh1] { + unresolved $testsimple + } else { + if {![info exists nm_output(bar)] \ + || ![info exists nm_output(foo)]} { + send_log "bad output from nm\n" + verbose "bad output from nm" + fail $testsimple + } else { + if {$nm_output(bar) != $nm_output(foo) + 4} { + send_log "foo == $nm_output(foo)\n" + verbose "foo == $nm_output(foo)" + send_log "bar == $nm_output(bar)\n" + verbose "bar == $nm_output(bar)" + fail $testsimple + } else { + pass $testsimple + } + } + } +} } + +set testsrec "SH relaxing to S-records" + +if { [istarget sh*-linux-*] || [istarget sh-*-vxworks] } { + # On these "non-embedded" targets, the default ELF and srec start + # addresses will be SIZEOF_HEADERS bytes apart. Ensure consistency + # by feeding the ELF start address to the srec link line. + catch "exec $objdump -x tmpdir/sh1 | grep start\\ address | sed s/start\\ address//" entry_addr + set srec_relax_arg "-Ttext $entry_addr -relax --oformat srec tmpdir/sh1.o" +} else { + set srec_relax_arg "-relax --oformat srec tmpdir/sh1.o" +} +if ![ld_simple_link $ld tmpdir/sh1.s1 $srec_relax_arg ] { + fail $testsrec +} else { + # The file name is embedded in the S-records, so create both + # files with the same name. + catch "exec rm -f tmpdir/sh1.s2" exec_output + send_log "mv tmpdir/sh1.s1 tmpdir/sh1.s2\n" + verbose "mv tmpdir/sh1.s1 tmpdir/sh1.s2" + catch "exec mv tmpdir/sh1.s1 tmpdir/sh1.s2" exec_output + if ![string match "" $exec_output] { + send_log "$exec_output\n" + verbose "$exec_output" + unresolved $testsrec + } else { + send_log "$objcopy -O srec tmpdir/sh1 tmpdir/sh1.s1\n" + verbose "$objcopy -O srec tmpdir/sh1 tmpdir/sh1.s1" + catch "exec $objcopy -O srec tmpdir/sh1 tmpdir/sh1.s1" exec_output + if ![string match "" $exec_output] { + send_log "$exec_output\n" + verbose "$exec_output" + unresolved $testsrec + } else { + send_log "cmp tmpdir/sh1.s1 tmpdir/sh1.s2\n" + verbose "cmp tmpdir/sh1.s1 tmpdir/sh1.s2" + catch "exec cmp tmpdir/sh1.s1 tmpdir/sh1.s2" exec_output + set exec_output [prune_warnings $exec_output] + if ![string match "" $exec_output] { + send_log "$exec_output\n" + verbose "$exec_output" + fail $testsrec + } else { + pass $testsrec + } + } + } +} + +set testlink "SH relaxing" +set testjsr "SH confirm relaxing" +set testrun "SH relaxing execution" + +if { [which $CC] == 0 } { + untested $testlink + untested $testjsr + untested $testrun + return +} + +if [istarget sh*-*linux*] { + exec sed -e s/_main/main/ -e s/_trap/trap/ -e s/_stack/stack/ \ + < $srcdir/$subdir/start.s >tmpdir/start.s +} else { + exec cp $srcdir/$subdir/start.s tmpdir/start.s +} + +if {![ld_assemble $as "-relax tmpdir/start.s" tmpdir/start.o] \ + || ![ld_compile $CC "-O -mrelax $srcdir/$subdir/sh2.c" tmpdir/sh2.o]} { + unresolved $testlink + unresolved $testjsr + unresolved $testrun + return +} + +if ![ld_simple_link $ld tmpdir/sh2 "-relax tmpdir/start.o tmpdir/sh2.o"] { + fail $testlink + unresolved $testjsr + unresolved $testrun + return +} + +pass $testlink + +send_log "$objdump -d tmpdir/sh2\n" +verbose "$objdump -d tmpdir/sh2" +catch "exec $objdump -d tmpdir/sh2" exec_output +if [string match "*jsr*" $exec_output] { + fail $testjsr +} else { + pass $testjsr +} + +if { ![info exists SIM] || [which $SIM] == 0 } { + untested $testrun + return +} + +set status [catch "exec $SIM tmpdir/sh2" exec_output] +if { $status == 0 } { + pass $testrun +} else { + fail $testrun +} diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh1.s b/binutils-2.21/ld/testsuite/ld-sh/sh1.s new file mode 100644 index 0000000..d18e439 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh1.s @@ -0,0 +1,13 @@ + .text +foo: +L1: + mov.l L2,r0 + .uses L1 + jsr @r0 + rts + .align 2 +L2: + .long bar +bar: + rts + .align 4 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh2.c b/binutils-2.21/ld/testsuite/ld-sh/sh2.c new file mode 100644 index 0000000..527fe88 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh2.c @@ -0,0 +1,120 @@ +int global; + +extern void trap (int, int); +static void quit (int); +static int foo (int); + +int +main () +{ + if (foo (0) != 0 || global != 0) + quit (1); + if (foo (1) != 1 || global != 1) + quit (1); + if (foo (2) != 2 || global != 2) + quit (1); + if (foo (3) != 3 || global != 3) + quit (1); + if (foo (4) != 4 || global != 4) + quit (1); + if (foo (5) != 5 || global != 5) + quit (1); + if (foo (6) != 6 || global != 6) + quit (1); + if (foo (7) != 7 || global != 7) + quit (1); + if (foo (8) != 8 || global != 8) + quit (1); + quit (0); +} + +void +__main () +{ +} + +static void +quit (int status) +{ + trap (1, status); +} + +int +bar (int i) +{ + global = i; + return i; +} + +int +bar0 (int i) +{ + global = 0; + return i; +} + +int +bar1 (int i) +{ + global = 1; + return i; +} + +int +bar2 (int i) +{ + global = 2; + return i; +} + +int +bar3 (int i) +{ + global = 3; + return i; +} + +int +bar4 (int i) +{ + global = 4; + return i; +} + +int +bar5 (int i) +{ + global = 5; + return i; +} + +int +bar6 (int i) +{ + global = 6; + return i; +} + +int +bar7 (int i) +{ + global = 7; + return i; +} + +int +foo (int i) +{ + switch (i) + { + case 0: bar0 (0); return 0; + case 1: bar1 (1); return 1; + case 2: bar2 (2); return 2; + case 3: bar3 (3); return 3; + case 4: bar4 (4); return 4; + case 5: bar5 (5); return 5; + case 6: bar6 (6); return 6; + case 7: bar7 (7); return 7; + default: return bar (i); + } +} diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/abi32.sd b/binutils-2.21/ld/testsuite/ld-sh/sh64/abi32.sd new file mode 100644 index 0000000..8b22e46 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/abi32.sd @@ -0,0 +1,16 @@ + +.*: file format .*-sh64.* + +Contents of section \.text: + 1000 cc000190 c8015590 6bf56630 6ff0fff0 .* + 1010 cc000210 c8400610 cc000150 c8403550 .* + 1020 cffffd90 cbff9590 6bf56630 cc0002b0 .* + 1030 c843e2b0 cc000350 c843c350 cc000040 .* + 1040 c843f040 cc000190 c8004590 6bf56650 .* + 1050 cc000190 c8002590 6bf56410 6ff0fff0 .* + 1060 6ff0fff0 .* +Contents of section \.data: + 10e8 000010f4 0000100d 0000105d 000010e8 .* + 10f8 000010e8 0000100d .* +Contents of section \.stack: + 80000 deaddead .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/abi32.xd b/binutils-2.21/ld/testsuite/ld-sh/sh64/abi32.xd new file mode 100644 index 0000000..94b1014 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/abi32.xd @@ -0,0 +1,45 @@ + +.*: file format .*-sh64 +.* +architecture: sh5, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x0+1011 + +Program Header: + LOAD off 0x0+100 vaddr 0x0+1000 paddr 0x0+1000 align 2\*\*7 + filesz 0x0+64 memsz 0x0+64 flags r-x + LOAD off 0x0+168 vaddr 0x0+10e8 paddr 0x0+10e8 align 2\*\*7 + filesz 0x0+18 memsz 0x0+18 flags rw- + LOAD off 0x0+180 vaddr 0x0+80000 paddr 0x0+80000 align 2\*\*7 + filesz 0x0+4 memsz 0x0+4 flags rw- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.text 00000064 0+1000 0+1000 00000100 2\*\*0 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 \.data 00000018 0+10e8 0+10e8 00000168 2\*\*2 + CONTENTS, ALLOC, LOAD, DATA + 2 \.stack 00000004 0+80000 0+80000 00000180 2\*\*0 + CONTENTS, ALLOC, LOAD, DATA +SYMBOL TABLE: +0+1000 l d \.text 0+ (|\.text) +0+10e8 l d \.data 0+ (|\.data) +0+80000 l d \.stack 0+ (|\.stack) +0+10f4 l \.data 0+ foobar +0+10fc l \.data 0+ foobar2 +0+1060 l \.text 0+ 0x04 plugh +0+10f8 g \.data 0+ foobar +0+10e8 g \.data 0+ baz +0+10e8 g .* 0+ ___dtors +0+105c g \.text 0+ 0x04 xyzzy +0+1100 g \*ABS\* 0+ __bss_start +0+10e8 g .* 0+ ___ctors_end +0+10f0 g \.data 0+ baz2 +0+10e8 g .* 0+ ___ctors +0+1000 g \.text 0+ 0x04 foo +0+1100 g \*ABS\* 0+ _edata +0+1100 g \*ABS\* 0+ _end +0+1010 g \.text 0+ 0x04 start +0+100c g \.text 0+ 0x04 bar +0+80000 g \.stack 0+ _stack +0+10e8 g .* 0+ ___dtors_end diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/abi64.sd b/binutils-2.21/ld/testsuite/ld-sh/sh64/abi64.sd new file mode 100644 index 0000000..ff26740 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/abi64.sd @@ -0,0 +1,20 @@ + +.*: file format .*-sh64 + +Contents of section \.text: + 1000 cc000190 c8000190 c8000190 c8025590 .* + 1010 6bf56630 6ff0fff0 cc000210 c8000210 .* + 1020 c8000210 c8400610 cc000150 c8000150 .* + 1030 c8000150 c8405550 cffffd90 cbfffd90 .* + 1040 cbfffd90 cbff3590 6bf56630 cc0002b0 .* + 1050 c80002b0 c80002b0 c84502b0 cc000350 .* + 1060 c8000350 c8000350 c844e350 cc000040 .* + 1070 c8000040 c8000040 c8451040 cc000190 .* + 1080 c8000190 c8000190 c8006590 6bf56650 .* + 1090 cc000190 c8000190 c8000190 c8002590 .* + 10a0 6bf56410 6ff0fff0 6ff0fff0 .* +Contents of section \.data: + 1130 0000113c 00001015 000010a5 00001130 .* + 1140 00001130 00001015 .* +Contents of section \.stack: + 80000 deaddead .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/abi64.xd b/binutils-2.21/ld/testsuite/ld-sh/sh64/abi64.xd new file mode 100644 index 0000000..9af5b47 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/abi64.xd @@ -0,0 +1,44 @@ +.*: file format .*-sh64 +.* +architecture: sh5, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x0000000000001019 + +Program Header: + LOAD off 0x0000000000000100 vaddr 0x0000000000001000 paddr 0x0000000000001000 align 2\*\*7 + filesz 0x00000000000000ac memsz 0x00000000000000ac flags r-x + LOAD off 0x00000000000001b0 vaddr 0x0000000000001130 paddr 0x0000000000001130 align 2\*\*7 + filesz 0x0000000000000018 memsz 0x0000000000000018 flags rw- + LOAD off 0x0000000000000200 vaddr 0x0000000000080000 paddr 0x0000000000080000 align 2\*\*7 + filesz 0x0000000000000004 memsz 0x0000000000000004 flags rw- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.text 000000ac 0000000000001000 0000000000001000 00000100 2\*\*0 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 \.data 00000018 0000000000001130 0000000000001130 000001b0 2\*\*2 + CONTENTS, ALLOC, LOAD, DATA + 2 \.stack 00000004 0000000000080000 0000000000080000 00000200 2\*\*0 + CONTENTS, ALLOC, LOAD, DATA +SYMBOL TABLE: +0000000000001000 l d \.text 0000000000000000 (|\.text) +0000000000001130 l d \.data 0000000000000000 (|\.data) +0000000000080000 l d \.stack 0000000000000000 (|\.stack) +000000000000113c l \.data 0000000000000000 foobar +0000000000001144 l \.data 0000000000000000 foobar2 +00000000000010a8 l \.text 0000000000000000 0x04 plugh +0000000000001140 g \.data 0000000000000000 foobar +0000000000001130 g \.data 0000000000000000 baz +0000000000001130 g .* 0000000000000000 ___dtors +00000000000010a4 g \.text 0000000000000000 0x04 xyzzy +0000000000001148 g \*ABS\* 0000000000000000 __bss_start +0000000000001130 g .* 0000000000000000 ___ctors_end +0000000000001138 g \.data 0000000000000000 baz2 +0000000000001130 g .* 0000000000000000 ___ctors +0000000000001000 g \.text 0000000000000000 0x04 foo +0000000000001148 g \*ABS\* 0000000000000000 _edata +0000000000001148 g \*ABS\* 0000000000000000 _end +0000000000001018 g \.text 0000000000000000 0x04 start +0000000000001014 g \.text 0000000000000000 0x04 bar +0000000000080000 g \.stack 0000000000000000 _stack +0000000000001130 g .* 0000000000000000 ___dtors_end diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/abixx-noexp.sd b/binutils-2.21/ld/testsuite/ld-sh/sh64/abixx-noexp.sd new file mode 100644 index 0000000..ce11156 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/abixx-noexp.sd @@ -0,0 +1,12 @@ + +.*: file format .*-sh64 + +Contents of section \.text: + 1000 e8002a30 6ff0fff0 cc400610 cc401550 .* + 1010 ebfff630 cc4302b0 cc42e350 cc431040 .* + 1020 e8000a50 e8000810 6ff0fff0 6ff0fff0 .* +Contents of section \.data: + 10b0 000010bc 00001005 00001029 000010b0 .* + 10c0 000010b0 00001005 .* +Contents of section \.stack: + 80000 deaddead .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/cmpct1.sd b/binutils-2.21/ld/testsuite/ld-sh/sh64/cmpct1.sd new file mode 100644 index 0000000..1f7e8a1 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/cmpct1.sd @@ -0,0 +1,9 @@ + +.*: file format elf32-sh64 + +Contents of section \.text: + 1000 c7000009 0009ea2a .* +Contents of section \.rodata: + 1008 00001000 0000100c 00001004 .* +Contents of section \.stack: + 80000 deaddead .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/cmpct1.xd b/binutils-2.21/ld/testsuite/ld-sh/sh64/cmpct1.xd new file mode 100644 index 0000000..41f898e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/cmpct1.xd @@ -0,0 +1,36 @@ + +.*: file format .*-sh64 +.* +architecture: sh5, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x0+1000 + +Program Header: + LOAD off 0x0+80 vaddr 0x0+1000 paddr 0x0+1000 align 2\*\*7 + filesz 0x0+14 memsz 0x0+14 flags r-x + LOAD off 0x0+100 vaddr 0x0+80000 paddr 0x0+80000 align 2\*\*7 + filesz 0x00000004 memsz 0x00000004 flags rw- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.text 00000008 0+1000 0+1000 00000080 2\*\*0 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 \.rodata 0000000c 0+1008 0+1008 00000088 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 \.stack 00000004 0+80000 0+80000 00000100 2\*\*0 + CONTENTS, ALLOC, LOAD, DATA +SYMBOL TABLE: +0+1000 l d \.text 0+ (|\.text) +0+1008 l d \.rodata 0+ (|\.rodata) +0+80000 l d \.stack 0+ (|\.stack) +0+1004 l \.text 0+ next +0+100c l \.rodata 0+ here +0+1098 g .* 0+ ___dtors +0+1098 g \*ABS\* 0+ __bss_start +0+1098 g .* 0+ ___ctors_end +0+1098 g .* 0+ ___ctors +0+1098 g \*ABS\* 0+ _edata +0+1098 g \*ABS\* 0+ _end +0+1000 g \.text 0+ start +0+80000 g \.stack 0+ _stack +0+1098 g .* 0+ ___dtors_end diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-1.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-1.s new file mode 100644 index 0000000..5dfae88 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-1.s @@ -0,0 +1,8 @@ +! Support file for .cranges tests to resolve all references for +! non-partial-link tests. + .section .init,"ax" + .mode SHmedia + .global start + .align 2 +start: + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2a.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2a.s new file mode 100644 index 0000000..9af6bbe --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2a.s @@ -0,0 +1,22 @@ +! Simple example with assembler-generated .cranges that do not need more +! .cranges added by the linker: A single section with SHmedia, constants +! and SHcompact. + .section .text.mixed,"ax" + .align 2 +! Make sure this symbol does not have the expected type. + .mode SHcompact + .global diversion2 +diversion2: + + .mode SHmedia +start2: + nop + nop + nop + + .long 42 + .long 43 + + .mode SHcompact + nop + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2b.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2b.s new file mode 100644 index 0000000..670a448 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2b.s @@ -0,0 +1,39 @@ +! Initially three separate sections, one with SHmedia and constants, one with +! SHcompact, and yet another with SHmedia. Two .cranges sections +! generated by the assembler; two more needed at link time, as they will be +! consolidated into the same section, and mixed with a file with +! assembler-generated .cranges only and one without any .cranges. + + .section .text.shmedia,"ax" + .mode SHmedia + .align 2 +sec1: + nop + nop + nop + nop +sec2: + .long 41 + .long 43 + .long 42 + .long 43 + .long 42 + + .section .text.shcompact,"ax" + .align 1 + .mode SHcompact +sec3: + nop + nop + nop + + .section .text.shmedia2,"ax" + .align 2 +sec4: + .mode SHmedia + nop + nop + nop + nop + nop + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2c.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2c.s new file mode 100644 index 0000000..fcc350d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2c.s @@ -0,0 +1,16 @@ +! First part of crange-2b.s, but in section .text.mixed. + + .section .text.mixed,"ax" + .mode SHmedia + .align 2 +sec1: + nop + nop + nop + nop +sec2: + .long 41 + .long 43 + .long 42 + .long 43 + .long 42 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2d.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2d.s new file mode 100644 index 0000000..11f3d5b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2d.s @@ -0,0 +1,9 @@ +! Second part of crange-2b.s, but in section .text.mixed. + + .section .text.mixed,"ax" + .align 1 + .mode SHcompact +sec3: + nop + nop + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2e.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2e.s new file mode 100644 index 0000000..3d7c997 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2e.s @@ -0,0 +1,12 @@ +! Third part of crange-2b.s, but in section .text.mixed. + + .section .text.mixed,"ax" + .align 2 +sec4: + .mode SHmedia + nop + nop + nop + nop + nop + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2f.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2f.s new file mode 100644 index 0000000..a8479c9 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2f.s @@ -0,0 +1,21 @@ +! Section with SHmedia in unique section. Note the absence of a symbol to +! key an ISA type. + + .section .text.2f,"ax" + .align 2 + + .mode SHmedia + movi 0x2f,r20 + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + movi 0x2f,r21 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2g.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2g.s new file mode 100644 index 0000000..ac7aacb --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2g.s @@ -0,0 +1,26 @@ +! Section with SHmedia in unique section, similar to crange-2f.s + + .section .text.2g,"ax" + .align 2 + + .mode SHmedia + movi 0x21,r12 + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + movi 0x21,r13 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2h.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2h.s new file mode 100644 index 0000000..99c6146 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2h.s @@ -0,0 +1,17 @@ +! SHcompact in .text, similar to crange-2f.s and crange-2g.s + .section .text,"ax" + .align 2 + + .mode SHcompact + mov #0xf,r1 + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + mov #0xe,r1 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2i.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2i.s new file mode 100644 index 0000000..78c1ce9 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange-2i.s @@ -0,0 +1,8 @@ +! If this file comes before a file with a SHcompact .text section but with +! no symbols, we will have a symbol of the "wrong kind" before the +! SHcompact insns. + .section .text,"ax" + .mode SHmedia + .align 2 + .global diversion +diversion: diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange1.rd b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange1.rd new file mode 100644 index 0000000..2d2e69c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange1.rd @@ -0,0 +1,46 @@ +.* + +Section Headers: + +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al + +\[ 0\] +NULL +00000000 000000 000000 00 +0 +0 +0 + +\[ 1\] \.init +PROGBITS +00001000 000080 000004 00 AXp +0 +0 +4 + +\[ 2\] \.text +PROGBITS +00001004 000084 000018 00 AXp +0 +0 +4 + +\[ 3\] \.stack +PROGBITS +00080000 000100 000004 00 +WA +0 +0 +1 + +\[ 4\] \.cranges +LOUSER\+1 +00000000 000104 00001e 00 +W +0 +0 +1 + +\[ 5\] \.shstrtab +STRTAB +.* + +\[ 6\] \.symtab +SYMTAB +.* + +\[ 7\] \.strtab +STRTAB +.* +Key to Flags: +#... + +There are no relocations in this file\. + +Symbol table '\.symtab' contains [0-9]+ entries: + +Num: +Value +Size +Type +Bind +Vis +Ndx +Name +.*: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +UND +.*: 00001000 +0 +SECTION +LOCAL +DEFAULT +1 +.*: 00001004 +0 +SECTION +LOCAL +DEFAULT +2 +.*: 00080000 +0 +SECTION +LOCAL +DEFAULT +3 +.*: 00000000 +0 +SECTION +LOCAL +DEFAULT +4 +.*: 00001004 +0 +NOTYPE +LOCAL +DEFAULT +\[<other>: 4\] +2 start2 +.*: 000010a0 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___dtors +.*: 000010a0 +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_start +.*: 000010a0 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___ctors_end +.*: 00001004 +0 +NOTYPE +GLOBAL +DEFAULT +2 diversion2 +.*: 000010a0 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___ctors +.*: 000010a0 +0 +NOTYPE +GLOBAL +DEFAULT +ABS _edata +.*: 000010a0 +0 +NOTYPE +GLOBAL +DEFAULT +ABS _end +.*: 00001000 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 start +.*: 00080000 +0 +NOTYPE +GLOBAL +DEFAULT +3 _stack +.*: 000010a0 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___dtors_end + +Hex dump of section '\.init': + 0x00001000 6ff0fff0 .* + +Hex dump of section '\.text': + 0x00001004 6ff0fff0 6ff0fff0 6ff0fff0 0000002a .* + 0x00001014 0000002b 00090009 .* + +Hex dump of section '\.cranges': + 0x00000000 00001004 0000000c 00030000 10100000 .* + 0x00000010 00080001 00001018 00000004 0002 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange2.rd b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange2.rd new file mode 100644 index 0000000..3ee4dbb --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange2.rd @@ -0,0 +1,54 @@ +.* + +Section Headers: + +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al + +\[ 0\] +NULL +00000000 000000 000000 00 +0 +0 +0 + +\[ 1\] \.init +PROGBITS +00001000 000080 000004 00 AXp +0 +0 +4 + +\[ 2\] \.text +PROGBITS +00001004 000084 00005c 00 AXp +0 +0 +4 + +\[ 3\] \.stack +PROGBITS +00080000 000100 000004 00 +WA +0 +0 +1 + +\[ 4\] \.cranges +LOUSER\+1 +00000000 000104 000046 00 +W +0 +0 +1 + +\[ 5\] \.shstrtab +STRTAB +.* + +\[ 6\] \.symtab +SYMTAB +.* + +\[ 7\] \.strtab +STRTAB +.* +Key to Flags: +#... + +There are no relocations in this file\. + +Symbol table '\.symtab' contains [0-9]+ entries: + +Num: +Value +Size +Type +Bind +Vis +Ndx +Name +.*: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +UND +.*: 00001000 +0 +SECTION +LOCAL +DEFAULT +1 +.*: 00001004 +0 +SECTION +LOCAL +DEFAULT +2 +.*: 00080000 +0 +SECTION +LOCAL +DEFAULT +3 +.*: 00000000 +0 +SECTION +LOCAL +DEFAULT +4 +.*: 00001004 +0 +NOTYPE +LOCAL +DEFAULT +\[<other>: 4\] +2 start2 +.*: 0000101c +0 +NOTYPE +LOCAL +DEFAULT +\[<other>: 4\] +2 sec1 +.*: 0000102c +0 +NOTYPE +LOCAL +DEFAULT +\[<other>: 4\] +2 sec2 +.*: 00001040 +0 +NOTYPE +LOCAL +DEFAULT +2 sec3 +.*: 00001048 +0 +NOTYPE +LOCAL +DEFAULT +2 sec4 +.*: 000010e0 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___dtors +.*: 000010e0 +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_start +.*: 000010e0 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___ctors_end +.*: 00001004 +0 +NOTYPE +GLOBAL +DEFAULT +2 diversion2 +.*: 000010e0 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___ctors +.*: 000010e0 +0 +NOTYPE +GLOBAL +DEFAULT +ABS _edata +.*: 000010e0 +0 +NOTYPE +GLOBAL +DEFAULT +ABS _end +.*: 00001000 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 start +.*: 00080000 +0 +NOTYPE +GLOBAL +DEFAULT +3 _stack +.*: 000010e0 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___dtors_end + +Hex dump of section '\.text': + 0x00001004 6ff0fff0 6ff0fff0 6ff0fff0 0000002a .* + 0x00001014 0000002b 00090009 6ff0fff0 6ff0fff0 .* + 0x00001024 6ff0fff0 6ff0fff0 00000029 0000002b .* + 0x00001034 0000002a 0000002b 0000002a 00090009 .* + 0x00001044 00090000 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001054 6ff0fff0 6ff0fff0 6ff0fff0 .* + +Hex dump of section '\.cranges': + 0x00000000 00001004 0000000c 00030000 10100000 .* + 0x00000010 00080001 00001018 00000004 00020000 .* + 0x00000020 101c0000 00100003 0000102c 00000014 .* + 0x00000030 00010000 10400000 00060002 00001048 .* + 0x00000040 00000018 0003 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange3-cmpct.rd b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange3-cmpct.rd new file mode 100644 index 0000000..21f5ec2 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange3-cmpct.rd @@ -0,0 +1,77 @@ +ELF Header: + +Magic: +7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00 + +Class: +ELF32 + +Data: +2's complement, big endian + +Version: +1 \(current\) + +OS/ABI: +UNIX - System V + +ABI Version: +0 + +Type: +EXEC \(Executable file\) + +Machine: +Renesas / SuperH SH + +Version: +0x1 + +Entry point address: +0x10c4 + +Start of program headers: +52 \(bytes into file\) + +Start of section headers: +504 \(bytes into file\) + +Flags: +0xa, sh5 + +Size of this header: +52 \(bytes\) + +Size of program headers: +32 \(bytes\) + +Number of program headers: +2 + +Size of section headers: +40 \(bytes\) + +Number of section headers: +8 + +Section header string table index: 5 + +Section Headers: + +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al + +\[ 0\] +NULL +00000000 000000 000000 00 +0 +0 +0 + +\[ 1\] \.init +PROGBITS +00001000 000080 000004 00 AXp +0 +0 +4 + +\[ 2\] \.text +PROGBITS +00001004 000084 0000d8 00 AXp +0 +0 +4 + +\[ 3\] \.stack +PROGBITS +00080000 000180 000004 00 +WA +0 +0 +1 + +\[ 4\] \.cranges +LOUSER\+1 +00000000 000184 00003c 00 +W +0 +0 +1 + +\[ 5\] \.shstrtab +STRTAB +.* + +\[ 6\] \.symtab +SYMTAB +.* + +\[ 7\] \.strtab +STRTAB +.* +Key to Flags: +#... + +Symbol table '\.symtab' contains [0-9]+ entries: + +Num: +Value +Size +Type +Bind +Vis +Ndx +Name +.*: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +UND +.*: 00001000 +0 +SECTION +LOCAL +DEFAULT +1 +.*: 00001004 +0 +SECTION +LOCAL +DEFAULT +2 +.*: 00080000 +0 +SECTION +LOCAL +DEFAULT +3 +.*: 00000000 +0 +SECTION +LOCAL +DEFAULT +4 +.*: 00001004 +0 +NOTYPE +LOCAL +DEFAULT +2 sec4 +.*: 000010a4 +0 +NOTYPE +LOCAL +DEFAULT +\[<other>: 4\] +2 start2 +.*: 000010bc +0 +NOTYPE +LOCAL +DEFAULT +2 sec3 +.*: 000010c4 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +2 diversion +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___dtors +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_start +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___ctors_end +.*: 000010a4 +0 +NOTYPE +GLOBAL +DEFAULT +2 diversion2 +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___ctors +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +ABS _edata +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +ABS _end +.*: 00001000 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 start +.*: 00080000 +0 +NOTYPE +GLOBAL +DEFAULT +3 _stack +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___dtors_end + +Hex dump of section '\.text': + 0x00001004 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001014 6ff0fff0 6ff0fff0 cc00bd40 6ff0fff0 .* + 0x00001024 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001034 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001044 6ff0fff0 6ff0fff0 6ff0fff0 cc00bd50 .* + 0x00001054 cc0084c0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001064 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001074 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001084 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001094 6ff0fff0 6ff0fff0 6ff0fff0 cc0084d0 .* + 0x000010a4 6ff0fff0 6ff0fff0 6ff0fff0 0000002a .* + 0x000010b4 0000002b 00090009 00090009 00090000 .* + 0x000010c4 e10f0009 00090009 00090009 00090009 .* + 0x000010d4 00090009 0009e10e .* + +Hex dump of section '\.cranges': + 0x00000000 00001004 000000a0 00030000 10a40000 .* + 0x00000010 000c0003 000010b0 00000008 00010000 .* + 0x00000020 10b80000 00040002 000010bc 00000006 .* + 0x00000030 00020000 10c40000 00180002 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange3-media.rd b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange3-media.rd new file mode 100644 index 0000000..18ce30e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange3-media.rd @@ -0,0 +1,77 @@ +ELF Header: + +Magic: +7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00 + +Class: +ELF32 + +Data: +2's complement, big endian + +Version: +1 \(current\) + +OS/ABI: +UNIX - System V + +ABI Version: +0 + +Type: +EXEC \(Executable file\) + +Machine: +Renesas / SuperH SH + +Version: +0x1 + +Entry point address: +0x10a5 + +Start of program headers: +52 \(bytes into file\) + +Start of section headers: +504 \(bytes into file\) + +Flags: +0xa, sh5 + +Size of this header: +52 \(bytes\) + +Size of program headers: +32 \(bytes\) + +Number of program headers: +2 + +Size of section headers: +40 \(bytes\) + +Number of section headers: +8 + +Section header string table index: 5 + +Section Headers: + +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al + +\[ 0\] +NULL +00000000 000000 000000 00 +0 +0 +0 + +\[ 1\] \.init +PROGBITS +00001000 000080 000004 00 AXp +0 +0 +4 + +\[ 2\] \.text +PROGBITS +00001004 000084 0000d8 00 AXp +0 +0 +4 + +\[ 3\] \.stack +PROGBITS +00080000 000180 000004 00 +WA +0 +0 +1 + +\[ 4\] \.cranges +LOUSER\+1 +00000000 000184 00003c 00 +W +0 +0 +1 + +\[ 5\] \.shstrtab +STRTAB +.* + +\[ 6\] \.symtab +SYMTAB +.* + +\[ 7\] \.strtab +STRTAB +.* +Key to Flags: +#... + +Symbol table '\.symtab' contains [0-9]+ entries: + +Num: +Value +Size +Type +Bind +Vis +Ndx +Name +.*: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +UND +.*: 00001000 +0 +SECTION +LOCAL +DEFAULT +1 +.*: 00001004 +0 +SECTION +LOCAL +DEFAULT +2 +.*: 00080000 +0 +SECTION +LOCAL +DEFAULT +3 +.*: 00000000 +0 +SECTION +LOCAL +DEFAULT +4 +.*: 00001004 +0 +NOTYPE +LOCAL +DEFAULT +2 sec4 +.*: 000010a4 +0 +NOTYPE +LOCAL +DEFAULT +\[<other>: 4\] +2 start2 +.*: 000010bc +0 +NOTYPE +LOCAL +DEFAULT +2 sec3 +.*: 000010c4 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +2 diversion +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___dtors +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_start +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___ctors_end +.*: 000010a4 +0 +NOTYPE +GLOBAL +DEFAULT +2 diversion2 +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___ctors +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +ABS _edata +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +ABS _end +.*: 00001000 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 start +.*: 00080000 +0 +NOTYPE +GLOBAL +DEFAULT +3 _stack +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___dtors_end + +Hex dump of section '\.text': + 0x00001004 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001014 6ff0fff0 6ff0fff0 cc00bd40 6ff0fff0 .* + 0x00001024 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001034 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001044 6ff0fff0 6ff0fff0 6ff0fff0 cc00bd50 .* + 0x00001054 cc0084c0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001064 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001074 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001084 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001094 6ff0fff0 6ff0fff0 6ff0fff0 cc0084d0 .* + 0x000010a4 6ff0fff0 6ff0fff0 6ff0fff0 0000002a .* + 0x000010b4 0000002b 00090009 00090009 00090000 .* + 0x000010c4 e10f0009 00090009 00090009 00090009 .* + 0x000010d4 00090009 0009e10e .* + +Hex dump of section '\.cranges': + 0x00000000 00001004 000000a0 00030000 10a40000 .* + 0x00000010 000c0003 000010b0 00000008 00010000 .* + 0x00000020 10b80000 00040002 000010bc 00000006 .* + 0x00000030 00020000 10c40000 00180002 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange3.dd b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange3.dd new file mode 100644 index 0000000..135f1c9 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange3.dd @@ -0,0 +1,80 @@ + +.*: file format elf32-sh64 + +Disassembly of section .init: + +00001000 <start>: + 1000: 6ff0fff0 nop +Disassembly of section .text: + +00001004 <sec4>: + 1004: 6ff0fff0 nop + 1008: 6ff0fff0 nop + 100c: 6ff0fff0 nop + 1010: 6ff0fff0 nop + 1014: 6ff0fff0 nop + 1018: 6ff0fff0 nop + 101c: cc00bd40 movi 47,r20 + 1020: 6ff0fff0 nop + 1024: 6ff0fff0 nop + 1028: 6ff0fff0 nop + 102c: 6ff0fff0 nop + 1030: 6ff0fff0 nop + 1034: 6ff0fff0 nop + 1038: 6ff0fff0 nop + 103c: 6ff0fff0 nop + 1040: 6ff0fff0 nop + 1044: 6ff0fff0 nop + 1048: 6ff0fff0 nop + 104c: 6ff0fff0 nop + 1050: cc00bd50 movi 47,r21 + 1054: cc0084c0 movi 33,r12 + 1058: 6ff0fff0 nop + 105c: 6ff0fff0 nop + 1060: 6ff0fff0 nop + 1064: 6ff0fff0 nop + 1068: 6ff0fff0 nop + 106c: 6ff0fff0 nop + 1070: 6ff0fff0 nop + 1074: 6ff0fff0 nop + 1078: 6ff0fff0 nop + 107c: 6ff0fff0 nop + 1080: 6ff0fff0 nop + 1084: 6ff0fff0 nop + 1088: 6ff0fff0 nop + 108c: 6ff0fff0 nop + 1090: 6ff0fff0 nop + 1094: 6ff0fff0 nop + 1098: 6ff0fff0 nop + 109c: 6ff0fff0 nop + 10a0: cc0084d0 movi 33,r13 + +000010a4 <diversion2>: + 10a4: 6ff0fff0 nop + 10a8: 6ff0fff0 nop + 10ac: 6ff0fff0 nop + 10b0: 00 00 00 2a \.long 0x0000002a + 10b4: 00 00 00 2b \.long 0x0000002b + 10b8: 00 09 nop + 10ba: 00 09 nop + +000010bc <sec3>: + 10bc: 00 09 nop + 10be: 00 09 nop + 10c0: 00 09 nop + \.\.\. + +000010c4 <diversion>: + 10c4: e1 0f mov #15,r1 + 10c6: 00 09 nop + 10c8: 00 09 nop + 10ca: 00 09 nop + 10cc: 00 09 nop + 10ce: 00 09 nop + 10d0: 00 09 nop + 10d2: 00 09 nop + 10d4: 00 09 nop + 10d6: 00 09 nop + 10d8: 00 09 nop + 10da: e1 0e mov #14,r1 + diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crange3.rd b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange3.rd new file mode 100644 index 0000000..1a0b7a5 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crange3.rd @@ -0,0 +1,58 @@ +.* + +Section Headers: + +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al + +\[ 0\] +NULL +00000000 000000 000000 00 +0 +0 +0 + +\[ 1\] \.init +PROGBITS +00001000 000080 000004 00 AXp +0 +0 +4 + +\[ 2\] \.text +PROGBITS +00001004 000084 0000d8 00 AXp +0 +0 +4 + +\[ 3\] \.stack +PROGBITS +00080000 000180 000004 00 +WA +0 +0 +1 + +\[ 4\] \.cranges +LOUSER\+1 +00000000 000184 00003c 00 +W +0 +0 +1 + +\[ 5\] \.shstrtab +STRTAB +.* + +\[ 6\] \.symtab +SYMTAB +.* + +\[ 7\] \.strtab +STRTAB +.* +Key to Flags: +#... + +Symbol table '\.symtab' contains [0-9]+ entries: + +Num: +Value +Size +Type +Bind +Vis +Ndx +Name +.*: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +UND +.*: 00001000 +0 +SECTION +LOCAL +DEFAULT +1 +.*: 00001004 +0 +SECTION +LOCAL +DEFAULT +2 +.*: 00080000 +0 +SECTION +LOCAL +DEFAULT +3 +.*: 00000000 +0 +SECTION +LOCAL +DEFAULT +4 +.*: 00001004 +0 +NOTYPE +LOCAL +DEFAULT +2 sec4 +.*: 000010a4 +0 +NOTYPE +LOCAL +DEFAULT +\[<other>: 4\] +2 start2 +.*: 000010bc +0 +NOTYPE +LOCAL +DEFAULT +2 sec3 +.*: 000010c4 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +2 diversion +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___dtors +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_start +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___ctors_end +.*: 000010a4 +0 +NOTYPE +GLOBAL +DEFAULT +2 diversion2 +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___ctors +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +ABS _edata +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +ABS _end +.*: 00001000 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 start +.*: 00080000 +0 +NOTYPE +GLOBAL +DEFAULT +3 _stack +.*: 00001160 +0 +NOTYPE +GLOBAL +DEFAULT +.* ___dtors_end + +Hex dump of section '\.text': + 0x00001004 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001014 6ff0fff0 6ff0fff0 cc00bd40 6ff0fff0 .* + 0x00001024 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001034 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001044 6ff0fff0 6ff0fff0 6ff0fff0 cc00bd50 .* + 0x00001054 cc0084c0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001064 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001074 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001084 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00001094 6ff0fff0 6ff0fff0 6ff0fff0 cc0084d0 .* + 0x000010a4 6ff0fff0 6ff0fff0 6ff0fff0 0000002a .* + 0x000010b4 0000002b 00090009 00090009 00090000 .* + 0x000010c4 e10f0009 00090009 00090009 00090009 .* + 0x000010d4 00090009 0009e10e .* + +Hex dump of section '\.cranges': + 0x00000000 00001004 000000a0 00030000 10a40000 .* + 0x00000010 000c0003 000010b0 00000008 00010000 .* + 0x00000020 10b80000 00040002 000010bc 00000006 .* + 0x00000030 00020000 10c40000 00180002 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crangerel1.rd b/binutils-2.21/ld/testsuite/ld-sh/sh64/crangerel1.rd new file mode 100644 index 0000000..0100b10 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crangerel1.rd @@ -0,0 +1,44 @@ +There are 11 section headers, starting at offset 0xbc: + +Section Headers: + +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al + +\[ 0\] +NULL +00000000 000000 000000 00 +0 +0 +0 + +\[ 1\] \.text +PROGBITS +00000000 000034 000000 00 +AX +0 +0 +1 + +\[ 2\] \.text\.mixed +PROGBITS +00000000 000034 000018 00 AXp +0 +0 +4 + +\[ 3\] \.data +PROGBITS +00000000 00004c 000000 00 +WA +0 +0 +1 + +\[ 4\] \.bss +NOBITS +00000000 00004c 000000 00 +WA +0 +0 +1 + +\[ 5\] \.stack +PROGBITS +00000000 00004c 000004 00 +WA +0 +0 +1 + +\[ 6\] \.cranges +PROGBITS +00000000 000050 00001e 00 +W +0 +0 +1 + +\[ 7\] \.rela\.cranges +RELA +00000000 000274 000024 0c +9 +6 +4 + +\[ 8\] \.shstrtab +STRTAB +00000000 00006e 00004d 00 +0 +0 +1 + +\[ 9\] \.symtab +SYMTAB +00000000 000298 000090 10 +10 +8 +4 + +\[10\] \.strtab +STRTAB +00000000 000328 000013 00 +0 +0 +1 +Key to Flags: +#... + +Relocation section '\.rela\.cranges' at offset 0x[0-9a-f]+ contains 3 entries: +.* +0*00000000 +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0 +0*0000000a +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0 +0*00000014 +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0 + +Symbol table '\.symtab' contains 9 entries: + +Num: +Value +Size +Type +Bind +Vis +Ndx +Name + +0: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +UND + +1: 00000000 +0 +SECTION +LOCAL +DEFAULT +1 + +2: 00000000 +0 +SECTION +LOCAL +DEFAULT +2 + +3: 00000000 +0 +SECTION +LOCAL +DEFAULT +3 + +4: 00000000 +0 +SECTION +LOCAL +DEFAULT +4 + +5: 00000000 +0 +SECTION +LOCAL +DEFAULT +5 + +6: 00000000 +0 +SECTION +LOCAL +DEFAULT +6 + +7: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +\[<other>: 4\] +2 start2 + +8: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +2 diversion2 + +Hex dump of section '\.text\.mixed': + 0x00000000 6ff0fff0 6ff0fff0 6ff0fff0 0000002a .* + 0x00000010 0000002b 00090009 .* + +Hex dump of section '\.cranges': +.* + 0x00000000 00000000 0000000c 00030000 000c0000 .* + 0x00000010 00080001 00000014 00000004 0002 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/crangerel2.rd b/binutils-2.21/ld/testsuite/ld-sh/sh64/crangerel2.rd new file mode 100644 index 0000000..4f8a9cd --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/crangerel2.rd @@ -0,0 +1,59 @@ +There are 11 section headers, starting at offset 0x128: + +Section Headers: + +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al + +\[ 0\] +NULL +00000000 000000 000000 00 +0 +0 +0 + +\[ 1\] \.text +PROGBITS +00000000 000034 000000 00 +AX +0 +0 +1 + +\[ 2\] \.text\.mixed +PROGBITS +00000000 000034 00005c 00 AXp +0 +0 +4 + +\[ 3\] \.data +PROGBITS +00000000 000090 000000 00 +WA +0 +0 +1 + +\[ 4\] \.bss +NOBITS +00000000 000090 000000 00 +WA +0 +0 +1 + +\[ 5\] \.stack +PROGBITS +00000000 000090 000004 00 +WA +0 +0 +1 + +\[ 6\] \.cranges +PROGBITS +00000000 000094 000046 00 +W +0 +0 +1 + +\[ 7\] \.rela\.cranges +RELA +00000000 0002e0 000054 0c +9 +6 +4 + +\[ 8\] \.shstrtab +STRTAB +00000000 0000da 00004d 00 +0 +0 +1 + +\[ 9\] \.symtab +SYMTAB +00000000 000334 0000d0 10 +10 +12 +4 + +\[10\] \.strtab +STRTAB +00000000 000404 000027 00 +0 +0 +1 +Key to Flags: +#... + +Relocation section '\.rela\.cranges' at offset 0x[0-9a-f]+ contains 7 entries: +.* +0*00000000 +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0 +0*0000000a +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0 +0*00000014 +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0 +0*0000001e +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0 +0*00000028 +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0 +0*00000032 +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0 +0*0000003c +0+0201 R_SH_DIR32 +00000000 +\.text\.mixed +\+ 0 + +Symbol table '\.symtab' contains 13 entries: + +Num: +Value +Size +Type +Bind +Vis +Ndx +Name + +0: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +UND + +1: 00000000 +0 +SECTION +LOCAL +DEFAULT +1 + +2: 00000000 +0 +SECTION +LOCAL +DEFAULT +2 + +3: 00000000 +0 +SECTION +LOCAL +DEFAULT +3 + +4: 00000000 +0 +SECTION +LOCAL +DEFAULT +4 + +5: 00000000 +0 +SECTION +LOCAL +DEFAULT +5 + +6: 00000000 +0 +SECTION +LOCAL +DEFAULT +6 + +7: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +\[<other>: 4\] +2 start2 + +8: 00000018 +0 +NOTYPE +LOCAL +DEFAULT +\[<other>: 4\] +2 sec1 + +9: 00000028 +0 +NOTYPE +LOCAL +DEFAULT +\[<other>: 4\] +2 sec2 + +10: 0000003c +0 +NOTYPE +LOCAL +DEFAULT +2 sec3 + +11: 00000044 +0 +NOTYPE +LOCAL +DEFAULT +2 sec4 + +12: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +2 diversion2 + +Hex dump of section '\.text\.mixed': + 0x00000000 6ff0fff0 6ff0fff0 6ff0fff0 0000002a .* + 0x00000010 0000002b 00090009 6ff0fff0 6ff0fff0 .* + 0x00000020 6ff0fff0 6ff0fff0 00000029 0000002b .* + 0x00000030 0000002a 0000002b 0000002a 00090009 .* + 0x00000040 00090000 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00000050 6ff0fff0 6ff0fff0 6ff0fff0 .* + +Hex dump of section '\.cranges': +.* + 0x00000000 00000000 0000000c 00030000 000c0000 .* + 0x00000010 00080001 00000014 00000004 00020000 .* + 0x00000020 00180000 00100003 00000028 00000014 .* + 0x00000030 00010000 003c0000 00060002 00000044 .* + 0x00000040 00000018 0003 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/dlsection-1.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/dlsection-1.s new file mode 100644 index 0000000..d83e6e1 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/dlsection-1.s @@ -0,0 +1,17 @@ +! Test gc-sections and datalabel references. +! +! Datalabel reference to symbol in section .text2 should +! prevent .text2 from being discarded. +! Section .spurious can be discarded. + .mode SHmedia + + .text + .global start + .global foo +start: .long datalabel foo + + .section .text2,"ax" +foo: .long 23 + + .section .spurious,"ax" + .long 17 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/dlsection.sd b/binutils-2.21/ld/testsuite/ld-sh/sh64/dlsection.sd new file mode 100644 index 0000000..58bf965 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/dlsection.sd @@ -0,0 +1,9 @@ + +.*: file format elf.*-sh64 + +Contents of section \.text: + 1000 00001004 .* +Contents of section \.text2: + 1004 00000017 .* +Contents of section \.stack: + 80000 deaddead .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.dbd b/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.dbd new file mode 100644 index 0000000..0369cbc --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.dbd @@ -0,0 +1,11 @@ + +.*:[ ]*file[ ]*format[ ]*elf64-sh64 + +Disassembly[ ]*of[ ]*section[ ]*.text: + +0000000000000000[ ]*<start>: +[ ]*0:[ ]*cc48d000[ ]*movi[ ]*4660,r0 +[ ]*4:[ ]*12345678[ ]*.long[ ]*0x12345678 +[ ]*8:[ ]*12340000[ ]*.long[ ]*0x12340000 +[ ]*c:[ ]*12345678[ ]*.long[ ]*0x12345678 + diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.dld b/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.dld new file mode 100644 index 0000000..f3c5bd5 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.dld @@ -0,0 +1,11 @@ + +.*:[ ]*file[ ]*format[ ]*elf64-sh64l + +Disassembly[ ]*of[ ]*section[ ]*.text: + +0000000000000000[ ]*<start>: +[ ]*0:[ ]*cc48d000[ ]*movi[ ]*4660,r0 +[ ]*4:[ ]*12345678[ ]*.long[ ]*0x12345678 +[ ]*8:[ ]*00001234[ ]*.long[ ]*0x00001234 +[ ]*c:[ ]*12345678[ ]*.long[ ]*0x12345678 + diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.ld b/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.ld new file mode 100644 index 0000000..e9635e1 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.ld @@ -0,0 +1,6 @@ +SECTIONS { + .text : { + *(.text) + LONG(0x12345678); + } +} diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.s new file mode 100644 index 0000000..79bc9e4 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.s @@ -0,0 +1,7 @@ + .text + .mode shmedia +start: + + movi 0x1234,r0 + .long 0x12345678 + .word 0x1234, 0 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.sbd b/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.sbd new file mode 100644 index 0000000..462f66d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.sbd @@ -0,0 +1,5 @@ + +.*: file format elf64-sh64 + +Contents of section .text: + 0000 cc48d000 12345678 12340000 12345678.* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.sld b/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.sld new file mode 100644 index 0000000..00975cb --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/endian.sld @@ -0,0 +1,6 @@ + +.*: file format elf64-sh64l + +Contents of section .text: + 0000 00d048cc 78563412 34120000 78563412.* + diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/gotplt.d b/binutils-2.21/ld/testsuite/ld-sh/sh64/gotplt.d new file mode 100644 index 0000000..5822326 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/gotplt.d @@ -0,0 +1,12 @@ +#source: gotplt.s +#as: --abi=32 --isa=SHmedia +#ld: -shared -mshelf32 --version-script=$srcdir/$subdir/gotplt.map +#readelf: -r +#target: sh64-*-elf + +# Make sure that gotplt relocations of forced local symbols +# use the GOT. + +Relocation section '\.rela\.dyn' at offset .* contains 1 entries: + Offset Info Type Sym\.Value Sym\. Name \+ Addend +[0-9a-f ]+R_SH_RELATIVE[0-9a-f ]+ diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/gotplt.map b/binutils-2.21/ld/testsuite/ld-sh/sh64/gotplt.map new file mode 100644 index 0000000..a27c22c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/gotplt.map @@ -0,0 +1,4 @@ +GLIBC_2.2 { + local: + xxx; +}; diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/gotplt.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/gotplt.s new file mode 100644 index 0000000..45ed0b2 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/gotplt.s @@ -0,0 +1,8 @@ + .text + .global xxx +xxx: + ptabs r18, tr0 + blink tr0, r63 + .global yyy +yyy: + movi ((xxx@GOTPLT) & 65535), r1 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/init-cmpct.d b/binutils-2.21/ld/testsuite/ld-sh/sh64/init-cmpct.d new file mode 100644 index 0000000..6f64bc4 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/init-cmpct.d @@ -0,0 +1,14 @@ +#source: init.s +#as: --abi=32 --isa=SHcompact +#ld: -shared -mshelf32 +#readelf: -d +#target: sh64-*-elf + +# Make sure that the lsb of DT_INIT and DT_FINI entries is not set +# when _init and _fini are SHcompact code. + +Dynamic section at offset .* contains 8 entries: + Tag Type Name/Value + 0x0000000c \(INIT\) .*[02468ace] + 0x0000000d \(FINI\) .*[02468ace] +#pass diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/init-media.d b/binutils-2.21/ld/testsuite/ld-sh/sh64/init-media.d new file mode 100644 index 0000000..56c6c19 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/init-media.d @@ -0,0 +1,14 @@ +#source: init.s +#as: --abi=32 --isa=SHmedia +#ld: -shared -mshelf32 +#readelf: -d +#target: sh64-*-elf + +# Make sure that the lsb of DT_INIT and DT_FINI entries is set +# when _init and _fini are SHmedia code. + +.* + Tag Type Name/Value + 0x0000000c \(INIT\) .*[13579bdf] + 0x0000000d \(FINI\) .*[13579bdf] +#pass diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/init.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/init.s new file mode 100644 index 0000000..900e764 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/init.s @@ -0,0 +1,18 @@ + .section .text,"ax" + .global _init + .type _init,@function + .align 1 +_init: + nop + nop + nop + nop + + .global _fini + .type _fini,@function + .align 1 +_fini: + nop + nop + nop + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/init64.d b/binutils-2.21/ld/testsuite/ld-sh/sh64/init64.d new file mode 100644 index 0000000..01c8e97 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/init64.d @@ -0,0 +1,14 @@ +#source: init.s +#as: --abi=64 +#ld: -shared -mshelf64 +#readelf: -d +#target: sh64-*-elf + +# Make sure that the lsb of DT_INIT and DT_FINI entries is set +# when _init and _fini are SHmedia code. + +.* + Tag Type Name/Value + 0x000000000000000c \(INIT\) .*[13579bdf] + 0x000000000000000d \(FINI\) .*[13579bdf] +#pass diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/mix1-noexp.sd b/binutils-2.21/ld/testsuite/ld-sh/sh64/mix1-noexp.sd new file mode 100644 index 0000000..fe73136 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/mix1-noexp.sd @@ -0,0 +1,14 @@ + +.*: file format .*-sh64 + +Contents of section \.text: + 1000 8902c700 00090009 00090009 0000100c .* + 1010 00001004 00001021 effff240 efffea50 .* + 1020 cc401360 cc4086d0 ebfffa70 6ff0fff0 .* +Contents of section \.data: + 10b0 000010b0 00001004 00001021 .* +Contents of section \.stack: + 80000 deaddead .* +Contents of section \.cranges: + 0000 00001000 00000018 00020000 10180000 .* + 0010 00180003 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/mix1.sd b/binutils-2.21/ld/testsuite/ld-sh/sh64/mix1.sd new file mode 100644 index 0000000..c5cc4b1 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/mix1.sd @@ -0,0 +1,16 @@ + +.*: file format .*-sh64 + +Contents of section \.text: + 1000 8902c700 00090009 00090009 0000100c .* + 1010 00001004 00001031 cffffd90 cbffa190 .* + 1020 6bf56640 cffffd90 cbff6190 6bf56650 .* + 1030 cc000360 c8401360 cc0002d0 c840c6d0 .* + 1040 ebfff270 6ff0fff0 .* +Contents of section \.data: + 10c8 000010c8 00001004 00001031 .* +Contents of section \.stack: + 80000 deaddead .* +Contents of section \.cranges: + 0000 00001000 00000018 00020000 10180000 .* + 0010 00300003 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/mix1.xd b/binutils-2.21/ld/testsuite/ld-sh/sh64/mix1.xd new file mode 100644 index 0000000..de72ce0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/mix1.xd @@ -0,0 +1,42 @@ + +.*: file format .*-sh64 +.* +architecture: sh5, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x0+1000 + +Program Header: + LOAD off 0x0+100 vaddr 0x0+1000 paddr 0x0+1000 align 2\*\*7 + filesz 0x0+48 memsz 0x0+48 flags r-x + LOAD off 0x0+148 vaddr 0x0+10c8 paddr 0x0+10c8 align 2\*\*7 + filesz 0x0+c memsz 0x0+c flags rw- + LOAD off 0x0+180 vaddr 0x0+80000 paddr 0x0+80000 align 2\*\*7 + filesz 0x0+4 memsz 0x0+4 flags rw- +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.text 00000048 0+1000 0+1000 00000100 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 \.data 0000000c 0+10c8 0+10c8 00000148 2\*\*2 + CONTENTS, ALLOC, LOAD, DATA + 2 \.stack 00000004 0+80000 0+80000 00000180 2\*\*0 + CONTENTS, ALLOC, LOAD, DATA + 3 \.cranges 00000014 0+ 0+ 00000184 2\*\*0 + CONTENTS, DEBUGGING, SORT_ENTRIES +SYMBOL TABLE: +0+1000 l d \.text 0+ (|\.text) +0+10c8 l d \.data 0+ (|\.data) +0+80000 l d \.stack 0+ (|\.stack) +0+ l d \.cranges 0+ (|\.cranges) +0+1008 l \.text 0+ forw +0+1004 l \.text 0+ start2 +0+1030 l \.text 0+ 0x04 mediacode2 +0+1018 l \.text 0+ 0x04 mediacode +0+10c8 g .* 0+ ___dtors +0+10d8 g \*ABS\* 0+ __bss_start +0+10c8 g .* 0+ ___ctors_end +0+10c8 g .* 0+ ___ctors +0+10d8 g \*ABS\* 0+ _edata +0+10d8 g \*ABS\* 0+ _end +0+1000 g \.text 0+ start +0+80000 g \.stack 0+ _stack +0+10c8 g .* 0+ ___dtors_end diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/mix2-noexp.sd b/binutils-2.21/ld/testsuite/ld-sh/sh64/mix2-noexp.sd new file mode 100644 index 0000000..9112cfc --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/mix2-noexp.sd @@ -0,0 +1,16 @@ + +.*: file format .*-sh64 + +Contents of section \.text: + 1000 cc4048e0 cc40c0e0 ec000e60 6ff0fff0 .* + 1010 0009c700 c7000009 00090009 00001009 .* + 1020 000010bc .* +Contents of section \.rodata: + 1024 00001018 000010c4 0000100d 00001028 .* +Contents of section \.data: + 10b8 00000000 00001014 00000000 000010bc .* +Contents of section \.stack: + 80000 deaddead .* +Contents of section \.cranges: + 0000 00001000 00000010 00030000 10100000 .* + 0010 00140002 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/mix2.sd b/binutils-2.21/ld/testsuite/ld-sh/sh64/mix2.sd new file mode 100644 index 0000000..122a472 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/mix2.sd @@ -0,0 +1,17 @@ + +.*: file format .*-sh64 + +Contents of section \.text: + 1000 cc0000e0 c84088e0 cc0000e0 c84100e0 .* + 1010 cc000190 c8003190 6bf56660 6ff0fff0 .* + 1020 0009c700 c7000009 00090009 00001011 .* + 1030 000010cc .* +Contents of section \.rodata: + 1034 00001028 000010d4 0000101d 00001038 .* +Contents of section \.data: + 10c8 00000000 00001024 00000000 000010cc .* +Contents of section \.stack: + 80000 deaddead .* +Contents of section \.cranges: + 0000 00001000 00000020 00030000 10200000 .* + 0010 00140002 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/mix2.xd b/binutils-2.21/ld/testsuite/ld-sh/sh64/mix2.xd new file mode 100644 index 0000000..5c72763 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/mix2.xd @@ -0,0 +1,52 @@ + +.*: file format .*-sh64 +.* +architecture: sh5, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x0+1001 + +Program Header: + LOAD off 0x0+100 vaddr 0x0+1000 paddr 0x0+1000 align 2\*\*7 + filesz 0x0+44 memsz 0x0+44 flags r-x + LOAD off 0x0+148 vaddr 0x0+10c8 paddr 0x0+10c8 align 2\*\*7 + filesz 0x0+10 memsz 0x0+10 flags rw- + LOAD off 0x0+180 vaddr 0x0+80000 paddr 0x0+80000 align 2\*\*7 + filesz 0x0+4 memsz 0x0+4 flags rw- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.text 00000034 0+1000 0+1000 00000100 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 \.rodata 00000010 0+1034 0+1034 00000134 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 \.data 00000010 0+10c8 0+10c8 00000148 2\*\*2 + CONTENTS, ALLOC, LOAD, DATA + 3 \.stack 00000004 0+80000 0+80000 00000180 2\*\*0 + CONTENTS, ALLOC, LOAD, DATA + 4 \.cranges 00000014 0+ 0+ 00000184 2\*\*0 + CONTENTS, DEBUGGING, SORT_ENTRIES +SYMBOL TABLE: +0+1000 l d \.text 0+ (|\.text) +0+1034 l d \.rodata 0+ (|\.rodata) +0+10c8 l d \.data 0+ (|\.data) +0+80000 l d \.stack 0+ (|\.stack) +0+ l d \.cranges 0+ (|\.cranges) +0+1020 l \.text 0+ locallabel +0+1040 g \.rodata 0+ compactlabel4 +0+101c g \.text 0+ 0x04 medialabel2 +0+1038 g \.rodata 0+ medialabel3 +0+1022 g \.text 0+ compactlabel1 +0+1024 g \.text 0+ compactlabel2 +0+1028 g \.text 0+ compactlabel3 +0+1010 g \.text 0+ 0x04 medialabel1 +0+10c8 g .* 0+ ___dtors +0+10cc g \.data 0+ medialabel4 +0+10d8 g \*ABS\* 0+ __bss_start +0+10c8 g .* 0+ ___ctors_end +0+10d4 g \.data 0+ compactlabel5 +0+10c8 g .* 0+ ___ctors +0+10d8 g \*ABS\* 0+ _edata +0+10d8 g \*ABS\* 0+ _end +0+1000 g \.text 0+ 0x04 start +0+80000 g \.stack 0+ _stack +0+10c8 g .* 0+ ___dtors_end diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/rd-sh64.exp b/binutils-2.21/ld/testsuite/ld-sh/sh64/rd-sh64.exp new file mode 100644 index 0000000..ebeed0a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/rd-sh64.exp @@ -0,0 +1,44 @@ +# Expect script for run_dump_test based ld-sh/sh64 tests. +# Copyright 2002, 2003, 2005, 2007 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. +# +# Written by Stephen Clarke (stephen.clarke@superh.com) +# + +if ![istarget sh64-*-*] { + return +} + +set rd_test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]] +foreach sh64test $rd_test_list { + # We need to strip the ".d", but can leave the dirname. + verbose [file rootname $sh64test] + run_dump_test [file rootname $sh64test] + if [string match $srcdir/$subdir/*-dso.d $sh64test] { + # Copy the output of the DSO-createing test to .so file. + # Notice that a DSO-creating test must preceed the tests + # which need that DSO in sort-order by name. + set cmd "cp tmpdir/dump \ + tmpdir/[file rootname [file tail $sh64test]].so" + send_log "$cmd\n" + set cmdret [catch "exec $cmd" comp_output] + send_log "$comp_output\n" + # FIXME: What if it fails? Need we do something? + } +} diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/rel-1.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/rel-1.s new file mode 100644 index 0000000..6cf18ca --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/rel-1.s @@ -0,0 +1,48 @@ +! Relative linking, simple files with global symbols but nothing really +! strange. Reference from same and other file to .text and .data in +! different combinations. + +! fileFsectionN, with F in rel-F.s, and N in: +! 1 - Same file and section. +! 2 - Same file, different section. +! 3 - Other file, same section. +! 4 - Other file, other section. + + .mode SHmedia + .text + .global start +start: + nop + .global file1text1 +file1text1: + nop + movi file1text1 & 65535,r10 + .global file1text2 +file1text2: + movi file1data2 & 65535,r20 + .global file1text3 +file1text3: + movi file2text3 & 65535,r20 + .global file1text4 +file1text4: + movi file2data4 & 65535,r20 + movi unresolved1 & 65535,r40 + movi unresolved6 & 65535,r30 + + .data + .long 0 + .global file1data1 +file1data1: + .long 0 + .long file1data1 + .global file1data2 +file1data2: + .long file1text2 + .global file1data3 +file1data3: + .long file2data3 + .global file1data4 +file1data4: + .long file2text4 + .long unresolved2 + .long unresolved5 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/rel-2.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/rel-2.s new file mode 100644 index 0000000..b1931b5 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/rel-2.s @@ -0,0 +1,46 @@ +! Relative linking, second file. + +! fileFsectionN, with F in rel-F.s, and N in: +! 1 - Same file and section. +! 2 - Same file, different section. +! 3 - Other file, same section. +! 4 - Other file, other section. + + .mode SHmedia + .text + .global start2 +start2: + nop + .global file2text1 +file2text1: + nop + movi file2text1 & 65535,r10 + .global file2text2 +file2text2: + movi file2data2 & 65535,r20 + .global file2text3 +file2text3: + movi file1text3 & 65535,r20 + .global file2text4 +file2text4: + movi file1data4 & 65535,r20 + movi unresolved1 & 65535,r30 + movi unresolved3 & 65535,r30 + + .data + .long 0 + .global file2data1 +file2data1: + .long 0 + .long file2data1 + .global file2data2 +file2data2: + .long file2text2 + .global file2data3 +file2data3: + .long file1data3 + .global file2data4 +file2data4: + .long file1text4 + .long unresolved2 + .long unresolved4 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/rel32.xd b/binutils-2.21/ld/testsuite/ld-sh/sh64/rel32.xd new file mode 100644 index 0000000..65c00ac --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/rel32.xd @@ -0,0 +1,92 @@ + +.*: file format .*-sh64 +.* +architecture: sh5, flags 0x0+11: +HAS_RELOC, HAS_SYMS +start address 0x0+ + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.text 0+40 0+ 0+ 0+34 2\*\*0 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 1 \.data 0+40 0+ 0+ 0+74 2\*\*2 + CONTENTS, ALLOC, LOAD, RELOC, DATA + 2 \.bss 0+ 0+ 0+ 0+b4 2\*\*0 + ALLOC + 3 \.stack 0+4 0+ 0+ 0+b4 2\*\*0 + CONTENTS, ALLOC, LOAD, DATA +SYMBOL TABLE: +0+ l d \.text 0+ (|.text) +0+ l d \.data 0+ (|.data) +0+ l d \.bss 0+ (|.bss) +0+ l d \.stack 0+ (|.stack) +0+ \*UND\* 0+ unresolved5 +0+c g \.text 0+ 0x04 file1text2 +0+24 g \.text 0+ 0x04 file2text1 +0+4 g \.data 0+ file1data1 +0+34 g \.data 0+ file2data4 +0+10 g \.text 0+ 0x04 file1text3 +0+2c g \.data 0+ file2data2 +0+c g \.data 0+ file1data2 +0+30 g \.text 0+ 0x04 file2text3 +0+20 g \.text 0+ 0x04 start2 +0+ \*UND\* 0+ unresolved1 +0+ \*UND\* 0+ unresolved6 +0+4 g \.text 0+ 0x04 file1text1 +0+2c g \.text 0+ 0x04 file2text2 +0+ \*UND\* 0+ unresolved3 +0+34 g \.text 0+ 0x04 file2text4 +0+ \*UND\* 0+ unresolved2 +0+ g \.text 0+ 0x04 start +0+14 g \.text 0+ 0x04 file1text4 +0+30 g \.data 0+ file2data3 +0+ \*UND\* 0+ unresolved4 +0+24 g \.data 0+ file2data1 +0+10 g \.data 0+ file1data3 +0+14 g \.data 0+ file1data4 + + +RELOCATION RECORDS FOR \[\.text\]: +OFFSET *TYPE *VALUE +0+8 R_SH_IMM_LOW16 file1text1 +0+c R_SH_IMM_LOW16 file1data2 +0+10 R_SH_IMM_LOW16 file2text3 +0+14 R_SH_IMM_LOW16 file2data4 +0+18 R_SH_IMM_LOW16 unresolved1 +0+1c R_SH_IMM_LOW16 unresolved6 +0+28 R_SH_IMM_LOW16 file2text1 +0+2c R_SH_IMM_LOW16 file2data2 +0+30 R_SH_IMM_LOW16 file1text3 +0+34 R_SH_IMM_LOW16 file1data4 +0+38 R_SH_IMM_LOW16 unresolved1 +0+3c R_SH_IMM_LOW16 unresolved3 + + +RELOCATION RECORDS FOR \[\.data\]: +OFFSET *TYPE *VALUE +0+8 R_SH_DIR32 file1data1 +0+c R_SH_DIR32 file1text2 +0+10 R_SH_DIR32 file2data3 +0+14 R_SH_DIR32 file2text4 +0+18 R_SH_DIR32 unresolved2 +0+1c R_SH_DIR32 unresolved5 +0+28 R_SH_DIR32 file2data1 +0+2c R_SH_DIR32 file2text2 +0+30 R_SH_DIR32 file1data3 +0+34 R_SH_DIR32 file1text4 +0+38 R_SH_DIR32 unresolved2 +0+3c R_SH_DIR32 unresolved4 + + +Contents of section \.text: + 0000 6ff0fff0 6ff0fff0 cc0000a0 cc000140 .* + 0010 cc000140 cc000140 cc000280 cc0001e0 .* + 0020 6ff0fff0 6ff0fff0 cc0000a0 cc000140 .* + 0030 cc000140 cc000140 cc0001e0 cc0001e0 .* +Contents of section \.data: + 0000 00000000 00000000 00000000 00000000 .* + 0010 00000000 00000000 00000000 00000000 .* + 0020 00000000 00000000 00000000 00000000 .* + 0030 00000000 00000000 00000000 00000000 .* +Contents of section .stack: + 0000 deaddead .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/rel64.xd b/binutils-2.21/ld/testsuite/ld-sh/sh64/rel64.xd new file mode 100644 index 0000000..986e013 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/rel64.xd @@ -0,0 +1,92 @@ + +.*: file format .*-sh64 +.* +architecture: sh5, flags 0x0+11: +HAS_RELOC, HAS_SYMS +start address 0x0+ + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.text 0+40 0+ 0+ 0+40 2\*\*0 + CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE + 1 \.data 0+40 0+ 0+ 0+80 2\*\*2 + CONTENTS, ALLOC, LOAD, RELOC, DATA + 2 \.bss 0+ 0+ 0+ 0+c0 2\*\*0 + ALLOC + 3 \.stack 0+4 0+ 0+ 0+c0 2\*\*0 + CONTENTS, ALLOC, LOAD, DATA +SYMBOL TABLE: +0+ l d \.text 0+ (|.text) +0+ l d \.data 0+ (|.data) +0+ l d \.bss 0+ (|.bss) +0+ l d \.stack 0+ (|.stack) +0+ \*UND\* 0+ unresolved5 +0+c g \.text 0+ 0x04 file1text2 +0+24 g \.text 0+ 0x04 file2text1 +0+4 g \.data 0+ file1data1 +0+34 g \.data 0+ file2data4 +0+10 g \.text 0+ 0x04 file1text3 +0+2c g \.data 0+ file2data2 +0+c g \.data 0+ file1data2 +0+30 g \.text 0+ 0x04 file2text3 +0+20 g \.text 0+ 0x04 start2 +0+ \*UND\* 0+ unresolved1 +0+ \*UND\* 0+ unresolved6 +0+4 g \.text 0+ 0x04 file1text1 +0+2c g \.text 0+ 0x04 file2text2 +0+ \*UND\* 0+ unresolved3 +0+34 g \.text 0+ 0x04 file2text4 +0+ \*UND\* 0+ unresolved2 +0+ g \.text 0+ 0x04 start +0+14 g \.text 0+ 0x04 file1text4 +0+30 g \.data 0+ file2data3 +0+ \*UND\* 0+ unresolved4 +0+24 g \.data 0+ file2data1 +0+10 g \.data 0+ file1data3 +0+14 g \.data 0+ file1data4 + + +RELOCATION RECORDS FOR \[\.text\]: +OFFSET TYPE VALUE +0+8 R_SH_IMM_LOW16 file1text1 +0+c R_SH_IMM_LOW16 file1data2 +0+10 R_SH_IMM_LOW16 file2text3 +0+14 R_SH_IMM_LOW16 file2data4 +0+18 R_SH_IMM_LOW16 unresolved1 +0+1c R_SH_IMM_LOW16 unresolved6 +0+28 R_SH_IMM_LOW16 file2text1 +0+2c R_SH_IMM_LOW16 file2data2 +0+30 R_SH_IMM_LOW16 file1text3 +0+34 R_SH_IMM_LOW16 file1data4 +0+38 R_SH_IMM_LOW16 unresolved1 +0+3c R_SH_IMM_LOW16 unresolved3 + + +RELOCATION RECORDS FOR \[\.data\]: +OFFSET TYPE VALUE +0+8 R_SH_DIR32 file1data1 +0+c R_SH_DIR32 file1text2 +0+10 R_SH_DIR32 file2data3 +0+14 R_SH_DIR32 file2text4 +0+18 R_SH_DIR32 unresolved2 +0+1c R_SH_DIR32 unresolved5 +0+28 R_SH_DIR32 file2data1 +0+2c R_SH_DIR32 file2text2 +0+30 R_SH_DIR32 file1data3 +0+34 R_SH_DIR32 file1text4 +0+38 R_SH_DIR32 unresolved2 +0+3c R_SH_DIR32 unresolved4 + + +Contents of section \.text: + 0000 6ff0fff0 6ff0fff0 cc0000a0 cc000140 .* + 0010 cc000140 cc000140 cc000280 cc0001e0 .* + 0020 6ff0fff0 6ff0fff0 cc0000a0 cc000140 .* + 0030 cc000140 cc000140 cc0001e0 cc0001e0 .* +Contents of section \.data: + 0000 00000000 00000000 00000000 00000000 .* + 0010 00000000 00000000 00000000 00000000 .* + 0020 00000000 00000000 00000000 00000000 .* + 0030 00000000 00000000 00000000 00000000 .* +Contents of section .stack: + 0000 deaddead .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/relax.exp b/binutils-2.21/ld/testsuite/ld-sh/sh64/relax.exp new file mode 100644 index 0000000..bb05e43 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/relax.exp @@ -0,0 +1,155 @@ +# Expect script for ld-sh tests +# Copyright (C) 2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. +# + +# Test SH relaxing - that is, that it's disabled when SHmedia sections +# are present. + +if ![istarget sh64-*-*] { + return +} + +# There are four source files: the first is SHcompact only, the second +# is SHmedia only, the third has both, and the fourth has only a +# .cranges section. The table below has: +# Title +# as flags for first source (else "n/a" to skip) +# ditto, other three files +# ld flags +# 1/0 whether relaxing should have been done or not, or -1 if we expect +# the linker to not produce an output file. + +if [istarget sh64*-*-linux*] { + set emul32 "shlelf32_linux" +} elseif { [istarget sh64*-*-netbsd*] || [istarget sh5*-*-netbsd*] } { + set emul32 "shelf32_nbsd" +} else { + set emul32 "shelf32" +} + +set sh64relaxtests { + {"SH64 not relaxing, shcompact" + {"-relax -isa shcompact" "n/a" "n/a" "n/a"} "-m$emul32" 0} + {"SH64 relaxing, shcompact" + {"-relax -isa shcompact" "n/a" "n/a" "n/a"} "-relax -m$emul32" 1} + {"SH64 relaxing, shcompacts" + {"-relax -isa shcompact" "-isa shcompact" "n/a" "n/a"} "-relax -m$emul32" 1} + {"SH64 relaxing disabled, shmedia" + {"-relax -isa shcompact" "-isa shmedia -no-mix" "n/a" "n/a"} "-relax -m$emul32" 0} + {"SH64 relaxing disabled, mixed" + {"-relax -isa shcompact" "n/a" "-isa shcompact" "n/a"} "-relax -m$emul32" 0} + {"SH64 relaxing disabled, cranges" + {"-relax -isa shcompact" "n/a" "n/a" ""} "-relax -m$emul32" 0} +} + +proc run_sh64relaxtest {sh64relaxtests} { + global ld + global as + global nm + global objdump + global readelf + global srcdir + global subdir + global emul32 + + set testindex 0 + + set sh64relaxfiles { + "relax1.s" "relax2.s" "relax3.s" "relax4.s" + } + + foreach testentry $sh64relaxtests { + set testname [lindex $testentry 0] + set as_options [lindex $testentry 1] + set ld_options [subst [lindex $testentry 2]] + set expect_relaxed [lindex $testentry 3] + + set is_unresolved 0 + set objfiles {} + + incr testindex + + # Assemble each file in the test. + for {set i 0} {$i < 4} {incr i} { + set as_file [lindex $sh64relaxfiles $i] + set as_opt [lindex $as_options $i] + if { [string compare $as_opt "n/a"] != 0 } { + set objfile "tmpdir/[file rootname $as_file]-$testindex.o" + lappend objfiles $objfile + + if ![ld_assemble $as "$as_opt $srcdir/$subdir/$as_file" $objfile] { + set is_unresolved 1 + break + } + } + } + + # Catch assembler errors. + if { $is_unresolved != 0 } { + unresolved $testname + continue + } + + set binfile "tmpdir/relax-$testindex.x" + + # We're not interested in the pass/fail of the linker as much + # as we're interested in whether or not relaxing got properly + # disabled. Hence the lax checking here. + + file delete $binfile + set result [ld_simple_link $ld $binfile " --no-warn-mismatch $ld_options $objfiles"] + if ![file exists $binfile] { + + if {$expect_relaxed == -1} { + pass $testname + continue + } + + verbose "$testname: file $binfile doesn't exist" 1 + fail $testname + continue + } + + catch "exec $objdump -d $binfile" objdump_output + + regexp "\[ \t](jsr|bsr)\[ \t]" $objdump_output ignore calltype + + if [string match $calltype "bsr"] { + set relaxed 1 + } elseif [string match $calltype "jsr"] { + set relaxed 0 + } else { + verbose "$testname: neither jsr nor bsr found" 1 + verbose $objdump_output 2 + fail $testname + continue + } + + if {$relaxed != $expect_relaxed} { + verbose $objdump_output 2 + fail $testname + exit + } else { + pass $testname + } + } +} + +run_sh64relaxtest $sh64relaxtests diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/relax1.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/relax1.s new file mode 100644 index 0000000..873954b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/relax1.s @@ -0,0 +1,12 @@ + .globl start +start: +.L3: + mov.l .L4,r1 + .uses .L3 + jsr @r1 + nop + nop +.L4: + .long .L5 +.L5: + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/relax2.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/relax2.s new file mode 100644 index 0000000..9bf0802 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/relax2.s @@ -0,0 +1,3 @@ + .text +foo1: + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/relax3.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/relax3.s new file mode 100644 index 0000000..964bacd --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/relax3.s @@ -0,0 +1,8 @@ + .text + .mode shmedia +foo1: + nop + + .mode shcompact +foo2: + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/relax4.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/relax4.s new file mode 100644 index 0000000..904df7c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/relax4.s @@ -0,0 +1,2 @@ + .section .cranges + .word 0 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/reldl-1.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/reldl-1.s new file mode 100644 index 0000000..0aeb332 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/reldl-1.s @@ -0,0 +1,171 @@ +! Relative linking. Like the simple test, but mixing in use of +! "datalabel" and offsets to the global symbols into the previous +! combinations. +! +! More systematic testing datalabel references, +! igoring section difference, symbol definition type and offset presence: +! Datalabel reference plus: +! (datalabel other file, other file, same file, none) +! = (1, 2, 3, 4, 12, 13, 23, 123) +! +! Definition: +! (none, same file, other file) = (a, b, c) +! +! Combined: +! = (a1, a2, a3, a4, a12, a13, a23, a123, b1, b2, b3, b4, b12, +! b13, b23, b123, c1, c2, c3, c4, c12, c13, c23, c123) + + .mode SHmedia + .text + .global start +start: + nop + .global file1text1 +file1text1: + nop + movi file1text1 & 65535,r10 + .global file1text2 +file1text2: + movi (datalabel file1data2) & 65535,r20 + .global file1text3 +file1text3: + movi file2text3 & 65535,r20 + .global file1text4 +file1text4: + movi file2data4 & 65535,r20 + .global file1text5 +file1text5: + movi unresolved1 & 65535,r40 + .global b1 +b1: + movi unresolved6 & 65535,r30 + .global b2 +b2: + movi (datalabel file1text1) & 65535,r10 + .global b3 +b3: + movi (datalabel file1text1 + 24) & 65535,r10 + .global b4 +b4: + movi (datalabel file1text5 + 8) & 65535, r40 + .global b12 +b12: + movi (datalabel file1data2 + 48) & 65535,r20 + .global b13 +b13: + movi file1data2 & 65535,r20 + .global b23 +b23: + movi (datalabel file2data4 + 16),r50 + .global b123 +b123: + movi (datalabel unresolved7) & 65535,r60 + .global oc1 +oc1: + movi (datalabel unresolved1) & 65535,r60 + .global oc2 +oc2: + nop + .global oc3 +oc3: + nop + .global oc4 +oc4: + nop + .global oc12 +oc12: + nop + .global oc13 +oc13: + nop + .global oc23 +oc23: + nop + .global oc123 +oc123: + nop + + .data + .long 0 + .global file1data1 +file1data1: + .long 0 + .long datalabel file1data1 + 8 + .global file1data2 +file1data2: + .long file1text2 + .global file1data3 +file1data3: + .long file2data3 + .global file1data4 +file1data4: + .long file2text4 + .global file1data5 +file1data5: + .long unresolved2 + .long unresolved5 + .long datalabel unresolved6 + 40 + .long unresolved9 + + .long datalabel a1 + .long a23 + .long b123 + .long c3 + .long c13 + .long datalabel a2 + .long datalabel a3 + .long datalabel a4 + .long datalabel a12 + .long datalabel a13 + .long datalabel a23 + .long datalabel a123 + .long datalabel b1 + .long datalabel b2 + .long a3 + .long a13 + .long datalabel b3 + .long datalabel b4 + .long datalabel b12 + .long datalabel b13 + .long a123 + .long b3 + .long b13 + .long b23 + .long datalabel b23 + .long datalabel b123 + .long datalabel c1 + .long datalabel c2 + .long datalabel c3 + .long c23 + .long c123 + .long datalabel c4 + .long datalabel c12 + .long datalabel c13 + .long datalabel c23 + .long datalabel c123 + + + .long datalabel oa1 + .long datalabel ob1 + .long ob123 + .long datalabel oc1 + .long oa2 + .long ob2 + .long oc2 + .long oa12 + .long datalabel oa12 + .long datalabel ob12 + .long ob12 + .long datalabel oc12 + .long oc12 + .long oa23 + .long datalabel oa13 + .long oc123 + .long datalabel ob13 + .long datalabel oc13 + .long ob23 + .long oc23 + .long oa123 + .long datalabel oa123 + .long datalabel ob123 + .long datalabel oc123 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/reldl-2.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/reldl-2.s new file mode 100644 index 0000000..d632021 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/reldl-2.s @@ -0,0 +1,156 @@ +! Relative linking with datalabel use, second file. Much like rel-2.s + + .mode SHmedia + .text + .global start2 +start2: + nop + .global file2text1 +file2text1: + nop + movi file2text1 & 65535,r10 + .global file2text2 +file2text2: + movi file2data2 & 65535,r20 + .global file2text3 +file2text3: + movi file1text3 & 65535,r20 + .global file2text4 +file2text4: + movi file1data4 & 65535,r20 + movi unresolved1 & 65535,r30 + movi unresolved3 & 65535,r30 + movi datalabel unresolved8 & 65535,r50 + movi datalabel unresolved9 & 65535,r50 + movi datalabel file1text1 & 65535,r40 + movi datalabel file1data2 & 65535,r40 + movi datalabel file1data3 & 65535,r40 + .global c1 +c1: + nop + .global c2 +c2: + nop + .global c3 +c3: + nop + .global c4 +c4: + nop + .global c12 +c12: + nop + .global c13 +c13: + nop + .global c23 +c23: + nop + .global c123 +c123: + nop + + .global ob1 +ob1: + nop + .global ob2 +ob2: + nop + .global ob3 +ob3: + nop + .global ob4 +ob4: + nop + .global ob12 +ob12: + nop + .global ob13 +ob13: + nop + .global ob23 +ob23: + nop + .global ob123 +ob123: + nop + + .data + .long 0 + .global file2data1 +file2data1: + .long 0 + .long file2data1 + .global file2data2 +file2data2: + .long file2text2 + .global file2data3 +file2data3: + .long file1data3 + .global file2data4 +file2data4: + .long file1text4 + .long unresolved2 + .long unresolved4 + + .long datalabel oa1 + .long datalabel oa2 + .long datalabel oa3 + .long oa13 + .long oc13 + .long datalabel oa4 + .long datalabel oa12 + .long datalabel oa13 + .long datalabel oa23 + .long oa23 + .long oa123 + .long oc3 + .long datalabel oa123 + .long datalabel ob1 + .long datalabel ob2 + .long datalabel ob3 + .long datalabel ob4 + .long oa3 + .long oc23 + .long oc123 + .long datalabel ob12 + .long datalabel ob13 + .long ob13 + .long ob23 + .long datalabel ob23 + .long datalabel ob123 + .long datalabel oc1 + .long ob3 + .long ob123 + .long datalabel oc2 + .long datalabel oc3 + .long datalabel oc4 + .long datalabel oc12 + .long datalabel oc13 + .long datalabel oc23 + .long datalabel oc123 + + .long datalabel a1 + .long c2 + .long b23 + .long datalabel b1 + .long datalabel c1 + .long datalabel a12 + .long a2 + .long b2 + .long datalabel b12 + .long datalabel c12 + .long b123 + .long c123 + .long datalabel a13 + .long datalabel b13 + .long c23 + .long a123 + .long datalabel c13 + .long datalabel a123 + .long c12 + .long a23 + .long datalabel b123 + .long a12 + .long b12 + .long datalabel c123 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/reldl32.rd b/binutils-2.21/ld/testsuite/ld-sh/sh64/reldl32.rd new file mode 100644 index 0000000..400e2af --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/reldl32.rd @@ -0,0 +1,358 @@ + +Relocation section '\.rela\.text' at offset 0x[0-9a-f]+ contains 26 entries: +.* +00000008 +0+5bf6 R_SH_IMM_LOW16 +00000004 +file1text1 +\+ 0 +0000000c +0+2df6 R_SH_IMM_LOW16 +0000000c +file1data2 +\+ 0 +00000010 +0+30f6 R_SH_IMM_LOW16 +00000070 +file2text3 +\+ 0 +00000014 +0+0ff6 R_SH_IMM_LOW16 +0000012c +file2data4 +\+ 0 +00000018 +0+4cf6 R_SH_IMM_LOW16 +00000000 +unresolved1 +\+ 0 +0000001c +0+51f6 R_SH_IMM_LOW16 +00000000 +unresolved6 +\+ 0 +00000020 +0+5df6 R_SH_IMM_LOW16 +00000000 +file1text1 +\+ 0 +00000024 +0+5df6 R_SH_IMM_LOW16 +00000000 +file1text1 +\+ 18 +00000028 +0+21f6 R_SH_IMM_LOW16 +00000000 +file1text5 +\+ 8 +0000002c +0+2df6 R_SH_IMM_LOW16 +0000000c +file1data2 +\+ 30 +00000030 +0+2df6 R_SH_IMM_LOW16 +0000000c +file1data2 +\+ 0 +0000003c +0+42f6 R_SH_IMM_LOW16 +00000000 +unresolved7 +\+ 0 +00000040 +0+27f6 R_SH_IMM_LOW16 +00000000 +unresolved1 +\+ 0 +00000034 +0+35f8 R_SH_IMM_MEDLOW16 +00000000 +file2data4 +\+ 10 +00000038 +0+35f6 R_SH_IMM_LOW16 +00000000 +file2data4 +\+ 10 +00000068 +0+08f6 R_SH_IMM_LOW16 +00000064 +file2text1 +\+ 0 +0000006c +0+24f6 R_SH_IMM_LOW16 +00000124 +file2data2 +\+ 0 +00000070 +0+23f6 R_SH_IMM_LOW16 +00000010 +file1text3 +\+ 0 +00000074 +0+81f6 R_SH_IMM_LOW16 +00000014 +file1data4 +\+ 0 +00000078 +0+4cf6 R_SH_IMM_LOW16 +00000000 +unresolved1 +\+ 0 +0000007c +0+64f6 R_SH_IMM_LOW16 +00000000 +unresolved3 +\+ 0 +00000080 +0+85f6 R_SH_IMM_LOW16 +00000000 +unresolved8 +\+ 0 +00000084 +0+32f6 R_SH_IMM_LOW16 +00000000 +unresolved9 +\+ 0 +00000088 +0+5df6 R_SH_IMM_LOW16 +00000000 +file1text1 +\+ 0 +0000008c +0+4bf6 R_SH_IMM_LOW16 +00000000 +file1data2 +\+ 0 +00000090 +0+28f6 R_SH_IMM_LOW16 +00000000 +file1data3 +\+ 0 + +Relocation section '\.rela\.data' at offset 0x[0-9a-f]+ contains 134 entries: +.* +00000008 +0+0b01 R_SH_DIR32 +00000004 +file1data1 +\+ 0 +0000000c +0+0701 R_SH_DIR32 +0000000c +file1text2 +\+ 0 +00000010 +0+7801 R_SH_DIR32 +00000128 +file2data3 +\+ 0 +00000014 +0+6701 R_SH_DIR32 +00000074 +file2text4 +\+ 0 +00000018 +0+7401 R_SH_DIR32 +00000000 +unresolved2 +\+ 0 +0000001c +0+0501 R_SH_DIR32 +00000000 +unresolved5 +\+ 0 +00000020 +0+6c01 R_SH_DIR32 +00000000 +unresolved6 +\+ 0 +00000024 +0+0601 R_SH_DIR32 +00000000 +unresolved9 +\+ 0 +00000028 +0+7a01 R_SH_DIR32 +00000000 +a1 +\+ 0 +0000002c +0+7001 R_SH_DIR32 +00000000 +a23 +\+ 0 +00000030 +0+5401 R_SH_DIR32 +0000003c +b123 +\+ 0 +00000034 +0+6a01 R_SH_DIR32 +0000009c +c3 +\+ 0 +00000038 +0+3c01 R_SH_DIR32 +000000a8 +c13 +\+ 0 +0000003c +0+2601 R_SH_DIR32 +00000000 +a2 +\+ 0 +00000040 +0+4e01 R_SH_DIR32 +00000000 +a3 +\+ 0 +00000044 +0+2501 R_SH_DIR32 +00000000 +a4 +\+ 0 +00000048 +0+6901 R_SH_DIR32 +00000000 +a12 +\+ 0 +0000004c +0+1501 R_SH_DIR32 +00000000 +a13 +\+ 0 +00000050 +0+7601 R_SH_DIR32 +00000000 +a23 +\+ 0 +00000054 +0+6201 R_SH_DIR32 +00000000 +a123 +\+ 0 +00000058 +0+3d01 R_SH_DIR32 +00000000 +b1 +\+ 0 +0000005c +0+7101 R_SH_DIR32 +00000000 +b2 +\+ 0 +00000060 +0+2f01 R_SH_DIR32 +00000000 +a3 +\+ 0 +00000064 +0+7f01 R_SH_DIR32 +00000000 +a13 +\+ 0 +00000068 +0+2e01 R_SH_DIR32 +00000000 +b3 +\+ 0 +0000006c +0+6801 R_SH_DIR32 +00000000 +b4 +\+ 0 +00000070 +0+5201 R_SH_DIR32 +00000000 +b12 +\+ 0 +00000074 +0+2901 R_SH_DIR32 +00000000 +b13 +\+ 0 +00000078 +0+3e01 R_SH_DIR32 +00000000 +a123 +\+ 0 +0000007c +0+6501 R_SH_DIR32 +00000024 +b3 +\+ 0 +00000080 +0+3b01 R_SH_DIR32 +00000030 +b13 +\+ 0 +00000084 +0+6f01 R_SH_DIR32 +00000034 +b23 +\+ 0 +00000088 +0+7d01 R_SH_DIR32 +00000000 +b23 +\+ 0 +0000008c +0+0c01 R_SH_DIR32 +00000000 +b123 +\+ 0 +00000090 +0+8301 R_SH_DIR32 +00000000 +c1 +\+ 0 +00000094 +0+2c01 R_SH_DIR32 +00000000 +c2 +\+ 0 +00000098 +0+6301 R_SH_DIR32 +00000000 +c3 +\+ 0 +0000009c +0+3901 R_SH_DIR32 +000000ac +c23 +\+ 0 +000000a0 +0+7e01 R_SH_DIR32 +000000b0 +c123 +\+ 0 +000000a4 +0+0e01 R_SH_DIR32 +00000000 +c4 +\+ 0 +000000a8 +0+2001 R_SH_DIR32 +00000000 +c12 +\+ 0 +000000ac +0+3101 R_SH_DIR32 +00000000 +c13 +\+ 0 +000000b0 +0+3601 R_SH_DIR32 +00000000 +c23 +\+ 0 +000000b4 +0+3a01 R_SH_DIR32 +00000000 +c123 +\+ 0 +000000b8 +0+4801 R_SH_DIR32 +00000000 +oa1 +\+ 0 +000000bc +0+1401 R_SH_DIR32 +00000000 +ob1 +\+ 0 +000000c0 +0+4401 R_SH_DIR32 +000000d0 +ob123 +\+ 0 +000000c4 +0+5901 R_SH_DIR32 +00000000 +oc1 +\+ 0 +000000c8 +0+7901 R_SH_DIR32 +00000000 +oa2 +\+ 0 +000000cc +0+6101 R_SH_DIR32 +000000b8 +ob2 +\+ 0 +000000d0 +0+7201 R_SH_DIR32 +00000044 +oc2 +\+ 0 +000000d4 +0+4901 R_SH_DIR32 +00000000 +oa12 +\+ 0 +000000d8 +0+1b01 R_SH_DIR32 +00000000 +oa12 +\+ 0 +000000dc +0+6001 R_SH_DIR32 +00000000 +ob12 +\+ 0 +000000e0 +0+4a01 R_SH_DIR32 +000000c4 +ob12 +\+ 0 +000000e4 +0+5a01 R_SH_DIR32 +00000000 +oc12 +\+ 0 +000000e8 +0+1201 R_SH_DIR32 +00000050 +oc12 +\+ 0 +000000ec +0+3f01 R_SH_DIR32 +00000000 +oa23 +\+ 0 +000000f0 +0+4501 R_SH_DIR32 +00000000 +oa13 +\+ 0 +000000f4 +0+0a01 R_SH_DIR32 +0000005c +oc123 +\+ 0 +000000f8 +0+5501 R_SH_DIR32 +00000000 +ob13 +\+ 0 +000000fc +0+5c01 R_SH_DIR32 +00000000 +oc13 +\+ 0 +00000100 +0+8201 R_SH_DIR32 +000000cc +ob23 +\+ 0 +00000104 +0+2b01 R_SH_DIR32 +00000058 +oc23 +\+ 0 +00000108 +0+5701 R_SH_DIR32 +00000000 +oa123 +\+ 0 +0000010c +0+5001 R_SH_DIR32 +00000000 +oa123 +\+ 0 +00000110 +0+6601 R_SH_DIR32 +00000000 +ob123 +\+ 0 +00000114 +0+3301 R_SH_DIR32 +00000000 +oc123 +\+ 0 +00000120 +0+7c01 R_SH_DIR32 +0000011c +file2data1 +\+ 0 +00000124 +0+5e01 R_SH_DIR32 +0000006c +file2text2 +\+ 0 +00000128 +0+8001 R_SH_DIR32 +00000010 +file1data3 +\+ 0 +0000012c +0+7701 R_SH_DIR32 +00000014 +file1text4 +\+ 0 +00000130 +0+7401 R_SH_DIR32 +00000000 +unresolved2 +\+ 0 +00000134 +0+7b01 R_SH_DIR32 +00000000 +unresolved4 +\+ 0 +00000138 +0+4801 R_SH_DIR32 +00000000 +oa1 +\+ 0 +0000013c +0+1701 R_SH_DIR32 +00000000 +oa2 +\+ 0 +00000140 +0+6d01 R_SH_DIR32 +00000000 +oa3 +\+ 0 +00000144 +0+1c01 R_SH_DIR32 +00000000 +oa13 +\+ 0 +00000148 +0+1901 R_SH_DIR32 +00000054 +oc13 +\+ 0 +0000014c +0+1001 R_SH_DIR32 +00000000 +oa4 +\+ 0 +00000150 +0+1b01 R_SH_DIR32 +00000000 +oa12 +\+ 0 +00000154 +0+4501 R_SH_DIR32 +00000000 +oa13 +\+ 0 +00000158 +0+3801 R_SH_DIR32 +00000000 +oa23 +\+ 0 +0000015c +0+3f01 R_SH_DIR32 +00000000 +oa23 +\+ 0 +00000160 +0+5701 R_SH_DIR32 +00000000 +oa123 +\+ 0 +00000164 +0+1601 R_SH_DIR32 +00000048 +oc3 +\+ 0 +00000168 +0+5001 R_SH_DIR32 +00000000 +oa123 +\+ 0 +0000016c +0+1401 R_SH_DIR32 +00000000 +ob1 +\+ 0 +00000170 +0+2201 R_SH_DIR32 +00000000 +ob2 +\+ 0 +00000174 +0+5f01 R_SH_DIR32 +00000000 +ob3 +\+ 0 +00000178 +0+1301 R_SH_DIR32 +00000000 +ob4 +\+ 0 +0000017c +0+8401 R_SH_DIR32 +00000000 +oa3 +\+ 0 +00000180 +0+2b01 R_SH_DIR32 +00000058 +oc23 +\+ 0 +00000184 +0+0a01 R_SH_DIR32 +0000005c +oc123 +\+ 0 +00000188 +0+6001 R_SH_DIR32 +00000000 +ob12 +\+ 0 +0000018c +0+5501 R_SH_DIR32 +00000000 +ob13 +\+ 0 +00000190 +0+4d01 R_SH_DIR32 +000000c8 +ob13 +\+ 0 +00000194 +0+8201 R_SH_DIR32 +000000cc +ob23 +\+ 0 +00000198 +0+5801 R_SH_DIR32 +00000000 +ob23 +\+ 0 +0000019c +0+6601 R_SH_DIR32 +00000000 +ob123 +\+ 0 +000001a0 +0+5901 R_SH_DIR32 +00000000 +oc1 +\+ 0 +000001a4 +0+1101 R_SH_DIR32 +000000bc +ob3 +\+ 0 +000001a8 +0+4401 R_SH_DIR32 +000000d0 +ob123 +\+ 0 +000001ac +0+0901 R_SH_DIR32 +00000000 +oc2 +\+ 0 +000001b0 +0+3701 R_SH_DIR32 +00000000 +oc3 +\+ 0 +000001b4 +0+5301 R_SH_DIR32 +00000000 +oc4 +\+ 0 +000001b8 +0+5a01 R_SH_DIR32 +00000000 +oc12 +\+ 0 +000001bc +0+5c01 R_SH_DIR32 +00000000 +oc13 +\+ 0 +000001c0 +0+2a01 R_SH_DIR32 +00000000 +oc23 +\+ 0 +000001c4 +0+3301 R_SH_DIR32 +00000000 +oc123 +\+ 0 +000001c8 +0+7a01 R_SH_DIR32 +00000000 +a1 +\+ 0 +000001cc +0+1a01 R_SH_DIR32 +00000098 +c2 +\+ 0 +000001d0 +0+6f01 R_SH_DIR32 +00000034 +b23 +\+ 0 +000001d4 +0+3d01 R_SH_DIR32 +00000000 +b1 +\+ 0 +000001d8 +0+8301 R_SH_DIR32 +00000000 +c1 +\+ 0 +000001dc +0+6901 R_SH_DIR32 +00000000 +a12 +\+ 0 +000001e0 +0+5601 R_SH_DIR32 +00000000 +a2 +\+ 0 +000001e4 +0+0d01 R_SH_DIR32 +00000020 +b2 +\+ 0 +000001e8 +0+5201 R_SH_DIR32 +00000000 +b12 +\+ 0 +000001ec +0+2001 R_SH_DIR32 +00000000 +c12 +\+ 0 +000001f0 +0+5401 R_SH_DIR32 +0000003c +b123 +\+ 0 +000001f4 +0+7e01 R_SH_DIR32 +000000b0 +c123 +\+ 0 +000001f8 +0+1501 R_SH_DIR32 +00000000 +a13 +\+ 0 +000001fc +0+2901 R_SH_DIR32 +00000000 +b13 +\+ 0 +00000200 +0+3901 R_SH_DIR32 +000000ac +c23 +\+ 0 +00000204 +0+3e01 R_SH_DIR32 +00000000 +a123 +\+ 0 +00000208 +0+3101 R_SH_DIR32 +00000000 +c13 +\+ 0 +0000020c +0+6201 R_SH_DIR32 +00000000 +a123 +\+ 0 +00000210 +0+6e01 R_SH_DIR32 +000000a4 +c12 +\+ 0 +00000214 +0+7001 R_SH_DIR32 +00000000 +a23 +\+ 0 +00000218 +0+0c01 R_SH_DIR32 +00000000 +b123 +\+ 0 +0000021c +0+4001 R_SH_DIR32 +00000000 +a12 +\+ 0 +00000220 +0+7301 R_SH_DIR32 +0000002c +b12 +\+ 0 +00000224 +0+3a01 R_SH_DIR32 +00000000 +c123 +\+ 0 + +Symbol table '\.symtab' contains 134 entries: + +Num: +Value +Size +Type +Bind +Vis +Ndx +Name + +0: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +UND + +1: 00000000 +0 +SECTION +LOCAL +DEFAULT +1 + +2: 00000000 +0 +SECTION +LOCAL +DEFAULT +3 + +3: 00000000 +0 +SECTION +LOCAL +DEFAULT +5 + +4: 00000000 +0 +SECTION +LOCAL +DEFAULT +6 + +5: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND unresolved5 + +6: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND unresolved9 + +7: 0000000c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file1text2 + +8: 00000064 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file2text1 + +9: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc2 + +10: 0000005c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc123 + +11: 00000004 +0 +NOTYPE +GLOBAL +DEFAULT +3 file1data1 + +12: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b123 + +13: 00000020 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b2 + +14: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c4 + +15: 0000012c +0 +NOTYPE +GLOBAL +DEFAULT +3 file2data4 + +16: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa4 + +17: 000000bc +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 ob3 + +18: 00000050 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc12 + +19: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob4 + +20: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob1 + +21: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a13 + +22: 00000048 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc3 + +23: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa2 + +24: 000000a0 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c4 + +25: 00000054 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc13 + +26: 00000098 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c2 + +27: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa12 + +28: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND oa13 + +29: 000000c0 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 ob4 + +30: 0000001c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b1 + +31: 00000018 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file1text5 + +32: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c12 + +33: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND file1text5 + +34: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob2 + +35: 00000010 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file1text3 + +36: 00000124 +0 +NOTYPE +GLOBAL +DEFAULT +3 file2data2 + +37: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a4 + +38: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a2 + +39: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND unresolved1 + +40: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND file1data3 + +41: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b13 + +42: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc23 + +43: 00000058 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc23 + +44: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c2 + +45: 0000000c +0 +NOTYPE +GLOBAL +DEFAULT +3 file1data2 + +46: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b3 + +47: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND a3 + +48: 00000070 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file2text3 + +49: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c13 + +50: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND unresolved9 + +51: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc123 + +52: 00000028 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b4 + +53: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND file2data4 + +54: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c23 + +55: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc3 + +56: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa23 + +57: 000000ac +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c23 + +58: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c123 + +59: 00000030 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b13 + +60: 000000a8 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c13 + +61: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b1 + +62: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND a123 + +63: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND oa23 + +64: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND a12 + +65: 000000b4 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 ob1 + +66: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND unresolved7 + +67: 00000060 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 start2 + +68: 000000d0 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 ob123 + +69: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa13 + +70: 00000094 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c1 + +71: 0000004c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc4 + +72: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa1 + +73: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND oa12 + +74: 000000c4 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 ob12 + +75: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND file1data2 + +76: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND unresolved1 + +77: 000000c8 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 ob13 + +78: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a3 + +79: 00000018 +0 +NOTYPE +GLOBAL +DEFAULT +3 file1data5 + +80: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa123 + +81: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND unresolved6 + +82: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b12 + +83: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc4 + +84: 0000003c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b123 + +85: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob13 + +86: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND a2 + +87: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND oa123 + +88: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob23 + +89: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc1 + +90: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc12 + +91: 00000004 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file1text1 + +92: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc13 + +93: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND file1text1 + +94: 0000006c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file2text2 + +95: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob3 + +96: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob12 + +97: 000000b8 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 ob2 + +98: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a123 + +99: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c3 + +100: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND unresolved3 + +101: 00000024 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b3 + +102: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob123 + +103: 00000074 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file2text4 + +104: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b4 + +105: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a12 + +106: 0000009c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c3 + +107: 00000040 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc1 + +108: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND unresolved6 + +109: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa3 + +110: 000000a4 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c12 + +111: 00000034 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b23 + +112: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND a23 + +113: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b2 + +114: 00000044 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc2 + +115: 0000002c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b12 + +116: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND unresolved2 + +117: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 start + +118: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a23 + +119: 00000014 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file1text4 + +120: 00000128 +0 +NOTYPE +GLOBAL +DEFAULT +3 file2data3 + +121: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND oa2 + +122: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a1 + +123: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND unresolved4 + +124: 0000011c +0 +NOTYPE +GLOBAL +DEFAULT +3 file2data1 + +125: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b23 + +126: 000000b0 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c123 + +127: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND a13 + +128: 00000010 +0 +NOTYPE +GLOBAL +DEFAULT +3 file1data3 + +129: 00000014 +0 +NOTYPE +GLOBAL +DEFAULT +3 file1data4 + +130: 000000cc +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 ob23 + +131: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c1 + +132: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND oa3 + +133: 00000000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND unresolved8 + +Hex dump of section '\.text': +.* + 0x00000000 6ff0fff0 6ff0fff0 cc0000a0 cc000140 .* + 0x00000010 cc000140 cc000140 cc000280 cc0001e0 .* + 0x00000020 cc0000a0 cc0000a0 cc000280 cc000140 .* + 0x00000030 cc000140 cc000320 c8000320 cc0003c0 .* + 0x00000040 cc0003c0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00000050 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00000060 6ff0fff0 6ff0fff0 cc0000a0 cc000140 .* + 0x00000070 cc000140 cc000140 cc0001e0 cc0001e0 .* + 0x00000080 cc000320 cc000320 cc000280 cc000280 .* + 0x00000090 cc000280 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x000000a0 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x000000b0 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x000000c0 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x000000d0 6ff0fff0 .* + +Hex dump of section '\.data': +.* + 0x00000000 00000000 00000000 00000008 00000000 .* + 0x00000010 00000000 00000000 00000000 00000000 .* + 0x00000020 00000028 00000000 00000000 00000000 .* + 0x00000030 00000000 00000000 00000000 00000000 .* + 0x00000040 00000000 00000000 00000000 00000000 .* + 0x00000050 00000000 00000000 00000000 00000000 .* + 0x00000060 00000000 00000000 00000000 00000000 .* + 0x00000070 00000000 00000000 00000000 00000000 .* + 0x00000080 00000000 00000000 00000000 00000000 .* + 0x00000090 00000000 00000000 00000000 00000000 .* + 0x000000a0 00000000 00000000 00000000 00000000 .* + 0x000000b0 00000000 00000000 00000000 00000000 .* + 0x000000c0 00000000 00000000 00000000 00000000 .* + 0x000000d0 00000000 00000000 00000000 00000000 .* + 0x000000e0 00000000 00000000 00000000 00000000 .* + 0x000000f0 00000000 00000000 00000000 00000000 .* + 0x00000100 00000000 00000000 00000000 00000000 .* + 0x00000110 00000000 00000000 00000000 00000000 .* + 0x00000120 00000000 00000000 00000000 00000000 .* + 0x00000130 00000000 00000000 00000000 00000000 .* + 0x00000140 00000000 00000000 00000000 00000000 .* + 0x00000150 00000000 00000000 00000000 00000000 .* + 0x00000160 00000000 00000000 00000000 00000000 .* + 0x00000170 00000000 00000000 00000000 00000000 .* + 0x00000180 00000000 00000000 00000000 00000000 .* + 0x00000190 00000000 00000000 00000000 00000000 .* + 0x000001a0 00000000 00000000 00000000 00000000 .* + 0x000001b0 00000000 00000000 00000000 00000000 .* + 0x000001c0 00000000 00000000 00000000 00000000 .* + 0x000001d0 00000000 00000000 00000000 00000000 .* + 0x000001e0 00000000 00000000 00000000 00000000 .* + 0x000001f0 00000000 00000000 00000000 00000000 .* + 0x00000200 00000000 00000000 00000000 00000000 .* + 0x00000210 00000000 00000000 00000000 00000000 .* + 0x00000220 00000000 00000000 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/reldl64.rd b/binutils-2.21/ld/testsuite/ld-sh/sh64/reldl64.rd new file mode 100644 index 0000000..8bd5502 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/reldl64.rd @@ -0,0 +1,360 @@ + +Relocation section '\.rela\.text' at offset 0x[0-9a-f]+ contains 28 entries: +.* +0+8 +0+5b000000f6 R_SH_IMM_LOW16[ ]+0+4 +file1text1[ ]+\+ 0 +0+c +0+2d000000f6 R_SH_IMM_LOW16[ ]+0+c +file1data2[ ]+\+ 0 +0+10 +0+30000000f6 R_SH_IMM_LOW16[ ]+0+78 +file2text3[ ]+\+ 0 +0+14 +0+0f000000f6 R_SH_IMM_LOW16[ ]+0+12c +file2data4[ ]+\+ 0 +0+18 +0+4c000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved1[ ]+\+ 0 +0+1c +0+51000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved6[ ]+\+ 0 +0+20 +0+5d000000f6 R_SH_IMM_LOW16[ ]+0+ +file1text1[ ]+\+ 0 +0+24 +0+5d000000f6 R_SH_IMM_LOW16[ ]+0+ +file1text1[ ]+\+ 18 +0+28 +0+21000000f6 R_SH_IMM_LOW16[ ]+0+ +file1text5[ ]+\+ 8 +0+2c +0+2d000000f6 R_SH_IMM_LOW16[ ]+0+c +file1data2[ ]+\+ 30 +0+30 +0+2d000000f6 R_SH_IMM_LOW16[ ]+0+c +file1data2[ ]+\+ 0 +0+44 +0+42000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved7[ ]+\+ 0 +0+48 +0+27000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved1[ ]+\+ 0 +0+34 +0+35000000fc R_SH_IMM_HI16[ ]+0+ +file2data4[ ]+\+ 10 +0+38 +0+35000000fa R_SH_IMM_MEDHI16[ ]+0+ +file2data4[ ]+\+ 10 +0+3c +0+35000000f8 R_SH_IMM_MEDLOW16[ ]+0+ +file2data4[ ]+\+ 10 +0+40 +0+35000000f6 R_SH_IMM_LOW16[ ]+0+ +file2data4[ ]+\+ 10 +0+70 +0+08000000f6 R_SH_IMM_LOW16[ ]+0+6c +file2text1[ ]+\+ 0 +0+74 +0+24000000f6 R_SH_IMM_LOW16[ ]+0+124 +file2data2[ ]+\+ 0 +0+78 +0+23000000f6 R_SH_IMM_LOW16[ ]+0+10 +file1text3[ ]+\+ 0 +0+7c +0+81000000f6 R_SH_IMM_LOW16[ ]+0+14 +file1data4[ ]+\+ 0 +0+80 +0+4c000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved1[ ]+\+ 0 +0+84 +0+64000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved3[ ]+\+ 0 +0+88 +0+85000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved8[ ]+\+ 0 +0+8c +0+32000000f6 R_SH_IMM_LOW16[ ]+0+ +unresolved9[ ]+\+ 0 +0+90 +0+5d000000f6 R_SH_IMM_LOW16[ ]+0+ +file1text1[ ]+\+ 0 +0+94 +0+4b000000f6 R_SH_IMM_LOW16[ ]+0+ +file1data2[ ]+\+ 0 +0+98 +0+28000000f6 R_SH_IMM_LOW16[ ]+0+ +file1data3[ ]+\+ 0 + +Relocation section '\.rela\.data' at offset 0x[0-9a-f]+ contains 134 entries: +.* +0+8 +0+0b00000001 R_SH_DIR32[ ]+0+4 +file1data1[ ]+\+ 0 +0+c +0+700000001 R_SH_DIR32[ ]+0+c +file1text2[ ]+\+ 0 +0+10 +0+7800000001 R_SH_DIR32[ ]+0+128 +file2data3[ ]+\+ 0 +0+14 +0+6700000001 R_SH_DIR32[ ]+0+7c +file2text4[ ]+\+ 0 +0+18 +0+7400000001 R_SH_DIR32[ ]+0+ +unresolved2[ ]+\+ 0 +0+1c +0+0500000001 R_SH_DIR32[ ]+0+ +unresolved5[ ]+\+ 0 +0+20 +0+6c00000001 R_SH_DIR32[ ]+0+ +unresolved6[ ]+\+ 0 +0+24 +0+0600000001 R_SH_DIR32[ ]+0+ +unresolved9[ ]+\+ 0 +0+28 +0+7a00000001 R_SH_DIR32[ ]+0+ +a1[ ]+\+ 0 +0+2c +0+7000000001 R_SH_DIR32[ ]+0+ +a23[ ]+\+ 0 +0+30 +0+5400000001 R_SH_DIR32[ ]+0+44 +b123[ ]+\+ 0 +0+34 +0+6a00000001 R_SH_DIR32[ ]+0+a4 +c3[ ]+\+ 0 +0+38 +0+3c00000001 R_SH_DIR32[ ]+0+b0 +c13[ ]+\+ 0 +0+3c +0+2600000001 R_SH_DIR32[ ]+0+ +a2[ ]+\+ 0 +0+40 +0+4e00000001 R_SH_DIR32[ ]+0+ +a3[ ]+\+ 0 +0+44 +0+2500000001 R_SH_DIR32[ ]+0+ +a4[ ]+\+ 0 +0+48 +0+6900000001 R_SH_DIR32[ ]+0+ +a12[ ]+\+ 0 +0+4c +0+1500000001 R_SH_DIR32[ ]+0+ +a13[ ]+\+ 0 +0+50 +0+7600000001 R_SH_DIR32[ ]+0+ +a23[ ]+\+ 0 +0+54 +0+6200000001 R_SH_DIR32[ ]+0+ +a123[ ]+\+ 0 +0+58 +0+3d00000001 R_SH_DIR32[ ]+0+ +b1[ ]+\+ 0 +0+5c +0+7100000001 R_SH_DIR32[ ]+0+ +b2[ ]+\+ 0 +0+60 +0+2f00000001 R_SH_DIR32[ ]+0+ +a3[ ]+\+ 0 +0+64 +0+7f00000001 R_SH_DIR32[ ]+0+ +a13[ ]+\+ 0 +0+68 +0+2e00000001 R_SH_DIR32[ ]+0+ +b3[ ]+\+ 0 +0+6c +0+6800000001 R_SH_DIR32[ ]+0+ +b4[ ]+\+ 0 +0+70 +0+5200000001 R_SH_DIR32[ ]+0+ +b12[ ]+\+ 0 +0+74 +0+2900000001 R_SH_DIR32[ ]+0+ +b13[ ]+\+ 0 +0+78 +0+3e00000001 R_SH_DIR32[ ]+0+ +a123[ ]+\+ 0 +0+7c +0+6500000001 R_SH_DIR32[ ]+0+24 +b3[ ]+\+ 0 +0+80 +0+3b00000001 R_SH_DIR32[ ]+0+30 +b13[ ]+\+ 0 +0+84 +0+6f00000001 R_SH_DIR32[ ]+0+34 +b23[ ]+\+ 0 +0+88 +0+7d00000001 R_SH_DIR32[ ]+0+ +b23[ ]+\+ 0 +0+8c +0+0c00000001 R_SH_DIR32[ ]+0+ +b123[ ]+\+ 0 +0+90 +0+8300000001 R_SH_DIR32[ ]+0+ +c1[ ]+\+ 0 +0+94 +0+2c00000001 R_SH_DIR32[ ]+0+ +c2[ ]+\+ 0 +0+98 +0+6300000001 R_SH_DIR32[ ]+0+ +c3[ ]+\+ 0 +0+9c +0+3900000001 R_SH_DIR32[ ]+0+b4 +c23[ ]+\+ 0 +0+a0 +0+7e00000001 R_SH_DIR32[ ]+0+b8 +c123[ ]+\+ 0 +0+a4 +0+0e00000001 R_SH_DIR32[ ]+0+ +c4[ ]+\+ 0 +0+a8 +0+2000000001 R_SH_DIR32[ ]+0+ +c12[ ]+\+ 0 +0+ac +0+3100000001 R_SH_DIR32[ ]+0+ +c13[ ]+\+ 0 +0+b0 +0+3600000001 R_SH_DIR32[ ]+0+ +c23[ ]+\+ 0 +0+b4 +0+3a00000001 R_SH_DIR32[ ]+0+ +c123[ ]+\+ 0 +0+b8 +0+4800000001 R_SH_DIR32[ ]+0+ +oa1[ ]+\+ 0 +0+bc +0+1400000001 R_SH_DIR32[ ]+0+ +ob1[ ]+\+ 0 +0+c0 +0+4400000001 R_SH_DIR32[ ]+0+d8 +ob123[ ]+\+ 0 +0+c4 +0+5900000001 R_SH_DIR32[ ]+0+ +oc1[ ]+\+ 0 +0+c8 +0+7900000001 R_SH_DIR32[ ]+0+ +oa2[ ]+\+ 0 +0+cc +0+6100000001 R_SH_DIR32[ ]+0+c0 +ob2[ ]+\+ 0 +0+d0 +0+7200000001 R_SH_DIR32[ ]+0+4c +oc2[ ]+\+ 0 +0+d4 +0+4900000001 R_SH_DIR32[ ]+0+ +oa12[ ]+\+ 0 +0+d8 +0+1b00000001 R_SH_DIR32[ ]+0+ +oa12[ ]+\+ 0 +0+dc +0+6000000001 R_SH_DIR32[ ]+0+ +ob12[ ]+\+ 0 +0+e0 +0+4a00000001 R_SH_DIR32[ ]+0+cc +ob12[ ]+\+ 0 +0+e4 +0+5a00000001 R_SH_DIR32[ ]+0+ +oc12[ ]+\+ 0 +0+e8 +0+1200000001 R_SH_DIR32[ ]+0+58 +oc12[ ]+\+ 0 +0+ec +0+3f00000001 R_SH_DIR32[ ]+0+ +oa23[ ]+\+ 0 +0+f0 +0+4500000001 R_SH_DIR32[ ]+0+ +oa13[ ]+\+ 0 +0+f4 +0+0a00000001 R_SH_DIR32[ ]+0+64 +oc123[ ]+\+ 0 +0+f8 +0+5500000001 R_SH_DIR32[ ]+0+ +ob13[ ]+\+ 0 +0+fc +0+5c00000001 R_SH_DIR32[ ]+0+ +oc13[ ]+\+ 0 +0+100 +0+8200000001 R_SH_DIR32[ ]+0+d4 +ob23[ ]+\+ 0 +0+104 +0+2b00000001 R_SH_DIR32[ ]+0+60 +oc23[ ]+\+ 0 +0+108 +0+5700000001 R_SH_DIR32[ ]+0+ +oa123[ ]+\+ 0 +0+10c +0+5000000001 R_SH_DIR32[ ]+0+ +oa123[ ]+\+ 0 +0+110 +0+6600000001 R_SH_DIR32[ ]+0+ +ob123[ ]+\+ 0 +0+114 +0+3300000001 R_SH_DIR32[ ]+0+ +oc123[ ]+\+ 0 +0+120 +0+7c00000001 R_SH_DIR32[ ]+0+11c +file2data1[ ]+\+ 0 +0+124 +0+5e00000001 R_SH_DIR32[ ]+0+74 +file2text2[ ]+\+ 0 +0+128 +0+8000000001 R_SH_DIR32[ ]+0+10 +file1data3[ ]+\+ 0 +0+12c +0+7700000001 R_SH_DIR32[ ]+0+14 +file1text4[ ]+\+ 0 +0+130 +0+7400000001 R_SH_DIR32[ ]+0+ +unresolved2[ ]+\+ 0 +0+134 +0+7b00000001 R_SH_DIR32[ ]+0+ +unresolved4[ ]+\+ 0 +0+138 +0+4800000001 R_SH_DIR32[ ]+0+ +oa1[ ]+\+ 0 +0+13c +0+1700000001 R_SH_DIR32[ ]+0+ +oa2[ ]+\+ 0 +0+140 +0+6d00000001 R_SH_DIR32[ ]+0+ +oa3[ ]+\+ 0 +0+144 +0+1c00000001 R_SH_DIR32[ ]+0+ +oa13[ ]+\+ 0 +0+148 +0+1900000001 R_SH_DIR32[ ]+0+5c +oc13[ ]+\+ 0 +0+14c +0+1000000001 R_SH_DIR32[ ]+0+ +oa4[ ]+\+ 0 +0+150 +0+1b00000001 R_SH_DIR32[ ]+0+ +oa12[ ]+\+ 0 +0+154 +0+4500000001 R_SH_DIR32[ ]+0+ +oa13[ ]+\+ 0 +0+158 +0+3800000001 R_SH_DIR32[ ]+0+ +oa23[ ]+\+ 0 +0+15c +0+3f00000001 R_SH_DIR32[ ]+0+ +oa23[ ]+\+ 0 +0+160 +0+5700000001 R_SH_DIR32[ ]+0+ +oa123[ ]+\+ 0 +0+164 +0+1600000001 R_SH_DIR32[ ]+0+50 +oc3[ ]+\+ 0 +0+168 +0+5000000001 R_SH_DIR32[ ]+0+ +oa123[ ]+\+ 0 +0+16c +0+1400000001 R_SH_DIR32[ ]+0+ +ob1[ ]+\+ 0 +0+170 +0+2200000001 R_SH_DIR32[ ]+0+ +ob2[ ]+\+ 0 +0+174 +0+5f00000001 R_SH_DIR32[ ]+0+ +ob3[ ]+\+ 0 +0+178 +0+1300000001 R_SH_DIR32[ ]+0+ +ob4[ ]+\+ 0 +0+17c +0+8400000001 R_SH_DIR32[ ]+0+ +oa3[ ]+\+ 0 +0+180 +0+2b00000001 R_SH_DIR32[ ]+0+60 +oc23[ ]+\+ 0 +0+184 +0+0a00000001 R_SH_DIR32[ ]+0+64 +oc123[ ]+\+ 0 +0+188 +0+6000000001 R_SH_DIR32[ ]+0+ +ob12[ ]+\+ 0 +0+18c +0+5500000001 R_SH_DIR32[ ]+0+ +ob13[ ]+\+ 0 +0+190 +0+4d00000001 R_SH_DIR32[ ]+0+d0 +ob13[ ]+\+ 0 +0+194 +0+8200000001 R_SH_DIR32[ ]+0+d4 +ob23[ ]+\+ 0 +0+198 +0+5800000001 R_SH_DIR32[ ]+0+ +ob23[ ]+\+ 0 +0+19c +0+6600000001 R_SH_DIR32[ ]+0+ +ob123[ ]+\+ 0 +0+1a0 +0+5900000001 R_SH_DIR32[ ]+0+ +oc1[ ]+\+ 0 +0+1a4 +0+1100000001 R_SH_DIR32[ ]+0+c4 +ob3[ ]+\+ 0 +0+1a8 +0+4400000001 R_SH_DIR32[ ]+0+d8 +ob123[ ]+\+ 0 +0+1ac +0+0900000001 R_SH_DIR32[ ]+0+ +oc2[ ]+\+ 0 +0+1b0 +0+3700000001 R_SH_DIR32[ ]+0+ +oc3[ ]+\+ 0 +0+1b4 +0+5300000001 R_SH_DIR32[ ]+0+ +oc4[ ]+\+ 0 +0+1b8 +0+5a00000001 R_SH_DIR32[ ]+0+ +oc12[ ]+\+ 0 +0+1bc +0+5c00000001 R_SH_DIR32[ ]+0+ +oc13[ ]+\+ 0 +0+1c0 +0+2a00000001 R_SH_DIR32[ ]+0+ +oc23[ ]+\+ 0 +0+1c4 +0+3300000001 R_SH_DIR32[ ]+0+ +oc123[ ]+\+ 0 +0+1c8 +0+7a00000001 R_SH_DIR32[ ]+0+ +a1[ ]+\+ 0 +0+1cc +0+1a00000001 R_SH_DIR32[ ]+0+a0 +c2[ ]+\+ 0 +0+1d0 +0+6f00000001 R_SH_DIR32[ ]+0+34 +b23[ ]+\+ 0 +0+1d4 +0+3d00000001 R_SH_DIR32[ ]+0+ +b1[ ]+\+ 0 +0+1d8 +0+8300000001 R_SH_DIR32[ ]+0+ +c1[ ]+\+ 0 +0+1dc +0+6900000001 R_SH_DIR32[ ]+0+ +a12[ ]+\+ 0 +0+1e0 +0+5600000001 R_SH_DIR32[ ]+0+ +a2[ ]+\+ 0 +0+1e4 +0+0d00000001 R_SH_DIR32[ ]+0+20 +b2[ ]+\+ 0 +0+1e8 +0+5200000001 R_SH_DIR32[ ]+0+ +b12[ ]+\+ 0 +0+1ec +0+2000000001 R_SH_DIR32[ ]+0+ +c12[ ]+\+ 0 +0+1f0 +0+5400000001 R_SH_DIR32[ ]+0+44 +b123[ ]+\+ 0 +0+1f4 +0+7e00000001 R_SH_DIR32[ ]+0+b8 +c123[ ]+\+ 0 +0+1f8 +0+1500000001 R_SH_DIR32[ ]+0+ +a13[ ]+\+ 0 +0+1fc +0+2900000001 R_SH_DIR32[ ]+0+ +b13[ ]+\+ 0 +0+200 +0+3900000001 R_SH_DIR32[ ]+0+b4 +c23[ ]+\+ 0 +0+204 +0+3e00000001 R_SH_DIR32[ ]+0+ +a123[ ]+\+ 0 +0+208 +0+3100000001 R_SH_DIR32[ ]+0+ +c13[ ]+\+ 0 +0+20c +0+6200000001 R_SH_DIR32[ ]+0+ +a123[ ]+\+ 0 +0+210 +0+6e00000001 R_SH_DIR32[ ]+0+ac +c12[ ]+\+ 0 +0+214 +0+7000000001 R_SH_DIR32[ ]+0+ +a23[ ]+\+ 0 +0+218 +0+0c00000001 R_SH_DIR32[ ]+0+ +b123[ ]+\+ 0 +0+21c +0+4000000001 R_SH_DIR32[ ]+0+ +a12[ ]+\+ 0 +0+220 +0+7300000001 R_SH_DIR32[ ]+0+2c +b12[ ]+\+ 0 +0+224 +0+3a00000001 R_SH_DIR32[ ]+0+ +c123[ ]+\+ 0 + +Symbol table '\.symtab' contains 134 entries: + +Num: +Value +Size +Type +Bind +Vis +Ndx +Name + +0: 0+0000 +0 +NOTYPE +LOCAL +DEFAULT +UND + +1: 0+0000 +0 +SECTION +LOCAL +DEFAULT +1 + +2: 0+0000 +0 +SECTION +LOCAL +DEFAULT +3 + +3: 0+0000 +0 +SECTION +LOCAL +DEFAULT +5 + +4: 0+0000 +0 +SECTION +LOCAL +DEFAULT +6 + +5: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND unresolved5 + +6: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND unresolved9 + +7: 0+000c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file1text2 + +8: 0+006c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file2text1 + +9: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc2 + +10: 0+0064 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc123 + +11: 0+0004 +0 +NOTYPE +GLOBAL +DEFAULT +3 file1data1 + +12: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b123 + +13: 0+0020 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b2 + +14: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c4 + +15: 0+012c +0 +NOTYPE +GLOBAL +DEFAULT +3 file2data4 + +16: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa4 + +17: 0+00c4 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 ob3 + +18: 0+0058 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc12 + +19: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob4 + +20: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob1 + +21: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a13 + +22: 0+0050 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc3 + +23: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa2 + +24: 0+00a8 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c4 + +25: 0+005c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc13 + +26: 0+00a0 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c2 + +27: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa12 + +28: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND oa13 + +29: 0+00c8 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 ob4 + +30: 0+001c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b1 + +31: 0+0018 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file1text5 + +32: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c12 + +33: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND file1text5 + +34: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob2 + +35: 0+0010 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file1text3 + +36: 0+0124 +0 +NOTYPE +GLOBAL +DEFAULT +3 file2data2 + +37: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a4 + +38: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a2 + +39: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND unresolved1 + +40: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND file1data3 + +41: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b13 + +42: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc23 + +43: 0+0060 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc23 + +44: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c2 + +45: 0+000c +0 +NOTYPE +GLOBAL +DEFAULT +3 file1data2 + +46: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b3 + +47: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND a3 + +48: 0+0078 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file2text3 + +49: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c13 + +50: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND unresolved9 + +51: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc123 + +52: 0+0028 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b4 + +53: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND file2data4 + +54: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c23 + +55: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc3 + +56: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa23 + +57: 0+00b4 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c23 + +58: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c123 + +59: 0+0030 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b13 + +60: 0+00b0 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c13 + +61: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b1 + +62: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND a123 + +63: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND oa23 + +64: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND a12 + +65: 0+00bc +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 ob1 + +66: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND unresolved7 + +67: 0+0068 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 start2 + +68: 0+00d8 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 ob123 + +69: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa13 + +70: 0+009c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c1 + +71: 0+0054 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc4 + +72: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa1 + +73: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND oa12 + +74: 0+00cc +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 ob12 + +75: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND file1data2 + +76: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND unresolved1 + +77: 0+00d0 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 ob13 + +78: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a3 + +79: 0+0018 +0 +NOTYPE +GLOBAL +DEFAULT +3 file1data5 + +80: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa123 + +81: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND unresolved6 + +82: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b12 + +83: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc4 + +84: 0+0044 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b123 + +85: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob13 + +86: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND a2 + +87: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND oa123 + +88: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob23 + +89: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc1 + +90: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc12 + +91: 0+0004 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file1text1 + +92: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oc13 + +93: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND file1text1 + +94: 0+0074 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file2text2 + +95: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob3 + +96: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob12 + +97: 0+00c0 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 ob2 + +98: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a123 + +99: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c3 + +100: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND unresolved3 + +101: 0+0024 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b3 + +102: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND ob123 + +103: 0+007c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file2text4 + +104: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b4 + +105: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a12 + +106: 0+00a4 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c3 + +107: 0+0048 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc1 + +108: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND unresolved6 + +109: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND oa3 + +110: 0+00ac +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c12 + +111: 0+0034 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b23 + +112: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND a23 + +113: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b2 + +114: 0+004c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 oc2 + +115: 0+002c +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 b12 + +116: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND unresolved2 + +117: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 start + +118: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a23 + +119: 0+0014 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 file1text4 + +120: 0+0128 +0 +NOTYPE +GLOBAL +DEFAULT +3 file2data3 + +121: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND oa2 + +122: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND a1 + +123: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND unresolved4 + +124: 0+011c +0 +NOTYPE +GLOBAL +DEFAULT +3 file2data1 + +125: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND b23 + +126: 0+00b8 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4\] +1 c123 + +127: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND a13 + +128: 0+0010 +0 +NOTYPE +GLOBAL +DEFAULT +3 file1data3 + +129: 0+0014 +0 +NOTYPE +GLOBAL +DEFAULT +3 file1data4 + +130: 0+00d4 +0 +NOTYPE +GLOBAL +DEFAULT +\[<other>: 4] +1 ob23 + +131: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND c1 + +132: 0+0000 +0 +NOTYPE +GLOBAL +DEFAULT +UND oa3 + +133: 0+0000 +0 +<processor specific>: 13 +GLOBAL +DEFAULT +UND unresolved8 + +Hex dump of section '\.text': +.* + 0x00000000 6ff0fff0 6ff0fff0 cc0000a0 cc000140 .* + 0x00000010 cc000140 cc000140 cc000280 cc0001e0 .* + 0x00000020 cc0000a0 cc0000a0 cc000280 cc000140 .* + 0x00000030 cc000140 cc000320 c8000320 c8000320 .* + 0x00000040 c8000320 cc0003c0 cc0003c0 6ff0fff0 .* + 0x00000050 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00000060 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x00000070 cc0000a0 cc000140 cc000140 cc000140 .* + 0x00000080 cc0001e0 cc0001e0 cc000320 cc000320 .* + 0x00000090 cc000280 cc000280 cc000280 6ff0fff0 .* + 0x000000a0 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x000000b0 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x000000c0 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 0x000000d0 6ff0fff0 6ff0fff0 6ff0fff0 .* + +Hex dump of section '\.data': +.* + 0x00000000 00000000 00000000 00000008 00000000 .* + 0x00000010 00000000 00000000 00000000 00000000 .* + 0x00000020 00000028 00000000 00000000 00000000 .* + 0x00000030 00000000 00000000 00000000 00000000 .* + 0x00000040 00000000 00000000 00000000 00000000 .* + 0x00000050 00000000 00000000 00000000 00000000 .* + 0x00000060 00000000 00000000 00000000 00000000 .* + 0x00000070 00000000 00000000 00000000 00000000 .* + 0x00000080 00000000 00000000 00000000 00000000 .* + 0x00000090 00000000 00000000 00000000 00000000 .* + 0x000000a0 00000000 00000000 00000000 00000000 .* + 0x000000b0 00000000 00000000 00000000 00000000 .* + 0x000000c0 00000000 00000000 00000000 00000000 .* + 0x000000d0 00000000 00000000 00000000 00000000 .* + 0x000000e0 00000000 00000000 00000000 00000000 .* + 0x000000f0 00000000 00000000 00000000 00000000 .* + 0x00000100 00000000 00000000 00000000 00000000 .* + 0x00000110 00000000 00000000 00000000 00000000 .* + 0x00000120 00000000 00000000 00000000 00000000 .* + 0x00000130 00000000 00000000 00000000 00000000 .* + 0x00000140 00000000 00000000 00000000 00000000 .* + 0x00000150 00000000 00000000 00000000 00000000 .* + 0x00000160 00000000 00000000 00000000 00000000 .* + 0x00000170 00000000 00000000 00000000 00000000 .* + 0x00000180 00000000 00000000 00000000 00000000 .* + 0x00000190 00000000 00000000 00000000 00000000 .* + 0x000001a0 00000000 00000000 00000000 00000000 .* + 0x000001b0 00000000 00000000 00000000 00000000 .* + 0x000001c0 00000000 00000000 00000000 00000000 .* + 0x000001d0 00000000 00000000 00000000 00000000 .* + 0x000001e0 00000000 00000000 00000000 00000000 .* + 0x000001f0 00000000 00000000 00000000 00000000 .* + 0x00000200 00000000 00000000 00000000 00000000 .* + 0x00000210 00000000 00000000 00000000 00000000 .* + 0x00000220 00000000 00000000 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/relfail.exp b/binutils-2.21/ld/testsuite/ld-sh/sh64/relfail.exp new file mode 100644 index 0000000..fbdf80a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/relfail.exp @@ -0,0 +1,219 @@ +# Expect script for ld-sh tests +# Copyright (C) 2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. +# + +# Test SH reloc failures - that is, cases that ld must not allow. + +if ![istarget sh64-*-*] { + return +} + +if [istarget sh64-*-linux*] { + set emul32 "shlelf32_linux" + set oformat32 "elf32-sh64-linux" + set startsym "_start" + set doabi64 0 +} elseif { [istarget sh64*-*-netbsd*] || [istarget sh5*-*-netbsd*] } then { + set emul32 "shelf32_nbsd" + set oformat32 "elf32-sh64-nbsd" + set startsym "__start" + set doabi64 1 + set emul64 "shelf64_nbsd" + set oformat64 "elf64-sh64-nbsd" +} else { + set emul32 "shelf32" + set oformat32 "elf32-sh64" + set startsym "start" + set doabi64 1 + set emul64 "shelf64" + set oformat64 "elf64-sh64" +} + +# opcode, asflags, ldflags, expected or "" for fail +# opcode blank means rebuild relfail.o and set default as/ld options + +set sh64abi32relfailtests { + + { "" "-isa=shcompact -abi=32" "-m $emul32 -Ttext 0x1000 --oformat $oformat32" "" } + { "mov.l lab,r0;.align 3;lab:nop" "" "" "mov.l 1008" } + { "mov.l to0,r0" "" "" "mov.l 1010" } + { "mov.l to1,r0" "" "" "" } + { "mov.l to2,r0" "" "" "" } + { "mov.l to3,r0" "" "" "" } + { "mov.l to4,r0" "" "" "mov.l 1014" } + + { "" "-isa=shmedia -abi=32 -no-expand" "-m $emul32 -Ttext 0x1000 --oformat $oformat32" "" } + { "pta lab,tr0;.align 3;lab:nop" "" "" "pta.*1008" } + + { "ld.q r0,datalabel to0 - 0x1000,r0" "" "" "ld.q.*,16," } + { "ld.q r0,datalabel to1 - 0x1000,r0" "" "" "" } + { "ld.q r0,datalabel to2 - 0x1000,r0" "" "" "" } + { "ld.q r0,datalabel to3 - 0x1000,r0" "" "" "" } + { "ld.q r0,datalabel to4 - 0x1000,r0" "" "" "" } + + { "ld.l r0,datalabel to0 - 0x1000,r0" "" "" "ld.l.*,16," } + { "ld.l r0,datalabel to1 - 0x1000,r0" "" "" "" } + { "ld.l r0,datalabel to2 - 0x1000,r0" "" "" "" } + { "ld.l r0,datalabel to3 - 0x1000,r0" "" "" "" } + { "ld.l r0,datalabel to4 - 0x1000,r0" "" "" "ld.l.*,20," } + + { "ld.w r0,datalabel to0 - 0x1000,r0" "" "" "ld.w.*,16," } + { "ld.w r0,datalabel to1 - 0x1000,r0" "" "" "" } + { "ld.w r0,datalabel to2 - 0x1000,r0" "" "" "ld.w.*,18," } + { "ld.w r0,datalabel to3 - 0x1000,r0" "" "" "" } + { "ld.w r0,datalabel to4 - 0x1000,r0" "" "" "ld.w.*,20," } + +} + +set sh64abi64relfailtests { + + { "" "-isa=shmedia -abi=64 -no-expand" "-m $emul64 -Ttext 0x1000 --oformat $oformat64" "" } + { "pta lab,tr0;.align 3;lab:nop" "" "" "pta.*1008" } + { "pta datalabel to0,tr0" "" "" "pta.*1010" } + { "pta datalabel to1,tr0" "" "" "pta.*1011" } + { "pta datalabel to2,tr0" "" "" "" } + { "pta datalabel to3,tr0" "" "" "" } + { "pta datalabel to4,tr0" "" "" "pta.*1014" } + + { "ld.q r0,datalabel to0 - 0x1000,r0" "" "" "ld.q.*,16," } + { "ld.q r0,datalabel to1 - 0x1000,r0" "" "" "" } + { "ld.q r0,datalabel to2 - 0x1000,r0" "" "" "" } + { "ld.q r0,datalabel to3 - 0x1000,r0" "" "" "" } + { "ld.q r0,datalabel to4 - 0x1000,r0" "" "" "" } + + { "ld.l r0,datalabel to0 - 0x1000,r0" "" "" "ld.l.*,16," } + { "ld.l r0,datalabel to1 - 0x1000,r0" "" "" "" } + { "ld.l r0,datalabel to2 - 0x1000,r0" "" "" "" } + { "ld.l r0,datalabel to3 - 0x1000,r0" "" "" "" } + { "ld.l r0,datalabel to4 - 0x1000,r0" "" "" "ld.l.*,20," } + + { "ld.w r0,datalabel to0 - 0x1000,r0" "" "" "ld.w.*,16," } + { "ld.w r0,datalabel to1 - 0x1000,r0" "" "" "" } + { "ld.w r0,datalabel to2 - 0x1000,r0" "" "" "ld.w.*,18," } + { "ld.w r0,datalabel to3 - 0x1000,r0" "" "" "" } + { "ld.w r0,datalabel to4 - 0x1000,r0" "" "" "ld.w.*,20," } + +} + +proc run_sh64relfailtests {sh64relfailtests} { + global ld + global as + global nm + global objdump + global readelf + global srcdir + global subdir + global emul32 + global emul64 + global oformat32 + global oformat64 + global startsym + + set testindex 0 + set is_unresolved 0 + + foreach testentry $sh64relfailtests { + set opcode [lindex $testentry 0] + set as_options [lindex $testentry 1] + set ld_options [subst [lindex $testentry 2]] + set expect_fail [lindex $testentry 3] + + set testname "SH64 relfail $opcode $as_options $ld_options" + + set objfiles {} + + incr testindex + + if {$opcode == ""} { + set def_as_options $as_options + set def_ld_options $ld_options + set is_unresolved 0 + set baseobj "tmpdir/relfail-$testindex.o" + if ![ld_assemble $as "$as_options $srcdir/$subdir/relfail.s" $baseobj] { + set is_unresolved 1 + } + continue + } + + if {$as_options == ""} { + set as_options $def_as_options + } + if {$ld_options == ""} { + set ld_options $def_ld_options + } + + if { $is_unresolved } { + unresolved $testname + continue + } + + set asm [open "tmpdir/relfail-$testindex.s" "w"] + puts $asm " .text" + puts $asm " .global $startsym" + puts $asm "$startsym:" + puts $asm " $opcode" + close $asm + + if ![ld_assemble $as "$as_options tmpdir/relfail-$testindex.s" "tmpdir/relfail-$testindex.o"] { + unresolved $testname + continue + } + + set binfile "tmpdir/relfail-$testindex.x" + + file delete $binfile + set objects "tmpdir/relfail-$testindex.o $baseobj" + set result [ld_simple_link $ld $binfile "--no-warn-mismatch $ld_options $objects"] + + set exists [file exists $binfile] + if {$exists && $expect_fail == ""} { + verbose "$testname: file $binfile exists when it shouldn't" 1 + catch "exec $objdump -d $binfile" objdump_output + verbose $objdump_output 1 + fail "$testname (file exists)" + continue + } + if {!$exists && $expect_fail != ""} { + verbose "$testname: file $binfile doesn't exist when it should" 1 + fail "$testname (file missing)" + continue + } + + if {$exists} { + catch "exec $objdump -d $binfile" objdump_output + regsub -all {[ ][ ]*} $objdump_output " " objdump_short + if ![regexp $expect_fail $objdump_short junk] { + verbose $objdump_output 1 + fail "$testname (incorrect reloc)" + continue + } + } + + file delete "tmpdir/relfail-$testindex.s" + file delete "tmpdir/relfail-$testindex.o" + file delete $binfile + pass $testname + } +} + +run_sh64relfailtests $sh64abi32relfailtests +if {$doabi64} { + run_sh64relfailtests $sh64abi64relfailtests +} diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/relfail.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/relfail.s new file mode 100644 index 0000000..5f5d171 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/relfail.s @@ -0,0 +1,36 @@ + .text + .align 4 + .global to0 +to0: + .byte 0 + .global to1 +to1: + .byte 0 + .global to2 +to2: + .byte 0 + .global to3 +to3: + .byte 0 + .global to4 +to4: + .byte 0 + .byte 0 + + .data + .align 4 + .global do0 +do0: + .byte 0 + .global do1 +do1: + .byte 0 + .global do2 +do2: + .byte 0 + .global do3 +do3: + .byte 0 + .global do4 +do4: + .byte 0 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/sh64-1.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/sh64-1.s new file mode 100644 index 0000000..3e488db --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/sh64-1.s @@ -0,0 +1,20 @@ +! Test that all common kinds of relocs get right for simple use. +! Auxiliary part. + .text + .mode SHmedia + .global foo + .global bar +foo: + pt/l xyzzy,tr3 +bar: + nop + + .data + .global baz +baz: + .long foobar + .long bar + .global baz2 +baz2: + .long xyzzy +foobar: .long baz diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/sh64-2.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/sh64-2.s new file mode 100644 index 0000000..8ca24c0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/sh64-2.s @@ -0,0 +1,27 @@ +! Test that all common kinds of relocs get right for simple cases. +! Main part. + .text + .global start + .mode SHmedia +start: + movi foo,r33 + movi bar,r21 + pt/l bar,tr3 + movi foobar,r43 + movi baz2,r53 + movi foobar2,r4 + pta xyzzy,tr5 + pt/u plugh,tr1 + + .data + .global foobar +foobar: .long baz +foobar2: + .long bar + + .section .text.other,"ax" + .global xyzzy +xyzzy: + nop +plugh: + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/sh64.exp b/binutils-2.21/ld/testsuite/ld-sh/sh64/sh64.exp new file mode 100644 index 0000000..af6cbfe --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/sh64.exp @@ -0,0 +1,137 @@ +# Expect script for ld-sh tests +# Copyright (C) 2000, 2001, 2002, 2003, 2005, 2007 Free Software Foundation +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. +# + +# Test SH linking; all types of relocs. This tests the assembler and +# tools like objdump as well as the linker. + +if ![istarget sh64-*-*] { + return +} + +if [istarget sh64*-*-linux*] { + return +} + +if { [istarget sh64*-*-netbsd*] || [istarget sh5*-*-netbsd*] } then { + return +} + +# List contains test-items with 3 items followed by 2 lists: +# 0:name 1:ld options 2:assembler options +# 3:filenames of assembler files 4: action and options. 5: name of output file + +# Actions: +# objdump: Apply objdump options on result. Compare with regex (last arg). +# nm: Apply nm options on result. Compare with regex (last arg). +# readelf: Apply readelf options on result. Compare with regex (last arg). + +# Note that the contents dump is the same for "inter-file datalabel +# references, 64-bit ABI" as for 32-bit ABI and ELF so we re-use it. + +set sh64tests { + {"SH64 linking, 64-bit ABI" "-mshelf64" + "--abi=64" {sh64-1.s sh64-2.s} + {{objdump -sr abi64.sd} {objdump -x abi64.xd}} "abi64.bin" } + {"SH64 linking, 64-bit ABI, -no-expand" "-mshelf64" + "--abi=64 -no-expand" {sh64-1.s sh64-2.s} + {{objdump -sr abixx-noexp.sd}} "abi64-noexp.bin" } + {"SH64 linking, 32-bit ABI" "-mshelf32" + "--abi=32" {sh64-1.s sh64-2.s} + {{objdump -sr abi32.sd} {objdump -x abi32.xd}} "abi32.bin" } + {"SH64 linking, 32-bit ABI, -no-expand" "-mshelf32" + "--abi=32 -no-expand" {sh64-1.s sh64-2.s} + {{objdump -sr abixx-noexp.sd}} "abi32-noexp.bin" } + {"SH64 linking, single multi-ISA object" "-mshelf32" + "--abi=32" {shmix-1.s} + {{objdump -sr mix1.sd} {objdump -x mix1.xd}} "mix1.bin" } + {"SH64 linking, single multi-ISA object, -no-expand" "-mshelf32" + "--abi=32 -no-expand" {shmix-1.s} + {{objdump -sr mix1-noexp.sd}} "mix1-noexp.bin" } + {"SH64 linking, two different-ISA objects" "-mshelf32" + "--abi=32" {shmix-2.s shmix-3.s} + {{objdump -sr mix2.sd} {objdump -x mix2.xd}} "mix2.bin" } + {"SH64 linking, two different-ISA objects, -no-expand" "-mshelf32" + "--abi=32 -no-expand" {shmix-2.s shmix-3.s} + {{objdump -sr mix2-noexp.sd}} "mix2-noexp.bin" } + {"SH64 linking, single SHcompact" "-mshelf32" + "--isa=SHcompact" {shcmp-1.s} + {{objdump -sr cmpct1.sd} {objdump -x cmpct1.xd}} "cmpct1.bin" } + {"SH64 inter-file datalabel references, 64-bit ABI" "-mshelf64" + "--abi=64" {shdl-1.s shdl-2.s} + {{objdump -sr shdl64.sd} {objdump -x shdl64.xd}} "shdl64.bin" } + {"SH64 inter-file datalabel references, 32-bit ABI" "-mshelf32" + "--abi=32" {shdl-1.s shdl-2.s} + {{objdump -sr shdl64.sd} {objdump -x shdl32.xd}} "shdl32.bin" } + {"SH64 inter-file datalabel references and gc-sections, 32-bit ABI" "-mshelf32 --gc-sections" + "--abi=32" {dlsection-1.s } + {{objdump -sr dlsection.sd}} "dlsection32.bin" } + {"SH64 inter-file datalabel references and gc-sections, 64-bit ABI" "-mshelf64 --gc-sections" + "--abi=64" {dlsection-1.s } + {{objdump -sr dlsection.sd}} "dlsection64.bin" } + {"SH64 simple partial linking, 32-bit ABI" "-mshelf32 -r" + "--abi=32" {rel-1.s rel-2.s} + {{objdump -sx rel32.xd}} "rel32.bin" } + {"SH64 simple partial linking, 64-bit ABI" "-mshelf64 -r" + "--abi=64" {rel-1.s rel-2.s} + {{objdump -sx rel64.xd}} "rel64.bin" } + {"SH64 partial linking with datalabel references, 32-bit ABI" "-mshelf32 -r" + "--abi=32" {reldl-1.s reldl-2.s} + {{readelf {-s -r -x 1 -x 3} reldl32.rd}} "reldl32.bin" } + {"SH64 partial linking with datalabel references, 64-bit ABI" "-mshelf64 -r" + "--abi=64" {reldl-1.s reldl-2.s} + {{readelf {-s -r -x 1 -x 3} reldl64.rd}} "reldl64.bin" } + {"Handling SH64 assembler-generated .cranges" "-mshelf32" + "--abi=32" {crange-2a.s crange-1.s} + {{readelf {-S -s -r -x 1 -x 2 -x 4} crange1.rd}} "crange1.bin" } + {"Handling SH64 assembler-generated .cranges, partial linking" "-mshelf32 -r" + "--abi=32" {crange-2a.s} + {{readelf {-S -s -r -x 2 -x 6} crangerel1.rd}} "crangerel1.bin" } + {"Mixing SH64 assembler-generated with linker-generated .cranges" "-mshelf32" + "--abi=32" {crange-2a.s crange-2b.s crange-1.s} + {{readelf {-S -s -r -x 2 -x 4} crange2.rd}} "crange2.bin" } + {"Mixing SH64 assembler-generated with linker-generated .cranges, partial linking" + "-mshelf32 -r" + "--abi=32" {crange-2a.s crange-2c.s crange-2d.s crange-2e.s} + {{readelf {-S -s -r -x 2 -x 6} crangerel2.rd}} "crangerel2.bin" } + {"Merge and use of SH64 .cranges, some not originally in order" "-mshelf32" + "--abi=32" + {crange-2e.s crange-2f.s crange-2g.s crange-2a.s crange-2d.s crange-2i.s + crange-2h.s crange-1.s} + {{readelf {-S -s -x 2 -x 4} crange3.rd} {objdump -d crange3.dd}} "crange3.bin" } + {"Sorted SH64 .cranges, entry at SHcompact code" "-mshelf32 --entry diversion" + "--abi=32" + {crange-2e.s crange-2f.s crange-2g.s crange-2a.s crange-2d.s crange-2i.s + crange-2h.s crange-1.s} + {{readelf {-h -S -s -x 2 -x 4} crange3-cmpct.rd}} "crange3-cmpct.bin" } + {"Sorted SH64 .cranges, entry at SHmedia code" "-mshelf32 --entry diversion2" + "--abi=32" + {crange-2e.s crange-2f.s crange-2g.s crange-2a.s crange-2d.s crange-2i.s + crange-2h.s crange-1.s} + {{readelf {-h -S -s -x 2 -x 4} crange3-media.rd}} "crange3-media.bin" } + {"SH64 Big Endianness" "-mshelf64 -Tendian.ld" + "--abi=64" {endian.s} + {{objdump -s endian.sbd} {objdump -d endian.dbd}} "endianb.bin" } + {"SH64 Little Endianness" "-mshlelf64 -Tendian.ld" + "--abi=64 --little" {endian.s} + {{objdump -s endian.sld} {objdump -d endian.dld}} "endinanl.bin" } +} + +run_ld_link_tests $sh64tests diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/shcmp-1.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/shcmp-1.s new file mode 100644 index 0000000..f915af4 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/shcmp-1.s @@ -0,0 +1,15 @@ +! A single SHcompact file, that should link correctly. + .text + .global start +start: + mova next,r0 + nop +next: + nop + mov #42,r10 + + .section .rodata + .long start +here: + .long here + .long next diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/shdl-1.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/shdl-1.s new file mode 100644 index 0000000..0f2803c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/shdl-1.s @@ -0,0 +1,359 @@ +! Test inter-file DataLabel support. +! +! We need to test symbols that are: +! * Global, defined in this file, with/without/both-with-without datalabel +! references. +! * The above in combinations where the reference is/is not from within +! the same section. The implementation is currently indifferent to that +! fact, but it seems likely to be something that can change. +! * Extern with/without/both-with-without datalabel-qualified references. +! * The above with reference from same *and* other file. +! * The above in combinations for where the symbol is/is not a +! STO_SH5_ISA32-marked symbol. + +! There will be omissions and overlap in combinations. Add spotted +! omissions with complementary tests in other files. + + .text + .mode SHmedia + +! For good measure, we start with a nop to get a non-zero offset within +! the .text section. + + .global start +start: + nop + +! Referenced from the same file, same section, is ISA32, only referenced +! with datalabel qualifier. + .global foo +foo: + nop + movi (datalabel foo + 8) & 65535,r30 + +! Referenced from same file, same section, both with and without +! datalabel qualifier, is ISA32. + .global fooboth +fooboth: + nop + movi (datalabel fooboth + 16) & 65535,r40 + movi (fooboth + 12) & 65535,r40 + +! Same as above, but in different order. + .global fooboth2 +fooboth2: + nop + movi (fooboth2 + 12) & 65535,r40 + movi (datalabel fooboth2 + 16) & 65535,r40 + +! Referenced from this file and another, same section, is ISA32. + .global foowithout +foowithout: + nop + movi (foowithout + 24) & 65535,r30 + +! Same as above, different section than definition. + + .global foo_other +foo_other: + nop + .global foo_otherboth +foo_otherboth: + nop + .global foo_otherboth2 +foo_otherboth2: + nop + .global foo_otherwithout +foo_otherwithout: + nop + + .section .rodata + .long datalabel foo_other + 4 + .long datalabel foo_otherboth + 40 + .long foo_otherboth + 24 + .long foo_otherboth2 + 24 + .long datalabel foo_otherboth2 + 40 + .long foo_otherwithout + + .text + +! Same as above, mixing references from same and other section. + .global foo_mix +foo_mix: + nop + movi (datalabel foo_mix + 8) & 65535,r30 + .global foo_mix2 +foo_mix2: + nop + movi (foo_mix2 + 8) & 65535,r30 + .global foo_mixboth +foo_mixboth: + nop + movi (datalabel foo_mixboth + 80) & 65535,r30 + movi (foo_mixboth + 80) & 65535,r30 + .global foo_mixboth2 +foo_mixboth2: + nop + movi (foo_mixboth2 + 64) & 65535,r30 + movi (datalabel foo_mixboth2 + 64) & 65535,r30 + .global foo_mixwithout +foo_mixwithout: + nop + movi (foo_mixwithout + 42) & 65535,r30 + .global foo_mixwithout2 +foo_mixwithout2: + nop + movi (foo_mixwithout2 + 24) & 65535,r30 + + .section .rodata + .long foo_mix + 4 + .long datalabel foo_mix2 + 48 + .long datalabel foo_mixboth + 400 + .long foo_mixboth + 420 + .long foo_mixboth2 + 248 + .long datalabel foo_mixboth2 + 240 + .long foo_mixwithout + +! Same as above, referencing symbol in other file (reference only from +! this to other file). + + .text + nop + movi (datalabel bar + 8) & 65535,r30 + + movi (datalabel barboth + 16) & 65535,r40 + movi (barboth + 12) & 65535,r40 + + movi (barboth2 + 12) & 65535,r40 + movi (datalabel barboth2 + 16) & 65535,r40 + + movi (barwithout + 24) & 65535,r30 + + .section .rodata + .long datalabel bar_other + 4 + .long datalabel bar_otherboth + 40 + .long bar_otherboth + 24 + .long bar_otherboth2 + 24 + .long datalabel bar_otherboth2 + 40 + .long bar_otherwithout + + .text + movi (datalabel bar_mix + 8) & 65535,r30 + movi (bar_mix2 + 8) & 65535,r30 + movi (datalabel bar_mixboth + 80) & 65535,r30 + movi (bar_mixboth + 80) & 65535,r30 + movi (bar_mixboth2 + 64) & 65535,r30 + movi (datalabel bar_mixboth2 + 64) & 65535,r30 + movi (bar_mixwithout + 42) & 65535,r30 + movi (bar_mixwithout2 + 24) & 65535,r30 + + .section .rodata + .long bar_mix + 4 + .long datalabel bar_mix2 + 48 + .long datalabel bar_mixboth + 400 + .long bar_mixboth + 420 + .long bar_mixboth2 + 248 + .long datalabel bar_mixboth2 + 240 + .long bar_mixwithout + +! Same as above, referencing symbol in other file *and* within that file. + + .text + movi (datalabel baz + 8) & 65535,r30 + + movi (datalabel bazboth + 16) & 65535,r40 + movi (bazboth + 12) & 65535,r40 + + movi (bazboth2 + 12) & 65535,r40 + movi (datalabel bazboth2 + 16) & 65535,r40 + + movi (bazwithout + 24) & 65535,r30 + + .section .rodata + .long datalabel baz_other + 4 + .long datalabel baz_otherboth + 40 + .long baz_otherboth + 24 + .long baz_otherboth2 + 24 + .long datalabel baz_otherboth2 + 40 + .long baz_otherwithout + + .text + movi (datalabel baz_mix + 8) & 65535,r30 + movi (baz_mix2 + 8) & 65535,r30 + movi (datalabel baz_mixboth + 80) & 65535,r30 + movi (baz_mixboth + 80) & 65535,r30 + movi (baz_mixboth2 + 64) & 65535,r30 + movi (datalabel baz_mixboth2 + 64) & 65535,r30 + movi (baz_mixwithout + 42) & 65535,r30 + movi (baz_mixwithout2 + 24) & 65535,r30 + + .section .rodata + .long baz_mix + 4 + .long datalabel baz_mix2 + 48 + .long datalabel baz_mixboth + 400 + .long baz_mixboth + 420 + .long baz_mixboth2 + 248 + .long datalabel baz_mixboth2 + 240 + .long baz_mixwithout + +! Same as all of the above, but where the symbol is not an ISA32 one. + + .data + .global dfoo +dfoo: + .long 0 + .long (datalabel dfoo + 8) + + .global dfooboth +dfooboth: + .long 0 + .long (datalabel dfooboth + 16) + .long (dfooboth + 12) + + .global dfooboth2 +dfooboth2: + .long 0 + .long (dfooboth2 + 12) + .long (datalabel dfooboth2 + 16) + + .global dfoowithout +dfoowithout: + .long 0 + .long (dfoowithout + 24) + + .global dfoo_other +dfoo_other: + .long 0 + .global dfoo_otherboth +dfoo_otherboth: + .long 0 + .global dfoo_otherboth2 +dfoo_otherboth2: + .long 0 + .global dfoo_otherwithout +dfoo_otherwithout: + .long 0 + + .section .rodata + .long datalabel dfoo_other + 4 + .long datalabel dfoo_otherboth + 40 + .long dfoo_otherboth + 24 + .long dfoo_otherboth2 + 24 + .long datalabel dfoo_otherboth2 + 40 + .long dfoo_otherwithout + + .data + +! Same as above, mixing references from same and other section. + .global dfoo_mix +dfoo_mix: + .long 0 + .long (datalabel dfoo_mix + 8) + .global dfoo_mix2 +dfoo_mix2: + .long 0 + .long (dfoo_mix2 + 8) + .global dfoo_mixboth +dfoo_mixboth: + .long 0 + .long (datalabel dfoo_mixboth + 80) + .long (dfoo_mixboth + 80) + .global dfoo_mixboth2 +dfoo_mixboth2: + .long 0 + .long (dfoo_mixboth2 + 64) + .long (datalabel dfoo_mixboth2 + 64) + .global dfoo_mixwithout +dfoo_mixwithout: + .long 0 + .long (dfoo_mixwithout + 42) + .global dfoo_mixwithout2 +dfoo_mixwithout2: + .long 0 + .long (dfoo_mixwithout2 + 24) + + .section .rodata + .long dfoo_mix + 4 + .long datalabel dfoo_mix2 + 48 + .long datalabel dfoo_mixboth + 400 + .long dfoo_mixboth + 420 + .long dfoo_mixboth2 + 248 + .long datalabel dfoo_mixboth2 + 240 + .long dfoo_mixwithout + +! Same as above, referencing symbol in other file (reference only from +! this to other file). + + .text + movi (datalabel dbarboth + 16) & 65535,r40 + movi (dbarboth + 12) & 65535,r40 + movi (dbarboth2 + 12) & 65535,r40 + movi (datalabel dbarboth2 + 16) & 65535,r40 + movi (dbarwithout + 24) & 65535,r30 + + .data + .long (datalabel dbar + 8) + .long datalabel dbar_other + 4 + .long datalabel dbar_otherboth + 40 + .long dbar_otherboth + 24 + .long dbar_otherboth2 + 24 + .long datalabel dbar_otherboth2 + 40 + .long dbar_otherwithout + + .text + movi (datalabel dbar_mix + 8) & 65535,r30 + movi (dbar_mix2 + 8) & 65535,r30 + movi (datalabel dbar_mixboth + 80) & 65535,r30 + movi (dbar_mixboth + 80) & 65535,r30 + movi (dbar_mixboth2 + 64) & 65535,r30 + movi (datalabel dbar_mixboth2 + 64) & 65535,r30 + movi (dbar_mixwithout + 42) & 65535,r30 + movi (dbar_mixwithout2 + 24) & 65535,r30 + + .data + .long dbar_mix + 4 + .long datalabel dbar_mix2 + 48 + .long datalabel dbar_mixboth + 400 + .long dbar_mixboth + 420 + .long dbar_mixboth2 + 248 + .long datalabel dbar_mixboth2 + 240 + .long dbar_mixwithout + +! Same as above, referencing symbol in other file *and* within that file. + + .text + movi (datalabel dbazboth + 16) & 65535,r40 + movi (dbazboth + 12) & 65535,r40 + + movi (dbazboth2 + 12) & 65535,r40 + movi (datalabel dbazboth2 + 16) & 65535,r40 + + movi (dbazwithout + 24) & 65535,r30 + + .data + .long (datalabel dbaz + 8) + .long datalabel dbaz_other + 4 + .long datalabel dbaz_otherboth + 40 + .long dbaz_otherboth + 24 + .long dbaz_otherboth2 + 24 + .long datalabel dbaz_otherboth2 + 40 + .long dbaz_otherwithout + + .text + movi (datalabel dbaz_mix + 8) & 65535,r30 + movi (dbaz_mix2 + 8) & 65535,r30 + movi (datalabel dbaz_mixboth + 80) & 65535,r30 + movi (dbaz_mixboth + 80) & 65535,r30 + movi (dbaz_mixboth2 + 64) & 65535,r30 + movi (datalabel dbaz_mixboth2 + 64) & 65535,r30 + movi (dbaz_mixwithout + 42) & 65535,r30 + movi (dbaz_mixwithout2 + 24) & 65535,r30 + + .data + .long dbaz_mix + 4 + .long datalabel dbaz_mix2 + 48 + .long datalabel dbaz_mixboth + 400 + .long dbaz_mixboth + 420 + .long dbaz_mixboth2 + 248 + .long datalabel dbaz_mixboth2 + 240 + .long dbaz_mixwithout diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/shdl-2.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/shdl-2.s new file mode 100644 index 0000000..a41fd52 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/shdl-2.s @@ -0,0 +1,286 @@ +! Part two of test for inter-file DataLabel support. + + .mode SHmedia + .text +part2: + movi (datalabel foowithout + 16) & 65535, r24 + + .section .rodata + .long datalabel foo_otherwithout + 32 + + .text + movi (datalabel foo_mixwithout + 1024) & 65535, r24 + .section .rodata + .long datalabel foo_mixwithout + 32 + + .text + movi (datalabel foo_mixwithout2 + 1024) & 65535, r24 + .section .rodata + .long foo_mixwithout2 + 32 + + .text + .global bar +bar: + nop + + .global barboth +barboth: + nop + + .global barboth2 +barboth2: + nop + + .global barwithout +barwithout: + nop + + .global bar_other +bar_other: + nop + .global bar_otherboth +bar_otherboth: + nop + .global bar_otherboth2 +bar_otherboth2: + nop + .global bar_otherwithout +bar_otherwithout: + nop + + .text + + .global bar_mix +bar_mix: + nop + .global bar_mix2 +bar_mix2: + nop + .global bar_mixboth +bar_mixboth: + nop + .global bar_mixboth2 +bar_mixboth2: + nop + .global bar_mixwithout +bar_mixwithout: + nop + .global bar_mixwithout2 +bar_mixwithout2: + nop + +! Almost-copy of "foo" in primary file. + + .global baz +baz: + nop + movi (datalabel baz + 8) & 65535,r30 + + .global bazboth +bazboth: + nop + movi (datalabel bazboth + 16) & 65535,r40 + movi (bazboth + 12) & 65535,r40 + + .global bazboth2 +bazboth2: + nop + movi (bazboth2 + 12) & 65535,r40 + movi (datalabel bazboth2 + 16) & 65535,r40 + + .global bazwithout +bazwithout: + nop + movi (datalabel bazwithout + 24) & 65535,r30 + + .global baz_other +baz_other: + nop + .global baz_otherboth +baz_otherboth: + nop + .global baz_otherboth2 +baz_otherboth2: + nop + .global baz_otherwithout +baz_otherwithout: + nop + + .section .rodata + .long datalabel baz_other + 4 + .long datalabel baz_otherboth + 40 + .long baz_otherboth + 24 + .long baz_otherboth2 + 24 + .long datalabel baz_otherboth2 + 40 + .long baz_otherwithout + + .text + + .global baz_mix +baz_mix: + nop + movi (datalabel baz_mix + 8) & 65535,r30 + .global baz_mix2 +baz_mix2: + nop + movi (baz_mix2 + 8) & 65535,r30 + .global baz_mixboth +baz_mixboth: + nop + movi (datalabel baz_mixboth + 80) & 65535,r30 + movi (baz_mixboth + 80) & 65535,r30 + .global baz_mixboth2 +baz_mixboth2: + nop + movi (baz_mixboth2 + 64) & 65535,r30 + movi (datalabel baz_mixboth2 + 64) & 65535,r30 + .global baz_mixwithout +baz_mixwithout: + nop + movi (baz_mixwithout + 42) & 65535,r30 + .global baz_mixwithout2 +baz_mixwithout2: + nop + movi (baz_mixwithout2 + 24) & 65535,r30 + + .section .rodata + .long baz_mix + 4 + .long datalabel baz_mix2 + 48 + .long datalabel baz_mixboth + 400 + .long baz_mixboth + 420 + .long baz_mixboth2 + 248 + .long datalabel baz_mixboth2 + 240 + .long baz_mixwithout + + .data + .long datalabel dfoowithout + 44 + .long datalabel dfoo_mixwithout + 48 + .long datalabel dfoo_mixwithout2 + 84 + + .global dbar +dbar: + .long 0 + .global dbarboth +dbarboth: + .long 0 + .global dbarboth2 +dbarboth2: + .long 0 + .global dbarwithout +dbarwithout: + .long 0 + .global dbar_other +dbar_other: + .long 0 + .global dbar_otherboth +dbar_otherboth: + .long 0 + .global dbar_otherboth2 +dbar_otherboth2: + .long 0 + .global dbar_otherwithout +dbar_otherwithout: + .long 0 + + .global dbar_mix +dbar_mix: + .long 0 + .global dbar_mix2 +dbar_mix2: + .long 0 + .global dbar_mixboth +dbar_mixboth: + .long 0 + .global dbar_mixboth2 +dbar_mixboth2: + .long 0 + .global dbar_mixwithout +dbar_mixwithout: + .long 0 + .global dbar_mixwithout2 +dbar_mixwithout2: + .long 0 + +! Almost-copy of "dfoo" in primary file. + + .data + .global dbaz +dbaz: + .long 0 + .long (datalabel dbaz + 8) + + .global dbazboth +dbazboth: + .long 0 + .long (datalabel dbazboth + 16) + .long (dbazboth + 12) + + .global dbazboth2 +dbazboth2: + .long 0 + .long (dbazboth2 + 12) + .long (datalabel dbazboth2 + 16) + + .global dbazwithout +dbazwithout: + .long 0 + .long (dbazwithout + 24) + + .global dbaz_other +dbaz_other: + .long 0 + .global dbaz_otherboth +dbaz_otherboth: + .long 0 + .global dbaz_otherboth2 +dbaz_otherboth2: + .long 0 + .global dbaz_otherwithout +dbaz_otherwithout: + .long 0 + + .section .rodata + .long datalabel dbaz_other + 4 + .long datalabel dbaz_otherboth + 40 + .long dbaz_otherboth + 24 + .long dbaz_otherboth2 + 24 + .long datalabel dbaz_otherboth2 + 40 + .long dbaz_otherwithout + + .data + + .global dbaz_mix +dbaz_mix: + .long 0 + .long (datalabel dbaz_mix + 8) + .global dbaz_mix2 +dbaz_mix2: + .long 0 + .long (dbaz_mix2 + 8) + .global dbaz_mixboth +dbaz_mixboth: + .long 0 + .long (datalabel dbaz_mixboth + 80) + .long (dbaz_mixboth + 80) + .global dbaz_mixboth2 +dbaz_mixboth2: + .long 0 + .long (dbaz_mixboth2 + 64) + .long (datalabel dbaz_mixboth2 + 64) + .global dbaz_mixwithout +dbaz_mixwithout: + .long 0 + .long (dbaz_mixwithout + 42) + .global dbaz_mixwithout2 +dbaz_mixwithout2: + .long 0 + .long (dbaz_mixwithout2 + 24) + + .section .rodata + .long dbaz_mix + 4 + .long datalabel dbaz_mix2 + 48 + .long datalabel dbaz_mixboth + 400 + .long dbaz_mixboth + 420 + .long dbaz_mixboth2 + 248 + .long datalabel dbaz_mixboth2 + 240 + .long dbaz_mixwithout diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/shdl32.xd b/binutils-2.21/ld/testsuite/ld-sh/sh64/shdl32.xd new file mode 100644 index 0000000..56773e3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/shdl32.xd @@ -0,0 +1,123 @@ +.*: file format .*-sh64 +.* +architecture: sh5, flags 0x0+112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x0+1001 + +Program Header: + LOAD off 0x0+100 vaddr 0x0+1000 paddr 0x0+1000 align 2\*\*7 + filesz 0x0+348 memsz 0x0+348 flags r-x + LOAD off 0x0+448 vaddr 0x0+13c8 paddr 0x0+13c8 align 2\*\*7 + filesz 0x0+194 memsz 0x0+194 flags rw- + LOAD off 0x0+600 vaddr 0x0+80000 paddr 0x0+80000 align 2\*\*7 + filesz 0x00000004 memsz 0x00000004 flags rw- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.text 0+204 0+1000 0+1000 0+100 2\*\*0 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 \.rodata 0+144 0+1204 0+1204 0+304 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 \.data 0+194 0+13c8 0+13c8 0+448 2\*\*2 + CONTENTS, ALLOC, LOAD, DATA + 3 \.stack 0+4 0+80000 0+80000 0+600 2\*\*0 + CONTENTS, ALLOC, LOAD, DATA +SYMBOL TABLE: +0+1000 l d \.text 0+ (|\.text) +0+1204 l d \.rodata 0+ (|\.rodata) +0+13c8 l d \.data 0+ (|\.data) +0+80000 l d \.stack 0+ (|\.stack) +0+1150 l \.text 0+ 0x04 part2 +0+13f8 g \.data 0+ dfoo_otherboth2 +0+1178 g \.text 0+ 0x04 bar_otherwithout +0+11b4 g \.text 0+ 0x04 bazwithout +0+1428 g \.data 0+ dfoo_mixwithout +0+1554 g \.data 0+ dbaz_mixwithout2 +0+11bc g \.text 0+ 0x04 baz_other +0+11cc g \.text 0+ 0x04 baz_mix +0+11c0 g \.text 0+ 0x04 baz_otherboth +0+13e8 g \.data 0+ dfoowithout +0+14b4 g \.data 0+ dbar +0+106c g \.text 0+ 0x04 foo_mixwithout2 +0+11a8 g \.text 0+ 0x04 bazboth2 +0+13fc g \.data 0+ dfoo_otherwithout +0+11c4 g \.text 0+ 0x04 baz_otherboth2 +0+1174 g \.text 0+ 0x04 bar_otherboth2 +0+1194 g \.text 0+ 0x04 baz +0+13c8 g \.data 0+ dfoo +0+14e8 g \.data 0+ dbar_mixwithout2 +0+13dc g \.data 0+ dfooboth2 +0+1408 g \.data 0+ dfoo_mix2 +0+154c g \.data 0+ dbaz_mixwithout +0+1044 g \.text 0+ 0x04 foo_mix2 +0+1018 g \.text 0+ 0x04 fooboth2 +0+14cc g \.data 0+ dbar_otherboth2 +0+117c g \.text 0+ 0x04 bar_mix +0+14d0 g \.data 0+ dbar_otherwithout +0+11dc g \.text 0+ 0x04 baz_mixboth +0+14c8 g \.data 0+ dbar_otherboth +0+150c g \.data 0+ dbazwithout +0+152c g \.data 0+ dbaz_mix2 +0+1184 g \.text 0+ 0x04 bar_mixboth +0+13f4 g \.data 0+ dfoo_otherboth +0+14dc g \.data 0+ dbar_mixboth +0+1024 g \.text 0+ 0x04 foowithout +0+14e4 g \.data 0+ dbar_mixwithout +0+11fc g \.text 0+ 0x04 baz_mixwithout2 +0+1030 g \.text 0+ 0x04 foo_otherboth +0+1540 g \.data 0+ dbaz_mixboth2 +0+104c g \.text 0+ 0x04 foo_mixboth +0+1534 g \.data 0+ dbaz_mixboth +0+103c g \.text 0+ 0x04 foo_mix +0+1518 g \.data 0+ dbaz_otherboth +0+14e0 g \.data 0+ dbar_mixboth2 +0+14ec g \.data 0+ dbaz +0+1524 g \.data 0+ dbaz_mix +0+13c8 g .* 0+ ___dtors +0+141c g \.data 0+ dfoo_mixboth2 +0+119c g \.text 0+ 0x04 bazboth +0+13f0 g \.data 0+ dfoo_other +0+11e8 g \.text 0+ 0x04 baz_mixboth2 +0+1514 g \.data 0+ dbaz_other +0+1164 g \.text 0+ 0x04 barboth2 +0+1168 g \.text 0+ 0x04 barwithout +0+14d8 g \.data 0+ dbar_mix2 +0+1560 g \*ABS\* 0+ __bss_start +0+1410 g \.data 0+ dfoo_mixboth +0+14c4 g \.data 0+ dbar_other +0+1180 g \.text 0+ 0x04 bar_mix2 +0+14f4 g \.data 0+ dbazboth +0+1038 g \.text 0+ 0x04 foo_otherwithout +0+1190 g \.text 0+ 0x04 bar_mixwithout2 +0+13c8 g .* 0+ ___ctors_end +0+1064 g \.text 0+ 0x04 foo_mixwithout +0+116c g \.text 0+ 0x04 bar_other +0+13d0 g \.data 0+ dfooboth +0+1034 g \.text 0+ 0x04 foo_otherboth2 +0+1400 g \.data 0+ dfoo_mix +0+13c8 g .* 0+ ___ctors +0+14d4 g \.data 0+ dbar_mix +0+100c g \.text 0+ 0x04 fooboth +0+1170 g \.text 0+ 0x04 bar_otherboth +0+14c0 g \.data 0+ dbarwithout +0+1004 g \.text 0+ 0x04 foo +0+102c g \.text 0+ 0x04 foo_other +0+1560 g \*ABS\* 0+ _edata +0+1560 g \*ABS\* 0+ _end +0+1430 g \.data 0+ dfoo_mixwithout2 +0+1058 g \.text 0+ 0x04 foo_mixboth2 +0+11d4 g \.text 0+ 0x04 baz_mix2 +0+11c8 g \.text 0+ 0x04 baz_otherwithout +0+1000 g \.text 0+ 0x04 start +0+14bc g \.data 0+ dbarboth2 +0+118c g \.text 0+ 0x04 bar_mixwithout +0+115c g \.text 0+ 0x04 bar +0+80000 g \.stack 0+ _stack +0+1520 g \.data 0+ dbaz_otherwithout +0+11f4 g \.text 0+ 0x04 baz_mixwithout +0+1160 g \.text 0+ 0x04 barboth +0+14b8 g \.data 0+ dbarboth +0+1188 g \.text 0+ 0x04 bar_mixboth2 +0+13c8 g .* 0+ ___dtors_end +0+151c g \.data 0+ dbaz_otherboth2 +0+1500 g \.data 0+ dbazboth2 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/shdl64.sd b/binutils-2.21/ld/testsuite/ld-sh/sh64/shdl64.sd new file mode 100644 index 0000000..abe257a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/shdl64.sd @@ -0,0 +1,87 @@ +.*: file format .*-sh64 + +Contents of section \.text: + 1000 6ff0fff0 6ff0fff0 cc4031e0 6ff0fff0 .* + 1010 cc407280 cc406680 6ff0fff0 cc409680 .* + 1020 cc40a280 6ff0fff0 cc40f5e0 6ff0fff0 .* + 1030 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 1040 cc4111e0 6ff0fff0 cc4135e0 6ff0fff0 .* + 1050 cc4271e0 cc4275e0 6ff0fff0 cc4265e0 .* + 1060 cc4261e0 6ff0fff0 cc423de0 6ff0fff0 .* + 1070 cc4215e0 6ff0fff0 cc4591e0 cc45c280 .* + 1080 cc45b680 cc45c680 cc45d280 cc4605e0 .* + 1090 cc4611e0 cc4625e0 cc4751e0 cc4755e0 .* + 10a0 cc4725e0 cc4721e0 cc46dde0 cc46a5e0 .* + 10b0 cc4671e0 cc46b280 cc46a680 cc46d680 .* + 10c0 cc46e280 cc4735e0 cc4751e0 cc4775e0 .* + 10d0 cc48b1e0 cc48b5e0 cc48a5e0 cc48a1e0 .* + 10e0 cc487de0 cc4855e0 cc532280 cc531280 .* + 10f0 cc532280 cc533280 cc5361e0 cc5371e0 .* + 1100 cc5381e0 cc54b1e0 cc54b1e0 cc5481e0 .* + 1110 cc5481e0 cc5439e0 cc5401e0 cc541280 .* + 1120 cc540280 cc543280 cc544280 cc5491e0 .* + 1130 cc54b1e0 cc54d1e0 cc5611e0 cc5611e0 .* + 1140 cc5601e0 cc5601e0 cc55d9e0 cc55b1e0 .* + 1150 cc40d180 cc519180 cc51b180 6ff0fff0 .* + 1160 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 1170 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 1180 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 1190 6ff0fff0 6ff0fff0 cc4671e0 6ff0fff0 .* + 11a0 cc46b280 cc46a680 6ff0fff0 cc46d680 .* + 11b0 cc46e280 6ff0fff0 cc4731e0 6ff0fff0 .* + 11c0 6ff0fff0 6ff0fff0 6ff0fff0 6ff0fff0 .* + 11d0 cc4751e0 6ff0fff0 cc4775e0 6ff0fff0 .* + 11e0 cc48b1e0 cc48b5e0 6ff0fff0 cc48a5e0 .* + 11f0 cc48a1e0 6ff0fff0 cc487de0 6ff0fff0 .* + 1200 cc4855e0 .* +Contents of section \.rodata: + 1204 00001030 00001058 00001049 0000104d .* + 1214 0000105c 00001039 00001041 00001074 .* + 1224 000011dc 000011f1 00001151 00001148 .* + 1234 00001065 00001170 00001198 00001189 .* + 1244 0000118d 0000119c 00001179 00001181 .* + 1254 000011b0 00001314 00001329 00001281 .* + 1264 00001278 0000118d 000011c0 000011e8 .* + 1274 000011d9 000011dd 000011ec 000011c9 .* + 1284 000011d1 00001204 0000136c 00001381 .* + 1294 000012e1 000012d8 000011f5 000013f4 .* + 12a4 0000141c 0000140c 00001410 00001420 .* + 12b4 000013fc 00001404 00001438 000015a0 .* + 12c4 000015b4 00001514 0000150c 00001428 .* + 12d4 00001058 00001084 0000108d 000011c0 .* + 12e4 000011e8 000011d9 000011dd 000011ec .* + 12f4 000011c9 000011d1 00001204 0000136c .* + 1304 00001381 000012e1 000012d8 000011f5 .* + 1314 00001518 00001540 00001530 00001534 .* + 1324 00001544 00001520 00001528 0000155c .* + 1334 000016c4 000016d8 00001638 00001630 .* + 1344 0000154c .* +Contents of section \.data: + 13c8 00000000 000013d0 00000000 000013e0 .* + 13d8 000013dc 00000000 000013e8 000013ec .* + 13e8 00000000 00001400 00000000 00000000 .* + 13f8 00000000 00000000 00000000 00001408 .* + 1408 00000000 00001410 00000000 00001460 .* + 1418 00001460 00000000 0000145c 0000145c .* + 1428 00000000 00001452 00000000 00001448 .* + 1438 000014bc 000014c8 000014f0 000014e0 .* + 1448 000014e4 000014f4 000014d0 000014d8 .* + 1458 00001508 0000166c 00001680 000015d8 .* + 1468 000015d0 000014e4 000014f4 00001518 .* + 1478 00001540 00001530 00001534 00001544 .* + 1488 00001520 00001528 0000155c 000016c4 .* + 1498 000016d8 00001638 00001630 0000154c .* + 14a8 00001414 00001458 00001484 00000000 .* + 14b8 00000000 00000000 00000000 00000000 .* + 14c8 00000000 00000000 00000000 00000000 .* + 14d8 00000000 00000000 00000000 00000000 .* + 14e8 00000000 00000000 000014f4 00000000 .* + 14f8 00001504 00001500 00000000 0000150c .* + 1508 00001510 00000000 00001524 00000000 .* + 1518 00000000 00000000 00000000 00000000 .* + 1528 0000152c 00000000 00001534 00000000 .* + 1538 00001584 00001584 00000000 00001580 .* + 1548 00001580 00000000 00001576 00000000 .* + 1558 0000156c .* +Contents of section \.stack: + 80000 deaddead .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/shdl64.xd b/binutils-2.21/ld/testsuite/ld-sh/sh64/shdl64.xd new file mode 100644 index 0000000..142ca96 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/shdl64.xd @@ -0,0 +1,123 @@ +.*: file format .*-sh64 +.* +architecture: sh5, flags 0x0+112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x0+1001 + +Program Header: + LOAD off 0x0+100 vaddr 0x0+1000 paddr 0x0+1000 align 2\*\*7 + filesz 0x0+348 memsz 0x0+348 flags r-x + LOAD off 0x0+448 vaddr 0x0+13c8 paddr 0x0+13c8 align 2\*\*7 + filesz 0x0+194 memsz 0x0+194 flags rw- + LOAD off 0x0+600 vaddr 0x0+80000 paddr 0x0+80000 align 2\*\*7 + filesz 0x0+4 memsz 0x0+4 flags rw- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.text 0+204 0+1000 0+1000 0+100 2\*\*0 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 \.rodata 0+144 0+1204 0+1204 0+304 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 \.data 0+194 0+13c8 0+13c8 0+448 2\*\*2 + CONTENTS, ALLOC, LOAD, DATA + 3 \.stack 0+4 0+80000 0+80000 0+600 2\*\*0 + CONTENTS, ALLOC, LOAD, DATA +SYMBOL TABLE: +0+1000 l d \.text 0+ (|\.text) +0+1204 l d \.rodata 0+ (|\.rodata) +0+13c8 l d \.data 0+ (|\.data) +0+80000 l d \.stack 0+ (|\.stack) +0+1150 l \.text 0+ 0x04 part2 +0+13f8 g \.data 0+ dfoo_otherboth2 +0+1178 g \.text 0+ 0x04 bar_otherwithout +0+11b4 g \.text 0+ 0x04 bazwithout +0+1428 g \.data 0+ dfoo_mixwithout +0+1554 g \.data 0+ dbaz_mixwithout2 +0+11bc g \.text 0+ 0x04 baz_other +0+11cc g \.text 0+ 0x04 baz_mix +0+11c0 g \.text 0+ 0x04 baz_otherboth +0+13e8 g \.data 0+ dfoowithout +0+14b4 g \.data 0+ dbar +0+106c g \.text 0+ 0x04 foo_mixwithout2 +0+11a8 g \.text 0+ 0x04 bazboth2 +0+13fc g \.data 0+ dfoo_otherwithout +0+11c4 g \.text 0+ 0x04 baz_otherboth2 +0+1174 g \.text 0+ 0x04 bar_otherboth2 +0+1194 g \.text 0+ 0x04 baz +0+13c8 g \.data 0+ dfoo +0+14e8 g \.data 0+ dbar_mixwithout2 +0+13dc g \.data 0+ dfooboth2 +0+1408 g \.data 0+ dfoo_mix2 +0+154c g \.data 0+ dbaz_mixwithout +0+1044 g \.text 0+ 0x04 foo_mix2 +0+1018 g \.text 0+ 0x04 fooboth2 +0+14cc g \.data 0+ dbar_otherboth2 +0+117c g \.text 0+ 0x04 bar_mix +0+14d0 g \.data 0+ dbar_otherwithout +0+11dc g \.text 0+ 0x04 baz_mixboth +0+14c8 g \.data 0+ dbar_otherboth +0+150c g \.data 0+ dbazwithout +0+152c g \.data 0+ dbaz_mix2 +0+1184 g \.text 0+ 0x04 bar_mixboth +0+13f4 g \.data 0+ dfoo_otherboth +0+14dc g \.data 0+ dbar_mixboth +0+1024 g \.text 0+ 0x04 foowithout +0+14e4 g \.data 0+ dbar_mixwithout +0+11fc g \.text 0+ 0x04 baz_mixwithout2 +0+1030 g \.text 0+ 0x04 foo_otherboth +0+1540 g \.data 0+ dbaz_mixboth2 +0+104c g \.text 0+ 0x04 foo_mixboth +0+1534 g \.data 0+ dbaz_mixboth +0+103c g \.text 0+ 0x04 foo_mix +0+1518 g \.data 0+ dbaz_otherboth +0+14e0 g \.data 0+ dbar_mixboth2 +0+14ec g \.data 0+ dbaz +0+1524 g \.data 0+ dbaz_mix +0+13c8 g .* 0+ ___dtors +0+141c g \.data 0+ dfoo_mixboth2 +0+119c g \.text 0+ 0x04 bazboth +0+13f0 g \.data 0+ dfoo_other +0+11e8 g \.text 0+ 0x04 baz_mixboth2 +0+1514 g \.data 0+ dbaz_other +0+1164 g \.text 0+ 0x04 barboth2 +0+1168 g \.text 0+ 0x04 barwithout +0+14d8 g \.data 0+ dbar_mix2 +0+1560 g \*ABS\* 0+ __bss_start +0+1410 g \.data 0+ dfoo_mixboth +0+14c4 g \.data 0+ dbar_other +0+1180 g \.text 0+ 0x04 bar_mix2 +0+14f4 g \.data 0+ dbazboth +0+1038 g \.text 0+ 0x04 foo_otherwithout +0+1190 g \.text 0+ 0x04 bar_mixwithout2 +0+13c8 g .* 0+ ___ctors_end +0+1064 g \.text 0+ 0x04 foo_mixwithout +0+116c g \.text 0+ 0x04 bar_other +0+13d0 g \.data 0+ dfooboth +0+1034 g \.text 0+ 0x04 foo_otherboth2 +0+1400 g \.data 0+ dfoo_mix +0+13c8 g .* 0+ ___ctors +0+14d4 g \.data 0+ dbar_mix +0+100c g \.text 0+ 0x04 fooboth +0+1170 g \.text 0+ 0x04 bar_otherboth +0+14c0 g \.data 0+ dbarwithout +0+1004 g \.text 0+ 0x04 foo +0+102c g \.text 0+ 0x04 foo_other +0+1560 g \*ABS\* 0+ _edata +0+1560 g \*ABS\* 0+ _end +0+1430 g \.data 0+ dfoo_mixwithout2 +0+1058 g \.text 0+ 0x04 foo_mixboth2 +0+11d4 g \.text 0+ 0x04 baz_mix2 +0+11c8 g \.text 0+ 0x04 baz_otherwithout +0+1000 g \.text 0+ 0x04 start +0+14bc g \.data 0+ dbarboth2 +0+118c g \.text 0+ 0x04 bar_mixwithout +0+115c g \.text 0+ 0x04 bar +0+80000 g \.stack 0+ _stack +0+1520 g \.data 0+ dbaz_otherwithout +0+11f4 g \.text 0+ 0x04 baz_mixwithout +0+1160 g \.text 0+ 0x04 barboth +0+14b8 g \.data 0+ dbarboth +0+1188 g \.text 0+ 0x04 bar_mixboth2 +0+13c8 g .* 0+ ___dtors_end +0+151c g \.data 0+ dbaz_otherboth2 +0+1500 g \.data 0+ dbazboth2 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/shmix-1.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/shmix-1.s new file mode 100644 index 0000000..e078ac2 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/shmix-1.s @@ -0,0 +1,33 @@ +! Check mixed-mode objects; different sections holding different ISA:s. + .mode SHcompact + .text + .global start +start: + bt forw + mova start2,r0 +start2: + nop + nop +forw: + nop + .align 2 + .long $ + .long start2 + .long mediacode2 + + .data + .long $ + .long start2 + .long mediacode2 + + .section .text.media,"ax" + .mode SHmedia + .align 2 +mediacode: + ptb forw,tr4 + pt start2,tr5 +mediacode2: + movi start2,r54 + movi mediacode2,r45 + pta mediacode2,tr7 + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/shmix-2.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/shmix-2.s new file mode 100644 index 0000000..2ea7344 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/shmix-2.s @@ -0,0 +1,28 @@ +! A SHmedia object, that we will link to a SHcompact object. +! We will be using .text for the SHmedia code and .text.compact for the +! SHcompact code, so we don't get two ISA in the same section. + .text + .mode SHmedia + + .global start + .global medialabel1 + .global medialabel2 + .global medialabel3 +start: + movi compactlabel1,r14 + movi compactlabel4,r14 +medialabel1: + pt compactlabel2,tr6 +medialabel2: + nop + + .section .rodata + .long compactlabel3 +medialabel3: + .long compactlabel5 + + .data + .global medialabel4 + .long 0 +medialabel4: + .long compactlabel2 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/shmix-3.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/shmix-3.s new file mode 100644 index 0000000..42d1212 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/shmix-3.s @@ -0,0 +1,32 @@ +! A SHcompact object, that we will link to a SHmedia object. +! We will be using .text for the SHmedia code and .text.compact for the +! SHcompact code, so we don't get two ISA in the same section. + .section .text.compact,"ax" + .mode SHcompact + .global compactlabel1 + .global compactlabel2 + .global compactlabel3 + .global compactlabel4 + .global compactlabel5 +locallabel: + nop +compactlabel1: + mova compactlabel2,r0 +compactlabel2: + mova compactlabel3,r0 + nop +compactlabel3: + nop + .align 2 + .long medialabel1 + .long medialabel4 + + .section .rodata + .long medialabel2 +compactlabel4: + .long medialabel3 + + .data + .long 0 +compactlabel5: + .long medialabel4 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/stobin-0-dso.d b/binutils-2.21/ld/testsuite/ld-sh/sh64/stobin-0-dso.d new file mode 100644 index 0000000..405c05a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/stobin-0-dso.d @@ -0,0 +1,9 @@ +#source: stolib.s +#as: --abi=32 --isa=SHmedia +#ld: -shared -mshelf32 +#objdump: -drj.text +#target: sh64-*-elf + +.*: +file format elf32-sh64.* + +#pass diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/stobin-1.d b/binutils-2.21/ld/testsuite/ld-sh/sh64/stobin-1.d new file mode 100644 index 0000000..e0f8b27 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/stobin-1.d @@ -0,0 +1,15 @@ +#source: stobin.s +#as: --abi=32 --isa=SHmedia +#ld: -mshelf32 tmpdir/stobin-0-dso.so +#objdump: -drj.text +#target: sh64-*-elf + +.*: +file format elf32-sh64.* + +Disassembly of section \.text: + +0+[0-9a-f]+ <start>: + [0-9a-f]+: cffffd90 movi -1,r25 + [0-9a-f]+: cbfee590 shori 65465,r25 ! 0xffffffb9 .* + [0-9a-f]+: 6bf56600 ptrel/l r25,tr0 + [0-9a-f]+: 4401fff0 blink tr0,r63 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/stobin.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/stobin.s new file mode 100644 index 0000000..30d3597 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/stobin.s @@ -0,0 +1,5 @@ + .text + .globl start +start: + pt bar, tr0 + blink tr0, r63 diff --git a/binutils-2.21/ld/testsuite/ld-sh/sh64/stolib.s b/binutils-2.21/ld/testsuite/ld-sh/sh64/stolib.s new file mode 100644 index 0000000..587faa6 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sh64/stolib.s @@ -0,0 +1,7 @@ + .text + .globl bar + .type bar,@function +bar: + ptabs r18, tr0 + blink tr0, r63 + .Lfe_bar: .size bar,.Lfe_bar-X diff --git a/binutils-2.21/ld/testsuite/ld-sh/shared-1.d b/binutils-2.21/ld/testsuite/ld-sh/shared-1.d new file mode 100644 index 0000000..940195d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/shared-1.d @@ -0,0 +1,23 @@ +#source: ldr1.s +#source: ldr2.s +#as: -little +#ld: -shared -EL -z nocombreloc +#readelf: -r -x4 -x5 +#target: sh*-*-elf + +# Make sure relocations against global and local symbols with relative and +# absolute 32-bit relocs don't come out wrong after ld -r. Remember that +# SH uses partial_inplace (sort-of REL within RELA) with related confusion +# about how, when, where and which addends to use. A DSO must have the +# same value in the addend as in the data, so either can be used. + +Relocation section '\.rela\.text' at offset 0x[0-9a-f]+ contains 1 entries: +.* +0000019c +[0-9a-f]+ R_SH_RELATIVE +000001a0 + +Hex dump of section '\.rela\.text': + 0x00000188 9c010000 a5000000 a0010000 .* + +Hex dump of section '\.text': +.* + 0x00000194 09000900 09000900 a0010000 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/shared-2.d b/binutils-2.21/ld/testsuite/ld-sh/shared-2.d new file mode 100644 index 0000000..e65fea4 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/shared-2.d @@ -0,0 +1,20 @@ +#source: textrel1.s +#source: textrel2.s +#as: -little +#ld: -shared -EL +#readelf: -d +#target: sh*-*-elf sh*-*-linux* sh*-*-netbsd* + +# Make sure that there is no unnecessary DT_TEXTREL entry. + +Dynamic section at offset 0x[0-9a-f]+ contains 9 entries: + Tag Type Name/Value + 0x00000004 \(HASH\) 0x[0-9a-f]+ + 0x00000005 \(STRTAB\) 0x[0-9a-f]+ + 0x00000006 \(SYMTAB\) 0x[0-9a-f]+ + 0x0000000a \(STRSZ\) [0-9]+ \(bytes\) + 0x0000000b \(SYMENT\) 16 \(bytes\) + 0x00000007 \(RELA\) 0x[0-9a-f]+ + 0x00000008 \(RELASZ\) 12 \(bytes\) + 0x00000009 \(RELAENT\) 12 \(bytes\) + 0x00000000 \(NULL\) 0x0 diff --git a/binutils-2.21/ld/testsuite/ld-sh/start.s b/binutils-2.21/ld/testsuite/ld-sh/start.s new file mode 100644 index 0000000..2af4c79 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/start.s @@ -0,0 +1,27 @@ + .section .text + .global start +start: + + mov.l stack_k,r15 + + ! call the mainline +L1: + mov.l main_k,r0 + .uses L1 + jsr @r0 + nop + + .align 2 +stack_k: + .long _stack +main_k: + .long _main + + .global _trap +_trap: + trapa #3 + rts + nop + + .section .stack +_stack: .long 0xdeaddead diff --git a/binutils-2.21/ld/testsuite/ld-sh/sub2l-1.d b/binutils-2.21/ld/testsuite/ld-sh/sub2l-1.d new file mode 100644 index 0000000..40d4e08 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sub2l-1.d @@ -0,0 +1,23 @@ +#source: sub2l.s +#as: -little +#ld: -EL -e 0x1000 +#objdump: -st +#target: sh*-*-elf + +.*/dump: file format elf32-sh.* + +SYMBOL TABLE: +#... +0+1000 l .text 00000000 f +0+1002 l .text 00000000 f2 +0+1028 l .text 00000000 L +0+1020 g .text 00000000 ff +#... + +Contents of section \.text: + 1000 0b000900 09000900 09000900 09000900 .* + 1010 09000900 09000900 09000900 09000900 .* + 1020 09000900 09000900 0b000900 d8ffffff .* + 1030 daffffff 02100000 28100000 24100000 .* +Contents of section \..*: +#pass diff --git a/binutils-2.21/ld/testsuite/ld-sh/sub2l.s b/binutils-2.21/ld/testsuite/ld-sh/sub2l.s new file mode 100644 index 0000000..1a077d0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/sub2l.s @@ -0,0 +1,26 @@ +! "The subtraction of two symbols". + .little + .text + .align 5 +f: + rts +f2: + nop + + .section .text.foo,"ax",@progbits + .align 5 + .global ff +ff: + nop + nop + nop + nop +L: + rts + nop + .align 2 + .long f-L + .long f2-L + .long f2 + .long L + .long ff+4 diff --git a/binutils-2.21/ld/testsuite/ld-sh/textrel1.s b/binutils-2.21/ld/testsuite/ld-sh/textrel1.s new file mode 100644 index 0000000..eda4804 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/textrel1.s @@ -0,0 +1,11 @@ + .text + .align 5 + .globl f +f: + mov.l .L1,r0 + rts + nop + .align 2 +.L1: .long g - f + .long foo@GOT + diff --git a/binutils-2.21/ld/testsuite/ld-sh/textrel2.s b/binutils-2.21/ld/testsuite/ld-sh/textrel2.s new file mode 100644 index 0000000..1846a6b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/textrel2.s @@ -0,0 +1,7 @@ + .text + .align 5 + .globl g + .hidden g +g: + rts + nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlsbin-0-dso.d b/binutils-2.21/ld/testsuite/ld-sh/tlsbin-0-dso.d new file mode 100644 index 0000000..dc3eaa6 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlsbin-0-dso.d @@ -0,0 +1,9 @@ +#source: tlslib.s +#as: -little +#ld: -shared -EL +#objdump: -drj.text +#target: sh*-*-linux* sh*-*-netbsd* + +.*: +file format elf32-sh.* + +#pass diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlsbin-1.d b/binutils-2.21/ld/testsuite/ld-sh/tlsbin-1.d new file mode 100644 index 0000000..9f5a086 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlsbin-1.d @@ -0,0 +1,308 @@ +#source: tlsbinpic.s +#source: tlsbin.s +#as: -little +#ld: -EL tmpdir/tlsbin-0-dso.so +#objdump: -drj.text +#target: sh*-*-linux* sh*-*-netbsd* + +.*: +file format elf32-sh.* + +Disassembly of section \.text: + +0+401000 <fn2>: + 401000: c6 2f mov\.l r12,@-r15 + 401002: e6 2f mov\.l r14,@-r15 + 401004: 22 4f sts\.l pr,@-r15 + 401006: 5f c7 mova 401184 <fn2\+0x184>,r0 + 401008: 5e dc mov\.l 401184 <fn2\+0x184>,r12 ! [0-9a-f]+ + 40100a: 0c 3c add r0,r12 + 40100c: f3 6e mov r15,r14 + 40100e: 09 00 nop + 401010: 09 00 nop + 401012: 09 00 nop + 401014: 09 00 nop + 401016: 04 d0 mov\.l 401028 <fn2\+0x28>,r0 ! 1c .* + 401018: 12 04 stc gbr,r4 + 40101a: ce 00 mov\.l @\(r0,r12\),r0 + 40101c: 4c 30 add r4,r0 + 40101e: 09 00 nop + 401020: 09 00 nop + 401022: 05 a0 bra 401030 <fn2\+0x30> + 401024: 09 00 nop + 401026: 09 00 nop + 401028: 1c 00 .*[ ]*.* + 40102a: 00 00 .*[ ]*.* + 40102c: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 40102e: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 401030: 09 00 nop + 401032: 09 00 nop + 401034: 09 00 nop + 401036: 09 00 nop + 401038: 03 d0 mov\.l 401048 <fn2\+0x48>,r0 ! 14 .* + 40103a: 12 04 stc gbr,r4 + 40103c: ce 00 mov\.l @\(r0,r12\),r0 + 40103e: 4c 30 add r4,r0 + 401040: 09 00 nop + 401042: 09 00 nop + 401044: 04 a0 bra 401050 <fn2\+0x50> + 401046: 09 00 nop + 401048: 14 00 .*[ ]*.* + 40104a: 00 00 .*[ ]*.* + 40104c: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 40104e: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 401050: 09 00 nop + 401052: 09 00 nop + 401054: 09 00 nop + 401056: 09 00 nop + 401058: 03 d4 mov\.l 401068 <fn2\+0x68>,r4 ! 8 .* + 40105a: 12 00 stc gbr,r0 + 40105c: 4c 30 add r4,r0 + 40105e: 09 00 nop + 401060: 09 00 nop + 401062: 09 00 nop + 401064: 04 a0 bra 401070 <fn2\+0x70> + 401066: 09 00 nop + 401068: 08 00 .*[ ]*.* + 40106a: 00 00 .*[ ]*.* + 40106c: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 40106e: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 401070: 09 00 nop + 401072: 09 00 nop + 401074: 09 00 nop + 401076: 09 00 nop + 401078: 03 d4 mov\.l 401088 <fn2\+0x88>,r4 ! 10 .* + 40107a: 12 00 stc gbr,r0 + 40107c: 4c 30 add r4,r0 + 40107e: 09 00 nop + 401080: 09 00 nop + 401082: 09 00 nop + 401084: 04 a0 bra 401090 <fn2\+0x90> + 401086: 09 00 nop + 401088: 10 00 .*[ ]*.* + 40108a: 00 00 .*[ ]*.* + 40108c: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 40108e: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 401090: 09 00 nop + 401092: 09 00 nop + 401094: 09 00 nop + 401096: 09 00 nop + 401098: 03 d4 mov\.l 4010a8 <fn2\+0xa8>,r4 ! 18 .* + 40109a: 12 00 stc gbr,r0 + 40109c: 4c 30 add r4,r0 + 40109e: 09 00 nop + 4010a0: 09 00 nop + 4010a2: 09 00 nop + 4010a4: 04 a0 bra 4010b0 <fn2\+0xb0> + 4010a6: 09 00 nop + 4010a8: 18 00 .*[ ]*.* + 4010aa: 00 00 .*[ ]*.* + 4010ac: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 4010ae: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 4010b0: 09 00 nop + 4010b2: 09 00 nop + 4010b4: 09 00 nop + 4010b6: 09 00 nop + 4010b8: 12 00 stc gbr,r0 + 4010ba: 09 00 nop + 4010bc: 09 00 nop + 4010be: 09 00 nop + 4010c0: 09 00 nop + 4010c2: 09 00 nop + 4010c4: 04 a0 bra 4010d0 <fn2\+0xd0> + 4010c6: 09 00 nop + 4010c8: 00 00 .*[ ]*.* + 4010ca: 00 00 .*[ ]*.* + 4010cc: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 4010ce: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 4010d0: 09 00 nop + 4010d2: 09 00 nop + 4010d4: 2c d1 mov\.l 401188 <fn2\+0x188>,r1 ! 10 .* + 4010d6: 0c 31 add r0,r1 + 4010d8: 09 00 nop + 4010da: 09 00 nop + 4010dc: 2b d2 mov\.l 40118c <fn2\+0x18c>,r2 ! 14 .* + 4010de: 0c 32 add r0,r2 + 4010e0: 09 00 nop + 4010e2: 09 00 nop + 4010e4: 09 00 nop + 4010e6: 09 00 nop + 4010e8: 12 00 stc gbr,r0 + 4010ea: 09 00 nop + 4010ec: 09 00 nop + 4010ee: 09 00 nop + 4010f0: 09 00 nop + 4010f2: 09 00 nop + 4010f4: 04 a0 bra 401100 <fn2\+0x100> + 4010f6: 09 00 nop + 4010f8: 00 00 .*[ ]*.* + 4010fa: 00 00 .*[ ]*.* + 4010fc: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 4010fe: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 401100: 09 00 nop + 401102: 09 00 nop + 401104: 22 d1 mov\.l 401190 <fn2\+0x190>,r1 ! 18 .* + 401106: 0c 31 add r0,r1 + 401108: 09 00 nop + 40110a: 09 00 nop + 40110c: 21 d2 mov\.l 401194 <fn2\+0x194>,r2 ! 1c .* + 40110e: 0c 32 add r0,r2 + 401110: 09 00 nop + 401112: 09 00 nop + 401114: 09 00 nop + 401116: 09 00 nop + 401118: 02 d0 mov\.l 401124 <fn2\+0x124>,r0 ! 14 .* + 40111a: 12 01 stc gbr,r1 + 40111c: ce 00 mov\.l @\(r0,r12\),r0 + 40111e: 03 a0 bra 401128 <fn2\+0x128> + 401120: 0c 31 add r0,r1 + 401122: 09 00 nop + 401124: 14 00 .*[ ]*.* + 401126: 00 00 .*[ ]*.* + 401128: 09 00 nop + 40112a: 09 00 nop + 40112c: 09 00 nop + 40112e: 09 00 nop + 401130: 02 d0 mov\.l 40113c <fn2\+0x13c>,r0 ! 18 .* + 401132: 12 01 stc gbr,r1 + 401134: ce 00 mov\.l @\(r0,r12\),r0 + 401136: 03 a0 bra 401140 <fn2\+0x140> + 401138: 1c 30 add r1,r0 + 40113a: 09 00 nop + 40113c: 18 00 .*[ ]*.* + 40113e: 00 00 .*[ ]*.* + 401140: 09 00 nop + 401142: 09 00 nop + 401144: 09 00 nop + 401146: 09 00 nop + 401148: 02 d0 mov\.l 401154 <fn2\+0x154>,r0 ! 8 .* + 40114a: 12 01 stc gbr,r1 + 40114c: 09 00 nop + 40114e: 03 a0 bra 401158 <fn2\+0x158> + 401150: 0c 31 add r0,r1 + 401152: 09 00 nop + 401154: 08 00 .*[ ]*.* + 401156: 00 00 .*[ ]*.* + 401158: 09 00 nop + 40115a: 09 00 nop + 40115c: 09 00 nop + 40115e: 09 00 nop + 401160: 02 d0 mov\.l 40116c <fn2\+0x16c>,r0 ! 18 .* + 401162: 12 01 stc gbr,r1 + 401164: 09 00 nop + 401166: 03 a0 bra 401170 <fn2\+0x170> + 401168: 0c 31 add r0,r1 + 40116a: 09 00 nop + 40116c: 18 00 .*[ ]*.* + 40116e: 00 00 .*[ ]*.* + 401170: 09 00 nop + 401172: 09 00 nop + 401174: 09 00 nop + 401176: 09 00 nop + 401178: e3 6f mov r14,r15 + 40117a: 26 4f lds\.l @r15\+,pr + 40117c: f6 6e mov\.l @r15\+,r14 + 40117e: 0b 00 rts + 401180: f6 6c mov\.l @r15\+,r12 + 401182: 09 00 nop + 401184: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 401186: 01 00 .*[ ]*.* + 401188: 10 00 .*[ ]*.* + 40118a: 00 00 .*[ ]*.* + 40118c: 14 00 .*[ ]*.* + 40118e: 00 00 .*[ ]*.* + 401190: 18 00 .*[ ]*.* + 401192: 00 00 .*[ ]*.* + 401194: 1c 00 .*[ ]*.* + \.\.\. + +00402000 <_start>: + 402000: c6 2f mov\.l r12,@-r15 + 402002: e6 2f mov\.l r14,@-r15 + 402004: f3 6e mov r15,r14 + 402006: 27 c7 mova 4020a4 <_start\+0xa4>,r0 + 402008: 26 dc mov\.l 4020a4 <_start\+0xa4>,r12 ! [0-9a-f]+ + 40200a: 0c 3c add r0,r12 + 40200c: 09 00 nop + 40200e: 09 00 nop + 402010: 09 00 nop + 402012: 09 00 nop + 402014: 02 d0 mov\.l 402020 <_start\+0x20>,r0 ! 10 .* + 402016: 12 01 stc gbr,r1 + 402018: ce 00 mov\.l @\(r0,r12\),r0 + 40201a: 03 a0 bra 402024 <_start\+0x24> + 40201c: 0c 31 add r0,r1 + 40201e: 09 00 nop + 402020: 10 00 .*[ ]*.* + 402022: 00 00 .*[ ]*.* + 402024: 09 00 nop + 402026: 09 00 nop + 402028: 09 00 nop + 40202a: 09 00 nop + 40202c: 02 d0 mov\.l 402038 <_start\+0x38>,r0 ! 20 .* + 40202e: 12 01 stc gbr,r1 + 402030: 09 00 nop + 402032: 03 a0 bra 40203c <_start\+0x3c> + 402034: 0c 31 add r0,r1 + 402036: 09 00 nop + 402038: 20 00 .*[ ]*.* + 40203a: 00 00 .*[ ]*.* + 40203c: 09 00 nop + 40203e: 09 00 nop + 402040: 09 00 nop + 402042: 09 00 nop + 402044: 02 d0 mov\.l 402050 <_start\+0x50>,r0 ! 2c + 402046: 12 01 stc gbr,r1 + 402048: 09 00 nop + 40204a: 03 a0 bra 402054 <_start\+0x54> + 40204c: 0c 31 add r0,r1 + 40204e: 09 00 nop + 402050: 2c 00 .*[ ]*.* + 402052: 00 00 .*[ ]*.* + 402054: 09 00 nop + 402056: 09 00 nop + 402058: 09 00 nop + 40205a: 09 00 nop + 40205c: 02 d0 mov\.l 402068 <_start\+0x68>,r0 ! 1c .* + 40205e: 12 01 stc gbr,r1 + 402060: 09 00 nop + 402062: 03 a0 bra 40206c <_start\+0x6c> + 402064: 0c 31 add r0,r1 + 402066: 09 00 nop + 402068: 1c 00 .*[ ]*.* + 40206a: 00 00 .*[ ]*.* + 40206c: 09 00 nop + 40206e: 09 00 nop + 402070: 09 00 nop + 402072: 09 00 nop + 402074: 12 01 stc gbr,r1 + 402076: 0c d0 mov\.l 4020a8 <_start\+0xa8>,r0 ! 8 .* + 402078: 1c 30 add r1,r0 + 40207a: 09 00 nop + 40207c: 09 00 nop + 40207e: 09 00 nop + 402080: 09 00 nop + 402082: 12 01 stc gbr,r1 + 402084: 09 d0 mov\.l 4020ac <_start\+0xac>,r0 ! 28 + 402086: 1c 30 add r1,r0 + 402088: 09 00 nop + 40208a: 09 00 nop + 40208c: 09 00 nop + 40208e: 09 00 nop + 402090: 12 01 stc gbr,r1 + 402092: 07 d0 mov\.l 4020b0 <_start\+0xb0>,r0 ! 18 .* + 402094: 1c 30 add r1,r0 + 402096: 09 00 nop + 402098: 09 00 nop + 40209a: 09 00 nop + 40209c: 09 00 nop + 40209e: e3 6f mov r14,r15 + 4020a0: 0b 00 rts + 4020a2: f6 6e mov\.l @r15\+,r14 + 4020a4: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + 4020a6: 01 00 .*[ ]*.* + 4020a8: 08 00 .*[ ]*.* + 4020aa: 00 00 .*[ ]*.* + 4020ac: 28 00 .*[ ]*.* + 4020ae: 00 00 .*[ ]*.* + 4020b0: 18 00 .*[ ]*.* + \.\.\. diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlsbin-2.d b/binutils-2.21/ld/testsuite/ld-sh/tlsbin-2.d new file mode 100644 index 0000000..cd30833 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlsbin-2.d @@ -0,0 +1,79 @@ +#source: tlsbinpic.s +#source: tlsbin.s +#as: -little +#ld: -EL tmpdir/tlsbin-0-dso.so +#readelf: -Ssrl +#target: sh*-*-linux* sh*-*-netbsd* + +There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+: + +Section Headers: + +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al + +\[ 0\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0 + +\[ 1\] \.interp .* + +\[ 2\] \.hash .* + +\[ 3\] \.dynsym .* + +\[ 4\] \.dynstr .* + +\[ 5\] \.rela\.dyn .* + +\[ 6\] \.rela\.plt .* + +\[ 7\] \.plt .* + +\[ 8\] \.text +PROGBITS .* + +\[ 9\] \.tdata +PROGBITS .* 0+018 00 WAT +0 +0 +4 + +\[10\] \.tbss +NOBITS .* 0+010 00 WAT +0 +0 +1 +#... + +\[[0-9a-f]+\] \.got +PROGBITS .* +#... + +\[[0-9a-f]+\] \.shstrtab .* + +\[[0-9a-f]+\] \.symtab .* + +\[[0-9a-f]+\] \.strtab .* +Key to Flags: +.* +.* +.* + +Elf file type is EXEC \(Executable file\) +Entry point 0x402000 +There are [0-9]+ program headers, starting at offset [0-9]+ + +Program Headers: + +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align + +PHDR.* + +INTERP.* +.*Requesting program interpreter.* + +LOAD.* + +LOAD.* + +DYNAMIC.* + +TLS +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x0+18 0x0+28 R +0x4 + + Section to Segment mapping: + +Segment Sections\.\.\. + +00 + + +01 +\.interp * + +02 +\.interp \.hash \.dynsym \.dynstr \.rela\.dyn \.rela\.plt \.plt \.text * + +03 +\.tdata \.dynamic \.got * + +04 +\.dynamic * + +05 +\.tdata \.tbss * + +Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 4 entries: + Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend +[0-9a-f ]+R_SH_TLS_TPOFF32 +0+ +sG3 \+ 0 +[0-9a-f ]+R_SH_TLS_TPOFF32 +0+ +sG2 \+ 0 +[0-9a-f ]+R_SH_TLS_TPOFF32 +0+ +sG4 \+ 0 +[0-9a-f ]+R_SH_TLS_TPOFF32 +0+ +sG1 \+ 0 + +Relocation section '\.rela\.plt' at offset 0x[0-9a-f]+ contains 1 entries: + Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend +[0-9a-f ]+R_SH_JMP_SLOT[0-9a-f ]+__tls_get_addr \+ [0-9a-f]+ + +Symbol table '\.dynsym' contains [0-9]+ entries: + +Num: +Value +Size +Type +Bind +Vis +Ndx +Name +.* NOTYPE +LOCAL +DEFAULT +UND * +.* TLS +GLOBAL +DEFAULT +UND sG3 +.* TLS +GLOBAL +DEFAULT +UND sG2 +.* TLS +GLOBAL +DEFAULT +UND sG4 +.* FUNC +GLOBAL +DEFAULT +UND __tls_get_addr +#... +.* TLS +GLOBAL +DEFAULT +UND sG1 +#... + +#pass diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlsbin-3.d b/binutils-2.21/ld/testsuite/ld-sh/tlsbin-3.d new file mode 100644 index 0000000..618ae59 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlsbin-3.d @@ -0,0 +1,12 @@ +#source: tlsbinpic.s +#source: tlsbin.s +#as: -little +#ld: -EL tmpdir/tlsbin-0-dso.so +#objdump: -sj.got +#target: sh*-*-linux* sh*-*-netbsd* + +.*: +file format elf32-sh.* + +Contents of section \.got: + [0-9a-f]+ [0-9a-f]+ 00000000 00000000 [0-9a-f]+ .* + [0-9a-f]+ 00000000 00000000 00000000 00000000 .* diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlsbin-4.d b/binutils-2.21/ld/testsuite/ld-sh/tlsbin-4.d new file mode 100644 index 0000000..b1683b8 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlsbin-4.d @@ -0,0 +1,12 @@ +#source: tlsbinpic.s +#source: tlsbin.s +#as: -little +#ld: -EL tmpdir/tlsbin-0-dso.so +#objdump: -sj.tdata +#target: sh*-*-linux* sh*-*-netbsd* + +.*: +file format elf32-sh.* + +Contents of section .tdata: + [0-9a-f]+ 11000000 12000000 41000000 42000000 .* + [0-9a-f]+ 01010000 02010000 +.* diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlsbin.s b/binutils-2.21/ld/testsuite/ld-sh/tlsbin.s new file mode 100644 index 0000000..642eb3d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlsbin.s @@ -0,0 +1,90 @@ + .section ".tbss", "awT", @nobits + .globl bg1, bg2 +bg1: .space 4 +bg2: .space 4 +bl1: .space 4 +bl2: .space 4 + .text + .globl _start + .type _start,@function +_start: + mov.l r12,@-r15 + mov.l r14,@-r15 + mov r15,r14 + ! Set up .GOT pointer for non-pic @gottpoff sequences + mova .L3,r0 + mov.l .L3,r12 + add r0,r12 + nop;nop;nop;nop + + ! @GOTTPOFF IE against global var + mov.l 1f,r0 + stc gbr,r1 + mov.l @(r0,r12),r0 + bra 2f + add r0,r1 + .align 2 +1: .long sG3@GOTTPOFF +2: + nop;nop;nop;nop + + ! @GOTTPOFF IE -> LE against global var defined in exec + mov.l 1f,r0 + stc gbr,r1 + mov.l @(r0,r12),r0 + bra 2f + add r0,r1 + .align 2 +1: .long bg1@GOTTPOFF +2: + nop;nop;nop;nop + + ! @GOTTPOFF IE -> LE against local var + mov.l 1f,r0 + stc gbr,r1 + mov.l @(r0,r12),r0 + bra 2f + add r0,r1 + .align 2 +1: .long bl2@GOTTPOFF +2: + nop;nop;nop;nop + + ! @GOTTPOFF IE -> LE against hidden but not local var + mov.l 1f,r0 + stc gbr,r1 + mov.l @(r0,r12),r0 + bra 2f + add r0,r1 + .align 2 +1: .long sh2@GOTTPOFF +2: + nop;nop;nop;nop + + ! LE @TPOFF, global var defined in exec + stc gbr,r1 + mov.l .L4,r0 + add r1,r0 + nop;nop;nop;nop + + ! LE @TPOFF, local var + stc gbr,r1 + mov.l .L5,r0 + add r1,r0 + nop;nop;nop;nop + + ! LE @TPOFF, hidden var defined in exec + stc gbr,r1 + mov.l .L6,r0 + add r1,r0 + nop;nop;nop;nop + + mov r14,r15 + rts + mov.l @r15+,r14 + + .align 2 +.L3: .long _GLOBAL_OFFSET_TABLE_ +.L4: .long sg1@TPOFF +.L5: .long bl1@TPOFF +.L6: .long sh1@TPOFF diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlsbinpic.s b/binutils-2.21/ld/testsuite/ld-sh/tlsbinpic.s new file mode 100644 index 0000000..cb8b361 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlsbinpic.s @@ -0,0 +1,206 @@ + ! Force .got aligned to 4K, so it very likely gets at 0x413000 + .data + .balign 4096 + .section ".tdata", "awT", @progbits + .globl sg1, sg2 + .globl sh1, sh2 + .hidden sh1, sh2 +sg1: .long 17 +sg2: .long 18 +sl1: .long 65 +sl2: .long 66 +sh1: .long 257 +sh2: .long 258 + ! Force .text aligned to 4K, so it very likely gets at 0x401000. + .text + .balign 4096 + .globl fn2 + .type fn2,@function +fn2: + mov.l r12,@-r15 + mov.l r14,@-r15 + sts.l pr,@-r15 + mova .L3,r0 + mov.l .L3,r12 + add r0,r12 + mov r15,r14 + nop;nop;nop;nop + + ! GD -> IE because variable is not defined in executable + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sG1@TLSGD +2: .long __tls_get_addr@PLT +3: + nop;nop;nop;nop + + ! GD -> IE because variable is not defined in executable where + ! the variable is referenced through @gottpoff too + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sG2@TLSGD +2: .long __tls_get_addr@PLT +3: + nop;nop;nop;nop + + ! GD -> LE with global variable defined in executable + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sg1@TLSGD +2: .long __tls_get_addr@PLT +3: + nop;nop;nop;nop + + ! GD -> LE with local variable defined in executable + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sl1@TLSGD +2: .long __tls_get_addr@PLT +3: + nop;nop;nop;nop + + ! GD -> LE with hidden variable defined in executable + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sh1@TLSGD +2: .long __tls_get_addr@PLT +3: + nop;nop;nop;nop + + ! LD -> LE with local variable defined in executable + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sl1@TLSLDM +2: .long __tls_get_addr@PLT +3: + nop;nop + mov.l .L4,r1 + add r0,r1 + nop;nop + mov.l .L5,r2 + add r0,r2 + nop;nop;nop;nop + + ! LD -> LE against hidden variables + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sh1@TLSLDM +2: .long __tls_get_addr@PLT +3: + nop;nop + mov.l .L6,r1 + add r0,r1 + nop;nop + mov.l .L7,r2 + add r0,r2 + nop;nop;nop;nop + + ! @GOTTPOFF IE against global var + mov.l 1f,r0 + stc gbr,r1 + mov.l @(r0,r12),r0 + bra 2f + add r0,r1 + .align 2 +1: .long sG2@GOTTPOFF +2: + nop;nop;nop;nop + + ! @GOTTPOFF IE against global var + mov.l 1f,r0 + stc gbr,r1 + mov.l @(r0,r12),r0 + bra 2f + add r1,r0 + .align 2 +1: .long sG4@GOTTPOFF +2: + nop;nop;nop;nop + + ! @GOTTPOFF IE -> LE against global var defined in exec + mov.l 1f,r0 + stc gbr,r1 + mov.l @(r0,r12),r0 + bra 2f + add r0,r1 + .align 2 +1: .long sg1@GOTTPOFF +2: + nop;nop;nop;nop + + ! @GOTTPOFF IE -> LE against hidden var + mov.l 1f,r0 + stc gbr,r1 + mov.l @(r0,r12),r0 + bra 2f + add r0,r1 + .align 2 +1: .long sh1@GOTTPOFF +2: + nop;nop;nop;nop + + mov r14,r15 + lds.l @r15+,pr + mov.l @r15+,r14 + rts + mov.l @r15+,r12 + + .align 2 +.L3: .long _GLOBAL_OFFSET_TABLE_ +.L4: .long sl1@DTPOFF +.L5: .long sl2@DTPOFF +.L6: .long sh1@DTPOFF +.L7: .long sh2@DTPOFF + ! Fill page with 0. + .space .L8-. + .balign 4096 +.L8: diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlslib.s b/binutils-2.21/ld/testsuite/ld-sh/tlslib.s new file mode 100644 index 0000000..35b6c70 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlslib.s @@ -0,0 +1,20 @@ + .section ".tdata", "awT", @progbits + .globl sG1, sG2, sG3, sG4, sG5, sG6, sG7, sG8 +sG1: .long 513 +sG2: .long 514 +sG3: .long 515 +sG4: .long 516 +sG5: .long 517 +sG6: .long 518 +sG7: .long 519 +sG8: .long 520 + + .text + .align 1 + ! Dummy. + .globl __tls_get_addr + .type __tls_get_addr,@function +__tls_get_addr: + rts + nop + diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlspic-1.d b/binutils-2.21/ld/testsuite/ld-sh/tlspic-1.d new file mode 100644 index 0000000..6638eda --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlspic-1.d @@ -0,0 +1,292 @@ +#source: tlspic1.s +#source: tlspic2.s +#as: -little +#ld: -shared -EL +#objdump: -drj.text +#target: sh*-*-linux* sh*-*-netbsd* + +.*: +file format elf32-sh.* + +Disassembly of section \.text: + +[0-9a-f]+ <fn1>: + [0-9a-f]+: c6 2f mov\.l r12,@-r15 + [0-9a-f]+: e6 2f mov\.l r14,@-r15 + [0-9a-f]+: 22 4f sts\.l pr,@-r15 + [0-9a-f]+: 83 c7 mova [0-9a-f]+ <fn1\+0x214>,r0 + [0-9a-f]+: 82 dc mov\.l [0-9a-f]+ <fn1\+0x214>,r12 ! [0-9a-f]+ + [0-9a-f]+: 0c 3c add r0,r12 + [0-9a-f]+: f3 6e mov r15,r14 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 04 d4 mov\.l [0-9a-f]+ <fn1\+0x28>,r4 ! 30 + [0-9a-f]+: 04 c7 mova [0-9a-f]+ <fn1\+0x2c>,r0 + [0-9a-f]+: 04 d1 mov\.l [0-9a-f]+ <fn1\+0x2c>,r1 ! [0-9a-f]+ + [0-9a-f]+: 0c 31 add r0,r1 + [0-9a-f]+: 0b 41 jsr @r1 + [0-9a-f]+: cc 34 add r12,r4 + [0-9a-f]+: 05 a0 bra [0-9a-f]+ <fn1\+0x30> + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 30 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 03 d0 mov\.l [0-9a-f]+ <fn1\+0x48>,r0 ! 38 + [0-9a-f]+: 12 04 stc gbr,r4 + [0-9a-f]+: ce 00 mov\.l @\(r0,r12\),r0 + [0-9a-f]+: 4c 30 add r4,r0 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 04 a0 bra [0-9a-f]+ <fn1\+0x50> + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 38 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 03 d4 mov\.l [0-9a-f]+ <fn1\+0x68>,r4 ! 10 .* + [0-9a-f]+: 04 c7 mova [0-9a-f]+ <fn1\+0x6c>,r0 + [0-9a-f]+: 03 d1 mov\.l [0-9a-f]+ <fn1\+0x6c>,r1 ! [0-9a-f]+ + [0-9a-f]+: 0c 31 add r0,r1 + [0-9a-f]+: 0b 41 jsr @r1 + [0-9a-f]+: cc 34 add r12,r4 + [0-9a-f]+: 04 a0 bra [0-9a-f]+ <fn1\+0x70> + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 10 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 03 d0 mov\.l [0-9a-f]+ <fn1\+0x88>,r0 ! 18 .* + [0-9a-f]+: 12 04 stc gbr,r4 + [0-9a-f]+: ce 00 mov\.l @\(r0,r12\),r0 + [0-9a-f]+: 4c 30 add r4,r0 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 04 a0 bra [0-9a-f]+ <fn1\+0x90> + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 18 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 03 d4 mov\.l [0-9a-f]+ <fn1\+0xa8>,r4 ! 3c + [0-9a-f]+: 04 c7 mova [0-9a-f]+ <fn1\+0xac>,r0 + [0-9a-f]+: 03 d1 mov\.l [0-9a-f]+ <fn1\+0xac>,r1 ! [0-9a-f]+ + [0-9a-f]+: 0c 31 add r0,r1 + [0-9a-f]+: 0b 41 jsr @r1 + [0-9a-f]+: cc 34 add r12,r4 + [0-9a-f]+: 04 a0 bra [0-9a-f]+ <fn1\+0xb0> + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 3c 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 03 d0 mov\.l [0-9a-f]+ <fn1\+0xc8>,r0 ! 44 + [0-9a-f]+: 12 04 stc gbr,r4 + [0-9a-f]+: ce 00 mov\.l @\(r0,r12\),r0 + [0-9a-f]+: 4c 30 add r4,r0 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 04 a0 bra [0-9a-f]+ <fn1\+0xd0> + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 44 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 03 d4 mov\.l [0-9a-f]+ <fn1\+0xe8>,r4 ! 24 + [0-9a-f]+: 04 c7 mova [0-9a-f]+ <fn1\+0xec>,r0 + [0-9a-f]+: 03 d1 mov\.l [0-9a-f]+ <fn1\+0xec>,r1 ! [0-9a-f]+ + [0-9a-f]+: 0c 31 add r0,r1 + [0-9a-f]+: 0b 41 jsr @r1 + [0-9a-f]+: cc 34 add r12,r4 + [0-9a-f]+: 04 a0 bra [0-9a-f]+ <fn1\+0xf0> + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 24 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 03 d0 mov\.l [0-9a-f]+ <fn1\+0x108>,r0 ! 2c + [0-9a-f]+: 12 04 stc gbr,r4 + [0-9a-f]+: ce 00 mov\.l @\(r0,r12\),r0 + [0-9a-f]+: 4c 30 add r4,r0 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 04 a0 bra [0-9a-f]+ <fn1\+0x110> + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 2c 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 03 d4 mov\.l [0-9a-f]+ <fn1\+0x128>,r4 ! 1c .* + [0-9a-f]+: 04 c7 mova [0-9a-f]+ <fn1\+0x12c>,r0 + [0-9a-f]+: 03 d1 mov\.l [0-9a-f]+ <fn1\+0x12c>,r1 ! [0-9a-f]+ + [0-9a-f]+: 0c 31 add r0,r1 + [0-9a-f]+: 0b 41 jsr @r1 + [0-9a-f]+: cc 34 add r12,r4 + [0-9a-f]+: 04 a0 bra [0-9a-f]+ <fn1\+0x130> + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 1c 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 38 d1 mov\.l [0-9a-f]+ <fn1\+0x218>,r1 ! 8 .* + [0-9a-f]+: 0c 31 add r0,r1 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 37 d2 mov\.l [0-9a-f]+ <fn1\+0x21c>,r2 ! c .* + [0-9a-f]+: 0c 32 add r0,r2 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 03 d4 .*[ ]*.* + [0-9a-f]+: 04 c7 .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: 0b 41 jsr @r1 + [0-9a-f]+: cc 34 add r12,r4 + [0-9a-f]+: 04 a0 bra [0-9a-f]+ <fn1\+0x160> + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 1c 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 2e d1 mov\.l [0-9a-f]+ <fn1\+0x220>,r1 ! 10 .* + [0-9a-f]+: 0c 31 add r0,r1 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 2d d2 mov\.l [0-9a-f]+ <fn1\+0x224>,r2 ! 14 .* + [0-9a-f]+: 0c 32 add r0,r2 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 03 d4 mov\.l [0-9a-f]+ <fn1\+0x188>,r4 ! 1c .* + [0-9a-f]+: 04 c7 mova [0-9a-f]+ <fn1\+0x18c>,r0 + [0-9a-f]+: 03 d1 mov\.l [0-9a-f]+ <fn1\+0x18c>,r1 ! [0-9a-f]+ + [0-9a-f]+: 0c 31 add r0,r1 + [0-9a-f]+: 0b 41 jsr @r1 + [0-9a-f]+: cc 34 add r12,r4 + [0-9a-f]+: 04 a0 bra [0-9a-f]+ <fn1\+0x190> + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 1c 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 24 d1 mov\.l [0-9a-f]+ <fn1\+0x228>,r1 ! 18 .* + [0-9a-f]+: 0c 31 add r0,r1 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 23 d2 mov\.l [0-9a-f]+ <fn1\+0x22c>,r2 ! 1c .* + [0-9a-f]+: 0c 32 add r0,r2 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 02 d0 mov\.l [0-9a-f]+ <fn1\+0x1b4>,r0 ! 38 + [0-9a-f]+: 12 01 stc gbr,r1 + [0-9a-f]+: ce 00 mov\.l @\(r0,r12\),r0 + [0-9a-f]+: 03 a0 bra [0-9a-f]+ <fn1\+0x1b8> + [0-9a-f]+: 0c 31 add r0,r1 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 38 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 02 d0 mov\.l [0-9a-f]+ <fn1\+0x1cc>,r0 ! 18 .* + [0-9a-f]+: 12 01 stc gbr,r1 + [0-9a-f]+: ce 00 mov\.l @\(r0,r12\),r0 + [0-9a-f]+: 03 a0 bra [0-9a-f]+ <fn1\+0x1d0> + [0-9a-f]+: 0c 31 add r0,r1 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 18 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 02 d0 mov\.l [0-9a-f]+ <fn1\+0x1e4>,r0 ! 44 + [0-9a-f]+: 12 01 stc gbr,r1 + [0-9a-f]+: ce 00 mov\.l @\(r0,r12\),r0 + [0-9a-f]+: 03 a0 bra [0-9a-f]+ <fn1\+0x1e8> + [0-9a-f]+: 0c 31 add r0,r1 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 44 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 02 d0 mov\.l [0-9a-f]+ <fn1\+0x1fc>,r0 ! 2c + [0-9a-f]+: 12 01 stc gbr,r1 + [0-9a-f]+: ce 00 mov\.l @\(r0,r12\),r0 + [0-9a-f]+: 03 a0 bra [0-9a-f]+ <fn1\+0x200> + [0-9a-f]+: 0c 31 add r0,r1 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 2c 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 09 00 nop + [0-9a-f]+: e3 6f mov r14,r15 + [0-9a-f]+: 26 4f lds\.l @r15\+,pr + [0-9a-f]+: f6 6e mov\.l @r15\+,r14 + [0-9a-f]+: 0b 00 rts + [0-9a-f]+: f6 6c mov\.l @r15\+,r12 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: 01 00 .*[ ]*.* + [0-9a-f]+: 08 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: 0c 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: 10 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: 14 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: 18 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: 1c 00 .*[ ]*.* + \.\.\. diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlspic-2.d b/binutils-2.21/ld/testsuite/ld-sh/tlspic-2.d new file mode 100644 index 0000000..4005299 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlspic-2.d @@ -0,0 +1,79 @@ +#source: tlspic1.s +#source: tlspic2.s +#as: -little +#ld: -shared -EL +#readelf: -Ssrl +#target: sh*-*-linux* sh*-*-netbsd* + +There are [0-9]+ section headers, starting at offset 0x[0-9a-f]+: + +Section Headers: + +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al + +\[ 0\] +NULL +0+ 0+ 0+ 0+ +0 +0 +0 + +\[ 1\] \.hash .* + +\[ 2\] \.dynsym .* + +\[ 3\] \.dynstr .* + +\[ 4\] \.rela\.dyn .* + +\[ 5\] \.rela\.plt .* + +\[ 6\] \.plt .* + +\[ 7\] \.text +PROGBITS .* + +\[ 8\] \.tdata +PROGBITS .* 0+18 00 WAT +0 +0 +4 + +\[ 9\] \.tbss +NOBITS .* 0+08 00 WAT +0 +0 +1 +#... + +\[[0-9a-f]+\] \.got +PROGBITS .* +#... + +\[[0-9a-f]+\] \.shstrtab .* + +\[[0-9a-f]+\] \.symtab .* + +\[[0-9a-f]+\] \.strtab .* +Key to Flags: +.* +.* +.* + +Elf file type is DYN \(Shared object file\) +Entry point 0x[0-9a-f]+ +There are 4 program headers, starting at offset [0-9]+ + +Program Headers: + +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg Align + +LOAD.* + +LOAD.* + +DYNAMIC.* + +TLS .* 0x0+18 0x0+20 R +0x4 + + Section to Segment mapping: + +Segment Sections\.\.\. + +00 +\.hash \.dynsym \.dynstr \.rela\.dyn \.rela\.plt \.plt \.text * + +01 +\.tdata \.dynamic \.got * + +02 +\.dynamic * + +03 +\.tdata \.tbss * + +Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 10 entries: + Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend +[0-9a-f ]+R_SH_TLS_DTPMOD32 +0+00 +[0-9a-f ]+R_SH_TLS_TPOFF32 +0+0c +[0-9a-f ]+R_SH_TLS_DTPMOD32 +0+00 +[0-9a-f ]+R_SH_TLS_DTPMOD32 +0+00 +[0-9a-f ]+R_SH_TLS_TPOFF32 +0+1c +[0-9a-f ]+R_SH_TLS_DTPMOD32 +0+00 +[0-9a-f ]+R_SH_TLS_TPOFF32 +0+14 +[0-9a-f ]+R_SH_TLS_DTPMOD32 +0+ +sg1 \+ 0 +[0-9a-f ]+R_SH_TLS_DTPOFF32 +0+ +sg1 \+ 0 +[0-9a-f ]+R_SH_TLS_TPOFF32 +0+04 +sg2 \+ 0 + +Relocation section '\.rela\.plt' at offset 0x[0-9a-f]+ contains 1 entries: + Offset +Info +Type +Sym\.Value +Sym\. Name \+ Addend +[0-9a-f ]+R_SH_JMP_SLOT[0-9a-f ]+__tls_get_addr \+ [0-9a-f]+ + +Symbol table '\.dynsym' contains [0-9]+ entries: + +Num: +Value +Size +Type +Bind +Vis +Ndx +Name +.* NOTYPE +LOCAL +DEFAULT +UND * +.* NOTYPE +GLOBAL +DEFAULT +UND __tls_get_addr +.* TLS +GLOBAL +DEFAULT +8 sg1 +#... +.* FUNC +GLOBAL +DEFAULT +7 fn1 +#... +.* TLS +GLOBAL +DEFAULT +8 sg2 +#... + +#pass diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlspic-3.d b/binutils-2.21/ld/testsuite/ld-sh/tlspic-3.d new file mode 100644 index 0000000..6e79989 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlspic-3.d @@ -0,0 +1,15 @@ +#source: tlspic1.s +#source: tlspic2.s +#as: -little +#ld: -shared -EL +#objdump: -sj.got +#target: sh*-*-linux* sh*-*-netbsd* + +.*: +file format elf32-sh.* + +Contents of section \.got: + [0-9a-f]+ [0-9a-f]+ 00000000 00000000 [0-9a-f]+ .* + [0-9a-f]+ 00000000 08000000 00000000 00000000 .* + [0-9a-f]+ 00000000 00000000 18000000 00000000 .* + [0-9a-f]+ 00000000 00000000 00000000 00000000 .* + [0-9a-f]+ 10000000 00000000 +.* diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlspic-4.d b/binutils-2.21/ld/testsuite/ld-sh/tlspic-4.d new file mode 100644 index 0000000..263c5d6 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlspic-4.d @@ -0,0 +1,12 @@ +#source: tlspic1.s +#source: tlspic2.s +#as: -little +#ld: -shared -EL +#objdump: -sj.tdata +#target: sh*-*-linux* sh*-*-netbsd* + +.*: +file format elf32-sh.* + +Contents of section \.tdata: + [0-9a-f]+ 11000000 12000000 41000000 42000000 .* + [0-9a-f]+ 01010000 02010000 +.* diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlspic1.s b/binutils-2.21/ld/testsuite/ld-sh/tlspic1.s new file mode 100644 index 0000000..153709a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlspic1.s @@ -0,0 +1,267 @@ + .section ".tdata", "awT", @progbits + .globl sg1, sg2 + .globl sh1, sh2 + .hidden sh1, sh2 +sg1: .long 17 +sg2: .long 18 +sl1: .long 65 +sl2: .long 66 +sh1: .long 257 +sh2: .long 258 + .text + .align 1 + .globl fn1 + .type fn1,@function +fn1: + mov.l r12,@-r15 + mov.l r14,@-r15 + sts.l pr,@-r15 + mova .L3,r0 + mov.l .L3,r12 + add r0,r12 + mov r15,r14 + nop;nop;nop;nop + + ! GD + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sg1@TLSGD +2: .long __tls_get_addr@PLT +3: + nop;nop;nop;nop + + ! GD -> IE because variable is referenced through @GOTTPOFF too + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sg2@TLSGD +2: .long __tls_get_addr@PLT +3: + nop;nop;nop;nop + + ! GD against local variable + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sl1@TLSGD +2: .long __tls_get_addr@PLT +3: + nop;nop;nop;nop + + ! GD -> IE against local variable referenced through @GOTTPOFF too + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sl2@TLSGD +2: .long __tls_get_addr@PLT +3: + nop;nop;nop;nop + + ! GD against hidden and local variable + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sh1@TLSGD +2: .long __tls_get_addr@PLT +3: + nop;nop;nop;nop + + ! GD -> IE against hidden and local variable referenced through + ! @GOTTPOFF too + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sh2@TLSGD +2: .long __tls_get_addr@PLT +3: + nop;nop;nop;nop + + ! GD against hidden but not local variable + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sH1@TLSGD +2: .long __tls_get_addr@PLT +3: + nop;nop;nop;nop + + ! GD -> IE against hidden but not local variable referenced through + ! @GOTTPOFF too + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sH2@TLSGD +2: .long __tls_get_addr@PLT +3: + nop;nop;nop;nop + + ! LD + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sl1@TLSLDM +2: .long __tls_get_addr@PLT +3: + nop;nop + mov.l .L4,r1 + add r0,r1 + nop;nop + mov.l .L5,r2 + add r0,r2 + nop;nop;nop;nop + + ! LD against hidden and local variables + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sl1@TLSLDM +2: .long __tls_get_addr@PLT +3: + nop;nop + mov.l .L6,r1 + add r0,r1 + nop;nop + mov.l .L7,r2 + add r0,r2 + nop;nop;nop;nop + + ! LD against hidden but not local variables + mov.l 1f,r4 + mova 2f,r0 + mov.l 2f,r1 + add r0,r1 + jsr @r1 + add r12,r4 + bra 3f + nop + .align 2 +1: .long sH1@TLSLDM +2: .long __tls_get_addr@PLT +3: + nop;nop + mov.l .L8,r1 + add r0,r1 + nop;nop + mov.l .L9,r2 + add r0,r2 + nop;nop;nop;nop + + ! @GOTTPOFF IE against global var + mov.l 1f,r0 + stc gbr,r1 + mov.l @(r0,r12),r0 + bra 2f + add r0,r1 + .align 2 +1: .long sg2@GOTTPOFF +2: + nop;nop;nop;nop + + ! @GOTTPOFF IE against local var + mov.l 1f,r0 + stc gbr,r1 + mov.l @(r0,r12),r0 + bra 2f + add r0,r1 + .align 2 +1: .long sl2@GOTTPOFF +2: + nop;nop;nop;nop + + ! @GOTTPOFF IE against hidden and local var + mov.l 1f,r0 + stc gbr,r1 + mov.l @(r0,r12),r0 + bra 2f + add r0,r1 + .align 2 +1: .long sh2@GOTTPOFF +2: + nop;nop;nop;nop + + ! @GOTTPOFF IE against hidden but not local var + mov.l 1f,r0 + stc gbr,r1 + mov.l @(r0,r12),r0 + bra 2f + add r0,r1 + .align 2 +1: .long sH2@GOTTPOFF +2: + nop;nop;nop;nop + + mov r14,r15 + lds.l @r15+,pr + mov.l @r15+,r14 + rts + mov.l @r15+,r12 + + .align 2 +.L3: .long _GLOBAL_OFFSET_TABLE_ +.L4: .long sl1@DTPOFF +.L5: .long sl1@DTPOFF + 4 +.L6: .long sh1@DTPOFF +.L7: .long sh2@DTPOFF +.L8: .long sH1@DTPOFF +.L9: .long sH2@DTPOFF diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlspic2.s b/binutils-2.21/ld/testsuite/ld-sh/tlspic2.s new file mode 100644 index 0000000..35319ba --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlspic2.s @@ -0,0 +1,5 @@ + .section ".tbss", "awT", @nobits + .globl sH1, sH2 + .hidden sH1, sH2 +sH1: .space 4 +sH2: .space 4 diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlstpoff-1.d b/binutils-2.21/ld/testsuite/ld-sh/tlstpoff-1.d new file mode 100644 index 0000000..a678596 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlstpoff-1.d @@ -0,0 +1,31 @@ +#source: tlstpoff1.s +#source: tlstpoff2.s +#as: -little +#ld: -EL -e foo +#objdump: -drj.text +#target: sh*-*-linux* sh*-*-netbsd* + +.*: +file format elf32-sh.* + +Disassembly of section \.text: + +[0-9a-f]+ <foo>: + [0-9a-f]+: c6 2f mov.l r12,@-r15 + [0-9a-f]+: 07 c7 mova [0-9a-f]+ <foo\+0x20>,r0 + [0-9a-f]+: 06 dc mov.l [0-9a-f]+ <foo\+0x20>,r12 ! [0-9a-f]+ + [0-9a-f]+: 0c 3c add r0,r12 + [0-9a-f]+: 02 d0 mov.l [0-9a-f]+ <foo\+0x14>,r0 ! c + [0-9a-f]+: 12 01 stc gbr,r1 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 03 a0 bra [0-9a-f]+ <foo\+0x18> + [0-9a-f]+: 0c 31 add r0,r1 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: 0c 00 .*[ ]*.* + [0-9a-f]+: 00 00 .*[ ]*.* + [0-9a-f]+: 12 60 mov.l @r1,r0 + [0-9a-f]+: 0b 00 rts + [0-9a-f]+: f6 6c mov.l @r15\+,r12 + [0-9a-f]+: 09 00 nop + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* + [0-9a-f]+: [0-9a-f]+ [0-9a-f]+ .*[ ]*.* +#pass diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlstpoff-2.d b/binutils-2.21/ld/testsuite/ld-sh/tlstpoff-2.d new file mode 100644 index 0000000..519c6ef --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlstpoff-2.d @@ -0,0 +1,8 @@ +#source: tlstpoff1.s +#source: tlstpoff2.s +#as: -little +#ld: -EL -e foo +#readelf: -r +#target: sh*-*-linux* sh*-*-netbsd* + +There are no relocations in this file. diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlstpoff1.s b/binutils-2.21/ld/testsuite/ld-sh/tlstpoff1.s new file mode 100644 index 0000000..754f3c1 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlstpoff1.s @@ -0,0 +1,23 @@ + .text + .align 5 + .global foo + .type foo, @function +foo: + mov.l r12,@-r15 + mova .L1,r0 + mov.l .L1,r12 + add r0,r12 + mov.l 1f,r0 + stc gbr,r1 + mov.l @(r0,r12),r0 + bra 2f + add r0,r1 + .align 2 +1: .long x@GOTTPOFF +2: + mov.l @r1,r0 + rts + mov.l @r15+,r12 + + .align 2 +.L1: .long _GLOBAL_OFFSET_TABLE_ diff --git a/binutils-2.21/ld/testsuite/ld-sh/tlstpoff2.s b/binutils-2.21/ld/testsuite/ld-sh/tlstpoff2.s new file mode 100644 index 0000000..6ae9e92 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/tlstpoff2.s @@ -0,0 +1,26 @@ + .section .tbss,"awT",@nobits + .global x +y: .space 4 +x: .space 4 + + .section barfn,"ax",@progbits + .align 1 + .type bar, @function +bar: + mova .L1,r0 + mov.l .L1,r12 + add r0,r12 + mov.l 1f,r0 + stc gbr,r1 + mov.l @(r0,r12),r0 + bra 2f + add r0,r1 + .align 2 +1: .long x@GOTTPOFF +2: + mov.l @r1,r0 + rts + mov.l @r15+,r12 + + .align 2 +.L1: .long _GLOBAL_OFFSET_TABLE_ diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks1-le.dd b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-le.dd new file mode 100644 index 0000000..03c817c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-le.dd @@ -0,0 +1,73 @@ + +.*: file format .* + +Disassembly of section \.plt: + +00080800 <_PROCEDURE_LINKAGE_TABLE_>: + 80800: 01 d1 mov\.l 80808 <_PROCEDURE_LINKAGE_TABLE_\+0x8>,r1 ! 81408 + 80802: 12 61 mov\.l @r1,r1 + 80804: 2b 41 jmp @r1 + 80806: 09 00 nop + 80808: 08 14 .* + 80808: R_SH_DIR32 _GLOBAL_OFFSET_TABLE_\+0x8 + 8080a: 08 00 .* + +0008080c <_sglobal@plt>: + 8080c: 01 d0 mov\.l 80814 <_sglobal@plt\+0x8>,r0 ! 8140c + 8080e: 02 60 mov\.l @r0,r0 + 80810: 2b 40 jmp @r0 + 80812: 09 00 nop + 80814: 0c 14 .* + 80814: R_SH_DIR32 _GLOBAL_OFFSET_TABLE_\+0xc + 80816: 08 00 .* + 80818: 01 d0 mov\.l 80820 <_sglobal@plt\+0x14>,r0 ! 0 + 8081a: f1 af bra 80800 <_PROCEDURE_LINKAGE_TABLE_> + 8081c: 09 00 nop + 8081e: 09 00 nop + 80820: 00 00 .* + \.\.\. + +00080824 <_foo@plt>: + 80824: 01 d0 mov\.l 8082c <_foo@plt\+0x8>,r0 ! 81410 + 80826: 02 60 mov\.l @r0,r0 + 80828: 2b 40 jmp @r0 + 8082a: 09 00 nop + 8082c: 10 14 .* + 8082c: R_SH_DIR32 _GLOBAL_OFFSET_TABLE_\+0x10 + 8082e: 08 00 .* + 80830: 01 d0 mov\.l 80838 <_foo@plt\+0x14>,r0 ! c + 80832: e5 af bra 80800 <_PROCEDURE_LINKAGE_TABLE_> + 80834: 09 00 nop + 80836: 09 00 nop + 80838: 0c 00 .* + \.\.\. +Disassembly of section \.text: + +00080c00 <__start>: + 80c00: 22 4f sts\.l pr,@-r15 + 80c02: 06 d0 mov\.l 80c1c <__start\+0x1c>,r0 ! 80824 <_foo@plt> + 80c04: 0b 40 jsr @r0 + 80c06: 09 00 nop + 80c08: 05 d0 mov\.l 80c20 <__start\+0x20>,r0 ! 8080c <_sglobal@plt> + 80c0a: 0b 40 jsr @r0 + 80c0c: 09 00 nop + 80c0e: 05 d0 mov\.l 80c24 <__start\+0x24>,r0 ! 80c28 <_sexternal> + 80c10: 0b 40 jsr @r0 + 80c12: 09 00 nop + 80c14: 26 4f lds\.l @r15\+,pr + 80c16: 0b 00 rts + 80c18: 09 00 nop + 80c1a: 09 00 nop + 80c1c: 24 08 .* + 80c1c: R_SH_DIR32 \.plt\+0x24 + 80c1e: 08 00 .* + 80c20: 0c 08 .* + 80c20: R_SH_DIR32 \.plt\+0xc + 80c22: 08 00 .* + 80c24: 28 0c .* + 80c24: R_SH_DIR32 _sexternal + 80c26: 08 00 .* + +00080c28 <_sexternal>: + 80c28: 0b 00 rts + 80c2a: 09 00 nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib-le.dd b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib-le.dd new file mode 100644 index 0000000..6511c16 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib-le.dd @@ -0,0 +1,76 @@ + +.*: file format .* + +Disassembly of section \.plt: + +00080800 <_PROCEDURE_LINKAGE_TABLE_>: + 80800: 01 d0 mov\.l 80808 <_PROCEDURE_LINKAGE_TABLE_\+0x8>,r0 ! c + 80802: ce 00 mov\.l @\(r0,r12\),r0 + 80804: 2b 40 jmp @r0 + 80806: 09 00 nop + 80808: 0c 00 .* + 8080a: 00 00 .* + 8080c: 01 d0 mov\.l 80814 <_PROCEDURE_LINKAGE_TABLE_\+0x14>,r0 ! 0 + 8080e: c2 51 mov\.l @\(8,r12\),r1 + 80810: 2b 41 jmp @r1 + 80812: 09 00 nop + 80814: 00 00 .* + \.\.\. + +00080818 <_sexternal@plt>: + 80818: 01 d0 mov\.l 80820 <_sexternal@plt\+0x8>,r0 ! 10 + 8081a: ce 00 mov\.l @\(r0,r12\),r0 + 8081c: 2b 40 jmp @r0 + 8081e: 09 00 nop + 80820: 10 00 .* + 80822: 00 00 .* + 80824: 01 d0 mov\.l 8082c <_sexternal@plt\+0x14>,r0 ! c + 80826: c2 51 mov\.l @\(8,r12\),r1 + 80828: 2b 41 jmp @r1 + 8082a: 09 00 nop + 8082c: 0c 00 .* + \.\.\. +Disassembly of section \.text: + +00080c00 <_foo>: + 80c00: c6 2f mov\.l r12,@-r15 + 80c02: 22 4f sts\.l pr,@-r15 + 80c04: 0a dc mov\.l 80c30 <_foo\+0x30>,r12 ! 0 + 80c06: c2 6c mov\.l @r12,r12 + 80c08: 0a d0 mov\.l 80c34 <_foo\+0x34>,r0 ! 0 + 80c0a: ce 0c mov\.l @\(r0,r12\),r12 + 80c0c: 0a d0 mov\.l 80c38 <_foo\+0x38>,r0 ! 14 + 80c0e: ce 01 mov\.l @\(r0,r12\),r1 + 80c10: 12 62 mov\.l @r1,r2 + 80c12: 01 72 add #1,r2 + 80c14: 22 21 mov\.l r2,@r1 + 80c16: 09 d0 mov\.l 80c3c <_foo\+0x3c>,r0 ! 2c + 80c18: 03 00 bsrf r0 + 80c1a: 09 00 nop + 80c1c: 08 d0 mov\.l 80c40 <_foo\+0x40>,r0 ! fffffbde + 80c1e: 03 00 bsrf r0 + 80c20: 09 00 nop + 80c22: 08 d0 mov\.l 80c44 <_foo\+0x44>,r0 ! fffffbf0 + 80c24: 03 00 bsrf r0 + 80c26: 09 00 nop + 80c28: 26 4f lds\.l @r15\+,pr + 80c2a: 0b 00 rts + 80c2c: f6 6c mov\.l @r15\+,r12 + 80c2e: 09 00 nop + ... + 80c38: 14 00 .* + 80c3a: 00 00 .* + 80c3c: 2c 00 .* + 80c3e: 00 00 .* + 80c40: de fb .* + 80c42: ff ff .* + 80c44: f0 fb .* + 80c46: ff ff .* + +00080c48 <_slocal>: + 80c48: 0b 00 rts + 80c4a: 09 00 nop + +00080c4c <_sglobal>: + 80c4c: 0b 00 rts + 80c4e: 09 00 nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib.dd b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib.dd new file mode 100644 index 0000000..e20f334 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib.dd @@ -0,0 +1,76 @@ + +.*: file format .* + +Disassembly of section \.plt: + +00080800 <_PROCEDURE_LINKAGE_TABLE_>: + 80800: d0 01 mov\.l 80808 <_PROCEDURE_LINKAGE_TABLE_\+0x8>,r0 ! c + 80802: 00 ce mov\.l @\(r0,r12\),r0 + 80804: 40 2b jmp @r0 + 80806: 00 09 nop + 80808: 00 00 .* + 8080a: 00 0c .* + 8080c: d0 01 mov\.l 80814 <_PROCEDURE_LINKAGE_TABLE_\+0x14>,r0 ! 0 + 8080e: 51 c2 mov\.l @\(8,r12\),r1 + 80810: 41 2b jmp @r1 + 80812: 00 09 nop + 80814: 00 00 .* + \.\.\. + +00080818 <_sexternal@plt>: + 80818: d0 01 mov\.l 80820 <_sexternal@plt\+0x8>,r0 ! 10 + 8081a: 00 ce mov\.l @\(r0,r12\),r0 + 8081c: 40 2b jmp @r0 + 8081e: 00 09 nop + 80820: 00 00 .* + 80822: 00 10 .* + 80824: d0 01 mov\.l 8082c <_sexternal@plt\+0x14>,r0 ! c + 80826: 51 c2 mov\.l @\(8,r12\),r1 + 80828: 41 2b jmp @r1 + 8082a: 00 09 nop + 8082c: 00 00 .* + 8082e: 00 0c .* +Disassembly of section \.text: + +00080c00 <_foo>: + 80c00: 2f c6 mov\.l r12,@-r15 + 80c02: 4f 22 sts\.l pr,@-r15 + 80c04: dc 0a mov\.l 80c30 <_foo\+0x30>,r12 ! 0 + 80c06: 6c c2 mov\.l @r12,r12 + 80c08: d0 0a mov\.l 80c34 <_foo\+0x34>,r0 ! 0 + 80c0a: 0c ce mov\.l @\(r0,r12\),r12 + 80c0c: d0 0a mov\.l 80c38 <_foo\+0x38>,r0 ! 14 + 80c0e: 01 ce mov\.l @\(r0,r12\),r1 + 80c10: 62 12 mov\.l @r1,r2 + 80c12: 72 01 add #1,r2 + 80c14: 21 22 mov\.l r2,@r1 + 80c16: d0 09 mov\.l 80c3c <_foo\+0x3c>,r0 ! 2c + 80c18: 00 03 bsrf r0 + 80c1a: 00 09 nop + 80c1c: d0 08 mov\.l 80c40 <_foo\+0x40>,r0 ! fffffbde + 80c1e: 00 03 bsrf r0 + 80c20: 00 09 nop + 80c22: d0 08 mov\.l 80c44 <_foo\+0x44>,r0 ! fffffbf0 + 80c24: 00 03 bsrf r0 + 80c26: 00 09 nop + 80c28: 4f 26 lds\.l @r15\+,pr + 80c2a: 00 0b rts + 80c2c: 6c f6 mov\.l @r15\+,r12 + 80c2e: 00 09 nop + ... + 80c38: 00 00 .* + 80c3a: 00 14 .* + 80c3c: 00 00 .* + 80c3e: 00 2c .* + 80c40: ff ff .* + 80c42: fb de .* + 80c44: ff ff .* + 80c46: fb f0 .* + +00080c48 <_slocal>: + 80c48: 00 0b rts + 80c4a: 00 09 nop + +00080c4c <_sglobal>: + 80c4c: 00 0b rts + 80c4e: 00 09 nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib.nd b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib.nd new file mode 100644 index 0000000..e9f916e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib.nd @@ -0,0 +1,9 @@ +#... +Symbol table '\.dynsym' .*: +#... +.*: 00081400 +0 +OBJECT +GLOBAL +DEFAULT +[0-9]+ _GLOBAL_OFFSET_TABLE_ +#... +Symbol table '\.symtab' .*: +#... +.*: 00081400 +0 +OBJECT +GLOBAL +DEFAULT +[0-9]+ _GLOBAL_OFFSET_TABLE_ +#pass diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib.rd b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib.rd new file mode 100644 index 0000000..d9c56a0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib.rd @@ -0,0 +1,12 @@ + +Relocation section '\.rela\.plt' at offset .* contains 2 entries: + Offset Info Type Sym\.Value Sym\. Name \+ Addend +0008140c .*a4 R_SH_JMP_SLOT 00080c4c _sglobal \+ 0 +00081410 .*a4 R_SH_JMP_SLOT 00000000 _sexternal \+ 0 + +Relocation section '\.rela\.dyn' at offset .* contains 4 entries: + Offset Info Type Sym\.Value Sym\. Name \+ Addend +00081800 000000a5 R_SH_RELATIVE * 00080c48 +00080c30 .*01 R_SH_DIR32 00000000 ___GOTT_BASE__ \+ 0 +00080c34 .*01 R_SH_DIR32 00000000 ___GOTT_INDEX__ \+ 0 +00081414 .*a3 R_SH_GLOB_DAT 00081c00 x \+ 0 diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib.s b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib.s new file mode 100644 index 0000000..ff21564 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib.s @@ -0,0 +1,61 @@ + .text + .globl _foo + .type _foo, %function +_foo: + mov.l r12,@-r15 + sts.l pr,@-r15 + mov.l 1f,r12 + mov.l @r12,r12 + mov.l 2f,r0 + mov.l @(r0,r12),r12 + + mov.l 3f,r0 + mov.l @(r0,r12),r1 + mov.l @r1,r2 + add #1,r2 + mov.l r2,@r1 + + mov.l 4f,r0 + bsrf r0 + nop +.Lb4: + + mov.l 5f,r0 + bsrf r0 + nop +.Lb5: + + mov.l 6f,r0 + bsrf r0 + nop +.Lb6: + + lds.l @r15+,pr + rts + mov.l @r15+,r12 + .align 2 +1: .long ___GOTT_BASE__ +2: .long ___GOTT_INDEX__ +3: .long x@GOT +4: .long _slocal - .Lb4 +5: .long _sglobal@PLT - (.Lb5 - .) +6: .long _sexternal@PLT - (.Lb6 - .) + .size _foo, .-_foo + + .type _slocal, %function +_slocal: + rts + nop + .size _slocal, .-_slocal + + .globl _sglobal + .type _sglobal, %function +_sglobal: + rts + nop + .size _sglobal, .-_sglobal + + .data + .4byte _slocal + + .comm x,4,4 diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib.td b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib.td new file mode 100644 index 0000000..9f223e3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-lib.td @@ -0,0 +1,3 @@ +#... + 0x0+16 \(TEXTREL\) +0x0 +#pass diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks1-static.d b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-static.d new file mode 100644 index 0000000..dffc45b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks1-static.d @@ -0,0 +1,4 @@ +#name: VxWorks executable test 1 (static) +#source: vxworks1.s +#ld: tmpdir/libvxworks1.so -Tvxworks1.ld -EL +#error: Dynamic sections created in non-dynamic link diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks1.dd b/binutils-2.21/ld/testsuite/ld-sh/vxworks1.dd new file mode 100644 index 0000000..4bb3b47 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks1.dd @@ -0,0 +1,73 @@ + +.*: file format .* + +Disassembly of section \.plt: + +00080800 <_PROCEDURE_LINKAGE_TABLE_>: + 80800: d1 01 mov\.l 80808 <_PROCEDURE_LINKAGE_TABLE_\+0x8>,r1 ! 81408 + 80802: 61 12 mov\.l @r1,r1 + 80804: 41 2b jmp @r1 + 80806: 00 09 nop + 80808: 00 08 .* + 80808: R_SH_DIR32 _GLOBAL_OFFSET_TABLE_\+0x8 + 8080a: 14 08 .* + +0008080c <_sglobal@plt>: + 8080c: d0 01 mov\.l 80814 <_sglobal@plt\+0x8>,r0 ! 8140c + 8080e: 60 02 mov\.l @r0,r0 + 80810: 40 2b jmp @r0 + 80812: 00 09 nop + 80814: 00 08 .* + 80814: R_SH_DIR32 _GLOBAL_OFFSET_TABLE_\+0xc + 80816: 14 0c .* + 80818: d0 01 mov\.l 80820 <_sglobal@plt\+0x14>,r0 ! 0 + 8081a: af f1 bra 80800 <_PROCEDURE_LINKAGE_TABLE_> + 8081c: 00 09 nop + 8081e: 00 09 nop + 80820: 00 00 .* + \.\.\. + +00080824 <_foo@plt>: + 80824: d0 01 mov\.l 8082c <_foo@plt\+0x8>,r0 ! 81410 + 80826: 60 02 mov\.l @r0,r0 + 80828: 40 2b jmp @r0 + 8082a: 00 09 nop + 8082c: 00 08 .* + 8082c: R_SH_DIR32 _GLOBAL_OFFSET_TABLE_\+0x10 + 8082e: 14 10 .* + 80830: d0 01 mov\.l 80838 <_foo@plt\+0x14>,r0 ! c + 80832: af e5 bra 80800 <_PROCEDURE_LINKAGE_TABLE_> + 80834: 00 09 nop + 80836: 00 09 nop + 80838: 00 00 .* + 8083a: 00 0c .* +Disassembly of section \.text: + +00080c00 <__start>: + 80c00: 4f 22 sts\.l pr,@-r15 + 80c02: d0 06 mov\.l 80c1c <__start\+0x1c>,r0 ! 80824 <_foo@plt> + 80c04: 40 0b jsr @r0 + 80c06: 00 09 nop + 80c08: d0 05 mov\.l 80c20 <__start\+0x20>,r0 ! 8080c <_sglobal@plt> + 80c0a: 40 0b jsr @r0 + 80c0c: 00 09 nop + 80c0e: d0 05 mov\.l 80c24 <__start\+0x24>,r0 ! 80c28 <_sexternal> + 80c10: 40 0b jsr @r0 + 80c12: 00 09 nop + 80c14: 4f 26 lds\.l @r15\+,pr + 80c16: 00 0b rts + 80c18: 00 09 nop + 80c1a: 00 09 nop + 80c1c: 00 08 .* + 80c1c: R_SH_DIR32 \.plt\+0x24 + 80c1e: 08 24 .* + 80c20: 00 08 .* + 80c20: R_SH_DIR32 \.plt\+0xc + 80c22: 08 0c .* + 80c24: 00 08 .* + 80c24: R_SH_DIR32 _sexternal + 80c26: 0c 28 .* + +00080c28 <_sexternal>: + 80c28: 00 0b rts + 80c2a: 00 09 nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks1.ld b/binutils-2.21/ld/testsuite/ld-sh/vxworks1.ld new file mode 100644 index 0000000..65bf65d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks1.ld @@ -0,0 +1,30 @@ +SECTIONS +{ + . = 0x80000; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + + . = ALIGN (0x400); + .rela.dyn : { *(.rela.dyn) } + .rela.plt : { *(.rela.plt) } + + . = ALIGN (0x400); + .plt : { *(.plt) } + + . = ALIGN (0x400); + .text : { *(.text) } + + . = ALIGN (0x1000); + .dynamic : { *(.dynamic) } + + . = ALIGN (0x400); + .got : { *(.got.plt) *(.got) } + + . = ALIGN (0x400); + .data : { *(.data) } + + . = ALIGN (0x400); + .bss : { *(.bss) *(.dynbss) } +} diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks1.rd b/binutils-2.21/ld/testsuite/ld-sh/vxworks1.rd new file mode 100644 index 0000000..ee50c74 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks1.rd @@ -0,0 +1,19 @@ + +Relocation section '\.rela\.plt' at offset .* contains 2 entries: + Offset Info Type Sym\.Value Sym\. Name \+ Addend +0008140c .*a4 R_SH_JMP_SLOT 0008080c _sglobal \+ 0 +00081410 .*a4 R_SH_JMP_SLOT 00080824 _foo \+ 0 + +Relocation section '\.rela\.text' at offset .* contains 3 entries: + Offset Info Type Sym.Value Sym. Name \+ Addend +00080c1c .*01 R_SH_DIR32 00080800 \.plt \+ 24 +00080c20 .*01 R_SH_DIR32 00080800 \.plt \+ c +00080c24 .*01 R_SH_DIR32 00080c28 _sexternal \+ 0 + +Relocation section '\.rela\.plt\.unloaded' at offset .* contains 5 entries: + Offset Info Type Sym\.Value Sym\. Name \+ Addend +00080808 .*01 R_SH_DIR32 00081400 _GLOBAL_OFFSET_TABLE_ \+ 8 +00080814 .*01 R_SH_DIR32 00081400 _GLOBAL_OFFSET_TABLE_ \+ c +0008140c .*01 R_SH_DIR32 00080800 _PROCEDURE_LINKAGE_TAB.* \+ 0 +0008082c .*01 R_SH_DIR32 00081400 _GLOBAL_OFFSET_TABLE_ \+ 10 +00081410 .*01 R_SH_DIR32 00080800 _PROCEDURE_LINKAGE_TAB.* \+ 0 diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks1.s b/binutils-2.21/ld/testsuite/ld-sh/vxworks1.s new file mode 100644 index 0000000..3ae2373 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks1.s @@ -0,0 +1,32 @@ + .text + .globl __start + .type __start, %function +__start: + sts.l pr,@-r15 + mov.l 1f,r0 + jsr @r0 + nop + + mov.l 2f,r0 + jsr @r0 + nop + + mov.l 3f,r0 + jsr @r0 + nop + + lds.l @r15+,pr + rts + nop + .align 2 +1: .long _foo +2: .long _sglobal +3: .long _sexternal + .size __start, .-__start + + .globl _sexternal + .type _sexternal, %function +_sexternal: + rts + nop + .size _sexternal, .-_sexternal diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks2-static.sd b/binutils-2.21/ld/testsuite/ld-sh/vxworks2-static.sd new file mode 100644 index 0000000..912755b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks2-static.sd @@ -0,0 +1,9 @@ +#... +Elf file type is EXEC \(Executable file\) +Entry point 0x80000 +#... +Program Headers: + Type .* + LOAD .* 0x00080000 0x00080000 .* R E 0x1000 + +#... diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks2.s b/binutils-2.21/ld/testsuite/ld-sh/vxworks2.s new file mode 100644 index 0000000..f680a58 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks2.s @@ -0,0 +1,6 @@ + .globl __start + .type __start, %function +__start: + rts + nop + .end __start diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks2.sd b/binutils-2.21/ld/testsuite/ld-sh/vxworks2.sd new file mode 100644 index 0000000..5ff87d3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks2.sd @@ -0,0 +1,13 @@ +#... +Elf file type is EXEC \(Executable file\) +Entry point 0x80400 +#... +Program Headers: + Type .* + PHDR .* +#... + LOAD .* 0x00080000 0x00080000 .* R E 0x1000 + LOAD .* 0x00081000 0x00081000 .* RW 0x1000 + DYNAMIC .* + +#... diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks3-le.dd b/binutils-2.21/ld/testsuite/ld-sh/vxworks3-le.dd new file mode 100644 index 0000000..6a0fc2d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks3-le.dd @@ -0,0 +1,34 @@ + +.*: file format .* + +Disassembly of section \.plt: + +#... +.*: 01 d0 mov\.l .*,r0 ! 0 +.*: f1 af bra .* <_PROCEDURE_LINKAGE_TABLE_> +.*: 09 00 nop +#... +.*: 01 d0 mov\.l .*,r0 ! 7ec +.*: 05 a8 bra .* <_PROCEDURE_LINKAGE_TABLE_> +.*: 09 00 nop +#... +.*: 01 d0 mov\.l .*,r0 ! 7f8 +.*: f2 af bra .* +.*: 09 00 nop +#... +.*: 01 d0 mov\.l .*,r0 ! fe4 +.*: 06 a8 bra .* +.*: 09 00 nop +#... +.*: 01 d0 mov\.l .*,r0 ! ff0 +.*: f2 af bra .* +.*: 09 00 nop +#... +.*: 01 d0 mov\.l .*,r0 ! 17dc +.*: 06 a8 bra .* +.*: 09 00 nop +#... +.*: 01 d0 mov\.l .*,r0 ! 17e8 +.*: f2 af bra .* +.*: 09 00 nop +#pass diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks3-lib-le.dd b/binutils-2.21/ld/testsuite/ld-sh/vxworks3-lib-le.dd new file mode 100644 index 0000000..011d20c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks3-lib-le.dd @@ -0,0 +1,12 @@ + +.*: file format .* + +Disassembly of section \.text: + +.* <foo0>: +.*: 0b 00 rts +.*: 09 00 nop +#... +.* <foo510>: +.*: 0b 00 rts +.*: 09 00 nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks3-lib.dd b/binutils-2.21/ld/testsuite/ld-sh/vxworks3-lib.dd new file mode 100644 index 0000000..555be00 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks3-lib.dd @@ -0,0 +1,12 @@ + +.*: file format .* + +Disassembly of section \.text: + +.* <foo0>: +.*: 00 0b rts +.*: 00 09 nop +#... +.* <foo510>: +.*: 00 0b rts +.*: 00 09 nop diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks3-lib.s b/binutils-2.21/ld/testsuite/ld-sh/vxworks3-lib.s new file mode 100644 index 0000000..6e10331 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks3-lib.s @@ -0,0 +1,12 @@ + .macro entry + .globl foo\@ + .size foo\@,4 + .type foo\@,@function +foo\@: + rts + nop + .endm + + .rept 511 + entry + .endr diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks3.dd b/binutils-2.21/ld/testsuite/ld-sh/vxworks3.dd new file mode 100644 index 0000000..f0593b6 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks3.dd @@ -0,0 +1,34 @@ + +.*: file format .* + +Disassembly of section \.plt: + +#... +.*: d0 01 mov\.l .*,r0 ! 0 +.*: af f1 bra .* <_PROCEDURE_LINKAGE_TABLE_> +.*: 00 09 nop +#... +.*: d0 01 mov\.l .*,r0 ! 7ec +.*: a8 05 bra .* <_PROCEDURE_LINKAGE_TABLE_> +.*: 00 09 nop +#... +.*: d0 01 mov\.l .*,r0 ! 7f8 +.*: af f2 bra .* +.*: 00 09 nop +#... +.*: d0 01 mov\.l .*,r0 ! fe4 +.*: a8 06 bra .* +.*: 00 09 nop +#... +.*: d0 01 mov\.l .*,r0 ! ff0 +.*: af f2 bra .* +.*: 00 09 nop +#... +.*: d0 01 mov\.l .*,r0 ! 17dc +.*: a8 06 bra .* +.*: 00 09 nop +#... +.*: d0 01 mov\.l .*,r0 ! 17e8 +.*: af f2 bra .* +.*: 00 09 nop +#pass diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks3.s b/binutils-2.21/ld/testsuite/ld-sh/vxworks3.s new file mode 100644 index 0000000..86d6310 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks3.s @@ -0,0 +1,7 @@ + .macro entry + .long foo\@ + .endm + + .rept 511 + entry + .endr diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks4.d b/binutils-2.21/ld/testsuite/ld-sh/vxworks4.d new file mode 100644 index 0000000..c5721dd --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks4.d @@ -0,0 +1,11 @@ +#source: vxworks4a.s +#source: vxworks4b.s +#ld: -shared -Tvxworks1.ld +#target: sh-*-vxworks +#readelf: --relocs + +Relocation section '\.rela\.dyn' at offset .* contains 3 entries: + Offset Info Type Sym\.Value Sym\. Name \+ Addend +00081810 000000a5 R_SH_RELATIVE 0008181c +00081814 .*01 R_SH_DIR32 00000000 global \+ 1234 +00081818 .*02 R_SH_REL32 00000000 global \+ 1234 diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks4a.s b/binutils-2.21/ld/testsuite/ld-sh/vxworks4a.s new file mode 100644 index 0000000..2785567 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks4a.s @@ -0,0 +1,2 @@ + .data + .fill 0x10 diff --git a/binutils-2.21/ld/testsuite/ld-sh/vxworks4b.s b/binutils-2.21/ld/testsuite/ld-sh/vxworks4b.s new file mode 100644 index 0000000..6c0228a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/vxworks4b.s @@ -0,0 +1,4 @@ + .data + .long . + 0xc + .long global + 0x1234 + .long global + 0x1234 - . diff --git a/binutils-2.21/ld/testsuite/ld-sh/weak1.d b/binutils-2.21/ld/testsuite/ld-sh/weak1.d new file mode 100644 index 0000000..d248bb9 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/weak1.d @@ -0,0 +1,21 @@ +#source: weak1.s +#as: -little +#ld: -e 0x1000 -EL +#objdump: -ts +#target: sh*-*-elf + +.*: file format elf32-sh.* + +SYMBOL TABLE: +#... +0+10a0 l .data 0+ d0 +0+1000 l .text 0+ f +0+10a4 w .data 0+ w0 +#... + +Contents of section .text: + 1000 01d11260 0b000900 a4100000 09000900 .* + 1010 09000900 09000900 09000900 09000900 .* +Contents of section .data: + 10a0 01000000 00000000 .* +#pass diff --git a/binutils-2.21/ld/testsuite/ld-sh/weak1.s b/binutils-2.21/ld/testsuite/ld-sh/weak1.s new file mode 100644 index 0000000..79192af --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-sh/weak1.s @@ -0,0 +1,19 @@ + .data + .align 2 +d0: + .long 1 + .global w0 +w0: + .long 0 + .weak w0 + .text + .align 5 +f: + mov.l .L3,r1 + mov.l @r1,r0 + rts + nop + .align 2 +.L3: + .long w0 + |