diff options
| author | Steve Ellcey <Steve.Ellcey@imgtec.com> | 2014-07-03 13:25:21 -0700 |
|---|---|---|
| committer | Steve Ellcey <Steve.Ellcey@imgtec.com> | 2014-07-03 16:13:56 -0700 |
| commit | 8390634fd5fb311f01b82ba35a8db4b40b983cc8 (patch) | |
| tree | 0a83785a2d0c687553eb05872c30582fe6b5d9b1 /binutils-2.24/ld | |
| parent | bcfb04363768d7eb2910bbefb263effae28ace10 (diff) | |
| download | toolchain_binutils-8390634fd5fb311f01b82ba35a8db4b40b983cc8.zip toolchain_binutils-8390634fd5fb311f01b82ba35a8db4b40b983cc8.tar.gz toolchain_binutils-8390634fd5fb311f01b82ba35a8db4b40b983cc8.tar.bz2 | |
Update Binutils 2.24 to include mips32r6, mips64r6 and MSA changes.
Change-Id: I24f28bc29dff188ba059388d8d5478f51da56a12
Diffstat (limited to 'binutils-2.24/ld')
198 files changed, 8695 insertions, 791 deletions
diff --git a/binutils-2.24/ld/ChangeLog b/binutils-2.24/ld/ChangeLog index 1687785..0422d81 100644 --- a/binutils-2.24/ld/ChangeLog +++ b/binutils-2.24/ld/ChangeLog @@ -1,3 +1,7 @@ +2014-04-16 Steve Ellcey <sellcey@mips.com> + + * emultempl/elf32.em: Include safe-ctype.h. + 2013-11-25 Yufeng Zhang <yufeng.zhang@arm.com> Backport from master diff --git a/binutils-2.24/ld/configure.tgt b/binutils-2.24/ld/configure.tgt index c50730b..714deab 100644 --- a/binutils-2.24/ld/configure.tgt +++ b/binutils-2.24/ld/configure.tgt @@ -454,7 +454,7 @@ mips*vr5000el-*-elf*) targ_emul=elf32l4300 ;; mips*vr5000-*-elf*) targ_emul=elf32b4300 ;; mips*el-sde-elf*) targ_emul=elf32ltsmip targ_extra_emuls="elf32btsmip elf32ltsmipn32 elf64ltsmip elf32btsmipn32 elf64btsmip" ;; -mips*-sde-elf* | mips*-mti-elf*) +mips*-sde-elf* | mips*-mti-elf* | mips*-img-elf*) targ_emul=elf32btsmip targ_extra_emuls="elf32ltsmip elf32btsmipn32 elf64btsmip elf32ltsmipn32 elf64ltsmip" ;; mips64*el-ps2-elf*) targ_emul=elf32lr5900n32 @@ -471,6 +471,9 @@ mips*el-*-vxworks*) targ_emul=elf32elmipvxworks mips*-*-vxworks*) targ_emul=elf32ebmipvxworks targ_extra_emuls="elf32elmipvxworks" ;; mips*-*-windiss) targ_emul=elf32mipswindiss ;; +mips64*el-*android*) targ_emul=elf64ltsmip + targ_extra_emuls="elf64btsmip elf32ltsmipn32 elf32btsmipn32 elf32ltsmip elf32btsmip" + targ_extra_libpath=$targ_extra_emuls ;; mips64*el-*-linux-*) targ_emul=elf32ltsmipn32 targ_extra_emuls="elf32btsmipn32 elf32ltsmip elf32btsmip elf64ltsmip elf64btsmip" targ_extra_libpath=$targ_extra_emuls ;; diff --git a/binutils-2.24/ld/emulparams/elf32bmip.sh b/binutils-2.24/ld/emulparams/elf32bmip.sh index 2289685..c8ed5df 100644 --- a/binutils-2.24/ld/emulparams/elf32bmip.sh +++ b/binutils-2.24/ld/emulparams/elf32bmip.sh @@ -17,7 +17,8 @@ if test -z "${CREATE_SHLIB}"; then INITIAL_READONLY_SECTIONS=".interp ${RELOCATING-0} : { *(.interp) }" fi INITIAL_READONLY_SECTIONS="${INITIAL_READONLY_SECTIONS} - .reginfo ${RELOCATING-0} : { *(.reginfo) } + .MIPS.abiflags ${RELOCATING-0} : { *(.MIPS.abiflags) } + .reginfo ${RELOCATING-0} : { *(.reginfo) } " OTHER_TEXT_SECTIONS='*(.mips16.fn.*) *(.mips16.call.*)' # Unlike most targets, the MIPS backend puts all dynamic relocations diff --git a/binutils-2.24/ld/emulparams/elf32bmipn32-defs.sh b/binutils-2.24/ld/emulparams/elf32bmipn32-defs.sh index 514990b..723eac8 100644 --- a/binutils-2.24/ld/emulparams/elf32bmipn32-defs.sh +++ b/binutils-2.24/ld/emulparams/elf32bmipn32-defs.sh @@ -88,6 +88,7 @@ if test -z "${CREATE_SHLIB}"; then INITIAL_READONLY_SECTIONS=".interp ${RELOCATING-0} : { *(.interp) }" fi INITIAL_READONLY_SECTIONS="${INITIAL_READONLY_SECTIONS} + .MIPS.abiflags ${RELOCATING-0} : { *(.MIPS.abiflags) } .reginfo ${RELOCATING-0} : { *(.reginfo) }" # Discard any .MIPS.content* or .MIPS.events* sections. The linker # doesn't know how to adjust them. diff --git a/binutils-2.24/ld/emulparams/elf64bmip-defs.sh b/binutils-2.24/ld/emulparams/elf64bmip-defs.sh index 110f892..8a0522f 100644 --- a/binutils-2.24/ld/emulparams/elf64bmip-defs.sh +++ b/binutils-2.24/ld/emulparams/elf64bmip-defs.sh @@ -1,3 +1,6 @@ . ${srcdir}/emulparams/elf32bmipn32-defs.sh COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" -INITIAL_READONLY_SECTIONS=".MIPS.options : { *(.MIPS.options) }" +INITIAL_READONLY_SECTIONS=" + .MIPS.abiflags ${RELOCATING-0} : { *(.MIPS.abiflags) } + .MIPS.options : { *(.MIPS.options) } +" diff --git a/binutils-2.24/ld/emultempl/elf32.em b/binutils-2.24/ld/emultempl/elf32.em index 9a2fe89..7d5ef28 100644 --- a/binutils-2.24/ld/emultempl/elf32.em +++ b/binutils-2.24/ld/emultempl/elf32.em @@ -40,6 +40,7 @@ fragment <<EOF #include "sysdep.h" #include "bfd.h" #include "libiberty.h" +#include "safe-ctype.h" #include "filenames.h" #include "safe-ctype.h" #include "getopt.h" diff --git a/binutils-2.24/ld/ldmain.c b/binutils-2.24/ld/ldmain.c index 6a53667..0aca0c1 100644 --- a/binutils-2.24/ld/ldmain.c +++ b/binutils-2.24/ld/ldmain.c @@ -597,8 +597,10 @@ get_emulation (int argc, char **argv) || strcmp (argv[i], "-mips5") == 0 || strcmp (argv[i], "-mips32") == 0 || strcmp (argv[i], "-mips32r2") == 0 + || strcmp (argv[i], "-mips32r6") == 0 || strcmp (argv[i], "-mips64") == 0 - || strcmp (argv[i], "-mips64r2") == 0) + || strcmp (argv[i], "-mips64r2") == 0 + || strcmp (argv[i], "-mips64r6") == 0) { /* FIXME: The arguments -mips1, -mips2, -mips3, etc. are passed to the linker by some MIPS compilers. They diff --git a/binutils-2.24/ld/testsuite/ChangeLog b/binutils-2.24/ld/testsuite/ChangeLog index 342d5b2..963d096 100644 --- a/binutils-2.24/ld/testsuite/ChangeLog +++ b/binutils-2.24/ld/testsuite/ChangeLog @@ -1,3 +1,30 @@ +2014-05-28 Matthew Fortune <matthew.fortune@imgtec.com> + + * lib/ld-lib.exp: Add objcopy_objects command to run_dump_test. + This allows each input object to be optionally run through + objcopy before linking. + +2014-04-17 Kwok Cheung Yeung <kcy@codesourcery.com> + + * ld-mips-elf/elf-rel-xgot-n32.d: Update for new GOT layout. + * ld-mips-elf/elf-rel-xgot-n32-embed.d: Likewise. + * ld-mips-elf/elf-rel-xgot-n64.d: Likewise. + * ld-mips-elf/elf-rel-xgot-n64-embed.d: Likewise. + * ld-mips-elf/elf-rel-xgot-n64-linux.d: Likewise. + +2014-03-20 Richard Sandiford <rdsandiford@googlemail.com> + + * ld-elf/merge.d: Remove MIPS XFAIL. + +2014-02-18 Jack Carter <jack.carter@imgtec.com> + + * ld-mips-elf/pic-and-nonpic-3a.sd: Check DYNAMIC segment flags. + +2013-11-27 Matthew Fortune <matthew.fortune@imgtec.com> + + * ld-mips-elf/mips-elf.exp: Consider mips-mti-elf the same as + mips-sde-elf + 2013-11-19 Roland McGrath <mcgrathr@google.com> * ld-elf/ehdr_start-userdef.t: New file. @@ -75,6 +102,68 @@ * ld-x86-64/plt-nacl.pd: Update expected disassembly for PLT nop fix. * ld-x86-64/tlsdesc-nacl.pd: Likewise. +2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com> + + * ld-mips-elf/attr-gnu-8-0.s, ld-mips-elf/attr-gnu-8-1.s, + ld-mips-elf/attr-gnu-8-2.s, + ld-mips-elf/attr-gnu-8-00.d, ld-mips-elf/attr-gnu-8-01.d, + ld-mips-elf/attr-gnu-8-02.d, ld-mips-elf/attr-gnu-8-10.d, + ld-mips-elf/attr-gnu-8-11.d, ld-mips-elf/attr-gnu-8-12.d, + ld-mips-elf/attr-gnu-8-20.d, ld-mips-elf/attr-gnu-8-21.d, + ld-mips-elf/attr-gnu-8-22.d: New. + * ld-mips-elf/mips-elf.exp: Run new tests. + +2013-10-13 Richard Sandiford <rdsandiford@googlemail.com> + + * lib/ld-lib.exp (default_ld_compile): Add a -I option for the source + directory. + * ld-mips-elf/compressed-plt-1.ld, ld-mips-elf/compressed-plt-1.s, + ld-mips-elf/compressed-plt-1-dyn.s, ld-mips-elf/compressed-plt-1a.s, + ld-mips-elf/compressed-plt-1b.s, ld-mips-elf/compressed-plt-1c.s, + ld-mips-elf/compressed-plt-1d.s, ld-mips-elf/compressed-plt-1e.s, + ld-mips-elf/compressed-plt-1-o32-se.rd, + ld-mips-elf/compressed-plt-1-o32-se.od, + ld-mips-elf/compressed-plt-1-o32-mips16-only.rd, + ld-mips-elf/compressed-plt-1-o32-mips16-only.od, + ld-mips-elf/compressed-plt-1-o32-umips-only.rd, + ld-mips-elf/compressed-plt-1-o32-umips-only.od, + ld-mips-elf/compressed-plt-1-o32-mips16.rd, + ld-mips-elf/compressed-plt-1-o32-mips16.od, + ld-mips-elf/compressed-plt-1-o32-mips16-got.rd, + ld-mips-elf/compressed-plt-1-o32-mips16-got.od, + ld-mips-elf/compressed-plt-1-o32-mips16-word.rd, + ld-mips-elf/compressed-plt-1-o32-mips16-word.od, + ld-mips-elf/compressed-plt-1-o32-umips.rd, + ld-mips-elf/compressed-plt-1-o32-umips.od, + ld-mips-elf/compressed-plt-1-o32-umips-got.rd, + ld-mips-elf/compressed-plt-1-o32-umips-got.od, + ld-mips-elf/compressed-plt-1-o32-umips-word.rd, + ld-mips-elf/compressed-plt-1-o32-umips-word.od, + ld-mips-elf/compressed-plt-1-n32-mips16.rd, + ld-mips-elf/compressed-plt-1-n32-mips16.od, + ld-mips-elf/compressed-plt-1-n32-umips.rd, + ld-mips-elf/compressed-plt-1-n32-umips.od: New tests. + * ld-mips-elf/mips-elf.exp: Run them. + +2013-10-13 Richard Sandiford <rdsandiford@googlemail.com> + + * ld-mips-elf/pic-and-nonpic-6-n32.ad, + ld-mips-elf/pic-and-nonpic-6-n32.dd, + ld-mips-elf/pic-and-nonpic-6-n32.gd, + ld-mips-elf/pic-and-nonpic-6-n32.nd, + ld-mips-elf/pic-and-nonpic-6-n32.rd, + ld-mips-elf/pic-and-nonpic-6-n64.ad, + ld-mips-elf/pic-and-nonpic-6-n64.dd, + ld-mips-elf/pic-and-nonpic-6-n64.gd, + ld-mips-elf/pic-and-nonpic-6-n64.nd, + ld-mips-elf/pic-and-nonpic-6-n64.rd, + ld-mips-elf/pic-and-nonpic-6-o32.ad, + ld-mips-elf/pic-and-nonpic-6-o32.dd, + ld-mips-elf/pic-and-nonpic-6-o32.gd, + ld-mips-elf/pic-and-nonpic-6-o32.nd, + ld-mips-elf/pic-and-nonpic-6-o32.rd: Fix symbol value of extf4. + No longer expect extf3, extf4 and extd2 to be in the global GOT. + 2013-10-05 Gregory Fong <gregory.0xf0@gmail.com> * ld-mips-elf/eh-frame5.d, ld-mips-elf/jalx-2.dd, diff --git a/binutils-2.24/ld/testsuite/ld-elf/group.ld b/binutils-2.24/ld/testsuite/ld-elf/group.ld index 123ab26..f8e50c3 100644 --- a/binutils-2.24/ld/testsuite/ld-elf/group.ld +++ b/binutils-2.24/ld/testsuite/ld-elf/group.ld @@ -2,5 +2,5 @@ SECTIONS { . = 0x1000; .text : { *(.text) *(.rodata.brlt) } - /DISCARD/ : { *(.dropme) *(.reginfo) } + /DISCARD/ : { *(.dropme) *(.reginfo) *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-elf/merge.d b/binutils-2.24/ld/testsuite/ld-elf/merge.d index c50de10..450ee07 100644 --- a/binutils-2.24/ld/testsuite/ld-elf/merge.d +++ b/binutils-2.24/ld/testsuite/ld-elf/merge.d @@ -4,7 +4,7 @@ #xfail: "arc-*-*" "avr-*-*" "bfin-*-*" "cr16-*-*" "cris*-*-*" "crx-*-*" "d10v-*-*" "d30v-*-*" #xfail: "dlx-*-*" "fr30-*-*" "frv-*-*" "hppa*64*-*-*" "h8300-*-*" "score-*-*" #xfail: "i370-*-*" "i860-*-*" "i960-*-*" "ip2k-*-*" "iq2000-*-*" "lm32-*-*" -#xfail: "mcore-*-*" "mn102*-*-*" "mips*-*-*" "ms1-*-*" "mep-*-*" +#xfail: "mcore-*-*" "mn102*-*-*" "ms1-*-*" "mep-*-*" #xfail: "or32-*-*" "pj-*-*" "sparc*-*-*" "tic6x-*-*" "vax-*-*" "xstormy16-*-*" #xfail: "xtensa*-*-*" "metag-*-*" diff --git a/binutils-2.24/ld/testsuite/ld-elf/orphan-region.ld b/binutils-2.24/ld/testsuite/ld-elf/orphan-region.ld index b7dfdba..2abf8bc 100644 --- a/binutils-2.24/ld/testsuite/ld-elf/orphan-region.ld +++ b/binutils-2.24/ld/testsuite/ld-elf/orphan-region.ld @@ -7,5 +7,5 @@ SECTIONS { .text : ALIGN (4) { *(.text) } > region .rodata : ALIGN (4) { *(.rodata) } > region - /DISCARD/ : { *(.reginfo) *(.trampolines) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) *(.trampolines) } } diff --git a/binutils-2.24/ld/testsuite/ld-elf/orphan.ld b/binutils-2.24/ld/testsuite/ld-elf/orphan.ld index d23222b..44eb7eb 100644 --- a/binutils-2.24/ld/testsuite/ld-elf/orphan.ld +++ b/binutils-2.24/ld/testsuite/ld-elf/orphan.ld @@ -4,5 +4,5 @@ SECTIONS .data : { *(.data) } .bss : { *(.bss) *(COMMON) } .note : { *(.note) } - /DISCARD/ : { *(.reginfo) *(.trampolines) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) *(.trampolines) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip1-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip1-ph.d new file mode 100644 index 0000000..3af3433 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip1-ph.d @@ -0,0 +1,13 @@ +#source: jr.s -mips32r2 -32 -mfp32 -EB RUN_OBJCOPY +#objcopy_objects: -R .MIPS.abiflags +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +#... +!0x70000003.* +#... +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip2-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip2-ph.d new file mode 100644 index 0000000..5c36ce0 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip2-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -mips32r2 -32 -mfpxx -EB +#source: jr.s -march=octeon -32 -mfp64 -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 808b1100: \[abi=O32\] \[mips64r2\] \[32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: Cavium Networks Octeon +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip3-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip3-ph.d new file mode 100644 index 0000000..3ad1143 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip3-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -march=octeon -32 -mfp64 -EB RUN_OBJCOPY +#source: jr.s -mips32r2 -32 -mfpxx -EB +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 808b1100: \[abi=O32\] \[mips64r2\] \[32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: Cavium Networks Octeon +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip4-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip4-ph.d new file mode 100644 index 0000000..d109d95 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip4-ph.d @@ -0,0 +1,33 @@ +#source: jr.s -march=octeon -32 -mfp64 -EB -mdmx RUN_OBJCOPY +#source: jr.s -mips32r2 -32 -mfpxx -EB +#source: jr.s -mips32r2 -32 -mfp64 -mmsa -EB +#source: jr.s -mips2 -32 -mfpxx -mips16 -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x00000... memsz 0x00000... flags r-x +private flags = 8c8b1100: \[abi=O32\] \[mips64r2\] \[mdmx\] \[mips16\] \[32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r2 +GPR size: 32 +CPR1 size: 128 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: Cavium Networks Octeon +ASEs: + MDMX ASE + MSA ASE + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip5-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip5-ph.d new file mode 100644 index 0000000..cfbda75 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip5-ph.d @@ -0,0 +1,33 @@ +#source: jr.s -mips32r2 -32 -mfpxx -EB +#source: jr.s -mips32r2 -32 -mfp64 -mmsa -EB +#source: jr.s -march=octeon -32 -mfp64 -EB -mdmx RUN_OBJCOPY +#source: jr.s -mips2 -32 -mips16 -mfpxx -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x00000... memsz 0x00000... flags r-x +private flags = 8c8b1100: \[abi=O32\] \[mips64r2\] \[mdmx\] \[mips16\] \[32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r2 +GPR size: 32 +CPR1 size: 128 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: Cavium Networks Octeon +ASEs: + MDMX ASE + MSA ASE + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip6-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip6-ph.d new file mode 100644 index 0000000..147df83 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip6-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -mips32r3 -32 -EB RUN_OBJCOPY +#source: jr.s -mips32r2 -32 -EB +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip7-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip7-ph.d new file mode 100644 index 0000000..7ce3175 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip7-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -mips32r3 -32 -EB +#source: jr.s -mips32r2 -32 -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r3 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip8-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip8-ph.d new file mode 100644 index 0000000..42fb0c3 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/abiflags-strip8-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -mips32r2 -32 -mfpxx -EB +#source: jr.s -mips32r2 -32 -mfp64 -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .gnu.attributes +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n32-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n32-ph.d new file mode 100644 index 0000000..9f424e4 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n32-ph.d @@ -0,0 +1,26 @@ +#source: attr-gnu-4-0.s -mips3 -n32 -EB +#ld: -melf32btsmipn32 -e 0 +#objdump: -p + +[^:]*: file format elf32-ntradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x100000.. paddr 0x100000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x10000000 paddr 0x10000000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 20000020: \[abi=N32\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard or soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n64-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n64-ph.d new file mode 100644 index 0000000..124f81c --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n64-ph.d @@ -0,0 +1,25 @@ +#source: attr-gnu-4-0.s -mips3 -64 -EB +#ld: -melf64btsmip -e 0 +#objdump: -p + +[^:]*: file format elf64-tradbigmips + +Program Header: +0x70000003 off 0x00000000000000b0 vaddr 0x00000001200000b0 paddr 0x00000001200000b0 align 2\*\*3 + filesz 0x0000000000000018 memsz 0x0000000000000018 flags r-- + LOAD off 0x0000000000000000 vaddr 0x0000000120000000 paddr 0x0000000120000000 align 2\*\*16 + filesz 0x00000000000000.. memsz 0x00000000000000.. flags r-- +private flags = 20000000: \[abi=64\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard or soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-ph.d new file mode 100644 index 0000000..ee50709 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-0-ph.d @@ -0,0 +1,26 @@ +#source: attr-gnu-4-0.s -mips32r2 -32 -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: .* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard or soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-00.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-00.d index 32bc319..d460449 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-00.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-00.d @@ -2,5 +2,16 @@ #source: attr-gnu-4-0.s #ld: -r #readelf: -A -#target: mips*-*-* +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard or soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-01.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-01.d index 7a5c7a1..168b7aa 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-01.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-01.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-1.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-02.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-02.d index f29d5d5..ec58964 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-02.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-02.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-2.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-03.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-03.d index e571e13..c254a2d 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-03.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-03.d @@ -1,9 +1,22 @@ #source: attr-gnu-4-0.s +#as: -msoft-float #source: attr-gnu-4-3.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-04.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-04.d index f8dee5c..628daee 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-04.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-04.d @@ -1,9 +1,5 @@ #source: attr-gnu-4-0.s -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #ld: -r -#readelf: -A -#target: mips*-*-* - -Attribute Section: gnu -File Attributes - Tag_GNU_MIPS_ABI_FP: Hard float \(MIPS32r2 64-bit FPU\) +#error: \A[^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-05.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-05.d index 6856df0..c3d9193 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-05.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-05.d @@ -1,9 +1,21 @@ -#source: attr-gnu-4-0.s -#source: attr-gnu-4-5.s -#ld: -r +#source: attr-gnu-4-0.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes - Tag_GNU_MIPS_ABI_FP: \?\?\? \(5\) + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-06.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-06.d new file mode 100644 index 0000000..5c640ff --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-06.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-0.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-07.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-07.d new file mode 100644 index 0000000..108e5a4 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-07.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-0.s +#source: attr-gnu-4-7.s -W +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: \?\?\? \(7\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: \?\?\? \(7\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n32-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n32-ph.d new file mode 100644 index 0000000..7e502ed --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n32-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips3 -n32 -EB +#ld: -melf32btsmipn32 -e 0 +#objdump: -p + +[^:]*: file format elf32-ntradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x100000.. paddr 0x100000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x10000000 paddr 0x10000000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 20000020: \[abi=N32\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n64-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n64-ph.d new file mode 100644 index 0000000..6c5878a --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n64-ph.d @@ -0,0 +1,25 @@ +#source: empty.s -mips3 -64 -EB +#ld: -melf64btsmip -e 0 +#objdump: -p + +[^:]*: file format elf64-tradbigmips + +Program Header: +0x70000003 off 0x00000000000000b0 vaddr 0x00000001200000b0 paddr 0x00000001200000b0 align 2\*\*3 + filesz 0x0000000000000018 memsz 0x0000000000000018 flags r-- + LOAD off 0x0000000000000000 vaddr 0x0000000120000000 paddr 0x0000000120000000 align 2\*\*16 + filesz 0x00000000000000.. memsz 0x00000000000000.. flags r-- +private flags = 20000000: \[abi=64\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-ph.d new file mode 100644 index 0000000..3b517b2 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-1-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -mfp32 -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d index 7661963..3ecf33b 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d @@ -1,9 +1,42 @@ -#source: attr-gnu-4-1.s -#source: attr-gnu-4-0.s -#ld: -r -#readelf: -A -#target: mips*-*-* +#source: attr-gnu-4-1.s -EB +#source: attr-gnu-4-0.s -EB +#ld: -r -melf32btsmip +#readelf: -hA + +ELF Header: + Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00.* + Class: ELF32 + Data: 2's complement, big endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 0 + Type: REL \(Relocatable file\) + Machine: MIPS R3000 + Version: 0x1 + Entry point address: 0x0 + Start of program headers: 0 \(bytes into file\) + Start of section headers: ... \(bytes into file\) + Flags: .* + Size of this header: 52 \(bytes\) + Size of program headers: 0 \(bytes\) + Number of program headers: 0 + Size of section headers: 40 \(bytes\) + Number of section headers: 11 + Section header string table index: 8 Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-11.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-11.d index f70306b..f546c0a 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-11.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-11.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-1.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-12.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-12.d index c0eace6..b1b0760 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-12.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-12.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-2.s #ld: -r #warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses -msingle-float -#target: mips*-*-* diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-13.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-13.d index cb30f7a..c9bf544 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-13.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-13.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-3.s #ld: -r #warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float -#target: mips*-*-* diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-14.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-14.d index bde387b..58cfd24 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-14.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-14.d @@ -1,5 +1,6 @@ #source: attr-gnu-4-1.s -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #ld: -r -#warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses -mips32r2 -mfp64 -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -mdouble-float \(set by .*\), .* uses -mips32r2 -mfp64 \(12 callee-saved\)\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-15.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-15.d index b19645f..4f4cd00 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-15.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-15.d @@ -1,10 +1,21 @@ -#source: attr-gnu-4-1.s -#source: attr-gnu-4-5.s -#ld: -r +#source: attr-gnu-4-1.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip #readelf: -A -#warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses unknown floating point ABI 5 -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-16.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-16.d new file mode 100644 index 0000000..430ab91 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-16.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-1.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A +#warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses -mgp32 -mfp64 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-17.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-17.d new file mode 100644 index 0000000..6d675ac --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-17.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-1.s +#source: attr-gnu-4-7.s -W +#ld: -r +#readelf: -A +#warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses unknown floating point ABI 7 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n32-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n32-ph.d new file mode 100644 index 0000000..57b8653 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n32-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips3 -n32 -msingle-float -EB +#ld: -melf32btsmipn32 -e 0 +#objdump: -p + +[^:]*: file format elf32-ntradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x100000.. paddr 0x100000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x10000000 paddr 0x10000000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 20000020: \[abi=N32\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n64-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n64-ph.d new file mode 100644 index 0000000..51a84db --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n64-ph.d @@ -0,0 +1,25 @@ +#source: empty.s -mips3 -64 -msingle-float -EB +#ld: -melf64btsmip -e 0 +#objdump: -p + +[^:]*: file format elf64-tradbigmips + +Program Header: +0x70000003 off 0x00000000000000b0 vaddr 0x00000001200000b0 paddr 0x00000001200000b0 align 2\*\*3 + filesz 0x0000000000000018 memsz 0x0000000000000018 flags r-- + LOAD off 0x0000000000000000 vaddr 0x0000000120000000 paddr 0x0000000120000000 align 2\*\*16 + filesz 0x00000000000000.. memsz 0x00000000000000.. flags r-- +private flags = 20000000: \[abi=64\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-ph.d new file mode 100644 index 0000000..dcdff3e --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -msingle-float -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2.s index 54ebf4e..4021bed 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2.s +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-2.s @@ -1 +1,2 @@ +.module singlefloat .gnu_attribute 4,2 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-20.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-20.d index 3620069..ab879e7 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-20.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-20.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-0.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-21.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-21.d index 68a006f..0081c72 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-21.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-21.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-1.s #ld: -r #warning: Warning: .* uses -msingle-float \(set by .*\), .* uses -mdouble-float -#target: mips*-*-* diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-22.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-22.d index 63edea9..051c96d 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-22.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-22.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-2.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-23.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-23.d index e16226f..0b8a6fc 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-23.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-23.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-3.s #ld: -r #warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float -#target: mips*-*-* diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-24.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-24.d index c31bb64..e48e5bb 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-24.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-24.d @@ -1,5 +1,6 @@ #source: attr-gnu-4-2.s -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #ld: -r -#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses -mips32r2 -mfp64 -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -msingle-float \(set by .*\), .* uses -mips32r2 -mfp64 \(12 callee-saved\)\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-25.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-25.d index b5456ab..cc0451e 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-25.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-25.d @@ -1,10 +1,22 @@ -#source: attr-gnu-4-2.s -#source: attr-gnu-4-5.s -#ld: -r +#source: attr-gnu-4-2.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip #readelf: -A -#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses unknown floating point ABI 5 -#target: mips*-*-* +#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses -mfpxx Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-26.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-26.d new file mode 100644 index 0000000..ec5d1c3 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-26.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-2.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A +#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses -mgp32 -mfp64 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-27.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-27.d new file mode 100644 index 0000000..8756697 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-27.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-2.s +#source: attr-gnu-4-7.s -W +#ld: -r +#readelf: -A +#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses unknown floating point ABI 7 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n32-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n32-ph.d new file mode 100644 index 0000000..57b8653 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n32-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips3 -n32 -msingle-float -EB +#ld: -melf32btsmipn32 -e 0 +#objdump: -p + +[^:]*: file format elf32-ntradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x100000.. paddr 0x100000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x10000000 paddr 0x10000000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 20000020: \[abi=N32\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n64-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n64-ph.d new file mode 100644 index 0000000..0252ac5 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n64-ph.d @@ -0,0 +1,25 @@ +#source: empty.s -mips3 -64 -msoft-float -EB +#ld: -melf64btsmip -e 0 +#objdump: -p + +[^:]*: file format elf64-tradbigmips + +Program Header: +0x70000003 off 0x00000000000000b0 vaddr 0x00000001200000b0 paddr 0x00000001200000b0 align 2\*\*3 + filesz 0x0000000000000018 memsz 0x0000000000000018 flags r-- + LOAD off 0x0000000000000000 vaddr 0x0000000120000000 paddr 0x0000000120000000 align 2\*\*16 + filesz 0x00000000000000.. memsz 0x00000000000000.. flags r-- +private flags = 20000000: \[abi=64\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 0 +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-ph.d new file mode 100644 index 0000000..5b220d1 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -msoft-float -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 0 +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3.s index 32e5f5d..0ba0b80 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3.s +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-3.s @@ -1 +1,2 @@ +.module softfloat .gnu_attribute 4,3 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-30.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-30.d index cdc108e..ecf319b 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-30.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-30.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-0.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-31.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-31.d index b749e82..4fcf76f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-31.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-31.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-1.s #ld: -r #warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float -#target: mips*-*-* diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-32.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-32.d index d0fd7bc..0d663c2 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-32.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-32.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-2.s #ld: -r #warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float -#target: mips*-*-* diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-33.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-33.d index 39eebb3..b543942 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-33.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-33.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-3.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-34.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-34.d index be24523..314515a 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-34.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-34.d @@ -1,5 +1,6 @@ #source: attr-gnu-4-3.s -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #ld: -r -#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-35.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-35.d index bcb1e02..f54b800 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-35.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-35.d @@ -1,10 +1,22 @@ -#source: attr-gnu-4-3.s -#source: attr-gnu-4-5.s -#ld: -r +#source: attr-gnu-4-3.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip #readelf: -A -#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses unknown floating point ABI 5 -#target: mips*-*-* +#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-36.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-36.d new file mode 100644 index 0000000..521af48 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-36.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-3.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A +#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-37.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-37.d new file mode 100644 index 0000000..7697607 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-37.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-3.s +#source: attr-gnu-4-7.s -W +#ld: -r +#readelf: -A +#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses unknown floating point ABI 7 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-4-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-4-ph.d new file mode 100644 index 0000000..2551060 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-4-ph.d @@ -0,0 +1,26 @@ +#source: attr-gnu-4-4.s -mips32r2 -32 -EB -W +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001200: \[abi=O32\] \[mips32r2\] \[old fp64\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(MIPS32r2 64-bit FPU 12 callee-saved\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-40.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-40.d index 27d4571..6aa22b9 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-40.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-40.d @@ -1,9 +1,5 @@ -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #source: attr-gnu-4-0.s #ld: -r -#readelf: -A -#target: mips*-*-* - -Attribute Section: gnu -File Attributes - Tag_GNU_MIPS_ABI_FP: Hard float \(MIPS32r2 64-bit FPU\) +#error: \A[^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-41.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-41.d index b652983..7c61365 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-41.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-41.d @@ -1,5 +1,6 @@ -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #source: attr-gnu-4-1.s #ld: -r -#warning: Warning: .* uses -mips32r2 -mfp64 \(set by .*\), .* uses -mdouble-float -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses -mdouble-float\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-42.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-42.d index a1b79ea..dad0421 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-42.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-42.d @@ -1,5 +1,6 @@ -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #source: attr-gnu-4-2.s #ld: -r -#warning: Warning: .* uses -mips32r2 -mfp64 \(set by .*\), .* uses -msingle-float -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses -msingle-float\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-43.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-43.d index 23f40c6..f30c18e 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-43.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-43.d @@ -1,5 +1,6 @@ -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #source: attr-gnu-4-3.s #ld: -r -#warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-44.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-44.d index 68b03a0..f870c8a 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-44.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-44.d @@ -1,9 +1,21 @@ -#source: attr-gnu-4-4.s -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W +#source: attr-gnu-4-4.s -W #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes - Tag_GNU_MIPS_ABI_FP: Hard float \(MIPS32r2 64-bit FPU\) + Tag_GNU_MIPS_ABI_FP: Hard float \(MIPS32r2 64-bit FPU 12 callee-saved\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(MIPS32r2 64-bit FPU 12 callee-saved\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-45.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-45.d index 0d1b079..d21e66f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-45.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-45.d @@ -1,10 +1,6 @@ -#source: attr-gnu-4-4.s -#source: attr-gnu-4-5.s -#ld: -r -#readelf: -A -#warning: Warning: .* uses -mips32r2 -mfp64 \(set by .*\), .* uses unknown floating point ABI 5 -#target: mips*-*-* - -Attribute Section: gnu -File Attributes - Tag_GNU_MIPS_ABI_FP: Hard float \(MIPS32r2 64-bit FPU\) +#source: attr-gnu-4-4.s -W -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses -mfpxx\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-46.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-46.d new file mode 100644 index 0000000..fb8baf8 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-46.d @@ -0,0 +1,6 @@ +#source: attr-gnu-4-4.s -W -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses -mgp32 -mfp64\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-47.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-47.d new file mode 100644 index 0000000..aa455ff --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-47.d @@ -0,0 +1,6 @@ +#source: attr-gnu-4-4.s -W +#source: attr-gnu-4-7.s -W +#ld: -r +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses unknown floating point ABI 7\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-5-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-5-ph.d new file mode 100644 index 0000000..dd4c1ef --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-5-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -mfpxx -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-5.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-5.s index b21ec3b..06f6c6f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-5.s +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-5.s @@ -1 +1,3 @@ +.module mips32r2 +.module fp=xx .gnu_attribute 4,5 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-50.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-50.d new file mode 100644 index 0000000..37a43f9 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-50.d @@ -0,0 +1,41 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-0.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -hA + +ELF Header: + Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00.* + Class: ELF32 + Data: 2's complement, big endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 0 + Type: REL \(Relocatable file\) + Machine: MIPS R3000 + Version: 0x1 + Entry point address: 0x0 + Start of program headers: 0 \(bytes into file\) + Start of section headers: ... \(bytes into file\) + Flags: 0x70001000, o32, mips32r2 + Size of this header: 52 \(bytes\) + Size of program headers: 0 \(bytes\) + Number of program headers: 0 + Size of section headers: 40 \(bytes\) + Number of section headers: 11 + Section header string table index: 8 +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-51.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-51.d index e183d54..7610b59 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-51.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-51.d @@ -1,5 +1,21 @@ -#source: attr-gnu-4-5.s -#source: attr-gnu-4-1.s -#ld: -r -#warning: Warning: .* uses unknown floating point ABI 5 \(set by .*\), .* uses -mdouble-float -#target: mips*-*-* +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-1.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-52.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-52.d new file mode 100644 index 0000000..b36547d --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-52.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-2.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mfpxx \(set by .*\), .* uses -msingle-float diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-53.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-53.d new file mode 100644 index 0000000..7312d17 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-53.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-3.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-54.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-54.d new file mode 100644 index 0000000..a5beaf1 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-54.d @@ -0,0 +1,6 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-4.s -W -32 -EB +#ld: -r -melf32btsmip +#error: \A[^\n]*: Warning: .* uses -mfpxx \(set by .*\), .* uses -mips32r2 -mfp64 \(12 callee-saved\)\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-55.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-55.d new file mode 100644 index 0000000..f3e3459 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-55.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-56.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-56.d new file mode 100644 index 0000000..856b7fc --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-56.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-57.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-57.d new file mode 100644 index 0000000..fb4906c --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-57.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-7.s -W -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mfpxx \(set by .*\), .* uses unknown floating point ABI 7 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-6-ph.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-6-ph.d new file mode 100644 index 0000000..73ee413 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-6-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -mfp64 -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-6.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-6.s new file mode 100644 index 0000000..adcff8a --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-6.s @@ -0,0 +1,4 @@ +.module mips32r2 +.module gp=32 +.module fp=64 +.gnu_attribute 4,6 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-60.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-60.d new file mode 100644 index 0000000..6cedcf5 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-60.d @@ -0,0 +1,41 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-0.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -hA + +ELF Header: + Magic: 7f 45 4c 46 01 02 01 00 03 00 00 00 00 00 00 00.* + Class: ELF32 + Data: 2's complement, big endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 3 + Type: REL \(Relocatable file\) + Machine: MIPS R3000 + Version: 0x1 + Entry point address: 0x0 + Start of program headers: 0 \(bytes into file\) + Start of section headers: ... \(bytes into file\) + Flags: 0x70001000, o32, mips32r2 + Size of this header: 52 \(bytes\) + Size of program headers: 0 \(bytes\) + Number of program headers: 0 + Size of section headers: 40 \(bytes\) + Number of section headers: 11 + Section header string table index: 8 +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-61.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-61.d new file mode 100644 index 0000000..6e9040c --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-61.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-1.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mgp32 -mfp64 \(set by .*\), .* uses -mdouble-float diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-62.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-62.d new file mode 100644 index 0000000..5eec884 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-62.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-2.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mgp32 -mfp64 \(set by .*\), .* uses -msingle-float diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-63.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-63.d new file mode 100644 index 0000000..eb750f3 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-63.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-3.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-64.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-64.d new file mode 100644 index 0000000..a5dcb7e --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-64.d @@ -0,0 +1,6 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-4.s -W -32 -EB +#ld: -r -melf32btsmip +#error: \A[^\n]*: Warning: .* uses -mgp32 -mfp64 \(set by .*\), .* uses -mips32r2 -mfp64 \(12 callee-saved\)\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-65.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-65.d new file mode 100644 index 0000000..960450d --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-65.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-66.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-66.d new file mode 100644 index 0000000..06cc2d9 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-66.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-67.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-67.d new file mode 100644 index 0000000..a138a31 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-67.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-7.s -W -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mgp32 -mfp64 \(set by .*\), .* uses unknown floating point ABI 7 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-7.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-7.s new file mode 100644 index 0000000..0ab9aea --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-7.s @@ -0,0 +1 @@ +.gnu_attribute 4,7 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-71.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-71.d new file mode 100644 index 0000000..ddfc242 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-4-71.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-7.s -W +#source: attr-gnu-4-1.s +#ld: -r +#warning: Warning: .* uses unknown floating point ABI 7 \(set by .*\), .* uses -mdouble-float diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-0.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-0.s new file mode 100644 index 0000000..b28c578 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-0.s @@ -0,0 +1 @@ +.gnu_attribute 8,0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-00.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-00.d new file mode 100644 index 0000000..2f8e5f0 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-00.d @@ -0,0 +1,9 @@ +#source: attr-gnu-8-0.s +#source: attr-gnu-8-0.s +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-01.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-01.d new file mode 100644 index 0000000..e2cda33 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-01.d @@ -0,0 +1,10 @@ +#source: attr-gnu-8-0.s +#source: attr-gnu-8-1.s +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Tag_GNU_MIPS_ABI_MSA: 128-bit MSA +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-02.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-02.d new file mode 100644 index 0000000..54b196f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-02.d @@ -0,0 +1,10 @@ +#source: attr-gnu-8-0.s +#source: attr-gnu-8-2.s +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Tag_GNU_MIPS_ABI_MSA: \?\?\? \(2\) +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-1.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-1.s new file mode 100644 index 0000000..81c7b7f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-1.s @@ -0,0 +1 @@ +.gnu_attribute 8,1 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-10.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-10.d new file mode 100644 index 0000000..f7c512b --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-10.d @@ -0,0 +1,10 @@ +#source: attr-gnu-8-1.s +#source: attr-gnu-8-0.s +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Tag_GNU_MIPS_ABI_MSA: 128-bit MSA +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-11.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-11.d new file mode 100644 index 0000000..be87af4 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-11.d @@ -0,0 +1,10 @@ +#source: attr-gnu-8-1.s +#source: attr-gnu-8-1.s +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Tag_GNU_MIPS_ABI_MSA: 128-bit MSA +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-12.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-12.d new file mode 100644 index 0000000..10249d0 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-12.d @@ -0,0 +1,4 @@ +#source: attr-gnu-8-1.s +#source: attr-gnu-8-2.s +#ld: -r +#warning: Warning: .* uses -mmsa \(set by .*\), .* uses unknown MSA ABI 2 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-2.s b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-2.s new file mode 100644 index 0000000..0f18f5f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-2.s @@ -0,0 +1 @@ +.gnu_attribute 8,2 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-20.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-20.d new file mode 100644 index 0000000..05f4da0 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-20.d @@ -0,0 +1,10 @@ +#source: attr-gnu-8-2.s +#source: attr-gnu-8-0.s +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Tag_GNU_MIPS_ABI_MSA: \?\?\? \(2\) +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-21.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-21.d new file mode 100644 index 0000000..b8f0e7c --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-21.d @@ -0,0 +1,4 @@ +#source: attr-gnu-8-2.s +#source: attr-gnu-8-1.s +#ld: -r +#warning: Warning: .* uses unknown MSA ABI 2 \(set by .*\), .* uses -mmsa diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-22.d b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-22.d new file mode 100644 index 0000000..908ce4f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/attr-gnu-8-22.d @@ -0,0 +1,10 @@ +#source: attr-gnu-8-2.s +#source: attr-gnu-8-2.s +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Tag_GNU_MIPS_ABI_MSA: \?\?\? \(2\) +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-dyn.s b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-dyn.s new file mode 100644 index 0000000..a56d1c9 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-dyn.s @@ -0,0 +1,18 @@ +# Create dummy DSO functions for everything that these tests call. + + .abicalls + .option pic2 + + .set filter, -1 + + .macro test_one, name, mask + .globl \name + .ent \name +\name: + jr $31 + .end \name + .endm + + .include "compressed-plt-1.s" + + test_all diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.od new file mode 100644 index 0000000..c17dacb --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.od @@ -0,0 +1,411 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# At present, all n32 PLT entries use the standard encoding. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c0e1020 lui \$14,0x1020 +.*: 8dd90000 lw \$25,0\(\$14\) +.*: 25ce0000 addiu \$14,\$14,0 +.*: 030ec023 subu \$24,\$24,\$14 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90008 lw \$25,8\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80008 addiu \$24,\$15,8 + +10100030 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100040 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100050 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100060 <f_lo_iu_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90018 lw \$25,24\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80018 addiu \$24,\$15,24 + +10100070 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100080 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100090 <f_iu_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90024 lw \$25,36\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80024 addiu \$24,\$15,36 + +101000a0 <f_lo_iu_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90028 lw \$25,40\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80028 addiu \$24,\$15,40 + +101000b0 <f_lo_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9002c lw \$25,44\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8002c addiu \$24,\$15,44 + +101000c0 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +101000d0 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +101000e0 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000f0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +10100100 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +10100110 <f_lo_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90044 lw \$25,68\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80044 addiu \$24,\$15,68 + +10100120 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +10100130 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +10100140 <f_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90050 lw \$25,80\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80050 addiu \$24,\$15,80 + +10100150 <f_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90054 lw \$25,84\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80054 addiu \$24,\$15,84 + +10100160 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +10100170 <f_iu_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9005c lw \$25,92\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8005c addiu \$24,\$15,92 + +10100180 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100190 <f_lo_iu_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90064 lw \$25,100\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80064 addiu \$24,\$15,100 + +101001a0 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +101001b0 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +101001c0 <f_lo_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90070 lw \$25,112\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80070 addiu \$24,\$15,112 + +101001d0 <f_lo@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90074 lw \$25,116\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80074 addiu \$24,\$15,116 + +Disassembly of section \.MIPS\.stubs: + +10101000 <_MIPS_STUBS_>: +# Lazy-binding stub for f_iu. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 24180021 li \$24,33 +# Lazy-binding stub for f_ic. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 24180020 li \$24,32 +# Lazy-binding stub for f_iu_ic. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 2418001f li \$24,31 + \.\.\. + +Disassembly of section \.text\.a: + +10102000 <testc>: +.*: .... .... jalx [0-9a-f]+ <f_dc@plt> +.*: 6500 nop +.*: f070 9b50 lw \$2,-32656\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jalx [0-9a-f]+ <f_ic_dc@plt> +.*: 6500 nop +.*: f010 9b58 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_du_dc@plt> +.*: 6500 nop +.*: f010 9b5c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_du_ic_dc@plt> +.*: 6500 nop +.*: f030 9b40 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_iu_dc@plt> +.*: 6500 nop +.*: f070 9b4c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jalx [0-9a-f]+ <f_iu_ic_dc@plt> +.*: 6500 nop +.*: f030 9b44 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_iu_du_dc@plt> +.*: 6500 nop +.*: f030 9b48 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 6500 nop +.*: f030 9b4c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_dc@plt> +.*: 6500 nop +.*: f030 9b50 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_ic_dc@plt> +.*: 6500 nop +.*: f030 9b54 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_du_dc@plt> +.*: 6500 nop +.*: f030 9b58 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 6500 nop +.*: f030 9b5c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_dc@plt> +.*: 6500 nop +.*: f050 9b40 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_ic_dc@plt> +.*: 6500 nop +.*: f050 9b44 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 6500 nop +.*: f050 9b48 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 6500 nop +.*: f050 9b4c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: e820 jr \$31 + +Disassembly of section \.text\.b: + +10103000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628074 lw \$2,-32652\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@plt +.*: 8c62806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@plt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@plt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10104000 <testlo>: +.*: 240201d0 li \$2,464 +# ^ low 16 bits of f_lo@plt +.*: 24020110 li \$2,272 +# ^ low 16 bits of f_lo_dc@plt +.*: 240200b0 li \$2,176 +# ^ low 16 bits of f_lo_ic@plt +.*: 240201c0 li \$2,448 +# ^ low 16 bits of f_lo_ic_dc@plt +.*: 24020160 li \$2,352 +# ^ low 16 bits of f_lo_du@plt +.*: 240200c0 li \$2,192 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 24020080 li \$2,128 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 24020040 li \$2,64 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 24020020 li \$2,32 +# ^ low 16 bits of f_lo_iu@plt +.*: 24020060 li \$2,96 +# ^ low 16 bits of f_lo_iu_dc@plt +.*: 240200a0 li \$2,160 +# ^ low 16 bits of f_lo_iu_ic@plt +.*: 24020190 li \$2,400 +# ^ low 16 bits of f_lo_iu_ic_dc@plt +.*: 24020130 li \$2,304 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 24020030 li \$2,48 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 240201a0 li \$2,416 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 240201b0 li \$2,432 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.rd new file mode 100644 index 0000000..82b0313 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-mips16.rd @@ -0,0 +1,167 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100040 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100080 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 101000a0 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 101000b0 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 101000c0 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 10100130 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 10100160 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 10100190 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 101001a0 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 101001b0 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 101001c0 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 101001d0 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# _lo symbols have their address taken, so their PLT symbols need to have +# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish +# them from old-style lazy-binding stubs. Non-_lo symbols are only called, +# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation. + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100040 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_dc + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic + .*: 10100080 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_dc + .*: 101000a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 101000b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 101000c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_dc + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du + .*: 10100130 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic_dc + .*: 10100160 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic_dc +#... + .*: 10100190 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 101001a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 101001b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 101001c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 101001d0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. The symbol value +# is the address of the lazy-binding stub. + 31: 10101020 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 10101010 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 10101000 0 FUNC GLOBAL DEFAULT UND f_iu + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 10100150 + 1020100c -32740\(gp\) 101000f0 + 10201010 -32736\(gp\) 101000e0 + 10201014 -32732\(gp\) 10100170 + 10201018 -32728\(gp\) 10100070 + 1020101c -32724\(gp\) 10100180 + 10201020 -32720\(gp\) 101000b0 + 10201024 -32716\(gp\) 101001c0 + 10201028 -32712\(gp\) 10100080 + 1020102c -32708\(gp\) 10100040 + 10201030 -32704\(gp\) 101000a0 + 10201034 -32700\(gp\) 10100190 + 10201038 -32696\(gp\) 101001a0 + 1020103c -32692\(gp\) 101001b0 + 10201040 -32688\(gp\) 10100090 + 10201044 -32684\(gp\) 10100120 + 10201048 -32680\(gp\) 10100100 + 1020104c -32676\(gp\) 10100020 + 10201050 -32672\(gp\) 10100060 + 10201054 -32668\(gp\) 10100130 + 10201058 -32664\(gp\) 10100030 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 1020105c -32660\(gp\) 10101020 10101020 FUNC UND f_iu_ic + 10201060 -32656\(gp\) 10101010 10101010 FUNC UND f_ic + 10201064 -32652\(gp\) 10101000 10101000 FUNC UND f_iu + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100020 FUNC UND f_lo_iu + 1020000c 10100000 10100030 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100040 FUNC UND f_lo_du_ic_dc + 10200014 10100000 00000000 FUNC UND f_du_dc + 10200018 10100000 10100060 FUNC UND f_lo_iu_dc + 1020001c 10100000 00000000 FUNC UND f_iu_du_ic + 10200020 10100000 10100080 FUNC UND f_lo_du_ic + 10200024 10100000 00000000 FUNC UND f_iu_dc + 10200028 10100000 101000a0 FUNC UND f_lo_iu_ic + 1020002c 10100000 101000b0 FUNC UND f_lo_ic + 10200030 10100000 101000c0 FUNC UND f_lo_du_dc + 10200034 10100000 00000000 FUNC UND f_du + 10200038 10100000 00000000 FUNC UND f_du_ic_dc + 1020003c 10100000 00000000 FUNC UND f_du_ic + 10200040 10100000 00000000 FUNC UND f_iu_du_dc + 10200044 10100000 10100110 FUNC UND f_lo_dc + 10200048 10100000 00000000 FUNC UND f_iu_du + 1020004c 10100000 10100130 FUNC UND f_lo_iu_du + 10200050 10100000 00000000 FUNC UND f_dc + 10200054 10100000 00000000 FUNC UND f_ic_dc + 10200058 10100000 10100160 FUNC UND f_lo_du + 1020005c 10100000 00000000 FUNC UND f_iu_ic_dc + 10200060 10100000 00000000 FUNC UND f_iu_du_ic_dc + 10200064 10100000 10100190 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 101001a0 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 101001b0 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 101001c0 FUNC UND f_lo_ic_dc + 10200074 10100000 101001d0 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.od new file mode 100644 index 0000000..fc0d4ea --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.od @@ -0,0 +1,411 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# At present, all n32 PLT entries use the standard encoding. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c0e1020 lui \$14,0x1020 +.*: 8dd90000 lw \$25,0\(\$14\) +.*: 25ce0000 addiu \$14,\$14,0 +.*: 030ec023 subu \$24,\$24,\$14 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90008 lw \$25,8\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80008 addiu \$24,\$15,8 + +10100030 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100040 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100050 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100060 <f_lo_iu_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90018 lw \$25,24\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80018 addiu \$24,\$15,24 + +10100070 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100080 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100090 <f_iu_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90024 lw \$25,36\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80024 addiu \$24,\$15,36 + +101000a0 <f_lo_iu_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90028 lw \$25,40\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80028 addiu \$24,\$15,40 + +101000b0 <f_lo_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9002c lw \$25,44\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8002c addiu \$24,\$15,44 + +101000c0 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +101000d0 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +101000e0 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000f0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +10100100 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +10100110 <f_lo_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90044 lw \$25,68\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80044 addiu \$24,\$15,68 + +10100120 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +10100130 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +10100140 <f_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90050 lw \$25,80\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80050 addiu \$24,\$15,80 + +10100150 <f_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90054 lw \$25,84\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80054 addiu \$24,\$15,84 + +10100160 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +10100170 <f_iu_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9005c lw \$25,92\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8005c addiu \$24,\$15,92 + +10100180 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100190 <f_lo_iu_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90064 lw \$25,100\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80064 addiu \$24,\$15,100 + +101001a0 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +101001b0 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +101001c0 <f_lo_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90070 lw \$25,112\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80070 addiu \$24,\$15,112 + +101001d0 <f_lo@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90074 lw \$25,116\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80074 addiu \$24,\$15,116 + +Disassembly of section \.MIPS\.stubs: + +10101000 <_MIPS_STUBS_>: +# Lazy-binding stub for f_iu. +.*: ff3c 8010 lw \$25,-32752\(\$28\) +.*: 0dff move \$15,\$31 +.*: 45d9 jalr \$25 +.*: 3300 0021 li \$24,33 +# Lazy-binding stub for f_ic. +.*: ff3c 8010 lw \$25,-32752\(\$28\) +.*: 0dff move \$15,\$31 +.*: 45d9 jalr \$25 +.*: 3300 0020 li \$24,32 +# Lazy-binding stub for f_iu_ic. +.*: ff3c 8010 lw \$25,-32752\(\$28\) +.*: 0dff move \$15,\$31 +.*: 45d9 jalr \$25 +.*: 3300 001f li \$24,31 + \.\.\. + +Disassembly of section \.text\.a: + +10102000 <testc>: +.*: .... .... jalx [0-9a-f]+ <f_dc@plt> +.*: 0000 0000 nop +.*: fc43 8070 lw \$2,-32656\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jalx [0-9a-f]+ <f_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 8018 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_du_dc@plt> +.*: 0000 0000 nop +.*: fc43 801c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_du_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 8020 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_iu_dc@plt> +.*: 0000 0000 nop +.*: fc43 806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jalx [0-9a-f]+ <f_iu_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 8024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_iu_du_dc@plt> +.*: 0000 0000 nop +.*: fc43 8028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_dc@plt> +.*: 0000 0000 nop +.*: fc43 8030 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 8034 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_du_dc@plt> +.*: 0000 0000 nop +.*: fc43 8038 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 803c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_dc@plt> +.*: 0000 0000 nop +.*: fc43 8040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 8044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 0000 0000 nop +.*: fc43 8048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jalx [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 0000 0000 nop +.*: fc43 804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 459f jr \$31 + +Disassembly of section \.text\.b: + +10103000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628074 lw \$2,-32652\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@plt +.*: 8c62806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@plt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@plt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10104000 <testlo>: +.*: 3040 01d0 li \$2,464 +# ^ low 16 bits of f_lo@plt +.*: 3040 0110 li \$2,272 +# ^ low 16 bits of f_lo_dc@plt +.*: 3040 00b0 li \$2,176 +# ^ low 16 bits of f_lo_ic@plt +.*: 3040 01c0 li \$2,448 +# ^ low 16 bits of f_lo_ic_dc@plt +.*: 3040 0160 li \$2,352 +# ^ low 16 bits of f_lo_du@plt +.*: 3040 00c0 li \$2,192 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 3040 0080 li \$2,128 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 3040 0040 li \$2,64 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 3040 0020 li \$2,32 +# ^ low 16 bits of f_lo_iu@plt +.*: 3040 0060 li \$2,96 +# ^ low 16 bits of f_lo_iu_dc@plt +.*: 3040 00a0 li \$2,160 +# ^ low 16 bits of f_lo_iu_ic@plt +.*: 3040 0190 li \$2,400 +# ^ low 16 bits of f_lo_iu_ic_dc@plt +.*: 3040 0130 li \$2,304 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 3040 0030 li \$2,48 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 3040 01a0 li \$2,416 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 3040 01b0 li \$2,432 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.rd new file mode 100644 index 0000000..d4dc838 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-n32-umips.rd @@ -0,0 +1,167 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100040 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100080 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 101000a0 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 101000b0 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 101000c0 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 10100130 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 10100160 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 10100190 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 101001a0 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 101001b0 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 101001c0 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 101001d0 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# _lo symbols have their address taken, so their PLT symbols need to have +# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish +# them from old-style lazy-binding stubs. Non-_lo symbols are only called, +# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation. + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100040 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_dc + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic + .*: 10100080 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_dc + .*: 101000a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 101000b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 101000c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_dc + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du + .*: 10100130 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic_dc + .*: 10100160 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic_dc +#... + .*: 10100190 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 101001a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 101001b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 101001c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 101001d0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. The symbol value +# is the address of the lazy-binding stub. + 31: 10101019 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 1010100d 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 10101001 0 FUNC GLOBAL DEFAULT UND f_iu + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 10100150 + 1020100c -32740\(gp\) 101000f0 + 10201010 -32736\(gp\) 101000e0 + 10201014 -32732\(gp\) 10100170 + 10201018 -32728\(gp\) 10100070 + 1020101c -32724\(gp\) 10100180 + 10201020 -32720\(gp\) 101000b0 + 10201024 -32716\(gp\) 101001c0 + 10201028 -32712\(gp\) 10100080 + 1020102c -32708\(gp\) 10100040 + 10201030 -32704\(gp\) 101000a0 + 10201034 -32700\(gp\) 10100190 + 10201038 -32696\(gp\) 101001a0 + 1020103c -32692\(gp\) 101001b0 + 10201040 -32688\(gp\) 10100090 + 10201044 -32684\(gp\) 10100120 + 10201048 -32680\(gp\) 10100100 + 1020104c -32676\(gp\) 10100020 + 10201050 -32672\(gp\) 10100060 + 10201054 -32668\(gp\) 10100130 + 10201058 -32664\(gp\) 10100030 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 1020105c -32660\(gp\) 10101019 10101019 FUNC UND f_iu_ic + 10201060 -32656\(gp\) 1010100d 1010100d FUNC UND f_ic + 10201064 -32652\(gp\) 10101001 10101001 FUNC UND f_iu + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100020 FUNC UND f_lo_iu + 1020000c 10100000 10100030 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100040 FUNC UND f_lo_du_ic_dc + 10200014 10100000 00000000 FUNC UND f_du_dc + 10200018 10100000 10100060 FUNC UND f_lo_iu_dc + 1020001c 10100000 00000000 FUNC UND f_iu_du_ic + 10200020 10100000 10100080 FUNC UND f_lo_du_ic + 10200024 10100000 00000000 FUNC UND f_iu_dc + 10200028 10100000 101000a0 FUNC UND f_lo_iu_ic + 1020002c 10100000 101000b0 FUNC UND f_lo_ic + 10200030 10100000 101000c0 FUNC UND f_lo_du_dc + 10200034 10100000 00000000 FUNC UND f_du + 10200038 10100000 00000000 FUNC UND f_du_ic_dc + 1020003c 10100000 00000000 FUNC UND f_du_ic + 10200040 10100000 00000000 FUNC UND f_iu_du_dc + 10200044 10100000 10100110 FUNC UND f_lo_dc + 10200048 10100000 00000000 FUNC UND f_iu_du + 1020004c 10100000 10100130 FUNC UND f_lo_iu_du + 10200050 10100000 00000000 FUNC UND f_dc + 10200054 10100000 00000000 FUNC UND f_ic_dc + 10200058 10100000 10100160 FUNC UND f_lo_du + 1020005c 10100000 00000000 FUNC UND f_iu_ic_dc + 10200060 10100000 00000000 FUNC UND f_iu_du_ic_dc + 10200064 10100000 10100190 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 101001a0 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 101001b0 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 101001c0 FUNC UND f_lo_ic_dc + 10200074 10100000 101001d0 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.od new file mode 100644 index 0000000..c48ef7f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.od @@ -0,0 +1,557 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# Only _dc (direct call from compressed code) functions should have a +# MIPS16 PLT. Note that indirect calls do not influence the choice, +# so f_ic and f_lo_ic have MIPS rather than MIPS16 PLTs. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90008 lw \$25,8\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80008 addiu \$24,\$15,8 + +10100030 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100040 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100050 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100060 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100070 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100080 <f_lo_iu_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90028 lw \$25,40\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80028 addiu \$24,\$15,40 + +10100090 <f_lo_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9002c lw \$25,44\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8002c addiu \$24,\$15,44 + +101000a0 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +101000b0 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +101000c0 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000d0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +101000e0 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +101000f0 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +10100100 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +10100110 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +10100120 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100130 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +10100140 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +10100150 <f_lo@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90074 lw \$25,116\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80074 addiu \$24,\$15,116 + +10100160 <f_lo_iu_du_dc@mips16plt>: +.*: b203 lw \$2,1010016c <f_lo_iu_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020000c + +10100170 <f_lo_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010017c <f_lo_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200010 + +10100180 <f_du_dc@mips16plt>: +.*: b203 lw \$2,1010018c <f_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200014 + +10100190 <f_lo_iu_dc@mips16plt>: +.*: b203 lw \$2,1010019c <f_lo_iu_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200018 + +101001a0 <f_iu_dc@mips16plt>: +.*: b203 lw \$2,101001ac <f_iu_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200024 + +101001b0 <f_lo_du_dc@mips16plt>: +.*: b203 lw \$2,101001bc <f_lo_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200030 + +101001c0 <f_du_ic_dc@mips16plt>: +.*: b203 lw \$2,101001cc <f_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200038 + +101001d0 <f_iu_du_dc@mips16plt>: +.*: b203 lw \$2,101001dc <f_iu_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200040 + +101001e0 <f_lo_dc@mips16plt>: +.*: b203 lw \$2,101001ec <f_lo_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200044 + +101001f0 <f_dc@mips16plt>: +.*: b203 lw \$2,101001fc <f_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200050 + +10100200 <f_ic_dc@mips16plt>: +.*: b203 lw \$2,1010020c <f_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200054 + +10100210 <f_iu_ic_dc@mips16plt>: +.*: b203 lw \$2,1010021c <f_iu_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020005c + +10100220 <f_iu_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010022c <f_iu_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200060 + +10100230 <f_lo_iu_ic_dc@mips16plt>: +.*: b203 lw \$2,1010023c <f_lo_iu_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200064 + +10100240 <f_lo_iu_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010024c <f_lo_iu_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020006c + +10100250 <f_lo_ic_dc@mips16plt>: +.*: b203 lw \$2,1010025c <f_lo_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200070 + +Disassembly of section \.text\.a: + +10101000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@mips16plt> +.*: 6500 nop +.*: f090 9b4c lw \$2,-32628\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@mips16plt> +.*: 6500 nop +.*: f010 9b58 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_du_dc@mips16plt> +.*: 6500 nop +.*: f010 9b5c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b40 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_iu_dc@mips16plt> +.*: 6500 nop +.*: f090 9b48 lw \$2,-32632\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jal [0-9a-f]+ <f_iu_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b44 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_dc@mips16plt> +.*: 6500 nop +.*: f030 9b48 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b4c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@mips16plt> +.*: 6500 nop +.*: f030 9b50 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b54 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_dc@mips16plt> +.*: 6500 nop +.*: f030 9b58 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b5c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_dc@mips16plt> +.*: 6500 nop +.*: f050 9b40 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_ic_dc@mips16plt> +.*: 6500 nop +.*: f050 9b44 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_dc@mips16plt> +.*: 6500 nop +.*: f050 9b48 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f050 9b4c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: e820 jr \$31 + +Disassembly of section \.text\.b: + +10102000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628090 lw \$2,-32624\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@mips16plt +.*: 8c628088 lw \$2,-32632\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@mips16plt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@plt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@mips16plt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10103000 <testlo>: +.*: 24020150 li \$2,336 +# ^ low 16 bits of f_lo@plt +.*: 240201e1 li \$2,481 +# ^ low 16 bits of f_lo_dc@mips16plt +.*: 24020090 li \$2,144 +# ^ low 16 bits of f_lo_ic@plt +.*: 24020251 li \$2,593 +# ^ low 16 bits of f_lo_ic_dc@mips16plt +.*: 24020110 li \$2,272 +# ^ low 16 bits of f_lo_du@plt +.*: 240200a0 li \$2,160 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 24020070 li \$2,112 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 24020040 li \$2,64 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 24020020 li \$2,32 +# ^ low 16 bits of f_lo_iu@plt +.*: 24020191 li \$2,401 +# ^ low 16 bits of f_lo_iu_dc@mips16plt +.*: 24020080 li \$2,128 +# ^ low 16 bits of f_lo_iu_ic@plt +.*: 24020231 li \$2,561 +# ^ low 16 bits of f_lo_iu_ic_dc@mips16plt +.*: 24020100 li \$2,256 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 24020030 li \$2,48 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 24020130 li \$2,304 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 24020140 li \$2,320 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + +Disassembly of section \.text\.d: + +10104000 <testgot>: +.*: 8f828094 lw \$2,-32620\(\$28\) +# ^ global GOT entry for f +.*: 8f82806c lw \$2,-32660\(\$28\) +# ^ local GOT entry for f_dc@mips16plt +.*: 8f82808c lw \$2,-32628\(\$28\) +# ^ global GOT entry for f_ic +.*: 8f828018 lw \$2,-32744\(\$28\) +# ^ local GOT entry for f_ic_dc@mips16plt +.*: 8f828070 lw \$2,-32656\(\$28\) +# ^ local GOT entry for f_du@plt +.*: 8f828074 lw \$2,-32652\(\$28\) +# ^ local GOT entry for f_du_dc@plt +.*: 8f82801c lw \$2,-32740\(\$28\) +# ^ local GOT entry for f_du_ic@plt +.*: 8f828020 lw \$2,-32736\(\$28\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: 8f828090 lw \$2,-32624\(\$28\) +# ^ global GOT entry for f_iu +.*: 8f828050 lw \$2,-32688\(\$28\) +# ^ local GOT entry for f_iu_dc@mips16plt +.*: 8f828088 lw \$2,-32632\(\$28\) +# ^ global GOT entry for f_iu_ic +.*: 8f828024 lw \$2,-32732\(\$28\) +# ^ local GOT entry for f_iu_ic_dc@mips16plt +.*: 8f828054 lw \$2,-32684\(\$28\) +# ^ local GOT entry for f_iu_du@plt +.*: 8f828058 lw \$2,-32680\(\$28\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: 8f828028 lw \$2,-32728\(\$28\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: 8f82802c lw \$2,-32724\(\$28\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: 8f828078 lw \$2,-32648\(\$28\) +# ^ local GOT entry for f_lo@plt +.*: 8f82807c lw \$2,-32644\(\$28\) +# ^ local GOT entry for f_lo_dc@mips16plt +.*: 8f828030 lw \$2,-32720\(\$28\) +# ^ local GOT entry for f_lo_ic@plt +.*: 8f828034 lw \$2,-32716\(\$28\) +# ^ local GOT entry for f_lo_ic_dc@mips16plt +.*: 8f828080 lw \$2,-32640\(\$28\) +# ^ local GOT entry for f_lo_du@plt +.*: 8f828084 lw \$2,-32636\(\$28\) +# ^ local GOT entry for f_lo_du_dc@plt +.*: 8f828038 lw \$2,-32712\(\$28\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: 8f82803c lw \$2,-32708\(\$28\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: 8f82805c lw \$2,-32676\(\$28\) +# ^ local GOT entry for f_lo_iu@plt +.*: 8f828060 lw \$2,-32672\(\$28\) +# ^ local GOT entry for f_lo_iu_dc@mips16plt +.*: 8f828040 lw \$2,-32704\(\$28\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: 8f828044 lw \$2,-32700\(\$28\) +# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt +.*: 8f828064 lw \$2,-32668\(\$28\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: 8f828068 lw \$2,-32664\(\$28\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: 8f828048 lw \$2,-32696\(\$28\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: 8f82804c lw \$2,-32692\(\$28\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.rd new file mode 100644 index 0000000..db623b7 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-got.rd @@ -0,0 +1,179 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100040 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 10100050 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100191 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100070 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 101001a1 f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 10100080 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 10100090 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 101000a0 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 101000b0 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 101000c0 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 101000d0 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 101000e0 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 101001e1 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 101000f0 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 10100100 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 101001f1 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 10100201 f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 10100211 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 10100120 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 10100231 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 10100130 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 10100140 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 10100251 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 10100150 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# All symbols have their address taken, so PLT symbols need to have a nonzero +# value. They must also have STO_MIPS_PLT in order to distinguish them from +# old-style lazy-binding stubs). +# +# A MIPS16 PLT should only be used as the symbol value if the function has +# a direct MIPS16 caller (dc) and no direct MIPS caller (du). + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100040 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 10100050 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_dc + .*: 10100191 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic + .*: 10100070 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 101001a1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_dc + .*: 10100080 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 10100090 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 101000a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 101000b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du + .*: 101000c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic_dc + .*: 101000d0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic + .*: 101000e0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_dc + .*: 101001e1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 101000f0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du + .*: 10100100 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 101001f1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_dc + .*: 10100201 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_ic_dc + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 10100211 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_ic_dc + .*: 10100120 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic_dc +#... + .*: 10100231 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 10100130 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 10100140 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 10100251 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100150 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. Since the functions +# have their addresses taken, they cannot use a lazy-binding stub. +# The symbol values are therefore all zero. + 31: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu + 34: 00000000 0 FUNC GLOBAL DEFAULT UND f + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 10100201 + 1020100c -32740\(gp\) 101000d0 + 10201010 -32736\(gp\) 101000c0 + 10201014 -32732\(gp\) 10100211 + 10201018 -32728\(gp\) 10100060 + 1020101c -32724\(gp\) 10100120 + 10201020 -32720\(gp\) 10100090 + 10201024 -32716\(gp\) 10100251 + 10201028 -32712\(gp\) 10100070 + 1020102c -32708\(gp\) 10100040 + 10201030 -32704\(gp\) 10100080 + 10201034 -32700\(gp\) 10100231 + 10201038 -32696\(gp\) 10100130 + 1020103c -32692\(gp\) 10100140 + 10201040 -32688\(gp\) 101001a1 + 10201044 -32684\(gp\) 101000f0 + 10201048 -32680\(gp\) 101000e0 + 1020104c -32676\(gp\) 10100020 + 10201050 -32672\(gp\) 10100191 + 10201054 -32668\(gp\) 10100100 + 10201058 -32664\(gp\) 10100030 + 1020105c -32660\(gp\) 101001f1 + 10201060 -32656\(gp\) 101000b0 + 10201064 -32652\(gp\) 10100050 + 10201068 -32648\(gp\) 10100150 + 1020106c -32644\(gp\) 101001e1 + 10201070 -32640\(gp\) 10100110 + 10201074 -32636\(gp\) 101000a0 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 10201078 -32632\(gp\) 00000000 00000000 FUNC UND f_iu_ic + 1020107c -32628\(gp\) 00000000 00000000 FUNC UND f_ic + 10201080 -32624\(gp\) 00000000 00000000 FUNC UND f_iu + 10201084 -32620\(gp\) 00000000 00000000 FUNC UND f + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100020 FUNC UND f_lo_iu + 1020000c 10100000 10100030 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100040 FUNC UND f_lo_du_ic_dc + 10200014 10100000 10100050 FUNC UND f_du_dc + 10200018 10100000 10100191 FUNC UND f_lo_iu_dc + 1020001c 10100000 10100060 FUNC UND f_iu_du_ic + 10200020 10100000 10100070 FUNC UND f_lo_du_ic + 10200024 10100000 101001a1 FUNC UND f_iu_dc + 10200028 10100000 10100080 FUNC UND f_lo_iu_ic + 1020002c 10100000 10100090 FUNC UND f_lo_ic + 10200030 10100000 101000a0 FUNC UND f_lo_du_dc + 10200034 10100000 101000b0 FUNC UND f_du + 10200038 10100000 101000c0 FUNC UND f_du_ic_dc + 1020003c 10100000 101000d0 FUNC UND f_du_ic + 10200040 10100000 101000e0 FUNC UND f_iu_du_dc + 10200044 10100000 101001e1 FUNC UND f_lo_dc + 10200048 10100000 101000f0 FUNC UND f_iu_du + 1020004c 10100000 10100100 FUNC UND f_lo_iu_du + 10200050 10100000 101001f1 FUNC UND f_dc + 10200054 10100000 10100201 FUNC UND f_ic_dc + 10200058 10100000 10100110 FUNC UND f_lo_du + 1020005c 10100000 10100211 FUNC UND f_iu_ic_dc + 10200060 10100000 10100120 FUNC UND f_iu_du_ic_dc + 10200064 10100000 10100231 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 10100130 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 10100140 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 10100251 FUNC UND f_lo_ic_dc + 10200074 10100000 10100150 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.od new file mode 100644 index 0000000..e76ca4f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.od @@ -0,0 +1,110 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# Only _dc (direct call from compressed code) functions should have a +# MIPS16 PLT. Note that indirect calls do not influence the choice, +# so f_ic and f_lo_ic have MIPS rather than MIPS16 PLTs. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90008 lw \$25,8\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80008 addiu \$24,\$15,8 + +10100030 <f_lo@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100040 <f_lo_dc@mips16plt>: +.*: b203 lw \$2,1010004c <f_lo_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020000c + +10100050 <f_dc@mips16plt>: +.*: b203 lw \$2,1010005c <f_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200010 + +10100060 <f_ic_dc@mips16plt>: +.*: b203 lw \$2,1010006c <f_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200014 + +10100070 <f_lo_ic_dc@mips16plt>: +.*: b203 lw \$2,1010007c <f_lo_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200018 + +Disassembly of section \.MIPS\.stubs: + +10101000 <_MIPS_STUBS_>: +# Lazy-binding stub for f_ic. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 24180009 li \$24,9 + \.\.\. + +Disassembly of section \.text\.a: + +10102000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@mips16plt> +.*: 6500 nop +.*: f030 9b44 lw \$2,-32732\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@mips16plt> +.*: 6500 nop +.*: f010 9b58 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@mips16plt> +.*: 6500 nop +.*: f010 9b5c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_lo_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b40 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@mips16plt +.*: e820 jr \$31 + +Disassembly of section \.text\.c: + +10103000 <testlo>: +.*: 24020030 li \$2,48 +# ^ low 16 bits of f_lo@plt +.*: 24020041 li \$2,65 +# ^ low 16 bits of f_lo_dc@mips16plt +.*: 24020020 li \$2,32 +# ^ low 16 bits of f_lo_ic@plt +.*: 24020071 li \$2,113 +# ^ low 16 bits of f_lo_ic_dc@mips16plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.rd new file mode 100644 index 0000000..a5d61be --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-only.rd @@ -0,0 +1,82 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x9 + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 48 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_ic +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100041 f_lo_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_ic_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100071 f_lo_ic_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# _lo symbols have their address taken, so their PLT symbols need to have +# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish +# them from old-style lazy-binding stubs. Non-_lo symbols are only called, +# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation. +# +# A MIPS16 PLT should only be used as the symbol value if the function has +# a direct MIPS16 caller (dc) and no direct MIPS caller (du). +#... + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 10100041 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic_dc +#... + .*: 10100071 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. The symbol value +# is the address of the lazy-binding stub. + 9: 10101000 0 FUNC GLOBAL DEFAULT UND f_ic + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 10100061 + 1020100c -32740\(gp\) 10100020 + 10201010 -32736\(gp\) 10100071 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 10201014 -32732\(gp\) 10101000 10101000 FUNC UND f_ic + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100020 FUNC UND f_lo_ic + 1020000c 10100000 10100041 FUNC UND f_lo_dc + 10200010 10100000 00000000 FUNC UND f_dc + 10200014 10100000 00000000 FUNC UND f_ic_dc + 10200018 10100000 10100071 FUNC UND f_lo_ic_dc + 1020001c 10100000 10100030 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.od new file mode 100644 index 0000000..7fc547b --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.od @@ -0,0 +1,489 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# Only _dc (direct call from compressed code) functions should have a +# MIPS16 PLT. Note that indirect calls do not influence the choice, +# so f_ic and f_lo_ic have MIPS rather than MIPS16 PLTs. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90008 lw \$25,8\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80008 addiu \$24,\$15,8 + +10100030 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100040 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100050 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100060 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100070 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100080 <f_lo_iu_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90028 lw \$25,40\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80028 addiu \$24,\$15,40 + +10100090 <f_lo_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9002c lw \$25,44\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8002c addiu \$24,\$15,44 + +101000a0 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +101000b0 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +101000c0 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000d0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +101000e0 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +101000f0 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +10100100 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +10100110 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +10100120 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100130 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +10100140 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +10100150 <f_lo@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90074 lw \$25,116\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80074 addiu \$24,\$15,116 + +10100160 <f_lo_iu_du_dc@mips16plt>: +.*: b203 lw \$2,1010016c <f_lo_iu_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020000c + +10100170 <f_lo_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010017c <f_lo_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200010 + +10100180 <f_du_dc@mips16plt>: +.*: b203 lw \$2,1010018c <f_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200014 + +10100190 <f_lo_iu_dc@mips16plt>: +.*: b203 lw \$2,1010019c <f_lo_iu_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200018 + +101001a0 <f_iu_dc@mips16plt>: +.*: b203 lw \$2,101001ac <f_iu_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200024 + +101001b0 <f_lo_du_dc@mips16plt>: +.*: b203 lw \$2,101001bc <f_lo_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200030 + +101001c0 <f_du_ic_dc@mips16plt>: +.*: b203 lw \$2,101001cc <f_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200038 + +101001d0 <f_iu_du_dc@mips16plt>: +.*: b203 lw \$2,101001dc <f_iu_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200040 + +101001e0 <f_lo_dc@mips16plt>: +.*: b203 lw \$2,101001ec <f_lo_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200044 + +101001f0 <f_dc@mips16plt>: +.*: b203 lw \$2,101001fc <f_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200050 + +10100200 <f_ic_dc@mips16plt>: +.*: b203 lw \$2,1010020c <f_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200054 + +10100210 <f_iu_ic_dc@mips16plt>: +.*: b203 lw \$2,1010021c <f_iu_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020005c + +10100220 <f_iu_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010022c <f_iu_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200060 + +10100230 <f_lo_iu_ic_dc@mips16plt>: +.*: b203 lw \$2,1010023c <f_lo_iu_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200064 + +10100240 <f_lo_iu_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010024c <f_lo_iu_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020006c + +10100250 <f_lo_ic_dc@mips16plt>: +.*: b203 lw \$2,1010025c <f_lo_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200070 + +Disassembly of section \.text\.a: + +10101000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@mips16plt> +.*: 6500 nop +.*: f070 9b50 lw \$2,-32656\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@mips16plt> +.*: 6500 nop +.*: f010 9b58 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_du_dc@mips16plt> +.*: 6500 nop +.*: f010 9b5c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b40 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_iu_dc@mips16plt> +.*: 6500 nop +.*: f070 9b4c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jal [0-9a-f]+ <f_iu_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b44 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_dc@mips16plt> +.*: 6500 nop +.*: f030 9b48 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b4c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@mips16plt> +.*: 6500 nop +.*: f030 9b50 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b54 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_dc@mips16plt> +.*: 6500 nop +.*: f030 9b58 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b5c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_dc@mips16plt> +.*: 6500 nop +.*: f050 9b40 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_ic_dc@mips16plt> +.*: 6500 nop +.*: f050 9b44 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_dc@mips16plt> +.*: 6500 nop +.*: f050 9b48 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f050 9b4c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: e820 jr \$31 + +Disassembly of section \.text\.b: + +10102000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628074 lw \$2,-32652\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@mips16plt +.*: 8c62806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@mips16plt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@plt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@mips16plt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10103000 <testlo>: +.*: 24020150 li \$2,336 +# ^ low 16 bits of f_lo@plt +.*: 240201e1 li \$2,481 +# ^ low 16 bits of f_lo_dc@mips16plt +.*: 24020090 li \$2,144 +# ^ low 16 bits of f_lo_ic@plt +.*: 24020251 li \$2,593 +# ^ low 16 bits of f_lo_ic_dc@mips16plt +.*: 24020110 li \$2,272 +# ^ low 16 bits of f_lo_du@plt +.*: 240200a0 li \$2,160 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 24020070 li \$2,112 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 24020040 li \$2,64 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 24020020 li \$2,32 +# ^ low 16 bits of f_lo_iu@plt +.*: 24020191 li \$2,401 +# ^ low 16 bits of f_lo_iu_dc@mips16plt +.*: 24020080 li \$2,128 +# ^ low 16 bits of f_lo_iu_ic@plt +.*: 24020231 li \$2,561 +# ^ low 16 bits of f_lo_iu_ic_dc@mips16plt +.*: 24020100 li \$2,256 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 24020030 li \$2,48 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 24020130 li \$2,304 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 24020140 li \$2,320 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.rd new file mode 100644 index 0000000..3ddec9b --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16-word.rd @@ -0,0 +1,198 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10202000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10005000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.dyn' .* +# All symbols are referenced by a .word in the .data section, so pointer +# equality matters. If a PLT is needed to satisfy a direct call or %lo +# relocation, the symbol should have a nonzero value and there should be +# no dynamic relocations against it. The only relocations here are for +# undefined 0-value symbols. Note that unlike x86, we do not create a PLT +# for the uncalled symbol 'f' in order to maintain backward compatibility +# with pre-PLT ld.sos. + Offset Info Type Sym\.Value Sym\. Name +00000000 00000000 R_MIPS_NONE +10201028 00001f03 R_MIPS_REL32 00000000 f_iu_ic +10201008 00002003 R_MIPS_REL32 00000000 f_ic +10201020 00002103 R_MIPS_REL32 00000000 f_iu +10201000 00002203 R_MIPS_REL32 00000000 f + +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100040 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 10100050 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100191 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100070 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 101001a1 f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 10100080 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 10100090 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 101000a0 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 101000b0 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 101000c0 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 101000d0 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 101000e0 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 101001e1 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 101000f0 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 10100100 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 101001f1 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 10100201 f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 10100211 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 10100120 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 10100231 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 10100130 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 10100140 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 10100251 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 10100150 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# All symbols have their address taken, so PLT symbols need to have a nonzero +# value. They must also have STO_MIPS_PLT in order to distinguish them from +# old-style lazy-binding stubs). +# +# A MIPS16 PLT should only be used as the symbol value if the function has +# a direct MIPS16 caller (dc) and no direct MIPS caller (du). + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100040 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 10100050 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_dc + .*: 10100191 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic + .*: 10100070 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 101001a1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_dc + .*: 10100080 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 10100090 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 101000a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 101000b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du + .*: 101000c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic_dc + .*: 101000d0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic + .*: 101000e0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_dc + .*: 101001e1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 101000f0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du + .*: 10100100 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 101001f1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_dc + .*: 10100201 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_ic_dc + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 10100211 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_ic_dc + .*: 10100120 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic_dc +#... + .*: 10100231 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 10100130 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 10100140 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 10100251 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100150 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. Since the functions +# have their addresses taken, they cannot use a lazy-binding stub. +# The symbol values are therefore all zero. + 31: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu + 34: 00000000 0 FUNC GLOBAL DEFAULT UND f + +Symbol table '\.symtab' .* +#... +Hex dump of section '\.data': + 0x10201000 (00000000|00000000) (101001f1|f1011010) (00000000|00000000) (10100201|01021010) .* + 0x10201010 (101000b0|b0001010) (10100050|50001010) (101000d0|d0001010) (101000c0|c0001010) .* + 0x10201020 (00000000|00000000) (101001a1|a1011010) (00000000|00000000) (10100211|11021010) .* + 0x10201030 (101000f0|f0001010) (101000e0|e0001010) (10100060|60001010) (10100120|20011010) .* + 0x10201040 (10100150|50011010) (101001e1|e1011010) (10100090|90001010) (10100251|51021010) .* + 0x10201050 (10100110|10011010) (101000a0|a0001010) (10100070|70001010) (10100040|40001010) .* + 0x10201060 (10100020|20001010) (10100191|91011010) (10100080|80001010) (10100231|31021010) .* + 0x10201070 (10100100|00011010) (10100030|30001010) (10100130|30011010) (10100140|40011010) .* + + +Primary GOT: + Canonical gp value: 10209ff0 + + Reserved entries: + Address Access Initial Purpose + 10202000 -32752\(gp\) 00000000 Lazy resolver + 10202004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10202008 -32744\(gp\) 10100201 + 1020200c -32740\(gp\) 101000d0 + 10202010 -32736\(gp\) 101000c0 + 10202014 -32732\(gp\) 10100211 + 10202018 -32728\(gp\) 10100060 + 1020201c -32724\(gp\) 10100120 + 10202020 -32720\(gp\) 10100090 + 10202024 -32716\(gp\) 10100251 + 10202028 -32712\(gp\) 10100070 + 1020202c -32708\(gp\) 10100040 + 10202030 -32704\(gp\) 10100080 + 10202034 -32700\(gp\) 10100231 + 10202038 -32696\(gp\) 10100130 + 1020203c -32692\(gp\) 10100140 + 10202040 -32688\(gp\) 101001a1 + 10202044 -32684\(gp\) 101000f0 + 10202048 -32680\(gp\) 101000e0 + 1020204c -32676\(gp\) 10100020 + 10202050 -32672\(gp\) 10100191 + 10202054 -32668\(gp\) 10100100 + 10202058 -32664\(gp\) 10100030 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 1020205c -32660\(gp\) 00000000 00000000 FUNC UND f_iu_ic + 10202060 -32656\(gp\) 00000000 00000000 FUNC UND f_ic + 10202064 -32652\(gp\) 00000000 00000000 FUNC UND f_iu + 10202068 -32648\(gp\) 00000000 00000000 FUNC UND f + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100020 FUNC UND f_lo_iu + 1020000c 10100000 10100030 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100040 FUNC UND f_lo_du_ic_dc + 10200014 10100000 10100050 FUNC UND f_du_dc + 10200018 10100000 10100191 FUNC UND f_lo_iu_dc + 1020001c 10100000 10100060 FUNC UND f_iu_du_ic + 10200020 10100000 10100070 FUNC UND f_lo_du_ic + 10200024 10100000 101001a1 FUNC UND f_iu_dc + 10200028 10100000 10100080 FUNC UND f_lo_iu_ic + 1020002c 10100000 10100090 FUNC UND f_lo_ic + 10200030 10100000 101000a0 FUNC UND f_lo_du_dc + 10200034 10100000 101000b0 FUNC UND f_du + 10200038 10100000 101000c0 FUNC UND f_du_ic_dc + 1020003c 10100000 101000d0 FUNC UND f_du_ic + 10200040 10100000 101000e0 FUNC UND f_iu_du_dc + 10200044 10100000 101001e1 FUNC UND f_lo_dc + 10200048 10100000 101000f0 FUNC UND f_iu_du + 1020004c 10100000 10100100 FUNC UND f_lo_iu_du + 10200050 10100000 101001f1 FUNC UND f_dc + 10200054 10100000 10100201 FUNC UND f_ic_dc + 10200058 10100000 10100110 FUNC UND f_lo_du + 1020005c 10100000 10100211 FUNC UND f_iu_ic_dc + 10200060 10100000 10100120 FUNC UND f_iu_du_ic_dc + 10200064 10100000 10100231 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 10100130 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 10100140 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 10100251 FUNC UND f_lo_ic_dc + 10200074 10100000 10100150 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.od new file mode 100644 index 0000000..712e651 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.od @@ -0,0 +1,509 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# Only _dc (direct call from compressed code) functions should have a +# MIPS16 PLT. Note that indirect calls do not influence the choice, +# so f_ic and f_lo_ic have MIPS rather than MIPS16 PLTs. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90008 lw \$25,8\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80008 addiu \$24,\$15,8 + +10100030 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100040 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100050 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100060 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100070 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100080 <f_lo_iu_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90028 lw \$25,40\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80028 addiu \$24,\$15,40 + +10100090 <f_lo_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9002c lw \$25,44\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8002c addiu \$24,\$15,44 + +101000a0 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +101000b0 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +101000c0 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000d0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +101000e0 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +101000f0 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +10100100 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +10100110 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +10100120 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100130 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +10100140 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +10100150 <f_lo@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90074 lw \$25,116\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80074 addiu \$24,\$15,116 + +10100160 <f_lo_iu_du_dc@mips16plt>: +.*: b203 lw \$2,1010016c <f_lo_iu_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020000c + +10100170 <f_lo_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010017c <f_lo_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200010 + +10100180 <f_du_dc@mips16plt>: +.*: b203 lw \$2,1010018c <f_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200014 + +10100190 <f_lo_iu_dc@mips16plt>: +.*: b203 lw \$2,1010019c <f_lo_iu_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200018 + +101001a0 <f_iu_dc@mips16plt>: +.*: b203 lw \$2,101001ac <f_iu_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200024 + +101001b0 <f_lo_du_dc@mips16plt>: +.*: b203 lw \$2,101001bc <f_lo_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200030 + +101001c0 <f_du_ic_dc@mips16plt>: +.*: b203 lw \$2,101001cc <f_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200038 + +101001d0 <f_iu_du_dc@mips16plt>: +.*: b203 lw \$2,101001dc <f_iu_du_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200040 + +101001e0 <f_lo_dc@mips16plt>: +.*: b203 lw \$2,101001ec <f_lo_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200044 + +101001f0 <f_dc@mips16plt>: +.*: b203 lw \$2,101001fc <f_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200050 + +10100200 <f_ic_dc@mips16plt>: +.*: b203 lw \$2,1010020c <f_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200054 + +10100210 <f_iu_ic_dc@mips16plt>: +.*: b203 lw \$2,1010021c <f_iu_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020005c + +10100220 <f_iu_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010022c <f_iu_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200060 + +10100230 <f_lo_iu_ic_dc@mips16plt>: +.*: b203 lw \$2,1010023c <f_lo_iu_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200064 + +10100240 <f_lo_iu_du_ic_dc@mips16plt>: +.*: b203 lw \$2,1010024c <f_lo_iu_du_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x1020006c + +10100250 <f_lo_ic_dc@mips16plt>: +.*: b203 lw \$2,1010025c <f_lo_ic_dc@mips16plt\+0xc> +.*: 9a60 lw \$3,0\(\$2\) +.*: 651a move \$24,\$2 +.*: eb00 jr \$3 +.*: 653b move \$25,\$3 +.*: 6500 nop +.*: .... .... \.word 0x10200070 + +Disassembly of section \.MIPS\.stubs: + +10101000 <_MIPS_STUBS_>: +# Lazy-binding stub for f_iu. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 24180021 li \$24,33 +# Lazy-binding stub for f_ic. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 24180020 li \$24,32 +# Lazy-binding stub for f_iu_ic. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 2418001f li \$24,31 + \.\.\. + +Disassembly of section \.text\.a: + +10102000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@mips16plt> +.*: 6500 nop +.*: f070 9b50 lw \$2,-32656\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@mips16plt> +.*: 6500 nop +.*: f010 9b58 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_du_dc@mips16plt> +.*: 6500 nop +.*: f010 9b5c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b40 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_iu_dc@mips16plt> +.*: 6500 nop +.*: f070 9b4c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jal [0-9a-f]+ <f_iu_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b44 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_dc@mips16plt> +.*: 6500 nop +.*: f030 9b48 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b4c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@mips16plt> +.*: 6500 nop +.*: f030 9b50 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b54 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_dc@mips16plt> +.*: 6500 nop +.*: f030 9b58 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f030 9b5c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_dc@mips16plt> +.*: 6500 nop +.*: f050 9b40 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_ic_dc@mips16plt> +.*: 6500 nop +.*: f050 9b44 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_dc@mips16plt> +.*: 6500 nop +.*: f050 9b48 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_ic_dc@mips16plt> +.*: 6500 nop +.*: f050 9b4c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: e820 jr \$31 + +Disassembly of section \.text\.b: + +10103000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628074 lw \$2,-32652\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@mips16plt +.*: 8c62806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@mips16plt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@plt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@mips16plt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@plt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@mips16plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10104000 <testlo>: +.*: 24020150 li \$2,336 +# ^ low 16 bits of f_lo@plt +.*: 240201e1 li \$2,481 +# ^ low 16 bits of f_lo_dc@mips16plt +.*: 24020090 li \$2,144 +# ^ low 16 bits of f_lo_ic@plt +.*: 24020251 li \$2,593 +# ^ low 16 bits of f_lo_ic_dc@mips16plt +.*: 24020110 li \$2,272 +# ^ low 16 bits of f_lo_du@plt +.*: 240200a0 li \$2,160 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 24020070 li \$2,112 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 24020040 li \$2,64 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 24020020 li \$2,32 +# ^ low 16 bits of f_lo_iu@plt +.*: 24020191 li \$2,401 +# ^ low 16 bits of f_lo_iu_dc@mips16plt +.*: 24020080 li \$2,128 +# ^ low 16 bits of f_lo_iu_ic@plt +.*: 24020231 li \$2,561 +# ^ low 16 bits of f_lo_iu_ic_dc@mips16plt +.*: 24020100 li \$2,256 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 24020030 li \$2,48 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 24020130 li \$2,304 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 24020140 li \$2,320 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.rd new file mode 100644 index 0000000..dc8a7c7 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-mips16.rd @@ -0,0 +1,170 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100040 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100191 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100070 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 10100080 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 10100090 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 101000a0 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 101001e1 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 10100100 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 10100231 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 10100130 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 10100140 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 10100251 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 10100150 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# _lo symbols have their address taken, so their PLT symbols need to have +# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish +# them from old-style lazy-binding stubs. Non-_lo symbols are only called, +# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation. +# +# A MIPS16 PLT should only be used as the symbol value if the function has +# a direct MIPS16 caller (dc) and no direct MIPS caller (du). + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100040 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_dc + .*: 10100191 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic + .*: 10100070 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_dc + .*: 10100080 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 10100090 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 101000a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_dc + .*: 101001e1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du + .*: 10100100 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic_dc + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic_dc +#... + .*: 10100231 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 10100130 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 10100140 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 10100251 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100150 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. The symbol value +# is the address of the lazy-binding stub. + 31: 10101020 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 10101010 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 10101000 0 FUNC GLOBAL DEFAULT UND f_iu + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 10100201 + 1020100c -32740\(gp\) 101000d0 + 10201010 -32736\(gp\) 101000c0 + 10201014 -32732\(gp\) 10100211 + 10201018 -32728\(gp\) 10100060 + 1020101c -32724\(gp\) 10100120 + 10201020 -32720\(gp\) 10100090 + 10201024 -32716\(gp\) 10100251 + 10201028 -32712\(gp\) 10100070 + 1020102c -32708\(gp\) 10100040 + 10201030 -32704\(gp\) 10100080 + 10201034 -32700\(gp\) 10100231 + 10201038 -32696\(gp\) 10100130 + 1020103c -32692\(gp\) 10100140 + 10201040 -32688\(gp\) 101001a1 + 10201044 -32684\(gp\) 101000f0 + 10201048 -32680\(gp\) 101000e0 + 1020104c -32676\(gp\) 10100020 + 10201050 -32672\(gp\) 10100191 + 10201054 -32668\(gp\) 10100100 + 10201058 -32664\(gp\) 10100030 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 1020105c -32660\(gp\) 10101020 10101020 FUNC UND f_iu_ic + 10201060 -32656\(gp\) 10101010 10101010 FUNC UND f_ic + 10201064 -32652\(gp\) 10101000 10101000 FUNC UND f_iu + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100020 FUNC UND f_lo_iu + 1020000c 10100000 10100030 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100040 FUNC UND f_lo_du_ic_dc + 10200014 10100000 00000000 FUNC UND f_du_dc + 10200018 10100000 10100191 FUNC UND f_lo_iu_dc + 1020001c 10100000 00000000 FUNC UND f_iu_du_ic + 10200020 10100000 10100070 FUNC UND f_lo_du_ic + 10200024 10100000 00000000 FUNC UND f_iu_dc + 10200028 10100000 10100080 FUNC UND f_lo_iu_ic + 1020002c 10100000 10100090 FUNC UND f_lo_ic + 10200030 10100000 101000a0 FUNC UND f_lo_du_dc + 10200034 10100000 00000000 FUNC UND f_du + 10200038 10100000 00000000 FUNC UND f_du_ic_dc + 1020003c 10100000 00000000 FUNC UND f_du_ic + 10200040 10100000 00000000 FUNC UND f_iu_du_dc + 10200044 10100000 101001e1 FUNC UND f_lo_dc + 10200048 10100000 00000000 FUNC UND f_iu_du + 1020004c 10100000 10100100 FUNC UND f_lo_iu_du + 10200050 10100000 00000000 FUNC UND f_dc + 10200054 10100000 00000000 FUNC UND f_ic_dc + 10200058 10100000 10100110 FUNC UND f_lo_du + 1020005c 10100000 00000000 FUNC UND f_iu_ic_dc + 10200060 10100000 00000000 FUNC UND f_iu_du_ic_dc + 10200064 10100000 10100231 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 10100130 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 10100140 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 10100251 FUNC UND f_lo_ic_dc + 10200074 10100000 10100150 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.od new file mode 100644 index 0000000..6e0d15a --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.od @@ -0,0 +1,103 @@ + +.* file format .* + + +Disassembly of section \.plt: + +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90008 lw \$25,8\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80008 addiu \$24,\$15,8 + +10100030 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100040 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100050 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100060 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90018 lw \$25,24\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80018 addiu \$24,\$15,24 + +10100070 <f_lo@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +Disassembly of section \.MIPS\.stubs: + +10101000 <_MIPS_STUBS_>: +# Lazy-binding stub for f_iu. +.*: 8f998010 lw \$25,-32752\(\$28\) +.*: 03e07821 move \$15,\$31 +.*: 0320f809 jalr \$25 +.*: 24180009 li \$24,9 + \.\.\. + +Disassembly of section \.text\.b: + +10102000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ global GOT entry for f_iu +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628018 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: 8c62801c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_lo_iu@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628020 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10103000 <testlo>: +.*: 24020070 li \$2,112 +# ^ low 16 bits of f_lo@plt +.*: 24020060 li \$2,96 +# ^ low 16 bits of f_lo_du@plt +.*: 24020020 li \$2,32 +# ^ low 16 bits of f_lo_iu@plt +.*: 24020050 li \$2,80 +# ^ low 16 bits of f_lo_iu_du@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.rd new file mode 100644 index 0000000..fa23221 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-se.rd @@ -0,0 +1,79 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x9 + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 48 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du +10200010 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du +10200014 [^ ]+ R_MIPS_JUMP_SLOT 10100050 f_lo_iu_du +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_lo_du +1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100070 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# _lo symbols have their address taken, so their PLT symbols need to have +# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish +# them from old-style lazy-binding stubs. Non-_lo symbols are only called, +# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation. + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu +#... + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du + .*: 10100050 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du +#... + .*: 10100070 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. The symbol value +# is the address of the lazy-binding stub. + 9: 10101000 0 FUNC GLOBAL DEFAULT UND f_iu + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 10100040 + 1020100c -32740\(gp\) 10100020 + 10201010 -32736\(gp\) 10100050 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 10201014 -32732\(gp\) 10101000 10101000 FUNC UND f_iu + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100020 FUNC UND f_lo_iu + 1020000c 10100000 00000000 FUNC UND f_du + 10200010 10100000 00000000 FUNC UND f_iu_du + 10200014 10100000 10100050 FUNC UND f_lo_iu_du + 10200018 10100000 10100060 FUNC UND f_lo_du + 1020001c 10100000 10100070 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.od new file mode 100644 index 0000000..2d7b513 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.od @@ -0,0 +1,560 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# Only _du (direct call from uncompressed code) functions should have +# non-microMIPS PLTs. All the rest must be microMIPS. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100030 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100040 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100050 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100060 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100070 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +10100080 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +10100090 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000a0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +101000b0 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +101000c0 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +101000d0 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +101000e0 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +101000f0 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100100 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +10100110 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +10100120 <f_lo_iu@micromipsplt>: +.*: 7903 ffba addiu \$2,\$pc,1048296 +# ^ 0x10200008 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010012c <f_lo_iu_du_dc@micromipsplt>: +.*: 7903 ffb8 addiu \$2,\$pc,1048288 +# ^ 0x1020000c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100138 <f_lo_du_ic_dc@micromipsplt>: +.*: 7903 ffb6 addiu \$2,\$pc,1048280 +# ^ 0x10200010 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100144 <f_du_dc@micromipsplt>: +.*: 7903 ffb4 addiu \$2,\$pc,1048272 +# ^ 0x10200014 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100150 <f_lo_iu_dc@micromipsplt>: +.*: 7903 ffb2 addiu \$2,\$pc,1048264 +# ^ 0x10200018 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010015c <f_iu_dc@micromipsplt>: +.*: 7903 ffb2 addiu \$2,\$pc,1048264 +# ^ 0x10200024 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100168 <f_lo_iu_ic@micromipsplt>: +.*: 7903 ffb0 addiu \$2,\$pc,1048256 +# ^ 0x10200028 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100174 <f_lo_ic@micromipsplt>: +.*: 7903 ffae addiu \$2,\$pc,1048248 +# ^ 0x1020002c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100180 <f_lo_du_dc@micromipsplt>: +.*: 7903 ffac addiu \$2,\$pc,1048240 +# ^ 0x10200030 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010018c <f_du_ic_dc@micromipsplt>: +.*: 7903 ffab addiu \$2,\$pc,1048236 +# ^ 0x10200038 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100198 <f_iu_du_dc@micromipsplt>: +.*: 7903 ffaa addiu \$2,\$pc,1048232 +# ^ 0x10200040 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001a4 <f_lo_dc@micromipsplt>: +.*: 7903 ffa8 addiu \$2,\$pc,1048224 +# ^ 0x10200044 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001b0 <f_dc@micromipsplt>: +.*: 7903 ffa8 addiu \$2,\$pc,1048224 +# ^ 0x10200050 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001bc <f_ic_dc@micromipsplt>: +.*: 7903 ffa6 addiu \$2,\$pc,1048216 +# ^ 0x10200054 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001c8 <f_iu_ic_dc@micromipsplt>: +.*: 7903 ffa5 addiu \$2,\$pc,1048212 +# ^ 0x1020005c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001d4 <f_iu_du_ic_dc@micromipsplt>: +.*: 7903 ffa3 addiu \$2,\$pc,1048204 +# ^ 0x10200060 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001e0 <f_lo_iu_ic_dc@micromipsplt>: +.*: 7903 ffa1 addiu \$2,\$pc,1048196 +# ^ 0x10200064 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001ec <f_lo_iu_du_ic_dc@micromipsplt>: +.*: 7903 ffa0 addiu \$2,\$pc,1048192 +# ^ 0x1020006c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001f8 <f_lo_ic_dc@micromipsplt>: +.*: 7903 ff9e addiu \$2,\$pc,1048184 +# ^ 0x10200070 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100204 <f_lo@micromipsplt>: +.*: 7903 ff9c addiu \$2,\$pc,1048176 +# ^ 0x10200074 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +Disassembly of section \.text\.a: + +10101000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 808c lw \$2,-32628\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8018 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 801c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8020 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_iu_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8088 lw \$2,-32632\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jal [0-9a-f]+ <f_iu_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_iu_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8030 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8034 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8038 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 803c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 459f jr \$31 + +Disassembly of section \.text\.b: + +10102000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628090 lw \$2,-32624\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@micromipsplt +.*: 8c628088 lw \$2,-32632\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@micromipsplt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@micromipsplt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@micromipsplt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@micromipsplt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@micromipsplt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10103000 <testlo>: +.*: 3040 0205 li \$2,517 +# ^ low 16 bits of f_lo@micromipsplt +.*: 3040 01a5 li \$2,421 +# ^ low 16 bits of f_lo_dc@micromipsplt +.*: 3040 0175 li \$2,373 +# ^ low 16 bits of f_lo_ic@micromipsplt +.*: 3040 01f9 li \$2,505 +# ^ low 16 bits of f_lo_ic_dc@micromipsplt +.*: 3040 00e0 li \$2,224 +# ^ low 16 bits of f_lo_du@plt +.*: 3040 0070 li \$2,112 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 3040 0060 li \$2,96 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 3040 0030 li \$2,48 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 3040 0121 li \$2,289 +# ^ low 16 bits of f_lo_iu@micromipsplt +.*: 3040 0151 li \$2,337 +# ^ low 16 bits of f_lo_iu_dc@micromipsplt +.*: 3040 0169 li \$2,361 +# ^ low 16 bits of f_lo_iu_ic@micromipsplt +.*: 3040 01e1 li \$2,481 +# ^ low 16 bits of f_lo_iu_ic_dc@micromipsplt +.*: 3040 00d0 li \$2,208 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 3040 0020 li \$2,32 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 3040 0100 li \$2,256 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 3040 0110 li \$2,272 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + +Disassembly of section \.text\.d: + +10104000 <testgot>: +.*: fc5c 8094 lw \$2,-32620\(\$28\) +# ^ global GOT entry for f +.*: fc5c 806c lw \$2,-32660\(\$28\) +# ^ local GOT entry for f_dc@micromipsplt +.*: fc5c 808c lw \$2,-32628\(\$28\) +# ^ global GOT entry for f_ic +.*: fc5c 8018 lw \$2,-32744\(\$28\) +# ^ local GOT entry for f_ic_dc@micromipsplt +.*: fc5c 8070 lw \$2,-32656\(\$28\) +# ^ local GOT entry for f_du@plt +.*: fc5c 8074 lw \$2,-32652\(\$28\) +# ^ local GOT entry for f_du_dc@plt +.*: fc5c 801c lw \$2,-32740\(\$28\) +# ^ local GOT entry for f_du_ic@plt +.*: fc5c 8020 lw \$2,-32736\(\$28\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: fc5c 8090 lw \$2,-32624\(\$28\) +# ^ global GOT entry for f_iu +.*: fc5c 8050 lw \$2,-32688\(\$28\) +# ^ local GOT entry for f_iu_dc@micromipsplt +.*: fc5c 8088 lw \$2,-32632\(\$28\) +# ^ global GOT entry for f_iu_ic +.*: fc5c 8024 lw \$2,-32732\(\$28\) +# ^ local GOT entry for f_iu_ic_dc@micromipsplt +.*: fc5c 8054 lw \$2,-32684\(\$28\) +# ^ local GOT entry for f_iu_du@plt +.*: fc5c 8058 lw \$2,-32680\(\$28\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: fc5c 8028 lw \$2,-32728\(\$28\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: fc5c 802c lw \$2,-32724\(\$28\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: fc5c 8078 lw \$2,-32648\(\$28\) +# ^ local GOT entry for f_lo@micromipsplt +.*: fc5c 807c lw \$2,-32644\(\$28\) +# ^ local GOT entry for f_lo_dc@micromipsplt +.*: fc5c 8030 lw \$2,-32720\(\$28\) +# ^ local GOT entry for f_lo_ic@micromipsplt +.*: fc5c 8034 lw \$2,-32716\(\$28\) +# ^ local GOT entry for f_lo_ic_dc@micromipsplt +.*: fc5c 8080 lw \$2,-32640\(\$28\) +# ^ local GOT entry for f_lo_du@plt +.*: fc5c 8084 lw \$2,-32636\(\$28\) +# ^ local GOT entry for f_lo_du_dc@plt +.*: fc5c 8038 lw \$2,-32712\(\$28\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: fc5c 803c lw \$2,-32708\(\$28\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: fc5c 805c lw \$2,-32676\(\$28\) +# ^ local GOT entry for f_lo_iu@micromipsplt +.*: fc5c 8060 lw \$2,-32672\(\$28\) +# ^ local GOT entry for f_lo_iu_dc@micromipsplt +.*: fc5c 8040 lw \$2,-32704\(\$28\) +# ^ local GOT entry for f_lo_iu_ic@micromipsplt +.*: fc5c 8044 lw \$2,-32700\(\$28\) +# ^ local GOT entry for f_lo_iu_ic_dc@micromipsplt +.*: fc5c 8064 lw \$2,-32668\(\$28\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: fc5c 8068 lw \$2,-32664\(\$28\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: fc5c 8048 lw \$2,-32696\(\$28\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: fc5c 804c lw \$2,-32692\(\$28\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.rd new file mode 100644 index 0000000..2a4c337 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-got.rd @@ -0,0 +1,179 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100121 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 10100040 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100151 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100050 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 1010015d f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 10100169 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 10100175 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 10100070 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 10100080 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 10100090 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 101000a0 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 101000b0 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 101001a5 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 101000c0 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 101000d0 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 101001b1 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 101001bd f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 101000e0 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 101001c9 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 101000f0 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 101001e1 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 10100100 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 101001f9 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 10100205 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# All symbols have their address taken, so PLT symbols need to have a nonzero +# value. They must also have STO_MIPS_PLT in order to distinguish them from +# old-style lazy-binding stubs). +# +# A MIPS (as opposed to microMIPS) PLT should be used as the symbol value +# if and only if the function has a direct MIPS caller (du). + .*: 10100121 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 10100040 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_dc + .*: 10100151 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 10100050 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 1010015d 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_dc + .*: 10100169 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 10100175 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 10100070 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 10100080 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du + .*: 10100090 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic_dc + .*: 101000a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic + .*: 101000b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_dc + .*: 101001a5 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 101000c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du + .*: 101000d0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 101001b1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_dc + .*: 101001bd 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_ic_dc + .*: 101000e0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 101001c9 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_ic_dc + .*: 101000f0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic_dc +#... + .*: 101001e1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 10100100 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 101001f9 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100205 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. Since the functions +# have their addresses taken, they cannot use a lazy-binding stub. +# The symbol values are therefore all zero. + 31: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu + 34: 00000000 0 FUNC GLOBAL DEFAULT UND f + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 101001bd + 1020100c -32740\(gp\) 101000a0 + 10201010 -32736\(gp\) 10100090 + 10201014 -32732\(gp\) 101001c9 + 10201018 -32728\(gp\) 10100050 + 1020101c -32724\(gp\) 101000f0 + 10201020 -32720\(gp\) 10100175 + 10201024 -32716\(gp\) 101001f9 + 10201028 -32712\(gp\) 10100060 + 1020102c -32708\(gp\) 10100030 + 10201030 -32704\(gp\) 10100169 + 10201034 -32700\(gp\) 101001e1 + 10201038 -32696\(gp\) 10100100 + 1020103c -32692\(gp\) 10100110 + 10201040 -32688\(gp\) 1010015d + 10201044 -32684\(gp\) 101000c0 + 10201048 -32680\(gp\) 101000b0 + 1020104c -32676\(gp\) 10100121 + 10201050 -32672\(gp\) 10100151 + 10201054 -32668\(gp\) 101000d0 + 10201058 -32664\(gp\) 10100020 + 1020105c -32660\(gp\) 101001b1 + 10201060 -32656\(gp\) 10100080 + 10201064 -32652\(gp\) 10100040 + 10201068 -32648\(gp\) 10100205 + 1020106c -32644\(gp\) 101001a5 + 10201070 -32640\(gp\) 101000e0 + 10201074 -32636\(gp\) 10100070 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 10201078 -32632\(gp\) 00000000 00000000 FUNC UND f_iu_ic + 1020107c -32628\(gp\) 00000000 00000000 FUNC UND f_ic + 10201080 -32624\(gp\) 00000000 00000000 FUNC UND f_iu + 10201084 -32620\(gp\) 00000000 00000000 FUNC UND f + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100121 FUNC UND f_lo_iu + 1020000c 10100000 10100020 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100030 FUNC UND f_lo_du_ic_dc + 10200014 10100000 10100040 FUNC UND f_du_dc + 10200018 10100000 10100151 FUNC UND f_lo_iu_dc + 1020001c 10100000 10100050 FUNC UND f_iu_du_ic + 10200020 10100000 10100060 FUNC UND f_lo_du_ic + 10200024 10100000 1010015d FUNC UND f_iu_dc + 10200028 10100000 10100169 FUNC UND f_lo_iu_ic + 1020002c 10100000 10100175 FUNC UND f_lo_ic + 10200030 10100000 10100070 FUNC UND f_lo_du_dc + 10200034 10100000 10100080 FUNC UND f_du + 10200038 10100000 10100090 FUNC UND f_du_ic_dc + 1020003c 10100000 101000a0 FUNC UND f_du_ic + 10200040 10100000 101000b0 FUNC UND f_iu_du_dc + 10200044 10100000 101001a5 FUNC UND f_lo_dc + 10200048 10100000 101000c0 FUNC UND f_iu_du + 1020004c 10100000 101000d0 FUNC UND f_lo_iu_du + 10200050 10100000 101001b1 FUNC UND f_dc + 10200054 10100000 101001bd FUNC UND f_ic_dc + 10200058 10100000 101000e0 FUNC UND f_lo_du + 1020005c 10100000 101001c9 FUNC UND f_iu_ic_dc + 10200060 10100000 101000f0 FUNC UND f_iu_du_ic_dc + 10200064 10100000 101001e1 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 10100100 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 10100110 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 101001f9 FUNC UND f_lo_ic_dc + 10200074 10100000 10100205 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-only.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-only.od new file mode 100644 index 0000000..b7d7241 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-only.od @@ -0,0 +1,111 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# All entries must be microMIPS. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 7984 0000 addiu \$3,\$pc,1048576 +.*: ff23 0000 lw \$25,0\(\$3\) +.*: 0535 subu \$2,\$2,\$3 +.*: 2525 srl \$2,\$2,2 +.*: 3302 fffe addiu \$24,\$2,-2 +.*: 0dff move \$15,\$31 +.*: 45f9 jalrs \$25 +.*: 0f83 move \$28,\$3 +.*: 0c00 nop + +10100018 <f_lo_ic@micromipsplt>: +.*: 7903 fffc addiu \$2,\$pc,1048560 +# ^ 0x10200008 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100024 <f_lo_dc@micromipsplt>: +.*: 7903 fffa addiu \$2,\$pc,1048552 +# ^ 0x1020000c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100030 <f_dc@micromipsplt>: +.*: 7903 fff8 addiu \$2,\$pc,1048544 +# ^ 0x10200010 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010003c <f_ic_dc@micromipsplt>: +.*: 7903 fff6 addiu \$2,\$pc,1048536 +# ^ 0x10200014 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100048 <f_lo_ic_dc@micromipsplt>: +.*: 7903 fff4 addiu \$2,\$pc,1048528 +# ^ 0x10200018 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100054 <f_lo@micromipsplt>: +.*: 7903 fff2 addiu \$2,\$pc,1048520 +# ^ 0x1020001c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +Disassembly of section \.MIPS\.stubs: + +10101000 <_MIPS_STUBS_>: +# Lazy-binding stub for f_ic. +.*: ff3c 8010 lw \$25,-32752\(\$28\) +.*: 0dff move \$15,\$31 +.*: 45d9 jalr \$25 +.*: 3300 0009 li \$24,9 + \.\.\. + +Disassembly of section \.text\.a: + +10102000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8024 lw \$2,-32732\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8018 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 801c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_lo_ic@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8020 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@micromipsplt +.*: 459f jr \$31 + +Disassembly of section \.text\.c: + +10103000 <testlo>: +.*: 3040 0055 li \$2,85 +# ^ low 16 bits of f_lo@micromipsplt +.*: 3040 0025 li \$2,37 +# ^ low 16 bits of f_lo_dc@micromipsplt +.*: 3040 0019 li \$2,25 +# ^ low 16 bits of f_lo_ic@micromipsplt +.*: 3040 0049 li \$2,73 +# ^ low 16 bits of f_lo_ic_dc@micromipsplt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-only.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-only.rd new file mode 100644 index 0000000..fd3e7c6 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-only.rd @@ -0,0 +1,81 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x9 + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 48 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100019 f_lo_ic +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100025 f_lo_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_ic_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100049 f_lo_ic_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100055 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# _lo symbols have their address taken, so their PLT symbols need to have +# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish +# them from old-style lazy-binding stubs. Non-_lo symbols are only called, +# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation. +# +# All PLTs should be microMIPS. +#... + .*: 10100019 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 10100025 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic_dc +#... + .*: 10100049 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100055 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. The symbol value +# is the address of the lazy-binding stub. + 9: 10101001 0 FUNC GLOBAL DEFAULT UND f_ic + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 1010003d + 1020100c -32740\(gp\) 10100019 + 10201010 -32736\(gp\) 10100049 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 10201014 -32732\(gp\) 10101001 10101001 FUNC UND f_ic + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100001 10100019 FUNC UND f_lo_ic + 1020000c 10100001 10100025 FUNC UND f_lo_dc + 10200010 10100001 00000000 FUNC UND f_dc + 10200014 10100001 00000000 FUNC UND f_ic_dc + 10200018 10100001 10100049 FUNC UND f_lo_ic_dc + 1020001c 10100001 10100055 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.od new file mode 100644 index 0000000..4d0572b --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.od @@ -0,0 +1,492 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# Only _du (direct call from uncompressed code) functions should have +# non-microMIPS PLTs. All the rest must be microMIPS. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100030 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100040 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100050 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100060 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100070 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +10100080 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +10100090 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000a0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +101000b0 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +101000c0 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +101000d0 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +101000e0 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +101000f0 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100100 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +10100110 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +10100120 <f_lo_iu@micromipsplt>: +.*: 7903 ffba addiu \$2,\$pc,1048296 +# ^ 0x10200008 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010012c <f_lo_iu_du_dc@micromipsplt>: +.*: 7903 ffb8 addiu \$2,\$pc,1048288 +# ^ 0x1020000c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100138 <f_lo_du_ic_dc@micromipsplt>: +.*: 7903 ffb6 addiu \$2,\$pc,1048280 +# ^ 0x10200010 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100144 <f_du_dc@micromipsplt>: +.*: 7903 ffb4 addiu \$2,\$pc,1048272 +# ^ 0x10200014 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100150 <f_lo_iu_dc@micromipsplt>: +.*: 7903 ffb2 addiu \$2,\$pc,1048264 +# ^ 0x10200018 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010015c <f_iu_dc@micromipsplt>: +.*: 7903 ffb2 addiu \$2,\$pc,1048264 +# ^ 0x10200024 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100168 <f_lo_iu_ic@micromipsplt>: +.*: 7903 ffb0 addiu \$2,\$pc,1048256 +# ^ 0x10200028 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100174 <f_lo_ic@micromipsplt>: +.*: 7903 ffae addiu \$2,\$pc,1048248 +# ^ 0x1020002c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100180 <f_lo_du_dc@micromipsplt>: +.*: 7903 ffac addiu \$2,\$pc,1048240 +# ^ 0x10200030 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010018c <f_du_ic_dc@micromipsplt>: +.*: 7903 ffab addiu \$2,\$pc,1048236 +# ^ 0x10200038 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100198 <f_iu_du_dc@micromipsplt>: +.*: 7903 ffaa addiu \$2,\$pc,1048232 +# ^ 0x10200040 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001a4 <f_lo_dc@micromipsplt>: +.*: 7903 ffa8 addiu \$2,\$pc,1048224 +# ^ 0x10200044 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001b0 <f_dc@micromipsplt>: +.*: 7903 ffa8 addiu \$2,\$pc,1048224 +# ^ 0x10200050 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001bc <f_ic_dc@micromipsplt>: +.*: 7903 ffa6 addiu \$2,\$pc,1048216 +# ^ 0x10200054 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001c8 <f_iu_ic_dc@micromipsplt>: +.*: 7903 ffa5 addiu \$2,\$pc,1048212 +# ^ 0x1020005c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001d4 <f_iu_du_ic_dc@micromipsplt>: +.*: 7903 ffa3 addiu \$2,\$pc,1048204 +# ^ 0x10200060 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001e0 <f_lo_iu_ic_dc@micromipsplt>: +.*: 7903 ffa1 addiu \$2,\$pc,1048196 +# ^ 0x10200064 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001ec <f_lo_iu_du_ic_dc@micromipsplt>: +.*: 7903 ffa0 addiu \$2,\$pc,1048192 +# ^ 0x1020006c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001f8 <f_lo_ic_dc@micromipsplt>: +.*: 7903 ff9e addiu \$2,\$pc,1048184 +# ^ 0x10200070 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100204 <f_lo@micromipsplt>: +.*: 7903 ff9c addiu \$2,\$pc,1048176 +# ^ 0x10200074 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +Disassembly of section \.text\.a: + +10101000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8070 lw \$2,-32656\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8018 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 801c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8020 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_iu_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jal [0-9a-f]+ <f_iu_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_iu_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8030 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8034 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8038 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 803c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 459f jr \$31 + +Disassembly of section \.text\.b: + +10102000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628074 lw \$2,-32652\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@micromipsplt +.*: 8c62806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@micromipsplt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@micromipsplt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@micromipsplt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@micromipsplt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@micromipsplt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10103000 <testlo>: +.*: 3040 0205 li \$2,517 +# ^ low 16 bits of f_lo@micromipsplt +.*: 3040 01a5 li \$2,421 +# ^ low 16 bits of f_lo_dc@micromipsplt +.*: 3040 0175 li \$2,373 +# ^ low 16 bits of f_lo_ic@micromipsplt +.*: 3040 01f9 li \$2,505 +# ^ low 16 bits of f_lo_ic_dc@micromipsplt +.*: 3040 00e0 li \$2,224 +# ^ low 16 bits of f_lo_du@plt +.*: 3040 0070 li \$2,112 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 3040 0060 li \$2,96 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 3040 0030 li \$2,48 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 3040 0121 li \$2,289 +# ^ low 16 bits of f_lo_iu@micromipsplt +.*: 3040 0151 li \$2,337 +# ^ low 16 bits of f_lo_iu_dc@micromipsplt +.*: 3040 0169 li \$2,361 +# ^ low 16 bits of f_lo_iu_ic@micromipsplt +.*: 3040 01e1 li \$2,481 +# ^ low 16 bits of f_lo_iu_ic_dc@micromipsplt +.*: 3040 00d0 li \$2,208 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 3040 0020 li \$2,32 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 3040 0100 li \$2,256 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 3040 0110 li \$2,272 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.rd new file mode 100644 index 0000000..2c872af --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-word.rd @@ -0,0 +1,198 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10202000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10005000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.dyn' .* +# All symbols are referenced by a .word in the .data section, so pointer +# equality matters. If a PLT is needed to satisfy a direct call or %lo +# relocation, the symbol should have a nonzero value and there should be +# no dynamic relocations against it. The only relocations here are for +# undefined 0-value symbols. Note that unlike x86, we do not create a PLT +# for the uncalled symbol 'f' in order to maintain backward compatibility +# with pre-PLT ld.sos. + Offset Info Type Sym\.Value Sym\. Name +00000000 00000000 R_MIPS_NONE +10201028 00001f03 R_MIPS_REL32 00000000 f_iu_ic +10201008 00002003 R_MIPS_REL32 00000000 f_ic +10201020 00002103 R_MIPS_REL32 00000000 f_iu +10201000 00002203 R_MIPS_REL32 00000000 f + +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100121 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 10100040 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100151 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100050 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 1010015d f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 10100169 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 10100175 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 10100070 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 10100080 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 10100090 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 101000a0 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 101000b0 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 101001a5 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 101000c0 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 101000d0 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 101001b1 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 101001bd f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 101000e0 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 101001c9 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 101000f0 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 101001e1 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 10100100 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 101001f9 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 10100205 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# All symbols have their address taken, so PLT symbols need to have a nonzero +# value. They must also have STO_MIPS_PLT in order to distinguish them from +# old-style lazy-binding stubs). +# +# A MIPS (as opposed to microMIPS) PLT should be used as the symbol value +# if and only if the function has a direct MIPS caller (du). + .*: 10100121 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 10100040 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_dc + .*: 10100151 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 10100050 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 1010015d 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_dc + .*: 10100169 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 10100175 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 10100070 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 10100080 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du + .*: 10100090 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic_dc + .*: 101000a0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_du_ic + .*: 101000b0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_dc + .*: 101001a5 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 101000c0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du + .*: 101000d0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 101001b1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_dc + .*: 101001bd 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_ic_dc + .*: 101000e0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 101001c9 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_ic_dc + .*: 101000f0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_iu_du_ic_dc +#... + .*: 101001e1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 10100100 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 101001f9 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100205 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. Since the functions +# have their addresses taken, they cannot use a lazy-binding stub. +# The symbol values are therefore all zero. + 31: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu + 34: 00000000 0 FUNC GLOBAL DEFAULT UND f + +Symbol table '\.symtab' .* +#... +Hex dump of section '\.data': + 0x10201000 (00000000|00000000) (101001b1|b1011010) (00000000|00000000) (101001bd|bd011010) .* + 0x10201010 (10100080|80001010) (10100040|40001010) (101000a0|a0001010) (10100090|90001010) .* + 0x10201020 (00000000|00000000) (1010015d|5d011010) (00000000|00000000) (101001c9|c9011010) .* + 0x10201030 (101000c0|c0001010) (101000b0|b0001010) (10100050|50001010) (101000f0|f0001010) .* + 0x10201040 (10100205|05021010) (101001a5|a5011010) (10100175|75011010) (101001f9|f9011010) .* + 0x10201050 (101000e0|e0001010) (10100070|70001010) (10100060|60001010) (10100030|30001010) .* + 0x10201060 (10100121|21011010) (10100151|51011010) (10100169|69011010) (101001e1|e1011010) .* + 0x10201070 (101000d0|d0001010) (10100020|20001010) (10100100|00011010) (10100110|10011010) .* + + +Primary GOT: + Canonical gp value: 10209ff0 + + Reserved entries: + Address Access Initial Purpose + 10202000 -32752\(gp\) 00000000 Lazy resolver + 10202004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10202008 -32744\(gp\) 101001bd + 1020200c -32740\(gp\) 101000a0 + 10202010 -32736\(gp\) 10100090 + 10202014 -32732\(gp\) 101001c9 + 10202018 -32728\(gp\) 10100050 + 1020201c -32724\(gp\) 101000f0 + 10202020 -32720\(gp\) 10100175 + 10202024 -32716\(gp\) 101001f9 + 10202028 -32712\(gp\) 10100060 + 1020202c -32708\(gp\) 10100030 + 10202030 -32704\(gp\) 10100169 + 10202034 -32700\(gp\) 101001e1 + 10202038 -32696\(gp\) 10100100 + 1020203c -32692\(gp\) 10100110 + 10202040 -32688\(gp\) 1010015d + 10202044 -32684\(gp\) 101000c0 + 10202048 -32680\(gp\) 101000b0 + 1020204c -32676\(gp\) 10100121 + 10202050 -32672\(gp\) 10100151 + 10202054 -32668\(gp\) 101000d0 + 10202058 -32664\(gp\) 10100020 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 1020205c -32660\(gp\) 00000000 00000000 FUNC UND f_iu_ic + 10202060 -32656\(gp\) 00000000 00000000 FUNC UND f_ic + 10202064 -32652\(gp\) 00000000 00000000 FUNC UND f_iu + 10202068 -32648\(gp\) 00000000 00000000 FUNC UND f + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100121 FUNC UND f_lo_iu + 1020000c 10100000 10100020 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100030 FUNC UND f_lo_du_ic_dc + 10200014 10100000 10100040 FUNC UND f_du_dc + 10200018 10100000 10100151 FUNC UND f_lo_iu_dc + 1020001c 10100000 10100050 FUNC UND f_iu_du_ic + 10200020 10100000 10100060 FUNC UND f_lo_du_ic + 10200024 10100000 1010015d FUNC UND f_iu_dc + 10200028 10100000 10100169 FUNC UND f_lo_iu_ic + 1020002c 10100000 10100175 FUNC UND f_lo_ic + 10200030 10100000 10100070 FUNC UND f_lo_du_dc + 10200034 10100000 10100080 FUNC UND f_du + 10200038 10100000 10100090 FUNC UND f_du_ic_dc + 1020003c 10100000 101000a0 FUNC UND f_du_ic + 10200040 10100000 101000b0 FUNC UND f_iu_du_dc + 10200044 10100000 101001a5 FUNC UND f_lo_dc + 10200048 10100000 101000c0 FUNC UND f_iu_du + 1020004c 10100000 101000d0 FUNC UND f_lo_iu_du + 10200050 10100000 101001b1 FUNC UND f_dc + 10200054 10100000 101001bd FUNC UND f_ic_dc + 10200058 10100000 101000e0 FUNC UND f_lo_du + 1020005c 10100000 101001c9 FUNC UND f_iu_ic_dc + 10200060 10100000 101000f0 FUNC UND f_iu_du_ic_dc + 10200064 10100000 101001e1 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 10100100 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 10100110 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 101001f9 FUNC UND f_lo_ic_dc + 10200074 10100000 10100205 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.od b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.od new file mode 100644 index 0000000..416509f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.od @@ -0,0 +1,512 @@ + +.* file format .* + + +Disassembly of section \.plt: + +# Only _du (direct call from uncompressed code) functions should have +# non-microMIPS PLTs. All the rest must be microMIPS. +10100000 <_PROCEDURE_LINKAGE_TABLE_>: +.*: 3c1c1020 lui \$28,0x1020 +.*: 8f990000 lw \$25,0\(\$28\) +.*: 279c0000 addiu \$28,\$28,0 +.*: 031cc023 subu \$24,\$24,\$28 +.*: 03e07821 move \$15,\$31 +.*: 0018c082 srl \$24,\$24,0x2 +.*: 0320f809 jalr \$25 +.*: 2718fffe addiu \$24,\$24,-2 + +10100020 <f_lo_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9000c lw \$25,12\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8000c addiu \$24,\$15,12 + +10100030 <f_lo_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90010 lw \$25,16\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80010 addiu \$24,\$15,16 + +10100040 <f_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90014 lw \$25,20\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80014 addiu \$24,\$15,20 + +10100050 <f_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9001c lw \$25,28\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8001c addiu \$24,\$15,28 + +10100060 <f_lo_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90020 lw \$25,32\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80020 addiu \$24,\$15,32 + +10100070 <f_lo_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90030 lw \$25,48\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80030 addiu \$24,\$15,48 + +10100080 <f_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90034 lw \$25,52\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80034 addiu \$24,\$15,52 + +10100090 <f_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90038 lw \$25,56\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80038 addiu \$24,\$15,56 + +101000a0 <f_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9003c lw \$25,60\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8003c addiu \$24,\$15,60 + +101000b0 <f_iu_du_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90040 lw \$25,64\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80040 addiu \$24,\$15,64 + +101000c0 <f_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90048 lw \$25,72\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80048 addiu \$24,\$15,72 + +101000d0 <f_lo_iu_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9004c lw \$25,76\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8004c addiu \$24,\$15,76 + +101000e0 <f_lo_du@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90058 lw \$25,88\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80058 addiu \$24,\$15,88 + +101000f0 <f_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90060 lw \$25,96\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80060 addiu \$24,\$15,96 + +10100100 <f_lo_iu_du_ic@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df90068 lw \$25,104\(\$15\) +.*: 03200008 jr \$25 +.*: 25f80068 addiu \$24,\$15,104 + +10100110 <f_lo_iu_du_ic_dc@plt>: +.*: 3c0f1020 lui \$15,0x1020 +.*: 8df9006c lw \$25,108\(\$15\) +.*: 03200008 jr \$25 +.*: 25f8006c addiu \$24,\$15,108 + +10100120 <f_lo_iu@micromipsplt>: +.*: 7903 ffba addiu \$2,\$pc,1048296 +# ^ 0x10200008 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010012c <f_lo_iu_du_dc@micromipsplt>: +.*: 7903 ffb8 addiu \$2,\$pc,1048288 +# ^ 0x1020000c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100138 <f_lo_du_ic_dc@micromipsplt>: +.*: 7903 ffb6 addiu \$2,\$pc,1048280 +# ^ 0x10200010 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100144 <f_du_dc@micromipsplt>: +.*: 7903 ffb4 addiu \$2,\$pc,1048272 +# ^ 0x10200014 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100150 <f_lo_iu_dc@micromipsplt>: +.*: 7903 ffb2 addiu \$2,\$pc,1048264 +# ^ 0x10200018 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010015c <f_iu_dc@micromipsplt>: +.*: 7903 ffb2 addiu \$2,\$pc,1048264 +# ^ 0x10200024 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100168 <f_lo_iu_ic@micromipsplt>: +.*: 7903 ffb0 addiu \$2,\$pc,1048256 +# ^ 0x10200028 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100174 <f_lo_ic@micromipsplt>: +.*: 7903 ffae addiu \$2,\$pc,1048248 +# ^ 0x1020002c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100180 <f_lo_du_dc@micromipsplt>: +.*: 7903 ffac addiu \$2,\$pc,1048240 +# ^ 0x10200030 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +1010018c <f_du_ic_dc@micromipsplt>: +.*: 7903 ffab addiu \$2,\$pc,1048236 +# ^ 0x10200038 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100198 <f_iu_du_dc@micromipsplt>: +.*: 7903 ffaa addiu \$2,\$pc,1048232 +# ^ 0x10200040 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001a4 <f_lo_dc@micromipsplt>: +.*: 7903 ffa8 addiu \$2,\$pc,1048224 +# ^ 0x10200044 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001b0 <f_dc@micromipsplt>: +.*: 7903 ffa8 addiu \$2,\$pc,1048224 +# ^ 0x10200050 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001bc <f_ic_dc@micromipsplt>: +.*: 7903 ffa6 addiu \$2,\$pc,1048216 +# ^ 0x10200054 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001c8 <f_iu_ic_dc@micromipsplt>: +.*: 7903 ffa5 addiu \$2,\$pc,1048212 +# ^ 0x1020005c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001d4 <f_iu_du_ic_dc@micromipsplt>: +.*: 7903 ffa3 addiu \$2,\$pc,1048204 +# ^ 0x10200060 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001e0 <f_lo_iu_ic_dc@micromipsplt>: +.*: 7903 ffa1 addiu \$2,\$pc,1048196 +# ^ 0x10200064 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001ec <f_lo_iu_du_ic_dc@micromipsplt>: +.*: 7903 ffa0 addiu \$2,\$pc,1048192 +# ^ 0x1020006c +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +101001f8 <f_lo_ic_dc@micromipsplt>: +.*: 7903 ff9e addiu \$2,\$pc,1048184 +# ^ 0x10200070 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +10100204 <f_lo@micromipsplt>: +.*: 7903 ff9c addiu \$2,\$pc,1048176 +# ^ 0x10200074 +.*: ff22 0000 lw \$25,0\(\$2\) +.*: 4599 jr \$25 +.*: 0f02 move \$24,\$2 + +Disassembly of section \.MIPS\.stubs: + +10101000 <_MIPS_STUBS_>: +# Lazy-binding stub for f_iu. +.*: ff3c 8010 lw \$25,-32752\(\$28\) +.*: 0dff move \$15,\$31 +.*: 45d9 jalr \$25 +.*: 3300 0021 li \$24,33 +# Lazy-binding stub for f_ic. +.*: ff3c 8010 lw \$25,-32752\(\$28\) +.*: 0dff move \$15,\$31 +.*: 45d9 jalr \$25 +.*: 3300 0020 li \$24,32 +# Lazy-binding stub for f_iu_ic. +.*: ff3c 8010 lw \$25,-32752\(\$28\) +.*: 0dff move \$15,\$31 +.*: 45d9 jalr \$25 +.*: 3300 001f li \$24,31 + \.\.\. + +Disassembly of section \.text\.a: + +10102000 <testc>: +.*: .... .... jal [0-9a-f]+ <f_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8070 lw \$2,-32656\(\$3\) +# ^ global GOT entry for f_ic +.*: .... .... jal [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8018 lw \$2,-32744\(\$3\) +# ^ local GOT entry for f_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 801c lw \$2,-32740\(\$3\) +# ^ local GOT entry for f_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8020 lw \$2,-32736\(\$3\) +# ^ local GOT entry for f_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_iu_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: .... .... jal [0-9a-f]+ <f_iu_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_iu_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_iu_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_iu_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8030 lw \$2,-32720\(\$3\) +# ^ local GOT entry for f_lo_ic@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8034 lw \$2,-32716\(\$3\) +# ^ local GOT entry for f_lo_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8038 lw \$2,-32712\(\$3\) +# ^ local GOT entry for f_lo_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 803c lw \$2,-32708\(\$3\) +# ^ local GOT entry for f_lo_du_ic_dc@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@micromipsplt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_du_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 8048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: .... .... jal [0-9a-f]+ <f_lo_iu_du_ic_dc@micromipsplt> +.*: 0000 0000 nop +.*: .... .... j [0-9a-f]+ <f_lo_iu_du_ic_dc@micromipsplt> +.*: 0c00 nop +.*: fc43 804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 459f jr \$31 + +Disassembly of section \.text\.b: + +10103000 <testu>: +.*: ........ jal [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c628074 lw \$2,-32652\(\$3\) +# ^ global GOT entry for f_iu +.*: 8c628050 lw \$2,-32688\(\$3\) +# ^ local GOT entry for f_iu_dc@micromipsplt +.*: 8c62806c lw \$2,-32660\(\$3\) +# ^ global GOT entry for f_iu_ic +.*: 8c628024 lw \$2,-32732\(\$3\) +# ^ local GOT entry for f_iu_ic_dc@micromipsplt +.*: ........ jal [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du@plt> +.*: 00000000 nop +.*: 8c628054 lw \$2,-32684\(\$3\) +# ^ local GOT entry for f_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628058 lw \$2,-32680\(\$3\) +# ^ local GOT entry for f_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628028 lw \$2,-32728\(\$3\) +# ^ local GOT entry for f_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62802c lw \$2,-32724\(\$3\) +# ^ local GOT entry for f_iu_du_ic_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_dc@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic@plt> +.*: 00000000 nop +.*: ........ jal [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62805c lw \$2,-32676\(\$3\) +# ^ local GOT entry for f_lo_iu@micromipsplt +.*: 8c628060 lw \$2,-32672\(\$3\) +# ^ local GOT entry for f_lo_iu_dc@micromipsplt +.*: 8c628040 lw \$2,-32704\(\$3\) +# ^ local GOT entry for f_lo_iu_ic@micromipsplt +.*: 8c628044 lw \$2,-32700\(\$3\) +# ^ local GOT entry for f_lo_iu_ic_dc@micromipsplt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt> +.*: 00000000 nop +.*: 8c628064 lw \$2,-32668\(\$3\) +# ^ local GOT entry for f_lo_iu_du@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_dc@plt> +.*: 00000000 nop +.*: 8c628068 lw \$2,-32664\(\$3\) +# ^ local GOT entry for f_lo_iu_du_dc@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic@plt> +.*: 00000000 nop +.*: 8c628048 lw \$2,-32696\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic@plt +.*: ........ jal [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: ........ j [0-9a-f]+ <f_lo_iu_du_ic_dc@plt> +.*: 00000000 nop +.*: 8c62804c lw \$2,-32692\(\$3\) +# ^ local GOT entry for f_lo_iu_du_ic_dc@plt +.*: 03e00008 jr \$31 + +Disassembly of section \.text\.c: + +10104000 <testlo>: +.*: 3040 0205 li \$2,517 +# ^ low 16 bits of f_lo@micromipsplt +.*: 3040 01a5 li \$2,421 +# ^ low 16 bits of f_lo_dc@micromipsplt +.*: 3040 0175 li \$2,373 +# ^ low 16 bits of f_lo_ic@micromipsplt +.*: 3040 01f9 li \$2,505 +# ^ low 16 bits of f_lo_ic_dc@micromipsplt +.*: 3040 00e0 li \$2,224 +# ^ low 16 bits of f_lo_du@plt +.*: 3040 0070 li \$2,112 +# ^ low 16 bits of f_lo_du_dc@plt +.*: 3040 0060 li \$2,96 +# ^ low 16 bits of f_lo_du_ic@plt +.*: 3040 0030 li \$2,48 +# ^ low 16 bits of f_lo_du_ic_dc@plt +.*: 3040 0121 li \$2,289 +# ^ low 16 bits of f_lo_iu@micromipsplt +.*: 3040 0151 li \$2,337 +# ^ low 16 bits of f_lo_iu_dc@micromipsplt +.*: 3040 0169 li \$2,361 +# ^ low 16 bits of f_lo_iu_ic@micromipsplt +.*: 3040 01e1 li \$2,481 +# ^ low 16 bits of f_lo_iu_ic_dc@micromipsplt +.*: 3040 00d0 li \$2,208 +# ^ low 16 bits of f_lo_iu_du@plt +.*: 3040 0020 li \$2,32 +# ^ low 16 bits of f_lo_iu_du_dc@plt +.*: 3040 0100 li \$2,256 +# ^ low 16 bits of f_lo_iu_du_ic@plt +.*: 3040 0110 li \$2,272 +# ^ low 16 bits of f_lo_iu_du_ic_dc@plt + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.rd new file mode 100644 index 0000000..8f7d85c --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips.rd @@ -0,0 +1,170 @@ + +Dynamic section .* +#... + 0x00000003 \(PLTGOT\) 0x10201000 +#... + 0x70000013 \(MIPS_GOTSYM\) 0x1f + 0x00000014 \(PLTREL\) REL + 0x00000017 \(JMPREL\) 0x10004000 + 0x00000002 \(PLTRELSZ\) 224 \(bytes\) + 0x70000032 \(MIPS_PLTGOT\) 0x10200000 +#... +Relocation section '\.rel\.plt' .* + Offset Info Type Sym\.Value Sym\. Name +10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100121 f_lo_iu +1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu_du_dc +10200010 [^ ]+ R_MIPS_JUMP_SLOT 10100030 f_lo_du_ic_dc +10200014 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_dc +10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100151 f_lo_iu_dc +1020001c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic +10200020 [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_lo_du_ic +10200024 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_dc +10200028 [^ ]+ R_MIPS_JUMP_SLOT 10100169 f_lo_iu_ic +1020002c [^ ]+ R_MIPS_JUMP_SLOT 10100175 f_lo_ic +10200030 [^ ]+ R_MIPS_JUMP_SLOT 10100070 f_lo_du_dc +10200034 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du +10200038 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic_dc +1020003c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du_ic +10200040 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_dc +10200044 [^ ]+ R_MIPS_JUMP_SLOT 101001a5 f_lo_dc +10200048 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du +1020004c [^ ]+ R_MIPS_JUMP_SLOT 101000d0 f_lo_iu_du +10200050 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_dc +10200054 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_ic_dc +10200058 [^ ]+ R_MIPS_JUMP_SLOT 101000e0 f_lo_du +1020005c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_ic_dc +10200060 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du_ic_dc +10200064 [^ ]+ R_MIPS_JUMP_SLOT 101001e1 f_lo_iu_ic_dc +10200068 [^ ]+ R_MIPS_JUMP_SLOT 10100100 f_lo_iu_du_ic +1020006c [^ ]+ R_MIPS_JUMP_SLOT 10100110 f_lo_iu_du_ic_dc +10200070 [^ ]+ R_MIPS_JUMP_SLOT 101001f9 f_lo_ic_dc +10200074 [^ ]+ R_MIPS_JUMP_SLOT 10100205 f_lo + +Symbol table '\.dynsym' .* + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# _lo symbols have their address taken, so their PLT symbols need to have +# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish +# them from old-style lazy-binding stubs. Non-_lo symbols are only called, +# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation. +# +# A MIPS (as opposed to microMIPS) PLT should be used as the symbol value +# if and only if the function has a direct MIPS caller (du). + .*: 10100121 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu + .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_dc +#... + .*: 10100030 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_dc + .*: 10100151 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic + .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_dc + .*: 10100169 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic + .*: 10100175 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic + .*: 10100070 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du_ic + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_dc + .*: 101001a5 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du + .*: 101000d0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic_dc + .*: 101000e0 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_ic_dc + .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du_ic_dc +#... + .*: 101001e1 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_ic_dc + .*: 10100100 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic + .*: 10100110 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du_ic_dc + .*: 101001f9 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc + .*: 10100205 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo +# The start of the GOT-mapped area. This should only contain functions that +# are accessed purely via the traditional psABI scheme. The symbol value +# is the address of the lazy-binding stub. + 31: 10101019 0 FUNC GLOBAL DEFAULT UND f_iu_ic + 32: 1010100d 0 FUNC GLOBAL DEFAULT UND f_ic + 33: 10101001 0 FUNC GLOBAL DEFAULT UND f_iu + +Symbol table '\.symtab' .* +#... +Primary GOT: + Canonical gp value: 10208ff0 + + Reserved entries: + Address Access Initial Purpose + 10201000 -32752\(gp\) 00000000 Lazy resolver + 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + +# See the disassembly output for the meaning of each entry. + Local entries: + Address Access Initial + 10201008 -32744\(gp\) 101001bd + 1020100c -32740\(gp\) 101000a0 + 10201010 -32736\(gp\) 10100090 + 10201014 -32732\(gp\) 101001c9 + 10201018 -32728\(gp\) 10100050 + 1020101c -32724\(gp\) 101000f0 + 10201020 -32720\(gp\) 10100175 + 10201024 -32716\(gp\) 101001f9 + 10201028 -32712\(gp\) 10100060 + 1020102c -32708\(gp\) 10100030 + 10201030 -32704\(gp\) 10100169 + 10201034 -32700\(gp\) 101001e1 + 10201038 -32696\(gp\) 10100100 + 1020103c -32692\(gp\) 10100110 + 10201040 -32688\(gp\) 1010015d + 10201044 -32684\(gp\) 101000c0 + 10201048 -32680\(gp\) 101000b0 + 1020104c -32676\(gp\) 10100121 + 10201050 -32672\(gp\) 10100151 + 10201054 -32668\(gp\) 101000d0 + 10201058 -32664\(gp\) 10100020 + + Global entries: + Address Access Initial Sym\.Val\. Type Ndx Name + 1020105c -32660\(gp\) 10101019 10101019 FUNC UND f_iu_ic + 10201060 -32656\(gp\) 1010100d 1010100d FUNC UND f_ic + 10201064 -32652\(gp\) 10101001 10101001 FUNC UND f_iu + + +PLT GOT: + + Reserved entries: + Address Initial Purpose + 10200000 00000000 PLT lazy resolver + 10200004 00000000 Module pointer + + Entries: + Address Initial Sym\.Val\. Type Ndx Name + 10200008 10100000 10100121 FUNC UND f_lo_iu + 1020000c 10100000 10100020 FUNC UND f_lo_iu_du_dc + 10200010 10100000 10100030 FUNC UND f_lo_du_ic_dc + 10200014 10100000 00000000 FUNC UND f_du_dc + 10200018 10100000 10100151 FUNC UND f_lo_iu_dc + 1020001c 10100000 00000000 FUNC UND f_iu_du_ic + 10200020 10100000 10100060 FUNC UND f_lo_du_ic + 10200024 10100000 00000000 FUNC UND f_iu_dc + 10200028 10100000 10100169 FUNC UND f_lo_iu_ic + 1020002c 10100000 10100175 FUNC UND f_lo_ic + 10200030 10100000 10100070 FUNC UND f_lo_du_dc + 10200034 10100000 00000000 FUNC UND f_du + 10200038 10100000 00000000 FUNC UND f_du_ic_dc + 1020003c 10100000 00000000 FUNC UND f_du_ic + 10200040 10100000 00000000 FUNC UND f_iu_du_dc + 10200044 10100000 101001a5 FUNC UND f_lo_dc + 10200048 10100000 00000000 FUNC UND f_iu_du + 1020004c 10100000 101000d0 FUNC UND f_lo_iu_du + 10200050 10100000 00000000 FUNC UND f_dc + 10200054 10100000 00000000 FUNC UND f_ic_dc + 10200058 10100000 101000e0 FUNC UND f_lo_du + 1020005c 10100000 00000000 FUNC UND f_iu_ic_dc + 10200060 10100000 00000000 FUNC UND f_iu_du_ic_dc + 10200064 10100000 101001e1 FUNC UND f_lo_iu_ic_dc + 10200068 10100000 10100100 FUNC UND f_lo_iu_du_ic + 1020006c 10100000 10100110 FUNC UND f_lo_iu_du_ic_dc + 10200070 10100000 101001f9 FUNC UND f_lo_ic_dc + 10200074 10100000 10100205 FUNC UND f_lo + + diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1.ld new file mode 100644 index 0000000..0108d0f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1.ld @@ -0,0 +1,40 @@ +SECTIONS +{ + . = 0x10000000; + .interp : { *(.interp) } + .reginfo : { *(.reginfo) } + .hash : { *(.hash) } + . = ALIGN(0x1000); + .dynsym : { *(.dynsym) } + . = ALIGN(0x1000); + .dynstr : { *(.dynstr) } + . = ALIGN(0x1000); + .dynamic : { *(.dynamic) } + . = ALIGN(0x1000); + .rel.dyn : { *(.rel.dyn) } + . = ALIGN(0x1000); + .rel.plt : { *(.rel.plt) } + . = 0x10100000; + .plt : { *(.plt) } + . = ALIGN(0x1000); + .MIPS.stubs : { *(.MIPS.stubs) } + . = ALIGN(0x1000); + .text.a : { *(.text.a) } + . = ALIGN(0x1000); + .text.b : { *(.text.b) } + . = ALIGN(0x1000); + .text.c : { *(.text.c) } + . = ALIGN(0x1000); + .text.d : { *(.text.d) } + . = 0x10200000; + .got.plt : { *(.got.plt) } + . = ALIGN(0x1000); + .data : { *(.data) } + . = ALIGN(0x1000); + _gp = . + 0x7ff0; + .got : { *(.got) } + . = ALIGN(0x1000); + .rld_map : { *(.rld_map) } + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } +} diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1.s b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1.s new file mode 100644 index 0000000..aa0b497 --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1.s @@ -0,0 +1,62 @@ + .macro call_stub, name + .set push + .set nomips16 + .section .mips16.call.\name, "ax", @progbits + .ent __call_stub_\name + .type __call_stub_\name, @function +__call_stub_\name: + la $25, \name + jr $25 + .set pop + .endm + + # Flags to specify how a particular function is referenced + + .equ DC, 1 # Direct call from "compressed" code + .equ IC, 2 # Indirect call from "compressed" code + .equ DU, 4 # Direct call from "uncompressed" code + .equ IU, 8 # Indirect call from "uncompressed" code + .equ LO, 16 # Direct address reference (%lo) + + # A wrapper around a macro called test_one, which is defined by + # the file that includes this one. NAME is the name of a function + # that is referenced in the way described by FLAGS, an inclusive OR + # of the flags above. The wrapper filters out any functions whose + # FLAGS are not a subset of FILTER. + + .macro test_filter, name, flags + .if (\flags & filter) == \flags + test_one \name, \flags + .endif + .endm + + .macro test_all_dc, name, flags + test_filter \name, \flags + test_filter \name\()_dc, (\flags | DC) + .endm + + .macro test_all_ic, name, flags + test_all_dc \name, \flags + test_all_dc \name\()_ic, (\flags | IC) + .endm + + .macro test_all_du, name, flags + test_all_ic \name, \flags + test_all_ic \name\()_du, (\flags | DU) + .endm + + .macro test_all_iu, name, flags + test_all_du \name, \flags + test_all_du \name\()_iu, (\flags | IU) + .endm + + .macro test_all_lo, name, flags + test_all_iu \name, \flags + test_all_iu \name\()_lo, (\flags | LO) + .endm + + # Test all the combinations of interest. + + .macro test_all + test_all_lo f, 0 + .endm diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1a.s b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1a.s new file mode 100644 index 0000000..d5c6b4f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1a.s @@ -0,0 +1,37 @@ +# Define a function with all "compressed" (dc and ic) references. + + .abicalls + .option pic0 + + .include "compressed-plt-1.s" + + .macro test_one, name, types + .if (\types) & DC + jal \name + nop + .if micromips + .ifdef o32 + j \name + nop + .endif + .endif + .endif + .if (\types) & IC + lw $2, %call16(\name)($3) + .endif + .endm + + .if micromips + .set micromips + .else + .set mips16 + .endif + + .section .text.a, "ax", @progbits + .globl testc + .ent testc + .set noreorder +testc: + test_all + jr $31 + .end testc diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1b.s b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1b.s new file mode 100644 index 0000000..33deccb --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1b.s @@ -0,0 +1,27 @@ +# Define a function with all "uncompressed" (du and iu) references. + + .abicalls + .option pic0 + + .include "compressed-plt-1.s" + + .macro test_one, name, types + .if (\types) & DU + jal \name + nop + j \name + nop + .endif + .if (\types) & IU + lw $2, %call16(\name)($3) + .endif + .endm + + .section .text.b, "ax", @progbits + .globl testu + .ent testu + .set noreorder +testu: + test_all + jr $31 + .end testu diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1c.s b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1c.s new file mode 100644 index 0000000..651424b --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1c.s @@ -0,0 +1,24 @@ +# Define a function with all direct (%lo) references. + + .abicalls + .option pic0 + + .include "compressed-plt-1.s" + + .macro test_one, name, types + .if (\types) & LO + li $2,%lo(\name) + .endif + .endm + + .if micromips + .set micromips + .endif + + .section .text.c, "ax", @progbits + .globl testlo + .ent testlo + .set noreorder +testlo: + test_all + .end testlo diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1d.s b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1d.s new file mode 100644 index 0000000..8163c8e --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1d.s @@ -0,0 +1,22 @@ +# Create a GOT reference for every function under test. + + .abicalls + .option pic2 + + .include "compressed-plt-1.s" + + .macro test_one, name, types + lw $2,%got(\name)($gp) + .endm + + .if micromips + .set micromips + .endif + + .section .text.d, "ax", @progbits + .globl testgot + .ent testgot + .set noreorder +testgot: + test_all + .end testgot diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1e.s b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1e.s new file mode 100644 index 0000000..4084a6f --- /dev/null +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/compressed-plt-1e.s @@ -0,0 +1,13 @@ +# Create a .word reference for every function under test. + + .abicalls + .option pic2 + + .include "compressed-plt-1.s" + + .macro test_one, name, types + .word \name + .endm + + .data + test_all diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/dyn-sec64.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/dyn-sec64.ld index 4c6353a..c7af3f4 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/dyn-sec64.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/dyn-sec64.ld @@ -20,4 +20,6 @@ SECTIONS HIDDEN (_gp = ALIGN (16) + 0x7ff0); .got : { *(.got) } .data : { *(.data) } + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32-embed.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32-embed.d index d492998..58f23ed 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32-embed.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32-embed.d @@ -1,6 +1,7 @@ #name: MIPS ELF got reloc n32 #as: -march=from-abi -EB -n32 -KPIC -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s +#objcopy_objects: -R .MIPS.abiflags +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d index 535a538..174153d 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d @@ -1,6 +1,7 @@ #name: MIPS ELF got reloc n32 #as: -march=from-abi -EB -n32 -KPIC -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-embed.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-embed.d index f2719f0..c55900f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-embed.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-embed.d @@ -1,6 +1,7 @@ #name: MIPS ELF got reloc n64 #as: -march=from-abi -EB -64 -KPIC -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d index c1c3326..8e2822d 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d @@ -1,6 +1,7 @@ #name: MIPS ELF got reloc n64 #as: -march=from-abi -EB -64 -KPIC -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64.d index 55dd7ae..492f76e 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-got-n64.d @@ -1,6 +1,7 @@ #name: MIPS ELF got reloc n64 #as: -march=from-abi -EB -64 -KPIC -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d index 1d0c045..d6c2e85 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d @@ -1,6 +1,7 @@ #name: MIPS ELF xgot reloc n32 #as: -march=from-abi -EB -n32 -KPIC -xgot -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn @@ -18,382 +19,382 @@ Disassembly of section \.text: 10000074 <fn>: 10000074: 3c050000 lui a1,0x0 10000078: 00bc2821 addu a1,a1,gp -1000007c: 8ca58018 lw a1,-32744\(a1\) +1000007c: 8ca58038 lw a1,-32712\(a1\) 10000080: 3c050000 lui a1,0x0 10000084: 00bc2821 addu a1,a1,gp -10000088: 8ca58018 lw a1,-32744\(a1\) +10000088: 8ca58038 lw a1,-32712\(a1\) 1000008c: 24a5000c addiu a1,a1,12 10000090: 3c050000 lui a1,0x0 10000094: 00bc2821 addu a1,a1,gp -10000098: 8ca58018 lw a1,-32744\(a1\) +10000098: 8ca58038 lw a1,-32712\(a1\) 1000009c: 3c010001 lui at,0x1 100000a0: 3421e240 ori at,at,0xe240 100000a4: 00a12821 addu a1,a1,at 100000a8: 3c050000 lui a1,0x0 100000ac: 00bc2821 addu a1,a1,gp -100000b0: 8ca58018 lw a1,-32744\(a1\) +100000b0: 8ca58038 lw a1,-32712\(a1\) 100000b4: 00b12821 addu a1,a1,s1 100000b8: 3c050000 lui a1,0x0 100000bc: 00bc2821 addu a1,a1,gp -100000c0: 8ca58018 lw a1,-32744\(a1\) +100000c0: 8ca58038 lw a1,-32712\(a1\) 100000c4: 24a5000c addiu a1,a1,12 100000c8: 00b12821 addu a1,a1,s1 100000cc: 3c050000 lui a1,0x0 100000d0: 00bc2821 addu a1,a1,gp -100000d4: 8ca58018 lw a1,-32744\(a1\) +100000d4: 8ca58038 lw a1,-32712\(a1\) 100000d8: 3c010001 lui at,0x1 100000dc: 3421e240 ori at,at,0xe240 100000e0: 00a12821 addu a1,a1,at 100000e4: 00b12821 addu a1,a1,s1 100000e8: 3c050000 lui a1,0x0 100000ec: 00bc2821 addu a1,a1,gp -100000f0: 8ca58018 lw a1,-32744\(a1\) +100000f0: 8ca58038 lw a1,-32712\(a1\) 100000f4: 8ca50000 lw a1,0\(a1\) 100000f8: 3c050000 lui a1,0x0 100000fc: 00bc2821 addu a1,a1,gp -10000100: 8ca58018 lw a1,-32744\(a1\) +10000100: 8ca58038 lw a1,-32712\(a1\) 10000104: 8ca5000c lw a1,12\(a1\) 10000108: 3c050000 lui a1,0x0 1000010c: 00bc2821 addu a1,a1,gp -10000110: 8ca58018 lw a1,-32744\(a1\) +10000110: 8ca58038 lw a1,-32712\(a1\) 10000114: 00b12821 addu a1,a1,s1 10000118: 8ca50000 lw a1,0\(a1\) 1000011c: 3c050000 lui a1,0x0 10000120: 00bc2821 addu a1,a1,gp -10000124: 8ca58018 lw a1,-32744\(a1\) +10000124: 8ca58038 lw a1,-32712\(a1\) 10000128: 00b12821 addu a1,a1,s1 1000012c: 8ca5000c lw a1,12\(a1\) 10000130: 3c010000 lui at,0x0 10000134: 003c0821 addu at,at,gp -10000138: 8c218018 lw at,-32744\(at\) +10000138: 8c218038 lw at,-32712\(at\) 1000013c: 00250821 addu at,at,a1 10000140: 8c250022 lw a1,34\(at\) 10000144: 3c010000 lui at,0x0 10000148: 003c0821 addu at,at,gp -1000014c: 8c218018 lw at,-32744\(at\) +1000014c: 8c218038 lw at,-32712\(at\) 10000150: 00250821 addu at,at,a1 10000154: ac250038 sw a1,56\(at\) 10000158: 3c010000 lui at,0x0 1000015c: 003c0821 addu at,at,gp -10000160: 8c218018 lw at,-32744\(at\) +10000160: 8c218038 lw at,-32712\(at\) 10000164: 88250000 lwl a1,0\(at\) 10000168: 98250003 lwr a1,3\(at\) 1000016c: 3c010000 lui at,0x0 10000170: 003c0821 addu at,at,gp -10000174: 8c218018 lw at,-32744\(at\) +10000174: 8c218038 lw at,-32712\(at\) 10000178: 2421000c addiu at,at,12 1000017c: 88250000 lwl a1,0\(at\) 10000180: 98250003 lwr a1,3\(at\) 10000184: 3c010000 lui at,0x0 10000188: 003c0821 addu at,at,gp -1000018c: 8c218018 lw at,-32744\(at\) +1000018c: 8c218038 lw at,-32712\(at\) 10000190: 00310821 addu at,at,s1 10000194: 88250000 lwl a1,0\(at\) 10000198: 98250003 lwr a1,3\(at\) 1000019c: 3c010000 lui at,0x0 100001a0: 003c0821 addu at,at,gp -100001a4: 8c218018 lw at,-32744\(at\) +100001a4: 8c218038 lw at,-32712\(at\) 100001a8: 2421000c addiu at,at,12 100001ac: 00310821 addu at,at,s1 100001b0: 88250000 lwl a1,0\(at\) 100001b4: 98250003 lwr a1,3\(at\) 100001b8: 3c010000 lui at,0x0 100001bc: 003c0821 addu at,at,gp -100001c0: 8c218018 lw at,-32744\(at\) +100001c0: 8c218038 lw at,-32712\(at\) 100001c4: 24210022 addiu at,at,34 100001c8: 00250821 addu at,at,a1 100001cc: 88250000 lwl a1,0\(at\) 100001d0: 98250003 lwr a1,3\(at\) 100001d4: 3c010000 lui at,0x0 100001d8: 003c0821 addu at,at,gp -100001dc: 8c218018 lw at,-32744\(at\) +100001dc: 8c218038 lw at,-32712\(at\) 100001e0: 24210038 addiu at,at,56 100001e4: 00250821 addu at,at,a1 100001e8: a8250000 swl a1,0\(at\) 100001ec: b8250003 swr a1,3\(at\) -100001f0: 8f85801c lw a1,-32740\(gp\) +100001f0: 8f858018 lw a1,-32744\(gp\) 100001f4: 24a506b8 addiu a1,a1,1720 -100001f8: 8f85801c lw a1,-32740\(gp\) +100001f8: 8f858018 lw a1,-32744\(gp\) 100001fc: 24a506c4 addiu a1,a1,1732 -10000200: 8f858020 lw a1,-32736\(gp\) +10000200: 8f85801c lw a1,-32740\(gp\) 10000204: 24a5e8f8 addiu a1,a1,-5896 -10000208: 8f85801c lw a1,-32740\(gp\) +10000208: 8f858018 lw a1,-32744\(gp\) 1000020c: 24a506b8 addiu a1,a1,1720 10000210: 00b12821 addu a1,a1,s1 -10000214: 8f85801c lw a1,-32740\(gp\) +10000214: 8f858018 lw a1,-32744\(gp\) 10000218: 24a506c4 addiu a1,a1,1732 1000021c: 00b12821 addu a1,a1,s1 -10000220: 8f858020 lw a1,-32736\(gp\) +10000220: 8f85801c lw a1,-32740\(gp\) 10000224: 24a5e8f8 addiu a1,a1,-5896 10000228: 00b12821 addu a1,a1,s1 -1000022c: 8f85801c lw a1,-32740\(gp\) +1000022c: 8f858018 lw a1,-32744\(gp\) 10000230: 8ca506b8 lw a1,1720\(a1\) -10000234: 8f85801c lw a1,-32740\(gp\) +10000234: 8f858018 lw a1,-32744\(gp\) 10000238: 8ca506c4 lw a1,1732\(a1\) -1000023c: 8f85801c lw a1,-32740\(gp\) +1000023c: 8f858018 lw a1,-32744\(gp\) 10000240: 00b12821 addu a1,a1,s1 10000244: 8ca506b8 lw a1,1720\(a1\) -10000248: 8f85801c lw a1,-32740\(gp\) +10000248: 8f858018 lw a1,-32744\(gp\) 1000024c: 00b12821 addu a1,a1,s1 10000250: 8ca506c4 lw a1,1732\(a1\) -10000254: 8f81801c lw at,-32740\(gp\) +10000254: 8f818018 lw at,-32744\(gp\) 10000258: 00250821 addu at,at,a1 1000025c: 8c2506da lw a1,1754\(at\) -10000260: 8f81801c lw at,-32740\(gp\) +10000260: 8f818018 lw at,-32744\(gp\) 10000264: 00250821 addu at,at,a1 10000268: ac2506f0 sw a1,1776\(at\) -1000026c: 8f81801c lw at,-32740\(gp\) +1000026c: 8f818018 lw at,-32744\(gp\) 10000270: 242106b8 addiu at,at,1720 10000274: 88250000 lwl a1,0\(at\) 10000278: 98250003 lwr a1,3\(at\) -1000027c: 8f81801c lw at,-32740\(gp\) +1000027c: 8f818018 lw at,-32744\(gp\) 10000280: 242106c4 addiu at,at,1732 10000284: 88250000 lwl a1,0\(at\) 10000288: 98250003 lwr a1,3\(at\) -1000028c: 8f81801c lw at,-32740\(gp\) +1000028c: 8f818018 lw at,-32744\(gp\) 10000290: 242106b8 addiu at,at,1720 10000294: 00310821 addu at,at,s1 10000298: 88250000 lwl a1,0\(at\) 1000029c: 98250003 lwr a1,3\(at\) -100002a0: 8f81801c lw at,-32740\(gp\) +100002a0: 8f818018 lw at,-32744\(gp\) 100002a4: 242106c4 addiu at,at,1732 100002a8: 00310821 addu at,at,s1 100002ac: 88250000 lwl a1,0\(at\) 100002b0: 98250003 lwr a1,3\(at\) -100002b4: 8f81801c lw at,-32740\(gp\) +100002b4: 8f818018 lw at,-32744\(gp\) 100002b8: 242106da addiu at,at,1754 100002bc: 00250821 addu at,at,a1 100002c0: 88250000 lwl a1,0\(at\) 100002c4: 98250003 lwr a1,3\(at\) -100002c8: 8f81801c lw at,-32740\(gp\) +100002c8: 8f818018 lw at,-32744\(gp\) 100002cc: 242106f0 addiu at,at,1776 100002d0: 00250821 addu at,at,a1 100002d4: a8250000 swl a1,0\(at\) 100002d8: b8250003 swr a1,3\(at\) 100002dc: 3c050000 lui a1,0x0 100002e0: 00bc2821 addu a1,a1,gp -100002e4: 8ca58024 lw a1,-32732\(a1\) -100002e8: 8f858028 lw a1,-32728\(gp\) +100002e4: 8ca58034 lw a1,-32716\(a1\) +100002e8: 8f858020 lw a1,-32736\(gp\) 100002ec: 24a50074 addiu a1,a1,116 100002f0: 3c190000 lui t9,0x0 100002f4: 033cc821 addu t9,t9,gp -100002f8: 8f398024 lw t9,-32732\(t9\) -100002fc: 8f998028 lw t9,-32728\(gp\) +100002f8: 8f398034 lw t9,-32716\(t9\) +100002fc: 8f998020 lw t9,-32736\(gp\) 10000300: 27390074 addiu t9,t9,116 10000304: 3c190000 lui t9,0x0 10000308: 033cc821 addu t9,t9,gp -1000030c: 8f398024 lw t9,-32732\(t9\) +1000030c: 8f398034 lw t9,-32716\(t9\) 10000310: 0411ff58 bal 10000074 <fn> 10000314: 00000000 nop -10000318: 8f998028 lw t9,-32728\(gp\) +10000318: 8f998020 lw t9,-32736\(gp\) 1000031c: 27390074 addiu t9,t9,116 10000320: 0411ff54 bal 10000074 <fn> 10000324: 00000000 nop 10000328: 3c050000 lui a1,0x0 1000032c: 00bc2821 addu a1,a1,gp -10000330: 8ca5802c lw a1,-32724\(a1\) +10000330: 8ca58030 lw a1,-32720\(a1\) 10000334: 3c050000 lui a1,0x0 10000338: 00bc2821 addu a1,a1,gp -1000033c: 8ca5802c lw a1,-32724\(a1\) +1000033c: 8ca58030 lw a1,-32720\(a1\) 10000340: 24a5000c addiu a1,a1,12 10000344: 3c050000 lui a1,0x0 10000348: 00bc2821 addu a1,a1,gp -1000034c: 8ca5802c lw a1,-32724\(a1\) +1000034c: 8ca58030 lw a1,-32720\(a1\) 10000350: 3c010001 lui at,0x1 10000354: 3421e240 ori at,at,0xe240 10000358: 00a12821 addu a1,a1,at 1000035c: 3c050000 lui a1,0x0 10000360: 00bc2821 addu a1,a1,gp -10000364: 8ca5802c lw a1,-32724\(a1\) +10000364: 8ca58030 lw a1,-32720\(a1\) 10000368: 00b12821 addu a1,a1,s1 1000036c: 3c050000 lui a1,0x0 10000370: 00bc2821 addu a1,a1,gp -10000374: 8ca5802c lw a1,-32724\(a1\) +10000374: 8ca58030 lw a1,-32720\(a1\) 10000378: 24a5000c addiu a1,a1,12 1000037c: 00b12821 addu a1,a1,s1 10000380: 3c050000 lui a1,0x0 10000384: 00bc2821 addu a1,a1,gp -10000388: 8ca5802c lw a1,-32724\(a1\) +10000388: 8ca58030 lw a1,-32720\(a1\) 1000038c: 3c010001 lui at,0x1 10000390: 3421e240 ori at,at,0xe240 10000394: 00a12821 addu a1,a1,at 10000398: 00b12821 addu a1,a1,s1 1000039c: 3c050000 lui a1,0x0 100003a0: 00bc2821 addu a1,a1,gp -100003a4: 8ca5802c lw a1,-32724\(a1\) +100003a4: 8ca58030 lw a1,-32720\(a1\) 100003a8: 8ca50000 lw a1,0\(a1\) 100003ac: 3c050000 lui a1,0x0 100003b0: 00bc2821 addu a1,a1,gp -100003b4: 8ca5802c lw a1,-32724\(a1\) +100003b4: 8ca58030 lw a1,-32720\(a1\) 100003b8: 8ca5000c lw a1,12\(a1\) 100003bc: 3c050000 lui a1,0x0 100003c0: 00bc2821 addu a1,a1,gp -100003c4: 8ca5802c lw a1,-32724\(a1\) +100003c4: 8ca58030 lw a1,-32720\(a1\) 100003c8: 00b12821 addu a1,a1,s1 100003cc: 8ca50000 lw a1,0\(a1\) 100003d0: 3c050000 lui a1,0x0 100003d4: 00bc2821 addu a1,a1,gp -100003d8: 8ca5802c lw a1,-32724\(a1\) +100003d8: 8ca58030 lw a1,-32720\(a1\) 100003dc: 00b12821 addu a1,a1,s1 100003e0: 8ca5000c lw a1,12\(a1\) 100003e4: 3c010000 lui at,0x0 100003e8: 003c0821 addu at,at,gp -100003ec: 8c21802c lw at,-32724\(at\) +100003ec: 8c218030 lw at,-32720\(at\) 100003f0: 00250821 addu at,at,a1 100003f4: 8c250022 lw a1,34\(at\) 100003f8: 3c010000 lui at,0x0 100003fc: 003c0821 addu at,at,gp -10000400: 8c21802c lw at,-32724\(at\) +10000400: 8c218030 lw at,-32720\(at\) 10000404: 00250821 addu at,at,a1 10000408: ac250038 sw a1,56\(at\) 1000040c: 3c010000 lui at,0x0 10000410: 003c0821 addu at,at,gp -10000414: 8c21802c lw at,-32724\(at\) +10000414: 8c218030 lw at,-32720\(at\) 10000418: 88250000 lwl a1,0\(at\) 1000041c: 98250003 lwr a1,3\(at\) 10000420: 3c010000 lui at,0x0 10000424: 003c0821 addu at,at,gp -10000428: 8c21802c lw at,-32724\(at\) +10000428: 8c218030 lw at,-32720\(at\) 1000042c: 2421000c addiu at,at,12 10000430: 88250000 lwl a1,0\(at\) 10000434: 98250003 lwr a1,3\(at\) 10000438: 3c010000 lui at,0x0 1000043c: 003c0821 addu at,at,gp -10000440: 8c21802c lw at,-32724\(at\) +10000440: 8c218030 lw at,-32720\(at\) 10000444: 00310821 addu at,at,s1 10000448: 88250000 lwl a1,0\(at\) 1000044c: 98250003 lwr a1,3\(at\) 10000450: 3c010000 lui at,0x0 10000454: 003c0821 addu at,at,gp -10000458: 8c21802c lw at,-32724\(at\) +10000458: 8c218030 lw at,-32720\(at\) 1000045c: 2421000c addiu at,at,12 10000460: 00310821 addu at,at,s1 10000464: 88250000 lwl a1,0\(at\) 10000468: 98250003 lwr a1,3\(at\) 1000046c: 3c010000 lui at,0x0 10000470: 003c0821 addu at,at,gp -10000474: 8c21802c lw at,-32724\(at\) +10000474: 8c218030 lw at,-32720\(at\) 10000478: 24210022 addiu at,at,34 1000047c: 00250821 addu at,at,a1 10000480: 88250000 lwl a1,0\(at\) 10000484: 98250003 lwr a1,3\(at\) 10000488: 3c010000 lui at,0x0 1000048c: 003c0821 addu at,at,gp -10000490: 8c21802c lw at,-32724\(at\) +10000490: 8c218030 lw at,-32720\(at\) 10000494: 24210038 addiu at,at,56 10000498: 00250821 addu at,at,a1 1000049c: a8250000 swl a1,0\(at\) 100004a0: b8250003 swr a1,3\(at\) -100004a4: 8f85801c lw a1,-32740\(gp\) +100004a4: 8f858018 lw a1,-32744\(gp\) 100004a8: 24a50730 addiu a1,a1,1840 -100004ac: 8f85801c lw a1,-32740\(gp\) +100004ac: 8f858018 lw a1,-32744\(gp\) 100004b0: 24a5073c addiu a1,a1,1852 -100004b4: 8f858020 lw a1,-32736\(gp\) +100004b4: 8f85801c lw a1,-32740\(gp\) 100004b8: 24a5e970 addiu a1,a1,-5776 -100004bc: 8f85801c lw a1,-32740\(gp\) +100004bc: 8f858018 lw a1,-32744\(gp\) 100004c0: 24a50730 addiu a1,a1,1840 100004c4: 00b12821 addu a1,a1,s1 -100004c8: 8f85801c lw a1,-32740\(gp\) +100004c8: 8f858018 lw a1,-32744\(gp\) 100004cc: 24a5073c addiu a1,a1,1852 100004d0: 00b12821 addu a1,a1,s1 -100004d4: 8f858020 lw a1,-32736\(gp\) +100004d4: 8f85801c lw a1,-32740\(gp\) 100004d8: 24a5e970 addiu a1,a1,-5776 100004dc: 00b12821 addu a1,a1,s1 -100004e0: 8f85801c lw a1,-32740\(gp\) +100004e0: 8f858018 lw a1,-32744\(gp\) 100004e4: 8ca50730 lw a1,1840\(a1\) -100004e8: 8f85801c lw a1,-32740\(gp\) +100004e8: 8f858018 lw a1,-32744\(gp\) 100004ec: 8ca5073c lw a1,1852\(a1\) -100004f0: 8f85801c lw a1,-32740\(gp\) +100004f0: 8f858018 lw a1,-32744\(gp\) 100004f4: 00b12821 addu a1,a1,s1 100004f8: 8ca50730 lw a1,1840\(a1\) -100004fc: 8f85801c lw a1,-32740\(gp\) +100004fc: 8f858018 lw a1,-32744\(gp\) 10000500: 00b12821 addu a1,a1,s1 10000504: 8ca5073c lw a1,1852\(a1\) -10000508: 8f81801c lw at,-32740\(gp\) +10000508: 8f818018 lw at,-32744\(gp\) 1000050c: 00250821 addu at,at,a1 10000510: 8c250752 lw a1,1874\(at\) -10000514: 8f81801c lw at,-32740\(gp\) +10000514: 8f818018 lw at,-32744\(gp\) 10000518: 00250821 addu at,at,a1 1000051c: ac250768 sw a1,1896\(at\) -10000520: 8f81801c lw at,-32740\(gp\) +10000520: 8f818018 lw at,-32744\(gp\) 10000524: 24210730 addiu at,at,1840 10000528: 88250000 lwl a1,0\(at\) 1000052c: 98250003 lwr a1,3\(at\) -10000530: 8f81801c lw at,-32740\(gp\) +10000530: 8f818018 lw at,-32744\(gp\) 10000534: 2421073c addiu at,at,1852 10000538: 88250000 lwl a1,0\(at\) 1000053c: 98250003 lwr a1,3\(at\) -10000540: 8f81801c lw at,-32740\(gp\) +10000540: 8f818018 lw at,-32744\(gp\) 10000544: 24210730 addiu at,at,1840 10000548: 00310821 addu at,at,s1 1000054c: 88250000 lwl a1,0\(at\) 10000550: 98250003 lwr a1,3\(at\) -10000554: 8f81801c lw at,-32740\(gp\) +10000554: 8f818018 lw at,-32744\(gp\) 10000558: 2421073c addiu at,at,1852 1000055c: 00310821 addu at,at,s1 10000560: 88250000 lwl a1,0\(at\) 10000564: 98250003 lwr a1,3\(at\) -10000568: 8f81801c lw at,-32740\(gp\) +10000568: 8f818018 lw at,-32744\(gp\) 1000056c: 24210752 addiu at,at,1874 10000570: 00250821 addu at,at,a1 10000574: 88250000 lwl a1,0\(at\) 10000578: 98250003 lwr a1,3\(at\) -1000057c: 8f81801c lw at,-32740\(gp\) +1000057c: 8f818018 lw at,-32744\(gp\) 10000580: 24210768 addiu at,at,1896 10000584: 00250821 addu at,at,a1 10000588: a8250000 swl a1,0\(at\) 1000058c: b8250003 swr a1,3\(at\) 10000590: 3c050000 lui a1,0x0 10000594: 00bc2821 addu a1,a1,gp -10000598: 8ca58030 lw a1,-32720\(a1\) -1000059c: 8f858028 lw a1,-32728\(gp\) +10000598: 8ca5802c lw a1,-32724\(a1\) +1000059c: 8f858020 lw a1,-32736\(gp\) 100005a0: 24a50674 addiu a1,a1,1652 100005a4: 3c190000 lui t9,0x0 100005a8: 033cc821 addu t9,t9,gp -100005ac: 8f398030 lw t9,-32720\(t9\) -100005b0: 8f998028 lw t9,-32728\(gp\) +100005ac: 8f39802c lw t9,-32724\(t9\) +100005b0: 8f998020 lw t9,-32736\(gp\) 100005b4: 27390674 addiu t9,t9,1652 100005b8: 3c190000 lui t9,0x0 100005bc: 033cc821 addu t9,t9,gp -100005c0: 8f398030 lw t9,-32720\(t9\) +100005c0: 8f39802c lw t9,-32724\(t9\) 100005c4: 0411002b bal 10000674 <fn2> 100005c8: 00000000 nop -100005cc: 8f998028 lw t9,-32728\(gp\) +100005cc: 8f998020 lw t9,-32736\(gp\) 100005d0: 27390674 addiu t9,t9,1652 100005d4: 04110027 bal 10000674 <fn2> 100005d8: 00000000 nop 100005dc: 3c050000 lui a1,0x0 100005e0: 00bc2821 addu a1,a1,gp -100005e4: 8ca58018 lw a1,-32744\(a1\) +100005e4: 8ca58038 lw a1,-32712\(a1\) 100005e8: 1000fea2 b 10000074 <fn> 100005ec: 00000000 nop 100005f0: 3c050000 lui a1,0x0 100005f4: 00bc2821 addu a1,a1,gp -100005f8: 8ca5802c lw a1,-32724\(a1\) +100005f8: 8ca58030 lw a1,-32720\(a1\) 100005fc: 8ca50000 lw a1,0\(a1\) 10000600: 1000001c b 10000674 <fn2> 10000604: 00000000 nop -10000608: 8f85801c lw a1,-32740\(gp\) +10000608: 8f858018 lw a1,-32744\(gp\) 1000060c: 24a506b8 addiu a1,a1,1720 10000610: 1000fe98 b 10000074 <fn> 10000614: 00000000 nop -10000618: 8f85801c lw a1,-32740\(gp\) +10000618: 8f858018 lw a1,-32744\(gp\) 1000061c: 24a5073c addiu a1,a1,1852 10000620: 10000014 b 10000674 <fn2> 10000624: 00000000 nop -10000628: 8f858020 lw a1,-32736\(gp\) +10000628: 8f85801c lw a1,-32740\(gp\) 1000062c: 24a5e8f8 addiu a1,a1,-5896 10000630: 1000fe90 b 10000074 <fn> 10000634: 00000000 nop -10000638: 8f85801c lw a1,-32740\(gp\) +10000638: 8f858018 lw a1,-32744\(gp\) 1000063c: 8ca50730 lw a1,1840\(a1\) 10000640: 1000000c b 10000674 <fn2> 10000644: 00000000 nop -10000648: 8f85801c lw a1,-32740\(gp\) +10000648: 8f858018 lw a1,-32744\(gp\) 1000064c: 8ca506c4 lw a1,1732\(a1\) 10000650: 1000fe88 b 10000074 <fn> 10000654: 00000000 nop -10000658: 8f81801c lw at,-32740\(gp\) +10000658: 8f818018 lw at,-32744\(gp\) 1000065c: 00250821 addu at,at,a1 10000660: 8c250752 lw a1,1874\(at\) 10000664: 10000003 b 10000674 <fn2> @@ -422,13 +423,13 @@ Disassembly of section \.got: 10010770 <_GLOBAL_OFFSET_TABLE_>: 10010770: 00000000 .* 10010774: 80000000 .* -10010778: 100106b8 .* -1001077c: 10010000 .* -10010780: 10030000 .* -10010784: 10000074 .* -10010788: 10000000 .* -1001078c: 10010730 .* -10010790: 10000674 .* -10010794: 00000000 .* -10010798: 00000000 .* +10010778: 10010000 .* +1001077c: 10030000 .* +10010780: 10000000 .* +10010784: 00000000 .* +10010788: 00000000 .* +1001078c: 10000674 .* +10010790: 10010730 .* +10010794: 10000074 .* +10010798: 100106b8 .* #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d index 4e105aa..b202e92 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d @@ -1,6 +1,7 @@ #name: MIPS ELF xgot reloc n32 #as: -march=from-abi -EB -n32 -KPIC -xgot -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn @@ -18,382 +19,382 @@ Disassembly of section \.text: 100000b0 <fn>: 100000b0: 3c050000 lui a1,0x0 100000b4: 00bc2821 addu a1,a1,gp -100000b8: 8ca58018 lw a1,-32744\(a1\) +100000b8: 8ca58038 lw a1,-32712\(a1\) 100000bc: 3c050000 lui a1,0x0 100000c0: 00bc2821 addu a1,a1,gp -100000c4: 8ca58018 lw a1,-32744\(a1\) +100000c4: 8ca58038 lw a1,-32712\(a1\) 100000c8: 24a5000c addiu a1,a1,12 100000cc: 3c050000 lui a1,0x0 100000d0: 00bc2821 addu a1,a1,gp -100000d4: 8ca58018 lw a1,-32744\(a1\) +100000d4: 8ca58038 lw a1,-32712\(a1\) 100000d8: 3c010001 lui at,0x1 100000dc: 3421e240 ori at,at,0xe240 100000e0: 00a12821 addu a1,a1,at 100000e4: 3c050000 lui a1,0x0 100000e8: 00bc2821 addu a1,a1,gp -100000ec: 8ca58018 lw a1,-32744\(a1\) +100000ec: 8ca58038 lw a1,-32712\(a1\) 100000f0: 00b12821 addu a1,a1,s1 100000f4: 3c050000 lui a1,0x0 100000f8: 00bc2821 addu a1,a1,gp -100000fc: 8ca58018 lw a1,-32744\(a1\) +100000fc: 8ca58038 lw a1,-32712\(a1\) 10000100: 24a5000c addiu a1,a1,12 10000104: 00b12821 addu a1,a1,s1 10000108: 3c050000 lui a1,0x0 1000010c: 00bc2821 addu a1,a1,gp -10000110: 8ca58018 lw a1,-32744\(a1\) +10000110: 8ca58038 lw a1,-32712\(a1\) 10000114: 3c010001 lui at,0x1 10000118: 3421e240 ori at,at,0xe240 1000011c: 00a12821 addu a1,a1,at 10000120: 00b12821 addu a1,a1,s1 10000124: 3c050000 lui a1,0x0 10000128: 00bc2821 addu a1,a1,gp -1000012c: 8ca58018 lw a1,-32744\(a1\) +1000012c: 8ca58038 lw a1,-32712\(a1\) 10000130: 8ca50000 lw a1,0\(a1\) 10000134: 3c050000 lui a1,0x0 10000138: 00bc2821 addu a1,a1,gp -1000013c: 8ca58018 lw a1,-32744\(a1\) +1000013c: 8ca58038 lw a1,-32712\(a1\) 10000140: 8ca5000c lw a1,12\(a1\) 10000144: 3c050000 lui a1,0x0 10000148: 00bc2821 addu a1,a1,gp -1000014c: 8ca58018 lw a1,-32744\(a1\) +1000014c: 8ca58038 lw a1,-32712\(a1\) 10000150: 00b12821 addu a1,a1,s1 10000154: 8ca50000 lw a1,0\(a1\) 10000158: 3c050000 lui a1,0x0 1000015c: 00bc2821 addu a1,a1,gp -10000160: 8ca58018 lw a1,-32744\(a1\) +10000160: 8ca58038 lw a1,-32712\(a1\) 10000164: 00b12821 addu a1,a1,s1 10000168: 8ca5000c lw a1,12\(a1\) 1000016c: 3c010000 lui at,0x0 10000170: 003c0821 addu at,at,gp -10000174: 8c218018 lw at,-32744\(at\) +10000174: 8c218038 lw at,-32712\(at\) 10000178: 00250821 addu at,at,a1 1000017c: 8c250022 lw a1,34\(at\) 10000180: 3c010000 lui at,0x0 10000184: 003c0821 addu at,at,gp -10000188: 8c218018 lw at,-32744\(at\) +10000188: 8c218038 lw at,-32712\(at\) 1000018c: 00250821 addu at,at,a1 10000190: ac250038 sw a1,56\(at\) 10000194: 3c010000 lui at,0x0 10000198: 003c0821 addu at,at,gp -1000019c: 8c218018 lw at,-32744\(at\) +1000019c: 8c218038 lw at,-32712\(at\) 100001a0: 88250000 lwl a1,0\(at\) 100001a4: 98250003 lwr a1,3\(at\) 100001a8: 3c010000 lui at,0x0 100001ac: 003c0821 addu at,at,gp -100001b0: 8c218018 lw at,-32744\(at\) +100001b0: 8c218038 lw at,-32712\(at\) 100001b4: 2421000c addiu at,at,12 100001b8: 88250000 lwl a1,0\(at\) 100001bc: 98250003 lwr a1,3\(at\) 100001c0: 3c010000 lui at,0x0 100001c4: 003c0821 addu at,at,gp -100001c8: 8c218018 lw at,-32744\(at\) +100001c8: 8c218038 lw at,-32712\(at\) 100001cc: 00310821 addu at,at,s1 100001d0: 88250000 lwl a1,0\(at\) 100001d4: 98250003 lwr a1,3\(at\) 100001d8: 3c010000 lui at,0x0 100001dc: 003c0821 addu at,at,gp -100001e0: 8c218018 lw at,-32744\(at\) +100001e0: 8c218038 lw at,-32712\(at\) 100001e4: 2421000c addiu at,at,12 100001e8: 00310821 addu at,at,s1 100001ec: 88250000 lwl a1,0\(at\) 100001f0: 98250003 lwr a1,3\(at\) 100001f4: 3c010000 lui at,0x0 100001f8: 003c0821 addu at,at,gp -100001fc: 8c218018 lw at,-32744\(at\) +100001fc: 8c218038 lw at,-32712\(at\) 10000200: 24210022 addiu at,at,34 10000204: 00250821 addu at,at,a1 10000208: 88250000 lwl a1,0\(at\) 1000020c: 98250003 lwr a1,3\(at\) 10000210: 3c010000 lui at,0x0 10000214: 003c0821 addu at,at,gp -10000218: 8c218018 lw at,-32744\(at\) +10000218: 8c218038 lw at,-32712\(at\) 1000021c: 24210038 addiu at,at,56 10000220: 00250821 addu at,at,a1 10000224: a8250000 swl a1,0\(at\) 10000228: b8250003 swr a1,3\(at\) -1000022c: 8f85801c lw a1,-32740\(gp\) +1000022c: 8f858018 lw a1,-32744\(gp\) 10000230: 24a506fc addiu a1,a1,1788 -10000234: 8f85801c lw a1,-32740\(gp\) +10000234: 8f858018 lw a1,-32744\(gp\) 10000238: 24a50708 addiu a1,a1,1800 -1000023c: 8f858020 lw a1,-32736\(gp\) +1000023c: 8f85801c lw a1,-32740\(gp\) 10000240: 24a5e93c addiu a1,a1,-5828 -10000244: 8f85801c lw a1,-32740\(gp\) +10000244: 8f858018 lw a1,-32744\(gp\) 10000248: 24a506fc addiu a1,a1,1788 1000024c: 00b12821 addu a1,a1,s1 -10000250: 8f85801c lw a1,-32740\(gp\) +10000250: 8f858018 lw a1,-32744\(gp\) 10000254: 24a50708 addiu a1,a1,1800 10000258: 00b12821 addu a1,a1,s1 -1000025c: 8f858020 lw a1,-32736\(gp\) +1000025c: 8f85801c lw a1,-32740\(gp\) 10000260: 24a5e93c addiu a1,a1,-5828 10000264: 00b12821 addu a1,a1,s1 -10000268: 8f85801c lw a1,-32740\(gp\) +10000268: 8f858018 lw a1,-32744\(gp\) 1000026c: 8ca506fc lw a1,1788\(a1\) -10000270: 8f85801c lw a1,-32740\(gp\) +10000270: 8f858018 lw a1,-32744\(gp\) 10000274: 8ca50708 lw a1,1800\(a1\) -10000278: 8f85801c lw a1,-32740\(gp\) +10000278: 8f858018 lw a1,-32744\(gp\) 1000027c: 00b12821 addu a1,a1,s1 10000280: 8ca506fc lw a1,1788\(a1\) -10000284: 8f85801c lw a1,-32740\(gp\) +10000284: 8f858018 lw a1,-32744\(gp\) 10000288: 00b12821 addu a1,a1,s1 1000028c: 8ca50708 lw a1,1800\(a1\) -10000290: 8f81801c lw at,-32740\(gp\) +10000290: 8f818018 lw at,-32744\(gp\) 10000294: 00250821 addu at,at,a1 10000298: 8c25071e lw a1,1822\(at\) -1000029c: 8f81801c lw at,-32740\(gp\) +1000029c: 8f818018 lw at,-32744\(gp\) 100002a0: 00250821 addu at,at,a1 100002a4: ac250734 sw a1,1844\(at\) -100002a8: 8f81801c lw at,-32740\(gp\) +100002a8: 8f818018 lw at,-32744\(gp\) 100002ac: 242106fc addiu at,at,1788 100002b0: 88250000 lwl a1,0\(at\) 100002b4: 98250003 lwr a1,3\(at\) -100002b8: 8f81801c lw at,-32740\(gp\) +100002b8: 8f818018 lw at,-32744\(gp\) 100002bc: 24210708 addiu at,at,1800 100002c0: 88250000 lwl a1,0\(at\) 100002c4: 98250003 lwr a1,3\(at\) -100002c8: 8f81801c lw at,-32740\(gp\) +100002c8: 8f818018 lw at,-32744\(gp\) 100002cc: 242106fc addiu at,at,1788 100002d0: 00310821 addu at,at,s1 100002d4: 88250000 lwl a1,0\(at\) 100002d8: 98250003 lwr a1,3\(at\) -100002dc: 8f81801c lw at,-32740\(gp\) +100002dc: 8f818018 lw at,-32744\(gp\) 100002e0: 24210708 addiu at,at,1800 100002e4: 00310821 addu at,at,s1 100002e8: 88250000 lwl a1,0\(at\) 100002ec: 98250003 lwr a1,3\(at\) -100002f0: 8f81801c lw at,-32740\(gp\) +100002f0: 8f818018 lw at,-32744\(gp\) 100002f4: 2421071e addiu at,at,1822 100002f8: 00250821 addu at,at,a1 100002fc: 88250000 lwl a1,0\(at\) 10000300: 98250003 lwr a1,3\(at\) -10000304: 8f81801c lw at,-32740\(gp\) +10000304: 8f818018 lw at,-32744\(gp\) 10000308: 24210734 addiu at,at,1844 1000030c: 00250821 addu at,at,a1 10000310: a8250000 swl a1,0\(at\) 10000314: b8250003 swr a1,3\(at\) 10000318: 3c050000 lui a1,0x0 1000031c: 00bc2821 addu a1,a1,gp -10000320: 8ca58024 lw a1,-32732\(a1\) -10000324: 8f858028 lw a1,-32728\(gp\) +10000320: 8ca58034 lw a1,-32716\(a1\) +10000324: 8f858020 lw a1,-32736\(gp\) 10000328: 24a500b0 addiu a1,a1,176 1000032c: 3c190000 lui t9,0x0 10000330: 033cc821 addu t9,t9,gp -10000334: 8f398024 lw t9,-32732\(t9\) -10000338: 8f998028 lw t9,-32728\(gp\) +10000334: 8f398034 lw t9,-32716\(t9\) +10000338: 8f998020 lw t9,-32736\(gp\) 1000033c: 273900b0 addiu t9,t9,176 10000340: 3c190000 lui t9,0x0 10000344: 033cc821 addu t9,t9,gp -10000348: 8f398024 lw t9,-32732\(t9\) +10000348: 8f398034 lw t9,-32716\(t9\) 1000034c: 0411ff58 bal 100000b0 <fn> 10000350: 00000000 nop -10000354: 8f998028 lw t9,-32728\(gp\) +10000354: 8f998020 lw t9,-32736\(gp\) 10000358: 273900b0 addiu t9,t9,176 1000035c: 0411ff54 bal 100000b0 <fn> 10000360: 00000000 nop 10000364: 3c050000 lui a1,0x0 10000368: 00bc2821 addu a1,a1,gp -1000036c: 8ca5802c lw a1,-32724\(a1\) +1000036c: 8ca58030 lw a1,-32720\(a1\) 10000370: 3c050000 lui a1,0x0 10000374: 00bc2821 addu a1,a1,gp -10000378: 8ca5802c lw a1,-32724\(a1\) +10000378: 8ca58030 lw a1,-32720\(a1\) 1000037c: 24a5000c addiu a1,a1,12 10000380: 3c050000 lui a1,0x0 10000384: 00bc2821 addu a1,a1,gp -10000388: 8ca5802c lw a1,-32724\(a1\) +10000388: 8ca58030 lw a1,-32720\(a1\) 1000038c: 3c010001 lui at,0x1 10000390: 3421e240 ori at,at,0xe240 10000394: 00a12821 addu a1,a1,at 10000398: 3c050000 lui a1,0x0 1000039c: 00bc2821 addu a1,a1,gp -100003a0: 8ca5802c lw a1,-32724\(a1\) +100003a0: 8ca58030 lw a1,-32720\(a1\) 100003a4: 00b12821 addu a1,a1,s1 100003a8: 3c050000 lui a1,0x0 100003ac: 00bc2821 addu a1,a1,gp -100003b0: 8ca5802c lw a1,-32724\(a1\) +100003b0: 8ca58030 lw a1,-32720\(a1\) 100003b4: 24a5000c addiu a1,a1,12 100003b8: 00b12821 addu a1,a1,s1 100003bc: 3c050000 lui a1,0x0 100003c0: 00bc2821 addu a1,a1,gp -100003c4: 8ca5802c lw a1,-32724\(a1\) +100003c4: 8ca58030 lw a1,-32720\(a1\) 100003c8: 3c010001 lui at,0x1 100003cc: 3421e240 ori at,at,0xe240 100003d0: 00a12821 addu a1,a1,at 100003d4: 00b12821 addu a1,a1,s1 100003d8: 3c050000 lui a1,0x0 100003dc: 00bc2821 addu a1,a1,gp -100003e0: 8ca5802c lw a1,-32724\(a1\) +100003e0: 8ca58030 lw a1,-32720\(a1\) 100003e4: 8ca50000 lw a1,0\(a1\) 100003e8: 3c050000 lui a1,0x0 100003ec: 00bc2821 addu a1,a1,gp -100003f0: 8ca5802c lw a1,-32724\(a1\) +100003f0: 8ca58030 lw a1,-32720\(a1\) 100003f4: 8ca5000c lw a1,12\(a1\) 100003f8: 3c050000 lui a1,0x0 100003fc: 00bc2821 addu a1,a1,gp -10000400: 8ca5802c lw a1,-32724\(a1\) +10000400: 8ca58030 lw a1,-32720\(a1\) 10000404: 00b12821 addu a1,a1,s1 10000408: 8ca50000 lw a1,0\(a1\) 1000040c: 3c050000 lui a1,0x0 10000410: 00bc2821 addu a1,a1,gp -10000414: 8ca5802c lw a1,-32724\(a1\) +10000414: 8ca58030 lw a1,-32720\(a1\) 10000418: 00b12821 addu a1,a1,s1 1000041c: 8ca5000c lw a1,12\(a1\) 10000420: 3c010000 lui at,0x0 10000424: 003c0821 addu at,at,gp -10000428: 8c21802c lw at,-32724\(at\) +10000428: 8c218030 lw at,-32720\(at\) 1000042c: 00250821 addu at,at,a1 10000430: 8c250022 lw a1,34\(at\) 10000434: 3c010000 lui at,0x0 10000438: 003c0821 addu at,at,gp -1000043c: 8c21802c lw at,-32724\(at\) +1000043c: 8c218030 lw at,-32720\(at\) 10000440: 00250821 addu at,at,a1 10000444: ac250038 sw a1,56\(at\) 10000448: 3c010000 lui at,0x0 1000044c: 003c0821 addu at,at,gp -10000450: 8c21802c lw at,-32724\(at\) +10000450: 8c218030 lw at,-32720\(at\) 10000454: 88250000 lwl a1,0\(at\) 10000458: 98250003 lwr a1,3\(at\) 1000045c: 3c010000 lui at,0x0 10000460: 003c0821 addu at,at,gp -10000464: 8c21802c lw at,-32724\(at\) +10000464: 8c218030 lw at,-32720\(at\) 10000468: 2421000c addiu at,at,12 1000046c: 88250000 lwl a1,0\(at\) 10000470: 98250003 lwr a1,3\(at\) 10000474: 3c010000 lui at,0x0 10000478: 003c0821 addu at,at,gp -1000047c: 8c21802c lw at,-32724\(at\) +1000047c: 8c218030 lw at,-32720\(at\) 10000480: 00310821 addu at,at,s1 10000484: 88250000 lwl a1,0\(at\) 10000488: 98250003 lwr a1,3\(at\) 1000048c: 3c010000 lui at,0x0 10000490: 003c0821 addu at,at,gp -10000494: 8c21802c lw at,-32724\(at\) +10000494: 8c218030 lw at,-32720\(at\) 10000498: 2421000c addiu at,at,12 1000049c: 00310821 addu at,at,s1 100004a0: 88250000 lwl a1,0\(at\) 100004a4: 98250003 lwr a1,3\(at\) 100004a8: 3c010000 lui at,0x0 100004ac: 003c0821 addu at,at,gp -100004b0: 8c21802c lw at,-32724\(at\) +100004b0: 8c218030 lw at,-32720\(at\) 100004b4: 24210022 addiu at,at,34 100004b8: 00250821 addu at,at,a1 100004bc: 88250000 lwl a1,0\(at\) 100004c0: 98250003 lwr a1,3\(at\) 100004c4: 3c010000 lui at,0x0 100004c8: 003c0821 addu at,at,gp -100004cc: 8c21802c lw at,-32724\(at\) +100004cc: 8c218030 lw at,-32720\(at\) 100004d0: 24210038 addiu at,at,56 100004d4: 00250821 addu at,at,a1 100004d8: a8250000 swl a1,0\(at\) 100004dc: b8250003 swr a1,3\(at\) -100004e0: 8f85801c lw a1,-32740\(gp\) +100004e0: 8f858018 lw a1,-32744\(gp\) 100004e4: 24a50774 addiu a1,a1,1908 -100004e8: 8f85801c lw a1,-32740\(gp\) +100004e8: 8f858018 lw a1,-32744\(gp\) 100004ec: 24a50780 addiu a1,a1,1920 -100004f0: 8f858020 lw a1,-32736\(gp\) +100004f0: 8f85801c lw a1,-32740\(gp\) 100004f4: 24a5e9b4 addiu a1,a1,-5708 -100004f8: 8f85801c lw a1,-32740\(gp\) +100004f8: 8f858018 lw a1,-32744\(gp\) 100004fc: 24a50774 addiu a1,a1,1908 10000500: 00b12821 addu a1,a1,s1 -10000504: 8f85801c lw a1,-32740\(gp\) +10000504: 8f858018 lw a1,-32744\(gp\) 10000508: 24a50780 addiu a1,a1,1920 1000050c: 00b12821 addu a1,a1,s1 -10000510: 8f858020 lw a1,-32736\(gp\) +10000510: 8f85801c lw a1,-32740\(gp\) 10000514: 24a5e9b4 addiu a1,a1,-5708 10000518: 00b12821 addu a1,a1,s1 -1000051c: 8f85801c lw a1,-32740\(gp\) +1000051c: 8f858018 lw a1,-32744\(gp\) 10000520: 8ca50774 lw a1,1908\(a1\) -10000524: 8f85801c lw a1,-32740\(gp\) +10000524: 8f858018 lw a1,-32744\(gp\) 10000528: 8ca50780 lw a1,1920\(a1\) -1000052c: 8f85801c lw a1,-32740\(gp\) +1000052c: 8f858018 lw a1,-32744\(gp\) 10000530: 00b12821 addu a1,a1,s1 10000534: 8ca50774 lw a1,1908\(a1\) -10000538: 8f85801c lw a1,-32740\(gp\) +10000538: 8f858018 lw a1,-32744\(gp\) 1000053c: 00b12821 addu a1,a1,s1 10000540: 8ca50780 lw a1,1920\(a1\) -10000544: 8f81801c lw at,-32740\(gp\) +10000544: 8f818018 lw at,-32744\(gp\) 10000548: 00250821 addu at,at,a1 1000054c: 8c250796 lw a1,1942\(at\) -10000550: 8f81801c lw at,-32740\(gp\) +10000550: 8f818018 lw at,-32744\(gp\) 10000554: 00250821 addu at,at,a1 10000558: ac2507ac sw a1,1964\(at\) -1000055c: 8f81801c lw at,-32740\(gp\) +1000055c: 8f818018 lw at,-32744\(gp\) 10000560: 24210774 addiu at,at,1908 10000564: 88250000 lwl a1,0\(at\) 10000568: 98250003 lwr a1,3\(at\) -1000056c: 8f81801c lw at,-32740\(gp\) +1000056c: 8f818018 lw at,-32744\(gp\) 10000570: 24210780 addiu at,at,1920 10000574: 88250000 lwl a1,0\(at\) 10000578: 98250003 lwr a1,3\(at\) -1000057c: 8f81801c lw at,-32740\(gp\) +1000057c: 8f818018 lw at,-32744\(gp\) 10000580: 24210774 addiu at,at,1908 10000584: 00310821 addu at,at,s1 10000588: 88250000 lwl a1,0\(at\) 1000058c: 98250003 lwr a1,3\(at\) -10000590: 8f81801c lw at,-32740\(gp\) +10000590: 8f818018 lw at,-32744\(gp\) 10000594: 24210780 addiu at,at,1920 10000598: 00310821 addu at,at,s1 1000059c: 88250000 lwl a1,0\(at\) 100005a0: 98250003 lwr a1,3\(at\) -100005a4: 8f81801c lw at,-32740\(gp\) +100005a4: 8f818018 lw at,-32744\(gp\) 100005a8: 24210796 addiu at,at,1942 100005ac: 00250821 addu at,at,a1 100005b0: 88250000 lwl a1,0\(at\) 100005b4: 98250003 lwr a1,3\(at\) -100005b8: 8f81801c lw at,-32740\(gp\) +100005b8: 8f818018 lw at,-32744\(gp\) 100005bc: 242107ac addiu at,at,1964 100005c0: 00250821 addu at,at,a1 100005c4: a8250000 swl a1,0\(at\) 100005c8: b8250003 swr a1,3\(at\) 100005cc: 3c050000 lui a1,0x0 100005d0: 00bc2821 addu a1,a1,gp -100005d4: 8ca58030 lw a1,-32720\(a1\) -100005d8: 8f858028 lw a1,-32728\(gp\) +100005d4: 8ca5802c lw a1,-32724\(a1\) +100005d8: 8f858020 lw a1,-32736\(gp\) 100005dc: 24a506b0 addiu a1,a1,1712 100005e0: 3c190000 lui t9,0x0 100005e4: 033cc821 addu t9,t9,gp -100005e8: 8f398030 lw t9,-32720\(t9\) -100005ec: 8f998028 lw t9,-32728\(gp\) +100005e8: 8f39802c lw t9,-32724\(t9\) +100005ec: 8f998020 lw t9,-32736\(gp\) 100005f0: 273906b0 addiu t9,t9,1712 100005f4: 3c190000 lui t9,0x0 100005f8: 033cc821 addu t9,t9,gp -100005fc: 8f398030 lw t9,-32720\(t9\) +100005fc: 8f39802c lw t9,-32724\(t9\) 10000600: 0411002b bal 100006b0 <fn2> 10000604: 00000000 nop -10000608: 8f998028 lw t9,-32728\(gp\) +10000608: 8f998020 lw t9,-32736\(gp\) 1000060c: 273906b0 addiu t9,t9,1712 10000610: 04110027 bal 100006b0 <fn2> 10000614: 00000000 nop 10000618: 3c050000 lui a1,0x0 1000061c: 00bc2821 addu a1,a1,gp -10000620: 8ca58018 lw a1,-32744\(a1\) +10000620: 8ca58038 lw a1,-32712\(a1\) 10000624: 1000fea2 b 100000b0 <fn> 10000628: 00000000 nop 1000062c: 3c050000 lui a1,0x0 10000630: 00bc2821 addu a1,a1,gp -10000634: 8ca5802c lw a1,-32724\(a1\) +10000634: 8ca58030 lw a1,-32720\(a1\) 10000638: 8ca50000 lw a1,0\(a1\) 1000063c: 1000001c b 100006b0 <fn2> 10000640: 00000000 nop -10000644: 8f85801c lw a1,-32740\(gp\) +10000644: 8f858018 lw a1,-32744\(gp\) 10000648: 24a506fc addiu a1,a1,1788 1000064c: 1000fe98 b 100000b0 <fn> 10000650: 00000000 nop -10000654: 8f85801c lw a1,-32740\(gp\) +10000654: 8f858018 lw a1,-32744\(gp\) 10000658: 24a50780 addiu a1,a1,1920 1000065c: 10000014 b 100006b0 <fn2> 10000660: 00000000 nop -10000664: 8f858020 lw a1,-32736\(gp\) +10000664: 8f85801c lw a1,-32740\(gp\) 10000668: 24a5e93c addiu a1,a1,-5828 1000066c: 1000fe90 b 100000b0 <fn> 10000670: 00000000 nop -10000674: 8f85801c lw a1,-32740\(gp\) +10000674: 8f858018 lw a1,-32744\(gp\) 10000678: 8ca50774 lw a1,1908\(a1\) 1000067c: 1000000c b 100006b0 <fn2> 10000680: 00000000 nop -10000684: 8f85801c lw a1,-32740\(gp\) +10000684: 8f858018 lw a1,-32744\(gp\) 10000688: 8ca50708 lw a1,1800\(a1\) 1000068c: 1000fe88 b 100000b0 <fn> 10000690: 00000000 nop -10000694: 8f81801c lw at,-32740\(gp\) +10000694: 8f818018 lw at,-32744\(gp\) 10000698: 00250821 addu at,at,a1 1000069c: 8c250796 lw a1,1942\(at\) 100006a0: 10000003 b 100006b0 <fn2> @@ -422,13 +423,13 @@ Disassembly of section \.got: 100107b0 <_GLOBAL_OFFSET_TABLE_>: 100107b0: 00000000 .* 100107b4: 80000000 .* -100107b8: 100106fc .* -100107bc: 10010000 .* -100107c0: 10030000 .* -100107c4: 100000b0 .* -100107c8: 10000000 .* -100107cc: 10010774 .* -100107d0: 100006b0 .* -100107d4: 00000000 .* -100107d8: 00000000 .* +100107b8: 10010000 .* +100107bc: 10030000 .* +100107c0: 10000000 .* +100107c4: 00000000 .* +100107c8: 00000000 .* +100107cc: 100006b0 .* +100107d0: 10010774 .* +100107d4: 100000b0 .* +100107d8: 100106fc .* #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d index 6da691c..bdacf78 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d @@ -1,6 +1,7 @@ #name: MIPS ELF xgot reloc n64 #as: -march=from-abi -EB -64 -KPIC -xgot -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn @@ -21,382 +22,382 @@ Disassembly of section \.text: 00000001200000b0 <fn>: 1200000b0: 3c050000 lui a1,0x0 1200000b4: 00bc282d daddu a1,a1,gp - 1200000b8: dca58020 ld a1,-32736\(a1\) + 1200000b8: dca58060 ld a1,-32672\(a1\) 1200000bc: 3c050000 lui a1,0x0 1200000c0: 00bc282d daddu a1,a1,gp - 1200000c4: dca58020 ld a1,-32736\(a1\) + 1200000c4: dca58060 ld a1,-32672\(a1\) 1200000c8: 64a5000c daddiu a1,a1,12 1200000cc: 3c050000 lui a1,0x0 1200000d0: 00bc282d daddu a1,a1,gp - 1200000d4: dca58020 ld a1,-32736\(a1\) + 1200000d4: dca58060 ld a1,-32672\(a1\) 1200000d8: 3c010001 lui at,0x1 1200000dc: 3421e240 ori at,at,0xe240 1200000e0: 00a1282d daddu a1,a1,at 1200000e4: 3c050000 lui a1,0x0 1200000e8: 00bc282d daddu a1,a1,gp - 1200000ec: dca58020 ld a1,-32736\(a1\) + 1200000ec: dca58060 ld a1,-32672\(a1\) 1200000f0: 00b1282d daddu a1,a1,s1 1200000f4: 3c050000 lui a1,0x0 1200000f8: 00bc282d daddu a1,a1,gp - 1200000fc: dca58020 ld a1,-32736\(a1\) + 1200000fc: dca58060 ld a1,-32672\(a1\) 120000100: 64a5000c daddiu a1,a1,12 120000104: 00b1282d daddu a1,a1,s1 120000108: 3c050000 lui a1,0x0 12000010c: 00bc282d daddu a1,a1,gp - 120000110: dca58020 ld a1,-32736\(a1\) + 120000110: dca58060 ld a1,-32672\(a1\) 120000114: 3c010001 lui at,0x1 120000118: 3421e240 ori at,at,0xe240 12000011c: 00a1282d daddu a1,a1,at 120000120: 00b1282d daddu a1,a1,s1 120000124: 3c050000 lui a1,0x0 120000128: 00bc282d daddu a1,a1,gp - 12000012c: dca58020 ld a1,-32736\(a1\) + 12000012c: dca58060 ld a1,-32672\(a1\) 120000130: dca50000 ld a1,0\(a1\) 120000134: 3c050000 lui a1,0x0 120000138: 00bc282d daddu a1,a1,gp - 12000013c: dca58020 ld a1,-32736\(a1\) + 12000013c: dca58060 ld a1,-32672\(a1\) 120000140: dca5000c ld a1,12\(a1\) 120000144: 3c050000 lui a1,0x0 120000148: 00bc282d daddu a1,a1,gp - 12000014c: dca58020 ld a1,-32736\(a1\) + 12000014c: dca58060 ld a1,-32672\(a1\) 120000150: 00b1282d daddu a1,a1,s1 120000154: dca50000 ld a1,0\(a1\) 120000158: 3c050000 lui a1,0x0 12000015c: 00bc282d daddu a1,a1,gp - 120000160: dca58020 ld a1,-32736\(a1\) + 120000160: dca58060 ld a1,-32672\(a1\) 120000164: 00b1282d daddu a1,a1,s1 120000168: dca5000c ld a1,12\(a1\) 12000016c: 3c010000 lui at,0x0 120000170: 003c082d daddu at,at,gp - 120000174: dc218020 ld at,-32736\(at\) + 120000174: dc218060 ld at,-32672\(at\) 120000178: 0025082d daddu at,at,a1 12000017c: dc250022 ld a1,34\(at\) 120000180: 3c010000 lui at,0x0 120000184: 003c082d daddu at,at,gp - 120000188: dc218020 ld at,-32736\(at\) + 120000188: dc218060 ld at,-32672\(at\) 12000018c: 0025082d daddu at,at,a1 120000190: fc250038 sd a1,56\(at\) 120000194: 3c010000 lui at,0x0 120000198: 003c082d daddu at,at,gp - 12000019c: dc218020 ld at,-32736\(at\) + 12000019c: dc218060 ld at,-32672\(at\) 1200001a0: 88250000 lwl a1,0\(at\) 1200001a4: 98250003 lwr a1,3\(at\) 1200001a8: 3c010000 lui at,0x0 1200001ac: 003c082d daddu at,at,gp - 1200001b0: dc218020 ld at,-32736\(at\) + 1200001b0: dc218060 ld at,-32672\(at\) 1200001b4: 6421000c daddiu at,at,12 1200001b8: 88250000 lwl a1,0\(at\) 1200001bc: 98250003 lwr a1,3\(at\) 1200001c0: 3c010000 lui at,0x0 1200001c4: 003c082d daddu at,at,gp - 1200001c8: dc218020 ld at,-32736\(at\) + 1200001c8: dc218060 ld at,-32672\(at\) 1200001cc: 0031082d daddu at,at,s1 1200001d0: 88250000 lwl a1,0\(at\) 1200001d4: 98250003 lwr a1,3\(at\) 1200001d8: 3c010000 lui at,0x0 1200001dc: 003c082d daddu at,at,gp - 1200001e0: dc218020 ld at,-32736\(at\) + 1200001e0: dc218060 ld at,-32672\(at\) 1200001e4: 6421000c daddiu at,at,12 1200001e8: 0031082d daddu at,at,s1 1200001ec: 88250000 lwl a1,0\(at\) 1200001f0: 98250003 lwr a1,3\(at\) 1200001f4: 3c010000 lui at,0x0 1200001f8: 003c082d daddu at,at,gp - 1200001fc: dc218020 ld at,-32736\(at\) + 1200001fc: dc218060 ld at,-32672\(at\) 120000200: 64210022 daddiu at,at,34 120000204: 0025082d daddu at,at,a1 120000208: 88250000 lwl a1,0\(at\) 12000020c: 98250003 lwr a1,3\(at\) 120000210: 3c010000 lui at,0x0 120000214: 003c082d daddu at,at,gp - 120000218: dc218020 ld at,-32736\(at\) + 120000218: dc218060 ld at,-32672\(at\) 12000021c: 64210038 daddiu at,at,56 120000220: 0025082d daddu at,at,a1 120000224: a8250000 swl a1,0\(at\) 120000228: b8250003 swr a1,3\(at\) - 12000022c: df858028 ld a1,-32728\(gp\) + 12000022c: df858020 ld a1,-32736\(gp\) 120000230: 64a506f4 daddiu a1,a1,1780 - 120000234: df858028 ld a1,-32728\(gp\) + 120000234: df858020 ld a1,-32736\(gp\) 120000238: 64a50700 daddiu a1,a1,1792 - 12000023c: df858030 ld a1,-32720\(gp\) + 12000023c: df858028 ld a1,-32728\(gp\) 120000240: 64a5e934 daddiu a1,a1,-5836 - 120000244: df858028 ld a1,-32728\(gp\) + 120000244: df858020 ld a1,-32736\(gp\) 120000248: 64a506f4 daddiu a1,a1,1780 12000024c: 00b1282d daddu a1,a1,s1 - 120000250: df858028 ld a1,-32728\(gp\) + 120000250: df858020 ld a1,-32736\(gp\) 120000254: 64a50700 daddiu a1,a1,1792 120000258: 00b1282d daddu a1,a1,s1 - 12000025c: df858030 ld a1,-32720\(gp\) + 12000025c: df858028 ld a1,-32728\(gp\) 120000260: 64a5e934 daddiu a1,a1,-5836 120000264: 00b1282d daddu a1,a1,s1 - 120000268: df858028 ld a1,-32728\(gp\) + 120000268: df858020 ld a1,-32736\(gp\) 12000026c: dca506f4 ld a1,1780\(a1\) - 120000270: df858028 ld a1,-32728\(gp\) + 120000270: df858020 ld a1,-32736\(gp\) 120000274: dca50700 ld a1,1792\(a1\) - 120000278: df858028 ld a1,-32728\(gp\) + 120000278: df858020 ld a1,-32736\(gp\) 12000027c: 00b1282d daddu a1,a1,s1 120000280: dca506f4 ld a1,1780\(a1\) - 120000284: df858028 ld a1,-32728\(gp\) + 120000284: df858020 ld a1,-32736\(gp\) 120000288: 00b1282d daddu a1,a1,s1 12000028c: dca50700 ld a1,1792\(a1\) - 120000290: df818028 ld at,-32728\(gp\) + 120000290: df818020 ld at,-32736\(gp\) 120000294: 0025082d daddu at,at,a1 120000298: dc250716 ld a1,1814\(at\) - 12000029c: df818028 ld at,-32728\(gp\) + 12000029c: df818020 ld at,-32736\(gp\) 1200002a0: 0025082d daddu at,at,a1 1200002a4: fc25072c sd a1,1836\(at\) - 1200002a8: df818028 ld at,-32728\(gp\) + 1200002a8: df818020 ld at,-32736\(gp\) 1200002ac: 642106f4 daddiu at,at,1780 1200002b0: 88250000 lwl a1,0\(at\) 1200002b4: 98250003 lwr a1,3\(at\) - 1200002b8: df818028 ld at,-32728\(gp\) + 1200002b8: df818020 ld at,-32736\(gp\) 1200002bc: 64210700 daddiu at,at,1792 1200002c0: 88250000 lwl a1,0\(at\) 1200002c4: 98250003 lwr a1,3\(at\) - 1200002c8: df818028 ld at,-32728\(gp\) + 1200002c8: df818020 ld at,-32736\(gp\) 1200002cc: 642106f4 daddiu at,at,1780 1200002d0: 0031082d daddu at,at,s1 1200002d4: 88250000 lwl a1,0\(at\) 1200002d8: 98250003 lwr a1,3\(at\) - 1200002dc: df818028 ld at,-32728\(gp\) + 1200002dc: df818020 ld at,-32736\(gp\) 1200002e0: 64210700 daddiu at,at,1792 1200002e4: 0031082d daddu at,at,s1 1200002e8: 88250000 lwl a1,0\(at\) 1200002ec: 98250003 lwr a1,3\(at\) - 1200002f0: df818028 ld at,-32728\(gp\) + 1200002f0: df818020 ld at,-32736\(gp\) 1200002f4: 64210716 daddiu at,at,1814 1200002f8: 0025082d daddu at,at,a1 1200002fc: 88250000 lwl a1,0\(at\) 120000300: 98250003 lwr a1,3\(at\) - 120000304: df818028 ld at,-32728\(gp\) + 120000304: df818020 ld at,-32736\(gp\) 120000308: 6421072c daddiu at,at,1836 12000030c: 0025082d daddu at,at,a1 120000310: a8250000 swl a1,0\(at\) 120000314: b8250003 swr a1,3\(at\) 120000318: 3c050000 lui a1,0x0 12000031c: 00bc282d daddu a1,a1,gp - 120000320: dca58038 ld a1,-32712\(a1\) - 120000324: df858040 ld a1,-32704\(gp\) + 120000320: dca58058 ld a1,-32680\(a1\) + 120000324: df858030 ld a1,-32720\(gp\) 120000328: 64a500b0 daddiu a1,a1,176 12000032c: 3c190000 lui t9,0x0 120000330: 033cc82d daddu t9,t9,gp - 120000334: df398038 ld t9,-32712\(t9\) - 120000338: df998040 ld t9,-32704\(gp\) + 120000334: df398058 ld t9,-32680\(t9\) + 120000338: df998030 ld t9,-32720\(gp\) 12000033c: 673900b0 daddiu t9,t9,176 120000340: 3c190000 lui t9,0x0 120000344: 033cc82d daddu t9,t9,gp - 120000348: df398038 ld t9,-32712\(t9\) + 120000348: df398058 ld t9,-32680\(t9\) 12000034c: 0411ff58 bal 1200000b0 <fn> 120000350: 00000000 nop - 120000354: df998040 ld t9,-32704\(gp\) + 120000354: df998030 ld t9,-32720\(gp\) 120000358: 673900b0 daddiu t9,t9,176 12000035c: 0411ff54 bal 1200000b0 <fn> 120000360: 00000000 nop 120000364: 3c050000 lui a1,0x0 120000368: 00bc282d daddu a1,a1,gp - 12000036c: dca58048 ld a1,-32696\(a1\) + 12000036c: dca58050 ld a1,-32688\(a1\) 120000370: 3c050000 lui a1,0x0 120000374: 00bc282d daddu a1,a1,gp - 120000378: dca58048 ld a1,-32696\(a1\) + 120000378: dca58050 ld a1,-32688\(a1\) 12000037c: 64a5000c daddiu a1,a1,12 120000380: 3c050000 lui a1,0x0 120000384: 00bc282d daddu a1,a1,gp - 120000388: dca58048 ld a1,-32696\(a1\) + 120000388: dca58050 ld a1,-32688\(a1\) 12000038c: 3c010001 lui at,0x1 120000390: 3421e240 ori at,at,0xe240 120000394: 00a1282d daddu a1,a1,at 120000398: 3c050000 lui a1,0x0 12000039c: 00bc282d daddu a1,a1,gp - 1200003a0: dca58048 ld a1,-32696\(a1\) + 1200003a0: dca58050 ld a1,-32688\(a1\) 1200003a4: 00b1282d daddu a1,a1,s1 1200003a8: 3c050000 lui a1,0x0 1200003ac: 00bc282d daddu a1,a1,gp - 1200003b0: dca58048 ld a1,-32696\(a1\) + 1200003b0: dca58050 ld a1,-32688\(a1\) 1200003b4: 64a5000c daddiu a1,a1,12 1200003b8: 00b1282d daddu a1,a1,s1 1200003bc: 3c050000 lui a1,0x0 1200003c0: 00bc282d daddu a1,a1,gp - 1200003c4: dca58048 ld a1,-32696\(a1\) + 1200003c4: dca58050 ld a1,-32688\(a1\) 1200003c8: 3c010001 lui at,0x1 1200003cc: 3421e240 ori at,at,0xe240 1200003d0: 00a1282d daddu a1,a1,at 1200003d4: 00b1282d daddu a1,a1,s1 1200003d8: 3c050000 lui a1,0x0 1200003dc: 00bc282d daddu a1,a1,gp - 1200003e0: dca58048 ld a1,-32696\(a1\) + 1200003e0: dca58050 ld a1,-32688\(a1\) 1200003e4: dca50000 ld a1,0\(a1\) 1200003e8: 3c050000 lui a1,0x0 1200003ec: 00bc282d daddu a1,a1,gp - 1200003f0: dca58048 ld a1,-32696\(a1\) + 1200003f0: dca58050 ld a1,-32688\(a1\) 1200003f4: dca5000c ld a1,12\(a1\) 1200003f8: 3c050000 lui a1,0x0 1200003fc: 00bc282d daddu a1,a1,gp - 120000400: dca58048 ld a1,-32696\(a1\) + 120000400: dca58050 ld a1,-32688\(a1\) 120000404: 00b1282d daddu a1,a1,s1 120000408: dca50000 ld a1,0\(a1\) 12000040c: 3c050000 lui a1,0x0 120000410: 00bc282d daddu a1,a1,gp - 120000414: dca58048 ld a1,-32696\(a1\) + 120000414: dca58050 ld a1,-32688\(a1\) 120000418: 00b1282d daddu a1,a1,s1 12000041c: dca5000c ld a1,12\(a1\) 120000420: 3c010000 lui at,0x0 120000424: 003c082d daddu at,at,gp - 120000428: dc218048 ld at,-32696\(at\) + 120000428: dc218050 ld at,-32688\(at\) 12000042c: 0025082d daddu at,at,a1 120000430: dc250022 ld a1,34\(at\) 120000434: 3c010000 lui at,0x0 120000438: 003c082d daddu at,at,gp - 12000043c: dc218048 ld at,-32696\(at\) + 12000043c: dc218050 ld at,-32688\(at\) 120000440: 0025082d daddu at,at,a1 120000444: fc250038 sd a1,56\(at\) 120000448: 3c010000 lui at,0x0 12000044c: 003c082d daddu at,at,gp - 120000450: dc218048 ld at,-32696\(at\) + 120000450: dc218050 ld at,-32688\(at\) 120000454: 88250000 lwl a1,0\(at\) 120000458: 98250003 lwr a1,3\(at\) 12000045c: 3c010000 lui at,0x0 120000460: 003c082d daddu at,at,gp - 120000464: dc218048 ld at,-32696\(at\) + 120000464: dc218050 ld at,-32688\(at\) 120000468: 6421000c daddiu at,at,12 12000046c: 88250000 lwl a1,0\(at\) 120000470: 98250003 lwr a1,3\(at\) 120000474: 3c010000 lui at,0x0 120000478: 003c082d daddu at,at,gp - 12000047c: dc218048 ld at,-32696\(at\) + 12000047c: dc218050 ld at,-32688\(at\) 120000480: 0031082d daddu at,at,s1 120000484: 88250000 lwl a1,0\(at\) 120000488: 98250003 lwr a1,3\(at\) 12000048c: 3c010000 lui at,0x0 120000490: 003c082d daddu at,at,gp - 120000494: dc218048 ld at,-32696\(at\) + 120000494: dc218050 ld at,-32688\(at\) 120000498: 6421000c daddiu at,at,12 12000049c: 0031082d daddu at,at,s1 1200004a0: 88250000 lwl a1,0\(at\) 1200004a4: 98250003 lwr a1,3\(at\) 1200004a8: 3c010000 lui at,0x0 1200004ac: 003c082d daddu at,at,gp - 1200004b0: dc218048 ld at,-32696\(at\) + 1200004b0: dc218050 ld at,-32688\(at\) 1200004b4: 64210022 daddiu at,at,34 1200004b8: 0025082d daddu at,at,a1 1200004bc: 88250000 lwl a1,0\(at\) 1200004c0: 98250003 lwr a1,3\(at\) 1200004c4: 3c010000 lui at,0x0 1200004c8: 003c082d daddu at,at,gp - 1200004cc: dc218048 ld at,-32696\(at\) + 1200004cc: dc218050 ld at,-32688\(at\) 1200004d0: 64210038 daddiu at,at,56 1200004d4: 0025082d daddu at,at,a1 1200004d8: a8250000 swl a1,0\(at\) 1200004dc: b8250003 swr a1,3\(at\) - 1200004e0: df858028 ld a1,-32728\(gp\) + 1200004e0: df858020 ld a1,-32736\(gp\) 1200004e4: 64a5076c daddiu a1,a1,1900 - 1200004e8: df858028 ld a1,-32728\(gp\) + 1200004e8: df858020 ld a1,-32736\(gp\) 1200004ec: 64a50778 daddiu a1,a1,1912 - 1200004f0: df858030 ld a1,-32720\(gp\) + 1200004f0: df858028 ld a1,-32728\(gp\) 1200004f4: 64a5e9ac daddiu a1,a1,-5716 - 1200004f8: df858028 ld a1,-32728\(gp\) + 1200004f8: df858020 ld a1,-32736\(gp\) 1200004fc: 64a5076c daddiu a1,a1,1900 120000500: 00b1282d daddu a1,a1,s1 - 120000504: df858028 ld a1,-32728\(gp\) + 120000504: df858020 ld a1,-32736\(gp\) 120000508: 64a50778 daddiu a1,a1,1912 12000050c: 00b1282d daddu a1,a1,s1 - 120000510: df858030 ld a1,-32720\(gp\) + 120000510: df858028 ld a1,-32728\(gp\) 120000514: 64a5e9ac daddiu a1,a1,-5716 120000518: 00b1282d daddu a1,a1,s1 - 12000051c: df858028 ld a1,-32728\(gp\) + 12000051c: df858020 ld a1,-32736\(gp\) 120000520: dca5076c ld a1,1900\(a1\) - 120000524: df858028 ld a1,-32728\(gp\) + 120000524: df858020 ld a1,-32736\(gp\) 120000528: dca50778 ld a1,1912\(a1\) - 12000052c: df858028 ld a1,-32728\(gp\) + 12000052c: df858020 ld a1,-32736\(gp\) 120000530: 00b1282d daddu a1,a1,s1 120000534: dca5076c ld a1,1900\(a1\) - 120000538: df858028 ld a1,-32728\(gp\) + 120000538: df858020 ld a1,-32736\(gp\) 12000053c: 00b1282d daddu a1,a1,s1 120000540: dca50778 ld a1,1912\(a1\) - 120000544: df818028 ld at,-32728\(gp\) + 120000544: df818020 ld at,-32736\(gp\) 120000548: 0025082d daddu at,at,a1 12000054c: dc25078e ld a1,1934\(at\) - 120000550: df818028 ld at,-32728\(gp\) + 120000550: df818020 ld at,-32736\(gp\) 120000554: 0025082d daddu at,at,a1 120000558: fc2507a4 sd a1,1956\(at\) - 12000055c: df818028 ld at,-32728\(gp\) + 12000055c: df818020 ld at,-32736\(gp\) 120000560: 6421076c daddiu at,at,1900 120000564: 88250000 lwl a1,0\(at\) 120000568: 98250003 lwr a1,3\(at\) - 12000056c: df818028 ld at,-32728\(gp\) + 12000056c: df818020 ld at,-32736\(gp\) 120000570: 64210778 daddiu at,at,1912 120000574: 88250000 lwl a1,0\(at\) 120000578: 98250003 lwr a1,3\(at\) - 12000057c: df818028 ld at,-32728\(gp\) + 12000057c: df818020 ld at,-32736\(gp\) 120000580: 6421076c daddiu at,at,1900 120000584: 0031082d daddu at,at,s1 120000588: 88250000 lwl a1,0\(at\) 12000058c: 98250003 lwr a1,3\(at\) - 120000590: df818028 ld at,-32728\(gp\) + 120000590: df818020 ld at,-32736\(gp\) 120000594: 64210778 daddiu at,at,1912 120000598: 0031082d daddu at,at,s1 12000059c: 88250000 lwl a1,0\(at\) 1200005a0: 98250003 lwr a1,3\(at\) - 1200005a4: df818028 ld at,-32728\(gp\) + 1200005a4: df818020 ld at,-32736\(gp\) 1200005a8: 6421078e daddiu at,at,1934 1200005ac: 0025082d daddu at,at,a1 1200005b0: 88250000 lwl a1,0\(at\) 1200005b4: 98250003 lwr a1,3\(at\) - 1200005b8: df818028 ld at,-32728\(gp\) + 1200005b8: df818020 ld at,-32736\(gp\) 1200005bc: 642107a4 daddiu at,at,1956 1200005c0: 0025082d daddu at,at,a1 1200005c4: a8250000 swl a1,0\(at\) 1200005c8: b8250003 swr a1,3\(at\) 1200005cc: 3c050000 lui a1,0x0 1200005d0: 00bc282d daddu a1,a1,gp - 1200005d4: dca58050 ld a1,-32688\(a1\) - 1200005d8: df858040 ld a1,-32704\(gp\) + 1200005d4: dca58048 ld a1,-32696\(a1\) + 1200005d8: df858030 ld a1,-32720\(gp\) 1200005dc: 64a506b0 daddiu a1,a1,1712 1200005e0: 3c190000 lui t9,0x0 1200005e4: 033cc82d daddu t9,t9,gp - 1200005e8: df398050 ld t9,-32688\(t9\) - 1200005ec: df998040 ld t9,-32704\(gp\) + 1200005e8: df398048 ld t9,-32696\(t9\) + 1200005ec: df998030 ld t9,-32720\(gp\) 1200005f0: 673906b0 daddiu t9,t9,1712 1200005f4: 3c190000 lui t9,0x0 1200005f8: 033cc82d daddu t9,t9,gp - 1200005fc: df398050 ld t9,-32688\(t9\) + 1200005fc: df398048 ld t9,-32696\(t9\) 120000600: 0411002b bal 1200006b0 <fn2> 120000604: 00000000 nop - 120000608: df998040 ld t9,-32704\(gp\) + 120000608: df998030 ld t9,-32720\(gp\) 12000060c: 673906b0 daddiu t9,t9,1712 120000610: 04110027 bal 1200006b0 <fn2> 120000614: 00000000 nop 120000618: 3c050000 lui a1,0x0 12000061c: 00bc282d daddu a1,a1,gp - 120000620: dca58020 ld a1,-32736\(a1\) + 120000620: dca58060 ld a1,-32672\(a1\) 120000624: 1000fea2 b 1200000b0 <fn> 120000628: 00000000 nop 12000062c: 3c050000 lui a1,0x0 120000630: 00bc282d daddu a1,a1,gp - 120000634: dca58048 ld a1,-32696\(a1\) + 120000634: dca58050 ld a1,-32688\(a1\) 120000638: dca50000 ld a1,0\(a1\) 12000063c: 1000001c b 1200006b0 <fn2> 120000640: 00000000 nop - 120000644: df858028 ld a1,-32728\(gp\) + 120000644: df858020 ld a1,-32736\(gp\) 120000648: 64a506f4 daddiu a1,a1,1780 12000064c: 1000fe98 b 1200000b0 <fn> 120000650: 00000000 nop - 120000654: df858028 ld a1,-32728\(gp\) + 120000654: df858020 ld a1,-32736\(gp\) 120000658: 64a50778 daddiu a1,a1,1912 12000065c: 10000014 b 1200006b0 <fn2> 120000660: 00000000 nop - 120000664: df858030 ld a1,-32720\(gp\) + 120000664: df858028 ld a1,-32728\(gp\) 120000668: 64a5e934 daddiu a1,a1,-5836 12000066c: 1000fe90 b 1200000b0 <fn> 120000670: 00000000 nop - 120000674: df858028 ld a1,-32728\(gp\) + 120000674: df858020 ld a1,-32736\(gp\) 120000678: dca5076c ld a1,1900\(a1\) 12000067c: 1000000c b 1200006b0 <fn2> 120000680: 00000000 nop - 120000684: df858028 ld a1,-32728\(gp\) + 120000684: df858020 ld a1,-32736\(gp\) 120000688: dca50700 ld a1,1792\(a1\) 12000068c: 1000fe88 b 1200000b0 <fn> 120000690: 00000000 nop - 120000694: df818028 ld at,-32728\(gp\) + 120000694: df818020 ld at,-32736\(gp\) 120000698: 0025082d daddu at,at,a1 12000069c: dc25078e ld a1,1934\(at\) 1200006a0: 10000003 b 1200006b0 <fn2> @@ -427,18 +428,18 @@ Disassembly of section \.got: 1200107b8: 80000000 .* 1200107bc: 00000000 .* 1200107c0: 00000001 .* - 1200107c4: 200106f4 .* + 1200107c4: 20010000 .* 1200107c8: 00000001 .* - 1200107cc: 20010000 .* + 1200107cc: 20030000 .* 1200107d0: 00000001 .* - 1200107d4: 20030000 .* - 1200107d8: 00000001 .* - 1200107dc: 200000b0 .* - 1200107e0: 00000001 .* - 1200107e4: 20000000 .* + 1200107d4: 20000000 .* + \.\.\. 1200107e8: 00000001 .* - 1200107ec: 2001076c .* + 1200107ec: 200006b0 .* 1200107f0: 00000001 .* - 1200107f4: 200006b0 .* - \.\.\. + 1200107f4: 2001076c .* + 1200107f8: 00000001 .* + 1200107fc: 200000b0 .* + 120010800: 00000001 .* + 120010804: 200106f4 .* #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d index be446f0..fd21487 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d @@ -1,6 +1,7 @@ #name: MIPS ELF xgot reloc n64 #as: -march=from-abi -EB -64 -KPIC -xgot -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn @@ -21,382 +22,382 @@ Disassembly of section \.text: 00000001200000e0 <fn>: 1200000e0: 3c050000 lui a1,0x0 1200000e4: 00bc282d daddu a1,a1,gp - 1200000e8: dca58020 ld a1,-32736\(a1\) + 1200000e8: dca58060 ld a1,-32672\(a1\) 1200000ec: 3c050000 lui a1,0x0 1200000f0: 00bc282d daddu a1,a1,gp - 1200000f4: dca58020 ld a1,-32736\(a1\) + 1200000f4: dca58060 ld a1,-32672\(a1\) 1200000f8: 64a5000c daddiu a1,a1,12 1200000fc: 3c050000 lui a1,0x0 120000100: 00bc282d daddu a1,a1,gp - 120000104: dca58020 ld a1,-32736\(a1\) + 120000104: dca58060 ld a1,-32672\(a1\) 120000108: 3c010001 lui at,0x1 12000010c: 3421e240 ori at,at,0xe240 120000110: 00a1282d daddu a1,a1,at 120000114: 3c050000 lui a1,0x0 120000118: 00bc282d daddu a1,a1,gp - 12000011c: dca58020 ld a1,-32736\(a1\) + 12000011c: dca58060 ld a1,-32672\(a1\) 120000120: 00b1282d daddu a1,a1,s1 120000124: 3c050000 lui a1,0x0 120000128: 00bc282d daddu a1,a1,gp - 12000012c: dca58020 ld a1,-32736\(a1\) + 12000012c: dca58060 ld a1,-32672\(a1\) 120000130: 64a5000c daddiu a1,a1,12 120000134: 00b1282d daddu a1,a1,s1 120000138: 3c050000 lui a1,0x0 12000013c: 00bc282d daddu a1,a1,gp - 120000140: dca58020 ld a1,-32736\(a1\) + 120000140: dca58060 ld a1,-32672\(a1\) 120000144: 3c010001 lui at,0x1 120000148: 3421e240 ori at,at,0xe240 12000014c: 00a1282d daddu a1,a1,at 120000150: 00b1282d daddu a1,a1,s1 120000154: 3c050000 lui a1,0x0 120000158: 00bc282d daddu a1,a1,gp - 12000015c: dca58020 ld a1,-32736\(a1\) + 12000015c: dca58060 ld a1,-32672\(a1\) 120000160: dca50000 ld a1,0\(a1\) 120000164: 3c050000 lui a1,0x0 120000168: 00bc282d daddu a1,a1,gp - 12000016c: dca58020 ld a1,-32736\(a1\) + 12000016c: dca58060 ld a1,-32672\(a1\) 120000170: dca5000c ld a1,12\(a1\) 120000174: 3c050000 lui a1,0x0 120000178: 00bc282d daddu a1,a1,gp - 12000017c: dca58020 ld a1,-32736\(a1\) + 12000017c: dca58060 ld a1,-32672\(a1\) 120000180: 00b1282d daddu a1,a1,s1 120000184: dca50000 ld a1,0\(a1\) 120000188: 3c050000 lui a1,0x0 12000018c: 00bc282d daddu a1,a1,gp - 120000190: dca58020 ld a1,-32736\(a1\) + 120000190: dca58060 ld a1,-32672\(a1\) 120000194: 00b1282d daddu a1,a1,s1 120000198: dca5000c ld a1,12\(a1\) 12000019c: 3c010000 lui at,0x0 1200001a0: 003c082d daddu at,at,gp - 1200001a4: dc218020 ld at,-32736\(at\) + 1200001a4: dc218060 ld at,-32672\(at\) 1200001a8: 0025082d daddu at,at,a1 1200001ac: dc250022 ld a1,34\(at\) 1200001b0: 3c010000 lui at,0x0 1200001b4: 003c082d daddu at,at,gp - 1200001b8: dc218020 ld at,-32736\(at\) + 1200001b8: dc218060 ld at,-32672\(at\) 1200001bc: 0025082d daddu at,at,a1 1200001c0: fc250038 sd a1,56\(at\) 1200001c4: 3c010000 lui at,0x0 1200001c8: 003c082d daddu at,at,gp - 1200001cc: dc218020 ld at,-32736\(at\) + 1200001cc: dc218060 ld at,-32672\(at\) 1200001d0: 88250000 lwl a1,0\(at\) 1200001d4: 98250003 lwr a1,3\(at\) 1200001d8: 3c010000 lui at,0x0 1200001dc: 003c082d daddu at,at,gp - 1200001e0: dc218020 ld at,-32736\(at\) + 1200001e0: dc218060 ld at,-32672\(at\) 1200001e4: 6421000c daddiu at,at,12 1200001e8: 88250000 lwl a1,0\(at\) 1200001ec: 98250003 lwr a1,3\(at\) 1200001f0: 3c010000 lui at,0x0 1200001f4: 003c082d daddu at,at,gp - 1200001f8: dc218020 ld at,-32736\(at\) + 1200001f8: dc218060 ld at,-32672\(at\) 1200001fc: 0031082d daddu at,at,s1 120000200: 88250000 lwl a1,0\(at\) 120000204: 98250003 lwr a1,3\(at\) 120000208: 3c010000 lui at,0x0 12000020c: 003c082d daddu at,at,gp - 120000210: dc218020 ld at,-32736\(at\) + 120000210: dc218060 ld at,-32672\(at\) 120000214: 6421000c daddiu at,at,12 120000218: 0031082d daddu at,at,s1 12000021c: 88250000 lwl a1,0\(at\) 120000220: 98250003 lwr a1,3\(at\) 120000224: 3c010000 lui at,0x0 120000228: 003c082d daddu at,at,gp - 12000022c: dc218020 ld at,-32736\(at\) + 12000022c: dc218060 ld at,-32672\(at\) 120000230: 64210022 daddiu at,at,34 120000234: 0025082d daddu at,at,a1 120000238: 88250000 lwl a1,0\(at\) 12000023c: 98250003 lwr a1,3\(at\) 120000240: 3c010000 lui at,0x0 120000244: 003c082d daddu at,at,gp - 120000248: dc218020 ld at,-32736\(at\) + 120000248: dc218060 ld at,-32672\(at\) 12000024c: 64210038 daddiu at,at,56 120000250: 0025082d daddu at,at,a1 120000254: a8250000 swl a1,0\(at\) 120000258: b8250003 swr a1,3\(at\) - 12000025c: df858028 ld a1,-32728\(gp\) + 12000025c: df858020 ld a1,-32736\(gp\) 120000260: 64a5072c daddiu a1,a1,1836 - 120000264: df858028 ld a1,-32728\(gp\) + 120000264: df858020 ld a1,-32736\(gp\) 120000268: 64a50738 daddiu a1,a1,1848 - 12000026c: df858030 ld a1,-32720\(gp\) + 12000026c: df858028 ld a1,-32728\(gp\) 120000270: 64a5e96c daddiu a1,a1,-5780 - 120000274: df858028 ld a1,-32728\(gp\) + 120000274: df858020 ld a1,-32736\(gp\) 120000278: 64a5072c daddiu a1,a1,1836 12000027c: 00b1282d daddu a1,a1,s1 - 120000280: df858028 ld a1,-32728\(gp\) + 120000280: df858020 ld a1,-32736\(gp\) 120000284: 64a50738 daddiu a1,a1,1848 120000288: 00b1282d daddu a1,a1,s1 - 12000028c: df858030 ld a1,-32720\(gp\) + 12000028c: df858028 ld a1,-32728\(gp\) 120000290: 64a5e96c daddiu a1,a1,-5780 120000294: 00b1282d daddu a1,a1,s1 - 120000298: df858028 ld a1,-32728\(gp\) + 120000298: df858020 ld a1,-32736\(gp\) 12000029c: dca5072c ld a1,1836\(a1\) - 1200002a0: df858028 ld a1,-32728\(gp\) + 1200002a0: df858020 ld a1,-32736\(gp\) 1200002a4: dca50738 ld a1,1848\(a1\) - 1200002a8: df858028 ld a1,-32728\(gp\) + 1200002a8: df858020 ld a1,-32736\(gp\) 1200002ac: 00b1282d daddu a1,a1,s1 1200002b0: dca5072c ld a1,1836\(a1\) - 1200002b4: df858028 ld a1,-32728\(gp\) + 1200002b4: df858020 ld a1,-32736\(gp\) 1200002b8: 00b1282d daddu a1,a1,s1 1200002bc: dca50738 ld a1,1848\(a1\) - 1200002c0: df818028 ld at,-32728\(gp\) + 1200002c0: df818020 ld at,-32736\(gp\) 1200002c4: 0025082d daddu at,at,a1 1200002c8: dc25074e ld a1,1870\(at\) - 1200002cc: df818028 ld at,-32728\(gp\) + 1200002cc: df818020 ld at,-32736\(gp\) 1200002d0: 0025082d daddu at,at,a1 1200002d4: fc250764 sd a1,1892\(at\) - 1200002d8: df818028 ld at,-32728\(gp\) + 1200002d8: df818020 ld at,-32736\(gp\) 1200002dc: 6421072c daddiu at,at,1836 1200002e0: 88250000 lwl a1,0\(at\) 1200002e4: 98250003 lwr a1,3\(at\) - 1200002e8: df818028 ld at,-32728\(gp\) + 1200002e8: df818020 ld at,-32736\(gp\) 1200002ec: 64210738 daddiu at,at,1848 1200002f0: 88250000 lwl a1,0\(at\) 1200002f4: 98250003 lwr a1,3\(at\) - 1200002f8: df818028 ld at,-32728\(gp\) + 1200002f8: df818020 ld at,-32736\(gp\) 1200002fc: 6421072c daddiu at,at,1836 120000300: 0031082d daddu at,at,s1 120000304: 88250000 lwl a1,0\(at\) 120000308: 98250003 lwr a1,3\(at\) - 12000030c: df818028 ld at,-32728\(gp\) + 12000030c: df818020 ld at,-32736\(gp\) 120000310: 64210738 daddiu at,at,1848 120000314: 0031082d daddu at,at,s1 120000318: 88250000 lwl a1,0\(at\) 12000031c: 98250003 lwr a1,3\(at\) - 120000320: df818028 ld at,-32728\(gp\) + 120000320: df818020 ld at,-32736\(gp\) 120000324: 6421074e daddiu at,at,1870 120000328: 0025082d daddu at,at,a1 12000032c: 88250000 lwl a1,0\(at\) 120000330: 98250003 lwr a1,3\(at\) - 120000334: df818028 ld at,-32728\(gp\) + 120000334: df818020 ld at,-32736\(gp\) 120000338: 64210764 daddiu at,at,1892 12000033c: 0025082d daddu at,at,a1 120000340: a8250000 swl a1,0\(at\) 120000344: b8250003 swr a1,3\(at\) 120000348: 3c050000 lui a1,0x0 12000034c: 00bc282d daddu a1,a1,gp - 120000350: dca58038 ld a1,-32712\(a1\) - 120000354: df858040 ld a1,-32704\(gp\) + 120000350: dca58058 ld a1,-32680\(a1\) + 120000354: df858030 ld a1,-32720\(gp\) 120000358: 64a500e0 daddiu a1,a1,224 12000035c: 3c190000 lui t9,0x0 120000360: 033cc82d daddu t9,t9,gp - 120000364: df398038 ld t9,-32712\(t9\) - 120000368: df998040 ld t9,-32704\(gp\) + 120000364: df398058 ld t9,-32680\(t9\) + 120000368: df998030 ld t9,-32720\(gp\) 12000036c: 673900e0 daddiu t9,t9,224 120000370: 3c190000 lui t9,0x0 120000374: 033cc82d daddu t9,t9,gp - 120000378: df398038 ld t9,-32712\(t9\) + 120000378: df398058 ld t9,-32680\(t9\) 12000037c: 0411ff58 bal 1200000e0 <fn> 120000380: 00000000 nop - 120000384: df998040 ld t9,-32704\(gp\) + 120000384: df998030 ld t9,-32720\(gp\) 120000388: 673900e0 daddiu t9,t9,224 12000038c: 0411ff54 bal 1200000e0 <fn> 120000390: 00000000 nop 120000394: 3c050000 lui a1,0x0 120000398: 00bc282d daddu a1,a1,gp - 12000039c: dca58048 ld a1,-32696\(a1\) + 12000039c: dca58050 ld a1,-32688\(a1\) 1200003a0: 3c050000 lui a1,0x0 1200003a4: 00bc282d daddu a1,a1,gp - 1200003a8: dca58048 ld a1,-32696\(a1\) + 1200003a8: dca58050 ld a1,-32688\(a1\) 1200003ac: 64a5000c daddiu a1,a1,12 1200003b0: 3c050000 lui a1,0x0 1200003b4: 00bc282d daddu a1,a1,gp - 1200003b8: dca58048 ld a1,-32696\(a1\) + 1200003b8: dca58050 ld a1,-32688\(a1\) 1200003bc: 3c010001 lui at,0x1 1200003c0: 3421e240 ori at,at,0xe240 1200003c4: 00a1282d daddu a1,a1,at 1200003c8: 3c050000 lui a1,0x0 1200003cc: 00bc282d daddu a1,a1,gp - 1200003d0: dca58048 ld a1,-32696\(a1\) + 1200003d0: dca58050 ld a1,-32688\(a1\) 1200003d4: 00b1282d daddu a1,a1,s1 1200003d8: 3c050000 lui a1,0x0 1200003dc: 00bc282d daddu a1,a1,gp - 1200003e0: dca58048 ld a1,-32696\(a1\) + 1200003e0: dca58050 ld a1,-32688\(a1\) 1200003e4: 64a5000c daddiu a1,a1,12 1200003e8: 00b1282d daddu a1,a1,s1 1200003ec: 3c050000 lui a1,0x0 1200003f0: 00bc282d daddu a1,a1,gp - 1200003f4: dca58048 ld a1,-32696\(a1\) + 1200003f4: dca58050 ld a1,-32688\(a1\) 1200003f8: 3c010001 lui at,0x1 1200003fc: 3421e240 ori at,at,0xe240 120000400: 00a1282d daddu a1,a1,at 120000404: 00b1282d daddu a1,a1,s1 120000408: 3c050000 lui a1,0x0 12000040c: 00bc282d daddu a1,a1,gp - 120000410: dca58048 ld a1,-32696\(a1\) + 120000410: dca58050 ld a1,-32688\(a1\) 120000414: dca50000 ld a1,0\(a1\) 120000418: 3c050000 lui a1,0x0 12000041c: 00bc282d daddu a1,a1,gp - 120000420: dca58048 ld a1,-32696\(a1\) + 120000420: dca58050 ld a1,-32688\(a1\) 120000424: dca5000c ld a1,12\(a1\) 120000428: 3c050000 lui a1,0x0 12000042c: 00bc282d daddu a1,a1,gp - 120000430: dca58048 ld a1,-32696\(a1\) + 120000430: dca58050 ld a1,-32688\(a1\) 120000434: 00b1282d daddu a1,a1,s1 120000438: dca50000 ld a1,0\(a1\) 12000043c: 3c050000 lui a1,0x0 120000440: 00bc282d daddu a1,a1,gp - 120000444: dca58048 ld a1,-32696\(a1\) + 120000444: dca58050 ld a1,-32688\(a1\) 120000448: 00b1282d daddu a1,a1,s1 12000044c: dca5000c ld a1,12\(a1\) 120000450: 3c010000 lui at,0x0 120000454: 003c082d daddu at,at,gp - 120000458: dc218048 ld at,-32696\(at\) + 120000458: dc218050 ld at,-32688\(at\) 12000045c: 0025082d daddu at,at,a1 120000460: dc250022 ld a1,34\(at\) 120000464: 3c010000 lui at,0x0 120000468: 003c082d daddu at,at,gp - 12000046c: dc218048 ld at,-32696\(at\) + 12000046c: dc218050 ld at,-32688\(at\) 120000470: 0025082d daddu at,at,a1 120000474: fc250038 sd a1,56\(at\) 120000478: 3c010000 lui at,0x0 12000047c: 003c082d daddu at,at,gp - 120000480: dc218048 ld at,-32696\(at\) + 120000480: dc218050 ld at,-32688\(at\) 120000484: 88250000 lwl a1,0\(at\) 120000488: 98250003 lwr a1,3\(at\) 12000048c: 3c010000 lui at,0x0 120000490: 003c082d daddu at,at,gp - 120000494: dc218048 ld at,-32696\(at\) + 120000494: dc218050 ld at,-32688\(at\) 120000498: 6421000c daddiu at,at,12 12000049c: 88250000 lwl a1,0\(at\) 1200004a0: 98250003 lwr a1,3\(at\) 1200004a4: 3c010000 lui at,0x0 1200004a8: 003c082d daddu at,at,gp - 1200004ac: dc218048 ld at,-32696\(at\) + 1200004ac: dc218050 ld at,-32688\(at\) 1200004b0: 0031082d daddu at,at,s1 1200004b4: 88250000 lwl a1,0\(at\) 1200004b8: 98250003 lwr a1,3\(at\) 1200004bc: 3c010000 lui at,0x0 1200004c0: 003c082d daddu at,at,gp - 1200004c4: dc218048 ld at,-32696\(at\) + 1200004c4: dc218050 ld at,-32688\(at\) 1200004c8: 6421000c daddiu at,at,12 1200004cc: 0031082d daddu at,at,s1 1200004d0: 88250000 lwl a1,0\(at\) 1200004d4: 98250003 lwr a1,3\(at\) 1200004d8: 3c010000 lui at,0x0 1200004dc: 003c082d daddu at,at,gp - 1200004e0: dc218048 ld at,-32696\(at\) + 1200004e0: dc218050 ld at,-32688\(at\) 1200004e4: 64210022 daddiu at,at,34 1200004e8: 0025082d daddu at,at,a1 1200004ec: 88250000 lwl a1,0\(at\) 1200004f0: 98250003 lwr a1,3\(at\) 1200004f4: 3c010000 lui at,0x0 1200004f8: 003c082d daddu at,at,gp - 1200004fc: dc218048 ld at,-32696\(at\) + 1200004fc: dc218050 ld at,-32688\(at\) 120000500: 64210038 daddiu at,at,56 120000504: 0025082d daddu at,at,a1 120000508: a8250000 swl a1,0\(at\) 12000050c: b8250003 swr a1,3\(at\) - 120000510: df858028 ld a1,-32728\(gp\) + 120000510: df858020 ld a1,-32736\(gp\) 120000514: 64a507a4 daddiu a1,a1,1956 - 120000518: df858028 ld a1,-32728\(gp\) + 120000518: df858020 ld a1,-32736\(gp\) 12000051c: 64a507b0 daddiu a1,a1,1968 - 120000520: df858030 ld a1,-32720\(gp\) + 120000520: df858028 ld a1,-32728\(gp\) 120000524: 64a5e9e4 daddiu a1,a1,-5660 - 120000528: df858028 ld a1,-32728\(gp\) + 120000528: df858020 ld a1,-32736\(gp\) 12000052c: 64a507a4 daddiu a1,a1,1956 120000530: 00b1282d daddu a1,a1,s1 - 120000534: df858028 ld a1,-32728\(gp\) + 120000534: df858020 ld a1,-32736\(gp\) 120000538: 64a507b0 daddiu a1,a1,1968 12000053c: 00b1282d daddu a1,a1,s1 - 120000540: df858030 ld a1,-32720\(gp\) + 120000540: df858028 ld a1,-32728\(gp\) 120000544: 64a5e9e4 daddiu a1,a1,-5660 120000548: 00b1282d daddu a1,a1,s1 - 12000054c: df858028 ld a1,-32728\(gp\) + 12000054c: df858020 ld a1,-32736\(gp\) 120000550: dca507a4 ld a1,1956\(a1\) - 120000554: df858028 ld a1,-32728\(gp\) + 120000554: df858020 ld a1,-32736\(gp\) 120000558: dca507b0 ld a1,1968\(a1\) - 12000055c: df858028 ld a1,-32728\(gp\) + 12000055c: df858020 ld a1,-32736\(gp\) 120000560: 00b1282d daddu a1,a1,s1 120000564: dca507a4 ld a1,1956\(a1\) - 120000568: df858028 ld a1,-32728\(gp\) + 120000568: df858020 ld a1,-32736\(gp\) 12000056c: 00b1282d daddu a1,a1,s1 120000570: dca507b0 ld a1,1968\(a1\) - 120000574: df818028 ld at,-32728\(gp\) + 120000574: df818020 ld at,-32736\(gp\) 120000578: 0025082d daddu at,at,a1 12000057c: dc2507c6 ld a1,1990\(at\) - 120000580: df818028 ld at,-32728\(gp\) + 120000580: df818020 ld at,-32736\(gp\) 120000584: 0025082d daddu at,at,a1 120000588: fc2507dc sd a1,2012\(at\) - 12000058c: df818028 ld at,-32728\(gp\) + 12000058c: df818020 ld at,-32736\(gp\) 120000590: 642107a4 daddiu at,at,1956 120000594: 88250000 lwl a1,0\(at\) 120000598: 98250003 lwr a1,3\(at\) - 12000059c: df818028 ld at,-32728\(gp\) + 12000059c: df818020 ld at,-32736\(gp\) 1200005a0: 642107b0 daddiu at,at,1968 1200005a4: 88250000 lwl a1,0\(at\) 1200005a8: 98250003 lwr a1,3\(at\) - 1200005ac: df818028 ld at,-32728\(gp\) + 1200005ac: df818020 ld at,-32736\(gp\) 1200005b0: 642107a4 daddiu at,at,1956 1200005b4: 0031082d daddu at,at,s1 1200005b8: 88250000 lwl a1,0\(at\) 1200005bc: 98250003 lwr a1,3\(at\) - 1200005c0: df818028 ld at,-32728\(gp\) + 1200005c0: df818020 ld at,-32736\(gp\) 1200005c4: 642107b0 daddiu at,at,1968 1200005c8: 0031082d daddu at,at,s1 1200005cc: 88250000 lwl a1,0\(at\) 1200005d0: 98250003 lwr a1,3\(at\) - 1200005d4: df818028 ld at,-32728\(gp\) + 1200005d4: df818020 ld at,-32736\(gp\) 1200005d8: 642107c6 daddiu at,at,1990 1200005dc: 0025082d daddu at,at,a1 1200005e0: 88250000 lwl a1,0\(at\) 1200005e4: 98250003 lwr a1,3\(at\) - 1200005e8: df818028 ld at,-32728\(gp\) + 1200005e8: df818020 ld at,-32736\(gp\) 1200005ec: 642107dc daddiu at,at,2012 1200005f0: 0025082d daddu at,at,a1 1200005f4: a8250000 swl a1,0\(at\) 1200005f8: b8250003 swr a1,3\(at\) 1200005fc: 3c050000 lui a1,0x0 120000600: 00bc282d daddu a1,a1,gp - 120000604: dca58050 ld a1,-32688\(a1\) - 120000608: df858040 ld a1,-32704\(gp\) + 120000604: dca58048 ld a1,-32696\(a1\) + 120000608: df858030 ld a1,-32720\(gp\) 12000060c: 64a506e0 daddiu a1,a1,1760 120000610: 3c190000 lui t9,0x0 120000614: 033cc82d daddu t9,t9,gp - 120000618: df398050 ld t9,-32688\(t9\) - 12000061c: df998040 ld t9,-32704\(gp\) + 120000618: df398048 ld t9,-32696\(t9\) + 12000061c: df998030 ld t9,-32720\(gp\) 120000620: 673906e0 daddiu t9,t9,1760 120000624: 3c190000 lui t9,0x0 120000628: 033cc82d daddu t9,t9,gp - 12000062c: df398050 ld t9,-32688\(t9\) + 12000062c: df398048 ld t9,-32696\(t9\) 120000630: 0411002b bal 1200006e0 <fn2> 120000634: 00000000 nop - 120000638: df998040 ld t9,-32704\(gp\) + 120000638: df998030 ld t9,-32720\(gp\) 12000063c: 673906e0 daddiu t9,t9,1760 120000640: 04110027 bal 1200006e0 <fn2> 120000644: 00000000 nop 120000648: 3c050000 lui a1,0x0 12000064c: 00bc282d daddu a1,a1,gp - 120000650: dca58020 ld a1,-32736\(a1\) + 120000650: dca58060 ld a1,-32672\(a1\) 120000654: 1000fea2 b 1200000e0 <fn> 120000658: 00000000 nop 12000065c: 3c050000 lui a1,0x0 120000660: 00bc282d daddu a1,a1,gp - 120000664: dca58048 ld a1,-32696\(a1\) + 120000664: dca58050 ld a1,-32688\(a1\) 120000668: dca50000 ld a1,0\(a1\) 12000066c: 1000001c b 1200006e0 <fn2> 120000670: 00000000 nop - 120000674: df858028 ld a1,-32728\(gp\) + 120000674: df858020 ld a1,-32736\(gp\) 120000678: 64a5072c daddiu a1,a1,1836 12000067c: 1000fe98 b 1200000e0 <fn> 120000680: 00000000 nop - 120000684: df858028 ld a1,-32728\(gp\) + 120000684: df858020 ld a1,-32736\(gp\) 120000688: 64a507b0 daddiu a1,a1,1968 12000068c: 10000014 b 1200006e0 <fn2> 120000690: 00000000 nop - 120000694: df858030 ld a1,-32720\(gp\) + 120000694: df858028 ld a1,-32728\(gp\) 120000698: 64a5e96c daddiu a1,a1,-5780 12000069c: 1000fe90 b 1200000e0 <fn> 1200006a0: 00000000 nop - 1200006a4: df858028 ld a1,-32728\(gp\) + 1200006a4: df858020 ld a1,-32736\(gp\) 1200006a8: dca507a4 ld a1,1956\(a1\) 1200006ac: 1000000c b 1200006e0 <fn2> 1200006b0: 00000000 nop - 1200006b4: df858028 ld a1,-32728\(gp\) + 1200006b4: df858020 ld a1,-32736\(gp\) 1200006b8: dca50738 ld a1,1848\(a1\) 1200006bc: 1000fe88 b 1200000e0 <fn> 1200006c0: 00000000 nop - 1200006c4: df818028 ld at,-32728\(gp\) + 1200006c4: df818020 ld at,-32736\(gp\) 1200006c8: 0025082d daddu at,at,a1 1200006cc: dc2507c6 ld a1,1990\(at\) 1200006d0: 10000003 b 1200006e0 <fn2> @@ -427,18 +428,18 @@ Disassembly of section \.got: 1200107e8: 80000000 .* 1200107ec: 00000000 .* 1200107f0: 00000001 .* - 1200107f4: 2001072c .* + 1200107f4: 20010000 .* 1200107f8: 00000001 .* - 1200107fc: 20010000 .* + 1200107fc: 20030000 .* 120010800: 00000001 .* - 120010804: 20030000 .* - 120010808: 00000001 .* - 12001080c: 200000e0 .* - 120010810: 00000001 .* - 120010814: 20000000 .* + 120010804: 20000000 .* + \.\.\. 120010818: 00000001 .* - 12001081c: 200107a4 .* + 12001081c: 200006e0 .* 120010820: 00000001 .* - 120010824: 200006e0 .* - \.\.\. + 120010824: 200107a4 .* + 120010828: 00000001 .* + 12001082c: 200000e0 .* + 120010830: 00000001 .* + 120010834: 2001072c .* #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d index 6a9ea40..348b718 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d @@ -1,6 +1,7 @@ #name: MIPS ELF xgot reloc n64 #as: -march=from-abi -EB -64 -KPIC -xgot -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn @@ -19,382 +20,382 @@ Disassembly of section \.text: 0000000010000110 <fn>: 10000110: 3c050000 lui a1,0x0 10000114: 00bc282d daddu a1,a1,gp - 10000118: dca58020 ld a1,-32736\(a1\) + 10000118: dca58060 ld a1,-32672\(a1\) 1000011c: 3c050000 lui a1,0x0 10000120: 00bc282d daddu a1,a1,gp - 10000124: dca58020 ld a1,-32736\(a1\) + 10000124: dca58060 ld a1,-32672\(a1\) 10000128: 64a5000c daddiu a1,a1,12 1000012c: 3c050000 lui a1,0x0 10000130: 00bc282d daddu a1,a1,gp - 10000134: dca58020 ld a1,-32736\(a1\) + 10000134: dca58060 ld a1,-32672\(a1\) 10000138: 3c010001 lui at,0x1 1000013c: 3421e240 ori at,at,0xe240 10000140: 00a1282d daddu a1,a1,at 10000144: 3c050000 lui a1,0x0 10000148: 00bc282d daddu a1,a1,gp - 1000014c: dca58020 ld a1,-32736\(a1\) + 1000014c: dca58060 ld a1,-32672\(a1\) 10000150: 00b1282d daddu a1,a1,s1 10000154: 3c050000 lui a1,0x0 10000158: 00bc282d daddu a1,a1,gp - 1000015c: dca58020 ld a1,-32736\(a1\) + 1000015c: dca58060 ld a1,-32672\(a1\) 10000160: 64a5000c daddiu a1,a1,12 10000164: 00b1282d daddu a1,a1,s1 10000168: 3c050000 lui a1,0x0 1000016c: 00bc282d daddu a1,a1,gp - 10000170: dca58020 ld a1,-32736\(a1\) + 10000170: dca58060 ld a1,-32672\(a1\) 10000174: 3c010001 lui at,0x1 10000178: 3421e240 ori at,at,0xe240 1000017c: 00a1282d daddu a1,a1,at 10000180: 00b1282d daddu a1,a1,s1 10000184: 3c050000 lui a1,0x0 10000188: 00bc282d daddu a1,a1,gp - 1000018c: dca58020 ld a1,-32736\(a1\) + 1000018c: dca58060 ld a1,-32672\(a1\) 10000190: dca50000 ld a1,0\(a1\) 10000194: 3c050000 lui a1,0x0 10000198: 00bc282d daddu a1,a1,gp - 1000019c: dca58020 ld a1,-32736\(a1\) + 1000019c: dca58060 ld a1,-32672\(a1\) 100001a0: dca5000c ld a1,12\(a1\) 100001a4: 3c050000 lui a1,0x0 100001a8: 00bc282d daddu a1,a1,gp - 100001ac: dca58020 ld a1,-32736\(a1\) + 100001ac: dca58060 ld a1,-32672\(a1\) 100001b0: 00b1282d daddu a1,a1,s1 100001b4: dca50000 ld a1,0\(a1\) 100001b8: 3c050000 lui a1,0x0 100001bc: 00bc282d daddu a1,a1,gp - 100001c0: dca58020 ld a1,-32736\(a1\) + 100001c0: dca58060 ld a1,-32672\(a1\) 100001c4: 00b1282d daddu a1,a1,s1 100001c8: dca5000c ld a1,12\(a1\) 100001cc: 3c010000 lui at,0x0 100001d0: 003c082d daddu at,at,gp - 100001d4: dc218020 ld at,-32736\(at\) + 100001d4: dc218060 ld at,-32672\(at\) 100001d8: 0025082d daddu at,at,a1 100001dc: dc250022 ld a1,34\(at\) 100001e0: 3c010000 lui at,0x0 100001e4: 003c082d daddu at,at,gp - 100001e8: dc218020 ld at,-32736\(at\) + 100001e8: dc218060 ld at,-32672\(at\) 100001ec: 0025082d daddu at,at,a1 100001f0: fc250038 sd a1,56\(at\) 100001f4: 3c010000 lui at,0x0 100001f8: 003c082d daddu at,at,gp - 100001fc: dc218020 ld at,-32736\(at\) + 100001fc: dc218060 ld at,-32672\(at\) 10000200: 88250000 lwl a1,0\(at\) 10000204: 98250003 lwr a1,3\(at\) 10000208: 3c010000 lui at,0x0 1000020c: 003c082d daddu at,at,gp - 10000210: dc218020 ld at,-32736\(at\) + 10000210: dc218060 ld at,-32672\(at\) 10000214: 6421000c daddiu at,at,12 10000218: 88250000 lwl a1,0\(at\) 1000021c: 98250003 lwr a1,3\(at\) 10000220: 3c010000 lui at,0x0 10000224: 003c082d daddu at,at,gp - 10000228: dc218020 ld at,-32736\(at\) + 10000228: dc218060 ld at,-32672\(at\) 1000022c: 0031082d daddu at,at,s1 10000230: 88250000 lwl a1,0\(at\) 10000234: 98250003 lwr a1,3\(at\) 10000238: 3c010000 lui at,0x0 1000023c: 003c082d daddu at,at,gp - 10000240: dc218020 ld at,-32736\(at\) + 10000240: dc218060 ld at,-32672\(at\) 10000244: 6421000c daddiu at,at,12 10000248: 0031082d daddu at,at,s1 1000024c: 88250000 lwl a1,0\(at\) 10000250: 98250003 lwr a1,3\(at\) 10000254: 3c010000 lui at,0x0 10000258: 003c082d daddu at,at,gp - 1000025c: dc218020 ld at,-32736\(at\) + 1000025c: dc218060 ld at,-32672\(at\) 10000260: 64210022 daddiu at,at,34 10000264: 0025082d daddu at,at,a1 10000268: 88250000 lwl a1,0\(at\) 1000026c: 98250003 lwr a1,3\(at\) 10000270: 3c010000 lui at,0x0 10000274: 003c082d daddu at,at,gp - 10000278: dc218020 ld at,-32736\(at\) + 10000278: dc218060 ld at,-32672\(at\) 1000027c: 64210038 daddiu at,at,56 10000280: 0025082d daddu at,at,a1 10000284: a8250000 swl a1,0\(at\) 10000288: b8250003 swr a1,3\(at\) - 1000028c: df858028 ld a1,-32728\(gp\) + 1000028c: df858020 ld a1,-32736\(gp\) 10000290: 64a5075c daddiu a1,a1,1884 - 10000294: df858028 ld a1,-32728\(gp\) + 10000294: df858020 ld a1,-32736\(gp\) 10000298: 64a50768 daddiu a1,a1,1896 - 1000029c: df858030 ld a1,-32720\(gp\) + 1000029c: df858028 ld a1,-32728\(gp\) 100002a0: 64a5e99c daddiu a1,a1,-5732 - 100002a4: df858028 ld a1,-32728\(gp\) + 100002a4: df858020 ld a1,-32736\(gp\) 100002a8: 64a5075c daddiu a1,a1,1884 100002ac: 00b1282d daddu a1,a1,s1 - 100002b0: df858028 ld a1,-32728\(gp\) + 100002b0: df858020 ld a1,-32736\(gp\) 100002b4: 64a50768 daddiu a1,a1,1896 100002b8: 00b1282d daddu a1,a1,s1 - 100002bc: df858030 ld a1,-32720\(gp\) + 100002bc: df858028 ld a1,-32728\(gp\) 100002c0: 64a5e99c daddiu a1,a1,-5732 100002c4: 00b1282d daddu a1,a1,s1 - 100002c8: df858028 ld a1,-32728\(gp\) + 100002c8: df858020 ld a1,-32736\(gp\) 100002cc: dca5075c ld a1,1884\(a1\) - 100002d0: df858028 ld a1,-32728\(gp\) + 100002d0: df858020 ld a1,-32736\(gp\) 100002d4: dca50768 ld a1,1896\(a1\) - 100002d8: df858028 ld a1,-32728\(gp\) + 100002d8: df858020 ld a1,-32736\(gp\) 100002dc: 00b1282d daddu a1,a1,s1 100002e0: dca5075c ld a1,1884\(a1\) - 100002e4: df858028 ld a1,-32728\(gp\) + 100002e4: df858020 ld a1,-32736\(gp\) 100002e8: 00b1282d daddu a1,a1,s1 100002ec: dca50768 ld a1,1896\(a1\) - 100002f0: df818028 ld at,-32728\(gp\) + 100002f0: df818020 ld at,-32736\(gp\) 100002f4: 0025082d daddu at,at,a1 100002f8: dc25077e ld a1,1918\(at\) - 100002fc: df818028 ld at,-32728\(gp\) + 100002fc: df818020 ld at,-32736\(gp\) 10000300: 0025082d daddu at,at,a1 10000304: fc250794 sd a1,1940\(at\) - 10000308: df818028 ld at,-32728\(gp\) + 10000308: df818020 ld at,-32736\(gp\) 1000030c: 6421075c daddiu at,at,1884 10000310: 88250000 lwl a1,0\(at\) 10000314: 98250003 lwr a1,3\(at\) - 10000318: df818028 ld at,-32728\(gp\) + 10000318: df818020 ld at,-32736\(gp\) 1000031c: 64210768 daddiu at,at,1896 10000320: 88250000 lwl a1,0\(at\) 10000324: 98250003 lwr a1,3\(at\) - 10000328: df818028 ld at,-32728\(gp\) + 10000328: df818020 ld at,-32736\(gp\) 1000032c: 6421075c daddiu at,at,1884 10000330: 0031082d daddu at,at,s1 10000334: 88250000 lwl a1,0\(at\) 10000338: 98250003 lwr a1,3\(at\) - 1000033c: df818028 ld at,-32728\(gp\) + 1000033c: df818020 ld at,-32736\(gp\) 10000340: 64210768 daddiu at,at,1896 10000344: 0031082d daddu at,at,s1 10000348: 88250000 lwl a1,0\(at\) 1000034c: 98250003 lwr a1,3\(at\) - 10000350: df818028 ld at,-32728\(gp\) + 10000350: df818020 ld at,-32736\(gp\) 10000354: 6421077e daddiu at,at,1918 10000358: 0025082d daddu at,at,a1 1000035c: 88250000 lwl a1,0\(at\) 10000360: 98250003 lwr a1,3\(at\) - 10000364: df818028 ld at,-32728\(gp\) + 10000364: df818020 ld at,-32736\(gp\) 10000368: 64210794 daddiu at,at,1940 1000036c: 0025082d daddu at,at,a1 10000370: a8250000 swl a1,0\(at\) 10000374: b8250003 swr a1,3\(at\) 10000378: 3c050000 lui a1,0x0 1000037c: 00bc282d daddu a1,a1,gp - 10000380: dca58038 ld a1,-32712\(a1\) - 10000384: df858040 ld a1,-32704\(gp\) + 10000380: dca58058 ld a1,-32680\(a1\) + 10000384: df858030 ld a1,-32720\(gp\) 10000388: 64a50110 daddiu a1,a1,272 1000038c: 3c190000 lui t9,0x0 10000390: 033cc82d daddu t9,t9,gp - 10000394: df398038 ld t9,-32712\(t9\) - 10000398: df998040 ld t9,-32704\(gp\) + 10000394: df398058 ld t9,-32680\(t9\) + 10000398: df998030 ld t9,-32720\(gp\) 1000039c: 67390110 daddiu t9,t9,272 100003a0: 3c190000 lui t9,0x0 100003a4: 033cc82d daddu t9,t9,gp - 100003a8: df398038 ld t9,-32712\(t9\) + 100003a8: df398058 ld t9,-32680\(t9\) 100003ac: 0411ff58 bal 10000110 <fn> 100003b0: 00000000 nop - 100003b4: df998040 ld t9,-32704\(gp\) + 100003b4: df998030 ld t9,-32720\(gp\) 100003b8: 67390110 daddiu t9,t9,272 100003bc: 0411ff54 bal 10000110 <fn> 100003c0: 00000000 nop 100003c4: 3c050000 lui a1,0x0 100003c8: 00bc282d daddu a1,a1,gp - 100003cc: dca58048 ld a1,-32696\(a1\) + 100003cc: dca58050 ld a1,-32688\(a1\) 100003d0: 3c050000 lui a1,0x0 100003d4: 00bc282d daddu a1,a1,gp - 100003d8: dca58048 ld a1,-32696\(a1\) + 100003d8: dca58050 ld a1,-32688\(a1\) 100003dc: 64a5000c daddiu a1,a1,12 100003e0: 3c050000 lui a1,0x0 100003e4: 00bc282d daddu a1,a1,gp - 100003e8: dca58048 ld a1,-32696\(a1\) + 100003e8: dca58050 ld a1,-32688\(a1\) 100003ec: 3c010001 lui at,0x1 100003f0: 3421e240 ori at,at,0xe240 100003f4: 00a1282d daddu a1,a1,at 100003f8: 3c050000 lui a1,0x0 100003fc: 00bc282d daddu a1,a1,gp - 10000400: dca58048 ld a1,-32696\(a1\) + 10000400: dca58050 ld a1,-32688\(a1\) 10000404: 00b1282d daddu a1,a1,s1 10000408: 3c050000 lui a1,0x0 1000040c: 00bc282d daddu a1,a1,gp - 10000410: dca58048 ld a1,-32696\(a1\) + 10000410: dca58050 ld a1,-32688\(a1\) 10000414: 64a5000c daddiu a1,a1,12 10000418: 00b1282d daddu a1,a1,s1 1000041c: 3c050000 lui a1,0x0 10000420: 00bc282d daddu a1,a1,gp - 10000424: dca58048 ld a1,-32696\(a1\) + 10000424: dca58050 ld a1,-32688\(a1\) 10000428: 3c010001 lui at,0x1 1000042c: 3421e240 ori at,at,0xe240 10000430: 00a1282d daddu a1,a1,at 10000434: 00b1282d daddu a1,a1,s1 10000438: 3c050000 lui a1,0x0 1000043c: 00bc282d daddu a1,a1,gp - 10000440: dca58048 ld a1,-32696\(a1\) + 10000440: dca58050 ld a1,-32688\(a1\) 10000444: dca50000 ld a1,0\(a1\) 10000448: 3c050000 lui a1,0x0 1000044c: 00bc282d daddu a1,a1,gp - 10000450: dca58048 ld a1,-32696\(a1\) + 10000450: dca58050 ld a1,-32688\(a1\) 10000454: dca5000c ld a1,12\(a1\) 10000458: 3c050000 lui a1,0x0 1000045c: 00bc282d daddu a1,a1,gp - 10000460: dca58048 ld a1,-32696\(a1\) + 10000460: dca58050 ld a1,-32688\(a1\) 10000464: 00b1282d daddu a1,a1,s1 10000468: dca50000 ld a1,0\(a1\) 1000046c: 3c050000 lui a1,0x0 10000470: 00bc282d daddu a1,a1,gp - 10000474: dca58048 ld a1,-32696\(a1\) + 10000474: dca58050 ld a1,-32688\(a1\) 10000478: 00b1282d daddu a1,a1,s1 1000047c: dca5000c ld a1,12\(a1\) 10000480: 3c010000 lui at,0x0 10000484: 003c082d daddu at,at,gp - 10000488: dc218048 ld at,-32696\(at\) + 10000488: dc218050 ld at,-32688\(at\) 1000048c: 0025082d daddu at,at,a1 10000490: dc250022 ld a1,34\(at\) 10000494: 3c010000 lui at,0x0 10000498: 003c082d daddu at,at,gp - 1000049c: dc218048 ld at,-32696\(at\) + 1000049c: dc218050 ld at,-32688\(at\) 100004a0: 0025082d daddu at,at,a1 100004a4: fc250038 sd a1,56\(at\) 100004a8: 3c010000 lui at,0x0 100004ac: 003c082d daddu at,at,gp - 100004b0: dc218048 ld at,-32696\(at\) + 100004b0: dc218050 ld at,-32688\(at\) 100004b4: 88250000 lwl a1,0\(at\) 100004b8: 98250003 lwr a1,3\(at\) 100004bc: 3c010000 lui at,0x0 100004c0: 003c082d daddu at,at,gp - 100004c4: dc218048 ld at,-32696\(at\) + 100004c4: dc218050 ld at,-32688\(at\) 100004c8: 6421000c daddiu at,at,12 100004cc: 88250000 lwl a1,0\(at\) 100004d0: 98250003 lwr a1,3\(at\) 100004d4: 3c010000 lui at,0x0 100004d8: 003c082d daddu at,at,gp - 100004dc: dc218048 ld at,-32696\(at\) + 100004dc: dc218050 ld at,-32688\(at\) 100004e0: 0031082d daddu at,at,s1 100004e4: 88250000 lwl a1,0\(at\) 100004e8: 98250003 lwr a1,3\(at\) 100004ec: 3c010000 lui at,0x0 100004f0: 003c082d daddu at,at,gp - 100004f4: dc218048 ld at,-32696\(at\) + 100004f4: dc218050 ld at,-32688\(at\) 100004f8: 6421000c daddiu at,at,12 100004fc: 0031082d daddu at,at,s1 10000500: 88250000 lwl a1,0\(at\) 10000504: 98250003 lwr a1,3\(at\) 10000508: 3c010000 lui at,0x0 1000050c: 003c082d daddu at,at,gp - 10000510: dc218048 ld at,-32696\(at\) + 10000510: dc218050 ld at,-32688\(at\) 10000514: 64210022 daddiu at,at,34 10000518: 0025082d daddu at,at,a1 1000051c: 88250000 lwl a1,0\(at\) 10000520: 98250003 lwr a1,3\(at\) 10000524: 3c010000 lui at,0x0 10000528: 003c082d daddu at,at,gp - 1000052c: dc218048 ld at,-32696\(at\) + 1000052c: dc218050 ld at,-32688\(at\) 10000530: 64210038 daddiu at,at,56 10000534: 0025082d daddu at,at,a1 10000538: a8250000 swl a1,0\(at\) 1000053c: b8250003 swr a1,3\(at\) - 10000540: df858028 ld a1,-32728\(gp\) + 10000540: df858020 ld a1,-32736\(gp\) 10000544: 64a507d4 daddiu a1,a1,2004 - 10000548: df858028 ld a1,-32728\(gp\) + 10000548: df858020 ld a1,-32736\(gp\) 1000054c: 64a507e0 daddiu a1,a1,2016 - 10000550: df858030 ld a1,-32720\(gp\) + 10000550: df858028 ld a1,-32728\(gp\) 10000554: 64a5ea14 daddiu a1,a1,-5612 - 10000558: df858028 ld a1,-32728\(gp\) + 10000558: df858020 ld a1,-32736\(gp\) 1000055c: 64a507d4 daddiu a1,a1,2004 10000560: 00b1282d daddu a1,a1,s1 - 10000564: df858028 ld a1,-32728\(gp\) + 10000564: df858020 ld a1,-32736\(gp\) 10000568: 64a507e0 daddiu a1,a1,2016 1000056c: 00b1282d daddu a1,a1,s1 - 10000570: df858030 ld a1,-32720\(gp\) + 10000570: df858028 ld a1,-32728\(gp\) 10000574: 64a5ea14 daddiu a1,a1,-5612 10000578: 00b1282d daddu a1,a1,s1 - 1000057c: df858028 ld a1,-32728\(gp\) + 1000057c: df858020 ld a1,-32736\(gp\) 10000580: dca507d4 ld a1,2004\(a1\) - 10000584: df858028 ld a1,-32728\(gp\) + 10000584: df858020 ld a1,-32736\(gp\) 10000588: dca507e0 ld a1,2016\(a1\) - 1000058c: df858028 ld a1,-32728\(gp\) + 1000058c: df858020 ld a1,-32736\(gp\) 10000590: 00b1282d daddu a1,a1,s1 10000594: dca507d4 ld a1,2004\(a1\) - 10000598: df858028 ld a1,-32728\(gp\) + 10000598: df858020 ld a1,-32736\(gp\) 1000059c: 00b1282d daddu a1,a1,s1 100005a0: dca507e0 ld a1,2016\(a1\) - 100005a4: df818028 ld at,-32728\(gp\) + 100005a4: df818020 ld at,-32736\(gp\) 100005a8: 0025082d daddu at,at,a1 100005ac: dc2507f6 ld a1,2038\(at\) - 100005b0: df818028 ld at,-32728\(gp\) + 100005b0: df818020 ld at,-32736\(gp\) 100005b4: 0025082d daddu at,at,a1 100005b8: fc25080c sd a1,2060\(at\) - 100005bc: df818028 ld at,-32728\(gp\) + 100005bc: df818020 ld at,-32736\(gp\) 100005c0: 642107d4 daddiu at,at,2004 100005c4: 88250000 lwl a1,0\(at\) 100005c8: 98250003 lwr a1,3\(at\) - 100005cc: df818028 ld at,-32728\(gp\) + 100005cc: df818020 ld at,-32736\(gp\) 100005d0: 642107e0 daddiu at,at,2016 100005d4: 88250000 lwl a1,0\(at\) 100005d8: 98250003 lwr a1,3\(at\) - 100005dc: df818028 ld at,-32728\(gp\) + 100005dc: df818020 ld at,-32736\(gp\) 100005e0: 642107d4 daddiu at,at,2004 100005e4: 0031082d daddu at,at,s1 100005e8: 88250000 lwl a1,0\(at\) 100005ec: 98250003 lwr a1,3\(at\) - 100005f0: df818028 ld at,-32728\(gp\) + 100005f0: df818020 ld at,-32736\(gp\) 100005f4: 642107e0 daddiu at,at,2016 100005f8: 0031082d daddu at,at,s1 100005fc: 88250000 lwl a1,0\(at\) 10000600: 98250003 lwr a1,3\(at\) - 10000604: df818028 ld at,-32728\(gp\) + 10000604: df818020 ld at,-32736\(gp\) 10000608: 642107f6 daddiu at,at,2038 1000060c: 0025082d daddu at,at,a1 10000610: 88250000 lwl a1,0\(at\) 10000614: 98250003 lwr a1,3\(at\) - 10000618: df818028 ld at,-32728\(gp\) + 10000618: df818020 ld at,-32736\(gp\) 1000061c: 6421080c daddiu at,at,2060 10000620: 0025082d daddu at,at,a1 10000624: a8250000 swl a1,0\(at\) 10000628: b8250003 swr a1,3\(at\) 1000062c: 3c050000 lui a1,0x0 10000630: 00bc282d daddu a1,a1,gp - 10000634: dca58050 ld a1,-32688\(a1\) - 10000638: df858040 ld a1,-32704\(gp\) + 10000634: dca58048 ld a1,-32696\(a1\) + 10000638: df858030 ld a1,-32720\(gp\) 1000063c: 64a50710 daddiu a1,a1,1808 10000640: 3c190000 lui t9,0x0 10000644: 033cc82d daddu t9,t9,gp - 10000648: df398050 ld t9,-32688\(t9\) - 1000064c: df998040 ld t9,-32704\(gp\) + 10000648: df398048 ld t9,-32696\(t9\) + 1000064c: df998030 ld t9,-32720\(gp\) 10000650: 67390710 daddiu t9,t9,1808 10000654: 3c190000 lui t9,0x0 10000658: 033cc82d daddu t9,t9,gp - 1000065c: df398050 ld t9,-32688\(t9\) + 1000065c: df398048 ld t9,-32696\(t9\) 10000660: 0411002b bal 10000710 <fn2> 10000664: 00000000 nop - 10000668: df998040 ld t9,-32704\(gp\) + 10000668: df998030 ld t9,-32720\(gp\) 1000066c: 67390710 daddiu t9,t9,1808 10000670: 04110027 bal 10000710 <fn2> 10000674: 00000000 nop 10000678: 3c050000 lui a1,0x0 1000067c: 00bc282d daddu a1,a1,gp - 10000680: dca58020 ld a1,-32736\(a1\) + 10000680: dca58060 ld a1,-32672\(a1\) 10000684: 1000fea2 b 10000110 <fn> 10000688: 00000000 nop 1000068c: 3c050000 lui a1,0x0 10000690: 00bc282d daddu a1,a1,gp - 10000694: dca58048 ld a1,-32696\(a1\) + 10000694: dca58050 ld a1,-32688\(a1\) 10000698: dca50000 ld a1,0\(a1\) 1000069c: 1000001c b 10000710 <fn2> 100006a0: 00000000 nop - 100006a4: df858028 ld a1,-32728\(gp\) + 100006a4: df858020 ld a1,-32736\(gp\) 100006a8: 64a5075c daddiu a1,a1,1884 100006ac: 1000fe98 b 10000110 <fn> 100006b0: 00000000 nop - 100006b4: df858028 ld a1,-32728\(gp\) + 100006b4: df858020 ld a1,-32736\(gp\) 100006b8: 64a507e0 daddiu a1,a1,2016 100006bc: 10000014 b 10000710 <fn2> 100006c0: 00000000 nop - 100006c4: df858030 ld a1,-32720\(gp\) + 100006c4: df858028 ld a1,-32728\(gp\) 100006c8: 64a5e99c daddiu a1,a1,-5732 100006cc: 1000fe90 b 10000110 <fn> 100006d0: 00000000 nop - 100006d4: df858028 ld a1,-32728\(gp\) + 100006d4: df858020 ld a1,-32736\(gp\) 100006d8: dca507d4 ld a1,2004\(a1\) 100006dc: 1000000c b 10000710 <fn2> 100006e0: 00000000 nop - 100006e4: df858028 ld a1,-32728\(gp\) + 100006e4: df858020 ld a1,-32736\(gp\) 100006e8: dca50768 ld a1,1896\(a1\) 100006ec: 1000fe88 b 10000110 <fn> 100006f0: 00000000 nop - 100006f4: df818028 ld at,-32728\(gp\) + 100006f4: df818020 ld at,-32736\(gp\) 100006f8: 0025082d daddu at,at,a1 100006fc: dc2507f6 ld a1,2038\(at\) 10000700: 10000003 b 10000710 <fn2> @@ -422,18 +423,17 @@ Disassembly of section \.got: \.\.\. 10010818: 80000000 .* \.\.\. - 10010824: 1001075c .* + 10010824: 10010000 .* 10010828: 00000000 .* - 1001082c: 10010000 .* + 1001082c: 10030000 .* 10010830: 00000000 .* - 10010834: 10030000 .* + 10010834: 10000000 .* 10010838: 00000000 .* - 1001083c: 10000110 .* - 10010840: 00000000 .* - 10010844: 10000000 .* - 10010848: 00000000 .* - 1001084c: 100107d4 .* + \.\.\. + 1001084c: 10000710 .* 10010850: 00000000 .* - 10010854: 10000710 .* + 10010854: 100107d4 .* 10010858: 00000000 .* - \.\.\. + 1001085c: 10000110 .* + 10010860: 00000000 .* + 10010864: 1001075c .* diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-1.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-1.ld index ba228f5..e8a40f1 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-1.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-1.ld @@ -16,4 +16,6 @@ SECTIONS .data : { *(.data) } HIDDEN (_gp = ALIGN (16) + 0x7ff0); .got : { *(.got) } + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-2.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-2.ld index 0e237de..d7ba691 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-2.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/got-dump-2.ld @@ -15,4 +15,6 @@ SECTIONS .data : { *(.data) } HIDDEN (_gp = ALIGN (16) + 0x7ff0); .got : { *(.got) } + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/got-page-1.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/got-page-1.ld index 3197c9b..cfe7c1f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/got-page-1.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/got-page-1.ld @@ -22,7 +22,7 @@ SECTIONS . = ALIGN (0x400); .bss : { *(.bss .bss.*) } - /DISCARD/ : { *(.reginfo) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } } VERSION diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/jalx-2.dd b/binutils-2.24/ld/testsuite/ld-mips-elf/jalx-2.dd index 50ebdb8..69985f6 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/jalx-2.dd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/jalx-2.dd @@ -28,7 +28,7 @@ Disassembly of section \.text: 4400034: f89e 0020 sw a0,32\(s8\) 4400038: f8be 0024 sw a1,36\(s8\) 440003c: 41a2 0440 lui v0,0x440 - 4400040: 3082 0260 addiu a0,v0,608 + 4400040: 3082 0280 addiu a0,v0,640 4400044: f620 004c jal 4400098 <printf@micromipsplt> 4400048: 0000 0000 nop 440004c: f620 0010 jal 4400020 <internal_function> diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/mips-dyn.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/mips-dyn.ld index e4f90d2..c59cc0f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/mips-dyn.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/mips-dyn.ld @@ -219,5 +219,5 @@ SECTIONS .debug_varnames 0 : { *(.debug_varnames) } .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } - /DISCARD/ : { *(.note.GNU-stack) } + /DISCARD/ : { *(.note.GNU-stack) *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/mips-elf.exp b/binutils-2.24/ld/testsuite/ld-mips-elf/mips-elf.exp index 827181b..b715898 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/mips-elf.exp +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/mips-elf.exp @@ -55,7 +55,9 @@ if {![istarget mips*-*-*] || ![is_elf_format]} { set has_newabi [expr [istarget *-*-irix6*] \ || [istarget mips*-*-linux*] \ - || [istarget mips*-sde-elf*]] + || [istarget mips*-sde-elf*] \ + || [istarget mips*-mti-elf*] \ + || [istarget mips*-img-elf*]] set linux_gnu [expr [istarget mips*-*-linux*]] set embedded_elf [expr [istarget mips*-*-elf]] @@ -78,7 +80,8 @@ if { [istarget *-*-irix6*] } { set abi_asflags(o32) "-32 -EB" set abi_ldflags(o32) -melf32btsmip_fbsd } -if { [istarget mips*-*-linux*] || [istarget mips*-sde-elf*] } { +if { [istarget mips*-*-linux*] || [istarget mips*-sde-elf*] + || [istarget mips*-mti-elf*] || [istarget mips*-img-elf*]} { set abi_ldflags(n32) -melf32btsmipn32 set abi_ldflags(n64) -melf64btsmip } elseif { [istarget mips64*-*freebsd*] } { @@ -633,37 +636,47 @@ run_ld_link_tests $mips16_intermix_test run_dump_test "mips16-local-stubs-1" -run_dump_test "attr-gnu-4-00" -run_dump_test "attr-gnu-4-01" -run_dump_test "attr-gnu-4-02" -run_dump_test "attr-gnu-4-03" -run_dump_test "attr-gnu-4-04" -run_dump_test "attr-gnu-4-05" -run_dump_test "attr-gnu-4-10" -run_dump_test "attr-gnu-4-11" -run_dump_test "attr-gnu-4-12" -run_dump_test "attr-gnu-4-13" -run_dump_test "attr-gnu-4-14" -run_dump_test "attr-gnu-4-15" -run_dump_test "attr-gnu-4-20" -run_dump_test "attr-gnu-4-21" -run_dump_test "attr-gnu-4-22" -run_dump_test "attr-gnu-4-23" -run_dump_test "attr-gnu-4-24" -run_dump_test "attr-gnu-4-25" -run_dump_test "attr-gnu-4-30" -run_dump_test "attr-gnu-4-31" -run_dump_test "attr-gnu-4-32" -run_dump_test "attr-gnu-4-33" -run_dump_test "attr-gnu-4-34" -run_dump_test "attr-gnu-4-35" -run_dump_test "attr-gnu-4-40" -run_dump_test "attr-gnu-4-41" -run_dump_test "attr-gnu-4-42" -run_dump_test "attr-gnu-4-43" -run_dump_test "attr-gnu-4-44" -run_dump_test "attr-gnu-4-45" -run_dump_test "attr-gnu-4-51" +foreach firstfpabi [list 0 1 2 3 4 5 6] { + foreach secondfpabi [list 0 1 2 3 4 5 6 7] { + run_dump_test "attr-gnu-4-${firstfpabi}${secondfpabi}" + } +} +run_dump_test "attr-gnu-4-71" + +run_dump_test "attr-gnu-8-00" +run_dump_test "attr-gnu-8-01" +run_dump_test "attr-gnu-8-02" +run_dump_test "attr-gnu-8-10" +run_dump_test "attr-gnu-8-11" +run_dump_test "attr-gnu-8-12" +run_dump_test "attr-gnu-8-20" +run_dump_test "attr-gnu-8-21" +run_dump_test "attr-gnu-8-22" + +run_dump_test "attr-gnu-4-0-ph" +run_dump_test "attr-gnu-4-1-ph" +run_dump_test "attr-gnu-4-2-ph" +run_dump_test "attr-gnu-4-3-ph" +run_dump_test "attr-gnu-4-4-ph" +run_dump_test "attr-gnu-4-5-ph" +run_dump_test "attr-gnu-4-6-ph" +run_dump_test "attr-gnu-4-0-n32-ph" +run_dump_test "attr-gnu-4-1-n32-ph" +run_dump_test "attr-gnu-4-2-n32-ph" +run_dump_test "attr-gnu-4-3-n32-ph" +run_dump_test "attr-gnu-4-0-n64-ph" +run_dump_test "attr-gnu-4-1-n64-ph" +run_dump_test "attr-gnu-4-2-n64-ph" +run_dump_test "attr-gnu-4-3-n64-ph" + +run_dump_test "abiflags-strip1-ph" +run_dump_test "abiflags-strip2-ph" +run_dump_test "abiflags-strip3-ph" +run_dump_test "abiflags-strip4-ph" +run_dump_test "abiflags-strip5-ph" +run_dump_test "abiflags-strip6-ph" +run_dump_test "abiflags-strip7-ph" +run_dump_test "abiflags-strip8-ph" run_dump_test "nan-legacy" run_dump_test "nan-2008" @@ -751,3 +764,89 @@ foreach { abi } $abis { [list "objdump -d jalr3.dd"] \ "jalr3-${abi}"]] } + +run_dump_test "attr-gnu-8-00" +run_dump_test "attr-gnu-8-01" +run_dump_test "attr-gnu-8-02" +run_dump_test "attr-gnu-8-10" +run_dump_test "attr-gnu-8-11" +run_dump_test "attr-gnu-8-12" +run_dump_test "attr-gnu-8-20" +run_dump_test "attr-gnu-8-21" +run_dump_test "attr-gnu-8-22" + +proc build_mips_plt_lib { abi } { + global abi_asflags + global abi_ldflags + + run_ld_link_tests [list \ + [list "Shared $abi library for compressed PLT tests" \ + "-shared $abi_ldflags($abi)" "" \ + "$abi_asflags($abi)" \ + { compressed-plt-1-dyn.s } \ + {} \ + "compressed-plt-1-${abi}-dyn.so"]] +} + +proc run_mips_plt_test { name abi filter micromips suffix {extra {}} } { + global abi_asflags + global abi_ldflags + + set as_flags "$abi_asflags($abi) --defsym filter=$filter" + append as_flags " --defsym micromips=$micromips --defsym $abi=1" + if {[string equal $abi o32]} { + append as_flags " -march=mips2" + } + set ld_flags "$abi_ldflags($abi) -T compressed-plt-1.ld" + set dynobj "tmpdir/compressed-plt-1-${abi}-dyn.so" + set files [list] + if { $filter & 3 } { + lappend files compressed-plt-1a.s + } + if { $filter & 12 } { + lappend files compressed-plt-1b.s + } + if { $filter & 16 } { + lappend files compressed-plt-1c.s + } + eval [list lappend files] $extra + set readelf_flags "-A --syms --relocs -d" + if { [string match "*word*" $suffix] } { + append readelf_flags " -x.data" + } + set objdump_flags "-d -Mgpr-names=numeric" + set basename "compressed-plt-1-${abi}-${suffix}" + run_ld_link_tests [list \ + [list "$name" $ld_flags $dynobj \ + "$as_flags" $files \ + [list [list readelf $readelf_flags ${basename}.rd] \ + [list objdump $objdump_flags ${basename}.od]] \ + $basename]] +} + +if { $linux_gnu } { + build_mips_plt_lib o32 + run_mips_plt_test "o32 PLTs for standard encoding" o32 28 0 se + run_mips_plt_test "o32 PLTs for MIPS16 encoding" o32 19 0 mips16-only + run_mips_plt_test "o32 PLTs for microMIPS encoding" o32 19 1 umips-only + run_mips_plt_test "o32 PLTs for mixed MIPS and MIPS16" \ + o32 -1 0 mips16 + run_mips_plt_test "o32 PLTs for mixed MIPS and MIPS16 with %got" \ + o32 -1 0 mips16-got compressed-plt-1d.s + run_mips_plt_test "o32 PLTs for mixed MIPS and MIPS16 with .word" \ + o32 -1 0 mips16-word compressed-plt-1e.s + run_mips_plt_test "o32 PLTs for mixed MIPS and microMIPS" \ + o32 -1 1 umips + run_mips_plt_test "o32 PLTs for mixed MIPS and microMIPS with %got" \ + o32 -1 1 umips-got compressed-plt-1d.s + run_mips_plt_test "o32 PLTs for mixed MIPS and microMIPS with .word" \ + o32 -1 1 umips-word compressed-plt-1e.s + + if $has_newabi { + build_mips_plt_lib n32 + run_mips_plt_test "n32 PLTs for mixed MIPS and MIPS16" \ + n32 -1 0 mips16 + run_mips_plt_test "n32 PLTs for mixed MIPS and microMIPS" \ + n32 -1 1 umips + } +} diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/mips-lib.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/mips-lib.ld index 5073d9f..8e75c77 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/mips-lib.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/mips-lib.ld @@ -214,5 +214,5 @@ SECTIONS .debug_varnames 0 : { *(.debug_varnames) } .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } - /DISCARD/ : { *(.note.GNU-stack) } + /DISCARD/ : { *(.note.GNU-stack) *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-1.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-1.gd index b8d8b34..cca758e 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-1.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-1.gd @@ -1,4 +1,21 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + Primary GOT: Canonical gp value: 00057ff0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-2.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-2.gd index c291bc8..269ae38 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-2.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-2.gd @@ -1,4 +1,21 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + Primary GOT: Canonical gp value: 00057ff0 @@ -16,8 +33,8 @@ Primary GOT: Global entries: Address Access Initial Sym\.Val\. Type Ndx Name - 00050018 -32728\(gp\) 00040574 00040574 FUNC 6 used6 - 0005001c -32724\(gp\) 00040598 00040598 FUNC 6 used7 - 00050020 -32720\(gp\) 00040550 00040550 FUNC 6 used5 - 00050024 -32716\(gp\) 0004052c 0004052c FUNC 6 used4 + 00050018 -32728\(gp\) 00040574 00040574 FUNC 7 used6 + 0005001c -32724\(gp\) 00040598 00040598 FUNC 7 used7 + 00050020 -32720\(gp\) 00040550 00040550 FUNC 7 used5 + 00050024 -32716\(gp\) 0004052c 0004052c FUNC 7 used4 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-3.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-3.gd index 9297fe6..141c4e6 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-3.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-3.gd @@ -1,4 +1,21 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + Primary GOT: Canonical gp value: 00057ff0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-4a.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-4a.gd index 1ab835e..55c8e1c 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-4a.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/mips16-pic-4a.gd @@ -1,4 +1,21 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + Primary GOT: Canonical gp value: 00057ff0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/multi-got-no-shared.d b/binutils-2.24/ld/testsuite/ld-mips-elf/multi-got-no-shared.d index 25af107..a3e1bb2 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/multi-got-no-shared.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/multi-got-no-shared.d @@ -8,11 +8,11 @@ .*: +file format.* Disassembly of section \.text: -004000b0 <[^>]*> 3c1c0043 lui gp,0x43 -004000b4 <[^>]*> 279c9ff0 addiu gp,gp,-24592 -004000b8 <[^>]*> afbc0008 sw gp,8\(sp\) +004000f0 <[^>]*> 3c1c0043 lui gp,0x43 +004000f4 <[^>]*> 279c9ff0 addiu gp,gp,-24592 +004000f8 <[^>]*> afbc0008 sw gp,8\(sp\) #... -00408d60 <[^>]*> 3c1c0043 lui gp,0x43 -00408d64 <[^>]*> 279c2c98 addiu gp,gp,11416 -00408d68 <[^>]*> afbc0008 sw gp,8\(sp\) +00408da0 <[^>]*> 3c1c0043 lui gp,0x43 +00408da4 <[^>]*> 279c2c98 addiu gp,gp,11416 +00408da8 <[^>]*> afbc0008 sw gp,8\(sp\) #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/nan-2008.d b/binutils-2.24/ld/testsuite/ld-mips-elf/nan-2008.d index aa20049..30ea837 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/nan-2008.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/nan-2008.d @@ -5,3 +5,4 @@ .*:.*file format.*mips.* private flags = [0-9a-f]*[4-7c-f]..: .*[[,]nan2008[],].* +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/nan-legacy.d b/binutils-2.24/ld/testsuite/ld-mips-elf/nan-legacy.d index 081abcf..8dacc06 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/nan-legacy.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/nan-legacy.d @@ -4,5 +4,5 @@ #objdump: -p .*:.*file format.*mips.* -#failif -private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* +!private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* +#pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.gd index aa9579b..b0f7b1e 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.gd @@ -1,4 +1,8 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Primary GOT: Canonical gp value: 000183f0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.ld index 81d0d8a..f2db79a 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.ld @@ -20,4 +20,6 @@ SECTIONS . = ALIGN (0x400); HIDDEN (_gp = . + 0x7ff0); .got : { *(.got) } + + /DISCARD/ : { *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd index 58b50c3..b178bdf 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd @@ -8,7 +8,7 @@ Program Headers: * REGINFO * [^ ]+ * 0x0+00000 * 0x0+00000 [^ ]+ * [^ ]+ * R * 0x.* * LOAD * [^ ]+ * 0x0+00000 * 0x0+00000 [^ ]+ * [^ ]+ * R E * 0x.* * LOAD * [^ ]+ * 0x0+10000 * 0x0+10000 [^ ]+ * [^ ]+ * RW * 0x.* - * DYNAMIC * [^ ]+ * 0x0+00400 * 0x0+00400 .* + * DYNAMIC * [^ ]+ * 0x0+00400 * 0x0+00400 [^ ]+ * [^ ]+ * R * 0x.* * NULL * .* *Section to Segment mapping: diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.gd index 6d3d677..e96e87f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.gd @@ -1,4 +1,8 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Primary GOT: Canonical gp value: 000a7ff0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ld index 693bbdd..ab64ea6 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ld @@ -32,4 +32,6 @@ SECTIONS . = 0xa1000; .data : { *(.data) } + + /DISCARD/ : { *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ld index bae9fd8..102c851 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ld @@ -30,4 +30,6 @@ SECTIONS . = 0xa2000; .bss : { *(.dynbss) } + + /DISCARD/ : { *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.gd index 6919a69..6d46b4f 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.gd @@ -1,4 +1,8 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Primary GOT: Canonical gp value: 000a7ff0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ld index b3ae77d..b76ceff 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ld @@ -35,4 +35,6 @@ SECTIONS . = 0xa2000; .bss : { *(.dynbss) } + + /DISCARD/ : { *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.ad b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.ad index fab5581..5df3c6c 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.ad +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.ad @@ -16,10 +16,10 @@ Dynamic section at offset .* contains .*: 0x70000001 \(MIPS_RLD_VERSION\) * 1 0x70000005 \(MIPS_FLAGS\) * NOTPOT 0x70000006 \(MIPS_BASE_ADDRESS\) * 0x40000 - 0x7000000a \(MIPS_LOCAL_GOTNO\) * 2 + 0x7000000a \(MIPS_LOCAL_GOTNO\) * 5 0x70000011 \(MIPS_SYMTABNO\) * 12 0x70000012 \(MIPS_UNREFEXTNO\) * .* - 0x70000013 \(MIPS_GOTSYM\) * 0x5 + 0x70000013 \(MIPS_GOTSYM\) * 0x8 0x00000014 \(PLTREL\) * REL 0x00000017 \(JMPREL\) * 0x43028 0x00000002 \(PLTRELSZ\) * 24 \(bytes\) diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd index df8d02a..276d874 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.dd @@ -2,13 +2,13 @@ # # -32752: lazy resolution function # -32748: reserved for module pointer -# -32744: extf2's GOT entry (undefined 0) -# -32740: extf3's GOT entry (PLT entry) -# -32736: extd2's GOT entry (copy reloc) -# -32732: extf1's GOT entry (.MIPS.stubs entry) -# -32728: extd1's GOT entry (undefined 0) -# -32724: extf4's GOT entry (PLT entry) -# -32620: extd4's GOT entry (undefined 0, reloc only) +# -32744: extd2's local GOT entry (copy reloc) +# -32740: extf3's local GOT entry (PLT entry) +# -32736: extf4's local GOT entry (PLT entry) +# -32732: extf2's global GOT entry (undefined 0) +# -32728: extf1's global GOT entry (.MIPS.stubs entry) +# -32724: extd1's global GOT entry (undefined 0) +# -32720: extd4's global GOT entry (undefined 0, reloc only) .* @@ -61,14 +61,14 @@ Disassembly of section \.text: 44020: 3c1c0006 lui gp,0x6 44024: 0399e021 addu gp,gp,t9 44028: 279c3fd0 addiu gp,gp,16336 - 4402c: 8f998024 lw t9,-32732\(gp\) - 44030: 8f848018 lw a0,-32744\(gp\) - 44034: 8f858028 lw a1,-32728\(gp\) + 4402c: 8f998028 lw t9,-32728\(gp\) + 44030: 8f848024 lw a0,-32732\(gp\) + 44034: 8f85802c lw a1,-32724\(gp\) 44038: 0320f809 jalr t9 - 4403c: 8f868020 lw a2,-32736\(gp\) + 4403c: 8f868018 lw a2,-32744\(gp\) 44040: 8f99801c lw t9,-32740\(gp\) 44044: 03200008 jr t9 - 44048: 8f84802c lw a0,-32724\(gp\) + 44048: 8f848020 lw a0,-32736\(gp\) 0004404c <f3>: 4404c: 03e00008 jr ra @@ -98,5 +98,5 @@ Disassembly of section \.MIPS\.stubs: 440a0: 8f998010 lw t9,-32752\(gp\) 440a4: 03e07821 move t3,ra 440a8: 0320f809 jalr t9 - 440ac: 24180008 li t8,8 + 440ac: 24180009 li t8,9 \.\.\. diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.gd index 8b6b5a0..d5d1b42 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.gd @@ -7,14 +7,17 @@ Primary GOT: 000a0000 -32752\(gp\) 00000000 Lazy resolver 000a0004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + Local entries: + Address Access Initial + 000a0008 -32744\(gp\) 000a2000 + 000a000c -32740\(gp\) 00043080 + 000a0010 -32736\(gp\) 00043060 + Global entries: Address Access Initial Sym\.Val\. Type Ndx Name - 000a0008 -32744\(gp\) 00000000 00000000 FUNC UND extf2 - 000a000c -32740\(gp\) 00000000 00000000 FUNC UND extf3 - 000a0010 -32736\(gp\) 000a2000 000a2000 OBJECT 16 extd2 - 000a0014 -32732\(gp\) 000440a0 000440a0 FUNC UND extf1 - 000a0018 -32728\(gp\) 00000000 00000000 OBJECT UND extd1 - 000a001c -32724\(gp\) 00000000 00000000 FUNC UND extf4 + 000a0014 -32732\(gp\) 00000000 00000000 FUNC UND extf2 + 000a0018 -32728\(gp\) 000440a0 000440a0 FUNC UND extf1 + 000a001c -32724\(gp\) 00000000 00000000 OBJECT UND extd1 000a0020 -32720\(gp\) 00000000 00000000 OBJECT UND extd4 @@ -27,6 +30,6 @@ PLT GOT: Entries: Address Initial Sym.Val. Type Ndx Name - 00081008 00043040 00000000 FUNC UND extf4 + 00081008 00043040 00043060 FUNC UND extf4 0008100c 00043040 00000000 FUNC UND extf5 00081010 00043040 00000000 FUNC UND extf3 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.nd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.nd index 07bfa6b..f93c741 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.nd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.nd @@ -1,17 +1,40 @@ Symbol table '\.dynsym' contains .*: +# +# extf4 is referenced by a JAL and .word. The former requires a PLT entry +# and the latter requires pointer equality, which means a symbol value is +# needed. #... -.*: 00000000 +0 +FUNC +GLOBAL +DEFAULT +UND +extf5 +.*: 0+43060 +0 +FUNC +GLOBAL +DEFAULT \[MIPS PLT\] +UND +extf4 +# +# extf5 is called but does not have its address taken. It needs a PLT +# but no symbol value should be set. +#... +.*: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf5 +# +# extd2 is referenced by %got, .word and %hi/%lo. The last pair forces +# a copy reloc. +# +.*: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2 +# +# extf3 is referenced by a JAL and a GOT CALL reloc. The JAL forces a PLT +# that the GOT CALL reloc will also use, but pointer equality isn't needed +# and so no symbol value should be set. +# +.*: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3 +# +# extd3 is referenced by .word and %hi/%lo. The latter pair forces +# a copy reloc. +#... +.*: 0+a2018 +28 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd3 +# # The index on the next line should correspond to MIPS_GOTSYM, # and the remaining symbols should have the same order as the # GOT layout given in the *.dd dump. -#... - *5: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2 - *6: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3 - *7: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2 - *8: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1 - *9: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1 - *10: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4 +# + *8: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2 + *9: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1 + *10: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1 *11: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4 #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.rd index 0fd5b7e..afeae98 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.rd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n32.rd @@ -2,13 +2,13 @@ Relocation section '\.rel\.dyn' at offset .* contains .*: * Offset * Info * Type * Sym\.Value * Sym\. Name 00000000 * 00000000 * R_MIPS_NONE * -000a2018 * [^ ]*7e * R_MIPS_COPY * 000a2018 * extd3 000a2000 * [^ ]*7e * R_MIPS_COPY * 000a2000 * extd2 +000a2018 * [^ ]*7e * R_MIPS_COPY * 000a2018 * extd3 000a1000 * [^ ]*03 * R_MIPS_REL32 * 00000000 * extd1 000a1014 * [^ ]*03 * R_MIPS_REL32 * 00000000 * extd4 Relocation section '\.rel\.plt' at offset .* contains .*: * Offset * Info * Type * Sym\.Value * Sym\. Name -00081008 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf4 +00081008 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00043060 * extf4 0008100c * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf5 00081010 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf3 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.ad b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.ad index 5550483..d8fc300 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.ad +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.ad @@ -16,10 +16,10 @@ Dynamic section at offset .* contains .*: 0x0+70000001 \(MIPS_RLD_VERSION\) * 1 0x0+70000005 \(MIPS_FLAGS\) * NOTPOT 0x0+70000006 \(MIPS_BASE_ADDRESS\) * 0x40000 - 0x0+7000000a \(MIPS_LOCAL_GOTNO\) * 2 + 0x0+7000000a \(MIPS_LOCAL_GOTNO\) * 5 0x0+70000011 \(MIPS_SYMTABNO\) * 12 0x0+70000012 \(MIPS_UNREFEXTNO\) * .* - 0x0+70000013 \(MIPS_GOTSYM\) * 0x5 + 0x0+70000013 \(MIPS_GOTSYM\) * 0x8 0x0+00000014 \(PLTREL\) * REL 0x0+00000017 \(JMPREL\) * 0x43050 0x0+00000002 \(PLTRELSZ\) * 48 \(bytes\) diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd index 2480623..fbb3615 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.dd @@ -1,14 +1,14 @@ # GOT layout: # # -32752: lazy resolution function -# -32744: reserved for module pointer -# -32736: extf2's GOT entry (undefined 0) -# -32728: extf3's GOT entry (PLT entry) -# -32720: extd2's GOT entry (copy reloc) -# -32712: extf1's GOT entry (.MIPS.stubs entry) -# -32704: extd1's GOT entry (undefined 0) -# -32696: extf4's GOT entry (PLT entry) -# -32688: extd4's GOT entry (undefined 0, reloc only) +# -32748: reserved for module pointer +# -32744: extd2's local GOT entry (copy reloc) +# -32740: extf3's local GOT entry (PLT entry) +# -32736: extf4's local GOT entry (PLT entry) +# -32732: extf2's global GOT entry (undefined 0) +# -32728: extf1's global GOT entry (.MIPS.stubs entry) +# -32724: extd1's global GOT entry (undefined 0) +# -32720: extd4's global GOT entry (undefined 0, reloc only) .* @@ -61,14 +61,14 @@ Disassembly of section \.text: 44020: 3c1c0006 lui gp,0x6 44024: 0399e021 addu gp,gp,t9 44028: 279c3fd0 addiu gp,gp,16336 - 4402c: df998038 ld t9,-32712\(gp\) - 44030: df848020 ld a0,-32736\(gp\) - 44034: df858040 ld a1,-32704\(gp\) + 4402c: df998040 ld t9,-32704\(gp\) + 44030: df848038 ld a0,-32712\(gp\) + 44034: df858048 ld a1,-32696\(gp\) 44038: 0320f809 jalr t9 - 4403c: df868030 ld a2,-32720\(gp\) + 4403c: df868020 ld a2,-32736\(gp\) 44040: df998028 ld t9,-32728\(gp\) 44044: 03200008 jr t9 - 44048: df848048 ld a0,-32696\(gp\) + 44048: df848030 ld a0,-32720\(gp\) 0+4404c <f3>: 4404c: 03e00008 jr ra @@ -98,5 +98,5 @@ Disassembly of section \.MIPS\.stubs: 440a0: df998010 ld t9,-32752\(gp\) 440a4: 03e0782d move t3,ra 440a8: 0320f809 jalr t9 - 440ac: 64180008 daddiu t8,zero,8 + 440ac: 64180009 daddiu t8,zero,9 \.\.\. diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.gd index 767d150..46cbcdd 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.gd @@ -1,32 +1,35 @@ Primary GOT: - Canonical gp value: 00000000000a7ff0 + Canonical gp value: 0+0a7ff0 Reserved entries: - Address Access Initial Purpose - 00000000000a0000 -32752\(gp\) 0000000000000000 Lazy resolver - 00000000000a0008 -32744\(gp\) 8000000000000000 Module pointer \(GNU extension\) + * Address * Access * Initial Purpose + 0+0a0000 -32752\(gp\) 0+ Lazy resolver + 0+0a0008 -32744\(gp\) 8000000000000000 Module pointer \(GNU extension\) + + Local entries: + * Address * Access * Initial + 0+0a0010 -32736\(gp\) 0+0a2000 + 0+0a0018 -32728\(gp\) 0+0430c0 + 0+0a0020 -32720\(gp\) 0+0430a0 Global entries: - Address Access Initial Sym\.Val\. Type Ndx Name - 00000000000a0010 -32736\(gp\) 0000000000000000 0000000000000000 FUNC UND extf2 - 00000000000a0018 -32728\(gp\) 0000000000000000 0000000000000000 FUNC UND extf3 - 00000000000a0020 -32720\(gp\) 00000000000a2000 00000000000a2000 OBJECT 16 extd2 - 00000000000a0028 -32712\(gp\) 00000000000440a0 00000000000440a0 FUNC UND extf1 - 00000000000a0030 -32704\(gp\) 0000000000000000 0000000000000000 OBJECT UND extd1 - 00000000000a0038 -32696\(gp\) 0000000000000000 0000000000000000 FUNC UND extf4 - 00000000000a0040 -32688\(gp\) 0000000000000000 0000000000000000 OBJECT UND extd4 + * Address * Access * Initial * Sym\.Val\. * Type * Ndx Name + 0+0a0028 -32712\(gp\) 0+000000 0+000000 FUNC UND extf2 + 0+0a0030 -32704\(gp\) 0+0440a0 0+0440a0 FUNC UND extf1 + 0+0a0038 -32696\(gp\) 0+000000 0+000000 OBJECT UND extd1 + 0+0a0040 -32688\(gp\) 0+000000 0+000000 OBJECT UND extd4 PLT GOT: Reserved entries: - Address Initial Purpose - 0000000000081000 0000000000000000 PLT lazy resolver - 0000000000081008 0000000000000000 Module pointer + * Address * Initial * Purpose + 0+081000 0+ PLT lazy resolver + 0+081008 0+ Module pointer Entries: - Address Initial Sym.Val. Type Ndx Name - 0000000000081010 0000000000043080 0000000000000000 FUNC UND extf4 - 0000000000081018 0000000000043080 0000000000000000 FUNC UND extf5 - 0000000000081020 0000000000043080 0000000000000000 FUNC UND extf3 + * Address * Initial * Sym.Val. * Type * Ndx Name + 0+081010 0+043080 0+0430a0 FUNC UND extf4 + 0+081018 0+043080 0+000000 FUNC UND extf5 + 0+081020 0+043080 0+000000 FUNC UND extf3 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.nd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.nd index 867389b..63b3fc4 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.nd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.nd @@ -1,17 +1,40 @@ Symbol table '\.dynsym' contains .*: +# +# extf4 is referenced by a JAL and .word. The former requires a PLT entry +# and the latter requires pointer equality, which means a symbol value is +# needed. +#... +.*: 0+430a0 +0 +FUNC +GLOBAL +DEFAULT \[MIPS PLT\] +UND +extf4 +# +# extf5 is called but does not have its address taken. It needs a PLT +# but no symbol value should be set. #... .*: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf5 +# +# extd2 is referenced by %got, .word and %hi/%lo. The last pair forces +# a copy reloc. +# +.*: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2 +# +# extf3 is referenced by a JAL and a GOT CALL reloc. The JAL forces a PLT +# that the GOT CALL reloc will also use, but pointer equality isn't needed +# and so no symbol value should be set. +# +.*: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3 +# +# extd3 is referenced by .word and %hi/%lo. The latter pair forces +# a copy reloc. +#... +.*: 0+a2018 +28 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd3 +# # The index on the next line should correspond to MIPS_GOTSYM, # and the remaining symbols should have the same order as the # GOT layout given in the *.dd dump. -#... - *5: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2 - *6: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3 - *7: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2 - *8: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1 - *9: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1 - *10: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4 +# + *8: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2 + *9: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1 + *10: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1 *11: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4 #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.rd index 666785e..2b25b0a 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.rd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-n64.rd @@ -4,10 +4,10 @@ Relocation section '\.rel\.dyn' at offset .* contains .*: 0+00000 * 0+ * R_MIPS_NONE * *Type2: R_MIPS_NONE * *Type3: R_MIPS_NONE * -0+a2018 * [^ ]*7e * R_MIPS_COPY * 0+a2018 * extd3 +0+a2000 * [^ ]*7e * R_MIPS_COPY * 0+a2000 * extd2 *Type2: R_MIPS_NONE * *Type3: R_MIPS_NONE * -0+a2000 * [^ ]*7e * R_MIPS_COPY * 0+a2000 * extd2 +0+a2018 * [^ ]*7e * R_MIPS_COPY * 0+a2018 * extd3 *Type2: R_MIPS_NONE * *Type3: R_MIPS_NONE * 0+a1000 * [^ ]*03 * R_MIPS_REL32 * 0+00000 * extd1 @@ -19,7 +19,7 @@ Relocation section '\.rel\.dyn' at offset .* contains .*: Relocation section '\.rel\.plt' at offset .* contains .*: * Offset * Info * Type * Sym\. Value * Sym\. Name -0+81010 * [^ ]*7f * R_MIPS_JUMP_SLOT * 0+00000 * extf4 +0+81010 * [^ ]*7f * R_MIPS_JUMP_SLOT * 0+430a0 * extf4 *Type2: R_MIPS_NONE * *Type3: R_MIPS_NONE * 0+81018 * [^ ]*7f * R_MIPS_JUMP_SLOT * 0+00000 * extf5 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.ad b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.ad index fab5581..5df3c6c 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.ad +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.ad @@ -16,10 +16,10 @@ Dynamic section at offset .* contains .*: 0x70000001 \(MIPS_RLD_VERSION\) * 1 0x70000005 \(MIPS_FLAGS\) * NOTPOT 0x70000006 \(MIPS_BASE_ADDRESS\) * 0x40000 - 0x7000000a \(MIPS_LOCAL_GOTNO\) * 2 + 0x7000000a \(MIPS_LOCAL_GOTNO\) * 5 0x70000011 \(MIPS_SYMTABNO\) * 12 0x70000012 \(MIPS_UNREFEXTNO\) * .* - 0x70000013 \(MIPS_GOTSYM\) * 0x5 + 0x70000013 \(MIPS_GOTSYM\) * 0x8 0x00000014 \(PLTREL\) * REL 0x00000017 \(JMPREL\) * 0x43028 0x00000002 \(PLTRELSZ\) * 24 \(bytes\) diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd index 7f101ac..e10a0af 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.dd @@ -2,13 +2,13 @@ # # -32752: lazy resolution function # -32748: reserved for module pointer -# -32744: extf2's GOT entry (undefined 0) -# -32740: extf3's GOT entry (PLT entry) -# -32736: extd2's GOT entry (copy reloc) -# -32732: extf1's GOT entry (.MIPS.stubs entry) -# -32728: extd1's GOT entry (undefined 0) -# -32724: extf4's GOT entry (PLT entry) -# -32620: extd4's GOT entry (undefined 0, reloc only) +# -32744: extd2's local GOT entry (copy reloc) +# -32740: extf3's local GOT entry (PLT entry) +# -32736: extf4's local GOT entry (PLT entry) +# -32732: extf2's global GOT entry (undefined 0) +# -32728: extf1's global GOT entry (.MIPS.stubs entry) +# -32724: extd1's global GOT entry (undefined 0) +# -32720: extd4's global GOT entry (undefined 0, reloc only) .* @@ -61,14 +61,14 @@ Disassembly of section \.text: 44020: 3c1c0006 lui gp,0x6 44024: 279c3fd0 addiu gp,gp,16336 44028: 0399e021 addu gp,gp,t9 - 4402c: 8f998024 lw t9,-32732\(gp\) - 44030: 8f848018 lw a0,-32744\(gp\) - 44034: 8f858028 lw a1,-32728\(gp\) + 4402c: 8f998028 lw t9,-32728\(gp\) + 44030: 8f848024 lw a0,-32732\(gp\) + 44034: 8f85802c lw a1,-32724\(gp\) 44038: 0320f809 jalr t9 - 4403c: 8f868020 lw a2,-32736\(gp\) + 4403c: 8f868018 lw a2,-32744\(gp\) 44040: 8f99801c lw t9,-32740\(gp\) 44044: 03200008 jr t9 - 44048: 8f84802c lw a0,-32724\(gp\) + 44048: 8f848020 lw a0,-32736\(gp\) 0004404c <f3>: 4404c: 03e00008 jr ra @@ -98,5 +98,5 @@ Disassembly of section \.MIPS\.stubs: 440a0: 8f998010 lw t9,-32752\(gp\) 440a4: 03e07821 move t7,ra 440a8: 0320f809 jalr t9 - 440ac: 24180008 li t8,8 + 440ac: 24180009 li t8,9 \.\.\. diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.gd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.gd index 8b6b5a0..d5d1b42 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.gd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.gd @@ -7,14 +7,17 @@ Primary GOT: 000a0000 -32752\(gp\) 00000000 Lazy resolver 000a0004 -32748\(gp\) 80000000 Module pointer \(GNU extension\) + Local entries: + Address Access Initial + 000a0008 -32744\(gp\) 000a2000 + 000a000c -32740\(gp\) 00043080 + 000a0010 -32736\(gp\) 00043060 + Global entries: Address Access Initial Sym\.Val\. Type Ndx Name - 000a0008 -32744\(gp\) 00000000 00000000 FUNC UND extf2 - 000a000c -32740\(gp\) 00000000 00000000 FUNC UND extf3 - 000a0010 -32736\(gp\) 000a2000 000a2000 OBJECT 16 extd2 - 000a0014 -32732\(gp\) 000440a0 000440a0 FUNC UND extf1 - 000a0018 -32728\(gp\) 00000000 00000000 OBJECT UND extd1 - 000a001c -32724\(gp\) 00000000 00000000 FUNC UND extf4 + 000a0014 -32732\(gp\) 00000000 00000000 FUNC UND extf2 + 000a0018 -32728\(gp\) 000440a0 000440a0 FUNC UND extf1 + 000a001c -32724\(gp\) 00000000 00000000 OBJECT UND extd1 000a0020 -32720\(gp\) 00000000 00000000 OBJECT UND extd4 @@ -27,6 +30,6 @@ PLT GOT: Entries: Address Initial Sym.Val. Type Ndx Name - 00081008 00043040 00000000 FUNC UND extf4 + 00081008 00043040 00043060 FUNC UND extf4 0008100c 00043040 00000000 FUNC UND extf5 00081010 00043040 00000000 FUNC UND extf3 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.nd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.nd index 07bfa6b..f93c741 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.nd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.nd @@ -1,17 +1,40 @@ Symbol table '\.dynsym' contains .*: +# +# extf4 is referenced by a JAL and .word. The former requires a PLT entry +# and the latter requires pointer equality, which means a symbol value is +# needed. #... -.*: 00000000 +0 +FUNC +GLOBAL +DEFAULT +UND +extf5 +.*: 0+43060 +0 +FUNC +GLOBAL +DEFAULT \[MIPS PLT\] +UND +extf4 +# +# extf5 is called but does not have its address taken. It needs a PLT +# but no symbol value should be set. +#... +.*: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf5 +# +# extd2 is referenced by %got, .word and %hi/%lo. The last pair forces +# a copy reloc. +# +.*: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2 +# +# extf3 is referenced by a JAL and a GOT CALL reloc. The JAL forces a PLT +# that the GOT CALL reloc will also use, but pointer equality isn't needed +# and so no symbol value should be set. +# +.*: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3 +# +# extd3 is referenced by .word and %hi/%lo. The latter pair forces +# a copy reloc. +#... +.*: 0+a2018 +28 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd3 +# # The index on the next line should correspond to MIPS_GOTSYM, # and the remaining symbols should have the same order as the # GOT layout given in the *.dd dump. -#... - *5: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2 - *6: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf3 - *7: 0+a2000 +24 +OBJECT +GLOBAL +DEFAULT +[0-9]+ +extd2 - *8: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1 - *9: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1 - *10: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf4 +# + *8: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND +extf2 + *9: 0+440a0 +0 +FUNC +GLOBAL +DEFAULT +UND +extf1 + *10: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd1 *11: 0+ +0 +OBJECT +GLOBAL +DEFAULT +UND +extd4 #pass diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.rd b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.rd index 0fd5b7e..afeae98 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.rd +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6-o32.rd @@ -2,13 +2,13 @@ Relocation section '\.rel\.dyn' at offset .* contains .*: * Offset * Info * Type * Sym\.Value * Sym\. Name 00000000 * 00000000 * R_MIPS_NONE * -000a2018 * [^ ]*7e * R_MIPS_COPY * 000a2018 * extd3 000a2000 * [^ ]*7e * R_MIPS_COPY * 000a2000 * extd2 +000a2018 * [^ ]*7e * R_MIPS_COPY * 000a2018 * extd3 000a1000 * [^ ]*03 * R_MIPS_REL32 * 00000000 * extd1 000a1014 * [^ ]*03 * R_MIPS_REL32 * 00000000 * extd4 Relocation section '\.rel\.plt' at offset .* contains .*: * Offset * Info * Type * Sym\.Value * Sym\. Name -00081008 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf4 +00081008 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00043060 * extf4 0008100c * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf5 00081010 * [^ ]*7f * R_MIPS_JUMP_SLOT * 00000000 * extf3 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6.ld index d9f276b..c819816 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/pic-and-nonpic-6.ld @@ -37,4 +37,6 @@ SECTIONS . = 0xa2000; .bss : { *(.dynbss) } + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/region1.t b/binutils-2.24/ld/testsuite/ld-mips-elf/region1.t index 13077ab..1f20e56 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/region1.t +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/region1.t @@ -9,4 +9,6 @@ SECTIONS .text : { *(.text) } > TEXTMEM .data : { *(.data) } > DATAMEM .bss : { *(.bss) } > DATAMEM + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-n32.d b/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-n32.d index 43c2632..9951615 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-n32.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-n32.d @@ -10,6 +10,6 @@ Relocation section '.rel.dyn' at offset .* contains 2 entries: [0-9a-f ]+R_MIPS_REL32 Hex dump of section '.text': - 0x000002a0 00000000 00000000 00000000 00000000 ................ - 0x000002b0 000002b0 00000000 00000000 00000000 ................ - 0x000002c0 00000000 00000000 00000000 00000000 ................ + 0x000002e0 00000000 00000000 00000000 00000000 ................ + 0x000002f0 000002f0 00000000 00000000 00000000 ................ + 0x00000300 00000000 00000000 00000000 00000000 ................ diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-o32.d b/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-o32.d index 0103d79..742cdaa 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-o32.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/rel32-o32.d @@ -10,6 +10,6 @@ Relocation section '.rel.dyn' at offset .* contains 2 entries: [0-9a-f ]+R_MIPS_REL32 Hex dump of section '.text': - 0x000002a0 00000000 00000000 00000000 00000000 ................ - 0x000002b0 000002b0 00000000 00000000 00000000 ................ - 0x000002c0 00000000 00000000 00000000 00000000 ................ + 0x000002e0 00000000 00000000 00000000 00000000 ................ + 0x000002f0 000002f0 00000000 00000000 00000000 ................ + 0x00000300 00000000 00000000 00000000 00000000 ................ diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/rel64.d b/binutils-2.24/ld/testsuite/ld-mips-elf/rel64.d index 89df314..01bffa3 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/rel64.d +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/rel64.d @@ -14,6 +14,6 @@ Relocation section '.rel.dyn' at offset .* contains 2 entries: +Type3: R_MIPS_NONE Hex dump of section '.text': - 0x00000400 00000000 00000000 00000000 00000000 ................ - 0x00000410 00000000 00000410 00000000 00000000 ................ - 0x00000420 00000000 00000000 00000000 00000000 ................ + 0x00000450 00000000 00000000 00000000 00000000 ................ + 0x00000460 00000000 00000460 00000000 00000000 ................ + 0x00000470 00000000 00000000 00000000 00000000 ................ diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld index 0a58e6f..dec5ca1 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld @@ -13,5 +13,5 @@ SECTIONS HIDDEN (_gp = . + 0x7ff0); .got : { *(.got) } - /DISCARD/ : { *(.reginfo) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/tls-hidden3.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/tls-hidden3.ld index 8e0d0aa..5609a4b 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/tls-hidden3.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/tls-hidden3.ld @@ -19,7 +19,7 @@ SECTIONS . = ALIGN (0x400); .tdata : { *(.tdata) } - /DISCARD/ : { *(.reginfo) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } } VERSION diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/tls-multi-got-1.r b/binutils-2.24/ld/testsuite/ld-mips-elf/tls-multi-got-1.r index aea3d2d..45bd791 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/tls-multi-got-1.r +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/tls-multi-got-1.r @@ -15,7 +15,7 @@ Dynamic section at offset .* contains 18 entries: 0x70000006 \(MIPS_BASE_ADDRESS\) 0x0 0x7000000a \(MIPS_LOCAL_GOTNO\) 2 0x70000011 \(MIPS_SYMTABNO\) 20011 - 0x70000012 \(MIPS_UNREFEXTNO\) 10 + 0x70000012 \(MIPS_UNREFEXTNO\) 11 0x70000013 \(MIPS_GOTSYM\) 0xb 0x0000001e \(FLAGS\) STATIC_TLS 0x00000000 \(NULL\) 0x0 diff --git a/binutils-2.24/ld/testsuite/ld-mips-elf/vxworks1.ld b/binutils-2.24/ld/testsuite/ld-mips-elf/vxworks1.ld index 8fe3c48..d9f8621 100644 --- a/binutils-2.24/ld/testsuite/ld-mips-elf/vxworks1.ld +++ b/binutils-2.24/ld/testsuite/ld-mips-elf/vxworks1.ld @@ -28,5 +28,5 @@ SECTIONS . = ALIGN (0x400); .bss : { *(.bss) *(.dynbss) } - /DISCARD/ : { *(.reginfo) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/ld-scripts/overlay-size.t b/binutils-2.24/ld/testsuite/ld-scripts/overlay-size.t index 0d9af35..68c0986 100644 --- a/binutils-2.24/ld/testsuite/ld-scripts/overlay-size.t +++ b/binutils-2.24/ld/testsuite/ld-scripts/overlay-size.t @@ -60,5 +60,5 @@ SECTIONS end_of_data_overlays = . ; . = 0x8000; - /DISCARD/ : { *(.reginfo) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } } diff --git a/binutils-2.24/ld/testsuite/lib/ld-lib.exp b/binutils-2.24/ld/testsuite/lib/ld-lib.exp index 64ac7b2..d1d8d21 100644 --- a/binutils-2.24/ld/testsuite/lib/ld-lib.exp +++ b/binutils-2.24/ld/testsuite/lib/ld-lib.exp @@ -331,10 +331,12 @@ proc default_ld_compile { cc source object } { proc default_ld_assemble { as in_flags source object } { global ASFLAGS global host_triplet + global srcdir + global subdir if ![info exists ASFLAGS] { set ASFLAGS "" } - set flags [big_or_little_endian] + set flags "[big_or_little_endian] -I$srcdir/$subdir" set exec_output [run_host_cmd "$as" "$flags $in_flags $ASFLAGS -o $object $source"] set exec_output [prune_warnings $exec_output] if [string match "" $exec_output] then { @@ -489,6 +491,11 @@ proc ld_simple_link_defsyms {} { # ld_after_inputfiles: FLAGS # Similar to "ld", but put after all input files. # +# objcopy_objects: FLAGS +# Run objcopy with the specified flags after assembling any source +# that has the special marker RUN_OBJCOPY in the source specific +# flags. +# # objcopy_linked_file: FLAGS # Run objcopy on the linked file with the specified flags. # This lets you transform the linked file using objcopy, before the @@ -597,6 +604,7 @@ proc run_dump_test { name {extra_options {}} } { set opts(error) {} set opts(warning) {} set opts(objcopy_linked_file) {} + set opts(objcopy_objects) {} foreach i $opt_array { set opt_name [lindex $i 0] @@ -776,6 +784,12 @@ proc run_dump_test { name {extra_options {}} } { for { set i 0 } { $i < [llength $sourcefiles] } { incr i } { set sourcefile [lindex $sourcefiles $i] set sourceasflags [lindex $asflags $i] + set run_objcopy_objects 0 + + if { [string match "*RUN_OBJCOPY*" $sourceasflags] } { + set run_objcopy_objects 1 + } + regsub "RUN_OBJCOPY" $sourceasflags "" sourceasflags set objfile "tmpdir/dump$i.o" catch "exec rm -f $objfile" exec_output @@ -799,6 +813,30 @@ proc run_dump_test { name {extra_options {}} } { fail $testname return } + + if { $run_objcopy_objects } { + set cmd "$OBJCOPY $opts(objcopy_objects) $objfile" + + send_log "$cmd\n" + set cmdret [remote_exec host [concat sh -c [list "$cmd 2>&1"]] \ + "" "/dev/null" "objcopy.tmp"] + remote_upload host "objcopy.tmp" + set comp_output [prune_warnings [file_contents "objcopy.tmp"]] + remote_file host delete "objcopy.tmp" + remote_file build delete "objcopy.tmp" + + if { [lindex $cmdret 0] != 0 \ + || ![string match "" $comp_output] } { + send_log "$comp_output\n" + verbose "$comp_output" 3 + + set exitstat "succeeded" + if { $cmdret != 0 } { set exitstat "failed" } + verbose -log "$exitstat with: <$comp_output>" + fail $testname + return + } + } } set expmsg $opts(error) |