diff options
Diffstat (limited to 'binutils-2.21/ld/testsuite/ld-arm')
317 files changed, 8905 insertions, 0 deletions
diff --git a/binutils-2.21/ld/testsuite/ld-arm/arch-v6.s b/binutils-2.21/ld/testsuite/ld-arm/arch-v6.s new file mode 100644 index 0000000..88aef8d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arch-v6.s @@ -0,0 +1,4 @@ + .cpu arm1136jfs + + @ Tag_CPU_raw_name + .eabi_attribute 4, "arch_v6" diff --git a/binutils-2.21/ld/testsuite/ld-arm/arch-v6k.s b/binutils-2.21/ld/testsuite/ld-arm/arch-v6k.s new file mode 100644 index 0000000..0bfec94 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arch-v6k.s @@ -0,0 +1,4 @@ + .cpu mpcore + + @ Tag_CPU_raw_name + .eabi_attribute 4, "arch_v6k" diff --git a/binutils-2.21/ld/testsuite/ld-arm/arch-v6t2.s b/binutils-2.21/ld/testsuite/ld-arm/arch-v6t2.s new file mode 100644 index 0000000..1148b20 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arch-v6t2.s @@ -0,0 +1,4 @@ + .cpu arm1156t2f-s + + @ Tag_CPU_raw_name + .eabi_attribute 4, "arch_v6t2" diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-app-abs32.d b/binutils-2.21/ld/testsuite/ld-arm/arm-app-abs32.d new file mode 100644 index 0000000..dbee189 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-app-abs32.d @@ -0,0 +1,29 @@ + +tmpdir/arm-app-abs32: file format elf32-(little|big)arm +architecture: arm, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address .* + +Disassembly of section .plt: + +.* <.plt>: + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x10> + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* .* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; .* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* +Disassembly of section .text: + +.* <_start>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: e59f0004 ldr r0, \[pc, #4\] ; .* <_start\+0x14> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: .* .* + +.* <app_func2>: + .*: e12fff1e bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-app-abs32.r b/binutils-2.21/ld/testsuite/ld-arm/arm-app-abs32.r new file mode 100644 index 0000000..08d668c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-app-abs32.r @@ -0,0 +1,8 @@ + +tmpdir/arm-app-abs32: file format elf32-(little|big)arm + +DYNAMIC RELOCATION RECORDS +OFFSET TYPE VALUE +.* R_ARM_JUMP_SLOT lib_func1 + + diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-app-abs32.s b/binutils-2.21/ld/testsuite/ld-arm/arm-app-abs32.s new file mode 100644 index 0000000..a1cf526 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-app-abs32.s @@ -0,0 +1,16 @@ + .text + .globl _start +_start: + mov ip, sp + stmdb sp!, {r11, ip, lr, pc} + ldr a1, .Lval + ldmia sp, {r11, sp, lr} + bx lr + +.Lval: + .long lib_func1 + + .globl app_func2 +app_func2: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-app-movw.s b/binutils-2.21/ld/testsuite/ld-arm/arm-app-movw.s new file mode 100644 index 0000000..55ced97 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-app-movw.s @@ -0,0 +1,11 @@ + .text + .globl _start +_start: + movw r0, #:lower16:data_obj + movt r0, #:upper16:data_obj + movw r0, #:lower16:lib_func1 + movt r0, #:upper16:lib_func1 + + .globl app_func2 +app_func2: + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-app.d b/binutils-2.21/ld/testsuite/ld-arm/arm-app.d new file mode 100644 index 0000000..7730e90 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-app.d @@ -0,0 +1,35 @@ + +tmpdir/arm-app: file format elf32-(little|big)arm +architecture: arm, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x.* + +Disassembly of section .plt: + +.* <.plt>: + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x10> + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* +Disassembly of section .text: + +.* <_start>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: eb000001 bl .* <app_func> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + +.* <app_func>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: ebfffff4 bl .* <_start-0xc> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + +.* <app_func2>: + .*: e12fff1e bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-app.r b/binutils-2.21/ld/testsuite/ld-arm/arm-app.r new file mode 100644 index 0000000..4b25e70 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-app.r @@ -0,0 +1,9 @@ + +tmpdir/arm-app.*: file format elf32-(little|big)arm + +DYNAMIC RELOCATION RECORDS +OFFSET TYPE VALUE +.* R_ARM_COPY data_obj +.* R_ARM_JUMP_SLOT lib_func1 + + diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-app.s b/binutils-2.21/ld/testsuite/ld-arm/arm-app.s new file mode 100644 index 0000000..8f6d27c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-app.s @@ -0,0 +1,23 @@ + .text + .globl _start +_start: + mov ip, sp + stmdb sp!, {r11, ip, lr, pc} + bl app_func + ldmia sp, {r11, sp, lr} + bx lr + + .globl app_func +app_func: + mov ip, sp + stmdb sp!, {r11, ip, lr, pc} + bl lib_func1 + ldmia sp, {r11, sp, lr} + bx lr + + .globl app_func2 +app_func2: + bx lr + + .data + .long data_obj diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-be8.d b/binutils-2.21/ld/testsuite/ld-arm/arm-be8.d new file mode 100644 index 0000000..16090b3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-be8.d @@ -0,0 +1,16 @@ + +.*: file format.* + +Disassembly of section .text: + +00008000 <arm>: + 8000: e3a00000 mov r0, #0 + 8004: e12fff1e bx lr + +00008008 <thumb>: + 8008: 46c0 nop ; \(mov r8, r8\) + 800a: 4770 bx lr + 800c: f7ff fffc bl 8008 <thumb> + +00008010 <data>: + 8010: 12345678 .word 0x12345678 diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-be8.s b/binutils-2.21/ld/testsuite/ld-arm/arm-be8.s new file mode 100644 index 0000000..871b691 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-be8.s @@ -0,0 +1,14 @@ +.arch armv6 +.text +arm: +mov r0, #0 +$m: +bx lr +.thumb +.thumb_func +thumb: +nop +bx lr +bl thumb +data: +.word 0x12345678 diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-call.d b/binutils-2.21/ld/testsuite/ld-arm/arm-call.d new file mode 100644 index 0000000..a320743 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-call.d @@ -0,0 +1,58 @@ + +.*: file format.* + +Disassembly of section .text: + +00008000 <_start>: + 8000: eb00000d bl 803c <arm> + 8004: fa00000d blx 8040 <t1> + 8008: fb00000c blx 8042 <t2> + 800c: fb00000d blx 804a <t5> + 8010: fa00000a blx 8040 <t1> + 8014: fb000009 blx 8042 <t2> + 8018: ea000010 b 8060 <__t1_from_arm> + 801c: ea000011 b 8068 <__t2_from_arm> + 8020: 1b00000e blne 8060 <__t1_from_arm> + 8024: 1b00000f blne 8068 <__t2_from_arm> + 8028: 1b000003 blne 803c <arm> + 802c: eb000002 bl 803c <arm> + 8030: faffffff blx 8034 <thumblocal> + +00008034 <thumblocal>: + 8034: 4770 bx lr + +00008036 <t3>: + 8036: 4770 bx lr + +00008038 <t4>: + 8038: 4770 bx lr + 803a: 46c0 nop ; \(mov r8, r8\) + +0000803c <arm>: + 803c: e12fff1e bx lr + +00008040 <t1>: + 8040: 4770 bx lr + +00008042 <t2>: + 8042: f7ff fff8 bl 8036 <t3> + 8046: f7ff fff7 bl 8038 <t4> + +0000804a <t5>: + 804a: f000 f801 bl 8050 <local_thumb> + 804e: 46c0 nop ; \(mov r8, r8\) + +00008050 <local_thumb>: + 8050: f7ff fff1 bl 8036 <t3> + 8054: f7ff efd4 blx 8000 <_start> + 8058: f7ff efd2 blx 8000 <_start> + 805c: 0000 movs r0, r0 + ... + +00008060 <__t1_from_arm>: + 8060: e51ff004 ldr pc, \[pc, #-4\] ; 8064 <__t1_from_arm\+0x4> + 8064: 00008041 .word 0x00008041 + +00008068 <__t2_from_arm>: + 8068: e51ff004 ldr pc, \[pc, #-4\] ; 806c <__t2_from_arm\+0x4> + 806c: 00008043 .word 0x00008043 diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-call1.s b/binutils-2.21/ld/testsuite/ld-arm/arm-call1.s new file mode 100644 index 0000000..e6ea1f2 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-call1.s @@ -0,0 +1,30 @@ +# Test R_ARM_CALL and R_ARM_JUMP24 relocations and interworking + .text + .arch armv5t + .global _start +_start: + bl arm + bl t1 + bl t2 + bl t5 + blx t1 + blx t2 + b t1 + b t2 + blne t1 + blne t2 + blne arm + blx arm + blx thumblocal + .thumb +thumblocal: + bx lr + .global t3 + .thumb_func +t3: + bx lr + .global t4 + .thumb_func +t4: + bx lr + nop diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-call2.s b/binutils-2.21/ld/testsuite/ld-arm/arm-call2.s new file mode 100644 index 0000000..30ae349 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-call2.s @@ -0,0 +1,24 @@ + .text + .arch armv5t + .global arm + .global t1 + .global t2 + .global t5 +arm: + bx lr + .thumb + .thumb_func +t1: + bx lr + .thumb_func +t2: + bl t3 + bl t4 + .thumb_func +t5: + bl local_thumb + nop +local_thumb: + blx t3 + bl _start + blx _start diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-dyn.ld b/binutils-2.21/ld/testsuite/ld-arm/arm-dyn.ld new file mode 100644 index 0000000..736fb17 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-dyn.ld @@ -0,0 +1,194 @@ +/* Script for -z combreloc: combine and sort reloc sections */ +OUTPUT_ARCH(arm) +ENTRY(_start) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x8000); . = 0x8000; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.dyn : + { + *(.rel.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rel.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rel.data.rel.ro*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rel.dtors) + *(.rel.got) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + } + .rela.dyn : + { + *(.rela.init) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rela.fini) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rela.ctors) + *(.rela.dtors) + *(.rela.got) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : + { + KEEP (*(.init)) + } =0 + .plt : { *(.plt) } + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.glue_7t) *(.glue_7) + } =0 + .fini : + { + KEEP (*(.fini)) + } =0 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } + .rodata1 : { *(.rodata1) } + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } + PROVIDE_HIDDEN (__exidx_end = .); + .eh_frame_hdr : { *(.eh_frame_hdr) } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN (0x8000) - ((0x8000 - .) & (0x8000 - 1)); . = DATA_SEGMENT_ALIGN (0x8000, 0x1000); + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + . = ALIGN(32 / 8); + PROVIDE (__preinit_array_start = .); + .preinit_array : { KEEP (*(.preinit_array)) } + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { KEEP (*(.init_array)) } + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { KEEP (*(.fini_array)) } + PROVIDE (__fini_array_end = .); + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + .jcr : { KEEP (*(.jcr)) } + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } + .dynamic : { *(.dynamic) } + .got : { *(.got.plt) *(.got) } + .data : + { + __data_start = . ; + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } + .data1 : { *(.data1) } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + __bss_start__ = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); + } + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + /DISCARD/ : { *(.note.GNU-stack) } +} + + diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-elf.exp b/binutils-2.21/ld/testsuite/ld-arm/arm-elf.exp new file mode 100644 index 0000000..0b1cdaa --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-elf.exp @@ -0,0 +1,547 @@ +# Expect script for various ARM ELF tests. +# Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 +# Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +# MA 02110-1301, USA. +# + +if {[istarget "arm-*-vxworks"]} { + set armvxworkstests { + {"VxWorks shared library test 1" "-shared -Tvxworks1.ld" + "" {vxworks1-lib.s} + {{readelf --relocs vxworks1-lib.rd} {objdump -dr vxworks1-lib.dd} + {readelf --symbols vxworks1-lib.nd} {readelf -d vxworks1-lib.td}} + "libvxworks1.so"} + {"VxWorks executable test 1 (dynamic)" \ + "tmpdir/libvxworks1.so -Tvxworks1.ld -q --force-dynamic" + "" {vxworks1.s} + {{readelf --relocs vxworks1.rd} {objdump -dr vxworks1.dd}} + "vxworks1"} + {"VxWorks executable test 2 (dynamic)" \ + "-Tvxworks1.ld -q --force-dynamic" + "" {vxworks2.s} + {{readelf --segments vxworks2.sd}} + "vxworks2"} + {"VxWorks executable test 2 (static)" + "-Tvxworks1.ld" + "" {vxworks2.s} + {{readelf --segments vxworks2-static.sd}} + "vxworks2"} + } + run_ld_link_tests $armvxworkstests + run_dump_test "vxworks1-static" + run_dump_test "emit-relocs1-vxworks" +} + +if { [istarget "arm*-*-symbianelf*"] } { + run_dump_test "symbian-seg1" +} + +# Exclude non-ARM-ELF targets. + +if { ![is_elf_format] || ![istarget "arm*-*-*"] } { + return +} + +# List contains test-items with 3 items followed by 2 lists and one more item: +# 0:name 1:ld options 2:assembler options +# 3:filenames of assembler files 4: action and options. 5: name of output file + +# Actions: +# objdump: Apply objdump options on result. Compare with regex (last arg). +# nm: Apply nm options on result. Compare with regex (last arg). +# readelf: Apply readelf options on result. Compare with regex (last arg). + +set armelftests { + {"Group relocations" "-Ttext 0x8000 --section-start zero=0x0 --section-start alpha=0xeef0 --section-start beta=0xffeef0" "" {group-relocs.s} + {{objdump -dr group-relocs.d}} + "group-relocs"} + {"Thumb-1 BL" "-Ttext 0x1000 --section-start .foo=0x401000" "" {thumb1-bl.s} + {{objdump -dr thumb1-bl.d}} + "thumb1-bl"} + {"Simple non-PIC shared library" "-shared" "" {arm-lib.s} + {{objdump -fdw arm-lib.d} {objdump -Rw arm-lib.r}} + "arm-lib.so"} + {"Simple PIC shared library" "-shared" "" {arm-lib-plt32.s} + {{objdump -fdw arm-lib-plt32.d} {objdump -Rw arm-lib-plt32.r}} + "arm-lib-plt32.so"} + {"Simple dynamic application" "tmpdir/arm-lib.so" "" {arm-app.s} + {{objdump -fdw arm-app.d} {objdump -Rw arm-app.r}} + "arm-app"} + {"Simple static application" "" "" {arm-static-app.s} + {{objdump -fdw arm-static-app.d} {objdump -rw arm-static-app.r}} + "arm-static-app"} + {"Non-pcrel function reference" "tmpdir/arm-lib.so" "" {arm-app-abs32.s} + {{objdump -fdw arm-app-abs32.d} {objdump -Rw arm-app-abs32.r}} + "arm-app-abs32"} + {"Thumb shared library with ARM entry points" "-shared -T arm-lib.ld" "-mthumb-interwork" + {mixed-lib.s} + {{objdump -fdw armthumb-lib.d} {readelf -Ds armthumb-lib.sym}} + "armthumb-lib.so"} + {"Mixed ARM/Thumb shared library" "-shared -T arm-lib.ld -use-blx" "" + {mixed-lib.s} + {{objdump -fdw mixed-lib.d} {objdump -Rw mixed-lib.r} + {readelf -Ds mixed-lib.sym}} + "mixed-lib.so"} + {"Mixed ARM/Thumb dynamic application" "tmpdir/mixed-lib.so -T arm-dyn.ld" "" + {mixed-app.s} + {{objdump -fdw mixed-app.d} {objdump -Rw mixed-app.r} + {readelf -Ds mixed-app.sym}} + "mixed-app"} + {"Mixed ARM/Thumb arch5 dynamic application" "tmpdir/mixed-lib.so -T arm-dyn.ld --use-blx" "" + {mixed-app.s} + {{objdump -fdw mixed-app-v5.d} {objdump -Rw mixed-app.r} + {readelf -Ds mixed-app.sym}} + "mixed-app-v5"} + {"target1-abs" "-static --target1-abs -T arm.ld" "" {arm-target1.s} + {{objdump -s arm-target1-abs.d}} + "arm-target1-abs"} + {"target1-rel" "-static --target1-rel -T arm.ld" "" {arm-target1.s} + {{objdump -s arm-target1-rel.d}} + "arm-target1-rel"} + {"target2-rel" "-static --target2=rel -T arm.ld" "" {arm-target2.s} + {{objdump -s arm-target2-rel.d}} + "arm-target2-rel"} + {"target2-abs" "-static --target2=abs -T arm.ld" "" {arm-target2.s} + {{objdump -s arm-target2-abs.d}} + "arm-target2-abs"} + {"target2-got-rel" "-static --target2=got-rel -T arm.ld" "" {arm-target2.s} + {{objdump -s arm-target2-got-rel.d}} + "arm-target2-got-rel"} + {"arm-rel31" "-static -T arm.ld" "" {arm-rel31.s} + {{objdump -s arm-rel31.d}} + "arm-rel31"} + {"arm-call" "-static -T arm.ld" "-meabi=4" {arm-call1.s arm-call2.s} + {{objdump -d arm-call.d}} + "arm-call"} + {"TLS shared library" "-shared -T arm-lib.ld" "" {tls-lib.s} + {{objdump -fdw tls-lib.d} {objdump -Rw tls-lib.r}} + "tls-lib.so"} + {"TLS dynamic application" "-T arm-dyn.ld tmpdir/tls-lib.so" "" {tls-app.s} + {{objdump -fdw tls-app.d} {objdump -Rw tls-app.r}} + "tls-app"} + {"Thumb entry point" "-T arm.ld" "" {thumb-entry.s} + {{readelf -h thumb-entry.d}} + "thumb-entry"} + {"thumb-rel32" "-static -T arm.ld" "" {thumb-rel32.s} + {{objdump -s thumb-rel32.d}} + "thumb-rel32"} + {"MOVW/MOVT" "-static -T arm.ld" "" {arm-movwt.s} + {{objdump -dw arm-movwt.d}} + "arm-movwt"} + {"BE8 Mapping Symbols" "-static -T arm.ld -EB --be8" "-EB" {arm-be8.s} + {{objdump -d arm-be8.d}} + "arm-be8"} + {"Using Thumb lib by another lib" "-shared tmpdir/mixed-lib.so" "" {use-thumb-lib.s} + {{readelf -Ds use-thumb-lib.sym}} + "use-thumb-lib.so"} + {"VFP11 denorm erratum fix, scalar operation" + "-EL --vfp11-denorm-fix=scalar -Ttext=0x8000" "-EL -mfpu=vfpxd" {vfp11-fix-scalar.s} + {{objdump -dr vfp11-fix-scalar.d}} + "vfp11-fix-scalar"} + {"VFP11 denorm erratum fix, vector operation" + "-EB --vfp11-denorm-fix=vector -Ttext=0x8000" "-EB -mfpu=vfpxd" {vfp11-fix-vector.s} + {{objdump -dr vfp11-fix-vector.d}} + "vfp11-fix-vector"} + {"VFP11 denorm erratum fix, embedded code-like data" + "-EL --vfp11-denorm-fix=scalar -Ttext=0x8000" "-EL -mfpu=vfpxd" {vfp11-fix-none.s} + {{objdump -dr vfp11-fix-none.d}} + "vfp11-fix-none"} + {"Cortex-A8 erratum fix, b.w" + "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-b.s} + {{objdump -dr cortex-a8-fix-b.d}} + "cortex-a8-fix-b"} + {"Cortex-A8 erratum fix, b.w to PLT" + "-EL -Tcortex-a8-fix-plt.ld --fix-cortex-a8 -shared" "-EL" + {cortex-a8-fix-b-plt.s} + {{objdump -dr cortex-a8-fix-b-plt.d}} + "cortex-a8-fix-b-plt"} + {"Cortex-A8 erratum fix, bl.w" + "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-bl.s} + {{objdump -dr cortex-a8-fix-bl.d}} + "cortex-a8-fix-bl"} + {"Cortex-A8 erratum fix, bl.w to PLT" + "-EL -Tcortex-a8-fix-plt.ld --fix-cortex-a8 -shared" "-EL" + {cortex-a8-fix-bl-plt.s} + {{objdump -dr cortex-a8-fix-bl-plt.d}} + "cortex-a8-fix-bl-plt"} + {"Cortex-A8 erratum fix, bcc.w" + "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-bcc.s} + {{objdump -dr cortex-a8-fix-bcc.d}} + "cortex-a8-fix-bcc"} + {"Cortex-A8 erratum fix, bcc.w to PLT" + "-EL -Tcortex-a8-fix-plt.ld --fix-cortex-a8 -shared" "-EL" + {cortex-a8-fix-bcc-plt.s} + {{objdump -dr cortex-a8-fix-bcc-plt.d}} + "cortex-a8-fix-bcc-plt"} + {"Cortex-A8 erratum fix, blx.w" + "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-blx.s} + {{objdump -dr cortex-a8-fix-blx.d}} + "cortex-a8-fix-blx"} + {"Cortex-A8 erratum fix, blx.w to PLT" + "-EL -Tcortex-a8-fix-plt.ld --fix-cortex-a8 -shared" "-EL" + {cortex-a8-fix-blx-plt.s} + {{objdump -dr cortex-a8-fix-blx-plt.d}} + "cortex-a8-fix-blx-plt"} + {"Cortex-A8 erratum fix, relocate b.w to ARM" + "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-arm-target.s cortex-a8-fix-b-rel.s} + {{objdump -dr cortex-a8-fix-b-rel-arm.d}} + "cortex-a8-fix-b-rel-arm"} + {"Cortex-A8 erratum fix, relocate b.w to Thumb" + "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-b-rel.s} + {{objdump -dr cortex-a8-fix-b-rel-thumb.d}} + "cortex-a8-fix-b-rel-thumb"} + {"Cortex-A8 erratum fix, relocate bl.w to ARM" + "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-arm-target.s cortex-a8-fix-bl-rel.s} + {{objdump -dr cortex-a8-fix-bl-rel-arm.d}} + "cortex-a8-fix-bl-rel-arm"} + {"Cortex-A8 erratum fix, relocate bl.w to Thumb" + "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-bl-rel.s} + {{objdump -dr cortex-a8-fix-bl-rel-thumb.d}} + "cortex-a8-fix-bl-rel-thumb"} + {"Cortex-A8 erratum fix, relocate bl.w to PLT" + "-EL --section-start=.plt=0x8e00 -Ttext=0x8f00 --fix-cortex-a8 -shared" + "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-bl-rel.s} + {{objdump -dr cortex-a8-fix-bl-rel-plt.d}} + "cortex-a8-fix-bl-rel-thumb"} + {"Cortex-A8 erratum fix, relocate b<cond>.w to Thumb" + "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-bcc-rel.s} + {{objdump -dr cortex-a8-fix-bcc-rel-thumb.d}} + "cortex-a8-fix-bcc-rel-thumb"} + {"Cortex-A8 erratum fix, relocate blx.w to ARM" + "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-arm-target.s cortex-a8-fix-blx-rel.s} + {{objdump -dr cortex-a8-fix-blx-rel-arm.d}} + "cortex-a8-fix-blx-rel-arm"} + {"Cortex-A8 erratum fix, relocate blx.w to Thumb" + "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-thumb-target.s cortex-a8-fix-blx-rel.s} + {{objdump -dr cortex-a8-fix-blx-rel-thumb.d}} + "cortex-a8-fix-blx-rel-thumb"} + {"Cortex-A8 erratum fix, relocate bl.w and far call" + "-EL -Ttext=0x00 --fix-cortex-a8 --defsym far_fn1=0x80000000 --defsym far_fn2=0x80000004 --defsym far_fn=0x7fff0000 --defsym _start=0" + "-EL -mcpu=cortex-a8" {cortex-a8-far-1.s cortex-a8-far-2.s} + {{objdump -dr cortex-a8-far.d}} + "cortex-a8-far"} + {"Cortex-A8 erratum fix, headers" + "-EL --fix-cortex-a8 -T cortex-a8-fix-hdr.t" + "-EL -mcpu=cortex-a8" {cortex-a8-fix-hdr.s} + {{objdump -dr cortex-a8-fix-hdr.d}} + "cortex-a8-fix-hdr"} + {"Cortex-A8 erratum fix, blx.w and b<cond>.w together" + "-EL -Ttext=0x8f00 --fix-cortex-a8" "-EL" {cortex-a8-fix-blx-bcond.s} + {{objdump -dr cortex-a8-fix-blx-bcond.d}} + "cortex-a8-fix-blx-bcond"} + {"Unwinding and -gc-sections" "-gc-sections" "" {gc-unwind.s} + {{objdump -sj.data gc-unwind.d}} + "gc-unwind"} + {"arm-pic-veneer" "-static -T arm.ld --pic-veneer" "" {arm-pic-veneer.s} + {{objdump -d arm-pic-veneer.d}} + "arm-pic-veneer"} + {"Preempt Thumb symbol" "tmpdir/mixed-lib.so -T arm-dyn.ld --use-blx" "" + {preempt-app.s} + {{readelf -Ds preempt-app.sym}} + "preempt-app"} + {"jump19" "-static -T arm.ld" "" {jump19.s} + {{objdump -dr jump19.d}} + "jump19"} + {"script-type" "-static -T script-type.ld" "" {script-type.s} + {{readelf -s script-type.sym}} + "script-type"} + {"callweak" "-static -T arm.ld" "" {callweak.s} + {{objdump -dr callweak.d}} + "callweak"} + {"callweak-2" "-static -T arm.ld" "" {callweak-2.s} + {{objdump -dr callweak-2.d}} + "callweak-2"} + {"Relocation boundaries" "-defsym x=0 -defsym y=0 -defsym _start=0" "" {reloc-boundaries.s} + {{objdump -s reloc-boundaries.d}} + "reloc-boundaries"} + {"Data only mapping symbols" "-T data-only-map.ld -Map map" "" {data-only-map.s} + {{objdump -dr data-only-map.d}} + "data-only-map"} +} + +run_ld_link_tests $armelftests +run_dump_test "group-relocs-alu-bad" +run_dump_test "group-relocs-ldr-bad" +run_dump_test "group-relocs-ldrs-bad" +run_dump_test "group-relocs-ldc-bad" +run_dump_test "thumb2-bl-undefweak" +run_dump_test "thumb2-bl-undefweak1" +run_dump_test "emit-relocs1" +run_dump_test "movw-shared-1" +run_dump_test "movw-shared-2" +run_dump_test "movw-shared-3" +run_dump_test "movw-shared-4" + +# Exclude non-ARM-EABI targets. + +if { ![istarget "arm*-*-*eabi"] } { + # Special variants of these tests, as a different farcall stub is + # generated for a non-ARM-EABI target: indeed in such a case, + # there are no attributes to indicate that blx can be used. + + set arm_noeabi_tests { + {"Thumb-2-as-Thumb-1 BL" "-Ttext 0x1000 --section-start .foo=0x100100c" "" {thumb2-bl-as-thumb1-bad.s} + {{objdump -d thumb2-bl-as-thumb1-bad-noeabi.d}} + "thumb2-bl-as-thumb1-bad"} + {"Thumb-2 BL bad" "-Ttext 0x1000 --section-start .foo=0x100100c" "" {thumb2-bl-bad.s} + {{objdump -d thumb2-bl-bad-noeabi.d}} + "thumb2-bl-bad"} + } + run_ld_link_tests $arm_noeabi_tests + + return +} + +# Farcalls stubs are fully supported for ARM-EABI only +set armeabitests { + {"EABI attribute merging" "-r" "" {attr-merge.s attr-merge.s} + {{readelf -A attr-merge.attr}} + "attr-merge"} + {"EABI attribute merging 2" "-r" "" {attr-merge-2a.s attr-merge-2b.s} + {{readelf -A attr-merge-2.attr}} + "attr-merge-2"} + {"EABI attribute merging 3" "-r" "" {attr-merge-3a.s attr-merge-3b.s} + {{readelf -A attr-merge-3.attr}} + "attr-merge-3"} + {"EABI attribute merging 4" "-r" "" {attr-merge-4a.s attr-merge-4b.s} + {{readelf -A attr-merge-4.attr}} + "attr-merge-4"} + {"EABI attribute merging 5" "-r" "" {attr-merge-5.s attr-merge-5.s} + {{readelf -A attr-merge-5.attr}} + "attr-merge-5"} + {"EABI attribute merging 6" "-r" "" {attr-merge-6a.s attr-merge-6b.s} + {{readelf -A attr-merge-6.attr}} + "attr-merge-6"} + {"EABI attribute merging 6 reversed" "-r" "" {attr-merge-6b.s attr-merge-6a.s} + {{readelf -A attr-merge-6.attr}} + "attr-merge-6r"} + {"EABI attribute merging 7" "-r" "" {attr-merge-7a.s attr-merge-7b.s} + {{readelf -A attr-merge-7.attr}} + "attr-merge-7"} + {"EABI attribute arch merging 1" "-r" "" {arch-v6k.s arch-v6t2.s} + {{readelf -A attr-merge-arch-1.attr}} + "attr-merge-arch-1"} + {"EABI attribute arch merging 1 reversed" "-r" "" {arch-v6t2.s arch-v6k.s} + {{readelf -A attr-merge-arch-1.attr}} + "attr-merge-arch-1r"} + {"EABI attribute arch merging 2" "-r" "" {arch-v6k.s arch-v6.s} + {{readelf -A attr-merge-arch-2.attr}} + "attr-merge-arch-2"} + {"EABI attribute arch merging 2 reversed" "-r" "" {arch-v6.s arch-v6k.s} + {{readelf -A attr-merge-arch-2.attr}} + "attr-merge-arch-2r"} + {"Thumb-2 BL" "-Ttext 0x1000 --section-start .foo=0x1001000" "" {thumb2-bl.s} + {{objdump -dr thumb2-bl.d}} + "thumb2-bl"} + {"Thumb-2 Interworked branch" "-T arm.ld" "" {thumb2-b-interwork.s} + {{objdump -dr thumb2-b-interwork.d}} + "thumb2-b-interwork"} + {"BL/BLX interworking" "-T arm.ld" "" {thumb2-bl-blx-interwork.s} + {{objdump -dr thumb2-bl-blx-interwork.d}} + "thumb2-bl-blx-interwork"} + {"ARMv4 interworking" "-static -T arm.ld --fix-v4bx-interworking" "--fix-v4bx -meabi=4" {armv4-bx.s} + {{objdump -d armv4-bx.d}} + "armv4-bx"} + {"MOVW/MOVT and merged sections" "-T arm.ld" "" {movw-merge.s} + {{objdump -dw movw-merge.d}} + "movw-merge"} + {"MOVW/MOVT against shared libraries" "tmpdir/arm-lib.so" "" {arm-app-movw.s} + {{objdump -Rw arm-app.r}} + "arm-app-movw"} + {"Thumb-2-as-Thumb-1 BL" "-Ttext 0x1000 --section-start .foo=0x100100c" "" {thumb2-bl-as-thumb1-bad.s} + {{objdump -d thumb2-bl-as-thumb1-bad.d}} + "thumb2-bl-as-thumb1-bad"} + {"Thumb-2 BL" "-Ttext 0x1000 --section-start .foo=0x100100c" "" {thumb2-bl-bad.s} + {{objdump -d thumb2-bl-bad.d}} + "thumb2-bl-bad"} + + {"ARM-ARM farcall" "-Ttext 0x1000 --section-start .foo=0x2001020" "" {farcall-arm-arm.s} + {{objdump -d farcall-arm-arm.d}} + "farcall-arm-arm"} + {"ARM-ARM farcall (PIC veneer)" "-Ttext 0x1000 --section-start .foo=0x2001020 --pic-veneer" "" {farcall-arm-arm.s} + {{objdump -d farcall-arm-arm-pic-veneer.d}} + "farcall-arm-arm-pic-veneer"} + {"ARM-ARM farcall (BE8)" "-Ttext 0x1000 --section-start .foo=0x2001020 -EB --be8" "-EB" {farcall-arm-arm.s} + {{objdump -d farcall-arm-arm.d}} + "farcall-arm-arm-be8"} + {"ARM-ARM farcall (BE)" "-Ttext 0x1000 --section-start .foo=0x2001020 -EB" "-EB" {farcall-arm-arm.s} + {{objdump -d farcall-arm-arm.d}} + "farcall-arm-arm-be"} + + {"ARM-Thumb farcall" "-Ttext 0x1000 --section-start .foo=0x2001014" "" {farcall-arm-thumb.s} + {{objdump -d farcall-arm-thumb.d}} + "farcall-arm-thumb"} + {"ARM-Thumb farcall with BLX" "-Ttext 0x1000 --section-start .foo=0x2001014" "-march=armv5t" {farcall-arm-thumb.s} + {{objdump -d farcall-arm-thumb-blx.d}} + "farcall-arm-thumb-blx"} + {"ARM-Thumb farcall (PIC veneer)" "-Ttext 0x1000 --section-start .foo=0x2001014 --pic-veneer" "" {farcall-arm-thumb.s} + {{objdump -d farcall-arm-thumb-pic-veneer.d}} + "farcall-arm-thumb-pic-veneer"} + {"ARM-Thumb farcall with BLX (PIC veneer)" "-Ttext 0x1000 --section-start .foo=0x2001014 --pic-veneer" "-march=armv5t" {farcall-arm-thumb.s} + {{objdump -d farcall-arm-thumb-blx-pic-veneer.d}} + "farcall-arm-thumb-blx-pic-veneer"} + + {"Thumb-Thumb farcall with BLX" "-Ttext 0x1000 --section-start .foo=0x2001014" "-march=armv5t" {farcall-thumb-thumb.s} + {{objdump -d farcall-thumb-thumb-blx.d}} + "farcall-thumb-thumb-blx"} + {"Thumb-Thumb farcall M profile" "-Ttext 0x1000 --section-start .foo=0x2001014" "-march=armv7-m" {farcall-thumb-thumb.s} + {{objdump -d farcall-thumb-thumb-m.d}} + "farcall-thumb-thumb-m"} + {"Thumb-Thumb farcall v6-M" "-Ttext 0x1000 --section-start .foo=0x2001014" "-march=armv6-m" {farcall-thumb-thumb.s} + {{objdump -d farcall-thumb-thumb-m.d}} + "farcall-thumb-thumb-v6-m"} + {"Thumb-Thumb farcall" "-Ttext 0x1000 --section-start .foo=0x2001014" "-march=armv4t" {farcall-thumb-thumb.s} + {{objdump -d farcall-thumb-thumb.d}} + "farcall-thumb-thumb"} + {"Thumb-Thumb farcall with BLX (PIC veneer)" "-Ttext 0x1000 --section-start .foo=0x2001014 --pic-veneer" "-march=armv5t" {farcall-thumb-thumb.s} + {{objdump -d farcall-thumb-thumb-blx-pic-veneer.d}} + "farcall-thumb-thumb-blx-pic-veneer"} + {"Thumb-Thumb farcall M profile (PIC veneer)" "-Ttext 0x1000 --section-start .foo=0x2001014 --pic-veneer" "-march=armv7-m" {farcall-thumb-thumb.s} + {{objdump -d farcall-thumb-thumb-m-pic-veneer.d}} + "farcall-thumb-thumb-m-pic-veneer"} + {"Thumb-Thumb farcall (PIC veneer)" "-Ttext 0x1000 --section-start .foo=0x2001014 --pic-veneer" "-march=armv4t" {farcall-thumb-thumb.s} + {{objdump -d farcall-thumb-thumb-pic-veneer.d}} + "farcall-thumb-thumb-pic-veneer"} + + {"Thumb-ARM farcall" "-Ttext 0x1c01010 --section-start .foo=0x2001014" "-W" {farcall-thumb-arm.s} + {{objdump -d farcall-thumb-arm.d}} + "farcall-thumb-arm"} + {"Thumb-ARM farcall (BE8)" "-Ttext 0x1c01010 --section-start .foo=0x2001014 -EB --be8" "-W -EB" {farcall-thumb-arm.s} + {{objdump -d farcall-thumb-arm.d}} + "farcall-thumb-arm-be8"} + {"Thumb-ARM farcall (BE)" "-Ttext 0x1c01010 --section-start .foo=0x2001014 -EB" "-W -EB" {farcall-thumb-arm.s} + {{objdump -d farcall-thumb-arm.d}} + "farcall-thumb-arm-be"} + {"Thumb-ARM (short) call" "-Ttext 0x1000 --section-start .foo=0x0002014" "-W" {farcall-thumb-arm-short.s} + {{objdump -d farcall-thumb-arm-short.d}} + "farcall-thumb-arm-short"} + {"Thumb-ARM farcall with BLX" "-Ttext 0x1c01010 --section-start .foo=0x2001014" "-W -march=armv5t" {farcall-thumb-arm.s} + {{objdump -d farcall-thumb-arm-blx.d}} + "farcall-thumb-arm-blx"} + {"Thumb-ARM farcall with BLX (PIC veneer)" "-Ttext 0x1c01010 --section-start .foo=0x2001014 --pic-veneer" "-W -march=armv5t" {farcall-thumb-arm.s} + {{objdump -d farcall-thumb-arm-blx-pic-veneer.d}} + "farcall-thumb-arm-blx-pic-veneer"} + {"Thumb-ARM farcall (PIC veneer)" "-Ttext 0x1c01010 --section-start .foo=0x2001014 --pic-veneer" "-W" {farcall-thumb-arm.s} + {{objdump -d farcall-thumb-arm-pic-veneer.d}} + "farcall-thumb-arm-pic-veneer"} + + {"Multiple farcalls" "-Ttext 0x1000 --section-start .foo=0x2002020" "" {farcall-mix.s} + {{objdump -d farcall-mix.d}} + "farcall-mix"} + {"Multiple farcalls from several sections" "-Ttext 0x1000 --section-start .mytext=0x2000 --section-start .foo=0x2003020" "" {farcall-mix2.s} + {{objdump -d farcall-mix2.d}} + "farcall-mix2"} + + {"Default group size" "-Ttext 0x1000 --section-start .foo=0x2003020" "" {farcall-group.s farcall-group2.s} + {{objdump -d farcall-group.d}} + "farcall-group-default"} + {"Group size=2" "-Ttext 0x1000 --section-start .foo=0x2003020 --stub-group-size=2" "" {farcall-group.s farcall-group2.s} + {{objdump -d farcall-group-size2.d}} + "farcall-group-size2"} + {"Group size limit" "-Ttext 0x1000 --section-start .far=0x2003020" "" {farcall-group3.s farcall-group4.s} + {{objdump -d farcall-group-limit.d}} + "farcall-group-limit"} + + {"Mixed ARM/Thumb dynamic application with farcalls" "tmpdir/mixed-lib.so -T arm-dyn.ld --section-start .far_arm=0x2100000 --section-start .far_thumb=0x2200000" "" + {farcall-mixed-app.s} + {{objdump -fdw farcall-mixed-app.d} {objdump -Rw farcall-mixed-app.r} + {readelf -Ds farcall-mixed-app.sym}} + "farcall-mixed-app"} + {"Mixed ARM/Thumb arch5 dynamic application with farcalls" "tmpdir/mixed-lib.so -T arm-dyn.ld --use-blx --section-start .far_arm=0x2100000 --section-start .far_thumb=0x2200000" "" + {farcall-mixed-app.s} + {{objdump -fdw farcall-mixed-app-v5.d} {objdump -Rw farcall-mixed-app.r} + {readelf -Ds farcall-mixed-app.sym}} + "farcall-mixed-app-v5"} + + {"Mixed ARM/Thumb shared library with long branches (v4t)" "-shared -T arm-lib.ld" "-march=armv4t" + {farcall-mixed-lib1.s farcall-mixed-lib2.s} + {{objdump -fdw farcall-mixed-lib-v4t.d}} + "farcall-mixed-lib.so"} + + {"Mixed ARM/Thumb shared library with long branches (v5t)" "-shared -T arm-lib.ld" "-march=armv5t" + {farcall-mixed-lib1.s farcall-mixed-lib2.s} + {{objdump -fdw farcall-mixed-lib.d}} + "farcall-mixed-lib.so"} + + {"Long branch with mixed text and data" "-T arm.ld" "" {farcall-data.s} + {{objdump -dr farcall-data.d}} + "farcall-data"} + + {"R_ARM_THM_JUMP24 Relocation veneers: Short 1" + "--section-start destsect=0x00009000 --section-start .text=0x8000" + "-march=armv7-a -mthumb" + {jump-reloc-veneers.s} + {{objdump -d jump-reloc-veneers-short1.d}} + "jump-reloc-veneers-short1"} + {"R_ARM_THM_JUMP24 Relocation veneers: Short 2" + "--section-start destsect=0x00900000 --section-start .text=0x8000" + "-march=armv7-a -mthumb" + {jump-reloc-veneers.s} + {{objdump -d jump-reloc-veneers-short2.d}} + "jump-reloc-veneers-short2"} + {"R_ARM_THM_JUMP24 Relocation veneers: Long" + "--section-start destsect=0x09000000 --section-start .text=0x8000" + "-march=armv7-a -mthumb" + {jump-reloc-veneers.s} + {{objdump -d jump-reloc-veneers-long.d}} + "jump-reloc-veneers-long"} +} + +run_ld_link_tests $armeabitests +run_dump_test "attr-merge-wchar-00" +run_dump_test "attr-merge-wchar-02" +run_dump_test "attr-merge-wchar-04" +run_dump_test "attr-merge-wchar-20" +run_dump_test "attr-merge-wchar-22" +run_dump_test "attr-merge-wchar-24" +run_dump_test "attr-merge-wchar-40" +run_dump_test "attr-merge-wchar-42" +run_dump_test "attr-merge-wchar-44" +run_dump_test "attr-merge-wchar-00-nowarn" +run_dump_test "attr-merge-wchar-02-nowarn" +run_dump_test "attr-merge-wchar-04-nowarn" +run_dump_test "attr-merge-wchar-20-nowarn" +run_dump_test "attr-merge-wchar-22-nowarn" +run_dump_test "attr-merge-wchar-24-nowarn" +run_dump_test "attr-merge-wchar-40-nowarn" +run_dump_test "attr-merge-wchar-42-nowarn" +run_dump_test "attr-merge-wchar-44-nowarn" +run_dump_test "farcall-section" +run_dump_test "attr-merge-unknown-1" +run_dump_test "attr-merge-unknown-2" +run_dump_test "attr-merge-unknown-2r" +run_dump_test "attr-merge-unknown-3" +run_dump_test "unwind-1" +run_dump_test "unwind-2" +run_dump_test "unwind-3" +run_dump_test "unwind-4" +run_dump_test "unwind-5" +run_dump_test "attr-merge-vfp-1" +run_dump_test "attr-merge-vfp-1r" +run_dump_test "attr-merge-vfp-2" +run_dump_test "attr-merge-vfp-2r" +run_dump_test "attr-merge-vfp-3" +run_dump_test "attr-merge-vfp-3r" +run_dump_test "attr-merge-vfp-4" +run_dump_test "attr-merge-vfp-4r" +run_dump_test "attr-merge-vfp-5" +run_dump_test "attr-merge-vfp-5r" +run_dump_test "attr-merge-vfp-6" +run_dump_test "attr-merge-vfp-6r" +run_dump_test "attr-merge-incompatible" diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-lib-plt32.d b/binutils-2.21/ld/testsuite/ld-arm/arm-lib-plt32.d new file mode 100644 index 0000000..3413dff --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-lib-plt32.d @@ -0,0 +1,28 @@ + +tmpdir/arm-lib-plt32.so: file format elf32-(little|big)arm +architecture: arm, flags 0x00000150: +HAS_SYMS, DYNAMIC, D_PAGED +start address 0x.* + +Disassembly of section .plt: + +.* <.plt>: + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1-0x10> + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* +Disassembly of section .text: + +.* <lib_func1>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: ebfffff9 bl .* <lib_func1-0xc> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + +.* <lib_func2>: + .*: e12fff1e bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-lib-plt32.r b/binutils-2.21/ld/testsuite/ld-arm/arm-lib-plt32.r new file mode 100644 index 0000000..3515539 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-lib-plt32.r @@ -0,0 +1,8 @@ + +tmpdir/arm-lib-plt32.so: file format elf32-(little|big)arm + +DYNAMIC RELOCATION RECORDS +OFFSET TYPE VALUE +.* R_ARM_JUMP_SLOT app_func2 + + diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-lib-plt32.s b/binutils-2.21/ld/testsuite/ld-arm/arm-lib-plt32.s new file mode 100644 index 0000000..d6c4787 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-lib-plt32.s @@ -0,0 +1,17 @@ + .text + + .globl lib_func1 + .type lib_func1, %function +lib_func1: + mov ip, sp + stmdb sp!, {r11, ip, lr, pc} + bl app_func2(PLT) + ldmia sp, {r11, sp, lr} + bx lr + .size lib_func1, . - lib_func1 + + .globl lib_func2 + .type lib_func2, %function +lib_func2: + bx lr + .size lib_func2, . - lib_func2 diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-lib.d b/binutils-2.21/ld/testsuite/ld-arm/arm-lib.d new file mode 100644 index 0000000..3a1c777 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-lib.d @@ -0,0 +1,28 @@ + +tmpdir/arm-lib.so: file format elf32-(little|big)arm +architecture: arm, flags 0x00000150: +HAS_SYMS, DYNAMIC, D_PAGED +start address 0x.* + +Disassembly of section .plt: + +.* <.plt>: + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1-0x10> + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* +Disassembly of section .text: + +.* <lib_func1>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: ebfffff9 bl .* <lib_func1-0xc> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + +.* <lib_func2>: + .*: e12fff1e bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-lib.ld b/binutils-2.21/ld/testsuite/ld-arm/arm-lib.ld new file mode 100644 index 0000000..c9482c3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-lib.ld @@ -0,0 +1,187 @@ +/* Script for --shared -z combreloc: shared library, combine & sort relocs */ +OUTPUT_ARCH(arm) +ENTRY(_start) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = 0 + SIZEOF_HEADERS; + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.dyn : + { + *(.rel.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rel.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rel.data.rel.ro*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rel.dtors) + *(.rel.got) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + } + .rela.dyn : + { + *(.rela.init) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rela.fini) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rela.ctors) + *(.rela.dtors) + *(.rela.got) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : + { + KEEP (*(.init)) + } =0 + .plt : { *(.plt) } + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + KEEP (*(.text.*personality*)) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.glue_7t) *(.glue_7) + } =0 + .fini : + { + KEEP (*(.fini)) + } =0 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } + .rodata1 : { *(.rodata1) } + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } + PROVIDE_HIDDEN (__exidx_end = .); + .eh_frame_hdr : { *(.eh_frame_hdr) } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + .gcc_except_table : ONLY_IF_RO { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN (0x8000) - ((0x8000 - .) & (0x8000 - 1)); . = DATA_SEGMENT_ALIGN (0x8000, 0x1000); + /* Exception handling */ + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } + .gcc_except_table : ONLY_IF_RW { KEEP (*(.gcc_except_table)) *(.gcc_except_table.*) } + /* Thread Local Storage sections */ + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + . = ALIGN(32 / 8); + .preinit_array : { KEEP (*(.preinit_array)) } + .init_array : { KEEP (*(.init_array)) } + .fini_array : { KEEP (*(.fini_array)) } + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin*.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + .dtors : + { + KEEP (*crtbegin*.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + .jcr : { KEEP (*(.jcr)) } + .data.rel.ro : { *(.data.rel.ro.local) *(.data.rel.ro*) } + .dynamic : { *(.dynamic) } + .got : { *(.got.plt) *(.got) } + .data : + { + __data_start = . ; + *(.data .data.* .gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + SORT(CONSTRUCTORS) + } + .data1 : { *(.data1) } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + __bss_start__ = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); + } + . = ALIGN(32 / 8); + _end = .; + _bss_end__ = . ; __bss_end__ = . ; __end__ = . ; + PROVIDE (end = .); + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + /DISCARD/ : { *(.note.GNU-stack) } +} + + diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-lib.r b/binutils-2.21/ld/testsuite/ld-arm/arm-lib.r new file mode 100644 index 0000000..a7dde47 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-lib.r @@ -0,0 +1,8 @@ + +tmpdir/arm-lib.so: file format elf32-(little|big)arm + +DYNAMIC RELOCATION RECORDS +OFFSET TYPE VALUE +.* R_ARM_JUMP_SLOT app_func2 + + diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-lib.s b/binutils-2.21/ld/testsuite/ld-arm/arm-lib.s new file mode 100644 index 0000000..949f61c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-lib.s @@ -0,0 +1,24 @@ + .text + + .globl lib_func1 + .type lib_func1, %function +lib_func1: + mov ip, sp + stmdb sp!, {r11, ip, lr, pc} + bl app_func2 + ldmia sp, {r11, sp, lr} + bx lr + .size lib_func1, . - lib_func1 + + .globl lib_func2 + .type lib_func2, %function +lib_func2: + bx lr + .size lib_func2, . - lib_func2 + + .data + .globl data_obj + .type data_obj, %object +data_obj: + .long 0 + .size data_obj, . - data_obj diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-movwt.d b/binutils-2.21/ld/testsuite/ld-arm/arm-movwt.d new file mode 100644 index 0000000..7d558b7 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-movwt.d @@ -0,0 +1,39 @@ + +.*: file format.* + +Disassembly of section .text: + +00008000 <[^>]*>: + 8000: e3000000 movw r0, #0 + 8004: e3411234 movt r1, #4660 ; 0x1234 + 8008: e3082000 movw r2, #32768 ; 0x8000 + 800c: e3413233 movt r3, #4659 ; 0x1233 + 8010: e3004011 movw r4, #17 + 8014: e3415234 movt r5, #4660 ; 0x1234 + 8018: e3086011 movw r6, #32785 ; 0x8011 + 801c: e3417233 movt r7, #4659 ; 0x1233 + +00008020 <[^>]*>: + 8020: f240 0700 movw r7, #0 + 8024: f2c1 2634 movt r6, #4660 ; 0x1234 + 8028: f248 0500 movw r5, #32768 ; 0x8000 + 802c: f2c1 2433 movt r4, #4659 ; 0x1233 + 8030: f240 0311 movw r3, #17 + 8034: f2c1 2234 movt r2, #4660 ; 0x1234 + 8038: f248 0111 movw r1, #32785 ; 0x8011 + 803c: f2c1 2033 movt r0, #4659 ; 0x1233 + +Disassembly of section .far: + +12340000 <[^>]*>: +12340000: e3080000 movw r0, #32768 ; 0x8000 +12340004: e34e0dcc movt r0, #60876 ; 0xedcc +12340008: e3080021 movw r0, #32801 ; 0x8021 +1234000c: e34e0dcc movt r0, #60876 ; 0xedcc + +12340010 <[^>]*>: +12340010: f248 0000 movw r0, #32768 ; 0x8000 +12340014: f6ce 50cc movt r0, #60876 ; 0xedcc +12340018: f248 0021 movw r0, #32801 ; 0x8021 +1234001c: f6ce 50cc movt r0, #60876 ; 0xedcc + diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-movwt.s b/binutils-2.21/ld/testsuite/ld-arm/arm-movwt.s new file mode 100644 index 0000000..ba8b1c5 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-movwt.s @@ -0,0 +1,44 @@ + .text + .arch armv6t2 + .syntax unified + .global _start + .type _start, %function +_start: +base1: +arm1: + movw r0, #:lower16:arm2 + movt r1, #:upper16:arm2 + movw r2, #:lower16:(arm2 - arm1) + movt r3, #:upper16:(arm2 - arm1) + movw r4, #:lower16:thumb2 + movt r5, #:upper16:thumb2 + movw r6, #:lower16:(thumb2 - arm1) + movt r7, #:upper16:(thumb2 - arm1) + .thumb + .type thumb1, %function + .thumb_func +thumb1: + movw r7, #:lower16:arm2 + movt r6, #:upper16:arm2 + movw r5, #:lower16:(arm2 - arm1) + movt r4, #:upper16:(arm2 - arm1) + movw r3, #:lower16:thumb2 + movt r2, #:upper16:thumb2 + movw r1, #:lower16:(thumb2 - arm1) + movt r0, #:upper16:(thumb2 - arm1) + + .section .far, "ax", %progbits + .arm +arm2: + movw r0, #:lower16:(arm1 - arm2) + movt r0, #:upper16:(arm1 - arm2) + movw r0, #:lower16:(thumb1 - arm2) + movt r0, #:upper16:(thumb1 - arm2) + .thumb + .type thumb2, %function + .thumb_func +thumb2: + movw r0, #:lower16:(arm1 - arm2) + movt r0, #:upper16:(arm1 - arm2) + movw r0, #:lower16:(thumb1 - arm2) + movt r0, #:upper16:(thumb1 - arm2) diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-pic-veneer.d b/binutils-2.21/ld/testsuite/ld-arm/arm-pic-veneer.d new file mode 100644 index 0000000..08e107b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-pic-veneer.d @@ -0,0 +1,17 @@ + +.*: file format.* + +Disassembly of section .text: + +00008000 <_start>: + 8000: ea...... b 800. <.*> + +00008004 <foo>: + 8004: 46c0 nop ; \(mov r8, r8\) + 8006: 4770 bx lr + +00008008 <__foo_from_arm>: + 8008: e59fc004 ldr ip, \[pc, #4\] ; 8014 <__foo_from_arm\+0xc> + 800c: e08fc00c add ip, pc, ip + 8010: e12fff1c bx ip + 8014: fffffff1 .word 0xfffffff1 diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-pic-veneer.s b/binutils-2.21/ld/testsuite/ld-arm/arm-pic-veneer.s new file mode 100644 index 0000000..9e09ed6 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-pic-veneer.s @@ -0,0 +1,14 @@ +.text +.arm +.global _start +.type _start, %function +_start: +b foo + +.thumb +.global foo +.type foo, %function +foo: +nop +bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-rel31.d b/binutils-2.21/ld/testsuite/ld-arm/arm-rel31.d new file mode 100644 index 0000000..ac99e92 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-rel31.d @@ -0,0 +1,7 @@ + +.*: file format.* + +Contents of section .text: + 8000 (10000000 fcffff7f 08000080 f4ffffff|00000010 7ffffffc 80000008 fffffff4) .* +# Ignore .ARM.attributes section +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-rel31.s b/binutils-2.21/ld/testsuite/ld-arm/arm-rel31.s new file mode 100644 index 0000000..37eee66 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-rel31.s @@ -0,0 +1,11 @@ +# Test the R_ARM_REL31 relocation + .section .before + .global _start +_start: + .text + .rel31 0, foo + .rel31 0, _start + .rel31 1, foo + .rel31 1, _start + .section .after +foo: diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-static-app.d b/binutils-2.21/ld/testsuite/ld-arm/arm-static-app.d new file mode 100644 index 0000000..f18f3c6 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-static-app.d @@ -0,0 +1,24 @@ + +tmpdir/arm-static-app: file format elf32-(little|big)arm +architecture: arm, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x.* + +Disassembly of section .text: + +.* <_start>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: eb000001 bl .* <app_func> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + +.* <app_func>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: eb000001 bl .* <app_func2> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + +.* <app_func2>: + .*: e12fff1e bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-static-app.r b/binutils-2.21/ld/testsuite/ld-arm/arm-static-app.r new file mode 100644 index 0000000..6034b7f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-static-app.r @@ -0,0 +1,3 @@ + +tmpdir/arm-static-app: file format elf32-(little|big)arm + diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-static-app.s b/binutils-2.21/ld/testsuite/ld-arm/arm-static-app.s new file mode 100644 index 0000000..99c579f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-static-app.s @@ -0,0 +1,20 @@ + .text + .globl _start +_start: + mov ip, sp + stmdb sp!, {r11, ip, lr, pc} + bl app_func + ldmia sp, {r11, sp, lr} + bx lr + + .globl app_func +app_func: + mov ip, sp + stmdb sp!, {r11, ip, lr, pc} + bl app_func2 + ldmia sp, {r11, sp, lr} + bx lr + + .globl app_func2 +app_func2: + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-target1-abs.d b/binutils-2.21/ld/testsuite/ld-arm/arm-target1-abs.d new file mode 100644 index 0000000..af64e60 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-target1-abs.d @@ -0,0 +1,7 @@ + +.*: file format.* + +Contents of section .text: + 8000 (04800000|00008004) .* +# Ignore .ARM.attributes section +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-target1-rel.d b/binutils-2.21/ld/testsuite/ld-arm/arm-target1-rel.d new file mode 100644 index 0000000..fcd6c1a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-target1-rel.d @@ -0,0 +1,7 @@ + +.*: file format .* + +Contents of section .text: + 8000 (04000000|00000004) .* +# Ignore .ARM.attributes section +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-target1.s b/binutils-2.21/ld/testsuite/ld-arm/arm-target1.s new file mode 100644 index 0000000..5a7ba91 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-target1.s @@ -0,0 +1,6 @@ +# Test the R_ARM_TARGET1 relocation + .text + .global _start +_start: + .word foo(target1) +foo: diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-target2-abs.d b/binutils-2.21/ld/testsuite/ld-arm/arm-target2-abs.d new file mode 100644 index 0000000..a86dc01 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-target2-abs.d @@ -0,0 +1,7 @@ + +.*: file format.* + +Contents of section .text: + 8000 (10800000|00008010) (44920000|00009244) (1080efcd|cdef8010) (20b25476|7654b220) .* +# Ignore .ARM.attributes section +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-target2-got-rel.d b/binutils-2.21/ld/testsuite/ld-arm/arm-target2-got-rel.d new file mode 100644 index 0000000..3433791 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-target2-got-rel.d @@ -0,0 +1,9 @@ + +.*: file format.* + +Contents of section .text: + 8000 (00100000|00001000) (30220000|00002230) (f80fefcd|cdef0ff8) (04425476|76544204) .* +Contents of section .got: + 9000 (10800000|00008010) .* +# Ignore .ARM.attributes section +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-target2-rel.d b/binutils-2.21/ld/testsuite/ld-arm/arm-target2-rel.d new file mode 100644 index 0000000..f812640 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-target2-rel.d @@ -0,0 +1,7 @@ + +.*: file format.* + +Contents of section .text: + 8000 (10000000|00000010) (40120000|00001240) (0800efcd|cdef0008) (14325476|76543214) .* +# Ignore .ARM.attributes section +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm-target2.s b/binutils-2.21/ld/testsuite/ld-arm/arm-target2.s new file mode 100644 index 0000000..26c4519 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm-target2.s @@ -0,0 +1,9 @@ +# Test the R_ARM_TARGET2 relocation + .text + .global _start +_start: + .word foo(target2) + .word foo+0x1234(target2) + .word foo+0xcdef0000(target2) + .word foo+0x76543210(target2) +foo: diff --git a/binutils-2.21/ld/testsuite/ld-arm/arm.ld b/binutils-2.21/ld/testsuite/ld-arm/arm.ld new file mode 100644 index 0000000..8e3fac2 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/arm.ld @@ -0,0 +1,23 @@ +/* Script for ld testsuite */ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x8000); . = 0x8000; + .text : + { + *(.before) + *(.text) + *(.after) + *(.ARM.extab*) + *(.glue_7) + *(.v4_bx) + } =0 + .ARM.exidx : { *(.ARM.exidx*) } + . = 0x9000; + .got : { *(.got) *(.got.plt)} + . = 0x12340000; + .far : { *(.far) } + .ARM.attribues 0 : { *(.ARM.atttributes) } +} diff --git a/binutils-2.21/ld/testsuite/ld-arm/armthumb-lib.d b/binutils-2.21/ld/testsuite/ld-arm/armthumb-lib.d new file mode 100644 index 0000000..6486ad5 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/armthumb-lib.d @@ -0,0 +1,44 @@ + +tmpdir/armthumb-lib.so: file format elf32-(little|big)arm +architecture: arm, flags 0x00000150: +HAS_SYMS, DYNAMIC, D_PAGED +start address 0x.* + +Disassembly of section .plt: + +.* <.plt>: + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1-0x1.> + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* +Disassembly of section .text: + +.* <lib_func1>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: ebfffff. bl .* <lib_func1-0x..?> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + +.* <__real_lib_func2>: + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + +.* <lib_func2>: + .*: e59fc004 ldr ip, \[pc, #4\] ; .* <lib_func2\+0xc> + .*: e08cc00f add ip, ip, pc + .*: e12fff1c bx ip + .*: ffffffe5 .* diff --git a/binutils-2.21/ld/testsuite/ld-arm/armthumb-lib.sym b/binutils-2.21/ld/testsuite/ld-arm/armthumb-lib.sym new file mode 100644 index 0000000..c7f4728 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/armthumb-lib.sym @@ -0,0 +1,15 @@ + +Symbol table for image: + +Num +Buc: +Value +Size +Type +Bind +Vis +Ndx +Name + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS _edata + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_start__ + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS _end + +.. +..: ........ +4 +OBJECT +GLOBAL +DEFAULT +9 data_obj + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_end__ + +.. +..: .......0 +20 +FUNC +GLOBAL +DEFAULT +6 lib_func1 + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +9 __data_start + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __end__ + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_start + +.. +..: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND app_func2 + +.. +..: .......0 +2 +FUNC +GLOBAL +DEFAULT +6 lib_func2 + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS _bss_end__ diff --git a/binutils-2.21/ld/testsuite/ld-arm/armv4-bx.d b/binutils-2.21/ld/testsuite/ld-arm/armv4-bx.d new file mode 100644 index 0000000..b30af8c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/armv4-bx.d @@ -0,0 +1,19 @@ + +.*: .*file format elf32-(big|little)arm + +Disassembly of section \.text: + +00008000 <_start>: + 8000: ea000001 b 800c \<__bx_r14\> + 8004: ea000003 b 8018 \<__bx_r0\> + 8008: 0a000002 beq 8018 \<__bx_r0\> + +0000800c <__bx_r14>: + 800c: e31e0001 tst lr, #1 + 8010: 01a0f00e moveq pc, lr + 8014: e12fff1e bx lr + +00008018 <__bx_r0>: + 8018: e3100001 tst r0, #1 + 801c: 01a0f000 moveq pc, r0 + 8020: e12fff10 bx r0 diff --git a/binutils-2.21/ld/testsuite/ld-arm/armv4-bx.s b/binutils-2.21/ld/testsuite/ld-arm/armv4-bx.s new file mode 100644 index 0000000..ef86357 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/armv4-bx.s @@ -0,0 +1,8 @@ +.text +.arch armv4 +.global _start +.type _start, %function +_start: +bx lr +bx r0 +bxeq r0 diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-2.attr b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-2.attr new file mode 100644 index 0000000..e34111b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-2.attr @@ -0,0 +1,15 @@ +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 4 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Allowed in v7-A with integer division extension diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-2a.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-2a.s new file mode 100644 index 0000000..9d9ae18 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-2a.s @@ -0,0 +1,11 @@ + .cpu arm7tdmi + .fpu softvfp + .eabi_attribute 20, 1 + .eabi_attribute 21, 1 + .eabi_attribute 23, 3 + .eabi_attribute 24, 1 + .eabi_attribute 25, 1 + .eabi_attribute 26, 1 + .eabi_attribute 30, 6 + .eabi_attribute Tag_DIV_use, 1 + .file "attr-merge-2a.s" diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-2b.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-2b.s new file mode 100644 index 0000000..6aa8da9 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-2b.s @@ -0,0 +1,12 @@ + .cpu arm7tdmi + .fpu softvfp + .eabi_attribute 20, 1 + .eabi_attribute 21, 1 + .eabi_attribute 23, 3 + .eabi_attribute 24, 1 + .eabi_attribute 25, 1 + .eabi_attribute 26, 1 + .eabi_attribute 30, 6 + .eabi_attribute 18, 4 + .eabi_attribute Tag_DIV_use, 2 + .file "attr-merge-2b.s" diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-3.attr b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-3.attr new file mode 100644 index 0000000..b0f8ef9 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-3.attr @@ -0,0 +1,31 @@ +Attribute Section: aeabi +File Attributes + Tag_nodefaults: True + Tag_CPU_name: "ARM9E" + Tag_CPU_arch: v5T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_FP_arch: VFPv3 + Tag_WMMX_arch: WMMXv2 + Tag_Advanced_SIMD_arch: NEONv1 + Tag_PCS_config: Linux application + Tag_ABI_PCS_R9_use: SB + Tag_ABI_PCS_RW_data: PC-relative + Tag_ABI_PCS_RO_data: PC-relative + Tag_ABI_PCS_GOT_use: direct + Tag_ABI_PCS_wchar_t: 4 + Tag_ABI_FP_rounding: Needed + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_user_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_HardFP_use: SP and DP + Tag_ABI_VFP_args: VFP registers + Tag_CPU_unaligned_access: v6 + Tag_FP_HP_extension: Allowed + Tag_MPextension_use: Allowed + Tag_T2EE_use: Allowed + Tag_Virtualization_use: TrustZone diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-3a.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-3a.s new file mode 100644 index 0000000..bc7a0c1 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-3a.s @@ -0,0 +1,39 @@ + .cpu arm7tdmi + .fpu softvfp + .eabi_attribute Tag_CPU_arch, 2 + @ .eabi_attribute Tag_CPU_arch_profile, 0x41 + .eabi_attribute Tag_ARM_ISA_use, 0 + .eabi_attribute Tag_THUMB_ISA_use, 1 + .eabi_attribute Tag_VFP_arch, 3 + .eabi_attribute Tag_WMMX_arch, 1 + .eabi_attribute Tag_Advanced_SIMD_arch, 0 + .eabi_attribute Tag_PCS_config, 0 + .eabi_attribute Tag_ABI_PCS_R9_use, 1 + .eabi_attribute Tag_ABI_PCS_RW_data, 1 + .eabi_attribute Tag_ABI_PCS_RO_data, 1 + .eabi_attribute Tag_ABI_PCS_GOT_use, 1 + .eabi_attribute Tag_ABI_PCS_wchar_t, 4 + .eabi_attribute Tag_ABI_FP_rounding, 0 + .eabi_attribute Tag_ABI_FP_denormal, 1 + .eabi_attribute Tag_ABI_FP_exceptions, 0 + .eabi_attribute Tag_ABI_FP_user_exceptions, 0 + .eabi_attribute Tag_ABI_FP_number_model, 0 + .eabi_attribute Tag_ABI_align8_needed, 1 + .eabi_attribute Tag_ABI_align8_preserved, 1 + .eabi_attribute Tag_ABI_enum_size, 1 + .eabi_attribute Tag_ABI_HardFP_use, 1 + .eabi_attribute Tag_ABI_VFP_args, 0 + @ .eabi_attribute Tag_ABI_WMMX_args, 0 + @ .eabi_attribute Tag_ABI_optimization_goals, 0 + @ .eabi_attribute Tag_ABI_FP_optimization_goals, 0 + @ .eabi_attribute Tag_compatibility, 1, "gnu" + .eabi_attribute Tag_CPU_unaligned_access, 0 + .eabi_attribute Tag_VFP_HP_extension, 0 + @ .eabi_attribute Tag_ABI_FP_16bit_format, 0 + .eabi_attribute Tag_nodefaults, 0 + @ .eabi_attribute Tag_also_compatible_with, + .eabi_attribute Tag_T2EE_use, 0 + .eabi_attribute Tag_conformance, "0" + .eabi_attribute Tag_Virtualization_use, 0 + .eabi_attribute Tag_MPextension_use, 0 + .eabi_attribute Tag_DIV_use, 0 diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-3b.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-3b.s new file mode 100644 index 0000000..681f661 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-3b.s @@ -0,0 +1,39 @@ + .cpu arm9e + .fpu neon + .eabi_attribute Tag_CPU_arch, 3 + @ .eabi_attribute Tag_CPU_arch_profile, 0x41 + .eabi_attribute Tag_ARM_ISA_use, 1 + .eabi_attribute Tag_THUMB_ISA_use, 2 + .eabi_attribute Tag_VFP_arch, 4 + .eabi_attribute Tag_WMMX_arch, 2 + .eabi_attribute Tag_Advanced_SIMD_arch, 1 + .eabi_attribute Tag_PCS_config, 2 + .eabi_attribute Tag_ABI_PCS_R9_use, 3 + .eabi_attribute Tag_ABI_PCS_RW_data, 3 + .eabi_attribute Tag_ABI_PCS_RO_data, 2 + .eabi_attribute Tag_ABI_PCS_GOT_use, 2 + .eabi_attribute Tag_ABI_PCS_wchar_t, 0 + .eabi_attribute Tag_ABI_FP_rounding, 1 + .eabi_attribute Tag_ABI_FP_denormal, 2 + .eabi_attribute Tag_ABI_FP_exceptions, 1 + .eabi_attribute Tag_ABI_FP_user_exceptions, 1 + .eabi_attribute Tag_ABI_FP_number_model, 3 + .eabi_attribute Tag_ABI_align8_needed, 2 + .eabi_attribute Tag_ABI_align8_preserved, 2 + .eabi_attribute Tag_ABI_enum_size, 3 + .eabi_attribute Tag_ABI_HardFP_use, 2 + .eabi_attribute Tag_ABI_VFP_args, 1 + @ .eabi_attribute Tag_ABI_WMMX_args, 0 + @ .eabi_attribute Tag_ABI_optimization_goals, 0 + @ .eabi_attribute Tag_ABI_FP_optimization_goals, 0 + @ .eabi_attribute Tag_compatibility, 1, "gnu" + .eabi_attribute Tag_CPU_unaligned_access, 1 + .eabi_attribute Tag_VFP_HP_extension, 1 + @ .eabi_attribute Tag_ABI_FP_16bit_format, 0 + .eabi_attribute Tag_nodefaults, 1 + @ .eabi_attribute Tag_also_compatible_with, + .eabi_attribute Tag_T2EE_use, 1 + .eabi_attribute Tag_conformance, "2.08" + .eabi_attribute Tag_Virtualization_use, 1 + .eabi_attribute Tag_MPextension_use, 1 + .eabi_attribute Tag_DIV_use, 1 diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-4.attr b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-4.attr new file mode 100644 index 0000000..c8fc7ec --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-4.attr @@ -0,0 +1,9 @@ +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_CPU_arch_profile: Microcontroller + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_DIV_use: Not allowed + Tag_also_compatible_with: v6-M diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-4a.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-4a.s new file mode 100644 index 0000000..b5b77bf --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-4a.s @@ -0,0 +1,7 @@ + .cpu arm7tdmi + + @ Tag_CPU_arch = v4T + .eabi_attribute Tag_CPU_arch, 2 + + @ Tag_also_compatible_with = v6-M + .eabi_attribute Tag_also_compatible_with, "\006\013" diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-4b.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-4b.s new file mode 100644 index 0000000..d2eb6de --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-4b.s @@ -0,0 +1,7 @@ + .cpu cortex-m1 + + @ Tag_CPU_arch = v6-M + .eabi_attribute Tag_CPU_arch, 11 + + @ Tag_also_compatible_with = v4T + .eabi_attribute Tag_also_compatible_with, "\006\002" diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-5.attr b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-5.attr new file mode 100644 index 0000000..f016708 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-5.attr @@ -0,0 +1,6 @@ +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_compatibility: flag = 1, vendor = gnu + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-5.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-5.s new file mode 100644 index 0000000..583d253 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-5.s @@ -0,0 +1 @@ + .eabi_attribute Tag_compatibility, 1, "gnu" diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-6.attr b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-6.attr new file mode 100644 index 0000000..9e2324f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-6.attr @@ -0,0 +1,10 @@ +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "Cortex-A9" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_MPextension_use: Allowed + Tag_DIV_use: Not allowed + Tag_Virtualization_use: TrustZone diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-6a.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-6a.s new file mode 100644 index 0000000..056d8c8 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-6a.s @@ -0,0 +1,4 @@ + .cpu cortex-a9 + .fpu softvfp + .eabi_attribute 70, 1 + .file "attr-merge-6a.s" diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-6b.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-6b.s new file mode 100644 index 0000000..b9ef4d2 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-6b.s @@ -0,0 +1,3 @@ + .cpu cortex-a9 + .fpu softvfp + .file "attr-merge-6b.s" diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-7.attr b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-7.attr new file mode 100644 index 0000000..9e2324f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-7.attr @@ -0,0 +1,10 @@ +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "Cortex-A9" + Tag_CPU_arch: v7 + Tag_CPU_arch_profile: Application + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_MPextension_use: Allowed + Tag_DIV_use: Not allowed + Tag_Virtualization_use: TrustZone diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-7a.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-7a.s new file mode 100644 index 0000000..d875d28 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-7a.s @@ -0,0 +1,4 @@ + .cpu cortex-a9 + .fpu softvfp + .eabi_attribute 70, 1 + .file "attr-merge-7a.s" diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-7b.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-7b.s new file mode 100644 index 0000000..2e83e71 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-7b.s @@ -0,0 +1,4 @@ + .cpu cortex-a9 + .fpu softvfp + .eabi_attribute Tag_MPextension_use, 1 + .file "attr-merge-7b.s" diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-arch-1.attr b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-arch-1.attr new file mode 100644 index 0000000..b39634f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-arch-1.attr @@ -0,0 +1,7 @@ +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM v7" + Tag_CPU_arch: v7 + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-2 + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-arch-2.attr b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-arch-2.attr new file mode 100644 index 0000000..ab8916b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-arch-2.attr @@ -0,0 +1,8 @@ +Attribute Section: aeabi +File Attributes + Tag_CPU_raw_name: "arch_v6k" + Tag_CPU_name: "MPCore" + Tag_CPU_arch: v6K + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-incompatible.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-incompatible.d new file mode 100644 index 0000000..41711da --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-incompatible.d @@ -0,0 +1,5 @@ +#source: attr-merge-incompatibleb.s +#source: attr-merge-incompatiblea.s +#as: +#ld: +#error: Object has vendor-specific contents that must be processed by the '.+' toolchain diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-incompatiblea.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-incompatiblea.s new file mode 100644 index 0000000..03e0f7e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-incompatiblea.s @@ -0,0 +1 @@ + .eabi_attribute Tag_compatibility, 1, "Random Toolchain Vendor" diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-incompatibleb.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-incompatibleb.s new file mode 100644 index 0000000..583d253 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-incompatibleb.s @@ -0,0 +1 @@ + .eabi_attribute Tag_compatibility, 1, "gnu" diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-1.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-1.d new file mode 100644 index 0000000..38acff9 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-1.d @@ -0,0 +1,5 @@ +#source: attr-merge-unknown-1.s +#source: blank.s +#as: +#ld: +#error: Unknown mandatory EABI object attribute 40 diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-1.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-1.s new file mode 100644 index 0000000..d2cff1f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-1.s @@ -0,0 +1,3 @@ + @ This attrubute is supposed to be unknown. + @ If this number should become known, change it. + .eabi_attribute 40, 1 diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-2.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-2.d new file mode 100644 index 0000000..5755803 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-2.d @@ -0,0 +1,14 @@ +#source: attr-merge-unknown-2.s +#source: blank.s +#as: +#ld: +#warning: Unknown EABI object attribute 82 +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-2.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-2.s new file mode 100644 index 0000000..d8d61e0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-2.s @@ -0,0 +1,3 @@ + @ This attrubute is supposed to be unknown. + @ If this number should become known, change it. + .eabi_attribute 82, 1 diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-2r.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-2r.d new file mode 100644 index 0000000..d950b3e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-2r.d @@ -0,0 +1,14 @@ +#source: blank.s +#source: attr-merge-unknown-2.s +#as: +#ld: +#warning: Unknown EABI object attribute 82 +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-3.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-3.d new file mode 100644 index 0000000..c210a06 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-unknown-3.d @@ -0,0 +1,15 @@ +#source: attr-merge-unknown-2.s +#source: attr-merge-unknown-2.s +#as: +#ld: +#warning: Unknown EABI object attribute 82 +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_DIV_use: Not allowed + Tag_unknown_82: 1 \(0x1\) diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-1.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-1.d new file mode 100644 index 0000000..99fc8e4 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-1.d @@ -0,0 +1,14 @@ +#source: attr-merge-vfp-2.s +#source: attr-merge-vfp-3-d16.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv3-D16 + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-1r.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-1r.d new file mode 100644 index 0000000..42bfe99 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-1r.d @@ -0,0 +1,14 @@ +#source: attr-merge-vfp-3-d16.s +#source: attr-merge-vfp-2.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv3-D16 + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-2.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-2.d new file mode 100644 index 0000000..3161e11 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-2.d @@ -0,0 +1,14 @@ +#source: attr-merge-vfp-3.s +#source: attr-merge-vfp-3-d16.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv3 + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-2.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-2.s new file mode 100644 index 0000000..32657d3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-2.s @@ -0,0 +1,2 @@ +.fpu vfpv2 + diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-2r.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-2r.d new file mode 100644 index 0000000..9c6367f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-2r.d @@ -0,0 +1,14 @@ +#source: attr-merge-vfp-3-d16.s +#source: attr-merge-vfp-3.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv3 + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-3-d16.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-3-d16.s new file mode 100644 index 0000000..74729e0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-3-d16.s @@ -0,0 +1,2 @@ +.fpu vfpv3-d16 + diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-3.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-3.d new file mode 100644 index 0000000..9853879 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-3.d @@ -0,0 +1,15 @@ +#source: attr-merge-vfp-3-d16.s +#source: attr-merge-vfp-4-d16.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv4-D16 + Tag_FP_HP_extension: Allowed + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-3.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-3.s new file mode 100644 index 0000000..4d60323 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-3.s @@ -0,0 +1,2 @@ +.fpu vfpv3 + diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-3r.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-3r.d new file mode 100644 index 0000000..24df972 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-3r.d @@ -0,0 +1,15 @@ +#source: attr-merge-vfp-4-d16.s +#source: attr-merge-vfp-3-d16.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv4-D16 + Tag_FP_HP_extension: Allowed + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-4-d16.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-4-d16.s new file mode 100644 index 0000000..8d8aedd --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-4-d16.s @@ -0,0 +1,2 @@ +.fpu vfpv4-d16 + diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-4.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-4.d new file mode 100644 index 0000000..469fc9b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-4.d @@ -0,0 +1,15 @@ +#source: attr-merge-vfp-3.s +#source: attr-merge-vfp-4-d16.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv4 + Tag_FP_HP_extension: Allowed + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-4.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-4.s new file mode 100644 index 0000000..190cdc0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-4.s @@ -0,0 +1,2 @@ +.fpu vfpv4 + diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-4r.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-4r.d new file mode 100644 index 0000000..c84e508 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-4r.d @@ -0,0 +1,15 @@ +#source: attr-merge-vfp-4-d16.s +#source: attr-merge-vfp-3.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv4 + Tag_FP_HP_extension: Allowed + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-5.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-5.d new file mode 100644 index 0000000..dc0c6ee --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-5.d @@ -0,0 +1,15 @@ +#source: attr-merge-vfp-4.s +#source: attr-merge-vfp-4-d16.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv4 + Tag_FP_HP_extension: Allowed + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-5r.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-5r.d new file mode 100644 index 0000000..5e1d23a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-5r.d @@ -0,0 +1,15 @@ +#source: attr-merge-vfp-4-d16.s +#source: attr-merge-vfp-4.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv4 + Tag_FP_HP_extension: Allowed + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-6.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-6.d new file mode 100644 index 0000000..ca89181 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-6.d @@ -0,0 +1,15 @@ +#source: attr-merge-vfp-3.s +#source: attr-merge-vfpv3xd.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv3 + Tag_ABI_HardFP_use: SP and DP + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-6r.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-6r.d new file mode 100644 index 0000000..f533632 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfp-6r.d @@ -0,0 +1,15 @@ +#source: attr-merge-vfpv3xd.s +#source: attr-merge-vfp-3.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_FP_arch: VFPv3 + Tag_ABI_HardFP_use: SP and DP + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfpv3xd.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfpv3xd.s new file mode 100644 index 0000000..295ca17 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-vfpv3xd.s @@ -0,0 +1,2 @@ +.fpu vfpv3xd + diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-0.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-0.s new file mode 100644 index 0000000..ef19a88 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-0.s @@ -0,0 +1,11 @@ + .cpu arm7tdmi + .fpu softvfp + .eabi_attribute 20, 1 + .eabi_attribute 21, 1 + .eabi_attribute 23, 3 + .eabi_attribute 24, 1 + .eabi_attribute 25, 1 + .eabi_attribute 26, 1 + .eabi_attribute 30, 6 + .eabi_attribute 18, 0 + .file "attr-merge-wchar-0.s" diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-00-nowarn.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-00-nowarn.d new file mode 100644 index 0000000..88e5d25 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-00-nowarn.d @@ -0,0 +1,22 @@ +#source: attr-merge-wchar-0.s +#source: attr-merge-wchar-0.s +#as: +#ld: -r --no-wchar-size-warning +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-00.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-00.d new file mode 100644 index 0000000..73df821 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-00.d @@ -0,0 +1,22 @@ +#source: attr-merge-wchar-0.s +#source: attr-merge-wchar-0.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-02-nowarn.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-02-nowarn.d new file mode 100644 index 0000000..f55bf52 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-02-nowarn.d @@ -0,0 +1,23 @@ +#source: attr-merge-wchar-0.s +#source: attr-merge-wchar-2.s +#as: +#ld: -r --no-wchar-size-warning +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 2 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-02.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-02.d new file mode 100644 index 0000000..500b6a9 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-02.d @@ -0,0 +1,23 @@ +#source: attr-merge-wchar-0.s +#source: attr-merge-wchar-2.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 2 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-04-nowarn.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-04-nowarn.d new file mode 100644 index 0000000..c1d4efd --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-04-nowarn.d @@ -0,0 +1,23 @@ +#source: attr-merge-wchar-0.s +#source: attr-merge-wchar-4.s +#as: +#ld: -r --no-wchar-size-warning +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 4 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-04.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-04.d new file mode 100644 index 0000000..cd11980 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-04.d @@ -0,0 +1,23 @@ +#source: attr-merge-wchar-0.s +#source: attr-merge-wchar-4.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 4 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-2.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-2.s new file mode 100644 index 0000000..4b3b96b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-2.s @@ -0,0 +1,11 @@ + .cpu arm7tdmi + .fpu softvfp + .eabi_attribute 20, 1 + .eabi_attribute 21, 1 + .eabi_attribute 23, 3 + .eabi_attribute 24, 1 + .eabi_attribute 25, 1 + .eabi_attribute 26, 1 + .eabi_attribute 30, 6 + .eabi_attribute 18, 2 + .file "attr-merge-wchar-2.s" diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-20-nowarn.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-20-nowarn.d new file mode 100644 index 0000000..b60e458 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-20-nowarn.d @@ -0,0 +1,23 @@ +#source: attr-merge-wchar-2.s +#source: attr-merge-wchar-0.s +#as: +#ld: -r --no-wchar-size-warning +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 2 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-20.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-20.d new file mode 100644 index 0000000..96738b1 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-20.d @@ -0,0 +1,23 @@ +#source: attr-merge-wchar-2.s +#source: attr-merge-wchar-0.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 2 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-22-nowarn.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-22-nowarn.d new file mode 100644 index 0000000..22539de --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-22-nowarn.d @@ -0,0 +1,23 @@ +#source: attr-merge-wchar-2.s +#source: attr-merge-wchar-2.s +#as: +#ld: -r --no-wchar-size-warning +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 2 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-22.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-22.d new file mode 100644 index 0000000..c0e67dc --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-22.d @@ -0,0 +1,23 @@ +#source: attr-merge-wchar-2.s +#source: attr-merge-wchar-2.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 2 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-24-nowarn.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-24-nowarn.d new file mode 100644 index 0000000..e7f2566 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-24-nowarn.d @@ -0,0 +1,23 @@ +#source: attr-merge-wchar-2.s +#source: attr-merge-wchar-4.s +#as: +#ld: -r --no-wchar-size-warning +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 2 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-24.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-24.d new file mode 100644 index 0000000..46d6c66 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-24.d @@ -0,0 +1,5 @@ +#source: attr-merge-wchar-2.s +#source: attr-merge-wchar-4.s +#as: +#ld: -r +#warning: warning: .* uses 4-byte wchar_t yet the output is to use 2-byte wchar_t; use of wchar_t values across objects may fail diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-4.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-4.s new file mode 100644 index 0000000..fdd03f9 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-4.s @@ -0,0 +1,11 @@ + .cpu arm7tdmi + .fpu softvfp + .eabi_attribute 20, 1 + .eabi_attribute 21, 1 + .eabi_attribute 23, 3 + .eabi_attribute 24, 1 + .eabi_attribute 25, 1 + .eabi_attribute 26, 1 + .eabi_attribute 30, 6 + .eabi_attribute 18, 4 + .file "attr-merge-wchar-4.s" diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-40-nowarn.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-40-nowarn.d new file mode 100644 index 0000000..efeafcc --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-40-nowarn.d @@ -0,0 +1,23 @@ +#source: attr-merge-wchar-4.s +#source: attr-merge-wchar-0.s +#as: +#ld: -r --no-wchar-size-warning +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 4 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-40.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-40.d new file mode 100644 index 0000000..39cb58a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-40.d @@ -0,0 +1,23 @@ +#source: attr-merge-wchar-4.s +#source: attr-merge-wchar-0.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 4 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-42-nowarn.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-42-nowarn.d new file mode 100644 index 0000000..b989f35 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-42-nowarn.d @@ -0,0 +1,23 @@ +#source: attr-merge-wchar-4.s +#source: attr-merge-wchar-2.s +#as: +#ld: -r --no-wchar-size-warning +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 4 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-42.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-42.d new file mode 100644 index 0000000..c2aca5e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-42.d @@ -0,0 +1,5 @@ +#source: attr-merge-wchar-4.s +#source: attr-merge-wchar-2.s +#as: +#ld: -r +#warning: warning: .* uses 2-byte wchar_t yet the output is to use 4-byte wchar_t; use of wchar_t values across objects may fail diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-44-nowarn.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-44-nowarn.d new file mode 100644 index 0000000..988dd6e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-44-nowarn.d @@ -0,0 +1,23 @@ +#source: attr-merge-wchar-4.s +#source: attr-merge-wchar-4.s +#as: +#ld: -r --no-wchar-size-warning +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 4 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-44.d b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-44.d new file mode 100644 index 0000000..acda7e7 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge-wchar-44.d @@ -0,0 +1,23 @@ +#source: attr-merge-wchar-4.s +#source: attr-merge-wchar-4.s +#as: +#ld: -r +#readelf: -A +# This test is only valid on ELF based ports. +# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 4 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge.attr b/binutils-2.21/ld/testsuite/ld-arm/attr-merge.attr new file mode 100644 index 0000000..f07930e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge.attr @@ -0,0 +1,15 @@ +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "ARM7TDMI" + Tag_CPU_arch: v4T + Tag_ARM_ISA_use: Yes + Tag_THUMB_ISA_use: Thumb-1 + Tag_ABI_PCS_wchar_t: 4 + Tag_ABI_FP_denormal: Needed + Tag_ABI_FP_exceptions: Needed + Tag_ABI_FP_number_model: IEEE 754 + Tag_ABI_align_needed: 8-byte + Tag_ABI_align_preserved: 8-byte, except leaf SP + Tag_ABI_enum_size: small + Tag_ABI_optimization_goals: Aggressive Debug + Tag_DIV_use: Not allowed diff --git a/binutils-2.21/ld/testsuite/ld-arm/attr-merge.s b/binutils-2.21/ld/testsuite/ld-arm/attr-merge.s new file mode 100644 index 0000000..b56f6e3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/attr-merge.s @@ -0,0 +1,11 @@ + .cpu arm7tdmi + .fpu softvfp + .eabi_attribute 20, 1 + .eabi_attribute 21, 1 + .eabi_attribute 23, 3 + .eabi_attribute 24, 1 + .eabi_attribute 25, 1 + .eabi_attribute 26, 1 + .eabi_attribute 30, 6 + .eabi_attribute 18, 4 + .file "attr-merge.s" diff --git a/binutils-2.21/ld/testsuite/ld-arm/blank.s b/binutils-2.21/ld/testsuite/ld-arm/blank.s new file mode 100644 index 0000000..1d22054 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/blank.s @@ -0,0 +1 @@ +@ this file left intentionally blank diff --git a/binutils-2.21/ld/testsuite/ld-arm/callweak-2.d b/binutils-2.21/ld/testsuite/ld-arm/callweak-2.d new file mode 100644 index 0000000..d401479 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/callweak-2.d @@ -0,0 +1,15 @@ + +.*: file format.* + +Disassembly of section .far: + +12340000 <[^>]*>: +12340000: e320f000 nop \{0\} +12340004: 0320f000 nopeq \{0\} + +12340008 <[^>]*>: +12340008: f3af 8000 nop.w +1234000c: 2000 movs r0, #0 +1234000e: f3af 8000 nop.w +12340012: 4770 bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/callweak-2.s b/binutils-2.21/ld/testsuite/ld-arm/callweak-2.s new file mode 100644 index 0000000..af4f026 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/callweak-2.s @@ -0,0 +1,17 @@ + .syntax unified + .arch armv6t2 + .weak bar + .section .far, "ax", %progbits + .global _start + .type _start, %function +_start: + bl bar + bleq bar + .thumb + .type foo, %function + .thumb_func +foo: + bl bar + movs r0, #0 + bl bar + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/callweak.d b/binutils-2.21/ld/testsuite/ld-arm/callweak.d new file mode 100644 index 0000000..89cb4a5 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/callweak.d @@ -0,0 +1,17 @@ + +.*: file format.* + +Disassembly of section .far: + +12340000 <[^>]*>: +12340000: e1a00000 nop ; \(mov r0, r0\) +12340004: 01a00000 moveq r0, r0 + +12340008 <[^>]*>: +12340008: e000 b.n 1234000c <[^>]*> +1234000a: bf00 nop +1234000c: 2000 movs r0, #0 +1234000e: e000 b.n 12340012 <[^>]*> +12340010: bf00 nop +12340012: 4770 bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/callweak.s b/binutils-2.21/ld/testsuite/ld-arm/callweak.s new file mode 100644 index 0000000..b9bcd1b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/callweak.s @@ -0,0 +1,17 @@ + .syntax unified + .arch armv6 + .weak bar + .section .far, "ax", %progbits + .global _start + .type _start, %function +_start: + bl bar + bleq bar + .thumb + .type foo, %function + .thumb_func +foo: + bl bar + movs r0, #0 + bl bar + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-arm-target.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-arm-target.s new file mode 100644 index 0000000..d5174c4 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-arm-target.s @@ -0,0 +1,9 @@ + .syntax unified + .cpu cortex-a8 + .text + .arm + .align 3 + .global targetfn + .type targetfn, %function +targetfn: + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-far-1.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-far-1.s new file mode 100644 index 0000000..09d3583 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-far-1.s @@ -0,0 +1,8 @@ + .syntax unified + .thumb + .globl two +two: + bl far_fn + .rept 0x200000 + .long 0 + .endr diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-far-2.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-far-2.s new file mode 100644 index 0000000..22fd40f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-far-2.s @@ -0,0 +1,20 @@ + .syntax unified + .thumb +three: + bl far_fn1 + bl far_fn2 + .rept 1016 + .long 0 + .endr + nop +label1: + eor.w r0, r1, r2 + beq.w label1 + + eor.w r0, r1, r2 + + eor.w r0, r1, r2 + b.w label1 + + eor.w r0, r1, r2 + eor.w r0, r1, r2 diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-far.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-far.d new file mode 100644 index 0000000..e327ac1 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-far.d @@ -0,0 +1,40 @@ + +.*: file format .* + + +Disassembly of section \.text: + +00000000 <two>: + 0: f000 c802 blx 800008 <__far_fn_from_thumb> + ... +#... +00800008 <__far_fn_from_thumb>: + 800008: e51ff004 ldr pc, \[pc, #-4\] ; 80000c <__far_fn_from_thumb\+0x4> + 80000c: 7fff0000 .word 0x7fff0000 + +00800010 <three>: + 800010: f001 e802 blx 801018 <__far_fn1_from_thumb> + 800014: f001 e804 blx 801020 <__far_fn2_from_thumb> + ... + 800ff8: bf00 nop + +00800ffa <label1>: + 800ffa: ea81 0002 eor.w r0, r1, r2 + 800ffe: f000 b813 b.w 801028 <__far_fn2_from_thumb\+0x8> + 801002: ea81 0002 eor.w r0, r1, r2 + 801006: ea81 0002 eor.w r0, r1, r2 + 80100a: f7ff bff6 b.w 800ffa <label1> + 80100e: ea81 0002 eor.w r0, r1, r2 + 801012: ea81 0002 eor.w r0, r1, r2 + ... + +00801018 <__far_fn1_from_thumb>: + 801018: e51ff004 ldr pc, \[pc, #-4\] ; 80101c <__far_fn1_from_thumb\+0x4> + 80101c: 80000000 .word 0x80000000 + +00801020 <__far_fn2_from_thumb>: + 801020: e51ff004 ldr pc, \[pc, #-4\] ; 801024 <__far_fn2_from_thumb\+0x4> + 801024: 80000004 .word 0x80000004 + 801028: d001 beq.n 80102e <__far_fn2_from_thumb\+0xe> + 80102a: f7ff bfea b.w 801002 <label1\+0x8> + 80102e: f7ff bfe4 b.w 800ffa <label1> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d new file mode 100644 index 0000000..59efecb --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d @@ -0,0 +1,30 @@ + +.* + + +Disassembly of section \.plt: + +00008000 <\.plt>: + 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <foo-0xfe0> + 8008: e08fe00e add lr, pc, lr + 800c: e5bef008 ldr pc, \[lr, #8\]! + 8010: 00000ffc \.word 0x00000ffc + 8014: 4778 bx pc + 8016: 46c0 nop ; \(mov r8, r8\) + 8018: e28fc600 add ip, pc, #0 + 801c: e28cca00 add ip, ip, #0 + 8020: e5bcfff8 ldr pc, \[ip, #4088\]! ; 0xff8 + +Disassembly of section \.text: + +00008ff0 <foo>: + 8ff0: 46c0 nop ; \(mov r8, r8\) + 8ff2: f240 0000 movw r0, #0 + 8ff6: f240 0000 movw r0, #0 + 8ffa: f240 0000 movw r0, #0 + 8ffe: f000 b803 b\.w 9008 <foo\+0x18> + 9002: 0000 movs r0, r0 + 9004: 0000 movs r0, r0 + 9006: 0000 movs r0, r0 + 9008: f7ff b804 b\.w 8014 <foo-0xfdc> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.s new file mode 100644 index 0000000..afd340d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.s @@ -0,0 +1,10 @@ + .syntax unified + .globl foo + .type foo,%function + .thumb_func +foo: + nop @ 0x00 + movw r0,#0 @ 0x02 + movw r0,#0 @ 0x06 + movw r0,#0 @ 0x0a + b.w bar(PLT) @ 0x0e diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d new file mode 100644 index 0000000..195a51b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-arm.d @@ -0,0 +1,83 @@ + +.*: file format .* + + +Disassembly of section \.text: + +00008f00 <targetfn>: + 8f00: e12fff1e bx lr + 8f04: e320f000 nop \{0\} + +00008f08 <_start>: + 8f08: bf00 nop + 8f0a: eb01 0002 add\.w r0, r1, r2 + 8f0e: f000 b87f b\.w 9010 <__targetfn_from_thumb> + 8f12: eb01 0002 add\.w r0, r1, r2 + 8f16: f000 b87b b\.w 9010 <__targetfn_from_thumb> + 8f1a: eb01 0002 add\.w r0, r1, r2 + 8f1e: f000 b877 b\.w 9010 <__targetfn_from_thumb> + 8f22: eb01 0002 add\.w r0, r1, r2 + 8f26: f000 b873 b\.w 9010 <__targetfn_from_thumb> + 8f2a: eb01 0002 add\.w r0, r1, r2 + 8f2e: f000 b86f b\.w 9010 <__targetfn_from_thumb> + 8f32: eb01 0002 add\.w r0, r1, r2 + 8f36: f000 b86b b\.w 9010 <__targetfn_from_thumb> + 8f3a: eb01 0002 add\.w r0, r1, r2 + 8f3e: f000 b867 b\.w 9010 <__targetfn_from_thumb> + 8f42: eb01 0002 add\.w r0, r1, r2 + 8f46: f000 b863 b\.w 9010 <__targetfn_from_thumb> + 8f4a: eb01 0002 add\.w r0, r1, r2 + 8f4e: f000 b85f b\.w 9010 <__targetfn_from_thumb> + 8f52: eb01 0002 add\.w r0, r1, r2 + 8f56: f000 b85b b\.w 9010 <__targetfn_from_thumb> + 8f5a: eb01 0002 add\.w r0, r1, r2 + 8f5e: f000 b857 b\.w 9010 <__targetfn_from_thumb> + 8f62: eb01 0002 add\.w r0, r1, r2 + 8f66: f000 b853 b\.w 9010 <__targetfn_from_thumb> + 8f6a: eb01 0002 add\.w r0, r1, r2 + 8f6e: f000 b84f b\.w 9010 <__targetfn_from_thumb> + 8f72: eb01 0002 add\.w r0, r1, r2 + 8f76: f000 b84b b\.w 9010 <__targetfn_from_thumb> + 8f7a: eb01 0002 add\.w r0, r1, r2 + 8f7e: f000 b847 b\.w 9010 <__targetfn_from_thumb> + 8f82: eb01 0002 add\.w r0, r1, r2 + 8f86: f000 b843 b\.w 9010 <__targetfn_from_thumb> + 8f8a: eb01 0002 add\.w r0, r1, r2 + 8f8e: f000 b83f b\.w 9010 <__targetfn_from_thumb> + 8f92: eb01 0002 add\.w r0, r1, r2 + 8f96: f000 b83b b\.w 9010 <__targetfn_from_thumb> + 8f9a: eb01 0002 add\.w r0, r1, r2 + 8f9e: f000 b837 b\.w 9010 <__targetfn_from_thumb> + 8fa2: eb01 0002 add\.w r0, r1, r2 + 8fa6: f000 b833 b\.w 9010 <__targetfn_from_thumb> + 8faa: eb01 0002 add\.w r0, r1, r2 + 8fae: f000 b82f b\.w 9010 <__targetfn_from_thumb> + 8fb2: eb01 0002 add\.w r0, r1, r2 + 8fb6: f000 b82b b\.w 9010 <__targetfn_from_thumb> + 8fba: eb01 0002 add\.w r0, r1, r2 + 8fbe: f000 b827 b\.w 9010 <__targetfn_from_thumb> + 8fc2: eb01 0002 add\.w r0, r1, r2 + 8fc6: f000 b823 b\.w 9010 <__targetfn_from_thumb> + 8fca: eb01 0002 add\.w r0, r1, r2 + 8fce: f000 b81f b\.w 9010 <__targetfn_from_thumb> + 8fd2: eb01 0002 add\.w r0, r1, r2 + 8fd6: f000 b81b b\.w 9010 <__targetfn_from_thumb> + 8fda: eb01 0002 add\.w r0, r1, r2 + 8fde: f000 b817 b\.w 9010 <__targetfn_from_thumb> + 8fe2: eb01 0002 add\.w r0, r1, r2 + 8fe6: f000 b813 b\.w 9010 <__targetfn_from_thumb> + 8fea: eb01 0002 add\.w r0, r1, r2 + 8fee: f000 b80f b\.w 9010 <__targetfn_from_thumb> + 8ff2: eb01 0002 add\.w r0, r1, r2 + 8ff6: f000 b80b b\.w 9010 <__targetfn_from_thumb> + 8ffa: eb01 0002 add\.w r0, r1, r2 + 8ffe: f000 b807 b\.w 9010 <__targetfn_from_thumb> + 9002: eb01 0002 add\.w r0, r1, r2 + 9006: f000 b803 b\.w 9010 <__targetfn_from_thumb> + 900a: 4770 bx lr + 900c: f3af 8000 nop\.w + +00009010 <__targetfn_from_thumb>: + 9010: 4778 bx pc + 9012: 46c0 nop ; \(mov r8, r8\) + 9014: eaffffb9 b 8f00 <targetfn> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-thumb.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-thumb.d new file mode 100644 index 0000000..60a254b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b-rel-thumb.d @@ -0,0 +1,80 @@ + +.*: file format .* + + +Disassembly of section \.text: + +00008f00 <targetfn>: + 8f00: 4770 bx lr + 8f02: bf00 nop + 8f04: f3af 8000 nop\.w + +00008f08 <_start>: + 8f08: bf00 nop + 8f0a: eb01 0002 add\.w r0, r1, r2 + 8f0e: f7ff bff7 b\.w 8f00 <targetfn> + 8f12: eb01 0002 add\.w r0, r1, r2 + 8f16: f7ff bff3 b\.w 8f00 <targetfn> + 8f1a: eb01 0002 add\.w r0, r1, r2 + 8f1e: f7ff bfef b\.w 8f00 <targetfn> + 8f22: eb01 0002 add\.w r0, r1, r2 + 8f26: f7ff bfeb b\.w 8f00 <targetfn> + 8f2a: eb01 0002 add\.w r0, r1, r2 + 8f2e: f7ff bfe7 b\.w 8f00 <targetfn> + 8f32: eb01 0002 add\.w r0, r1, r2 + 8f36: f7ff bfe3 b\.w 8f00 <targetfn> + 8f3a: eb01 0002 add\.w r0, r1, r2 + 8f3e: f7ff bfdf b\.w 8f00 <targetfn> + 8f42: eb01 0002 add\.w r0, r1, r2 + 8f46: f7ff bfdb b\.w 8f00 <targetfn> + 8f4a: eb01 0002 add\.w r0, r1, r2 + 8f4e: f7ff bfd7 b\.w 8f00 <targetfn> + 8f52: eb01 0002 add\.w r0, r1, r2 + 8f56: f7ff bfd3 b\.w 8f00 <targetfn> + 8f5a: eb01 0002 add\.w r0, r1, r2 + 8f5e: f7ff bfcf b\.w 8f00 <targetfn> + 8f62: eb01 0002 add\.w r0, r1, r2 + 8f66: f7ff bfcb b\.w 8f00 <targetfn> + 8f6a: eb01 0002 add\.w r0, r1, r2 + 8f6e: f7ff bfc7 b\.w 8f00 <targetfn> + 8f72: eb01 0002 add\.w r0, r1, r2 + 8f76: f7ff bfc3 b\.w 8f00 <targetfn> + 8f7a: eb01 0002 add\.w r0, r1, r2 + 8f7e: f7ff bfbf b\.w 8f00 <targetfn> + 8f82: eb01 0002 add\.w r0, r1, r2 + 8f86: f7ff bfbb b\.w 8f00 <targetfn> + 8f8a: eb01 0002 add\.w r0, r1, r2 + 8f8e: f7ff bfb7 b\.w 8f00 <targetfn> + 8f92: eb01 0002 add\.w r0, r1, r2 + 8f96: f7ff bfb3 b\.w 8f00 <targetfn> + 8f9a: eb01 0002 add\.w r0, r1, r2 + 8f9e: f7ff bfaf b\.w 8f00 <targetfn> + 8fa2: eb01 0002 add\.w r0, r1, r2 + 8fa6: f7ff bfab b\.w 8f00 <targetfn> + 8faa: eb01 0002 add\.w r0, r1, r2 + 8fae: f7ff bfa7 b\.w 8f00 <targetfn> + 8fb2: eb01 0002 add\.w r0, r1, r2 + 8fb6: f7ff bfa3 b\.w 8f00 <targetfn> + 8fba: eb01 0002 add\.w r0, r1, r2 + 8fbe: f7ff bf9f b\.w 8f00 <targetfn> + 8fc2: eb01 0002 add\.w r0, r1, r2 + 8fc6: f7ff bf9b b\.w 8f00 <targetfn> + 8fca: eb01 0002 add\.w r0, r1, r2 + 8fce: f7ff bf97 b\.w 8f00 <targetfn> + 8fd2: eb01 0002 add\.w r0, r1, r2 + 8fd6: f7ff bf93 b\.w 8f00 <targetfn> + 8fda: eb01 0002 add\.w r0, r1, r2 + 8fde: f7ff bf8f b\.w 8f00 <targetfn> + 8fe2: eb01 0002 add\.w r0, r1, r2 + 8fe6: f7ff bf8b b\.w 8f00 <targetfn> + 8fea: eb01 0002 add\.w r0, r1, r2 + 8fee: f7ff bf87 b\.w 8f00 <targetfn> + 8ff2: eb01 0002 add\.w r0, r1, r2 + 8ff6: f7ff bf83 b\.w 8f00 <targetfn> + 8ffa: eb01 0002 add\.w r0, r1, r2 + 8ffe: f000 b807 b\.w 9010 <_start\+0x108> + 9002: eb01 0002 add\.w r0, r1, r2 + 9006: f7ff bf7b b\.w 8f00 <targetfn> + 900a: 4770 bx lr + 900c: f3af 8000 nop\.w + 9010: f7ff bf76 b\.w 8f00 <targetfn> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b-rel.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b-rel.s new file mode 100644 index 0000000..3ec95ab --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b-rel.s @@ -0,0 +1,41 @@ + .syntax unified + .cpu cortex-a8 + .thumb + .text + + @ expansion 32 bytes + .macro bw1 +1: + add.w r0, r1, r2 + b.w targetfn + add.w r0, r1, r2 + b.w targetfn + add.w r0, r1, r2 + b.w targetfn + add.w r0, r1, r2 + b.w targetfn + .endm + + @ expansion 128 bytes + .macro bw2 + bw1 + bw1 + bw1 + bw1 + .endm + + .align 3 + .global _start + .thumb + .thumb_func + .type _start, %function +_start: + nop + + @ If branching to an ARM destination, we *don't* want to create a + @ Cortex-A8 stub: the Thumb-to-ARM stub will suffice (and we need it + @ to change mode). + bw2 + bw2 + + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b.d new file mode 100644 index 0000000..b2d4481 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b.d @@ -0,0 +1,75 @@ + +.*: file format .* + + +Disassembly of section \.text: + +00008f00 <_start>: + 8f00: bf00 nop + 8f02: eb01 0002 add\.w r0, r1, r2 + 8f06: f7ff bffc b\.w 8f02 <_start\+0x2> + 8f0a: eb01 0002 add\.w r0, r1, r2 + 8f0e: f7ff bff8 b\.w 8f02 <_start\+0x2> + 8f12: eb01 0002 add\.w r0, r1, r2 + 8f16: f7ff bff4 b\.w 8f02 <_start\+0x2> + 8f1a: eb01 0002 add\.w r0, r1, r2 + 8f1e: f7ff bff0 b\.w 8f02 <_start\+0x2> + 8f22: eb01 0002 add\.w r0, r1, r2 + 8f26: f7ff bffc b\.w 8f22 <_start\+0x22> + 8f2a: eb01 0002 add\.w r0, r1, r2 + 8f2e: f7ff bff8 b\.w 8f22 <_start\+0x22> + 8f32: eb01 0002 add\.w r0, r1, r2 + 8f36: f7ff bff4 b\.w 8f22 <_start\+0x22> + 8f3a: eb01 0002 add\.w r0, r1, r2 + 8f3e: f7ff bff0 b\.w 8f22 <_start\+0x22> + 8f42: eb01 0002 add\.w r0, r1, r2 + 8f46: f7ff bffc b\.w 8f42 <_start\+0x42> + 8f4a: eb01 0002 add\.w r0, r1, r2 + 8f4e: f7ff bff8 b\.w 8f42 <_start\+0x42> + 8f52: eb01 0002 add\.w r0, r1, r2 + 8f56: f7ff bff4 b\.w 8f42 <_start\+0x42> + 8f5a: eb01 0002 add\.w r0, r1, r2 + 8f5e: f7ff bff0 b\.w 8f42 <_start\+0x42> + 8f62: eb01 0002 add\.w r0, r1, r2 + 8f66: f7ff bffc b\.w 8f62 <_start\+0x62> + 8f6a: eb01 0002 add\.w r0, r1, r2 + 8f6e: f7ff bff8 b\.w 8f62 <_start\+0x62> + 8f72: eb01 0002 add\.w r0, r1, r2 + 8f76: f7ff bff4 b\.w 8f62 <_start\+0x62> + 8f7a: eb01 0002 add\.w r0, r1, r2 + 8f7e: f7ff bff0 b\.w 8f62 <_start\+0x62> + 8f82: eb01 0002 add\.w r0, r1, r2 + 8f86: f7ff bffc b\.w 8f82 <_start\+0x82> + 8f8a: eb01 0002 add\.w r0, r1, r2 + 8f8e: f7ff bff8 b\.w 8f82 <_start\+0x82> + 8f92: eb01 0002 add\.w r0, r1, r2 + 8f96: f7ff bff4 b\.w 8f82 <_start\+0x82> + 8f9a: eb01 0002 add\.w r0, r1, r2 + 8f9e: f7ff bff0 b\.w 8f82 <_start\+0x82> + 8fa2: eb01 0002 add\.w r0, r1, r2 + 8fa6: f7ff bffc b\.w 8fa2 <_start\+0xa2> + 8faa: eb01 0002 add\.w r0, r1, r2 + 8fae: f7ff bff8 b\.w 8fa2 <_start\+0xa2> + 8fb2: eb01 0002 add\.w r0, r1, r2 + 8fb6: f7ff bff4 b\.w 8fa2 <_start\+0xa2> + 8fba: eb01 0002 add\.w r0, r1, r2 + 8fbe: f7ff bff0 b\.w 8fa2 <_start\+0xa2> + 8fc2: eb01 0002 add\.w r0, r1, r2 + 8fc6: f7ff bffc b\.w 8fc2 <_start\+0xc2> + 8fca: eb01 0002 add\.w r0, r1, r2 + 8fce: f7ff bff8 b\.w 8fc2 <_start\+0xc2> + 8fd2: eb01 0002 add\.w r0, r1, r2 + 8fd6: f7ff bff4 b\.w 8fc2 <_start\+0xc2> + 8fda: eb01 0002 add\.w r0, r1, r2 + 8fde: f7ff bff0 b\.w 8fc2 <_start\+0xc2> + 8fe2: eb01 0002 add\.w r0, r1, r2 + 8fe6: f7ff bffc b\.w 8fe2 <_start\+0xe2> + 8fea: eb01 0002 add\.w r0, r1, r2 + 8fee: f7ff bff8 b\.w 8fe2 <_start\+0xe2> + 8ff2: eb01 0002 add\.w r0, r1, r2 + 8ff6: f7ff bff4 b\.w 8fe2 <_start\+0xe2> + 8ffa: eb01 0002 add\.w r0, r1, r2 + 8ffe: f000 b803 b\.w 9008 <_start\+0x108> + 9002: 4770 bx lr + 9004: f3af 8000 nop\.w + 9008: f7ff bfeb b\.w 8fe2 <_start\+0xe2> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b.s new file mode 100644 index 0000000..c0f21ac --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-b.s @@ -0,0 +1,39 @@ + .syntax unified + .cpu cortex-a8 + .thumb + .text + + @ expansion 32 bytes + .macro bw1 +1: + add.w r0, r1, r2 + b.w 1b + add.w r0, r1, r2 + b.w 1b + add.w r0, r1, r2 + b.w 1b + add.w r0, r1, r2 + b.w 1b + .endm + + @ expansion 128 bytes + .macro bw2 + bw1 + bw1 + bw1 + bw1 + .endm + + .align 3 + .global _start + .thumb + .thumb_func + .type _start, %function +_start: + nop + + @ Trigger Cortex-A8 erratum workaround with b instructions. + bw2 + bw2 + + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d new file mode 100644 index 0000000..3d064b6 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d @@ -0,0 +1,32 @@ + +.* + + +Disassembly of section \.plt: + +00008000 <\.plt>: + 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <foo-0xfe0> + 8008: e08fe00e add lr, pc, lr + 800c: e5bef008 ldr pc, \[lr, #8\]! + 8010: 00001004 \.word 0x00001004 + 8014: 4778 bx pc + 8016: 46c0 nop ; \(mov r8, r8\) + 8018: e28fc600 add ip, pc, #0 + 801c: e28cca01 add ip, ip, #4096 ; 0x1000 + 8020: e5bcf000 ldr pc, \[ip\]! + +Disassembly of section \.text: + +00008ff0 <foo>: + 8ff0: 46c0 nop ; \(mov r8, r8\) + 8ff2: f240 0000 movw r0, #0 + 8ff6: f240 0000 movw r0, #0 + 8ffa: f240 0000 movw r0, #0 + 8ffe: f000 b803 b\.w 9008 <foo\+0x18> + 9002: 0000 movs r0, r0 + 9004: 0000 movs r0, r0 + 9006: 0000 movs r0, r0 + 9008: d001 beq\.n 900e <foo\+0x1e> + 900a: f7ff bffa b\.w 9002 <foo\+0x12> + 900e: f7ff b801 b\.w 8014 <foo-0xfdc> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.s new file mode 100644 index 0000000..026fa95 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.s @@ -0,0 +1,10 @@ + .syntax unified + .globl foo + .type foo,%function + .thumb_func +foo: + nop @ 0x00 + movw r0,#0 @ 0x02 + movw r0,#0 @ 0x06 + movw r0,#0 @ 0x0a + beq.w bar(PLT) @ 0x0e diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel-thumb.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel-thumb.d new file mode 100644 index 0000000..27a7fd4 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel-thumb.d @@ -0,0 +1,82 @@ + +.*: file format .* + + +Disassembly of section \.text: + +00008f00 <targetfn>: + 8f00: 4770 bx lr + 8f02: bf00 nop + 8f04: f3af 8000 nop\.w + +00008f08 <_start>: + 8f08: bf00 nop + 8f0a: eb01 0002 add\.w r0, r1, r2 + 8f0e: f53f aff7 bmi\.w 8f00 <targetfn> + 8f12: eb01 0002 add\.w r0, r1, r2 + 8f16: f53f aff3 bmi\.w 8f00 <targetfn> + 8f1a: eb01 0002 add\.w r0, r1, r2 + 8f1e: f53f afef bmi\.w 8f00 <targetfn> + 8f22: eb01 0002 add\.w r0, r1, r2 + 8f26: f53f afeb bmi\.w 8f00 <targetfn> + 8f2a: eb01 0002 add\.w r0, r1, r2 + 8f2e: f53f afe7 bmi\.w 8f00 <targetfn> + 8f32: eb01 0002 add\.w r0, r1, r2 + 8f36: f53f afe3 bmi\.w 8f00 <targetfn> + 8f3a: eb01 0002 add\.w r0, r1, r2 + 8f3e: f53f afdf bmi\.w 8f00 <targetfn> + 8f42: eb01 0002 add\.w r0, r1, r2 + 8f46: f53f afdb bmi\.w 8f00 <targetfn> + 8f4a: eb01 0002 add\.w r0, r1, r2 + 8f4e: f53f afd7 bmi\.w 8f00 <targetfn> + 8f52: eb01 0002 add\.w r0, r1, r2 + 8f56: f53f afd3 bmi\.w 8f00 <targetfn> + 8f5a: eb01 0002 add\.w r0, r1, r2 + 8f5e: f53f afcf bmi\.w 8f00 <targetfn> + 8f62: eb01 0002 add\.w r0, r1, r2 + 8f66: f53f afcb bmi\.w 8f00 <targetfn> + 8f6a: eb01 0002 add\.w r0, r1, r2 + 8f6e: f53f afc7 bmi\.w 8f00 <targetfn> + 8f72: eb01 0002 add\.w r0, r1, r2 + 8f76: f53f afc3 bmi\.w 8f00 <targetfn> + 8f7a: eb01 0002 add\.w r0, r1, r2 + 8f7e: f53f afbf bmi\.w 8f00 <targetfn> + 8f82: eb01 0002 add\.w r0, r1, r2 + 8f86: f53f afbb bmi\.w 8f00 <targetfn> + 8f8a: eb01 0002 add\.w r0, r1, r2 + 8f8e: f53f afb7 bmi\.w 8f00 <targetfn> + 8f92: eb01 0002 add\.w r0, r1, r2 + 8f96: f53f afb3 bmi\.w 8f00 <targetfn> + 8f9a: eb01 0002 add\.w r0, r1, r2 + 8f9e: f53f afaf bmi\.w 8f00 <targetfn> + 8fa2: eb01 0002 add\.w r0, r1, r2 + 8fa6: f53f afab bmi\.w 8f00 <targetfn> + 8faa: eb01 0002 add\.w r0, r1, r2 + 8fae: f53f afa7 bmi\.w 8f00 <targetfn> + 8fb2: eb01 0002 add\.w r0, r1, r2 + 8fb6: f53f afa3 bmi\.w 8f00 <targetfn> + 8fba: eb01 0002 add\.w r0, r1, r2 + 8fbe: f53f af9f bmi\.w 8f00 <targetfn> + 8fc2: eb01 0002 add\.w r0, r1, r2 + 8fc6: f53f af9b bmi\.w 8f00 <targetfn> + 8fca: eb01 0002 add\.w r0, r1, r2 + 8fce: f53f af97 bmi\.w 8f00 <targetfn> + 8fd2: eb01 0002 add\.w r0, r1, r2 + 8fd6: f53f af93 bmi\.w 8f00 <targetfn> + 8fda: eb01 0002 add\.w r0, r1, r2 + 8fde: f53f af8f bmi\.w 8f00 <targetfn> + 8fe2: eb01 0002 add\.w r0, r1, r2 + 8fe6: f53f af8b bmi\.w 8f00 <targetfn> + 8fea: eb01 0002 add\.w r0, r1, r2 + 8fee: f53f af87 bmi\.w 8f00 <targetfn> + 8ff2: eb01 0002 add\.w r0, r1, r2 + 8ff6: f53f af83 bmi\.w 8f00 <targetfn> + 8ffa: eb01 0002 add\.w r0, r1, r2 + 8ffe: f000 b807 b\.w 9010 <_start\+0x108> + 9002: eb01 0002 add\.w r0, r1, r2 + 9006: f53f af7b bmi\.w 8f00 <targetfn> + 900a: 4770 bx lr + 900c: f3af 8000 nop\.w + 9010: d401 bmi\.n 9016 <_start\+0x10e> + 9012: f7ff bff6 b\.w 9002 <_start\+0xfa> + 9016: f7ff bf73 b\.w 8f00 <targetfn> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel.s new file mode 100644 index 0000000..b7b9451 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc-rel.s @@ -0,0 +1,38 @@ + .syntax unified + .cpu cortex-a8 + .thumb + .text + + @ expansion 32 bytes + .macro bw1 +1: + add.w r0, r1, r2 + bmi.w targetfn + add.w r0, r1, r2 + bmi.w targetfn + add.w r0, r1, r2 + bmi.w targetfn + add.w r0, r1, r2 + bmi.w targetfn + .endm + + @ expansion 128 bytes + .macro bw2 + bw1 + bw1 + bw1 + bw1 + .endm + + .align 3 + .global _start + .thumb + .thumb_func + .type _start, %function +_start: + nop + + bw2 + bw2 + + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc.d new file mode 100644 index 0000000..44b8110 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc.d @@ -0,0 +1,77 @@ + +.*: file format .* + + +Disassembly of section \.text: + +00008f00 <_start>: + 8f00: bf00 nop + 8f02: eb01 0002 add\.w r0, r1, r2 + 8f06: f4ff affc bcc\.w 8f02 <_start\+0x2> + 8f0a: eb01 0002 add\.w r0, r1, r2 + 8f0e: f4ff aff8 bcc\.w 8f02 <_start\+0x2> + 8f12: eb01 0002 add\.w r0, r1, r2 + 8f16: f4ff aff4 bcc\.w 8f02 <_start\+0x2> + 8f1a: eb01 0002 add\.w r0, r1, r2 + 8f1e: f4ff aff0 bcc\.w 8f02 <_start\+0x2> + 8f22: eb01 0002 add\.w r0, r1, r2 + 8f26: f4ff affc bcc\.w 8f22 <_start\+0x22> + 8f2a: eb01 0002 add\.w r0, r1, r2 + 8f2e: f4ff aff8 bcc\.w 8f22 <_start\+0x22> + 8f32: eb01 0002 add\.w r0, r1, r2 + 8f36: f4ff aff4 bcc\.w 8f22 <_start\+0x22> + 8f3a: eb01 0002 add\.w r0, r1, r2 + 8f3e: f4ff aff0 bcc\.w 8f22 <_start\+0x22> + 8f42: eb01 0002 add\.w r0, r1, r2 + 8f46: f4ff affc bcc\.w 8f42 <_start\+0x42> + 8f4a: eb01 0002 add\.w r0, r1, r2 + 8f4e: f4ff aff8 bcc\.w 8f42 <_start\+0x42> + 8f52: eb01 0002 add\.w r0, r1, r2 + 8f56: f4ff aff4 bcc\.w 8f42 <_start\+0x42> + 8f5a: eb01 0002 add\.w r0, r1, r2 + 8f5e: f4ff aff0 bcc\.w 8f42 <_start\+0x42> + 8f62: eb01 0002 add\.w r0, r1, r2 + 8f66: f4ff affc bcc\.w 8f62 <_start\+0x62> + 8f6a: eb01 0002 add\.w r0, r1, r2 + 8f6e: f4ff aff8 bcc\.w 8f62 <_start\+0x62> + 8f72: eb01 0002 add\.w r0, r1, r2 + 8f76: f4ff aff4 bcc\.w 8f62 <_start\+0x62> + 8f7a: eb01 0002 add\.w r0, r1, r2 + 8f7e: f4ff aff0 bcc\.w 8f62 <_start\+0x62> + 8f82: eb01 0002 add\.w r0, r1, r2 + 8f86: f4ff affc bcc\.w 8f82 <_start\+0x82> + 8f8a: eb01 0002 add\.w r0, r1, r2 + 8f8e: f4ff aff8 bcc\.w 8f82 <_start\+0x82> + 8f92: eb01 0002 add\.w r0, r1, r2 + 8f96: f4ff aff4 bcc\.w 8f82 <_start\+0x82> + 8f9a: eb01 0002 add\.w r0, r1, r2 + 8f9e: f4ff aff0 bcc\.w 8f82 <_start\+0x82> + 8fa2: eb01 0002 add\.w r0, r1, r2 + 8fa6: f4ff affc bcc\.w 8fa2 <_start\+0xa2> + 8faa: eb01 0002 add\.w r0, r1, r2 + 8fae: f4ff aff8 bcc\.w 8fa2 <_start\+0xa2> + 8fb2: eb01 0002 add\.w r0, r1, r2 + 8fb6: f4ff aff4 bcc\.w 8fa2 <_start\+0xa2> + 8fba: eb01 0002 add\.w r0, r1, r2 + 8fbe: f4ff aff0 bcc\.w 8fa2 <_start\+0xa2> + 8fc2: eb01 0002 add\.w r0, r1, r2 + 8fc6: f4ff affc bcc\.w 8fc2 <_start\+0xc2> + 8fca: eb01 0002 add\.w r0, r1, r2 + 8fce: f4ff aff8 bcc\.w 8fc2 <_start\+0xc2> + 8fd2: eb01 0002 add\.w r0, r1, r2 + 8fd6: f4ff aff4 bcc\.w 8fc2 <_start\+0xc2> + 8fda: eb01 0002 add\.w r0, r1, r2 + 8fde: f4ff aff0 bcc\.w 8fc2 <_start\+0xc2> + 8fe2: eb01 0002 add\.w r0, r1, r2 + 8fe6: f4ff affc bcc\.w 8fe2 <_start\+0xe2> + 8fea: eb01 0002 add\.w r0, r1, r2 + 8fee: f4ff aff8 bcc\.w 8fe2 <_start\+0xe2> + 8ff2: eb01 0002 add\.w r0, r1, r2 + 8ff6: f4ff aff4 bcc\.w 8fe2 <_start\+0xe2> + 8ffa: eb01 0002 add\.w r0, r1, r2 + 8ffe: f000 b803 b\.w 9008 <_start\+0x108> + 9002: 4770 bx lr + 9004: f3af 8000 nop\.w + 9008: d301 bcc\.n 900e <_start\+0x10e> + 900a: f7ff bffa b\.w 9002 <_start\+0x102> + 900e: f7ff bfe8 b\.w 8fe2 <_start\+0xe2> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc.s new file mode 100644 index 0000000..8a667a3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bcc.s @@ -0,0 +1,39 @@ + .syntax unified + .cpu cortex-a8 + .thumb + .text + + @ expansion 32 bytes + .macro bw1 +1: + add.w r0, r1, r2 + bcc.w 1b + add.w r0, r1, r2 + bcc.w 1b + add.w r0, r1, r2 + bcc.w 1b + add.w r0, r1, r2 + bcc.w 1b + .endm + + @ expansion 128 bytes + .macro bw2 + bw1 + bw1 + bw1 + bw1 + .endm + + .align 3 + .global _start + .thumb + .thumb_func + .type _start, %function +_start: + nop + + @ Trigger Cortex-A8 erratum workaround with conditional branches. + bw2 + bw2 + + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d new file mode 100644 index 0000000..17cb9ac --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d @@ -0,0 +1,28 @@ + +.* + + +Disassembly of section \.plt: + +00008000 <\.plt>: + 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <foo-0xfe0> + 8008: e08fe00e add lr, pc, lr + 800c: e5bef008 ldr pc, \[lr, #8\]! + 8010: 00000ffc \.word 0x00000ffc + 8014: e28fc600 add ip, pc, #0 + 8018: e28cca00 add ip, ip, #0 + 801c: e5bcfffc ldr pc, \[ip, #4092\]! ; 0xffc + +Disassembly of section \.text: + +00008ff0 <foo>: + 8ff0: 46c0 nop ; \(mov r8, r8\) + 8ff2: f240 0000 movw r0, #0 + 8ff6: f240 0000 movw r0, #0 + 8ffa: f240 0000 movw r0, #0 + 8ffe: f000 e804 blx 9008 <foo\+0x18> + 9002: 0000 movs r0, r0 + 9004: 0000 movs r0, r0 + 9006: 0000 movs r0, r0 + 9008: eafffc01 b 8014 <foo-0xfdc> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.s new file mode 100644 index 0000000..7f2db05 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.s @@ -0,0 +1,10 @@ + .syntax unified + .globl foo + .type foo,%function + .thumb_func +foo: + nop @ 0x00 + movw r0,#0 @ 0x02 + movw r0,#0 @ 0x06 + movw r0,#0 @ 0x0a + bl bar(PLT) @ 0x0e diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-arm.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-arm.d new file mode 100644 index 0000000..fcb3bab --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-arm.d @@ -0,0 +1,79 @@ + +.*: file format .* + + +Disassembly of section \.text: + +00008f00 <targetfn>: + 8f00: e12fff1e bx lr + 8f04: e320f000 nop \{0\} + +00008f08 <_start>: + 8f08: bf00 nop + 8f0a: eb01 0002 add\.w r0, r1, r2 + 8f0e: f7ff eff8 blx 8f00 <targetfn> + 8f12: eb01 0002 add\.w r0, r1, r2 + 8f16: f7ff eff4 blx 8f00 <targetfn> + 8f1a: eb01 0002 add\.w r0, r1, r2 + 8f1e: f7ff eff0 blx 8f00 <targetfn> + 8f22: eb01 0002 add\.w r0, r1, r2 + 8f26: f7ff efec blx 8f00 <targetfn> + 8f2a: eb01 0002 add\.w r0, r1, r2 + 8f2e: f7ff efe8 blx 8f00 <targetfn> + 8f32: eb01 0002 add\.w r0, r1, r2 + 8f36: f7ff efe4 blx 8f00 <targetfn> + 8f3a: eb01 0002 add\.w r0, r1, r2 + 8f3e: f7ff efe0 blx 8f00 <targetfn> + 8f42: eb01 0002 add\.w r0, r1, r2 + 8f46: f7ff efdc blx 8f00 <targetfn> + 8f4a: eb01 0002 add\.w r0, r1, r2 + 8f4e: f7ff efd8 blx 8f00 <targetfn> + 8f52: eb01 0002 add\.w r0, r1, r2 + 8f56: f7ff efd4 blx 8f00 <targetfn> + 8f5a: eb01 0002 add\.w r0, r1, r2 + 8f5e: f7ff efd0 blx 8f00 <targetfn> + 8f62: eb01 0002 add\.w r0, r1, r2 + 8f66: f7ff efcc blx 8f00 <targetfn> + 8f6a: eb01 0002 add\.w r0, r1, r2 + 8f6e: f7ff efc8 blx 8f00 <targetfn> + 8f72: eb01 0002 add\.w r0, r1, r2 + 8f76: f7ff efc4 blx 8f00 <targetfn> + 8f7a: eb01 0002 add\.w r0, r1, r2 + 8f7e: f7ff efc0 blx 8f00 <targetfn> + 8f82: eb01 0002 add\.w r0, r1, r2 + 8f86: f7ff efbc blx 8f00 <targetfn> + 8f8a: eb01 0002 add\.w r0, r1, r2 + 8f8e: f7ff efb8 blx 8f00 <targetfn> + 8f92: eb01 0002 add\.w r0, r1, r2 + 8f96: f7ff efb4 blx 8f00 <targetfn> + 8f9a: eb01 0002 add\.w r0, r1, r2 + 8f9e: f7ff efb0 blx 8f00 <targetfn> + 8fa2: eb01 0002 add\.w r0, r1, r2 + 8fa6: f7ff efac blx 8f00 <targetfn> + 8faa: eb01 0002 add\.w r0, r1, r2 + 8fae: f7ff efa8 blx 8f00 <targetfn> + 8fb2: eb01 0002 add\.w r0, r1, r2 + 8fb6: f7ff efa4 blx 8f00 <targetfn> + 8fba: eb01 0002 add\.w r0, r1, r2 + 8fbe: f7ff efa0 blx 8f00 <targetfn> + 8fc2: eb01 0002 add\.w r0, r1, r2 + 8fc6: f7ff ef9c blx 8f00 <targetfn> + 8fca: eb01 0002 add\.w r0, r1, r2 + 8fce: f7ff ef98 blx 8f00 <targetfn> + 8fd2: eb01 0002 add\.w r0, r1, r2 + 8fd6: f7ff ef94 blx 8f00 <targetfn> + 8fda: eb01 0002 add\.w r0, r1, r2 + 8fde: f7ff ef90 blx 8f00 <targetfn> + 8fe2: eb01 0002 add\.w r0, r1, r2 + 8fe6: f7ff ef8c blx 8f00 <targetfn> + 8fea: eb01 0002 add\.w r0, r1, r2 + 8fee: f7ff ef88 blx 8f00 <targetfn> + 8ff2: eb01 0002 add\.w r0, r1, r2 + 8ff6: f7ff ef84 blx 8f00 <targetfn> + 8ffa: eb01 0002 add\.w r0, r1, r2 + 8ffe: f000 e808 blx 9010 <_start\+0x108> + 9002: eb01 0002 add\.w r0, r1, r2 + 9006: f7ff ef7c blx 8f00 <targetfn> + 900a: 4770 bx lr + 900c: f3af 8000 nop\.w + 9010: eaffffba b 8f00 <targetfn> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d new file mode 100644 index 0000000..e885a17 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d @@ -0,0 +1,92 @@ + +.*: file format .* + + +Disassembly of section \.plt: + +00008e00 <\.plt>: + 8e00: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + 8e04: e59fe004 ldr lr, \[pc, #4\] ; 8e10 <targetfn-0xf0> + 8e08: e08fe00e add lr, pc, lr + 8e0c: e5bef008 ldr pc, \[lr, #8\]! + 8e10: 0000827c \.word 0x0000827c + 8e14: e28fc600 add ip, pc, #0 + 8e18: e28cca08 add ip, ip, #32768 ; 0x8000 + 8e1c: e5bcf27c ldr pc, \[ip, #636\]! ; 0x27c + +Disassembly of section \.text: + +00008f00 <targetfn>: + 8f00: 4770 bx lr + 8f02: bf00 nop + 8f04: f3af 8000 nop\.w + +00008f08 <_start>: + 8f08: bf00 nop + 8f0a: eb01 0002 add\.w r0, r1, r2 + 8f0e: f7ff ef82 blx 8e14 <targetfn-0xec> + 8f12: eb01 0002 add\.w r0, r1, r2 + 8f16: f7ff ef7e blx 8e14 <targetfn-0xec> + 8f1a: eb01 0002 add\.w r0, r1, r2 + 8f1e: f7ff ef7a blx 8e14 <targetfn-0xec> + 8f22: eb01 0002 add\.w r0, r1, r2 + 8f26: f7ff ef76 blx 8e14 <targetfn-0xec> + 8f2a: eb01 0002 add\.w r0, r1, r2 + 8f2e: f7ff ef72 blx 8e14 <targetfn-0xec> + 8f32: eb01 0002 add\.w r0, r1, r2 + 8f36: f7ff ef6e blx 8e14 <targetfn-0xec> + 8f3a: eb01 0002 add\.w r0, r1, r2 + 8f3e: f7ff ef6a blx 8e14 <targetfn-0xec> + 8f42: eb01 0002 add\.w r0, r1, r2 + 8f46: f7ff ef66 blx 8e14 <targetfn-0xec> + 8f4a: eb01 0002 add\.w r0, r1, r2 + 8f4e: f7ff ef62 blx 8e14 <targetfn-0xec> + 8f52: eb01 0002 add\.w r0, r1, r2 + 8f56: f7ff ef5e blx 8e14 <targetfn-0xec> + 8f5a: eb01 0002 add\.w r0, r1, r2 + 8f5e: f7ff ef5a blx 8e14 <targetfn-0xec> + 8f62: eb01 0002 add\.w r0, r1, r2 + 8f66: f7ff ef56 blx 8e14 <targetfn-0xec> + 8f6a: eb01 0002 add\.w r0, r1, r2 + 8f6e: f7ff ef52 blx 8e14 <targetfn-0xec> + 8f72: eb01 0002 add\.w r0, r1, r2 + 8f76: f7ff ef4e blx 8e14 <targetfn-0xec> + 8f7a: eb01 0002 add\.w r0, r1, r2 + 8f7e: f7ff ef4a blx 8e14 <targetfn-0xec> + 8f82: eb01 0002 add\.w r0, r1, r2 + 8f86: f7ff ef46 blx 8e14 <targetfn-0xec> + 8f8a: eb01 0002 add\.w r0, r1, r2 + 8f8e: f7ff ef42 blx 8e14 <targetfn-0xec> + 8f92: eb01 0002 add\.w r0, r1, r2 + 8f96: f7ff ef3e blx 8e14 <targetfn-0xec> + 8f9a: eb01 0002 add\.w r0, r1, r2 + 8f9e: f7ff ef3a blx 8e14 <targetfn-0xec> + 8fa2: eb01 0002 add\.w r0, r1, r2 + 8fa6: f7ff ef36 blx 8e14 <targetfn-0xec> + 8faa: eb01 0002 add\.w r0, r1, r2 + 8fae: f7ff ef32 blx 8e14 <targetfn-0xec> + 8fb2: eb01 0002 add\.w r0, r1, r2 + 8fb6: f7ff ef2e blx 8e14 <targetfn-0xec> + 8fba: eb01 0002 add\.w r0, r1, r2 + 8fbe: f7ff ef2a blx 8e14 <targetfn-0xec> + 8fc2: eb01 0002 add\.w r0, r1, r2 + 8fc6: f7ff ef26 blx 8e14 <targetfn-0xec> + 8fca: eb01 0002 add\.w r0, r1, r2 + 8fce: f7ff ef22 blx 8e14 <targetfn-0xec> + 8fd2: eb01 0002 add\.w r0, r1, r2 + 8fd6: f7ff ef1e blx 8e14 <targetfn-0xec> + 8fda: eb01 0002 add\.w r0, r1, r2 + 8fde: f7ff ef1a blx 8e14 <targetfn-0xec> + 8fe2: eb01 0002 add\.w r0, r1, r2 + 8fe6: f7ff ef16 blx 8e14 <targetfn-0xec> + 8fea: eb01 0002 add\.w r0, r1, r2 + 8fee: f7ff ef12 blx 8e14 <targetfn-0xec> + 8ff2: eb01 0002 add\.w r0, r1, r2 + 8ff6: f7ff ef0e blx 8e14 <targetfn-0xec> + 8ffa: eb01 0002 add\.w r0, r1, r2 + 8ffe: f000 e808 blx 9010 <_start\+0x108> + 9002: eb01 0002 add\.w r0, r1, r2 + 9006: f7ff ef06 blx 8e14 <targetfn-0xec> + 900a: 4770 bx lr + 900c: f3af 8000 nop\.w + 9010: eaffff7f b 8e14 <targetfn-0xec> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-thumb.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-thumb.d new file mode 100644 index 0000000..8cbd3e0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-thumb.d @@ -0,0 +1,80 @@ + +.*: file format .* + + +Disassembly of section \.text: + +00008f00 <targetfn>: + 8f00: 4770 bx lr + 8f02: bf00 nop + 8f04: f3af 8000 nop\.w + +00008f08 <_start>: + 8f08: bf00 nop + 8f0a: eb01 0002 add\.w r0, r1, r2 + 8f0e: f7ff fff7 bl 8f00 <targetfn> + 8f12: eb01 0002 add\.w r0, r1, r2 + 8f16: f7ff fff3 bl 8f00 <targetfn> + 8f1a: eb01 0002 add\.w r0, r1, r2 + 8f1e: f7ff ffef bl 8f00 <targetfn> + 8f22: eb01 0002 add\.w r0, r1, r2 + 8f26: f7ff ffeb bl 8f00 <targetfn> + 8f2a: eb01 0002 add\.w r0, r1, r2 + 8f2e: f7ff ffe7 bl 8f00 <targetfn> + 8f32: eb01 0002 add\.w r0, r1, r2 + 8f36: f7ff ffe3 bl 8f00 <targetfn> + 8f3a: eb01 0002 add\.w r0, r1, r2 + 8f3e: f7ff ffdf bl 8f00 <targetfn> + 8f42: eb01 0002 add\.w r0, r1, r2 + 8f46: f7ff ffdb bl 8f00 <targetfn> + 8f4a: eb01 0002 add\.w r0, r1, r2 + 8f4e: f7ff ffd7 bl 8f00 <targetfn> + 8f52: eb01 0002 add\.w r0, r1, r2 + 8f56: f7ff ffd3 bl 8f00 <targetfn> + 8f5a: eb01 0002 add\.w r0, r1, r2 + 8f5e: f7ff ffcf bl 8f00 <targetfn> + 8f62: eb01 0002 add\.w r0, r1, r2 + 8f66: f7ff ffcb bl 8f00 <targetfn> + 8f6a: eb01 0002 add\.w r0, r1, r2 + 8f6e: f7ff ffc7 bl 8f00 <targetfn> + 8f72: eb01 0002 add\.w r0, r1, r2 + 8f76: f7ff ffc3 bl 8f00 <targetfn> + 8f7a: eb01 0002 add\.w r0, r1, r2 + 8f7e: f7ff ffbf bl 8f00 <targetfn> + 8f82: eb01 0002 add\.w r0, r1, r2 + 8f86: f7ff ffbb bl 8f00 <targetfn> + 8f8a: eb01 0002 add\.w r0, r1, r2 + 8f8e: f7ff ffb7 bl 8f00 <targetfn> + 8f92: eb01 0002 add\.w r0, r1, r2 + 8f96: f7ff ffb3 bl 8f00 <targetfn> + 8f9a: eb01 0002 add\.w r0, r1, r2 + 8f9e: f7ff ffaf bl 8f00 <targetfn> + 8fa2: eb01 0002 add\.w r0, r1, r2 + 8fa6: f7ff ffab bl 8f00 <targetfn> + 8faa: eb01 0002 add\.w r0, r1, r2 + 8fae: f7ff ffa7 bl 8f00 <targetfn> + 8fb2: eb01 0002 add\.w r0, r1, r2 + 8fb6: f7ff ffa3 bl 8f00 <targetfn> + 8fba: eb01 0002 add\.w r0, r1, r2 + 8fbe: f7ff ff9f bl 8f00 <targetfn> + 8fc2: eb01 0002 add\.w r0, r1, r2 + 8fc6: f7ff ff9b bl 8f00 <targetfn> + 8fca: eb01 0002 add\.w r0, r1, r2 + 8fce: f7ff ff97 bl 8f00 <targetfn> + 8fd2: eb01 0002 add\.w r0, r1, r2 + 8fd6: f7ff ff93 bl 8f00 <targetfn> + 8fda: eb01 0002 add\.w r0, r1, r2 + 8fde: f7ff ff8f bl 8f00 <targetfn> + 8fe2: eb01 0002 add\.w r0, r1, r2 + 8fe6: f7ff ff8b bl 8f00 <targetfn> + 8fea: eb01 0002 add\.w r0, r1, r2 + 8fee: f7ff ff87 bl 8f00 <targetfn> + 8ff2: eb01 0002 add\.w r0, r1, r2 + 8ff6: f7ff ff83 bl 8f00 <targetfn> + 8ffa: eb01 0002 add\.w r0, r1, r2 + 8ffe: f000 f807 bl 9010 <_start\+0x108> + 9002: eb01 0002 add\.w r0, r1, r2 + 9006: f7ff ff7b bl 8f00 <targetfn> + 900a: 4770 bx lr + 900c: f3af 8000 nop\.w + 9010: f7ff bf76 b\.w 8f00 <targetfn> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel.s new file mode 100644 index 0000000..2d21bbf --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel.s @@ -0,0 +1,40 @@ + .syntax unified + .cpu cortex-a8 + .thumb + .text + + @ expansion 32 bytes + .macro bw1 +1: + add.w r0, r1, r2 + bl.w targetfn + add.w r0, r1, r2 + bl.w targetfn + add.w r0, r1, r2 + bl.w targetfn + add.w r0, r1, r2 + bl.w targetfn + .endm + + @ expansion 128 bytes + .macro bw2 + bw1 + bw1 + bw1 + bw1 + .endm + + .align 3 + .global _start + .thumb + .thumb_func + .type _start, %function +_start: + nop + + @ If calling an ARM destination, we *don't* want to create a + @ Cortex-A8 stub: the Thumb-to-ARM stub will suffice. + bw2 + bw2 + + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl.d new file mode 100644 index 0000000..50dcd4f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl.d @@ -0,0 +1,75 @@ + +.*: file format .* + + +Disassembly of section \.text: + +00008f00 <_start>: + 8f00: bf00 nop + 8f02: eb01 0002 add\.w r0, r1, r2 + 8f06: f7ff fffc bl 8f02 <_start\+0x2> + 8f0a: eb01 0002 add\.w r0, r1, r2 + 8f0e: f7ff fff8 bl 8f02 <_start\+0x2> + 8f12: eb01 0002 add\.w r0, r1, r2 + 8f16: f7ff fff4 bl 8f02 <_start\+0x2> + 8f1a: eb01 0002 add\.w r0, r1, r2 + 8f1e: f7ff fff0 bl 8f02 <_start\+0x2> + 8f22: eb01 0002 add\.w r0, r1, r2 + 8f26: f7ff fffc bl 8f22 <_start\+0x22> + 8f2a: eb01 0002 add\.w r0, r1, r2 + 8f2e: f7ff fff8 bl 8f22 <_start\+0x22> + 8f32: eb01 0002 add\.w r0, r1, r2 + 8f36: f7ff fff4 bl 8f22 <_start\+0x22> + 8f3a: eb01 0002 add\.w r0, r1, r2 + 8f3e: f7ff fff0 bl 8f22 <_start\+0x22> + 8f42: eb01 0002 add\.w r0, r1, r2 + 8f46: f7ff fffc bl 8f42 <_start\+0x42> + 8f4a: eb01 0002 add\.w r0, r1, r2 + 8f4e: f7ff fff8 bl 8f42 <_start\+0x42> + 8f52: eb01 0002 add\.w r0, r1, r2 + 8f56: f7ff fff4 bl 8f42 <_start\+0x42> + 8f5a: eb01 0002 add\.w r0, r1, r2 + 8f5e: f7ff fff0 bl 8f42 <_start\+0x42> + 8f62: eb01 0002 add\.w r0, r1, r2 + 8f66: f7ff fffc bl 8f62 <_start\+0x62> + 8f6a: eb01 0002 add\.w r0, r1, r2 + 8f6e: f7ff fff8 bl 8f62 <_start\+0x62> + 8f72: eb01 0002 add\.w r0, r1, r2 + 8f76: f7ff fff4 bl 8f62 <_start\+0x62> + 8f7a: eb01 0002 add\.w r0, r1, r2 + 8f7e: f7ff fff0 bl 8f62 <_start\+0x62> + 8f82: eb01 0002 add\.w r0, r1, r2 + 8f86: f7ff fffc bl 8f82 <_start\+0x82> + 8f8a: eb01 0002 add\.w r0, r1, r2 + 8f8e: f7ff fff8 bl 8f82 <_start\+0x82> + 8f92: eb01 0002 add\.w r0, r1, r2 + 8f96: f7ff fff4 bl 8f82 <_start\+0x82> + 8f9a: eb01 0002 add\.w r0, r1, r2 + 8f9e: f7ff fff0 bl 8f82 <_start\+0x82> + 8fa2: eb01 0002 add\.w r0, r1, r2 + 8fa6: f7ff fffc bl 8fa2 <_start\+0xa2> + 8faa: eb01 0002 add\.w r0, r1, r2 + 8fae: f7ff fff8 bl 8fa2 <_start\+0xa2> + 8fb2: eb01 0002 add\.w r0, r1, r2 + 8fb6: f7ff fff4 bl 8fa2 <_start\+0xa2> + 8fba: eb01 0002 add\.w r0, r1, r2 + 8fbe: f7ff fff0 bl 8fa2 <_start\+0xa2> + 8fc2: eb01 0002 add\.w r0, r1, r2 + 8fc6: f7ff fffc bl 8fc2 <_start\+0xc2> + 8fca: eb01 0002 add\.w r0, r1, r2 + 8fce: f7ff fff8 bl 8fc2 <_start\+0xc2> + 8fd2: eb01 0002 add\.w r0, r1, r2 + 8fd6: f7ff fff4 bl 8fc2 <_start\+0xc2> + 8fda: eb01 0002 add\.w r0, r1, r2 + 8fde: f7ff fff0 bl 8fc2 <_start\+0xc2> + 8fe2: eb01 0002 add\.w r0, r1, r2 + 8fe6: f7ff fffc bl 8fe2 <_start\+0xe2> + 8fea: eb01 0002 add\.w r0, r1, r2 + 8fee: f7ff fff8 bl 8fe2 <_start\+0xe2> + 8ff2: eb01 0002 add\.w r0, r1, r2 + 8ff6: f7ff fff4 bl 8fe2 <_start\+0xe2> + 8ffa: eb01 0002 add\.w r0, r1, r2 + 8ffe: f000 f803 bl 9008 <_start\+0x108> + 9002: 4770 bx lr + 9004: f3af 8000 nop\.w + 9008: f7ff bfeb b\.w 8fe2 <_start\+0xe2> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl.s new file mode 100644 index 0000000..6e40fb8 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-bl.s @@ -0,0 +1,39 @@ + .syntax unified + .cpu cortex-a8 + .thumb + .text + + @ expansion 32 bytes + .macro bw1 +1: + add.w r0, r1, r2 + bl.w 1b + add.w r0, r1, r2 + bl.w 1b + add.w r0, r1, r2 + bl.w 1b + add.w r0, r1, r2 + bl.w 1b + .endm + + @ expansion 128 bytes + .macro bw2 + bw1 + bw1 + bw1 + bw1 + .endm + + .align 3 + .global _start + .thumb + .thumb_func + .type _start, %function +_start: + nop + + @ Trigger Cortex-A8 erratum workaround with bl instructions. + bw2 + bw2 + + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.d new file mode 100644 index 0000000..692a606 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.d @@ -0,0 +1,1107 @@ + +.*: file format .* + + +Disassembly of section \.text: + +00008f00 <_start>: + 8f00: bf00 nop + 8f02: eb01 0002 add\.w r0, r1, r2 + 8f06: f47f affc bne\.w 8f02 <_start\+0x2> + 8f0a: eb01 0002 add\.w r0, r1, r2 + 8f0e: f47f aff8 bne\.w 8f02 <_start\+0x2> + 8f12: eb01 0002 add\.w r0, r1, r2 + 8f16: f47f aff4 bne\.w 8f02 <_start\+0x2> + 8f1a: eb01 0002 add\.w r0, r1, r2 + 8f1e: f47f aff0 bne\.w 8f02 <_start\+0x2> + 8f22: eb01 0002 add\.w r0, r1, r2 + 8f26: f47f affc bne\.w 8f22 <_start\+0x22> + 8f2a: eb01 0002 add\.w r0, r1, r2 + 8f2e: f47f aff8 bne\.w 8f22 <_start\+0x22> + 8f32: eb01 0002 add\.w r0, r1, r2 + 8f36: f47f aff4 bne\.w 8f22 <_start\+0x22> + 8f3a: eb01 0002 add\.w r0, r1, r2 + 8f3e: f47f aff0 bne\.w 8f22 <_start\+0x22> + 8f42: eb01 0002 add\.w r0, r1, r2 + 8f46: f47f affc bne\.w 8f42 <_start\+0x42> + 8f4a: eb01 0002 add\.w r0, r1, r2 + 8f4e: f47f aff8 bne\.w 8f42 <_start\+0x42> + 8f52: eb01 0002 add\.w r0, r1, r2 + 8f56: f47f aff4 bne\.w 8f42 <_start\+0x42> + 8f5a: eb01 0002 add\.w r0, r1, r2 + 8f5e: f47f aff0 bne\.w 8f42 <_start\+0x42> + 8f62: eb01 0002 add\.w r0, r1, r2 + 8f66: f47f affc bne\.w 8f62 <_start\+0x62> + 8f6a: eb01 0002 add\.w r0, r1, r2 + 8f6e: f47f aff8 bne\.w 8f62 <_start\+0x62> + 8f72: eb01 0002 add\.w r0, r1, r2 + 8f76: f47f aff4 bne\.w 8f62 <_start\+0x62> + 8f7a: eb01 0002 add\.w r0, r1, r2 + 8f7e: f47f aff0 bne\.w 8f62 <_start\+0x62> + 8f82: eb01 0002 add\.w r0, r1, r2 + 8f86: f47f affc bne\.w 8f82 <_start\+0x82> + 8f8a: eb01 0002 add\.w r0, r1, r2 + 8f8e: f47f aff8 bne\.w 8f82 <_start\+0x82> + 8f92: eb01 0002 add\.w r0, r1, r2 + 8f96: f47f aff4 bne\.w 8f82 <_start\+0x82> + 8f9a: eb01 0002 add\.w r0, r1, r2 + 8f9e: f47f aff0 bne\.w 8f82 <_start\+0x82> + 8fa2: eb01 0002 add\.w r0, r1, r2 + 8fa6: f47f affc bne\.w 8fa2 <_start\+0xa2> + 8faa: eb01 0002 add\.w r0, r1, r2 + 8fae: f47f aff8 bne\.w 8fa2 <_start\+0xa2> + 8fb2: eb01 0002 add\.w r0, r1, r2 + 8fb6: f47f aff4 bne\.w 8fa2 <_start\+0xa2> + 8fba: eb01 0002 add\.w r0, r1, r2 + 8fbe: f47f aff0 bne\.w 8fa2 <_start\+0xa2> + 8fc2: eb01 0002 add\.w r0, r1, r2 + 8fc6: f47f affc bne\.w 8fc2 <_start\+0xc2> + 8fca: eb01 0002 add\.w r0, r1, r2 + 8fce: f47f aff8 bne\.w 8fc2 <_start\+0xc2> + 8fd2: eb01 0002 add\.w r0, r1, r2 + 8fd6: f47f aff4 bne\.w 8fc2 <_start\+0xc2> + 8fda: eb01 0002 add\.w r0, r1, r2 + 8fde: f47f aff0 bne\.w 8fc2 <_start\+0xc2> + 8fe2: eb01 0002 add\.w r0, r1, r2 + 8fe6: f47f affc bne\.w 8fe2 <_start\+0xe2> + 8fea: eb01 0002 add\.w r0, r1, r2 + 8fee: f47f aff8 bne\.w 8fe2 <_start\+0xe2> + 8ff2: eb01 0002 add\.w r0, r1, r2 + 8ff6: f47f aff4 bne\.w 8fe2 <_start\+0xe2> + 8ffa: eb01 0002 add\.w r0, r1, r2 + 8ffe: f001 b805 b\.w a00c <bl_insns\+0x10c> + 9002: bf00 nop + 9004: f3af 8000 nop\.w + 9008: f3af 8000 nop\.w + 900c: f3af 8000 nop\.w + 9010: f3af 8000 nop\.w + 9014: f3af 8000 nop\.w + 9018: f3af 8000 nop\.w + 901c: f3af 8000 nop\.w + 9020: f3af 8000 nop\.w + 9024: f3af 8000 nop\.w + 9028: f3af 8000 nop\.w + 902c: f3af 8000 nop\.w + 9030: f3af 8000 nop\.w + 9034: f3af 8000 nop\.w + 9038: f3af 8000 nop\.w + 903c: f3af 8000 nop\.w + 9040: f3af 8000 nop\.w + 9044: f3af 8000 nop\.w + 9048: f3af 8000 nop\.w + 904c: f3af 8000 nop\.w + 9050: f3af 8000 nop\.w + 9054: f3af 8000 nop\.w + 9058: f3af 8000 nop\.w + 905c: f3af 8000 nop\.w + 9060: f3af 8000 nop\.w + 9064: f3af 8000 nop\.w + 9068: f3af 8000 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nop\.w + 9ecc: f3af 8000 nop\.w + 9ed0: f3af 8000 nop\.w + 9ed4: f3af 8000 nop\.w + 9ed8: f3af 8000 nop\.w + 9edc: f3af 8000 nop\.w + 9ee0: f3af 8000 nop\.w + 9ee4: f3af 8000 nop\.w + 9ee8: f3af 8000 nop\.w + 9eec: f3af 8000 nop\.w + 9ef0: f3af 8000 nop\.w + 9ef4: f3af 8000 nop\.w + +00009ef8 <arm_target>: + 9ef8: e0843005 add r3, r4, r5 + 9efc: e12fff1e bx lr + +00009f00 <bl_insns>: + 9f00: bf00 nop + 9f02: eb01 0002 add\.w r0, r1, r2 + 9f06: f7ff eff8 blx 9ef8 <arm_target> + 9f0a: eb01 0002 add\.w r0, r1, r2 + 9f0e: f7ff eff4 blx 9ef8 <arm_target> + 9f12: eb01 0002 add\.w r0, r1, r2 + 9f16: f7ff eff0 blx 9ef8 <arm_target> + 9f1a: eb01 0002 add\.w r0, r1, r2 + 9f1e: f7ff efec blx 9ef8 <arm_target> + 9f22: eb01 0002 add\.w r0, r1, r2 + 9f26: f7ff efe8 blx 9ef8 <arm_target> + 9f2a: eb01 0002 add\.w r0, r1, r2 + 9f2e: f7ff efe4 blx 9ef8 <arm_target> + 9f32: eb01 0002 add\.w r0, r1, r2 + 9f36: f7ff efe0 blx 9ef8 <arm_target> + 9f3a: eb01 0002 add\.w r0, r1, r2 + 9f3e: f7ff efdc blx 9ef8 <arm_target> + 9f42: eb01 0002 add\.w r0, r1, r2 + 9f46: f7ff efd8 blx 9ef8 <arm_target> + 9f4a: eb01 0002 add\.w r0, r1, r2 + 9f4e: f7ff efd4 blx 9ef8 <arm_target> + 9f52: eb01 0002 add\.w r0, r1, r2 + 9f56: f7ff efd0 blx 9ef8 <arm_target> + 9f5a: eb01 0002 add\.w r0, r1, r2 + 9f5e: f7ff efcc blx 9ef8 <arm_target> + 9f62: eb01 0002 add\.w r0, r1, r2 + 9f66: f7ff efc8 blx 9ef8 <arm_target> + 9f6a: eb01 0002 add\.w r0, r1, r2 + 9f6e: f7ff efc4 blx 9ef8 <arm_target> + 9f72: eb01 0002 add\.w r0, r1, r2 + 9f76: f7ff efc0 blx 9ef8 <arm_target> + 9f7a: eb01 0002 add\.w r0, r1, r2 + 9f7e: f7ff efbc blx 9ef8 <arm_target> + 9f82: eb01 0002 add\.w r0, r1, r2 + 9f86: f7ff efb8 blx 9ef8 <arm_target> + 9f8a: eb01 0002 add\.w r0, r1, r2 + 9f8e: f7ff efb4 blx 9ef8 <arm_target> + 9f92: eb01 0002 add\.w r0, r1, r2 + 9f96: f7ff efb0 blx 9ef8 <arm_target> + 9f9a: eb01 0002 add\.w r0, r1, r2 + 9f9e: f7ff efac blx 9ef8 <arm_target> + 9fa2: eb01 0002 add\.w r0, r1, r2 + 9fa6: f7ff efa8 blx 9ef8 <arm_target> + 9faa: eb01 0002 add\.w r0, r1, r2 + 9fae: f7ff efa4 blx 9ef8 <arm_target> + 9fb2: eb01 0002 add\.w r0, r1, r2 + 9fb6: f7ff efa0 blx 9ef8 <arm_target> + 9fba: eb01 0002 add\.w r0, r1, r2 + 9fbe: f7ff ef9c blx 9ef8 <arm_target> + 9fc2: eb01 0002 add\.w r0, r1, r2 + 9fc6: f7ff ef98 blx 9ef8 <arm_target> + 9fca: eb01 0002 add\.w r0, r1, r2 + 9fce: f7ff ef94 blx 9ef8 <arm_target> + 9fd2: eb01 0002 add\.w r0, r1, r2 + 9fd6: f7ff ef90 blx 9ef8 <arm_target> + 9fda: eb01 0002 add\.w r0, r1, r2 + 9fde: f7ff ef8c blx 9ef8 <arm_target> + 9fe2: eb01 0002 add\.w r0, r1, r2 + 9fe6: f7ff ef88 blx 9ef8 <arm_target> + 9fea: eb01 0002 add\.w r0, r1, r2 + 9fee: f7ff ef84 blx 9ef8 <arm_target> + 9ff2: eb01 0002 add\.w r0, r1, r2 + 9ff6: f7ff ef80 blx 9ef8 <arm_target> + 9ffa: eb01 0002 add\.w r0, r1, r2 + 9ffe: f000 e804 blx a008 <bl_insns\+0x108> + a002: 4770 bx lr + a004: f3af 8000 nop\.w + a008: eaffffba b 9ef8 <arm_target> + a00c: d101 bne\.n a012 <bl_insns\+0x112> + a00e: f7fe bff8 b\.w 9002 <_start\+0x102> + a012: f7fe bfe6 b\.w 8fe2 <_start\+0xe2> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.s new file mode 100644 index 0000000..cb40fb4 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-bcond.s @@ -0,0 +1,81 @@ + .syntax unified + .cpu cortex-a8 + .thumb + .text + + @ expansion 32 bytes + .macro bw1 +1: + add.w r0, r1, r2 + blx.w arm_target + add.w r0, r1, r2 + blx.w arm_target + add.w r0, r1, r2 + blx.w arm_target + add.w r0, r1, r2 + blx.w arm_target + .endm + + @ expansion 128 bytes + .macro bw2 + bw1 + bw1 + bw1 + bw1 + .endm + + @ expansion 32 bytes + .macro bw3 +1: + add.w r0, r1, r2 + bne.w 1b + add.w r0, r1, r2 + bne.w 1b + add.w r0, r1, r2 + bne.w 1b + add.w r0, r1, r2 + bne.w 1b + .endm + + @ expansion 128 bytes + .macro bw4 + bw3 + bw3 + bw3 + bw3 + .endm + + .align 3 + .global _start + + .thumb + .thumb_func + .type _start, %function +_start: + nop + + @ Trigger Cortex-A8 erratum workaround with b<cond> instructions. + bw4 + bw4 + + nop + + .rept 957 + nop.w + .endr + + .arm +arm_target: + add r3, r4, r5 + bx lr + + .thumb +bl_insns: + + nop + + @ ...and again with bl instructions. + bw2 + bw2 + + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d new file mode 100644 index 0000000..17cb9ac --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d @@ -0,0 +1,28 @@ + +.* + + +Disassembly of section \.plt: + +00008000 <\.plt>: + 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <foo-0xfe0> + 8008: e08fe00e add lr, pc, lr + 800c: e5bef008 ldr pc, \[lr, #8\]! + 8010: 00000ffc \.word 0x00000ffc + 8014: e28fc600 add ip, pc, #0 + 8018: e28cca00 add ip, ip, #0 + 801c: e5bcfffc ldr pc, \[ip, #4092\]! ; 0xffc + +Disassembly of section \.text: + +00008ff0 <foo>: + 8ff0: 46c0 nop ; \(mov r8, r8\) + 8ff2: f240 0000 movw r0, #0 + 8ff6: f240 0000 movw r0, #0 + 8ffa: f240 0000 movw r0, #0 + 8ffe: f000 e804 blx 9008 <foo\+0x18> + 9002: 0000 movs r0, r0 + 9004: 0000 movs r0, r0 + 9006: 0000 movs r0, r0 + 9008: eafffc01 b 8014 <foo-0xfdc> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.s new file mode 100644 index 0000000..1932034 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.s @@ -0,0 +1,10 @@ + .syntax unified + .globl foo + .type foo,%function + .thumb_func +foo: + nop @ 0x00 + movw r0,#0 @ 0x02 + movw r0,#0 @ 0x06 + movw r0,#0 @ 0x0a + blx bar @ 0x0e diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-arm.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-arm.d new file mode 100644 index 0000000..fcb3bab --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-arm.d @@ -0,0 +1,79 @@ + +.*: file format .* + + +Disassembly of section \.text: + +00008f00 <targetfn>: + 8f00: e12fff1e bx lr + 8f04: e320f000 nop \{0\} + +00008f08 <_start>: + 8f08: bf00 nop + 8f0a: eb01 0002 add\.w r0, r1, r2 + 8f0e: f7ff eff8 blx 8f00 <targetfn> + 8f12: eb01 0002 add\.w r0, r1, r2 + 8f16: f7ff eff4 blx 8f00 <targetfn> + 8f1a: eb01 0002 add\.w r0, r1, r2 + 8f1e: f7ff eff0 blx 8f00 <targetfn> + 8f22: eb01 0002 add\.w r0, r1, r2 + 8f26: f7ff efec blx 8f00 <targetfn> + 8f2a: eb01 0002 add\.w r0, r1, r2 + 8f2e: f7ff efe8 blx 8f00 <targetfn> + 8f32: eb01 0002 add\.w r0, r1, r2 + 8f36: f7ff efe4 blx 8f00 <targetfn> + 8f3a: eb01 0002 add\.w r0, r1, r2 + 8f3e: f7ff efe0 blx 8f00 <targetfn> + 8f42: eb01 0002 add\.w r0, r1, r2 + 8f46: f7ff efdc blx 8f00 <targetfn> + 8f4a: eb01 0002 add\.w r0, r1, r2 + 8f4e: f7ff efd8 blx 8f00 <targetfn> + 8f52: eb01 0002 add\.w r0, r1, r2 + 8f56: f7ff efd4 blx 8f00 <targetfn> + 8f5a: eb01 0002 add\.w r0, r1, r2 + 8f5e: f7ff efd0 blx 8f00 <targetfn> + 8f62: eb01 0002 add\.w r0, r1, r2 + 8f66: f7ff efcc blx 8f00 <targetfn> + 8f6a: eb01 0002 add\.w r0, r1, r2 + 8f6e: f7ff efc8 blx 8f00 <targetfn> + 8f72: eb01 0002 add\.w r0, r1, r2 + 8f76: f7ff efc4 blx 8f00 <targetfn> + 8f7a: eb01 0002 add\.w r0, r1, r2 + 8f7e: f7ff efc0 blx 8f00 <targetfn> + 8f82: eb01 0002 add\.w r0, r1, r2 + 8f86: f7ff efbc blx 8f00 <targetfn> + 8f8a: eb01 0002 add\.w r0, r1, r2 + 8f8e: f7ff efb8 blx 8f00 <targetfn> + 8f92: eb01 0002 add\.w r0, r1, r2 + 8f96: f7ff efb4 blx 8f00 <targetfn> + 8f9a: eb01 0002 add\.w r0, r1, r2 + 8f9e: f7ff efb0 blx 8f00 <targetfn> + 8fa2: eb01 0002 add\.w r0, r1, r2 + 8fa6: f7ff efac blx 8f00 <targetfn> + 8faa: eb01 0002 add\.w r0, r1, r2 + 8fae: f7ff efa8 blx 8f00 <targetfn> + 8fb2: eb01 0002 add\.w r0, r1, r2 + 8fb6: f7ff efa4 blx 8f00 <targetfn> + 8fba: eb01 0002 add\.w r0, r1, r2 + 8fbe: f7ff efa0 blx 8f00 <targetfn> + 8fc2: eb01 0002 add\.w r0, r1, r2 + 8fc6: f7ff ef9c blx 8f00 <targetfn> + 8fca: eb01 0002 add\.w r0, r1, r2 + 8fce: f7ff ef98 blx 8f00 <targetfn> + 8fd2: eb01 0002 add\.w r0, r1, r2 + 8fd6: f7ff ef94 blx 8f00 <targetfn> + 8fda: eb01 0002 add\.w r0, r1, r2 + 8fde: f7ff ef90 blx 8f00 <targetfn> + 8fe2: eb01 0002 add\.w r0, r1, r2 + 8fe6: f7ff ef8c blx 8f00 <targetfn> + 8fea: eb01 0002 add\.w r0, r1, r2 + 8fee: f7ff ef88 blx 8f00 <targetfn> + 8ff2: eb01 0002 add\.w r0, r1, r2 + 8ff6: f7ff ef84 blx 8f00 <targetfn> + 8ffa: eb01 0002 add\.w r0, r1, r2 + 8ffe: f000 e808 blx 9010 <_start\+0x108> + 9002: eb01 0002 add\.w r0, r1, r2 + 9006: f7ff ef7c blx 8f00 <targetfn> + 900a: 4770 bx lr + 900c: f3af 8000 nop\.w + 9010: eaffffba b 8f00 <targetfn> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-thumb.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-thumb.d new file mode 100644 index 0000000..8cbd3e0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel-thumb.d @@ -0,0 +1,80 @@ + +.*: file format .* + + +Disassembly of section \.text: + +00008f00 <targetfn>: + 8f00: 4770 bx lr + 8f02: bf00 nop + 8f04: f3af 8000 nop\.w + +00008f08 <_start>: + 8f08: bf00 nop + 8f0a: eb01 0002 add\.w r0, r1, r2 + 8f0e: f7ff fff7 bl 8f00 <targetfn> + 8f12: eb01 0002 add\.w r0, r1, r2 + 8f16: f7ff fff3 bl 8f00 <targetfn> + 8f1a: eb01 0002 add\.w r0, r1, r2 + 8f1e: f7ff ffef bl 8f00 <targetfn> + 8f22: eb01 0002 add\.w r0, r1, r2 + 8f26: f7ff ffeb bl 8f00 <targetfn> + 8f2a: eb01 0002 add\.w r0, r1, r2 + 8f2e: f7ff ffe7 bl 8f00 <targetfn> + 8f32: eb01 0002 add\.w r0, r1, r2 + 8f36: f7ff ffe3 bl 8f00 <targetfn> + 8f3a: eb01 0002 add\.w r0, r1, r2 + 8f3e: f7ff ffdf bl 8f00 <targetfn> + 8f42: eb01 0002 add\.w r0, r1, r2 + 8f46: f7ff ffdb bl 8f00 <targetfn> + 8f4a: eb01 0002 add\.w r0, r1, r2 + 8f4e: f7ff ffd7 bl 8f00 <targetfn> + 8f52: eb01 0002 add\.w r0, r1, r2 + 8f56: f7ff ffd3 bl 8f00 <targetfn> + 8f5a: eb01 0002 add\.w r0, r1, r2 + 8f5e: f7ff ffcf bl 8f00 <targetfn> + 8f62: eb01 0002 add\.w r0, r1, r2 + 8f66: f7ff ffcb bl 8f00 <targetfn> + 8f6a: eb01 0002 add\.w r0, r1, r2 + 8f6e: f7ff ffc7 bl 8f00 <targetfn> + 8f72: eb01 0002 add\.w r0, r1, r2 + 8f76: f7ff ffc3 bl 8f00 <targetfn> + 8f7a: eb01 0002 add\.w r0, r1, r2 + 8f7e: f7ff ffbf bl 8f00 <targetfn> + 8f82: eb01 0002 add\.w r0, r1, r2 + 8f86: f7ff ffbb bl 8f00 <targetfn> + 8f8a: eb01 0002 add\.w r0, r1, r2 + 8f8e: f7ff ffb7 bl 8f00 <targetfn> + 8f92: eb01 0002 add\.w r0, r1, r2 + 8f96: f7ff ffb3 bl 8f00 <targetfn> + 8f9a: eb01 0002 add\.w r0, r1, r2 + 8f9e: f7ff ffaf bl 8f00 <targetfn> + 8fa2: eb01 0002 add\.w r0, r1, r2 + 8fa6: f7ff ffab bl 8f00 <targetfn> + 8faa: eb01 0002 add\.w r0, r1, r2 + 8fae: f7ff ffa7 bl 8f00 <targetfn> + 8fb2: eb01 0002 add\.w r0, r1, r2 + 8fb6: f7ff ffa3 bl 8f00 <targetfn> + 8fba: eb01 0002 add\.w r0, r1, r2 + 8fbe: f7ff ff9f bl 8f00 <targetfn> + 8fc2: eb01 0002 add\.w r0, r1, r2 + 8fc6: f7ff ff9b bl 8f00 <targetfn> + 8fca: eb01 0002 add\.w r0, r1, r2 + 8fce: f7ff ff97 bl 8f00 <targetfn> + 8fd2: eb01 0002 add\.w r0, r1, r2 + 8fd6: f7ff ff93 bl 8f00 <targetfn> + 8fda: eb01 0002 add\.w r0, r1, r2 + 8fde: f7ff ff8f bl 8f00 <targetfn> + 8fe2: eb01 0002 add\.w r0, r1, r2 + 8fe6: f7ff ff8b bl 8f00 <targetfn> + 8fea: eb01 0002 add\.w r0, r1, r2 + 8fee: f7ff ff87 bl 8f00 <targetfn> + 8ff2: eb01 0002 add\.w r0, r1, r2 + 8ff6: f7ff ff83 bl 8f00 <targetfn> + 8ffa: eb01 0002 add\.w r0, r1, r2 + 8ffe: f000 f807 bl 9010 <_start\+0x108> + 9002: eb01 0002 add\.w r0, r1, r2 + 9006: f7ff ff7b bl 8f00 <targetfn> + 900a: 4770 bx lr + 900c: f3af 8000 nop\.w + 9010: f7ff bf76 b\.w 8f00 <targetfn> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel.s new file mode 100644 index 0000000..efbfb4b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx-rel.s @@ -0,0 +1,38 @@ + .syntax unified + .cpu cortex-a8 + .thumb + .text + + @ expansion 32 bytes + .macro bw1 +1: + add.w r0, r1, r2 + blx.w targetfn + add.w r0, r1, r2 + blx.w targetfn + add.w r0, r1, r2 + blx.w targetfn + add.w r0, r1, r2 + blx.w targetfn + .endm + + @ expansion 128 bytes + .macro bw2 + bw1 + bw1 + bw1 + bw1 + .endm + + .align 3 + .global _start + .thumb + .thumb_func + .type _start, %function +_start: + nop + + bw2 + bw2 + + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx.d new file mode 100644 index 0000000..4805256 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx.d @@ -0,0 +1,79 @@ + +.*: file format .* + + +Disassembly of section \.text: + +00008f00 <armfn>: + 8f00: e1a02413 lsl r2, r3, r4 + 8f04: e12fff1e bx lr + +00008f08 <_start>: + 8f08: bf00 nop + 8f0a: eb01 0002 add\.w r0, r1, r2 + 8f0e: f7ff eff8 blx 8f00 <armfn> + 8f12: eb01 0002 add\.w r0, r1, r2 + 8f16: f7ff eff4 blx 8f00 <armfn> + 8f1a: eb01 0002 add\.w r0, r1, r2 + 8f1e: f7ff eff0 blx 8f00 <armfn> + 8f22: eb01 0002 add\.w r0, r1, r2 + 8f26: f7ff efec blx 8f00 <armfn> + 8f2a: eb01 0002 add\.w r0, r1, r2 + 8f2e: f7ff efe8 blx 8f00 <armfn> + 8f32: eb01 0002 add\.w r0, r1, r2 + 8f36: f7ff efe4 blx 8f00 <armfn> + 8f3a: eb01 0002 add\.w r0, r1, r2 + 8f3e: f7ff efe0 blx 8f00 <armfn> + 8f42: eb01 0002 add\.w r0, r1, r2 + 8f46: f7ff efdc blx 8f00 <armfn> + 8f4a: eb01 0002 add\.w r0, r1, r2 + 8f4e: f7ff efd8 blx 8f00 <armfn> + 8f52: eb01 0002 add\.w r0, r1, r2 + 8f56: f7ff efd4 blx 8f00 <armfn> + 8f5a: eb01 0002 add\.w r0, r1, r2 + 8f5e: f7ff efd0 blx 8f00 <armfn> + 8f62: eb01 0002 add\.w r0, r1, r2 + 8f66: f7ff efcc blx 8f00 <armfn> + 8f6a: eb01 0002 add\.w r0, r1, r2 + 8f6e: f7ff efc8 blx 8f00 <armfn> + 8f72: eb01 0002 add\.w r0, r1, r2 + 8f76: f7ff efc4 blx 8f00 <armfn> + 8f7a: eb01 0002 add\.w r0, r1, r2 + 8f7e: f7ff efc0 blx 8f00 <armfn> + 8f82: eb01 0002 add\.w r0, r1, r2 + 8f86: f7ff efbc blx 8f00 <armfn> + 8f8a: eb01 0002 add\.w r0, r1, r2 + 8f8e: f7ff efb8 blx 8f00 <armfn> + 8f92: eb01 0002 add\.w r0, r1, r2 + 8f96: f7ff efb4 blx 8f00 <armfn> + 8f9a: eb01 0002 add\.w r0, r1, r2 + 8f9e: f7ff efb0 blx 8f00 <armfn> + 8fa2: eb01 0002 add\.w r0, r1, r2 + 8fa6: f7ff efac blx 8f00 <armfn> + 8faa: eb01 0002 add\.w r0, r1, r2 + 8fae: f7ff efa8 blx 8f00 <armfn> + 8fb2: eb01 0002 add\.w r0, r1, r2 + 8fb6: f7ff efa4 blx 8f00 <armfn> + 8fba: eb01 0002 add\.w r0, r1, r2 + 8fbe: f7ff efa0 blx 8f00 <armfn> + 8fc2: eb01 0002 add\.w r0, r1, r2 + 8fc6: f7ff ef9c blx 8f00 <armfn> + 8fca: eb01 0002 add\.w r0, r1, r2 + 8fce: f7ff ef98 blx 8f00 <armfn> + 8fd2: eb01 0002 add\.w r0, r1, r2 + 8fd6: f7ff ef94 blx 8f00 <armfn> + 8fda: eb01 0002 add\.w r0, r1, r2 + 8fde: f7ff ef90 blx 8f00 <armfn> + 8fe2: eb01 0002 add\.w r0, r1, r2 + 8fe6: f7ff ef8c blx 8f00 <armfn> + 8fea: eb01 0002 add\.w r0, r1, r2 + 8fee: f7ff ef88 blx 8f00 <armfn> + 8ff2: eb01 0002 add\.w r0, r1, r2 + 8ff6: f7ff ef84 blx 8f00 <armfn> + 8ffa: eb01 0002 add\.w r0, r1, r2 + 8ffe: f000 e808 blx 9010 <_start\+0x108> + 9002: eb01 0002 add\.w r0, r1, r2 + 9006: f7ff ef7c blx 8f00 <armfn> + 900a: 4770 bx lr + 900c: f3af 8000 nop\.w + 9010: eaffffba b 8f00 <armfn> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx.s new file mode 100644 index 0000000..5d74024 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-blx.s @@ -0,0 +1,44 @@ + .syntax unified + .cpu cortex-a8 + .text + + @ expansion 32 bytes + .macro bw1 + add.w r0, r1, r2 + blx.w armfn + add.w r0, r1, r2 + blx.w armfn + add.w r0, r1, r2 + blx.w armfn + add.w r0, r1, r2 + blx.w armfn + .endm + + @ expansion 128 bytes + .macro bw2 + bw1 + bw1 + bw1 + bw1 + .endm + + .arm + .align 2 +armfn: + mov r2, r3, asl r4 + bx lr + + .global _start + + .thumb + .thumb_func + .align 3 + .type _start, %function +_start: + nop + + @ Trigger Cortex-A8 erratum workaround with blx instructions. + bw2 + bw2 + + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-hdr.d b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-hdr.d new file mode 100644 index 0000000..027d2a1 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-hdr.d @@ -0,0 +1,24 @@ + +.*: file format .* + + +Disassembly of section \.text: + +00000fe0 <_start>: + fe0: bf00 nop + fe2: bf00 nop + fe4: bf00 nop + fe6: bf00 nop + fe8: bf00 nop + fea: bf00 nop + fec: bf00 nop + fee: bf00 nop + ff0: bf00 nop + ff2: bf00 nop + ff4: bf00 nop + ff6: bf00 nop + ff8: bf00 nop + ffa: ea81 0002 eor.w r0, r1, r2 + ffe: f000 b80f b.w 1020 <_start\+0x40> +#... + 1020: f7ff bfde b.w fe0 <_start> diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-hdr.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-hdr.s new file mode 100644 index 0000000..827c0f8 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-hdr.s @@ -0,0 +1,14 @@ + .syntax unified + + .section .text, "ax" + + .align 5 + .globl _start + .thumb_func +_start: + .rept 13 + nop + .endr + eor r0, r1, r2 + b.w _start + diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-hdr.t b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-hdr.t new file mode 100644 index 0000000..d3afacb --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-hdr.t @@ -0,0 +1,10 @@ + + +SECTIONS { + . = SIZEOF_HEADERS; + . += 0xf80; + .text : { + *(.text) + } = 0 + /DISCARD/ : { *(*) } +} diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-plt.ld b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-plt.ld new file mode 100644 index 0000000..3103f67 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-fix-plt.ld @@ -0,0 +1,18 @@ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x07000; + .hash : { *(.hash) } + .gnu.hash : { *(.gnu.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.dyn : { *(.rel.dyn) } + .rel.plt : { *(.rel.plt) } + . = 0x08000; + .plt : { *(.plt) } + . = 0x08ff0; + .text : { *(.text) } + . = 0x10000; + .dynamic : { *(.dynamic) } +} diff --git a/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-thumb-target.s b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-thumb-target.s new file mode 100644 index 0000000..96c180f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/cortex-a8-thumb-target.s @@ -0,0 +1,10 @@ + .syntax unified + .cpu cortex-a8 + .text + .thumb + .thumb_func + .align 3 + .global targetfn + .type targetfn, %function +targetfn: + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/data-only-map.d b/binutils-2.21/ld/testsuite/ld-arm/data-only-map.d new file mode 100644 index 0000000..39eed87 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/data-only-map.d @@ -0,0 +1,13 @@ + +[^:]*: file format elf32-littlearm + + +Disassembly of section \.text: + +00000000 <_start>: + 0: eb01 0002 add\.w r0, r1, r2 + 4: eb010002 \.word 0xeb010002 + 8: eb01 0002 add\.w r0, r1, r2 + c: eb01 0200 add\.w r2, r1, r0 + 10: eb010002 \.word 0xeb010002 + 14: eb010002 \.word 0xeb010002 diff --git a/binutils-2.21/ld/testsuite/ld-arm/data-only-map.ld b/binutils-2.21/ld/testsuite/ld-arm/data-only-map.ld new file mode 100644 index 0000000..7d6ea92 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/data-only-map.ld @@ -0,0 +1,16 @@ +/* Script for ld testsuite */ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + *(.text) + *(.after1) + *(.after2) + *(.after3) + *(.after4) + *(.after5) + } =0 +} + diff --git a/binutils-2.21/ld/testsuite/ld-arm/data-only-map.s b/binutils-2.21/ld/testsuite/ld-arm/data-only-map.s new file mode 100644 index 0000000..0c5e797 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/data-only-map.s @@ -0,0 +1,20 @@ +.syntax unified +.thumb +.global _start +_start: +add.w r0, r1, r2 + +.section .after1 +.word 0xeb010002 + +.section .after2 +add.w r0, r1, r2 + +.section .after3 +add.w r2, r1, r0 + +.section .after4 +.word 0xeb010002 + +.section .after5 +.word 0xeb010002 diff --git a/binutils-2.21/ld/testsuite/ld-arm/discard-unwind.ld b/binutils-2.21/ld/testsuite/ld-arm/discard-unwind.ld new file mode 100644 index 0000000..d8f6524 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/discard-unwind.ld @@ -0,0 +1,19 @@ +/* Script for ld testsuite */ +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + PROVIDE (__executable_start = 0x8000); . = 0x8000; + .text : + { + *(.before) + *(.text) + *(.after) + *(.ARM.extab*) + *(.glue_7) + *(.v4_bx) + } =0 + /DISCARD/ : { *(.ARM.exidx*) } + .ARM.attribues 0 : { *(.ARM.atttributes) } +} diff --git a/binutils-2.21/ld/testsuite/ld-arm/emit-relocs1-vxworks.d b/binutils-2.21/ld/testsuite/ld-arm/emit-relocs1-vxworks.d new file mode 100644 index 0000000..6d84a4c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/emit-relocs1-vxworks.d @@ -0,0 +1,12 @@ +#source: emit-relocs1.s +#ld: -Ttext 0x10000 --defsym target=0xc000 -e0 --emit-relocs +#objdump: -dr +#... + +10000: e1a00000 nop .* + +10004: e1a00000 nop .* + +10008: e1a00000 nop .* + +1000c: e1a00000 nop .* + +10010: eaffeffa b c000 <target> + +10010: R_ARM_PC24 target\+0xf+8 + +10014: eaffeffd b c010 <target\+0x10> + +10014: R_ARM_PC24 target\+0x8 diff --git a/binutils-2.21/ld/testsuite/ld-arm/emit-relocs1.d b/binutils-2.21/ld/testsuite/ld-arm/emit-relocs1.d new file mode 100644 index 0000000..191cb52 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/emit-relocs1.d @@ -0,0 +1,12 @@ +#source: emit-relocs1.s +#ld: -Ttext 0x10000 --defsym target=0xc000 -e0 --emit-relocs +#objdump: -dr +#... + +10000: e1a00000 nop .* + +10004: e1a00000 nop .* + +10008: e1a00000 nop .* + +1000c: e1a00000 nop .* + +10010: eaffeffa b c000 <target> + +10010: R_ARM_(JUMP|PC)24 target + +10014: eaffeffd b c010 <target\+0x10> + +10014: R_ARM_(JUMP|PC)24 target diff --git a/binutils-2.21/ld/testsuite/ld-arm/emit-relocs1.s b/binutils-2.21/ld/testsuite/ld-arm/emit-relocs1.s new file mode 100644 index 0000000..8971d4d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/emit-relocs1.s @@ -0,0 +1,6 @@ + nop + nop + nop + nop + b target + b target+16 diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-arm-pic-veneer.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-arm-pic-veneer.d new file mode 100644 index 0000000..f5ff227 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-arm-pic-veneer.d @@ -0,0 +1,17 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: eb000000 bl 1008 <__bar_veneer> + 1004: 00000000 andeq r0, r0, r0 + +00001008 <__bar_veneer>: + 1008: e59fc000 ldr ip, \[pc, #0\] ; 1010 <__bar_veneer\+0x8> + 100c: e08ff00c add pc, pc, ip + 1010: 0200000c .word 0x0200000c + 1014: 00000000 .word 0x00000000 +Disassembly of section .foo: + +02001020 <bar>: + 2001020: e12fff1e bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-arm.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-arm.d new file mode 100644 index 0000000..7ee6d66 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-arm.d @@ -0,0 +1,15 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: eb000000 bl 1008 <__bar_veneer> + 1004: 00000000 andeq r0, r0, r0 + +00001008 <__bar_veneer>: + 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_veneer\+0x4> + 100c: 02001020 .word 0x02001020 +Disassembly of section .foo: + +02001020 <bar>: + 2001020: e12fff1e bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-arm.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-arm.s new file mode 100644 index 0000000..00c1e48 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-arm.s @@ -0,0 +1,20 @@ +@ Test to ensure that a ARM to ARM call exceeding 32Mb generates a stub. + + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + +_start: + bl bar + +@ We will place the section .foo at 0x2001020. + + .section .foo, "xa" + + .type bar, %function +bar: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-thumb-blx-pic-veneer.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-thumb-blx-pic-veneer.d new file mode 100644 index 0000000..45bc01c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-thumb-blx-pic-veneer.d @@ -0,0 +1,17 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: eb000000 bl 1008 <__bar_from_arm> + 1004: 00000000 andeq r0, r0, r0 + +00001008 <__bar_from_arm>: + 1008: e59fc004 ldr ip, \[pc, #4\] ; 1014 <__bar_from_arm\+0xc> + 100c: e08fc00c add ip, pc, ip + 1010: e12fff1c bx ip + 1014: 02000001 .word 0x02000001 +Disassembly of section .foo: + +02001014 <bar>: + 2001014: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-thumb-blx.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-thumb-blx.d new file mode 100644 index 0000000..993a028 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-thumb-blx.d @@ -0,0 +1,15 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: eb000000 bl 1008 <__bar_from_arm> + 1004: 00000000 andeq r0, r0, r0 + +00001008 <__bar_from_arm>: + 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_from_arm\+0x4> + 100c: 02001015 .word 0x02001015 +Disassembly of section .foo: + +02001014 <bar>: + 2001014: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-thumb-pic-veneer.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-thumb-pic-veneer.d new file mode 100644 index 0000000..45bc01c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-thumb-pic-veneer.d @@ -0,0 +1,17 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: eb000000 bl 1008 <__bar_from_arm> + 1004: 00000000 andeq r0, r0, r0 + +00001008 <__bar_from_arm>: + 1008: e59fc004 ldr ip, \[pc, #4\] ; 1014 <__bar_from_arm\+0xc> + 100c: e08fc00c add ip, pc, ip + 1010: e12fff1c bx ip + 1014: 02000001 .word 0x02000001 +Disassembly of section .foo: + +02001014 <bar>: + 2001014: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-thumb.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-thumb.d new file mode 100644 index 0000000..8291be3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-thumb.d @@ -0,0 +1,17 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: eb000000 bl 1008 <__bar_from_arm> + 1004: 00000000 andeq r0, r0, r0 + +00001008 <__bar_from_arm>: + 1008: e59fc000 ldr ip, \[pc, #0\] ; 1010 <__bar_from_arm\+0x8> + 100c: e12fff1c bx ip + 1010: 02001015 .word 0x02001015 + 1014: 00000000 .word 0x00000000 +Disassembly of section .foo: + +02001014 <bar>: + 2001014: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-thumb.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-thumb.s new file mode 100644 index 0000000..c69f31c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-arm-thumb.s @@ -0,0 +1,20 @@ +@ Test to ensure that a ARM to Thumb call exceeding 32Mb generates a stub. + + .global _start + .global bar + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + +_start: + bl bar + +@ We will place the section .foo at 0x2001010. + + .section .foo, "xa" + .thumb_func +bar: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-data.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-data.d new file mode 100644 index 0000000..a8b231c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-data.d @@ -0,0 +1,19 @@ +.*: file format .* + +Disassembly of section .text: + +00008000 <_start>: + 8000: ea000000 b 8008 <__far_veneer> + 8004: 00000000 andeq r0, r0, r0 + +00008008 <__far_veneer>: + 8008: e51ff004 ldr pc, \[pc, #-4\] ; 800c <__far_veneer\+0x4> + 800c: 12340000 \.word 0x12340000 + +00008010 <after>: + 8010: 11111111 \.word 0x11111111 + +Disassembly of section \.far: + +12340000 <far>: +12340000: e12fff1e bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-data.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-data.s new file mode 100644 index 0000000..ed66199 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-data.s @@ -0,0 +1,14 @@ + .syntax unified + .text + .global _start + .type _start, %function +_start: + b far + +.section .after +after: + .word 0x11111111 + + .section .far, "ax" + .type far, %function +far: bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-group-limit.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-group-limit.d new file mode 100644 index 0000000..204dcd8 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-group-limit.d @@ -0,0 +1,21 @@ + +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: eb000000 bl 1008 <__bar_veneer> + 1004: 00000000 andeq r0, r0, r0 + +00001008 <__bar_veneer>: + 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_veneer\+0x4> + 100c: 02003020 .word 0x02003020 + +00001010 <myfunc>: + ... + 2001010: eb000802 bl 2003020 <bar> + +Disassembly of section .far: + +02003020 <bar>: + 2003020: e12fff1e bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-group-size2.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-group-size2.d new file mode 100644 index 0000000..8a35313 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-group-size2.d @@ -0,0 +1,57 @@ + +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: eb000000 bl 1008 <__bar_from_arm> + 1004: eb000002 bl 1014 <__bar2_veneer> + +00001008 <__bar_from_arm>: + 1008: e59fc000 ldr ip, \[pc, #0\] ; 1010 <__bar_from_arm\+0x8> + 100c: e12fff1c bx ip + 1010: 02003021 .word 0x02003021 + +00001014 <__bar2_veneer>: + 1014: e51ff004 ldr pc, \[pc, #-4\] ; 1018 <__bar2_veneer\+0x4> + 1018: 02003024 .word 0x02003024 + 101c: 00000000 .word 0x00000000 + +00001020 <myfunc>: + 1020: eb000008 bl 1048 <__bar3_veneer> + 1024: eb000001 bl 1030 <__bar4_from_arm> + 1028: eb000003 bl 103c <__bar5_from_arm> + 102c: 00000000 andeq r0, r0, r0 + +00001030 <__bar4_from_arm>: + 1030: e59fc000 ldr ip, \[pc, #0\] ; 1038 <__bar4_from_arm\+0x8> + 1034: e12fff1c bx ip + 1038: 0200302d .word 0x0200302d + +0000103c <__bar5_from_arm>: + 103c: e59fc000 ldr ip, \[pc, #0\] ; 1044 <__bar5_from_arm\+0x8> + 1040: e12fff1c bx ip + 1044: 0200302f .word 0x0200302f + +00001048 <__bar3_veneer>: + 1048: e51ff004 ldr pc, \[pc, #-4\] ; 104c <__bar3_veneer\+0x4> + 104c: 02003028 .word 0x02003028 + ... + +Disassembly of section .foo: + +02003020 <bar>: + 2003020: 4770 bx lr + ... + +02003024 <bar2>: + 2003024: e12fff1e bx lr + +02003028 <bar3>: + 2003028: e12fff1e bx lr + +0200302c <bar4>: + 200302c: 4770 bx lr + +0200302e <bar5>: + 200302e: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-group.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-group.d new file mode 100644 index 0000000..a72c14f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-group.d @@ -0,0 +1,56 @@ + +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: eb000009 bl 102c <__bar_from_arm> + 1004: eb000006 bl 1024 <__bar2_veneer> + +00001008 <myfunc>: + 1008: eb00000d bl 1044 <__bar3_veneer> + 100c: eb000001 bl 1018 <__bar4_from_arm> + 1010: eb000008 bl 1038 <__bar5_from_arm> + 1014: 00000000 andeq r0, r0, r0 + +00001018 <__bar4_from_arm>: + 1018: e59fc000 ldr ip, \[pc, #0\] ; 1020 <__bar4_from_arm\+0x8> + 101c: e12fff1c bx ip + 1020: 0200302d .word 0x0200302d + +00001024 <__bar2_veneer>: + 1024: e51ff004 ldr pc, \[pc, #-4\] ; 1028 <__bar2_veneer\+0x4> + 1028: 02003024 .word 0x02003024 + +0000102c <__bar_from_arm>: + 102c: e59fc000 ldr ip, \[pc, #0\] ; 1034 <__bar_from_arm\+0x8> + 1030: e12fff1c bx ip + 1034: 02003021 .word 0x02003021 + +00001038 <__bar5_from_arm>: + 1038: e59fc000 ldr ip, \[pc, #0\] ; 1040 <__bar5_from_arm\+0x8> + 103c: e12fff1c bx ip + 1040: 0200302f .word 0x0200302f + +00001044 <__bar3_veneer>: + 1044: e51ff004 ldr pc, \[pc, #-4\] ; 1048 <__bar3_veneer\+0x4> + 1048: 02003028 .word 0x02003028 + ... + +Disassembly of section .foo: + +02003020 <bar>: + 2003020: 4770 bx lr + ... + +02003024 <bar2>: + 2003024: e12fff1e bx lr + +02003028 <bar3>: + 2003028: e12fff1e bx lr + +0200302c <bar4>: + 200302c: 4770 bx lr + +0200302e <bar5>: + 200302e: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-group.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-group.s new file mode 100644 index 0000000..0ede36d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-group.s @@ -0,0 +1,44 @@ +@ Test to ensure that ARM calls exceeding 32Mb generate stubs. + + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + +_start: + bl bar + bl bar2 + + +@ We will place the section .foo at 0x2003020. + + .section .foo, "xa" + + .global bar + .thumb_func +bar: + bx lr + + .arm + .global bar2 + .type bar2, %function +bar2: + bx lr + + .global bar3 + .type bar3, %function +bar3: + bx lr + + .global bar4 + .thumb_func +bar4: + bx lr + + .global bar5 + .type bar5, %function +bar5: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-group2.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-group2.s new file mode 100644 index 0000000..774869f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-group2.s @@ -0,0 +1,7 @@ +@ Test to ensure that ARM calls exceeding 32Mb generate stubs. + + .text +myfunc: + bl bar3 + bl bar4 + bl bar5 diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-group3.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-group3.s new file mode 100644 index 0000000..ea2ce7f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-group3.s @@ -0,0 +1,9 @@ +@ Test to ensure that ARM calls exceeding 32Mb generate stubs, +@ and that stubs are correctly inserted between input sections +@ when one contribution size exceeds the limit. + + .text + .global bar + .global _start +_start: + bl bar diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-group4.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-group4.s new file mode 100644 index 0000000..17f503b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-group4.s @@ -0,0 +1,13 @@ +@ Test to ensure that ARM calls exceeding 32Mb generate stubs, +@ and that a large input section forces stub insertion before its +@ contribution. + + .text +myfunc: + .space 0x2000000 + bl bar + + .section .far, "xa" + .global bar +bar: + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-mix.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-mix.d new file mode 100644 index 0000000..97e062c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-mix.d @@ -0,0 +1,51 @@ + +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: eb000004 bl 1018 <__bar_from_arm> + 1004: eb00000e bl 1044 <__bar2_veneer> + 1008: eb000005 bl 1024 <__bar3_veneer> + 100c: eb000009 bl 1038 <__bar4_from_arm> + 1010: eb000005 bl 102c <__bar5_from_arm> + 1014: 00000000 andeq r0, r0, r0 + +00001018 <__bar_from_arm>: + 1018: e59fc000 ldr ip, \[pc, #0\] ; 1020 <__bar_from_arm\+0x8> + 101c: e12fff1c bx ip + 1020: 02002021 .word 0x02002021 +00001024 <__bar3_veneer>: + 1024: e51ff004 ldr pc, \[pc, #-4\] ; 1028 <__bar3_veneer\+0x4> + 1028: 02002028 .word 0x02002028 +0000102c <__bar5_from_arm>: + 102c: e59fc000 ldr ip, \[pc, #0\] ; 1034 <__bar5_from_arm\+0x8> + 1030: e12fff1c bx ip + 1034: 0200202f .word 0x0200202f +00001038 <__bar4_from_arm>: + 1038: e59fc000 ldr ip, \[pc, #0\] ; 1040 <__bar4_from_arm\+0x8> + 103c: e12fff1c bx ip + 1040: 0200202d .word 0x0200202d + +00001044 <__bar2_veneer>: + 1044: e51ff004 ldr pc, \[pc, #-4\] ; 1048 <__bar2_veneer\+0x4> + 1048: 02002024 .word 0x02002024 + ... + +Disassembly of section .foo: + +02002020 <bar>: + 2002020: 4770 bx lr + ... + +02002024 <bar2>: + 2002024: e12fff1e bx lr + +02002028 <bar3>: + 2002028: e12fff1e bx lr + +0200202c <bar4>: + 200202c: 4770 bx lr + +0200202e <bar5>: + 200202e: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-mix.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-mix.s new file mode 100644 index 0000000..41b27f2 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-mix.s @@ -0,0 +1,46 @@ +@ Test to ensure that ARM calls exceeding 32Mb generate stubs. + + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + +_start: + bl bar + bl bar2 + bl bar3 + bl bar4 + bl bar5 + +@ We will place the section .foo at 0x2002020. + + .section .foo, "xa" + + .global bar + .thumb_func +bar: + bx lr + + .arm + .global bar2 + .type bar2, %function +bar2: + bx lr + + .global bar3 + .type bar3, %function +bar3: + bx lr + + .global bar4 + .thumb_func +bar4: + bx lr + + .global bar5 + .type bar5, %function +bar5: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-mix2.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-mix2.d new file mode 100644 index 0000000..c79ddea --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-mix2.d @@ -0,0 +1,56 @@ + +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: eb000000 bl 1008 <__bar_from_arm> + 1004: eb000002 bl 1014 <__bar2_veneer> + +00001008 <__bar_from_arm>: + 1008: e59fc000 ldr ip, \[pc, #0\] ; 1010 <__bar_from_arm\+0x8> + 100c: e12fff1c bx ip + 1010: 02003021 .word 0x02003021 +00001014 <__bar2_veneer>: + 1014: e51ff004 ldr pc, \[pc, #-4\] ; 1018 <__bar2_veneer\+0x4> + 1018: 02003024 .word 0x02003024 + 101c: 00000000 .word 0x00000000 +Disassembly of section .mytext: + +00002000 <__bar3_veneer-0x10>: + 2000: eb000002 bl 2010 <__bar3_veneer> + 2004: eb000003 bl 2018 <__bar4_from_arm> + 2008: eb000005 bl 2024 <__bar5_from_arm> + 200c: 00000000 andeq r0, r0, r0 + +00002010 <__bar3_veneer>: + 2010: e51ff004 ldr pc, \[pc, #-4\] ; 2014 <__bar3_veneer\+0x4> + 2014: 02003028 .word 0x02003028 + +00002018 <__bar4_from_arm>: + 2018: e59fc000 ldr ip, \[pc, #0\] ; 2020 <__bar4_from_arm\+0x8> + 201c: e12fff1c bx ip + 2020: 0200302d .word 0x0200302d + +00002024 <__bar5_from_arm>: + 2024: e59fc000 ldr ip, \[pc, #0\] ; 202c <__bar5_from_arm\+0x8> + 2028: e12fff1c bx ip + 202c: 0200302f .word 0x0200302f + ... +Disassembly of section .foo: + +02003020 <bar>: + 2003020: 4770 bx lr + ... + +02003024 <bar2>: + 2003024: e12fff1e bx lr + +02003028 <bar3>: + 2003028: e12fff1e bx lr + +0200302c <bar4>: + 200302c: 4770 bx lr + +0200302e <bar5>: + 200302e: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-mix2.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-mix2.s new file mode 100644 index 0000000..803e8d0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-mix2.s @@ -0,0 +1,51 @@ +@ Test to ensure that ARM calls exceeding 32Mb generate stubs. + + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + +_start: + bl bar + bl bar2 + + +@ We will place the section .mytext at 0x2000. + + .section .mytext, "xa" + bl bar3 + bl bar4 + bl bar5 + +@ We will place the section .foo at 0x2003020. + + .section .foo, "xa" + + .global bar + .thumb_func +bar: + bx lr + + .arm + .global bar2 + .type bar2, %function +bar2: + bx lr + + .global bar3 + .type bar3, %function +bar3: + bx lr + + .global bar4 + .thumb_func +bar4: + bx lr + + .global bar5 + .type bar5, %function +bar5: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-app-v5.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-app-v5.d new file mode 100644 index 0000000..ec8312f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-app-v5.d @@ -0,0 +1,85 @@ + +tmpdir/farcall-mixed-app-v5: file format elf32-(little|big)arm +architecture: arm, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x.* + +Disassembly of section .plt: + +.* <.plt>: + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x28> + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* + +Disassembly of section .text: + +.* <_start>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: eb000008 bl .* <__app_func_veneer> + .*: ebfffff5 bl .* <_start-0x18> + .*: ebfffff1 bl .* <_start-0x24> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + +.* <app_tfunc_close>: + .*: b500 push {lr} + .*: f7ff efdc blx .* <_start-0x24> + .*: bd00 pop {pc} + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + +.* <__app_func_veneer>: + .*: e51ff004 ldr pc, \[pc, #-4\] ; .* <__app_func_veneer\+0x4> + .*: 02100000 .word 0x02100000 + +Disassembly of section .far_arm: + +.* <app_func>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: eb000008 bl .* <__lib_func1_veneer> + .*: eb000009 bl .* <__lib_func2_veneer> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + +.* <app_func2>: + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + +.* <__lib_func1_veneer>: + .*: e51ff004 ldr pc, \[pc, #-4\] ; 2100034 <__lib_func1_veneer\+0x4> + .*: 000081e8 .word 0x000081e8 +.* <__lib_func2_veneer>: + .*: e51ff004 ldr pc, \[pc, #-4\] ; 210003c <__lib_func2_veneer\+0x4> + .*: 000081dc .word 0x000081dc + +Disassembly of section .far_thumb: + +.* <app_tfunc>: + .*: b500 push {lr} + .*: f000 e806 blx .* <__lib_func2_from_thumb> + .*: bd00 pop {pc} + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + +.* <__lib_func2_from_thumb>: + .*: e51ff004 ldr pc, \[pc, #-4\] ; 2200014 <__lib_func2_from_thumb\+0x4> + .*: 000081dc .word 0x000081dc diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-app.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-app.d new file mode 100644 index 0000000..c7aff3e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-app.d @@ -0,0 +1,90 @@ + +tmpdir/farcall-mixed-app: file format elf32-(little|big)arm +architecture: arm, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x.* + +Disassembly of section .plt: + +.* <.plt>: + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x28> + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* + +Disassembly of section .text: + +.* <_start>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: eb000008 bl .* <__app_func_veneer> + .*: ebfffff6 bl .* <_start-0x14> + .*: ebfffff2 bl .* <_start-0x20> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + +.* <app_tfunc_close>: + .*: b500 push {lr} + .*: f7ff ffdb bl 81dc <_start-0x24> + .*: bd00 pop {pc} + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + +.* <__app_func_veneer>: + .*: e51ff004 ldr pc, \[pc, #-4\] ; 8234 <__app_func_veneer\+0x4> + .*: 02100000 .word 0x02100000 + +Disassembly of section .far_arm: + +.* <app_func>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: eb000008 bl .* <__lib_func1_veneer> + .*: eb000009 bl .* <__lib_func2_veneer> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + +.* <app_func2>: + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + +.* <__lib_func1_veneer>: + .*: e51ff004 ldr pc, \[pc, #-4\] ; 2100034 <__lib_func1_veneer\+0x4> + .*: 000081ec .word 0x000081ec +.* <__lib_func2_veneer>: + .*: e51ff004 ldr pc, \[pc, #-4\] ; 210003c <__lib_func2_veneer\+0x4> + .*: 000081e0 .word 0x000081e0 + +Disassembly of section .far_thumb: + +.* <app_tfunc>: + .*: b500 push {lr} + .*: f000 f805 bl .* <__lib_func2_from_thumb> + .*: bd00 pop {pc} + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + +.* <__lib_func2_from_thumb>: + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e51ff004 ldr pc, \[pc, #-4\] ; 2200018 <__lib_func2_from_thumb\+0x8> + .*: 000081e0 .word 0x000081e0 + .*: 00000000 .word 0x00000000 diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-app.r b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-app.r new file mode 100644 index 0000000..910a361 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-app.r @@ -0,0 +1,10 @@ + +tmpdir/farcall-mixed-app.*: file format elf32-(little|big)arm + +DYNAMIC RELOCATION RECORDS +OFFSET TYPE VALUE +.* R_ARM_COPY data_obj +.* R_ARM_JUMP_SLOT lib_func2 +.* R_ARM_JUMP_SLOT lib_func1 + + diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-app.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-app.s new file mode 100644 index 0000000..e462ba3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-app.s @@ -0,0 +1,61 @@ + .text + .p2align 4 + .globl _start +_start: + mov ip, sp + stmdb sp!, {r11, ip, lr, pc} + bl app_func + bl lib_func1 + bl lib_func2 + ldmia sp, {r11, sp, lr} + bx lr + + .p2align 4 + .globl app_tfunc_close + .type app_tfunc_close,%function + .thumb_func + .code 16 +app_tfunc_close: + push {lr} + bl lib_func2 + pop {pc} + bx lr + +@ We will place the section .far_arm at 0x2100000. + .section .far_arm, "xa" + + .arm + .p2align 4 + .globl app_func + .type app_func,%function +app_func: + mov ip, sp + stmdb sp!, {r11, ip, lr, pc} + bl lib_func1 + bl lib_func2 + ldmia sp, {r11, sp, lr} + bx lr + + .arm + .p2align 4 + .globl app_func2 + .type app_func2,%function +app_func2: + bx lr + +@ We will place the section .far_thumb at 0x2200000. + .section .far_thumb, "xa" + + .p2align 4 + .globl app_tfunc + .type app_tfunc,%function + .thumb_func + .code 16 +app_tfunc: + push {lr} + bl lib_func2 + pop {pc} + bx lr + + .data + .long data_obj diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-app.sym b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-app.sym new file mode 100644 index 0000000..8e04cc3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-app.sym @@ -0,0 +1,15 @@ + +Symbol table for image: + +Num +Buc: +Value +Size +Type +Bind +Vis +Ndx +Name + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS _edata + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_start__ + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS _end + +.. +..: ........ +4 +OBJECT +GLOBAL +DEFAULT +12 data_obj + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_end__ + +.. +..: 0*[^0]*.* +0 +FUNC +GLOBAL +DEFAULT +UND lib_func1 + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +11 __data_start + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __end__ + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_start + +.. +..: .......0 +0 +FUNC +GLOBAL +DEFAULT +14 app_func2 + +.. +..: 0*[^0]*.* +0 +FUNC +GLOBAL +DEFAULT +UND lib_func2 + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS _bss_end__ diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d new file mode 100644 index 0000000..b6729b2 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d @@ -0,0 +1,123 @@ +tmpdir/farcall-mixed-lib.so: file format elf32-(little|big)arm +architecture: arm, flags 0x00000150: +HAS_SYMS, DYNAMIC, D_PAGED +start address 0x.* + +Disassembly of section .plt: + +.* <.plt>: + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1-0x.*> + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* .word .* + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]! ; .* + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]! ; 0x.* + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]! ; 0x.* + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]! ; 0x.* + +Disassembly of section .text: + +.* <lib_func1>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: ebffff.. bl .* <lib_func1-0x.*> + .*: ebffff.. bl .* <lib_func1-0x.*> + .*: ebffff.. bl .* <lib_func1-0x.*> + .*: ebffff.. bl .* <lib_func1-0x.*> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + ... + +.* <__real_lib_func2>: + .*: f000 f80e bl 1000330 <__app_func_from_thumb> + .*: f000 f81c bl 1000350 <__app_func_weak_from_thumb> + .*: f000 f822 bl 1000360 <__lib_func3_from_thumb> + .*: f000 f810 bl 1000340 <__lib_func4_from_thumb> + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + +.* <__app_func_from_thumb>: + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e59fc000 ldr ip, \[pc, #0\] ; 100033c <__app_func_from_thumb\+0xc> + .*: e08cf00f add pc, ip, pc + .*: feffff68 .word 0xfeffff68 + +.* <__lib_func4_from_thumb>: + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e59fc000 ldr ip, \[pc, #0\] ; 100034c <__lib_func4_from_thumb\+0xc> + .*: e08cf00f add pc, ip, pc + .*: feffff88 .word 0xfeffff88 + +.* <__app_func_weak_from_thumb>: + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e59fc000 ldr ip, \[pc, #0\] ; 100035c <__app_func_weak_from_thumb\+0xc> + .*: e08cf00f add pc, ip, pc + .*: feffff58 .word 0xfeffff58 + +.* <__lib_func3_from_thumb>: + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e59fc000 ldr ip, \[pc, #0\] ; 100036c <__lib_func3_from_thumb\+0xc> + .*: e08cf00f add pc, ip, pc + .*: feffff58 .word 0xfeffff58 + ... + +.* <__real_lib_func3>: + .*: f000 f806 bl 2000380 <__app_func_from_thumb> + .*: f000 f80c bl 2000390 <__app_func_weak_from_thumb> + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + +.* <__app_func_from_thumb>: + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e59fc000 ldr ip, \[pc, #0\] ; 200038c <__app_func_from_thumb\+0xc> + .*: e08cf00f add pc, ip, pc + .*: fdffff18 .word 0xfdffff18 + +.* <__app_func_weak_from_thumb>: + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e59fc000 ldr ip, \[pc, #0\] ; 200039c <__app_func_weak_from_thumb\+0xc> + .*: e08cf00f add pc, ip, pc + .*: fdffff18 .word 0xfdffff18 + +.* <lib_func3>: + .*: e59fc004 ldr ip, \[pc, #4\] ; 20003ac <lib_func3\+0xc> + .*: e08cc00f add ip, ip, pc + .*: e12fff1c bx ip + .*: ffffffc5 .word 0xffffffc5 + +.* <lib_func2>: + .*: e59fc004 ldr ip, \[pc, #4\] ; 20003bc <lib_func2\+0xc> + .*: e08cc00f add ip, ip, pc + .*: e12fff1c bx ip + .*: feffff55 .word 0xfeffff55 diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-lib.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-lib.d new file mode 100644 index 0000000..9df3933 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-lib.d @@ -0,0 +1,92 @@ +tmpdir/farcall-mixed-lib.so: file format elf32-(little|big)arm +architecture: arm, flags 0x00000150: +HAS_SYMS, DYNAMIC, D_PAGED +start address 0x.* + +Disassembly of section .plt: + +.* <.plt>: + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1-0x.*> + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* + +Disassembly of section .text: + +.* <lib_func1>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: ebffff.. bl .* <lib_func1-0x..?> + .*: ebffff.. bl .* <lib_func1-0x..?> + .*: ebfffff. bl .* <lib_func1-0x..?> + .*: ebfffff. bl .* <lib_func1-0x..?> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + ... + +.* <lib_func2>: + .*: f000 e820 blx 1000344 <__app_func_from_thumb> + .*: f000 e812 blx 100032c <__app_func_weak_from_thumb> + .*: f000 e80a blx 1000320 <__lib_func3_from_thumb> + .*: f000 e814 blx 1000338 <__lib_func4_from_thumb> + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + +.* <__lib_func3_from_thumb>: + .*: e59fc000 ldr ip, \[pc, #0\] ; 1000328 <__lib_func3_from_thumb\+0x8> + .*: e08ff00c add pc, pc, ip + .*: feffff90 .word 0xfeffff90 + +.* <__app_func_weak_from_thumb>: + .*: e59fc000 ldr ip, \[pc, #0\] ; 1000334 <__app_func_weak_from_thumb\+0x8> + .*: e08ff00c add pc, pc, ip + .*: feffff78 .word 0xfeffff78 + +.* <__lib_func4_from_thumb>: + .*: e59fc000 ldr ip, \[pc, #0\] ; 1000340 <__lib_func4_from_thumb\+0x8> + .*: e08ff00c add pc, pc, ip + .*: feffff84 .word 0xfeffff84 + +.* <__app_func_from_thumb>: + .*: e59fc000 ldr ip, \[pc, #0\] ; 100034c <__app_func_from_thumb\+0x8> + .*: e08ff00c add pc, pc, ip + .*: feffff54 .word 0xfeffff54 + ... + +.* <lib_func3>: + .*: f000 e806 blx 2000370 <__app_func_from_thumb> + .*: f000 e80a blx 200037c <__app_func_weak_from_thumb> + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + +.* <__app_func_from_thumb>: + .*: e59fc000 ldr ip, \[pc, #0\] ; 2000378 <__app_func_from_thumb\+0x8> + .*: e08ff00c add pc, pc, ip + .*: fdffff28 .word 0xfdffff28 + +.* <__app_func_weak_from_thumb>: + .*: e59fc000 ldr ip, \[pc, #0\] ; 2000384 <__app_func_weak_from_thumb\+0x8> + .*: e08ff00c add pc, pc, ip + .*: fdffff28 .word 0xfdffff28 + ... diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-lib.r b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-lib.r new file mode 100644 index 0000000..a44f83b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-lib.r @@ -0,0 +1,8 @@ + +tmpdir/farcall-mixed-lib.so: file format elf32-(little|big)arm + +DYNAMIC RELOCATION RECORDS +OFFSET TYPE VALUE +.* R_ARM_JUMP_SLOT app_func2 + + diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-lib1.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-lib1.s new file mode 100644 index 0000000..dea26b9 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-lib1.s @@ -0,0 +1,34 @@ +@ Create a large shared library so that calls through PLT to an undef +@ symbol require insertion of a long branch stub. +@ Check also calls to an undef weak symbol. + + .text + + .p2align 4 + .globl lib_func1 + .type lib_func1, %function +lib_func1: + mov ip, sp + stmdb sp!, {r11, ip, lr, pc} + bl app_func + .weak app_func_weak + bl app_func_weak + bl lib_func3 + bl lib_func4 + ldmia sp, {r11, sp, lr} + bx lr + .size lib_func1, . - lib_func1 + + .space 0x1000000 + .p2align 4 + .globl lib_func2 + .type lib_func2, %function + .thumb_func + .code 16 +lib_func2: + bl app_func + bl app_func_weak + bl lib_func3 + bl lib_func4 + bx lr + .size lib_func2, . - lib_func2 diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-lib2.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-lib2.s new file mode 100644 index 0000000..b75c534 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-mixed-lib2.s @@ -0,0 +1,18 @@ +@ Create a large shared library so that calls through PLT to an undef +@ symbol require insertion of a long branch stub. +@ Check also calls to an undef weak symbol. + + .text + + .space 0x1000000 + .p2align 4 + .globl lib_func3 + .type lib_func3, %function + .thumb_func + .code 16 +lib_func3: + bl app_func + .weak app_func_weak + bl app_func_weak + bx lr + .size lib_func3, . - lib_func3 diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-section.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-section.d new file mode 100644 index 0000000..4e6d37d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-section.d @@ -0,0 +1,5 @@ +#name: ARM-ARM farcall to symbol of type STT_SECTION +#source: farcall-section.s +#as: +#ld: -Ttext 0x1000 --section-start .foo=0x2001014 +#error: .*\(.text\+0x0\): relocation truncated to fit: R_ARM_CALL against `.foo' diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-section.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-section.s new file mode 100644 index 0000000..31c9038 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-section.s @@ -0,0 +1,20 @@ +@ Test to ensure that a ARM to ARM call exceeding 32Mb generates an error +@ if the destination is of type STT_SECTION (eg non-global symbol) + + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + +_start: + bl bar + +@ We will place the section .foo at 0x2001020. + + .section .foo, "xa" + +bar: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm-blx-pic-veneer.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm-blx-pic-veneer.d new file mode 100644 index 0000000..a0d1f36 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm-blx-pic-veneer.d @@ -0,0 +1,18 @@ +.*: file format .* + +Disassembly of section .text: + +01c01010 <_start>: + 1c01010: f300 e802 blx 1f01018 <__bar_from_thumb> + \.\.\. + 1f01014: f0ff effe blx 2001014 <bar> + +01f01018 <__bar_from_thumb>: + 1f01018: e59fc000 ldr ip, \[pc, #0\] ; 1f01020 <__bar_from_thumb\+0x8> + 1f0101c: e08ff00c add pc, pc, ip + 1f01020: 000ffff0 .word 0x000ffff0 + 1f01024: 00000000 .word 0x00000000 +Disassembly of section .foo: + +02001014 <bar>: + 2001014: e12fff1e bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm-blx.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm-blx.d new file mode 100644 index 0000000..4a2b36a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm-blx.d @@ -0,0 +1,16 @@ +.*: file format .* + +Disassembly of section .text: + +01c01010 <_start>: + 1c01010: f300 e802 blx 1f01018 <__bar_from_thumb> + \.\.\. + 1f01014: f0ff effe blx 2001014 <bar> + +01f01018 <__bar_from_thumb>: + 1f01018: e51ff004 ldr pc, \[pc, #-4\] ; 1f0101c <__bar_from_thumb\+0x4> + 1f0101c: 02001014 .word 0x02001014 +Disassembly of section .foo: + +02001014 <bar>: + 2001014: e12fff1e bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d new file mode 100644 index 0000000..eb8da17 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm-pic-veneer.d @@ -0,0 +1,20 @@ +.*: file format .* + +Disassembly of section .text: + +01c01010 <_start>: + 1c01010: f300 f802 bl 1f01018 <__bar_from_thumb> + ... + 1f01014: f000 f800 bl 1f01018 <__bar_from_thumb> + +01f01018 <__bar_from_thumb>: + 1f01018: 4778 bx pc + 1f0101a: 46c0 nop ; \(mov r8, r8\) + 1f0101c: e59fc000 ldr ip, \[pc, #0\] ; 1f01024 <__bar_from_thumb\+0xc> + 1f01020: e08cf00f add pc, ip, pc + 1f01024: 000fffec .word 0x000fffec + +Disassembly of section .foo: + +02001014 <bar>: + 2001014: e12fff1e bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm-short.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm-short.d new file mode 100644 index 0000000..4e19039 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm-short.d @@ -0,0 +1,17 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: f000 f802 bl 1008 <__bar_from_thumb> + 1004: 0000 movs r0, r0 + \.\.\. + +00001008 <__bar_from_thumb>: + 1008: 4778 bx pc + 100a: 46c0 nop ; \(mov r8, r8\) + 100c: ea000400 b 2014 <bar> +Disassembly of section .foo: + +00002014 <bar>: + 2014: e12fff1e bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm-short.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm-short.s new file mode 100644 index 0000000..1865380 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm-short.s @@ -0,0 +1,21 @@ +@ Test to ensure that a Thumb to ARM call within 4Mb does not generate a stub. + + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + .thumb_func +_start: + bl bar + +@ We will place the section .foo at 0x2014. + + .section .foo, "xa" + + .arm + .type bar, %function +bar: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm.d new file mode 100644 index 0000000..5dc377a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm.d @@ -0,0 +1,25 @@ +.*: file format .* + +Disassembly of section .text: + +01c01010 <_start>: + 1c01010: f300 f802 bl 1f01018 <__bar_from_thumb> + \.\.\. + 1f01014: f000 f806 bl 1f01024 <__bar_from_thumb> + +01f01018 <__bar_from_thumb>: + 1f01018: 4778 bx pc + 1f0101a: 46c0 nop ; \(mov r8, r8\) + 1f0101c: e51ff004 ldr pc, \[pc, #-4\] ; 1f01020 <__bar_from_thumb\+0x8> + 1f01020: 02001014 .word 0x02001014 + +01f01024 <__bar_from_thumb>: + 1f01024: 4778 bx pc + 1f01026: 46c0 nop ; \(mov r8, r8\) + 1f01028: ea03fff9 b 2001014 <bar> + 1f0102c: 00000000 andeq r0, r0, r0 + +Disassembly of section .foo: + +02001014 <bar>: + 2001014: e12fff1e bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm.s new file mode 100644 index 0000000..1fd6a07 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-arm.s @@ -0,0 +1,27 @@ +@ Test to ensure that a Thumb to ARM call exceeding 4Mb generates a stub. +@ Check that we can generate two types of stub in the same section. + + .global _start + .syntax unified + +@ We will place the section .text at 0x1c01010. + + .text + .thumb_func +_start: + .global bar + bl bar +@ This call is close enough to generate a "short branch" stub +@ or no stub if blx is available. + .space 0x0300000 + bl bar + +@ We will place the section .foo at 0x2001014. + + .section .foo, "xa" + + .arm + .type bar, %function +bar: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d new file mode 100644 index 0000000..27b208e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d @@ -0,0 +1,18 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: f000 e802 blx 1008 <__bar_veneer> + 1004: 0000 movs r0, r0 + \.\.\. + +00001008 <__bar_veneer>: + 1008: e59fc004 ldr ip, \[pc, #4\] ; 1014 <__bar_veneer\+0xc> + 100c: e08fc00c add ip, pc, ip + 1010: e12fff1c bx ip + 1014: 02000001 .word 0x02000001 +Disassembly of section .foo: + +02001014 <bar>: + 2001014: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d new file mode 100644 index 0000000..7998746 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d @@ -0,0 +1,16 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: f000 e802 blx 1008 <__bar_veneer> + 1004: 0000 movs r0, r0 + \.\.\. + +00001008 <__bar_veneer>: + 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_veneer\+0x4> + 100c: 02001015 .word 0x02001015 +Disassembly of section .foo: + +02001014 <bar>: + 2001014: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d new file mode 100644 index 0000000..974c1e9 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d @@ -0,0 +1,22 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: f000 f802 bl 1008 <__bar_veneer> + 1004: 0000 movs r0, r0 + ... + +00001008 <__bar_veneer>: + 1008: b401 push {r0} + 100a: 4802 ldr r0, \[pc, #8\] ; \(1014 <__bar_veneer\+0xc>\) + 100c: 46fc mov ip, pc + 100e: 4484 add ip, r0 + 1010: bc01 pop {r0} + 1012: 4760 bx ip + 1014: 02000005 .word 0x02000005 + +Disassembly of section .foo: + +02001014 <bar>: + 2001014: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb-m.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb-m.d new file mode 100644 index 0000000..e63b3f8 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb-m.d @@ -0,0 +1,21 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: f000 f802 bl 1008 <__bar_veneer> + 1004: 0000 movs r0, r0 + \.\.\. + +00001008 <__bar_veneer>: + 1008: b401 push {r0} + 100a: 4802 ldr r0, \[pc, #8\] ; \(1014 <__bar_veneer\+0xc>\) + 100c: 4684 mov ip, r0 + 100e: bc01 pop {r0} + 1010: 4760 bx ip + 1012: bf00 nop + 1014: 02001015 .word 0x02001015 +Disassembly of section .foo: + +02001014 <bar>: + 2001014: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d new file mode 100644 index 0000000..8b14599 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d @@ -0,0 +1,22 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: f000 f802 bl 1008 <__bar_veneer> + 1004: 0000 movs r0, r0 + ... + +00001008 <__bar_veneer>: + 1008: 4778 bx pc + 100a: 46c0 nop ; \(mov r8, r8\) + 100c: e59fc004 ldr ip, \[pc, #4\] ; 1018 <__bar_veneer\+0x10> + 1010: e08fc00c add ip, pc, ip + 1014: e12fff1c bx ip + 1018: 01fffffd .word 0x01fffffd + 101c: 00000000 .word 0x00000000 + +Disassembly of section .foo: + +02001014 <bar>: + 2001014: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb.d b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb.d new file mode 100644 index 0000000..ffbc6df --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb.d @@ -0,0 +1,19 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: f000 f802 bl 1008 <__bar_veneer> + 1004: 0000 movs r0, r0 + \.\.\. + +00001008 <__bar_veneer>: + 1008: 4778 bx pc + 100a: 46c0 nop ; \(mov r8, r8\) + 100c: e59fc000 ldr ip, \[pc, #0\] ; 1014 <__bar_veneer\+0xc> + 1010: e12fff1c bx ip + 1014: 02001015 .word 0x02001015 +Disassembly of section .foo: + +02001014 <bar>: + 2001014: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb.s b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb.s new file mode 100644 index 0000000..650b1a6 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/farcall-thumb-thumb.s @@ -0,0 +1,19 @@ +@ Test to ensure that a Thumb to Thumb call exceeding 4Mb generates a stub. + + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + .thumb_func +_start: + bl bar + +@ We will place the section .foo at 0x02001014. + + .section .foo, "xa" + .thumb_func +bar: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/gc-unwind.d b/binutils-2.21/ld/testsuite/ld-arm/gc-unwind.d new file mode 100644 index 0000000..fbb7911 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/gc-unwind.d @@ -0,0 +1,5 @@ + +.*: file format.* + +Contents of section .data: + [^ ]* 22222222 .* diff --git a/binutils-2.21/ld/testsuite/ld-arm/gc-unwind.s b/binutils-2.21/ld/testsuite/ld-arm/gc-unwind.s new file mode 100644 index 0000000..c5326c2 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/gc-unwind.s @@ -0,0 +1,38 @@ +@ Test -gc-sections and unwinding tables. .data.eh should be pulled in +@ via the EH tables, .data.foo should not. +.text +.global _start +.fnstart +_start: +bx lr +.personality my_pr +.handlerdata +.word 0 +.fnend + +.section .data.foo +my_foo: +.word 0x11111111 + +.section .text.foo +.fnstart +foo: +bx lr +.personality my_pr +.handlerdata +.word my_foo +.fnend + +.section .data.eh +my_eh: +.word 0x22222222 + +.section .text.eh +.fnstart +my_pr: +bx lr +.personality my_pr +.handlerdata +.word my_eh +.fnend + diff --git a/binutils-2.21/ld/testsuite/ld-arm/group-relocs-alu-bad.d b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-alu-bad.d new file mode 100644 index 0000000..0346db1 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-alu-bad.d @@ -0,0 +1,4 @@ +#name: ALU group relocations failure test +#source: group-relocs-alu-bad.s +#ld: -Ttext 0x8000 --section-start foo=0x9010 +#error: Overflow whilst splitting 0x1010 for group relocation diff --git a/binutils-2.21/ld/testsuite/ld-arm/group-relocs-alu-bad.s b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-alu-bad.s new file mode 100644 index 0000000..e644669 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-alu-bad.s @@ -0,0 +1,20 @@ +@ Test intended to fail for ALU group relocations. +@ +@ Beware when editing this file: it is carefully crafted so that +@ a specific PC-relative offset arises. + +@ We will place .text at 0x8000. + + .text + .globl _start + +_start: + add r0, r0, #:pc_g0:(bar) + +@ We will place the section foo at 0x9004. + + .section foo + +bar: + mov r0, #0 + diff --git a/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldc-bad.d b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldc-bad.d new file mode 100644 index 0000000..d4bfb2d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldc-bad.d @@ -0,0 +1,4 @@ +#name: LDC group relocations failure test +#source: group-relocs-ldc-bad.s +#ld: -Ttext 0x8000 --section-start foo=0x118400 +#error: Overflow whilst splitting 0x110400 for group relocation diff --git a/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldc-bad.s b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldc-bad.s new file mode 100644 index 0000000..611255b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldc-bad.s @@ -0,0 +1,19 @@ +@ Test intended to fail for LDC group relocations. + +@ We will place .text at 0x8000. + + .text + .globl _start + +_start: + add r0, r0, #:pc_g0_nc:(bar) + ldc 0, c0, [r0, #:pc_g1:(bar + 4)] + +@ We will place the section foo at 0x118400. +@ (The relocations above would be OK if it were at 0x118200, for example.) + + .section foo + +bar: + mov r0, #0 + diff --git a/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldr-bad.d b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldr-bad.d new file mode 100644 index 0000000..04586af --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldr-bad.d @@ -0,0 +1,4 @@ +#name: LDR group relocations failure test +#source: group-relocs-ldr-bad.s +#ld: -Ttext 0x8000 --section-start foo=0x8001000 +#error: .*Overflow whilst splitting 0x8001000 for group relocation.* diff --git a/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldr-bad.s b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldr-bad.s new file mode 100644 index 0000000..6ab4f3c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldr-bad.s @@ -0,0 +1,18 @@ +@ Test intended to fail for LDR group relocations. + +@ We will place .text at 0x8000. + + .text + .globl _start + +_start: + add r0, r0, #:sb_g0_nc:(bar) + ldr r1, [r0, #:sb_g1:(bar)] + +@ We will place the section foo at 0x8001000. + + .section foo + +bar: + mov r0, #0 + diff --git a/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldrs-bad.d b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldrs-bad.d new file mode 100644 index 0000000..0520184 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldrs-bad.d @@ -0,0 +1,4 @@ +#name: LDRS group relocations failure test +#source: group-relocs-ldrs-bad.s +#ld: -Ttext 0x8000 --section-start foo=0x8000100 +#error: Overflow whilst splitting 0x8000100 for group relocation diff --git a/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldrs-bad.s b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldrs-bad.s new file mode 100644 index 0000000..4480d4a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/group-relocs-ldrs-bad.s @@ -0,0 +1,17 @@ +@ Test intended to fail for LDRS group relocations. + +@ We will place .text at 0x8000. + + .text + .globl _start + +_start: + add r0, r0, #:sb_g0_nc:(bar) + ldrd r2, [r0, #:sb_g1:(bar)] + +@ We will place the section foo at 0x8000100. + + .section foo + +bar: + mov r0, #0 diff --git a/binutils-2.21/ld/testsuite/ld-arm/group-relocs.d b/binutils-2.21/ld/testsuite/ld-arm/group-relocs.d new file mode 100644 index 0000000..e81739d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/group-relocs.d @@ -0,0 +1,69 @@ + +tmpdir/group-relocs: file format elf32-(little|big)arm + +Disassembly of section .text: + +00008000 <_start>: + 8000: e28f00bc add r0, pc, #188 ; 0xbc + 8004: e28f0c6e add r0, pc, #28160 ; 0x6e00 + 8008: e28000ec add r0, r0, #236 ; 0xec + 800c: e28f08ff add r0, pc, #16711680 ; 0xff0000 + 8010: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8014: e28000e4 add r0, r0, #228 ; 0xe4 + 8018: e2800000 add r0, r0, #0 + 801c: e28f0cee add r0, pc, #60928 ; 0xee00 + 8020: e28000f0 add r0, r0, #240 ; 0xf0 + 8024: e28008ff add r0, r0, #16711680 ; 0xff0000 + 8028: e2800cee add r0, r0, #60928 ; 0xee00 + 802c: e28000f0 add r0, r0, #240 ; 0xf0 + 8030: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8034: e59010c0 ldr r1, \[r0, #192\].* + 8038: e28008ff add r0, r0, #16711680 ; 0xff0000 + 803c: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8040: e59010b8 ldr r1, \[r0, #184\].* + 8044: e5901000 ldr r1, \[r0\] + 8048: e2800cee add r0, r0, #60928 ; 0xee00 + 804c: e59010f0 ldr r1, \[r0, #240\].* + 8050: e28008ff add r0, r0, #16711680 ; 0xff0000 + 8054: e2800cee add r0, r0, #60928 ; 0xee00 + 8058: e59010f0 ldr r1, \[r0, #240\].* + 805c: e1c026d0 ldrd r2, \[r0, #96\].* + 8060: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8064: e1c029d0 ldrd r2, \[r0, #144\].* + 8068: e28008ff add r0, r0, #16711680 ; 0xff0000 + 806c: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8070: e1c028d8 ldrd r2, \[r0, #136\].* + 8074: e1c020d0 ldrd r2, \[r0\] + 8078: e2800cee add r0, r0, #60928 ; 0xee00 + 807c: e1c02fd0 ldrd r2, \[r0, #240\].* + 8080: e28008ff add r0, r0, #16711680 ; 0xff0000 + 8084: e2800cee add r0, r0, #60928 ; 0xee00 + 8088: e1c02fd0 ldrd r2, \[r0, #240\].* + 808c: ed90000c ldc 0, cr0, \[r0, #48\].* + 8090: e2800c6e add r0, r0, #28160 ; 0x6e00 + 8094: ed900018 ldc 0, cr0, \[r0, #96\].* + 8098: e28008ff add r0, r0, #16711680 ; 0xff0000 + 809c: e2800c6e add r0, r0, #28160 ; 0x6e00 + 80a0: ed900016 ldc 0, cr0, \[r0, #88\].* + 80a4: ed900000 ldc 0, cr0, \[r0\] + 80a8: e2800cee add r0, r0, #60928 ; 0xee00 + 80ac: ed90003c ldc 0, cr0, \[r0, #240\].* + 80b0: e28008ff add r0, r0, #16711680 ; 0xff0000 + 80b4: e2800cee add r0, r0, #60928 ; 0xee00 + 80b8: ed90003c ldc 0, cr0, \[r0, #240\].* + +000080bc <one_group_needed_alu_pc>: + 80bc: e3a00000 mov r0, #0 +Disassembly of section zero: + +00000000 <one_group_needed_alu_sb>: + 0: e3a00000 mov r0, #0 +Disassembly of section alpha: + +0000eef0 <two_groups_needed_alu_pc>: + eef0: e3a00000 mov r0, #0 +Disassembly of section beta: + +00ffeef0 <three_groups_needed_alu_pc>: + ffeef0: e3a00000 mov r0, #0 +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/group-relocs.s b/binutils-2.21/ld/testsuite/ld-arm/group-relocs.s new file mode 100644 index 0000000..b6467f4 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/group-relocs.s @@ -0,0 +1,156 @@ +@ Tests for group relocations. +@ +@ Beware when editing this file: it is carefully crafted so that +@ specific PC- and SB-relative offsets arise. +@ +@ Note that the gas tests have already checked that group relocations are +@ handled in the same way for local and external symbols. + +@ We will place .text at 0x8000. + + .text + .globl _start + +_start: + @ ALU, PC-relative + + @ Instructions start at .text + 0x0 + add r0, r15, #:pc_g0:(one_group_needed_alu_pc) + + @ Instructions start at .text + 0x4 + add r0, r15, #:pc_g0_nc:(two_groups_needed_alu_pc) + add r0, r0, #:pc_g1:(two_groups_needed_alu_pc + 4) + + @ Instructions start at .text + 0xc + add r0, r15, #:pc_g0_nc:(three_groups_needed_alu_pc) + add r0, r0, #:pc_g1_nc:(three_groups_needed_alu_pc + 4) + add r0, r0, #:pc_g2:(three_groups_needed_alu_pc + 8) + + @ ALU, SB-relative + + add r0, r0, #:sb_g0:(one_group_needed_alu_sb) + + add r0, r15, #:sb_g0_nc:(two_groups_needed_alu_sb) + add r0, r0, #:sb_g1:(two_groups_needed_alu_sb) + + add r0, r0, #:sb_g0_nc:(three_groups_needed_alu_sb) + add r0, r0, #:sb_g1_nc:(three_groups_needed_alu_sb) + add r0, r0, #:sb_g2:(three_groups_needed_alu_sb) + + @ LDR, PC-relative + + @ Instructions start at .text + 0x30 + add r0, r0, #:pc_g0_nc:(two_groups_needed_ldr_pc) + ldr r1, [r0, #:pc_g1:(two_groups_needed_ldr_pc + 4)] + + @ Instructions start at .text + 0x38 + add r0, r0, #:pc_g0_nc:(three_groups_needed_ldr_pc) + add r0, r0, #:pc_g1_nc:(three_groups_needed_ldr_pc + 4) + ldr r1, [r0, #:pc_g2:(three_groups_needed_ldr_pc + 8)] + + @ LDR, SB-relative + + ldr r1, [r0, #:sb_g0:(one_group_needed_ldr_sb)] + + add r0, r0, #:sb_g0_nc:(two_groups_needed_ldr_sb) + ldr r1, [r0, #:sb_g1:(two_groups_needed_ldr_sb)] + + add r0, r0, #:sb_g0_nc:(three_groups_needed_ldr_sb) + add r0, r0, #:sb_g1_nc:(three_groups_needed_ldr_sb) + ldr r1, [r0, #:sb_g2:(three_groups_needed_ldr_sb)] + + @ LDRS, PC-relative + + @ Instructions start at .text + 0x5c + ldrd r2, [r0, #:pc_g0:(one_group_needed_ldrs_pc)] + + @ Instructions start at .text + 0x60 + add r0, r0, #:pc_g0_nc:(two_groups_needed_ldrs_pc) + ldrd r2, [r0, #:pc_g1:(two_groups_needed_ldrs_pc + 4)] + + @ Instructions start at .text + 0x68 + add r0, r0, #:pc_g0_nc:(three_groups_needed_ldrs_pc) + add r0, r0, #:pc_g1_nc:(three_groups_needed_ldrs_pc + 4) + ldrd r2, [r0, #:pc_g2:(three_groups_needed_ldrs_pc + 8)] + + @ LDRS, SB-relative + + ldrd r2, [r0, #:sb_g0:(one_group_needed_ldrs_sb)] + + add r0, r0, #:sb_g0_nc:(two_groups_needed_ldrs_sb) + ldrd r2, [r0, #:sb_g1:(two_groups_needed_ldrs_sb)] + + add r0, r0, #:sb_g0_nc:(three_groups_needed_ldrs_sb) + add r0, r0, #:sb_g1_nc:(three_groups_needed_ldrs_sb) + ldrd r2, [r0, #:sb_g2:(three_groups_needed_ldrs_sb)] + + @ LDC, PC-relative + + @ Instructions start at .text + 0x8c + ldc 0, c0, [r0, #:pc_g0:(one_group_needed_ldc_pc)] + + @ Instructions start at .text + 0x90 + add r0, r0, #:pc_g0_nc:(two_groups_needed_ldc_pc) + ldc 0, c0, [r0, #:pc_g1:(two_groups_needed_ldc_pc + 4)] + + @ Instructions start at .text + 0x98 + add r0, r0, #:pc_g0_nc:(three_groups_needed_ldc_pc) + add r0, r0, #:pc_g1_nc:(three_groups_needed_ldc_pc + 4) + ldc 0, c0, [r0, #:pc_g2:(three_groups_needed_ldc_pc + 8)] + + @ LDC, SB-relative + + ldc 0, c0, [r0, #:sb_g0:(one_group_needed_ldc_sb)] + + add r0, r0, #:sb_g0_nc:(two_groups_needed_ldc_sb) + ldc 0, c0, [r0, #:sb_g1:(two_groups_needed_ldc_sb)] + + add r0, r0, #:sb_g0_nc:(three_groups_needed_ldc_sb) + add r0, r0, #:sb_g1_nc:(three_groups_needed_ldc_sb) + ldc 0, c0, [r0, #:sb_g2:(three_groups_needed_ldc_sb)] + +@ This point in the file is .text + 0xbc. + +one_group_needed_alu_pc: +one_group_needed_ldrs_pc: +one_group_needed_ldc_pc: + mov r0, #0 + +@ We will place the section zero at 0x0. + + .section zero, "x" + +one_group_needed_alu_sb: +one_group_needed_ldr_sb: +one_group_needed_ldrs_sb: +one_group_needed_ldc_sb: + mov r0, #0 + +@ We will place the section alpha at 0xeef0. + + .section alpha, "x" + +two_groups_needed_alu_sb: +two_groups_needed_ldr_sb: +two_groups_needed_ldrs_sb: +two_groups_needed_ldc_sb: +two_groups_needed_alu_pc: +two_groups_needed_ldr_pc: +two_groups_needed_ldrs_pc: +two_groups_needed_ldc_pc: + mov r0, #0 + +@ We will place the section beta at 0xffeef0. + + .section beta, "x" + +three_groups_needed_alu_sb: +three_groups_needed_ldr_sb: +three_groups_needed_ldrs_sb: +three_groups_needed_ldc_sb: +three_groups_needed_alu_pc: +three_groups_needed_ldr_pc: +three_groups_needed_ldrs_pc: +three_groups_needed_ldc_pc: + mov r0, #0 + diff --git a/binutils-2.21/ld/testsuite/ld-arm/jump-reloc-veneers-long.d b/binutils-2.21/ld/testsuite/ld-arm/jump-reloc-veneers-long.d new file mode 100644 index 0000000..0dba9ec --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/jump-reloc-veneers-long.d @@ -0,0 +1,21 @@ + +.*: file format.* + + +Disassembly of section destsect: + +09000000 <[^>]*>: + 9000000: e7fe b.n 9000000 <dest> + +Disassembly of section .text: + +000080.. <[^>]*>: + 80..: b802f000 .word 0xb802f000 + 80..: 00000000 andeq r0, r0, r0 + +000080.. <[^>]*>: + 80..: 4778 bx pc + 80..: 46c0 nop ; \(mov r8, r8\) + 80..: e59fc000 ldr ip, \[pc, #0\] ; 80.. <__dest_veneer\+0xc> + 80..: e12fff1c bx ip + 80..: 09000001 .word 0x09000001 diff --git a/binutils-2.21/ld/testsuite/ld-arm/jump-reloc-veneers-short1.d b/binutils-2.21/ld/testsuite/ld-arm/jump-reloc-veneers-short1.d new file mode 100644 index 0000000..3796652 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/jump-reloc-veneers-short1.d @@ -0,0 +1,13 @@ + +.*: file format.* + + +Disassembly of section destsect: + +00009000 <[^>]*>: + 9000: e7fe b.n 9000 <dest> + +Disassembly of section .text: + +000080.. <[^>]*>: + 80..: f000 bf.. b.w 9000 <dest> diff --git a/binutils-2.21/ld/testsuite/ld-arm/jump-reloc-veneers-short2.d b/binutils-2.21/ld/testsuite/ld-arm/jump-reloc-veneers-short2.d new file mode 100644 index 0000000..22fa6df --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/jump-reloc-veneers-short2.d @@ -0,0 +1,13 @@ + +.*: file format.* + + +Disassembly of section destsect: + +00900000 <[^>]*>: + 900000: e7fe b.n 900000 <dest> + +Disassembly of section .text: + +000080.. <[^>]*>: + 80..: f0f7 9f.. b.w 900000 <dest> diff --git a/binutils-2.21/ld/testsuite/ld-arm/jump-reloc-veneers.s b/binutils-2.21/ld/testsuite/ld-arm/jump-reloc-veneers.s new file mode 100644 index 0000000..d307c08 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/jump-reloc-veneers.s @@ -0,0 +1,12 @@ + .text + .syntax unified + .thumb_func + .global _start + .type _start,%function +_start: + b.w dest + + .section destsect, "x" + .thumb_func +dest: + b dest diff --git a/binutils-2.21/ld/testsuite/ld-arm/jump19.d b/binutils-2.21/ld/testsuite/ld-arm/jump19.d new file mode 100644 index 0000000..303477f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/jump19.d @@ -0,0 +1,12 @@ + +.*jump19: file format elf32-(big|little)arm + +Disassembly of section .text: + +00008000 <_start>: + 8000: 4280 cmp r0, r0 + 8002: f010 8000 beq.w 18006 <bar> + ... + +00018006 <bar>: + 18006: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/jump19.s b/binutils-2.21/ld/testsuite/ld-arm/jump19.s new file mode 100644 index 0000000..1e3ddf0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/jump19.s @@ -0,0 +1,12 @@ +@ Test the Thumb-2 JUMP19 relocation. + + .syntax unified + .thumb + .global _start +_start: + cmp r0, r0 + beq.w bar + .space 65536 + .weak bar +bar: + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/mixed-app-v5.d b/binutils-2.21/ld/testsuite/ld-arm/mixed-app-v5.d new file mode 100644 index 0000000..a30fde4 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/mixed-app-v5.d @@ -0,0 +1,56 @@ + +tmpdir/mixed-app-v5: file format elf32-(little|big)arm +architecture: arm, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x.* + +Disassembly of section .plt: + +.* <.plt>: + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x28> + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* +Disassembly of section .text: + +.* <_start>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: eb000004 bl .* <app_func> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + +.* <app_func>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: ebffffee bl .* + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + +.* <app_func2>: + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + +.* <app_tfunc>: + .*: b500 push {lr} + .*: f7ff efc. blx .* <_start-0x..> + .*: bd00 pop {pc} + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) diff --git a/binutils-2.21/ld/testsuite/ld-arm/mixed-app.d b/binutils-2.21/ld/testsuite/ld-arm/mixed-app.d new file mode 100644 index 0000000..592e18a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/mixed-app.d @@ -0,0 +1,58 @@ + +tmpdir/mixed-app: file format elf32-(little|big)arm +architecture: arm, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x.* + +Disassembly of section .plt: + +.* <.plt>: + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x28> + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* +Disassembly of section .text: + +.* <_start>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: eb000004 bl .* <app_func> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + +.* <app_func>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: ebffff.. bl .* + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + +.* <app_func2>: + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + +.* <app_tfunc>: + .*: b500 push {lr} + .*: f7ff ffc. bl .* <_start-0x..> + .*: bd00 pop {pc} + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) diff --git a/binutils-2.21/ld/testsuite/ld-arm/mixed-app.r b/binutils-2.21/ld/testsuite/ld-arm/mixed-app.r new file mode 100644 index 0000000..648e92f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/mixed-app.r @@ -0,0 +1,10 @@ + +tmpdir/mixed-app.*: file format elf32-(little|big)arm + +DYNAMIC RELOCATION RECORDS +OFFSET TYPE VALUE +.* R_ARM_COPY data_obj +.* R_ARM_JUMP_SLOT lib_func2 +.* R_ARM_JUMP_SLOT lib_func1 + + diff --git a/binutils-2.21/ld/testsuite/ld-arm/mixed-app.s b/binutils-2.21/ld/testsuite/ld-arm/mixed-app.s new file mode 100644 index 0000000..ce82487 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/mixed-app.s @@ -0,0 +1,39 @@ + .text + .p2align 4 + .globl _start +_start: + mov ip, sp + stmdb sp!, {r11, ip, lr, pc} + bl app_func + ldmia sp, {r11, sp, lr} + bx lr + + .p2align 4 + .globl app_func + .type app_func,%function +app_func: + mov ip, sp + stmdb sp!, {r11, ip, lr, pc} + bl lib_func1 + ldmia sp, {r11, sp, lr} + bx lr + + .p2align 4 + .globl app_func2 + .type app_func2,%function +app_func2: + bx lr + + .p2align 4 + .globl app_tfunc + .type app_tfunc,%function + .thumb_func + .code 16 +app_tfunc: + push {lr} + bl lib_func2 + pop {pc} + bx lr + + .data + .long data_obj diff --git a/binutils-2.21/ld/testsuite/ld-arm/mixed-app.sym b/binutils-2.21/ld/testsuite/ld-arm/mixed-app.sym new file mode 100644 index 0000000..2884b3d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/mixed-app.sym @@ -0,0 +1,15 @@ + +Symbol table for image: + +Num +Buc: +Value +Size +Type +Bind +Vis +Ndx +Name + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS _edata + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_start__ + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS _end + +.. +..: ........ +4 +OBJECT +GLOBAL +DEFAULT +12 data_obj + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_end__ + +.. +..: 0*[^0]*.* +0 +FUNC +GLOBAL +DEFAULT +UND lib_func1 + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +11 __data_start + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __end__ + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_start + +.. +..: .......0 +0 +FUNC +GLOBAL +DEFAULT +8 app_func2 + +.. +..: 0*[^0]*.* +0 +FUNC +GLOBAL +DEFAULT +UND lib_func2 + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS _bss_end__ diff --git a/binutils-2.21/ld/testsuite/ld-arm/mixed-lib.d b/binutils-2.21/ld/testsuite/ld-arm/mixed-lib.d new file mode 100644 index 0000000..bcd2e41 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/mixed-lib.d @@ -0,0 +1,38 @@ + +tmpdir/mixed-lib.so: file format elf32-(little|big)arm +architecture: arm, flags 0x00000150: +HAS_SYMS, DYNAMIC, D_PAGED +start address 0x.* + +Disassembly of section .plt: + +.* <.plt>: + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1-0x.*> + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* +Disassembly of section .text: + +.* <lib_func1>: + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: ebfffff. bl .* <lib_func1-0x..?> + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + +.* <lib_func2>: + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) + .*: 46c0 nop ; \(mov r8, r8\) diff --git a/binutils-2.21/ld/testsuite/ld-arm/mixed-lib.r b/binutils-2.21/ld/testsuite/ld-arm/mixed-lib.r new file mode 100644 index 0000000..0137880 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/mixed-lib.r @@ -0,0 +1,8 @@ + +tmpdir/mixed-lib.so: file format elf32-(little|big)arm + +DYNAMIC RELOCATION RECORDS +OFFSET TYPE VALUE +.* R_ARM_JUMP_SLOT app_func2 + + diff --git a/binutils-2.21/ld/testsuite/ld-arm/mixed-lib.s b/binutils-2.21/ld/testsuite/ld-arm/mixed-lib.s new file mode 100644 index 0000000..86f5ace --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/mixed-lib.s @@ -0,0 +1,28 @@ + .text + + .p2align 4 + .globl lib_func1 + .type lib_func1, %function +lib_func1: + mov ip, sp + stmdb sp!, {r11, ip, lr, pc} + bl app_func2 + ldmia sp, {r11, sp, lr} + bx lr + .size lib_func1, . - lib_func1 + + .p2align 4 + .globl lib_func2 + .type lib_func2, %function + .thumb_func + .code 16 +lib_func2: + bx lr + .size lib_func2, . - lib_func2 + + .data + .globl data_obj + .type data_obj, %object +data_obj: + .long 0 + .size data_obj, . - data_obj diff --git a/binutils-2.21/ld/testsuite/ld-arm/mixed-lib.sym b/binutils-2.21/ld/testsuite/ld-arm/mixed-lib.sym new file mode 100644 index 0000000..9f7a326 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/mixed-lib.sym @@ -0,0 +1,15 @@ + +Symbol table for image: + +Num +Buc: +Value +Size +Type +Bind +Vis +Ndx +Name + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS _edata + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_start__ + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS _end + +.. +..: ........ +4 +OBJECT +GLOBAL +DEFAULT +9 data_obj + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_end__ + +.. +..: .......0 +20 +FUNC +GLOBAL +DEFAULT +6 lib_func1 + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +9 __data_start + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __end__ + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_start + +.. +..: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND app_func2 + +.. +..: .......1 +2 +FUNC +GLOBAL +DEFAULT +6 lib_func2 + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS _bss_end__ diff --git a/binutils-2.21/ld/testsuite/ld-arm/movw-merge.d b/binutils-2.21/ld/testsuite/ld-arm/movw-merge.d new file mode 100644 index 0000000..40e1681 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/movw-merge.d @@ -0,0 +1,13 @@ + +.*: file format.* + +Disassembly of section .text: + +00008000 <[^>]*>: + 8000: e3080013 movw r0, #32787 ; 0x8013 + 8004: e3400000 movt r0, #0 + +00008008 <[^>]*>: + 8008: f248 0013 movw r0, #32787 ; 0x8013 + 800c: f2c0 0000 movt r0, #0 + diff --git a/binutils-2.21/ld/testsuite/ld-arm/movw-merge.s b/binutils-2.21/ld/testsuite/ld-arm/movw-merge.s new file mode 100644 index 0000000..17c70a5 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/movw-merge.s @@ -0,0 +1,20 @@ + .arch armv7-a + .syntax unified + .text + .global _start + .type _start, %function +_start: + movw r0, #:lower16:.LC0 + movt r0, #:upper16:.LC0 + .thumb + .global tfunc + .type tfunc, %function +tfunc: + movw r0, #:lower16:.LC0 + movt r0, #:upper16:.LC0 + + .section .rodata.str1.4,"aMS",%progbits,1 + .align 2 + .ascii "pad" +.LC0: + .ascii "inner: cont \000" diff --git a/binutils-2.21/ld/testsuite/ld-arm/movw-shared-1.d b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-1.d new file mode 100644 index 0000000..5a05818 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-1.d @@ -0,0 +1,4 @@ +#name: MOVW/MOVT shared libraries test 1 +#source: movw-shared-1.s +#ld: -shared +#error: .*: relocation R_ARM_MOVW_ABS_NC against `a' can not be used when making a shared object; recompile with -fPIC diff --git a/binutils-2.21/ld/testsuite/ld-arm/movw-shared-1.s b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-1.s new file mode 100644 index 0000000..512946a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-1.s @@ -0,0 +1,5 @@ +.arch armv7-a +.text +.syntax unified +f: +movw r0, #:lower16:a diff --git a/binutils-2.21/ld/testsuite/ld-arm/movw-shared-2.d b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-2.d new file mode 100644 index 0000000..08ceaf0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-2.d @@ -0,0 +1,4 @@ +#name: MOVW/MOVT shared libraries test 2 +#source: movw-shared-2.s +#ld: -shared +#error: .*: relocation R_ARM_MOVT_ABS against `b' can not be used when making a shared object; recompile with -fPIC diff --git a/binutils-2.21/ld/testsuite/ld-arm/movw-shared-2.s b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-2.s new file mode 100644 index 0000000..bd70b76 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-2.s @@ -0,0 +1,5 @@ +.arch armv7-a +.text +.syntax unified +f: +movt r0, #:upper16:b diff --git a/binutils-2.21/ld/testsuite/ld-arm/movw-shared-3.d b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-3.d new file mode 100644 index 0000000..90b9cf1 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-3.d @@ -0,0 +1,4 @@ +#name: MOVW/MOVT shared libraries test 3 +#source: movw-shared-3.s +#ld: -shared +#error: .*: relocation R_ARM_THM_MOVW_ABS_NC against `c' can not be used when making a shared object; recompile with -fPIC diff --git a/binutils-2.21/ld/testsuite/ld-arm/movw-shared-3.s b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-3.s new file mode 100644 index 0000000..a4db9a9 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-3.s @@ -0,0 +1,6 @@ +.arch armv7-a +.text +.syntax unified +f: +.thumb +movw r0, #:lower16:c diff --git a/binutils-2.21/ld/testsuite/ld-arm/movw-shared-4.d b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-4.d new file mode 100644 index 0000000..cc7a418 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-4.d @@ -0,0 +1,4 @@ +#name: MOVW/MOVT shared libraries test 4 +#source: movw-shared-4.s +#ld: -shared +#error: .*: relocation R_ARM_THM_MOVT_ABS against `d' can not be used when making a shared object; recompile with -fPIC diff --git a/binutils-2.21/ld/testsuite/ld-arm/movw-shared-4.s b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-4.s new file mode 100644 index 0000000..09f2952 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/movw-shared-4.s @@ -0,0 +1,6 @@ +.arch armv7-a +.text +.syntax unified +f: +.thumb +movt r0, #:upper16:d diff --git a/binutils-2.21/ld/testsuite/ld-arm/preempt-app.s b/binutils-2.21/ld/testsuite/ld-arm/preempt-app.s new file mode 100644 index 0000000..f1eccc2 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/preempt-app.s @@ -0,0 +1,27 @@ + @ Preempt an ARM shared library function with a Thumb function + @ in the application. + .text + .p2align 4 + .globl _start +_start: + mov ip, sp + stmdb sp!, {r11, ip, lr, pc} + bl lib_func1 + ldmia sp, {r11, sp, lr} + bx lr + + .p2align 4 + .globl app_func2 + .type app_func2,%function +app_func2: + bx lr + + .p2align 4 + .globl lib_func1 + .type lib_func1,%function + .thumb_func +lib_func1: + bx lr + + .data + .long data_obj diff --git a/binutils-2.21/ld/testsuite/ld-arm/preempt-app.sym b/binutils-2.21/ld/testsuite/ld-arm/preempt-app.sym new file mode 100644 index 0000000..c169757 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/preempt-app.sym @@ -0,0 +1,14 @@ + +Symbol table for image: + +Num +Buc: +Value +Size +Type +Bind +Vis +Ndx +Name + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS _edata + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_start__ + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS _end + +.. +..: ........ +4 +OBJECT +GLOBAL +DEFAULT +10 data_obj + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_end__ + +.. +..: .......1 +20 +FUNC +GLOBAL +DEFAULT +6 lib_func1 + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +9 __data_start + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __end__ + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS __bss_start + +.. +..: .......0 +0 +FUNC +GLOBAL +DEFAULT +6 app_func2 + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +ABS _bss_end__ diff --git a/binutils-2.21/ld/testsuite/ld-arm/reloc-boundaries.d b/binutils-2.21/ld/testsuite/ld-arm/reloc-boundaries.d new file mode 100644 index 0000000..bcc13d0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/reloc-boundaries.d @@ -0,0 +1,6 @@ + +[^:]*: file format elf32-(little|big)arm + +Contents of section .text: + 80.. 80ff0080 ffff ...... +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/reloc-boundaries.s b/binutils-2.21/ld/testsuite/ld-arm/reloc-boundaries.s new file mode 100644 index 0000000..7e65bc0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/reloc-boundaries.s @@ -0,0 +1,5 @@ +.syntax unified + .byte x -128 + .byte x +255 + .short y -32768 + .short y +65535 diff --git a/binutils-2.21/ld/testsuite/ld-arm/script-type.ld b/binutils-2.21/ld/testsuite/ld-arm/script-type.ld new file mode 100644 index 0000000..01995eb --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/script-type.ld @@ -0,0 +1,9 @@ +SECTIONS { + .text : { + foo_a = bar_a; + foo_t = bar_t; + foo_o = bar_o; + *(.text) + } + .ARM.attribues 0 : { *(.ARM.attributes) } +} diff --git a/binutils-2.21/ld/testsuite/ld-arm/script-type.s b/binutils-2.21/ld/testsuite/ld-arm/script-type.s new file mode 100644 index 0000000..f9d41e8 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/script-type.s @@ -0,0 +1,20 @@ +.syntax unified +.text +.global bar_a +.type bar_a %function +bar_a: +bx lr + +.p2align 4 +.global bar_o +.type bar_o %object +bar_o: +.word 0 + +.p2align 4 +.thumb +.global bar_t +.type bar_t %function +bar_t: +bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/script-type.sym b/binutils-2.21/ld/testsuite/ld-arm/script-type.sym new file mode 100644 index 0000000..d319d5c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/script-type.sym @@ -0,0 +1,16 @@ + +Symbol table '.symtab' contains 13 entries: + Num: Value Size Type Bind Vis Ndx Name + 0: 00000000 0 NOTYPE LOCAL DEFAULT UND + 1: 00000000 0 SECTION LOCAL DEFAULT 1 + 2: 00000000 0 SECTION LOCAL DEFAULT 2 + 3: 00000000 0 NOTYPE LOCAL DEFAULT 1 \$a + 4: 00000010 0 NOTYPE LOCAL DEFAULT 1 \$d + 5: 00000014 0 NOTYPE LOCAL DEFAULT 1 \$a + 6: 00000020 0 NOTYPE LOCAL DEFAULT 1 \$t + 7: 00000010 0 OBJECT GLOBAL DEFAULT 1 bar_o + 8: 00000021 0 FUNC GLOBAL DEFAULT 1 bar_t + 9: 00000000 0 FUNC GLOBAL DEFAULT 1 foo_a + 10: 00000021 0 FUNC GLOBAL DEFAULT 1 foo_t + 11: 00000010 0 OBJECT GLOBAL DEFAULT 1 foo_o + 12: 00000000 0 FUNC GLOBAL DEFAULT 1 bar_a diff --git a/binutils-2.21/ld/testsuite/ld-arm/symbian-seg1.d b/binutils-2.21/ld/testsuite/ld-arm/symbian-seg1.d new file mode 100644 index 0000000..21d8a00 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/symbian-seg1.d @@ -0,0 +1,8 @@ +#source: symbian-seg1.s +#ld: -Ttext 0x10000 -Tdata 0x400000 +#objdump: -dR +#... + +10000: 00400000 .word 0x00400000 + +10000: R_ARM_RELATIVE .data + +10004: 00010008 .word 0x00010008 + +10004: R_ARM_RELATIVE .text diff --git a/binutils-2.21/ld/testsuite/ld-arm/symbian-seg1.s b/binutils-2.21/ld/testsuite/ld-arm/symbian-seg1.s new file mode 100644 index 0000000..8f893a2 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/symbian-seg1.s @@ -0,0 +1,13 @@ + .text + .globl _start +_start: + .word datavar + .word rodatavar + + .section ".rodata", "a" +rodatavar: + .word 0 + + .section ".data", "aw" +datavar: + .word 0 diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb-entry.d b/binutils-2.21/ld/testsuite/ld-arm/thumb-entry.d new file mode 100644 index 0000000..602fd6c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb-entry.d @@ -0,0 +1,3 @@ +#... + Entry point address: 0x8001 +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb-entry.s b/binutils-2.21/ld/testsuite/ld-arm/thumb-entry.s new file mode 100644 index 0000000..5b3659d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb-entry.s @@ -0,0 +1,8 @@ + .text + .arch armv4t + .thumb + .global _start + .thumb_func +_start: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb-rel32.d b/binutils-2.21/ld/testsuite/ld-arm/thumb-rel32.d new file mode 100644 index 0000000..34cde4d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb-rel32.d @@ -0,0 +1,7 @@ + +.*: file format.* + +Contents of section .text: + 8000 (00000011 fffffffd 00ffffff f8000000|11000000 fdffffff 00f8ffff ff000000) .* +# Ignore .ARM.attributes section +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb-rel32.s b/binutils-2.21/ld/testsuite/ld-arm/thumb-rel32.s new file mode 100644 index 0000000..83eb0e5 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb-rel32.s @@ -0,0 +1,18 @@ + .text + .arch armv4t + .global _start + .type _start, %function + .thumb_func +_start: + .word bar - . + .word _start - . + .byte 0 + .4byte (_start - .) + 1 + .byte 0, 0, 0 + .section .after, "ax", %progbits + .global bar + .type bar, %function + .thumb_func +bar: + .word 0 + .ident "GCC: (GNU) 4.1.0 (CodeSourcery ARM)" diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb1-bl.d b/binutils-2.21/ld/testsuite/ld-arm/thumb1-bl.d new file mode 100644 index 0000000..09d7095 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb1-bl.d @@ -0,0 +1,11 @@ + +.*thumb1-bl: file format elf32-.*arm + +Disassembly of section .text: + +00001000 <_start>: + 1000: f3ff fffe bl 401000 <bar> +Disassembly of section .foo: + +00401000 <bar>: + 401000: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb1-bl.s b/binutils-2.21/ld/testsuite/ld-arm/thumb1-bl.s new file mode 100644 index 0000000..cdecaa4 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb1-bl.s @@ -0,0 +1,22 @@ +@ Test to ensure that a Thumb-1 BL works. + + .arch armv5t + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + .thumb_func + +_start: + bl bar + +@ We will place the section .foo at 0x401000. + + .section .foo, "xa" + .thumb_func + +bar: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-b-interwork.d b/binutils-2.21/ld/testsuite/ld-arm/thumb2-b-interwork.d new file mode 100644 index 0000000..431989c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-b-interwork.d @@ -0,0 +1,16 @@ + +.*thumb2-b-interwork: file format elf32-.*arm + +Disassembly of section .text: + +00008000 <_start>: + 8000: f000 b802 b.w 8008 <__bar_from_thumb> + +00008004 <bar>: + 8004: e12fff1e bx lr + +00008008 <__bar_from_thumb>: + 8008: 4778 bx pc + 800a: 46c0 nop ; \(mov r8, r8\) + 800c: eafffffc b 8004 <bar> + diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-b-interwork.s b/binutils-2.21/ld/testsuite/ld-arm/thumb2-b-interwork.s new file mode 100644 index 0000000..4452a8f --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-b-interwork.s @@ -0,0 +1,20 @@ +@ Test to ensure that a Thumb-2 B.W can branch to an ARM funtion. + + .arch armv7-a + .global _start + .syntax unified + .text + .thumb_func + +_start: + b.w bar + +@ Put this in a separate section to force the assembler to generate a reloc + + .arm + .section .after, "xa" + .global bar + .type bar, %function +bar: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad-noeabi.d b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad-noeabi.d new file mode 100644 index 0000000..8872909 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad-noeabi.d @@ -0,0 +1,22 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: f000 f802 bl 1008 <__bar_veneer> + 1004: 0000 movs r0, r0 + ... + +00001008 <__bar_veneer>: + 1008: b401 push {r0} + 100a: 4802 ldr r0, \[pc, #8\] \(1014 <__bar_veneer\+0xc>\) + 100c: 4684 mov ip, r0 + 100e: bc01 pop {r0} + 1010: 4760 bx ip + 1012: bf00 nop + 1014: 0100100d .word 0x0100100d + +Disassembly of section .foo: + +0100100c <bar>: + 100100c: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d new file mode 100644 index 0000000..6b47810 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d @@ -0,0 +1,17 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: f000 e802 blx 1008 <__bar_veneer> + 1004: 0000 movs r0, r0 + \.\.\. + +00001008 <__bar_veneer>: + 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_veneer\+0x4> + 100c: 0100100d .word 0x0100100d + +Disassembly of section .foo: + +0100100c <bar>: + 100100c: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.s b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.s new file mode 100644 index 0000000..834001c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.s @@ -0,0 +1,22 @@ +@ Test to ensure that a Thumb-1 BL with a Thumb-2-only offset makes the linker generate a stub. + + .arch armv5t + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + .thumb_func + +_start: + bl bar + +@ We will place the section .foo at 0x100100c. + + .section .foo, "xa" + .thumb_func + +bar: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-bad-noeabi.d b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-bad-noeabi.d new file mode 100644 index 0000000..8872909 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-bad-noeabi.d @@ -0,0 +1,22 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: f000 f802 bl 1008 <__bar_veneer> + 1004: 0000 movs r0, r0 + ... + +00001008 <__bar_veneer>: + 1008: b401 push {r0} + 100a: 4802 ldr r0, \[pc, #8\] \(1014 <__bar_veneer\+0xc>\) + 100c: 4684 mov ip, r0 + 100e: bc01 pop {r0} + 1010: 4760 bx ip + 1012: bf00 nop + 1014: 0100100d .word 0x0100100d + +Disassembly of section .foo: + +0100100c <bar>: + 100100c: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-bad.d b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-bad.d new file mode 100644 index 0000000..d78e451 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-bad.d @@ -0,0 +1,16 @@ +.*: file format .* + +Disassembly of section .text: + +00001000 <_start>: + 1000: f000 e802 blx 1008 <__bar_veneer> + 1004: 0000 movs r0, r0 + \.\.\. + +00001008 <__bar_veneer>: + 1008: e51ff004 ldr pc, \[pc, #-4\] ; 100c <__bar_veneer\+0x4> + 100c: 0100100d .word 0x0100100d +Disassembly of section .foo: + +0100100c <bar>: + 100100c: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-bad.s b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-bad.s new file mode 100644 index 0000000..7685860 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-bad.s @@ -0,0 +1,22 @@ +@ Test to ensure that a Thumb-2 BL with an oversize offset makes the linker generate a stub. + + .arch armv7 + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + .thumb_func + +_start: + bl bar + +@ We will place the section .foo at 0x100100c. + + .section .foo, "xa" + .thumb_func + +bar: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-blx-interwork.d b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-blx-interwork.d new file mode 100644 index 0000000..ba5a732 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-blx-interwork.d @@ -0,0 +1,71 @@ + +.*: file format .* + + +Disassembly of section \.text: + +00008000 <_start>: + 8000: f000 e81a blx 8038 <arm0> + 8004: f000 e81e blx 8044 <arm4> + 8008: bf00 nop + 800a: f000 e816 blx 8038 <arm0> + 800e: f000 e81a blx 8044 <arm4> + 8012: bf00 nop + 8014: f000 f818 bl 8048 <thumb0> + 8018: f000 f81b bl 8052 <thumb2> + 801c: f000 f81e bl 805c <thumb4> + 8020: f000 f821 bl 8066 <thumb6> + 8024: bf00 nop + 8026: f000 f80f bl 8048 <thumb0> + 802a: f000 f812 bl 8052 <thumb2> + 802e: f000 f815 bl 805c <thumb4> + 8032: f000 f818 bl 8066 <thumb6> + 8036: bf00 nop + +00008038 <arm0>: + 8038: e12fff1e bx lr + 803c: e320f000 nop \{0\} + 8040: e320f000 nop \{0\} + +00008044 <arm4>: + 8044: e12fff1e bx lr + +00008048 <thumb0>: + 8048: 4770 bx lr + 804a: bf00 nop + 804c: f3af 8000 nop\.w + 8050: bf00 nop + +00008052 <thumb2>: + 8052: 4770 bx lr + 8054: f3af 8000 nop\.w + 8058: bf00 nop + 805a: bf00 nop + +0000805c <thumb4>: + 805c: 4770 bx lr + 805e: bf00 nop + 8060: bf00 nop + 8062: bf00 nop + 8064: bf00 nop + +00008066 <thumb6>: + 8066: 4770 bx lr + +00008068 <backwards>: + 8068: f7ff efe6 blx 8038 <arm0> + 806c: f7ff efea blx 8044 <arm4> + 8070: bf00 nop + 8072: f7ff efe2 blx 8038 <arm0> + 8076: f7ff efe6 blx 8044 <arm4> + 807a: bf00 nop + 807c: f7ff ffe4 bl 8048 <thumb0> + 8080: f7ff ffe7 bl 8052 <thumb2> + 8084: f7ff ffea bl 805c <thumb4> + 8088: f7ff ffed bl 8066 <thumb6> + 808c: bf00 nop + 808e: f7ff ffdb bl 8048 <thumb0> + 8092: f7ff ffde bl 8052 <thumb2> + 8096: f7ff ffe1 bl 805c <thumb4> + 809a: f7ff ffe4 bl 8066 <thumb6> + 809e: bf00 nop diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-blx-interwork.s b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-blx-interwork.s new file mode 100644 index 0000000..dba46af --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-blx-interwork.s @@ -0,0 +1,87 @@ + .arch armv7-a + .global _start + .syntax unified + .text + .thumb + + .macro do_calls + @ The following four instructions are accepted by gas, but generate + @ meaningless code. + @bl.w arm0 + @bl.w arm4 + @nop + @bl.w arm0 + @bl.w arm4 + @nop + blx.w arm0 + blx.w arm4 + nop + blx.w arm0 + blx.w arm4 + nop + bl.w thumb0 + bl.w thumb2 + bl.w thumb4 + bl.w thumb6 + nop + bl.w thumb0 + bl.w thumb2 + bl.w thumb4 + bl.w thumb6 + nop + @ These eight are all accepted by gas, but generate bad code. + @blx.w thumb0 + @blx.w thumb2 + @blx.w thumb4 + @blx.w thumb6 + @nop + @blx.w thumb0 + @blx.w thumb2 + @blx.w thumb4 + @blx.w thumb6 + .endm + + .thumb_func + .align 3 +_start: + do_calls + + .arm + .align 3 +arm0: + bx lr + + .align 3 + nop +arm4: + bx lr + + .thumb + .thumb_func + .align 3 +thumb0: + bx lr + + .thumb_func + .align 3 + nop +thumb2: + bx lr + + .thumb_func + .align 3 + nop + nop +thumb4: + bx lr + + .thumb_func + .align 3 + nop + nop + nop +thumb6: + bx lr + +backwards: + do_calls diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-undefweak.d b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-undefweak.d new file mode 100644 index 0000000..32f7cc1 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-undefweak.d @@ -0,0 +1,9 @@ +#source: thumb2-bl-undefweak.s +#as: +#ld: -shared +#objdump: -dr +#... +Disassembly of section .text: + +.* <foo>: + .*: .... .... bl. ... <foo-0x.*> diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-undefweak.s b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-undefweak.s new file mode 100644 index 0000000..5e70eea --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-undefweak.s @@ -0,0 +1,10 @@ +@ Test that calls to undefined weak functions resolve to call through +@ the PLT in shared libraries. + + .arch armv7 + .syntax unified + .text + .thumb_func +foo: + bl bar + .weak bar diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-undefweak1.d b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-undefweak1.d new file mode 100644 index 0000000..929d180 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-undefweak1.d @@ -0,0 +1,9 @@ +#source: thumb2-bl-undefweak1.s +#as: +#ld: -shared +#objdump: -dr +#... +Disassembly of section .text: + +.* <foo>: + .*: ........ bl ... <foo-0x.*> diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-undefweak1.s b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-undefweak1.s new file mode 100644 index 0000000..a302811 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl-undefweak1.s @@ -0,0 +1,9 @@ +@ Test that calls to undefined weak functions resolve to call through +@ the PLT in shared libraries in ARM mode. + + .arch armv6 + .syntax unified + .text +foo: + bl bar + .weak bar diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl.d b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl.d new file mode 100644 index 0000000..bdfb9b7 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl.d @@ -0,0 +1,11 @@ + +.*thumb2-bl: file format elf32-.*arm + +Disassembly of section .text: + +00001000 <_start>: + 1000: f3ff d7fe bl 1001000 <bar> +Disassembly of section .foo: + +01001000 <bar>: + 1001000: 4770 bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl.s b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl.s new file mode 100644 index 0000000..ddb1cd3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/thumb2-bl.s @@ -0,0 +1,23 @@ +@ Test to ensure that a Thumb-2 BL works with an offset that is +@ not permissable for Thumb-1. + + .arch armv7 + .global _start + .syntax unified + +@ We will place the section .text at 0x1000. + + .text + .thumb_func + +_start: + bl bar + +@ We will place the section .foo at 0x1001000. + + .section .foo, "xa" + .thumb_func + +bar: + bx lr + diff --git a/binutils-2.21/ld/testsuite/ld-arm/tls-app.d b/binutils-2.21/ld/testsuite/ld-arm/tls-app.d new file mode 100644 index 0000000..7d2a709 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/tls-app.d @@ -0,0 +1,18 @@ + +.*: file format elf32-.*arm +architecture: arm, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x000081c8 + +Disassembly of section .text: + +000081c8 <foo>: + 81c8: e1a00000 nop ; \(mov r0, r0\) + 81cc: e1a00000 nop ; \(mov r0, r0\) + 81d0: e1a0f00e mov pc, lr + 81d4: 000080bc .word 0x000080bc + 81d8: 000080b4 .word 0x000080b4 + 81dc: 000080ac .word 0x000080ac + 81e0: 00000004 .word 0x00000004 + 81e4: 000080c4 .word 0x000080c4 + 81e8: 00000014 .word 0x00000014 diff --git a/binutils-2.21/ld/testsuite/ld-arm/tls-app.r b/binutils-2.21/ld/testsuite/ld-arm/tls-app.r new file mode 100644 index 0000000..af6c2d7 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/tls-app.r @@ -0,0 +1,10 @@ + +.*: file format elf32-.*arm + +DYNAMIC RELOCATION RECORDS +OFFSET TYPE VALUE +[0-9a-f]+ R_ARM_TLS_DTPMOD32 app_gd +[0-9a-f]+ R_ARM_TLS_DTPOFF32 app_gd +[0-9a-f]+ R_ARM_TLS_DTPMOD32 lib_gd +[0-9a-f]+ R_ARM_TLS_DTPOFF32 lib_gd +[0-9a-f]+ R_ARM_TLS_TPOFF32 app_ie diff --git a/binutils-2.21/ld/testsuite/ld-arm/tls-app.s b/binutils-2.21/ld/testsuite/ld-arm/tls-app.s new file mode 100644 index 0000000..d505295 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/tls-app.s @@ -0,0 +1,34 @@ + .text + .globl foo + .type foo, %function +foo: + nop +.L2: + nop + mov pc, lr + +.Lpool: + .word lib_gd(tlsgd) + (. - .L2 - 8) + .word app_gd(tlsgd) + (. - .L2 - 8) + .word app_ld(tlsldm) + (. - .L2 - 8) + .word app_ld(tlsldo) + .word app_ie(gottpoff) + (. - .L2 - 8) + .word app_le(tpoff) + + .section .tdata,"awT" + .global app_gd +app_gd: + .space 4 + + .global app_ld +app_ld: + .space 4 + + .section .tbss,"awT",%nobits + .global app_ie +app_ie: + .space 4 + + .global app_le +app_le: + .space 4 diff --git a/binutils-2.21/ld/testsuite/ld-arm/tls-lib.d b/binutils-2.21/ld/testsuite/ld-arm/tls-lib.d new file mode 100644 index 0000000..4580ead --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/tls-lib.d @@ -0,0 +1,15 @@ + +.*: file format elf32-.*arm +architecture: arm, flags 0x00000150: +HAS_SYMS, DYNAMIC, D_PAGED +start address 0x.* + +Disassembly of section .text: + +.* <foo>: + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a00000 nop ; \(mov r0, r0\) + .*: e1a0f00e mov pc, lr + .*: 00008098 .word 0x00008098 + .*: 0000808c .word 0x0000808c + .*: 00000004 .word 0x00000004 diff --git a/binutils-2.21/ld/testsuite/ld-arm/tls-lib.r b/binutils-2.21/ld/testsuite/ld-arm/tls-lib.r new file mode 100644 index 0000000..279b805 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/tls-lib.r @@ -0,0 +1,10 @@ + +.*: file format elf32-.*arm + +DYNAMIC RELOCATION RECORDS +OFFSET TYPE VALUE +.* R_ARM_TLS_DTPMOD32 \*ABS\* +.* R_ARM_TLS_DTPMOD32 lib_gd +.* R_ARM_TLS_DTPOFF32 lib_gd + + diff --git a/binutils-2.21/ld/testsuite/ld-arm/tls-lib.s b/binutils-2.21/ld/testsuite/ld-arm/tls-lib.s new file mode 100644 index 0000000..fa928c0 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/tls-lib.s @@ -0,0 +1,22 @@ + .text + .globl foo + .type foo, %function +foo: + nop +.L2: + nop + mov pc, lr + +.Lpool: + .word lib_gd(tlsgd) + (. - .L2 - 8) + .word lib_ld(tlsldm) + (. - .L2 - 8) + .word lib_ld(tlsldo) + + .section .tdata,"awT" + .global lib_gd +lib_gd: + .space 4 + + .global lib_ld +lib_ld: + .space 4 diff --git a/binutils-2.21/ld/testsuite/ld-arm/unwind-1.d b/binutils-2.21/ld/testsuite/ld-arm/unwind-1.d new file mode 100644 index 0000000..add5cb7 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/unwind-1.d @@ -0,0 +1,10 @@ +#ld: -T arm.ld +#objdump: -s + +.*: file format.* + +#... +Contents of section .ARM.exidx: + 8008 (f8ffff7f b0b0a880 f4ffff7f 01000000|7ffffff8 80a8b0b0 7ffffff4 00000001) .* +Contents of section .far: +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/unwind-1.s b/binutils-2.21/ld/testsuite/ld-arm/unwind-1.s new file mode 100644 index 0000000..a4eb390 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/unwind-1.s @@ -0,0 +1,19 @@ + .syntax unified + .text + .global _start + .type _start, %function +_start: + .fnstart + .save {r4, lr} + bx lr + .fnend + + @ Section with no unwinding information. Linker should insert a cantunwind entry. + .section .after, "xa" + .global __aeabi_unwind_cpp_pr0 + .type __aeabi_unwind_cpp_pr0, %function +__aeabi_unwind_cpp_pr0: + bx lr + + .section .far + .word 0 diff --git a/binutils-2.21/ld/testsuite/ld-arm/unwind-2.d b/binutils-2.21/ld/testsuite/ld-arm/unwind-2.d new file mode 100644 index 0000000..a096c9b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/unwind-2.d @@ -0,0 +1,10 @@ +#ld: -T arm.ld +#objdump: -s + +.*: file format.* + +#... +Contents of section .ARM.exidx: + 8004 (fcffff7f b0b0a880 f8ffff7f 01000000|7ffffffc 80a8b0b0 7ffffff8 00000001) .* +Contents of section .far: +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/unwind-2.s b/binutils-2.21/ld/testsuite/ld-arm/unwind-2.s new file mode 100644 index 0000000..cd5851c --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/unwind-2.s @@ -0,0 +1,19 @@ + .syntax unified + .text + + .global __aeabi_unwind_cpp_pr0 + .type __aeabi_unwind_cpp_pr0, %function +__aeabi_unwind_cpp_pr0: + .global _start + .type _start, %function +_start: + .fnstart + .save {r4, lr} + bx lr + .fnend + + @ last text section has unwind information. Linker should append a + @ terminating cantunwind entry. + + .section .far + .word 0 diff --git a/binutils-2.21/ld/testsuite/ld-arm/unwind-3.d b/binutils-2.21/ld/testsuite/ld-arm/unwind-3.d new file mode 100644 index 0000000..0b8e85e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/unwind-3.d @@ -0,0 +1,11 @@ +#ld: -T arm.ld +#objdump: -s + +.*: file format.* + +#... +Contents of section .ARM.exidx: + 800c (f4ffff7f b0b0a880 f0ffff7f 01000000|7ffffff4 80a8b0b0 7ffffff0 00000001) .* + 801c (ecffff7f b0b0a880 e8ffff7f 01000000|7fffffec 80a8b0b0 7fffffe8 00000001) .* +Contents of section .far: +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/unwind-3.s b/binutils-2.21/ld/testsuite/ld-arm/unwind-3.s new file mode 100644 index 0000000..9cd8514 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/unwind-3.s @@ -0,0 +1,29 @@ + .syntax unified + .text + @ section without unwind info + .global _start + .type _start, %function +_start: + bl _before + + @ Section that will be placed first + .section .before, "xa" + .type _before, %function +_before: + .fnstart + .save {r4, lr} + bx lr + .fnend + + @ section that will be placed last + .section .after, "xa" + .global __aeabi_unwind_cpp_pr0 + .type __aeabi_unwind_cpp_pr0, %function +__aeabi_unwind_cpp_pr0: + .fnstart + .save {r4, lr} + bx lr + .fnend + + .section .far + .word 0 diff --git a/binutils-2.21/ld/testsuite/ld-arm/unwind-4.d b/binutils-2.21/ld/testsuite/ld-arm/unwind-4.d new file mode 100644 index 0000000..0a4427a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/unwind-4.d @@ -0,0 +1,11 @@ +#ld: -T arm.ld +#objdump: -s + +.*: file format.* + +#... +Contents of section .ARM.exidx: + 8020 (e0ffff7f b0b0a880 dcffff7f e8ffff7f|7fffffe0 80a8b0b0 7fffffdc 7fffffe8) .* + 8030 (d8ffff7f b0b0a880 d8ffff7f 01000000|7fffffd8 80a8b0b0 7fffffd8 00000001) .* +Contents of section .far: +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/unwind-4.s b/binutils-2.21/ld/testsuite/ld-arm/unwind-4.s new file mode 100644 index 0000000..015311b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/unwind-4.s @@ -0,0 +1,49 @@ + .syntax unified + .text + @ out of line table entry + .global _start + .type _start, %function +_start: + .fnstart + .save {r4, lr} + .vsave {d0} + .vsave {d4} + bl _before + .fnend + + @ entry that can be merged + .fnstart + .save {r4, lr} + bx lr + .fnend + + @ Section that will be placed first + .section .before, "xa" + .type _before, %function +_before: + .fnstart + .save {r4, lr} + bx lr + .fnend + + @ section that will be placed last + .section .after, "xa" + .global __aeabi_unwind_cpp_pr0 + .type __aeabi_unwind_cpp_pr0, %function +__aeabi_unwind_cpp_pr0: + .fnstart + .save {r4, lr} + bx lr + .fnend + @ final function is cantunwind, so output table size is smaller + @ than sum of input sections + .global __aeabi_unwind_cpp_pr1 + .type __aeabi_unwind_cpp_pr1, %function +__aeabi_unwind_cpp_pr1: + .fnstart + .cantunwind + bx lr + .fnend + + .section .far + .word 0 diff --git a/binutils-2.21/ld/testsuite/ld-arm/unwind-5.d b/binutils-2.21/ld/testsuite/ld-arm/unwind-5.d new file mode 100644 index 0000000..4928874 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/unwind-5.d @@ -0,0 +1,7 @@ +#ld: -T discard-unwind.ld +#objdump: -s + +.*: file format.* + +# Check we don't crash when discarding unwind info. +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/unwind-5.s b/binutils-2.21/ld/testsuite/ld-arm/unwind-5.s new file mode 100644 index 0000000..d15677d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/unwind-5.s @@ -0,0 +1,12 @@ + .syntax unified + .text + .global __aeabi_unwind_cpp_pr0 + .type __aeabi_unwind_cpp_pr0, %function +__aeabi_unwind_cpp_pr0: + .global _start + .type _start, %function +_start: + .fnstart + .save {r4, lr} + bx lr + .fnend diff --git a/binutils-2.21/ld/testsuite/ld-arm/use-thumb-lib.s b/binutils-2.21/ld/testsuite/ld-arm/use-thumb-lib.s new file mode 100644 index 0000000..07a7f57 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/use-thumb-lib.s @@ -0,0 +1,25 @@ + .cpu arm10tdmi + .fpu softvfp + .eabi_attribute 18, 4 + .eabi_attribute 20, 1 + .eabi_attribute 21, 1 + .eabi_attribute 23, 3 + .eabi_attribute 24, 1 + .eabi_attribute 25, 1 + .eabi_attribute 26, 2 + .eabi_attribute 30, 6 + .file "use_thumb_lib.c" + .text + .align 2 + .global foo + .type foo, %function +foo: + @ args = 0, pretend = 0, frame = 0 + @ frame_needed = 1, uses_anonymous_args = 0 + mov ip, sp + stmfd sp!, {fp, ip, lr, pc} + sub fp, ip, #4 + bl lib_func2 + ldmfd sp, {fp, sp, pc} + .size foo, .-foo + .ident "GCC: (GNU) 4.1.0 (CodeSourcery ARM 2006q1-7)" diff --git a/binutils-2.21/ld/testsuite/ld-arm/use-thumb-lib.sym b/binutils-2.21/ld/testsuite/ld-arm/use-thumb-lib.sym new file mode 100644 index 0000000..2db6c06 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/use-thumb-lib.sym @@ -0,0 +1,4 @@ +#... + +.. +..: 0+ +0 +FUNC +GLOBAL +DEFAULT +UND lib_func2 +#pass + diff --git a/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-none.d b/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-none.d new file mode 100644 index 0000000..64a67ae --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-none.d @@ -0,0 +1,9 @@ + +.*: .*file format elf32-(big|little)arm + +Disassembly of section \.text: + +00008000 <_start>: + 8000: ee474a20 \.word 0xee474a20 + 8004: ed927a00 \.word 0xed927a00 + 8008: e12fff1e bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-none.s b/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-none.s new file mode 100644 index 0000000..a016c49 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-none.s @@ -0,0 +1,7 @@ + .arm + .text + .globl _start +_start: + .word 0xee474a20 + .word 0xed927a00 + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-scalar.d b/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-scalar.d new file mode 100644 index 0000000..5095137 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-scalar.d @@ -0,0 +1,15 @@ + +.*: .*file format elf32-(big|little)arm + +Disassembly of section \.text: + +00008000 <_start>: + 8000: 0a000001 beq 800c <__vfp11_veneer_0> + +00008004 <__vfp11_veneer_0_r>: + 8004: ed927a00 (vldr|flds) s14, \[r2\] + 8008: e12fff1e bx lr + +0000800c <__vfp11_veneer_0>: + 800c: 0e474a20 (vmlaeq\.f32|fmacseq) s9, s14, s1 + 8010: eafffffb b 8004 <__vfp11_veneer_0_r> diff --git a/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-scalar.s b/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-scalar.s new file mode 100644 index 0000000..4ffb891 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-scalar.s @@ -0,0 +1,7 @@ + .arm + .text + .globl _start +_start: + fmacseq s9, s14, s1 + flds s14, [r2] + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-vector.d b/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-vector.d new file mode 100644 index 0000000..15c080a --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-vector.d @@ -0,0 +1,16 @@ + +.*: .*file format elf32-(big|little)arm + +Disassembly of section \.text: + +00008000 <_start>: + 8000: 0a000002 beq 8010 <__vfp11_veneer_0> + +00008004 <__vfp11_veneer_0_r>: + 8004: e1a02003 mov r2, r3 + 8008: ed927a00 (vldr|flds) s14, \[r2\] + 800c: e12fff1e bx lr + +00008010 <__vfp11_veneer_0>: + 8010: 0e474a20 (vmlaeq\.f32|fmacseq) s9, s14, s1 + 8014: eafffffa b 8004 <__vfp11_veneer_0_r> diff --git a/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-vector.s b/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-vector.s new file mode 100644 index 0000000..05b6100 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vfp11-fix-vector.s @@ -0,0 +1,8 @@ + .arm + .text + .globl _start +_start: + fmacseq s9, s14, s1 + mov r2,r3 + flds s14, [r2] + bx lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/vxworks1-lib.dd b/binutils-2.21/ld/testsuite/ld-arm/vxworks1-lib.dd new file mode 100644 index 0000000..77bdf72 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vxworks1-lib.dd @@ -0,0 +1,41 @@ + +.*: file format .* + +Disassembly of section \.plt: + +00080800 <_PROCEDURE_LINKAGE_TABLE_>: + 80800: e59fc000 ldr ip, \[pc, #0\] ; 80808 <.*> + 80804: e79cf009 ldr pc, \[ip, r9\] + 80808: 0000000c .word 0x0000000c + 8080c: e59fc000 ldr ip, \[pc, #0\] ; 80814 <.*> + 80810: e599f008 ldr pc, \[r9, #8\] + 80814: 00000000 .word 0x00000000 + 80818: e59fc000 ldr ip, \[pc, #0\] ; 80820 <.*> + 8081c: e79cf009 ldr pc, \[ip, r9\] + 80820: 00000010 .word 0x00000010 + 80824: e59fc000 ldr ip, \[pc, #0\] ; 8082c <.*> + 80828: e599f008 ldr pc, \[r9, #8\] + 8082c: 0000000c .word 0x0000000c +Disassembly of section \.text: + +00080c00 <foo>: + 80c00: e92dc200 push {r9, lr, pc} + 80c04: e59f9024 ldr r9, \[pc, #36\] ; 80c30 <.*> + 80c08: e5999000 ldr r9, \[r9\] + 80c0c: e5999000 ldr r9, \[r9\] + 80c10: e59f001c ldr r0, \[pc, #28\] ; 80c34 <.*> + 80c14: e7991000 ldr r1, \[r9, r0\] + 80c18: e2811001 add r1, r1, #1 ; 0x1 + 80c1c: e7891000 str r1, \[r9, r0\] + 80c20: eb000004 bl 80c38 <slocal> + 80c24: ebfffefb bl 80818 <.*> + 80c28: ebfffef4 bl 80800 <.*> + 80c2c: e8bd8200 pop {r9, pc} + 80c30: 00000000 .word 0x00000000 + 80c34: 00000014 .word 0x00000014 + +00080c38 <slocal>: + 80c38: e1a0f00e mov pc, lr + +00080c3c <sglobal>: + 80c3c: e1a0f00e mov pc, lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/vxworks1-lib.nd b/binutils-2.21/ld/testsuite/ld-arm/vxworks1-lib.nd new file mode 100644 index 0000000..edf3db3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vxworks1-lib.nd @@ -0,0 +1,9 @@ +#... +Symbol table '\.dynsym' .*: +#... +.*: 00081400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_ +#... +Symbol table '\.symtab' .*: +#... +.*: 00081400 * 0 * OBJECT * GLOBAL * DEFAULT * [0-9]+ _GLOBAL_OFFSET_TABLE_ +#pass diff --git a/binutils-2.21/ld/testsuite/ld-arm/vxworks1-lib.rd b/binutils-2.21/ld/testsuite/ld-arm/vxworks1-lib.rd new file mode 100644 index 0000000..226bd09 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vxworks1-lib.rd @@ -0,0 +1,12 @@ + +Relocation section '\.rela\.plt' at offset .* contains 2 entries: + Offset Info Type Sym\.Value Sym\. Name \+ Addend +0008140c .*16 R_ARM_JUMP_SLOT 00000000 sexternal \+ 0 +00081410 .*16 R_ARM_JUMP_SLOT 00080c3c sglobal \+ 0 + +Relocation section '\.rela\.dyn' at offset .* contains 4 entries: + Offset Info Type Sym\.Value Sym\. Name \+ Addend +00081800 00000017 R_ARM_RELATIVE * 00080c38 +00080c0c .*06 R_ARM_ABS12 00000000 __GOTT_INDEX__ \+ 0 +00080c30 .*02 R_ARM_ABS32 00000000 __GOTT_BASE__ \+ 0 +00081414 .*15 R_ARM_GLOB_DAT 00081c00 x \+ 0 diff --git a/binutils-2.21/ld/testsuite/ld-arm/vxworks1-lib.s b/binutils-2.21/ld/testsuite/ld-arm/vxworks1-lib.s new file mode 100644 index 0000000..66dfd1e --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vxworks1-lib.s @@ -0,0 +1,36 @@ + .text + .globl foo + .type foo, %function +foo: + stmfd sp!, {r9, lr, pc} + ldr r9, 1f + ldr r9, [r9] + ldr r9, [r9, #__GOTT_INDEX__] + ldr r0, 1f + 4 + ldr r1, [r9, r0] + add r1, r1, #1 + str r1, [r9, r0] + bl slocal(PLT) + bl sglobal(PLT) + bl sexternal(PLT) + ldmfd sp!, {r9, pc} +1: + .word __GOTT_BASE__ + .word x(got) + .size foo, .-foo + + .type slocal, %function +slocal: + mov pc,lr + .size slocal, .-slocal + + .globl sglobal + .type sglobal, %function +sglobal: + mov pc,lr + .size sglobal, .-sglobal + + .data + .4byte slocal + + .comm x,4,4 diff --git a/binutils-2.21/ld/testsuite/ld-arm/vxworks1-lib.td b/binutils-2.21/ld/testsuite/ld-arm/vxworks1-lib.td new file mode 100644 index 0000000..9f223e3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vxworks1-lib.td @@ -0,0 +1,3 @@ +#... + 0x0+16 \(TEXTREL\) +0x0 +#pass diff --git a/binutils-2.21/ld/testsuite/ld-arm/vxworks1-static.d b/binutils-2.21/ld/testsuite/ld-arm/vxworks1-static.d new file mode 100644 index 0000000..88c0baf --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vxworks1-static.d @@ -0,0 +1,4 @@ +#name: VxWorks executable test 1 (static) +#source: vxworks1.s +#ld: tmpdir/libvxworks1.so -Tvxworks1.ld +#error: Dynamic sections created in non-dynamic link diff --git a/binutils-2.21/ld/testsuite/ld-arm/vxworks1.dd b/binutils-2.21/ld/testsuite/ld-arm/vxworks1.dd new file mode 100644 index 0000000..0443122 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vxworks1.dd @@ -0,0 +1,37 @@ + +.*: file format .* + +Disassembly of section \.plt: + +00080800 <_PROCEDURE_LINKAGE_TABLE_>: + 80800: e52dc008 str ip, \[sp, #-8\]! + 80804: e59fc000 ldr ip, \[pc, #0\] ; 8080c <.*> + 80808: e59cf008 ldr pc, \[ip, #8\] + 8080c: 00081400 .word 0x00081400 + 8080c: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_ + 80810: e59fc000 ldr ip, \[pc, #0\] ; 80818 <.*> + 80814: e59cf000 ldr pc, \[ip\] + 80818: 0008140c .word 0x0008140c + 80818: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_\+0xc + 8081c: e59fc000 ldr ip, \[pc, #0\] ; 80824 <.*> + 80820: eafffff6 b 80800 <.*> + 80824: 00000000 .word 0x00000000 + 80828: e59fc000 ldr ip, \[pc, #0\] ; 80830 <.*> + 8082c: e59cf000 ldr pc, \[ip\] + 80830: 00081410 .word 0x00081410 + 80830: R_ARM_ABS32 _GLOBAL_OFFSET_TABLE_\+0x10 + 80834: e59fc000 ldr ip, \[pc, #0\] ; 8083c <.*> + 80838: eafffff0 b 80800 <.*> + 8083c: 0000000c .word 0x0000000c +Disassembly of section \.text: + +00080c00 <_start>: + 80c00: ebffff08 bl 80828 <.*> + 80c00: R_ARM_PC24 \.plt\+0x20 + 80c04: eb000000 bl 80c0c <sexternal> + 80c04: R_ARM_PC24 sexternal\+0xfffffff8 + 80c08: eaffff00 b 80810 <.*> + 80c08: R_ARM_PC24 \.plt\+0x8 + +00080c0c <sexternal>: + 80c0c: e1a0f00e mov pc, lr diff --git a/binutils-2.21/ld/testsuite/ld-arm/vxworks1.ld b/binutils-2.21/ld/testsuite/ld-arm/vxworks1.ld new file mode 100644 index 0000000..65bf65d --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vxworks1.ld @@ -0,0 +1,30 @@ +SECTIONS +{ + . = 0x80000; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + + . = ALIGN (0x400); + .rela.dyn : { *(.rela.dyn) } + .rela.plt : { *(.rela.plt) } + + . = ALIGN (0x400); + .plt : { *(.plt) } + + . = ALIGN (0x400); + .text : { *(.text) } + + . = ALIGN (0x1000); + .dynamic : { *(.dynamic) } + + . = ALIGN (0x400); + .got : { *(.got.plt) *(.got) } + + . = ALIGN (0x400); + .data : { *(.data) } + + . = ALIGN (0x400); + .bss : { *(.bss) *(.dynbss) } +} diff --git a/binutils-2.21/ld/testsuite/ld-arm/vxworks1.rd b/binutils-2.21/ld/testsuite/ld-arm/vxworks1.rd new file mode 100644 index 0000000..8d7d5cb --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vxworks1.rd @@ -0,0 +1,19 @@ + +Relocation section '\.rela\.plt' at offset .* contains 2 entries: + Offset Info Type Sym\.Value Sym\. Name \+ Addend +0008140c .*16 R_ARM_JUMP_SLOT 00080810 sglobal \+ 0 +00081410 .*16 R_ARM_JUMP_SLOT 00080828 foo \+ 0 + +Relocation section '\.rela\.text' at offset .* contains 3 entries: + Offset Info Type Sym.Value Sym. Name \+ Addend +00080c00 .*01 R_ARM_PC24 00080800 \.plt \+ 20 +00080c04 .*01 R_ARM_PC24 00080c0c sexternal \+ fffffff8 +00080c08 .*01 R_ARM_PC24 00080800 \.plt \+ 8 + +Relocation section '\.rela\.plt\.unloaded' at offset .* contains 5 entries: + Offset Info Type Sym\.Value Sym\. Name \+ Addend +0008080c .*02 R_ARM_ABS32 00081400 _GLOBAL_OFFSET_TABLE_ \+ 0 +00080818 .*02 R_ARM_ABS32 00081400 _GLOBAL_OFFSET_TABLE_ \+ c +0008140c .*02 R_ARM_ABS32 00080800 _PROCEDURE_LINKAGE_TAB.* \+ 0 +00080830 .*02 R_ARM_ABS32 00081400 _GLOBAL_OFFSET_TABLE_ \+ 10 +00081410 .*02 R_ARM_ABS32 00080800 _PROCEDURE_LINKAGE_TAB.* \+ 0 diff --git a/binutils-2.21/ld/testsuite/ld-arm/vxworks1.s b/binutils-2.21/ld/testsuite/ld-arm/vxworks1.s new file mode 100644 index 0000000..0139a11 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vxworks1.s @@ -0,0 +1,14 @@ + .text + .globl _start + .type _start, %function +_start: + bl foo + bl sexternal + b sglobal + .size _start, .-_start + + .globl sexternal + .type sexternal, %function +sexternal: + mov pc, lr + .size sexternal, .-sexternal diff --git a/binutils-2.21/ld/testsuite/ld-arm/vxworks2-static.sd b/binutils-2.21/ld/testsuite/ld-arm/vxworks2-static.sd new file mode 100644 index 0000000..912755b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vxworks2-static.sd @@ -0,0 +1,9 @@ +#... +Elf file type is EXEC \(Executable file\) +Entry point 0x80000 +#... +Program Headers: + Type .* + LOAD .* 0x00080000 0x00080000 .* R E 0x1000 + +#... diff --git a/binutils-2.21/ld/testsuite/ld-arm/vxworks2.s b/binutils-2.21/ld/testsuite/ld-arm/vxworks2.s new file mode 100644 index 0000000..1bd207b --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vxworks2.s @@ -0,0 +1,5 @@ + .globl _start + .type _start, %function +_start: + mov pc, lr + .end _start diff --git a/binutils-2.21/ld/testsuite/ld-arm/vxworks2.sd b/binutils-2.21/ld/testsuite/ld-arm/vxworks2.sd new file mode 100644 index 0000000..5ff87d3 --- /dev/null +++ b/binutils-2.21/ld/testsuite/ld-arm/vxworks2.sd @@ -0,0 +1,13 @@ +#... +Elf file type is EXEC \(Executable file\) +Entry point 0x80400 +#... +Program Headers: + Type .* + PHDR .* +#... + LOAD .* 0x00080000 0x00080000 .* R E 0x1000 + LOAD .* 0x00081000 0x00081000 .* RW 0x1000 + DYNAMIC .* + +#... |