18 files changed, 1178 insertions, 0 deletions
diff --git a/binutils-2.21/ld/testsuite/ld-spu/ear.d b/binutils-2.21/ld/testsuite/ld-spu/ear.d
new file mode 100644
index 0000000..df5546f
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/ear.d
@@ -0,0 +1,30 @@
+#as:
+#objdump: -Dr
+#name: ear
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+00 <_start>:
+   0:	32 00 00 00 	br	0
+			0: SPU_REL16	_start
+
+Disassembly of section \.data:
+
+0+00 <_EAR_main>:
+	\.\.\.
+
+0+20 <_EAR_foo>:
+	\.\.\.
+Disassembly of section \.toe:
+
+0+00 <_EAR_>:
+	\.\.\.
+
+0+10 <_EAR_bar>:
+	\.\.\.
+Disassembly of section \.data\.blah:
+
+0+00 <_EAR_blah>:
+	\.\.\.
diff --git a/binutils-2.21/ld/testsuite/ld-spu/ear.s b/binutils-2.21/ld/testsuite/ld-spu/ear.s
new file mode 100644
index 0000000..724a525
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/ear.s
@@ -0,0 +1,28 @@
+ .text
+ .global _start
+_start:
+ br _start
+
+#test old-style toe _EAR_ syms
+ .section .toe,"a",@nobits
+ .p2align 4
+_EAR_:
+ .space 16
+_EAR_bar:
+ .space 16
+
+#test new-style _EAR_ syms
+ .data
+ .p2align 4
+_EAR_main:
+ .space 16
+
+#new ones don't need to be 16 bytes apart
+ .space 16
+_EAR_foo:
+ .space 16
+
+ .section .data.blah,"aw",@progbits
+ .p2align 4
+_EAR_blah:
+ .space 16
diff --git a/binutils-2.21/ld/testsuite/ld-spu/embed.rd b/binutils-2.21/ld/testsuite/ld-spu/embed.rd
new file mode 100644
index 0000000..4fcfe2a
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/embed.rd
@@ -0,0 +1,16 @@
+
+Relocation section '\.rela\.rodata\.speelf' at .* contains 3 entries:
+ Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend
+0+184 .* R_PPC_ADDR32 +0+0 +main \+ 0
+0+1a4 .* R_PPC_ADDR32 +0+0 +foo \+ 0
+0+1b4 .* R_PPC_ADDR32 +0+0 +blah \+ 0
+
+Relocation section '\.rela\.data\.spetoe' at .* contains 2 entries:
+ Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend
+0+004 .* R_PPC_ADDR32 +0+0 +\.rodata\.speelf \+ 0
+0+014 .* R_PPC_ADDR32 +0+0 +bar \+ 0
+
+Relocation section '\.rela\.data\.spehandle' at .* contains 2 entries:
+ Offset +Info +Type +Sym\. Value +Symbol's Name \+ Addend
+0+004 .* R_PPC_ADDR32 +0+0 +\.rodata\.speelf \+ 0
+0+008 .* R_PPC_ADDR32 +0+0 +\.data\.spetoe \+ 0
diff --git a/binutils-2.21/ld/testsuite/ld-spu/fixup.d b/binutils-2.21/ld/testsuite/ld-spu/fixup.d
new file mode 100644
index 0000000..39f731b
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/fixup.d
@@ -0,0 +1,20 @@
+#source: fixup.s
+#ld: --emit-fixups
+#objdump: -s 
+
+.*elf32-spu
+
+Contents of section .text:
+ 0000 00000000                             ....            
+Contents of section .fixup:
+ 0004 0000008b 00000091 000000c1 00000000  ................
+Contents of section .data:
+ 0080 000000d0 00000000 00000000 000000c0  ................
+ 0090 00000000 00000000 00000000 000000b0  ................
+ 00a0 00000001 00000000 00000000 00000000  ................
+ 00b0 00000002 00000000 00000000 00000000  ................
+ 00c0 00000000 00000000 00000000 00000080  ................
+Contents of section .note.spu_name:
+.*
+.*
+#pass
diff --git a/binutils-2.21/ld/testsuite/ld-spu/fixup.s b/binutils-2.21/ld/testsuite/ld-spu/fixup.s
new file mode 100644
index 0000000..c0fd6db
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/fixup.s
@@ -0,0 +1,24 @@
+ .global _end
+ .global _start
+ .global glob
+ .global after
+ .global before
+ .weak undef
+
+ .section .text,"ax"
+_start:
+ stop
+
+
+ .data
+ .p2align 4
+before:
+ .long _end, 0, _start, after
+ .long 0, 0, 0, glob
+loc:
+ .long 1,0,0,0
+glob:
+ .long 2,0,0,0
+after:
+ .long 0, 0, 0, before
+
diff --git a/binutils-2.21/ld/testsuite/ld-spu/icache1.d b/binutils-2.21/ld/testsuite/ld-spu/icache1.d
new file mode 100644
index 0000000..01b42ba
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/icache1.d
@@ -0,0 +1,193 @@
+#source: icache1.s
+#ld: --soft-icache --num-lines=4 --non-ia-text --auto-overlay=tmpdir/icache1.lnk --auto-relink
+#objdump: -D
+
+.* elf32-spu
+
+
+Disassembly of section \.text:
+
+00000000 <_start>:
+.*	41 00 02 03 	ilhu	\$3,4
+.*	60 88 00 03 	iohl	\$3,4096	# 1000
+.*	32 00 03 80 	br	24.*
+0000000c <__icache_br_handler>:
+   c:	00 00 00 00 	stop
+00000010 <__icache_call_handler>:
+	\.\.\.
+  20:	00 04 08 00.*
+  24:	31 00 02 4b 	brasl	\$75,10 <__icache_call_handler>
+  28:	a0 00 00 08.*
+  2c:	00 00 fc 80.*
+	\.\.\.
+
+Disassembly of section \.data:
+
+.* <.data>:
+.*	00 04 08 00 	.*
+.*	00 04 0d 04 	.*
+.*	00 04 0c 00 	.*
+.*	00 08 10 00 	.*
+
+Disassembly of section \.bss:
+
+.* <__icache_tag_array>:
+	\.\.\.
+
+.* <__icache_rewrite_to>:
+	\.\.\.
+
+.* <__icache_rewrite_from>:
+	\.\.\.
+
+Disassembly of section \.ovl\.init:
+
+00000400 <__icache_fileoff>:
+.*	00 00 00 00.*
+.*	00 00 02 00.*
+	\.\.\.
+
+Disassembly of section \.ovly1:
+
+00000400 <\.ovly1>:
+.*	ai	\$1,\$1,64	# 40
+.*	lqd	\$0,16\(\$1\)
+.*	bi	\$0
+	\.\.\.
+
+Disassembly of section \.ovly2:
+
+00000800 <f1>:
+.*	40 20 00 00 	nop	\$0
+.*	24 00 40 80 	stqd	\$0,16\(\$1\)
+.*	1c f0 00 81 	ai	\$1,\$1,-64
+.*	24 00 00 81 	stqd	\$1,0\(\$1\)
+.*	33 00 78 80 	brsl	\$0,bd4 .*
+.*	33 00 7a 00 	brsl	\$0,be4 .*
+	\.\.\.
+.*	32 00 17 80 	br	bf4 .*
+	\.\.\.
+ bd0:	00 04 0d 04.*
+ bd4:	31 00 01 cb 	brasl	\$75,c .*
+ bd8:	a0 00 08 10.*
+ bdc:	00 00 e6 00.*
+ be0:	00 04 0c 00.*
+ be4:	31 00 01 cb 	brasl	\$75,c .*
+ be8:	a0 00 08 14.*
+ bec:	00 00 07 80.*
+ bf0:	00 04 04 00.*
+ bf4:	31 00 01 cb 	brasl	\$75,c .*
+ bf8:	20 00 0b 38.*
+ bfc:	00 7f 0e 80.*
+
+Disassembly of section \.ovly3:
+
+00000c00 <f3>:
+	\.\.\.
+.*	35 00 00 00 	bi	\$0
+
+00000d04 <f2>:
+.*	1c e0 00 81 	ai	\$1,\$1,-128
+.*	24 00 00 81 	stqd	\$1,0\(\$1\)
+	\.\.\.
+.*	1c 20 00 81 	ai	\$1,\$1,128	# 80
+.*	35 00 00 00 	bi	\$0
+	\.\.\.
+
+Disassembly of section \.ovly4:
+
+00001000 <f5>:
+.*	24 00 40 80 	stqd	\$0,16\(\$1\)
+.*	24 f8 00 81 	stqd	\$1,-512\(\$1\)
+.*	1c 80 00 81 	ai	\$1,\$1,-512
+.*	33 7f fe 80 	brsl	\$0,1000 <f5>	# 1000
+	\.\.\.
+.*	42 01 00 03 	ila	\$3,200.*
+.*	18 00 c0 81 	a	\$1,\$1,\$3
+.*	34 00 40 80 	lqd	\$0,16\(\$1\)
+.*	35 00 00 00 	bi	\$0
+	\.\.\.
+
+Disassembly of section \.ovly5:
+
+00000400 <\.ovly5>:
+	\.\.\.
+.*	42 01 00 03 	ila	\$3,200 .*
+.*	18 00 c0 81 	a	\$1,\$1,\$3
+.*	34 00 40 80 	lqd	\$0,16\(\$1\)
+.*	30 00 fe 80 	bra	7f4 .*
+	\.\.\.
+ 7f0:	00 04 10 00.*
+ 7f4:	31 00 01 cb 	brasl	\$75,c .*
+ 7f8:	a0 00 07 2c.*
+ 7fc:	00 02 fe 80.*
+
+Disassembly of section \.ovly6:
+
+00000800 <\.ovly6>:
+.*	31 01 7a 80 	brasl	\$0,bd4 .*
+.*	33 00 7c 00 	brsl	\$0,be4 .*
+	\.\.\.
+.*	32 00 19 80 	br	bf4 .*
+	\.\.\.
+ bd0:	00 08 10 00.*
+ bd4:	31 00 01 cb 	brasl	\$75,c .*
+ bd8:	a0 00 08 00.*
+ bdc:	00 03 7a 80.*
+ be0:	00 08 10 00.*
+ be4:	31 00 01 cb 	brasl	\$75,c .*
+ be8:	a0 00 08 04.*
+ bec:	00 00 83 80.*
+ bf0:	00 08 04 00.*
+ bf4:	31 00 01 cb 	brasl	\$75,c .*
+ bf8:	20 00 0b 28.*
+ bfc:	00 7f 02 80.*
+
+Disassembly of section \.ovly7:
+
+00000c00 <\.ovly7>:
+.*	41 7f ff 83 	ilhu	\$3,65535	# ffff
+.*	60 f8 30 03 	iohl	\$3,61536	# f060
+.*	18 00 c0 84 	a	\$4,\$1,\$3
+.*	00 20 00 00 	lnop
+.*	04 00 02 01 	ori	\$1,\$4,0
+.*	24 00 02 04 	stqd	\$4,0\(\$4\)
+.*	33 00 77 80 	brsl	\$0,fd4 .*
+.*	33 00 79 00 	brsl	\$0,fe4 .*
+.*	34 00 00 81 	lqd	\$1,0\(\$1\)
+	\.\.\.
+.*	32 00 16 00 	br	ff4 .*
+	\.\.\.
+     fd0:	00 04 10 00.*
+     fd4:	31 00 01 cb 	brasl	\$75,c .*
+     fd8:	a0 00 0c 18.*
+     fdc:	00 00 0a 80.*
+     fe0:	00 08 10 00.*
+     fe4:	31 00 01 cb 	brasl	\$75,c .*
+     fe8:	a0 00 0c 1c.*
+     fec:	00 00 05 80.*
+     ff0:	00 08 08 00.*
+     ff4:	31 00 01 cb 	brasl	\$75,c .*
+     ff8:	20 00 0f 44.*
+     ffc:	00 7f 01 80.*
+
+Disassembly of section \.ovly8:
+
+00001000 <f4>:
+.*	24 00 40 80 	stqd	\$0,16\(\$1\)
+.*	24 f8 00 81 	stqd	\$1,-512\(\$1\)
+.*	1c 80 00 81 	ai	\$1,\$1,-512
+.*	31 02 7c 80 	brasl	\$0,13e4 .*
+	\.\.\.
+.*	32 00 18 80 	br	13f4 .*
+	\.\.\.
+    13e0:	00 04 0d 04.*
+    13e4:	31 00 01 cb 	brasl	\$75,c .*
+    13e8:	a0 00 10 0c.*
+    13ec:	00 03 dc 00.*
+    13f0:	00 08 0c 00.*
+    13f4:	31 00 01 cb 	brasl	\$75,c .*
+    13f8:	20 00 13 30.*
+    13fc:	00 7f 02 80.*
+
+#pass
diff --git a/binutils-2.21/ld/testsuite/ld-spu/icache1.s b/binutils-2.21/ld/testsuite/ld-spu/icache1.s
new file mode 100644
index 0000000..a65664c
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/icache1.s
@@ -0,0 +1,111 @@
+ .text
+ .globl _start
+ .type _start,@function
+_start:
+ ilhu $3,f5@h
+ iohl $3,f5@l
+ br f1
+
+ .data
+ .word f1, f2, f3, f4
+
+ .section ".f1.part1","ax",@progbits
+ .globl f1
+ .type f1,@function
+f1:
+ nop
+ stqd $0,16($1)
+ ai $1,$1,-64
+ stqd $1,0($1)
+ brsl $0,f2
+ brsl $0,f3
+ .fill 800
+ br .Lf1.part2
+ .size f1,.-f1
+
+ .section ".f1.part2","ax",@progbits
+.Lf1.part2:
+ ai $1,$1,64
+ lqd $0,16($1)
+ bi $0
+ .fill 800
+ .size .Lf1.part2,.-.Lf1.part2
+
+ .section ".f2.part1","ax",@progbits
+ .globl f2
+ .type f2,@function
+f2:
+ ai $1,$1,-128
+ stqd $1,0($1)
+ .fill 512
+ ai $1,$1,128
+ bi $0
+ .size f2,.-f2
+
+ .section ".f3.part1","ax",@progbits
+ .type f3,@function
+f3:
+ .fill 256
+ bi $0
+ .size f3,.-f3
+
+ .section ".f4.part1","ax",@progbits
+ .type f4,@function
+f4:
+ stqd $(0),16($1)
+ stqd $1,-512($1)
+ ai $1,$1,-512
+ brasl $0,f2
+ .fill 800
+ br .Lf4.part2
+ .size f4,.-f4
+
+ .section ".f4.part2","ax",@progbits
+.Lf4.part2:
+#alloca
+ ilhu $3,-4000@h
+ iohl $3,-4000@l
+ a $4,$1,$3
+ lnop
+ ori $1,$4,0
+ stqd $4,0($4)
+ brsl $0,f5
+#recursion
+ brsl $0,f4
+ lqd $1,0($1)
+ .fill 800
+ br .Lf4.part3
+ .size .Lf4.part2,.-.Lf4.part2
+
+ .section ".f4.part3","ax",@progbits
+.Lf4.part3:
+#recursion
+ brasl $0,f4
+ brsl $0,f4
+ .fill 800
+ br .Lf4.part4
+ .size .Lf4.part3,.-.Lf4.part3
+
+ .section ".f4.part4","ax",@progbits
+.Lf4.part4:
+ .fill 800
+ ila $3,512
+ a $1,$1,$3
+ lqd $0,16($1)
+#sibling call
+ bra f5
+ .size .Lf4.part4,.-.Lf4.part4
+
+ .section ".f5.part1","ax",@progbits
+ .type f5,@function
+f5:
+ stqd $(0),16($1)
+ stqd $1,-512($1)
+ ai $1,$1,-512
+ brsl $0,f5
+ .fill 800
+ ila $3,512
+ a $1,$1,$3
+ lqd $0,16($1)
+ bi $0
+ .size f5,.-f5
diff --git a/binutils-2.21/ld/testsuite/ld-spu/ovl.d b/binutils-2.21/ld/testsuite/ld-spu/ovl.d
new file mode 100644
index 0000000..cbf7573
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/ovl.d
@@ -0,0 +1,179 @@
+#source: ovl.s
+#ld: -N -T ovl1.lnk -T ovl.lnk --emit-relocs
+#objdump: -D -r
+
+.*elf32-spu
+
+Disassembly of section \.text:
+
+00000100 <_start>:
+.*	ai	\$1,\$1,-32
+.*	xor	\$0,\$0,\$0
+.*	stqd	\$0,0\(\$1\)
+.*	stqd	\$0,16\(\$1\)
+.*	brsl	\$0,.* <00000000\.ovl_call\.f1_a1>.*
+.*SPU_REL16	f1_a1
+.*	brsl	\$0,.* <00000000\.ovl_call\.f2_a1>.*
+.*SPU_REL16	f2_a1
+.*	brsl	\$0,.* <00000000\.ovl_call\.f1_a2>.*
+.*SPU_REL16	f1_a2
+.*	ila	\$9,.*
+.*SPU_ADDR18	f2_a2
+.*	bisl	\$0,\$9
+.*	ai	\$1,\$1,32	# 20
+.*	br	100 <_start>	# 100
+.*SPU_REL16	_start
+
+0000012c <f0>:
+.*	bi	\$0
+
+#...
+[0-9a-f]+ <__ovly_return>:
+#...
+[0-9a-f]+ <__ovly_load>:
+#...
+[0-9a-f]+ <_ovly_debug_event>:
+#...
+00000330 <00000000\.ovl_call\.f1_a1>:
+.*	ila	\$78,1
+.*	lnop
+.*	ila	\$79,1024	# 400
+.*	bra?	.* <__ovly_load>.*
+
+00000340 <00000000\.ovl_call\.f2_a1>:
+.*	ila	\$78,1
+.*	lnop
+.*	ila	\$79,1028	# 404
+.*	bra?	.* <__ovly_load>.*
+
+00000350 <00000000.ovl_call.f1_a2>:
+.*	ila	\$78,2
+.*	lnop
+.*	ila	\$79,1024	# 400
+.*	bra?	.* <__ovly_load>.*
+
+00000360 <00000000\.ovl_call\.f2_a2>:
+.*	ila	\$78,2
+.*	lnop
+.*	ila	\$79,1060	# 424
+.*	bra?	.* <__ovly_load>.*
+
+00000370 <00000000\.ovl_call\.f4_a1>:
+.*	ila	\$78,1
+.*	lnop
+.*	ila	\$79,1040	# 410
+.*	bra?	.* <__ovly_load>.*
+
+00000380 <00000000.ovl_call.14:8>:
+.*	ila	\$78,2
+.*	lnop
+.*	ila	\$79,1076	# 434
+.*	bra?	.* <__ovly_load>.*
+
+#00000330 <00000000\.ovl_call\.f1_a1>:
+#.*	bra?sl	\$75,.* <__ovly_load>.*
+#.*00 04 04 00.*
+#
+#00000338 <00000000\.ovl_call\.f2_a1>:
+#.*	bra?sl	\$75,.* <__ovly_load>.*
+#.*00 04 04 04.*
+#
+#00000340 <00000000\.ovl_call\.f1_a2>:
+#.*	bra?sl	\$75,.* <__ovly_load>.*
+#.*00 08 04 00.*
+#
+#00000348 <00000000\.ovl_call\.f2_a2>:
+#.*	bra?sl	\$75,.* <__ovly_load>.*
+#.*00 08 04 24.*
+#
+#00000350 <00000000\.ovl_call\.f4_a1>:
+#.*	bra?sl	\$75,.* <__ovly_load>.*
+#.*00 04 04 10.*
+#
+#00000358 <00000000.ovl_call.14:8>:
+#.*	bra?sl	\$75,.* <__ovly_load>.*
+#.*00 08 04 34.*
+
+Disassembly of section \.ov_a1:
+
+00000400 <f1_a1>:
+.*	br	.* <f3_a1>.*
+.*SPU_REL16	f3_a1
+
+00000404 <f2_a1>:
+.*	ila	\$3,.*
+.*SPU_ADDR18	f4_a1
+.*	bi	\$0
+
+0000040c <f3_a1>:
+.*	bi	\$0
+
+00000410 <f4_a1>:
+.*	bi	\$0
+	\.\.\.
+Disassembly of section \.ov_a2:
+
+00000400 <f1_a2>:
+.*	stqd	\$0,16\(\$1\)
+.*	stqd	\$1,-32\(\$1\)
+.*	ai	\$1,\$1,-32
+.*	brsl	\$0,12c <f0>	# 12c
+.*SPU_REL16	f0
+.*	brsl	\$0,.* <00000000\.ovl_call\.f1_a1>.*
+.*SPU_REL16	f1_a1
+.*	brsl	\$0,.* <f3_a2>.*
+.*SPU_REL16	f3_a2
+.*	lqd	\$0,48\(\$1\)	# 30
+.*	ai	\$1,\$1,32	# 20
+.*	bi	\$0
+
+00000424 <f2_a2>:
+.*	ilhu	\$3,.*
+.*SPU_ADDR16_HI	f4_a2
+.*	iohl	\$3,.*
+.*SPU_ADDR16_LO	f4_a2
+.*	bi	\$0
+
+00000430 <f3_a2>:
+.*	bi	\$0
+
+00000434 <f4_a2>:
+.*	br	.* <f3_a2>.*
+.*SPU_REL16	f3_a2
+	\.\.\.
+Disassembly of section .data:
+
+00000440 <_ovly_table-0x10>:
+ 440:	00 00 00 00 .*
+ 444:	00 00 00 01 .*
+	\.\.\.
+00000450 <_ovly_table>:
+ 450:	00 00 04 00 .*
+ 454:	00 00 00 20 .*
+# 458:	00 00 03 40 .*
+ 458:	00 00 01 00 .*
+ 45c:	00 00 00 01 .*
+ 460:	00 00 04 00 .*
+ 464:	00 00 00 40 .*
+# 468:	00 00 03 60 .*
+ 468:	00 00 01 20 .*
+ 46c:	00 00 00 01 .*
+
+00000470 <_ovly_buf_table>:
+ 470:	00 00 00 00 .*
+
+Disassembly of section \.toe:
+
+00000480 <_EAR_>:
+	\.\.\.
+Disassembly of section \.note\.spu_name:
+
+.* <\.note\.spu_name>:
+.*:	00 00 00 08 .*
+.*:	00 00 00 0c .*
+.*:	00 00 00 01 .*
+.*:	53 50 55 4e .*
+.*:	41 4d 45 00 .*
+.*:	74 6d 70 64 .*
+.*:	69 72 2f 64 .*
+.*:	75 6d 70 00 .*
diff --git a/binutils-2.21/ld/testsuite/ld-spu/ovl.lnk b/binutils-2.21/ld/testsuite/ld-spu/ovl.lnk
new file mode 100644
index 0000000..0015652
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/ovl.lnk
@@ -0,0 +1,7 @@
+SECTIONS
+{
+  . = SIZEOF_HEADERS;
+  .text : { *(.text) *(.stub) }
+  .data : { *(.data) *(.ovtab) }
+  .bss : { *(.bss) }
+}
diff --git a/binutils-2.21/ld/testsuite/ld-spu/ovl.s b/binutils-2.21/ld/testsuite/ld-spu/ovl.s
new file mode 100644
index 0000000..2ca380a
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/ovl.s
@@ -0,0 +1,82 @@
+ .text
+ .p2align 2
+ .globl _start
+_start:
+ ai sp,sp,-32
+ xor lr,lr,lr
+ stqd lr,0(sp)
+ stqd lr,16(sp)
+ brsl lr,f1_a1
+ brsl lr,f2_a1
+ brsl lr,f1_a2
+ ila 9,f2_a2
+ bisl lr,9
+ ai sp,sp,32
+ br _start
+
+ .type f0,@function
+f0:
+ bi lr
+ .size f0,.-f0
+
+ .section .ov_a1,"ax",@progbits
+ .p2align 2
+ .global f1_a1
+ .type f1_a1,@function
+f1_a1:
+ br f3_a1
+ .size f1_a1,.-f1_a1
+
+ .global f2_a1
+ .type f2_a1,@function
+f2_a1:
+ ila 3,f4_a1
+ bi lr
+ .size f2_a1,.-f2_a1
+
+ .global f3_a1
+ .type f3_a1,@function
+f3_a1:
+ bi lr
+ .size f3_a1,.-f3_a1
+
+ .global f4_a1
+ .type f4_a1,@function
+f4_a1:
+ bi lr
+ .size f4_a1,.-f4_a1
+
+
+ .section .ov_a2,"ax",@progbits
+ .p2align 2
+ .global f1_a2
+ .type f1_a2,@function
+f1_a2:
+ stqd lr,16(sp)
+ stqd sp,-32(sp)
+ ai sp,sp,-32
+ brsl lr,f0
+ brsl lr,f1_a1
+ brsl lr,f3_a2
+ lqd lr,48(sp)
+ ai sp,sp,32
+ bi lr
+ .size f1_a2,.-f1_a2
+
+ .global f2_a2
+ .type f2_a2,@function
+f2_a2:
+ ilhu 3,f4_a2@h
+ iohl 3,f4_a2@l
+ bi lr
+ .size f2_a2,.-f2_a2
+
+ .type f3_a2,@function
+f3_a2:
+ bi lr
+ .size f3_a2,.-f3_a2
+
+ .type f4_a2,@function
+f4_a2:
+ br f3_a2
+ .size f4_a2,.-f4_a2
diff --git a/binutils-2.21/ld/testsuite/ld-spu/ovl1.lnk b/binutils-2.21/ld/testsuite/ld-spu/ovl1.lnk
new file mode 100644
index 0000000..5fd4844
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/ovl1.lnk
@@ -0,0 +1,9 @@
+SECTIONS
+{
+  OVERLAY 0x400 :
+  {
+    .ov_a1 { *(.ov_a1) }
+    .ov_a2 { *(.ov_a2) }
+  }
+}
+INSERT AFTER .text;
diff --git a/binutils-2.21/ld/testsuite/ld-spu/ovl2.d b/binutils-2.21/ld/testsuite/ld-spu/ovl2.d
new file mode 100644
index 0000000..b1e344c
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/ovl2.d
@@ -0,0 +1,145 @@
+#source: ovl2.s
+#ld: -N -T ovl2.lnk -T ovl.lnk --emit-relocs
+#objdump: -D -r
+
+.*elf32-spu
+
+Disassembly of section \.text:
+
+00000100 <_start>:
+.*	brsl	\$0,.* <00000000\.ovl_call\.f1_a1>.*
+.*SPU_REL16	f1_a1
+.*	brsl	\$0,.* <00000000\.ovl_call\.setjmp>.*
+.*SPU_REL16	setjmp
+.*	br	100 <_start>	# 100
+.*SPU_REL16	_start
+
+0000010c <setjmp>:
+.*	bi	\$0
+
+00000110 <longjmp>:
+.*	bi	\$0
+
+.*00 00 03 40.*
+.*SPU_ADDR32	\.ov_a1\+0x14
+	\.\.\.
+#...
+00000320 <00000000\.ovl_call.f1_a1>:
+.*	ila	\$78,1
+.*	lnop
+.*	ila	\$79,1040	# 410
+.*	bra?	.* <__ovly_load>.*
+
+00000330 <00000000\.ovl_call.setjmp>:
+.*	ila	\$78,0
+.*	lnop
+.*	ila	\$79,268	# 10c
+.*	bra?	.* <__ovly_load>.*
+
+00000340 <00000000\.ovl_call\.13:5>:
+.* 	ila	\$78,1
+.* 	lnop
+.* 	ila	\$79,1044	# 414
+.* 	bra?	.* <__ovly_load>.*
+
+00000350 <_SPUEAR_f1_a2>:
+.*	ila	\$78,2
+.*	lnop
+.*	ila	\$79,1040	# 410
+.*	bra?	.* <__ovly_load>.*
+
+#00000318 <00000000\.ovl_call.f1_a1>:
+#.*	bra?sl	\$75,.* <__ovly_load>.*
+#.*00 04 04 00.*
+#
+#00000320 <00000000\.ovl_call.setjmp>:
+#.*	bra?sl	\$75,.* <__ovly_load>.*
+#.*00 00 01 0c.*
+#
+#00000328 <_SPUEAR_f1_a2>:
+#.*	bra?sl	\$75,.* <__ovly_load>.*
+#.*00 08 04 00.*
+
+Disassembly of section \.ov_a1:
+
+00000400 <00000001\.ovl_call\.14:6>:
+.* 	ila	\$78,2
+.* 	lnop
+.* 	ila	\$79,1044	# 414
+.* 	bra?	.* <__ovly_load>.*
+
+00000410 <f1_a1>:
+.*	bi	\$0
+.*00 00 04 14.*
+.*SPU_ADDR32	\.ov_a1\+0x14
+.*00 00 04 20.*
+.*SPU_ADDR32	\.ov_a1\+0x20
+.*00 00 04 00.*
+.*SPU_ADDR32	\.ov_a2\+0x14
+
+Disassembly of section \.ov_a2:
+
+00000400 <00000002\.ovl_call\.13:5>:
+.*	ila	\$78,1
+.*	lnop
+.*	ila	\$79,1056	# 420
+.*	bra?	.* <__ovly_load>.*
+
+00000410 <f1_a2>:
+.*	br	.* <longjmp>.*
+.*SPU_REL16	longjmp
+.*00 00 04 00.*
+.*SPU_ADDR32	\.ov_a1\+0x20
+.*00 00 04 1c.*
+.*SPU_ADDR32	\.ov_a2\+0x1c
+.*00 00 00 00.*
+
+Disassembly of section \.data:
+
+00000420 <_ovly_table-0x10>:
+.*00 00 00 00 .*
+.*00 00 00 01 .*
+	\.\.\.
+00000430 <_ovly_table>:
+.*00 00 04 00 .*
+.*00 00 00 20 .*
+#.*00 00 03 10 .*
+.*00 00 01 00 .*
+.*00 00 00 01 .*
+.*00 00 04 00 .*
+.*00 00 00 20 .*
+#.*00 00 03 20 .*
+.*00 00 01 20 .*
+.*00 00 00 01 .*
+
+00000450 <_ovly_buf_table>:
+.*00 00 00 00 .*
+
+Disassembly of section \.toe:
+
+00000460 <_EAR_>:
+	\.\.\.
+
+Disassembly of section .nonalloc:
+
+00000000 <.nonalloc>:
+.*00 00 04 14.*
+.*SPU_ADDR32	\.ov_a1\+0x14
+.*00 00 04 20.*
+.*SPU_ADDR32	\.ov_a1\+0x20
+.*00 00 04 14.*
+.*SPU_ADDR32	\.ov_a2\+0x14
+.*00 00 04 1c.*
+.*SPU_ADDR32	\.ov_a2\+0x1c
+
+Disassembly of section \.note\.spu_name:
+
+.* <\.note\.spu_name>:
+.*:	00 00 00 08 .*
+.*:	00 00 00 0c .*
+.*:	00 00 00 01 .*
+.*:	53 50 55 4e .*
+.*:	41 4d 45 00 .*
+.*:	74 6d 70 64 .*
+.*:	69 72 2f 64 .*
+.*:	75 6d 70 00 .*
diff --git a/binutils-2.21/ld/testsuite/ld-spu/ovl2.lnk b/binutils-2.21/ld/testsuite/ld-spu/ovl2.lnk
new file mode 100644
index 0000000..9916ab2
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/ovl2.lnk
@@ -0,0 +1,10 @@
+SECTIONS
+{
+  OVERLAY 0x400 :
+  {
+    .ov_a1 { *(.ov_a1) }
+    .ov_a2 { *(.ov_a2) }
+    .empty { empty.o?(.text) }
+  }
+}
+INSERT BEFORE .data;
diff --git a/binutils-2.21/ld/testsuite/ld-spu/ovl2.s b/binutils-2.21/ld/testsuite/ld-spu/ovl2.s
new file mode 100644
index 0000000..9147a78
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/ovl2.s
@@ -0,0 +1,52 @@
+ .text
+ .p2align 2
+ .global _start
+_start:
+ brsl lr,f1_a1
+ brsl lr,setjmp
+ br _start
+
+ .type setjmp,@function
+ .global setjmp
+setjmp:
+ bi lr
+ .size setjmp,.-setjmp
+
+ .type longjmp,@function
+longjmp:
+ bi lr
+ .size longjmp,.-longjmp
+
+ .word .L1
+
+ .section .ov_a1,"ax",@progbits
+ .p2align 2
+ .global f1_a1
+ .type f1_a1,@function
+f1_a1:
+ bi lr
+ .size f1_a1,.-f1_a1
+
+.L1:
+ .word .L1, .L2, .L3
+.L2:
+
+ .section .ov_a2,"ax",@progbits
+ .p2align 2
+ .type f1_a2,@function
+f1_a2:
+ br longjmp
+ .size f1_a2,.-f1_a2
+
+.L3:
+ .word .L2, .L4
+.L4:
+
+ .section .nonalloc,"",@progbits
+ .word .L1,.L2,.L3,.L4
+
+_SPUEAR_f1_a2 = f1_a2
+ .global _SPUEAR_f1_a2
+
+_SPUEAR_version=3
+ .global _SPUEAR_version
diff --git a/binutils-2.21/ld/testsuite/ld-spu/pic.d b/binutils-2.21/ld/testsuite/ld-spu/pic.d
new file mode 100644
index 0000000..87edc1d
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/pic.d
@@ -0,0 +1,105 @@
+#source: pic.s
+#source: picdef.s
+#ld: --emit-relocs
+#objdump: -D -r
+
+.*elf32-spu
+
+
+Disassembly of section \.text:
+
+00000000 <before>:
+	\.\.\.
+
+00000008 <_start>:
+   8:	42 00 08 02 	ila	\$2,10 <_start\+0x8>
+			8: SPU_ADDR18	\.text\+0x10
+   c:	33 00 00 fe 	brsl	\$126,10 <_start\+0x8>
+			c: SPU_REL16	\.text\+0x10
+  10:	08 1f 81 7e 	sf	\$126,\$2,\$126
+  14:	42 00 02 04 	ila	\$4,4 <before\+0x4>
+			14: SPU_ADDR18	\.text\+0x4
+  18:	42 00 42 05 	ila	\$5,84 <end>
+			18: SPU_ADDR18	\.text\+0x84
+  1c:	42 00 04 06 	ila	\$6,8 <_start>
+			1c: SPU_ADDR18	_start
+  20:	42 00 42 07 	ila	\$7,84 <end>
+			20: SPU_ADDR18	\.text\+0x84
+  24:	18 1f 82 04 	a	\$4,\$4,\$126
+			24: SPU_ADD_PIC	before\+0x4
+  28:	18 1f 82 85 	a	\$5,\$5,\$126
+			28: SPU_ADD_PIC	after\+0xfffffffc
+  2c:	18 1f 83 06 	a	\$6,\$6,\$126
+			2c: SPU_ADD_PIC	_start
+  30:	18 1f 83 87 	a	\$7,\$7,\$126
+			30: SPU_ADD_PIC	end
+  34:	42 00 00 0e 	ila	\$14,0
+			34: SPU_ADDR18	\.text
+  38:	18 1f 87 0e 	a	\$14,\$14,\$126
+			38: SPU_ADD_PIC	before
+  3c:	42 00 00 03 	ila	\$3,0
+			3c: SPU_ADDR18	undef
+  40:	1c 00 01 83 	ai	\$3,\$3,0
+			40: SPU_ADD_PIC	undef
+  44:	41 00 00 07 	ilhu	\$7,0
+			44: SPU_ADDR16_HI	ext
+  48:	60 ab 3c 07 	iohl	\$7,22136	# 5678
+			48: SPU_ADDR16_LO	ext
+  4c:	18 1f 83 84 	a	\$4,\$7,\$126
+			4c: SPU_ADD_PIC	ext
+  50:	42 00 80 09 	ila	\$9,100 <loc>
+			50: SPU_ADDR18	\.data
+  54:	18 1f 84 85 	a	\$5,\$9,\$126
+			54: SPU_ADD_PIC	loc
+  58:	42 00 88 08 	ila	\$8,110 <glob>
+			58: SPU_ADDR18	glob
+  5c:	18 1f 84 06 	a	\$6,\$8,\$126
+			5c: SPU_ADD_PIC	glob
+  60:	42 00 90 09 	ila	\$9,120 <__bss_start>
+			60: SPU_ADDR18	_end
+  64:	18 1f 84 89 	a	\$9,\$9,\$126
+			64: SPU_ADD_PIC	_end
+  68:	12 02 39 85 	hbrr	7c <acall>,1234 <abscall>	# 1234
+			68: SPU_REL16	abscall
+  6c:	33 ff f2 82 	lqr	\$2,0 <before>
+			6c: SPU_REL16	undef
+  70:	23 ff f2 02 	stqr	\$2,0 <before>
+			70: SPU_REL16	undef
+  74:	33 8a c0 83 	lqr	\$3,5678 <ext>	# 5678
+			74: SPU_REL16	ext
+  78:	33 8a c2 04 	lqr	\$4,5688 <ext\+0x10>	# 5688
+			78: SPU_REL16	ext\+0x10
+
+0000007c <acall>:
+  7c:	33 02 37 00 	brsl	\$0,1234 <abscall>	# 1234
+			7c: SPU_REL16	abscall
+  80:	32 02 36 80 	br	1234 <abscall>	# 1234
+			80: SPU_REL16	abscall
+
+00000084 <end>:
+  84:	00 00 00 00 	stop
+
+00000088 <after>:
+  88:	00 00 00 00 	stop
+
+Disassembly of section \.data:
+
+00000100 <loc>:
+ 100:	00 00 00 01 	stop
+	\.\.\.
+
+00000110 <glob>:
+ 110:	00 00 00 02 	stop
+	\.\.\.
+
+Disassembly of section \.note\.spu_name:
+
+00000000 <\.note\.spu_name>:
+.*
+.*
+.*
+.*
+.*
+.*
+.*
+#pass
diff --git a/binutils-2.21/ld/testsuite/ld-spu/pic.s b/binutils-2.21/ld/testsuite/ld-spu/pic.s
new file mode 100644
index 0000000..67ee7bc
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/pic.s
@@ -0,0 +1,68 @@
+ .global _end
+ .global _start
+ .global glob
+ .weak undef
+
+ .section .text.a,"ax"
+before:
+ .long 0
+ .long 0
+
+ .section .text.b,"ax"
+_start:
+ ila 2,.+8
+ brsl 126,.+4
+ sf 126,2,126
+ ila 4,before+4
+ ila 5,after-4
+ ila 6,_start
+ ila 7,end
+ .reloc .,SPU_ADD_PIC,before+4
+ a 4,4,126
+ .reloc .,SPU_ADD_PIC,after-4
+ a 5,5,126
+ .reloc .,SPU_ADD_PIC,_start
+ a 6,6,126
+ .reloc .,SPU_ADD_PIC,end
+ a 7,7,126
+ ila 14,before
+ .reloc .,SPU_ADD_PIC,before
+ a 14,14,126
+
+ ila 3,undef
+ .reloc .,SPU_ADD_PIC,undef
+ a 3,3,126
+ ilhu 7,ext@h
+ iohl 7,ext@l
+ .reloc .,SPU_ADD_PIC,ext
+ a 4,7,126
+ ila 9,loc
+ .reloc .,SPU_ADD_PIC,loc
+ a 5,9,126
+ ila 8,glob
+ .reloc .,SPU_ADD_PIC,glob
+ a 6,8,126
+ ila 9,_end
+ .reloc .,SPU_ADD_PIC,_end
+ a 9,9,126
+
+ hbrr acall,abscall
+ lqr 2,undef
+ stqr 2,undef
+ lqr 3,ext
+ lqr 4,ext+16
+acall:
+ brsl 0,abscall
+ br abscall
+end:
+
+ .section .text.c,"ax"
+ .long 0
+after:
+ .long 0
+
+ .data
+loc:
+ .long 1,0,0,0
+glob:
+ .long 2,0,0,0
diff --git a/binutils-2.21/ld/testsuite/ld-spu/picdef.s b/binutils-2.21/ld/testsuite/ld-spu/picdef.s
new file mode 100644
index 0000000..4df3e4b
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/picdef.s
@@ -0,0 +1,5 @@
+ .global abscall
+ .global ext
+
+abscall = 0x1234
+ext = 0x5678
diff --git a/binutils-2.21/ld/testsuite/ld-spu/spu.exp b/binutils-2.21/ld/testsuite/ld-spu/spu.exp
new file mode 100644
index 0000000..39d1c96
--- /dev/null
+++ b/binutils-2.21/ld/testsuite/ld-spu/spu.exp
@@ -0,0 +1,94 @@
+# Expect script for ld-spu tests
+#   Copyright (C) 2006, 2007 Free Software Foundation
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+if { ![istarget "spu-*-*"] } {
+    return
+}
+
+proc embed_test { } {
+    global subdir srcdir
+    global AS ASFLAGS LD LDFLAGS READELF READELFFLAGS
+
+    set cmd "$AS $ASFLAGS -o tmpdir/ear.o $srcdir/$subdir/ear.s"
+    send_log "$cmd\n"
+    set cmdret [catch "exec $cmd" comp_output]
+    set comp_output [prune_warnings $comp_output]
+    if { $cmdret != 0 || $comp_output != ""} then {
+	send_log "$comp_output\n"
+	verbose "$comp_output" 3
+	fail "ear assembly"
+	return
+    }
+
+    set cmd "$LD $LDFLAGS -o tmpdir/ear tmpdir/ear.o"
+    send_log "$cmd\n"
+    set cmdret [catch "exec $cmd" comp_output]
+    set comp_output [prune_warnings $comp_output]
+    if { $cmdret != 0 || $comp_output != ""} then {
+	send_log "$comp_output\n"
+	verbose "$comp_output" 3
+	fail "ear link"
+	return
+    }
+
+    set cmd "sh $srcdir/../../binutils/embedspu.sh -m32 ear tmpdir/ear tmpdir/embed.o"
+    send_log "$cmd\n"
+    set cmdret [catch "exec $cmd" comp_output]
+    set comp_output [prune_warnings $comp_output]
+    if { $cmdret != 0 || $comp_output != ""} then {
+	send_log "$comp_output\n"
+	verbose "$comp_output" 3
+	if { [regexp "unknown pseudo-op: `.reloc'" $comp_output] } {
+	    untested "ear embedspu"
+	    return
+	}
+	fail "ear embedspu"
+	return
+    }
+
+    set cmd "$READELF $READELFFLAGS -r --wide tmpdir/embed.o > tmpdir/embed.out"
+    send_log "$cmd\n"
+    set cmdret [catch "exec $cmd" comp_output]
+    set comp_output [prune_warnings $comp_output]
+    if { $cmdret != 0 || $comp_output != ""} then {
+	send_log "$comp_output\n"
+	verbose "$comp_output" 3
+	fail "ear embed readelf"
+	return
+    }
+
+    if { [regexp_diff "tmpdir/embed.out" $srcdir/$subdir/embed.rd] } then {
+	fail "ear embed output"
+	return
+    }
+
+    pass "ear embed"
+}
+
+set rd_test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]]
+foreach sputest $rd_test_list {
+    verbose [file rootname $sputest]
+    run_dump_test [file rootname $sputest]
+}
+
+if { [isbuild "powerpc*-*-linux*"] } {
+    embed_test
+}